Commit | Line | Data |
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c906108c SS |
1 | /* Target-machine dependent code for the Intel 960 |
2 | Copyright 1991, 1992, 1993, 1994, 1995 Free Software Foundation, Inc. | |
3 | Contributed by Intel Corporation. | |
4 | examine_prologue and other parts contributed by Wind River Systems. | |
5 | ||
c5aa993b | 6 | This file is part of GDB. |
c906108c | 7 | |
c5aa993b JM |
8 | This program is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
c906108c | 12 | |
c5aa993b JM |
13 | This program is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
c906108c | 17 | |
c5aa993b JM |
18 | You should have received a copy of the GNU General Public License |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
22 | |
23 | #include "defs.h" | |
24 | #include "symtab.h" | |
25 | #include "value.h" | |
26 | #include "frame.h" | |
27 | #include "floatformat.h" | |
28 | #include "target.h" | |
29 | #include "gdbcore.h" | |
2acceee2 | 30 | #include "inferior.h" |
c906108c SS |
31 | |
32 | static CORE_ADDR next_insn PARAMS ((CORE_ADDR memaddr, | |
33 | unsigned int *pword1, | |
34 | unsigned int *pword2)); | |
35 | ||
36 | /* Does the specified function use the "struct returning" convention | |
37 | or the "value returning" convention? The "value returning" convention | |
38 | almost invariably returns the entire value in registers. The | |
39 | "struct returning" convention often returns the entire value in | |
40 | memory, and passes a pointer (out of or into the function) saying | |
41 | where the value (is or should go). | |
42 | ||
43 | Since this sometimes depends on whether it was compiled with GCC, | |
44 | this is also an argument. This is used in call_function to build a | |
45 | stack, and in value_being_returned to print return values. | |
46 | ||
47 | On i960, a structure is returned in registers g0-g3, if it will fit. | |
48 | If it's more than 16 bytes long, g13 pointed to it on entry. */ | |
49 | ||
50 | int | |
51 | i960_use_struct_convention (gcc_p, type) | |
52 | int gcc_p; | |
53 | struct type *type; | |
54 | { | |
55 | return (TYPE_LENGTH (type) > 16); | |
56 | } | |
57 | ||
58 | /* gdb960 is always running on a non-960 host. Check its characteristics. | |
59 | This routine must be called as part of gdb initialization. */ | |
60 | ||
61 | static void | |
c5aa993b | 62 | check_host () |
c906108c | 63 | { |
c5aa993b | 64 | int i; |
c906108c | 65 | |
c5aa993b JM |
66 | static struct typestruct |
67 | { | |
68 | int hostsize; /* Size of type on host */ | |
69 | int i960size; /* Size of type on i960 */ | |
70 | char *typename; /* Name of type, for error msg */ | |
71 | } | |
72 | types[] = | |
73 | { | |
74 | { | |
75 | sizeof (short), 2, "short" | |
76 | } | |
77 | , | |
78 | { | |
79 | sizeof (int), 4, "int" | |
80 | } | |
81 | , | |
82 | { | |
83 | sizeof (long), 4, "long" | |
84 | } | |
85 | , | |
86 | { | |
87 | sizeof (float), 4, "float" | |
88 | } | |
89 | , | |
90 | { | |
91 | sizeof (double), 8, "double" | |
92 | } | |
93 | , | |
94 | { | |
95 | sizeof (char *), 4, "pointer" | |
96 | } | |
97 | , | |
98 | }; | |
99 | #define TYPELEN (sizeof(types) / sizeof(struct typestruct)) | |
c906108c | 100 | |
c5aa993b JM |
101 | /* Make sure that host type sizes are same as i960 |
102 | */ | |
103 | for (i = 0; i < TYPELEN; i++) | |
104 | { | |
105 | if (types[i].hostsize != types[i].i960size) | |
106 | { | |
107 | printf_unfiltered ("sizeof(%s) != %d: PROCEED AT YOUR OWN RISK!\n", | |
108 | types[i].typename, types[i].i960size); | |
c906108c | 109 | } |
c5aa993b JM |
110 | |
111 | } | |
c906108c SS |
112 | } |
113 | \f | |
114 | /* Examine an i960 function prologue, recording the addresses at which | |
115 | registers are saved explicitly by the prologue code, and returning | |
116 | the address of the first instruction after the prologue (but not | |
117 | after the instruction at address LIMIT, as explained below). | |
118 | ||
119 | LIMIT places an upper bound on addresses of the instructions to be | |
120 | examined. If the prologue code scan reaches LIMIT, the scan is | |
121 | aborted and LIMIT is returned. This is used, when examining the | |
122 | prologue for the current frame, to keep examine_prologue () from | |
123 | claiming that a given register has been saved when in fact the | |
124 | instruction that saves it has not yet been executed. LIMIT is used | |
125 | at other times to stop the scan when we hit code after the true | |
126 | function prologue (e.g. for the first source line) which might | |
127 | otherwise be mistaken for function prologue. | |
128 | ||
129 | The format of the function prologue matched by this routine is | |
130 | derived from examination of the source to gcc960 1.21, particularly | |
131 | the routine i960_function_prologue (). A "regular expression" for | |
132 | the function prologue is given below: | |
133 | ||
134 | (lda LRn, g14 | |
c5aa993b JM |
135 | mov g14, g[0-7] |
136 | (mov 0, g14) | (lda 0, g14))? | |
c906108c SS |
137 | |
138 | (mov[qtl]? g[0-15], r[4-15])* | |
139 | ((addo [1-31], sp, sp) | (lda n(sp), sp))? | |
140 | (st[qtl]? g[0-15], n(fp))* | |
141 | ||
142 | (cmpobne 0, g14, LFn | |
c5aa993b JM |
143 | mov sp, g14 |
144 | lda 0x30(sp), sp | |
145 | LFn: stq g0, (g14) | |
146 | stq g4, 0x10(g14) | |
147 | stq g8, 0x20(g14))? | |
c906108c SS |
148 | |
149 | (st g14, n(fp))? | |
150 | (mov g13,r[4-15])? | |
c5aa993b | 151 | */ |
c906108c SS |
152 | |
153 | /* Macros for extracting fields from i960 instructions. */ | |
154 | ||
155 | #define BITMASK(pos, width) (((0x1 << (width)) - 1) << (pos)) | |
156 | #define EXTRACT_FIELD(val, pos, width) ((val) >> (pos) & BITMASK (0, width)) | |
157 | ||
158 | #define REG_SRC1(insn) EXTRACT_FIELD (insn, 0, 5) | |
159 | #define REG_SRC2(insn) EXTRACT_FIELD (insn, 14, 5) | |
160 | #define REG_SRCDST(insn) EXTRACT_FIELD (insn, 19, 5) | |
161 | #define MEM_SRCDST(insn) EXTRACT_FIELD (insn, 19, 5) | |
162 | #define MEMA_OFFSET(insn) EXTRACT_FIELD (insn, 0, 12) | |
163 | ||
164 | /* Fetch the instruction at ADDR, returning 0 if ADDR is beyond LIM or | |
165 | is not the address of a valid instruction, the address of the next | |
166 | instruction beyond ADDR otherwise. *PWORD1 receives the first word | |
167 | of the instruction, and (for two-word instructions), *PWORD2 receives | |
168 | the second. */ | |
169 | ||
170 | #define NEXT_PROLOGUE_INSN(addr, lim, pword1, pword2) \ | |
171 | (((addr) < (lim)) ? next_insn (addr, pword1, pword2) : 0) | |
172 | ||
173 | static CORE_ADDR | |
174 | examine_prologue (ip, limit, frame_addr, fsr) | |
175 | register CORE_ADDR ip; | |
176 | register CORE_ADDR limit; | |
177 | CORE_ADDR frame_addr; | |
178 | struct frame_saved_regs *fsr; | |
179 | { | |
180 | register CORE_ADDR next_ip; | |
181 | register int src, dst; | |
182 | register unsigned int *pcode; | |
183 | unsigned int insn1, insn2; | |
184 | int size; | |
185 | int within_leaf_prologue; | |
186 | CORE_ADDR save_addr; | |
c5aa993b JM |
187 | static unsigned int varargs_prologue_code[] = |
188 | { | |
189 | 0x3507a00c, /* cmpobne 0x0, g14, LFn */ | |
190 | 0x5cf01601, /* mov sp, g14 */ | |
191 | 0x8c086030, /* lda 0x30(sp), sp */ | |
192 | 0xb2879000, /* LFn: stq g0, (g14) */ | |
193 | 0xb2a7a010, /* stq g4, 0x10(g14) */ | |
194 | 0xb2c7a020 /* stq g8, 0x20(g14) */ | |
195 | }; | |
c906108c SS |
196 | |
197 | /* Accept a leaf procedure prologue code fragment if present. | |
198 | Note that ip might point to either the leaf or non-leaf | |
199 | entry point; we look for the non-leaf entry point first: */ | |
200 | ||
201 | within_leaf_prologue = 0; | |
202 | if ((next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2)) | |
c5aa993b JM |
203 | && ((insn1 & 0xfffff000) == 0x8cf00000 /* lda LRx, g14 (MEMA) */ |
204 | || (insn1 & 0xfffffc60) == 0x8cf03000)) /* lda LRx, g14 (MEMB) */ | |
c906108c SS |
205 | { |
206 | within_leaf_prologue = 1; | |
207 | next_ip = NEXT_PROLOGUE_INSN (next_ip, limit, &insn1, &insn2); | |
208 | } | |
209 | ||
210 | /* Now look for the prologue code at a leaf entry point: */ | |
211 | ||
212 | if (next_ip | |
c5aa993b | 213 | && (insn1 & 0xff87ffff) == 0x5c80161e /* mov g14, gx */ |
c906108c SS |
214 | && REG_SRCDST (insn1) <= G0_REGNUM + 7) |
215 | { | |
216 | within_leaf_prologue = 1; | |
217 | if ((next_ip = NEXT_PROLOGUE_INSN (next_ip, limit, &insn1, &insn2)) | |
c5aa993b JM |
218 | && (insn1 == 0x8cf00000 /* lda 0, g14 */ |
219 | || insn1 == 0x5cf01e00)) /* mov 0, g14 */ | |
c906108c SS |
220 | { |
221 | ip = next_ip; | |
222 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); | |
223 | within_leaf_prologue = 0; | |
224 | } | |
225 | } | |
226 | ||
227 | /* If something that looks like the beginning of a leaf prologue | |
228 | has been seen, but the remainder of the prologue is missing, bail. | |
229 | We don't know what we've got. */ | |
230 | ||
231 | if (within_leaf_prologue) | |
232 | return (ip); | |
c5aa993b | 233 | |
c906108c SS |
234 | /* Accept zero or more instances of "mov[qtl]? gx, ry", where y >= 4. |
235 | This may cause us to mistake the moving of a register | |
236 | parameter to a local register for the saving of a callee-saved | |
237 | register, but that can't be helped, since with the | |
238 | "-fcall-saved" flag, any register can be made callee-saved. */ | |
239 | ||
240 | while (next_ip | |
241 | && (insn1 & 0xfc802fb0) == 0x5c000610 | |
242 | && (dst = REG_SRCDST (insn1)) >= (R0_REGNUM + 4)) | |
243 | { | |
244 | src = REG_SRC1 (insn1); | |
245 | size = EXTRACT_FIELD (insn1, 24, 2) + 1; | |
246 | save_addr = frame_addr + ((dst - R0_REGNUM) * 4); | |
247 | while (size--) | |
248 | { | |
249 | fsr->regs[src++] = save_addr; | |
250 | save_addr += 4; | |
251 | } | |
252 | ip = next_ip; | |
253 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); | |
254 | } | |
255 | ||
256 | /* Accept an optional "addo n, sp, sp" or "lda n(sp), sp". */ | |
257 | ||
258 | if (next_ip && | |
259 | ((insn1 & 0xffffffe0) == 0x59084800 /* addo n, sp, sp */ | |
260 | || (insn1 & 0xfffff000) == 0x8c086000 /* lda n(sp), sp (MEMA) */ | |
261 | || (insn1 & 0xfffffc60) == 0x8c087400)) /* lda n(sp), sp (MEMB) */ | |
262 | { | |
263 | ip = next_ip; | |
264 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); | |
265 | } | |
266 | ||
267 | /* Accept zero or more instances of "st[qtl]? gx, n(fp)". | |
268 | This may cause us to mistake the copying of a register | |
269 | parameter to the frame for the saving of a callee-saved | |
270 | register, but that can't be helped, since with the | |
271 | "-fcall-saved" flag, any register can be made callee-saved. | |
272 | We can, however, refuse to accept a save of register g14, | |
273 | since that is matched explicitly below. */ | |
274 | ||
275 | while (next_ip && | |
c5aa993b JM |
276 | ((insn1 & 0xf787f000) == 0x9287e000 /* stl? gx, n(fp) (MEMA) */ |
277 | || (insn1 & 0xf787fc60) == 0x9287f400 /* stl? gx, n(fp) (MEMB) */ | |
278 | || (insn1 & 0xef87f000) == 0xa287e000 /* st[tq] gx, n(fp) (MEMA) */ | |
279 | || (insn1 & 0xef87fc60) == 0xa287f400) /* st[tq] gx, n(fp) (MEMB) */ | |
c906108c SS |
280 | && ((src = MEM_SRCDST (insn1)) != G14_REGNUM)) |
281 | { | |
282 | save_addr = frame_addr + ((insn1 & BITMASK (12, 1)) | |
283 | ? insn2 : MEMA_OFFSET (insn1)); | |
284 | size = (insn1 & BITMASK (29, 1)) ? ((insn1 & BITMASK (28, 1)) ? 4 : 3) | |
c5aa993b | 285 | : ((insn1 & BITMASK (27, 1)) ? 2 : 1); |
c906108c SS |
286 | while (size--) |
287 | { | |
288 | fsr->regs[src++] = save_addr; | |
289 | save_addr += 4; | |
290 | } | |
291 | ip = next_ip; | |
292 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); | |
293 | } | |
294 | ||
295 | /* Accept the varargs prologue code if present. */ | |
296 | ||
297 | size = sizeof (varargs_prologue_code) / sizeof (int); | |
298 | pcode = varargs_prologue_code; | |
299 | while (size-- && next_ip && *pcode++ == insn1) | |
300 | { | |
301 | ip = next_ip; | |
302 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); | |
303 | } | |
304 | ||
305 | /* Accept an optional "st g14, n(fp)". */ | |
306 | ||
307 | if (next_ip && | |
c5aa993b JM |
308 | ((insn1 & 0xfffff000) == 0x92f7e000 /* st g14, n(fp) (MEMA) */ |
309 | || (insn1 & 0xfffffc60) == 0x92f7f400)) /* st g14, n(fp) (MEMB) */ | |
c906108c SS |
310 | { |
311 | fsr->regs[G14_REGNUM] = frame_addr + ((insn1 & BITMASK (12, 1)) | |
c5aa993b | 312 | ? insn2 : MEMA_OFFSET (insn1)); |
c906108c SS |
313 | ip = next_ip; |
314 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); | |
315 | } | |
316 | ||
317 | /* Accept zero or one instance of "mov g13, ry", where y >= 4. | |
318 | This is saving the address where a struct should be returned. */ | |
319 | ||
320 | if (next_ip | |
321 | && (insn1 & 0xff802fbf) == 0x5c00061d | |
322 | && (dst = REG_SRCDST (insn1)) >= (R0_REGNUM + 4)) | |
323 | { | |
324 | save_addr = frame_addr + ((dst - R0_REGNUM) * 4); | |
c5aa993b | 325 | fsr->regs[G0_REGNUM + 13] = save_addr; |
c906108c | 326 | ip = next_ip; |
c5aa993b | 327 | #if 0 /* We'll need this once there is a subsequent instruction examined. */ |
c906108c SS |
328 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); |
329 | #endif | |
330 | } | |
331 | ||
332 | return (ip); | |
333 | } | |
334 | ||
335 | /* Given an ip value corresponding to the start of a function, | |
336 | return the ip of the first instruction after the function | |
337 | prologue. */ | |
338 | ||
339 | CORE_ADDR | |
b83266a0 | 340 | i960_skip_prologue (ip) |
c5aa993b | 341 | CORE_ADDR (ip); |
c906108c SS |
342 | { |
343 | struct frame_saved_regs saved_regs_dummy; | |
344 | struct symtab_and_line sal; | |
345 | CORE_ADDR limit; | |
346 | ||
347 | sal = find_pc_line (ip, 0); | |
348 | limit = (sal.end) ? sal.end : 0xffffffff; | |
349 | ||
350 | return (examine_prologue (ip, limit, (CORE_ADDR) 0, &saved_regs_dummy)); | |
351 | } | |
352 | ||
353 | /* Put here the code to store, into a struct frame_saved_regs, | |
354 | the addresses of the saved registers of frame described by FRAME_INFO. | |
355 | This includes special registers such as pc and fp saved in special | |
356 | ways in the stack frame. sp is even more special: | |
357 | the address we return for it IS the sp for the next frame. | |
358 | ||
359 | We cache the result of doing this in the frame_obstack, since it is | |
360 | fairly expensive. */ | |
361 | ||
362 | void | |
363 | frame_find_saved_regs (fi, fsr) | |
364 | struct frame_info *fi; | |
365 | struct frame_saved_regs *fsr; | |
366 | { | |
367 | register CORE_ADDR next_addr; | |
368 | register CORE_ADDR *saved_regs; | |
369 | register int regnum; | |
370 | register struct frame_saved_regs *cache_fsr; | |
371 | CORE_ADDR ip; | |
372 | struct symtab_and_line sal; | |
373 | CORE_ADDR limit; | |
374 | ||
375 | if (!fi->fsr) | |
376 | { | |
377 | cache_fsr = (struct frame_saved_regs *) | |
378 | frame_obstack_alloc (sizeof (struct frame_saved_regs)); | |
379 | memset (cache_fsr, '\0', sizeof (struct frame_saved_regs)); | |
380 | fi->fsr = cache_fsr; | |
381 | ||
382 | /* Find the start and end of the function prologue. If the PC | |
c5aa993b JM |
383 | is in the function prologue, we only consider the part that |
384 | has executed already. */ | |
385 | ||
c906108c SS |
386 | ip = get_pc_function_start (fi->pc); |
387 | sal = find_pc_line (ip, 0); | |
c5aa993b | 388 | limit = (sal.end && sal.end < fi->pc) ? sal.end : fi->pc; |
c906108c SS |
389 | |
390 | examine_prologue (ip, limit, fi->frame, cache_fsr); | |
391 | ||
392 | /* Record the addresses at which the local registers are saved. | |
c5aa993b JM |
393 | Strictly speaking, we should only do this for non-leaf procedures, |
394 | but no one will ever look at these values if it is a leaf procedure, | |
395 | since local registers are always caller-saved. */ | |
c906108c SS |
396 | |
397 | next_addr = (CORE_ADDR) fi->frame; | |
398 | saved_regs = cache_fsr->regs; | |
399 | for (regnum = R0_REGNUM; regnum <= R15_REGNUM; regnum++) | |
400 | { | |
401 | *saved_regs++ = next_addr; | |
402 | next_addr += 4; | |
403 | } | |
404 | ||
405 | cache_fsr->regs[FP_REGNUM] = cache_fsr->regs[PFP_REGNUM]; | |
406 | } | |
407 | ||
408 | *fsr = *fi->fsr; | |
409 | ||
410 | /* Fetch the value of the sp from memory every time, since it | |
411 | is conceivable that it has changed since the cache was flushed. | |
412 | This unfortunately undoes much of the savings from caching the | |
413 | saved register values. I suggest adding an argument to | |
414 | get_frame_saved_regs () specifying the register number we're | |
415 | interested in (or -1 for all registers). This would be passed | |
416 | through to FRAME_FIND_SAVED_REGS (), permitting more efficient | |
417 | computation of saved register addresses (e.g., on the i960, | |
418 | we don't have to examine the prologue to find local registers). | |
c5aa993b | 419 | -- markf@wrs.com |
c906108c SS |
420 | FIXME, we don't need to refetch this, since the cache is cleared |
421 | every time the child process is restarted. If GDB itself | |
422 | modifies SP, it has to clear the cache by hand (does it?). -gnu */ | |
423 | ||
424 | fsr->regs[SP_REGNUM] = read_memory_integer (fsr->regs[SP_REGNUM], 4); | |
425 | } | |
426 | ||
427 | /* Return the address of the argument block for the frame | |
428 | described by FI. Returns 0 if the address is unknown. */ | |
429 | ||
430 | CORE_ADDR | |
431 | frame_args_address (fi, must_be_correct) | |
432 | struct frame_info *fi; | |
433 | { | |
434 | struct frame_saved_regs fsr; | |
435 | CORE_ADDR ap; | |
436 | ||
437 | /* If g14 was saved in the frame by the function prologue code, return | |
438 | the saved value. If the frame is current and we are being sloppy, | |
439 | return the value of g14. Otherwise, return zero. */ | |
440 | ||
441 | get_frame_saved_regs (fi, &fsr); | |
442 | if (fsr.regs[G14_REGNUM]) | |
c5aa993b | 443 | ap = read_memory_integer (fsr.regs[G14_REGNUM], 4); |
c906108c SS |
444 | else |
445 | { | |
446 | if (must_be_correct) | |
c5aa993b | 447 | return 0; /* Don't cache this result */ |
c906108c SS |
448 | if (get_next_frame (fi)) |
449 | ap = 0; | |
450 | else | |
451 | ap = read_register (G14_REGNUM); | |
452 | if (ap == 0) | |
453 | ap = fi->frame; | |
454 | } | |
455 | fi->arg_pointer = ap; /* Cache it for next time */ | |
456 | return ap; | |
457 | } | |
458 | ||
459 | /* Return the address of the return struct for the frame | |
460 | described by FI. Returns 0 if the address is unknown. */ | |
461 | ||
462 | CORE_ADDR | |
463 | frame_struct_result_address (fi) | |
464 | struct frame_info *fi; | |
465 | { | |
466 | struct frame_saved_regs fsr; | |
467 | CORE_ADDR ap; | |
468 | ||
469 | /* If the frame is non-current, check to see if g14 was saved in the | |
470 | frame by the function prologue code; return the saved value if so, | |
471 | zero otherwise. If the frame is current, return the value of g14. | |
472 | ||
473 | FIXME, shouldn't this use the saved value as long as we are past | |
474 | the function prologue, and only use the current value if we have | |
475 | no saved value and are at TOS? -- gnu@cygnus.com */ | |
476 | ||
477 | if (get_next_frame (fi)) | |
478 | { | |
479 | get_frame_saved_regs (fi, &fsr); | |
480 | if (fsr.regs[G13_REGNUM]) | |
c5aa993b | 481 | ap = read_memory_integer (fsr.regs[G13_REGNUM], 4); |
c906108c SS |
482 | else |
483 | ap = 0; | |
484 | } | |
485 | else | |
486 | ap = read_register (G13_REGNUM); | |
487 | ||
488 | return ap; | |
489 | } | |
490 | ||
491 | /* Return address to which the currently executing leafproc will return, | |
492 | or 0 if ip is not in a leafproc (or if we can't tell if it is). | |
c5aa993b | 493 | |
c906108c SS |
494 | Do this by finding the starting address of the routine in which ip lies. |
495 | If the instruction there is "mov g14, gx" (where x is in [0,7]), this | |
496 | is a leafproc and the return address is in register gx. Well, this is | |
497 | true unless the return address points at a RET instruction in the current | |
498 | procedure, which indicates that we have a 'dual entry' routine that | |
499 | has been entered through the CALL entry point. */ | |
500 | ||
501 | CORE_ADDR | |
502 | leafproc_return (ip) | |
c5aa993b | 503 | CORE_ADDR ip; /* ip from currently executing function */ |
c906108c SS |
504 | { |
505 | register struct minimal_symbol *msymbol; | |
506 | char *p; | |
507 | int dst; | |
508 | unsigned int insn1, insn2; | |
509 | CORE_ADDR return_addr; | |
510 | ||
511 | if ((msymbol = lookup_minimal_symbol_by_pc (ip)) != NULL) | |
512 | { | |
c5aa993b | 513 | if ((p = strchr (SYMBOL_NAME (msymbol), '.')) && STREQ (p, ".lf")) |
c906108c SS |
514 | { |
515 | if (next_insn (SYMBOL_VALUE_ADDRESS (msymbol), &insn1, &insn2) | |
c5aa993b | 516 | && (insn1 & 0xff87ffff) == 0x5c80161e /* mov g14, gx */ |
c906108c SS |
517 | && (dst = REG_SRCDST (insn1)) <= G0_REGNUM + 7) |
518 | { | |
519 | /* Get the return address. If the "mov g14, gx" | |
c5aa993b JM |
520 | instruction hasn't been executed yet, read |
521 | the return address from g14; otherwise, read it | |
522 | from the register into which g14 was moved. */ | |
c906108c SS |
523 | |
524 | return_addr = | |
c5aa993b JM |
525 | read_register ((ip == SYMBOL_VALUE_ADDRESS (msymbol)) |
526 | ? G14_REGNUM : dst); | |
c906108c SS |
527 | |
528 | /* We know we are in a leaf procedure, but we don't know | |
c5aa993b JM |
529 | whether the caller actually did a "bal" to the ".lf" |
530 | entry point, or a normal "call" to the non-leaf entry | |
531 | point one instruction before. In the latter case, the | |
532 | return address will be the address of a "ret" | |
533 | instruction within the procedure itself. We test for | |
534 | this below. */ | |
c906108c SS |
535 | |
536 | if (!next_insn (return_addr, &insn1, &insn2) | |
c5aa993b JM |
537 | || (insn1 & 0xff000000) != 0xa000000 /* ret */ |
538 | || lookup_minimal_symbol_by_pc (return_addr) != msymbol) | |
c906108c SS |
539 | return (return_addr); |
540 | } | |
541 | } | |
542 | } | |
c5aa993b | 543 | |
c906108c SS |
544 | return (0); |
545 | } | |
546 | ||
547 | /* Immediately after a function call, return the saved pc. | |
548 | Can't go through the frames for this because on some machines | |
549 | the new frame is not set up until the new function executes | |
550 | some instructions. | |
551 | On the i960, the frame *is* set up immediately after the call, | |
552 | unless the function is a leaf procedure. */ | |
553 | ||
554 | CORE_ADDR | |
555 | saved_pc_after_call (frame) | |
556 | struct frame_info *frame; | |
557 | { | |
558 | CORE_ADDR saved_pc; | |
559 | ||
560 | saved_pc = leafproc_return (get_frame_pc (frame)); | |
561 | if (!saved_pc) | |
562 | saved_pc = FRAME_SAVED_PC (frame); | |
563 | ||
564 | return saved_pc; | |
565 | } | |
566 | ||
567 | /* Discard from the stack the innermost frame, | |
568 | restoring all saved registers. */ | |
569 | ||
570 | void | |
d4f3574e | 571 | i960_pop_frame (void) |
c906108c SS |
572 | { |
573 | register struct frame_info *current_fi, *prev_fi; | |
574 | register int i; | |
575 | CORE_ADDR save_addr; | |
576 | CORE_ADDR leaf_return_addr; | |
577 | struct frame_saved_regs fsr; | |
578 | char local_regs_buf[16 * 4]; | |
579 | ||
580 | current_fi = get_current_frame (); | |
581 | ||
582 | /* First, undo what the hardware does when we return. | |
583 | If this is a non-leaf procedure, restore local registers from | |
584 | the save area in the calling frame. Otherwise, load the return | |
585 | address obtained from leafproc_return () into the rip. */ | |
586 | ||
587 | leaf_return_addr = leafproc_return (current_fi->pc); | |
588 | if (!leaf_return_addr) | |
589 | { | |
590 | /* Non-leaf procedure. Restore local registers, incl IP. */ | |
591 | prev_fi = get_prev_frame (current_fi); | |
592 | read_memory (prev_fi->frame, local_regs_buf, sizeof (local_regs_buf)); | |
c5aa993b JM |
593 | write_register_bytes (REGISTER_BYTE (R0_REGNUM), local_regs_buf, |
594 | sizeof (local_regs_buf)); | |
c906108c SS |
595 | |
596 | /* Restore frame pointer. */ | |
597 | write_register (FP_REGNUM, prev_fi->frame); | |
598 | } | |
599 | else | |
600 | { | |
601 | /* Leaf procedure. Just restore the return address into the IP. */ | |
602 | write_register (RIP_REGNUM, leaf_return_addr); | |
603 | } | |
604 | ||
605 | /* Now restore any global regs that the current function had saved. */ | |
606 | get_frame_saved_regs (current_fi, &fsr); | |
607 | for (i = G0_REGNUM; i < G14_REGNUM; i++) | |
608 | { | |
7a292a7a SS |
609 | save_addr = fsr.regs[i]; |
610 | if (save_addr != 0) | |
c906108c SS |
611 | write_register (i, read_memory_integer (save_addr, 4)); |
612 | } | |
613 | ||
614 | /* Flush the frame cache, create a frame for the new innermost frame, | |
615 | and make it the current frame. */ | |
616 | ||
617 | flush_cached_frames (); | |
618 | } | |
619 | ||
620 | /* Given a 960 stop code (fault or trace), return the signal which | |
621 | corresponds. */ | |
622 | ||
623 | enum target_signal | |
624 | i960_fault_to_signal (fault) | |
c5aa993b | 625 | int fault; |
c906108c SS |
626 | { |
627 | switch (fault) | |
628 | { | |
c5aa993b JM |
629 | case 0: |
630 | return TARGET_SIGNAL_BUS; /* parallel fault */ | |
631 | case 1: | |
632 | return TARGET_SIGNAL_UNKNOWN; | |
633 | case 2: | |
634 | return TARGET_SIGNAL_ILL; /* operation fault */ | |
635 | case 3: | |
636 | return TARGET_SIGNAL_FPE; /* arithmetic fault */ | |
637 | case 4: | |
638 | return TARGET_SIGNAL_FPE; /* floating point fault */ | |
c906108c SS |
639 | |
640 | /* constraint fault. This appears not to distinguish between | |
c5aa993b JM |
641 | a range constraint fault (which should be SIGFPE) and a privileged |
642 | fault (which should be SIGILL). */ | |
643 | case 5: | |
644 | return TARGET_SIGNAL_ILL; | |
c906108c | 645 | |
c5aa993b JM |
646 | case 6: |
647 | return TARGET_SIGNAL_SEGV; /* virtual memory fault */ | |
c906108c SS |
648 | |
649 | /* protection fault. This is for an out-of-range argument to | |
c5aa993b JM |
650 | "calls". I guess it also could be SIGILL. */ |
651 | case 7: | |
652 | return TARGET_SIGNAL_SEGV; | |
653 | ||
654 | case 8: | |
655 | return TARGET_SIGNAL_BUS; /* machine fault */ | |
656 | case 9: | |
657 | return TARGET_SIGNAL_BUS; /* structural fault */ | |
658 | case 0xa: | |
659 | return TARGET_SIGNAL_ILL; /* type fault */ | |
660 | case 0xb: | |
661 | return TARGET_SIGNAL_UNKNOWN; /* reserved fault */ | |
662 | case 0xc: | |
663 | return TARGET_SIGNAL_BUS; /* process fault */ | |
664 | case 0xd: | |
665 | return TARGET_SIGNAL_SEGV; /* descriptor fault */ | |
666 | case 0xe: | |
667 | return TARGET_SIGNAL_BUS; /* event fault */ | |
668 | case 0xf: | |
669 | return TARGET_SIGNAL_UNKNOWN; /* reserved fault */ | |
670 | case 0x10: | |
671 | return TARGET_SIGNAL_TRAP; /* single-step trace */ | |
672 | case 0x11: | |
673 | return TARGET_SIGNAL_TRAP; /* branch trace */ | |
674 | case 0x12: | |
675 | return TARGET_SIGNAL_TRAP; /* call trace */ | |
676 | case 0x13: | |
677 | return TARGET_SIGNAL_TRAP; /* return trace */ | |
678 | case 0x14: | |
679 | return TARGET_SIGNAL_TRAP; /* pre-return trace */ | |
680 | case 0x15: | |
681 | return TARGET_SIGNAL_TRAP; /* supervisor call trace */ | |
682 | case 0x16: | |
683 | return TARGET_SIGNAL_TRAP; /* breakpoint trace */ | |
684 | default: | |
685 | return TARGET_SIGNAL_UNKNOWN; | |
c906108c SS |
686 | } |
687 | } | |
688 | ||
689 | /****************************************/ | |
c5aa993b | 690 | /* MEM format */ |
c906108c SS |
691 | /****************************************/ |
692 | ||
c5aa993b JM |
693 | struct tabent |
694 | { | |
695 | char *name; | |
696 | char numops; | |
c906108c SS |
697 | }; |
698 | ||
c5aa993b JM |
699 | static int /* returns instruction length: 4 or 8 */ |
700 | mem (memaddr, word1, word2, noprint) | |
701 | unsigned long memaddr; | |
702 | unsigned long word1, word2; | |
703 | int noprint; /* If TRUE, return instruction length, but | |
c906108c SS |
704 | don't output any text. */ |
705 | { | |
c5aa993b JM |
706 | int i, j; |
707 | int len; | |
708 | int mode; | |
709 | int offset; | |
710 | const char *reg1, *reg2, *reg3; | |
711 | ||
712 | /* This lookup table is too sparse to make it worth typing in, but not | |
713 | * so large as to make a sparse array necessary. We allocate the | |
714 | * table at runtime, initialize all entries to empty, and copy the | |
715 | * real ones in from an initialization table. | |
716 | * | |
717 | * NOTE: In this table, the meaning of 'numops' is: | |
718 | * 1: single operand | |
719 | * 2: 2 operands, load instruction | |
720 | * -2: 2 operands, store instruction | |
721 | */ | |
722 | static struct tabent *mem_tab = NULL; | |
c906108c SS |
723 | /* Opcodes of 0x8X, 9X, aX, bX, and cX must be in the table. */ |
724 | #define MEM_MIN 0x80 | |
725 | #define MEM_MAX 0xcf | |
726 | #define MEM_SIZ ((MEM_MAX-MEM_MIN+1) * sizeof(struct tabent)) | |
727 | ||
c5aa993b JM |
728 | static struct |
729 | { | |
730 | int opcode; | |
731 | char *name; | |
732 | char numops; | |
733 | } | |
734 | mem_init[] = | |
735 | { | |
736 | 0x80, "ldob", 2, | |
737 | 0x82, "stob", -2, | |
738 | 0x84, "bx", 1, | |
739 | 0x85, "balx", 2, | |
740 | 0x86, "callx", 1, | |
741 | 0x88, "ldos", 2, | |
742 | 0x8a, "stos", -2, | |
743 | 0x8c, "lda", 2, | |
744 | 0x90, "ld", 2, | |
745 | 0x92, "st", -2, | |
746 | 0x98, "ldl", 2, | |
747 | 0x9a, "stl", -2, | |
748 | 0xa0, "ldt", 2, | |
749 | 0xa2, "stt", -2, | |
750 | 0xb0, "ldq", 2, | |
751 | 0xb2, "stq", -2, | |
752 | 0xc0, "ldib", 2, | |
753 | 0xc2, "stib", -2, | |
754 | 0xc8, "ldis", 2, | |
755 | 0xca, "stis", -2, | |
756 | 0, NULL, 0 | |
757 | }; | |
758 | ||
759 | if (mem_tab == NULL) | |
760 | { | |
761 | mem_tab = (struct tabent *) xmalloc (MEM_SIZ); | |
762 | memset (mem_tab, '\0', MEM_SIZ); | |
763 | for (i = 0; mem_init[i].opcode != 0; i++) | |
764 | { | |
765 | j = mem_init[i].opcode - MEM_MIN; | |
766 | mem_tab[j].name = mem_init[i].name; | |
767 | mem_tab[j].numops = mem_init[i].numops; | |
c906108c | 768 | } |
c5aa993b | 769 | } |
c906108c | 770 | |
c5aa993b JM |
771 | i = ((word1 >> 24) & 0xff) - MEM_MIN; |
772 | mode = (word1 >> 10) & 0xf; | |
c906108c | 773 | |
c5aa993b JM |
774 | if ((mem_tab[i].name != NULL) /* Valid instruction */ |
775 | && ((mode == 5) || (mode >= 12))) | |
776 | { /* With 32-bit displacement */ | |
777 | len = 8; | |
778 | } | |
779 | else | |
780 | { | |
781 | len = 4; | |
782 | } | |
c906108c | 783 | |
c5aa993b JM |
784 | if (noprint) |
785 | { | |
786 | return len; | |
787 | } | |
788 | abort (); | |
c906108c SS |
789 | } |
790 | ||
791 | /* Read the i960 instruction at 'memaddr' and return the address of | |
792 | the next instruction after that, or 0 if 'memaddr' is not the | |
793 | address of a valid instruction. The first word of the instruction | |
794 | is stored at 'pword1', and the second word, if any, is stored at | |
795 | 'pword2'. */ | |
796 | ||
797 | static CORE_ADDR | |
798 | next_insn (memaddr, pword1, pword2) | |
799 | unsigned int *pword1, *pword2; | |
800 | CORE_ADDR memaddr; | |
801 | { | |
802 | int len; | |
803 | char buf[8]; | |
804 | ||
805 | /* Read the two (potential) words of the instruction at once, | |
806 | to eliminate the overhead of two calls to read_memory (). | |
807 | FIXME: Loses if the first one is readable but the second is not | |
808 | (e.g. last word of the segment). */ | |
809 | ||
810 | read_memory (memaddr, buf, 8); | |
811 | *pword1 = extract_unsigned_integer (buf, 4); | |
812 | *pword2 = extract_unsigned_integer (buf + 4, 4); | |
813 | ||
c5aa993b | 814 | /* Divide instruction set into classes based on high 4 bits of opcode */ |
c906108c SS |
815 | |
816 | switch ((*pword1 >> 28) & 0xf) | |
817 | { | |
818 | case 0x0: | |
c5aa993b | 819 | case 0x1: /* ctrl */ |
c906108c SS |
820 | |
821 | case 0x2: | |
c5aa993b | 822 | case 0x3: /* cobr */ |
c906108c SS |
823 | |
824 | case 0x5: | |
825 | case 0x6: | |
c5aa993b | 826 | case 0x7: /* reg */ |
c906108c SS |
827 | len = 4; |
828 | break; | |
829 | ||
830 | case 0x8: | |
831 | case 0x9: | |
832 | case 0xa: | |
833 | case 0xb: | |
834 | case 0xc: | |
835 | len = mem (memaddr, *pword1, *pword2, 1); | |
836 | break; | |
837 | ||
c5aa993b | 838 | default: /* invalid instruction */ |
c906108c SS |
839 | len = 0; |
840 | break; | |
841 | } | |
842 | ||
843 | if (len) | |
844 | return memaddr + len; | |
845 | else | |
846 | return 0; | |
847 | } | |
848 | ||
849 | /* 'start_frame' is a variable in the MON960 runtime startup routine | |
850 | that contains the frame pointer of the 'start' routine (the routine | |
851 | that calls 'main'). By reading its contents out of remote memory, | |
852 | we can tell where the frame chain ends: backtraces should halt before | |
853 | they display this frame. */ | |
854 | ||
855 | int | |
856 | mon960_frame_chain_valid (chain, curframe) | |
c5aa993b JM |
857 | CORE_ADDR chain; |
858 | struct frame_info *curframe; | |
c906108c | 859 | { |
c5aa993b JM |
860 | struct symbol *sym; |
861 | struct minimal_symbol *msymbol; | |
862 | ||
863 | /* crtmon960.o is an assembler module that is assumed to be linked | |
864 | * first in an i80960 executable. It contains the true entry point; | |
865 | * it performs startup up initialization and then calls 'main'. | |
866 | * | |
867 | * 'sf' is the name of a variable in crtmon960.o that is set | |
868 | * during startup to the address of the first frame. | |
869 | * | |
870 | * 'a' is the address of that variable in 80960 memory. | |
871 | */ | |
872 | static char sf[] = "start_frame"; | |
873 | CORE_ADDR a; | |
874 | ||
875 | ||
876 | chain &= ~0x3f; /* Zero low 6 bits because previous frame pointers | |
877 | contain return status info in them. */ | |
878 | if (chain == 0) | |
879 | { | |
880 | return 0; | |
881 | } | |
c906108c | 882 | |
c5aa993b JM |
883 | sym = lookup_symbol (sf, 0, VAR_NAMESPACE, (int *) NULL, |
884 | (struct symtab **) NULL); | |
885 | if (sym != 0) | |
886 | { | |
887 | a = SYMBOL_VALUE (sym); | |
888 | } | |
889 | else | |
890 | { | |
891 | msymbol = lookup_minimal_symbol (sf, NULL, NULL); | |
892 | if (msymbol == NULL) | |
893 | return 0; | |
894 | a = SYMBOL_VALUE_ADDRESS (msymbol); | |
895 | } | |
c906108c | 896 | |
c5aa993b | 897 | return (chain != read_memory_integer (a, 4)); |
c906108c SS |
898 | } |
899 | ||
2acceee2 | 900 | |
c906108c SS |
901 | void |
902 | _initialize_i960_tdep () | |
903 | { | |
904 | check_host (); | |
905 | ||
906 | tm_print_insn = print_insn_i960; | |
907 | } |