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1 | /* Functions specific to running gdb native on IA-64 running Linux. |
2 | Copyright 1999, 2000 Free Software Foundation, Inc. | |
16461d7d KB |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
18 | Foundation, Inc., 59 Temple Place - Suite 330, | |
19 | Boston, MA 02111-1307, USA. */ | |
20 | ||
21 | #include "defs.h" | |
22 | #include "inferior.h" | |
23 | #include "target.h" | |
24 | #include "gdbcore.h" | |
25 | ||
26 | #include <signal.h> | |
27 | #include <sys/ptrace.h> | |
28 | #include <sys/wait.h> | |
29 | #ifdef HAVE_SYS_REG_H | |
30 | #include <sys/reg.h> | |
31 | #endif | |
32 | #include <sys/user.h> | |
33 | ||
34 | #include <asm/ptrace_offsets.h> | |
35 | #include <sys/procfs.h> | |
36 | ||
37 | /* These must match the order of the register names. | |
38 | ||
39 | Some sort of lookup table is needed because the offsets associated | |
40 | with the registers are all over the board. */ | |
41 | ||
42 | static int u_offsets[] = | |
43 | { | |
44 | /* general registers */ | |
45 | -1, /* gr0 not available; i.e, it's always zero */ | |
46 | PT_R1, | |
47 | PT_R2, | |
48 | PT_R3, | |
49 | PT_R4, | |
50 | PT_R5, | |
51 | PT_R6, | |
52 | PT_R7, | |
53 | PT_R8, | |
54 | PT_R9, | |
55 | PT_R10, | |
56 | PT_R11, | |
57 | PT_R12, | |
58 | PT_R13, | |
59 | PT_R14, | |
60 | PT_R15, | |
61 | PT_R16, | |
62 | PT_R17, | |
63 | PT_R18, | |
64 | PT_R19, | |
65 | PT_R20, | |
66 | PT_R21, | |
67 | PT_R22, | |
68 | PT_R23, | |
69 | PT_R24, | |
70 | PT_R25, | |
71 | PT_R26, | |
72 | PT_R27, | |
73 | PT_R28, | |
74 | PT_R29, | |
75 | PT_R30, | |
76 | PT_R31, | |
77 | /* gr32 through gr127 not directly available via the ptrace interface */ | |
78 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
79 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
80 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
81 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
82 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
83 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
84 | /* Floating point registers */ | |
85 | -1, -1, /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0) */ | |
86 | PT_F2, | |
87 | PT_F3, | |
88 | PT_F4, | |
89 | PT_F5, | |
90 | PT_F6, | |
91 | PT_F7, | |
92 | PT_F8, | |
93 | PT_F9, | |
94 | PT_F10, | |
95 | PT_F11, | |
96 | PT_F12, | |
97 | PT_F13, | |
98 | PT_F14, | |
99 | PT_F15, | |
100 | PT_F16, | |
101 | PT_F17, | |
102 | PT_F18, | |
103 | PT_F19, | |
104 | PT_F20, | |
105 | PT_F21, | |
106 | PT_F22, | |
107 | PT_F23, | |
108 | PT_F24, | |
109 | PT_F25, | |
110 | PT_F26, | |
111 | PT_F27, | |
112 | PT_F28, | |
113 | PT_F29, | |
114 | PT_F30, | |
115 | PT_F31, | |
116 | PT_F32, | |
117 | PT_F33, | |
118 | PT_F34, | |
119 | PT_F35, | |
120 | PT_F36, | |
121 | PT_F37, | |
122 | PT_F38, | |
123 | PT_F39, | |
124 | PT_F40, | |
125 | PT_F41, | |
126 | PT_F42, | |
127 | PT_F43, | |
128 | PT_F44, | |
129 | PT_F45, | |
130 | PT_F46, | |
131 | PT_F47, | |
132 | PT_F48, | |
133 | PT_F49, | |
134 | PT_F50, | |
135 | PT_F51, | |
136 | PT_F52, | |
137 | PT_F53, | |
138 | PT_F54, | |
139 | PT_F55, | |
140 | PT_F56, | |
141 | PT_F57, | |
142 | PT_F58, | |
143 | PT_F59, | |
144 | PT_F60, | |
145 | PT_F61, | |
146 | PT_F62, | |
147 | PT_F63, | |
148 | PT_F64, | |
149 | PT_F65, | |
150 | PT_F66, | |
151 | PT_F67, | |
152 | PT_F68, | |
153 | PT_F69, | |
154 | PT_F70, | |
155 | PT_F71, | |
156 | PT_F72, | |
157 | PT_F73, | |
158 | PT_F74, | |
159 | PT_F75, | |
160 | PT_F76, | |
161 | PT_F77, | |
162 | PT_F78, | |
163 | PT_F79, | |
164 | PT_F80, | |
165 | PT_F81, | |
166 | PT_F82, | |
167 | PT_F83, | |
168 | PT_F84, | |
169 | PT_F85, | |
170 | PT_F86, | |
171 | PT_F87, | |
172 | PT_F88, | |
173 | PT_F89, | |
174 | PT_F90, | |
175 | PT_F91, | |
176 | PT_F92, | |
177 | PT_F93, | |
178 | PT_F94, | |
179 | PT_F95, | |
180 | PT_F96, | |
181 | PT_F97, | |
182 | PT_F98, | |
183 | PT_F99, | |
184 | PT_F100, | |
185 | PT_F101, | |
186 | PT_F102, | |
187 | PT_F103, | |
188 | PT_F104, | |
189 | PT_F105, | |
190 | PT_F106, | |
191 | PT_F107, | |
192 | PT_F108, | |
193 | PT_F109, | |
194 | PT_F110, | |
195 | PT_F111, | |
196 | PT_F112, | |
197 | PT_F113, | |
198 | PT_F114, | |
199 | PT_F115, | |
200 | PT_F116, | |
201 | PT_F117, | |
202 | PT_F118, | |
203 | PT_F119, | |
204 | PT_F120, | |
205 | PT_F121, | |
206 | PT_F122, | |
207 | PT_F123, | |
208 | PT_F124, | |
209 | PT_F125, | |
210 | PT_F126, | |
211 | PT_F127, | |
212 | /* predicate registers - we don't fetch these individually */ | |
213 | -1, -1, -1, -1, -1, -1, -1, -1, | |
214 | -1, -1, -1, -1, -1, -1, -1, -1, | |
215 | -1, -1, -1, -1, -1, -1, -1, -1, | |
216 | -1, -1, -1, -1, -1, -1, -1, -1, | |
217 | -1, -1, -1, -1, -1, -1, -1, -1, | |
218 | -1, -1, -1, -1, -1, -1, -1, -1, | |
219 | -1, -1, -1, -1, -1, -1, -1, -1, | |
220 | -1, -1, -1, -1, -1, -1, -1, -1, | |
221 | /* branch registers */ | |
222 | PT_B0, | |
223 | PT_B1, | |
224 | PT_B2, | |
225 | PT_B3, | |
226 | PT_B4, | |
227 | PT_B5, | |
228 | PT_B6, | |
229 | PT_B7, | |
230 | /* virtual frame pointer and virtual return address pointer */ | |
231 | -1, -1, | |
232 | /* other registers */ | |
233 | PT_PR, | |
234 | PT_CR_IIP, /* ip */ | |
235 | PT_CR_IPSR, /* psr */ | |
236 | PT_CR_IFS, /* cfm */ | |
237 | /* kernel registers not visible via ptrace interface (?) */ | |
238 | -1, -1, -1, -1, -1, -1, -1, -1, | |
239 | /* hole */ | |
240 | -1, -1, -1, -1, -1, -1, -1, -1, | |
241 | PT_AR_RSC, | |
242 | PT_AR_BSP, | |
243 | PT_AR_BSPSTORE, | |
244 | PT_AR_RNAT, | |
245 | -1, | |
246 | -1, /* Not available: FCR, IA32 floating control register */ | |
247 | -1, -1, | |
248 | -1, /* Not available: EFLAG */ | |
249 | -1, /* Not available: CSD */ | |
250 | -1, /* Not available: SSD */ | |
251 | -1, /* Not available: CFLG */ | |
252 | -1, /* Not available: FSR */ | |
253 | -1, /* Not available: FIR */ | |
254 | -1, /* Not available: FDR */ | |
255 | -1, | |
256 | PT_AR_CCV, | |
257 | -1, -1, -1, | |
258 | PT_AR_UNAT, | |
259 | -1, -1, -1, | |
260 | PT_AR_FPSR, | |
261 | -1, -1, -1, | |
262 | -1, /* Not available: ITC */ | |
263 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
264 | -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
265 | PT_AR_PFS, | |
266 | PT_AR_LC, | |
267 | -1, /* Not available: EC, the Epilog Count register */ | |
268 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
269 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
270 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
271 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
272 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
273 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
274 | -1, | |
275 | /* nat bits - not fetched directly; instead we obtain these bits from | |
276 | either rnat or unat or from memory. */ | |
277 | -1, -1, -1, -1, -1, -1, -1, -1, | |
278 | -1, -1, -1, -1, -1, -1, -1, -1, | |
279 | -1, -1, -1, -1, -1, -1, -1, -1, | |
280 | -1, -1, -1, -1, -1, -1, -1, -1, | |
281 | -1, -1, -1, -1, -1, -1, -1, -1, | |
282 | -1, -1, -1, -1, -1, -1, -1, -1, | |
283 | -1, -1, -1, -1, -1, -1, -1, -1, | |
284 | -1, -1, -1, -1, -1, -1, -1, -1, | |
285 | -1, -1, -1, -1, -1, -1, -1, -1, | |
286 | -1, -1, -1, -1, -1, -1, -1, -1, | |
287 | -1, -1, -1, -1, -1, -1, -1, -1, | |
288 | -1, -1, -1, -1, -1, -1, -1, -1, | |
289 | -1, -1, -1, -1, -1, -1, -1, -1, | |
290 | -1, -1, -1, -1, -1, -1, -1, -1, | |
291 | -1, -1, -1, -1, -1, -1, -1, -1, | |
292 | -1, -1, -1, -1, -1, -1, -1, -1, | |
293 | }; | |
294 | ||
295 | CORE_ADDR | |
296 | register_addr (regno, blockend) | |
297 | int regno; | |
298 | CORE_ADDR blockend; | |
299 | { | |
300 | CORE_ADDR addr; | |
301 | ||
302 | if (regno < 0 || regno >= NUM_REGS) | |
303 | error ("Invalid register number %d.", regno); | |
304 | ||
305 | if (u_offsets[regno] == -1) | |
306 | addr = 0; | |
307 | else | |
308 | addr = (CORE_ADDR) u_offsets[regno]; | |
309 | ||
310 | return addr; | |
311 | } | |
312 | ||
313 | int ia64_cannot_fetch_register (regno) | |
314 | int regno; | |
315 | { | |
316 | return regno < 0 || regno >= NUM_REGS || u_offsets[regno] == -1; | |
317 | } | |
318 | ||
319 | int ia64_cannot_store_register (regno) | |
320 | int regno; | |
321 | { | |
322 | /* Rationale behind not permitting stores to bspstore... | |
323 | ||
324 | The IA-64 architecture provides bspstore and bsp which refer | |
325 | memory locations in the RSE's backing store. bspstore is the | |
326 | next location which will be written when the RSE needs to write | |
327 | to memory. bsp is the address at which r32 in the current frame | |
328 | would be found if it were written to the backing store. | |
329 | ||
330 | The IA-64 architecture provides read-only access to bsp and | |
331 | read/write access to bspstore (but only when the RSE is in | |
332 | the enforced lazy mode). It should be noted that stores | |
333 | to bspstore also affect the value of bsp. Changing bspstore | |
334 | does not affect the number of dirty entries between bspstore | |
335 | and bsp, so changing bspstore by N words will also cause bsp | |
336 | to be changed by (roughly) N as well. (It could be N-1 or N+1 | |
337 | depending upon where the NaT collection bits fall.) | |
338 | ||
339 | OTOH, the linux kernel provides read/write access to bsp (and | |
340 | currently read/write access to bspstore as well). But it | |
341 | is definitely the case that if you change one, the other | |
342 | will change at the same time. It is more useful to gdb to | |
343 | be able to change bsp. So in order to prevent strange and | |
344 | undesirable things from happening when a dummy stack frame | |
345 | is popped (after calling an inferior function), we allow | |
346 | bspstore to be read, but not written. (Note that popping | |
347 | a (generic) dummy stack frame causes all registers that | |
348 | were previously read from the inferior process to be written | |
349 | back.) */ | |
350 | ||
351 | return regno < 0 || regno >= NUM_REGS || u_offsets[regno] == -1 | |
352 | || regno == IA64_BSPSTORE_REGNUM; | |
353 | } | |
354 | ||
355 | void | |
356 | supply_gregset (gregsetp) | |
357 | gregset_t *gregsetp; | |
358 | { | |
359 | int regi; | |
360 | greg_t *regp = (greg_t *) gregsetp; | |
361 | ||
362 | for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++) | |
363 | { | |
364 | supply_register (regi, (char *) (regp + (regi - IA64_GR0_REGNUM))); | |
365 | } | |
366 | ||
367 | /* FIXME: NAT collection bits are at index 32; gotta deal with these | |
368 | somehow... */ | |
369 | ||
370 | supply_register (IA64_PR_REGNUM, (char *) (regp + 33)); | |
371 | ||
372 | for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++) | |
373 | { | |
374 | supply_register (regi, (char *) (regp + 34 + (regi - IA64_BR0_REGNUM))); | |
375 | } | |
376 | ||
377 | supply_register (IA64_IP_REGNUM, (char *) (regp + 42)); | |
378 | supply_register (IA64_CFM_REGNUM, (char *) (regp + 43)); | |
379 | supply_register (IA64_PSR_REGNUM, (char *) (regp + 44)); | |
380 | supply_register (IA64_RSC_REGNUM, (char *) (regp + 45)); | |
381 | supply_register (IA64_BSP_REGNUM, (char *) (regp + 46)); | |
382 | supply_register (IA64_BSPSTORE_REGNUM, (char *) (regp + 47)); | |
383 | supply_register (IA64_RNAT_REGNUM, (char *) (regp + 48)); | |
384 | supply_register (IA64_CCV_REGNUM, (char *) (regp + 49)); | |
385 | supply_register (IA64_UNAT_REGNUM, (char *) (regp + 50)); | |
386 | supply_register (IA64_FPSR_REGNUM, (char *) (regp + 51)); | |
387 | supply_register (IA64_PFS_REGNUM, (char *) (regp + 52)); | |
388 | supply_register (IA64_LC_REGNUM, (char *) (regp + 53)); | |
389 | supply_register (IA64_EC_REGNUM, (char *) (regp + 54)); | |
390 | } | |
391 | ||
392 | void | |
393 | fill_gregset (gregsetp, regno) | |
394 | gregset_t *gregsetp; | |
395 | int regno; | |
396 | { | |
76d689a6 KB |
397 | int regi; |
398 | greg_t *regp = (greg_t *) gregsetp; | |
399 | ||
400 | #define COPY_REG(_idx_,_regi_) \ | |
401 | if ((regno == -1) || regno == _regi_) \ | |
402 | memcpy (regp + _idx_, ®isters[REGISTER_BYTE (_regi_)], \ | |
403 | REGISTER_RAW_SIZE (_regi_)) | |
404 | ||
405 | for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++) | |
406 | { | |
407 | COPY_REG (regi - IA64_GR0_REGNUM, regi); | |
408 | } | |
409 | ||
410 | /* FIXME: NAT collection bits at index 32? */ | |
411 | ||
412 | COPY_REG (33, IA64_PR_REGNUM); | |
413 | ||
414 | for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++) | |
415 | { | |
416 | COPY_REG (34 + (regi - IA64_BR0_REGNUM), regi); | |
417 | } | |
418 | ||
419 | COPY_REG (42, IA64_IP_REGNUM); | |
420 | COPY_REG (43, IA64_CFM_REGNUM); | |
421 | COPY_REG (44, IA64_PSR_REGNUM); | |
422 | COPY_REG (45, IA64_RSC_REGNUM); | |
423 | COPY_REG (46, IA64_BSP_REGNUM); | |
424 | COPY_REG (47, IA64_BSPSTORE_REGNUM); | |
425 | COPY_REG (48, IA64_RNAT_REGNUM); | |
426 | COPY_REG (49, IA64_CCV_REGNUM); | |
427 | COPY_REG (50, IA64_UNAT_REGNUM); | |
428 | COPY_REG (51, IA64_FPSR_REGNUM); | |
429 | COPY_REG (52, IA64_PFS_REGNUM); | |
430 | COPY_REG (53, IA64_LC_REGNUM); | |
431 | COPY_REG (54, IA64_EC_REGNUM); | |
432 | } | |
433 | ||
434 | /* Given a pointer to a floating point register set in /proc format | |
435 | (fpregset_t *), unpack the register contents and supply them as gdb's | |
436 | idea of the current floating point register values. */ | |
437 | ||
438 | void | |
439 | supply_fpregset (fpregsetp) | |
440 | fpregset_t *fpregsetp; | |
441 | { | |
442 | register int regi; | |
443 | char *from; | |
444 | ||
445 | for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++) | |
446 | { | |
447 | from = (char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]); | |
448 | supply_register (regi, from); | |
449 | } | |
450 | } | |
451 | ||
452 | /* Given a pointer to a floating point register set in /proc format | |
453 | (fpregset_t *), update the register specified by REGNO from gdb's idea | |
454 | of the current floating point register set. If REGNO is -1, update | |
455 | them all. */ | |
456 | ||
457 | void | |
458 | fill_fpregset (fpregsetp, regno) | |
459 | fpregset_t *fpregsetp; | |
460 | int regno; | |
461 | { | |
462 | int regi; | |
463 | char *to; | |
464 | char *from; | |
465 | ||
466 | for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++) | |
467 | { | |
468 | if ((regno == -1) || (regno == regi)) | |
469 | { | |
470 | from = (char *) ®isters[REGISTER_BYTE (regi)]; | |
471 | to = (char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]); | |
472 | memcpy (to, from, REGISTER_RAW_SIZE (regi)); | |
473 | } | |
474 | } | |
16461d7d | 475 | } |
acf7b9e1 KB |
476 | |
477 | #define IA64_PSR_DB (1UL << 24) | |
478 | #define IA64_PSR_DD (1UL << 39) | |
479 | ||
480 | static void | |
481 | enable_watchpoints_in_psr (int pid) | |
482 | { | |
483 | CORE_ADDR psr; | |
484 | ||
485 | psr = read_register_pid (IA64_PSR_REGNUM, pid); | |
486 | if (!(psr & IA64_PSR_DB)) | |
487 | { | |
488 | psr |= IA64_PSR_DB; /* Set the db bit - this enables hardware | |
489 | watchpoints and breakpoints. */ | |
490 | write_register_pid (IA64_PSR_REGNUM, psr, pid); | |
491 | } | |
492 | } | |
493 | ||
494 | static long | |
495 | fetch_debug_register (int pid, int idx) | |
496 | { | |
497 | long val; | |
498 | int tid; | |
499 | ||
500 | tid = TIDGET(pid); | |
501 | if (tid == 0) | |
502 | tid = pid; | |
503 | ||
504 | val = ptrace (PT_READ_U, tid, (PTRACE_ARG3_TYPE) (PT_DBR + 8 * idx), 0); | |
505 | ||
506 | return val; | |
507 | } | |
508 | ||
509 | static void | |
510 | store_debug_register (int pid, int idx, long val) | |
511 | { | |
512 | int tid; | |
513 | ||
514 | tid = TIDGET(pid); | |
515 | if (tid == 0) | |
516 | tid = pid; | |
517 | ||
518 | (void) ptrace (PT_WRITE_U, tid, (PTRACE_ARG3_TYPE) (PT_DBR + 8 * idx), val); | |
519 | } | |
520 | ||
521 | static void | |
522 | fetch_debug_register_pair (int pid, int idx, long *dbr_addr, long *dbr_mask) | |
523 | { | |
524 | if (dbr_addr) | |
525 | *dbr_addr = fetch_debug_register (pid, 2 * idx); | |
526 | if (dbr_mask) | |
527 | *dbr_mask = fetch_debug_register (pid, 2 * idx + 1); | |
528 | } | |
529 | ||
530 | static void | |
531 | store_debug_register_pair (int pid, int idx, long *dbr_addr, long *dbr_mask) | |
532 | { | |
533 | if (dbr_addr) | |
534 | store_debug_register (pid, 2 * idx, *dbr_addr); | |
535 | if (dbr_mask) | |
536 | store_debug_register (pid, 2 * idx + 1, *dbr_mask); | |
537 | } | |
538 | ||
539 | static int | |
540 | is_power_of_2 (int val) | |
541 | { | |
542 | int i, onecount; | |
543 | ||
544 | onecount = 0; | |
545 | for (i = 0; i < 8 * sizeof (val); i++) | |
546 | if (val & (1 << i)) | |
547 | onecount++; | |
548 | ||
549 | return onecount <= 1; | |
550 | } | |
551 | ||
552 | int | |
553 | ia64_linux_insert_watchpoint (int pid, CORE_ADDR addr, int len, int rw) | |
554 | { | |
555 | int idx; | |
556 | long dbr_addr, dbr_mask; | |
557 | int max_watchpoints = 4; | |
558 | ||
559 | if (len <= 0 || !is_power_of_2 (len)) | |
560 | return -1; | |
561 | ||
562 | for (idx = 0; idx < max_watchpoints; idx++) | |
563 | { | |
564 | fetch_debug_register_pair (pid, idx, NULL, &dbr_mask); | |
565 | if ((dbr_mask & (0x3UL << 62)) == 0) | |
566 | { | |
567 | /* Exit loop if both r and w bits clear */ | |
568 | break; | |
569 | } | |
570 | } | |
571 | ||
572 | if (idx == max_watchpoints) | |
573 | return -1; | |
574 | ||
575 | dbr_addr = (long) addr; | |
576 | dbr_mask = (~(len - 1) & 0x00ffffffffffffffL); /* construct mask to match */ | |
577 | dbr_mask |= 0x0800000000000000L; /* Only match privilege level 3 */ | |
578 | switch (rw) | |
579 | { | |
580 | case hw_write: | |
581 | dbr_mask |= (1L << 62); /* Set w bit */ | |
582 | break; | |
583 | case hw_read: | |
584 | dbr_mask |= (1L << 63); /* Set r bit */ | |
585 | break; | |
586 | case hw_access: | |
587 | dbr_mask |= (3L << 62); /* Set both r and w bits */ | |
588 | break; | |
589 | default: | |
590 | return -1; | |
591 | } | |
592 | ||
593 | store_debug_register_pair (pid, idx, &dbr_addr, &dbr_mask); | |
594 | enable_watchpoints_in_psr (pid); | |
595 | ||
596 | return 0; | |
597 | } | |
598 | ||
599 | int | |
600 | ia64_linux_remove_watchpoint (int pid, CORE_ADDR addr, int len) | |
601 | { | |
602 | int idx; | |
603 | long dbr_addr, dbr_mask; | |
604 | int max_watchpoints = 4; | |
605 | ||
606 | if (len <= 0 || !is_power_of_2 (len)) | |
607 | return -1; | |
608 | ||
609 | for (idx = 0; idx < max_watchpoints; idx++) | |
610 | { | |
611 | fetch_debug_register_pair (pid, idx, &dbr_addr, &dbr_mask); | |
612 | if ((dbr_mask & (0x3UL << 62)) && addr == (CORE_ADDR) dbr_addr) | |
613 | { | |
614 | dbr_addr = 0; | |
615 | dbr_mask = 0; | |
616 | store_debug_register_pair (pid, idx, &dbr_addr, &dbr_mask); | |
617 | return 0; | |
618 | } | |
619 | } | |
620 | return -1; | |
621 | } | |
622 | ||
623 | CORE_ADDR | |
624 | ia64_linux_stopped_by_watchpoint (int pid) | |
625 | { | |
626 | CORE_ADDR psr; | |
627 | int tid; | |
628 | struct siginfo siginfo; | |
629 | ||
630 | tid = TIDGET(pid); | |
631 | if (tid == 0) | |
632 | tid = pid; | |
633 | ||
634 | errno = 0; | |
635 | ptrace (PTRACE_GETSIGINFO, tid, (PTRACE_ARG3_TYPE) 0, &siginfo); | |
636 | ||
637 | if (errno != 0 || siginfo.si_code != 4 /* TRAP_HWBKPT */) | |
638 | return 0; | |
639 | ||
640 | psr = read_register_pid (IA64_PSR_REGNUM, pid); | |
641 | psr |= IA64_PSR_DD; /* Set the dd bit - this will disable the watchpoint | |
642 | for the next instruction */ | |
643 | write_register_pid (IA64_PSR_REGNUM, psr, pid); | |
644 | ||
645 | return (CORE_ADDR) siginfo.si_addr; | |
646 | } |