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[deliverable/binutils-gdb.git] / gdb / ia64-tdep.c
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16461d7d 1/* Target-dependent code for the IA-64 for GDB, the GNU debugger.
ca557f44 2
0fd88904 3 Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software
9fc9f5e2 4 Foundation, Inc.
16461d7d
KB		 5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
22
23#include "defs.h"
24#include "inferior.h"
16461d7d 25#include "gdbcore.h"
8064c6ae 26#include "arch-utils.h"
16461d7d 27#include "floatformat.h"
4e052eda 28#include "regcache.h"
004d836a
JJ		 29#include "reggroups.h"
30#include "frame.h"
31#include "frame-base.h"
32#include "frame-unwind.h"
d16aafd8 33#include "doublest.h"
fd0407d6 34#include "value.h"
bd1ce8ba 35#include "gdb_assert.h"
16461d7d
KB		 36#include "objfiles.h"
37#include "elf/common.h" /* for DT_PLTGOT value */
244bc108 38#include "elf-bfd.h"
a89aa300 39#include "dis-asm.h"
7d9b040b 40#include "infcall.h"
b33e8514 41#include "osabi.h"
9fc9f5e2 42#include "ia64-tdep.h"
16461d7d 43
968d1cb4 44#ifdef HAVE_LIBUNWIND_IA64_H
8973ff21 45#include "elf/ia64.h" /* for PT_IA_64_UNWIND value */
968d1cb4
JJ		 46#include "libunwind-frame.h"
47#include "libunwind-ia64.h"
c5a27d9c
JJ		 48
49/* Note: KERNEL_START is supposed to be an address which is not going
50 to ever contain any valid unwind info. For ia64 linux, the choice
51 of 0xc000000000000000 is fairly safe since that's uncached space.
52
53 We use KERNEL_START as follows: after obtaining the kernel's
54 unwind table via getunwind(), we project its unwind data into
55 address-range KERNEL_START-(KERNEL_START+ktab_size) and then
56 when ia64_access_mem() sees a memory access to this
57 address-range, we redirect it to ktab instead.
58
59 None of this hackery is needed with a modern kernel/libcs
60 which uses the kernel virtual DSO to provide access to the
61 kernel's unwind info. In that case, ktab_size remains 0 and
62 hence the value of KERNEL_START doesn't matter. */
63
64#define KERNEL_START 0xc000000000000000ULL
65
66static size_t ktab_size = 0;
67struct ia64_table_entry
68 {
69 uint64_t start_offset;
70 uint64_t end_offset;
71 uint64_t info_offset;
72 };
73
74static struct ia64_table_entry *ktab = NULL;
75
968d1cb4
JJ		 76#endif
77
698cb3f0
KB		 78/* An enumeration of the different IA-64 instruction types. */
79
16461d7d
KB		 80typedef enum instruction_type
81{
82 A, /* Integer ALU ; I-unit or M-unit */
83 I, /* Non-ALU integer; I-unit */
84 M, /* Memory ; M-unit */
85 F, /* Floating-point ; F-unit */
86 B, /* Branch ; B-unit */
87 L, /* Extended (L+X) ; I-unit */
88 X, /* Extended (L+X) ; I-unit */
89 undefined /* undefined or reserved */
90} instruction_type;
91
92/* We represent IA-64 PC addresses as the value of the instruction
93 pointer or'd with some bit combination in the low nibble which
94 represents the slot number in the bundle addressed by the
95 instruction pointer. The problem is that the Linux kernel
96 multiplies its slot numbers (for exceptions) by one while the
97 disassembler multiplies its slot numbers by 6. In addition, I've
98 heard it said that the simulator uses 1 as the multiplier.
99
100 I've fixed the disassembler so that the bytes_per_line field will
101 be the slot multiplier. If bytes_per_line comes in as zero, it
102 is set to six (which is how it was set up initially). -- objdump
103 displays pretty disassembly dumps with this value. For our purposes,
104 we'll set bytes_per_line to SLOT_MULTIPLIER. This is okay since we
105 never want to also display the raw bytes the way objdump does. */
106
107#define SLOT_MULTIPLIER 1
108
109/* Length in bytes of an instruction bundle */
110
111#define BUNDLE_LEN 16
112
16461d7d
KB		 113static gdbarch_init_ftype ia64_gdbarch_init;
114
115static gdbarch_register_name_ftype ia64_register_name;
004d836a 116static gdbarch_register_type_ftype ia64_register_type;
16461d7d 117static gdbarch_breakpoint_from_pc_ftype ia64_breakpoint_from_pc;
16461d7d 118static gdbarch_skip_prologue_ftype ia64_skip_prologue;
64a5b29c 119static struct type *is_float_or_hfa_type (struct type *t);
b33e8514 120static CORE_ADDR ia64_find_global_pointer (CORE_ADDR faddr);
16461d7d 121
004d836a
JJ		 122static struct type *builtin_type_ia64_ext;
123
124#define NUM_IA64_RAW_REGS 462
16461d7d 125
16461d7d
KB		 126static int sp_regnum = IA64_GR12_REGNUM;
127static int fp_regnum = IA64_VFP_REGNUM;
128static int lr_regnum = IA64_VRAP_REGNUM;
129
004d836a 130/* NOTE: we treat the register stack registers r32-r127 as pseudo-registers because
4afcc598 131 they may not be accessible via the ptrace register get/set interfaces. */
004d836a
JJ		 132enum pseudo_regs { FIRST_PSEUDO_REGNUM = NUM_IA64_RAW_REGS, VBOF_REGNUM = IA64_NAT127_REGNUM + 1, V32_REGNUM,
133 V127_REGNUM = V32_REGNUM + 95,
134 VP0_REGNUM, VP16_REGNUM = VP0_REGNUM + 16, VP63_REGNUM = VP0_REGNUM + 63, LAST_PSEUDO_REGNUM };
16461d7d
KB		 135
136/* Array of register names; There should be ia64_num_regs strings in
137 the initializer. */
138
139static char *ia64_register_names[] =
140{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
141 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
142 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
143 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
004d836a
JJ		 144 "", "", "", "", "", "", "", "",
145 "", "", "", "", "", "", "", "",
146 "", "", "", "", "", "", "", "",
147 "", "", "", "", "", "", "", "",
148 "", "", "", "", "", "", "", "",
149 "", "", "", "", "", "", "", "",
150 "", "", "", "", "", "", "", "",
151 "", "", "", "", "", "", "", "",
152 "", "", "", "", "", "", "", "",
153 "", "", "", "", "", "", "", "",
154 "", "", "", "", "", "", "", "",
155 "", "", "", "", "", "", "", "",
16461d7d
KB		 156
157 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
158 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
159 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
160 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
161 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
162 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
163 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
164 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
165 "f64", "f65", "f66", "f67", "f68", "f69", "f70", "f71",
166 "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79",
167 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87",
168 "f88", "f89", "f90", "f91", "f92", "f93", "f94", "f95",
169 "f96", "f97", "f98", "f99", "f100", "f101", "f102", "f103",
170 "f104", "f105", "f106", "f107", "f108", "f109", "f110", "f111",
171 "f112", "f113", "f114", "f115", "f116", "f117", "f118", "f119",
172 "f120", "f121", "f122", "f123", "f124", "f125", "f126", "f127",
173
004d836a
JJ		 174 "", "", "", "", "", "", "", "",
175 "", "", "", "", "", "", "", "",
176 "", "", "", "", "", "", "", "",
177 "", "", "", "", "", "", "", "",
178 "", "", "", "", "", "", "", "",
179 "", "", "", "", "", "", "", "",
180 "", "", "", "", "", "", "", "",
181 "", "", "", "", "", "", "", "",
16461d7d
KB		 182
183 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
184
185 "vfp", "vrap",
186
187 "pr", "ip", "psr", "cfm",
188
189 "kr0", "kr1", "kr2", "kr3", "kr4", "kr5", "kr6", "kr7",
190 "", "", "", "", "", "", "", "",
191 "rsc", "bsp", "bspstore", "rnat",
192 "", "fcr", "", "",
193 "eflag", "csd", "ssd", "cflg", "fsr", "fir", "fdr", "",
194 "ccv", "", "", "", "unat", "", "", "",
195 "fpsr", "", "", "", "itc",
196 "", "", "", "", "", "", "", "", "", "",
197 "", "", "", "", "", "", "", "", "",
198 "pfs", "lc", "ec",
199 "", "", "", "", "", "", "", "", "", "",
200 "", "", "", "", "", "", "", "", "", "",
201 "", "", "", "", "", "", "", "", "", "",
202 "", "", "", "", "", "", "", "", "", "",
203 "", "", "", "", "", "", "", "", "", "",
204 "", "", "", "", "", "", "", "", "", "",
205 "",
206 "nat0", "nat1", "nat2", "nat3", "nat4", "nat5", "nat6", "nat7",
207 "nat8", "nat9", "nat10", "nat11", "nat12", "nat13", "nat14", "nat15",
208 "nat16", "nat17", "nat18", "nat19", "nat20", "nat21", "nat22", "nat23",
209 "nat24", "nat25", "nat26", "nat27", "nat28", "nat29", "nat30", "nat31",
210 "nat32", "nat33", "nat34", "nat35", "nat36", "nat37", "nat38", "nat39",
211 "nat40", "nat41", "nat42", "nat43", "nat44", "nat45", "nat46", "nat47",
212 "nat48", "nat49", "nat50", "nat51", "nat52", "nat53", "nat54", "nat55",
213 "nat56", "nat57", "nat58", "nat59", "nat60", "nat61", "nat62", "nat63",
214 "nat64", "nat65", "nat66", "nat67", "nat68", "nat69", "nat70", "nat71",
215 "nat72", "nat73", "nat74", "nat75", "nat76", "nat77", "nat78", "nat79",
216 "nat80", "nat81", "nat82", "nat83", "nat84", "nat85", "nat86", "nat87",
217 "nat88", "nat89", "nat90", "nat91", "nat92", "nat93", "nat94", "nat95",
218 "nat96", "nat97", "nat98", "nat99", "nat100","nat101","nat102","nat103",
219 "nat104","nat105","nat106","nat107","nat108","nat109","nat110","nat111",
220 "nat112","nat113","nat114","nat115","nat116","nat117","nat118","nat119",
221 "nat120","nat121","nat122","nat123","nat124","nat125","nat126","nat127",
004d836a
JJ		 222
223 "bof",
224
225 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
226 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
227 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
228 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
229 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
230 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
231 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
232 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
233 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
234 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
235 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
236 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
237
238 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7",
239 "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15",
240 "p16", "p17", "p18", "p19", "p20", "p21", "p22", "p23",
241 "p24", "p25", "p26", "p27", "p28", "p29", "p30", "p31",
242 "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39",
243 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47",
244 "p48", "p49", "p50", "p51", "p52", "p53", "p54", "p55",
245 "p56", "p57", "p58", "p59", "p60", "p61", "p62", "p63",
16461d7d
KB		 246};
247
004d836a
JJ		 248struct ia64_frame_cache
249{
250 CORE_ADDR base; /* frame pointer base for frame */
251 CORE_ADDR pc; /* function start pc for frame */
252 CORE_ADDR saved_sp; /* stack pointer for frame */
253 CORE_ADDR bsp; /* points at r32 for the current frame */
254 CORE_ADDR cfm; /* cfm value for current frame */
4afcc598 255 CORE_ADDR prev_cfm; /* cfm value for previous frame */
004d836a
JJ		 256 int frameless;
257 int sof; /* Size of frame (decoded from cfm value) */
258 int sol; /* Size of locals (decoded from cfm value) */
259 int sor; /* Number of rotating registers. (decoded from cfm value) */
260 CORE_ADDR after_prologue;
261 /* Address of first instruction after the last
262 prologue instruction; Note that there may
263 be instructions from the function's body
264 intermingled with the prologue. */
265 int mem_stack_frame_size;
266 /* Size of the memory stack frame (may be zero),
267 or -1 if it has not been determined yet. */
268 int fp_reg; /* Register number (if any) used a frame pointer
244bc108 269 for this frame. 0 if no register is being used
16461d7d 270 as the frame pointer. */
004d836a
JJ		 271
272 /* Saved registers. */
273 CORE_ADDR saved_regs[NUM_IA64_RAW_REGS];
274
275};
244bc108 276
698cb3f0
KB		 277#define SIGCONTEXT_REGISTER_ADDRESS \
278 (gdbarch_tdep (current_gdbarch)->sigcontext_register_address)
16461d7d 279
004d836a
JJ		 280int
281ia64_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
282 struct reggroup *group)
16461d7d 283{
004d836a
JJ		 284 int vector_p;
285 int float_p;
286 int raw_p;
287 if (group == all_reggroup)
288 return 1;
289 vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
290 float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
291 raw_p = regnum < NUM_IA64_RAW_REGS;
292 if (group == float_reggroup)
293 return float_p;
294 if (group == vector_reggroup)
295 return vector_p;
296 if (group == general_reggroup)
297 return (!vector_p && !float_p);
298 if (group == save_reggroup || group == restore_reggroup)
299 return raw_p;
300 return 0;
16461d7d
KB		 301}
302
004d836a
JJ		 303static const char *
304ia64_register_name (int reg)
16461d7d 305{
004d836a 306 return ia64_register_names[reg];
16461d7d
KB		 307}
308
004d836a
JJ		 309struct type *
310ia64_register_type (struct gdbarch *arch, int reg)
16461d7d 311{
004d836a
JJ		 312 if (reg >= IA64_FR0_REGNUM && reg <= IA64_FR127_REGNUM)
313 return builtin_type_ia64_ext;
314 else
315 return builtin_type_long;
16461d7d
KB		 316}
317
a78f21af 318static int
004d836a 319ia64_dwarf_reg_to_regnum (int reg)
16461d7d 320{
004d836a
JJ		 321 if (reg >= IA64_GR32_REGNUM && reg <= IA64_GR127_REGNUM)
322 return V32_REGNUM + (reg - IA64_GR32_REGNUM);
323 return reg;
16461d7d
KB		 324}
325
4afcc598 326static int
7be0c536 327floatformat_valid (const struct floatformat *fmt, const char *from)
4afcc598
JJ		 328{
329 return 1;
330}
331
16461d7d
KB		 332const struct floatformat floatformat_ia64_ext =
333{
334 floatformat_little, 82, 0, 1, 17, 65535, 0x1ffff, 18, 64,
4afcc598 335 floatformat_intbit_yes, "floatformat_ia64_ext", floatformat_valid
16461d7d
KB		 336};
337
16461d7d
KB		 338
339/* Extract ``len'' bits from an instruction bundle starting at
340 bit ``from''. */
341
244bc108 342static long long
16461d7d
KB		 343extract_bit_field (char *bundle, int from, int len)
344{
345 long long result = 0LL;
346 int to = from + len;
347 int from_byte = from / 8;
348 int to_byte = to / 8;
349 unsigned char *b = (unsigned char *) bundle;
350 unsigned char c;
351 int lshift;
352 int i;
353
354 c = b[from_byte];
355 if (from_byte == to_byte)
356 c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
357 result = c >> (from % 8);
358 lshift = 8 - (from % 8);
359
360 for (i = from_byte+1; i < to_byte; i++)
361 {
362 result |= ((long long) b[i]) << lshift;
363 lshift += 8;
364 }
365
366 if (from_byte < to_byte && (to % 8 != 0))
367 {
368 c = b[to_byte];
369 c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
370 result |= ((long long) c) << lshift;
371 }
372
373 return result;
374}
375
376/* Replace the specified bits in an instruction bundle */
377
244bc108 378static void
16461d7d
KB		 379replace_bit_field (char *bundle, long long val, int from, int len)
380{
381 int to = from + len;
382 int from_byte = from / 8;
383 int to_byte = to / 8;
384 unsigned char *b = (unsigned char *) bundle;
385 unsigned char c;
386
387 if (from_byte == to_byte)
388 {
389 unsigned char left, right;
390 c = b[from_byte];
391 left = (c >> (to % 8)) << (to % 8);
392 right = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
393 c = (unsigned char) (val & 0xff);
394 c = (unsigned char) (c << (from % 8 + 8 - to % 8)) >> (8 - to % 8);
395 c |= right | left;
396 b[from_byte] = c;
397 }
398 else
399 {
400 int i;
401 c = b[from_byte];
402 c = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
403 c = c | (val << (from % 8));
404 b[from_byte] = c;
405 val >>= 8 - from % 8;
406
407 for (i = from_byte+1; i < to_byte; i++)
408 {
409 c = val & 0xff;
410 val >>= 8;
411 b[i] = c;
412 }
413
414 if (to % 8 != 0)
415 {
416 unsigned char cv = (unsigned char) val;
417 c = b[to_byte];
418 c = c >> (to % 8) << (to % 8);
419 c |= ((unsigned char) (cv << (8 - to % 8))) >> (8 - to % 8);
420 b[to_byte] = c;
421 }
422 }
423}
424
425/* Return the contents of slot N (for N = 0, 1, or 2) in
426 and instruction bundle */
427
244bc108 428static long long
2fc3ac7e 429slotN_contents (char *bundle, int slotnum)
16461d7d
KB		 430{
431 return extract_bit_field (bundle, 5+41*slotnum, 41);
432}
433
434/* Store an instruction in an instruction bundle */
435
244bc108 436static void
2fc3ac7e 437replace_slotN_contents (char *bundle, long long instr, int slotnum)
16461d7d
KB		 438{
439 replace_bit_field (bundle, instr, 5+41*slotnum, 41);
440}
441
64a5b29c 442static enum instruction_type template_encoding_table[32][3] =
16461d7d
KB		 443{
444 { M, I, I }, /* 00 */
445 { M, I, I }, /* 01 */
446 { M, I, I }, /* 02 */
447 { M, I, I }, /* 03 */
448 { M, L, X }, /* 04 */
449 { M, L, X }, /* 05 */
450 { undefined, undefined, undefined }, /* 06 */
451 { undefined, undefined, undefined }, /* 07 */
452 { M, M, I }, /* 08 */
453 { M, M, I }, /* 09 */
454 { M, M, I }, /* 0A */
455 { M, M, I }, /* 0B */
456 { M, F, I }, /* 0C */
457 { M, F, I }, /* 0D */
458 { M, M, F }, /* 0E */
459 { M, M, F }, /* 0F */
460 { M, I, B }, /* 10 */
461 { M, I, B }, /* 11 */
462 { M, B, B }, /* 12 */
463 { M, B, B }, /* 13 */
464 { undefined, undefined, undefined }, /* 14 */
465 { undefined, undefined, undefined }, /* 15 */
466 { B, B, B }, /* 16 */
467 { B, B, B }, /* 17 */
468 { M, M, B }, /* 18 */
469 { M, M, B }, /* 19 */
470 { undefined, undefined, undefined }, /* 1A */
471 { undefined, undefined, undefined }, /* 1B */
472 { M, F, B }, /* 1C */
473 { M, F, B }, /* 1D */
474 { undefined, undefined, undefined }, /* 1E */
475 { undefined, undefined, undefined }, /* 1F */
476};
477
478/* Fetch and (partially) decode an instruction at ADDR and return the
479 address of the next instruction to fetch. */
480
481static CORE_ADDR
482fetch_instruction (CORE_ADDR addr, instruction_type *it, long long *instr)
483{
484 char bundle[BUNDLE_LEN];
485 int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER;
486 long long template;
487 int val;
488
c26e1c2b
KB		 489 /* Warn about slot numbers greater than 2. We used to generate
490 an error here on the assumption that the user entered an invalid
491 address. But, sometimes GDB itself requests an invalid address.
492 This can (easily) happen when execution stops in a function for
493 which there are no symbols. The prologue scanner will attempt to
494 find the beginning of the function - if the nearest symbol
495 happens to not be aligned on a bundle boundary (16 bytes), the
496 resulting starting address will cause GDB to think that the slot
497 number is too large.
498
499 So we warn about it and set the slot number to zero. It is
500 not necessarily a fatal condition, particularly if debugging
501 at the assembly language level. */
16461d7d 502 if (slotnum > 2)
c26e1c2b 503 {
8a3fe4f8
AC		 504 warning (_("Can't fetch instructions for slot numbers greater than 2.\n"
505 "Using slot 0 instead"));
c26e1c2b
KB		 506 slotnum = 0;
507 }
16461d7d
KB		 508
509 addr &= ~0x0f;
510
511 val = target_read_memory (addr, bundle, BUNDLE_LEN);
512
513 if (val != 0)
514 return 0;
515
516 *instr = slotN_contents (bundle, slotnum);
517 template = extract_bit_field (bundle, 0, 5);
518 *it = template_encoding_table[(int)template][slotnum];
519
64a5b29c 520 if (slotnum == 2 || (slotnum == 1 && *it == L))
16461d7d
KB		 521 addr += 16;
522 else
523 addr += (slotnum + 1) * SLOT_MULTIPLIER;
524
525 return addr;
526}
527
528/* There are 5 different break instructions (break.i, break.b,
529 break.m, break.f, and break.x), but they all have the same
530 encoding. (The five bit template in the low five bits of the
531 instruction bundle distinguishes one from another.)
532
533 The runtime architecture manual specifies that break instructions
534 used for debugging purposes must have the upper two bits of the 21
535 bit immediate set to a 0 and a 1 respectively. A breakpoint
536 instruction encodes the most significant bit of its 21 bit
537 immediate at bit 36 of the 41 bit instruction. The penultimate msb
538 is at bit 25 which leads to the pattern below.
539
540 Originally, I had this set up to do, e.g, a "break.i 0x80000" But
541 it turns out that 0x80000 was used as the syscall break in the early
542 simulators. So I changed the pattern slightly to do "break.i 0x080001"
543 instead. But that didn't work either (I later found out that this
544 pattern was used by the simulator that I was using.) So I ended up
545 using the pattern seen below. */
546
547#if 0
aaab4dba 548#define IA64_BREAKPOINT 0x00002000040LL
16461d7d 549#endif
aaab4dba 550#define IA64_BREAKPOINT 0x00003333300LL
16461d7d
KB		 551
552static int
5a168c78 553ia64_memory_insert_breakpoint (CORE_ADDR addr, bfd_byte *contents_cache)
16461d7d
KB		 554{
555 char bundle[BUNDLE_LEN];
556 int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER;
557 long long instr;
558 int val;
126fa72d 559 int template;
16461d7d
KB		 560
561 if (slotnum > 2)
8a3fe4f8 562 error (_("Can't insert breakpoint for slot numbers greater than 2."));
16461d7d
KB		 563
564 addr &= ~0x0f;
565
566 val = target_read_memory (addr, bundle, BUNDLE_LEN);
126fa72d
PS		 567
568 /* Check for L type instruction in 2nd slot, if present then
569 bump up the slot number to the 3rd slot */
570 template = extract_bit_field (bundle, 0, 5);
571 if (slotnum == 1 && template_encoding_table[template][1] == L)
572 {
573 slotnum = 2;
574 }
575
16461d7d
KB		 576 instr = slotN_contents (bundle, slotnum);
577 memcpy(contents_cache, &instr, sizeof(instr));
aaab4dba 578 replace_slotN_contents (bundle, IA64_BREAKPOINT, slotnum);
16461d7d
KB		 579 if (val == 0)
580 target_write_memory (addr, bundle, BUNDLE_LEN);
581
582 return val;
583}
584
585static int
5a168c78 586ia64_memory_remove_breakpoint (CORE_ADDR addr, bfd_byte *contents_cache)
16461d7d
KB		 587{
588 char bundle[BUNDLE_LEN];
589 int slotnum = (addr & 0x0f) / SLOT_MULTIPLIER;
590 long long instr;
591 int val;
126fa72d 592 int template;
16461d7d
KB		 593
594 addr &= ~0x0f;
595
596 val = target_read_memory (addr, bundle, BUNDLE_LEN);
126fa72d
PS		 597
598 /* Check for L type instruction in 2nd slot, if present then
599 bump up the slot number to the 3rd slot */
600 template = extract_bit_field (bundle, 0, 5);
601 if (slotnum == 1 && template_encoding_table[template][1] == L)
602 {
603 slotnum = 2;
604 }
605
16461d7d
KB		 606 memcpy (&instr, contents_cache, sizeof instr);
607 replace_slotN_contents (bundle, instr, slotnum);
608 if (val == 0)
609 target_write_memory (addr, bundle, BUNDLE_LEN);
610
611 return val;
612}
613
614/* We don't really want to use this, but remote.c needs to call it in order
615 to figure out if Z-packets are supported or not. Oh, well. */
f4f9705a 616const unsigned char *
fba45db2 617ia64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
16461d7d
KB		 618{
619 static unsigned char breakpoint[] =
620 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
621 *lenptr = sizeof (breakpoint);
622#if 0
623 *pcptr &= ~0x0f;
624#endif
625 return breakpoint;
626}
627
a78f21af 628static CORE_ADDR
39f77062 629ia64_read_pc (ptid_t ptid)
16461d7d 630{
39f77062
KB		 631 CORE_ADDR psr_value = read_register_pid (IA64_PSR_REGNUM, ptid);
632 CORE_ADDR pc_value = read_register_pid (IA64_IP_REGNUM, ptid);
16461d7d
KB		 633 int slot_num = (psr_value >> 41) & 3;
634
635 return pc_value | (slot_num * SLOT_MULTIPLIER);
636}
637
54a5c8d8 638void
39f77062 639ia64_write_pc (CORE_ADDR new_pc, ptid_t ptid)
16461d7d
KB		 640{
641 int slot_num = (int) (new_pc & 0xf) / SLOT_MULTIPLIER;
39f77062 642 CORE_ADDR psr_value = read_register_pid (IA64_PSR_REGNUM, ptid);
16461d7d
KB		 643 psr_value &= ~(3LL << 41);
644 psr_value |= (CORE_ADDR)(slot_num & 0x3) << 41;
645
646 new_pc &= ~0xfLL;
647
39f77062
KB		 648 write_register_pid (IA64_PSR_REGNUM, psr_value, ptid);
649 write_register_pid (IA64_IP_REGNUM, new_pc, ptid);
16461d7d
KB		 650}
651
652#define IS_NaT_COLLECTION_ADDR(addr) ((((addr) >> 3) & 0x3f) == 0x3f)
653
654/* Returns the address of the slot that's NSLOTS slots away from
655 the address ADDR. NSLOTS may be positive or negative. */
656static CORE_ADDR
657rse_address_add(CORE_ADDR addr, int nslots)
658{
659 CORE_ADDR new_addr;
660 int mandatory_nat_slots = nslots / 63;
661 int direction = nslots < 0 ? -1 : 1;
662
663 new_addr = addr + 8 * (nslots + mandatory_nat_slots);
664
665 if ((new_addr >> 9) != ((addr + 8 * 64 * mandatory_nat_slots) >> 9))
666 new_addr += 8 * direction;
667
668 if (IS_NaT_COLLECTION_ADDR(new_addr))
669 new_addr += 8 * direction;
670
671 return new_addr;
672}
673
004d836a
JJ		 674static void
675ia64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
88d82102 676 int regnum, gdb_byte *buf)
16461d7d 677{
004d836a 678 if (regnum >= V32_REGNUM && regnum <= V127_REGNUM)
244bc108 679 {
88d82102 680#ifdef HAVE_LIBUNWIND_IA64_H
c5a27d9c
JJ		 681 /* First try and use the libunwind special reg accessor, otherwise fallback to
682 standard logic. */
683 if (!libunwind_is_initialized ()
684 || libunwind_get_reg_special (gdbarch, regnum, buf) != 0)
88d82102 685#endif
004d836a 686 {
c5a27d9c
JJ		 687 /* The fallback position is to assume that r32-r127 are found sequentially
688 in memory starting at $bof. This isn't always true, but without libunwind,
689 this is the best we can do. */
690 ULONGEST cfm;
691 ULONGEST bsp;
692 CORE_ADDR reg;
693 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
694 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
695
696 /* The bsp points at the end of the register frame so we
697 subtract the size of frame from it to get start of register frame. */
698 bsp = rse_address_add (bsp, -(cfm & 0x7f));
699
700 if ((cfm & 0x7f) > regnum - V32_REGNUM)
701 {
702 ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
703 reg = read_memory_integer ((CORE_ADDR)reg_addr, 8);
704 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), reg);
705 }
706 else
707 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), 0);
004d836a 708 }
004d836a
JJ		 709 }
710 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
711 {
712 ULONGEST unatN_val;
713 ULONGEST unat;
714 regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat);
715 unatN_val = (unat & (1LL << (regnum - IA64_NAT0_REGNUM))) != 0;
aa2a9a3c 716 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), unatN_val);
004d836a
JJ		 717 }
718 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
719 {
720 ULONGEST natN_val = 0;
721 ULONGEST bsp;
722 ULONGEST cfm;
723 CORE_ADDR gr_addr = 0;
724 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
725 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
726
727 /* The bsp points at the end of the register frame so we
728 subtract the size of frame from it to get start of register frame. */
729 bsp = rse_address_add (bsp, -(cfm & 0x7f));
730
731 if ((cfm & 0x7f) > regnum - V32_REGNUM)
732 gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
733
734 if (gr_addr != 0)
735 {
736 /* Compute address of nat collection bits. */
737 CORE_ADDR nat_addr = gr_addr | 0x1f8;
738 CORE_ADDR nat_collection;
739 int nat_bit;
740 /* If our nat collection address is bigger than bsp, we have to get
741 the nat collection from rnat. Otherwise, we fetch the nat
742 collection from the computed address. */
743 if (nat_addr >= bsp)
744 regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM, &nat_collection);
745 else
746 nat_collection = read_memory_integer (nat_addr, 8);
747 nat_bit = (gr_addr >> 3) & 0x3f;
748 natN_val = (nat_collection >> nat_bit) & 1;
749 }
750
aa2a9a3c 751 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), natN_val);
244bc108 752 }
004d836a
JJ		 753 else if (regnum == VBOF_REGNUM)
754 {
755 /* A virtual register frame start is provided for user convenience.
756 It can be calculated as the bsp - sof (sizeof frame). */
757 ULONGEST bsp, vbsp;
758 ULONGEST cfm;
759 CORE_ADDR reg;
760 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
761 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
762
763 /* The bsp points at the end of the register frame so we
764 subtract the size of frame from it to get beginning of frame. */
765 vbsp = rse_address_add (bsp, -(cfm & 0x7f));
aa2a9a3c 766 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), vbsp);
004d836a
JJ		 767 }
768 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
769 {
770 ULONGEST pr;
771 ULONGEST cfm;
772 ULONGEST prN_val;
773 CORE_ADDR reg;
774 regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr);
775 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
776
777 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
778 {
779 /* Fetch predicate register rename base from current frame
780 marker for this frame. */
781 int rrb_pr = (cfm >> 32) & 0x3f;
782
783 /* Adjust the register number to account for register rotation. */
784 regnum = VP16_REGNUM
785 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
786 }
787 prN_val = (pr & (1LL << (regnum - VP0_REGNUM))) != 0;
aa2a9a3c 788 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), prN_val);
004d836a
JJ		 789 }
790 else
aa2a9a3c 791 memset (buf, 0, register_size (current_gdbarch, regnum));
16461d7d
KB		 792}
793
004d836a
JJ		 794static void
795ia64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
88d82102 796 int regnum, const gdb_byte *buf)
16461d7d 797{
004d836a 798 if (regnum >= V32_REGNUM && regnum <= V127_REGNUM)
244bc108 799 {
004d836a
JJ		 800 ULONGEST bsp;
801 ULONGEST cfm;
802 CORE_ADDR reg;
803 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
804 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
805
806 bsp = rse_address_add (bsp, -(cfm & 0x7f));
807
808 if ((cfm & 0x7f) > regnum - V32_REGNUM)
809 {
810 ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
811 write_memory (reg_addr, (void *)buf, 8);
812 }
813 }
814 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
815 {
816 ULONGEST unatN_val, unat, unatN_mask;
817 regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat);
aa2a9a3c 818 unatN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum));
004d836a
JJ		 819 unatN_mask = (1LL << (regnum - IA64_NAT0_REGNUM));
820 if (unatN_val == 0)
821 unat &= ~unatN_mask;
822 else if (unatN_val == 1)
823 unat |= unatN_mask;
824 regcache_cooked_write_unsigned (regcache, IA64_UNAT_REGNUM, unat);
825 }
826 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
827 {
828 ULONGEST natN_val;
829 ULONGEST bsp;
830 ULONGEST cfm;
831 CORE_ADDR gr_addr = 0;
832 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
833 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
834
835 /* The bsp points at the end of the register frame so we
836 subtract the size of frame from it to get start of register frame. */
837 bsp = rse_address_add (bsp, -(cfm & 0x7f));
838
839 if ((cfm & 0x7f) > regnum - V32_REGNUM)
840 gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
841
aa2a9a3c 842 natN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum));
004d836a
JJ		 843
844 if (gr_addr != 0 && (natN_val == 0 || natN_val == 1))
845 {
846 /* Compute address of nat collection bits. */
847 CORE_ADDR nat_addr = gr_addr | 0x1f8;
848 CORE_ADDR nat_collection;
849 int natN_bit = (gr_addr >> 3) & 0x3f;
850 ULONGEST natN_mask = (1LL << natN_bit);
851 /* If our nat collection address is bigger than bsp, we have to get
852 the nat collection from rnat. Otherwise, we fetch the nat
853 collection from the computed address. */
854 if (nat_addr >= bsp)
855 {
856 regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM, &nat_collection);
857 if (natN_val)
858 nat_collection |= natN_mask;
859 else
860 nat_collection &= ~natN_mask;
861 regcache_cooked_write_unsigned (regcache, IA64_RNAT_REGNUM, nat_collection);
862 }
863 else
864 {
865 char nat_buf[8];
866 nat_collection = read_memory_integer (nat_addr, 8);
867 if (natN_val)
868 nat_collection |= natN_mask;
869 else
870 nat_collection &= ~natN_mask;
aa2a9a3c 871 store_unsigned_integer (nat_buf, register_size (current_gdbarch, regnum), nat_collection);
004d836a
JJ		 872 write_memory (nat_addr, nat_buf, 8);
873 }
874 }
875 }
876 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
877 {
878 ULONGEST pr;
879 ULONGEST cfm;
880 ULONGEST prN_val;
881 ULONGEST prN_mask;
882
883 regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr);
884 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
885
886 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
887 {
888 /* Fetch predicate register rename base from current frame
889 marker for this frame. */
890 int rrb_pr = (cfm >> 32) & 0x3f;
891
892 /* Adjust the register number to account for register rotation. */
893 regnum = VP16_REGNUM
894 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
895 }
aa2a9a3c 896 prN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum));
004d836a
JJ		 897 prN_mask = (1LL << (regnum - VP0_REGNUM));
898 if (prN_val == 0)
899 pr &= ~prN_mask;
900 else if (prN_val == 1)
901 pr |= prN_mask;
902 regcache_cooked_write_unsigned (regcache, IA64_PR_REGNUM, pr);
244bc108 903 }
16461d7d
KB		 904}
905
004d836a
JJ		 906/* The ia64 needs to convert between various ieee floating-point formats
907 and the special ia64 floating point register format. */
908
909static int
910ia64_convert_register_p (int regno, struct type *type)
911{
912 return (regno >= IA64_FR0_REGNUM && regno <= IA64_FR127_REGNUM);
913}
914
915static void
916ia64_register_to_value (struct frame_info *frame, int regnum,
88d82102 917 struct type *valtype, gdb_byte *out)
004d836a
JJ		 918{
919 char in[MAX_REGISTER_SIZE];
920 frame_register_read (frame, regnum, in);
921 convert_typed_floating (in, builtin_type_ia64_ext, out, valtype);
922}
923
924static void
925ia64_value_to_register (struct frame_info *frame, int regnum,
88d82102 926 struct type *valtype, const gdb_byte *in)
004d836a
JJ		 927{
928 char out[MAX_REGISTER_SIZE];
929 convert_typed_floating (in, valtype, out, builtin_type_ia64_ext);
930 put_frame_register (frame, regnum, out);
931}
932
933
58ab00f9
KB		 934/* Limit the number of skipped non-prologue instructions since examining
935 of the prologue is expensive. */
5ea2bd7f 936static int max_skip_non_prologue_insns = 40;
58ab00f9
KB		 937
938/* Given PC representing the starting address of a function, and
939 LIM_PC which is the (sloppy) limit to which to scan when looking
940 for a prologue, attempt to further refine this limit by using
941 the line data in the symbol table. If successful, a better guess
942 on where the prologue ends is returned, otherwise the previous
943 value of lim_pc is returned. TRUST_LIMIT is a pointer to a flag
944 which will be set to indicate whether the returned limit may be
945 used with no further scanning in the event that the function is
946 frameless. */
947
634aa483
AC		 948/* FIXME: cagney/2004-02-14: This function and logic have largely been
949 superseded by skip_prologue_using_sal. */
950
58ab00f9
KB		 951static CORE_ADDR
952refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc, int *trust_limit)
953{
954 struct symtab_and_line prologue_sal;
955 CORE_ADDR start_pc = pc;
956
957 /* Start off not trusting the limit. */
958 *trust_limit = 0;
959
960 prologue_sal = find_pc_line (pc, 0);
961 if (prologue_sal.line != 0)
962 {
963 int i;
964 CORE_ADDR addr = prologue_sal.end;
965
966 /* Handle the case in which compiler's optimizer/scheduler
967 has moved instructions into the prologue. We scan ahead
968 in the function looking for address ranges whose corresponding
969 line number is less than or equal to the first one that we
970 found for the function. (It can be less than when the
971 scheduler puts a body instruction before the first prologue
972 instruction.) */
973 for (i = 2 * max_skip_non_prologue_insns;
974 i > 0 && (lim_pc == 0 || addr < lim_pc);
975 i--)
976 {
977 struct symtab_and_line sal;
978
979 sal = find_pc_line (addr, 0);
980 if (sal.line == 0)
981 break;
982 if (sal.line <= prologue_sal.line
983 && sal.symtab == prologue_sal.symtab)
984 {
985 prologue_sal = sal;
986 }
987 addr = sal.end;
988 }
989
990 if (lim_pc == 0 || prologue_sal.end < lim_pc)
991 {
992 lim_pc = prologue_sal.end;
993 if (start_pc == get_pc_function_start (lim_pc))
994 *trust_limit = 1;
995 }
996 }
997 return lim_pc;
998}
999
16461d7d
KB		 1000#define isScratch(_regnum_) ((_regnum_) == 2 || (_regnum_) == 3 \
1001 || (8 <= (_regnum_) && (_regnum_) <= 11) \
1002 || (14 <= (_regnum_) && (_regnum_) <= 31))
1003#define imm9(_instr_) \
1004 ( ((((_instr_) & 0x01000000000LL) ? -1 : 0) << 8) \
1005 | (((_instr_) & 0x00008000000LL) >> 20) \
1006 | (((_instr_) & 0x00000001fc0LL) >> 6))
1007
004d836a
JJ		 1008/* Allocate and initialize a frame cache. */
1009
1010static struct ia64_frame_cache *
1011ia64_alloc_frame_cache (void)
1012{
1013 struct ia64_frame_cache *cache;
1014 int i;
1015
1016 cache = FRAME_OBSTACK_ZALLOC (struct ia64_frame_cache);
1017
1018 /* Base address. */
1019 cache->base = 0;
1020 cache->pc = 0;
1021 cache->cfm = 0;
4afcc598 1022 cache->prev_cfm = 0;
004d836a
JJ		 1023 cache->sof = 0;
1024 cache->sol = 0;
1025 cache->sor = 0;
1026 cache->bsp = 0;
1027 cache->fp_reg = 0;
1028 cache->frameless = 1;
1029
1030 for (i = 0; i < NUM_IA64_RAW_REGS; i++)
1031 cache->saved_regs[i] = 0;
1032
1033 return cache;
1034}
1035
16461d7d 1036static CORE_ADDR
004d836a 1037examine_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct frame_info *next_frame, struct ia64_frame_cache *cache)
16461d7d
KB		 1038{
1039 CORE_ADDR next_pc;
1040 CORE_ADDR last_prologue_pc = pc;
16461d7d
KB		 1041 instruction_type it;
1042 long long instr;
16461d7d
KB		 1043 int cfm_reg = 0;
1044 int ret_reg = 0;
1045 int fp_reg = 0;
1046 int unat_save_reg = 0;
1047 int pr_save_reg = 0;
1048 int mem_stack_frame_size = 0;
1049 int spill_reg = 0;
1050 CORE_ADDR spill_addr = 0;
0927a22b
KB		 1051 char instores[8];
1052 char infpstores[8];
5ea2bd7f 1053 char reg_contents[256];
58ab00f9 1054 int trust_limit;
004d836a
JJ		 1055 int frameless = 1;
1056 int i;
1057 CORE_ADDR addr;
1058 char buf[8];
1059 CORE_ADDR bof, sor, sol, sof, cfm, rrb_gr;
0927a22b
KB		 1060
1061 memset (instores, 0, sizeof instores);
1062 memset (infpstores, 0, sizeof infpstores);
5ea2bd7f 1063 memset (reg_contents, 0, sizeof reg_contents);
16461d7d 1064
004d836a
JJ		 1065 if (cache->after_prologue != 0
1066 && cache->after_prologue <= lim_pc)
1067 return cache->after_prologue;
16461d7d 1068
58ab00f9 1069 lim_pc = refine_prologue_limit (pc, lim_pc, &trust_limit);
16461d7d 1070 next_pc = fetch_instruction (pc, &it, &instr);
5ea2bd7f
JJ		 1071
1072 /* We want to check if we have a recognizable function start before we
1073 look ahead for a prologue. */
16461d7d
KB		 1074 if (pc < lim_pc && next_pc
1075 && it == M && ((instr & 0x1ee0000003fLL) == 0x02c00000000LL))
1076 {
5ea2bd7f 1077 /* alloc - start of a regular function. */
16461d7d
KB		 1078 int sor = (int) ((instr & 0x00078000000LL) >> 27);
1079 int sol = (int) ((instr & 0x00007f00000LL) >> 20);
1080 int sof = (int) ((instr & 0x000000fe000LL) >> 13);
16461d7d 1081 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
004d836a
JJ		 1082
1083 /* Verify that the current cfm matches what we think is the
1084 function start. If we have somehow jumped within a function,
1085 we do not want to interpret the prologue and calculate the
1086 addresses of various registers such as the return address.
1087 We will instead treat the frame as frameless. */
1088 if (!next_frame ||
1089 (sof == (cache->cfm & 0x7f) &&
1090 sol == ((cache->cfm >> 7) & 0x7f)))
1091 frameless = 0;
1092
16461d7d
KB		 1093 cfm_reg = rN;
1094 last_prologue_pc = next_pc;
1095 pc = next_pc;
1096 }
1097 else
58ab00f9 1098 {
5ea2bd7f
JJ		 1099 /* Look for a leaf routine. */
1100 if (pc < lim_pc && next_pc
1101 && (it == I || it == M)
1102 && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
1103 {
1104 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1105 int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
1106 | ((instr & 0x001f8000000LL) >> 20)
1107 | ((instr & 0x000000fe000LL) >> 13));
1108 int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1109 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1110 int qp = (int) (instr & 0x0000000003fLL);
1111 if (qp == 0 && rN == 2 && imm == 0 && rM == 12 && fp_reg == 0)
1112 {
1113 /* mov r2, r12 - beginning of leaf routine */
1114 fp_reg = rN;
5ea2bd7f
JJ		 1115 last_prologue_pc = next_pc;
1116 }
1117 }
1118
1119 /* If we don't recognize a regular function or leaf routine, we are
1120 done. */
1121 if (!fp_reg)
1122 {
1123 pc = lim_pc;
1124 if (trust_limit)
1125 last_prologue_pc = lim_pc;
1126 }
58ab00f9 1127 }
16461d7d
KB		 1128
1129 /* Loop, looking for prologue instructions, keeping track of
1130 where preserved registers were spilled. */
1131 while (pc < lim_pc)
1132 {
1133 next_pc = fetch_instruction (pc, &it, &instr);
1134 if (next_pc == 0)
1135 break;
1136
594706e6 1137 if (it == B && ((instr & 0x1e1f800003fLL) != 0x04000000000LL))
0927a22b 1138 {
102d615a
JJ		 1139 /* Exit loop upon hitting a non-nop branch instruction. */
1140 if (trust_limit)
1141 lim_pc = pc;
1142 break;
1143 }
1144 else if (((instr & 0x3fLL) != 0LL) &&
1145 (frameless || ret_reg != 0))
1146 {
1147 /* Exit loop upon hitting a predicated instruction if
1148 we already have the return register or if we are frameless. */
5ea2bd7f
JJ		 1149 if (trust_limit)
1150 lim_pc = pc;
0927a22b
KB		 1151 break;
1152 }
1153 else if (it == I && ((instr & 0x1eff8000000LL) == 0x00188000000LL))
16461d7d
KB		 1154 {
1155 /* Move from BR */
1156 int b2 = (int) ((instr & 0x0000000e000LL) >> 13);
1157 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1158 int qp = (int) (instr & 0x0000000003f);
1159
1160 if (qp == 0 && b2 == 0 && rN >= 32 && ret_reg == 0)
1161 {
1162 ret_reg = rN;
1163 last_prologue_pc = next_pc;
1164 }
1165 }
1166 else if ((it == I || it == M)
1167 && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
1168 {
1169 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1170 int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
1171 | ((instr & 0x001f8000000LL) >> 20)
1172 | ((instr & 0x000000fe000LL) >> 13));
1173 int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1174 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1175 int qp = (int) (instr & 0x0000000003fLL);
1176
1177 if (qp == 0 && rN >= 32 && imm == 0 && rM == 12 && fp_reg == 0)
1178 {
1179 /* mov rN, r12 */
1180 fp_reg = rN;
1181 last_prologue_pc = next_pc;
1182 }
1183 else if (qp == 0 && rN == 12 && rM == 12)
1184 {
1185 /* adds r12, -mem_stack_frame_size, r12 */
1186 mem_stack_frame_size -= imm;
1187 last_prologue_pc = next_pc;
1188 }
1189 else if (qp == 0 && rN == 2
1190 && ((rM == fp_reg && fp_reg != 0) || rM == 12))
1191 {
004d836a
JJ		 1192 char buf[MAX_REGISTER_SIZE];
1193 CORE_ADDR saved_sp = 0;
16461d7d
KB		 1194 /* adds r2, spilloffset, rFramePointer
1195 or
1196 adds r2, spilloffset, r12
1197
1198 Get ready for stf.spill or st8.spill instructions.
1199 The address to start spilling at is loaded into r2.
1200 FIXME: Why r2? That's what gcc currently uses; it
1201 could well be different for other compilers. */
1202
1203 /* Hmm... whether or not this will work will depend on
1204 where the pc is. If it's still early in the prologue
1205 this'll be wrong. FIXME */
004d836a
JJ		 1206 if (next_frame)
1207 {
1208 frame_unwind_register (next_frame, sp_regnum, buf);
1209 saved_sp = extract_unsigned_integer (buf, 8);
1210 }
1211 spill_addr = saved_sp
16461d7d
KB		 1212 + (rM == 12 ? 0 : mem_stack_frame_size)
1213 + imm;
1214 spill_reg = rN;
1215 last_prologue_pc = next_pc;
1216 }
5ea2bd7f
JJ		 1217 else if (qp == 0 && rM >= 32 && rM < 40 && !instores[rM] &&
1218 rN < 256 && imm == 0)
1219 {
1220 /* mov rN, rM where rM is an input register */
1221 reg_contents[rN] = rM;
1222 last_prologue_pc = next_pc;
1223 }
1224 else if (frameless && qp == 0 && rN == fp_reg && imm == 0 &&
1225 rM == 2)
1226 {
1227 /* mov r12, r2 */
1228 last_prologue_pc = next_pc;
1229 break;
1230 }
16461d7d
KB		 1231 }
1232 else if (it == M
1233 && ( ((instr & 0x1efc0000000LL) == 0x0eec0000000LL)
1234 || ((instr & 0x1ffc8000000LL) == 0x0cec0000000LL) ))
1235 {
1236 /* stf.spill [rN] = fM, imm9
1237 or
1238 stf.spill [rN] = fM */
1239
1240 int imm = imm9(instr);
1241 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1242 int fM = (int) ((instr & 0x000000fe000LL) >> 13);
1243 int qp = (int) (instr & 0x0000000003fLL);
1244 if (qp == 0 && rN == spill_reg && spill_addr != 0
1245 && ((2 <= fM && fM <= 5) || (16 <= fM && fM <= 31)))
1246 {
004d836a 1247 cache->saved_regs[IA64_FR0_REGNUM + fM] = spill_addr;
16461d7d 1248
594706e6 1249 if ((instr & 0x1efc0000000LL) == 0x0eec0000000LL)
16461d7d
KB		 1250 spill_addr += imm;
1251 else
1252 spill_addr = 0; /* last one; must be done */
1253 last_prologue_pc = next_pc;
1254 }
1255 }
1256 else if ((it == M && ((instr & 0x1eff8000000LL) == 0x02110000000LL))
1257 || (it == I && ((instr & 0x1eff8000000LL) == 0x00050000000LL)) )
1258 {
1259 /* mov.m rN = arM
1260 or
1261 mov.i rN = arM */
1262
1263 int arM = (int) ((instr & 0x00007f00000LL) >> 20);
1264 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1265 int qp = (int) (instr & 0x0000000003fLL);
1266 if (qp == 0 && isScratch (rN) && arM == 36 /* ar.unat */)
1267 {
1268 /* We have something like "mov.m r3 = ar.unat". Remember the
1269 r3 (or whatever) and watch for a store of this register... */
1270 unat_save_reg = rN;
1271 last_prologue_pc = next_pc;
1272 }
1273 }
1274 else if (it == I && ((instr & 0x1eff8000000LL) == 0x00198000000LL))
1275 {
1276 /* mov rN = pr */
1277 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1278 int qp = (int) (instr & 0x0000000003fLL);
1279 if (qp == 0 && isScratch (rN))
1280 {
1281 pr_save_reg = rN;
1282 last_prologue_pc = next_pc;
1283 }
1284 }
1285 else if (it == M
1286 && ( ((instr & 0x1ffc8000000LL) == 0x08cc0000000LL)
1287 || ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)))
1288 {
1289 /* st8 [rN] = rM
1290 or
1291 st8 [rN] = rM, imm9 */
1292 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1293 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1294 int qp = (int) (instr & 0x0000000003fLL);
5ea2bd7f 1295 int indirect = rM < 256 ? reg_contents[rM] : 0;
16461d7d
KB		 1296 if (qp == 0 && rN == spill_reg && spill_addr != 0
1297 && (rM == unat_save_reg || rM == pr_save_reg))
1298 {
1299 /* We've found a spill of either the UNAT register or the PR
1300 register. (Well, not exactly; what we've actually found is
1301 a spill of the register that UNAT or PR was moved to).
1302 Record that fact and move on... */
1303 if (rM == unat_save_reg)
1304 {
1305 /* Track UNAT register */
004d836a 1306 cache->saved_regs[IA64_UNAT_REGNUM] = spill_addr;
16461d7d
KB		 1307 unat_save_reg = 0;
1308 }
1309 else
1310 {
1311 /* Track PR register */
004d836a 1312 cache->saved_regs[IA64_PR_REGNUM] = spill_addr;
16461d7d
KB		 1313 pr_save_reg = 0;
1314 }
1315 if ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)
1316 /* st8 [rN] = rM, imm9 */
1317 spill_addr += imm9(instr);
1318 else
1319 spill_addr = 0; /* must be done spilling */
1320 last_prologue_pc = next_pc;
1321 }
0927a22b
KB		 1322 else if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1323 {
1324 /* Allow up to one store of each input register. */
1325 instores[rM-32] = 1;
1326 last_prologue_pc = next_pc;
1327 }
5ea2bd7f
JJ		 1328 else if (qp == 0 && 32 <= indirect && indirect < 40 &&
1329 !instores[indirect-32])
1330 {
1331 /* Allow an indirect store of an input register. */
1332 instores[indirect-32] = 1;
1333 last_prologue_pc = next_pc;
1334 }
0927a22b
KB		 1335 }
1336 else if (it == M && ((instr & 0x1ff08000000LL) == 0x08c00000000LL))
1337 {
1338 /* One of
1339 st1 [rN] = rM
1340 st2 [rN] = rM
1341 st4 [rN] = rM
1342 st8 [rN] = rM
1343 Note that the st8 case is handled in the clause above.
1344
1345 Advance over stores of input registers. One store per input
1346 register is permitted. */
1347 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1348 int qp = (int) (instr & 0x0000000003fLL);
5ea2bd7f 1349 int indirect = rM < 256 ? reg_contents[rM] : 0;
0927a22b
KB		 1350 if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1351 {
1352 instores[rM-32] = 1;
1353 last_prologue_pc = next_pc;
1354 }
5ea2bd7f
JJ		 1355 else if (qp == 0 && 32 <= indirect && indirect < 40 &&
1356 !instores[indirect-32])
1357 {
1358 /* Allow an indirect store of an input register. */
1359 instores[indirect-32] = 1;
1360 last_prologue_pc = next_pc;
1361 }
0927a22b
KB		 1362 }
1363 else if (it == M && ((instr & 0x1ff88000000LL) == 0x0cc80000000LL))
1364 {
1365 /* Either
1366 stfs [rN] = fM
1367 or
1368 stfd [rN] = fM
1369
1370 Advance over stores of floating point input registers. Again
1371 one store per register is permitted */
1372 int fM = (int) ((instr & 0x000000fe000LL) >> 13);
1373 int qp = (int) (instr & 0x0000000003fLL);
1374 if (qp == 0 && 8 <= fM && fM < 16 && !infpstores[fM - 8])
1375 {
1376 infpstores[fM-8] = 1;
1377 last_prologue_pc = next_pc;
1378 }
16461d7d
KB		 1379 }
1380 else if (it == M
1381 && ( ((instr & 0x1ffc8000000LL) == 0x08ec0000000LL)
1382 || ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)))
1383 {
1384 /* st8.spill [rN] = rM
1385 or
1386 st8.spill [rN] = rM, imm9 */
1387 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1388 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1389 int qp = (int) (instr & 0x0000000003fLL);
1390 if (qp == 0 && rN == spill_reg && 4 <= rM && rM <= 7)
1391 {
1392 /* We've found a spill of one of the preserved general purpose
1393 regs. Record the spill address and advance the spill
1394 register if appropriate. */
004d836a 1395 cache->saved_regs[IA64_GR0_REGNUM + rM] = spill_addr;
16461d7d
KB		 1396 if ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)
1397 /* st8.spill [rN] = rM, imm9 */
1398 spill_addr += imm9(instr);
1399 else
1400 spill_addr = 0; /* Done spilling */
1401 last_prologue_pc = next_pc;
1402 }
1403 }
16461d7d
KB		 1404
1405 pc = next_pc;
1406 }
1407
004d836a
JJ		 1408 /* If not frameless and we aren't called by skip_prologue, then we need to calculate
1409 registers for the previous frame which will be needed later. */
16461d7d 1410
004d836a 1411 if (!frameless && next_frame)
da50a4b7 1412 {
004d836a
JJ		 1413 /* Extract the size of the rotating portion of the stack
1414 frame and the register rename base from the current
1415 frame marker. */
1416 cfm = cache->cfm;
1417 sor = cache->sor;
1418 sof = cache->sof;
1419 sol = cache->sol;
1420 rrb_gr = (cfm >> 18) & 0x7f;
1421
1422 /* Find the bof (beginning of frame). */
1423 bof = rse_address_add (cache->bsp, -sof);
1424
1425 for (i = 0, addr = bof;
1426 i < sof;
1427 i++, addr += 8)
1428 {
1429 if (IS_NaT_COLLECTION_ADDR (addr))
1430 {
1431 addr += 8;
1432 }
1433 if (i+32 == cfm_reg)
1434 cache->saved_regs[IA64_CFM_REGNUM] = addr;
1435 if (i+32 == ret_reg)
1436 cache->saved_regs[IA64_VRAP_REGNUM] = addr;
1437 if (i+32 == fp_reg)
1438 cache->saved_regs[IA64_VFP_REGNUM] = addr;
1439 }
16461d7d 1440
004d836a
JJ		 1441 /* For the previous argument registers we require the previous bof.
1442 If we can't find the previous cfm, then we can do nothing. */
4afcc598 1443 cfm = 0;
004d836a
JJ		 1444 if (cache->saved_regs[IA64_CFM_REGNUM] != 0)
1445 {
1446 cfm = read_memory_integer (cache->saved_regs[IA64_CFM_REGNUM], 8);
4afcc598
JJ		 1447 }
1448 else if (cfm_reg != 0)
1449 {
1450 frame_unwind_register (next_frame, cfm_reg, buf);
1451 cfm = extract_unsigned_integer (buf, 8);
1452 }
1453 cache->prev_cfm = cfm;
1454
1455 if (cfm != 0)
1456 {
004d836a
JJ		 1457 sor = ((cfm >> 14) & 0xf) * 8;
1458 sof = (cfm & 0x7f);
1459 sol = (cfm >> 7) & 0x7f;
1460 rrb_gr = (cfm >> 18) & 0x7f;
1461
1462 /* The previous bof only requires subtraction of the sol (size of locals)
1463 due to the overlap between output and input of subsequent frames. */
1464 bof = rse_address_add (bof, -sol);
1465
1466 for (i = 0, addr = bof;
1467 i < sof;
1468 i++, addr += 8)
1469 {
1470 if (IS_NaT_COLLECTION_ADDR (addr))
1471 {
1472 addr += 8;
1473 }
1474 if (i < sor)
1475 cache->saved_regs[IA64_GR32_REGNUM + ((i + (sor - rrb_gr)) % sor)]
1476 = addr;
1477 else
1478 cache->saved_regs[IA64_GR32_REGNUM + i] = addr;
1479 }
1480
1481 }
1482 }
1483
5ea2bd7f
JJ		 1484 /* Try and trust the lim_pc value whenever possible. */
1485 if (trust_limit && lim_pc >= last_prologue_pc)
004d836a
JJ		 1486 last_prologue_pc = lim_pc;
1487
1488 cache->frameless = frameless;
1489 cache->after_prologue = last_prologue_pc;
1490 cache->mem_stack_frame_size = mem_stack_frame_size;
1491 cache->fp_reg = fp_reg;
5ea2bd7f 1492
16461d7d
KB		 1493 return last_prologue_pc;
1494}
1495
1496CORE_ADDR
1497ia64_skip_prologue (CORE_ADDR pc)
1498{
004d836a
JJ		 1499 struct ia64_frame_cache cache;
1500 cache.base = 0;
1501 cache.after_prologue = 0;
1502 cache.cfm = 0;
1503 cache.bsp = 0;
1504
1505 /* Call examine_prologue with - as third argument since we don't have a next frame pointer to send. */
1506 return examine_prologue (pc, pc+1024, 0, &cache);
16461d7d
KB		 1507}
1508
004d836a
JJ		 1509
1510/* Normal frames. */
1511
1512static struct ia64_frame_cache *
1513ia64_frame_cache (struct frame_info *next_frame, void **this_cache)
16461d7d 1514{
004d836a
JJ		 1515 struct ia64_frame_cache *cache;
1516 char buf[8];
1517 CORE_ADDR cfm, sof, sol, bsp, psr;
1518 int i;
16461d7d 1519
004d836a
JJ		 1520 if (*this_cache)
1521 return *this_cache;
16461d7d 1522
004d836a
JJ		 1523 cache = ia64_alloc_frame_cache ();
1524 *this_cache = cache;
16461d7d 1525
004d836a
JJ		 1526 frame_unwind_register (next_frame, sp_regnum, buf);
1527 cache->saved_sp = extract_unsigned_integer (buf, 8);
16461d7d 1528
004d836a
JJ		 1529 /* We always want the bsp to point to the end of frame.
1530 This way, we can always get the beginning of frame (bof)
1531 by subtracting frame size. */
1532 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1533 cache->bsp = extract_unsigned_integer (buf, 8);
1534
1535 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
1536 psr = extract_unsigned_integer (buf, 8);
1537
1538 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
1539 cfm = extract_unsigned_integer (buf, 8);
1540
1541 cache->sof = (cfm & 0x7f);
1542 cache->sol = (cfm >> 7) & 0x7f;
1543 cache->sor = ((cfm >> 14) & 0xf) * 8;
1544
1545 cache->cfm = cfm;
1546
1547 cache->pc = frame_func_unwind (next_frame);
1548
1549 if (cache->pc != 0)
1550 examine_prologue (cache->pc, frame_pc_unwind (next_frame), next_frame, cache);
1551
1552 cache->base = cache->saved_sp + cache->mem_stack_frame_size;
1553
1554 return cache;
16461d7d
KB		 1555}
1556
a78f21af 1557static void
004d836a
JJ		 1558ia64_frame_this_id (struct frame_info *next_frame, void **this_cache,
1559 struct frame_id *this_id)
16461d7d 1560{
004d836a
JJ		 1561 struct ia64_frame_cache *cache =
1562 ia64_frame_cache (next_frame, this_cache);
16461d7d 1563
c5a27d9c 1564 /* If outermost frame, mark with null frame id. */
004d836a 1565 if (cache->base == 0)
c5a27d9c
JJ		 1566 (*this_id) = null_frame_id;
1567 else
1568 (*this_id) = frame_id_build_special (cache->base, cache->pc, cache->bsp);
4afcc598
JJ		 1569 if (gdbarch_debug >= 1)
1570 fprintf_unfiltered (gdb_stdlog,
78ced177
JJ		 1571 "regular frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
1572 paddr_nz (this_id->code_addr),
1573 paddr_nz (this_id->stack_addr),
1574 paddr_nz (cache->bsp), next_frame);
004d836a 1575}
244bc108 1576
004d836a
JJ		 1577static void
1578ia64_frame_prev_register (struct frame_info *next_frame, void **this_cache,
1579 int regnum, int *optimizedp,
1580 enum lval_type *lvalp, CORE_ADDR *addrp,
88d82102 1581 int *realnump, gdb_byte *valuep)
004d836a
JJ		 1582{
1583 struct ia64_frame_cache *cache =
1584 ia64_frame_cache (next_frame, this_cache);
1585 char dummy_valp[MAX_REGISTER_SIZE];
1586 char buf[8];
1587
1588 gdb_assert (regnum >= 0);
244bc108 1589
004d836a 1590 if (!target_has_registers)
8a3fe4f8 1591 error (_("No registers."));
244bc108 1592
004d836a
JJ		 1593 *optimizedp = 0;
1594 *addrp = 0;
1595 *lvalp = not_lval;
1596 *realnump = -1;
244bc108 1597
004d836a
JJ		 1598 /* Rather than check each time if valuep is non-null, supply a dummy buffer
1599 when valuep is not supplied. */
1600 if (!valuep)
1601 valuep = dummy_valp;
1602
aa2a9a3c 1603 memset (valuep, 0, register_size (current_gdbarch, regnum));
004d836a
JJ		 1604
1605 if (regnum == SP_REGNUM)
16461d7d
KB		 1606 {
1607 /* Handle SP values for all frames but the topmost. */
aa2a9a3c 1608 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
004d836a 1609 cache->base);
16461d7d
KB		 1610 }
1611 else if (regnum == IA64_BSP_REGNUM)
1612 {
004d836a
JJ		 1613 char cfm_valuep[MAX_REGISTER_SIZE];
1614 int cfm_optim;
1615 int cfm_realnum;
1616 enum lval_type cfm_lval;
1617 CORE_ADDR cfm_addr;
1618 CORE_ADDR bsp, prev_cfm, prev_bsp;
1619
1620 /* We want to calculate the previous bsp as the end of the previous register stack frame.
1621 This corresponds to what the hardware bsp register will be if we pop the frame
1622 back which is why we might have been called. We know the beginning of the current
aa2a9a3c 1623 frame is cache->bsp - cache->sof. This value in the previous frame points to
004d836a
JJ		 1624 the start of the output registers. We can calculate the end of that frame by adding
1625 the size of output (sof (size of frame) - sol (size of locals)). */
1626 ia64_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
1627 &cfm_optim, &cfm_lval, &cfm_addr, &cfm_realnum, cfm_valuep);
1628 prev_cfm = extract_unsigned_integer (cfm_valuep, 8);
1629
1630 bsp = rse_address_add (cache->bsp, -(cache->sof));
1631 prev_bsp = rse_address_add (bsp, (prev_cfm & 0x7f) - ((prev_cfm >> 7) & 0x7f));
1632
aa2a9a3c 1633 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
004d836a
JJ		 1634 prev_bsp);
1635 }
1636 else if (regnum == IA64_CFM_REGNUM)
1637 {
4afcc598
JJ		 1638 CORE_ADDR addr = cache->saved_regs[IA64_CFM_REGNUM];
1639
1640 if (addr != 0)
004d836a 1641 {
4afcc598
JJ		 1642 *lvalp = lval_memory;
1643 *addrp = addr;
1644 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
004d836a 1645 }
4afcc598
JJ		 1646 else if (cache->prev_cfm)
1647 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), cache->prev_cfm);
1648 else if (cache->frameless)
004d836a 1649 {
4afcc598
JJ		 1650 CORE_ADDR cfm = 0;
1651 frame_unwind_register (next_frame, IA64_PFS_REGNUM, valuep);
004d836a 1652 }
16461d7d
KB		 1653 }
1654 else if (regnum == IA64_VFP_REGNUM)
1655 {
1656 /* If the function in question uses an automatic register (r32-r127)
1657 for the frame pointer, it'll be found by ia64_find_saved_register()
1658 above. If the function lacks one of these frame pointers, we can
004d836a
JJ		 1659 still provide a value since we know the size of the frame. */
1660 CORE_ADDR vfp = cache->base;
aa2a9a3c 1661 store_unsigned_integer (valuep, register_size (current_gdbarch, IA64_VFP_REGNUM), vfp);
16461d7d 1662 }
004d836a 1663 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
16461d7d 1664 {
004d836a 1665 char pr_valuep[MAX_REGISTER_SIZE];
16461d7d 1666 int pr_optim;
004d836a 1667 int pr_realnum;
16461d7d
KB		 1668 enum lval_type pr_lval;
1669 CORE_ADDR pr_addr;
004d836a
JJ		 1670 ULONGEST prN_val;
1671 ia64_frame_prev_register (next_frame, this_cache, IA64_PR_REGNUM,
1672 &pr_optim, &pr_lval, &pr_addr, &pr_realnum, pr_valuep);
1673 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
3a854e23
KB		 1674 {
1675 /* Fetch predicate register rename base from current frame
004d836a
JJ		 1676 marker for this frame. */
1677 int rrb_pr = (cache->cfm >> 32) & 0x3f;
3a854e23 1678
004d836a
JJ		 1679 /* Adjust the register number to account for register rotation. */
1680 regnum = VP16_REGNUM
1681 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
3a854e23 1682 }
004d836a
JJ		 1683 prN_val = extract_bit_field ((unsigned char *) pr_valuep,
1684 regnum - VP0_REGNUM, 1);
aa2a9a3c 1685 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), prN_val);
16461d7d
KB		 1686 }
1687 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
1688 {
004d836a 1689 char unat_valuep[MAX_REGISTER_SIZE];
16461d7d 1690 int unat_optim;
004d836a 1691 int unat_realnum;
16461d7d
KB		 1692 enum lval_type unat_lval;
1693 CORE_ADDR unat_addr;
004d836a
JJ		 1694 ULONGEST unatN_val;
1695 ia64_frame_prev_register (next_frame, this_cache, IA64_UNAT_REGNUM,
1696 &unat_optim, &unat_lval, &unat_addr, &unat_realnum, unat_valuep);
1697 unatN_val = extract_bit_field ((unsigned char *) unat_valuep,
16461d7d 1698 regnum - IA64_NAT0_REGNUM, 1);
aa2a9a3c 1699 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
16461d7d 1700 unatN_val);
16461d7d
KB		 1701 }
1702 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
1703 {
1704 int natval = 0;
1705 /* Find address of general register corresponding to nat bit we're
004d836a
JJ		 1706 interested in. */
1707 CORE_ADDR gr_addr;
244bc108 1708
004d836a
JJ		 1709 gr_addr = cache->saved_regs[regnum - IA64_NAT0_REGNUM
1710 + IA64_GR0_REGNUM];
1711 if (gr_addr != 0)
244bc108 1712 {
004d836a 1713 /* Compute address of nat collection bits. */
16461d7d 1714 CORE_ADDR nat_addr = gr_addr | 0x1f8;
004d836a 1715 CORE_ADDR bsp;
16461d7d
KB		 1716 CORE_ADDR nat_collection;
1717 int nat_bit;
1718 /* If our nat collection address is bigger than bsp, we have to get
1719 the nat collection from rnat. Otherwise, we fetch the nat
004d836a
JJ		 1720 collection from the computed address. */
1721 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1722 bsp = extract_unsigned_integer (buf, 8);
16461d7d 1723 if (nat_addr >= bsp)
004d836a
JJ		 1724 {
1725 frame_unwind_register (next_frame, IA64_RNAT_REGNUM, buf);
1726 nat_collection = extract_unsigned_integer (buf, 8);
1727 }
16461d7d
KB		 1728 else
1729 nat_collection = read_memory_integer (nat_addr, 8);
1730 nat_bit = (gr_addr >> 3) & 0x3f;
1731 natval = (nat_collection >> nat_bit) & 1;
1732 }
004d836a 1733
aa2a9a3c 1734 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), natval);
244bc108
KB		 1735 }
1736 else if (regnum == IA64_IP_REGNUM)
1737 {
004d836a 1738 CORE_ADDR pc = 0;
4afcc598 1739 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
004d836a 1740
4afcc598 1741 if (addr != 0)
004d836a 1742 {
4afcc598
JJ		 1743 *lvalp = lval_memory;
1744 *addrp = addr;
1745 read_memory (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM));
004d836a
JJ		 1746 pc = extract_unsigned_integer (buf, 8);
1747 }
4afcc598 1748 else if (cache->frameless)
004d836a 1749 {
4afcc598
JJ		 1750 frame_unwind_register (next_frame, IA64_BR0_REGNUM, buf);
1751 pc = extract_unsigned_integer (buf, 8);
244bc108 1752 }
004d836a
JJ		 1753 pc &= ~0xf;
1754 store_unsigned_integer (valuep, 8, pc);
244bc108 1755 }
004d836a 1756 else if (regnum == IA64_PSR_REGNUM)
244bc108 1757 {
4afcc598
JJ		 1758 /* We don't know how to get the complete previous PSR, but we need it for
1759 the slot information when we unwind the pc (pc is formed of IP register
1760 plus slot information from PSR). To get the previous slot information,
1761 we mask it off the return address. */
004d836a
JJ		 1762 ULONGEST slot_num = 0;
1763 CORE_ADDR pc= 0;
1764 CORE_ADDR psr = 0;
4afcc598 1765 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
004d836a
JJ		 1766
1767 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
1768 psr = extract_unsigned_integer (buf, 8);
1769
4afcc598 1770 if (addr != 0)
244bc108 1771 {
4afcc598
JJ		 1772 *lvalp = lval_memory;
1773 *addrp = addr;
1774 read_memory (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM));
004d836a 1775 pc = extract_unsigned_integer (buf, 8);
244bc108 1776 }
4afcc598 1777 else if (cache->frameless)
004d836a 1778 {
4afcc598
JJ		 1779 CORE_ADDR pc;
1780 frame_unwind_register (next_frame, IA64_BR0_REGNUM, buf);
1781 pc = extract_unsigned_integer (buf, 8);
004d836a
JJ		 1782 }
1783 psr &= ~(3LL << 41);
1784 slot_num = pc & 0x3LL;
1785 psr |= (CORE_ADDR)slot_num << 41;
1786 store_unsigned_integer (valuep, 8, psr);
1787 }
4afcc598
JJ		 1788 else if (regnum == IA64_BR0_REGNUM)
1789 {
1790 CORE_ADDR br0 = 0;
1791 CORE_ADDR addr = cache->saved_regs[IA64_BR0_REGNUM];
1792 if (addr != 0)
1793 {
1794 *lvalp = lval_memory;
1795 *addrp = addr;
1796 read_memory (addr, buf, register_size (current_gdbarch, IA64_BR0_REGNUM));
1797 br0 = extract_unsigned_integer (buf, 8);
1798 }
1799 store_unsigned_integer (valuep, 8, br0);
1800 }
004d836a
JJ		 1801 else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM) ||
1802 (regnum >= V32_REGNUM && regnum <= V127_REGNUM))
1803 {
1804 CORE_ADDR addr = 0;
1805 if (regnum >= V32_REGNUM)
1806 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
1807 addr = cache->saved_regs[regnum];
244bc108
KB		 1808 if (addr != 0)
1809 {
004d836a
JJ		 1810 *lvalp = lval_memory;
1811 *addrp = addr;
aa2a9a3c 1812 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
244bc108 1813 }
004d836a 1814 else if (cache->frameless)
244bc108 1815 {
004d836a
JJ		 1816 char r_valuep[MAX_REGISTER_SIZE];
1817 int r_optim;
1818 int r_realnum;
1819 enum lval_type r_lval;
1820 CORE_ADDR r_addr;
1821 CORE_ADDR prev_cfm, prev_bsp, prev_bof;
1822 CORE_ADDR addr = 0;
1823 if (regnum >= V32_REGNUM)
1824 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
1825 ia64_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
1826 &r_optim, &r_lval, &r_addr, &r_realnum, r_valuep);
1827 prev_cfm = extract_unsigned_integer (r_valuep, 8);
1828 ia64_frame_prev_register (next_frame, this_cache, IA64_BSP_REGNUM,
1829 &r_optim, &r_lval, &r_addr, &r_realnum, r_valuep);
1830 prev_bsp = extract_unsigned_integer (r_valuep, 8);
1831 prev_bof = rse_address_add (prev_bsp, -(prev_cfm & 0x7f));
1832
1833 addr = rse_address_add (prev_bof, (regnum - IA64_GR32_REGNUM));
1834 *lvalp = lval_memory;
1835 *addrp = addr;
aa2a9a3c 1836 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
244bc108 1837 }
16461d7d
KB		 1838 }
1839 else
1840 {
004d836a 1841 CORE_ADDR addr = 0;
3a854e23
KB		 1842 if (IA64_FR32_REGNUM <= regnum && regnum <= IA64_FR127_REGNUM)
1843 {
1844 /* Fetch floating point register rename base from current
004d836a
JJ		 1845 frame marker for this frame. */
1846 int rrb_fr = (cache->cfm >> 25) & 0x7f;
3a854e23
KB		 1847
1848 /* Adjust the floating point register number to account for
004d836a 1849 register rotation. */
3a854e23
KB		 1850 regnum = IA64_FR32_REGNUM
1851 + ((regnum - IA64_FR32_REGNUM) + rrb_fr) % 96;
1852 }
1853
004d836a
JJ		 1854 /* If we have stored a memory address, access the register. */
1855 addr = cache->saved_regs[regnum];
1856 if (addr != 0)
1857 {
1858 *lvalp = lval_memory;
1859 *addrp = addr;
aa2a9a3c 1860 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
004d836a
JJ		 1861 }
1862 /* Otherwise, punt and get the current value of the register. */
1863 else
1864 frame_unwind_register (next_frame, regnum, valuep);
16461d7d 1865 }
4afcc598
JJ		 1866
1867 if (gdbarch_debug >= 1)
1868 fprintf_unfiltered (gdb_stdlog,
78ced177 1869 "regular prev register <%d> <%s> is 0x%s\n", regnum,
4afcc598 1870 (((unsigned) regnum <= IA64_NAT127_REGNUM)
78ced177
JJ		 1871 ? ia64_register_names[regnum] : "r??"),
1872 paddr_nz (extract_unsigned_integer (valuep, 8)));
16461d7d 1873}
004d836a
JJ		 1874
1875static const struct frame_unwind ia64_frame_unwind =
1876{
1877 NORMAL_FRAME,
1878 &ia64_frame_this_id,
1879 &ia64_frame_prev_register
1880};
1881
1882static const struct frame_unwind *
1883ia64_frame_sniffer (struct frame_info *next_frame)
1884{
1885 return &ia64_frame_unwind;
1886}
1887
1888/* Signal trampolines. */
1889
1890static void
1891ia64_sigtramp_frame_init_saved_regs (struct ia64_frame_cache *cache)
1892{
1893 if (SIGCONTEXT_REGISTER_ADDRESS)
1894 {
1895 int regno;
1896
1897 cache->saved_regs[IA64_VRAP_REGNUM] =
1898 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_IP_REGNUM);
1899 cache->saved_regs[IA64_CFM_REGNUM] =
1900 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_CFM_REGNUM);
1901 cache->saved_regs[IA64_PSR_REGNUM] =
1902 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_PSR_REGNUM);
004d836a 1903 cache->saved_regs[IA64_BSP_REGNUM] =
4afcc598 1904 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_BSP_REGNUM);
004d836a
JJ		 1905 cache->saved_regs[IA64_RNAT_REGNUM] =
1906 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_RNAT_REGNUM);
1907 cache->saved_regs[IA64_CCV_REGNUM] =
1908 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_CCV_REGNUM);
1909 cache->saved_regs[IA64_UNAT_REGNUM] =
1910 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_UNAT_REGNUM);
1911 cache->saved_regs[IA64_FPSR_REGNUM] =
1912 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_FPSR_REGNUM);
1913 cache->saved_regs[IA64_PFS_REGNUM] =
1914 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_PFS_REGNUM);
1915 cache->saved_regs[IA64_LC_REGNUM] =
1916 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_LC_REGNUM);
1917 for (regno = IA64_GR1_REGNUM; regno <= IA64_GR31_REGNUM; regno++)
4afcc598
JJ		 1918 cache->saved_regs[regno] =
1919 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
004d836a
JJ		 1920 for (regno = IA64_BR0_REGNUM; regno <= IA64_BR7_REGNUM; regno++)
1921 cache->saved_regs[regno] =
1922 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
932644f0 1923 for (regno = IA64_FR2_REGNUM; regno <= IA64_FR31_REGNUM; regno++)
004d836a
JJ		 1924 cache->saved_regs[regno] =
1925 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
1926 }
1927}
1928
1929static struct ia64_frame_cache *
1930ia64_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache)
1931{
1932 struct ia64_frame_cache *cache;
1933 CORE_ADDR addr;
1934 char buf[8];
1935 int i;
1936
1937 if (*this_cache)
1938 return *this_cache;
1939
1940 cache = ia64_alloc_frame_cache ();
1941
1942 frame_unwind_register (next_frame, sp_regnum, buf);
4afcc598
JJ		 1943 /* Note that frame size is hard-coded below. We cannot calculate it
1944 via prologue examination. */
1945 cache->base = extract_unsigned_integer (buf, 8) + 16;
1946
1947 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1948 cache->bsp = extract_unsigned_integer (buf, 8);
1949
1950 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
1951 cache->cfm = extract_unsigned_integer (buf, 8);
1952 cache->sof = cache->cfm & 0x7f;
004d836a
JJ		 1953
1954 ia64_sigtramp_frame_init_saved_regs (cache);
1955
1956 *this_cache = cache;
1957 return cache;
1958}
1959
1960static void
1961ia64_sigtramp_frame_this_id (struct frame_info *next_frame,
1962 void **this_cache, struct frame_id *this_id)
1963{
1964 struct ia64_frame_cache *cache =
1965 ia64_sigtramp_frame_cache (next_frame, this_cache);
1966
4afcc598
JJ		 1967 (*this_id) = frame_id_build_special (cache->base, frame_pc_unwind (next_frame), cache->bsp);
1968 if (gdbarch_debug >= 1)
1969 fprintf_unfiltered (gdb_stdlog,
78ced177
JJ		 1970 "sigtramp frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
1971 paddr_nz (this_id->code_addr),
1972 paddr_nz (this_id->stack_addr),
1973 paddr_nz (cache->bsp), next_frame);
004d836a
JJ		 1974}
1975
1976static void
1977ia64_sigtramp_frame_prev_register (struct frame_info *next_frame,
1978 void **this_cache,
1979 int regnum, int *optimizedp,
1980 enum lval_type *lvalp, CORE_ADDR *addrp,
88d82102 1981 int *realnump, gdb_byte *valuep)
004d836a 1982{
4afcc598
JJ		 1983 char dummy_valp[MAX_REGISTER_SIZE];
1984 char buf[MAX_REGISTER_SIZE];
1985
1986 struct ia64_frame_cache *cache =
1987 ia64_sigtramp_frame_cache (next_frame, this_cache);
1988
1989 gdb_assert (regnum >= 0);
1990
1991 if (!target_has_registers)
8a3fe4f8 1992 error (_("No registers."));
4afcc598
JJ		 1993
1994 *optimizedp = 0;
1995 *addrp = 0;
1996 *lvalp = not_lval;
1997 *realnump = -1;
1998
1999 /* Rather than check each time if valuep is non-null, supply a dummy buffer
2000 when valuep is not supplied. */
2001 if (!valuep)
2002 valuep = dummy_valp;
2003
2004 memset (valuep, 0, register_size (current_gdbarch, regnum));
2005
2006 if (regnum == IA64_IP_REGNUM)
2007 {
2008 CORE_ADDR pc = 0;
2009 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
2010
2011 if (addr != 0)
2012 {
2013 *lvalp = lval_memory;
2014 *addrp = addr;
2015 read_memory (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM));
2016 pc = extract_unsigned_integer (buf, 8);
2017 }
2018 pc &= ~0xf;
2019 store_unsigned_integer (valuep, 8, pc);
2020 }
2021 else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM) ||
2022 (regnum >= V32_REGNUM && regnum <= V127_REGNUM))
2023 {
2024 CORE_ADDR addr = 0;
2025 if (regnum >= V32_REGNUM)
2026 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
2027 addr = cache->saved_regs[regnum];
2028 if (addr != 0)
2029 {
2030 *lvalp = lval_memory;
2031 *addrp = addr;
2032 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
2033 }
2034 }
2035 else
2036 {
2037 /* All other registers not listed above. */
2038 CORE_ADDR addr = cache->saved_regs[regnum];
2039 if (addr != 0)
2040 {
2041 *lvalp = lval_memory;
2042 *addrp = addr;
2043 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
2044 }
2045 }
004d836a 2046
4afcc598
JJ		 2047 if (gdbarch_debug >= 1)
2048 fprintf_unfiltered (gdb_stdlog,
78ced177 2049 "sigtramp prev register <%s> is 0x%s\n",
c5a27d9c
JJ		 2050 (regnum < IA64_GR32_REGNUM
2051 || (regnum > IA64_GR127_REGNUM
2052 && regnum < LAST_PSEUDO_REGNUM))
2053 ? ia64_register_names[regnum]
2054 : (regnum < LAST_PSEUDO_REGNUM
2055 ? ia64_register_names[regnum-IA64_GR32_REGNUM+V32_REGNUM]
2056 : "OUT_OF_RANGE"),
78ced177 2057 paddr_nz (extract_unsigned_integer (valuep, 8)));
004d836a
JJ		 2058}
2059
2060static const struct frame_unwind ia64_sigtramp_frame_unwind =
2061{
2062 SIGTRAMP_FRAME,
2063 ia64_sigtramp_frame_this_id,
2064 ia64_sigtramp_frame_prev_register
2065};
2066
2067static const struct frame_unwind *
2068ia64_sigtramp_frame_sniffer (struct frame_info *next_frame)
2069{
2070 char *name;
2071 CORE_ADDR pc = frame_pc_unwind (next_frame);
2072
2073 find_pc_partial_function (pc, &name, NULL, NULL);
0b281939 2074 if (legacy_pc_in_sigtramp (pc, name))
004d836a
JJ		 2075 return &ia64_sigtramp_frame_unwind;
2076
2077 return NULL;
2078}
2079\f
2080
2081static CORE_ADDR
2082ia64_frame_base_address (struct frame_info *next_frame, void **this_cache)
2083{
2084 struct ia64_frame_cache *cache =
2085 ia64_frame_cache (next_frame, this_cache);
2086
2087 return cache->base;
2088}
2089
2090static const struct frame_base ia64_frame_base =
2091{
2092 &ia64_frame_unwind,
2093 ia64_frame_base_address,
2094 ia64_frame_base_address,
2095 ia64_frame_base_address
2096};
16461d7d 2097
968d1cb4
JJ		 2098#ifdef HAVE_LIBUNWIND_IA64_H
2099
2100struct ia64_unwind_table_entry
2101 {
2102 unw_word_t start_offset;
2103 unw_word_t end_offset;
2104 unw_word_t info_offset;
2105 };
2106
2107static __inline__ uint64_t
2108ia64_rse_slot_num (uint64_t addr)
2109{
2110 return (addr >> 3) & 0x3f;
2111}
2112
2113/* Skip over a designated number of registers in the backing
2114 store, remembering every 64th position is for NAT. */
2115static __inline__ uint64_t
2116ia64_rse_skip_regs (uint64_t addr, long num_regs)
2117{
2118 long delta = ia64_rse_slot_num(addr) + num_regs;
2119
2120 if (num_regs < 0)
2121 delta -= 0x3e;
2122 return addr + ((num_regs + delta/0x3f) << 3);
2123}
2124
2125/* Gdb libunwind-frame callback function to convert from an ia64 gdb register
2126 number to a libunwind register number. */
2127static int
2128ia64_gdb2uw_regnum (int regnum)
2129{
2130 if (regnum == sp_regnum)
2131 return UNW_IA64_SP;
2132 else if (regnum == IA64_BSP_REGNUM)
2133 return UNW_IA64_BSP;
2134 else if ((unsigned) (regnum - IA64_GR0_REGNUM) < 128)
2135 return UNW_IA64_GR + (regnum - IA64_GR0_REGNUM);
2136 else if ((unsigned) (regnum - V32_REGNUM) < 95)
2137 return UNW_IA64_GR + 32 + (regnum - V32_REGNUM);
2138 else if ((unsigned) (regnum - IA64_FR0_REGNUM) < 128)
2139 return UNW_IA64_FR + (regnum - IA64_FR0_REGNUM);
2140 else if ((unsigned) (regnum - IA64_PR0_REGNUM) < 64)
2141 return -1;
2142 else if ((unsigned) (regnum - IA64_BR0_REGNUM) < 8)
2143 return UNW_IA64_BR + (regnum - IA64_BR0_REGNUM);
2144 else if (regnum == IA64_PR_REGNUM)
2145 return UNW_IA64_PR;
2146 else if (regnum == IA64_IP_REGNUM)
2147 return UNW_REG_IP;
2148 else if (regnum == IA64_CFM_REGNUM)
2149 return UNW_IA64_CFM;
2150 else if ((unsigned) (regnum - IA64_AR0_REGNUM) < 128)
2151 return UNW_IA64_AR + (regnum - IA64_AR0_REGNUM);
2152 else if ((unsigned) (regnum - IA64_NAT0_REGNUM) < 128)
2153 return UNW_IA64_NAT + (regnum - IA64_NAT0_REGNUM);
2154 else
2155 return -1;
2156}
2157
2158/* Gdb libunwind-frame callback function to convert from a libunwind register
2159 number to a ia64 gdb register number. */
2160static int
2161ia64_uw2gdb_regnum (int uw_regnum)
2162{
2163 if (uw_regnum == UNW_IA64_SP)
2164 return sp_regnum;
2165 else if (uw_regnum == UNW_IA64_BSP)
2166 return IA64_BSP_REGNUM;
2167 else if ((unsigned) (uw_regnum - UNW_IA64_GR) < 32)
2168 return IA64_GR0_REGNUM + (uw_regnum - UNW_IA64_GR);
2169 else if ((unsigned) (uw_regnum - UNW_IA64_GR) < 128)
2170 return V32_REGNUM + (uw_regnum - (IA64_GR0_REGNUM + 32));
2171 else if ((unsigned) (uw_regnum - UNW_IA64_FR) < 128)
2172 return IA64_FR0_REGNUM + (uw_regnum - UNW_IA64_FR);
2173 else if ((unsigned) (uw_regnum - UNW_IA64_BR) < 8)
2174 return IA64_BR0_REGNUM + (uw_regnum - UNW_IA64_BR);
2175 else if (uw_regnum == UNW_IA64_PR)
2176 return IA64_PR_REGNUM;
2177 else if (uw_regnum == UNW_REG_IP)
2178 return IA64_IP_REGNUM;
2179 else if (uw_regnum == UNW_IA64_CFM)
2180 return IA64_CFM_REGNUM;
2181 else if ((unsigned) (uw_regnum - UNW_IA64_AR) < 128)
2182 return IA64_AR0_REGNUM + (uw_regnum - UNW_IA64_AR);
2183 else if ((unsigned) (uw_regnum - UNW_IA64_NAT) < 128)
2184 return IA64_NAT0_REGNUM + (uw_regnum - UNW_IA64_NAT);
2185 else
2186 return -1;
2187}
2188
2189/* Gdb libunwind-frame callback function to reveal if register is a float
2190 register or not. */
2191static int
2192ia64_is_fpreg (int uw_regnum)
2193{
2194 return unw_is_fpreg (uw_regnum);
2195}
2196
2197/* Libunwind callback accessor function for general registers. */
2198static int
2199ia64_access_reg (unw_addr_space_t as, unw_regnum_t uw_regnum, unw_word_t *val,
2200 int write, void *arg)
2201{
2202 int regnum = ia64_uw2gdb_regnum (uw_regnum);
2203 unw_word_t bsp, sof, sol, cfm, psr, ip;
2204 struct frame_info *next_frame = arg;
2205 long new_sof, old_sof;
2206 char buf[MAX_REGISTER_SIZE];
2207
2208 if (write)
2209 {
2210 if (regnum < 0)
2211 /* ignore writes to pseudo-registers such as UNW_IA64_PROC_STARTI. */
2212 return 0;
2213
2214 switch (uw_regnum)
2215 {
2216 case UNW_REG_IP:
2217 ia64_write_pc (*val, inferior_ptid);
2218 break;
2219
2220 case UNW_IA64_AR_BSPSTORE:
2221 write_register (IA64_BSP_REGNUM, *val);
2222 break;
2223
2224 case UNW_IA64_AR_BSP:
2225 case UNW_IA64_BSP:
2226 /* Account for the fact that ptrace() expects bsp to point
2227 after the current register frame. */
2228 cfm = read_register (IA64_CFM_REGNUM);
2229 sof = (cfm & 0x7f);
2230 bsp = ia64_rse_skip_regs (*val, sof);
2231 write_register (IA64_BSP_REGNUM, bsp);
2232 break;
2233
2234 case UNW_IA64_CFM:
2235 /* If we change CFM, we need to adjust ptrace's notion of
2236 bsp accordingly, so that the real bsp remains
2237 unchanged. */
2238 bsp = read_register (IA64_BSP_REGNUM);
2239 cfm = read_register (IA64_CFM_REGNUM);
2240 old_sof = (cfm & 0x7f);
2241 new_sof = (*val & 0x7f);
2242 if (old_sof != new_sof)
2243 {
2244 bsp = ia64_rse_skip_regs (bsp, -old_sof + new_sof);
2245 write_register (IA64_BSP_REGNUM, bsp);
2246 }
2247 write_register (IA64_CFM_REGNUM, *val);
2248 break;
2249
2250 default:
2251 write_register (regnum, *val);
2252 break;
2253 }
2254 if (gdbarch_debug >= 1)
2255 fprintf_unfiltered (gdb_stdlog,
78ced177 2256 " access_reg: to cache: %4s=0x%s\n",
968d1cb4 2257 (((unsigned) regnum <= IA64_NAT127_REGNUM)
78ced177
JJ		 2258 ? ia64_register_names[regnum] : "r??"),
2259 paddr_nz (*val));
968d1cb4
JJ		 2260 }
2261 else
2262 {
2263 switch (uw_regnum)
2264 {
2265 case UNW_REG_IP:
2266 /* Libunwind expects to see the pc value which means the slot number
2267 from the psr must be merged with the ip word address. */
2268 frame_unwind_register (next_frame, IA64_IP_REGNUM, buf);
2269 ip = extract_unsigned_integer (buf, 8);
2270 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
2271 psr = extract_unsigned_integer (buf, 8);
2272 *val = ip | ((psr >> 41) & 0x3);
2273 break;
2274
2275 case UNW_IA64_AR_BSP:
2276 /* Libunwind expects to see the beginning of the current register
2277 frame so we must account for the fact that ptrace() will return a value
2278 for bsp that points *after* the current register frame. */
2279 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2280 bsp = extract_unsigned_integer (buf, 8);
2281 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
2282 cfm = extract_unsigned_integer (buf, 8);
2283 sof = (cfm & 0x7f);
2284 *val = ia64_rse_skip_regs (bsp, -sof);
2285 break;
2286
2287 case UNW_IA64_AR_BSPSTORE:
2288 /* Libunwind wants bspstore to be after the current register frame.
2289 This is what ptrace() and gdb treats as the regular bsp value. */
2290 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2291 *val = extract_unsigned_integer (buf, 8);
2292 break;
2293
2294 default:
2295 /* For all other registers, just unwind the value directly. */
2296 frame_unwind_register (next_frame, regnum, buf);
2297 *val = extract_unsigned_integer (buf, 8);
2298 break;
2299 }
2300
2301 if (gdbarch_debug >= 1)
2302 fprintf_unfiltered (gdb_stdlog,
78ced177 2303 " access_reg: from cache: %4s=0x%s\n",
968d1cb4 2304 (((unsigned) regnum <= IA64_NAT127_REGNUM)
78ced177
JJ		 2305 ? ia64_register_names[regnum] : "r??"),
2306 paddr_nz (*val));
968d1cb4
JJ		 2307 }
2308 return 0;
2309}
2310
2311/* Libunwind callback accessor function for floating-point registers. */
2312static int
2313ia64_access_fpreg (unw_addr_space_t as, unw_regnum_t uw_regnum, unw_fpreg_t *val,
2314 int write, void *arg)
2315{
2316 int regnum = ia64_uw2gdb_regnum (uw_regnum);
2317
2318 if (write)
2319 regcache_cooked_write (current_regcache, regnum, (char *) val);
2320 else
2321 regcache_cooked_read (current_regcache, regnum, (char *) val);
2322 return 0;
2323}
2324
c5a27d9c
JJ		 2325/* Libunwind callback accessor function for top-level rse registers. */
2326static int
2327ia64_access_rse_reg (unw_addr_space_t as, unw_regnum_t uw_regnum, unw_word_t *val,
2328 int write, void *arg)
2329{
2330 int regnum = ia64_uw2gdb_regnum (uw_regnum);
2331 unw_word_t bsp, sof, sol, cfm, psr, ip;
2332 long new_sof, old_sof;
2333
2334 if (write)
2335 {
2336 if (regnum < 0)
2337 /* ignore writes to pseudo-registers such as UNW_IA64_PROC_STARTI. */
2338 return 0;
2339
2340 switch (uw_regnum)
2341 {
2342 case UNW_REG_IP:
2343 ia64_write_pc (*val, inferior_ptid);
2344 break;
2345
2346 case UNW_IA64_AR_BSPSTORE:
2347 write_register (IA64_BSP_REGNUM, *val);
2348 break;
2349
2350 case UNW_IA64_AR_BSP:
2351 case UNW_IA64_BSP:
2352 /* Account for the fact that ptrace() expects bsp to point
2353 after the current register frame. */
2354 cfm = read_register (IA64_CFM_REGNUM);
2355 sof = (cfm & 0x7f);
2356 bsp = ia64_rse_skip_regs (*val, sof);
2357 write_register (IA64_BSP_REGNUM, bsp);
2358 break;
2359
2360 case UNW_IA64_CFM:
2361 /* If we change CFM, we need to adjust ptrace's notion of
2362 bsp accordingly, so that the real bsp remains
2363 unchanged. */
2364 bsp = read_register (IA64_BSP_REGNUM);
2365 cfm = read_register (IA64_CFM_REGNUM);
2366 old_sof = (cfm & 0x7f);
2367 new_sof = (*val & 0x7f);
2368 if (old_sof != new_sof)
2369 {
2370 bsp = ia64_rse_skip_regs (bsp, -old_sof + new_sof);
2371 write_register (IA64_BSP_REGNUM, bsp);
2372 }
2373 write_register (IA64_CFM_REGNUM, *val);
2374 break;
2375
2376 default:
2377 write_register (regnum, *val);
2378 break;
2379 }
2380 if (gdbarch_debug >= 1)
2381 fprintf_unfiltered (gdb_stdlog,
2382 " access_rse_reg: to cache: %4s=0x%s\n",
2383 (((unsigned) regnum <= IA64_NAT127_REGNUM)
2384 ? ia64_register_names[regnum] : "r??"),
2385 paddr_nz (*val));
2386 }
2387 else
2388 {
2389 switch (uw_regnum)
2390 {
2391 case UNW_REG_IP:
2392 /* Libunwind expects to see the pc value which means the slot number
2393 from the psr must be merged with the ip word address. */
2394 ip = read_register (IA64_IP_REGNUM);
2395 psr = read_register (IA64_PSR_REGNUM);
2396 *val = ip | ((psr >> 41) & 0x3);
2397 break;
2398
2399 case UNW_IA64_AR_BSP:
2400 /* Libunwind expects to see the beginning of the current register
2401 frame so we must account for the fact that ptrace() will return a value
2402 for bsp that points *after* the current register frame. */
2403 bsp = read_register (IA64_BSP_REGNUM);
2404 cfm = read_register (IA64_CFM_REGNUM);
2405 sof = (cfm & 0x7f);
2406 *val = ia64_rse_skip_regs (bsp, -sof);
2407 break;
2408
2409 case UNW_IA64_AR_BSPSTORE:
2410 /* Libunwind wants bspstore to be after the current register frame.
2411 This is what ptrace() and gdb treats as the regular bsp value. */
2412 *val = read_register (IA64_BSP_REGNUM);
2413 break;
2414
2415 default:
2416 /* For all other registers, just read the value directly. */
2417 *val = read_register (regnum);
2418 break;
2419 }
2420 }
2421
2422 if (gdbarch_debug >= 1)
2423 fprintf_unfiltered (gdb_stdlog,
2424 " access_rse_reg: from cache: %4s=0x%s\n",
2425 (((unsigned) regnum <= IA64_NAT127_REGNUM)
2426 ? ia64_register_names[regnum] : "r??"),
2427 paddr_nz (*val));
2428
2429 return 0;
2430}
2431
968d1cb4
JJ		 2432/* Libunwind callback accessor function for accessing memory. */
2433static int
2434ia64_access_mem (unw_addr_space_t as,
2435 unw_word_t addr, unw_word_t *val,
2436 int write, void *arg)
2437{
c5a27d9c
JJ		 2438 if (addr - KERNEL_START < ktab_size)
2439 {
2440 unw_word_t *laddr = (unw_word_t*) ((char *) ktab
2441 + (addr - KERNEL_START));
2442
2443 if (write)
2444 *laddr = *val;
2445 else
2446 *val = *laddr;
2447 return 0;
2448 }
2449
968d1cb4
JJ		 2450 /* XXX do we need to normalize byte-order here? */
2451 if (write)
2452 return target_write_memory (addr, (char *) val, sizeof (unw_word_t));
2453 else
2454 return target_read_memory (addr, (char *) val, sizeof (unw_word_t));
2455}
2456
2457/* Call low-level function to access the kernel unwind table. */
2458static int
2459getunwind_table (void *buf, size_t len)
2460{
2461 LONGEST x;
c5a27d9c
JJ		 2462
2463 /* FIXME: This is a temporary solution to backtracing syscalls in corefiles.
2464 To do this properly, the AUXV section should be used. This
2465 fix will work as long as the kernel used to generate the corefile
2466 is equivalent to the kernel used to debug the corefile. */
2467 x = ia64_linux_xfer_unwind_table (&current_target,
2468 TARGET_OBJECT_UNWIND_TABLE, NULL,
2469 buf, NULL, 0, len);
968d1cb4
JJ		 2470
2471 return (int)x;
2472}
2473
2474/* Get the kernel unwind table. */
2475static int
2476get_kernel_table (unw_word_t ip, unw_dyn_info_t *di)
2477{
c5a27d9c 2478 static struct ia64_table_entry *etab;
968d1cb4 2479
c5a27d9c 2480 if (!ktab)
968d1cb4 2481 {
c5a27d9c 2482 size_t size;
968d1cb4
JJ		 2483 size = getunwind_table (NULL, 0);
2484 if ((int)size < 0)
c5a27d9c
JJ		 2485 return -UNW_ENOINFO;
2486 ktab_size = size;
2487 ktab = xmalloc (ktab_size);
2488 getunwind_table (ktab, ktab_size);
2489
968d1cb4 2490 for (etab = ktab; etab->start_offset; ++etab)
c5a27d9c 2491 etab->info_offset += KERNEL_START;
968d1cb4
JJ		 2492 }
2493
2494 if (ip < ktab[0].start_offset || ip >= etab[-1].end_offset)
2495 return -UNW_ENOINFO;
2496
2497 di->format = UNW_INFO_FORMAT_TABLE;
2498 di->gp = 0;
2499 di->start_ip = ktab[0].start_offset;
2500 di->end_ip = etab[-1].end_offset;
2501 di->u.ti.name_ptr = (unw_word_t) "<kernel>";
2502 di->u.ti.segbase = 0;
2503 di->u.ti.table_len = ((char *) etab - (char *) ktab) / sizeof (unw_word_t);
2504 di->u.ti.table_data = (unw_word_t *) ktab;
2505
2506 if (gdbarch_debug >= 1)
2507 fprintf_unfiltered (gdb_stdlog, "get_kernel_table: found table `%s': "
78ced177
JJ		 2508 "segbase=0x%s, length=%s, gp=0x%s\n",
2509 (char *) di->u.ti.name_ptr,
2510 paddr_nz (di->u.ti.segbase),
2511 paddr_u (di->u.ti.table_len),
2512 paddr_nz (di->gp));
968d1cb4
JJ		 2513 return 0;
2514}
2515
2516/* Find the unwind table entry for a specified address. */
2517static int
2518ia64_find_unwind_table (struct objfile *objfile, unw_word_t ip,
2519 unw_dyn_info_t *dip, void **buf)
2520{
2521 Elf_Internal_Phdr *phdr, *p_text = NULL, *p_unwind = NULL;
2522 Elf_Internal_Ehdr *ehdr;
2523 unw_word_t segbase = 0;
2524 CORE_ADDR load_base;
2525 bfd *bfd;
2526 int i;
2527
2528 bfd = objfile->obfd;
2529
2530 ehdr = elf_tdata (bfd)->elf_header;
2531 phdr = elf_tdata (bfd)->phdr;
2532
2533 load_base = ANOFFSET (objfile->section_offsets, SECT_OFF_TEXT (objfile));
2534
2535 for (i = 0; i < ehdr->e_phnum; ++i)
2536 {
2537 switch (phdr[i].p_type)
2538 {
2539 case PT_LOAD:
2540 if ((unw_word_t) (ip - load_base - phdr[i].p_vaddr)
2541 < phdr[i].p_memsz)
2542 p_text = phdr + i;
2543 break;
2544
2545 case PT_IA_64_UNWIND:
2546 p_unwind = phdr + i;
2547 break;
2548
2549 default:
2550 break;
2551 }
2552 }
2553
c5a27d9c 2554 if (!p_text || !p_unwind)
968d1cb4
JJ		 2555 return -UNW_ENOINFO;
2556
c5a27d9c
JJ		 2557 /* Verify that the segment that contains the IP also contains
2558 the static unwind table. If not, we may be in the Linux kernel's
2559 DSO gate page in which case the unwind table is another segment.
2560 Otherwise, we are dealing with runtime-generated code, for which we
2561 have no info here. */
968d1cb4
JJ		 2562 segbase = p_text->p_vaddr + load_base;
2563
c5a27d9c
JJ		 2564 if ((p_unwind->p_vaddr - p_text->p_vaddr) >= p_text->p_memsz)
2565 {
2566 int ok = 0;
2567 for (i = 0; i < ehdr->e_phnum; ++i)
2568 {
2569 if (phdr[i].p_type == PT_LOAD
2570 && (p_unwind->p_vaddr - phdr[i].p_vaddr) < phdr[i].p_memsz)
2571 {
2572 ok = 1;
2573 /* Get the segbase from the section containing the
2574 libunwind table. */
2575 segbase = phdr[i].p_vaddr + load_base;
2576 }
2577 }
2578 if (!ok)
2579 return -UNW_ENOINFO;
2580 }
2581
2582 dip->start_ip = p_text->p_vaddr + load_base;
968d1cb4 2583 dip->end_ip = dip->start_ip + p_text->p_memsz;
b33e8514 2584 dip->gp = ia64_find_global_pointer (ip);
503ff15d
KB		 2585 dip->format = UNW_INFO_FORMAT_REMOTE_TABLE;
2586 dip->u.rti.name_ptr = (unw_word_t) bfd_get_filename (bfd);
2587 dip->u.rti.segbase = segbase;
2588 dip->u.rti.table_len = p_unwind->p_memsz / sizeof (unw_word_t);
2589 dip->u.rti.table_data = p_unwind->p_vaddr + load_base;
968d1cb4
JJ		 2590
2591 return 0;
2592}
2593
2594/* Libunwind callback accessor function to acquire procedure unwind-info. */
2595static int
2596ia64_find_proc_info_x (unw_addr_space_t as, unw_word_t ip, unw_proc_info_t *pi,
2597 int need_unwind_info, void *arg)
2598{
2599 struct obj_section *sec = find_pc_section (ip);
2600 unw_dyn_info_t di;
2601 int ret;
2602 void *buf = NULL;
2603
2604 if (!sec)
2605 {
2606 /* XXX This only works if the host and the target architecture are
2607 both ia64 and if the have (more or less) the same kernel
2608 version. */
2609 if (get_kernel_table (ip, &di) < 0)
2610 return -UNW_ENOINFO;
503ff15d
KB		 2611
2612 if (gdbarch_debug >= 1)
78ced177
JJ		 2613 fprintf_unfiltered (gdb_stdlog, "ia64_find_proc_info_x: 0x%s -> "
2614 "(name=`%s',segbase=0x%s,start=0x%s,end=0x%s,gp=0x%s,"
2615 "length=%s,data=0x%s)\n",
2616 paddr_nz (ip), (char *)di.u.ti.name_ptr,
2617 paddr_nz (di.u.ti.segbase),
2618 paddr_nz (di.start_ip), paddr_nz (di.end_ip),
2619 paddr_nz (di.gp),
2620 paddr_u (di.u.ti.table_len),
2621 paddr_nz ((CORE_ADDR)di.u.ti.table_data));
968d1cb4
JJ		 2622 }
2623 else
2624 {
2625 ret = ia64_find_unwind_table (sec->objfile, ip, &di, &buf);
2626 if (ret < 0)
2627 return ret;
968d1cb4 2628
503ff15d 2629 if (gdbarch_debug >= 1)
78ced177
JJ		 2630 fprintf_unfiltered (gdb_stdlog, "ia64_find_proc_info_x: 0x%s -> "
2631 "(name=`%s',segbase=0x%s,start=0x%s,end=0x%s,gp=0x%s,"
2632 "length=%s,data=0x%s)\n",
2633 paddr_nz (ip), (char *)di.u.rti.name_ptr,
2634 paddr_nz (di.u.rti.segbase),
2635 paddr_nz (di.start_ip), paddr_nz (di.end_ip),
2636 paddr_nz (di.gp),
2637 paddr_u (di.u.rti.table_len),
2638 paddr_nz (di.u.rti.table_data));
503ff15d 2639 }
968d1cb4 2640
503ff15d
KB		 2641 ret = libunwind_search_unwind_table (&as, ip, &di, pi, need_unwind_info,
2642 arg);
968d1cb4
JJ		 2643
2644 /* We no longer need the dyn info storage so free it. */
2645 xfree (buf);
2646
2647 return ret;
2648}
2649
2650/* Libunwind callback accessor function for cleanup. */
2651static void
2652ia64_put_unwind_info (unw_addr_space_t as,
2653 unw_proc_info_t *pip, void *arg)
2654{
2655 /* Nothing required for now. */
2656}
2657
2658/* Libunwind callback accessor function to get head of the dynamic
2659 unwind-info registration list. */
2660static int
2661ia64_get_dyn_info_list (unw_addr_space_t as,
2662 unw_word_t *dilap, void *arg)
2663{
2664 struct obj_section *text_sec;
2665 struct objfile *objfile;
2666 unw_word_t ip, addr;
2667 unw_dyn_info_t di;
2668 int ret;
2669
2670 if (!libunwind_is_initialized ())
2671 return -UNW_ENOINFO;
2672
2673 for (objfile = object_files; objfile; objfile = objfile->next)
2674 {
2675 void *buf = NULL;
2676
2677 text_sec = objfile->sections + SECT_OFF_TEXT (objfile);
2678 ip = text_sec->addr;
2679 ret = ia64_find_unwind_table (objfile, ip, &di, &buf);
2680 if (ret >= 0)
2681 {
503ff15d 2682 addr = libunwind_find_dyn_list (as, &di, arg);
968d1cb4
JJ		 2683 /* We no longer need the dyn info storage so free it. */
2684 xfree (buf);
2685
2686 if (addr)
2687 {
2688 if (gdbarch_debug >= 1)
2689 fprintf_unfiltered (gdb_stdlog,
2690 "dynamic unwind table in objfile %s "
78ced177 2691 "at 0x%s (gp=0x%s)\n",
968d1cb4 2692 bfd_get_filename (objfile->obfd),
78ced177 2693 paddr_nz (addr), paddr_nz (di.gp));
968d1cb4
JJ		 2694 *dilap = addr;
2695 return 0;
2696 }
2697 }
2698 }
2699 return -UNW_ENOINFO;
2700}
2701
2702
2703/* Frame interface functions for libunwind. */
2704
2705static void
2706ia64_libunwind_frame_this_id (struct frame_info *next_frame, void **this_cache,
7166c4a9 2707 struct frame_id *this_id)
968d1cb4
JJ		 2708{
2709 char buf[8];
2710 CORE_ADDR bsp;
2711 struct frame_id id;
c5a27d9c
JJ		 2712 CORE_ADDR prev_ip, addr;
2713 int realnum, optimized;
2714 enum lval_type lval;
2715
968d1cb4
JJ		 2716
2717 libunwind_frame_this_id (next_frame, this_cache, &id);
c5a27d9c
JJ		 2718 if (frame_id_eq (id, null_frame_id))
2719 {
2720 (*this_id) = null_frame_id;
2721 return;
2722 }
968d1cb4 2723
c5a27d9c
JJ		 2724 /* We must add the bsp as the special address for frame comparison
2725 purposes. */
968d1cb4
JJ		 2726 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2727 bsp = extract_unsigned_integer (buf, 8);
2728
c5a27d9c
JJ		 2729 /* If the previous frame pc value is 0, then we are at the end of the stack
2730 and don't want to unwind past this frame. We return a null frame_id to
2731 indicate this. */
2732 libunwind_frame_prev_register (next_frame, this_cache, IA64_IP_REGNUM,
2733 &optimized, &lval, &addr, &realnum, &prev_ip);
2734
2735 if (prev_ip != 0)
2736 (*this_id) = frame_id_build_special (id.stack_addr, id.code_addr, bsp);
2737 else
2738 (*this_id) = null_frame_id;
968d1cb4
JJ		 2739
2740 if (gdbarch_debug >= 1)
2741 fprintf_unfiltered (gdb_stdlog,
78ced177
JJ		 2742 "libunwind frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
2743 paddr_nz (id.code_addr), paddr_nz (id.stack_addr),
2744 paddr_nz (bsp), next_frame);
968d1cb4
JJ		 2745}
2746
2747static void
2748ia64_libunwind_frame_prev_register (struct frame_info *next_frame,
2749 void **this_cache,
2750 int regnum, int *optimizedp,
2751 enum lval_type *lvalp, CORE_ADDR *addrp,
88d82102 2752 int *realnump, gdb_byte *valuep)
968d1cb4
JJ		 2753{
2754 int reg = regnum;
2755
2756 if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
2757 reg = IA64_PR_REGNUM;
2758 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
2759 reg = IA64_UNAT_REGNUM;
2760
2761 /* Let libunwind do most of the work. */
2762 libunwind_frame_prev_register (next_frame, this_cache, reg,
2763 optimizedp, lvalp, addrp, realnump, valuep);
2764
6672f2ae
AS		 2765 /* No more to do if the value is not supposed to be supplied. */
2766 if (!valuep)
2767 return;
2768
968d1cb4
JJ		 2769 if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
2770 {
2771 ULONGEST prN_val;
2772
2773 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
2774 {
2775 int rrb_pr = 0;
2776 ULONGEST cfm;
2777 unsigned char buf[MAX_REGISTER_SIZE];
2778
2779 /* Fetch predicate register rename base from current frame
2780 marker for this frame. */
2781 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
2782 cfm = extract_unsigned_integer (buf, 8);
2783 rrb_pr = (cfm >> 32) & 0x3f;
2784
2785 /* Adjust the register number to account for register rotation. */
2786 regnum = VP16_REGNUM
2787 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
2788 }
2789 prN_val = extract_bit_field ((unsigned char *) valuep,
2790 regnum - VP0_REGNUM, 1);
2791 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), prN_val);
2792 }
2793 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
2794 {
2795 ULONGEST unatN_val;
2796
2797 unatN_val = extract_bit_field ((unsigned char *) valuep,
2798 regnum - IA64_NAT0_REGNUM, 1);
2799 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
2800 unatN_val);
2801 }
2802 else if (regnum == IA64_BSP_REGNUM)
2803 {
2804 char cfm_valuep[MAX_REGISTER_SIZE];
2805 int cfm_optim;
2806 int cfm_realnum;
2807 enum lval_type cfm_lval;
2808 CORE_ADDR cfm_addr;
2809 CORE_ADDR bsp, prev_cfm, prev_bsp;
2810
2811 /* We want to calculate the previous bsp as the end of the previous register stack frame.
2812 This corresponds to what the hardware bsp register will be if we pop the frame
2813 back which is why we might have been called. We know that libunwind will pass us back
2814 the beginning of the current frame so we should just add sof to it. */
2815 prev_bsp = extract_unsigned_integer (valuep, 8);
2816 libunwind_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
2817 &cfm_optim, &cfm_lval, &cfm_addr, &cfm_realnum, cfm_valuep);
2818 prev_cfm = extract_unsigned_integer (cfm_valuep, 8);
2819 prev_bsp = rse_address_add (prev_bsp, (prev_cfm & 0x7f));
2820
2821 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
2822 prev_bsp);
2823 }
2824
2825 if (gdbarch_debug >= 1)
2826 fprintf_unfiltered (gdb_stdlog,
78ced177 2827 "libunwind prev register <%s> is 0x%s\n",
c5a27d9c
JJ		 2828 (regnum < IA64_GR32_REGNUM
2829 || (regnum > IA64_GR127_REGNUM
2830 && regnum < LAST_PSEUDO_REGNUM))
2831 ? ia64_register_names[regnum]
2832 : (regnum < LAST_PSEUDO_REGNUM
2833 ? ia64_register_names[regnum-IA64_GR32_REGNUM+V32_REGNUM]
2834 : "OUT_OF_RANGE"),
78ced177 2835 paddr_nz (extract_unsigned_integer (valuep, 8)));
968d1cb4
JJ		 2836}
2837
2838static const struct frame_unwind ia64_libunwind_frame_unwind =
2839{
2840 NORMAL_FRAME,
2841 ia64_libunwind_frame_this_id,
2842 ia64_libunwind_frame_prev_register
2843};
2844
2845static const struct frame_unwind *
2846ia64_libunwind_frame_sniffer (struct frame_info *next_frame)
2847{
2848 if (libunwind_is_initialized () && libunwind_frame_sniffer (next_frame))
2849 return &ia64_libunwind_frame_unwind;
2850
2851 return NULL;
2852}
2853
c5a27d9c
JJ		 2854static void
2855ia64_libunwind_sigtramp_frame_this_id (struct frame_info *next_frame, void **this_cache,
2856 struct frame_id *this_id)
2857{
2858 char buf[8];
2859 CORE_ADDR bsp;
2860 struct frame_id id;
2861 CORE_ADDR prev_ip;
2862
2863 libunwind_frame_this_id (next_frame, this_cache, &id);
2864 if (frame_id_eq (id, null_frame_id))
2865 {
2866 (*this_id) = null_frame_id;
2867 return;
2868 }
2869
2870 /* We must add the bsp as the special address for frame comparison
2871 purposes. */
2872 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2873 bsp = extract_unsigned_integer (buf, 8);
2874
2875 /* For a sigtramp frame, we don't make the check for previous ip being 0. */
2876 (*this_id) = frame_id_build_special (id.stack_addr, id.code_addr, bsp);
2877
2878 if (gdbarch_debug >= 1)
2879 fprintf_unfiltered (gdb_stdlog,
2880 "libunwind sigtramp frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
2881 paddr_nz (id.code_addr), paddr_nz (id.stack_addr),
2882 paddr_nz (bsp), next_frame);
2883}
2884
2885static void
2886ia64_libunwind_sigtramp_frame_prev_register (struct frame_info *next_frame,
2887 void **this_cache,
2888 int regnum, int *optimizedp,
2889 enum lval_type *lvalp, CORE_ADDR *addrp,
88d82102 2890 int *realnump, gdb_byte *valuep)
c5a27d9c
JJ		 2891
2892{
2893 CORE_ADDR prev_ip, addr;
2894 int realnum, optimized;
2895 enum lval_type lval;
2896
2897
2898 /* If the previous frame pc value is 0, then we want to use the SIGCONTEXT
2899 method of getting previous registers. */
2900 libunwind_frame_prev_register (next_frame, this_cache, IA64_IP_REGNUM,
2901 &optimized, &lval, &addr, &realnum, &prev_ip);
2902
2903 if (prev_ip == 0)
2904 {
2905 void *tmp_cache = NULL;
2906 ia64_sigtramp_frame_prev_register (next_frame, &tmp_cache, regnum, optimizedp, lvalp,
2907 addrp, realnump, valuep);
2908 }
2909 else
2910 ia64_libunwind_frame_prev_register (next_frame, this_cache, regnum, optimizedp, lvalp,
2911 addrp, realnump, valuep);
2912}
2913
2914static const struct frame_unwind ia64_libunwind_sigtramp_frame_unwind =
2915{
2916 SIGTRAMP_FRAME,
2917 ia64_libunwind_sigtramp_frame_this_id,
2918 ia64_libunwind_sigtramp_frame_prev_register
2919};
2920
2921static const struct frame_unwind *
2922ia64_libunwind_sigtramp_frame_sniffer (struct frame_info *next_frame)
2923{
2924 if (libunwind_is_initialized ())
2925 {
2926 if (libunwind_sigtramp_frame_sniffer (next_frame))
2927 return &ia64_libunwind_sigtramp_frame_unwind;
2928 return NULL;
2929 }
2930 else
2931 return ia64_sigtramp_frame_sniffer (next_frame);
2932}
2933
968d1cb4
JJ		 2934/* Set of libunwind callback acccessor functions. */
2935static unw_accessors_t ia64_unw_accessors =
2936{
2937 ia64_find_proc_info_x,
2938 ia64_put_unwind_info,
2939 ia64_get_dyn_info_list,
2940 ia64_access_mem,
2941 ia64_access_reg,
2942 ia64_access_fpreg,
2943 /* resume */
2944 /* get_proc_name */
2945};
2946
c5a27d9c
JJ		 2947/* Set of special libunwind callback acccessor functions specific for accessing
2948 the rse registers. At the top of the stack, we want libunwind to figure out
2949 how to read r32 - r127. Though usually they are found sequentially in memory
2950 starting from $bof, this is not always true. */
2951static unw_accessors_t ia64_unw_rse_accessors =
2952{
2953 ia64_find_proc_info_x,
2954 ia64_put_unwind_info,
2955 ia64_get_dyn_info_list,
2956 ia64_access_mem,
2957 ia64_access_rse_reg,
2958 ia64_access_fpreg,
2959 /* resume */
2960 /* get_proc_name */
2961};
2962
968d1cb4
JJ		 2963/* Set of ia64 gdb libunwind-frame callbacks and data for generic libunwind-frame code to use. */
2964static struct libunwind_descr ia64_libunwind_descr =
2965{
2966 ia64_gdb2uw_regnum,
2967 ia64_uw2gdb_regnum,
2968 ia64_is_fpreg,
2969 &ia64_unw_accessors,
c5a27d9c 2970 &ia64_unw_rse_accessors,
968d1cb4
JJ		 2971};
2972
2973#endif /* HAVE_LIBUNWIND_IA64_H */
2974
74055713
AC		 2975/* Should we use DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS instead of
2976 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc and TYPE
2977 is the type (which is known to be struct, union or array). */
16461d7d
KB		 2978int
2979ia64_use_struct_convention (int gcc_p, struct type *type)
2980{
64a5b29c
KB		 2981 struct type *float_elt_type;
2982
2983 /* HFAs are structures (or arrays) consisting entirely of floating
2984 point values of the same length. Up to 8 of these are returned
2985 in registers. Don't use the struct convention when this is the
004d836a 2986 case. */
64a5b29c
KB		 2987 float_elt_type = is_float_or_hfa_type (type);
2988 if (float_elt_type != NULL
2989 && TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type) <= 8)
2990 return 0;
2991
2992 /* Other structs of length 32 or less are returned in r8-r11.
004d836a 2993 Don't use the struct convention for those either. */
16461d7d
KB		 2994 return TYPE_LENGTH (type) > 32;
2995}
2996
2997void
2d522557
AC		 2998ia64_extract_return_value (struct type *type, struct regcache *regcache,
2999 gdb_byte *valbuf)
16461d7d 3000{
64a5b29c
KB		 3001 struct type *float_elt_type;
3002
3003 float_elt_type = is_float_or_hfa_type (type);
3004 if (float_elt_type != NULL)
3005 {
004d836a 3006 char from[MAX_REGISTER_SIZE];
64a5b29c
KB		 3007 int offset = 0;
3008 int regnum = IA64_FR8_REGNUM;
3009 int n = TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type);
3010
3011 while (n-- > 0)
3012 {
004d836a
JJ		 3013 regcache_cooked_read (regcache, regnum, from);
3014 convert_typed_floating (from, builtin_type_ia64_ext,
3015 (char *)valbuf + offset, float_elt_type);
64a5b29c
KB		 3016 offset += TYPE_LENGTH (float_elt_type);
3017 regnum++;
3018 }
3019 }
16461d7d 3020 else
004d836a
JJ		 3021 {
3022 ULONGEST val;
3023 int offset = 0;
3024 int regnum = IA64_GR8_REGNUM;
3025 int reglen = TYPE_LENGTH (ia64_register_type (NULL, IA64_GR8_REGNUM));
3026 int n = TYPE_LENGTH (type) / reglen;
3027 int m = TYPE_LENGTH (type) % reglen;
16461d7d 3028
004d836a
JJ		 3029 while (n-- > 0)
3030 {
3031 ULONGEST val;
3032 regcache_cooked_read_unsigned (regcache, regnum, &val);
3033 memcpy ((char *)valbuf + offset, &val, reglen);
3034 offset += reglen;
3035 regnum++;
3036 }
16461d7d 3037
004d836a
JJ		 3038 if (m)
3039 {
3040 regcache_cooked_read_unsigned (regcache, regnum, &val);
3041 memcpy ((char *)valbuf + offset, &val, m);
3042 }
3043 }
16461d7d
KB		 3044}
3045
3046CORE_ADDR
004d836a 3047ia64_extract_struct_value_address (struct regcache *regcache)
16461d7d 3048{
8a3fe4f8 3049 error (_("ia64_extract_struct_value_address called and cannot get struct value address"));
004d836a 3050 return 0;
16461d7d
KB		 3051}
3052
16461d7d 3053
64a5b29c
KB		 3054static int
3055is_float_or_hfa_type_recurse (struct type *t, struct type **etp)
3056{
3057 switch (TYPE_CODE (t))
3058 {
3059 case TYPE_CODE_FLT:
3060 if (*etp)
3061 return TYPE_LENGTH (*etp) == TYPE_LENGTH (t);
3062 else
3063 {
3064 *etp = t;
3065 return 1;
3066 }
3067 break;
3068 case TYPE_CODE_ARRAY:
98f96ba1
KB		 3069 return
3070 is_float_or_hfa_type_recurse (check_typedef (TYPE_TARGET_TYPE (t)),
3071 etp);
64a5b29c
KB		 3072 break;
3073 case TYPE_CODE_STRUCT:
3074 {
3075 int i;
3076
3077 for (i = 0; i < TYPE_NFIELDS (t); i++)
98f96ba1
KB		 3078 if (!is_float_or_hfa_type_recurse
3079 (check_typedef (TYPE_FIELD_TYPE (t, i)), etp))
64a5b29c
KB		 3080 return 0;
3081 return 1;
3082 }
3083 break;
3084 default:
3085 return 0;
3086 break;
3087 }
3088}
3089
3090/* Determine if the given type is one of the floating point types or
3091 and HFA (which is a struct, array, or combination thereof whose
004d836a 3092 bottom-most elements are all of the same floating point type). */
64a5b29c
KB		 3093
3094static struct type *
3095is_float_or_hfa_type (struct type *t)
3096{
3097 struct type *et = 0;
3098
3099 return is_float_or_hfa_type_recurse (t, &et) ? et : 0;
3100}
3101
3102
98f96ba1
KB		 3103/* Return 1 if the alignment of T is such that the next even slot
3104 should be used. Return 0, if the next available slot should
3105 be used. (See section 8.5.1 of the IA-64 Software Conventions
004d836a 3106 and Runtime manual). */
98f96ba1
KB		 3107
3108static int
3109slot_alignment_is_next_even (struct type *t)
3110{
3111 switch (TYPE_CODE (t))
3112 {
3113 case TYPE_CODE_INT:
3114 case TYPE_CODE_FLT:
3115 if (TYPE_LENGTH (t) > 8)
3116 return 1;
3117 else
3118 return 0;
3119 case TYPE_CODE_ARRAY:
3120 return
3121 slot_alignment_is_next_even (check_typedef (TYPE_TARGET_TYPE (t)));
3122 case TYPE_CODE_STRUCT:
3123 {
3124 int i;
3125
3126 for (i = 0; i < TYPE_NFIELDS (t); i++)
3127 if (slot_alignment_is_next_even
3128 (check_typedef (TYPE_FIELD_TYPE (t, i))))
3129 return 1;
3130 return 0;
3131 }
3132 default:
3133 return 0;
3134 }
3135}
3136
64a5b29c
KB		 3137/* Attempt to find (and return) the global pointer for the given
3138 function.
3139
3140 This is a rather nasty bit of code searchs for the .dynamic section
3141 in the objfile corresponding to the pc of the function we're trying
3142 to call. Once it finds the addresses at which the .dynamic section
3143 lives in the child process, it scans the Elf64_Dyn entries for a
3144 DT_PLTGOT tag. If it finds one of these, the corresponding
3145 d_un.d_ptr value is the global pointer. */
3146
3147static CORE_ADDR
b33e8514 3148ia64_find_global_pointer (CORE_ADDR faddr)
64a5b29c 3149{
76d689a6 3150 struct obj_section *faddr_sect;
64a5b29c 3151
76d689a6
KB		 3152 faddr_sect = find_pc_section (faddr);
3153 if (faddr_sect != NULL)
64a5b29c
KB		 3154 {
3155 struct obj_section *osect;
3156
76d689a6 3157 ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect)
64a5b29c
KB		 3158 {
3159 if (strcmp (osect->the_bfd_section->name, ".dynamic") == 0)
3160 break;
3161 }
3162
76d689a6 3163 if (osect < faddr_sect->objfile->sections_end)
64a5b29c
KB		 3164 {
3165 CORE_ADDR addr;
3166
3167 addr = osect->addr;
3168 while (addr < osect->endaddr)
3169 {
3170 int status;
3171 LONGEST tag;
3172 char buf[8];
3173
3174 status = target_read_memory (addr, buf, sizeof (buf));
3175 if (status != 0)
3176 break;
3177 tag = extract_signed_integer (buf, sizeof (buf));
3178
3179 if (tag == DT_PLTGOT)
3180 {
3181 CORE_ADDR global_pointer;
3182
3183 status = target_read_memory (addr + 8, buf, sizeof (buf));
3184 if (status != 0)
3185 break;
7c0b4a20 3186 global_pointer = extract_unsigned_integer (buf, sizeof (buf));
64a5b29c
KB		 3187
3188 /* The payoff... */
3189 return global_pointer;
3190 }
3191
3192 if (tag == DT_NULL)
3193 break;
3194
3195 addr += 16;
3196 }
3197 }
3198 }
3199 return 0;
3200}
3201
3202/* Given a function's address, attempt to find (and return) the
3203 corresponding (canonical) function descriptor. Return 0 if
004d836a 3204 not found. */
64a5b29c
KB		 3205static CORE_ADDR
3206find_extant_func_descr (CORE_ADDR faddr)
3207{
76d689a6 3208 struct obj_section *faddr_sect;
64a5b29c 3209
004d836a 3210 /* Return early if faddr is already a function descriptor. */
76d689a6
KB		 3211 faddr_sect = find_pc_section (faddr);
3212 if (faddr_sect && strcmp (faddr_sect->the_bfd_section->name, ".opd") == 0)
64a5b29c
KB		 3213 return faddr;
3214
76d689a6 3215 if (faddr_sect != NULL)
64a5b29c 3216 {
76d689a6
KB		 3217 struct obj_section *osect;
3218 ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect)
64a5b29c
KB		 3219 {
3220 if (strcmp (osect->the_bfd_section->name, ".opd") == 0)
3221 break;
3222 }
3223
76d689a6 3224 if (osect < faddr_sect->objfile->sections_end)
64a5b29c
KB		 3225 {
3226 CORE_ADDR addr;
3227
3228 addr = osect->addr;
3229 while (addr < osect->endaddr)
3230 {
3231 int status;
3232 LONGEST faddr2;
3233 char buf[8];
3234
3235 status = target_read_memory (addr, buf, sizeof (buf));
3236 if (status != 0)
3237 break;
3238 faddr2 = extract_signed_integer (buf, sizeof (buf));
3239
3240 if (faddr == faddr2)
3241 return addr;
3242
3243 addr += 16;
3244 }
3245 }
3246 }
3247 return 0;
3248}
3249
3250/* Attempt to find a function descriptor corresponding to the
3251 given address. If none is found, construct one on the
004d836a 3252 stack using the address at fdaptr. */
64a5b29c
KB		 3253
3254static CORE_ADDR
3255find_func_descr (CORE_ADDR faddr, CORE_ADDR *fdaptr)
3256{
3257 CORE_ADDR fdesc;
3258
3259 fdesc = find_extant_func_descr (faddr);
3260
3261 if (fdesc == 0)
3262 {
3263 CORE_ADDR global_pointer;
3264 char buf[16];
3265
3266 fdesc = *fdaptr;
3267 *fdaptr += 16;
3268
b33e8514 3269 global_pointer = ia64_find_global_pointer (faddr);
64a5b29c
KB		 3270
3271 if (global_pointer == 0)
3272 global_pointer = read_register (IA64_GR1_REGNUM);
3273
fbd9dcd3
AC		 3274 store_unsigned_integer (buf, 8, faddr);
3275 store_unsigned_integer (buf + 8, 8, global_pointer);
64a5b29c
KB		 3276
3277 write_memory (fdesc, buf, 16);
3278 }
3279
3280 return fdesc;
3281}
16461d7d 3282
af8b88dd
JJ		 3283/* Use the following routine when printing out function pointers
3284 so the user can see the function address rather than just the
3285 function descriptor. */
3286static CORE_ADDR
e2d0e7eb
AC		 3287ia64_convert_from_func_ptr_addr (struct gdbarch *gdbarch, CORE_ADDR addr,
3288 struct target_ops *targ)
af8b88dd
JJ		 3289{
3290 struct obj_section *s;
3291
3292 s = find_pc_section (addr);
3293
3294 /* check if ADDR points to a function descriptor. */
3295 if (s && strcmp (s->the_bfd_section->name, ".opd") == 0)
3296 return read_memory_unsigned_integer (addr, 8);
3297
3298 return addr;
3299}
3300
a78f21af 3301static CORE_ADDR
004d836a
JJ		 3302ia64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
3303{
3304 return sp & ~0xfLL;
3305}
3306
3307static CORE_ADDR
7d9b040b 3308ia64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
8dd5115e
AS		 3309 struct regcache *regcache, CORE_ADDR bp_addr,
3310 int nargs, struct value **args, CORE_ADDR sp,
3311 int struct_return, CORE_ADDR struct_addr)
16461d7d
KB		 3312{
3313 int argno;
ea7c478f 3314 struct value *arg;
16461d7d
KB		 3315 struct type *type;
3316 int len, argoffset;
64a5b29c 3317 int nslots, rseslots, memslots, slotnum, nfuncargs;
16461d7d 3318 int floatreg;
004d836a 3319 CORE_ADDR bsp, cfm, pfs, new_bsp, funcdescaddr, pc, global_pointer;
7d9b040b 3320 CORE_ADDR func_addr = find_function_addr (function, NULL);
16461d7d
KB		 3321
3322 nslots = 0;
64a5b29c 3323 nfuncargs = 0;
004d836a 3324 /* Count the number of slots needed for the arguments. */
16461d7d
KB		 3325 for (argno = 0; argno < nargs; argno++)
3326 {
3327 arg = args[argno];
4991999e 3328 type = check_typedef (value_type (arg));
16461d7d
KB		 3329 len = TYPE_LENGTH (type);
3330
98f96ba1 3331 if ((nslots & 1) && slot_alignment_is_next_even (type))
16461d7d
KB		 3332 nslots++;
3333
64a5b29c
KB		 3334 if (TYPE_CODE (type) == TYPE_CODE_FUNC)
3335 nfuncargs++;
3336
16461d7d
KB		 3337 nslots += (len + 7) / 8;
3338 }
3339
004d836a 3340 /* Divvy up the slots between the RSE and the memory stack. */
16461d7d
KB		 3341 rseslots = (nslots > 8) ? 8 : nslots;
3342 memslots = nslots - rseslots;
3343
004d836a
JJ		 3344 /* Allocate a new RSE frame. */
3345 cfm = read_register (IA64_CFM_REGNUM);
16461d7d 3346
004d836a 3347 bsp = read_register (IA64_BSP_REGNUM);
16461d7d 3348 new_bsp = rse_address_add (bsp, rseslots);
004d836a 3349 write_register (IA64_BSP_REGNUM, new_bsp);
16461d7d 3350
004d836a 3351 pfs = read_register (IA64_PFS_REGNUM);
16461d7d
KB		 3352 pfs &= 0xc000000000000000LL;
3353 pfs |= (cfm & 0xffffffffffffLL);
004d836a 3354 write_register (IA64_PFS_REGNUM, pfs);
16461d7d
KB		 3355
3356 cfm &= 0xc000000000000000LL;
3357 cfm |= rseslots;
004d836a 3358 write_register (IA64_CFM_REGNUM, cfm);
16461d7d 3359
64a5b29c
KB		 3360 /* We will attempt to find function descriptors in the .opd segment,
3361 but if we can't we'll construct them ourselves. That being the
004d836a 3362 case, we'll need to reserve space on the stack for them. */
64a5b29c
KB		 3363 funcdescaddr = sp - nfuncargs * 16;
3364 funcdescaddr &= ~0xfLL;
3365
3366 /* Adjust the stack pointer to it's new value. The calling conventions
3367 require us to have 16 bytes of scratch, plus whatever space is
004d836a 3368 necessary for the memory slots and our function descriptors. */
64a5b29c 3369 sp = sp - 16 - (memslots + nfuncargs) * 8;
004d836a 3370 sp &= ~0xfLL; /* Maintain 16 byte alignment. */
16461d7d 3371
64a5b29c
KB		 3372 /* Place the arguments where they belong. The arguments will be
3373 either placed in the RSE backing store or on the memory stack.
3374 In addition, floating point arguments or HFAs are placed in
004d836a 3375 floating point registers. */
16461d7d
KB		 3376 slotnum = 0;
3377 floatreg = IA64_FR8_REGNUM;
3378 for (argno = 0; argno < nargs; argno++)
3379 {
64a5b29c
KB		 3380 struct type *float_elt_type;
3381
16461d7d 3382 arg = args[argno];
4991999e 3383 type = check_typedef (value_type (arg));
16461d7d 3384 len = TYPE_LENGTH (type);
64a5b29c 3385
004d836a 3386 /* Special handling for function parameters. */
64a5b29c
KB		 3387 if (len == 8
3388 && TYPE_CODE (type) == TYPE_CODE_PTR
3389 && TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC)
3390 {
3391 char val_buf[8];
3392
fbd9dcd3 3393 store_unsigned_integer (val_buf, 8,
0fd88904 3394 find_func_descr (extract_unsigned_integer (value_contents (arg), 8),
fbd9dcd3 3395 &funcdescaddr));
64a5b29c
KB		 3396 if (slotnum < rseslots)
3397 write_memory (rse_address_add (bsp, slotnum), val_buf, 8);
3398 else
3399 write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
3400 slotnum++;
3401 continue;
3402 }
3403
004d836a 3404 /* Normal slots. */
98f96ba1
KB		 3405
3406 /* Skip odd slot if necessary... */
3407 if ((slotnum & 1) && slot_alignment_is_next_even (type))
16461d7d 3408 slotnum++;
98f96ba1 3409
16461d7d
KB		 3410 argoffset = 0;
3411 while (len > 0)
3412 {
3413 char val_buf[8];
3414
3415 memset (val_buf, 0, 8);
0fd88904 3416 memcpy (val_buf, value_contents (arg) + argoffset, (len > 8) ? 8 : len);
16461d7d
KB		 3417
3418 if (slotnum < rseslots)
3419 write_memory (rse_address_add (bsp, slotnum), val_buf, 8);
3420 else
3421 write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
3422
3423 argoffset += 8;
3424 len -= 8;
3425 slotnum++;
3426 }
64a5b29c 3427
004d836a 3428 /* Handle floating point types (including HFAs). */
64a5b29c
KB		 3429 float_elt_type = is_float_or_hfa_type (type);
3430 if (float_elt_type != NULL)
3431 {
3432 argoffset = 0;
3433 len = TYPE_LENGTH (type);
3434 while (len > 0 && floatreg < IA64_FR16_REGNUM)
3435 {
004d836a 3436 char to[MAX_REGISTER_SIZE];
0fd88904 3437 convert_typed_floating (value_contents (arg) + argoffset, float_elt_type,
004d836a
JJ		 3438 to, builtin_type_ia64_ext);
3439 regcache_cooked_write (regcache, floatreg, (void *)to);
64a5b29c
KB		 3440 floatreg++;
3441 argoffset += TYPE_LENGTH (float_elt_type);
3442 len -= TYPE_LENGTH (float_elt_type);
3443 }
16461d7d
KB		 3444 }
3445 }
3446
004d836a 3447 /* Store the struct return value in r8 if necessary. */
16461d7d
KB		 3448 if (struct_return)
3449 {
004d836a 3450 regcache_cooked_write_unsigned (regcache, IA64_GR8_REGNUM, (ULONGEST)struct_addr);
16461d7d
KB		 3451 }
3452
b33e8514 3453 global_pointer = ia64_find_global_pointer (func_addr);
8dd5115e 3454
004d836a
JJ		 3455 if (global_pointer != 0)
3456 write_register (IA64_GR1_REGNUM, global_pointer);
a59fe496 3457
004d836a 3458 write_register (IA64_BR0_REGNUM, bp_addr);
16461d7d 3459
004d836a 3460 write_register (sp_regnum, sp);
16461d7d
KB		 3461
3462 return sp;
3463}
3464
004d836a
JJ		 3465static struct frame_id
3466ia64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
16461d7d 3467{
004d836a 3468 char buf[8];
4afcc598 3469 CORE_ADDR sp, bsp;
004d836a
JJ		 3470
3471 frame_unwind_register (next_frame, sp_regnum, buf);
3472 sp = extract_unsigned_integer (buf, 8);
3473
4afcc598
JJ		 3474 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
3475 bsp = extract_unsigned_integer (buf, 8);
3476
3477 if (gdbarch_debug >= 1)
3478 fprintf_unfiltered (gdb_stdlog,
78ced177
JJ		 3479 "dummy frame id: code 0x%s, stack 0x%s, special 0x%s\n",
3480 paddr_nz (frame_pc_unwind (next_frame)),
3481 paddr_nz (sp), paddr_nz (bsp));
4afcc598
JJ		 3482
3483 return frame_id_build_special (sp, frame_pc_unwind (next_frame), bsp);
16461d7d
KB		 3484}
3485
004d836a
JJ		 3486static CORE_ADDR
3487ia64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
16461d7d 3488{
004d836a
JJ		 3489 char buf[8];
3490 CORE_ADDR ip, psr, pc;
3491
3492 frame_unwind_register (next_frame, IA64_IP_REGNUM, buf);
3493 ip = extract_unsigned_integer (buf, 8);
3494 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
3495 psr = extract_unsigned_integer (buf, 8);
3496
3497 pc = (ip & ~0xf) | ((psr >> 41) & 3);
3498 return pc;
16461d7d
KB		 3499}
3500
3501static void
88d82102
JJ		 3502ia64_store_return_value (struct type *type, struct regcache *regcache,
3503 const gdb_byte *valbuf)
16461d7d 3504{
004d836a 3505 if (TYPE_CODE (type) == TYPE_CODE_FLT)
16461d7d 3506 {
004d836a
JJ		 3507 char to[MAX_REGISTER_SIZE];
3508 convert_typed_floating (valbuf, type, to, builtin_type_ia64_ext);
3509 regcache_cooked_write (regcache, IA64_FR8_REGNUM, (void *)to);
3510 target_store_registers (IA64_FR8_REGNUM);
16461d7d
KB		 3511 }
3512 else
004d836a 3513 regcache_cooked_write (regcache, IA64_GR8_REGNUM, valbuf);
16461d7d
KB		 3514}
3515
3516static void
1750fa04
AC		 3517ia64_remote_translate_xfer_address (struct gdbarch *gdbarch,
3518 struct regcache *regcache,
3519 CORE_ADDR memaddr, int nr_bytes,
16461d7d
KB		 3520 CORE_ADDR *targ_addr, int *targ_len)
3521{
3522 *targ_addr = memaddr;
3523 *targ_len = nr_bytes;
3524}
3525
6926787d
AS		 3526static int
3527ia64_print_insn (bfd_vma memaddr, struct disassemble_info *info)
3528{
3529 info->bytes_per_line = SLOT_MULTIPLIER;
3530 return print_insn_ia64 (memaddr, info);
3531}
3532
16461d7d
KB		 3533static struct gdbarch *
3534ia64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3535{
3536 struct gdbarch *gdbarch;
244bc108 3537 struct gdbarch_tdep *tdep;
244bc108 3538
85bf2b91
JJ		 3539 /* If there is already a candidate, use it. */
3540 arches = gdbarch_list_lookup_by_info (arches, &info);
3541 if (arches != NULL)
3542 return arches->gdbarch;
16461d7d 3543
244bc108
KB		 3544 tdep = xmalloc (sizeof (struct gdbarch_tdep));
3545 gdbarch = gdbarch_alloc (&info, tdep);
244bc108 3546
b33e8514 3547 tdep->sigcontext_register_address = 0;
698cb3f0 3548
004d836a
JJ		 3549 /* Define the ia64 floating-point format to gdb. */
3550 builtin_type_ia64_ext =
3551 init_type (TYPE_CODE_FLT, 128 / 8,
3552 0, "builtin_type_ia64_ext", NULL);
3553 TYPE_FLOATFORMAT (builtin_type_ia64_ext) = &floatformat_ia64_ext;
3554
5439edaa
AC		 3555 /* According to the ia64 specs, instructions that store long double
3556 floats in memory use a long-double format different than that
3557 used in the floating registers. The memory format matches the
3558 x86 extended float format which is 80 bits. An OS may choose to
3559 use this format (e.g. GNU/Linux) or choose to use a different
3560 format for storing long doubles (e.g. HPUX). In the latter case,
3561 the setting of the format may be moved/overridden in an
3562 OS-specific tdep file. */
32edc941
JJ		 3563 set_gdbarch_long_double_format (gdbarch, &floatformat_i387_ext);
3564
16461d7d
KB		 3565 set_gdbarch_short_bit (gdbarch, 16);
3566 set_gdbarch_int_bit (gdbarch, 32);
3567 set_gdbarch_long_bit (gdbarch, 64);
3568 set_gdbarch_long_long_bit (gdbarch, 64);
3569 set_gdbarch_float_bit (gdbarch, 32);
3570 set_gdbarch_double_bit (gdbarch, 64);
33c08150 3571 set_gdbarch_long_double_bit (gdbarch, 128);
16461d7d
KB		 3572 set_gdbarch_ptr_bit (gdbarch, 64);
3573
004d836a
JJ		 3574 set_gdbarch_num_regs (gdbarch, NUM_IA64_RAW_REGS);
3575 set_gdbarch_num_pseudo_regs (gdbarch, LAST_PSEUDO_REGNUM - FIRST_PSEUDO_REGNUM);
16461d7d 3576 set_gdbarch_sp_regnum (gdbarch, sp_regnum);
698cb3f0 3577 set_gdbarch_fp0_regnum (gdbarch, IA64_FR0_REGNUM);
16461d7d
KB		 3578
3579 set_gdbarch_register_name (gdbarch, ia64_register_name);
004d836a
JJ		 3580 /* FIXME: Following interface should not be needed, however, without it recurse.exp
3581 gets a number of extra failures. */
b1e29e33 3582 set_gdbarch_deprecated_register_size (gdbarch, 8);
004d836a 3583 set_gdbarch_register_type (gdbarch, ia64_register_type);
16461d7d 3584
004d836a
JJ		 3585 set_gdbarch_pseudo_register_read (gdbarch, ia64_pseudo_register_read);
3586 set_gdbarch_pseudo_register_write (gdbarch, ia64_pseudo_register_write);
3587 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, ia64_dwarf_reg_to_regnum);
3588 set_gdbarch_register_reggroup_p (gdbarch, ia64_register_reggroup_p);
3589 set_gdbarch_convert_register_p (gdbarch, ia64_convert_register_p);
3590 set_gdbarch_register_to_value (gdbarch, ia64_register_to_value);
3591 set_gdbarch_value_to_register (gdbarch, ia64_value_to_register);
16461d7d 3592
004d836a 3593 set_gdbarch_skip_prologue (gdbarch, ia64_skip_prologue);
16461d7d 3594
b5622e8d 3595 set_gdbarch_deprecated_use_struct_convention (gdbarch, ia64_use_struct_convention);
004d836a 3596 set_gdbarch_extract_return_value (gdbarch, ia64_extract_return_value);
16461d7d 3597
004d836a 3598 set_gdbarch_store_return_value (gdbarch, ia64_store_return_value);
74055713 3599 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, ia64_extract_struct_value_address);
16461d7d
KB		 3600
3601 set_gdbarch_memory_insert_breakpoint (gdbarch, ia64_memory_insert_breakpoint);
3602 set_gdbarch_memory_remove_breakpoint (gdbarch, ia64_memory_remove_breakpoint);
3603 set_gdbarch_breakpoint_from_pc (gdbarch, ia64_breakpoint_from_pc);
3604 set_gdbarch_read_pc (gdbarch, ia64_read_pc);
b33e8514 3605 set_gdbarch_write_pc (gdbarch, ia64_write_pc);
16461d7d
KB		 3606
3607 /* Settings for calling functions in the inferior. */
8dd5115e 3608 set_gdbarch_push_dummy_call (gdbarch, ia64_push_dummy_call);
004d836a
JJ		 3609 set_gdbarch_frame_align (gdbarch, ia64_frame_align);
3610 set_gdbarch_unwind_dummy_id (gdbarch, ia64_unwind_dummy_id);
16461d7d 3611
004d836a 3612 set_gdbarch_unwind_pc (gdbarch, ia64_unwind_pc);
968d1cb4 3613#ifdef HAVE_LIBUNWIND_IA64_H
c5a27d9c 3614 frame_unwind_append_sniffer (gdbarch, ia64_libunwind_sigtramp_frame_sniffer);
968d1cb4
JJ		 3615 frame_unwind_append_sniffer (gdbarch, ia64_libunwind_frame_sniffer);
3616 libunwind_frame_set_descr (gdbarch, &ia64_libunwind_descr);
c5a27d9c
JJ		 3617#else
3618 frame_unwind_append_sniffer (gdbarch, ia64_sigtramp_frame_sniffer);
968d1cb4 3619#endif
004d836a
JJ		 3620 frame_unwind_append_sniffer (gdbarch, ia64_frame_sniffer);
3621 frame_base_set_default (gdbarch, &ia64_frame_base);
16461d7d
KB		 3622
3623 /* Settings that should be unnecessary. */
3624 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3625
16461d7d
KB		 3626 set_gdbarch_remote_translate_xfer_address (
3627 gdbarch, ia64_remote_translate_xfer_address);
3628
6926787d 3629 set_gdbarch_print_insn (gdbarch, ia64_print_insn);
af8b88dd 3630 set_gdbarch_convert_from_func_ptr_addr (gdbarch, ia64_convert_from_func_ptr_addr);
6926787d 3631
b33e8514
AS		 3632 /* Hook in ABI-specific overrides, if they have been registered. */
3633 gdbarch_init_osabi (info, gdbarch);
3634
16461d7d
KB		 3635 return gdbarch;
3636}
3637
a78f21af
AC		 3638extern initialize_file_ftype _initialize_ia64_tdep; /* -Wmissing-prototypes */
3639
16461d7d
KB		 3640void
3641_initialize_ia64_tdep (void)
3642{
b33e8514 3643 gdbarch_register (bfd_arch_ia64, ia64_gdbarch_init, NULL);
16461d7d 3644}
GDB Binutils - Deliverables
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