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16461d7d | 1 | /* Target-dependent code for the IA-64 for GDB, the GNU debugger. |
ca557f44 | 2 | |
e2882c85 | 3 | Copyright (C) 1999-2018 Free Software Foundation, Inc. |
16461d7d KB |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
16461d7d KB |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
16461d7d KB |
19 | |
20 | #include "defs.h" | |
21 | #include "inferior.h" | |
16461d7d | 22 | #include "gdbcore.h" |
8064c6ae | 23 | #include "arch-utils.h" |
16461d7d | 24 | #include "floatformat.h" |
e6bb342a | 25 | #include "gdbtypes.h" |
4e052eda | 26 | #include "regcache.h" |
004d836a JJ |
27 | #include "reggroups.h" |
28 | #include "frame.h" | |
29 | #include "frame-base.h" | |
30 | #include "frame-unwind.h" | |
3b2ca824 | 31 | #include "target-float.h" |
fd0407d6 | 32 | #include "value.h" |
16461d7d KB |
33 | #include "objfiles.h" |
34 | #include "elf/common.h" /* for DT_PLTGOT value */ | |
244bc108 | 35 | #include "elf-bfd.h" |
a89aa300 | 36 | #include "dis-asm.h" |
7d9b040b | 37 | #include "infcall.h" |
b33e8514 | 38 | #include "osabi.h" |
9fc9f5e2 | 39 | #include "ia64-tdep.h" |
0d5de010 | 40 | #include "cp-abi.h" |
16461d7d | 41 | |
968d1cb4 | 42 | #ifdef HAVE_LIBUNWIND_IA64_H |
8973ff21 | 43 | #include "elf/ia64.h" /* for PT_IA_64_UNWIND value */ |
05e7c244 | 44 | #include "ia64-libunwind-tdep.h" |
c5a27d9c JJ |
45 | |
46 | /* Note: KERNEL_START is supposed to be an address which is not going | |
47 | to ever contain any valid unwind info. For ia64 linux, the choice | |
48 | of 0xc000000000000000 is fairly safe since that's uncached space. | |
49 | ||
50 | We use KERNEL_START as follows: after obtaining the kernel's | |
51 | unwind table via getunwind(), we project its unwind data into | |
52 | address-range KERNEL_START-(KERNEL_START+ktab_size) and then | |
53 | when ia64_access_mem() sees a memory access to this | |
54 | address-range, we redirect it to ktab instead. | |
55 | ||
56 | None of this hackery is needed with a modern kernel/libcs | |
57 | which uses the kernel virtual DSO to provide access to the | |
58 | kernel's unwind info. In that case, ktab_size remains 0 and | |
59 | hence the value of KERNEL_START doesn't matter. */ | |
60 | ||
61 | #define KERNEL_START 0xc000000000000000ULL | |
62 | ||
63 | static size_t ktab_size = 0; | |
64 | struct ia64_table_entry | |
65 | { | |
66 | uint64_t start_offset; | |
67 | uint64_t end_offset; | |
68 | uint64_t info_offset; | |
69 | }; | |
70 | ||
71 | static struct ia64_table_entry *ktab = NULL; | |
5d691c88 | 72 | static gdb::optional<gdb::byte_vector> ktab_buf; |
c5a27d9c | 73 | |
968d1cb4 JJ |
74 | #endif |
75 | ||
698cb3f0 KB |
76 | /* An enumeration of the different IA-64 instruction types. */ |
77 | ||
16461d7d KB |
78 | typedef enum instruction_type |
79 | { | |
80 | A, /* Integer ALU ; I-unit or M-unit */ | |
81 | I, /* Non-ALU integer; I-unit */ | |
82 | M, /* Memory ; M-unit */ | |
83 | F, /* Floating-point ; F-unit */ | |
84 | B, /* Branch ; B-unit */ | |
85 | L, /* Extended (L+X) ; I-unit */ | |
86 | X, /* Extended (L+X) ; I-unit */ | |
87 | undefined /* undefined or reserved */ | |
88 | } instruction_type; | |
89 | ||
90 | /* We represent IA-64 PC addresses as the value of the instruction | |
91 | pointer or'd with some bit combination in the low nibble which | |
92 | represents the slot number in the bundle addressed by the | |
93 | instruction pointer. The problem is that the Linux kernel | |
94 | multiplies its slot numbers (for exceptions) by one while the | |
95 | disassembler multiplies its slot numbers by 6. In addition, I've | |
96 | heard it said that the simulator uses 1 as the multiplier. | |
97 | ||
98 | I've fixed the disassembler so that the bytes_per_line field will | |
99 | be the slot multiplier. If bytes_per_line comes in as zero, it | |
100 | is set to six (which is how it was set up initially). -- objdump | |
101 | displays pretty disassembly dumps with this value. For our purposes, | |
102 | we'll set bytes_per_line to SLOT_MULTIPLIER. This is okay since we | |
1777feb0 | 103 | never want to also display the raw bytes the way objdump does. */ |
16461d7d KB |
104 | |
105 | #define SLOT_MULTIPLIER 1 | |
106 | ||
1777feb0 | 107 | /* Length in bytes of an instruction bundle. */ |
16461d7d KB |
108 | |
109 | #define BUNDLE_LEN 16 | |
110 | ||
939c61fa JK |
111 | /* See the saved memory layout comment for ia64_memory_insert_breakpoint. */ |
112 | ||
113 | #if BREAKPOINT_MAX < BUNDLE_LEN - 2 | |
114 | # error "BREAKPOINT_MAX < BUNDLE_LEN - 2" | |
115 | #endif | |
116 | ||
16461d7d KB |
117 | static gdbarch_init_ftype ia64_gdbarch_init; |
118 | ||
119 | static gdbarch_register_name_ftype ia64_register_name; | |
004d836a | 120 | static gdbarch_register_type_ftype ia64_register_type; |
16461d7d | 121 | static gdbarch_breakpoint_from_pc_ftype ia64_breakpoint_from_pc; |
16461d7d | 122 | static gdbarch_skip_prologue_ftype ia64_skip_prologue; |
64a5b29c | 123 | static struct type *is_float_or_hfa_type (struct type *t); |
e17a4113 UW |
124 | static CORE_ADDR ia64_find_global_pointer (struct gdbarch *gdbarch, |
125 | CORE_ADDR faddr); | |
16461d7d | 126 | |
004d836a | 127 | #define NUM_IA64_RAW_REGS 462 |
16461d7d | 128 | |
ae0d01d6 AH |
129 | /* Big enough to hold a FP register in bytes. */ |
130 | #define IA64_FP_REGISTER_SIZE 16 | |
131 | ||
16461d7d | 132 | static int sp_regnum = IA64_GR12_REGNUM; |
16461d7d | 133 | |
1777feb0 MS |
134 | /* NOTE: we treat the register stack registers r32-r127 as |
135 | pseudo-registers because they may not be accessible via the ptrace | |
136 | register get/set interfaces. */ | |
137 | ||
138 | enum pseudo_regs { FIRST_PSEUDO_REGNUM = NUM_IA64_RAW_REGS, | |
139 | VBOF_REGNUM = IA64_NAT127_REGNUM + 1, V32_REGNUM, | |
004d836a | 140 | V127_REGNUM = V32_REGNUM + 95, |
1777feb0 MS |
141 | VP0_REGNUM, VP16_REGNUM = VP0_REGNUM + 16, |
142 | VP63_REGNUM = VP0_REGNUM + 63, LAST_PSEUDO_REGNUM }; | |
16461d7d KB |
143 | |
144 | /* Array of register names; There should be ia64_num_regs strings in | |
145 | the initializer. */ | |
146 | ||
a121b7c1 | 147 | static const char *ia64_register_names[] = |
16461d7d KB |
148 | { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
149 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
150 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
151 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", | |
004d836a JJ |
152 | "", "", "", "", "", "", "", "", |
153 | "", "", "", "", "", "", "", "", | |
154 | "", "", "", "", "", "", "", "", | |
155 | "", "", "", "", "", "", "", "", | |
156 | "", "", "", "", "", "", "", "", | |
157 | "", "", "", "", "", "", "", "", | |
158 | "", "", "", "", "", "", "", "", | |
159 | "", "", "", "", "", "", "", "", | |
160 | "", "", "", "", "", "", "", "", | |
161 | "", "", "", "", "", "", "", "", | |
162 | "", "", "", "", "", "", "", "", | |
163 | "", "", "", "", "", "", "", "", | |
16461d7d KB |
164 | |
165 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
166 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
167 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
168 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
169 | "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", | |
170 | "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", | |
171 | "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55", | |
172 | "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63", | |
173 | "f64", "f65", "f66", "f67", "f68", "f69", "f70", "f71", | |
174 | "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79", | |
175 | "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", | |
176 | "f88", "f89", "f90", "f91", "f92", "f93", "f94", "f95", | |
177 | "f96", "f97", "f98", "f99", "f100", "f101", "f102", "f103", | |
178 | "f104", "f105", "f106", "f107", "f108", "f109", "f110", "f111", | |
179 | "f112", "f113", "f114", "f115", "f116", "f117", "f118", "f119", | |
180 | "f120", "f121", "f122", "f123", "f124", "f125", "f126", "f127", | |
181 | ||
004d836a JJ |
182 | "", "", "", "", "", "", "", "", |
183 | "", "", "", "", "", "", "", "", | |
184 | "", "", "", "", "", "", "", "", | |
185 | "", "", "", "", "", "", "", "", | |
186 | "", "", "", "", "", "", "", "", | |
187 | "", "", "", "", "", "", "", "", | |
188 | "", "", "", "", "", "", "", "", | |
189 | "", "", "", "", "", "", "", "", | |
16461d7d KB |
190 | |
191 | "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", | |
192 | ||
193 | "vfp", "vrap", | |
194 | ||
195 | "pr", "ip", "psr", "cfm", | |
196 | ||
197 | "kr0", "kr1", "kr2", "kr3", "kr4", "kr5", "kr6", "kr7", | |
198 | "", "", "", "", "", "", "", "", | |
199 | "rsc", "bsp", "bspstore", "rnat", | |
200 | "", "fcr", "", "", | |
201 | "eflag", "csd", "ssd", "cflg", "fsr", "fir", "fdr", "", | |
202 | "ccv", "", "", "", "unat", "", "", "", | |
203 | "fpsr", "", "", "", "itc", | |
204 | "", "", "", "", "", "", "", "", "", "", | |
205 | "", "", "", "", "", "", "", "", "", | |
206 | "pfs", "lc", "ec", | |
207 | "", "", "", "", "", "", "", "", "", "", | |
208 | "", "", "", "", "", "", "", "", "", "", | |
209 | "", "", "", "", "", "", "", "", "", "", | |
210 | "", "", "", "", "", "", "", "", "", "", | |
211 | "", "", "", "", "", "", "", "", "", "", | |
212 | "", "", "", "", "", "", "", "", "", "", | |
213 | "", | |
214 | "nat0", "nat1", "nat2", "nat3", "nat4", "nat5", "nat6", "nat7", | |
215 | "nat8", "nat9", "nat10", "nat11", "nat12", "nat13", "nat14", "nat15", | |
216 | "nat16", "nat17", "nat18", "nat19", "nat20", "nat21", "nat22", "nat23", | |
217 | "nat24", "nat25", "nat26", "nat27", "nat28", "nat29", "nat30", "nat31", | |
218 | "nat32", "nat33", "nat34", "nat35", "nat36", "nat37", "nat38", "nat39", | |
219 | "nat40", "nat41", "nat42", "nat43", "nat44", "nat45", "nat46", "nat47", | |
220 | "nat48", "nat49", "nat50", "nat51", "nat52", "nat53", "nat54", "nat55", | |
221 | "nat56", "nat57", "nat58", "nat59", "nat60", "nat61", "nat62", "nat63", | |
222 | "nat64", "nat65", "nat66", "nat67", "nat68", "nat69", "nat70", "nat71", | |
223 | "nat72", "nat73", "nat74", "nat75", "nat76", "nat77", "nat78", "nat79", | |
224 | "nat80", "nat81", "nat82", "nat83", "nat84", "nat85", "nat86", "nat87", | |
225 | "nat88", "nat89", "nat90", "nat91", "nat92", "nat93", "nat94", "nat95", | |
226 | "nat96", "nat97", "nat98", "nat99", "nat100","nat101","nat102","nat103", | |
227 | "nat104","nat105","nat106","nat107","nat108","nat109","nat110","nat111", | |
228 | "nat112","nat113","nat114","nat115","nat116","nat117","nat118","nat119", | |
229 | "nat120","nat121","nat122","nat123","nat124","nat125","nat126","nat127", | |
004d836a JJ |
230 | |
231 | "bof", | |
232 | ||
233 | "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", | |
234 | "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", | |
235 | "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", | |
236 | "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", | |
237 | "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71", | |
238 | "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79", | |
239 | "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87", | |
240 | "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95", | |
241 | "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103", | |
242 | "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111", | |
243 | "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119", | |
244 | "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127", | |
245 | ||
246 | "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", | |
247 | "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", | |
248 | "p16", "p17", "p18", "p19", "p20", "p21", "p22", "p23", | |
249 | "p24", "p25", "p26", "p27", "p28", "p29", "p30", "p31", | |
250 | "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39", | |
251 | "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47", | |
252 | "p48", "p49", "p50", "p51", "p52", "p53", "p54", "p55", | |
253 | "p56", "p57", "p58", "p59", "p60", "p61", "p62", "p63", | |
16461d7d KB |
254 | }; |
255 | ||
004d836a JJ |
256 | struct ia64_frame_cache |
257 | { | |
258 | CORE_ADDR base; /* frame pointer base for frame */ | |
259 | CORE_ADDR pc; /* function start pc for frame */ | |
260 | CORE_ADDR saved_sp; /* stack pointer for frame */ | |
261 | CORE_ADDR bsp; /* points at r32 for the current frame */ | |
262 | CORE_ADDR cfm; /* cfm value for current frame */ | |
4afcc598 | 263 | CORE_ADDR prev_cfm; /* cfm value for previous frame */ |
004d836a | 264 | int frameless; |
1777feb0 MS |
265 | int sof; /* Size of frame (decoded from cfm value). */ |
266 | int sol; /* Size of locals (decoded from cfm value). */ | |
267 | int sor; /* Number of rotating registers (decoded from | |
268 | cfm value). */ | |
004d836a JJ |
269 | CORE_ADDR after_prologue; |
270 | /* Address of first instruction after the last | |
271 | prologue instruction; Note that there may | |
272 | be instructions from the function's body | |
1777feb0 | 273 | intermingled with the prologue. */ |
004d836a JJ |
274 | int mem_stack_frame_size; |
275 | /* Size of the memory stack frame (may be zero), | |
1777feb0 | 276 | or -1 if it has not been determined yet. */ |
004d836a | 277 | int fp_reg; /* Register number (if any) used a frame pointer |
244bc108 | 278 | for this frame. 0 if no register is being used |
1777feb0 | 279 | as the frame pointer. */ |
004d836a JJ |
280 | |
281 | /* Saved registers. */ | |
282 | CORE_ADDR saved_regs[NUM_IA64_RAW_REGS]; | |
283 | ||
284 | }; | |
244bc108 | 285 | |
27067745 UW |
286 | static int |
287 | floatformat_valid (const struct floatformat *fmt, const void *from) | |
288 | { | |
289 | return 1; | |
290 | } | |
291 | ||
7458e667 | 292 | static const struct floatformat floatformat_ia64_ext_little = |
27067745 UW |
293 | { |
294 | floatformat_little, 82, 0, 1, 17, 65535, 0x1ffff, 18, 64, | |
7458e667 JB |
295 | floatformat_intbit_yes, "floatformat_ia64_ext_little", floatformat_valid, NULL |
296 | }; | |
297 | ||
298 | static const struct floatformat floatformat_ia64_ext_big = | |
299 | { | |
300 | floatformat_big, 82, 46, 47, 17, 65535, 0x1ffff, 64, 64, | |
301 | floatformat_intbit_yes, "floatformat_ia64_ext_big", floatformat_valid | |
27067745 UW |
302 | }; |
303 | ||
304 | static const struct floatformat *floatformats_ia64_ext[2] = | |
305 | { | |
7458e667 JB |
306 | &floatformat_ia64_ext_big, |
307 | &floatformat_ia64_ext_little | |
27067745 UW |
308 | }; |
309 | ||
310 | static struct type * | |
311 | ia64_ext_type (struct gdbarch *gdbarch) | |
312 | { | |
313 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
314 | ||
315 | if (!tdep->ia64_ext_type) | |
316 | tdep->ia64_ext_type | |
e9bb382b | 317 | = arch_float_type (gdbarch, 128, "builtin_type_ia64_ext", |
27067745 UW |
318 | floatformats_ia64_ext); |
319 | ||
320 | return tdep->ia64_ext_type; | |
321 | } | |
322 | ||
63807e1d | 323 | static int |
004d836a JJ |
324 | ia64_register_reggroup_p (struct gdbarch *gdbarch, int regnum, |
325 | struct reggroup *group) | |
16461d7d | 326 | { |
004d836a JJ |
327 | int vector_p; |
328 | int float_p; | |
329 | int raw_p; | |
330 | if (group == all_reggroup) | |
331 | return 1; | |
332 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
333 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
334 | raw_p = regnum < NUM_IA64_RAW_REGS; | |
335 | if (group == float_reggroup) | |
336 | return float_p; | |
337 | if (group == vector_reggroup) | |
338 | return vector_p; | |
339 | if (group == general_reggroup) | |
340 | return (!vector_p && !float_p); | |
341 | if (group == save_reggroup || group == restore_reggroup) | |
342 | return raw_p; | |
343 | return 0; | |
16461d7d KB |
344 | } |
345 | ||
004d836a | 346 | static const char * |
d93859e2 | 347 | ia64_register_name (struct gdbarch *gdbarch, int reg) |
16461d7d | 348 | { |
004d836a | 349 | return ia64_register_names[reg]; |
16461d7d KB |
350 | } |
351 | ||
004d836a JJ |
352 | struct type * |
353 | ia64_register_type (struct gdbarch *arch, int reg) | |
16461d7d | 354 | { |
004d836a | 355 | if (reg >= IA64_FR0_REGNUM && reg <= IA64_FR127_REGNUM) |
27067745 | 356 | return ia64_ext_type (arch); |
004d836a | 357 | else |
0dfff4cb | 358 | return builtin_type (arch)->builtin_long; |
16461d7d KB |
359 | } |
360 | ||
a78f21af | 361 | static int |
d3f73121 | 362 | ia64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
16461d7d | 363 | { |
004d836a JJ |
364 | if (reg >= IA64_GR32_REGNUM && reg <= IA64_GR127_REGNUM) |
365 | return V32_REGNUM + (reg - IA64_GR32_REGNUM); | |
366 | return reg; | |
16461d7d KB |
367 | } |
368 | ||
16461d7d KB |
369 | |
370 | /* Extract ``len'' bits from an instruction bundle starting at | |
371 | bit ``from''. */ | |
372 | ||
244bc108 | 373 | static long long |
948f8e3d | 374 | extract_bit_field (const gdb_byte *bundle, int from, int len) |
16461d7d KB |
375 | { |
376 | long long result = 0LL; | |
377 | int to = from + len; | |
378 | int from_byte = from / 8; | |
379 | int to_byte = to / 8; | |
380 | unsigned char *b = (unsigned char *) bundle; | |
381 | unsigned char c; | |
382 | int lshift; | |
383 | int i; | |
384 | ||
385 | c = b[from_byte]; | |
386 | if (from_byte == to_byte) | |
387 | c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8); | |
388 | result = c >> (from % 8); | |
389 | lshift = 8 - (from % 8); | |
390 | ||
391 | for (i = from_byte+1; i < to_byte; i++) | |
392 | { | |
393 | result |= ((long long) b[i]) << lshift; | |
394 | lshift += 8; | |
395 | } | |
396 | ||
397 | if (from_byte < to_byte && (to % 8 != 0)) | |
398 | { | |
399 | c = b[to_byte]; | |
400 | c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8); | |
401 | result |= ((long long) c) << lshift; | |
402 | } | |
403 | ||
404 | return result; | |
405 | } | |
406 | ||
1777feb0 | 407 | /* Replace the specified bits in an instruction bundle. */ |
16461d7d | 408 | |
244bc108 | 409 | static void |
948f8e3d | 410 | replace_bit_field (gdb_byte *bundle, long long val, int from, int len) |
16461d7d KB |
411 | { |
412 | int to = from + len; | |
413 | int from_byte = from / 8; | |
414 | int to_byte = to / 8; | |
415 | unsigned char *b = (unsigned char *) bundle; | |
416 | unsigned char c; | |
417 | ||
418 | if (from_byte == to_byte) | |
419 | { | |
420 | unsigned char left, right; | |
421 | c = b[from_byte]; | |
422 | left = (c >> (to % 8)) << (to % 8); | |
423 | right = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8); | |
424 | c = (unsigned char) (val & 0xff); | |
425 | c = (unsigned char) (c << (from % 8 + 8 - to % 8)) >> (8 - to % 8); | |
426 | c |= right | left; | |
427 | b[from_byte] = c; | |
428 | } | |
429 | else | |
430 | { | |
431 | int i; | |
432 | c = b[from_byte]; | |
433 | c = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8); | |
434 | c = c | (val << (from % 8)); | |
435 | b[from_byte] = c; | |
436 | val >>= 8 - from % 8; | |
437 | ||
438 | for (i = from_byte+1; i < to_byte; i++) | |
439 | { | |
440 | c = val & 0xff; | |
441 | val >>= 8; | |
442 | b[i] = c; | |
443 | } | |
444 | ||
445 | if (to % 8 != 0) | |
446 | { | |
447 | unsigned char cv = (unsigned char) val; | |
448 | c = b[to_byte]; | |
449 | c = c >> (to % 8) << (to % 8); | |
450 | c |= ((unsigned char) (cv << (8 - to % 8))) >> (8 - to % 8); | |
451 | b[to_byte] = c; | |
452 | } | |
453 | } | |
454 | } | |
455 | ||
456 | /* Return the contents of slot N (for N = 0, 1, or 2) in | |
1777feb0 | 457 | and instruction bundle. */ |
16461d7d | 458 | |
244bc108 | 459 | static long long |
948f8e3d | 460 | slotN_contents (gdb_byte *bundle, int slotnum) |
16461d7d KB |
461 | { |
462 | return extract_bit_field (bundle, 5+41*slotnum, 41); | |
463 | } | |
464 | ||
1777feb0 | 465 | /* Store an instruction in an instruction bundle. */ |
16461d7d | 466 | |
244bc108 | 467 | static void |
948f8e3d | 468 | replace_slotN_contents (gdb_byte *bundle, long long instr, int slotnum) |
16461d7d KB |
469 | { |
470 | replace_bit_field (bundle, instr, 5+41*slotnum, 41); | |
471 | } | |
472 | ||
939c61fa | 473 | static const enum instruction_type template_encoding_table[32][3] = |
16461d7d KB |
474 | { |
475 | { M, I, I }, /* 00 */ | |
476 | { M, I, I }, /* 01 */ | |
477 | { M, I, I }, /* 02 */ | |
478 | { M, I, I }, /* 03 */ | |
479 | { M, L, X }, /* 04 */ | |
480 | { M, L, X }, /* 05 */ | |
481 | { undefined, undefined, undefined }, /* 06 */ | |
482 | { undefined, undefined, undefined }, /* 07 */ | |
483 | { M, M, I }, /* 08 */ | |
484 | { M, M, I }, /* 09 */ | |
485 | { M, M, I }, /* 0A */ | |
486 | { M, M, I }, /* 0B */ | |
487 | { M, F, I }, /* 0C */ | |
488 | { M, F, I }, /* 0D */ | |
489 | { M, M, F }, /* 0E */ | |
490 | { M, M, F }, /* 0F */ | |
491 | { M, I, B }, /* 10 */ | |
492 | { M, I, B }, /* 11 */ | |
493 | { M, B, B }, /* 12 */ | |
494 | { M, B, B }, /* 13 */ | |
495 | { undefined, undefined, undefined }, /* 14 */ | |
496 | { undefined, undefined, undefined }, /* 15 */ | |
497 | { B, B, B }, /* 16 */ | |
498 | { B, B, B }, /* 17 */ | |
499 | { M, M, B }, /* 18 */ | |
500 | { M, M, B }, /* 19 */ | |
501 | { undefined, undefined, undefined }, /* 1A */ | |
502 | { undefined, undefined, undefined }, /* 1B */ | |
503 | { M, F, B }, /* 1C */ | |
504 | { M, F, B }, /* 1D */ | |
505 | { undefined, undefined, undefined }, /* 1E */ | |
506 | { undefined, undefined, undefined }, /* 1F */ | |
507 | }; | |
508 | ||
509 | /* Fetch and (partially) decode an instruction at ADDR and return the | |
510 | address of the next instruction to fetch. */ | |
511 | ||
512 | static CORE_ADDR | |
513 | fetch_instruction (CORE_ADDR addr, instruction_type *it, long long *instr) | |
514 | { | |
948f8e3d | 515 | gdb_byte bundle[BUNDLE_LEN]; |
16461d7d | 516 | int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER; |
fe978cb0 | 517 | long long templ; |
16461d7d KB |
518 | int val; |
519 | ||
c26e1c2b KB |
520 | /* Warn about slot numbers greater than 2. We used to generate |
521 | an error here on the assumption that the user entered an invalid | |
522 | address. But, sometimes GDB itself requests an invalid address. | |
523 | This can (easily) happen when execution stops in a function for | |
524 | which there are no symbols. The prologue scanner will attempt to | |
525 | find the beginning of the function - if the nearest symbol | |
526 | happens to not be aligned on a bundle boundary (16 bytes), the | |
527 | resulting starting address will cause GDB to think that the slot | |
528 | number is too large. | |
529 | ||
530 | So we warn about it and set the slot number to zero. It is | |
531 | not necessarily a fatal condition, particularly if debugging | |
532 | at the assembly language level. */ | |
16461d7d | 533 | if (slotnum > 2) |
c26e1c2b | 534 | { |
8a3fe4f8 AC |
535 | warning (_("Can't fetch instructions for slot numbers greater than 2.\n" |
536 | "Using slot 0 instead")); | |
c26e1c2b KB |
537 | slotnum = 0; |
538 | } | |
16461d7d KB |
539 | |
540 | addr &= ~0x0f; | |
541 | ||
542 | val = target_read_memory (addr, bundle, BUNDLE_LEN); | |
543 | ||
544 | if (val != 0) | |
545 | return 0; | |
546 | ||
547 | *instr = slotN_contents (bundle, slotnum); | |
fe978cb0 PA |
548 | templ = extract_bit_field (bundle, 0, 5); |
549 | *it = template_encoding_table[(int)templ][slotnum]; | |
16461d7d | 550 | |
64a5b29c | 551 | if (slotnum == 2 || (slotnum == 1 && *it == L)) |
16461d7d KB |
552 | addr += 16; |
553 | else | |
554 | addr += (slotnum + 1) * SLOT_MULTIPLIER; | |
555 | ||
556 | return addr; | |
557 | } | |
558 | ||
559 | /* There are 5 different break instructions (break.i, break.b, | |
560 | break.m, break.f, and break.x), but they all have the same | |
561 | encoding. (The five bit template in the low five bits of the | |
562 | instruction bundle distinguishes one from another.) | |
563 | ||
564 | The runtime architecture manual specifies that break instructions | |
565 | used for debugging purposes must have the upper two bits of the 21 | |
566 | bit immediate set to a 0 and a 1 respectively. A breakpoint | |
567 | instruction encodes the most significant bit of its 21 bit | |
568 | immediate at bit 36 of the 41 bit instruction. The penultimate msb | |
569 | is at bit 25 which leads to the pattern below. | |
570 | ||
571 | Originally, I had this set up to do, e.g, a "break.i 0x80000" But | |
572 | it turns out that 0x80000 was used as the syscall break in the early | |
573 | simulators. So I changed the pattern slightly to do "break.i 0x080001" | |
574 | instead. But that didn't work either (I later found out that this | |
575 | pattern was used by the simulator that I was using.) So I ended up | |
939c61fa JK |
576 | using the pattern seen below. |
577 | ||
578 | SHADOW_CONTENTS has byte-based addressing (PLACED_ADDRESS and SHADOW_LEN) | |
579 | while we need bit-based addressing as the instructions length is 41 bits and | |
580 | we must not modify/corrupt the adjacent slots in the same bundle. | |
581 | Fortunately we may store larger memory incl. the adjacent bits with the | |
582 | original memory content (not the possibly already stored breakpoints there). | |
583 | We need to be careful in ia64_memory_remove_breakpoint to always restore | |
584 | only the specific bits of this instruction ignoring any adjacent stored | |
585 | bits. | |
586 | ||
587 | We use the original addressing with the low nibble in the range <0..2> which | |
588 | gets incorrectly interpreted by generic non-ia64 breakpoint_restore_shadows | |
589 | as the direct byte offset of SHADOW_CONTENTS. We store whole BUNDLE_LEN | |
590 | bytes just without these two possibly skipped bytes to not to exceed to the | |
591 | next bundle. | |
592 | ||
593 | If we would like to store the whole bundle to SHADOW_CONTENTS we would have | |
594 | to store already the base address (`address & ~0x0f') into PLACED_ADDRESS. | |
595 | In such case there is no other place where to store | |
596 | SLOTNUM (`adress & 0x0f', value in the range <0..2>). We need to know | |
597 | SLOTNUM in ia64_memory_remove_breakpoint. | |
598 | ||
ca8b5032 JB |
599 | There is one special case where we need to be extra careful: |
600 | L-X instructions, which are instructions that occupy 2 slots | |
601 | (The L part is always in slot 1, and the X part is always in | |
602 | slot 2). We must refuse to insert breakpoints for an address | |
603 | that points at slot 2 of a bundle where an L-X instruction is | |
604 | present, since there is logically no instruction at that address. | |
605 | However, to make things more interesting, the opcode of L-X | |
606 | instructions is located in slot 2. This means that, to insert | |
607 | a breakpoint at an address that points to slot 1, we actually | |
608 | need to write the breakpoint in slot 2! Slot 1 is actually | |
609 | the extended operand, so writing the breakpoint there would not | |
610 | have the desired effect. Another side-effect of this issue | |
611 | is that we need to make sure that the shadow contents buffer | |
612 | does save byte 15 of our instruction bundle (this is the tail | |
613 | end of slot 2, which wouldn't be saved if we were to insert | |
614 | the breakpoint in slot 1). | |
615 | ||
939c61fa JK |
616 | ia64 16-byte bundle layout: |
617 | | 5 bits | slot 0 with 41 bits | slot 1 with 41 bits | slot 2 with 41 bits | | |
618 | ||
619 | The current addressing used by the code below: | |
620 | original PC placed_address placed_size required covered | |
621 | == bp_tgt->shadow_len reqd \subset covered | |
73a9714c JB |
622 | 0xABCDE0 0xABCDE0 0x10 <0x0...0x5> <0x0..0xF> |
623 | 0xABCDE1 0xABCDE1 0xF <0x5...0xA> <0x1..0xF> | |
939c61fa | 624 | 0xABCDE2 0xABCDE2 0xE <0xA...0xF> <0x2..0xF> |
ca8b5032 JB |
625 | |
626 | L-X instructions are treated a little specially, as explained above: | |
627 | 0xABCDE1 0xABCDE1 0xF <0xA...0xF> <0x1..0xF> | |
628 | ||
939c61fa JK |
629 | `objdump -d' and some other tools show a bit unjustified offsets: |
630 | original PC byte where starts the instruction objdump offset | |
631 | 0xABCDE0 0xABCDE0 0xABCDE0 | |
632 | 0xABCDE1 0xABCDE5 0xABCDE6 | |
633 | 0xABCDE2 0xABCDEA 0xABCDEC | |
634 | */ | |
16461d7d | 635 | |
aaab4dba | 636 | #define IA64_BREAKPOINT 0x00003333300LL |
16461d7d KB |
637 | |
638 | static int | |
ae4b2284 MD |
639 | ia64_memory_insert_breakpoint (struct gdbarch *gdbarch, |
640 | struct bp_target_info *bp_tgt) | |
16461d7d | 641 | { |
0d5ed153 | 642 | CORE_ADDR addr = bp_tgt->placed_address = bp_tgt->reqstd_address; |
939c61fa | 643 | gdb_byte bundle[BUNDLE_LEN]; |
73a9714c | 644 | int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER, shadow_slotnum; |
939c61fa | 645 | long long instr_breakpoint; |
16461d7d | 646 | int val; |
fe978cb0 | 647 | int templ; |
16461d7d KB |
648 | |
649 | if (slotnum > 2) | |
8a3fe4f8 | 650 | error (_("Can't insert breakpoint for slot numbers greater than 2.")); |
16461d7d KB |
651 | |
652 | addr &= ~0x0f; | |
653 | ||
b554e4bd JK |
654 | /* Enable the automatic memory restoration from breakpoints while |
655 | we read our instruction bundle for the purpose of SHADOW_CONTENTS. | |
656 | Otherwise, we could possibly store into the shadow parts of the adjacent | |
939c61fa JK |
657 | placed breakpoints. It is due to our SHADOW_CONTENTS overlapping the real |
658 | breakpoint instruction bits region. */ | |
cb85b21b TT |
659 | scoped_restore restore_memory_0 |
660 | = make_scoped_restore_show_memory_breakpoints (0); | |
16461d7d | 661 | val = target_read_memory (addr, bundle, BUNDLE_LEN); |
fbfaaae5 | 662 | if (val != 0) |
cb85b21b | 663 | return val; |
126fa72d | 664 | |
73a9714c JB |
665 | /* SHADOW_SLOTNUM saves the original slot number as expected by the caller |
666 | for addressing the SHADOW_CONTENTS placement. */ | |
667 | shadow_slotnum = slotnum; | |
668 | ||
ca8b5032 JB |
669 | /* Always cover the last byte of the bundle in case we are inserting |
670 | a breakpoint on an L-X instruction. */ | |
73a9714c JB |
671 | bp_tgt->shadow_len = BUNDLE_LEN - shadow_slotnum; |
672 | ||
fe978cb0 PA |
673 | templ = extract_bit_field (bundle, 0, 5); |
674 | if (template_encoding_table[templ][slotnum] == X) | |
73a9714c | 675 | { |
ca8b5032 JB |
676 | /* X unit types can only be used in slot 2, and are actually |
677 | part of a 2-slot L-X instruction. We cannot break at this | |
678 | address, as this is the second half of an instruction that | |
679 | lives in slot 1 of that bundle. */ | |
73a9714c JB |
680 | gdb_assert (slotnum == 2); |
681 | error (_("Can't insert breakpoint for non-existing slot X")); | |
682 | } | |
fe978cb0 | 683 | if (template_encoding_table[templ][slotnum] == L) |
73a9714c | 684 | { |
ca8b5032 JB |
685 | /* L unit types can only be used in slot 1. But the associated |
686 | opcode for that instruction is in slot 2, so bump the slot number | |
687 | accordingly. */ | |
73a9714c JB |
688 | gdb_assert (slotnum == 1); |
689 | slotnum = 2; | |
690 | } | |
939c61fa JK |
691 | |
692 | /* Store the whole bundle, except for the initial skipped bytes by the slot | |
693 | number interpreted as bytes offset in PLACED_ADDRESS. */ | |
1777feb0 MS |
694 | memcpy (bp_tgt->shadow_contents, bundle + shadow_slotnum, |
695 | bp_tgt->shadow_len); | |
939c61fa | 696 | |
b554e4bd JK |
697 | /* Re-read the same bundle as above except that, this time, read it in order |
698 | to compute the new bundle inside which we will be inserting the | |
699 | breakpoint. Therefore, disable the automatic memory restoration from | |
700 | breakpoints while we read our instruction bundle. Otherwise, the general | |
701 | restoration mechanism kicks in and we would possibly remove parts of the | |
702 | adjacent placed breakpoints. It is due to our SHADOW_CONTENTS overlapping | |
703 | the real breakpoint instruction bits region. */ | |
cb85b21b TT |
704 | scoped_restore restore_memory_1 |
705 | = make_scoped_restore_show_memory_breakpoints (1); | |
fbfaaae5 JK |
706 | val = target_read_memory (addr, bundle, BUNDLE_LEN); |
707 | if (val != 0) | |
cb85b21b | 708 | return val; |
b554e4bd | 709 | |
939c61fa JK |
710 | /* Breakpoints already present in the code will get deteacted and not get |
711 | reinserted by bp_loc_is_permanent. Multiple breakpoints at the same | |
712 | location cannot induce the internal error as they are optimized into | |
713 | a single instance by update_global_location_list. */ | |
714 | instr_breakpoint = slotN_contents (bundle, slotnum); | |
715 | if (instr_breakpoint == IA64_BREAKPOINT) | |
716 | internal_error (__FILE__, __LINE__, | |
717 | _("Address %s already contains a breakpoint."), | |
5af949e3 | 718 | paddress (gdbarch, bp_tgt->placed_address)); |
aaab4dba | 719 | replace_slotN_contents (bundle, IA64_BREAKPOINT, slotnum); |
939c61fa | 720 | |
73a9714c | 721 | val = target_write_memory (addr + shadow_slotnum, bundle + shadow_slotnum, |
fbfaaae5 | 722 | bp_tgt->shadow_len); |
16461d7d KB |
723 | |
724 | return val; | |
725 | } | |
726 | ||
727 | static int | |
ae4b2284 MD |
728 | ia64_memory_remove_breakpoint (struct gdbarch *gdbarch, |
729 | struct bp_target_info *bp_tgt) | |
16461d7d | 730 | { |
8181d85f | 731 | CORE_ADDR addr = bp_tgt->placed_address; |
939c61fa | 732 | gdb_byte bundle_mem[BUNDLE_LEN], bundle_saved[BUNDLE_LEN]; |
73a9714c | 733 | int slotnum = (addr & 0x0f) / SLOT_MULTIPLIER, shadow_slotnum; |
939c61fa | 734 | long long instr_breakpoint, instr_saved; |
16461d7d | 735 | int val; |
fe978cb0 | 736 | int templ; |
16461d7d KB |
737 | |
738 | addr &= ~0x0f; | |
739 | ||
1de34ab7 JB |
740 | /* Disable the automatic memory restoration from breakpoints while |
741 | we read our instruction bundle. Otherwise, the general restoration | |
939c61fa JK |
742 | mechanism kicks in and we would possibly remove parts of the adjacent |
743 | placed breakpoints. It is due to our SHADOW_CONTENTS overlapping the real | |
744 | breakpoint instruction bits region. */ | |
cb85b21b TT |
745 | scoped_restore restore_memory_1 |
746 | = make_scoped_restore_show_memory_breakpoints (1); | |
939c61fa | 747 | val = target_read_memory (addr, bundle_mem, BUNDLE_LEN); |
fbfaaae5 | 748 | if (val != 0) |
cb85b21b | 749 | return val; |
126fa72d | 750 | |
73a9714c JB |
751 | /* SHADOW_SLOTNUM saves the original slot number as expected by the caller |
752 | for addressing the SHADOW_CONTENTS placement. */ | |
753 | shadow_slotnum = slotnum; | |
754 | ||
fe978cb0 PA |
755 | templ = extract_bit_field (bundle_mem, 0, 5); |
756 | if (template_encoding_table[templ][slotnum] == X) | |
73a9714c | 757 | { |
ca8b5032 JB |
758 | /* X unit types can only be used in slot 2, and are actually |
759 | part of a 2-slot L-X instruction. We refuse to insert | |
760 | breakpoints at this address, so there should be no reason | |
761 | for us attempting to remove one there, except if the program's | |
762 | code somehow got modified in memory. */ | |
73a9714c | 763 | gdb_assert (slotnum == 2); |
ca8b5032 JB |
764 | warning (_("Cannot remove breakpoint at address %s from non-existing " |
765 | "X-type slot, memory has changed underneath"), | |
73a9714c | 766 | paddress (gdbarch, bp_tgt->placed_address)); |
73a9714c JB |
767 | return -1; |
768 | } | |
fe978cb0 | 769 | if (template_encoding_table[templ][slotnum] == L) |
73a9714c | 770 | { |
ca8b5032 JB |
771 | /* L unit types can only be used in slot 1. But the breakpoint |
772 | was actually saved using slot 2, so update the slot number | |
773 | accordingly. */ | |
73a9714c JB |
774 | gdb_assert (slotnum == 1); |
775 | slotnum = 2; | |
776 | } | |
939c61fa | 777 | |
cd6c3b4f | 778 | gdb_assert (bp_tgt->shadow_len == BUNDLE_LEN - shadow_slotnum); |
939c61fa JK |
779 | |
780 | instr_breakpoint = slotN_contents (bundle_mem, slotnum); | |
781 | if (instr_breakpoint != IA64_BREAKPOINT) | |
126fa72d | 782 | { |
939c61fa JK |
783 | warning (_("Cannot remove breakpoint at address %s, " |
784 | "no break instruction at such address."), | |
5af949e3 | 785 | paddress (gdbarch, bp_tgt->placed_address)); |
939c61fa | 786 | return -1; |
126fa72d PS |
787 | } |
788 | ||
939c61fa JK |
789 | /* Extract the original saved instruction from SLOTNUM normalizing its |
790 | bit-shift for INSTR_SAVED. */ | |
791 | memcpy (bundle_saved, bundle_mem, BUNDLE_LEN); | |
73a9714c JB |
792 | memcpy (bundle_saved + shadow_slotnum, bp_tgt->shadow_contents, |
793 | bp_tgt->shadow_len); | |
939c61fa JK |
794 | instr_saved = slotN_contents (bundle_saved, slotnum); |
795 | ||
ca8b5032 JB |
796 | /* In BUNDLE_MEM, be careful to modify only the bits belonging to SLOTNUM |
797 | and not any of the other ones that are stored in SHADOW_CONTENTS. */ | |
939c61fa | 798 | replace_slotN_contents (bundle_mem, instr_saved, slotnum); |
dd110abf | 799 | val = target_write_raw_memory (addr, bundle_mem, BUNDLE_LEN); |
16461d7d KB |
800 | |
801 | return val; | |
802 | } | |
803 | ||
cd6c3b4f YQ |
804 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ |
805 | ||
806 | static int | |
807 | ia64_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
808 | { | |
809 | /* A place holder of gdbarch method breakpoint_kind_from_pc. */ | |
810 | return 0; | |
811 | } | |
812 | ||
939c61fa JK |
813 | /* As gdbarch_breakpoint_from_pc ranges have byte granularity and ia64 |
814 | instruction slots ranges are bit-granular (41 bits) we have to provide an | |
815 | extended range as described for ia64_memory_insert_breakpoint. We also take | |
816 | care of preserving the `break' instruction 21-bit (or 62-bit) parameter to | |
817 | make a match for permanent breakpoints. */ | |
818 | ||
819 | static const gdb_byte * | |
1777feb0 MS |
820 | ia64_breakpoint_from_pc (struct gdbarch *gdbarch, |
821 | CORE_ADDR *pcptr, int *lenptr) | |
16461d7d | 822 | { |
939c61fa JK |
823 | CORE_ADDR addr = *pcptr; |
824 | static gdb_byte bundle[BUNDLE_LEN]; | |
73a9714c | 825 | int slotnum = (int) (*pcptr & 0x0f) / SLOT_MULTIPLIER, shadow_slotnum; |
939c61fa JK |
826 | long long instr_fetched; |
827 | int val; | |
fe978cb0 | 828 | int templ; |
939c61fa JK |
829 | |
830 | if (slotnum > 2) | |
831 | error (_("Can't insert breakpoint for slot numbers greater than 2.")); | |
832 | ||
833 | addr &= ~0x0f; | |
834 | ||
835 | /* Enable the automatic memory restoration from breakpoints while | |
836 | we read our instruction bundle to match bp_loc_is_permanent. */ | |
cb85b21b TT |
837 | { |
838 | scoped_restore restore_memory_0 | |
839 | = make_scoped_restore_show_memory_breakpoints (0); | |
840 | val = target_read_memory (addr, bundle, BUNDLE_LEN); | |
841 | } | |
939c61fa JK |
842 | |
843 | /* The memory might be unreachable. This can happen, for instance, | |
844 | when the user inserts a breakpoint at an invalid address. */ | |
845 | if (val != 0) | |
846 | return NULL; | |
847 | ||
73a9714c JB |
848 | /* SHADOW_SLOTNUM saves the original slot number as expected by the caller |
849 | for addressing the SHADOW_CONTENTS placement. */ | |
850 | shadow_slotnum = slotnum; | |
851 | ||
852 | /* Cover always the last byte of the bundle for the L-X slot case. */ | |
853 | *lenptr = BUNDLE_LEN - shadow_slotnum; | |
854 | ||
939c61fa JK |
855 | /* Check for L type instruction in slot 1, if present then bump up the slot |
856 | number to the slot 2. */ | |
fe978cb0 PA |
857 | templ = extract_bit_field (bundle, 0, 5); |
858 | if (template_encoding_table[templ][slotnum] == X) | |
73a9714c JB |
859 | { |
860 | gdb_assert (slotnum == 2); | |
861 | error (_("Can't insert breakpoint for non-existing slot X")); | |
862 | } | |
fe978cb0 | 863 | if (template_encoding_table[templ][slotnum] == L) |
73a9714c JB |
864 | { |
865 | gdb_assert (slotnum == 1); | |
866 | slotnum = 2; | |
867 | } | |
939c61fa JK |
868 | |
869 | /* A break instruction has its all its opcode bits cleared except for | |
870 | the parameter value. For L+X slot pair we are at the X slot (slot 2) so | |
871 | we should not touch the L slot - the upper 41 bits of the parameter. */ | |
872 | instr_fetched = slotN_contents (bundle, slotnum); | |
116e0965 | 873 | instr_fetched &= 0x1003ffffc0LL; |
939c61fa JK |
874 | replace_slotN_contents (bundle, instr_fetched, slotnum); |
875 | ||
73a9714c | 876 | return bundle + shadow_slotnum; |
16461d7d KB |
877 | } |
878 | ||
a78f21af | 879 | static CORE_ADDR |
c113ed0c | 880 | ia64_read_pc (readable_regcache *regcache) |
16461d7d | 881 | { |
61a1198a UW |
882 | ULONGEST psr_value, pc_value; |
883 | int slot_num; | |
884 | ||
c113ed0c YQ |
885 | regcache->cooked_read (IA64_PSR_REGNUM, &psr_value); |
886 | regcache->cooked_read (IA64_IP_REGNUM, &pc_value); | |
61a1198a | 887 | slot_num = (psr_value >> 41) & 3; |
16461d7d KB |
888 | |
889 | return pc_value | (slot_num * SLOT_MULTIPLIER); | |
890 | } | |
891 | ||
54a5c8d8 | 892 | void |
61a1198a | 893 | ia64_write_pc (struct regcache *regcache, CORE_ADDR new_pc) |
16461d7d KB |
894 | { |
895 | int slot_num = (int) (new_pc & 0xf) / SLOT_MULTIPLIER; | |
61a1198a UW |
896 | ULONGEST psr_value; |
897 | ||
898 | regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr_value); | |
16461d7d | 899 | psr_value &= ~(3LL << 41); |
61a1198a | 900 | psr_value |= (ULONGEST)(slot_num & 0x3) << 41; |
16461d7d KB |
901 | |
902 | new_pc &= ~0xfLL; | |
903 | ||
61a1198a UW |
904 | regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr_value); |
905 | regcache_cooked_write_unsigned (regcache, IA64_IP_REGNUM, new_pc); | |
16461d7d KB |
906 | } |
907 | ||
908 | #define IS_NaT_COLLECTION_ADDR(addr) ((((addr) >> 3) & 0x3f) == 0x3f) | |
909 | ||
910 | /* Returns the address of the slot that's NSLOTS slots away from | |
1777feb0 | 911 | the address ADDR. NSLOTS may be positive or negative. */ |
16461d7d KB |
912 | static CORE_ADDR |
913 | rse_address_add(CORE_ADDR addr, int nslots) | |
914 | { | |
915 | CORE_ADDR new_addr; | |
916 | int mandatory_nat_slots = nslots / 63; | |
917 | int direction = nslots < 0 ? -1 : 1; | |
918 | ||
919 | new_addr = addr + 8 * (nslots + mandatory_nat_slots); | |
920 | ||
921 | if ((new_addr >> 9) != ((addr + 8 * 64 * mandatory_nat_slots) >> 9)) | |
922 | new_addr += 8 * direction; | |
923 | ||
924 | if (IS_NaT_COLLECTION_ADDR(new_addr)) | |
925 | new_addr += 8 * direction; | |
926 | ||
927 | return new_addr; | |
928 | } | |
929 | ||
05d1431c | 930 | static enum register_status |
849d0ba8 | 931 | ia64_pseudo_register_read (struct gdbarch *gdbarch, readable_regcache *regcache, |
88d82102 | 932 | int regnum, gdb_byte *buf) |
16461d7d | 933 | { |
e17a4113 | 934 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
05d1431c | 935 | enum register_status status; |
e17a4113 | 936 | |
004d836a | 937 | if (regnum >= V32_REGNUM && regnum <= V127_REGNUM) |
244bc108 | 938 | { |
88d82102 | 939 | #ifdef HAVE_LIBUNWIND_IA64_H |
1777feb0 MS |
940 | /* First try and use the libunwind special reg accessor, |
941 | otherwise fallback to standard logic. */ | |
c5a27d9c | 942 | if (!libunwind_is_initialized () |
45ecac4b | 943 | || libunwind_get_reg_special (gdbarch, regcache, regnum, buf) != 0) |
88d82102 | 944 | #endif |
004d836a | 945 | { |
1777feb0 MS |
946 | /* The fallback position is to assume that r32-r127 are |
947 | found sequentially in memory starting at $bof. This | |
948 | isn't always true, but without libunwind, this is the | |
949 | best we can do. */ | |
05d1431c | 950 | enum register_status status; |
c5a27d9c JJ |
951 | ULONGEST cfm; |
952 | ULONGEST bsp; | |
953 | CORE_ADDR reg; | |
05d1431c | 954 | |
11f57cb6 | 955 | status = regcache->cooked_read (IA64_BSP_REGNUM, &bsp); |
05d1431c PA |
956 | if (status != REG_VALID) |
957 | return status; | |
958 | ||
11f57cb6 | 959 | status = regcache->cooked_read (IA64_CFM_REGNUM, &cfm); |
05d1431c PA |
960 | if (status != REG_VALID) |
961 | return status; | |
962 | ||
c5a27d9c | 963 | /* The bsp points at the end of the register frame so we |
1777feb0 MS |
964 | subtract the size of frame from it to get start of |
965 | register frame. */ | |
c5a27d9c JJ |
966 | bsp = rse_address_add (bsp, -(cfm & 0x7f)); |
967 | ||
968 | if ((cfm & 0x7f) > regnum - V32_REGNUM) | |
969 | { | |
970 | ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM)); | |
e17a4113 UW |
971 | reg = read_memory_integer ((CORE_ADDR)reg_addr, 8, byte_order); |
972 | store_unsigned_integer (buf, register_size (gdbarch, regnum), | |
973 | byte_order, reg); | |
c5a27d9c JJ |
974 | } |
975 | else | |
e17a4113 UW |
976 | store_unsigned_integer (buf, register_size (gdbarch, regnum), |
977 | byte_order, 0); | |
004d836a | 978 | } |
004d836a JJ |
979 | } |
980 | else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM) | |
981 | { | |
982 | ULONGEST unatN_val; | |
983 | ULONGEST unat; | |
11f57cb6 YQ |
984 | |
985 | status = regcache->cooked_read (IA64_UNAT_REGNUM, &unat); | |
05d1431c PA |
986 | if (status != REG_VALID) |
987 | return status; | |
004d836a | 988 | unatN_val = (unat & (1LL << (regnum - IA64_NAT0_REGNUM))) != 0; |
e17a4113 UW |
989 | store_unsigned_integer (buf, register_size (gdbarch, regnum), |
990 | byte_order, unatN_val); | |
004d836a JJ |
991 | } |
992 | else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM) | |
993 | { | |
994 | ULONGEST natN_val = 0; | |
995 | ULONGEST bsp; | |
996 | ULONGEST cfm; | |
997 | CORE_ADDR gr_addr = 0; | |
11f57cb6 YQ |
998 | |
999 | status = regcache->cooked_read (IA64_BSP_REGNUM, &bsp); | |
05d1431c PA |
1000 | if (status != REG_VALID) |
1001 | return status; | |
11f57cb6 YQ |
1002 | |
1003 | status = regcache->cooked_read (IA64_CFM_REGNUM, &cfm); | |
05d1431c PA |
1004 | if (status != REG_VALID) |
1005 | return status; | |
004d836a JJ |
1006 | |
1007 | /* The bsp points at the end of the register frame so we | |
1008 | subtract the size of frame from it to get start of register frame. */ | |
1009 | bsp = rse_address_add (bsp, -(cfm & 0x7f)); | |
1010 | ||
1011 | if ((cfm & 0x7f) > regnum - V32_REGNUM) | |
1012 | gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM)); | |
1013 | ||
1014 | if (gr_addr != 0) | |
1015 | { | |
1016 | /* Compute address of nat collection bits. */ | |
1017 | CORE_ADDR nat_addr = gr_addr | 0x1f8; | |
11f57cb6 | 1018 | ULONGEST nat_collection; |
004d836a JJ |
1019 | int nat_bit; |
1020 | /* If our nat collection address is bigger than bsp, we have to get | |
1021 | the nat collection from rnat. Otherwise, we fetch the nat | |
1022 | collection from the computed address. */ | |
1023 | if (nat_addr >= bsp) | |
11f57cb6 | 1024 | regcache->cooked_read (IA64_RNAT_REGNUM, &nat_collection); |
004d836a | 1025 | else |
e17a4113 | 1026 | nat_collection = read_memory_integer (nat_addr, 8, byte_order); |
004d836a JJ |
1027 | nat_bit = (gr_addr >> 3) & 0x3f; |
1028 | natN_val = (nat_collection >> nat_bit) & 1; | |
1029 | } | |
1030 | ||
e17a4113 UW |
1031 | store_unsigned_integer (buf, register_size (gdbarch, regnum), |
1032 | byte_order, natN_val); | |
244bc108 | 1033 | } |
004d836a JJ |
1034 | else if (regnum == VBOF_REGNUM) |
1035 | { | |
1036 | /* A virtual register frame start is provided for user convenience. | |
1777feb0 | 1037 | It can be calculated as the bsp - sof (sizeof frame). */ |
004d836a JJ |
1038 | ULONGEST bsp, vbsp; |
1039 | ULONGEST cfm; | |
11f57cb6 YQ |
1040 | |
1041 | status = regcache->cooked_read (IA64_BSP_REGNUM, &bsp); | |
05d1431c PA |
1042 | if (status != REG_VALID) |
1043 | return status; | |
11f57cb6 | 1044 | status = regcache->cooked_read (IA64_CFM_REGNUM, &cfm); |
05d1431c PA |
1045 | if (status != REG_VALID) |
1046 | return status; | |
004d836a JJ |
1047 | |
1048 | /* The bsp points at the end of the register frame so we | |
1049 | subtract the size of frame from it to get beginning of frame. */ | |
1050 | vbsp = rse_address_add (bsp, -(cfm & 0x7f)); | |
e17a4113 UW |
1051 | store_unsigned_integer (buf, register_size (gdbarch, regnum), |
1052 | byte_order, vbsp); | |
004d836a JJ |
1053 | } |
1054 | else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM) | |
1055 | { | |
1056 | ULONGEST pr; | |
1057 | ULONGEST cfm; | |
1058 | ULONGEST prN_val; | |
11f57cb6 YQ |
1059 | |
1060 | status = regcache->cooked_read (IA64_PR_REGNUM, &pr); | |
05d1431c PA |
1061 | if (status != REG_VALID) |
1062 | return status; | |
11f57cb6 | 1063 | status = regcache->cooked_read (IA64_CFM_REGNUM, &cfm); |
05d1431c PA |
1064 | if (status != REG_VALID) |
1065 | return status; | |
004d836a JJ |
1066 | |
1067 | if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM) | |
1068 | { | |
1069 | /* Fetch predicate register rename base from current frame | |
1777feb0 | 1070 | marker for this frame. */ |
004d836a JJ |
1071 | int rrb_pr = (cfm >> 32) & 0x3f; |
1072 | ||
1777feb0 | 1073 | /* Adjust the register number to account for register rotation. */ |
004d836a JJ |
1074 | regnum = VP16_REGNUM |
1075 | + ((regnum - VP16_REGNUM) + rrb_pr) % 48; | |
1076 | } | |
1077 | prN_val = (pr & (1LL << (regnum - VP0_REGNUM))) != 0; | |
e17a4113 UW |
1078 | store_unsigned_integer (buf, register_size (gdbarch, regnum), |
1079 | byte_order, prN_val); | |
004d836a JJ |
1080 | } |
1081 | else | |
088568da | 1082 | memset (buf, 0, register_size (gdbarch, regnum)); |
05d1431c PA |
1083 | |
1084 | return REG_VALID; | |
16461d7d KB |
1085 | } |
1086 | ||
004d836a JJ |
1087 | static void |
1088 | ia64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
88d82102 | 1089 | int regnum, const gdb_byte *buf) |
16461d7d | 1090 | { |
e17a4113 UW |
1091 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1092 | ||
004d836a | 1093 | if (regnum >= V32_REGNUM && regnum <= V127_REGNUM) |
244bc108 | 1094 | { |
004d836a JJ |
1095 | ULONGEST bsp; |
1096 | ULONGEST cfm; | |
004d836a JJ |
1097 | regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp); |
1098 | regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm); | |
1099 | ||
1100 | bsp = rse_address_add (bsp, -(cfm & 0x7f)); | |
1101 | ||
1102 | if ((cfm & 0x7f) > regnum - V32_REGNUM) | |
1103 | { | |
1104 | ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM)); | |
ce746418 | 1105 | write_memory (reg_addr, buf, 8); |
004d836a JJ |
1106 | } |
1107 | } | |
1108 | else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM) | |
1109 | { | |
1110 | ULONGEST unatN_val, unat, unatN_mask; | |
1111 | regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat); | |
1777feb0 MS |
1112 | unatN_val = extract_unsigned_integer (buf, register_size (gdbarch, |
1113 | regnum), | |
e17a4113 | 1114 | byte_order); |
004d836a JJ |
1115 | unatN_mask = (1LL << (regnum - IA64_NAT0_REGNUM)); |
1116 | if (unatN_val == 0) | |
1117 | unat &= ~unatN_mask; | |
1118 | else if (unatN_val == 1) | |
1119 | unat |= unatN_mask; | |
1120 | regcache_cooked_write_unsigned (regcache, IA64_UNAT_REGNUM, unat); | |
1121 | } | |
1122 | else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM) | |
1123 | { | |
1124 | ULONGEST natN_val; | |
1125 | ULONGEST bsp; | |
1126 | ULONGEST cfm; | |
1127 | CORE_ADDR gr_addr = 0; | |
1128 | regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp); | |
1129 | regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm); | |
1130 | ||
1131 | /* The bsp points at the end of the register frame so we | |
1132 | subtract the size of frame from it to get start of register frame. */ | |
1133 | bsp = rse_address_add (bsp, -(cfm & 0x7f)); | |
1134 | ||
1135 | if ((cfm & 0x7f) > regnum - V32_REGNUM) | |
1136 | gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM)); | |
1137 | ||
1777feb0 MS |
1138 | natN_val = extract_unsigned_integer (buf, register_size (gdbarch, |
1139 | regnum), | |
e17a4113 | 1140 | byte_order); |
004d836a JJ |
1141 | |
1142 | if (gr_addr != 0 && (natN_val == 0 || natN_val == 1)) | |
1143 | { | |
1144 | /* Compute address of nat collection bits. */ | |
1145 | CORE_ADDR nat_addr = gr_addr | 0x1f8; | |
1146 | CORE_ADDR nat_collection; | |
1147 | int natN_bit = (gr_addr >> 3) & 0x3f; | |
1148 | ULONGEST natN_mask = (1LL << natN_bit); | |
1149 | /* If our nat collection address is bigger than bsp, we have to get | |
1150 | the nat collection from rnat. Otherwise, we fetch the nat | |
1151 | collection from the computed address. */ | |
1152 | if (nat_addr >= bsp) | |
1153 | { | |
05d1431c PA |
1154 | regcache_cooked_read_unsigned (regcache, |
1155 | IA64_RNAT_REGNUM, | |
1777feb0 | 1156 | &nat_collection); |
004d836a JJ |
1157 | if (natN_val) |
1158 | nat_collection |= natN_mask; | |
1159 | else | |
1160 | nat_collection &= ~natN_mask; | |
1777feb0 MS |
1161 | regcache_cooked_write_unsigned (regcache, IA64_RNAT_REGNUM, |
1162 | nat_collection); | |
004d836a JJ |
1163 | } |
1164 | else | |
1165 | { | |
948f8e3d | 1166 | gdb_byte nat_buf[8]; |
e17a4113 | 1167 | nat_collection = read_memory_integer (nat_addr, 8, byte_order); |
004d836a JJ |
1168 | if (natN_val) |
1169 | nat_collection |= natN_mask; | |
1170 | else | |
1171 | nat_collection &= ~natN_mask; | |
e17a4113 UW |
1172 | store_unsigned_integer (nat_buf, register_size (gdbarch, regnum), |
1173 | byte_order, nat_collection); | |
004d836a JJ |
1174 | write_memory (nat_addr, nat_buf, 8); |
1175 | } | |
1176 | } | |
1177 | } | |
1178 | else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM) | |
1179 | { | |
1180 | ULONGEST pr; | |
1181 | ULONGEST cfm; | |
1182 | ULONGEST prN_val; | |
1183 | ULONGEST prN_mask; | |
1184 | ||
1185 | regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr); | |
1186 | regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm); | |
1187 | ||
1188 | if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM) | |
1189 | { | |
1190 | /* Fetch predicate register rename base from current frame | |
1777feb0 | 1191 | marker for this frame. */ |
004d836a JJ |
1192 | int rrb_pr = (cfm >> 32) & 0x3f; |
1193 | ||
1777feb0 | 1194 | /* Adjust the register number to account for register rotation. */ |
004d836a JJ |
1195 | regnum = VP16_REGNUM |
1196 | + ((regnum - VP16_REGNUM) + rrb_pr) % 48; | |
1197 | } | |
e17a4113 UW |
1198 | prN_val = extract_unsigned_integer (buf, register_size (gdbarch, regnum), |
1199 | byte_order); | |
004d836a JJ |
1200 | prN_mask = (1LL << (regnum - VP0_REGNUM)); |
1201 | if (prN_val == 0) | |
1202 | pr &= ~prN_mask; | |
1203 | else if (prN_val == 1) | |
1204 | pr |= prN_mask; | |
1205 | regcache_cooked_write_unsigned (regcache, IA64_PR_REGNUM, pr); | |
244bc108 | 1206 | } |
16461d7d KB |
1207 | } |
1208 | ||
004d836a JJ |
1209 | /* The ia64 needs to convert between various ieee floating-point formats |
1210 | and the special ia64 floating point register format. */ | |
1211 | ||
1212 | static int | |
0abe36f5 | 1213 | ia64_convert_register_p (struct gdbarch *gdbarch, int regno, struct type *type) |
004d836a | 1214 | { |
83acabca | 1215 | return (regno >= IA64_FR0_REGNUM && regno <= IA64_FR127_REGNUM |
88954b49 | 1216 | && TYPE_CODE (type) == TYPE_CODE_FLT |
27067745 | 1217 | && type != ia64_ext_type (gdbarch)); |
004d836a JJ |
1218 | } |
1219 | ||
8dccd430 | 1220 | static int |
004d836a | 1221 | ia64_register_to_value (struct frame_info *frame, int regnum, |
8dccd430 PA |
1222 | struct type *valtype, gdb_byte *out, |
1223 | int *optimizedp, int *unavailablep) | |
004d836a | 1224 | { |
27067745 | 1225 | struct gdbarch *gdbarch = get_frame_arch (frame); |
ae0d01d6 | 1226 | gdb_byte in[IA64_FP_REGISTER_SIZE]; |
8dccd430 PA |
1227 | |
1228 | /* Convert to TYPE. */ | |
1229 | if (!get_frame_register_bytes (frame, regnum, 0, | |
1230 | register_size (gdbarch, regnum), | |
1231 | in, optimizedp, unavailablep)) | |
1232 | return 0; | |
1233 | ||
3b2ca824 | 1234 | target_float_convert (in, ia64_ext_type (gdbarch), out, valtype); |
8dccd430 PA |
1235 | *optimizedp = *unavailablep = 0; |
1236 | return 1; | |
004d836a JJ |
1237 | } |
1238 | ||
1239 | static void | |
1240 | ia64_value_to_register (struct frame_info *frame, int regnum, | |
88d82102 | 1241 | struct type *valtype, const gdb_byte *in) |
004d836a | 1242 | { |
27067745 | 1243 | struct gdbarch *gdbarch = get_frame_arch (frame); |
ae0d01d6 | 1244 | gdb_byte out[IA64_FP_REGISTER_SIZE]; |
3b2ca824 | 1245 | target_float_convert (in, valtype, out, ia64_ext_type (gdbarch)); |
004d836a JJ |
1246 | put_frame_register (frame, regnum, out); |
1247 | } | |
1248 | ||
1249 | ||
58ab00f9 KB |
1250 | /* Limit the number of skipped non-prologue instructions since examining |
1251 | of the prologue is expensive. */ | |
5ea2bd7f | 1252 | static int max_skip_non_prologue_insns = 40; |
58ab00f9 KB |
1253 | |
1254 | /* Given PC representing the starting address of a function, and | |
1255 | LIM_PC which is the (sloppy) limit to which to scan when looking | |
1256 | for a prologue, attempt to further refine this limit by using | |
1257 | the line data in the symbol table. If successful, a better guess | |
1258 | on where the prologue ends is returned, otherwise the previous | |
1259 | value of lim_pc is returned. TRUST_LIMIT is a pointer to a flag | |
1260 | which will be set to indicate whether the returned limit may be | |
1261 | used with no further scanning in the event that the function is | |
1262 | frameless. */ | |
1263 | ||
634aa483 AC |
1264 | /* FIXME: cagney/2004-02-14: This function and logic have largely been |
1265 | superseded by skip_prologue_using_sal. */ | |
1266 | ||
58ab00f9 KB |
1267 | static CORE_ADDR |
1268 | refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc, int *trust_limit) | |
1269 | { | |
1270 | struct symtab_and_line prologue_sal; | |
1271 | CORE_ADDR start_pc = pc; | |
39312971 JB |
1272 | CORE_ADDR end_pc; |
1273 | ||
1274 | /* The prologue can not possibly go past the function end itself, | |
1275 | so we can already adjust LIM_PC accordingly. */ | |
1276 | if (find_pc_partial_function (pc, NULL, NULL, &end_pc) && end_pc < lim_pc) | |
1277 | lim_pc = end_pc; | |
58ab00f9 KB |
1278 | |
1279 | /* Start off not trusting the limit. */ | |
1280 | *trust_limit = 0; | |
1281 | ||
1282 | prologue_sal = find_pc_line (pc, 0); | |
1283 | if (prologue_sal.line != 0) | |
1284 | { | |
1285 | int i; | |
1286 | CORE_ADDR addr = prologue_sal.end; | |
1287 | ||
1288 | /* Handle the case in which compiler's optimizer/scheduler | |
1289 | has moved instructions into the prologue. We scan ahead | |
1290 | in the function looking for address ranges whose corresponding | |
1291 | line number is less than or equal to the first one that we | |
1292 | found for the function. (It can be less than when the | |
1293 | scheduler puts a body instruction before the first prologue | |
1294 | instruction.) */ | |
1295 | for (i = 2 * max_skip_non_prologue_insns; | |
1296 | i > 0 && (lim_pc == 0 || addr < lim_pc); | |
1297 | i--) | |
1298 | { | |
1299 | struct symtab_and_line sal; | |
1300 | ||
1301 | sal = find_pc_line (addr, 0); | |
1302 | if (sal.line == 0) | |
1303 | break; | |
1304 | if (sal.line <= prologue_sal.line | |
1305 | && sal.symtab == prologue_sal.symtab) | |
1306 | { | |
1307 | prologue_sal = sal; | |
1308 | } | |
1309 | addr = sal.end; | |
1310 | } | |
1311 | ||
1312 | if (lim_pc == 0 || prologue_sal.end < lim_pc) | |
1313 | { | |
1314 | lim_pc = prologue_sal.end; | |
1315 | if (start_pc == get_pc_function_start (lim_pc)) | |
1316 | *trust_limit = 1; | |
1317 | } | |
1318 | } | |
1319 | return lim_pc; | |
1320 | } | |
1321 | ||
16461d7d KB |
1322 | #define isScratch(_regnum_) ((_regnum_) == 2 || (_regnum_) == 3 \ |
1323 | || (8 <= (_regnum_) && (_regnum_) <= 11) \ | |
1324 | || (14 <= (_regnum_) && (_regnum_) <= 31)) | |
1325 | #define imm9(_instr_) \ | |
1326 | ( ((((_instr_) & 0x01000000000LL) ? -1 : 0) << 8) \ | |
1327 | | (((_instr_) & 0x00008000000LL) >> 20) \ | |
1328 | | (((_instr_) & 0x00000001fc0LL) >> 6)) | |
1329 | ||
004d836a JJ |
1330 | /* Allocate and initialize a frame cache. */ |
1331 | ||
1332 | static struct ia64_frame_cache * | |
1333 | ia64_alloc_frame_cache (void) | |
1334 | { | |
1335 | struct ia64_frame_cache *cache; | |
1336 | int i; | |
1337 | ||
1338 | cache = FRAME_OBSTACK_ZALLOC (struct ia64_frame_cache); | |
1339 | ||
1340 | /* Base address. */ | |
1341 | cache->base = 0; | |
1342 | cache->pc = 0; | |
1343 | cache->cfm = 0; | |
4afcc598 | 1344 | cache->prev_cfm = 0; |
004d836a JJ |
1345 | cache->sof = 0; |
1346 | cache->sol = 0; | |
1347 | cache->sor = 0; | |
1348 | cache->bsp = 0; | |
1349 | cache->fp_reg = 0; | |
1350 | cache->frameless = 1; | |
1351 | ||
1352 | for (i = 0; i < NUM_IA64_RAW_REGS; i++) | |
1353 | cache->saved_regs[i] = 0; | |
1354 | ||
1355 | return cache; | |
1356 | } | |
1357 | ||
16461d7d | 1358 | static CORE_ADDR |
15c1e57f JB |
1359 | examine_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, |
1360 | struct frame_info *this_frame, | |
1361 | struct ia64_frame_cache *cache) | |
16461d7d KB |
1362 | { |
1363 | CORE_ADDR next_pc; | |
1364 | CORE_ADDR last_prologue_pc = pc; | |
16461d7d KB |
1365 | instruction_type it; |
1366 | long long instr; | |
16461d7d KB |
1367 | int cfm_reg = 0; |
1368 | int ret_reg = 0; | |
1369 | int fp_reg = 0; | |
1370 | int unat_save_reg = 0; | |
1371 | int pr_save_reg = 0; | |
1372 | int mem_stack_frame_size = 0; | |
1373 | int spill_reg = 0; | |
1374 | CORE_ADDR spill_addr = 0; | |
0927a22b KB |
1375 | char instores[8]; |
1376 | char infpstores[8]; | |
5ea2bd7f | 1377 | char reg_contents[256]; |
58ab00f9 | 1378 | int trust_limit; |
004d836a JJ |
1379 | int frameless = 1; |
1380 | int i; | |
1381 | CORE_ADDR addr; | |
e362b510 | 1382 | gdb_byte buf[8]; |
004d836a | 1383 | CORE_ADDR bof, sor, sol, sof, cfm, rrb_gr; |
0927a22b KB |
1384 | |
1385 | memset (instores, 0, sizeof instores); | |
1386 | memset (infpstores, 0, sizeof infpstores); | |
5ea2bd7f | 1387 | memset (reg_contents, 0, sizeof reg_contents); |
16461d7d | 1388 | |
004d836a JJ |
1389 | if (cache->after_prologue != 0 |
1390 | && cache->after_prologue <= lim_pc) | |
1391 | return cache->after_prologue; | |
16461d7d | 1392 | |
58ab00f9 | 1393 | lim_pc = refine_prologue_limit (pc, lim_pc, &trust_limit); |
16461d7d | 1394 | next_pc = fetch_instruction (pc, &it, &instr); |
5ea2bd7f JJ |
1395 | |
1396 | /* We want to check if we have a recognizable function start before we | |
1397 | look ahead for a prologue. */ | |
16461d7d KB |
1398 | if (pc < lim_pc && next_pc |
1399 | && it == M && ((instr & 0x1ee0000003fLL) == 0x02c00000000LL)) | |
1400 | { | |
5ea2bd7f | 1401 | /* alloc - start of a regular function. */ |
16461d7d KB |
1402 | int sol = (int) ((instr & 0x00007f00000LL) >> 20); |
1403 | int sof = (int) ((instr & 0x000000fe000LL) >> 13); | |
16461d7d | 1404 | int rN = (int) ((instr & 0x00000001fc0LL) >> 6); |
004d836a JJ |
1405 | |
1406 | /* Verify that the current cfm matches what we think is the | |
1407 | function start. If we have somehow jumped within a function, | |
1408 | we do not want to interpret the prologue and calculate the | |
1777feb0 MS |
1409 | addresses of various registers such as the return address. |
1410 | We will instead treat the frame as frameless. */ | |
15c1e57f | 1411 | if (!this_frame || |
004d836a JJ |
1412 | (sof == (cache->cfm & 0x7f) && |
1413 | sol == ((cache->cfm >> 7) & 0x7f))) | |
1414 | frameless = 0; | |
1415 | ||
16461d7d KB |
1416 | cfm_reg = rN; |
1417 | last_prologue_pc = next_pc; | |
1418 | pc = next_pc; | |
1419 | } | |
1420 | else | |
58ab00f9 | 1421 | { |
5ea2bd7f JJ |
1422 | /* Look for a leaf routine. */ |
1423 | if (pc < lim_pc && next_pc | |
1424 | && (it == I || it == M) | |
1425 | && ((instr & 0x1ee00000000LL) == 0x10800000000LL)) | |
1426 | { | |
1427 | /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */ | |
1428 | int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13) | |
1429 | | ((instr & 0x001f8000000LL) >> 20) | |
1430 | | ((instr & 0x000000fe000LL) >> 13)); | |
1431 | int rM = (int) ((instr & 0x00007f00000LL) >> 20); | |
1432 | int rN = (int) ((instr & 0x00000001fc0LL) >> 6); | |
1433 | int qp = (int) (instr & 0x0000000003fLL); | |
1434 | if (qp == 0 && rN == 2 && imm == 0 && rM == 12 && fp_reg == 0) | |
1435 | { | |
1777feb0 | 1436 | /* mov r2, r12 - beginning of leaf routine. */ |
5ea2bd7f | 1437 | fp_reg = rN; |
5ea2bd7f JJ |
1438 | last_prologue_pc = next_pc; |
1439 | } | |
1440 | } | |
1441 | ||
1442 | /* If we don't recognize a regular function or leaf routine, we are | |
1443 | done. */ | |
1444 | if (!fp_reg) | |
1445 | { | |
1446 | pc = lim_pc; | |
1447 | if (trust_limit) | |
1448 | last_prologue_pc = lim_pc; | |
1449 | } | |
58ab00f9 | 1450 | } |
16461d7d KB |
1451 | |
1452 | /* Loop, looking for prologue instructions, keeping track of | |
1777feb0 | 1453 | where preserved registers were spilled. */ |
16461d7d KB |
1454 | while (pc < lim_pc) |
1455 | { | |
1456 | next_pc = fetch_instruction (pc, &it, &instr); | |
1457 | if (next_pc == 0) | |
1458 | break; | |
1459 | ||
594706e6 | 1460 | if (it == B && ((instr & 0x1e1f800003fLL) != 0x04000000000LL)) |
0927a22b | 1461 | { |
1777feb0 | 1462 | /* Exit loop upon hitting a non-nop branch instruction. */ |
102d615a JJ |
1463 | if (trust_limit) |
1464 | lim_pc = pc; | |
1465 | break; | |
1466 | } | |
1467 | else if (((instr & 0x3fLL) != 0LL) && | |
1468 | (frameless || ret_reg != 0)) | |
1469 | { | |
1470 | /* Exit loop upon hitting a predicated instruction if | |
1471 | we already have the return register or if we are frameless. */ | |
5ea2bd7f JJ |
1472 | if (trust_limit) |
1473 | lim_pc = pc; | |
0927a22b KB |
1474 | break; |
1475 | } | |
1476 | else if (it == I && ((instr & 0x1eff8000000LL) == 0x00188000000LL)) | |
16461d7d KB |
1477 | { |
1478 | /* Move from BR */ | |
1479 | int b2 = (int) ((instr & 0x0000000e000LL) >> 13); | |
1480 | int rN = (int) ((instr & 0x00000001fc0LL) >> 6); | |
1481 | int qp = (int) (instr & 0x0000000003f); | |
1482 | ||
1483 | if (qp == 0 && b2 == 0 && rN >= 32 && ret_reg == 0) | |
1484 | { | |
1485 | ret_reg = rN; | |
1486 | last_prologue_pc = next_pc; | |
1487 | } | |
1488 | } | |
1489 | else if ((it == I || it == M) | |
1490 | && ((instr & 0x1ee00000000LL) == 0x10800000000LL)) | |
1491 | { | |
1492 | /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */ | |
1493 | int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13) | |
1494 | | ((instr & 0x001f8000000LL) >> 20) | |
1495 | | ((instr & 0x000000fe000LL) >> 13)); | |
1496 | int rM = (int) ((instr & 0x00007f00000LL) >> 20); | |
1497 | int rN = (int) ((instr & 0x00000001fc0LL) >> 6); | |
1498 | int qp = (int) (instr & 0x0000000003fLL); | |
1499 | ||
1500 | if (qp == 0 && rN >= 32 && imm == 0 && rM == 12 && fp_reg == 0) | |
1501 | { | |
1502 | /* mov rN, r12 */ | |
1503 | fp_reg = rN; | |
1504 | last_prologue_pc = next_pc; | |
1505 | } | |
1506 | else if (qp == 0 && rN == 12 && rM == 12) | |
1507 | { | |
1508 | /* adds r12, -mem_stack_frame_size, r12 */ | |
1509 | mem_stack_frame_size -= imm; | |
1510 | last_prologue_pc = next_pc; | |
1511 | } | |
1512 | else if (qp == 0 && rN == 2 | |
1513 | && ((rM == fp_reg && fp_reg != 0) || rM == 12)) | |
1514 | { | |
004d836a | 1515 | CORE_ADDR saved_sp = 0; |
16461d7d KB |
1516 | /* adds r2, spilloffset, rFramePointer |
1517 | or | |
1518 | adds r2, spilloffset, r12 | |
1519 | ||
1520 | Get ready for stf.spill or st8.spill instructions. | |
1777feb0 | 1521 | The address to start spilling at is loaded into r2. |
16461d7d KB |
1522 | FIXME: Why r2? That's what gcc currently uses; it |
1523 | could well be different for other compilers. */ | |
1524 | ||
1777feb0 | 1525 | /* Hmm... whether or not this will work will depend on |
16461d7d KB |
1526 | where the pc is. If it's still early in the prologue |
1527 | this'll be wrong. FIXME */ | |
15c1e57f | 1528 | if (this_frame) |
8d49165d TT |
1529 | saved_sp = get_frame_register_unsigned (this_frame, |
1530 | sp_regnum); | |
004d836a | 1531 | spill_addr = saved_sp |
16461d7d KB |
1532 | + (rM == 12 ? 0 : mem_stack_frame_size) |
1533 | + imm; | |
1534 | spill_reg = rN; | |
1535 | last_prologue_pc = next_pc; | |
1536 | } | |
b7d038ae | 1537 | else if (qp == 0 && rM >= 32 && rM < 40 && !instores[rM-32] && |
5ea2bd7f JJ |
1538 | rN < 256 && imm == 0) |
1539 | { | |
1777feb0 | 1540 | /* mov rN, rM where rM is an input register. */ |
5ea2bd7f JJ |
1541 | reg_contents[rN] = rM; |
1542 | last_prologue_pc = next_pc; | |
1543 | } | |
1544 | else if (frameless && qp == 0 && rN == fp_reg && imm == 0 && | |
1545 | rM == 2) | |
1546 | { | |
1547 | /* mov r12, r2 */ | |
1548 | last_prologue_pc = next_pc; | |
1549 | break; | |
1550 | } | |
16461d7d KB |
1551 | } |
1552 | else if (it == M | |
1553 | && ( ((instr & 0x1efc0000000LL) == 0x0eec0000000LL) | |
1554 | || ((instr & 0x1ffc8000000LL) == 0x0cec0000000LL) )) | |
1555 | { | |
1556 | /* stf.spill [rN] = fM, imm9 | |
1557 | or | |
1558 | stf.spill [rN] = fM */ | |
1559 | ||
1560 | int imm = imm9(instr); | |
1561 | int rN = (int) ((instr & 0x00007f00000LL) >> 20); | |
1562 | int fM = (int) ((instr & 0x000000fe000LL) >> 13); | |
1563 | int qp = (int) (instr & 0x0000000003fLL); | |
1564 | if (qp == 0 && rN == spill_reg && spill_addr != 0 | |
1565 | && ((2 <= fM && fM <= 5) || (16 <= fM && fM <= 31))) | |
1566 | { | |
004d836a | 1567 | cache->saved_regs[IA64_FR0_REGNUM + fM] = spill_addr; |
16461d7d | 1568 | |
594706e6 | 1569 | if ((instr & 0x1efc0000000LL) == 0x0eec0000000LL) |
16461d7d KB |
1570 | spill_addr += imm; |
1571 | else | |
1777feb0 | 1572 | spill_addr = 0; /* last one; must be done. */ |
16461d7d KB |
1573 | last_prologue_pc = next_pc; |
1574 | } | |
1575 | } | |
1576 | else if ((it == M && ((instr & 0x1eff8000000LL) == 0x02110000000LL)) | |
1577 | || (it == I && ((instr & 0x1eff8000000LL) == 0x00050000000LL)) ) | |
1578 | { | |
1579 | /* mov.m rN = arM | |
1580 | or | |
1581 | mov.i rN = arM */ | |
1582 | ||
1583 | int arM = (int) ((instr & 0x00007f00000LL) >> 20); | |
1584 | int rN = (int) ((instr & 0x00000001fc0LL) >> 6); | |
1585 | int qp = (int) (instr & 0x0000000003fLL); | |
1586 | if (qp == 0 && isScratch (rN) && arM == 36 /* ar.unat */) | |
1587 | { | |
1588 | /* We have something like "mov.m r3 = ar.unat". Remember the | |
1777feb0 | 1589 | r3 (or whatever) and watch for a store of this register... */ |
16461d7d KB |
1590 | unat_save_reg = rN; |
1591 | last_prologue_pc = next_pc; | |
1592 | } | |
1593 | } | |
1594 | else if (it == I && ((instr & 0x1eff8000000LL) == 0x00198000000LL)) | |
1595 | { | |
1596 | /* mov rN = pr */ | |
1597 | int rN = (int) ((instr & 0x00000001fc0LL) >> 6); | |
1598 | int qp = (int) (instr & 0x0000000003fLL); | |
1599 | if (qp == 0 && isScratch (rN)) | |
1600 | { | |
1601 | pr_save_reg = rN; | |
1602 | last_prologue_pc = next_pc; | |
1603 | } | |
1604 | } | |
1605 | else if (it == M | |
1606 | && ( ((instr & 0x1ffc8000000LL) == 0x08cc0000000LL) | |
1607 | || ((instr & 0x1efc0000000LL) == 0x0acc0000000LL))) | |
1608 | { | |
1609 | /* st8 [rN] = rM | |
1610 | or | |
1611 | st8 [rN] = rM, imm9 */ | |
1612 | int rN = (int) ((instr & 0x00007f00000LL) >> 20); | |
1613 | int rM = (int) ((instr & 0x000000fe000LL) >> 13); | |
1614 | int qp = (int) (instr & 0x0000000003fLL); | |
5ea2bd7f | 1615 | int indirect = rM < 256 ? reg_contents[rM] : 0; |
16461d7d KB |
1616 | if (qp == 0 && rN == spill_reg && spill_addr != 0 |
1617 | && (rM == unat_save_reg || rM == pr_save_reg)) | |
1618 | { | |
1619 | /* We've found a spill of either the UNAT register or the PR | |
1620 | register. (Well, not exactly; what we've actually found is | |
1621 | a spill of the register that UNAT or PR was moved to). | |
1777feb0 | 1622 | Record that fact and move on... */ |
16461d7d KB |
1623 | if (rM == unat_save_reg) |
1624 | { | |
1777feb0 | 1625 | /* Track UNAT register. */ |
004d836a | 1626 | cache->saved_regs[IA64_UNAT_REGNUM] = spill_addr; |
16461d7d KB |
1627 | unat_save_reg = 0; |
1628 | } | |
1629 | else | |
1630 | { | |
1777feb0 | 1631 | /* Track PR register. */ |
004d836a | 1632 | cache->saved_regs[IA64_PR_REGNUM] = spill_addr; |
16461d7d KB |
1633 | pr_save_reg = 0; |
1634 | } | |
1635 | if ((instr & 0x1efc0000000LL) == 0x0acc0000000LL) | |
1636 | /* st8 [rN] = rM, imm9 */ | |
1637 | spill_addr += imm9(instr); | |
1638 | else | |
1777feb0 | 1639 | spill_addr = 0; /* Must be done spilling. */ |
16461d7d KB |
1640 | last_prologue_pc = next_pc; |
1641 | } | |
0927a22b KB |
1642 | else if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32]) |
1643 | { | |
1777feb0 | 1644 | /* Allow up to one store of each input register. */ |
0927a22b KB |
1645 | instores[rM-32] = 1; |
1646 | last_prologue_pc = next_pc; | |
1647 | } | |
5ea2bd7f JJ |
1648 | else if (qp == 0 && 32 <= indirect && indirect < 40 && |
1649 | !instores[indirect-32]) | |
1650 | { | |
1651 | /* Allow an indirect store of an input register. */ | |
1652 | instores[indirect-32] = 1; | |
1653 | last_prologue_pc = next_pc; | |
1654 | } | |
0927a22b KB |
1655 | } |
1656 | else if (it == M && ((instr & 0x1ff08000000LL) == 0x08c00000000LL)) | |
1657 | { | |
1658 | /* One of | |
1659 | st1 [rN] = rM | |
1660 | st2 [rN] = rM | |
1661 | st4 [rN] = rM | |
1662 | st8 [rN] = rM | |
1663 | Note that the st8 case is handled in the clause above. | |
1664 | ||
1777feb0 MS |
1665 | Advance over stores of input registers. One store per input |
1666 | register is permitted. */ | |
0927a22b KB |
1667 | int rM = (int) ((instr & 0x000000fe000LL) >> 13); |
1668 | int qp = (int) (instr & 0x0000000003fLL); | |
5ea2bd7f | 1669 | int indirect = rM < 256 ? reg_contents[rM] : 0; |
0927a22b KB |
1670 | if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32]) |
1671 | { | |
1672 | instores[rM-32] = 1; | |
1673 | last_prologue_pc = next_pc; | |
1674 | } | |
5ea2bd7f JJ |
1675 | else if (qp == 0 && 32 <= indirect && indirect < 40 && |
1676 | !instores[indirect-32]) | |
1677 | { | |
1678 | /* Allow an indirect store of an input register. */ | |
1679 | instores[indirect-32] = 1; | |
1680 | last_prologue_pc = next_pc; | |
1681 | } | |
0927a22b KB |
1682 | } |
1683 | else if (it == M && ((instr & 0x1ff88000000LL) == 0x0cc80000000LL)) | |
1684 | { | |
1685 | /* Either | |
1686 | stfs [rN] = fM | |
1687 | or | |
1688 | stfd [rN] = fM | |
1689 | ||
1690 | Advance over stores of floating point input registers. Again | |
1777feb0 | 1691 | one store per register is permitted. */ |
0927a22b KB |
1692 | int fM = (int) ((instr & 0x000000fe000LL) >> 13); |
1693 | int qp = (int) (instr & 0x0000000003fLL); | |
1694 | if (qp == 0 && 8 <= fM && fM < 16 && !infpstores[fM - 8]) | |
1695 | { | |
1696 | infpstores[fM-8] = 1; | |
1697 | last_prologue_pc = next_pc; | |
1698 | } | |
16461d7d KB |
1699 | } |
1700 | else if (it == M | |
1701 | && ( ((instr & 0x1ffc8000000LL) == 0x08ec0000000LL) | |
1702 | || ((instr & 0x1efc0000000LL) == 0x0aec0000000LL))) | |
1703 | { | |
1704 | /* st8.spill [rN] = rM | |
1705 | or | |
1706 | st8.spill [rN] = rM, imm9 */ | |
1707 | int rN = (int) ((instr & 0x00007f00000LL) >> 20); | |
1708 | int rM = (int) ((instr & 0x000000fe000LL) >> 13); | |
1709 | int qp = (int) (instr & 0x0000000003fLL); | |
1710 | if (qp == 0 && rN == spill_reg && 4 <= rM && rM <= 7) | |
1711 | { | |
1712 | /* We've found a spill of one of the preserved general purpose | |
1713 | regs. Record the spill address and advance the spill | |
1777feb0 | 1714 | register if appropriate. */ |
004d836a | 1715 | cache->saved_regs[IA64_GR0_REGNUM + rM] = spill_addr; |
16461d7d KB |
1716 | if ((instr & 0x1efc0000000LL) == 0x0aec0000000LL) |
1717 | /* st8.spill [rN] = rM, imm9 */ | |
1718 | spill_addr += imm9(instr); | |
1719 | else | |
1777feb0 | 1720 | spill_addr = 0; /* Done spilling. */ |
16461d7d KB |
1721 | last_prologue_pc = next_pc; |
1722 | } | |
1723 | } | |
16461d7d KB |
1724 | |
1725 | pc = next_pc; | |
1726 | } | |
1727 | ||
15c1e57f JB |
1728 | /* If not frameless and we aren't called by skip_prologue, then we need |
1729 | to calculate registers for the previous frame which will be needed | |
1730 | later. */ | |
16461d7d | 1731 | |
15c1e57f | 1732 | if (!frameless && this_frame) |
da50a4b7 | 1733 | { |
e17a4113 UW |
1734 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1735 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1736 | ||
004d836a JJ |
1737 | /* Extract the size of the rotating portion of the stack |
1738 | frame and the register rename base from the current | |
1777feb0 | 1739 | frame marker. */ |
004d836a JJ |
1740 | cfm = cache->cfm; |
1741 | sor = cache->sor; | |
1742 | sof = cache->sof; | |
1743 | sol = cache->sol; | |
1744 | rrb_gr = (cfm >> 18) & 0x7f; | |
1745 | ||
1746 | /* Find the bof (beginning of frame). */ | |
1747 | bof = rse_address_add (cache->bsp, -sof); | |
1748 | ||
1749 | for (i = 0, addr = bof; | |
1750 | i < sof; | |
1751 | i++, addr += 8) | |
1752 | { | |
1753 | if (IS_NaT_COLLECTION_ADDR (addr)) | |
1754 | { | |
1755 | addr += 8; | |
1756 | } | |
1757 | if (i+32 == cfm_reg) | |
1758 | cache->saved_regs[IA64_CFM_REGNUM] = addr; | |
1759 | if (i+32 == ret_reg) | |
1760 | cache->saved_regs[IA64_VRAP_REGNUM] = addr; | |
1761 | if (i+32 == fp_reg) | |
1762 | cache->saved_regs[IA64_VFP_REGNUM] = addr; | |
1763 | } | |
16461d7d | 1764 | |
1777feb0 | 1765 | /* For the previous argument registers we require the previous bof. |
004d836a | 1766 | If we can't find the previous cfm, then we can do nothing. */ |
4afcc598 | 1767 | cfm = 0; |
004d836a JJ |
1768 | if (cache->saved_regs[IA64_CFM_REGNUM] != 0) |
1769 | { | |
e17a4113 UW |
1770 | cfm = read_memory_integer (cache->saved_regs[IA64_CFM_REGNUM], |
1771 | 8, byte_order); | |
4afcc598 JJ |
1772 | } |
1773 | else if (cfm_reg != 0) | |
1774 | { | |
15c1e57f | 1775 | get_frame_register (this_frame, cfm_reg, buf); |
e17a4113 | 1776 | cfm = extract_unsigned_integer (buf, 8, byte_order); |
4afcc598 JJ |
1777 | } |
1778 | cache->prev_cfm = cfm; | |
1779 | ||
1780 | if (cfm != 0) | |
1781 | { | |
004d836a JJ |
1782 | sor = ((cfm >> 14) & 0xf) * 8; |
1783 | sof = (cfm & 0x7f); | |
1784 | sol = (cfm >> 7) & 0x7f; | |
1785 | rrb_gr = (cfm >> 18) & 0x7f; | |
1786 | ||
15c1e57f JB |
1787 | /* The previous bof only requires subtraction of the sol (size of |
1788 | locals) due to the overlap between output and input of | |
1789 | subsequent frames. */ | |
004d836a JJ |
1790 | bof = rse_address_add (bof, -sol); |
1791 | ||
1792 | for (i = 0, addr = bof; | |
1793 | i < sof; | |
1794 | i++, addr += 8) | |
1795 | { | |
1796 | if (IS_NaT_COLLECTION_ADDR (addr)) | |
1797 | { | |
1798 | addr += 8; | |
1799 | } | |
1800 | if (i < sor) | |
1777feb0 MS |
1801 | cache->saved_regs[IA64_GR32_REGNUM |
1802 | + ((i + (sor - rrb_gr)) % sor)] | |
004d836a JJ |
1803 | = addr; |
1804 | else | |
1805 | cache->saved_regs[IA64_GR32_REGNUM + i] = addr; | |
1806 | } | |
1807 | ||
1808 | } | |
1809 | } | |
1810 | ||
5ea2bd7f JJ |
1811 | /* Try and trust the lim_pc value whenever possible. */ |
1812 | if (trust_limit && lim_pc >= last_prologue_pc) | |
004d836a JJ |
1813 | last_prologue_pc = lim_pc; |
1814 | ||
1815 | cache->frameless = frameless; | |
1816 | cache->after_prologue = last_prologue_pc; | |
1817 | cache->mem_stack_frame_size = mem_stack_frame_size; | |
1818 | cache->fp_reg = fp_reg; | |
5ea2bd7f | 1819 | |
16461d7d KB |
1820 | return last_prologue_pc; |
1821 | } | |
1822 | ||
1823 | CORE_ADDR | |
6093d2eb | 1824 | ia64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
16461d7d | 1825 | { |
004d836a JJ |
1826 | struct ia64_frame_cache cache; |
1827 | cache.base = 0; | |
1828 | cache.after_prologue = 0; | |
1829 | cache.cfm = 0; | |
1830 | cache.bsp = 0; | |
1831 | ||
1777feb0 MS |
1832 | /* Call examine_prologue with - as third argument since we don't |
1833 | have a next frame pointer to send. */ | |
004d836a | 1834 | return examine_prologue (pc, pc+1024, 0, &cache); |
16461d7d KB |
1835 | } |
1836 | ||
004d836a JJ |
1837 | |
1838 | /* Normal frames. */ | |
1839 | ||
1840 | static struct ia64_frame_cache * | |
15c1e57f | 1841 | ia64_frame_cache (struct frame_info *this_frame, void **this_cache) |
16461d7d | 1842 | { |
e17a4113 UW |
1843 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1844 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
004d836a | 1845 | struct ia64_frame_cache *cache; |
e362b510 | 1846 | gdb_byte buf[8]; |
870f88f7 | 1847 | CORE_ADDR cfm; |
16461d7d | 1848 | |
004d836a | 1849 | if (*this_cache) |
9a3c8263 | 1850 | return (struct ia64_frame_cache *) *this_cache; |
16461d7d | 1851 | |
004d836a JJ |
1852 | cache = ia64_alloc_frame_cache (); |
1853 | *this_cache = cache; | |
16461d7d | 1854 | |
15c1e57f | 1855 | get_frame_register (this_frame, sp_regnum, buf); |
e17a4113 | 1856 | cache->saved_sp = extract_unsigned_integer (buf, 8, byte_order); |
16461d7d | 1857 | |
004d836a JJ |
1858 | /* We always want the bsp to point to the end of frame. |
1859 | This way, we can always get the beginning of frame (bof) | |
1860 | by subtracting frame size. */ | |
15c1e57f | 1861 | get_frame_register (this_frame, IA64_BSP_REGNUM, buf); |
e17a4113 | 1862 | cache->bsp = extract_unsigned_integer (buf, 8, byte_order); |
004d836a | 1863 | |
15c1e57f | 1864 | get_frame_register (this_frame, IA64_PSR_REGNUM, buf); |
004d836a | 1865 | |
15c1e57f | 1866 | get_frame_register (this_frame, IA64_CFM_REGNUM, buf); |
e17a4113 | 1867 | cfm = extract_unsigned_integer (buf, 8, byte_order); |
004d836a JJ |
1868 | |
1869 | cache->sof = (cfm & 0x7f); | |
1870 | cache->sol = (cfm >> 7) & 0x7f; | |
1871 | cache->sor = ((cfm >> 14) & 0xf) * 8; | |
1872 | ||
1873 | cache->cfm = cfm; | |
1874 | ||
15c1e57f | 1875 | cache->pc = get_frame_func (this_frame); |
004d836a JJ |
1876 | |
1877 | if (cache->pc != 0) | |
15c1e57f | 1878 | examine_prologue (cache->pc, get_frame_pc (this_frame), this_frame, cache); |
004d836a JJ |
1879 | |
1880 | cache->base = cache->saved_sp + cache->mem_stack_frame_size; | |
1881 | ||
1882 | return cache; | |
16461d7d KB |
1883 | } |
1884 | ||
a78f21af | 1885 | static void |
15c1e57f | 1886 | ia64_frame_this_id (struct frame_info *this_frame, void **this_cache, |
004d836a | 1887 | struct frame_id *this_id) |
16461d7d | 1888 | { |
5af949e3 | 1889 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
004d836a | 1890 | struct ia64_frame_cache *cache = |
15c1e57f | 1891 | ia64_frame_cache (this_frame, this_cache); |
16461d7d | 1892 | |
c5a27d9c | 1893 | /* If outermost frame, mark with null frame id. */ |
005ca36a | 1894 | if (cache->base != 0) |
c5a27d9c | 1895 | (*this_id) = frame_id_build_special (cache->base, cache->pc, cache->bsp); |
4afcc598 JJ |
1896 | if (gdbarch_debug >= 1) |
1897 | fprintf_unfiltered (gdb_stdlog, | |
1777feb0 MS |
1898 | "regular frame id: code %s, stack %s, " |
1899 | "special %s, this_frame %s\n", | |
5af949e3 UW |
1900 | paddress (gdbarch, this_id->code_addr), |
1901 | paddress (gdbarch, this_id->stack_addr), | |
1902 | paddress (gdbarch, cache->bsp), | |
dfc3cd0e | 1903 | host_address_to_string (this_frame)); |
004d836a | 1904 | } |
244bc108 | 1905 | |
15c1e57f JB |
1906 | static struct value * |
1907 | ia64_frame_prev_register (struct frame_info *this_frame, void **this_cache, | |
1908 | int regnum) | |
004d836a | 1909 | { |
15c1e57f | 1910 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
e17a4113 | 1911 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
15c1e57f | 1912 | struct ia64_frame_cache *cache = ia64_frame_cache (this_frame, this_cache); |
e362b510 | 1913 | gdb_byte buf[8]; |
004d836a JJ |
1914 | |
1915 | gdb_assert (regnum >= 0); | |
244bc108 | 1916 | |
004d836a | 1917 | if (!target_has_registers) |
8a3fe4f8 | 1918 | error (_("No registers.")); |
244bc108 | 1919 | |
088568da | 1920 | if (regnum == gdbarch_sp_regnum (gdbarch)) |
15c1e57f JB |
1921 | return frame_unwind_got_constant (this_frame, regnum, cache->base); |
1922 | ||
16461d7d KB |
1923 | else if (regnum == IA64_BSP_REGNUM) |
1924 | { | |
15c1e57f JB |
1925 | struct value *val; |
1926 | CORE_ADDR prev_cfm, bsp, prev_bsp; | |
1927 | ||
1928 | /* We want to calculate the previous bsp as the end of the previous | |
1929 | register stack frame. This corresponds to what the hardware bsp | |
1930 | register will be if we pop the frame back which is why we might | |
1931 | have been called. We know the beginning of the current frame is | |
1932 | cache->bsp - cache->sof. This value in the previous frame points | |
1933 | to the start of the output registers. We can calculate the end of | |
1934 | that frame by adding the size of output: | |
1935 | (sof (size of frame) - sol (size of locals)). */ | |
1936 | val = ia64_frame_prev_register (this_frame, this_cache, IA64_CFM_REGNUM); | |
e17a4113 UW |
1937 | prev_cfm = extract_unsigned_integer (value_contents_all (val), |
1938 | 8, byte_order); | |
004d836a | 1939 | bsp = rse_address_add (cache->bsp, -(cache->sof)); |
15c1e57f JB |
1940 | prev_bsp = |
1941 | rse_address_add (bsp, (prev_cfm & 0x7f) - ((prev_cfm >> 7) & 0x7f)); | |
004d836a | 1942 | |
15c1e57f | 1943 | return frame_unwind_got_constant (this_frame, regnum, prev_bsp); |
004d836a | 1944 | } |
15c1e57f | 1945 | |
004d836a JJ |
1946 | else if (regnum == IA64_CFM_REGNUM) |
1947 | { | |
4afcc598 JJ |
1948 | CORE_ADDR addr = cache->saved_regs[IA64_CFM_REGNUM]; |
1949 | ||
1950 | if (addr != 0) | |
15c1e57f JB |
1951 | return frame_unwind_got_memory (this_frame, regnum, addr); |
1952 | ||
1953 | if (cache->prev_cfm) | |
1954 | return frame_unwind_got_constant (this_frame, regnum, cache->prev_cfm); | |
1955 | ||
1956 | if (cache->frameless) | |
1957 | return frame_unwind_got_register (this_frame, IA64_PFS_REGNUM, | |
1958 | IA64_PFS_REGNUM); | |
1959 | return frame_unwind_got_register (this_frame, regnum, 0); | |
16461d7d | 1960 | } |
15c1e57f | 1961 | |
16461d7d KB |
1962 | else if (regnum == IA64_VFP_REGNUM) |
1963 | { | |
1964 | /* If the function in question uses an automatic register (r32-r127) | |
1965 | for the frame pointer, it'll be found by ia64_find_saved_register() | |
1966 | above. If the function lacks one of these frame pointers, we can | |
004d836a | 1967 | still provide a value since we know the size of the frame. */ |
15c1e57f | 1968 | return frame_unwind_got_constant (this_frame, regnum, cache->base); |
16461d7d | 1969 | } |
15c1e57f | 1970 | |
004d836a | 1971 | else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM) |
16461d7d | 1972 | { |
15c1e57f JB |
1973 | struct value *pr_val; |
1974 | ULONGEST prN; | |
1975 | ||
1976 | pr_val = ia64_frame_prev_register (this_frame, this_cache, | |
1977 | IA64_PR_REGNUM); | |
004d836a | 1978 | if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM) |
3a854e23 KB |
1979 | { |
1980 | /* Fetch predicate register rename base from current frame | |
004d836a JJ |
1981 | marker for this frame. */ |
1982 | int rrb_pr = (cache->cfm >> 32) & 0x3f; | |
3a854e23 | 1983 | |
004d836a | 1984 | /* Adjust the register number to account for register rotation. */ |
15c1e57f | 1985 | regnum = VP16_REGNUM + ((regnum - VP16_REGNUM) + rrb_pr) % 48; |
3a854e23 | 1986 | } |
15c1e57f JB |
1987 | prN = extract_bit_field (value_contents_all (pr_val), |
1988 | regnum - VP0_REGNUM, 1); | |
1989 | return frame_unwind_got_constant (this_frame, regnum, prN); | |
16461d7d | 1990 | } |
15c1e57f | 1991 | |
16461d7d KB |
1992 | else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM) |
1993 | { | |
15c1e57f JB |
1994 | struct value *unat_val; |
1995 | ULONGEST unatN; | |
1996 | unat_val = ia64_frame_prev_register (this_frame, this_cache, | |
1997 | IA64_UNAT_REGNUM); | |
1998 | unatN = extract_bit_field (value_contents_all (unat_val), | |
1999 | regnum - IA64_NAT0_REGNUM, 1); | |
2000 | return frame_unwind_got_constant (this_frame, regnum, unatN); | |
16461d7d | 2001 | } |
15c1e57f | 2002 | |
16461d7d KB |
2003 | else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM) |
2004 | { | |
2005 | int natval = 0; | |
2006 | /* Find address of general register corresponding to nat bit we're | |
004d836a JJ |
2007 | interested in. */ |
2008 | CORE_ADDR gr_addr; | |
244bc108 | 2009 | |
15c1e57f JB |
2010 | gr_addr = cache->saved_regs[regnum - IA64_NAT0_REGNUM + IA64_GR0_REGNUM]; |
2011 | ||
004d836a | 2012 | if (gr_addr != 0) |
244bc108 | 2013 | { |
004d836a | 2014 | /* Compute address of nat collection bits. */ |
16461d7d | 2015 | CORE_ADDR nat_addr = gr_addr | 0x1f8; |
004d836a | 2016 | CORE_ADDR bsp; |
16461d7d KB |
2017 | CORE_ADDR nat_collection; |
2018 | int nat_bit; | |
15c1e57f | 2019 | |
16461d7d KB |
2020 | /* If our nat collection address is bigger than bsp, we have to get |
2021 | the nat collection from rnat. Otherwise, we fetch the nat | |
004d836a | 2022 | collection from the computed address. */ |
15c1e57f | 2023 | get_frame_register (this_frame, IA64_BSP_REGNUM, buf); |
e17a4113 | 2024 | bsp = extract_unsigned_integer (buf, 8, byte_order); |
16461d7d | 2025 | if (nat_addr >= bsp) |
004d836a | 2026 | { |
15c1e57f | 2027 | get_frame_register (this_frame, IA64_RNAT_REGNUM, buf); |
e17a4113 | 2028 | nat_collection = extract_unsigned_integer (buf, 8, byte_order); |
004d836a | 2029 | } |
16461d7d | 2030 | else |
e17a4113 | 2031 | nat_collection = read_memory_integer (nat_addr, 8, byte_order); |
16461d7d KB |
2032 | nat_bit = (gr_addr >> 3) & 0x3f; |
2033 | natval = (nat_collection >> nat_bit) & 1; | |
2034 | } | |
004d836a | 2035 | |
15c1e57f | 2036 | return frame_unwind_got_constant (this_frame, regnum, natval); |
244bc108 | 2037 | } |
15c1e57f | 2038 | |
244bc108 KB |
2039 | else if (regnum == IA64_IP_REGNUM) |
2040 | { | |
004d836a | 2041 | CORE_ADDR pc = 0; |
4afcc598 | 2042 | CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM]; |
004d836a | 2043 | |
4afcc598 | 2044 | if (addr != 0) |
15c1e57f JB |
2045 | { |
2046 | read_memory (addr, buf, register_size (gdbarch, IA64_IP_REGNUM)); | |
e17a4113 | 2047 | pc = extract_unsigned_integer (buf, 8, byte_order); |
15c1e57f | 2048 | } |
4afcc598 | 2049 | else if (cache->frameless) |
004d836a | 2050 | { |
15c1e57f | 2051 | get_frame_register (this_frame, IA64_BR0_REGNUM, buf); |
e17a4113 | 2052 | pc = extract_unsigned_integer (buf, 8, byte_order); |
244bc108 | 2053 | } |
004d836a | 2054 | pc &= ~0xf; |
15c1e57f | 2055 | return frame_unwind_got_constant (this_frame, regnum, pc); |
244bc108 | 2056 | } |
15c1e57f | 2057 | |
004d836a | 2058 | else if (regnum == IA64_PSR_REGNUM) |
244bc108 | 2059 | { |
15c1e57f JB |
2060 | /* We don't know how to get the complete previous PSR, but we need it |
2061 | for the slot information when we unwind the pc (pc is formed of IP | |
2062 | register plus slot information from PSR). To get the previous | |
2063 | slot information, we mask it off the return address. */ | |
004d836a | 2064 | ULONGEST slot_num = 0; |
15c1e57f | 2065 | CORE_ADDR pc = 0; |
004d836a | 2066 | CORE_ADDR psr = 0; |
4afcc598 | 2067 | CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM]; |
004d836a | 2068 | |
15c1e57f | 2069 | get_frame_register (this_frame, IA64_PSR_REGNUM, buf); |
e17a4113 | 2070 | psr = extract_unsigned_integer (buf, 8, byte_order); |
004d836a | 2071 | |
4afcc598 | 2072 | if (addr != 0) |
244bc108 | 2073 | { |
088568da | 2074 | read_memory (addr, buf, register_size (gdbarch, IA64_IP_REGNUM)); |
e17a4113 | 2075 | pc = extract_unsigned_integer (buf, 8, byte_order); |
244bc108 | 2076 | } |
4afcc598 | 2077 | else if (cache->frameless) |
004d836a | 2078 | { |
15c1e57f | 2079 | get_frame_register (this_frame, IA64_BR0_REGNUM, buf); |
e17a4113 | 2080 | pc = extract_unsigned_integer (buf, 8, byte_order); |
004d836a JJ |
2081 | } |
2082 | psr &= ~(3LL << 41); | |
2083 | slot_num = pc & 0x3LL; | |
2084 | psr |= (CORE_ADDR)slot_num << 41; | |
15c1e57f | 2085 | return frame_unwind_got_constant (this_frame, regnum, psr); |
004d836a | 2086 | } |
15c1e57f | 2087 | |
4afcc598 JJ |
2088 | else if (regnum == IA64_BR0_REGNUM) |
2089 | { | |
4afcc598 | 2090 | CORE_ADDR addr = cache->saved_regs[IA64_BR0_REGNUM]; |
15c1e57f | 2091 | |
4afcc598 | 2092 | if (addr != 0) |
15c1e57f JB |
2093 | return frame_unwind_got_memory (this_frame, regnum, addr); |
2094 | ||
2095 | return frame_unwind_got_constant (this_frame, regnum, 0); | |
4afcc598 | 2096 | } |
15c1e57f JB |
2097 | |
2098 | else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM) | |
2099 | || (regnum >= V32_REGNUM && regnum <= V127_REGNUM)) | |
004d836a JJ |
2100 | { |
2101 | CORE_ADDR addr = 0; | |
15c1e57f | 2102 | |
004d836a JJ |
2103 | if (regnum >= V32_REGNUM) |
2104 | regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM); | |
2105 | addr = cache->saved_regs[regnum]; | |
244bc108 | 2106 | if (addr != 0) |
15c1e57f JB |
2107 | return frame_unwind_got_memory (this_frame, regnum, addr); |
2108 | ||
2109 | if (cache->frameless) | |
244bc108 | 2110 | { |
15c1e57f JB |
2111 | struct value *reg_val; |
2112 | CORE_ADDR prev_cfm, prev_bsp, prev_bof; | |
2113 | ||
2114 | /* FIXME: brobecker/2008-05-01: Doesn't this seem redundant | |
2115 | with the same code above? */ | |
004d836a JJ |
2116 | if (regnum >= V32_REGNUM) |
2117 | regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM); | |
15c1e57f JB |
2118 | reg_val = ia64_frame_prev_register (this_frame, this_cache, |
2119 | IA64_CFM_REGNUM); | |
2120 | prev_cfm = extract_unsigned_integer (value_contents_all (reg_val), | |
e17a4113 | 2121 | 8, byte_order); |
15c1e57f JB |
2122 | reg_val = ia64_frame_prev_register (this_frame, this_cache, |
2123 | IA64_BSP_REGNUM); | |
2124 | prev_bsp = extract_unsigned_integer (value_contents_all (reg_val), | |
e17a4113 | 2125 | 8, byte_order); |
004d836a JJ |
2126 | prev_bof = rse_address_add (prev_bsp, -(prev_cfm & 0x7f)); |
2127 | ||
2128 | addr = rse_address_add (prev_bof, (regnum - IA64_GR32_REGNUM)); | |
15c1e57f | 2129 | return frame_unwind_got_memory (this_frame, regnum, addr); |
244bc108 | 2130 | } |
15c1e57f JB |
2131 | |
2132 | return frame_unwind_got_constant (this_frame, regnum, 0); | |
16461d7d | 2133 | } |
15c1e57f JB |
2134 | |
2135 | else /* All other registers. */ | |
16461d7d | 2136 | { |
004d836a | 2137 | CORE_ADDR addr = 0; |
15c1e57f | 2138 | |
3a854e23 KB |
2139 | if (IA64_FR32_REGNUM <= regnum && regnum <= IA64_FR127_REGNUM) |
2140 | { | |
2141 | /* Fetch floating point register rename base from current | |
004d836a JJ |
2142 | frame marker for this frame. */ |
2143 | int rrb_fr = (cache->cfm >> 25) & 0x7f; | |
3a854e23 KB |
2144 | |
2145 | /* Adjust the floating point register number to account for | |
004d836a | 2146 | register rotation. */ |
3a854e23 KB |
2147 | regnum = IA64_FR32_REGNUM |
2148 | + ((regnum - IA64_FR32_REGNUM) + rrb_fr) % 96; | |
2149 | } | |
2150 | ||
004d836a JJ |
2151 | /* If we have stored a memory address, access the register. */ |
2152 | addr = cache->saved_regs[regnum]; | |
2153 | if (addr != 0) | |
15c1e57f | 2154 | return frame_unwind_got_memory (this_frame, regnum, addr); |
004d836a JJ |
2155 | /* Otherwise, punt and get the current value of the register. */ |
2156 | else | |
15c1e57f | 2157 | return frame_unwind_got_register (this_frame, regnum, regnum); |
16461d7d | 2158 | } |
16461d7d | 2159 | } |
004d836a JJ |
2160 | |
2161 | static const struct frame_unwind ia64_frame_unwind = | |
2162 | { | |
2163 | NORMAL_FRAME, | |
8fbca658 | 2164 | default_frame_unwind_stop_reason, |
004d836a | 2165 | &ia64_frame_this_id, |
15c1e57f JB |
2166 | &ia64_frame_prev_register, |
2167 | NULL, | |
2168 | default_frame_sniffer | |
004d836a JJ |
2169 | }; |
2170 | ||
004d836a JJ |
2171 | /* Signal trampolines. */ |
2172 | ||
2173 | static void | |
15c1e57f | 2174 | ia64_sigtramp_frame_init_saved_regs (struct frame_info *this_frame, |
2685572f | 2175 | struct ia64_frame_cache *cache) |
004d836a | 2176 | { |
e17a4113 UW |
2177 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2178 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2685572f UW |
2179 | |
2180 | if (tdep->sigcontext_register_address) | |
004d836a JJ |
2181 | { |
2182 | int regno; | |
2183 | ||
1777feb0 MS |
2184 | cache->saved_regs[IA64_VRAP_REGNUM] |
2185 | = tdep->sigcontext_register_address (gdbarch, cache->base, | |
2186 | IA64_IP_REGNUM); | |
2187 | cache->saved_regs[IA64_CFM_REGNUM] | |
2188 | = tdep->sigcontext_register_address (gdbarch, cache->base, | |
2189 | IA64_CFM_REGNUM); | |
2190 | cache->saved_regs[IA64_PSR_REGNUM] | |
2191 | = tdep->sigcontext_register_address (gdbarch, cache->base, | |
2192 | IA64_PSR_REGNUM); | |
2193 | cache->saved_regs[IA64_BSP_REGNUM] | |
2194 | = tdep->sigcontext_register_address (gdbarch, cache->base, | |
2195 | IA64_BSP_REGNUM); | |
2196 | cache->saved_regs[IA64_RNAT_REGNUM] | |
2197 | = tdep->sigcontext_register_address (gdbarch, cache->base, | |
2198 | IA64_RNAT_REGNUM); | |
2199 | cache->saved_regs[IA64_CCV_REGNUM] | |
2200 | = tdep->sigcontext_register_address (gdbarch, cache->base, | |
2201 | IA64_CCV_REGNUM); | |
2202 | cache->saved_regs[IA64_UNAT_REGNUM] | |
2203 | = tdep->sigcontext_register_address (gdbarch, cache->base, | |
2204 | IA64_UNAT_REGNUM); | |
2205 | cache->saved_regs[IA64_FPSR_REGNUM] | |
2206 | = tdep->sigcontext_register_address (gdbarch, cache->base, | |
2207 | IA64_FPSR_REGNUM); | |
2208 | cache->saved_regs[IA64_PFS_REGNUM] | |
2209 | = tdep->sigcontext_register_address (gdbarch, cache->base, | |
2210 | IA64_PFS_REGNUM); | |
2211 | cache->saved_regs[IA64_LC_REGNUM] | |
2212 | = tdep->sigcontext_register_address (gdbarch, cache->base, | |
2213 | IA64_LC_REGNUM); | |
2214 | ||
004d836a | 2215 | for (regno = IA64_GR1_REGNUM; regno <= IA64_GR31_REGNUM; regno++) |
4afcc598 | 2216 | cache->saved_regs[regno] = |
e17a4113 | 2217 | tdep->sigcontext_register_address (gdbarch, cache->base, regno); |
004d836a JJ |
2218 | for (regno = IA64_BR0_REGNUM; regno <= IA64_BR7_REGNUM; regno++) |
2219 | cache->saved_regs[regno] = | |
e17a4113 | 2220 | tdep->sigcontext_register_address (gdbarch, cache->base, regno); |
932644f0 | 2221 | for (regno = IA64_FR2_REGNUM; regno <= IA64_FR31_REGNUM; regno++) |
004d836a | 2222 | cache->saved_regs[regno] = |
e17a4113 | 2223 | tdep->sigcontext_register_address (gdbarch, cache->base, regno); |
004d836a JJ |
2224 | } |
2225 | } | |
2226 | ||
2227 | static struct ia64_frame_cache * | |
15c1e57f | 2228 | ia64_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) |
004d836a | 2229 | { |
e17a4113 UW |
2230 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2231 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
004d836a | 2232 | struct ia64_frame_cache *cache; |
e362b510 | 2233 | gdb_byte buf[8]; |
004d836a JJ |
2234 | |
2235 | if (*this_cache) | |
9a3c8263 | 2236 | return (struct ia64_frame_cache *) *this_cache; |
004d836a JJ |
2237 | |
2238 | cache = ia64_alloc_frame_cache (); | |
2239 | ||
15c1e57f | 2240 | get_frame_register (this_frame, sp_regnum, buf); |
4afcc598 JJ |
2241 | /* Note that frame size is hard-coded below. We cannot calculate it |
2242 | via prologue examination. */ | |
e17a4113 | 2243 | cache->base = extract_unsigned_integer (buf, 8, byte_order) + 16; |
4afcc598 | 2244 | |
15c1e57f | 2245 | get_frame_register (this_frame, IA64_BSP_REGNUM, buf); |
e17a4113 | 2246 | cache->bsp = extract_unsigned_integer (buf, 8, byte_order); |
4afcc598 | 2247 | |
15c1e57f | 2248 | get_frame_register (this_frame, IA64_CFM_REGNUM, buf); |
e17a4113 | 2249 | cache->cfm = extract_unsigned_integer (buf, 8, byte_order); |
4afcc598 | 2250 | cache->sof = cache->cfm & 0x7f; |
004d836a | 2251 | |
15c1e57f | 2252 | ia64_sigtramp_frame_init_saved_regs (this_frame, cache); |
004d836a JJ |
2253 | |
2254 | *this_cache = cache; | |
2255 | return cache; | |
2256 | } | |
2257 | ||
2258 | static void | |
15c1e57f JB |
2259 | ia64_sigtramp_frame_this_id (struct frame_info *this_frame, |
2260 | void **this_cache, struct frame_id *this_id) | |
004d836a | 2261 | { |
5af949e3 | 2262 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
004d836a | 2263 | struct ia64_frame_cache *cache = |
15c1e57f | 2264 | ia64_sigtramp_frame_cache (this_frame, this_cache); |
004d836a | 2265 | |
15c1e57f JB |
2266 | (*this_id) = frame_id_build_special (cache->base, |
2267 | get_frame_pc (this_frame), | |
2268 | cache->bsp); | |
4afcc598 JJ |
2269 | if (gdbarch_debug >= 1) |
2270 | fprintf_unfiltered (gdb_stdlog, | |
1777feb0 MS |
2271 | "sigtramp frame id: code %s, stack %s, " |
2272 | "special %s, this_frame %s\n", | |
5af949e3 UW |
2273 | paddress (gdbarch, this_id->code_addr), |
2274 | paddress (gdbarch, this_id->stack_addr), | |
2275 | paddress (gdbarch, cache->bsp), | |
dfc3cd0e | 2276 | host_address_to_string (this_frame)); |
004d836a JJ |
2277 | } |
2278 | ||
15c1e57f JB |
2279 | static struct value * |
2280 | ia64_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
2281 | void **this_cache, int regnum) | |
004d836a | 2282 | { |
4afcc598 | 2283 | struct ia64_frame_cache *cache = |
15c1e57f | 2284 | ia64_sigtramp_frame_cache (this_frame, this_cache); |
4afcc598 JJ |
2285 | |
2286 | gdb_assert (regnum >= 0); | |
2287 | ||
2288 | if (!target_has_registers) | |
8a3fe4f8 | 2289 | error (_("No registers.")); |
4afcc598 | 2290 | |
4afcc598 JJ |
2291 | if (regnum == IA64_IP_REGNUM) |
2292 | { | |
2293 | CORE_ADDR pc = 0; | |
2294 | CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM]; | |
2295 | ||
2296 | if (addr != 0) | |
2297 | { | |
5c99fcf8 AH |
2298 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2299 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
2300 | pc = read_memory_unsigned_integer (addr, 8, byte_order); | |
4afcc598 JJ |
2301 | } |
2302 | pc &= ~0xf; | |
15c1e57f | 2303 | return frame_unwind_got_constant (this_frame, regnum, pc); |
4afcc598 | 2304 | } |
15c1e57f JB |
2305 | |
2306 | else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM) | |
2307 | || (regnum >= V32_REGNUM && regnum <= V127_REGNUM)) | |
4afcc598 JJ |
2308 | { |
2309 | CORE_ADDR addr = 0; | |
15c1e57f | 2310 | |
4afcc598 JJ |
2311 | if (regnum >= V32_REGNUM) |
2312 | regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM); | |
2313 | addr = cache->saved_regs[regnum]; | |
2314 | if (addr != 0) | |
15c1e57f JB |
2315 | return frame_unwind_got_memory (this_frame, regnum, addr); |
2316 | ||
2317 | return frame_unwind_got_constant (this_frame, regnum, 0); | |
4afcc598 | 2318 | } |
15c1e57f JB |
2319 | |
2320 | else /* All other registers not listed above. */ | |
4afcc598 | 2321 | { |
4afcc598 | 2322 | CORE_ADDR addr = cache->saved_regs[regnum]; |
15c1e57f | 2323 | |
4afcc598 | 2324 | if (addr != 0) |
15c1e57f | 2325 | return frame_unwind_got_memory (this_frame, regnum, addr); |
004d836a | 2326 | |
15c1e57f JB |
2327 | return frame_unwind_got_constant (this_frame, regnum, 0); |
2328 | } | |
004d836a JJ |
2329 | } |
2330 | ||
15c1e57f JB |
2331 | static int |
2332 | ia64_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
2333 | struct frame_info *this_frame, | |
2334 | void **this_cache) | |
004d836a | 2335 | { |
15c1e57f | 2336 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
74174d2e UW |
2337 | if (tdep->pc_in_sigtramp) |
2338 | { | |
15c1e57f | 2339 | CORE_ADDR pc = get_frame_pc (this_frame); |
004d836a | 2340 | |
74174d2e | 2341 | if (tdep->pc_in_sigtramp (pc)) |
15c1e57f | 2342 | return 1; |
74174d2e | 2343 | } |
004d836a | 2344 | |
15c1e57f | 2345 | return 0; |
004d836a | 2346 | } |
15c1e57f JB |
2347 | |
2348 | static const struct frame_unwind ia64_sigtramp_frame_unwind = | |
2349 | { | |
2350 | SIGTRAMP_FRAME, | |
8fbca658 | 2351 | default_frame_unwind_stop_reason, |
15c1e57f JB |
2352 | ia64_sigtramp_frame_this_id, |
2353 | ia64_sigtramp_frame_prev_register, | |
2354 | NULL, | |
2355 | ia64_sigtramp_frame_sniffer | |
2356 | }; | |
2357 | ||
004d836a JJ |
2358 | \f |
2359 | ||
2360 | static CORE_ADDR | |
15c1e57f | 2361 | ia64_frame_base_address (struct frame_info *this_frame, void **this_cache) |
004d836a | 2362 | { |
15c1e57f | 2363 | struct ia64_frame_cache *cache = ia64_frame_cache (this_frame, this_cache); |
004d836a JJ |
2364 | |
2365 | return cache->base; | |
2366 | } | |
2367 | ||
2368 | static const struct frame_base ia64_frame_base = | |
2369 | { | |
2370 | &ia64_frame_unwind, | |
2371 | ia64_frame_base_address, | |
2372 | ia64_frame_base_address, | |
2373 | ia64_frame_base_address | |
2374 | }; | |
16461d7d | 2375 | |
968d1cb4 JJ |
2376 | #ifdef HAVE_LIBUNWIND_IA64_H |
2377 | ||
2378 | struct ia64_unwind_table_entry | |
2379 | { | |
2380 | unw_word_t start_offset; | |
2381 | unw_word_t end_offset; | |
2382 | unw_word_t info_offset; | |
2383 | }; | |
2384 | ||
2385 | static __inline__ uint64_t | |
2386 | ia64_rse_slot_num (uint64_t addr) | |
2387 | { | |
2388 | return (addr >> 3) & 0x3f; | |
2389 | } | |
2390 | ||
2391 | /* Skip over a designated number of registers in the backing | |
2392 | store, remembering every 64th position is for NAT. */ | |
2393 | static __inline__ uint64_t | |
2394 | ia64_rse_skip_regs (uint64_t addr, long num_regs) | |
2395 | { | |
2396 | long delta = ia64_rse_slot_num(addr) + num_regs; | |
2397 | ||
2398 | if (num_regs < 0) | |
2399 | delta -= 0x3e; | |
2400 | return addr + ((num_regs + delta/0x3f) << 3); | |
2401 | } | |
2402 | ||
05e7c244 JK |
2403 | /* Gdb ia64-libunwind-tdep callback function to convert from an ia64 gdb |
2404 | register number to a libunwind register number. */ | |
968d1cb4 JJ |
2405 | static int |
2406 | ia64_gdb2uw_regnum (int regnum) | |
2407 | { | |
2408 | if (regnum == sp_regnum) | |
2409 | return UNW_IA64_SP; | |
2410 | else if (regnum == IA64_BSP_REGNUM) | |
2411 | return UNW_IA64_BSP; | |
2412 | else if ((unsigned) (regnum - IA64_GR0_REGNUM) < 128) | |
2413 | return UNW_IA64_GR + (regnum - IA64_GR0_REGNUM); | |
2414 | else if ((unsigned) (regnum - V32_REGNUM) < 95) | |
2415 | return UNW_IA64_GR + 32 + (regnum - V32_REGNUM); | |
2416 | else if ((unsigned) (regnum - IA64_FR0_REGNUM) < 128) | |
2417 | return UNW_IA64_FR + (regnum - IA64_FR0_REGNUM); | |
2418 | else if ((unsigned) (regnum - IA64_PR0_REGNUM) < 64) | |
2419 | return -1; | |
2420 | else if ((unsigned) (regnum - IA64_BR0_REGNUM) < 8) | |
2421 | return UNW_IA64_BR + (regnum - IA64_BR0_REGNUM); | |
2422 | else if (regnum == IA64_PR_REGNUM) | |
2423 | return UNW_IA64_PR; | |
2424 | else if (regnum == IA64_IP_REGNUM) | |
2425 | return UNW_REG_IP; | |
2426 | else if (regnum == IA64_CFM_REGNUM) | |
2427 | return UNW_IA64_CFM; | |
2428 | else if ((unsigned) (regnum - IA64_AR0_REGNUM) < 128) | |
2429 | return UNW_IA64_AR + (regnum - IA64_AR0_REGNUM); | |
2430 | else if ((unsigned) (regnum - IA64_NAT0_REGNUM) < 128) | |
2431 | return UNW_IA64_NAT + (regnum - IA64_NAT0_REGNUM); | |
2432 | else | |
2433 | return -1; | |
2434 | } | |
2435 | ||
05e7c244 JK |
2436 | /* Gdb ia64-libunwind-tdep callback function to convert from a libunwind |
2437 | register number to a ia64 gdb register number. */ | |
968d1cb4 JJ |
2438 | static int |
2439 | ia64_uw2gdb_regnum (int uw_regnum) | |
2440 | { | |
2441 | if (uw_regnum == UNW_IA64_SP) | |
2442 | return sp_regnum; | |
2443 | else if (uw_regnum == UNW_IA64_BSP) | |
2444 | return IA64_BSP_REGNUM; | |
2445 | else if ((unsigned) (uw_regnum - UNW_IA64_GR) < 32) | |
2446 | return IA64_GR0_REGNUM + (uw_regnum - UNW_IA64_GR); | |
2447 | else if ((unsigned) (uw_regnum - UNW_IA64_GR) < 128) | |
2448 | return V32_REGNUM + (uw_regnum - (IA64_GR0_REGNUM + 32)); | |
2449 | else if ((unsigned) (uw_regnum - UNW_IA64_FR) < 128) | |
2450 | return IA64_FR0_REGNUM + (uw_regnum - UNW_IA64_FR); | |
2451 | else if ((unsigned) (uw_regnum - UNW_IA64_BR) < 8) | |
2452 | return IA64_BR0_REGNUM + (uw_regnum - UNW_IA64_BR); | |
2453 | else if (uw_regnum == UNW_IA64_PR) | |
2454 | return IA64_PR_REGNUM; | |
2455 | else if (uw_regnum == UNW_REG_IP) | |
2456 | return IA64_IP_REGNUM; | |
2457 | else if (uw_regnum == UNW_IA64_CFM) | |
2458 | return IA64_CFM_REGNUM; | |
2459 | else if ((unsigned) (uw_regnum - UNW_IA64_AR) < 128) | |
2460 | return IA64_AR0_REGNUM + (uw_regnum - UNW_IA64_AR); | |
2461 | else if ((unsigned) (uw_regnum - UNW_IA64_NAT) < 128) | |
2462 | return IA64_NAT0_REGNUM + (uw_regnum - UNW_IA64_NAT); | |
2463 | else | |
2464 | return -1; | |
2465 | } | |
2466 | ||
05e7c244 JK |
2467 | /* Gdb ia64-libunwind-tdep callback function to reveal if register is |
2468 | a float register or not. */ | |
968d1cb4 JJ |
2469 | static int |
2470 | ia64_is_fpreg (int uw_regnum) | |
2471 | { | |
2472 | return unw_is_fpreg (uw_regnum); | |
2473 | } | |
77ca787b | 2474 | |
968d1cb4 JJ |
2475 | /* Libunwind callback accessor function for general registers. */ |
2476 | static int | |
2477 | ia64_access_reg (unw_addr_space_t as, unw_regnum_t uw_regnum, unw_word_t *val, | |
2478 | int write, void *arg) | |
2479 | { | |
2480 | int regnum = ia64_uw2gdb_regnum (uw_regnum); | |
5c99fcf8 | 2481 | unw_word_t bsp, sof, cfm, psr, ip; |
bfb0d950 | 2482 | struct frame_info *this_frame = (struct frame_info *) arg; |
5af949e3 | 2483 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
968d1cb4 | 2484 | |
45ecac4b UW |
2485 | /* We never call any libunwind routines that need to write registers. */ |
2486 | gdb_assert (!write); | |
968d1cb4 | 2487 | |
45ecac4b | 2488 | switch (uw_regnum) |
968d1cb4 | 2489 | { |
45ecac4b UW |
2490 | case UNW_REG_IP: |
2491 | /* Libunwind expects to see the pc value which means the slot number | |
2492 | from the psr must be merged with the ip word address. */ | |
5c99fcf8 AH |
2493 | ip = get_frame_register_unsigned (this_frame, IA64_IP_REGNUM); |
2494 | psr = get_frame_register_unsigned (this_frame, IA64_PSR_REGNUM); | |
45ecac4b UW |
2495 | *val = ip | ((psr >> 41) & 0x3); |
2496 | break; | |
2497 | ||
2498 | case UNW_IA64_AR_BSP: | |
1777feb0 MS |
2499 | /* Libunwind expects to see the beginning of the current |
2500 | register frame so we must account for the fact that | |
2501 | ptrace() will return a value for bsp that points *after* | |
2502 | the current register frame. */ | |
5c99fcf8 AH |
2503 | bsp = get_frame_register_unsigned (this_frame, IA64_BSP_REGNUM); |
2504 | cfm = get_frame_register_unsigned (this_frame, IA64_CFM_REGNUM); | |
77ca787b | 2505 | sof = gdbarch_tdep (gdbarch)->size_of_register_frame (this_frame, cfm); |
45ecac4b UW |
2506 | *val = ia64_rse_skip_regs (bsp, -sof); |
2507 | break; | |
968d1cb4 | 2508 | |
45ecac4b UW |
2509 | case UNW_IA64_AR_BSPSTORE: |
2510 | /* Libunwind wants bspstore to be after the current register frame. | |
2511 | This is what ptrace() and gdb treats as the regular bsp value. */ | |
5c99fcf8 | 2512 | *val = get_frame_register_unsigned (this_frame, IA64_BSP_REGNUM); |
45ecac4b UW |
2513 | break; |
2514 | ||
2515 | default: | |
2516 | /* For all other registers, just unwind the value directly. */ | |
5c99fcf8 | 2517 | *val = get_frame_register_unsigned (this_frame, regnum); |
45ecac4b | 2518 | break; |
968d1cb4 | 2519 | } |
45ecac4b UW |
2520 | |
2521 | if (gdbarch_debug >= 1) | |
2522 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 | 2523 | " access_reg: from cache: %4s=%s\n", |
45ecac4b UW |
2524 | (((unsigned) regnum <= IA64_NAT127_REGNUM) |
2525 | ? ia64_register_names[regnum] : "r??"), | |
2edfe795 | 2526 | paddress (gdbarch, *val)); |
968d1cb4 JJ |
2527 | return 0; |
2528 | } | |
2529 | ||
2530 | /* Libunwind callback accessor function for floating-point registers. */ | |
2531 | static int | |
1777feb0 MS |
2532 | ia64_access_fpreg (unw_addr_space_t as, unw_regnum_t uw_regnum, |
2533 | unw_fpreg_t *val, int write, void *arg) | |
968d1cb4 JJ |
2534 | { |
2535 | int regnum = ia64_uw2gdb_regnum (uw_regnum); | |
bfb0d950 | 2536 | struct frame_info *this_frame = (struct frame_info *) arg; |
968d1cb4 | 2537 | |
45ecac4b UW |
2538 | /* We never call any libunwind routines that need to write registers. */ |
2539 | gdb_assert (!write); | |
2540 | ||
2b692d32 | 2541 | get_frame_register (this_frame, regnum, (gdb_byte *) val); |
45ecac4b | 2542 | |
968d1cb4 JJ |
2543 | return 0; |
2544 | } | |
2545 | ||
c5a27d9c JJ |
2546 | /* Libunwind callback accessor function for top-level rse registers. */ |
2547 | static int | |
1777feb0 MS |
2548 | ia64_access_rse_reg (unw_addr_space_t as, unw_regnum_t uw_regnum, |
2549 | unw_word_t *val, int write, void *arg) | |
c5a27d9c JJ |
2550 | { |
2551 | int regnum = ia64_uw2gdb_regnum (uw_regnum); | |
5c99fcf8 | 2552 | unw_word_t bsp, sof, cfm, psr, ip; |
bfb0d950 | 2553 | struct regcache *regcache = (struct regcache *) arg; |
ac7936df | 2554 | struct gdbarch *gdbarch = regcache->arch (); |
c5a27d9c | 2555 | |
45ecac4b UW |
2556 | /* We never call any libunwind routines that need to write registers. */ |
2557 | gdb_assert (!write); | |
c5a27d9c | 2558 | |
45ecac4b | 2559 | switch (uw_regnum) |
c5a27d9c | 2560 | { |
45ecac4b UW |
2561 | case UNW_REG_IP: |
2562 | /* Libunwind expects to see the pc value which means the slot number | |
2563 | from the psr must be merged with the ip word address. */ | |
5c99fcf8 AH |
2564 | regcache_cooked_read_unsigned (regcache, IA64_IP_REGNUM, &ip); |
2565 | regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr); | |
45ecac4b UW |
2566 | *val = ip | ((psr >> 41) & 0x3); |
2567 | break; | |
c5a27d9c | 2568 | |
45ecac4b | 2569 | case UNW_IA64_AR_BSP: |
1777feb0 MS |
2570 | /* Libunwind expects to see the beginning of the current |
2571 | register frame so we must account for the fact that | |
2572 | ptrace() will return a value for bsp that points *after* | |
2573 | the current register frame. */ | |
5c99fcf8 AH |
2574 | regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp); |
2575 | regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm); | |
45ecac4b UW |
2576 | sof = (cfm & 0x7f); |
2577 | *val = ia64_rse_skip_regs (bsp, -sof); | |
2578 | break; | |
c5a27d9c | 2579 | |
45ecac4b UW |
2580 | case UNW_IA64_AR_BSPSTORE: |
2581 | /* Libunwind wants bspstore to be after the current register frame. | |
2582 | This is what ptrace() and gdb treats as the regular bsp value. */ | |
5c99fcf8 | 2583 | regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, val); |
45ecac4b | 2584 | break; |
c5a27d9c | 2585 | |
45ecac4b UW |
2586 | default: |
2587 | /* For all other registers, just unwind the value directly. */ | |
5c99fcf8 | 2588 | regcache_cooked_read_unsigned (regcache, regnum, val); |
45ecac4b | 2589 | break; |
c5a27d9c JJ |
2590 | } |
2591 | ||
2592 | if (gdbarch_debug >= 1) | |
2593 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 | 2594 | " access_rse_reg: from cache: %4s=%s\n", |
c5a27d9c JJ |
2595 | (((unsigned) regnum <= IA64_NAT127_REGNUM) |
2596 | ? ia64_register_names[regnum] : "r??"), | |
5af949e3 | 2597 | paddress (gdbarch, *val)); |
c5a27d9c JJ |
2598 | |
2599 | return 0; | |
2600 | } | |
2601 | ||
45ecac4b UW |
2602 | /* Libunwind callback accessor function for top-level fp registers. */ |
2603 | static int | |
2604 | ia64_access_rse_fpreg (unw_addr_space_t as, unw_regnum_t uw_regnum, | |
2605 | unw_fpreg_t *val, int write, void *arg) | |
2606 | { | |
2607 | int regnum = ia64_uw2gdb_regnum (uw_regnum); | |
bfb0d950 | 2608 | struct regcache *regcache = (struct regcache *) arg; |
45ecac4b UW |
2609 | |
2610 | /* We never call any libunwind routines that need to write registers. */ | |
2611 | gdb_assert (!write); | |
2612 | ||
dca08e1f | 2613 | regcache->cooked_read (regnum, (gdb_byte *) val); |
45ecac4b UW |
2614 | |
2615 | return 0; | |
2616 | } | |
2617 | ||
968d1cb4 JJ |
2618 | /* Libunwind callback accessor function for accessing memory. */ |
2619 | static int | |
2620 | ia64_access_mem (unw_addr_space_t as, | |
2621 | unw_word_t addr, unw_word_t *val, | |
2622 | int write, void *arg) | |
2623 | { | |
c5a27d9c JJ |
2624 | if (addr - KERNEL_START < ktab_size) |
2625 | { | |
2626 | unw_word_t *laddr = (unw_word_t*) ((char *) ktab | |
2627 | + (addr - KERNEL_START)); | |
2628 | ||
2629 | if (write) | |
2630 | *laddr = *val; | |
2631 | else | |
2632 | *val = *laddr; | |
2633 | return 0; | |
2634 | } | |
2635 | ||
968d1cb4 JJ |
2636 | /* XXX do we need to normalize byte-order here? */ |
2637 | if (write) | |
2b692d32 | 2638 | return target_write_memory (addr, (gdb_byte *) val, sizeof (unw_word_t)); |
968d1cb4 | 2639 | else |
2b692d32 | 2640 | return target_read_memory (addr, (gdb_byte *) val, sizeof (unw_word_t)); |
968d1cb4 JJ |
2641 | } |
2642 | ||
2643 | /* Call low-level function to access the kernel unwind table. */ | |
5d691c88 SM |
2644 | static gdb::optional<gdb::byte_vector> |
2645 | getunwind_table () | |
968d1cb4 | 2646 | { |
10d6c8cd DJ |
2647 | /* FIXME drow/2005-09-10: This code used to call |
2648 | ia64_linux_xfer_unwind_table directly to fetch the unwind table | |
2649 | for the currently running ia64-linux kernel. That data should | |
2650 | come from the core file and be accessed via the auxv vector; if | |
2651 | we want to preserve fall back to the running kernel's table, then | |
2652 | we should find a way to override the corefile layer's | |
2653 | xfer_partial method. */ | |
968d1cb4 | 2654 | |
5d691c88 SM |
2655 | return target_read_alloc (current_top_target (), TARGET_OBJECT_UNWIND_TABLE, |
2656 | NULL); | |
968d1cb4 | 2657 | } |
10d6c8cd | 2658 | |
968d1cb4 JJ |
2659 | /* Get the kernel unwind table. */ |
2660 | static int | |
2661 | get_kernel_table (unw_word_t ip, unw_dyn_info_t *di) | |
2662 | { | |
c5a27d9c | 2663 | static struct ia64_table_entry *etab; |
968d1cb4 | 2664 | |
c5a27d9c | 2665 | if (!ktab) |
968d1cb4 | 2666 | { |
5d691c88 SM |
2667 | ktab_buf = getunwind_table (); |
2668 | if (!ktab_buf) | |
13547ab6 | 2669 | return -UNW_ENOINFO; |
eeec829c | 2670 | |
5d691c88 SM |
2671 | ktab = (struct ia64_table_entry *) ktab_buf->data (); |
2672 | ktab_size = ktab_buf->size (); | |
13547ab6 | 2673 | |
968d1cb4 | 2674 | for (etab = ktab; etab->start_offset; ++etab) |
c5a27d9c | 2675 | etab->info_offset += KERNEL_START; |
968d1cb4 JJ |
2676 | } |
2677 | ||
2678 | if (ip < ktab[0].start_offset || ip >= etab[-1].end_offset) | |
2679 | return -UNW_ENOINFO; | |
2680 | ||
2681 | di->format = UNW_INFO_FORMAT_TABLE; | |
2682 | di->gp = 0; | |
2683 | di->start_ip = ktab[0].start_offset; | |
2684 | di->end_ip = etab[-1].end_offset; | |
2685 | di->u.ti.name_ptr = (unw_word_t) "<kernel>"; | |
2686 | di->u.ti.segbase = 0; | |
2687 | di->u.ti.table_len = ((char *) etab - (char *) ktab) / sizeof (unw_word_t); | |
2688 | di->u.ti.table_data = (unw_word_t *) ktab; | |
2689 | ||
2690 | if (gdbarch_debug >= 1) | |
2691 | fprintf_unfiltered (gdb_stdlog, "get_kernel_table: found table `%s': " | |
5af949e3 | 2692 | "segbase=%s, length=%s, gp=%s\n", |
78ced177 | 2693 | (char *) di->u.ti.name_ptr, |
5af949e3 | 2694 | hex_string (di->u.ti.segbase), |
623d3eb1 | 2695 | pulongest (di->u.ti.table_len), |
5af949e3 | 2696 | hex_string (di->gp)); |
968d1cb4 JJ |
2697 | return 0; |
2698 | } | |
2699 | ||
2700 | /* Find the unwind table entry for a specified address. */ | |
2701 | static int | |
2702 | ia64_find_unwind_table (struct objfile *objfile, unw_word_t ip, | |
2703 | unw_dyn_info_t *dip, void **buf) | |
2704 | { | |
2705 | Elf_Internal_Phdr *phdr, *p_text = NULL, *p_unwind = NULL; | |
2706 | Elf_Internal_Ehdr *ehdr; | |
2707 | unw_word_t segbase = 0; | |
2708 | CORE_ADDR load_base; | |
2709 | bfd *bfd; | |
2710 | int i; | |
2711 | ||
2712 | bfd = objfile->obfd; | |
2713 | ||
2714 | ehdr = elf_tdata (bfd)->elf_header; | |
2715 | phdr = elf_tdata (bfd)->phdr; | |
2716 | ||
2717 | load_base = ANOFFSET (objfile->section_offsets, SECT_OFF_TEXT (objfile)); | |
2718 | ||
2719 | for (i = 0; i < ehdr->e_phnum; ++i) | |
2720 | { | |
2721 | switch (phdr[i].p_type) | |
2722 | { | |
2723 | case PT_LOAD: | |
2724 | if ((unw_word_t) (ip - load_base - phdr[i].p_vaddr) | |
2725 | < phdr[i].p_memsz) | |
2726 | p_text = phdr + i; | |
2727 | break; | |
2728 | ||
2729 | case PT_IA_64_UNWIND: | |
2730 | p_unwind = phdr + i; | |
2731 | break; | |
2732 | ||
2733 | default: | |
2734 | break; | |
2735 | } | |
2736 | } | |
2737 | ||
c5a27d9c | 2738 | if (!p_text || !p_unwind) |
968d1cb4 JJ |
2739 | return -UNW_ENOINFO; |
2740 | ||
c5a27d9c JJ |
2741 | /* Verify that the segment that contains the IP also contains |
2742 | the static unwind table. If not, we may be in the Linux kernel's | |
1777feb0 | 2743 | DSO gate page in which case the unwind table is another segment. |
c5a27d9c JJ |
2744 | Otherwise, we are dealing with runtime-generated code, for which we |
2745 | have no info here. */ | |
968d1cb4 JJ |
2746 | segbase = p_text->p_vaddr + load_base; |
2747 | ||
c5a27d9c JJ |
2748 | if ((p_unwind->p_vaddr - p_text->p_vaddr) >= p_text->p_memsz) |
2749 | { | |
2750 | int ok = 0; | |
2751 | for (i = 0; i < ehdr->e_phnum; ++i) | |
2752 | { | |
2753 | if (phdr[i].p_type == PT_LOAD | |
2754 | && (p_unwind->p_vaddr - phdr[i].p_vaddr) < phdr[i].p_memsz) | |
2755 | { | |
2756 | ok = 1; | |
2757 | /* Get the segbase from the section containing the | |
2758 | libunwind table. */ | |
2759 | segbase = phdr[i].p_vaddr + load_base; | |
2760 | } | |
2761 | } | |
2762 | if (!ok) | |
2763 | return -UNW_ENOINFO; | |
2764 | } | |
2765 | ||
2766 | dip->start_ip = p_text->p_vaddr + load_base; | |
968d1cb4 | 2767 | dip->end_ip = dip->start_ip + p_text->p_memsz; |
e17a4113 | 2768 | dip->gp = ia64_find_global_pointer (get_objfile_arch (objfile), ip); |
503ff15d KB |
2769 | dip->format = UNW_INFO_FORMAT_REMOTE_TABLE; |
2770 | dip->u.rti.name_ptr = (unw_word_t) bfd_get_filename (bfd); | |
2771 | dip->u.rti.segbase = segbase; | |
2772 | dip->u.rti.table_len = p_unwind->p_memsz / sizeof (unw_word_t); | |
2773 | dip->u.rti.table_data = p_unwind->p_vaddr + load_base; | |
968d1cb4 JJ |
2774 | |
2775 | return 0; | |
2776 | } | |
2777 | ||
2778 | /* Libunwind callback accessor function to acquire procedure unwind-info. */ | |
2779 | static int | |
2780 | ia64_find_proc_info_x (unw_addr_space_t as, unw_word_t ip, unw_proc_info_t *pi, | |
2781 | int need_unwind_info, void *arg) | |
2782 | { | |
2783 | struct obj_section *sec = find_pc_section (ip); | |
2784 | unw_dyn_info_t di; | |
2785 | int ret; | |
2786 | void *buf = NULL; | |
2787 | ||
2788 | if (!sec) | |
2789 | { | |
2790 | /* XXX This only works if the host and the target architecture are | |
2791 | both ia64 and if the have (more or less) the same kernel | |
2792 | version. */ | |
2793 | if (get_kernel_table (ip, &di) < 0) | |
2794 | return -UNW_ENOINFO; | |
503ff15d KB |
2795 | |
2796 | if (gdbarch_debug >= 1) | |
5af949e3 UW |
2797 | fprintf_unfiltered (gdb_stdlog, "ia64_find_proc_info_x: %s -> " |
2798 | "(name=`%s',segbase=%s,start=%s,end=%s,gp=%s," | |
2799 | "length=%s,data=%s)\n", | |
2800 | hex_string (ip), (char *)di.u.ti.name_ptr, | |
2801 | hex_string (di.u.ti.segbase), | |
2802 | hex_string (di.start_ip), hex_string (di.end_ip), | |
2803 | hex_string (di.gp), | |
623d3eb1 | 2804 | pulongest (di.u.ti.table_len), |
5af949e3 | 2805 | hex_string ((CORE_ADDR)di.u.ti.table_data)); |
968d1cb4 JJ |
2806 | } |
2807 | else | |
2808 | { | |
2809 | ret = ia64_find_unwind_table (sec->objfile, ip, &di, &buf); | |
2810 | if (ret < 0) | |
2811 | return ret; | |
968d1cb4 | 2812 | |
503ff15d | 2813 | if (gdbarch_debug >= 1) |
5af949e3 UW |
2814 | fprintf_unfiltered (gdb_stdlog, "ia64_find_proc_info_x: %s -> " |
2815 | "(name=`%s',segbase=%s,start=%s,end=%s,gp=%s," | |
2816 | "length=%s,data=%s)\n", | |
2817 | hex_string (ip), (char *)di.u.rti.name_ptr, | |
2818 | hex_string (di.u.rti.segbase), | |
2819 | hex_string (di.start_ip), hex_string (di.end_ip), | |
2820 | hex_string (di.gp), | |
623d3eb1 | 2821 | pulongest (di.u.rti.table_len), |
5af949e3 | 2822 | hex_string (di.u.rti.table_data)); |
503ff15d | 2823 | } |
968d1cb4 | 2824 | |
503ff15d KB |
2825 | ret = libunwind_search_unwind_table (&as, ip, &di, pi, need_unwind_info, |
2826 | arg); | |
968d1cb4 JJ |
2827 | |
2828 | /* We no longer need the dyn info storage so free it. */ | |
2829 | xfree (buf); | |
2830 | ||
2831 | return ret; | |
2832 | } | |
2833 | ||
2834 | /* Libunwind callback accessor function for cleanup. */ | |
2835 | static void | |
2836 | ia64_put_unwind_info (unw_addr_space_t as, | |
2837 | unw_proc_info_t *pip, void *arg) | |
2838 | { | |
2839 | /* Nothing required for now. */ | |
2840 | } | |
2841 | ||
2842 | /* Libunwind callback accessor function to get head of the dynamic | |
2843 | unwind-info registration list. */ | |
2844 | static int | |
2845 | ia64_get_dyn_info_list (unw_addr_space_t as, | |
2846 | unw_word_t *dilap, void *arg) | |
2847 | { | |
2848 | struct obj_section *text_sec; | |
2849 | struct objfile *objfile; | |
2850 | unw_word_t ip, addr; | |
2851 | unw_dyn_info_t di; | |
2852 | int ret; | |
2853 | ||
2854 | if (!libunwind_is_initialized ()) | |
2855 | return -UNW_ENOINFO; | |
2856 | ||
2857 | for (objfile = object_files; objfile; objfile = objfile->next) | |
2858 | { | |
2859 | void *buf = NULL; | |
2860 | ||
2861 | text_sec = objfile->sections + SECT_OFF_TEXT (objfile); | |
8b7a6d61 | 2862 | ip = obj_section_addr (text_sec); |
968d1cb4 JJ |
2863 | ret = ia64_find_unwind_table (objfile, ip, &di, &buf); |
2864 | if (ret >= 0) | |
2865 | { | |
503ff15d | 2866 | addr = libunwind_find_dyn_list (as, &di, arg); |
968d1cb4 JJ |
2867 | /* We no longer need the dyn info storage so free it. */ |
2868 | xfree (buf); | |
2869 | ||
2870 | if (addr) | |
2871 | { | |
2872 | if (gdbarch_debug >= 1) | |
2873 | fprintf_unfiltered (gdb_stdlog, | |
2874 | "dynamic unwind table in objfile %s " | |
5af949e3 | 2875 | "at %s (gp=%s)\n", |
968d1cb4 | 2876 | bfd_get_filename (objfile->obfd), |
5af949e3 | 2877 | hex_string (addr), hex_string (di.gp)); |
968d1cb4 JJ |
2878 | *dilap = addr; |
2879 | return 0; | |
2880 | } | |
2881 | } | |
2882 | } | |
2883 | return -UNW_ENOINFO; | |
2884 | } | |
2885 | ||
2886 | ||
2887 | /* Frame interface functions for libunwind. */ | |
2888 | ||
2889 | static void | |
15c1e57f | 2890 | ia64_libunwind_frame_this_id (struct frame_info *this_frame, void **this_cache, |
7166c4a9 | 2891 | struct frame_id *this_id) |
968d1cb4 | 2892 | { |
5af949e3 | 2893 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
e17a4113 | 2894 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
005ca36a | 2895 | struct frame_id id = outer_frame_id; |
e362b510 | 2896 | gdb_byte buf[8]; |
968d1cb4 | 2897 | CORE_ADDR bsp; |
c5a27d9c | 2898 | |
15c1e57f | 2899 | libunwind_frame_this_id (this_frame, this_cache, &id); |
005ca36a | 2900 | if (frame_id_eq (id, outer_frame_id)) |
c5a27d9c | 2901 | { |
005ca36a | 2902 | (*this_id) = outer_frame_id; |
c5a27d9c JJ |
2903 | return; |
2904 | } | |
968d1cb4 | 2905 | |
c5a27d9c JJ |
2906 | /* We must add the bsp as the special address for frame comparison |
2907 | purposes. */ | |
15c1e57f | 2908 | get_frame_register (this_frame, IA64_BSP_REGNUM, buf); |
e17a4113 | 2909 | bsp = extract_unsigned_integer (buf, 8, byte_order); |
968d1cb4 | 2910 | |
15c1e57f | 2911 | (*this_id) = frame_id_build_special (id.stack_addr, id.code_addr, bsp); |
968d1cb4 JJ |
2912 | |
2913 | if (gdbarch_debug >= 1) | |
2914 | fprintf_unfiltered (gdb_stdlog, | |
1777feb0 MS |
2915 | "libunwind frame id: code %s, stack %s, " |
2916 | "special %s, this_frame %s\n", | |
5af949e3 UW |
2917 | paddress (gdbarch, id.code_addr), |
2918 | paddress (gdbarch, id.stack_addr), | |
2919 | paddress (gdbarch, bsp), | |
dfc3cd0e | 2920 | host_address_to_string (this_frame)); |
968d1cb4 JJ |
2921 | } |
2922 | ||
15c1e57f JB |
2923 | static struct value * |
2924 | ia64_libunwind_frame_prev_register (struct frame_info *this_frame, | |
2925 | void **this_cache, int regnum) | |
968d1cb4 JJ |
2926 | { |
2927 | int reg = regnum; | |
15c1e57f | 2928 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
e17a4113 | 2929 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
15c1e57f | 2930 | struct value *val; |
968d1cb4 JJ |
2931 | |
2932 | if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM) | |
2933 | reg = IA64_PR_REGNUM; | |
2934 | else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM) | |
2935 | reg = IA64_UNAT_REGNUM; | |
2936 | ||
2937 | /* Let libunwind do most of the work. */ | |
15c1e57f | 2938 | val = libunwind_frame_prev_register (this_frame, this_cache, reg); |
6672f2ae | 2939 | |
968d1cb4 JJ |
2940 | if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM) |
2941 | { | |
2942 | ULONGEST prN_val; | |
2943 | ||
2944 | if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM) | |
2945 | { | |
2946 | int rrb_pr = 0; | |
2947 | ULONGEST cfm; | |
968d1cb4 JJ |
2948 | |
2949 | /* Fetch predicate register rename base from current frame | |
2950 | marker for this frame. */ | |
5c99fcf8 | 2951 | cfm = get_frame_register_unsigned (this_frame, IA64_CFM_REGNUM); |
968d1cb4 JJ |
2952 | rrb_pr = (cfm >> 32) & 0x3f; |
2953 | ||
2954 | /* Adjust the register number to account for register rotation. */ | |
15c1e57f | 2955 | regnum = VP16_REGNUM + ((regnum - VP16_REGNUM) + rrb_pr) % 48; |
968d1cb4 | 2956 | } |
15c1e57f | 2957 | prN_val = extract_bit_field (value_contents_all (val), |
968d1cb4 | 2958 | regnum - VP0_REGNUM, 1); |
15c1e57f | 2959 | return frame_unwind_got_constant (this_frame, regnum, prN_val); |
968d1cb4 | 2960 | } |
15c1e57f | 2961 | |
968d1cb4 JJ |
2962 | else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM) |
2963 | { | |
2964 | ULONGEST unatN_val; | |
2965 | ||
15c1e57f JB |
2966 | unatN_val = extract_bit_field (value_contents_all (val), |
2967 | regnum - IA64_NAT0_REGNUM, 1); | |
2968 | return frame_unwind_got_constant (this_frame, regnum, unatN_val); | |
968d1cb4 | 2969 | } |
15c1e57f | 2970 | |
968d1cb4 JJ |
2971 | else if (regnum == IA64_BSP_REGNUM) |
2972 | { | |
15c1e57f JB |
2973 | struct value *cfm_val; |
2974 | CORE_ADDR prev_bsp, prev_cfm; | |
2975 | ||
2976 | /* We want to calculate the previous bsp as the end of the previous | |
2977 | register stack frame. This corresponds to what the hardware bsp | |
2978 | register will be if we pop the frame back which is why we might | |
2979 | have been called. We know that libunwind will pass us back the | |
1777feb0 | 2980 | beginning of the current frame so we should just add sof to it. */ |
e17a4113 UW |
2981 | prev_bsp = extract_unsigned_integer (value_contents_all (val), |
2982 | 8, byte_order); | |
15c1e57f JB |
2983 | cfm_val = libunwind_frame_prev_register (this_frame, this_cache, |
2984 | IA64_CFM_REGNUM); | |
e17a4113 UW |
2985 | prev_cfm = extract_unsigned_integer (value_contents_all (cfm_val), |
2986 | 8, byte_order); | |
968d1cb4 JJ |
2987 | prev_bsp = rse_address_add (prev_bsp, (prev_cfm & 0x7f)); |
2988 | ||
15c1e57f | 2989 | return frame_unwind_got_constant (this_frame, regnum, prev_bsp); |
968d1cb4 | 2990 | } |
15c1e57f JB |
2991 | else |
2992 | return val; | |
2993 | } | |
968d1cb4 | 2994 | |
15c1e57f JB |
2995 | static int |
2996 | ia64_libunwind_frame_sniffer (const struct frame_unwind *self, | |
2997 | struct frame_info *this_frame, | |
2998 | void **this_cache) | |
2999 | { | |
3000 | if (libunwind_is_initialized () | |
3001 | && libunwind_frame_sniffer (self, this_frame, this_cache)) | |
3002 | return 1; | |
3003 | ||
3004 | return 0; | |
968d1cb4 JJ |
3005 | } |
3006 | ||
3007 | static const struct frame_unwind ia64_libunwind_frame_unwind = | |
3008 | { | |
3009 | NORMAL_FRAME, | |
8fbca658 | 3010 | default_frame_unwind_stop_reason, |
968d1cb4 | 3011 | ia64_libunwind_frame_this_id, |
272dfcfd AS |
3012 | ia64_libunwind_frame_prev_register, |
3013 | NULL, | |
15c1e57f | 3014 | ia64_libunwind_frame_sniffer, |
272dfcfd | 3015 | libunwind_frame_dealloc_cache |
968d1cb4 JJ |
3016 | }; |
3017 | ||
c5a27d9c | 3018 | static void |
15c1e57f JB |
3019 | ia64_libunwind_sigtramp_frame_this_id (struct frame_info *this_frame, |
3020 | void **this_cache, | |
c5a27d9c JJ |
3021 | struct frame_id *this_id) |
3022 | { | |
5af949e3 | 3023 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
e17a4113 | 3024 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
e362b510 | 3025 | gdb_byte buf[8]; |
c5a27d9c | 3026 | CORE_ADDR bsp; |
005ca36a | 3027 | struct frame_id id = outer_frame_id; |
c5a27d9c | 3028 | |
15c1e57f | 3029 | libunwind_frame_this_id (this_frame, this_cache, &id); |
005ca36a | 3030 | if (frame_id_eq (id, outer_frame_id)) |
c5a27d9c | 3031 | { |
005ca36a | 3032 | (*this_id) = outer_frame_id; |
c5a27d9c JJ |
3033 | return; |
3034 | } | |
3035 | ||
3036 | /* We must add the bsp as the special address for frame comparison | |
3037 | purposes. */ | |
15c1e57f | 3038 | get_frame_register (this_frame, IA64_BSP_REGNUM, buf); |
e17a4113 | 3039 | bsp = extract_unsigned_integer (buf, 8, byte_order); |
c5a27d9c JJ |
3040 | |
3041 | /* For a sigtramp frame, we don't make the check for previous ip being 0. */ | |
3042 | (*this_id) = frame_id_build_special (id.stack_addr, id.code_addr, bsp); | |
3043 | ||
3044 | if (gdbarch_debug >= 1) | |
3045 | fprintf_unfiltered (gdb_stdlog, | |
1777feb0 MS |
3046 | "libunwind sigtramp frame id: code %s, " |
3047 | "stack %s, special %s, this_frame %s\n", | |
5af949e3 UW |
3048 | paddress (gdbarch, id.code_addr), |
3049 | paddress (gdbarch, id.stack_addr), | |
3050 | paddress (gdbarch, bsp), | |
dfc3cd0e | 3051 | host_address_to_string (this_frame)); |
c5a27d9c JJ |
3052 | } |
3053 | ||
15c1e57f JB |
3054 | static struct value * |
3055 | ia64_libunwind_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
3056 | void **this_cache, int regnum) | |
c5a27d9c | 3057 | { |
e17a4113 UW |
3058 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
3059 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
15c1e57f JB |
3060 | struct value *prev_ip_val; |
3061 | CORE_ADDR prev_ip; | |
c5a27d9c JJ |
3062 | |
3063 | /* If the previous frame pc value is 0, then we want to use the SIGCONTEXT | |
3064 | method of getting previous registers. */ | |
15c1e57f JB |
3065 | prev_ip_val = libunwind_frame_prev_register (this_frame, this_cache, |
3066 | IA64_IP_REGNUM); | |
e17a4113 UW |
3067 | prev_ip = extract_unsigned_integer (value_contents_all (prev_ip_val), |
3068 | 8, byte_order); | |
c5a27d9c JJ |
3069 | |
3070 | if (prev_ip == 0) | |
3071 | { | |
3072 | void *tmp_cache = NULL; | |
15c1e57f JB |
3073 | return ia64_sigtramp_frame_prev_register (this_frame, &tmp_cache, |
3074 | regnum); | |
c5a27d9c JJ |
3075 | } |
3076 | else | |
15c1e57f | 3077 | return ia64_libunwind_frame_prev_register (this_frame, this_cache, regnum); |
c5a27d9c JJ |
3078 | } |
3079 | ||
15c1e57f JB |
3080 | static int |
3081 | ia64_libunwind_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
3082 | struct frame_info *this_frame, | |
3083 | void **this_cache) | |
c5a27d9c JJ |
3084 | { |
3085 | if (libunwind_is_initialized ()) | |
3086 | { | |
15c1e57f JB |
3087 | if (libunwind_sigtramp_frame_sniffer (self, this_frame, this_cache)) |
3088 | return 1; | |
3089 | return 0; | |
c5a27d9c JJ |
3090 | } |
3091 | else | |
15c1e57f | 3092 | return ia64_sigtramp_frame_sniffer (self, this_frame, this_cache); |
c5a27d9c JJ |
3093 | } |
3094 | ||
15c1e57f JB |
3095 | static const struct frame_unwind ia64_libunwind_sigtramp_frame_unwind = |
3096 | { | |
3097 | SIGTRAMP_FRAME, | |
8fbca658 | 3098 | default_frame_unwind_stop_reason, |
15c1e57f JB |
3099 | ia64_libunwind_sigtramp_frame_this_id, |
3100 | ia64_libunwind_sigtramp_frame_prev_register, | |
3101 | NULL, | |
3102 | ia64_libunwind_sigtramp_frame_sniffer | |
3103 | }; | |
3104 | ||
968d1cb4 | 3105 | /* Set of libunwind callback acccessor functions. */ |
696759ad | 3106 | unw_accessors_t ia64_unw_accessors = |
968d1cb4 JJ |
3107 | { |
3108 | ia64_find_proc_info_x, | |
3109 | ia64_put_unwind_info, | |
3110 | ia64_get_dyn_info_list, | |
3111 | ia64_access_mem, | |
3112 | ia64_access_reg, | |
3113 | ia64_access_fpreg, | |
3114 | /* resume */ | |
3115 | /* get_proc_name */ | |
3116 | }; | |
3117 | ||
c5a27d9c JJ |
3118 | /* Set of special libunwind callback acccessor functions specific for accessing |
3119 | the rse registers. At the top of the stack, we want libunwind to figure out | |
1777feb0 MS |
3120 | how to read r32 - r127. Though usually they are found sequentially in |
3121 | memory starting from $bof, this is not always true. */ | |
696759ad | 3122 | unw_accessors_t ia64_unw_rse_accessors = |
c5a27d9c JJ |
3123 | { |
3124 | ia64_find_proc_info_x, | |
3125 | ia64_put_unwind_info, | |
3126 | ia64_get_dyn_info_list, | |
3127 | ia64_access_mem, | |
3128 | ia64_access_rse_reg, | |
45ecac4b | 3129 | ia64_access_rse_fpreg, |
c5a27d9c JJ |
3130 | /* resume */ |
3131 | /* get_proc_name */ | |
3132 | }; | |
3133 | ||
05e7c244 JK |
3134 | /* Set of ia64-libunwind-tdep gdb callbacks and data for generic |
3135 | ia64-libunwind-tdep code to use. */ | |
696759ad | 3136 | struct libunwind_descr ia64_libunwind_descr = |
968d1cb4 JJ |
3137 | { |
3138 | ia64_gdb2uw_regnum, | |
3139 | ia64_uw2gdb_regnum, | |
3140 | ia64_is_fpreg, | |
3141 | &ia64_unw_accessors, | |
c5a27d9c | 3142 | &ia64_unw_rse_accessors, |
968d1cb4 JJ |
3143 | }; |
3144 | ||
3145 | #endif /* HAVE_LIBUNWIND_IA64_H */ | |
3146 | ||
4c8b6ae0 UW |
3147 | static int |
3148 | ia64_use_struct_convention (struct type *type) | |
16461d7d | 3149 | { |
64a5b29c KB |
3150 | struct type *float_elt_type; |
3151 | ||
4c8b6ae0 UW |
3152 | /* Don't use the struct convention for anything but structure, |
3153 | union, or array types. */ | |
3154 | if (!(TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3155 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3156 | || TYPE_CODE (type) == TYPE_CODE_ARRAY)) | |
3157 | return 0; | |
3158 | ||
64a5b29c KB |
3159 | /* HFAs are structures (or arrays) consisting entirely of floating |
3160 | point values of the same length. Up to 8 of these are returned | |
3161 | in registers. Don't use the struct convention when this is the | |
004d836a | 3162 | case. */ |
64a5b29c KB |
3163 | float_elt_type = is_float_or_hfa_type (type); |
3164 | if (float_elt_type != NULL | |
3165 | && TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type) <= 8) | |
3166 | return 0; | |
3167 | ||
3168 | /* Other structs of length 32 or less are returned in r8-r11. | |
004d836a | 3169 | Don't use the struct convention for those either. */ |
16461d7d KB |
3170 | return TYPE_LENGTH (type) > 32; |
3171 | } | |
3172 | ||
825d6d8a JB |
3173 | /* Return non-zero if TYPE is a structure or union type. */ |
3174 | ||
3175 | static int | |
3176 | ia64_struct_type_p (const struct type *type) | |
3177 | { | |
3178 | return (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3179 | || TYPE_CODE (type) == TYPE_CODE_UNION); | |
3180 | } | |
3181 | ||
4c8b6ae0 | 3182 | static void |
2d522557 AC |
3183 | ia64_extract_return_value (struct type *type, struct regcache *regcache, |
3184 | gdb_byte *valbuf) | |
16461d7d | 3185 | { |
ac7936df | 3186 | struct gdbarch *gdbarch = regcache->arch (); |
64a5b29c KB |
3187 | struct type *float_elt_type; |
3188 | ||
3189 | float_elt_type = is_float_or_hfa_type (type); | |
3190 | if (float_elt_type != NULL) | |
3191 | { | |
ae0d01d6 | 3192 | gdb_byte from[IA64_FP_REGISTER_SIZE]; |
64a5b29c KB |
3193 | int offset = 0; |
3194 | int regnum = IA64_FR8_REGNUM; | |
3195 | int n = TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type); | |
3196 | ||
3197 | while (n-- > 0) | |
3198 | { | |
dca08e1f | 3199 | regcache->cooked_read (regnum, from); |
3b2ca824 UW |
3200 | target_float_convert (from, ia64_ext_type (gdbarch), |
3201 | valbuf + offset, float_elt_type); | |
64a5b29c KB |
3202 | offset += TYPE_LENGTH (float_elt_type); |
3203 | regnum++; | |
3204 | } | |
3205 | } | |
825d6d8a JB |
3206 | else if (!ia64_struct_type_p (type) && TYPE_LENGTH (type) < 8) |
3207 | { | |
3208 | /* This is an integral value, and its size is less than 8 bytes. | |
3209 | These values are LSB-aligned, so extract the relevant bytes, | |
3210 | and copy them into VALBUF. */ | |
3211 | /* brobecker/2005-12-30: Actually, all integral values are LSB aligned, | |
3212 | so I suppose we should also add handling here for integral values | |
3213 | whose size is greater than 8. But I wasn't able to create such | |
3214 | a type, neither in C nor in Ada, so not worrying about these yet. */ | |
3215 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
3216 | ULONGEST val; | |
3217 | ||
3218 | regcache_cooked_read_unsigned (regcache, IA64_GR8_REGNUM, &val); | |
3219 | store_unsigned_integer (valbuf, TYPE_LENGTH (type), byte_order, val); | |
3220 | } | |
16461d7d | 3221 | else |
004d836a JJ |
3222 | { |
3223 | ULONGEST val; | |
3224 | int offset = 0; | |
3225 | int regnum = IA64_GR8_REGNUM; | |
27067745 | 3226 | int reglen = TYPE_LENGTH (register_type (gdbarch, IA64_GR8_REGNUM)); |
004d836a JJ |
3227 | int n = TYPE_LENGTH (type) / reglen; |
3228 | int m = TYPE_LENGTH (type) % reglen; | |
16461d7d | 3229 | |
004d836a JJ |
3230 | while (n-- > 0) |
3231 | { | |
3232 | ULONGEST val; | |
3233 | regcache_cooked_read_unsigned (regcache, regnum, &val); | |
3234 | memcpy ((char *)valbuf + offset, &val, reglen); | |
3235 | offset += reglen; | |
3236 | regnum++; | |
3237 | } | |
16461d7d | 3238 | |
004d836a JJ |
3239 | if (m) |
3240 | { | |
3241 | regcache_cooked_read_unsigned (regcache, regnum, &val); | |
3242 | memcpy ((char *)valbuf + offset, &val, m); | |
3243 | } | |
3244 | } | |
16461d7d KB |
3245 | } |
3246 | ||
4c8b6ae0 UW |
3247 | static void |
3248 | ia64_store_return_value (struct type *type, struct regcache *regcache, | |
3249 | const gdb_byte *valbuf) | |
3250 | { | |
ac7936df | 3251 | struct gdbarch *gdbarch = regcache->arch (); |
4c8b6ae0 UW |
3252 | struct type *float_elt_type; |
3253 | ||
3254 | float_elt_type = is_float_or_hfa_type (type); | |
3255 | if (float_elt_type != NULL) | |
3256 | { | |
ae0d01d6 | 3257 | gdb_byte to[IA64_FP_REGISTER_SIZE]; |
4c8b6ae0 UW |
3258 | int offset = 0; |
3259 | int regnum = IA64_FR8_REGNUM; | |
3260 | int n = TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type); | |
3261 | ||
3262 | while (n-- > 0) | |
3263 | { | |
3b2ca824 UW |
3264 | target_float_convert (valbuf + offset, float_elt_type, |
3265 | to, ia64_ext_type (gdbarch)); | |
b66f5587 | 3266 | regcache->cooked_write (regnum, to); |
4c8b6ae0 UW |
3267 | offset += TYPE_LENGTH (float_elt_type); |
3268 | regnum++; | |
3269 | } | |
3270 | } | |
3271 | else | |
3272 | { | |
3273 | ULONGEST val; | |
3274 | int offset = 0; | |
3275 | int regnum = IA64_GR8_REGNUM; | |
27067745 | 3276 | int reglen = TYPE_LENGTH (register_type (gdbarch, IA64_GR8_REGNUM)); |
4c8b6ae0 UW |
3277 | int n = TYPE_LENGTH (type) / reglen; |
3278 | int m = TYPE_LENGTH (type) % reglen; | |
3279 | ||
3280 | while (n-- > 0) | |
3281 | { | |
3282 | ULONGEST val; | |
3283 | memcpy (&val, (char *)valbuf + offset, reglen); | |
3284 | regcache_cooked_write_unsigned (regcache, regnum, val); | |
3285 | offset += reglen; | |
3286 | regnum++; | |
3287 | } | |
3288 | ||
3289 | if (m) | |
3290 | { | |
3291 | memcpy (&val, (char *)valbuf + offset, m); | |
3292 | regcache_cooked_write_unsigned (regcache, regnum, val); | |
3293 | } | |
3294 | } | |
3295 | } | |
3296 | ||
3297 | static enum return_value_convention | |
6a3a010b | 3298 | ia64_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
3299 | struct type *valtype, struct regcache *regcache, |
3300 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
4c8b6ae0 UW |
3301 | { |
3302 | int struct_return = ia64_use_struct_convention (valtype); | |
3303 | ||
3304 | if (writebuf != NULL) | |
3305 | { | |
3306 | gdb_assert (!struct_return); | |
3307 | ia64_store_return_value (valtype, regcache, writebuf); | |
3308 | } | |
3309 | ||
3310 | if (readbuf != NULL) | |
3311 | { | |
3312 | gdb_assert (!struct_return); | |
3313 | ia64_extract_return_value (valtype, regcache, readbuf); | |
3314 | } | |
3315 | ||
3316 | if (struct_return) | |
3317 | return RETURN_VALUE_STRUCT_CONVENTION; | |
3318 | else | |
3319 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3320 | } | |
16461d7d | 3321 | |
64a5b29c KB |
3322 | static int |
3323 | is_float_or_hfa_type_recurse (struct type *t, struct type **etp) | |
3324 | { | |
3325 | switch (TYPE_CODE (t)) | |
3326 | { | |
3327 | case TYPE_CODE_FLT: | |
3328 | if (*etp) | |
3329 | return TYPE_LENGTH (*etp) == TYPE_LENGTH (t); | |
3330 | else | |
3331 | { | |
3332 | *etp = t; | |
3333 | return 1; | |
3334 | } | |
3335 | break; | |
3336 | case TYPE_CODE_ARRAY: | |
98f96ba1 KB |
3337 | return |
3338 | is_float_or_hfa_type_recurse (check_typedef (TYPE_TARGET_TYPE (t)), | |
3339 | etp); | |
64a5b29c KB |
3340 | break; |
3341 | case TYPE_CODE_STRUCT: | |
3342 | { | |
3343 | int i; | |
3344 | ||
3345 | for (i = 0; i < TYPE_NFIELDS (t); i++) | |
98f96ba1 KB |
3346 | if (!is_float_or_hfa_type_recurse |
3347 | (check_typedef (TYPE_FIELD_TYPE (t, i)), etp)) | |
64a5b29c KB |
3348 | return 0; |
3349 | return 1; | |
3350 | } | |
3351 | break; | |
3352 | default: | |
3353 | return 0; | |
3354 | break; | |
3355 | } | |
3356 | } | |
3357 | ||
3358 | /* Determine if the given type is one of the floating point types or | |
3359 | and HFA (which is a struct, array, or combination thereof whose | |
004d836a | 3360 | bottom-most elements are all of the same floating point type). */ |
64a5b29c KB |
3361 | |
3362 | static struct type * | |
3363 | is_float_or_hfa_type (struct type *t) | |
3364 | { | |
3365 | struct type *et = 0; | |
3366 | ||
3367 | return is_float_or_hfa_type_recurse (t, &et) ? et : 0; | |
3368 | } | |
3369 | ||
3370 | ||
98f96ba1 KB |
3371 | /* Return 1 if the alignment of T is such that the next even slot |
3372 | should be used. Return 0, if the next available slot should | |
3373 | be used. (See section 8.5.1 of the IA-64 Software Conventions | |
004d836a | 3374 | and Runtime manual). */ |
98f96ba1 KB |
3375 | |
3376 | static int | |
3377 | slot_alignment_is_next_even (struct type *t) | |
3378 | { | |
3379 | switch (TYPE_CODE (t)) | |
3380 | { | |
3381 | case TYPE_CODE_INT: | |
3382 | case TYPE_CODE_FLT: | |
3383 | if (TYPE_LENGTH (t) > 8) | |
3384 | return 1; | |
3385 | else | |
3386 | return 0; | |
3387 | case TYPE_CODE_ARRAY: | |
3388 | return | |
3389 | slot_alignment_is_next_even (check_typedef (TYPE_TARGET_TYPE (t))); | |
3390 | case TYPE_CODE_STRUCT: | |
3391 | { | |
3392 | int i; | |
3393 | ||
3394 | for (i = 0; i < TYPE_NFIELDS (t); i++) | |
3395 | if (slot_alignment_is_next_even | |
3396 | (check_typedef (TYPE_FIELD_TYPE (t, i)))) | |
3397 | return 1; | |
3398 | return 0; | |
3399 | } | |
3400 | default: | |
3401 | return 0; | |
3402 | } | |
3403 | } | |
3404 | ||
64a5b29c KB |
3405 | /* Attempt to find (and return) the global pointer for the given |
3406 | function. | |
3407 | ||
3408 | This is a rather nasty bit of code searchs for the .dynamic section | |
3409 | in the objfile corresponding to the pc of the function we're trying | |
3410 | to call. Once it finds the addresses at which the .dynamic section | |
3411 | lives in the child process, it scans the Elf64_Dyn entries for a | |
3412 | DT_PLTGOT tag. If it finds one of these, the corresponding | |
3413 | d_un.d_ptr value is the global pointer. */ | |
3414 | ||
3415 | static CORE_ADDR | |
c4de7027 JB |
3416 | ia64_find_global_pointer_from_dynamic_section (struct gdbarch *gdbarch, |
3417 | CORE_ADDR faddr) | |
64a5b29c | 3418 | { |
e17a4113 | 3419 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
76d689a6 | 3420 | struct obj_section *faddr_sect; |
64a5b29c | 3421 | |
76d689a6 KB |
3422 | faddr_sect = find_pc_section (faddr); |
3423 | if (faddr_sect != NULL) | |
64a5b29c KB |
3424 | { |
3425 | struct obj_section *osect; | |
3426 | ||
76d689a6 | 3427 | ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect) |
64a5b29c KB |
3428 | { |
3429 | if (strcmp (osect->the_bfd_section->name, ".dynamic") == 0) | |
3430 | break; | |
3431 | } | |
3432 | ||
76d689a6 | 3433 | if (osect < faddr_sect->objfile->sections_end) |
64a5b29c | 3434 | { |
aded6f54 | 3435 | CORE_ADDR addr, endaddr; |
64a5b29c | 3436 | |
aded6f54 PA |
3437 | addr = obj_section_addr (osect); |
3438 | endaddr = obj_section_endaddr (osect); | |
3439 | ||
3440 | while (addr < endaddr) | |
64a5b29c KB |
3441 | { |
3442 | int status; | |
3443 | LONGEST tag; | |
e362b510 | 3444 | gdb_byte buf[8]; |
64a5b29c KB |
3445 | |
3446 | status = target_read_memory (addr, buf, sizeof (buf)); | |
3447 | if (status != 0) | |
3448 | break; | |
e17a4113 | 3449 | tag = extract_signed_integer (buf, sizeof (buf), byte_order); |
64a5b29c KB |
3450 | |
3451 | if (tag == DT_PLTGOT) | |
3452 | { | |
3453 | CORE_ADDR global_pointer; | |
3454 | ||
3455 | status = target_read_memory (addr + 8, buf, sizeof (buf)); | |
3456 | if (status != 0) | |
3457 | break; | |
e17a4113 UW |
3458 | global_pointer = extract_unsigned_integer (buf, sizeof (buf), |
3459 | byte_order); | |
64a5b29c | 3460 | |
1777feb0 | 3461 | /* The payoff... */ |
64a5b29c KB |
3462 | return global_pointer; |
3463 | } | |
3464 | ||
3465 | if (tag == DT_NULL) | |
3466 | break; | |
3467 | ||
3468 | addr += 16; | |
3469 | } | |
3470 | } | |
3471 | } | |
3472 | return 0; | |
3473 | } | |
3474 | ||
c4de7027 JB |
3475 | /* Attempt to find (and return) the global pointer for the given |
3476 | function. We first try the find_global_pointer_from_solib routine | |
3477 | from the gdbarch tdep vector, if provided. And if that does not | |
3478 | work, then we try ia64_find_global_pointer_from_dynamic_section. */ | |
3479 | ||
3480 | static CORE_ADDR | |
3481 | ia64_find_global_pointer (struct gdbarch *gdbarch, CORE_ADDR faddr) | |
3482 | { | |
3483 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3484 | CORE_ADDR addr = 0; | |
3485 | ||
3486 | if (tdep->find_global_pointer_from_solib) | |
3487 | addr = tdep->find_global_pointer_from_solib (gdbarch, faddr); | |
3488 | if (addr == 0) | |
3489 | addr = ia64_find_global_pointer_from_dynamic_section (gdbarch, faddr); | |
3490 | return addr; | |
3491 | } | |
3492 | ||
64a5b29c KB |
3493 | /* Given a function's address, attempt to find (and return) the |
3494 | corresponding (canonical) function descriptor. Return 0 if | |
004d836a | 3495 | not found. */ |
64a5b29c | 3496 | static CORE_ADDR |
e17a4113 | 3497 | find_extant_func_descr (struct gdbarch *gdbarch, CORE_ADDR faddr) |
64a5b29c | 3498 | { |
e17a4113 | 3499 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
76d689a6 | 3500 | struct obj_section *faddr_sect; |
64a5b29c | 3501 | |
004d836a | 3502 | /* Return early if faddr is already a function descriptor. */ |
76d689a6 KB |
3503 | faddr_sect = find_pc_section (faddr); |
3504 | if (faddr_sect && strcmp (faddr_sect->the_bfd_section->name, ".opd") == 0) | |
64a5b29c KB |
3505 | return faddr; |
3506 | ||
76d689a6 | 3507 | if (faddr_sect != NULL) |
64a5b29c | 3508 | { |
76d689a6 KB |
3509 | struct obj_section *osect; |
3510 | ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect) | |
64a5b29c KB |
3511 | { |
3512 | if (strcmp (osect->the_bfd_section->name, ".opd") == 0) | |
3513 | break; | |
3514 | } | |
3515 | ||
76d689a6 | 3516 | if (osect < faddr_sect->objfile->sections_end) |
64a5b29c | 3517 | { |
aded6f54 PA |
3518 | CORE_ADDR addr, endaddr; |
3519 | ||
3520 | addr = obj_section_addr (osect); | |
3521 | endaddr = obj_section_endaddr (osect); | |
64a5b29c | 3522 | |
aded6f54 | 3523 | while (addr < endaddr) |
64a5b29c KB |
3524 | { |
3525 | int status; | |
3526 | LONGEST faddr2; | |
e362b510 | 3527 | gdb_byte buf[8]; |
64a5b29c KB |
3528 | |
3529 | status = target_read_memory (addr, buf, sizeof (buf)); | |
3530 | if (status != 0) | |
3531 | break; | |
e17a4113 | 3532 | faddr2 = extract_signed_integer (buf, sizeof (buf), byte_order); |
64a5b29c KB |
3533 | |
3534 | if (faddr == faddr2) | |
3535 | return addr; | |
3536 | ||
3537 | addr += 16; | |
3538 | } | |
3539 | } | |
3540 | } | |
3541 | return 0; | |
3542 | } | |
3543 | ||
3544 | /* Attempt to find a function descriptor corresponding to the | |
3545 | given address. If none is found, construct one on the | |
004d836a | 3546 | stack using the address at fdaptr. */ |
64a5b29c KB |
3547 | |
3548 | static CORE_ADDR | |
9c9acae0 | 3549 | find_func_descr (struct regcache *regcache, CORE_ADDR faddr, CORE_ADDR *fdaptr) |
64a5b29c | 3550 | { |
ac7936df | 3551 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 3552 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
64a5b29c KB |
3553 | CORE_ADDR fdesc; |
3554 | ||
e17a4113 | 3555 | fdesc = find_extant_func_descr (gdbarch, faddr); |
64a5b29c KB |
3556 | |
3557 | if (fdesc == 0) | |
3558 | { | |
9c9acae0 | 3559 | ULONGEST global_pointer; |
e362b510 | 3560 | gdb_byte buf[16]; |
64a5b29c KB |
3561 | |
3562 | fdesc = *fdaptr; | |
3563 | *fdaptr += 16; | |
3564 | ||
e17a4113 | 3565 | global_pointer = ia64_find_global_pointer (gdbarch, faddr); |
64a5b29c KB |
3566 | |
3567 | if (global_pointer == 0) | |
9c9acae0 UW |
3568 | regcache_cooked_read_unsigned (regcache, |
3569 | IA64_GR1_REGNUM, &global_pointer); | |
64a5b29c | 3570 | |
e17a4113 UW |
3571 | store_unsigned_integer (buf, 8, byte_order, faddr); |
3572 | store_unsigned_integer (buf + 8, 8, byte_order, global_pointer); | |
64a5b29c KB |
3573 | |
3574 | write_memory (fdesc, buf, 16); | |
3575 | } | |
3576 | ||
3577 | return fdesc; | |
3578 | } | |
16461d7d | 3579 | |
af8b88dd JJ |
3580 | /* Use the following routine when printing out function pointers |
3581 | so the user can see the function address rather than just the | |
3582 | function descriptor. */ | |
3583 | static CORE_ADDR | |
e2d0e7eb AC |
3584 | ia64_convert_from_func_ptr_addr (struct gdbarch *gdbarch, CORE_ADDR addr, |
3585 | struct target_ops *targ) | |
af8b88dd | 3586 | { |
e17a4113 | 3587 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
af8b88dd | 3588 | struct obj_section *s; |
e453266f | 3589 | gdb_byte buf[8]; |
af8b88dd JJ |
3590 | |
3591 | s = find_pc_section (addr); | |
3592 | ||
3593 | /* check if ADDR points to a function descriptor. */ | |
3594 | if (s && strcmp (s->the_bfd_section->name, ".opd") == 0) | |
e17a4113 | 3595 | return read_memory_unsigned_integer (addr, 8, byte_order); |
af8b88dd | 3596 | |
fcac911a JB |
3597 | /* Normally, functions live inside a section that is executable. |
3598 | So, if ADDR points to a non-executable section, then treat it | |
3599 | as a function descriptor and return the target address iff | |
e453266f JK |
3600 | the target address itself points to a section that is executable. |
3601 | Check first the memory of the whole length of 8 bytes is readable. */ | |
3602 | if (s && (s->the_bfd_section->flags & SEC_CODE) == 0 | |
3603 | && target_read_memory (addr, buf, 8) == 0) | |
fcac911a | 3604 | { |
e453266f | 3605 | CORE_ADDR pc = extract_unsigned_integer (buf, 8, byte_order); |
fcac911a JB |
3606 | struct obj_section *pc_section = find_pc_section (pc); |
3607 | ||
3608 | if (pc_section && (pc_section->the_bfd_section->flags & SEC_CODE)) | |
3609 | return pc; | |
3610 | } | |
b1e6fd19 | 3611 | |
0d5de010 DJ |
3612 | /* There are also descriptors embedded in vtables. */ |
3613 | if (s) | |
3614 | { | |
7cbd4a93 | 3615 | struct bound_minimal_symbol minsym; |
0d5de010 DJ |
3616 | |
3617 | minsym = lookup_minimal_symbol_by_pc (addr); | |
3618 | ||
efd66ac6 TT |
3619 | if (minsym.minsym |
3620 | && is_vtable_name (MSYMBOL_LINKAGE_NAME (minsym.minsym))) | |
e17a4113 | 3621 | return read_memory_unsigned_integer (addr, 8, byte_order); |
0d5de010 DJ |
3622 | } |
3623 | ||
af8b88dd JJ |
3624 | return addr; |
3625 | } | |
3626 | ||
a78f21af | 3627 | static CORE_ADDR |
004d836a JJ |
3628 | ia64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) |
3629 | { | |
3630 | return sp & ~0xfLL; | |
3631 | } | |
3632 | ||
c4de7027 JB |
3633 | /* The default "allocate_new_rse_frame" ia64_infcall_ops routine for ia64. */ |
3634 | ||
3635 | static void | |
3636 | ia64_allocate_new_rse_frame (struct regcache *regcache, ULONGEST bsp, int sof) | |
3637 | { | |
3638 | ULONGEST cfm, pfs, new_bsp; | |
3639 | ||
3640 | regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm); | |
3641 | ||
3642 | new_bsp = rse_address_add (bsp, sof); | |
3643 | regcache_cooked_write_unsigned (regcache, IA64_BSP_REGNUM, new_bsp); | |
3644 | ||
3645 | regcache_cooked_read_unsigned (regcache, IA64_PFS_REGNUM, &pfs); | |
3646 | pfs &= 0xc000000000000000LL; | |
3647 | pfs |= (cfm & 0xffffffffffffLL); | |
3648 | regcache_cooked_write_unsigned (regcache, IA64_PFS_REGNUM, pfs); | |
3649 | ||
3650 | cfm &= 0xc000000000000000LL; | |
3651 | cfm |= sof; | |
3652 | regcache_cooked_write_unsigned (regcache, IA64_CFM_REGNUM, cfm); | |
3653 | } | |
3654 | ||
3655 | /* The default "store_argument_in_slot" ia64_infcall_ops routine for | |
3656 | ia64. */ | |
3657 | ||
3658 | static void | |
3659 | ia64_store_argument_in_slot (struct regcache *regcache, CORE_ADDR bsp, | |
3660 | int slotnum, gdb_byte *buf) | |
3661 | { | |
3662 | write_memory (rse_address_add (bsp, slotnum), buf, 8); | |
3663 | } | |
3664 | ||
3665 | /* The default "set_function_addr" ia64_infcall_ops routine for ia64. */ | |
3666 | ||
3667 | static void | |
3668 | ia64_set_function_addr (struct regcache *regcache, CORE_ADDR func_addr) | |
3669 | { | |
3670 | /* Nothing needed. */ | |
3671 | } | |
3672 | ||
004d836a | 3673 | static CORE_ADDR |
7d9b040b | 3674 | ia64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
8dd5115e AS |
3675 | struct regcache *regcache, CORE_ADDR bp_addr, |
3676 | int nargs, struct value **args, CORE_ADDR sp, | |
3677 | int struct_return, CORE_ADDR struct_addr) | |
16461d7d | 3678 | { |
c4de7027 | 3679 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 3680 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
16461d7d | 3681 | int argno; |
ea7c478f | 3682 | struct value *arg; |
16461d7d KB |
3683 | struct type *type; |
3684 | int len, argoffset; | |
64a5b29c | 3685 | int nslots, rseslots, memslots, slotnum, nfuncargs; |
16461d7d | 3686 | int floatreg; |
c4de7027 | 3687 | ULONGEST bsp; |
870f88f7 | 3688 | CORE_ADDR funcdescaddr, global_pointer; |
7d9b040b | 3689 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
16461d7d KB |
3690 | |
3691 | nslots = 0; | |
64a5b29c | 3692 | nfuncargs = 0; |
004d836a | 3693 | /* Count the number of slots needed for the arguments. */ |
16461d7d KB |
3694 | for (argno = 0; argno < nargs; argno++) |
3695 | { | |
3696 | arg = args[argno]; | |
4991999e | 3697 | type = check_typedef (value_type (arg)); |
16461d7d KB |
3698 | len = TYPE_LENGTH (type); |
3699 | ||
98f96ba1 | 3700 | if ((nslots & 1) && slot_alignment_is_next_even (type)) |
16461d7d KB |
3701 | nslots++; |
3702 | ||
64a5b29c KB |
3703 | if (TYPE_CODE (type) == TYPE_CODE_FUNC) |
3704 | nfuncargs++; | |
3705 | ||
16461d7d KB |
3706 | nslots += (len + 7) / 8; |
3707 | } | |
3708 | ||
004d836a | 3709 | /* Divvy up the slots between the RSE and the memory stack. */ |
16461d7d KB |
3710 | rseslots = (nslots > 8) ? 8 : nslots; |
3711 | memslots = nslots - rseslots; | |
3712 | ||
004d836a | 3713 | /* Allocate a new RSE frame. */ |
9c9acae0 | 3714 | regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp); |
c4de7027 | 3715 | tdep->infcall_ops.allocate_new_rse_frame (regcache, bsp, rseslots); |
16461d7d | 3716 | |
64a5b29c KB |
3717 | /* We will attempt to find function descriptors in the .opd segment, |
3718 | but if we can't we'll construct them ourselves. That being the | |
004d836a | 3719 | case, we'll need to reserve space on the stack for them. */ |
64a5b29c KB |
3720 | funcdescaddr = sp - nfuncargs * 16; |
3721 | funcdescaddr &= ~0xfLL; | |
3722 | ||
3723 | /* Adjust the stack pointer to it's new value. The calling conventions | |
3724 | require us to have 16 bytes of scratch, plus whatever space is | |
004d836a | 3725 | necessary for the memory slots and our function descriptors. */ |
64a5b29c | 3726 | sp = sp - 16 - (memslots + nfuncargs) * 8; |
004d836a | 3727 | sp &= ~0xfLL; /* Maintain 16 byte alignment. */ |
16461d7d | 3728 | |
64a5b29c KB |
3729 | /* Place the arguments where they belong. The arguments will be |
3730 | either placed in the RSE backing store or on the memory stack. | |
3731 | In addition, floating point arguments or HFAs are placed in | |
004d836a | 3732 | floating point registers. */ |
16461d7d KB |
3733 | slotnum = 0; |
3734 | floatreg = IA64_FR8_REGNUM; | |
3735 | for (argno = 0; argno < nargs; argno++) | |
3736 | { | |
64a5b29c KB |
3737 | struct type *float_elt_type; |
3738 | ||
16461d7d | 3739 | arg = args[argno]; |
4991999e | 3740 | type = check_typedef (value_type (arg)); |
16461d7d | 3741 | len = TYPE_LENGTH (type); |
64a5b29c | 3742 | |
004d836a | 3743 | /* Special handling for function parameters. */ |
64a5b29c KB |
3744 | if (len == 8 |
3745 | && TYPE_CODE (type) == TYPE_CODE_PTR | |
3746 | && TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC) | |
3747 | { | |
948f8e3d | 3748 | gdb_byte val_buf[8]; |
e17a4113 UW |
3749 | ULONGEST faddr = extract_unsigned_integer (value_contents (arg), |
3750 | 8, byte_order); | |
3751 | store_unsigned_integer (val_buf, 8, byte_order, | |
9c9acae0 | 3752 | find_func_descr (regcache, faddr, |
fbd9dcd3 | 3753 | &funcdescaddr)); |
64a5b29c | 3754 | if (slotnum < rseslots) |
c4de7027 JB |
3755 | tdep->infcall_ops.store_argument_in_slot (regcache, bsp, |
3756 | slotnum, val_buf); | |
64a5b29c KB |
3757 | else |
3758 | write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8); | |
3759 | slotnum++; | |
3760 | continue; | |
3761 | } | |
3762 | ||
004d836a | 3763 | /* Normal slots. */ |
98f96ba1 KB |
3764 | |
3765 | /* Skip odd slot if necessary... */ | |
3766 | if ((slotnum & 1) && slot_alignment_is_next_even (type)) | |
16461d7d | 3767 | slotnum++; |
98f96ba1 | 3768 | |
16461d7d KB |
3769 | argoffset = 0; |
3770 | while (len > 0) | |
3771 | { | |
948f8e3d | 3772 | gdb_byte val_buf[8]; |
16461d7d KB |
3773 | |
3774 | memset (val_buf, 0, 8); | |
825d6d8a JB |
3775 | if (!ia64_struct_type_p (type) && len < 8) |
3776 | { | |
3777 | /* Integral types are LSB-aligned, so we have to be careful | |
3778 | to insert the argument on the correct side of the buffer. | |
3779 | This is why we use store_unsigned_integer. */ | |
3780 | store_unsigned_integer | |
3781 | (val_buf, 8, byte_order, | |
3782 | extract_unsigned_integer (value_contents (arg), len, | |
3783 | byte_order)); | |
3784 | } | |
3785 | else | |
3786 | { | |
3787 | /* This is either an 8bit integral type, or an aggregate. | |
3788 | For 8bit integral type, there is no problem, we just | |
3789 | copy the value over. | |
3790 | ||
3791 | For aggregates, the only potentially tricky portion | |
3792 | is to write the last one if it is less than 8 bytes. | |
3793 | In this case, the data is Byte0-aligned. Happy news, | |
3794 | this means that we don't need to differentiate the | |
3795 | handling of 8byte blocks and less-than-8bytes blocks. */ | |
3796 | memcpy (val_buf, value_contents (arg) + argoffset, | |
3797 | (len > 8) ? 8 : len); | |
3798 | } | |
16461d7d KB |
3799 | |
3800 | if (slotnum < rseslots) | |
c4de7027 JB |
3801 | tdep->infcall_ops.store_argument_in_slot (regcache, bsp, |
3802 | slotnum, val_buf); | |
16461d7d KB |
3803 | else |
3804 | write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8); | |
3805 | ||
3806 | argoffset += 8; | |
3807 | len -= 8; | |
3808 | slotnum++; | |
3809 | } | |
64a5b29c | 3810 | |
004d836a | 3811 | /* Handle floating point types (including HFAs). */ |
64a5b29c KB |
3812 | float_elt_type = is_float_or_hfa_type (type); |
3813 | if (float_elt_type != NULL) | |
3814 | { | |
3815 | argoffset = 0; | |
3816 | len = TYPE_LENGTH (type); | |
3817 | while (len > 0 && floatreg < IA64_FR16_REGNUM) | |
3818 | { | |
ae0d01d6 | 3819 | gdb_byte to[IA64_FP_REGISTER_SIZE]; |
3b2ca824 UW |
3820 | target_float_convert (value_contents (arg) + argoffset, |
3821 | float_elt_type, to, | |
3822 | ia64_ext_type (gdbarch)); | |
b66f5587 | 3823 | regcache->cooked_write (floatreg, to); |
64a5b29c KB |
3824 | floatreg++; |
3825 | argoffset += TYPE_LENGTH (float_elt_type); | |
3826 | len -= TYPE_LENGTH (float_elt_type); | |
3827 | } | |
16461d7d KB |
3828 | } |
3829 | } | |
3830 | ||
004d836a | 3831 | /* Store the struct return value in r8 if necessary. */ |
16461d7d KB |
3832 | if (struct_return) |
3833 | { | |
1777feb0 MS |
3834 | regcache_cooked_write_unsigned (regcache, IA64_GR8_REGNUM, |
3835 | (ULONGEST) struct_addr); | |
16461d7d KB |
3836 | } |
3837 | ||
e17a4113 | 3838 | global_pointer = ia64_find_global_pointer (gdbarch, func_addr); |
8dd5115e | 3839 | |
004d836a | 3840 | if (global_pointer != 0) |
9c9acae0 | 3841 | regcache_cooked_write_unsigned (regcache, IA64_GR1_REGNUM, global_pointer); |
a59fe496 | 3842 | |
c4de7027 JB |
3843 | /* The following is not necessary on HP-UX, because we're using |
3844 | a dummy code sequence pushed on the stack to make the call, and | |
3845 | this sequence doesn't need b0 to be set in order for our dummy | |
3846 | breakpoint to be hit. Nonetheless, this doesn't interfere, and | |
3847 | it's needed for other OSes, so we do this unconditionaly. */ | |
9c9acae0 | 3848 | regcache_cooked_write_unsigned (regcache, IA64_BR0_REGNUM, bp_addr); |
16461d7d | 3849 | |
9c9acae0 | 3850 | regcache_cooked_write_unsigned (regcache, sp_regnum, sp); |
16461d7d | 3851 | |
c4de7027 JB |
3852 | tdep->infcall_ops.set_function_addr (regcache, func_addr); |
3853 | ||
16461d7d KB |
3854 | return sp; |
3855 | } | |
3856 | ||
c4de7027 JB |
3857 | static const struct ia64_infcall_ops ia64_infcall_ops = |
3858 | { | |
3859 | ia64_allocate_new_rse_frame, | |
3860 | ia64_store_argument_in_slot, | |
3861 | ia64_set_function_addr | |
3862 | }; | |
3863 | ||
004d836a | 3864 | static struct frame_id |
15c1e57f | 3865 | ia64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
16461d7d | 3866 | { |
e17a4113 | 3867 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
e362b510 | 3868 | gdb_byte buf[8]; |
4afcc598 | 3869 | CORE_ADDR sp, bsp; |
004d836a | 3870 | |
15c1e57f | 3871 | get_frame_register (this_frame, sp_regnum, buf); |
e17a4113 | 3872 | sp = extract_unsigned_integer (buf, 8, byte_order); |
004d836a | 3873 | |
15c1e57f | 3874 | get_frame_register (this_frame, IA64_BSP_REGNUM, buf); |
e17a4113 | 3875 | bsp = extract_unsigned_integer (buf, 8, byte_order); |
4afcc598 JJ |
3876 | |
3877 | if (gdbarch_debug >= 1) | |
3878 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
3879 | "dummy frame id: code %s, stack %s, special %s\n", |
3880 | paddress (gdbarch, get_frame_pc (this_frame)), | |
3881 | paddress (gdbarch, sp), paddress (gdbarch, bsp)); | |
4afcc598 | 3882 | |
15c1e57f | 3883 | return frame_id_build_special (sp, get_frame_pc (this_frame), bsp); |
16461d7d KB |
3884 | } |
3885 | ||
004d836a JJ |
3886 | static CORE_ADDR |
3887 | ia64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
16461d7d | 3888 | { |
e17a4113 | 3889 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
e362b510 | 3890 | gdb_byte buf[8]; |
004d836a JJ |
3891 | CORE_ADDR ip, psr, pc; |
3892 | ||
3893 | frame_unwind_register (next_frame, IA64_IP_REGNUM, buf); | |
e17a4113 | 3894 | ip = extract_unsigned_integer (buf, 8, byte_order); |
004d836a | 3895 | frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf); |
e17a4113 | 3896 | psr = extract_unsigned_integer (buf, 8, byte_order); |
004d836a JJ |
3897 | |
3898 | pc = (ip & ~0xf) | ((psr >> 41) & 3); | |
3899 | return pc; | |
16461d7d KB |
3900 | } |
3901 | ||
6926787d AS |
3902 | static int |
3903 | ia64_print_insn (bfd_vma memaddr, struct disassemble_info *info) | |
3904 | { | |
3905 | info->bytes_per_line = SLOT_MULTIPLIER; | |
6394c606 | 3906 | return default_print_insn (memaddr, info); |
6926787d AS |
3907 | } |
3908 | ||
77ca787b JB |
3909 | /* The default "size_of_register_frame" gdbarch_tdep routine for ia64. */ |
3910 | ||
3911 | static int | |
3912 | ia64_size_of_register_frame (struct frame_info *this_frame, ULONGEST cfm) | |
3913 | { | |
3914 | return (cfm & 0x7f); | |
3915 | } | |
3916 | ||
16461d7d KB |
3917 | static struct gdbarch * |
3918 | ia64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
3919 | { | |
3920 | struct gdbarch *gdbarch; | |
244bc108 | 3921 | struct gdbarch_tdep *tdep; |
244bc108 | 3922 | |
85bf2b91 JJ |
3923 | /* If there is already a candidate, use it. */ |
3924 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
3925 | if (arches != NULL) | |
3926 | return arches->gdbarch; | |
16461d7d | 3927 | |
8d749320 | 3928 | tdep = XCNEW (struct gdbarch_tdep); |
244bc108 | 3929 | gdbarch = gdbarch_alloc (&info, tdep); |
244bc108 | 3930 | |
77ca787b JB |
3931 | tdep->size_of_register_frame = ia64_size_of_register_frame; |
3932 | ||
5439edaa AC |
3933 | /* According to the ia64 specs, instructions that store long double |
3934 | floats in memory use a long-double format different than that | |
3935 | used in the floating registers. The memory format matches the | |
3936 | x86 extended float format which is 80 bits. An OS may choose to | |
3937 | use this format (e.g. GNU/Linux) or choose to use a different | |
3938 | format for storing long doubles (e.g. HPUX). In the latter case, | |
3939 | the setting of the format may be moved/overridden in an | |
3940 | OS-specific tdep file. */ | |
8da61cc4 | 3941 | set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext); |
32edc941 | 3942 | |
16461d7d KB |
3943 | set_gdbarch_short_bit (gdbarch, 16); |
3944 | set_gdbarch_int_bit (gdbarch, 32); | |
3945 | set_gdbarch_long_bit (gdbarch, 64); | |
3946 | set_gdbarch_long_long_bit (gdbarch, 64); | |
3947 | set_gdbarch_float_bit (gdbarch, 32); | |
3948 | set_gdbarch_double_bit (gdbarch, 64); | |
33c08150 | 3949 | set_gdbarch_long_double_bit (gdbarch, 128); |
16461d7d KB |
3950 | set_gdbarch_ptr_bit (gdbarch, 64); |
3951 | ||
004d836a | 3952 | set_gdbarch_num_regs (gdbarch, NUM_IA64_RAW_REGS); |
1777feb0 MS |
3953 | set_gdbarch_num_pseudo_regs (gdbarch, |
3954 | LAST_PSEUDO_REGNUM - FIRST_PSEUDO_REGNUM); | |
16461d7d | 3955 | set_gdbarch_sp_regnum (gdbarch, sp_regnum); |
698cb3f0 | 3956 | set_gdbarch_fp0_regnum (gdbarch, IA64_FR0_REGNUM); |
16461d7d KB |
3957 | |
3958 | set_gdbarch_register_name (gdbarch, ia64_register_name); | |
004d836a | 3959 | set_gdbarch_register_type (gdbarch, ia64_register_type); |
16461d7d | 3960 | |
004d836a JJ |
3961 | set_gdbarch_pseudo_register_read (gdbarch, ia64_pseudo_register_read); |
3962 | set_gdbarch_pseudo_register_write (gdbarch, ia64_pseudo_register_write); | |
3963 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, ia64_dwarf_reg_to_regnum); | |
3964 | set_gdbarch_register_reggroup_p (gdbarch, ia64_register_reggroup_p); | |
3965 | set_gdbarch_convert_register_p (gdbarch, ia64_convert_register_p); | |
3966 | set_gdbarch_register_to_value (gdbarch, ia64_register_to_value); | |
3967 | set_gdbarch_value_to_register (gdbarch, ia64_value_to_register); | |
16461d7d | 3968 | |
004d836a | 3969 | set_gdbarch_skip_prologue (gdbarch, ia64_skip_prologue); |
16461d7d | 3970 | |
4c8b6ae0 | 3971 | set_gdbarch_return_value (gdbarch, ia64_return_value); |
16461d7d | 3972 | |
1777feb0 MS |
3973 | set_gdbarch_memory_insert_breakpoint (gdbarch, |
3974 | ia64_memory_insert_breakpoint); | |
3975 | set_gdbarch_memory_remove_breakpoint (gdbarch, | |
3976 | ia64_memory_remove_breakpoint); | |
16461d7d | 3977 | set_gdbarch_breakpoint_from_pc (gdbarch, ia64_breakpoint_from_pc); |
cd6c3b4f | 3978 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, ia64_breakpoint_kind_from_pc); |
16461d7d | 3979 | set_gdbarch_read_pc (gdbarch, ia64_read_pc); |
b33e8514 | 3980 | set_gdbarch_write_pc (gdbarch, ia64_write_pc); |
16461d7d KB |
3981 | |
3982 | /* Settings for calling functions in the inferior. */ | |
8dd5115e | 3983 | set_gdbarch_push_dummy_call (gdbarch, ia64_push_dummy_call); |
c4de7027 | 3984 | tdep->infcall_ops = ia64_infcall_ops; |
004d836a | 3985 | set_gdbarch_frame_align (gdbarch, ia64_frame_align); |
15c1e57f | 3986 | set_gdbarch_dummy_id (gdbarch, ia64_dummy_id); |
16461d7d | 3987 | |
004d836a | 3988 | set_gdbarch_unwind_pc (gdbarch, ia64_unwind_pc); |
968d1cb4 | 3989 | #ifdef HAVE_LIBUNWIND_IA64_H |
15c1e57f JB |
3990 | frame_unwind_append_unwinder (gdbarch, |
3991 | &ia64_libunwind_sigtramp_frame_unwind); | |
3992 | frame_unwind_append_unwinder (gdbarch, &ia64_libunwind_frame_unwind); | |
3993 | frame_unwind_append_unwinder (gdbarch, &ia64_sigtramp_frame_unwind); | |
968d1cb4 | 3994 | libunwind_frame_set_descr (gdbarch, &ia64_libunwind_descr); |
c5a27d9c | 3995 | #else |
15c1e57f | 3996 | frame_unwind_append_unwinder (gdbarch, &ia64_sigtramp_frame_unwind); |
968d1cb4 | 3997 | #endif |
15c1e57f | 3998 | frame_unwind_append_unwinder (gdbarch, &ia64_frame_unwind); |
004d836a | 3999 | frame_base_set_default (gdbarch, &ia64_frame_base); |
16461d7d KB |
4000 | |
4001 | /* Settings that should be unnecessary. */ | |
4002 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
4003 | ||
6926787d | 4004 | set_gdbarch_print_insn (gdbarch, ia64_print_insn); |
1777feb0 MS |
4005 | set_gdbarch_convert_from_func_ptr_addr (gdbarch, |
4006 | ia64_convert_from_func_ptr_addr); | |
6926787d | 4007 | |
0d5de010 DJ |
4008 | /* The virtual table contains 16-byte descriptors, not pointers to |
4009 | descriptors. */ | |
4010 | set_gdbarch_vtable_function_descriptors (gdbarch, 1); | |
4011 | ||
b33e8514 AS |
4012 | /* Hook in ABI-specific overrides, if they have been registered. */ |
4013 | gdbarch_init_osabi (info, gdbarch); | |
4014 | ||
16461d7d KB |
4015 | return gdbarch; |
4016 | } | |
4017 | ||
4018 | void | |
4019 | _initialize_ia64_tdep (void) | |
4020 | { | |
b33e8514 | 4021 | gdbarch_register (bfd_arch_ia64, ia64_gdbarch_init, NULL); |
16461d7d | 4022 | } |