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It turns out that 1.2 wasn't botched after all. (I was failing to take
[deliverable/binutils-gdb.git] / gdb / ia64-tdep.c
CommitLineData
16461d7d
KB		 1/* Target-dependent code for the IA-64 for GDB, the GNU debugger.
2 Copyright 1999, 2000
3 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22#include "defs.h"
23#include "inferior.h"
24#include "symfile.h" /* for entry_point_address */
25#include "gdbcore.h"
26#include "floatformat.h"
27
28#include "objfiles.h"
29#include "elf/common.h" /* for DT_PLTGOT value */
30
31typedef enum instruction_type
32{
33 A, /* Integer ALU ; I-unit or M-unit */
34 I, /* Non-ALU integer; I-unit */
35 M, /* Memory ; M-unit */
36 F, /* Floating-point ; F-unit */
37 B, /* Branch ; B-unit */
38 L, /* Extended (L+X) ; I-unit */
39 X, /* Extended (L+X) ; I-unit */
40 undefined /* undefined or reserved */
41} instruction_type;
42
43/* We represent IA-64 PC addresses as the value of the instruction
44 pointer or'd with some bit combination in the low nibble which
45 represents the slot number in the bundle addressed by the
46 instruction pointer. The problem is that the Linux kernel
47 multiplies its slot numbers (for exceptions) by one while the
48 disassembler multiplies its slot numbers by 6. In addition, I've
49 heard it said that the simulator uses 1 as the multiplier.
50
51 I've fixed the disassembler so that the bytes_per_line field will
52 be the slot multiplier. If bytes_per_line comes in as zero, it
53 is set to six (which is how it was set up initially). -- objdump
54 displays pretty disassembly dumps with this value. For our purposes,
55 we'll set bytes_per_line to SLOT_MULTIPLIER. This is okay since we
56 never want to also display the raw bytes the way objdump does. */
57
58#define SLOT_MULTIPLIER 1
59
60/* Length in bytes of an instruction bundle */
61
62#define BUNDLE_LEN 16
63
64extern void _initialize_ia64_tdep (void);
65
66static gdbarch_init_ftype ia64_gdbarch_init;
67
68static gdbarch_register_name_ftype ia64_register_name;
69static gdbarch_register_raw_size_ftype ia64_register_raw_size;
70static gdbarch_register_virtual_size_ftype ia64_register_virtual_size;
71static gdbarch_register_virtual_type_ftype ia64_register_virtual_type;
72static gdbarch_register_byte_ftype ia64_register_byte;
73static gdbarch_breakpoint_from_pc_ftype ia64_breakpoint_from_pc;
74static gdbarch_frame_chain_ftype ia64_frame_chain;
75static gdbarch_frame_saved_pc_ftype ia64_frame_saved_pc;
76static gdbarch_skip_prologue_ftype ia64_skip_prologue;
77static gdbarch_frame_init_saved_regs_ftype ia64_frame_init_saved_regs;
78static gdbarch_get_saved_register_ftype ia64_get_saved_register;
79static gdbarch_extract_return_value_ftype ia64_extract_return_value;
80static gdbarch_extract_struct_value_address_ftype ia64_extract_struct_value_address;
81static gdbarch_use_struct_convention_ftype ia64_use_struct_convention;
82static gdbarch_frameless_function_invocation_ftype ia64_frameless_function_invocation;
83static gdbarch_init_extra_frame_info_ftype ia64_init_extra_frame_info;
84static gdbarch_store_return_value_ftype ia64_store_return_value;
85static gdbarch_store_struct_return_ftype ia64_store_struct_return;
86static gdbarch_push_arguments_ftype ia64_push_arguments;
87static gdbarch_push_return_address_ftype ia64_push_return_address;
88static gdbarch_pop_frame_ftype ia64_pop_frame;
89static gdbarch_saved_pc_after_call_ftype ia64_saved_pc_after_call;
90
91static void ia64_pop_frame_regular (struct frame_info *frame);
92
93static int ia64_num_regs = 590;
94
95static int pc_regnum = IA64_IP_REGNUM;
96static int sp_regnum = IA64_GR12_REGNUM;
97static int fp_regnum = IA64_VFP_REGNUM;
98static int lr_regnum = IA64_VRAP_REGNUM;
99
100static LONGEST ia64_call_dummy_words[] = {0};
101
102/* Array of register names; There should be ia64_num_regs strings in
103 the initializer. */
104
105static char *ia64_register_names[] =
106{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
107 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
108 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
109 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
110 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
111 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
112 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
113 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
114 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
115 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
116 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
117 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
118 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
119 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
120 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
121 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
122
123 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
124 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
125 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
126 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
127 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
128 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
129 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
130 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
131 "f64", "f65", "f66", "f67", "f68", "f69", "f70", "f71",
132 "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79",
133 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87",
134 "f88", "f89", "f90", "f91", "f92", "f93", "f94", "f95",
135 "f96", "f97", "f98", "f99", "f100", "f101", "f102", "f103",
136 "f104", "f105", "f106", "f107", "f108", "f109", "f110", "f111",
137 "f112", "f113", "f114", "f115", "f116", "f117", "f118", "f119",
138 "f120", "f121", "f122", "f123", "f124", "f125", "f126", "f127",
139
140 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7",
141 "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15",
142 "p16", "p17", "p18", "p19", "p20", "p21", "p22", "p23",
143 "p24", "p25", "p26", "p27", "p28", "p29", "p30", "p31",
144 "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39",
145 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47",
146 "p48", "p49", "p50", "p51", "p52", "p53", "p54", "p55",
147 "p56", "p57", "p58", "p59", "p60", "p61", "p62", "p63",
148
149 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
150
151 "vfp", "vrap",
152
153 "pr", "ip", "psr", "cfm",
154
155 "kr0", "kr1", "kr2", "kr3", "kr4", "kr5", "kr6", "kr7",
156 "", "", "", "", "", "", "", "",
157 "rsc", "bsp", "bspstore", "rnat",
158 "", "fcr", "", "",
159 "eflag", "csd", "ssd", "cflg", "fsr", "fir", "fdr", "",
160 "ccv", "", "", "", "unat", "", "", "",
161 "fpsr", "", "", "", "itc",
162 "", "", "", "", "", "", "", "", "", "",
163 "", "", "", "", "", "", "", "", "",
164 "pfs", "lc", "ec",
165 "", "", "", "", "", "", "", "", "", "",
166 "", "", "", "", "", "", "", "", "", "",
167 "", "", "", "", "", "", "", "", "", "",
168 "", "", "", "", "", "", "", "", "", "",
169 "", "", "", "", "", "", "", "", "", "",
170 "", "", "", "", "", "", "", "", "", "",
171 "",
172 "nat0", "nat1", "nat2", "nat3", "nat4", "nat5", "nat6", "nat7",
173 "nat8", "nat9", "nat10", "nat11", "nat12", "nat13", "nat14", "nat15",
174 "nat16", "nat17", "nat18", "nat19", "nat20", "nat21", "nat22", "nat23",
175 "nat24", "nat25", "nat26", "nat27", "nat28", "nat29", "nat30", "nat31",
176 "nat32", "nat33", "nat34", "nat35", "nat36", "nat37", "nat38", "nat39",
177 "nat40", "nat41", "nat42", "nat43", "nat44", "nat45", "nat46", "nat47",
178 "nat48", "nat49", "nat50", "nat51", "nat52", "nat53", "nat54", "nat55",
179 "nat56", "nat57", "nat58", "nat59", "nat60", "nat61", "nat62", "nat63",
180 "nat64", "nat65", "nat66", "nat67", "nat68", "nat69", "nat70", "nat71",
181 "nat72", "nat73", "nat74", "nat75", "nat76", "nat77", "nat78", "nat79",
182 "nat80", "nat81", "nat82", "nat83", "nat84", "nat85", "nat86", "nat87",
183 "nat88", "nat89", "nat90", "nat91", "nat92", "nat93", "nat94", "nat95",
184 "nat96", "nat97", "nat98", "nat99", "nat100","nat101","nat102","nat103",
185 "nat104","nat105","nat106","nat107","nat108","nat109","nat110","nat111",
186 "nat112","nat113","nat114","nat115","nat116","nat117","nat118","nat119",
187 "nat120","nat121","nat122","nat123","nat124","nat125","nat126","nat127",
188};
189
190struct frame_extra_info
191{
192 CORE_ADDR bsp; /* points at r32 for the current frame */
193 CORE_ADDR cfm; /* cfm value for current frame */
194 int sof; /* Size of frame (decoded from cfm value) */
195 int sol; /* Size of locals (decoded from cfm value) */
196 CORE_ADDR after_prologue;
197 /* Address of first instruction after the last
198 prologue instruction; Note that there may
199 be instructions from the function's body
200 intermingled with the prologue. */
201 int mem_stack_frame_size;
202 /* Size of the memory stack frame (may be zero),
203 or -1 if it has not been determined yet. */
204 int fp_reg; /* Register number (if any) used a frame pointer
205 for this frame. 0 if no register is being used
206 as the frame pointer. */
207};
208
209static char *
210ia64_register_name (int reg)
211{
212 return ia64_register_names[reg];
213}
214
215int
216ia64_register_raw_size (int reg)
217{
218 return (IA64_FR0_REGNUM <= reg && reg <= IA64_FR127_REGNUM) ? 16 : 8;
219}
220
221int
222ia64_register_virtual_size (int reg)
223{
224 return (IA64_FR0_REGNUM <= reg && reg <= IA64_FR127_REGNUM) ? 16 : 8;
225}
226
227/* Return true iff register N's virtual format is different from
228 its raw format. */
229int
230ia64_register_convertible (int nr)
231{
232 return (IA64_FR0_REGNUM <= nr && nr <= IA64_FR127_REGNUM);
233}
234
235const struct floatformat floatformat_ia64_ext =
236{
237 floatformat_little, 82, 0, 1, 17, 65535, 0x1ffff, 18, 64,
238 floatformat_intbit_yes
239};
240
241void
242ia64_register_convert_to_virtual (int regnum, struct type *type,
243 char *from, char *to)
244{
245 if (regnum >= IA64_FR0_REGNUM && regnum <= IA64_FR127_REGNUM)
246 {
247 DOUBLEST val;
248 floatformat_to_doublest (&floatformat_ia64_ext, from, &val);
249 store_floating(to, TYPE_LENGTH(type), val);
250 }
251 else
252 error("ia64_register_convert_to_virtual called with non floating point register number");
253}
254
255void
256ia64_register_convert_to_raw (struct type *type, int regnum,
257 char *from, char *to)
258{
259 if (regnum >= IA64_FR0_REGNUM && regnum <= IA64_FR127_REGNUM)
260 {
261 DOUBLEST val = extract_floating (from, TYPE_LENGTH(type));
262 floatformat_from_doublest (&floatformat_ia64_ext, &val, to);
263 }
264 else
265 error("ia64_register_convert_to_raw called with non floating point register number");
266}
267
268struct type *
269ia64_register_virtual_type (int reg)
270{
271 if (reg >= IA64_FR0_REGNUM && reg <= IA64_FR127_REGNUM)
272 return builtin_type_long_double;
273 else
274 return builtin_type_long;
275}
276
277int
278ia64_register_byte (int reg)
279{
280 return (8 * reg) +
281 (reg <= IA64_FR0_REGNUM ? 0 : 8 * ((reg > IA64_FR127_REGNUM) ? 128 : reg - IA64_FR0_REGNUM));
282}
283
284/* Extract ``len'' bits from an instruction bundle starting at
285 bit ``from''. */
286
287long long
288extract_bit_field (char *bundle, int from, int len)
289{
290 long long result = 0LL;
291 int to = from + len;
292 int from_byte = from / 8;
293 int to_byte = to / 8;
294 unsigned char *b = (unsigned char *) bundle;
295 unsigned char c;
296 int lshift;
297 int i;
298
299 c = b[from_byte];
300 if (from_byte == to_byte)
301 c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
302 result = c >> (from % 8);
303 lshift = 8 - (from % 8);
304
305 for (i = from_byte+1; i < to_byte; i++)
306 {
307 result |= ((long long) b[i]) << lshift;
308 lshift += 8;
309 }
310
311 if (from_byte < to_byte && (to % 8 != 0))
312 {
313 c = b[to_byte];
314 c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
315 result |= ((long long) c) << lshift;
316 }
317
318 return result;
319}
320
321/* Replace the specified bits in an instruction bundle */
322
323void
324replace_bit_field (char *bundle, long long val, int from, int len)
325{
326 int to = from + len;
327 int from_byte = from / 8;
328 int to_byte = to / 8;
329 unsigned char *b = (unsigned char *) bundle;
330 unsigned char c;
331
332 if (from_byte == to_byte)
333 {
334 unsigned char left, right;
335 c = b[from_byte];
336 left = (c >> (to % 8)) << (to % 8);
337 right = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
338 c = (unsigned char) (val & 0xff);
339 c = (unsigned char) (c << (from % 8 + 8 - to % 8)) >> (8 - to % 8);
340 c |= right | left;
341 b[from_byte] = c;
342 }
343 else
344 {
345 int i;
346 c = b[from_byte];
347 c = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
348 c = c | (val << (from % 8));
349 b[from_byte] = c;
350 val >>= 8 - from % 8;
351
352 for (i = from_byte+1; i < to_byte; i++)
353 {
354 c = val & 0xff;
355 val >>= 8;
356 b[i] = c;
357 }
358
359 if (to % 8 != 0)
360 {
361 unsigned char cv = (unsigned char) val;
362 c = b[to_byte];
363 c = c >> (to % 8) << (to % 8);
364 c |= ((unsigned char) (cv << (8 - to % 8))) >> (8 - to % 8);
365 b[to_byte] = c;
366 }
367 }
368}
369
370/* Return the contents of slot N (for N = 0, 1, or 2) in
371 and instruction bundle */
372
373long long
374slotN_contents (unsigned char *bundle, int slotnum)
375{
376 return extract_bit_field (bundle, 5+41*slotnum, 41);
377}
378
379/* Store an instruction in an instruction bundle */
380
381void
382replace_slotN_contents (unsigned char *bundle, long long instr, int slotnum)
383{
384 replace_bit_field (bundle, instr, 5+41*slotnum, 41);
385}
386
387static template_encoding_table[32][3] =
388{
389 { M, I, I }, /* 00 */
390 { M, I, I }, /* 01 */
391 { M, I, I }, /* 02 */
392 { M, I, I }, /* 03 */
393 { M, L, X }, /* 04 */
394 { M, L, X }, /* 05 */
395 { undefined, undefined, undefined }, /* 06 */
396 { undefined, undefined, undefined }, /* 07 */
397 { M, M, I }, /* 08 */
398 { M, M, I }, /* 09 */
399 { M, M, I }, /* 0A */
400 { M, M, I }, /* 0B */
401 { M, F, I }, /* 0C */
402 { M, F, I }, /* 0D */
403 { M, M, F }, /* 0E */
404 { M, M, F }, /* 0F */
405 { M, I, B }, /* 10 */
406 { M, I, B }, /* 11 */
407 { M, B, B }, /* 12 */
408 { M, B, B }, /* 13 */
409 { undefined, undefined, undefined }, /* 14 */
410 { undefined, undefined, undefined }, /* 15 */
411 { B, B, B }, /* 16 */
412 { B, B, B }, /* 17 */
413 { M, M, B }, /* 18 */
414 { M, M, B }, /* 19 */
415 { undefined, undefined, undefined }, /* 1A */
416 { undefined, undefined, undefined }, /* 1B */
417 { M, F, B }, /* 1C */
418 { M, F, B }, /* 1D */
419 { undefined, undefined, undefined }, /* 1E */
420 { undefined, undefined, undefined }, /* 1F */
421};
422
423/* Fetch and (partially) decode an instruction at ADDR and return the
424 address of the next instruction to fetch. */
425
426static CORE_ADDR
427fetch_instruction (CORE_ADDR addr, instruction_type *it, long long *instr)
428{
429 char bundle[BUNDLE_LEN];
430 int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER;
431 long long template;
432 int val;
433
434 if (slotnum > 2)
435 error("Can't fetch instructions for slot numbers greater than 2.");
436
437 addr &= ~0x0f;
438
439 val = target_read_memory (addr, bundle, BUNDLE_LEN);
440
441 if (val != 0)
442 return 0;
443
444 *instr = slotN_contents (bundle, slotnum);
445 template = extract_bit_field (bundle, 0, 5);
446 *it = template_encoding_table[(int)template][slotnum];
447
448 if (slotnum == 2 || slotnum == 1 && *it == L)
449 addr += 16;
450 else
451 addr += (slotnum + 1) * SLOT_MULTIPLIER;
452
453 return addr;
454}
455
456/* There are 5 different break instructions (break.i, break.b,
457 break.m, break.f, and break.x), but they all have the same
458 encoding. (The five bit template in the low five bits of the
459 instruction bundle distinguishes one from another.)
460
461 The runtime architecture manual specifies that break instructions
462 used for debugging purposes must have the upper two bits of the 21
463 bit immediate set to a 0 and a 1 respectively. A breakpoint
464 instruction encodes the most significant bit of its 21 bit
465 immediate at bit 36 of the 41 bit instruction. The penultimate msb
466 is at bit 25 which leads to the pattern below.
467
468 Originally, I had this set up to do, e.g, a "break.i 0x80000" But
469 it turns out that 0x80000 was used as the syscall break in the early
470 simulators. So I changed the pattern slightly to do "break.i 0x080001"
471 instead. But that didn't work either (I later found out that this
472 pattern was used by the simulator that I was using.) So I ended up
473 using the pattern seen below. */
474
475#if 0
476#define BREAKPOINT 0x00002000040LL
477#endif
478#define BREAKPOINT 0x00003333300LL
479
480static int
481ia64_memory_insert_breakpoint (CORE_ADDR addr, char *contents_cache)
482{
483 char bundle[BUNDLE_LEN];
484 int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER;
485 long long instr;
486 int val;
487
488 if (slotnum > 2)
489 error("Can't insert breakpoint for slot numbers greater than 2.");
490
491 addr &= ~0x0f;
492
493 val = target_read_memory (addr, bundle, BUNDLE_LEN);
494 instr = slotN_contents (bundle, slotnum);
495 memcpy(contents_cache, &instr, sizeof(instr));
496 replace_slotN_contents (bundle, BREAKPOINT, slotnum);
497 if (val == 0)
498 target_write_memory (addr, bundle, BUNDLE_LEN);
499
500 return val;
501}
502
503static int
504ia64_memory_remove_breakpoint (CORE_ADDR addr, char *contents_cache)
505{
506 char bundle[BUNDLE_LEN];
507 int slotnum = (addr & 0x0f) / SLOT_MULTIPLIER;
508 long long instr;
509 int val;
510
511 addr &= ~0x0f;
512
513 val = target_read_memory (addr, bundle, BUNDLE_LEN);
514 memcpy (&instr, contents_cache, sizeof instr);
515 replace_slotN_contents (bundle, instr, slotnum);
516 if (val == 0)
517 target_write_memory (addr, bundle, BUNDLE_LEN);
518
519 return val;
520}
521
522/* We don't really want to use this, but remote.c needs to call it in order
523 to figure out if Z-packets are supported or not. Oh, well. */
524unsigned char *
525ia64_breakpoint_from_pc (pcptr, lenptr)
526 CORE_ADDR *pcptr;
527 int *lenptr;
528{
529 static unsigned char breakpoint[] =
530 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
531 *lenptr = sizeof (breakpoint);
532#if 0
533 *pcptr &= ~0x0f;
534#endif
535 return breakpoint;
536}
537
538CORE_ADDR
539ia64_read_pc (int pid)
540{
541 CORE_ADDR psr_value = read_register_pid (IA64_PSR_REGNUM, pid);
542 CORE_ADDR pc_value = read_register_pid (IA64_IP_REGNUM, pid);
543 int slot_num = (psr_value >> 41) & 3;
544
545 return pc_value | (slot_num * SLOT_MULTIPLIER);
546}
547
548void
549ia64_write_pc (CORE_ADDR new_pc, int pid)
550{
551 int slot_num = (int) (new_pc & 0xf) / SLOT_MULTIPLIER;
552 CORE_ADDR psr_value = read_register_pid (IA64_PSR_REGNUM, pid);
553 psr_value &= ~(3LL << 41);
554 psr_value |= (CORE_ADDR)(slot_num & 0x3) << 41;
555
556 new_pc &= ~0xfLL;
557
558 write_register_pid (IA64_PSR_REGNUM, psr_value, pid);
559 write_register_pid (IA64_IP_REGNUM, new_pc, pid);
560}
561
562#define IS_NaT_COLLECTION_ADDR(addr) ((((addr) >> 3) & 0x3f) == 0x3f)
563
564/* Returns the address of the slot that's NSLOTS slots away from
565 the address ADDR. NSLOTS may be positive or negative. */
566static CORE_ADDR
567rse_address_add(CORE_ADDR addr, int nslots)
568{
569 CORE_ADDR new_addr;
570 int mandatory_nat_slots = nslots / 63;
571 int direction = nslots < 0 ? -1 : 1;
572
573 new_addr = addr + 8 * (nslots + mandatory_nat_slots);
574
575 if ((new_addr >> 9) != ((addr + 8 * 64 * mandatory_nat_slots) >> 9))
576 new_addr += 8 * direction;
577
578 if (IS_NaT_COLLECTION_ADDR(new_addr))
579 new_addr += 8 * direction;
580
581 return new_addr;
582}
583
584/* The IA-64 frame chain is a bit odd. We won't always have a frame
585 pointer, so we use the SP value as the FP for the purpose of
586 creating a frame. There is sometimes a register (not fixed) which
587 is used as a frame pointer. When this register exists, it is not
588 especially hard to determine which one is being used. It isn't
589 even really hard to compute the frame chain, but it can be
590 computationally expensive. So, instead of making life difficult
591 (and slow), we pick a more convenient representation of the frame
592 chain, knowing that we'll have to make some small adjustments
593 in other places. (E.g, note that read_fp() and write_fp() are
594 actually read_sp() and write_sp() below in ia64_gdbarch_init()
595 below.)
596
597 Okay, so what is the frame chain exactly? It'll be the SP value
598 at the time that the function in question was entered.
599
600 Note that this *should* actually the frame pointer for the current
601 function! But as I note above, if we were to attempt to find the
602 address of the beginning of the previous frame, we'd waste a lot
603 of cycles for no good reason. So instead, we simply choose to
604 represent the frame chain as the end of the previous frame instead
605 of the beginning. */
606
607CORE_ADDR
608ia64_frame_chain (struct frame_info *frame)
609{
610 FRAME_INIT_SAVED_REGS (frame);
611
612 if (frame->saved_regs[IA64_VFP_REGNUM])
613 return read_memory_integer (frame->saved_regs[IA64_VFP_REGNUM], 8);
614 else
615 return frame->frame + frame->extra_info->mem_stack_frame_size;
616}
617
618CORE_ADDR
619ia64_frame_saved_pc (struct frame_info *frame)
620{
621 FRAME_INIT_SAVED_REGS (frame);
622
623 if (frame->saved_regs[IA64_VRAP_REGNUM])
624 return read_memory_integer (frame->saved_regs[IA64_VRAP_REGNUM], 8);
625 else /* either frameless, or not far enough along in the prologue... */
626 return ia64_saved_pc_after_call (frame);
627}
628
629#define isScratch(_regnum_) ((_regnum_) == 2 || (_regnum_) == 3 \
630 || (8 <= (_regnum_) && (_regnum_) <= 11) \
631 || (14 <= (_regnum_) && (_regnum_) <= 31))
632#define imm9(_instr_) \
633 ( ((((_instr_) & 0x01000000000LL) ? -1 : 0) << 8) \
634 | (((_instr_) & 0x00008000000LL) >> 20) \
635 | (((_instr_) & 0x00000001fc0LL) >> 6))
636
637static CORE_ADDR
638examine_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct frame_info *frame)
639{
640 CORE_ADDR next_pc;
641 CORE_ADDR last_prologue_pc = pc;
642 int done = 0;
643 instruction_type it;
644 long long instr;
645 int do_fsr_stuff = 0;
646
647 int cfm_reg = 0;
648 int ret_reg = 0;
649 int fp_reg = 0;
650 int unat_save_reg = 0;
651 int pr_save_reg = 0;
652 int mem_stack_frame_size = 0;
653 int spill_reg = 0;
654 CORE_ADDR spill_addr = 0;
655
656 if (frame && !frame->saved_regs)
657 {
658 frame_saved_regs_zalloc (frame);
659 do_fsr_stuff = 1;
660 }
661
662 if (frame
663 && !do_fsr_stuff
664 && frame->extra_info->after_prologue != 0
665 && frame->extra_info->after_prologue <= lim_pc)
666 return frame->extra_info->after_prologue;
667
668 /* Must start with an alloc instruction */
669 next_pc = fetch_instruction (pc, &it, &instr);
670 if (pc < lim_pc && next_pc
671 && it == M && ((instr & 0x1ee0000003fLL) == 0x02c00000000LL))
672 {
673 /* alloc */
674 int sor = (int) ((instr & 0x00078000000LL) >> 27);
675 int sol = (int) ((instr & 0x00007f00000LL) >> 20);
676 int sof = (int) ((instr & 0x000000fe000LL) >> 13);
677 /* Okay, so sor, sol, and sof aren't used right now; but perhaps
678 we could compare against the size given to us via the cfm as
679 either a sanity check or possibly to see if the frame has been
680 changed by a later alloc instruction... */
681 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
682 cfm_reg = rN;
683 last_prologue_pc = next_pc;
684 pc = next_pc;
685 }
686 else
687 pc = lim_pc; /* We're done early */
688
689 /* Loop, looking for prologue instructions, keeping track of
690 where preserved registers were spilled. */
691 while (pc < lim_pc)
692 {
693 next_pc = fetch_instruction (pc, &it, &instr);
694 if (next_pc == 0)
695 break;
696
697 if (it == I && ((instr & 0x1eff8000000LL) == 0x00188000000LL))
698 {
699 /* Move from BR */
700 int b2 = (int) ((instr & 0x0000000e000LL) >> 13);
701 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
702 int qp = (int) (instr & 0x0000000003f);
703
704 if (qp == 0 && b2 == 0 && rN >= 32 && ret_reg == 0)
705 {
706 ret_reg = rN;
707 last_prologue_pc = next_pc;
708 }
709 }
710 else if ((it == I || it == M)
711 && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
712 {
713 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
714 int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
715 | ((instr & 0x001f8000000LL) >> 20)
716 | ((instr & 0x000000fe000LL) >> 13));
717 int rM = (int) ((instr & 0x00007f00000LL) >> 20);
718 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
719 int qp = (int) (instr & 0x0000000003fLL);
720
721 if (qp == 0 && rN >= 32 && imm == 0 && rM == 12 && fp_reg == 0)
722 {
723 /* mov rN, r12 */
724 fp_reg = rN;
725 last_prologue_pc = next_pc;
726 }
727 else if (qp == 0 && rN == 12 && rM == 12)
728 {
729 /* adds r12, -mem_stack_frame_size, r12 */
730 mem_stack_frame_size -= imm;
731 last_prologue_pc = next_pc;
732 }
733 else if (qp == 0 && rN == 2
734 && ((rM == fp_reg && fp_reg != 0) || rM == 12))
735 {
736 /* adds r2, spilloffset, rFramePointer
737 or
738 adds r2, spilloffset, r12
739
740 Get ready for stf.spill or st8.spill instructions.
741 The address to start spilling at is loaded into r2.
742 FIXME: Why r2? That's what gcc currently uses; it
743 could well be different for other compilers. */
744
745 /* Hmm... whether or not this will work will depend on
746 where the pc is. If it's still early in the prologue
747 this'll be wrong. FIXME */
748 spill_addr = (frame ? frame->frame : 0)
749 + (rM == 12 ? 0 : mem_stack_frame_size)
750 + imm;
751 spill_reg = rN;
752 last_prologue_pc = next_pc;
753 }
754 }
755 else if (it == M
756 && ( ((instr & 0x1efc0000000LL) == 0x0eec0000000LL)
757 || ((instr & 0x1ffc8000000LL) == 0x0cec0000000LL) ))
758 {
759 /* stf.spill [rN] = fM, imm9
760 or
761 stf.spill [rN] = fM */
762
763 int imm = imm9(instr);
764 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
765 int fM = (int) ((instr & 0x000000fe000LL) >> 13);
766 int qp = (int) (instr & 0x0000000003fLL);
767 if (qp == 0 && rN == spill_reg && spill_addr != 0
768 && ((2 <= fM && fM <= 5) || (16 <= fM && fM <= 31)))
769 {
770 if (do_fsr_stuff)
771 frame->saved_regs[IA64_FR0_REGNUM + fM] = spill_addr;
772
773 if ((instr & 0x1efc0000000) == 0x0eec0000000)
774 spill_addr += imm;
775 else
776 spill_addr = 0; /* last one; must be done */
777 last_prologue_pc = next_pc;
778 }
779 }
780 else if ((it == M && ((instr & 0x1eff8000000LL) == 0x02110000000LL))
781 || (it == I && ((instr & 0x1eff8000000LL) == 0x00050000000LL)) )
782 {
783 /* mov.m rN = arM
784 or
785 mov.i rN = arM */
786
787 int arM = (int) ((instr & 0x00007f00000LL) >> 20);
788 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
789 int qp = (int) (instr & 0x0000000003fLL);
790 if (qp == 0 && isScratch (rN) && arM == 36 /* ar.unat */)
791 {
792 /* We have something like "mov.m r3 = ar.unat". Remember the
793 r3 (or whatever) and watch for a store of this register... */
794 unat_save_reg = rN;
795 last_prologue_pc = next_pc;
796 }
797 }
798 else if (it == I && ((instr & 0x1eff8000000LL) == 0x00198000000LL))
799 {
800 /* mov rN = pr */
801 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
802 int qp = (int) (instr & 0x0000000003fLL);
803 if (qp == 0 && isScratch (rN))
804 {
805 pr_save_reg = rN;
806 last_prologue_pc = next_pc;
807 }
808 }
809 else if (it == M
810 && ( ((instr & 0x1ffc8000000LL) == 0x08cc0000000LL)
811 || ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)))
812 {
813 /* st8 [rN] = rM
814 or
815 st8 [rN] = rM, imm9 */
816 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
817 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
818 int qp = (int) (instr & 0x0000000003fLL);
819 if (qp == 0 && rN == spill_reg && spill_addr != 0
820 && (rM == unat_save_reg || rM == pr_save_reg))
821 {
822 /* We've found a spill of either the UNAT register or the PR
823 register. (Well, not exactly; what we've actually found is
824 a spill of the register that UNAT or PR was moved to).
825 Record that fact and move on... */
826 if (rM == unat_save_reg)
827 {
828 /* Track UNAT register */
829 if (do_fsr_stuff)
830 frame->saved_regs[IA64_UNAT_REGNUM] = spill_addr;
831 unat_save_reg = 0;
832 }
833 else
834 {
835 /* Track PR register */
836 if (do_fsr_stuff)
837 frame->saved_regs[IA64_PR_REGNUM] = spill_addr;
838 pr_save_reg = 0;
839 }
840 if ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)
841 /* st8 [rN] = rM, imm9 */
842 spill_addr += imm9(instr);
843 else
844 spill_addr = 0; /* must be done spilling */
845 last_prologue_pc = next_pc;
846 }
847 }
848 else if (it == M
849 && ( ((instr & 0x1ffc8000000LL) == 0x08ec0000000LL)
850 || ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)))
851 {
852 /* st8.spill [rN] = rM
853 or
854 st8.spill [rN] = rM, imm9 */
855 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
856 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
857 int qp = (int) (instr & 0x0000000003fLL);
858 if (qp == 0 && rN == spill_reg && 4 <= rM && rM <= 7)
859 {
860 /* We've found a spill of one of the preserved general purpose
861 regs. Record the spill address and advance the spill
862 register if appropriate. */
863 if (do_fsr_stuff)
864 frame->saved_regs[IA64_GR0_REGNUM + rM] = spill_addr;
865 if ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)
866 /* st8.spill [rN] = rM, imm9 */
867 spill_addr += imm9(instr);
868 else
869 spill_addr = 0; /* Done spilling */
870 last_prologue_pc = next_pc;
871 }
872 }
873 else if (it == B || ((instr & 0x3fLL) != 0LL))
874 break;
875
876 pc = next_pc;
877 }
878
879 if (do_fsr_stuff) {
880 int i;
881 CORE_ADDR addr;
882
883 for (i = 0, addr = frame->extra_info->bsp;
884 i < frame->extra_info->sof;
885 i++, addr += 8)
886 {
887 if (IS_NaT_COLLECTION_ADDR (addr))
888 {
889 addr += 8;
890 }
891 frame->saved_regs[IA64_GR32_REGNUM + i] = addr;
892
893 if (i+32 == cfm_reg)
894 frame->saved_regs[IA64_CFM_REGNUM] = addr;
895 if (i+32 == ret_reg)
896 frame->saved_regs[IA64_VRAP_REGNUM] = addr;
897 if (i+32 == fp_reg)
898 frame->saved_regs[IA64_VFP_REGNUM] = addr;
899 }
900 }
901
902 if (frame && frame->extra_info) {
903 frame->extra_info->after_prologue = last_prologue_pc;
904 frame->extra_info->mem_stack_frame_size = mem_stack_frame_size;
905 frame->extra_info->fp_reg = fp_reg;
906 }
907
908 return last_prologue_pc;
909}
910
911CORE_ADDR
912ia64_skip_prologue (CORE_ADDR pc)
913{
914 return examine_prologue (pc, pc+1024, 0);
915}
916
917void
918ia64_frame_init_saved_regs (struct frame_info *frame)
919{
920 CORE_ADDR func_start;
921
922 if (frame->saved_regs)
923 return;
924
925 func_start = get_pc_function_start (frame->pc);
926 examine_prologue (func_start, frame->pc, frame);
927}
928
929static CORE_ADDR
930ia64_find_saved_register (frame, regnum)
931 struct frame_info *frame;
932 int regnum;
933{
934 register CORE_ADDR addr = 0;
935
936 if ((IA64_GR32_REGNUM <= regnum && regnum <= IA64_GR127_REGNUM)
937 || regnum == IA64_VFP_REGNUM
938 || regnum == IA64_VRAP_REGNUM)
939 {
940 FRAME_INIT_SAVED_REGS (frame);
941 return frame->saved_regs[regnum];
942 }
943 else if (regnum == IA64_IP_REGNUM && frame->next)
944 {
945 FRAME_INIT_SAVED_REGS (frame->next);
946 return frame->next->saved_regs[IA64_VRAP_REGNUM];
947 }
948 else
949 {
950 struct frame_info *frame1 = NULL;
951 while (1)
952 {
953 QUIT;
954 frame1 = get_prev_frame (frame1);
955 if (frame1 == 0 || frame1 == frame)
956 break;
957 FRAME_INIT_SAVED_REGS (frame1);
958 if (frame1->saved_regs[regnum])
959 addr = frame1->saved_regs[regnum];
960 }
961 }
962
963 return addr;
964}
965
966void
967ia64_get_saved_register (char *raw_buffer,
968 int *optimized,
969 CORE_ADDR *addrp,
970 struct frame_info *frame,
971 int regnum,
972 enum lval_type *lval)
973{
974 CORE_ADDR addr;
975
976 if (!target_has_registers)
977 error ("No registers.");
978
979 if (optimized != NULL)
980 *optimized = 0;
981 addr = ia64_find_saved_register (frame, regnum);
982 if (addr != 0)
983 {
984 if (lval != NULL)
985 *lval = lval_memory;
986 if (regnum == SP_REGNUM)
987 {
988 if (raw_buffer != NULL)
989 {
990 /* Put it back in target format. */
991 store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), (LONGEST) addr);
992 }
993 if (addrp != NULL)
994 *addrp = 0;
995 return;
996 }
997 if (raw_buffer != NULL)
998 read_memory (addr, raw_buffer, REGISTER_RAW_SIZE (regnum));
999 }
1000 else if (IA64_GR32_REGNUM <= regnum && regnum <= IA64_GR127_REGNUM)
1001 {
1002 /* r32 - r127 must be fetchable via memory. If they aren't,
1003 then the register is unavailable */
1004 addr = 0;
1005 if (lval != NULL)
1006 *lval = not_lval;
1007 memset (raw_buffer, 0, REGISTER_RAW_SIZE (regnum));
1008 }
1009 else if (regnum == IA64_IP_REGNUM)
1010 {
1011 CORE_ADDR pc;
1012 if (frame->next)
1013 {
1014 /* This case will normally be handled above, except when it's
1015 frameless or we haven't advanced far enough into the prologue
1016 of the top frame to save the register. */
1017 addr = REGISTER_BYTE (regnum);
1018 if (lval != NULL)
1019 *lval = lval_register;
1020 pc = ia64_saved_pc_after_call (frame);
1021 }
1022 else
1023 {
1024 addr = 0;
1025 if (lval != NULL)
1026 *lval = not_lval;
1027 pc = read_pc ();
1028 }
1029 store_address (raw_buffer, REGISTER_RAW_SIZE (IA64_IP_REGNUM), pc);
1030 }
1031 else if (regnum == SP_REGNUM && frame->next)
1032 {
1033 /* Handle SP values for all frames but the topmost. */
1034 addr = 0;
1035 if (lval != NULL)
1036 *lval = not_lval;
1037 store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), frame->frame);
1038 }
1039 else if (regnum == IA64_BSP_REGNUM)
1040 {
1041 addr = 0;
1042 if (lval != NULL)
1043 *lval = not_lval;
1044 store_address (raw_buffer, REGISTER_RAW_SIZE (regnum),
1045 frame->extra_info->bsp);
1046 }
1047 else if (regnum == IA64_VFP_REGNUM)
1048 {
1049 /* If the function in question uses an automatic register (r32-r127)
1050 for the frame pointer, it'll be found by ia64_find_saved_register()
1051 above. If the function lacks one of these frame pointers, we can
1052 still provide a value since we know the size of the frame */
1053 CORE_ADDR vfp = frame->frame + frame->extra_info->mem_stack_frame_size;
1054 addr = 0;
1055 if (lval != NULL)
1056 *lval = not_lval;
1057 store_address (raw_buffer, REGISTER_RAW_SIZE (IA64_VFP_REGNUM), vfp);
1058 }
1059 else if (IA64_PR0_REGNUM <= regnum && regnum <= IA64_PR63_REGNUM)
1060 {
1061 char pr_raw_buffer[MAX_REGISTER_RAW_SIZE];
1062 int pr_optim;
1063 enum lval_type pr_lval;
1064 CORE_ADDR pr_addr;
1065 int prN_val;
1066 ia64_get_saved_register (pr_raw_buffer, &pr_optim, &pr_addr,
1067 frame, IA64_PR_REGNUM, &pr_lval);
1068 prN_val = extract_bit_field ((unsigned char *) pr_raw_buffer,
1069 regnum - IA64_PR0_REGNUM, 1);
1070 store_unsigned_integer (raw_buffer, REGISTER_RAW_SIZE (regnum), prN_val);
1071 addr = 0;
1072 if (lval != NULL)
1073 *lval = not_lval;
1074 }
1075 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
1076 {
1077 char unat_raw_buffer[MAX_REGISTER_RAW_SIZE];
1078 int unat_optim;
1079 enum lval_type unat_lval;
1080 CORE_ADDR unat_addr;
1081 int unatN_val;
1082 ia64_get_saved_register (unat_raw_buffer, &unat_optim, &unat_addr,
1083 frame, IA64_UNAT_REGNUM, &unat_lval);
1084 unatN_val = extract_bit_field ((unsigned char *) unat_raw_buffer,
1085 regnum - IA64_NAT0_REGNUM, 1);
1086 store_unsigned_integer (raw_buffer, REGISTER_RAW_SIZE (regnum),
1087 unatN_val);
1088 addr = 0;
1089 if (lval != NULL)
1090 *lval = not_lval;
1091 }
1092 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
1093 {
1094 int natval = 0;
1095 /* Find address of general register corresponding to nat bit we're
1096 interested in. */
1097 CORE_ADDR gr_addr =
1098 ia64_find_saved_register (frame,
1099 regnum - IA64_NAT0_REGNUM + IA64_GR0_REGNUM);
1100 if (gr_addr)
1101 {
1102 /* Compute address of nat collection bits */
1103 CORE_ADDR nat_addr = gr_addr | 0x1f8;
1104 CORE_ADDR bsp = read_register (IA64_BSP_REGNUM);
1105 CORE_ADDR nat_collection;
1106 int nat_bit;
1107 /* If our nat collection address is bigger than bsp, we have to get
1108 the nat collection from rnat. Otherwise, we fetch the nat
1109 collection from the computed address. */
1110 if (nat_addr >= bsp)
1111 nat_collection = read_register (IA64_RNAT_REGNUM);
1112 else
1113 nat_collection = read_memory_integer (nat_addr, 8);
1114 nat_bit = (gr_addr >> 3) & 0x3f;
1115 natval = (nat_collection >> nat_bit) & 1;
1116 }
1117 store_unsigned_integer (raw_buffer, REGISTER_RAW_SIZE (regnum), natval);
1118 addr = 0;
1119 if (lval != NULL)
1120 *lval = not_lval;
1121 }
1122 else
1123 {
1124 if (lval != NULL)
1125 *lval = lval_register;
1126 addr = REGISTER_BYTE (regnum);
1127 if (raw_buffer != NULL)
1128 read_register_gen (regnum, raw_buffer);
1129 }
1130 if (addrp != NULL)
1131 *addrp = addr;
1132}
1133
1134/* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of
1135 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc
1136 and TYPE is the type (which is known to be struct, union or array). */
1137int
1138ia64_use_struct_convention (int gcc_p, struct type *type)
1139{
1140 /* FIXME: Need to check for HFAs; structures containing (only) up to 8
1141 floating point values of the same size are returned in floating point
1142 registers. */
1143 return TYPE_LENGTH (type) > 32;
1144}
1145
1146void
1147ia64_extract_return_value (struct type *type, char *regbuf, char *valbuf)
1148{
1149 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1150 ia64_register_convert_to_virtual (IA64_FR8_REGNUM, type,
1151 &regbuf[REGISTER_BYTE (IA64_FR8_REGNUM)], valbuf);
1152 else
1153 memcpy (valbuf, &regbuf[REGISTER_BYTE (IA64_GR8_REGNUM)], TYPE_LENGTH (type));
1154}
1155
1156/* FIXME: Turn this into a stack of some sort. Unfortunately, something
1157 like this is necessary though since the IA-64 calling conventions specify
1158 that r8 is not preserved. */
1159static CORE_ADDR struct_return_address;
1160
1161CORE_ADDR
1162ia64_extract_struct_value_address (char *regbuf)
1163{
1164 /* FIXME: See above. */
1165 return struct_return_address;
1166}
1167
1168void
1169ia64_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
1170{
1171 /* FIXME: See above. */
1172 /* Note that most of the work was done in ia64_push_arguments() */
1173 struct_return_address = addr;
1174}
1175
1176int
1177ia64_frameless_function_invocation (struct frame_info *frame)
1178{
1179 /* FIXME: Implement */
1180 return 0;
1181}
1182
1183CORE_ADDR
1184ia64_saved_pc_after_call (struct frame_info *frame)
1185{
1186 return read_register (IA64_BR0_REGNUM);
1187}
1188
1189CORE_ADDR
1190ia64_frame_args_address (struct frame_info *frame)
1191{
1192 /* frame->frame points at the SP for this frame; But we want the start
1193 of the frame, not the end. Calling frame chain will get his for us. */
1194 return ia64_frame_chain (frame);
1195}
1196
1197CORE_ADDR
1198ia64_frame_locals_address (struct frame_info *frame)
1199{
1200 /* frame->frame points at the SP for this frame; But we want the start
1201 of the frame, not the end. Calling frame chain will get his for us. */
1202 return ia64_frame_chain (frame);
1203}
1204
1205void
1206ia64_init_extra_frame_info (int fromleaf, struct frame_info *frame)
1207{
1208 CORE_ADDR bsp, cfm;
1209
1210 frame->extra_info = (struct frame_extra_info *)
1211 frame_obstack_alloc (sizeof (struct frame_extra_info));
1212
1213 if (frame->next == 0)
1214 {
1215 bsp = read_register (IA64_BSP_REGNUM);
1216 cfm = read_register (IA64_CFM_REGNUM);
1217
1218 }
1219 else
1220 {
1221 struct frame_info *frn = frame->next;
1222 CORE_ADDR cfm_addr;
1223
1224 FRAME_INIT_SAVED_REGS (frn);
1225
1226 if (frn->saved_regs[IA64_CFM_REGNUM] != 0)
1227 cfm = read_memory_integer (frn->saved_regs[IA64_CFM_REGNUM], 8);
1228 else
1229 cfm = read_register (IA64_CFM_REGNUM);
1230
1231 bsp = frn->extra_info->bsp;
1232 }
1233 frame->extra_info->cfm = cfm;
1234 frame->extra_info->sof = cfm & 0x7f;
1235 frame->extra_info->sol = (cfm >> 7) & 0x7f;
1236 if (frame->next == 0)
1237 frame->extra_info->bsp = rse_address_add (bsp, -frame->extra_info->sof);
1238 else
1239 frame->extra_info->bsp = rse_address_add (bsp, -frame->extra_info->sol);
1240
1241 frame->extra_info->after_prologue = 0;
1242 frame->extra_info->mem_stack_frame_size = -1; /* Not yet determined */
1243 frame->extra_info->fp_reg = 0;
1244}
1245
1246#define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
1247
1248CORE_ADDR
1249ia64_push_arguments (int nargs, value_ptr *args, CORE_ADDR sp,
1250 int struct_return, CORE_ADDR struct_addr)
1251{
1252 int argno;
1253 value_ptr arg;
1254 struct type *type;
1255 int len, argoffset;
1256 int nslots, rseslots, memslots, slotnum;
1257 int floatreg;
1258 CORE_ADDR bsp, cfm, pfs, new_bsp;
1259
1260 nslots = 0;
1261 /* Count the number of slots needed for the arguments */
1262 for (argno = 0; argno < nargs; argno++)
1263 {
1264 arg = args[argno];
1265 type = check_typedef (VALUE_TYPE (arg));
1266 len = TYPE_LENGTH (type);
1267
1268 /* FIXME: This is crude and it is wrong (IMO), but it matches
1269 what gcc does, I think. */
1270 if (len > 8 && (nslots & 1))
1271 nslots++;
1272
1273 nslots += (len + 7) / 8;
1274 }
1275
1276 rseslots = (nslots > 8) ? 8 : nslots;
1277 memslots = nslots - rseslots;
1278
1279 cfm = read_register (IA64_CFM_REGNUM);
1280
1281 bsp = read_register (IA64_BSP_REGNUM);
1282 bsp = rse_address_add (bsp, cfm & 0x7f);
1283 new_bsp = rse_address_add (bsp, rseslots);
1284 write_register (IA64_BSP_REGNUM, new_bsp);
1285
1286 pfs = read_register (IA64_PFS_REGNUM);
1287 pfs &= 0xc000000000000000LL;
1288 pfs |= (cfm & 0xffffffffffffLL);
1289 write_register (IA64_PFS_REGNUM, pfs);
1290
1291 cfm &= 0xc000000000000000LL;
1292 cfm |= rseslots;
1293 write_register (IA64_CFM_REGNUM, cfm);
1294
1295
1296
1297 sp = sp - 16 - memslots * 8;
1298 sp &= ~0xfLL; /* Maintain 16 byte alignment */
1299
1300 slotnum = 0;
1301 floatreg = IA64_FR8_REGNUM;
1302 for (argno = 0; argno < nargs; argno++)
1303 {
1304 arg = args[argno];
1305 type = check_typedef (VALUE_TYPE (arg));
1306 len = TYPE_LENGTH (type);
1307 if (len > 8 && (slotnum & 1))
1308 slotnum++;
1309 argoffset = 0;
1310 while (len > 0)
1311 {
1312 char val_buf[8];
1313
1314 memset (val_buf, 0, 8);
1315 memcpy (val_buf, VALUE_CONTENTS (arg) + argoffset, (len > 8) ? 8 : len);
1316
1317 if (slotnum < rseslots)
1318 write_memory (rse_address_add (bsp, slotnum), val_buf, 8);
1319 else
1320 write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
1321
1322 argoffset += 8;
1323 len -= 8;
1324 slotnum++;
1325 }
1326 if (TYPE_CODE (type) == TYPE_CODE_FLT && floatreg < IA64_FR16_REGNUM)
1327 {
1328 ia64_register_convert_to_raw (type, floatreg, VALUE_CONTENTS (arg),
1329 &registers[REGISTER_BYTE (floatreg)]);
1330 floatreg++;
1331 }
1332 }
1333
1334 if (struct_return)
1335 {
1336 store_address (&registers[REGISTER_BYTE (IA64_GR8_REGNUM)],
1337 REGISTER_RAW_SIZE (IA64_GR8_REGNUM),
1338 struct_addr);
1339 }
1340
1341
1342 target_store_registers (-1);
1343
1344 /* FIXME: This doesn't belong here! Instead, SAVE_DUMMY_FRAME_TOS needs
1345 to be defined to call generic_save_dummy_frame_tos(). But at the
1346 time of this writing, SAVE_DUMMY_FRAME_TOS wasn't gdbarch'd, so
1347 I chose to put this call here instead of using the old mechanisms.
1348 Once SAVE_DUMMY_FRAME_TOS is gdbarch'd, all we need to do is add the
1349 line
1350
1351 set_gdbarch_save_dummy_frame_tos (gdbarch, generic_save_dummy_frame_tos);
1352
1353 to ia64_gdbarch_init() and remove the line below. */
1354 generic_save_dummy_frame_tos (sp);
1355
1356 return sp;
1357}
1358
1359CORE_ADDR
1360ia64_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
1361{
1362 struct partial_symtab *pst;
1363
1364 /* Attempt to determine and set global pointer (r1) for this pc.
1365
1366 This rather nasty bit of code searchs for the .dynamic section
1367 in the objfile corresponding to the pc of the function we're
1368 trying to call. Once it finds the addresses at which the .dynamic
1369 section lives in the child process, it scans the Elf64_Dyn entries
1370 for a DT_PLTGOT tag. If it finds one of these, the corresponding
1371 d_un.d_ptr value is the global pointer. */
1372 pst = find_pc_psymtab (pc);
1373 if (pst != NULL)
1374 {
1375 struct obj_section *osect;
1376
1377 ALL_OBJFILE_OSECTIONS (pst->objfile, osect)
1378 {
1379 if (strcmp (osect->the_bfd_section->name, ".dynamic") == 0)
1380 break;
1381 }
1382
1383 if (osect < pst->objfile->sections_end)
1384 {
1385 CORE_ADDR addr;
1386
1387 addr = osect->addr;
1388 while (addr < osect->endaddr)
1389 {
1390 int status;
1391 LONGEST tag;
1392 char buf[8];
1393
1394 status = target_read_memory (addr, buf, sizeof (buf));
1395 if (status != 0)
1396 break;
1397 tag = extract_signed_integer (buf, sizeof (buf));
1398
1399 if (tag == DT_PLTGOT)
1400 {
1401 CORE_ADDR global_pointer;
1402
1403 status = target_read_memory (addr + 8, buf, sizeof (buf));
1404 if (status != 0)
1405 break;
1406 global_pointer = extract_address (buf, sizeof (buf));
1407
1408 /* The payoff... */
1409 write_register (IA64_GR1_REGNUM, global_pointer);
1410 break;
1411 }
1412
1413 if (tag == DT_NULL)
1414 break;
1415
1416 addr += 16;
1417 }
1418 }
1419 }
1420
1421 write_register (IA64_BR0_REGNUM, CALL_DUMMY_ADDRESS ());
1422 return sp;
1423}
1424
1425void
1426ia64_store_return_value (struct type *type, char *valbuf)
1427{
1428 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1429 {
1430 ia64_register_convert_to_raw (type, IA64_FR8_REGNUM, valbuf,
1431 &registers[REGISTER_BYTE (IA64_FR8_REGNUM)]);
1432 target_store_registers (IA64_FR8_REGNUM);
1433 }
1434 else
1435 write_register_bytes (REGISTER_BYTE (IA64_GR8_REGNUM),
1436 valbuf, TYPE_LENGTH (type));
1437}
1438
1439void
1440ia64_pop_frame (void)
1441{
1442 generic_pop_current_frame (ia64_pop_frame_regular);
1443}
1444
1445static void
1446ia64_pop_frame_regular (struct frame_info *frame)
1447{
1448 int regno;
1449 CORE_ADDR bsp, cfm, pfs;
1450
1451 FRAME_INIT_SAVED_REGS (frame);
1452
1453 for (regno = 0; regno < ia64_num_regs; regno++)
1454 {
1455 if (frame->saved_regs[regno]
1456 && (!(IA64_GR32_REGNUM <= regno && regno <= IA64_GR127_REGNUM))
1457 && regno != pc_regnum
1458 && regno != sp_regnum
1459 && regno != IA64_PFS_REGNUM
1460 && regno != IA64_CFM_REGNUM
1461 && regno != IA64_BSP_REGNUM
1462 && regno != IA64_BSPSTORE_REGNUM)
1463 {
1464 write_register (regno,
1465 read_memory_integer (frame->saved_regs[regno],
1466 REGISTER_RAW_SIZE (regno)));
1467 }
1468 }
1469
1470 write_register (sp_regnum, FRAME_CHAIN (frame));
1471 write_pc (FRAME_SAVED_PC (frame));
1472
1473 cfm = read_register (IA64_CFM_REGNUM);
1474
1475 if (frame->saved_regs[IA64_PFS_REGNUM])
1476 {
1477 pfs = read_memory_integer (frame->saved_regs[IA64_PFS_REGNUM],
1478 REGISTER_RAW_SIZE (IA64_PFS_REGNUM));
1479 }
1480 else
1481 pfs = read_register (IA64_PFS_REGNUM);
1482
1483 /* Compute the new bsp by *adding* the difference between the
1484 size of the frame and the size of the locals (both wrt the
1485 frame that we're going back to). This seems kind of strange,
1486 especially since it seems like we ought to be subtracting the
1487 size of the locals... and we should; but the linux kernel
1488 wants bsp to be set at the end of all used registers. It's
1489 likely that this code will need to be revised to accomodate
1490 other operating systems. */
1491 bsp = rse_address_add (frame->extra_info->bsp,
1492 (pfs & 0x7f) - ((pfs >> 7) & 0x7f));
1493 write_register (IA64_BSP_REGNUM, bsp);
1494
1495 /* FIXME: What becomes of the epilog count in the PFS? */
1496 cfm = (cfm & ~0xffffffffffffLL) | (pfs & 0xffffffffffffLL);
1497 write_register (IA64_CFM_REGNUM, cfm);
1498
1499 flush_cached_frames ();
1500}
1501
1502static void
1503ia64_remote_translate_xfer_address (CORE_ADDR memaddr, int nr_bytes,
1504 CORE_ADDR *targ_addr, int *targ_len)
1505{
1506 *targ_addr = memaddr;
1507 *targ_len = nr_bytes;
1508}
1509
1510static struct gdbarch *
1511ia64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1512{
1513 struct gdbarch *gdbarch;
1514
1515 arches = gdbarch_list_lookup_by_info (arches, &info);
1516 if (arches != NULL)
1517 return arches->gdbarch;
1518
1519 gdbarch = gdbarch_alloc (&info, NULL);
1520
1521 set_gdbarch_short_bit (gdbarch, 16);
1522 set_gdbarch_int_bit (gdbarch, 32);
1523 set_gdbarch_long_bit (gdbarch, 64);
1524 set_gdbarch_long_long_bit (gdbarch, 64);
1525 set_gdbarch_float_bit (gdbarch, 32);
1526 set_gdbarch_double_bit (gdbarch, 64);
1527 set_gdbarch_long_double_bit (gdbarch, 64);
1528 set_gdbarch_ptr_bit (gdbarch, 64);
1529
1530 set_gdbarch_num_regs (gdbarch, ia64_num_regs);
1531 set_gdbarch_sp_regnum (gdbarch, sp_regnum);
1532 set_gdbarch_fp_regnum (gdbarch, fp_regnum);
1533 set_gdbarch_pc_regnum (gdbarch, pc_regnum);
1534
1535 set_gdbarch_register_name (gdbarch, ia64_register_name);
1536 set_gdbarch_register_size (gdbarch, 8);
1537 set_gdbarch_register_bytes (gdbarch, ia64_num_regs * 8 + 128*8);
1538 set_gdbarch_register_byte (gdbarch, ia64_register_byte);
1539 set_gdbarch_register_raw_size (gdbarch, ia64_register_raw_size);
1540 set_gdbarch_max_register_raw_size (gdbarch, 16);
1541 set_gdbarch_register_virtual_size (gdbarch, ia64_register_virtual_size);
1542 set_gdbarch_max_register_virtual_size (gdbarch, 16);
1543 set_gdbarch_register_virtual_type (gdbarch, ia64_register_virtual_type);
1544
1545 set_gdbarch_skip_prologue (gdbarch, ia64_skip_prologue);
1546
1547 set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
1548 set_gdbarch_frameless_function_invocation (gdbarch, ia64_frameless_function_invocation);
1549
1550 set_gdbarch_saved_pc_after_call (gdbarch, ia64_saved_pc_after_call);
1551
1552 set_gdbarch_frame_chain (gdbarch, ia64_frame_chain);
1553 set_gdbarch_frame_chain_valid (gdbarch, func_frame_chain_valid);
1554 set_gdbarch_frame_saved_pc (gdbarch, ia64_frame_saved_pc);
1555
1556 set_gdbarch_frame_init_saved_regs (gdbarch, ia64_frame_init_saved_regs);
1557 set_gdbarch_get_saved_register (gdbarch, ia64_get_saved_register);
1558
1559 set_gdbarch_register_convertible (gdbarch, ia64_register_convertible);
1560 set_gdbarch_register_convert_to_virtual (gdbarch, ia64_register_convert_to_virtual);
1561 set_gdbarch_register_convert_to_raw (gdbarch, ia64_register_convert_to_raw);
1562
1563 set_gdbarch_use_struct_convention (gdbarch, ia64_use_struct_convention);
1564 set_gdbarch_extract_return_value (gdbarch, ia64_extract_return_value);
1565
1566 set_gdbarch_store_struct_return (gdbarch, ia64_store_struct_return);
1567 set_gdbarch_store_return_value (gdbarch, ia64_store_return_value);
1568 set_gdbarch_extract_struct_value_address (gdbarch, ia64_extract_struct_value_address);
1569
1570 set_gdbarch_memory_insert_breakpoint (gdbarch, ia64_memory_insert_breakpoint);
1571 set_gdbarch_memory_remove_breakpoint (gdbarch, ia64_memory_remove_breakpoint);
1572 set_gdbarch_breakpoint_from_pc (gdbarch, ia64_breakpoint_from_pc);
1573 set_gdbarch_read_pc (gdbarch, ia64_read_pc);
1574 set_gdbarch_write_pc (gdbarch, ia64_write_pc);
1575
1576 /* Settings for calling functions in the inferior. */
1577 set_gdbarch_use_generic_dummy_frames (gdbarch, 1);
1578 set_gdbarch_call_dummy_length (gdbarch, 0);
1579 set_gdbarch_push_arguments (gdbarch, ia64_push_arguments);
1580 set_gdbarch_push_return_address (gdbarch, ia64_push_return_address);
1581 set_gdbarch_pop_frame (gdbarch, ia64_pop_frame);
1582
1583 set_gdbarch_call_dummy_p (gdbarch, 1);
1584 set_gdbarch_call_dummy_words (gdbarch, ia64_call_dummy_words);
1585 set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (ia64_call_dummy_words));
1586 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1);
1587 set_gdbarch_init_extra_frame_info (gdbarch, ia64_init_extra_frame_info);
1588 set_gdbarch_frame_args_address (gdbarch, ia64_frame_args_address);
1589 set_gdbarch_frame_locals_address (gdbarch, ia64_frame_locals_address);
1590
1591 /* We won't necessarily have a frame pointer and even if we do,
1592 it winds up being extraordinarly messy when attempting to find
1593 the frame chain. So for the purposes of creating frames (which
1594 is all read_fp() is used for), simply use the stack pointer value
1595 instead. */
1596 set_gdbarch_read_fp (gdbarch, generic_target_read_sp);
1597 set_gdbarch_write_fp (gdbarch, generic_target_write_sp);
1598
1599 /* Settings that should be unnecessary. */
1600 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1601
1602 set_gdbarch_read_sp (gdbarch, generic_target_read_sp);
1603 set_gdbarch_write_sp (gdbarch, generic_target_write_sp);
1604
1605 set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT);
1606 set_gdbarch_call_dummy_address (gdbarch, entry_point_address);
1607 set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
1608 set_gdbarch_call_dummy_start_offset (gdbarch, 0);
1609 set_gdbarch_pc_in_call_dummy (gdbarch, generic_pc_in_call_dummy);
1610 set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
1611 set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame);
1612 set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy);
1613
1614 set_gdbarch_decr_pc_after_break (gdbarch, 0);
1615 set_gdbarch_function_start_offset (gdbarch, 0);
1616
1617 set_gdbarch_remote_translate_xfer_address (
1618 gdbarch, ia64_remote_translate_xfer_address);
1619
1620 return gdbarch;
1621}
1622
1623void
1624_initialize_ia64_tdep (void)
1625{
1626 register_gdbarch_init (bfd_arch_ia64, ia64_gdbarch_init);
1627
1628 tm_print_insn = print_insn_ia64;
1629 tm_print_insn_info.bytes_per_line = SLOT_MULTIPLIER;
1630}
GDB Binutils - Deliverables
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