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c28c63d8 JB |
1 | /* Target-dependent code for Lattice Mico32 processor, for GDB. |
2 | Contributed by Jon Beniston <jon@beniston.com> | |
3 | ||
4 | Copyright (C) 2009 Free Software Foundation, Inc. | |
5 | ||
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "defs.h" | |
22 | #include "frame.h" | |
23 | #include "frame-unwind.h" | |
24 | #include "frame-base.h" | |
25 | #include "inferior.h" | |
26 | #include "dis-asm.h" | |
27 | #include "symfile.h" | |
28 | #include "remote.h" | |
29 | #include "gdbcore.h" | |
30 | #include "gdb/sim-lm32.h" | |
31 | #include "gdb/callback.h" | |
32 | #include "gdb/remote-sim.h" | |
33 | #include "sim-regno.h" | |
34 | #include "arch-utils.h" | |
35 | #include "regcache.h" | |
36 | #include "trad-frame.h" | |
37 | #include "reggroups.h" | |
38 | #include "opcodes/lm32-desc.h" | |
39 | ||
40 | #include "gdb_string.h" | |
41 | ||
42 | /* Macros to extract fields from an instruction. */ | |
43 | #define LM32_OPCODE(insn) ((insn >> 26) & 0x3f) | |
44 | #define LM32_REG0(insn) ((insn >> 21) & 0x1f) | |
45 | #define LM32_REG1(insn) ((insn >> 16) & 0x1f) | |
46 | #define LM32_REG2(insn) ((insn >> 11) & 0x1f) | |
47 | #define LM32_IMM16(insn) ((((long)insn & 0xffff) << 16) >> 16) | |
48 | ||
49 | struct gdbarch_tdep | |
50 | { | |
51 | /* gdbarch target dependent data here. Currently unused for LM32. */ | |
52 | }; | |
53 | ||
54 | struct lm32_frame_cache | |
55 | { | |
56 | /* The frame's base. Used when constructing a frame ID. */ | |
57 | CORE_ADDR base; | |
58 | CORE_ADDR pc; | |
59 | /* Size of frame. */ | |
60 | int size; | |
61 | /* Table indicating the location of each and every register. */ | |
62 | struct trad_frame_saved_reg *saved_regs; | |
63 | }; | |
64 | ||
65 | /* Add the available register groups. */ | |
66 | ||
67 | static void | |
68 | lm32_add_reggroups (struct gdbarch *gdbarch) | |
69 | { | |
70 | reggroup_add (gdbarch, general_reggroup); | |
71 | reggroup_add (gdbarch, all_reggroup); | |
72 | reggroup_add (gdbarch, system_reggroup); | |
73 | } | |
74 | ||
75 | /* Return whether a given register is in a given group. */ | |
76 | ||
77 | static int | |
78 | lm32_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
79 | struct reggroup *group) | |
80 | { | |
81 | if (group == general_reggroup) | |
82 | return ((regnum >= SIM_LM32_R0_REGNUM) && (regnum <= SIM_LM32_RA_REGNUM)) | |
83 | || (regnum == SIM_LM32_PC_REGNUM); | |
84 | else if (group == system_reggroup) | |
85 | return ((regnum >= SIM_LM32_EA_REGNUM) && (regnum <= SIM_LM32_BA_REGNUM)) | |
86 | || ((regnum >= SIM_LM32_EID_REGNUM) && (regnum <= SIM_LM32_IP_REGNUM)); | |
87 | return default_register_reggroup_p (gdbarch, regnum, group); | |
88 | } | |
89 | ||
90 | /* Return a name that corresponds to the given register number. */ | |
91 | ||
92 | static const char * | |
93 | lm32_register_name (struct gdbarch *gdbarch, int reg_nr) | |
94 | { | |
95 | static char *register_names[] = { | |
96 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
97 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
98 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
99 | "r24", "r25", "gp", "fp", "sp", "ra", "ea", "ba", | |
100 | "PC", "EID", "EBA", "DEBA", "IE", "IM", "IP" | |
101 | }; | |
102 | ||
103 | if ((reg_nr < 0) || (reg_nr >= ARRAY_SIZE (register_names))) | |
104 | return NULL; | |
105 | else | |
106 | return register_names[reg_nr]; | |
107 | } | |
108 | ||
109 | /* Return type of register. */ | |
110 | ||
111 | static struct type * | |
112 | lm32_register_type (struct gdbarch *gdbarch, int reg_nr) | |
113 | { | |
114 | return builtin_type_int32; | |
115 | } | |
116 | ||
117 | /* Return non-zero if a register can't be written. */ | |
118 | ||
119 | static int | |
120 | lm32_cannot_store_register (struct gdbarch *gdbarch, int regno) | |
121 | { | |
122 | return (regno == SIM_LM32_R0_REGNUM) || (regno == SIM_LM32_EID_REGNUM); | |
123 | } | |
124 | ||
125 | /* Analyze a function's prologue. */ | |
126 | ||
127 | static CORE_ADDR | |
128 | lm32_analyze_prologue (CORE_ADDR pc, CORE_ADDR limit, | |
129 | struct lm32_frame_cache *info) | |
130 | { | |
131 | unsigned long instruction; | |
132 | ||
133 | /* Keep reading though instructions, until we come across an instruction | |
134 | that isn't likely to be part of the prologue. */ | |
135 | info->size = 0; | |
136 | for (; pc < limit; pc += 4) | |
137 | { | |
138 | ||
139 | /* Read an instruction. */ | |
140 | instruction = read_memory_integer (pc, 4); | |
141 | ||
142 | if ((LM32_OPCODE (instruction) == OP_SW) | |
143 | && (LM32_REG0 (instruction) == SIM_LM32_SP_REGNUM)) | |
144 | { | |
145 | /* Any stack displaced store is likely part of the prologue. | |
146 | Record that the register is being saved, and the offset | |
147 | into the stack. */ | |
148 | info->saved_regs[LM32_REG1 (instruction)].addr = | |
149 | LM32_IMM16 (instruction); | |
150 | } | |
151 | else if ((LM32_OPCODE (instruction) == OP_ADDI) | |
152 | && (LM32_REG1 (instruction) == SIM_LM32_SP_REGNUM)) | |
153 | { | |
154 | /* An add to the SP is likely to be part of the prologue. | |
155 | Adjust stack size by whatever the instruction adds to the sp. */ | |
156 | info->size -= LM32_IMM16 (instruction); | |
157 | } | |
158 | else if ( /* add fp,fp,sp */ | |
159 | ((LM32_OPCODE (instruction) == OP_ADD) | |
160 | && (LM32_REG2 (instruction) == SIM_LM32_FP_REGNUM) | |
161 | && (LM32_REG0 (instruction) == SIM_LM32_FP_REGNUM) | |
162 | && (LM32_REG1 (instruction) == SIM_LM32_SP_REGNUM)) | |
163 | /* mv fp,imm */ | |
164 | || ((LM32_OPCODE (instruction) == OP_ADDI) | |
165 | && (LM32_REG1 (instruction) == SIM_LM32_FP_REGNUM) | |
166 | && (LM32_REG0 (instruction) == SIM_LM32_R0_REGNUM))) | |
167 | { | |
168 | /* Likely to be in the prologue for functions that require | |
169 | a frame pointer. */ | |
170 | } | |
171 | else | |
172 | { | |
173 | /* Any other instruction is likely not to be part of the prologue. */ | |
174 | break; | |
175 | } | |
176 | } | |
177 | ||
178 | return pc; | |
179 | } | |
180 | ||
181 | /* Return PC of first non prologue instruction, for the function at the | |
182 | specified address. */ | |
183 | ||
184 | static CORE_ADDR | |
185 | lm32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
186 | { | |
187 | CORE_ADDR func_addr, limit_pc; | |
188 | struct symtab_and_line sal; | |
189 | struct lm32_frame_cache frame_info; | |
190 | struct trad_frame_saved_reg saved_regs[SIM_LM32_NUM_REGS]; | |
191 | ||
192 | /* See if we can determine the end of the prologue via the symbol table. | |
193 | If so, then return either PC, or the PC after the prologue, whichever | |
194 | is greater. */ | |
195 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) | |
196 | { | |
197 | CORE_ADDR post_prologue_pc = skip_prologue_using_sal (func_addr); | |
198 | if (post_prologue_pc != 0) | |
199 | return max (pc, post_prologue_pc); | |
200 | } | |
201 | ||
202 | /* Can't determine prologue from the symbol table, need to examine | |
203 | instructions. */ | |
204 | ||
205 | /* Find an upper limit on the function prologue using the debug | |
206 | information. If the debug information could not be used to provide | |
207 | that bound, then use an arbitrary large number as the upper bound. */ | |
208 | limit_pc = skip_prologue_using_sal (pc); | |
209 | if (limit_pc == 0) | |
210 | limit_pc = pc + 100; /* Magic. */ | |
211 | ||
212 | frame_info.saved_regs = saved_regs; | |
213 | return lm32_analyze_prologue (pc, limit_pc, &frame_info); | |
214 | } | |
215 | ||
216 | /* Create a breakpoint instruction. */ | |
217 | ||
218 | static const gdb_byte * | |
219 | lm32_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, | |
220 | int *lenptr) | |
221 | { | |
222 | static const gdb_byte breakpoint[4] = { OP_RAISE << 2, 0, 0, 2 }; | |
223 | ||
224 | *lenptr = sizeof (breakpoint); | |
225 | return breakpoint; | |
226 | } | |
227 | ||
228 | /* Setup registers and stack for faking a call to a function in the | |
229 | inferior. */ | |
230 | ||
231 | static CORE_ADDR | |
232 | lm32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | |
233 | struct regcache *regcache, CORE_ADDR bp_addr, | |
234 | int nargs, struct value **args, CORE_ADDR sp, | |
235 | int struct_return, CORE_ADDR struct_addr) | |
236 | { | |
237 | int first_arg_reg = SIM_LM32_R1_REGNUM; | |
238 | int num_arg_regs = 8; | |
239 | int i; | |
240 | ||
241 | /* Set the return address. */ | |
242 | regcache_cooked_write_signed (regcache, SIM_LM32_RA_REGNUM, bp_addr); | |
243 | ||
244 | /* If we're returning a large struct, a pointer to the address to | |
245 | store it at is passed as a first hidden parameter. */ | |
246 | if (struct_return) | |
247 | { | |
248 | regcache_cooked_write_unsigned (regcache, first_arg_reg, struct_addr); | |
249 | first_arg_reg++; | |
250 | num_arg_regs--; | |
251 | sp -= 4; | |
252 | } | |
253 | ||
254 | /* Setup parameters. */ | |
255 | for (i = 0; i < nargs; i++) | |
256 | { | |
257 | struct value *arg = args[i]; | |
258 | struct type *arg_type = check_typedef (value_type (arg)); | |
259 | gdb_byte *contents; | |
260 | int len; | |
261 | int j; | |
262 | int reg; | |
263 | ULONGEST val; | |
264 | ||
265 | /* Promote small integer types to int. */ | |
266 | switch (TYPE_CODE (arg_type)) | |
267 | { | |
268 | case TYPE_CODE_INT: | |
269 | case TYPE_CODE_BOOL: | |
270 | case TYPE_CODE_CHAR: | |
271 | case TYPE_CODE_RANGE: | |
272 | case TYPE_CODE_ENUM: | |
273 | if (TYPE_LENGTH (arg_type) < 4) | |
274 | { | |
275 | arg_type = builtin_type_int32; | |
276 | arg = value_cast (arg_type, arg); | |
277 | } | |
278 | break; | |
279 | } | |
280 | ||
281 | /* FIXME: Handle structures. */ | |
282 | ||
283 | contents = (gdb_byte *) value_contents (arg); | |
284 | len = TYPE_LENGTH (arg_type); | |
285 | val = extract_unsigned_integer (contents, len); | |
286 | ||
287 | /* First num_arg_regs parameters are passed by registers, | |
288 | and the rest are passed on the stack. */ | |
289 | if (i < num_arg_regs) | |
290 | regcache_cooked_write_unsigned (regcache, first_arg_reg + i, val); | |
291 | else | |
292 | { | |
293 | write_memory (sp, (void *) &val, len); | |
294 | sp -= 4; | |
295 | } | |
296 | } | |
297 | ||
298 | /* Update stack pointer. */ | |
299 | regcache_cooked_write_signed (regcache, SIM_LM32_SP_REGNUM, sp); | |
300 | ||
301 | /* Return adjusted stack pointer. */ | |
302 | return sp; | |
303 | } | |
304 | ||
305 | /* Extract return value after calling a function in the inferior. */ | |
306 | ||
307 | static void | |
308 | lm32_extract_return_value (struct type *type, struct regcache *regcache, | |
309 | gdb_byte *valbuf) | |
310 | { | |
311 | int offset; | |
312 | ULONGEST l; | |
313 | CORE_ADDR return_buffer; | |
314 | ||
315 | if (TYPE_CODE (type) != TYPE_CODE_STRUCT | |
316 | && TYPE_CODE (type) != TYPE_CODE_UNION | |
317 | && TYPE_CODE (type) != TYPE_CODE_ARRAY && TYPE_LENGTH (type) <= 4) | |
318 | { | |
319 | /* Return value is returned in a single register. */ | |
320 | regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l); | |
321 | store_unsigned_integer (valbuf, TYPE_LENGTH (type), l); | |
322 | } | |
323 | else if ((TYPE_CODE (type) == TYPE_CODE_INT) && (TYPE_LENGTH (type) == 8)) | |
324 | { | |
325 | /* 64-bit values are returned in a register pair. */ | |
326 | regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l); | |
327 | memcpy (valbuf, &l, 4); | |
328 | regcache_cooked_read_unsigned (regcache, SIM_LM32_R2_REGNUM, &l); | |
329 | memcpy (valbuf + 4, &l, 4); | |
330 | } | |
331 | else | |
332 | { | |
333 | /* Aggregate types greater than a single register are returned in memory. | |
334 | FIXME: Unless they are only 2 regs?. */ | |
335 | regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l); | |
336 | return_buffer = l; | |
337 | read_memory (return_buffer, valbuf, TYPE_LENGTH (type)); | |
338 | } | |
339 | } | |
340 | ||
341 | /* Write into appropriate registers a function return value of type | |
342 | TYPE, given in virtual format. */ | |
343 | static void | |
344 | lm32_store_return_value (struct type *type, struct regcache *regcache, | |
345 | const gdb_byte *valbuf) | |
346 | { | |
347 | ULONGEST val; | |
348 | int len = TYPE_LENGTH (type); | |
349 | ||
350 | if (len <= 4) | |
351 | { | |
352 | val = extract_unsigned_integer (valbuf, len); | |
353 | regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val); | |
354 | } | |
355 | else if (len <= 8) | |
356 | { | |
357 | val = extract_unsigned_integer (valbuf, 4); | |
358 | regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val); | |
359 | val = extract_unsigned_integer (valbuf + 4, len - 4); | |
360 | regcache_cooked_write_unsigned (regcache, SIM_LM32_R2_REGNUM, val); | |
361 | } | |
362 | else | |
363 | error (_("lm32_store_return_value: type length too large.")); | |
364 | } | |
365 | ||
366 | /* Determine whether a functions return value is in a register or memory. */ | |
367 | static enum return_value_convention | |
368 | lm32_return_value (struct gdbarch *gdbarch, struct type *func_type, | |
369 | struct type *valtype, struct regcache *regcache, | |
370 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
371 | { | |
372 | enum type_code code = TYPE_CODE (valtype); | |
373 | ||
374 | if (code == TYPE_CODE_STRUCT | |
375 | || code == TYPE_CODE_UNION | |
376 | || code == TYPE_CODE_ARRAY || TYPE_LENGTH (valtype) > 8) | |
377 | return RETURN_VALUE_STRUCT_CONVENTION; | |
378 | ||
379 | if (readbuf) | |
380 | lm32_extract_return_value (valtype, regcache, readbuf); | |
381 | if (writebuf) | |
382 | lm32_store_return_value (valtype, regcache, writebuf); | |
383 | ||
384 | return RETURN_VALUE_REGISTER_CONVENTION; | |
385 | } | |
386 | ||
387 | static CORE_ADDR | |
388 | lm32_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
389 | { | |
390 | return frame_unwind_register_unsigned (next_frame, SIM_LM32_PC_REGNUM); | |
391 | } | |
392 | ||
393 | static CORE_ADDR | |
394 | lm32_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
395 | { | |
396 | return frame_unwind_register_unsigned (next_frame, SIM_LM32_SP_REGNUM); | |
397 | } | |
398 | ||
399 | static struct frame_id | |
400 | lm32_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
401 | { | |
402 | CORE_ADDR sp = get_frame_register_unsigned (this_frame, SIM_LM32_SP_REGNUM); | |
403 | ||
404 | return frame_id_build (sp, get_frame_pc (this_frame)); | |
405 | } | |
406 | ||
407 | /* Put here the code to store, into fi->saved_regs, the addresses of | |
408 | the saved registers of frame described by FRAME_INFO. This | |
409 | includes special registers such as pc and fp saved in special ways | |
410 | in the stack frame. sp is even more special: the address we return | |
411 | for it IS the sp for the next frame. */ | |
412 | ||
413 | static struct lm32_frame_cache * | |
414 | lm32_frame_cache (struct frame_info *this_frame, void **this_prologue_cache) | |
415 | { | |
416 | CORE_ADDR prologue_pc; | |
417 | CORE_ADDR current_pc; | |
418 | ULONGEST prev_sp; | |
419 | ULONGEST this_base; | |
420 | struct lm32_frame_cache *info; | |
421 | int prefixed; | |
422 | unsigned long instruction; | |
423 | int op; | |
424 | int offsets[32]; | |
425 | int i; | |
426 | long immediate; | |
427 | ||
428 | if ((*this_prologue_cache)) | |
429 | return (*this_prologue_cache); | |
430 | ||
431 | info = FRAME_OBSTACK_ZALLOC (struct lm32_frame_cache); | |
432 | (*this_prologue_cache) = info; | |
433 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
434 | ||
435 | info->pc = get_frame_func (this_frame); | |
436 | current_pc = get_frame_pc (this_frame); | |
437 | lm32_analyze_prologue (info->pc, current_pc, info); | |
438 | ||
439 | /* Compute the frame's base, and the previous frame's SP. */ | |
440 | this_base = get_frame_register_unsigned (this_frame, SIM_LM32_SP_REGNUM); | |
441 | prev_sp = this_base + info->size; | |
442 | info->base = this_base; | |
443 | ||
444 | /* Convert callee save offsets into addresses. */ | |
445 | for (i = 0; i < gdbarch_num_regs (get_frame_arch (this_frame)) - 1; i++) | |
446 | { | |
447 | if (trad_frame_addr_p (info->saved_regs, i)) | |
448 | info->saved_regs[i].addr = this_base + info->saved_regs[i].addr; | |
449 | } | |
450 | ||
451 | /* The call instruction moves the caller's PC in the callee's RA register. | |
452 | Since this is an unwind, do the reverse. Copy the location of RA register | |
453 | into PC (the address / regnum) so that a request for PC will be | |
454 | converted into a request for the RA register. */ | |
455 | info->saved_regs[SIM_LM32_PC_REGNUM] = info->saved_regs[SIM_LM32_RA_REGNUM]; | |
456 | ||
457 | /* The previous frame's SP needed to be computed. Save the computed value. */ | |
458 | trad_frame_set_value (info->saved_regs, SIM_LM32_SP_REGNUM, prev_sp); | |
459 | ||
460 | return info; | |
461 | } | |
462 | ||
463 | static void | |
464 | lm32_frame_this_id (struct frame_info *this_frame, void **this_cache, | |
465 | struct frame_id *this_id) | |
466 | { | |
467 | struct lm32_frame_cache *cache = lm32_frame_cache (this_frame, this_cache); | |
468 | ||
469 | /* This marks the outermost frame. */ | |
470 | if (cache->base == 0) | |
471 | return; | |
472 | ||
473 | (*this_id) = frame_id_build (cache->base, cache->pc); | |
474 | } | |
475 | ||
476 | static struct value * | |
477 | lm32_frame_prev_register (struct frame_info *this_frame, | |
478 | void **this_prologue_cache, int regnum) | |
479 | { | |
480 | struct lm32_frame_cache *info; | |
481 | ||
482 | info = lm32_frame_cache (this_frame, this_prologue_cache); | |
483 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); | |
484 | } | |
485 | ||
486 | static const struct frame_unwind lm32_frame_unwind = { | |
487 | NORMAL_FRAME, | |
488 | lm32_frame_this_id, | |
489 | lm32_frame_prev_register, | |
490 | NULL, | |
491 | default_frame_sniffer | |
492 | }; | |
493 | ||
494 | static CORE_ADDR | |
495 | lm32_frame_base_address (struct frame_info *this_frame, void **this_cache) | |
496 | { | |
497 | struct lm32_frame_cache *info = lm32_frame_cache (this_frame, this_cache); | |
498 | ||
499 | return info->base; | |
500 | } | |
501 | ||
502 | static const struct frame_base lm32_frame_base = { | |
503 | &lm32_frame_unwind, | |
504 | lm32_frame_base_address, | |
505 | lm32_frame_base_address, | |
506 | lm32_frame_base_address | |
507 | }; | |
508 | ||
509 | static CORE_ADDR | |
510 | lm32_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
511 | { | |
512 | /* Align to the size of an instruction (so that they can safely be | |
513 | pushed onto the stack. */ | |
514 | return sp & ~3; | |
515 | } | |
516 | ||
517 | static struct gdbarch * | |
518 | lm32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
519 | { | |
520 | struct gdbarch *gdbarch; | |
521 | struct gdbarch_tdep *tdep; | |
522 | ||
523 | /* If there is already a candidate, use it. */ | |
524 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
525 | if (arches != NULL) | |
526 | return arches->gdbarch; | |
527 | ||
528 | /* None found, create a new architecture from the information provided. */ | |
529 | tdep = XMALLOC (struct gdbarch_tdep); | |
530 | gdbarch = gdbarch_alloc (&info, tdep); | |
531 | ||
532 | /* Type sizes. */ | |
533 | set_gdbarch_short_bit (gdbarch, 16); | |
534 | set_gdbarch_int_bit (gdbarch, 32); | |
535 | set_gdbarch_long_bit (gdbarch, 32); | |
536 | set_gdbarch_long_long_bit (gdbarch, 64); | |
537 | set_gdbarch_float_bit (gdbarch, 32); | |
538 | set_gdbarch_double_bit (gdbarch, 64); | |
539 | set_gdbarch_long_double_bit (gdbarch, 64); | |
540 | set_gdbarch_ptr_bit (gdbarch, 32); | |
541 | ||
542 | /* Register info. */ | |
543 | set_gdbarch_num_regs (gdbarch, SIM_LM32_NUM_REGS); | |
544 | set_gdbarch_sp_regnum (gdbarch, SIM_LM32_SP_REGNUM); | |
545 | set_gdbarch_pc_regnum (gdbarch, SIM_LM32_PC_REGNUM); | |
546 | set_gdbarch_register_name (gdbarch, lm32_register_name); | |
547 | set_gdbarch_register_type (gdbarch, lm32_register_type); | |
548 | set_gdbarch_cannot_store_register (gdbarch, lm32_cannot_store_register); | |
549 | ||
550 | /* Frame info. */ | |
551 | set_gdbarch_skip_prologue (gdbarch, lm32_skip_prologue); | |
552 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
553 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
554 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
555 | ||
556 | /* Frame unwinding. */ | |
557 | set_gdbarch_frame_align (gdbarch, lm32_frame_align); | |
558 | frame_base_set_default (gdbarch, &lm32_frame_base); | |
559 | set_gdbarch_unwind_pc (gdbarch, lm32_unwind_pc); | |
560 | set_gdbarch_unwind_sp (gdbarch, lm32_unwind_sp); | |
561 | set_gdbarch_dummy_id (gdbarch, lm32_dummy_id); | |
562 | frame_unwind_append_unwinder (gdbarch, &lm32_frame_unwind); | |
563 | ||
564 | /* Breakpoints. */ | |
565 | set_gdbarch_breakpoint_from_pc (gdbarch, lm32_breakpoint_from_pc); | |
566 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
567 | ||
568 | /* Calling functions in the inferior. */ | |
569 | set_gdbarch_push_dummy_call (gdbarch, lm32_push_dummy_call); | |
570 | set_gdbarch_return_value (gdbarch, lm32_return_value); | |
571 | ||
572 | /* Instruction disassembler. */ | |
573 | set_gdbarch_print_insn (gdbarch, print_insn_lm32); | |
574 | ||
575 | lm32_add_reggroups (gdbarch); | |
576 | set_gdbarch_register_reggroup_p (gdbarch, lm32_register_reggroup_p); | |
577 | ||
578 | return gdbarch; | |
579 | } | |
580 | ||
581 | void | |
582 | _initialize_lm32_tdep (void) | |
583 | { | |
584 | register_gdbarch_init (bfd_arch_lm32, lm32_gdbarch_init); | |
585 | } |