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96309189 MS |
1 | /* Renesas M32C target-dependent code for GDB, the GNU debugger. |
2 | ||
3666a048 | 3 | Copyright (C) 2004-2021 Free Software Foundation, Inc. |
96309189 MS |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
96309189 MS |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
96309189 MS |
19 | |
20 | #include "defs.h" | |
96309189 | 21 | #include "gdb/sim-m32c.h" |
96309189 MS |
22 | #include "gdbtypes.h" |
23 | #include "regcache.h" | |
24 | #include "arch-utils.h" | |
25 | #include "frame.h" | |
26 | #include "frame-unwind.h" | |
96309189 MS |
27 | #include "symtab.h" |
28 | #include "gdbcore.h" | |
29 | #include "value.h" | |
30 | #include "reggroups.h" | |
31 | #include "prologue-value.h" | |
77e371c0 | 32 | #include "objfiles.h" |
96309189 MS |
33 | |
34 | \f | |
35 | /* The m32c tdep structure. */ | |
36 | ||
37 | static struct reggroup *m32c_dma_reggroup; | |
38 | ||
96309189 MS |
39 | /* The type of a function that moves the value of REG between CACHE or |
40 | BUF --- in either direction. */ | |
6da660c7 SM |
41 | typedef enum register_status (m32c_write_reg_t) (struct m32c_reg *reg, |
42 | struct regcache *cache, | |
43 | const gdb_byte *buf); | |
44 | ||
45 | typedef enum register_status (m32c_read_reg_t) (struct m32c_reg *reg, | |
849d0ba8 | 46 | readable_regcache *cache, |
6da660c7 | 47 | gdb_byte *buf); |
96309189 MS |
48 | |
49 | struct m32c_reg | |
50 | { | |
51 | /* The name of this register. */ | |
52 | const char *name; | |
53 | ||
54 | /* Its type. */ | |
55 | struct type *type; | |
56 | ||
57 | /* The architecture this register belongs to. */ | |
58 | struct gdbarch *arch; | |
59 | ||
60 | /* Its GDB register number. */ | |
61 | int num; | |
62 | ||
63 | /* Its sim register number. */ | |
64 | int sim_num; | |
65 | ||
66 | /* Its DWARF register number, or -1 if it doesn't have one. */ | |
67 | int dwarf_num; | |
68 | ||
69 | /* Register group memberships. */ | |
70 | unsigned int general_p : 1; | |
71 | unsigned int dma_p : 1; | |
72 | unsigned int system_p : 1; | |
73 | unsigned int save_restore_p : 1; | |
74 | ||
75 | /* Functions to read its value from a regcache, and write its value | |
76 | to a regcache. */ | |
6da660c7 SM |
77 | m32c_read_reg_t *read; |
78 | m32c_write_reg_t *write; | |
96309189 MS |
79 | |
80 | /* Data for READ and WRITE functions. The exact meaning depends on | |
81 | the specific functions selected; see the comments for those | |
82 | functions. */ | |
83 | struct m32c_reg *rx, *ry; | |
84 | int n; | |
85 | }; | |
86 | ||
87 | ||
88 | /* An overestimate of the number of raw and pseudoregisters we will | |
89 | have. The exact answer depends on the variant of the architecture | |
90 | at hand, but we can use this to declare statically allocated | |
91 | arrays, and bump it up when needed. */ | |
92 | #define M32C_MAX_NUM_REGS (75) | |
93 | ||
94 | /* The largest assigned DWARF register number. */ | |
95 | #define M32C_MAX_DWARF_REGNUM (40) | |
96 | ||
97 | ||
98 | struct gdbarch_tdep | |
99 | { | |
100 | /* All the registers for this variant, indexed by GDB register | |
101 | number, and the number of registers present. */ | |
102 | struct m32c_reg regs[M32C_MAX_NUM_REGS]; | |
103 | ||
104 | /* The number of valid registers. */ | |
105 | int num_regs; | |
106 | ||
107 | /* Interesting registers. These are pointers into REGS. */ | |
108 | struct m32c_reg *pc, *flg; | |
109 | struct m32c_reg *r0, *r1, *r2, *r3, *a0, *a1; | |
110 | struct m32c_reg *r2r0, *r3r2r1r0, *r3r1r2r0; | |
111 | struct m32c_reg *sb, *fb, *sp; | |
112 | ||
113 | /* A table indexed by DWARF register numbers, pointing into | |
114 | REGS. */ | |
115 | struct m32c_reg *dwarf_regs[M32C_MAX_DWARF_REGNUM + 1]; | |
116 | ||
117 | /* Types for this architecture. We can't use the builtin_type_foo | |
118 | types, because they're not initialized when building a gdbarch | |
119 | structure. */ | |
120 | struct type *voyd, *ptr_voyd, *func_voyd; | |
121 | struct type *uint8, *uint16; | |
122 | struct type *int8, *int16, *int32, *int64; | |
123 | ||
124 | /* The types for data address and code address registers. */ | |
125 | struct type *data_addr_reg_type, *code_addr_reg_type; | |
126 | ||
127 | /* The number of bytes a return address pushed by a 'jsr' instruction | |
128 | occupies on the stack. */ | |
129 | int ret_addr_bytes; | |
130 | ||
131 | /* The number of bytes an address register occupies on the stack | |
132 | when saved by an 'enter' or 'pushm' instruction. */ | |
133 | int push_addr_bytes; | |
134 | }; | |
135 | ||
136 | \f | |
137 | /* Types. */ | |
138 | ||
139 | static void | |
140 | make_types (struct gdbarch *arch) | |
141 | { | |
142 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); | |
143 | unsigned long mach = gdbarch_bfd_arch_info (arch)->mach; | |
144 | int data_addr_reg_bits, code_addr_reg_bits; | |
145 | char type_name[50]; | |
146 | ||
147 | #if 0 | |
148 | /* This is used to clip CORE_ADDR values, so this value is | |
149 | appropriate both on the m32c, where pointers are 32 bits long, | |
150 | and on the m16c, where pointers are sixteen bits long, but there | |
151 | may be code above the 64k boundary. */ | |
152 | set_gdbarch_addr_bit (arch, 24); | |
153 | #else | |
154 | /* GCC uses 32 bits for addrs in the dwarf info, even though | |
155 | only 16/24 bits are used. Setting addr_bit to 24 causes | |
156 | errors in reading the dwarf addresses. */ | |
157 | set_gdbarch_addr_bit (arch, 32); | |
158 | #endif | |
159 | ||
160 | set_gdbarch_int_bit (arch, 16); | |
161 | switch (mach) | |
162 | { | |
163 | case bfd_mach_m16c: | |
164 | data_addr_reg_bits = 16; | |
165 | code_addr_reg_bits = 24; | |
166 | set_gdbarch_ptr_bit (arch, 16); | |
167 | tdep->ret_addr_bytes = 3; | |
168 | tdep->push_addr_bytes = 2; | |
169 | break; | |
170 | ||
171 | case bfd_mach_m32c: | |
172 | data_addr_reg_bits = 24; | |
173 | code_addr_reg_bits = 24; | |
174 | set_gdbarch_ptr_bit (arch, 32); | |
175 | tdep->ret_addr_bytes = 4; | |
176 | tdep->push_addr_bytes = 4; | |
177 | break; | |
178 | ||
179 | default: | |
f3574227 | 180 | gdb_assert_not_reached ("unexpected mach"); |
96309189 MS |
181 | } |
182 | ||
183 | /* The builtin_type_mumble variables are sometimes uninitialized when | |
184 | this is called, so we avoid using them. */ | |
77b7c781 | 185 | tdep->voyd = arch_type (arch, TYPE_CODE_VOID, TARGET_CHAR_BIT, "void"); |
e9bb382b | 186 | tdep->ptr_voyd |
88dfca6c | 187 | = arch_pointer_type (arch, gdbarch_ptr_bit (arch), NULL, tdep->voyd); |
96309189 MS |
188 | tdep->func_voyd = lookup_function_type (tdep->voyd); |
189 | ||
8c042590 PM |
190 | xsnprintf (type_name, sizeof (type_name), "%s_data_addr_t", |
191 | gdbarch_bfd_arch_info (arch)->printable_name); | |
96309189 | 192 | tdep->data_addr_reg_type |
88dfca6c | 193 | = arch_pointer_type (arch, data_addr_reg_bits, type_name, tdep->voyd); |
96309189 | 194 | |
8c042590 PM |
195 | xsnprintf (type_name, sizeof (type_name), "%s_code_addr_t", |
196 | gdbarch_bfd_arch_info (arch)->printable_name); | |
96309189 | 197 | tdep->code_addr_reg_type |
88dfca6c | 198 | = arch_pointer_type (arch, code_addr_reg_bits, type_name, tdep->func_voyd); |
e9bb382b UW |
199 | |
200 | tdep->uint8 = arch_integer_type (arch, 8, 1, "uint8_t"); | |
201 | tdep->uint16 = arch_integer_type (arch, 16, 1, "uint16_t"); | |
202 | tdep->int8 = arch_integer_type (arch, 8, 0, "int8_t"); | |
203 | tdep->int16 = arch_integer_type (arch, 16, 0, "int16_t"); | |
204 | tdep->int32 = arch_integer_type (arch, 32, 0, "int32_t"); | |
205 | tdep->int64 = arch_integer_type (arch, 64, 0, "int64_t"); | |
96309189 MS |
206 | } |
207 | ||
208 | ||
209 | \f | |
210 | /* Register set. */ | |
211 | ||
212 | static const char * | |
d93859e2 | 213 | m32c_register_name (struct gdbarch *gdbarch, int num) |
96309189 | 214 | { |
d93859e2 | 215 | return gdbarch_tdep (gdbarch)->regs[num].name; |
96309189 MS |
216 | } |
217 | ||
218 | ||
219 | static struct type * | |
220 | m32c_register_type (struct gdbarch *arch, int reg_nr) | |
221 | { | |
222 | return gdbarch_tdep (arch)->regs[reg_nr].type; | |
223 | } | |
224 | ||
225 | ||
226 | static int | |
e7faf938 | 227 | m32c_register_sim_regno (struct gdbarch *gdbarch, int reg_nr) |
96309189 | 228 | { |
e7faf938 | 229 | return gdbarch_tdep (gdbarch)->regs[reg_nr].sim_num; |
96309189 MS |
230 | } |
231 | ||
232 | ||
233 | static int | |
d3f73121 | 234 | m32c_debug_info_reg_to_regnum (struct gdbarch *gdbarch, int reg_nr) |
96309189 | 235 | { |
d3f73121 | 236 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
96309189 MS |
237 | if (0 <= reg_nr && reg_nr <= M32C_MAX_DWARF_REGNUM |
238 | && tdep->dwarf_regs[reg_nr]) | |
239 | return tdep->dwarf_regs[reg_nr]->num; | |
240 | else | |
241 | /* The DWARF CFI code expects to see -1 for invalid register | |
242 | numbers. */ | |
243 | return -1; | |
244 | } | |
245 | ||
246 | ||
63807e1d | 247 | static int |
96309189 MS |
248 | m32c_register_reggroup_p (struct gdbarch *gdbarch, int regnum, |
249 | struct reggroup *group) | |
250 | { | |
40a6adc1 | 251 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
96309189 MS |
252 | struct m32c_reg *reg = &tdep->regs[regnum]; |
253 | ||
254 | /* The anonymous raw registers aren't in any groups. */ | |
255 | if (! reg->name) | |
256 | return 0; | |
257 | ||
258 | if (group == all_reggroup) | |
259 | return 1; | |
260 | ||
261 | if (group == general_reggroup | |
262 | && reg->general_p) | |
263 | return 1; | |
264 | ||
265 | if (group == m32c_dma_reggroup | |
266 | && reg->dma_p) | |
267 | return 1; | |
268 | ||
269 | if (group == system_reggroup | |
270 | && reg->system_p) | |
271 | return 1; | |
272 | ||
273 | /* Since the m32c DWARF register numbers refer to cooked registers, not | |
274 | raw registers, and frame_pop depends on the save and restore groups | |
275 | containing registers the DWARF CFI will actually mention, our save | |
276 | and restore groups are cooked registers, not raw registers. (This is | |
277 | why we can't use the default reggroup function.) */ | |
278 | if ((group == save_reggroup | |
279 | || group == restore_reggroup) | |
280 | && reg->save_restore_p) | |
281 | return 1; | |
282 | ||
283 | return 0; | |
284 | } | |
285 | ||
286 | ||
287 | /* Register move functions. We declare them here using | |
6da660c7 SM |
288 | m32c_{read,write}_reg_t to check the types. */ |
289 | static m32c_read_reg_t m32c_raw_read; | |
290 | static m32c_read_reg_t m32c_banked_read; | |
291 | static m32c_read_reg_t m32c_sb_read; | |
292 | static m32c_read_reg_t m32c_part_read; | |
293 | static m32c_read_reg_t m32c_cat_read; | |
294 | static m32c_read_reg_t m32c_r3r2r1r0_read; | |
295 | ||
296 | static m32c_write_reg_t m32c_raw_write; | |
297 | static m32c_write_reg_t m32c_banked_write; | |
298 | static m32c_write_reg_t m32c_sb_write; | |
299 | static m32c_write_reg_t m32c_part_write; | |
300 | static m32c_write_reg_t m32c_cat_write; | |
301 | static m32c_write_reg_t m32c_r3r2r1r0_write; | |
96309189 MS |
302 | |
303 | /* Copy the value of the raw register REG from CACHE to BUF. */ | |
05d1431c | 304 | static enum register_status |
849d0ba8 | 305 | m32c_raw_read (struct m32c_reg *reg, readable_regcache *cache, gdb_byte *buf) |
96309189 | 306 | { |
03f50fc8 | 307 | return cache->raw_read (reg->num, buf); |
96309189 MS |
308 | } |
309 | ||
310 | ||
311 | /* Copy the value of the raw register REG from BUF to CACHE. */ | |
05d1431c | 312 | static enum register_status |
6da660c7 SM |
313 | m32c_raw_write (struct m32c_reg *reg, struct regcache *cache, |
314 | const gdb_byte *buf) | |
96309189 | 315 | { |
10eaee5f | 316 | cache->raw_write (reg->num, buf); |
05d1431c PA |
317 | |
318 | return REG_VALID; | |
96309189 MS |
319 | } |
320 | ||
321 | ||
322 | /* Return the value of the 'flg' register in CACHE. */ | |
323 | static int | |
849d0ba8 | 324 | m32c_read_flg (readable_regcache *cache) |
96309189 | 325 | { |
ac7936df | 326 | struct gdbarch_tdep *tdep = gdbarch_tdep (cache->arch ()); |
96309189 | 327 | ULONGEST flg; |
03f50fc8 YQ |
328 | |
329 | cache->raw_read (tdep->flg->num, &flg); | |
96309189 MS |
330 | return flg & 0xffff; |
331 | } | |
332 | ||
333 | ||
7830cb4f CV |
334 | /* Evaluate the real register number of a banked register. */ |
335 | static struct m32c_reg * | |
849d0ba8 | 336 | m32c_banked_register (struct m32c_reg *reg, readable_regcache *cache) |
7830cb4f CV |
337 | { |
338 | return ((m32c_read_flg (cache) & reg->n) ? reg->ry : reg->rx); | |
339 | } | |
340 | ||
341 | ||
96309189 MS |
342 | /* Move the value of a banked register from CACHE to BUF. |
343 | If the value of the 'flg' register in CACHE has any of the bits | |
344 | masked in REG->n set, then read REG->ry. Otherwise, read | |
345 | REG->rx. */ | |
05d1431c | 346 | static enum register_status |
849d0ba8 | 347 | m32c_banked_read (struct m32c_reg *reg, readable_regcache *cache, gdb_byte *buf) |
96309189 | 348 | { |
7830cb4f | 349 | struct m32c_reg *bank_reg = m32c_banked_register (reg, cache); |
03f50fc8 | 350 | return cache->raw_read (bank_reg->num, buf); |
96309189 MS |
351 | } |
352 | ||
353 | ||
354 | /* Move the value of a banked register from BUF to CACHE. | |
355 | If the value of the 'flg' register in CACHE has any of the bits | |
356 | masked in REG->n set, then write REG->ry. Otherwise, write | |
357 | REG->rx. */ | |
05d1431c | 358 | static enum register_status |
6da660c7 SM |
359 | m32c_banked_write (struct m32c_reg *reg, struct regcache *cache, |
360 | const gdb_byte *buf) | |
96309189 | 361 | { |
7830cb4f | 362 | struct m32c_reg *bank_reg = m32c_banked_register (reg, cache); |
10eaee5f | 363 | cache->raw_write (bank_reg->num, buf); |
05d1431c PA |
364 | |
365 | return REG_VALID; | |
96309189 MS |
366 | } |
367 | ||
368 | ||
369 | /* Move the value of SB from CACHE to BUF. On bfd_mach_m32c, SB is a | |
370 | banked register; on bfd_mach_m16c, it's not. */ | |
05d1431c | 371 | static enum register_status |
849d0ba8 | 372 | m32c_sb_read (struct m32c_reg *reg, readable_regcache *cache, gdb_byte *buf) |
96309189 MS |
373 | { |
374 | if (gdbarch_bfd_arch_info (reg->arch)->mach == bfd_mach_m16c) | |
05d1431c | 375 | return m32c_raw_read (reg->rx, cache, buf); |
96309189 | 376 | else |
05d1431c | 377 | return m32c_banked_read (reg, cache, buf); |
96309189 MS |
378 | } |
379 | ||
380 | ||
381 | /* Move the value of SB from BUF to CACHE. On bfd_mach_m32c, SB is a | |
382 | banked register; on bfd_mach_m16c, it's not. */ | |
05d1431c | 383 | static enum register_status |
6da660c7 | 384 | m32c_sb_write (struct m32c_reg *reg, struct regcache *cache, const gdb_byte *buf) |
96309189 MS |
385 | { |
386 | if (gdbarch_bfd_arch_info (reg->arch)->mach == bfd_mach_m16c) | |
387 | m32c_raw_write (reg->rx, cache, buf); | |
388 | else | |
389 | m32c_banked_write (reg, cache, buf); | |
05d1431c PA |
390 | |
391 | return REG_VALID; | |
96309189 MS |
392 | } |
393 | ||
394 | ||
395 | /* Assuming REG uses m32c_part_read and m32c_part_write, set *OFFSET_P | |
396 | and *LEN_P to the offset and length, in bytes, of the part REG | |
397 | occupies in its underlying register. The offset is from the | |
398 | lower-addressed end, regardless of the architecture's endianness. | |
399 | (The M32C family is always little-endian, but let's keep those | |
400 | assumptions out of here.) */ | |
401 | static void | |
402 | m32c_find_part (struct m32c_reg *reg, int *offset_p, int *len_p) | |
403 | { | |
404 | /* The length of the containing register, of which REG is one part. */ | |
405 | int containing_len = TYPE_LENGTH (reg->rx->type); | |
406 | ||
407 | /* The length of one "element" in our imaginary array. */ | |
408 | int elt_len = TYPE_LENGTH (reg->type); | |
409 | ||
410 | /* The offset of REG's "element" from the least significant end of | |
411 | the containing register. */ | |
412 | int elt_offset = reg->n * elt_len; | |
413 | ||
414 | /* If we extend off the end, trim the length of the element. */ | |
415 | if (elt_offset + elt_len > containing_len) | |
416 | { | |
417 | elt_len = containing_len - elt_offset; | |
418 | /* We shouldn't be declaring partial registers that go off the | |
419 | end of their containing registers. */ | |
420 | gdb_assert (elt_len > 0); | |
421 | } | |
422 | ||
423 | /* Flip the offset around if we're big-endian. */ | |
424 | if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG) | |
425 | elt_offset = TYPE_LENGTH (reg->rx->type) - elt_offset - elt_len; | |
426 | ||
427 | *offset_p = elt_offset; | |
428 | *len_p = elt_len; | |
429 | } | |
430 | ||
431 | ||
432 | /* Move the value of a partial register (r0h, intbl, etc.) from CACHE | |
433 | to BUF. Treating the value of the register REG->rx as an array of | |
434 | REG->type values, where higher indices refer to more significant | |
435 | bits, read the value of the REG->n'th element. */ | |
05d1431c | 436 | static enum register_status |
849d0ba8 | 437 | m32c_part_read (struct m32c_reg *reg, readable_regcache *cache, gdb_byte *buf) |
96309189 MS |
438 | { |
439 | int offset, len; | |
05d1431c | 440 | |
96309189 MS |
441 | memset (buf, 0, TYPE_LENGTH (reg->type)); |
442 | m32c_find_part (reg, &offset, &len); | |
03f50fc8 | 443 | return cache->cooked_read_part (reg->rx->num, offset, len, buf); |
96309189 MS |
444 | } |
445 | ||
446 | ||
447 | /* Move the value of a banked register from BUF to CACHE. | |
448 | Treating the value of the register REG->rx as an array of REG->type | |
449 | values, where higher indices refer to more significant bits, write | |
450 | the value of the REG->n'th element. */ | |
05d1431c | 451 | static enum register_status |
6da660c7 SM |
452 | m32c_part_write (struct m32c_reg *reg, struct regcache *cache, |
453 | const gdb_byte *buf) | |
96309189 MS |
454 | { |
455 | int offset, len; | |
05d1431c | 456 | |
96309189 | 457 | m32c_find_part (reg, &offset, &len); |
e4c4a59b | 458 | cache->cooked_write_part (reg->rx->num, offset, len, buf); |
05d1431c PA |
459 | |
460 | return REG_VALID; | |
96309189 MS |
461 | } |
462 | ||
463 | ||
464 | /* Move the value of REG from CACHE to BUF. REG's value is the | |
465 | concatenation of the values of the registers REG->rx and REG->ry, | |
466 | with REG->rx contributing the more significant bits. */ | |
05d1431c | 467 | static enum register_status |
849d0ba8 | 468 | m32c_cat_read (struct m32c_reg *reg, readable_regcache *cache, gdb_byte *buf) |
96309189 MS |
469 | { |
470 | int high_bytes = TYPE_LENGTH (reg->rx->type); | |
471 | int low_bytes = TYPE_LENGTH (reg->ry->type); | |
05d1431c | 472 | enum register_status status; |
96309189 MS |
473 | |
474 | gdb_assert (TYPE_LENGTH (reg->type) == high_bytes + low_bytes); | |
475 | ||
476 | if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG) | |
477 | { | |
11f57cb6 | 478 | status = cache->cooked_read (reg->rx->num, buf); |
05d1431c | 479 | if (status == REG_VALID) |
11f57cb6 | 480 | status = cache->cooked_read (reg->ry->num, buf + high_bytes); |
96309189 MS |
481 | } |
482 | else | |
483 | { | |
11f57cb6 | 484 | status = cache->cooked_read (reg->rx->num, buf + low_bytes); |
05d1431c | 485 | if (status == REG_VALID) |
11f57cb6 | 486 | status = cache->cooked_read (reg->ry->num, buf); |
96309189 | 487 | } |
05d1431c | 488 | return status; |
96309189 MS |
489 | } |
490 | ||
491 | ||
492 | /* Move the value of REG from CACHE to BUF. REG's value is the | |
493 | concatenation of the values of the registers REG->rx and REG->ry, | |
494 | with REG->rx contributing the more significant bits. */ | |
05d1431c | 495 | static enum register_status |
6da660c7 SM |
496 | m32c_cat_write (struct m32c_reg *reg, struct regcache *cache, |
497 | const gdb_byte *buf) | |
96309189 MS |
498 | { |
499 | int high_bytes = TYPE_LENGTH (reg->rx->type); | |
500 | int low_bytes = TYPE_LENGTH (reg->ry->type); | |
96309189 MS |
501 | |
502 | gdb_assert (TYPE_LENGTH (reg->type) == high_bytes + low_bytes); | |
503 | ||
504 | if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG) | |
505 | { | |
b66f5587 SM |
506 | cache->cooked_write (reg->rx->num, buf); |
507 | cache->cooked_write (reg->ry->num, buf + high_bytes); | |
96309189 MS |
508 | } |
509 | else | |
510 | { | |
b66f5587 SM |
511 | cache->cooked_write (reg->rx->num, buf + low_bytes); |
512 | cache->cooked_write (reg->ry->num, buf); | |
96309189 | 513 | } |
05d1431c PA |
514 | |
515 | return REG_VALID; | |
96309189 MS |
516 | } |
517 | ||
518 | ||
519 | /* Copy the value of the raw register REG from CACHE to BUF. REG is | |
520 | the concatenation (from most significant to least) of r3, r2, r1, | |
521 | and r0. */ | |
05d1431c | 522 | static enum register_status |
849d0ba8 | 523 | m32c_r3r2r1r0_read (struct m32c_reg *reg, readable_regcache *cache, gdb_byte *buf) |
96309189 MS |
524 | { |
525 | struct gdbarch_tdep *tdep = gdbarch_tdep (reg->arch); | |
526 | int len = TYPE_LENGTH (tdep->r0->type); | |
05d1431c | 527 | enum register_status status; |
96309189 | 528 | |
96309189 MS |
529 | if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG) |
530 | { | |
11f57cb6 | 531 | status = cache->cooked_read (tdep->r0->num, buf + len * 3); |
05d1431c | 532 | if (status == REG_VALID) |
11f57cb6 | 533 | status = cache->cooked_read (tdep->r1->num, buf + len * 2); |
05d1431c | 534 | if (status == REG_VALID) |
11f57cb6 | 535 | status = cache->cooked_read (tdep->r2->num, buf + len * 1); |
05d1431c | 536 | if (status == REG_VALID) |
11f57cb6 | 537 | status = cache->cooked_read (tdep->r3->num, buf); |
96309189 MS |
538 | } |
539 | else | |
540 | { | |
11f57cb6 | 541 | status = cache->cooked_read (tdep->r0->num, buf); |
05d1431c | 542 | if (status == REG_VALID) |
11f57cb6 | 543 | status = cache->cooked_read (tdep->r1->num, buf + len * 1); |
05d1431c | 544 | if (status == REG_VALID) |
11f57cb6 | 545 | status = cache->cooked_read (tdep->r2->num, buf + len * 2); |
05d1431c | 546 | if (status == REG_VALID) |
11f57cb6 | 547 | status = cache->cooked_read (tdep->r3->num, buf + len * 3); |
96309189 | 548 | } |
05d1431c PA |
549 | |
550 | return status; | |
96309189 MS |
551 | } |
552 | ||
553 | ||
554 | /* Copy the value of the raw register REG from BUF to CACHE. REG is | |
555 | the concatenation (from most significant to least) of r3, r2, r1, | |
556 | and r0. */ | |
05d1431c | 557 | static enum register_status |
6da660c7 SM |
558 | m32c_r3r2r1r0_write (struct m32c_reg *reg, struct regcache *cache, |
559 | const gdb_byte *buf) | |
96309189 MS |
560 | { |
561 | struct gdbarch_tdep *tdep = gdbarch_tdep (reg->arch); | |
562 | int len = TYPE_LENGTH (tdep->r0->type); | |
563 | ||
96309189 MS |
564 | if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG) |
565 | { | |
b66f5587 SM |
566 | cache->cooked_write (tdep->r0->num, buf + len * 3); |
567 | cache->cooked_write (tdep->r1->num, buf + len * 2); | |
568 | cache->cooked_write (tdep->r2->num, buf + len * 1); | |
569 | cache->cooked_write (tdep->r3->num, buf); | |
96309189 MS |
570 | } |
571 | else | |
572 | { | |
b66f5587 SM |
573 | cache->cooked_write (tdep->r0->num, buf); |
574 | cache->cooked_write (tdep->r1->num, buf + len * 1); | |
575 | cache->cooked_write (tdep->r2->num, buf + len * 2); | |
576 | cache->cooked_write (tdep->r3->num, buf + len * 3); | |
96309189 | 577 | } |
05d1431c PA |
578 | |
579 | return REG_VALID; | |
96309189 MS |
580 | } |
581 | ||
582 | ||
05d1431c | 583 | static enum register_status |
96309189 | 584 | m32c_pseudo_register_read (struct gdbarch *arch, |
849d0ba8 | 585 | readable_regcache *cache, |
96309189 MS |
586 | int cookednum, |
587 | gdb_byte *buf) | |
588 | { | |
589 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); | |
590 | struct m32c_reg *reg; | |
591 | ||
592 | gdb_assert (0 <= cookednum && cookednum < tdep->num_regs); | |
ac7936df | 593 | gdb_assert (arch == cache->arch ()); |
96309189 MS |
594 | gdb_assert (arch == tdep->regs[cookednum].arch); |
595 | reg = &tdep->regs[cookednum]; | |
596 | ||
05d1431c | 597 | return reg->read (reg, cache, buf); |
96309189 MS |
598 | } |
599 | ||
600 | ||
601 | static void | |
602 | m32c_pseudo_register_write (struct gdbarch *arch, | |
603 | struct regcache *cache, | |
604 | int cookednum, | |
605 | const gdb_byte *buf) | |
606 | { | |
607 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); | |
608 | struct m32c_reg *reg; | |
609 | ||
610 | gdb_assert (0 <= cookednum && cookednum < tdep->num_regs); | |
ac7936df | 611 | gdb_assert (arch == cache->arch ()); |
96309189 MS |
612 | gdb_assert (arch == tdep->regs[cookednum].arch); |
613 | reg = &tdep->regs[cookednum]; | |
614 | ||
6da660c7 | 615 | reg->write (reg, cache, buf); |
96309189 MS |
616 | } |
617 | ||
618 | ||
619 | /* Add a register with the given fields to the end of ARCH's table. | |
620 | Return a pointer to the newly added register. */ | |
621 | static struct m32c_reg * | |
622 | add_reg (struct gdbarch *arch, | |
623 | const char *name, | |
624 | struct type *type, | |
625 | int sim_num, | |
6da660c7 SM |
626 | m32c_read_reg_t *read, |
627 | m32c_write_reg_t *write, | |
96309189 MS |
628 | struct m32c_reg *rx, |
629 | struct m32c_reg *ry, | |
630 | int n) | |
631 | { | |
632 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); | |
633 | struct m32c_reg *r = &tdep->regs[tdep->num_regs]; | |
634 | ||
635 | gdb_assert (tdep->num_regs < M32C_MAX_NUM_REGS); | |
636 | ||
637 | r->name = name; | |
638 | r->type = type; | |
639 | r->arch = arch; | |
640 | r->num = tdep->num_regs; | |
641 | r->sim_num = sim_num; | |
642 | r->dwarf_num = -1; | |
643 | r->general_p = 0; | |
644 | r->dma_p = 0; | |
645 | r->system_p = 0; | |
646 | r->save_restore_p = 0; | |
647 | r->read = read; | |
648 | r->write = write; | |
649 | r->rx = rx; | |
650 | r->ry = ry; | |
651 | r->n = n; | |
652 | ||
653 | tdep->num_regs++; | |
654 | ||
655 | return r; | |
656 | } | |
657 | ||
658 | ||
659 | /* Record NUM as REG's DWARF register number. */ | |
660 | static void | |
661 | set_dwarf_regnum (struct m32c_reg *reg, int num) | |
662 | { | |
663 | gdb_assert (num < M32C_MAX_NUM_REGS); | |
664 | ||
665 | /* Update the reg->DWARF mapping. Only count the first number | |
666 | assigned to this register. */ | |
667 | if (reg->dwarf_num == -1) | |
668 | reg->dwarf_num = num; | |
669 | ||
670 | /* Update the DWARF->reg mapping. */ | |
671 | gdbarch_tdep (reg->arch)->dwarf_regs[num] = reg; | |
672 | } | |
673 | ||
674 | ||
675 | /* Mark REG as a general-purpose register, and return it. */ | |
676 | static struct m32c_reg * | |
677 | mark_general (struct m32c_reg *reg) | |
678 | { | |
679 | reg->general_p = 1; | |
680 | return reg; | |
681 | } | |
682 | ||
683 | ||
374fd1fd TT |
684 | /* Mark REG as a DMA register. */ |
685 | static void | |
96309189 MS |
686 | mark_dma (struct m32c_reg *reg) |
687 | { | |
688 | reg->dma_p = 1; | |
96309189 MS |
689 | } |
690 | ||
691 | ||
692 | /* Mark REG as a SYSTEM register, and return it. */ | |
693 | static struct m32c_reg * | |
694 | mark_system (struct m32c_reg *reg) | |
695 | { | |
696 | reg->system_p = 1; | |
697 | return reg; | |
698 | } | |
699 | ||
700 | ||
701 | /* Mark REG as a save-restore register, and return it. */ | |
702 | static struct m32c_reg * | |
703 | mark_save_restore (struct m32c_reg *reg) | |
704 | { | |
705 | reg->save_restore_p = 1; | |
706 | return reg; | |
707 | } | |
708 | ||
709 | ||
710 | #define FLAGBIT_B 0x0010 | |
711 | #define FLAGBIT_U 0x0080 | |
712 | ||
713 | /* Handy macros for declaring registers. These all evaluate to | |
714 | pointers to the register declared. Macros that define two | |
715 | registers evaluate to a pointer to the first. */ | |
716 | ||
717 | /* A raw register named NAME, with type TYPE and sim number SIM_NUM. */ | |
718 | #define R(name, type, sim_num) \ | |
719 | (add_reg (arch, (name), (type), (sim_num), \ | |
720 | m32c_raw_read, m32c_raw_write, NULL, NULL, 0)) | |
721 | ||
722 | /* The simulator register number for a raw register named NAME. */ | |
723 | #define SIM(name) (m32c_sim_reg_ ## name) | |
724 | ||
725 | /* A raw unsigned 16-bit data register named NAME. | |
726 | NAME should be an identifier, not a string. */ | |
727 | #define R16U(name) \ | |
728 | (R(#name, tdep->uint16, SIM (name))) | |
729 | ||
730 | /* A raw data address register named NAME. | |
731 | NAME should be an identifier, not a string. */ | |
732 | #define RA(name) \ | |
733 | (R(#name, tdep->data_addr_reg_type, SIM (name))) | |
734 | ||
735 | /* A raw code address register named NAME. NAME should | |
736 | be an identifier, not a string. */ | |
737 | #define RC(name) \ | |
738 | (R(#name, tdep->code_addr_reg_type, SIM (name))) | |
739 | ||
740 | /* A pair of raw registers named NAME0 and NAME1, with type TYPE. | |
741 | NAME should be an identifier, not a string. */ | |
742 | #define RP(name, type) \ | |
743 | (R(#name "0", (type), SIM (name ## 0)), \ | |
744 | R(#name "1", (type), SIM (name ## 1)) - 1) | |
745 | ||
746 | /* A raw banked general-purpose data register named NAME. | |
747 | NAME should be an identifier, not a string. */ | |
748 | #define RBD(name) \ | |
749 | (R(NULL, tdep->int16, SIM (name ## _bank0)), \ | |
750 | R(NULL, tdep->int16, SIM (name ## _bank1)) - 1) | |
751 | ||
752 | /* A raw banked data address register named NAME. | |
753 | NAME should be an identifier, not a string. */ | |
754 | #define RBA(name) \ | |
755 | (R(NULL, tdep->data_addr_reg_type, SIM (name ## _bank0)), \ | |
756 | R(NULL, tdep->data_addr_reg_type, SIM (name ## _bank1)) - 1) | |
757 | ||
758 | /* A cooked register named NAME referring to a raw banked register | |
759 | from the bank selected by the current value of FLG. RAW_PAIR | |
760 | should be a pointer to the first register in the banked pair. | |
761 | NAME must be an identifier, not a string. */ | |
762 | #define CB(name, raw_pair) \ | |
763 | (add_reg (arch, #name, (raw_pair)->type, 0, \ | |
764 | m32c_banked_read, m32c_banked_write, \ | |
dda83cd7 | 765 | (raw_pair), (raw_pair + 1), FLAGBIT_B)) |
96309189 MS |
766 | |
767 | /* A pair of registers named NAMEH and NAMEL, of type TYPE, that | |
768 | access the top and bottom halves of the register pointed to by | |
769 | NAME. NAME should be an identifier. */ | |
770 | #define CHL(name, type) \ | |
771 | (add_reg (arch, #name "h", (type), 0, \ | |
772 | m32c_part_read, m32c_part_write, name, NULL, 1), \ | |
773 | add_reg (arch, #name "l", (type), 0, \ | |
774 | m32c_part_read, m32c_part_write, name, NULL, 0) - 1) | |
775 | ||
776 | /* A register constructed by concatenating the two registers HIGH and | |
777 | LOW, whose name is HIGHLOW and whose type is TYPE. */ | |
778 | #define CCAT(high, low, type) \ | |
779 | (add_reg (arch, #high #low, (type), 0, \ | |
780 | m32c_cat_read, m32c_cat_write, (high), (low), 0)) | |
781 | ||
782 | /* Abbreviations for marking register group membership. */ | |
783 | #define G(reg) (mark_general (reg)) | |
784 | #define S(reg) (mark_system (reg)) | |
785 | #define DMA(reg) (mark_dma (reg)) | |
786 | ||
787 | ||
788 | /* Construct the register set for ARCH. */ | |
789 | static void | |
790 | make_regs (struct gdbarch *arch) | |
791 | { | |
792 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); | |
793 | int mach = gdbarch_bfd_arch_info (arch)->mach; | |
f79b9530 DJ |
794 | int num_raw_regs; |
795 | int num_cooked_regs; | |
796 | ||
797 | struct m32c_reg *r0; | |
798 | struct m32c_reg *r1; | |
799 | struct m32c_reg *r2; | |
800 | struct m32c_reg *r3; | |
801 | struct m32c_reg *a0; | |
802 | struct m32c_reg *a1; | |
803 | struct m32c_reg *fb; | |
804 | struct m32c_reg *sb; | |
805 | struct m32c_reg *sp; | |
806 | struct m32c_reg *r0hl; | |
807 | struct m32c_reg *r1hl; | |
f79b9530 DJ |
808 | struct m32c_reg *r2r0; |
809 | struct m32c_reg *r3r1; | |
810 | struct m32c_reg *r3r1r2r0; | |
811 | struct m32c_reg *r3r2r1r0; | |
812 | struct m32c_reg *a1a0; | |
96309189 MS |
813 | |
814 | struct m32c_reg *raw_r0_pair = RBD (r0); | |
815 | struct m32c_reg *raw_r1_pair = RBD (r1); | |
816 | struct m32c_reg *raw_r2_pair = RBD (r2); | |
817 | struct m32c_reg *raw_r3_pair = RBD (r3); | |
818 | struct m32c_reg *raw_a0_pair = RBA (a0); | |
819 | struct m32c_reg *raw_a1_pair = RBA (a1); | |
820 | struct m32c_reg *raw_fb_pair = RBA (fb); | |
821 | ||
822 | /* sb is banked on the bfd_mach_m32c, but not on bfd_mach_m16c. | |
823 | We always declare both raw registers, and deal with the distinction | |
824 | in the pseudoregister. */ | |
825 | struct m32c_reg *raw_sb_pair = RBA (sb); | |
826 | ||
827 | struct m32c_reg *usp = S (RA (usp)); | |
828 | struct m32c_reg *isp = S (RA (isp)); | |
829 | struct m32c_reg *intb = S (RC (intb)); | |
830 | struct m32c_reg *pc = G (RC (pc)); | |
831 | struct m32c_reg *flg = G (R16U (flg)); | |
832 | ||
833 | if (mach == bfd_mach_m32c) | |
834 | { | |
374fd1fd TT |
835 | S (R16U (svf)); |
836 | S (RC (svp)); | |
837 | S (RC (vct)); | |
838 | ||
839 | DMA (RP (dmd, tdep->uint8)); | |
840 | DMA (RP (dct, tdep->uint16)); | |
841 | DMA (RP (drc, tdep->uint16)); | |
842 | DMA (RP (dma, tdep->data_addr_reg_type)); | |
843 | DMA (RP (dsa, tdep->data_addr_reg_type)); | |
844 | DMA (RP (dra, tdep->data_addr_reg_type)); | |
96309189 MS |
845 | } |
846 | ||
f79b9530 | 847 | num_raw_regs = tdep->num_regs; |
96309189 | 848 | |
f79b9530 DJ |
849 | r0 = G (CB (r0, raw_r0_pair)); |
850 | r1 = G (CB (r1, raw_r1_pair)); | |
851 | r2 = G (CB (r2, raw_r2_pair)); | |
852 | r3 = G (CB (r3, raw_r3_pair)); | |
853 | a0 = G (CB (a0, raw_a0_pair)); | |
854 | a1 = G (CB (a1, raw_a1_pair)); | |
855 | fb = G (CB (fb, raw_fb_pair)); | |
96309189 MS |
856 | |
857 | /* sb is banked on the bfd_mach_m32c, but not on bfd_mach_m16c. | |
858 | Specify custom read/write functions that do the right thing. */ | |
f79b9530 DJ |
859 | sb = G (add_reg (arch, "sb", raw_sb_pair->type, 0, |
860 | m32c_sb_read, m32c_sb_write, | |
861 | raw_sb_pair, raw_sb_pair + 1, 0)); | |
96309189 MS |
862 | |
863 | /* The current sp is either usp or isp, depending on the value of | |
864 | the FLG register's U bit. */ | |
f79b9530 DJ |
865 | sp = G (add_reg (arch, "sp", usp->type, 0, |
866 | m32c_banked_read, m32c_banked_write, | |
867 | isp, usp, FLAGBIT_U)); | |
96309189 | 868 | |
f79b9530 DJ |
869 | r0hl = CHL (r0, tdep->int8); |
870 | r1hl = CHL (r1, tdep->int8); | |
ac298888 TT |
871 | CHL (r2, tdep->int8); |
872 | CHL (r3, tdep->int8); | |
873 | CHL (intb, tdep->int16); | |
96309189 | 874 | |
f79b9530 DJ |
875 | r2r0 = CCAT (r2, r0, tdep->int32); |
876 | r3r1 = CCAT (r3, r1, tdep->int32); | |
877 | r3r1r2r0 = CCAT (r3r1, r2r0, tdep->int64); | |
96309189 | 878 | |
f79b9530 | 879 | r3r2r1r0 |
96309189 MS |
880 | = add_reg (arch, "r3r2r1r0", tdep->int64, 0, |
881 | m32c_r3r2r1r0_read, m32c_r3r2r1r0_write, NULL, NULL, 0); | |
882 | ||
96309189 MS |
883 | if (mach == bfd_mach_m16c) |
884 | a1a0 = CCAT (a1, a0, tdep->int32); | |
885 | else | |
886 | a1a0 = NULL; | |
887 | ||
f79b9530 | 888 | num_cooked_regs = tdep->num_regs - num_raw_regs; |
96309189 MS |
889 | |
890 | tdep->pc = pc; | |
891 | tdep->flg = flg; | |
892 | tdep->r0 = r0; | |
893 | tdep->r1 = r1; | |
894 | tdep->r2 = r2; | |
895 | tdep->r3 = r3; | |
896 | tdep->r2r0 = r2r0; | |
897 | tdep->r3r2r1r0 = r3r2r1r0; | |
898 | tdep->r3r1r2r0 = r3r1r2r0; | |
899 | tdep->a0 = a0; | |
900 | tdep->a1 = a1; | |
901 | tdep->sb = sb; | |
902 | tdep->fb = fb; | |
903 | tdep->sp = sp; | |
904 | ||
905 | /* Set up the DWARF register table. */ | |
906 | memset (tdep->dwarf_regs, 0, sizeof (tdep->dwarf_regs)); | |
907 | set_dwarf_regnum (r0hl + 1, 0x01); | |
908 | set_dwarf_regnum (r0hl + 0, 0x02); | |
909 | set_dwarf_regnum (r1hl + 1, 0x03); | |
910 | set_dwarf_regnum (r1hl + 0, 0x04); | |
911 | set_dwarf_regnum (r0, 0x05); | |
912 | set_dwarf_regnum (r1, 0x06); | |
913 | set_dwarf_regnum (r2, 0x07); | |
914 | set_dwarf_regnum (r3, 0x08); | |
915 | set_dwarf_regnum (a0, 0x09); | |
916 | set_dwarf_regnum (a1, 0x0a); | |
917 | set_dwarf_regnum (fb, 0x0b); | |
918 | set_dwarf_regnum (sp, 0x0c); | |
919 | set_dwarf_regnum (pc, 0x0d); /* GCC's invention */ | |
920 | set_dwarf_regnum (sb, 0x13); | |
921 | set_dwarf_regnum (r2r0, 0x15); | |
922 | set_dwarf_regnum (r3r1, 0x16); | |
923 | if (a1a0) | |
924 | set_dwarf_regnum (a1a0, 0x17); | |
925 | ||
926 | /* Enumerate the save/restore register group. | |
927 | ||
928 | The regcache_save and regcache_restore functions apply their read | |
929 | function to each register in this group. | |
930 | ||
931 | Since frame_pop supplies frame_unwind_register as its read | |
932 | function, the registers meaningful to the Dwarf unwinder need to | |
933 | be in this group. | |
934 | ||
935 | On the other hand, when we make inferior calls, save_inferior_status | |
936 | and restore_inferior_status use them to preserve the current register | |
937 | values across the inferior call. For this, you'd kind of like to | |
938 | preserve all the raw registers, to protect the interrupted code from | |
939 | any sort of bank switching the callee might have done. But we handle | |
940 | those cases so badly anyway --- for example, it matters whether we | |
941 | restore FLG before or after we restore the general-purpose registers, | |
942 | but there's no way to express that --- that it isn't worth worrying | |
943 | about. | |
944 | ||
945 | We omit control registers like inthl: if you call a function that | |
946 | changes those, it's probably because you wanted that change to be | |
947 | visible to the interrupted code. */ | |
948 | mark_save_restore (r0); | |
949 | mark_save_restore (r1); | |
950 | mark_save_restore (r2); | |
951 | mark_save_restore (r3); | |
952 | mark_save_restore (a0); | |
953 | mark_save_restore (a1); | |
954 | mark_save_restore (sb); | |
955 | mark_save_restore (fb); | |
956 | mark_save_restore (sp); | |
957 | mark_save_restore (pc); | |
958 | mark_save_restore (flg); | |
959 | ||
960 | set_gdbarch_num_regs (arch, num_raw_regs); | |
961 | set_gdbarch_num_pseudo_regs (arch, num_cooked_regs); | |
962 | set_gdbarch_pc_regnum (arch, pc->num); | |
963 | set_gdbarch_sp_regnum (arch, sp->num); | |
964 | set_gdbarch_register_name (arch, m32c_register_name); | |
965 | set_gdbarch_register_type (arch, m32c_register_type); | |
966 | set_gdbarch_pseudo_register_read (arch, m32c_pseudo_register_read); | |
967 | set_gdbarch_pseudo_register_write (arch, m32c_pseudo_register_write); | |
968 | set_gdbarch_register_sim_regno (arch, m32c_register_sim_regno); | |
969 | set_gdbarch_stab_reg_to_regnum (arch, m32c_debug_info_reg_to_regnum); | |
96309189 MS |
970 | set_gdbarch_dwarf2_reg_to_regnum (arch, m32c_debug_info_reg_to_regnum); |
971 | set_gdbarch_register_reggroup_p (arch, m32c_register_reggroup_p); | |
972 | ||
973 | reggroup_add (arch, general_reggroup); | |
974 | reggroup_add (arch, all_reggroup); | |
975 | reggroup_add (arch, save_reggroup); | |
976 | reggroup_add (arch, restore_reggroup); | |
977 | reggroup_add (arch, system_reggroup); | |
978 | reggroup_add (arch, m32c_dma_reggroup); | |
979 | } | |
980 | ||
981 | ||
982 | \f | |
983 | /* Breakpoints. */ | |
04180708 | 984 | constexpr gdb_byte m32c_break_insn[] = { 0x00 }; /* brk */ |
96309189 | 985 | |
04180708 | 986 | typedef BP_MANIPULATION (m32c_break_insn) m32c_breakpoint; |
96309189 MS |
987 | |
988 | \f | |
989 | /* Prologue analysis. */ | |
990 | ||
52059ffd TT |
991 | enum m32c_prologue_kind |
992 | { | |
993 | /* This function uses a frame pointer. */ | |
994 | prologue_with_frame_ptr, | |
995 | ||
996 | /* This function has no frame pointer. */ | |
997 | prologue_sans_frame_ptr, | |
998 | ||
999 | /* This function sets up the stack, so its frame is the first | |
1000 | frame on the stack. */ | |
1001 | prologue_first_frame | |
1002 | }; | |
1003 | ||
96309189 MS |
1004 | struct m32c_prologue |
1005 | { | |
1006 | /* For consistency with the DWARF 2 .debug_frame info generated by | |
1007 | GCC, a frame's CFA is the address immediately after the saved | |
1008 | return address. */ | |
1009 | ||
1010 | /* The architecture for which we generated this prologue info. */ | |
1011 | struct gdbarch *arch; | |
1012 | ||
52059ffd | 1013 | enum m32c_prologue_kind kind; |
96309189 MS |
1014 | |
1015 | /* If KIND is prologue_with_frame_ptr, this is the offset from the | |
1016 | CFA to where the frame pointer points. This is always zero or | |
1017 | negative. */ | |
1018 | LONGEST frame_ptr_offset; | |
1019 | ||
1020 | /* If KIND is prologue_sans_frame_ptr, the offset from the CFA to | |
1021 | the stack pointer --- always zero or negative. | |
1022 | ||
1023 | Calling this a "size" is a bit misleading, but given that the | |
1024 | stack grows downwards, using offsets for everything keeps one | |
1025 | from going completely sign-crazy: you never change anything's | |
1026 | sign for an ADD instruction; always change the second operand's | |
1027 | sign for a SUB instruction; and everything takes care of | |
1028 | itself. | |
1029 | ||
1030 | Functions that use alloca don't have a constant frame size. But | |
1031 | they always have frame pointers, so we must use that to find the | |
1032 | CFA (and perhaps to unwind the stack pointer). */ | |
1033 | LONGEST frame_size; | |
1034 | ||
1035 | /* The address of the first instruction at which the frame has been | |
1036 | set up and the arguments are where the debug info says they are | |
1037 | --- as best as we can tell. */ | |
1038 | CORE_ADDR prologue_end; | |
1039 | ||
1040 | /* reg_offset[R] is the offset from the CFA at which register R is | |
1041 | saved, or 1 if register R has not been saved. (Real values are | |
1042 | always zero or negative.) */ | |
1043 | LONGEST reg_offset[M32C_MAX_NUM_REGS]; | |
1044 | }; | |
1045 | ||
1046 | ||
1047 | /* The longest I've seen, anyway. */ | |
1048 | #define M32C_MAX_INSN_LEN (9) | |
1049 | ||
1050 | /* Processor state, for the prologue analyzer. */ | |
1051 | struct m32c_pv_state | |
1052 | { | |
1053 | struct gdbarch *arch; | |
1054 | pv_t r0, r1, r2, r3; | |
1055 | pv_t a0, a1; | |
1056 | pv_t sb, fb, sp; | |
1057 | pv_t pc; | |
1058 | struct pv_area *stack; | |
1059 | ||
1060 | /* Bytes from the current PC, the address they were read from, | |
1061 | and the address of the next unconsumed byte. */ | |
1062 | gdb_byte insn[M32C_MAX_INSN_LEN]; | |
1063 | CORE_ADDR scan_pc, next_addr; | |
1064 | }; | |
1065 | ||
1066 | ||
1067 | /* Push VALUE on STATE's stack, occupying SIZE bytes. Return zero if | |
1068 | all went well, or non-zero if simulating the action would trash our | |
1069 | state. */ | |
1070 | static int | |
1071 | m32c_pv_push (struct m32c_pv_state *state, pv_t value, int size) | |
1072 | { | |
f7b7ed97 | 1073 | if (state->stack->store_would_trash (state->sp)) |
96309189 MS |
1074 | return 1; |
1075 | ||
1076 | state->sp = pv_add_constant (state->sp, -size); | |
f7b7ed97 | 1077 | state->stack->store (state->sp, size, value); |
96309189 MS |
1078 | |
1079 | return 0; | |
1080 | } | |
1081 | ||
1082 | ||
52059ffd TT |
1083 | enum srcdest_kind |
1084 | { | |
1085 | srcdest_reg, | |
1086 | srcdest_partial_reg, | |
1087 | srcdest_mem | |
1088 | }; | |
1089 | ||
96309189 MS |
1090 | /* A source or destination location for an m16c or m32c |
1091 | instruction. */ | |
1092 | struct srcdest | |
1093 | { | |
1094 | /* If srcdest_reg, the location is a register pointed to by REG. | |
1095 | If srcdest_partial_reg, the location is part of a register pointed | |
1096 | to by REG. We don't try to handle this too well. | |
1097 | If srcdest_mem, the location is memory whose address is ADDR. */ | |
52059ffd | 1098 | enum srcdest_kind kind; |
96309189 MS |
1099 | pv_t *reg, addr; |
1100 | }; | |
1101 | ||
1102 | ||
1103 | /* Return the SIZE-byte value at LOC in STATE. */ | |
1104 | static pv_t | |
1105 | m32c_srcdest_fetch (struct m32c_pv_state *state, struct srcdest loc, int size) | |
1106 | { | |
1107 | if (loc.kind == srcdest_mem) | |
f7b7ed97 | 1108 | return state->stack->fetch (loc.addr, size); |
96309189 MS |
1109 | else if (loc.kind == srcdest_partial_reg) |
1110 | return pv_unknown (); | |
1111 | else | |
1112 | return *loc.reg; | |
1113 | } | |
1114 | ||
1115 | ||
1116 | /* Write VALUE, a SIZE-byte value, to LOC in STATE. Return zero if | |
1117 | all went well, or non-zero if simulating the store would trash our | |
1118 | state. */ | |
1119 | static int | |
1120 | m32c_srcdest_store (struct m32c_pv_state *state, struct srcdest loc, | |
1121 | pv_t value, int size) | |
1122 | { | |
1123 | if (loc.kind == srcdest_mem) | |
1124 | { | |
f7b7ed97 | 1125 | if (state->stack->store_would_trash (loc.addr)) |
96309189 | 1126 | return 1; |
f7b7ed97 | 1127 | state->stack->store (loc.addr, size, value); |
96309189 MS |
1128 | } |
1129 | else if (loc.kind == srcdest_partial_reg) | |
1130 | *loc.reg = pv_unknown (); | |
1131 | else | |
1132 | *loc.reg = value; | |
1133 | ||
1134 | return 0; | |
1135 | } | |
1136 | ||
1137 | ||
1138 | static int | |
1139 | m32c_sign_ext (int v, int bits) | |
1140 | { | |
1141 | int mask = 1 << (bits - 1); | |
1142 | return (v ^ mask) - mask; | |
1143 | } | |
1144 | ||
1145 | static unsigned int | |
1146 | m32c_next_byte (struct m32c_pv_state *st) | |
1147 | { | |
1148 | gdb_assert (st->next_addr - st->scan_pc < sizeof (st->insn)); | |
1149 | return st->insn[st->next_addr++ - st->scan_pc]; | |
1150 | } | |
1151 | ||
1152 | static int | |
1153 | m32c_udisp8 (struct m32c_pv_state *st) | |
1154 | { | |
1155 | return m32c_next_byte (st); | |
1156 | } | |
1157 | ||
1158 | ||
1159 | static int | |
1160 | m32c_sdisp8 (struct m32c_pv_state *st) | |
1161 | { | |
1162 | return m32c_sign_ext (m32c_next_byte (st), 8); | |
1163 | } | |
1164 | ||
1165 | ||
1166 | static int | |
1167 | m32c_udisp16 (struct m32c_pv_state *st) | |
1168 | { | |
1169 | int low = m32c_next_byte (st); | |
1170 | int high = m32c_next_byte (st); | |
1171 | ||
1172 | return low + (high << 8); | |
1173 | } | |
1174 | ||
1175 | ||
1176 | static int | |
1177 | m32c_sdisp16 (struct m32c_pv_state *st) | |
1178 | { | |
1179 | int low = m32c_next_byte (st); | |
1180 | int high = m32c_next_byte (st); | |
1181 | ||
1182 | return m32c_sign_ext (low + (high << 8), 16); | |
1183 | } | |
1184 | ||
1185 | ||
1186 | static int | |
1187 | m32c_udisp24 (struct m32c_pv_state *st) | |
1188 | { | |
1189 | int low = m32c_next_byte (st); | |
1190 | int mid = m32c_next_byte (st); | |
1191 | int high = m32c_next_byte (st); | |
1192 | ||
1193 | return low + (mid << 8) + (high << 16); | |
1194 | } | |
1195 | ||
1196 | ||
1197 | /* Extract the 'source' field from an m32c MOV.size:G-format instruction. */ | |
1198 | static int | |
1199 | m32c_get_src23 (unsigned char *i) | |
1200 | { | |
1201 | return (((i[0] & 0x70) >> 2) | |
1202 | | ((i[1] & 0x30) >> 4)); | |
1203 | } | |
1204 | ||
1205 | ||
1206 | /* Extract the 'dest' field from an m32c MOV.size:G-format instruction. */ | |
1207 | static int | |
1208 | m32c_get_dest23 (unsigned char *i) | |
1209 | { | |
1210 | return (((i[0] & 0x0e) << 1) | |
1211 | | ((i[1] & 0xc0) >> 6)); | |
1212 | } | |
1213 | ||
1214 | ||
1215 | static struct srcdest | |
1216 | m32c_decode_srcdest4 (struct m32c_pv_state *st, | |
1217 | int code, int size) | |
1218 | { | |
1219 | struct srcdest sd; | |
1220 | ||
1221 | if (code < 6) | |
1222 | sd.kind = (size == 2 ? srcdest_reg : srcdest_partial_reg); | |
1223 | else | |
1224 | sd.kind = srcdest_mem; | |
1225 | ||
d56874a7 DD |
1226 | sd.addr = pv_unknown (); |
1227 | sd.reg = 0; | |
1228 | ||
96309189 MS |
1229 | switch (code) |
1230 | { | |
a4497d2f | 1231 | case 0x0: sd.reg = &st->r0; break; |
96309189 MS |
1232 | case 0x1: sd.reg = (size == 1 ? &st->r0 : &st->r1); break; |
1233 | case 0x2: sd.reg = (size == 1 ? &st->r1 : &st->r2); break; | |
1234 | case 0x3: sd.reg = (size == 1 ? &st->r1 : &st->r3); break; | |
1235 | ||
1236 | case 0x4: sd.reg = &st->a0; break; | |
1237 | case 0x5: sd.reg = &st->a1; break; | |
1238 | ||
1239 | case 0x6: sd.addr = st->a0; break; | |
1240 | case 0x7: sd.addr = st->a1; break; | |
1241 | ||
1242 | case 0x8: sd.addr = pv_add_constant (st->a0, m32c_udisp8 (st)); break; | |
1243 | case 0x9: sd.addr = pv_add_constant (st->a1, m32c_udisp8 (st)); break; | |
1244 | case 0xa: sd.addr = pv_add_constant (st->sb, m32c_udisp8 (st)); break; | |
1245 | case 0xb: sd.addr = pv_add_constant (st->fb, m32c_sdisp8 (st)); break; | |
1246 | ||
1247 | case 0xc: sd.addr = pv_add_constant (st->a0, m32c_udisp16 (st)); break; | |
1248 | case 0xd: sd.addr = pv_add_constant (st->a1, m32c_udisp16 (st)); break; | |
1249 | case 0xe: sd.addr = pv_add_constant (st->sb, m32c_udisp16 (st)); break; | |
1250 | case 0xf: sd.addr = pv_constant (m32c_udisp16 (st)); break; | |
1251 | ||
1252 | default: | |
f3574227 | 1253 | gdb_assert_not_reached ("unexpected srcdest4"); |
96309189 MS |
1254 | } |
1255 | ||
1256 | return sd; | |
1257 | } | |
1258 | ||
1259 | ||
1260 | static struct srcdest | |
1261 | m32c_decode_sd23 (struct m32c_pv_state *st, int code, int size, int ind) | |
1262 | { | |
1263 | struct srcdest sd; | |
1264 | ||
d56874a7 DD |
1265 | sd.addr = pv_unknown (); |
1266 | sd.reg = 0; | |
1267 | ||
96309189 MS |
1268 | switch (code) |
1269 | { | |
1270 | case 0x12: | |
1271 | case 0x13: | |
1272 | case 0x10: | |
1273 | case 0x11: | |
1274 | sd.kind = (size == 1) ? srcdest_partial_reg : srcdest_reg; | |
1275 | break; | |
1276 | ||
1277 | case 0x02: | |
1278 | case 0x03: | |
1279 | sd.kind = (size == 4) ? srcdest_reg : srcdest_partial_reg; | |
1280 | break; | |
1281 | ||
1282 | default: | |
1283 | sd.kind = srcdest_mem; | |
1284 | break; | |
1285 | ||
1286 | } | |
1287 | ||
1288 | switch (code) | |
1289 | { | |
1290 | case 0x12: sd.reg = &st->r0; break; | |
1291 | case 0x13: sd.reg = &st->r1; break; | |
1292 | case 0x10: sd.reg = ((size == 1) ? &st->r0 : &st->r2); break; | |
1293 | case 0x11: sd.reg = ((size == 1) ? &st->r1 : &st->r3); break; | |
1294 | case 0x02: sd.reg = &st->a0; break; | |
1295 | case 0x03: sd.reg = &st->a1; break; | |
1296 | ||
1297 | case 0x00: sd.addr = st->a0; break; | |
1298 | case 0x01: sd.addr = st->a1; break; | |
1299 | case 0x04: sd.addr = pv_add_constant (st->a0, m32c_udisp8 (st)); break; | |
1300 | case 0x05: sd.addr = pv_add_constant (st->a1, m32c_udisp8 (st)); break; | |
1301 | case 0x06: sd.addr = pv_add_constant (st->sb, m32c_udisp8 (st)); break; | |
1302 | case 0x07: sd.addr = pv_add_constant (st->fb, m32c_sdisp8 (st)); break; | |
1303 | case 0x08: sd.addr = pv_add_constant (st->a0, m32c_udisp16 (st)); break; | |
1304 | case 0x09: sd.addr = pv_add_constant (st->a1, m32c_udisp16 (st)); break; | |
1305 | case 0x0a: sd.addr = pv_add_constant (st->sb, m32c_udisp16 (st)); break; | |
1306 | case 0x0b: sd.addr = pv_add_constant (st->fb, m32c_sdisp16 (st)); break; | |
1307 | case 0x0c: sd.addr = pv_add_constant (st->a0, m32c_udisp24 (st)); break; | |
1308 | case 0x0d: sd.addr = pv_add_constant (st->a1, m32c_udisp24 (st)); break; | |
1309 | case 0x0f: sd.addr = pv_constant (m32c_udisp16 (st)); break; | |
1310 | case 0x0e: sd.addr = pv_constant (m32c_udisp24 (st)); break; | |
1311 | default: | |
f3574227 | 1312 | gdb_assert_not_reached ("unexpected sd23"); |
96309189 MS |
1313 | } |
1314 | ||
1315 | if (ind) | |
1316 | { | |
1317 | sd.addr = m32c_srcdest_fetch (st, sd, 4); | |
1318 | sd.kind = srcdest_mem; | |
1319 | } | |
1320 | ||
1321 | return sd; | |
1322 | } | |
1323 | ||
1324 | ||
1325 | /* The r16c and r32c machines have instructions with similar | |
1326 | semantics, but completely different machine language encodings. So | |
1327 | we break out the semantics into their own functions, and leave | |
1328 | machine-specific decoding in m32c_analyze_prologue. | |
1329 | ||
1330 | The following functions all expect their arguments already decoded, | |
1331 | and they all return zero if analysis should continue past this | |
1332 | instruction, or non-zero if analysis should stop. */ | |
1333 | ||
1334 | ||
1335 | /* Simulate an 'enter SIZE' instruction in STATE. */ | |
1336 | static int | |
1337 | m32c_pv_enter (struct m32c_pv_state *state, int size) | |
1338 | { | |
1339 | struct gdbarch_tdep *tdep = gdbarch_tdep (state->arch); | |
1340 | ||
1341 | /* If simulating this store would require us to forget | |
1342 | everything we know about the stack frame in the name of | |
1343 | accuracy, it would be better to just quit now. */ | |
f7b7ed97 | 1344 | if (state->stack->store_would_trash (state->sp)) |
96309189 MS |
1345 | return 1; |
1346 | ||
1347 | if (m32c_pv_push (state, state->fb, tdep->push_addr_bytes)) | |
1348 | return 1; | |
1349 | state->fb = state->sp; | |
1350 | state->sp = pv_add_constant (state->sp, -size); | |
1351 | ||
1352 | return 0; | |
1353 | } | |
1354 | ||
1355 | ||
1356 | static int | |
1357 | m32c_pv_pushm_one (struct m32c_pv_state *state, pv_t reg, | |
1358 | int bit, int src, int size) | |
1359 | { | |
1360 | if (bit & src) | |
1361 | { | |
1362 | if (m32c_pv_push (state, reg, size)) | |
1363 | return 1; | |
1364 | } | |
1365 | ||
1366 | return 0; | |
1367 | } | |
1368 | ||
1369 | ||
1370 | /* Simulate a 'pushm SRC' instruction in STATE. */ | |
1371 | static int | |
1372 | m32c_pv_pushm (struct m32c_pv_state *state, int src) | |
1373 | { | |
1374 | struct gdbarch_tdep *tdep = gdbarch_tdep (state->arch); | |
1375 | ||
1376 | /* The bits in SRC indicating which registers to save are: | |
1377 | r0 r1 r2 r3 a0 a1 sb fb */ | |
1378 | return | |
1379 | ( m32c_pv_pushm_one (state, state->fb, 0x01, src, tdep->push_addr_bytes) | |
1380 | || m32c_pv_pushm_one (state, state->sb, 0x02, src, tdep->push_addr_bytes) | |
1381 | || m32c_pv_pushm_one (state, state->a1, 0x04, src, tdep->push_addr_bytes) | |
1382 | || m32c_pv_pushm_one (state, state->a0, 0x08, src, tdep->push_addr_bytes) | |
1383 | || m32c_pv_pushm_one (state, state->r3, 0x10, src, 2) | |
1384 | || m32c_pv_pushm_one (state, state->r2, 0x20, src, 2) | |
1385 | || m32c_pv_pushm_one (state, state->r1, 0x40, src, 2) | |
1386 | || m32c_pv_pushm_one (state, state->r0, 0x80, src, 2)); | |
1387 | } | |
1388 | ||
1389 | /* Return non-zero if VALUE is the first incoming argument register. */ | |
1390 | ||
1391 | static int | |
1392 | m32c_is_1st_arg_reg (struct m32c_pv_state *state, pv_t value) | |
1393 | { | |
1394 | struct gdbarch_tdep *tdep = gdbarch_tdep (state->arch); | |
1395 | return (value.kind == pvk_register | |
dda83cd7 | 1396 | && (gdbarch_bfd_arch_info (state->arch)->mach == bfd_mach_m16c |
96309189 MS |
1397 | ? (value.reg == tdep->r1->num) |
1398 | : (value.reg == tdep->r0->num)) | |
dda83cd7 | 1399 | && value.k == 0); |
96309189 MS |
1400 | } |
1401 | ||
1402 | /* Return non-zero if VALUE is an incoming argument register. */ | |
1403 | ||
1404 | static int | |
1405 | m32c_is_arg_reg (struct m32c_pv_state *state, pv_t value) | |
1406 | { | |
1407 | struct gdbarch_tdep *tdep = gdbarch_tdep (state->arch); | |
1408 | return (value.kind == pvk_register | |
dda83cd7 | 1409 | && (gdbarch_bfd_arch_info (state->arch)->mach == bfd_mach_m16c |
96309189 MS |
1410 | ? (value.reg == tdep->r1->num || value.reg == tdep->r2->num) |
1411 | : (value.reg == tdep->r0->num)) | |
dda83cd7 | 1412 | && value.k == 0); |
96309189 MS |
1413 | } |
1414 | ||
1415 | /* Return non-zero if a store of VALUE to LOC is probably spilling an | |
1416 | argument register to its stack slot in STATE. Such instructions | |
1417 | should be included in the prologue, if possible. | |
1418 | ||
1419 | The store is a spill if: | |
1420 | - the value being stored is the original value of an argument register; | |
1421 | - the value has not already been stored somewhere in STACK; and | |
1422 | - LOC is a stack slot (e.g., a memory location whose address is | |
1423 | relative to the original value of the SP). */ | |
1424 | ||
1425 | static int | |
1426 | m32c_is_arg_spill (struct m32c_pv_state *st, | |
1427 | struct srcdest loc, | |
1428 | pv_t value) | |
1429 | { | |
1430 | struct gdbarch_tdep *tdep = gdbarch_tdep (st->arch); | |
1431 | ||
1432 | return (m32c_is_arg_reg (st, value) | |
1433 | && loc.kind == srcdest_mem | |
dda83cd7 SM |
1434 | && pv_is_register (loc.addr, tdep->sp->num) |
1435 | && ! st->stack->find_reg (st->arch, value.reg, 0)); | |
96309189 MS |
1436 | } |
1437 | ||
1438 | /* Return non-zero if a store of VALUE to LOC is probably | |
1439 | copying the struct return address into an address register | |
1440 | for immediate use. This is basically a "spill" into the | |
1441 | address register, instead of onto the stack. | |
1442 | ||
1443 | The prerequisites are: | |
1444 | - value being stored is original value of the FIRST arg register; | |
1445 | - value has not already been stored on stack; and | |
1446 | - LOC is an address register (a0 or a1). */ | |
1447 | ||
1448 | static int | |
1449 | m32c_is_struct_return (struct m32c_pv_state *st, | |
1450 | struct srcdest loc, | |
1451 | pv_t value) | |
1452 | { | |
1453 | struct gdbarch_tdep *tdep = gdbarch_tdep (st->arch); | |
1454 | ||
1455 | return (m32c_is_1st_arg_reg (st, value) | |
f7b7ed97 | 1456 | && !st->stack->find_reg (st->arch, value.reg, 0) |
96309189 MS |
1457 | && loc.kind == srcdest_reg |
1458 | && (pv_is_register (*loc.reg, tdep->a0->num) | |
1459 | || pv_is_register (*loc.reg, tdep->a1->num))); | |
1460 | } | |
1461 | ||
1462 | /* Return non-zero if a 'pushm' saving the registers indicated by SRC | |
1463 | was a register save: | |
1464 | - all the named registers should have their original values, and | |
1465 | - the stack pointer should be at a constant offset from the | |
1466 | original stack pointer. */ | |
1467 | static int | |
1468 | m32c_pushm_is_reg_save (struct m32c_pv_state *st, int src) | |
1469 | { | |
1470 | struct gdbarch_tdep *tdep = gdbarch_tdep (st->arch); | |
1471 | /* The bits in SRC indicating which registers to save are: | |
1472 | r0 r1 r2 r3 a0 a1 sb fb */ | |
1473 | return | |
1474 | (pv_is_register (st->sp, tdep->sp->num) | |
1475 | && (! (src & 0x01) || pv_is_register_k (st->fb, tdep->fb->num, 0)) | |
1476 | && (! (src & 0x02) || pv_is_register_k (st->sb, tdep->sb->num, 0)) | |
1477 | && (! (src & 0x04) || pv_is_register_k (st->a1, tdep->a1->num, 0)) | |
1478 | && (! (src & 0x08) || pv_is_register_k (st->a0, tdep->a0->num, 0)) | |
1479 | && (! (src & 0x10) || pv_is_register_k (st->r3, tdep->r3->num, 0)) | |
1480 | && (! (src & 0x20) || pv_is_register_k (st->r2, tdep->r2->num, 0)) | |
1481 | && (! (src & 0x40) || pv_is_register_k (st->r1, tdep->r1->num, 0)) | |
1482 | && (! (src & 0x80) || pv_is_register_k (st->r0, tdep->r0->num, 0))); | |
1483 | } | |
1484 | ||
1485 | ||
1486 | /* Function for finding saved registers in a 'struct pv_area'; we pass | |
f7b7ed97 | 1487 | this to pv_area::scan. |
96309189 MS |
1488 | |
1489 | If VALUE is a saved register, ADDR says it was saved at a constant | |
1490 | offset from the frame base, and SIZE indicates that the whole | |
1491 | register was saved, record its offset in RESULT_UNTYPED. */ | |
1492 | static void | |
1493 | check_for_saved (void *prologue_untyped, pv_t addr, CORE_ADDR size, pv_t value) | |
1494 | { | |
1495 | struct m32c_prologue *prologue = (struct m32c_prologue *) prologue_untyped; | |
1496 | struct gdbarch *arch = prologue->arch; | |
1497 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); | |
1498 | ||
1499 | /* Is this the unchanged value of some register being saved on the | |
1500 | stack? */ | |
1501 | if (value.kind == pvk_register | |
1502 | && value.k == 0 | |
1503 | && pv_is_register (addr, tdep->sp->num)) | |
1504 | { | |
1505 | /* Some registers require special handling: they're saved as a | |
1506 | larger value than the register itself. */ | |
1507 | CORE_ADDR saved_size = register_size (arch, value.reg); | |
1508 | ||
1509 | if (value.reg == tdep->pc->num) | |
1510 | saved_size = tdep->ret_addr_bytes; | |
7b9ee6a8 | 1511 | else if (register_type (arch, value.reg) |
96309189 MS |
1512 | == tdep->data_addr_reg_type) |
1513 | saved_size = tdep->push_addr_bytes; | |
1514 | ||
1515 | if (size == saved_size) | |
1516 | { | |
1517 | /* Find which end of the saved value corresponds to our | |
1518 | register. */ | |
1519 | if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG) | |
1520 | prologue->reg_offset[value.reg] | |
1521 | = (addr.k + saved_size - register_size (arch, value.reg)); | |
1522 | else | |
1523 | prologue->reg_offset[value.reg] = addr.k; | |
1524 | } | |
1525 | } | |
1526 | } | |
1527 | ||
1528 | ||
1529 | /* Analyze the function prologue for ARCH at START, going no further | |
1530 | than LIMIT, and place a description of what we found in | |
1531 | PROLOGUE. */ | |
63807e1d | 1532 | static void |
96309189 MS |
1533 | m32c_analyze_prologue (struct gdbarch *arch, |
1534 | CORE_ADDR start, CORE_ADDR limit, | |
1535 | struct m32c_prologue *prologue) | |
1536 | { | |
1537 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); | |
1538 | unsigned long mach = gdbarch_bfd_arch_info (arch)->mach; | |
1539 | CORE_ADDR after_last_frame_related_insn; | |
96309189 MS |
1540 | struct m32c_pv_state st; |
1541 | ||
1542 | st.arch = arch; | |
1543 | st.r0 = pv_register (tdep->r0->num, 0); | |
1544 | st.r1 = pv_register (tdep->r1->num, 0); | |
1545 | st.r2 = pv_register (tdep->r2->num, 0); | |
1546 | st.r3 = pv_register (tdep->r3->num, 0); | |
1547 | st.a0 = pv_register (tdep->a0->num, 0); | |
1548 | st.a1 = pv_register (tdep->a1->num, 0); | |
1549 | st.sb = pv_register (tdep->sb->num, 0); | |
1550 | st.fb = pv_register (tdep->fb->num, 0); | |
1551 | st.sp = pv_register (tdep->sp->num, 0); | |
1552 | st.pc = pv_register (tdep->pc->num, 0); | |
f7b7ed97 TT |
1553 | pv_area stack (tdep->sp->num, gdbarch_addr_bit (arch)); |
1554 | st.stack = &stack; | |
96309189 MS |
1555 | |
1556 | /* Record that the call instruction has saved the return address on | |
1557 | the stack. */ | |
1558 | m32c_pv_push (&st, st.pc, tdep->ret_addr_bytes); | |
1559 | ||
1560 | memset (prologue, 0, sizeof (*prologue)); | |
1561 | prologue->arch = arch; | |
1562 | { | |
1563 | int i; | |
1564 | for (i = 0; i < M32C_MAX_NUM_REGS; i++) | |
1565 | prologue->reg_offset[i] = 1; | |
1566 | } | |
1567 | ||
1568 | st.scan_pc = after_last_frame_related_insn = start; | |
1569 | ||
1570 | while (st.scan_pc < limit) | |
1571 | { | |
1572 | pv_t pre_insn_fb = st.fb; | |
1573 | pv_t pre_insn_sp = st.sp; | |
1574 | ||
1575 | /* In theory we could get in trouble by trying to read ahead | |
1576 | here, when we only know we're expecting one byte. In | |
1577 | practice I doubt anyone will care, and it makes the rest of | |
1578 | the code easier. */ | |
1579 | if (target_read_memory (st.scan_pc, st.insn, sizeof (st.insn))) | |
1580 | /* If we can't fetch the instruction from memory, stop here | |
1581 | and hope for the best. */ | |
1582 | break; | |
1583 | st.next_addr = st.scan_pc; | |
1584 | ||
1585 | /* The assembly instructions are written as they appear in the | |
1586 | section of the processor manuals that describe the | |
1587 | instruction encodings. | |
1588 | ||
1589 | When a single assembly language instruction has several | |
1590 | different machine-language encodings, the manual | |
1591 | distinguishes them by a number in parens, before the | |
1592 | mnemonic. Those numbers are included, as well. | |
1593 | ||
1594 | The srcdest decoding instructions have the same names as the | |
1595 | analogous functions in the simulator. */ | |
1596 | if (mach == bfd_mach_m16c) | |
1597 | { | |
1598 | /* (1) ENTER #imm8 */ | |
1599 | if (st.insn[0] == 0x7c && st.insn[1] == 0xf2) | |
1600 | { | |
1601 | if (m32c_pv_enter (&st, st.insn[2])) | |
1602 | break; | |
1603 | st.next_addr += 3; | |
1604 | } | |
1605 | /* (1) PUSHM src */ | |
1606 | else if (st.insn[0] == 0xec) | |
1607 | { | |
1608 | int src = st.insn[1]; | |
1609 | if (m32c_pv_pushm (&st, src)) | |
1610 | break; | |
1611 | st.next_addr += 2; | |
1612 | ||
1613 | if (m32c_pushm_is_reg_save (&st, src)) | |
1614 | after_last_frame_related_insn = st.next_addr; | |
1615 | } | |
1616 | ||
1617 | /* (6) MOV.size:G src, dest */ | |
1618 | else if ((st.insn[0] & 0xfe) == 0x72) | |
1619 | { | |
1620 | int size = (st.insn[0] & 0x01) ? 2 : 1; | |
f79b9530 DJ |
1621 | struct srcdest src; |
1622 | struct srcdest dest; | |
1623 | pv_t src_value; | |
96309189 MS |
1624 | st.next_addr += 2; |
1625 | ||
f79b9530 | 1626 | src |
96309189 | 1627 | = m32c_decode_srcdest4 (&st, (st.insn[1] >> 4) & 0xf, size); |
f79b9530 | 1628 | dest |
96309189 | 1629 | = m32c_decode_srcdest4 (&st, st.insn[1] & 0xf, size); |
f79b9530 | 1630 | src_value = m32c_srcdest_fetch (&st, src, size); |
96309189 MS |
1631 | |
1632 | if (m32c_is_arg_spill (&st, dest, src_value)) | |
1633 | after_last_frame_related_insn = st.next_addr; | |
1634 | else if (m32c_is_struct_return (&st, dest, src_value)) | |
1635 | after_last_frame_related_insn = st.next_addr; | |
1636 | ||
1637 | if (m32c_srcdest_store (&st, dest, src_value, size)) | |
1638 | break; | |
1639 | } | |
1640 | ||
1641 | /* (1) LDC #IMM16, sp */ | |
1642 | else if (st.insn[0] == 0xeb | |
1643 | && st.insn[1] == 0x50) | |
1644 | { | |
1645 | st.next_addr += 2; | |
1646 | st.sp = pv_constant (m32c_udisp16 (&st)); | |
1647 | } | |
1648 | ||
1649 | else | |
1650 | /* We've hit some instruction we don't know how to simulate. | |
1651 | Strictly speaking, we should set every value we're | |
1652 | tracking to "unknown". But we'll be optimistic, assume | |
1653 | that we have enough information already, and stop | |
1654 | analysis here. */ | |
1655 | break; | |
1656 | } | |
1657 | else | |
1658 | { | |
1659 | int src_indirect = 0; | |
1660 | int dest_indirect = 0; | |
1661 | int i = 0; | |
1662 | ||
1663 | gdb_assert (mach == bfd_mach_m32c); | |
1664 | ||
1665 | /* Check for prefix bytes indicating indirect addressing. */ | |
1666 | if (st.insn[0] == 0x41) | |
1667 | { | |
1668 | src_indirect = 1; | |
1669 | i++; | |
1670 | } | |
1671 | else if (st.insn[0] == 0x09) | |
1672 | { | |
1673 | dest_indirect = 1; | |
1674 | i++; | |
1675 | } | |
1676 | else if (st.insn[0] == 0x49) | |
1677 | { | |
1678 | src_indirect = dest_indirect = 1; | |
1679 | i++; | |
1680 | } | |
1681 | ||
1682 | /* (1) ENTER #imm8 */ | |
1683 | if (st.insn[i] == 0xec) | |
1684 | { | |
1685 | if (m32c_pv_enter (&st, st.insn[i + 1])) | |
1686 | break; | |
1687 | st.next_addr += 2; | |
1688 | } | |
1689 | ||
1690 | /* (1) PUSHM src */ | |
1691 | else if (st.insn[i] == 0x8f) | |
1692 | { | |
1693 | int src = st.insn[i + 1]; | |
1694 | if (m32c_pv_pushm (&st, src)) | |
1695 | break; | |
1696 | st.next_addr += 2; | |
1697 | ||
1698 | if (m32c_pushm_is_reg_save (&st, src)) | |
1699 | after_last_frame_related_insn = st.next_addr; | |
1700 | } | |
1701 | ||
1702 | /* (7) MOV.size:G src, dest */ | |
1703 | else if ((st.insn[i] & 0x80) == 0x80 | |
1704 | && (st.insn[i + 1] & 0x0f) == 0x0b | |
1705 | && m32c_get_src23 (&st.insn[i]) < 20 | |
1706 | && m32c_get_dest23 (&st.insn[i]) < 20) | |
1707 | { | |
f79b9530 DJ |
1708 | struct srcdest src; |
1709 | struct srcdest dest; | |
1710 | pv_t src_value; | |
96309189 MS |
1711 | int bw = st.insn[i] & 0x01; |
1712 | int size = bw ? 2 : 1; | |
96309189 MS |
1713 | st.next_addr += 2; |
1714 | ||
f79b9530 | 1715 | src |
96309189 MS |
1716 | = m32c_decode_sd23 (&st, m32c_get_src23 (&st.insn[i]), |
1717 | size, src_indirect); | |
f79b9530 | 1718 | dest |
96309189 MS |
1719 | = m32c_decode_sd23 (&st, m32c_get_dest23 (&st.insn[i]), |
1720 | size, dest_indirect); | |
f79b9530 | 1721 | src_value = m32c_srcdest_fetch (&st, src, size); |
96309189 MS |
1722 | |
1723 | if (m32c_is_arg_spill (&st, dest, src_value)) | |
1724 | after_last_frame_related_insn = st.next_addr; | |
1725 | ||
1726 | if (m32c_srcdest_store (&st, dest, src_value, size)) | |
1727 | break; | |
1728 | } | |
1729 | /* (2) LDC #IMM24, sp */ | |
1730 | else if (st.insn[i] == 0xd5 | |
1731 | && st.insn[i + 1] == 0x29) | |
1732 | { | |
1733 | st.next_addr += 2; | |
1734 | st.sp = pv_constant (m32c_udisp24 (&st)); | |
1735 | } | |
1736 | else | |
1737 | /* We've hit some instruction we don't know how to simulate. | |
1738 | Strictly speaking, we should set every value we're | |
1739 | tracking to "unknown". But we'll be optimistic, assume | |
1740 | that we have enough information already, and stop | |
1741 | analysis here. */ | |
1742 | break; | |
1743 | } | |
1744 | ||
1745 | /* If this instruction changed the FB or decreased the SP (i.e., | |
dda83cd7 SM |
1746 | allocated more stack space), then this may be a good place to |
1747 | declare the prologue finished. However, there are some | |
1748 | exceptions: | |
96309189 | 1749 | |
dda83cd7 SM |
1750 | - If the instruction just changed the FB back to its original |
1751 | value, then that's probably a restore instruction. The | |
1752 | prologue should definitely end before that. | |
96309189 | 1753 | |
dda83cd7 SM |
1754 | - If the instruction increased the value of the SP (that is, |
1755 | shrunk the frame), then it's probably part of a frame | |
1756 | teardown sequence, and the prologue should end before | |
1757 | that. */ | |
96309189 MS |
1758 | |
1759 | if (! pv_is_identical (st.fb, pre_insn_fb)) | |
dda83cd7 SM |
1760 | { |
1761 | if (! pv_is_register_k (st.fb, tdep->fb->num, 0)) | |
1762 | after_last_frame_related_insn = st.next_addr; | |
1763 | } | |
96309189 | 1764 | else if (! pv_is_identical (st.sp, pre_insn_sp)) |
dda83cd7 SM |
1765 | { |
1766 | /* The comparison of the constants looks odd, there, because | |
1767 | .k is unsigned. All it really means is that the SP is | |
1768 | lower than it was before the instruction. */ | |
1769 | if ( pv_is_register (pre_insn_sp, tdep->sp->num) | |
1770 | && pv_is_register (st.sp, tdep->sp->num) | |
1771 | && ((pre_insn_sp.k - st.sp.k) < (st.sp.k - pre_insn_sp.k))) | |
1772 | after_last_frame_related_insn = st.next_addr; | |
1773 | } | |
96309189 MS |
1774 | |
1775 | st.scan_pc = st.next_addr; | |
1776 | } | |
1777 | ||
1778 | /* Did we load a constant value into the stack pointer? */ | |
1779 | if (pv_is_constant (st.sp)) | |
1780 | prologue->kind = prologue_first_frame; | |
1781 | ||
1782 | /* Alternatively, did we initialize the frame pointer? Remember | |
1783 | that the CFA is the address after the return address. */ | |
1784 | if (pv_is_register (st.fb, tdep->sp->num)) | |
1785 | { | |
1786 | prologue->kind = prologue_with_frame_ptr; | |
1787 | prologue->frame_ptr_offset = st.fb.k; | |
1788 | } | |
1789 | ||
1790 | /* Is the frame size a known constant? Remember that frame_size is | |
1791 | actually the offset from the CFA to the SP (i.e., a negative | |
1792 | value). */ | |
1793 | else if (pv_is_register (st.sp, tdep->sp->num)) | |
1794 | { | |
1795 | prologue->kind = prologue_sans_frame_ptr; | |
1796 | prologue->frame_size = st.sp.k; | |
1797 | } | |
1798 | ||
1799 | /* We haven't been able to make sense of this function's frame. Treat | |
1800 | it as the first frame. */ | |
1801 | else | |
1802 | prologue->kind = prologue_first_frame; | |
1803 | ||
1804 | /* Record where all the registers were saved. */ | |
f7b7ed97 | 1805 | st.stack->scan (check_for_saved, (void *) prologue); |
96309189 MS |
1806 | |
1807 | prologue->prologue_end = after_last_frame_related_insn; | |
96309189 MS |
1808 | } |
1809 | ||
1810 | ||
1811 | static CORE_ADDR | |
6093d2eb | 1812 | m32c_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR ip) |
96309189 | 1813 | { |
2c02bd72 | 1814 | const char *name; |
96309189 MS |
1815 | CORE_ADDR func_addr, func_end, sal_end; |
1816 | struct m32c_prologue p; | |
1817 | ||
1818 | /* Try to find the extent of the function that contains IP. */ | |
1819 | if (! find_pc_partial_function (ip, &name, &func_addr, &func_end)) | |
1820 | return ip; | |
1821 | ||
1822 | /* Find end by prologue analysis. */ | |
6093d2eb | 1823 | m32c_analyze_prologue (gdbarch, ip, func_end, &p); |
96309189 | 1824 | /* Find end by line info. */ |
d80b854b | 1825 | sal_end = skip_prologue_using_sal (gdbarch, ip); |
96309189 MS |
1826 | /* Return whichever is lower. */ |
1827 | if (sal_end != 0 && sal_end != ip && sal_end < p.prologue_end) | |
1828 | return sal_end; | |
1829 | else | |
1830 | return p.prologue_end; | |
1831 | } | |
1832 | ||
1833 | ||
1834 | \f | |
1835 | /* Stack unwinding. */ | |
1836 | ||
1837 | static struct m32c_prologue * | |
94afd7a6 | 1838 | m32c_analyze_frame_prologue (struct frame_info *this_frame, |
96309189 MS |
1839 | void **this_prologue_cache) |
1840 | { | |
1841 | if (! *this_prologue_cache) | |
1842 | { | |
94afd7a6 UW |
1843 | CORE_ADDR func_start = get_frame_func (this_frame); |
1844 | CORE_ADDR stop_addr = get_frame_pc (this_frame); | |
96309189 MS |
1845 | |
1846 | /* If we couldn't find any function containing the PC, then | |
dda83cd7 | 1847 | just initialize the prologue cache, but don't do anything. */ |
96309189 | 1848 | if (! func_start) |
dda83cd7 | 1849 | stop_addr = func_start; |
96309189 MS |
1850 | |
1851 | *this_prologue_cache = FRAME_OBSTACK_ZALLOC (struct m32c_prologue); | |
94afd7a6 | 1852 | m32c_analyze_prologue (get_frame_arch (this_frame), |
9a3c8263 SM |
1853 | func_start, stop_addr, |
1854 | (struct m32c_prologue *) *this_prologue_cache); | |
96309189 MS |
1855 | } |
1856 | ||
9a3c8263 | 1857 | return (struct m32c_prologue *) *this_prologue_cache; |
96309189 MS |
1858 | } |
1859 | ||
1860 | ||
1861 | static CORE_ADDR | |
94afd7a6 | 1862 | m32c_frame_base (struct frame_info *this_frame, |
dda83cd7 | 1863 | void **this_prologue_cache) |
96309189 MS |
1864 | { |
1865 | struct m32c_prologue *p | |
94afd7a6 UW |
1866 | = m32c_analyze_frame_prologue (this_frame, this_prologue_cache); |
1867 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); | |
96309189 MS |
1868 | |
1869 | /* In functions that use alloca, the distance between the stack | |
1870 | pointer and the frame base varies dynamically, so we can't use | |
1871 | the SP plus static information like prologue analysis to find the | |
1872 | frame base. However, such functions must have a frame pointer, | |
1873 | to be able to restore the SP on exit. So whenever we do have a | |
1874 | frame pointer, use that to find the base. */ | |
1875 | switch (p->kind) | |
1876 | { | |
1877 | case prologue_with_frame_ptr: | |
1878 | { | |
1879 | CORE_ADDR fb | |
94afd7a6 | 1880 | = get_frame_register_unsigned (this_frame, tdep->fb->num); |
96309189 MS |
1881 | return fb - p->frame_ptr_offset; |
1882 | } | |
1883 | ||
1884 | case prologue_sans_frame_ptr: | |
1885 | { | |
1886 | CORE_ADDR sp | |
94afd7a6 | 1887 | = get_frame_register_unsigned (this_frame, tdep->sp->num); |
96309189 MS |
1888 | return sp - p->frame_size; |
1889 | } | |
1890 | ||
1891 | case prologue_first_frame: | |
1892 | return 0; | |
1893 | ||
1894 | default: | |
f3574227 | 1895 | gdb_assert_not_reached ("unexpected prologue kind"); |
96309189 MS |
1896 | } |
1897 | } | |
1898 | ||
1899 | ||
1900 | static void | |
94afd7a6 | 1901 | m32c_this_id (struct frame_info *this_frame, |
96309189 MS |
1902 | void **this_prologue_cache, |
1903 | struct frame_id *this_id) | |
1904 | { | |
94afd7a6 | 1905 | CORE_ADDR base = m32c_frame_base (this_frame, this_prologue_cache); |
96309189 MS |
1906 | |
1907 | if (base) | |
94afd7a6 | 1908 | *this_id = frame_id_build (base, get_frame_func (this_frame)); |
96309189 MS |
1909 | /* Otherwise, leave it unset, and that will terminate the backtrace. */ |
1910 | } | |
1911 | ||
1912 | ||
94afd7a6 UW |
1913 | static struct value * |
1914 | m32c_prev_register (struct frame_info *this_frame, | |
1915 | void **this_prologue_cache, int regnum) | |
96309189 | 1916 | { |
94afd7a6 | 1917 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
96309189 | 1918 | struct m32c_prologue *p |
94afd7a6 UW |
1919 | = m32c_analyze_frame_prologue (this_frame, this_prologue_cache); |
1920 | CORE_ADDR frame_base = m32c_frame_base (this_frame, this_prologue_cache); | |
96309189 MS |
1921 | |
1922 | if (regnum == tdep->sp->num) | |
94afd7a6 | 1923 | return frame_unwind_got_constant (this_frame, regnum, frame_base); |
96309189 MS |
1924 | |
1925 | /* If prologue analysis says we saved this register somewhere, | |
1926 | return a description of the stack slot holding it. */ | |
94afd7a6 UW |
1927 | if (p->reg_offset[regnum] != 1) |
1928 | return frame_unwind_got_memory (this_frame, regnum, | |
dda83cd7 | 1929 | frame_base + p->reg_offset[regnum]); |
96309189 MS |
1930 | |
1931 | /* Otherwise, presume we haven't changed the value of this | |
1932 | register, and get it from the next frame. */ | |
94afd7a6 | 1933 | return frame_unwind_got_register (this_frame, regnum, regnum); |
96309189 MS |
1934 | } |
1935 | ||
1936 | ||
1937 | static const struct frame_unwind m32c_unwind = { | |
1938 | NORMAL_FRAME, | |
8fbca658 | 1939 | default_frame_unwind_stop_reason, |
96309189 | 1940 | m32c_this_id, |
94afd7a6 UW |
1941 | m32c_prev_register, |
1942 | NULL, | |
1943 | default_frame_sniffer | |
96309189 MS |
1944 | }; |
1945 | ||
96309189 MS |
1946 | \f |
1947 | /* Inferior calls. */ | |
1948 | ||
1949 | /* The calling conventions, according to GCC: | |
1950 | ||
1951 | r8c, m16c | |
1952 | --------- | |
1953 | First arg may be passed in r1l or r1 if it (1) fits (QImode or | |
1954 | HImode), (2) is named, and (3) is an integer or pointer type (no | |
1955 | structs, floats, etc). Otherwise, it's passed on the stack. | |
1956 | ||
1957 | Second arg may be passed in r2, same restrictions (but not QImode), | |
1958 | even if the first arg is passed on the stack. | |
1959 | ||
1960 | Third and further args are passed on the stack. No padding is | |
1961 | used, stack "alignment" is 8 bits. | |
1962 | ||
1963 | m32cm, m32c | |
1964 | ----------- | |
1965 | ||
1966 | First arg may be passed in r0l or r0, same restrictions as above. | |
1967 | ||
1968 | Second and further args are passed on the stack. Padding is used | |
1969 | after QImode parameters (i.e. lower-addressed byte is the value, | |
1970 | higher-addressed byte is the padding), stack "alignment" is 16 | |
1971 | bits. */ | |
1972 | ||
1973 | ||
1974 | /* Return true if TYPE is a type that can be passed in registers. (We | |
1975 | ignore the size, and pay attention only to the type code; | |
1976 | acceptable sizes depends on which register is being considered to | |
1977 | hold it.) */ | |
1978 | static int | |
1979 | m32c_reg_arg_type (struct type *type) | |
1980 | { | |
78134374 | 1981 | enum type_code code = type->code (); |
96309189 MS |
1982 | |
1983 | return (code == TYPE_CODE_INT | |
1984 | || code == TYPE_CODE_ENUM | |
1985 | || code == TYPE_CODE_PTR | |
aa006118 | 1986 | || TYPE_IS_REFERENCE (type) |
96309189 MS |
1987 | || code == TYPE_CODE_BOOL |
1988 | || code == TYPE_CODE_CHAR); | |
1989 | } | |
1990 | ||
1991 | ||
1992 | static CORE_ADDR | |
1993 | m32c_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | |
1994 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
cf84fa6b AH |
1995 | struct value **args, CORE_ADDR sp, |
1996 | function_call_return_method return_method, | |
96309189 MS |
1997 | CORE_ADDR struct_addr) |
1998 | { | |
1999 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
e17a4113 | 2000 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
96309189 MS |
2001 | unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach; |
2002 | CORE_ADDR cfa; | |
2003 | int i; | |
2004 | ||
2005 | /* The number of arguments given in this function's prototype, or | |
2006 | zero if it has a non-prototyped function type. The m32c ABI | |
2007 | passes arguments mentioned in the prototype differently from | |
2008 | those in the ellipsis of a varargs function, or from those passed | |
2009 | to a non-prototyped function. */ | |
2010 | int num_prototyped_args = 0; | |
2011 | ||
2012 | { | |
2013 | struct type *func_type = value_type (function); | |
2014 | ||
ed09d7da | 2015 | /* Dereference function pointer types. */ |
78134374 | 2016 | if (func_type->code () == TYPE_CODE_PTR) |
ed09d7da KB |
2017 | func_type = TYPE_TARGET_TYPE (func_type); |
2018 | ||
78134374 SM |
2019 | gdb_assert (func_type->code () == TYPE_CODE_FUNC || |
2020 | func_type->code () == TYPE_CODE_METHOD); | |
96309189 MS |
2021 | |
2022 | #if 0 | |
2023 | /* The ABI description in gcc/config/m32c/m32c.abi says that | |
2024 | we need to handle prototyped and non-prototyped functions | |
2025 | separately, but the code in GCC doesn't actually do so. */ | |
2026 | if (TYPE_PROTOTYPED (func_type)) | |
2027 | #endif | |
1f704f76 | 2028 | num_prototyped_args = func_type->num_fields (); |
96309189 MS |
2029 | } |
2030 | ||
2031 | /* First, if the function returns an aggregate by value, push a | |
2032 | pointer to a buffer for it. This doesn't affect the way | |
2033 | subsequent arguments are allocated to registers. */ | |
cf84fa6b | 2034 | if (return_method == return_method_struct) |
96309189 MS |
2035 | { |
2036 | int ptr_len = TYPE_LENGTH (tdep->ptr_voyd); | |
2037 | sp -= ptr_len; | |
e17a4113 | 2038 | write_memory_unsigned_integer (sp, ptr_len, byte_order, struct_addr); |
96309189 MS |
2039 | } |
2040 | ||
2041 | /* Push the arguments. */ | |
2042 | for (i = nargs - 1; i >= 0; i--) | |
2043 | { | |
2044 | struct value *arg = args[i]; | |
2045 | const gdb_byte *arg_bits = value_contents (arg); | |
2046 | struct type *arg_type = value_type (arg); | |
2047 | ULONGEST arg_size = TYPE_LENGTH (arg_type); | |
2048 | ||
2049 | /* Can it go in r1 or r1l (for m16c) or r0 or r0l (for m32c)? */ | |
2050 | if (i == 0 | |
2051 | && arg_size <= 2 | |
2052 | && i < num_prototyped_args | |
2053 | && m32c_reg_arg_type (arg_type)) | |
2054 | { | |
2055 | /* Extract and re-store as an integer as a terse way to make | |
2056 | sure it ends up in the least significant end of r1. (GDB | |
2057 | should avoid assuming endianness, even on uni-endian | |
2058 | processors.) */ | |
e17a4113 UW |
2059 | ULONGEST u = extract_unsigned_integer (arg_bits, arg_size, |
2060 | byte_order); | |
96309189 MS |
2061 | struct m32c_reg *reg = (mach == bfd_mach_m16c) ? tdep->r1 : tdep->r0; |
2062 | regcache_cooked_write_unsigned (regcache, reg->num, u); | |
2063 | } | |
2064 | ||
2065 | /* Can it go in r2? */ | |
2066 | else if (mach == bfd_mach_m16c | |
2067 | && i == 1 | |
2068 | && arg_size == 2 | |
2069 | && i < num_prototyped_args | |
2070 | && m32c_reg_arg_type (arg_type)) | |
b66f5587 | 2071 | regcache->cooked_write (tdep->r2->num, arg_bits); |
96309189 MS |
2072 | |
2073 | /* Everything else goes on the stack. */ | |
2074 | else | |
2075 | { | |
2076 | sp -= arg_size; | |
2077 | ||
2078 | /* Align the stack. */ | |
2079 | if (mach == bfd_mach_m32c) | |
2080 | sp &= ~1; | |
2081 | ||
2082 | write_memory (sp, arg_bits, arg_size); | |
2083 | } | |
2084 | } | |
2085 | ||
2086 | /* This is the CFA we use to identify the dummy frame. */ | |
2087 | cfa = sp; | |
2088 | ||
2089 | /* Push the return address. */ | |
2090 | sp -= tdep->ret_addr_bytes; | |
e17a4113 UW |
2091 | write_memory_unsigned_integer (sp, tdep->ret_addr_bytes, byte_order, |
2092 | bp_addr); | |
96309189 MS |
2093 | |
2094 | /* Update the stack pointer. */ | |
2095 | regcache_cooked_write_unsigned (regcache, tdep->sp->num, sp); | |
2096 | ||
2097 | /* We need to borrow an odd trick from the i386 target here. | |
2098 | ||
2099 | The value we return from this function gets used as the stack | |
2100 | address (the CFA) for the dummy frame's ID. The obvious thing is | |
2101 | to return the new TOS. However, that points at the return | |
2102 | address, saved on the stack, which is inconsistent with the CFA's | |
2103 | described by GCC's DWARF 2 .debug_frame information: DWARF 2 | |
2104 | .debug_frame info uses the address immediately after the saved | |
2105 | return address. So you end up with a dummy frame whose CFA | |
2106 | points at the return address, but the frame for the function | |
2107 | being called has a CFA pointing after the return address: the | |
2108 | younger CFA is *greater than* the older CFA. The sanity checks | |
2109 | in frame.c don't like that. | |
2110 | ||
2111 | So we try to be consistent with the CFA's used by DWARF 2. | |
2112 | Having a dummy frame and a real frame with the *same* CFA is | |
2113 | tolerable. */ | |
2114 | return cfa; | |
2115 | } | |
2116 | ||
2117 | ||
96309189 MS |
2118 | \f |
2119 | /* Return values. */ | |
2120 | ||
2121 | /* Return value conventions, according to GCC: | |
2122 | ||
2123 | r8c, m16c | |
2124 | --------- | |
2125 | ||
2126 | QImode in r0l | |
2127 | HImode in r0 | |
2128 | SImode in r2r0 | |
2129 | near pointer in r0 | |
2130 | far pointer in r2r0 | |
2131 | ||
2132 | Aggregate values (regardless of size) are returned by pushing a | |
2133 | pointer to a temporary area on the stack after the args are pushed. | |
2134 | The function fills in this area with the value. Note that this | |
2135 | pointer on the stack does not affect how register arguments, if any, | |
2136 | are configured. | |
2137 | ||
2138 | m32cm, m32c | |
2139 | ----------- | |
2140 | Same. */ | |
2141 | ||
2142 | /* Return non-zero if values of type TYPE are returned by storing them | |
2143 | in a buffer whose address is passed on the stack, ahead of the | |
2144 | other arguments. */ | |
2145 | static int | |
2146 | m32c_return_by_passed_buf (struct type *type) | |
2147 | { | |
78134374 | 2148 | enum type_code code = type->code (); |
96309189 MS |
2149 | |
2150 | return (code == TYPE_CODE_STRUCT | |
2151 | || code == TYPE_CODE_UNION); | |
2152 | } | |
2153 | ||
2154 | static enum return_value_convention | |
2155 | m32c_return_value (struct gdbarch *gdbarch, | |
6a3a010b | 2156 | struct value *function, |
96309189 MS |
2157 | struct type *valtype, |
2158 | struct regcache *regcache, | |
2159 | gdb_byte *readbuf, | |
2160 | const gdb_byte *writebuf) | |
2161 | { | |
2162 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
e17a4113 | 2163 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
96309189 MS |
2164 | enum return_value_convention conv; |
2165 | ULONGEST valtype_len = TYPE_LENGTH (valtype); | |
2166 | ||
2167 | if (m32c_return_by_passed_buf (valtype)) | |
2168 | conv = RETURN_VALUE_STRUCT_CONVENTION; | |
2169 | else | |
2170 | conv = RETURN_VALUE_REGISTER_CONVENTION; | |
2171 | ||
2172 | if (readbuf) | |
2173 | { | |
2174 | /* We should never be called to find values being returned by | |
2175 | RETURN_VALUE_STRUCT_CONVENTION. Those can't be located, | |
2176 | unless we made the call ourselves. */ | |
2177 | gdb_assert (conv == RETURN_VALUE_REGISTER_CONVENTION); | |
2178 | ||
2179 | gdb_assert (valtype_len <= 8); | |
2180 | ||
2181 | /* Anything that fits in r0 is returned there. */ | |
2182 | if (valtype_len <= TYPE_LENGTH (tdep->r0->type)) | |
2183 | { | |
2184 | ULONGEST u; | |
2185 | regcache_cooked_read_unsigned (regcache, tdep->r0->num, &u); | |
e17a4113 | 2186 | store_unsigned_integer (readbuf, valtype_len, byte_order, u); |
96309189 MS |
2187 | } |
2188 | else | |
2189 | { | |
2190 | /* Everything else is passed in mem0, using as many bytes as | |
2191 | needed. This is not what the Renesas tools do, but it's | |
2192 | what GCC does at the moment. */ | |
3b7344d5 | 2193 | struct bound_minimal_symbol mem0 |
96309189 MS |
2194 | = lookup_minimal_symbol ("mem0", NULL, NULL); |
2195 | ||
3b7344d5 | 2196 | if (! mem0.minsym) |
a73c6dcd MS |
2197 | error (_("The return value is stored in memory at 'mem0', " |
2198 | "but GDB cannot find\n" | |
2199 | "its address.")); | |
77e371c0 | 2200 | read_memory (BMSYMBOL_VALUE_ADDRESS (mem0), readbuf, valtype_len); |
96309189 MS |
2201 | } |
2202 | } | |
2203 | ||
2204 | if (writebuf) | |
2205 | { | |
2206 | /* We should never be called to store values to be returned | |
2207 | using RETURN_VALUE_STRUCT_CONVENTION. We have no way of | |
2208 | finding the buffer, unless we made the call ourselves. */ | |
2209 | gdb_assert (conv == RETURN_VALUE_REGISTER_CONVENTION); | |
2210 | ||
2211 | gdb_assert (valtype_len <= 8); | |
2212 | ||
2213 | /* Anything that fits in r0 is returned there. */ | |
2214 | if (valtype_len <= TYPE_LENGTH (tdep->r0->type)) | |
2215 | { | |
e17a4113 UW |
2216 | ULONGEST u = extract_unsigned_integer (writebuf, valtype_len, |
2217 | byte_order); | |
96309189 MS |
2218 | regcache_cooked_write_unsigned (regcache, tdep->r0->num, u); |
2219 | } | |
2220 | else | |
2221 | { | |
2222 | /* Everything else is passed in mem0, using as many bytes as | |
2223 | needed. This is not what the Renesas tools do, but it's | |
2224 | what GCC does at the moment. */ | |
3b7344d5 | 2225 | struct bound_minimal_symbol mem0 |
96309189 MS |
2226 | = lookup_minimal_symbol ("mem0", NULL, NULL); |
2227 | ||
3b7344d5 | 2228 | if (! mem0.minsym) |
a73c6dcd MS |
2229 | error (_("The return value is stored in memory at 'mem0', " |
2230 | "but GDB cannot find\n" | |
2231 | " its address.")); | |
77e371c0 | 2232 | write_memory (BMSYMBOL_VALUE_ADDRESS (mem0), writebuf, valtype_len); |
96309189 MS |
2233 | } |
2234 | } | |
2235 | ||
2236 | return conv; | |
2237 | } | |
2238 | ||
2239 | ||
2240 | \f | |
2241 | /* Trampolines. */ | |
2242 | ||
2243 | /* The m16c and m32c use a trampoline function for indirect function | |
2244 | calls. An indirect call looks like this: | |
2245 | ||
2246 | ... push arguments ... | |
2247 | ... push target function address ... | |
2248 | jsr.a m32c_jsri16 | |
2249 | ||
2250 | The code for m32c_jsri16 looks like this: | |
2251 | ||
2252 | m32c_jsri16: | |
2253 | ||
dda83cd7 | 2254 | # Save return address. |
96309189 MS |
2255 | pop.w m32c_jsri_ret |
2256 | pop.b m32c_jsri_ret+2 | |
2257 | ||
dda83cd7 | 2258 | # Store target function address. |
96309189 MS |
2259 | pop.w m32c_jsri_addr |
2260 | ||
2261 | # Re-push return address. | |
2262 | push.b m32c_jsri_ret+2 | |
2263 | push.w m32c_jsri_ret | |
2264 | ||
2265 | # Call the target function. | |
2266 | jmpi.a m32c_jsri_addr | |
2267 | ||
2268 | Without further information, GDB will treat calls to m32c_jsri16 | |
2269 | like calls to any other function. Since m32c_jsri16 doesn't have | |
2270 | debugging information, that normally means that GDB sets a step- | |
2271 | resume breakpoint and lets the program continue --- which is not | |
2272 | what the user wanted. (Giving the trampoline debugging info | |
2273 | doesn't help: the user expects the program to stop in the function | |
2274 | their program is calling, not in some trampoline code they've never | |
2275 | seen before.) | |
2276 | ||
e76f05fa | 2277 | The gdbarch_skip_trampoline_code method tells GDB how to step |
96309189 MS |
2278 | through such trampoline functions transparently to the user. When |
2279 | given the address of a trampoline function's first instruction, | |
e76f05fa | 2280 | gdbarch_skip_trampoline_code should return the address of the first |
96309189 MS |
2281 | instruction of the function really being called. If GDB decides it |
2282 | wants to step into that function, it will set a breakpoint there | |
2283 | and silently continue to it. | |
2284 | ||
2285 | We recognize the trampoline by name, and extract the target address | |
2286 | directly from the stack. This isn't great, but recognizing by its | |
2287 | code sequence seems more fragile. */ | |
2288 | ||
2289 | static CORE_ADDR | |
52f729a7 | 2290 | m32c_skip_trampoline_code (struct frame_info *frame, CORE_ADDR stop_pc) |
96309189 | 2291 | { |
e17a4113 UW |
2292 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2293 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2294 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
96309189 MS |
2295 | |
2296 | /* It would be nicer to simply look up the addresses of known | |
2297 | trampolines once, and then compare stop_pc with them. However, | |
2298 | we'd need to ensure that that cached address got invalidated when | |
2299 | someone loaded a new executable, and I'm not quite sure of the | |
2300 | best way to do that. find_pc_partial_function does do some | |
2301 | caching, so we'll see how this goes. */ | |
2c02bd72 | 2302 | const char *name; |
96309189 MS |
2303 | CORE_ADDR start, end; |
2304 | ||
2305 | if (find_pc_partial_function (stop_pc, &name, &start, &end)) | |
2306 | { | |
2307 | /* Are we stopped at the beginning of the trampoline function? */ | |
2308 | if (strcmp (name, "m32c_jsri16") == 0 | |
2309 | && stop_pc == start) | |
2310 | { | |
2311 | /* Get the stack pointer. The return address is at the top, | |
2312 | and the target function's address is just below that. We | |
2313 | know it's a two-byte address, since the trampoline is | |
2314 | m32c_jsri*16*. */ | |
2315 | CORE_ADDR sp = get_frame_sp (get_current_frame ()); | |
2316 | CORE_ADDR target | |
e17a4113 UW |
2317 | = read_memory_unsigned_integer (sp + tdep->ret_addr_bytes, |
2318 | 2, byte_order); | |
96309189 MS |
2319 | |
2320 | /* What we have now is the address of a jump instruction. | |
2321 | What we need is the destination of that jump. | |
025bb325 MS |
2322 | The opcode is 1 byte, and the destination is the next 3 bytes. */ |
2323 | ||
e17a4113 | 2324 | target = read_memory_unsigned_integer (target + 1, 3, byte_order); |
96309189 MS |
2325 | return target; |
2326 | } | |
2327 | } | |
2328 | ||
2329 | return 0; | |
2330 | } | |
2331 | ||
2332 | ||
2333 | /* Address/pointer conversions. */ | |
2334 | ||
2335 | /* On the m16c, there is a 24-bit address space, but only a very few | |
2336 | instructions can generate addresses larger than 0xffff: jumps, | |
2337 | jumps to subroutines, and the lde/std (load/store extended) | |
2338 | instructions. | |
2339 | ||
2340 | Since GCC can only support one size of pointer, we can't have | |
2341 | distinct 'near' and 'far' pointer types; we have to pick one size | |
2342 | for everything. If we wanted to use 24-bit pointers, then GCC | |
2343 | would have to use lde and ste for all memory references, which | |
2344 | would be terrible for performance and code size. So the GNU | |
2345 | toolchain uses 16-bit pointers for everything, and gives up the | |
2346 | ability to have pointers point outside the first 64k of memory. | |
2347 | ||
2348 | However, as a special hack, we let the linker place functions at | |
2349 | addresses above 0xffff, as long as it also places a trampoline in | |
2350 | the low 64k for every function whose address is taken. Each | |
2351 | trampoline consists of a single jmp.a instruction that jumps to the | |
2352 | function's real entry point. Pointers to functions can be 16 bits | |
2353 | long, even though the functions themselves are at higher addresses: | |
2354 | the pointers refer to the trampolines, not the functions. | |
2355 | ||
2356 | This complicates things for GDB, however: given the address of a | |
2357 | function (from debug info or linker symbols, say) which could be | |
2358 | anywhere in the 24-bit address space, how can we find an | |
2359 | appropriate 16-bit value to use as a pointer to it? | |
2360 | ||
2361 | If the linker has not generated a trampoline for the function, | |
2362 | we're out of luck. Well, I guess we could malloc some space and | |
2363 | write a jmp.a instruction to it, but I'm not going to get into that | |
2364 | at the moment. | |
2365 | ||
2366 | If the linker has generated a trampoline for the function, then it | |
2367 | also emitted a symbol for the trampoline: if the function's linker | |
2368 | symbol is named NAME, then the function's trampoline's linker | |
2369 | symbol is named NAME.plt. | |
2370 | ||
2371 | So, given a code address: | |
2372 | - We try to find a linker symbol at that address. | |
2373 | - If we find such a symbol named NAME, we look for a linker symbol | |
2374 | named NAME.plt. | |
2375 | - If we find such a symbol, we assume it is a trampoline, and use | |
2376 | its address as the pointer value. | |
2377 | ||
2378 | And, given a function pointer: | |
2379 | - We try to find a linker symbol at that address named NAME.plt. | |
2380 | - If we find such a symbol, we look for a linker symbol named NAME. | |
2381 | - If we find that, we provide that as the function's address. | |
2382 | - If any of the above steps fail, we return the original address | |
2383 | unchanged; it might really be a function in the low 64k. | |
2384 | ||
2385 | See? You *knew* there was a reason you wanted to be a computer | |
2386 | programmer! :) */ | |
2387 | ||
2388 | static void | |
9898f801 UW |
2389 | m32c_m16c_address_to_pointer (struct gdbarch *gdbarch, |
2390 | struct type *type, gdb_byte *buf, CORE_ADDR addr) | |
96309189 | 2391 | { |
e17a4113 | 2392 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
f79b9530 | 2393 | enum type_code target_code; |
78134374 | 2394 | gdb_assert (type->code () == TYPE_CODE_PTR || TYPE_IS_REFERENCE (type)); |
96309189 | 2395 | |
78134374 | 2396 | target_code = TYPE_TARGET_TYPE (type)->code (); |
96309189 MS |
2397 | |
2398 | if (target_code == TYPE_CODE_FUNC || target_code == TYPE_CODE_METHOD) | |
2399 | { | |
0d5cff50 | 2400 | const char *func_name; |
f79b9530 | 2401 | char *tramp_name; |
3b7344d5 | 2402 | struct bound_minimal_symbol tramp_msym; |
f79b9530 | 2403 | |
96309189 | 2404 | /* Try to find a linker symbol at this address. */ |
7cbd4a93 TT |
2405 | struct bound_minimal_symbol func_msym |
2406 | = lookup_minimal_symbol_by_pc (addr); | |
96309189 | 2407 | |
7cbd4a93 | 2408 | if (! func_msym.minsym) |
dda83cd7 SM |
2409 | error (_("Cannot convert code address %s to function pointer:\n" |
2410 | "couldn't find a symbol at that address, to find trampoline."), | |
2411 | paddress (gdbarch, addr)); | |
96309189 | 2412 | |
c9d95fa3 | 2413 | func_name = func_msym.minsym->linkage_name (); |
224c3ddb | 2414 | tramp_name = (char *) xmalloc (strlen (func_name) + 5); |
96309189 MS |
2415 | strcpy (tramp_name, func_name); |
2416 | strcat (tramp_name, ".plt"); | |
2417 | ||
2418 | /* Try to find a linker symbol for the trampoline. */ | |
f79b9530 | 2419 | tramp_msym = lookup_minimal_symbol (tramp_name, NULL, NULL); |
96309189 MS |
2420 | |
2421 | /* We've either got another copy of the name now, or don't need | |
dda83cd7 | 2422 | the name any more. */ |
96309189 MS |
2423 | xfree (tramp_name); |
2424 | ||
3b7344d5 | 2425 | if (! tramp_msym.minsym) |
d77b48cf KB |
2426 | { |
2427 | CORE_ADDR ptrval; | |
2428 | ||
2429 | /* No PLT entry found. Mask off the upper bits of the address | |
2430 | to make a pointer. As noted in the warning to the user | |
2431 | below, this value might be useful if converted back into | |
2432 | an address by GDB, but will otherwise, almost certainly, | |
2433 | be garbage. | |
2434 | ||
2435 | Using this masked result does seem to be useful | |
2436 | in gdb.cp/cplusfuncs.exp in which ~40 FAILs turn into | |
2437 | PASSes. These results appear to be correct as well. | |
2438 | ||
2439 | We print a warning here so that the user can make a | |
2440 | determination about whether the result is useful or not. */ | |
2441 | ptrval = addr & 0xffff; | |
2442 | ||
2443 | warning (_("Cannot convert code address %s to function pointer:\n" | |
2444 | "couldn't find trampoline named '%s.plt'.\n" | |
2445 | "Returning pointer value %s instead; this may produce\n" | |
2446 | "a useful result if converted back into an address by GDB,\n" | |
422186a9 | 2447 | "but will most likely not be useful otherwise."), |
d77b48cf KB |
2448 | paddress (gdbarch, addr), func_name, |
2449 | paddress (gdbarch, ptrval)); | |
2450 | ||
2451 | addr = ptrval; | |
96309189 | 2452 | |
d77b48cf KB |
2453 | } |
2454 | else | |
2455 | { | |
2456 | /* The trampoline's address is our pointer. */ | |
77e371c0 | 2457 | addr = BMSYMBOL_VALUE_ADDRESS (tramp_msym); |
d77b48cf | 2458 | } |
96309189 MS |
2459 | } |
2460 | ||
e17a4113 | 2461 | store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order, addr); |
96309189 MS |
2462 | } |
2463 | ||
2464 | ||
2465 | static CORE_ADDR | |
9898f801 UW |
2466 | m32c_m16c_pointer_to_address (struct gdbarch *gdbarch, |
2467 | struct type *type, const gdb_byte *buf) | |
96309189 | 2468 | { |
e17a4113 | 2469 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
f79b9530 DJ |
2470 | CORE_ADDR ptr; |
2471 | enum type_code target_code; | |
2472 | ||
78134374 | 2473 | gdb_assert (type->code () == TYPE_CODE_PTR || TYPE_IS_REFERENCE (type)); |
96309189 | 2474 | |
e17a4113 | 2475 | ptr = extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order); |
96309189 | 2476 | |
78134374 | 2477 | target_code = TYPE_TARGET_TYPE (type)->code (); |
96309189 MS |
2478 | |
2479 | if (target_code == TYPE_CODE_FUNC || target_code == TYPE_CODE_METHOD) | |
2480 | { | |
2481 | /* See if there is a minimal symbol at that address whose name is | |
dda83cd7 | 2482 | "NAME.plt". */ |
7cbd4a93 | 2483 | struct bound_minimal_symbol ptr_msym = lookup_minimal_symbol_by_pc (ptr); |
96309189 | 2484 | |
7cbd4a93 | 2485 | if (ptr_msym.minsym) |
dda83cd7 SM |
2486 | { |
2487 | const char *ptr_msym_name = ptr_msym.minsym->linkage_name (); | |
2488 | int len = strlen (ptr_msym_name); | |
96309189 | 2489 | |
dda83cd7 SM |
2490 | if (len > 4 |
2491 | && strcmp (ptr_msym_name + len - 4, ".plt") == 0) | |
2492 | { | |
3b7344d5 | 2493 | struct bound_minimal_symbol func_msym; |
dda83cd7 SM |
2494 | /* We have a .plt symbol; try to find the symbol for the |
2495 | corresponding function. | |
2496 | ||
2497 | Since the trampoline contains a jump instruction, we | |
2498 | could also just extract the jump's target address. I | |
2499 | don't see much advantage one way or the other. */ | |
2500 | char *func_name = (char *) xmalloc (len - 4 + 1); | |
2501 | memcpy (func_name, ptr_msym_name, len - 4); | |
2502 | func_name[len - 4] = '\0'; | |
2503 | func_msym | |
2504 | = lookup_minimal_symbol (func_name, NULL, NULL); | |
2505 | ||
2506 | /* If we do have such a symbol, return its value as the | |
2507 | function's true address. */ | |
2508 | if (func_msym.minsym) | |
2509 | ptr = BMSYMBOL_VALUE_ADDRESS (func_msym); | |
2510 | } | |
2511 | } | |
d77b48cf KB |
2512 | else |
2513 | { | |
2514 | int aspace; | |
2515 | ||
2516 | for (aspace = 1; aspace <= 15; aspace++) | |
2517 | { | |
2518 | ptr_msym = lookup_minimal_symbol_by_pc ((aspace << 16) | ptr); | |
2519 | ||
7cbd4a93 | 2520 | if (ptr_msym.minsym) |
d77b48cf KB |
2521 | ptr |= aspace << 16; |
2522 | } | |
2523 | } | |
96309189 MS |
2524 | } |
2525 | ||
2526 | return ptr; | |
2527 | } | |
2528 | ||
63807e1d | 2529 | static void |
a54fba4c | 2530 | m32c_virtual_frame_pointer (struct gdbarch *gdbarch, CORE_ADDR pc, |
7830cb4f CV |
2531 | int *frame_regnum, |
2532 | LONGEST *frame_offset) | |
2533 | { | |
2c02bd72 | 2534 | const char *name; |
22e048c9 | 2535 | CORE_ADDR func_addr, func_end; |
7830cb4f CV |
2536 | struct m32c_prologue p; |
2537 | ||
594f7785 | 2538 | struct regcache *regcache = get_current_regcache (); |
a54fba4c | 2539 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7830cb4f CV |
2540 | |
2541 | if (!find_pc_partial_function (pc, &name, &func_addr, &func_end)) | |
025bb325 MS |
2542 | internal_error (__FILE__, __LINE__, |
2543 | _("No virtual frame pointer available")); | |
7830cb4f | 2544 | |
a54fba4c | 2545 | m32c_analyze_prologue (gdbarch, func_addr, pc, &p); |
7830cb4f CV |
2546 | switch (p.kind) |
2547 | { | |
2548 | case prologue_with_frame_ptr: | |
594f7785 | 2549 | *frame_regnum = m32c_banked_register (tdep->fb, regcache)->num; |
7830cb4f CV |
2550 | *frame_offset = p.frame_ptr_offset; |
2551 | break; | |
2552 | case prologue_sans_frame_ptr: | |
594f7785 | 2553 | *frame_regnum = m32c_banked_register (tdep->sp, regcache)->num; |
7830cb4f CV |
2554 | *frame_offset = p.frame_size; |
2555 | break; | |
2556 | default: | |
594f7785 | 2557 | *frame_regnum = m32c_banked_register (tdep->sp, regcache)->num; |
7830cb4f CV |
2558 | *frame_offset = 0; |
2559 | break; | |
2560 | } | |
2561 | /* Sanity check */ | |
a54fba4c | 2562 | if (*frame_regnum > gdbarch_num_regs (gdbarch)) |
025bb325 MS |
2563 | internal_error (__FILE__, __LINE__, |
2564 | _("No virtual frame pointer available")); | |
7830cb4f | 2565 | } |
96309189 MS |
2566 | |
2567 | \f | |
2568 | /* Initialization. */ | |
2569 | ||
2570 | static struct gdbarch * | |
2571 | m32c_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2572 | { | |
97ce08cb | 2573 | struct gdbarch *gdbarch; |
96309189 MS |
2574 | struct gdbarch_tdep *tdep; |
2575 | unsigned long mach = info.bfd_arch_info->mach; | |
2576 | ||
2577 | /* Find a candidate among the list of architectures we've created | |
2578 | already. */ | |
2579 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
2580 | arches != NULL; | |
2581 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
2582 | return arches->gdbarch; | |
2583 | ||
8d749320 | 2584 | tdep = XCNEW (struct gdbarch_tdep); |
97ce08cb | 2585 | gdbarch = gdbarch_alloc (&info, tdep); |
96309189 MS |
2586 | |
2587 | /* Essential types. */ | |
97ce08cb | 2588 | make_types (gdbarch); |
96309189 MS |
2589 | |
2590 | /* Address/pointer conversions. */ | |
2591 | if (mach == bfd_mach_m16c) | |
2592 | { | |
97ce08cb YQ |
2593 | set_gdbarch_address_to_pointer (gdbarch, m32c_m16c_address_to_pointer); |
2594 | set_gdbarch_pointer_to_address (gdbarch, m32c_m16c_pointer_to_address); | |
96309189 MS |
2595 | } |
2596 | ||
2597 | /* Register set. */ | |
97ce08cb | 2598 | make_regs (gdbarch); |
96309189 | 2599 | |
96309189 | 2600 | /* Breakpoints. */ |
04180708 YQ |
2601 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, m32c_breakpoint::kind_from_pc); |
2602 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, m32c_breakpoint::bp_from_kind); | |
96309189 MS |
2603 | |
2604 | /* Prologue analysis and unwinding. */ | |
97ce08cb YQ |
2605 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
2606 | set_gdbarch_skip_prologue (gdbarch, m32c_skip_prologue); | |
96309189 MS |
2607 | #if 0 |
2608 | /* I'm dropping the dwarf2 sniffer because it has a few problems. | |
2609 | They may be in the dwarf2 cfi code in GDB, or they may be in | |
2610 | the debug info emitted by the upstream toolchain. I don't | |
2611 | know which, but I do know that the prologue analyzer works better. | |
025bb325 | 2612 | MVS 04/13/06 */ |
97ce08cb | 2613 | dwarf2_append_sniffers (gdbarch); |
96309189 | 2614 | #endif |
97ce08cb | 2615 | frame_unwind_append_unwinder (gdbarch, &m32c_unwind); |
96309189 MS |
2616 | |
2617 | /* Inferior calls. */ | |
97ce08cb YQ |
2618 | set_gdbarch_push_dummy_call (gdbarch, m32c_push_dummy_call); |
2619 | set_gdbarch_return_value (gdbarch, m32c_return_value); | |
96309189 MS |
2620 | |
2621 | /* Trampolines. */ | |
97ce08cb | 2622 | set_gdbarch_skip_trampoline_code (gdbarch, m32c_skip_trampoline_code); |
96309189 | 2623 | |
97ce08cb | 2624 | set_gdbarch_virtual_frame_pointer (gdbarch, m32c_virtual_frame_pointer); |
7830cb4f | 2625 | |
ed09d7da KB |
2626 | /* m32c function boundary addresses are not necessarily even. |
2627 | Therefore, the `vbit', which indicates a pointer to a virtual | |
2628 | member function, is stored in the delta field, rather than as | |
025bb325 | 2629 | the low bit of a function pointer address. |
ed09d7da KB |
2630 | |
2631 | In order to verify this, see the definition of | |
2632 | TARGET_PTRMEMFUNC_VBIT_LOCATION in gcc/defaults.h along with the | |
2633 | definition of FUNCTION_BOUNDARY in gcc/config/m32c/m32c.h. */ | |
97ce08cb | 2634 | set_gdbarch_vbit_in_delta (gdbarch, 1); |
ed09d7da | 2635 | |
97ce08cb | 2636 | return gdbarch; |
96309189 MS |
2637 | } |
2638 | ||
6c265988 | 2639 | void _initialize_m32c_tdep (); |
96309189 | 2640 | void |
6c265988 | 2641 | _initialize_m32c_tdep () |
96309189 MS |
2642 | { |
2643 | register_gdbarch_init (bfd_arch_m32c, m32c_gdbarch_init); | |
2644 | ||
2645 | m32c_dma_reggroup = reggroup_new ("dma", USER_REGGROUP); | |
2646 | } |