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96309189 MS |
1 | /* Renesas M32C target-dependent code for GDB, the GNU debugger. |
2 | ||
7b6bb8da JB |
3 | Copyright 2004, 2005, 2007, 2008, 2009, 2010, 2011 |
4 | Free Software Foundation, Inc. | |
96309189 MS |
5 | |
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 10 | the Free Software Foundation; either version 3 of the License, or |
96309189 MS |
11 | (at your option) any later version. |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
96309189 MS |
20 | |
21 | #include "defs.h" | |
22 | ||
23 | #include <stdarg.h> | |
24 | ||
25 | #if defined (HAVE_STRING_H) | |
26 | #include <string.h> | |
27 | #endif | |
28 | ||
29 | #include "gdb_assert.h" | |
30 | #include "elf-bfd.h" | |
31 | #include "elf/m32c.h" | |
32 | #include "gdb/sim-m32c.h" | |
33 | #include "dis-asm.h" | |
34 | #include "gdbtypes.h" | |
35 | #include "regcache.h" | |
36 | #include "arch-utils.h" | |
37 | #include "frame.h" | |
38 | #include "frame-unwind.h" | |
39 | #include "dwarf2-frame.h" | |
40 | #include "dwarf2expr.h" | |
41 | #include "symtab.h" | |
42 | #include "gdbcore.h" | |
43 | #include "value.h" | |
44 | #include "reggroups.h" | |
45 | #include "prologue-value.h" | |
46 | #include "target.h" | |
47 | ||
48 | \f | |
49 | /* The m32c tdep structure. */ | |
50 | ||
51 | static struct reggroup *m32c_dma_reggroup; | |
52 | ||
53 | struct m32c_reg; | |
54 | ||
55 | /* The type of a function that moves the value of REG between CACHE or | |
56 | BUF --- in either direction. */ | |
05d1431c PA |
57 | typedef enum register_status (m32c_move_reg_t) (struct m32c_reg *reg, |
58 | struct regcache *cache, | |
59 | void *buf); | |
96309189 MS |
60 | |
61 | struct m32c_reg | |
62 | { | |
63 | /* The name of this register. */ | |
64 | const char *name; | |
65 | ||
66 | /* Its type. */ | |
67 | struct type *type; | |
68 | ||
69 | /* The architecture this register belongs to. */ | |
70 | struct gdbarch *arch; | |
71 | ||
72 | /* Its GDB register number. */ | |
73 | int num; | |
74 | ||
75 | /* Its sim register number. */ | |
76 | int sim_num; | |
77 | ||
78 | /* Its DWARF register number, or -1 if it doesn't have one. */ | |
79 | int dwarf_num; | |
80 | ||
81 | /* Register group memberships. */ | |
82 | unsigned int general_p : 1; | |
83 | unsigned int dma_p : 1; | |
84 | unsigned int system_p : 1; | |
85 | unsigned int save_restore_p : 1; | |
86 | ||
87 | /* Functions to read its value from a regcache, and write its value | |
88 | to a regcache. */ | |
89 | m32c_move_reg_t *read, *write; | |
90 | ||
91 | /* Data for READ and WRITE functions. The exact meaning depends on | |
92 | the specific functions selected; see the comments for those | |
93 | functions. */ | |
94 | struct m32c_reg *rx, *ry; | |
95 | int n; | |
96 | }; | |
97 | ||
98 | ||
99 | /* An overestimate of the number of raw and pseudoregisters we will | |
100 | have. The exact answer depends on the variant of the architecture | |
101 | at hand, but we can use this to declare statically allocated | |
102 | arrays, and bump it up when needed. */ | |
103 | #define M32C_MAX_NUM_REGS (75) | |
104 | ||
105 | /* The largest assigned DWARF register number. */ | |
106 | #define M32C_MAX_DWARF_REGNUM (40) | |
107 | ||
108 | ||
109 | struct gdbarch_tdep | |
110 | { | |
111 | /* All the registers for this variant, indexed by GDB register | |
112 | number, and the number of registers present. */ | |
113 | struct m32c_reg regs[M32C_MAX_NUM_REGS]; | |
114 | ||
115 | /* The number of valid registers. */ | |
116 | int num_regs; | |
117 | ||
118 | /* Interesting registers. These are pointers into REGS. */ | |
119 | struct m32c_reg *pc, *flg; | |
120 | struct m32c_reg *r0, *r1, *r2, *r3, *a0, *a1; | |
121 | struct m32c_reg *r2r0, *r3r2r1r0, *r3r1r2r0; | |
122 | struct m32c_reg *sb, *fb, *sp; | |
123 | ||
124 | /* A table indexed by DWARF register numbers, pointing into | |
125 | REGS. */ | |
126 | struct m32c_reg *dwarf_regs[M32C_MAX_DWARF_REGNUM + 1]; | |
127 | ||
128 | /* Types for this architecture. We can't use the builtin_type_foo | |
129 | types, because they're not initialized when building a gdbarch | |
130 | structure. */ | |
131 | struct type *voyd, *ptr_voyd, *func_voyd; | |
132 | struct type *uint8, *uint16; | |
133 | struct type *int8, *int16, *int32, *int64; | |
134 | ||
135 | /* The types for data address and code address registers. */ | |
136 | struct type *data_addr_reg_type, *code_addr_reg_type; | |
137 | ||
138 | /* The number of bytes a return address pushed by a 'jsr' instruction | |
139 | occupies on the stack. */ | |
140 | int ret_addr_bytes; | |
141 | ||
142 | /* The number of bytes an address register occupies on the stack | |
143 | when saved by an 'enter' or 'pushm' instruction. */ | |
144 | int push_addr_bytes; | |
145 | }; | |
146 | ||
147 | \f | |
148 | /* Types. */ | |
149 | ||
150 | static void | |
151 | make_types (struct gdbarch *arch) | |
152 | { | |
153 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); | |
154 | unsigned long mach = gdbarch_bfd_arch_info (arch)->mach; | |
155 | int data_addr_reg_bits, code_addr_reg_bits; | |
156 | char type_name[50]; | |
157 | ||
158 | #if 0 | |
159 | /* This is used to clip CORE_ADDR values, so this value is | |
160 | appropriate both on the m32c, where pointers are 32 bits long, | |
161 | and on the m16c, where pointers are sixteen bits long, but there | |
162 | may be code above the 64k boundary. */ | |
163 | set_gdbarch_addr_bit (arch, 24); | |
164 | #else | |
165 | /* GCC uses 32 bits for addrs in the dwarf info, even though | |
166 | only 16/24 bits are used. Setting addr_bit to 24 causes | |
167 | errors in reading the dwarf addresses. */ | |
168 | set_gdbarch_addr_bit (arch, 32); | |
169 | #endif | |
170 | ||
171 | set_gdbarch_int_bit (arch, 16); | |
172 | switch (mach) | |
173 | { | |
174 | case bfd_mach_m16c: | |
175 | data_addr_reg_bits = 16; | |
176 | code_addr_reg_bits = 24; | |
177 | set_gdbarch_ptr_bit (arch, 16); | |
178 | tdep->ret_addr_bytes = 3; | |
179 | tdep->push_addr_bytes = 2; | |
180 | break; | |
181 | ||
182 | case bfd_mach_m32c: | |
183 | data_addr_reg_bits = 24; | |
184 | code_addr_reg_bits = 24; | |
185 | set_gdbarch_ptr_bit (arch, 32); | |
186 | tdep->ret_addr_bytes = 4; | |
187 | tdep->push_addr_bytes = 4; | |
188 | break; | |
189 | ||
190 | default: | |
f3574227 | 191 | gdb_assert_not_reached ("unexpected mach"); |
96309189 MS |
192 | } |
193 | ||
194 | /* The builtin_type_mumble variables are sometimes uninitialized when | |
195 | this is called, so we avoid using them. */ | |
e9bb382b UW |
196 | tdep->voyd = arch_type (arch, TYPE_CODE_VOID, 1, "void"); |
197 | tdep->ptr_voyd | |
bd333fb7 KB |
198 | = arch_type (arch, TYPE_CODE_PTR, gdbarch_ptr_bit (arch) / TARGET_CHAR_BIT, |
199 | NULL); | |
96309189 | 200 | TYPE_TARGET_TYPE (tdep->ptr_voyd) = tdep->voyd; |
e9bb382b | 201 | TYPE_UNSIGNED (tdep->ptr_voyd) = 1; |
96309189 MS |
202 | tdep->func_voyd = lookup_function_type (tdep->voyd); |
203 | ||
204 | sprintf (type_name, "%s_data_addr_t", | |
205 | gdbarch_bfd_arch_info (arch)->printable_name); | |
206 | tdep->data_addr_reg_type | |
bd333fb7 KB |
207 | = arch_type (arch, TYPE_CODE_PTR, data_addr_reg_bits / TARGET_CHAR_BIT, |
208 | xstrdup (type_name)); | |
96309189 | 209 | TYPE_TARGET_TYPE (tdep->data_addr_reg_type) = tdep->voyd; |
e9bb382b | 210 | TYPE_UNSIGNED (tdep->data_addr_reg_type) = 1; |
96309189 MS |
211 | |
212 | sprintf (type_name, "%s_code_addr_t", | |
213 | gdbarch_bfd_arch_info (arch)->printable_name); | |
214 | tdep->code_addr_reg_type | |
bd333fb7 KB |
215 | = arch_type (arch, TYPE_CODE_PTR, code_addr_reg_bits / TARGET_CHAR_BIT, |
216 | xstrdup (type_name)); | |
96309189 | 217 | TYPE_TARGET_TYPE (tdep->code_addr_reg_type) = tdep->func_voyd; |
e9bb382b UW |
218 | TYPE_UNSIGNED (tdep->code_addr_reg_type) = 1; |
219 | ||
220 | tdep->uint8 = arch_integer_type (arch, 8, 1, "uint8_t"); | |
221 | tdep->uint16 = arch_integer_type (arch, 16, 1, "uint16_t"); | |
222 | tdep->int8 = arch_integer_type (arch, 8, 0, "int8_t"); | |
223 | tdep->int16 = arch_integer_type (arch, 16, 0, "int16_t"); | |
224 | tdep->int32 = arch_integer_type (arch, 32, 0, "int32_t"); | |
225 | tdep->int64 = arch_integer_type (arch, 64, 0, "int64_t"); | |
96309189 MS |
226 | } |
227 | ||
228 | ||
229 | \f | |
230 | /* Register set. */ | |
231 | ||
232 | static const char * | |
d93859e2 | 233 | m32c_register_name (struct gdbarch *gdbarch, int num) |
96309189 | 234 | { |
d93859e2 | 235 | return gdbarch_tdep (gdbarch)->regs[num].name; |
96309189 MS |
236 | } |
237 | ||
238 | ||
239 | static struct type * | |
240 | m32c_register_type (struct gdbarch *arch, int reg_nr) | |
241 | { | |
242 | return gdbarch_tdep (arch)->regs[reg_nr].type; | |
243 | } | |
244 | ||
245 | ||
246 | static int | |
e7faf938 | 247 | m32c_register_sim_regno (struct gdbarch *gdbarch, int reg_nr) |
96309189 | 248 | { |
e7faf938 | 249 | return gdbarch_tdep (gdbarch)->regs[reg_nr].sim_num; |
96309189 MS |
250 | } |
251 | ||
252 | ||
253 | static int | |
d3f73121 | 254 | m32c_debug_info_reg_to_regnum (struct gdbarch *gdbarch, int reg_nr) |
96309189 | 255 | { |
d3f73121 | 256 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
96309189 MS |
257 | if (0 <= reg_nr && reg_nr <= M32C_MAX_DWARF_REGNUM |
258 | && tdep->dwarf_regs[reg_nr]) | |
259 | return tdep->dwarf_regs[reg_nr]->num; | |
260 | else | |
261 | /* The DWARF CFI code expects to see -1 for invalid register | |
262 | numbers. */ | |
263 | return -1; | |
264 | } | |
265 | ||
266 | ||
63807e1d | 267 | static int |
96309189 MS |
268 | m32c_register_reggroup_p (struct gdbarch *gdbarch, int regnum, |
269 | struct reggroup *group) | |
270 | { | |
40a6adc1 | 271 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
96309189 MS |
272 | struct m32c_reg *reg = &tdep->regs[regnum]; |
273 | ||
274 | /* The anonymous raw registers aren't in any groups. */ | |
275 | if (! reg->name) | |
276 | return 0; | |
277 | ||
278 | if (group == all_reggroup) | |
279 | return 1; | |
280 | ||
281 | if (group == general_reggroup | |
282 | && reg->general_p) | |
283 | return 1; | |
284 | ||
285 | if (group == m32c_dma_reggroup | |
286 | && reg->dma_p) | |
287 | return 1; | |
288 | ||
289 | if (group == system_reggroup | |
290 | && reg->system_p) | |
291 | return 1; | |
292 | ||
293 | /* Since the m32c DWARF register numbers refer to cooked registers, not | |
294 | raw registers, and frame_pop depends on the save and restore groups | |
295 | containing registers the DWARF CFI will actually mention, our save | |
296 | and restore groups are cooked registers, not raw registers. (This is | |
297 | why we can't use the default reggroup function.) */ | |
298 | if ((group == save_reggroup | |
299 | || group == restore_reggroup) | |
300 | && reg->save_restore_p) | |
301 | return 1; | |
302 | ||
303 | return 0; | |
304 | } | |
305 | ||
306 | ||
307 | /* Register move functions. We declare them here using | |
308 | m32c_move_reg_t to check the types. */ | |
309 | static m32c_move_reg_t m32c_raw_read, m32c_raw_write; | |
310 | static m32c_move_reg_t m32c_banked_read, m32c_banked_write; | |
311 | static m32c_move_reg_t m32c_sb_read, m32c_sb_write; | |
312 | static m32c_move_reg_t m32c_part_read, m32c_part_write; | |
313 | static m32c_move_reg_t m32c_cat_read, m32c_cat_write; | |
314 | static m32c_move_reg_t m32c_r3r2r1r0_read, m32c_r3r2r1r0_write; | |
315 | ||
316 | ||
317 | /* Copy the value of the raw register REG from CACHE to BUF. */ | |
05d1431c | 318 | static enum register_status |
96309189 MS |
319 | m32c_raw_read (struct m32c_reg *reg, struct regcache *cache, void *buf) |
320 | { | |
05d1431c | 321 | return regcache_raw_read (cache, reg->num, buf); |
96309189 MS |
322 | } |
323 | ||
324 | ||
325 | /* Copy the value of the raw register REG from BUF to CACHE. */ | |
05d1431c | 326 | static enum register_status |
96309189 MS |
327 | m32c_raw_write (struct m32c_reg *reg, struct regcache *cache, void *buf) |
328 | { | |
329 | regcache_raw_write (cache, reg->num, (const void *) buf); | |
05d1431c PA |
330 | |
331 | return REG_VALID; | |
96309189 MS |
332 | } |
333 | ||
334 | ||
335 | /* Return the value of the 'flg' register in CACHE. */ | |
336 | static int | |
337 | m32c_read_flg (struct regcache *cache) | |
338 | { | |
339 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (cache)); | |
340 | ULONGEST flg; | |
341 | regcache_raw_read_unsigned (cache, tdep->flg->num, &flg); | |
342 | return flg & 0xffff; | |
343 | } | |
344 | ||
345 | ||
7830cb4f CV |
346 | /* Evaluate the real register number of a banked register. */ |
347 | static struct m32c_reg * | |
348 | m32c_banked_register (struct m32c_reg *reg, struct regcache *cache) | |
349 | { | |
350 | return ((m32c_read_flg (cache) & reg->n) ? reg->ry : reg->rx); | |
351 | } | |
352 | ||
353 | ||
96309189 MS |
354 | /* Move the value of a banked register from CACHE to BUF. |
355 | If the value of the 'flg' register in CACHE has any of the bits | |
356 | masked in REG->n set, then read REG->ry. Otherwise, read | |
357 | REG->rx. */ | |
05d1431c | 358 | static enum register_status |
96309189 MS |
359 | m32c_banked_read (struct m32c_reg *reg, struct regcache *cache, void *buf) |
360 | { | |
7830cb4f | 361 | struct m32c_reg *bank_reg = m32c_banked_register (reg, cache); |
05d1431c | 362 | return regcache_raw_read (cache, bank_reg->num, buf); |
96309189 MS |
363 | } |
364 | ||
365 | ||
366 | /* Move the value of a banked register from BUF to CACHE. | |
367 | If the value of the 'flg' register in CACHE has any of the bits | |
368 | masked in REG->n set, then write REG->ry. Otherwise, write | |
369 | REG->rx. */ | |
05d1431c | 370 | static enum register_status |
96309189 MS |
371 | m32c_banked_write (struct m32c_reg *reg, struct regcache *cache, void *buf) |
372 | { | |
7830cb4f | 373 | struct m32c_reg *bank_reg = m32c_banked_register (reg, cache); |
96309189 | 374 | regcache_raw_write (cache, bank_reg->num, (const void *) buf); |
05d1431c PA |
375 | |
376 | return REG_VALID; | |
96309189 MS |
377 | } |
378 | ||
379 | ||
380 | /* Move the value of SB from CACHE to BUF. On bfd_mach_m32c, SB is a | |
381 | banked register; on bfd_mach_m16c, it's not. */ | |
05d1431c | 382 | static enum register_status |
96309189 MS |
383 | m32c_sb_read (struct m32c_reg *reg, struct regcache *cache, void *buf) |
384 | { | |
385 | if (gdbarch_bfd_arch_info (reg->arch)->mach == bfd_mach_m16c) | |
05d1431c | 386 | return m32c_raw_read (reg->rx, cache, buf); |
96309189 | 387 | else |
05d1431c | 388 | return m32c_banked_read (reg, cache, buf); |
96309189 MS |
389 | } |
390 | ||
391 | ||
392 | /* Move the value of SB from BUF to CACHE. On bfd_mach_m32c, SB is a | |
393 | banked register; on bfd_mach_m16c, it's not. */ | |
05d1431c | 394 | static enum register_status |
96309189 MS |
395 | m32c_sb_write (struct m32c_reg *reg, struct regcache *cache, void *buf) |
396 | { | |
397 | if (gdbarch_bfd_arch_info (reg->arch)->mach == bfd_mach_m16c) | |
398 | m32c_raw_write (reg->rx, cache, buf); | |
399 | else | |
400 | m32c_banked_write (reg, cache, buf); | |
05d1431c PA |
401 | |
402 | return REG_VALID; | |
96309189 MS |
403 | } |
404 | ||
405 | ||
406 | /* Assuming REG uses m32c_part_read and m32c_part_write, set *OFFSET_P | |
407 | and *LEN_P to the offset and length, in bytes, of the part REG | |
408 | occupies in its underlying register. The offset is from the | |
409 | lower-addressed end, regardless of the architecture's endianness. | |
410 | (The M32C family is always little-endian, but let's keep those | |
411 | assumptions out of here.) */ | |
412 | static void | |
413 | m32c_find_part (struct m32c_reg *reg, int *offset_p, int *len_p) | |
414 | { | |
415 | /* The length of the containing register, of which REG is one part. */ | |
416 | int containing_len = TYPE_LENGTH (reg->rx->type); | |
417 | ||
418 | /* The length of one "element" in our imaginary array. */ | |
419 | int elt_len = TYPE_LENGTH (reg->type); | |
420 | ||
421 | /* The offset of REG's "element" from the least significant end of | |
422 | the containing register. */ | |
423 | int elt_offset = reg->n * elt_len; | |
424 | ||
425 | /* If we extend off the end, trim the length of the element. */ | |
426 | if (elt_offset + elt_len > containing_len) | |
427 | { | |
428 | elt_len = containing_len - elt_offset; | |
429 | /* We shouldn't be declaring partial registers that go off the | |
430 | end of their containing registers. */ | |
431 | gdb_assert (elt_len > 0); | |
432 | } | |
433 | ||
434 | /* Flip the offset around if we're big-endian. */ | |
435 | if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG) | |
436 | elt_offset = TYPE_LENGTH (reg->rx->type) - elt_offset - elt_len; | |
437 | ||
438 | *offset_p = elt_offset; | |
439 | *len_p = elt_len; | |
440 | } | |
441 | ||
442 | ||
443 | /* Move the value of a partial register (r0h, intbl, etc.) from CACHE | |
444 | to BUF. Treating the value of the register REG->rx as an array of | |
445 | REG->type values, where higher indices refer to more significant | |
446 | bits, read the value of the REG->n'th element. */ | |
05d1431c | 447 | static enum register_status |
96309189 MS |
448 | m32c_part_read (struct m32c_reg *reg, struct regcache *cache, void *buf) |
449 | { | |
450 | int offset, len; | |
05d1431c | 451 | |
96309189 MS |
452 | memset (buf, 0, TYPE_LENGTH (reg->type)); |
453 | m32c_find_part (reg, &offset, &len); | |
05d1431c | 454 | return regcache_cooked_read_part (cache, reg->rx->num, offset, len, buf); |
96309189 MS |
455 | } |
456 | ||
457 | ||
458 | /* Move the value of a banked register from BUF to CACHE. | |
459 | Treating the value of the register REG->rx as an array of REG->type | |
460 | values, where higher indices refer to more significant bits, write | |
461 | the value of the REG->n'th element. */ | |
05d1431c | 462 | static enum register_status |
96309189 MS |
463 | m32c_part_write (struct m32c_reg *reg, struct regcache *cache, void *buf) |
464 | { | |
465 | int offset, len; | |
05d1431c | 466 | |
96309189 MS |
467 | m32c_find_part (reg, &offset, &len); |
468 | regcache_cooked_write_part (cache, reg->rx->num, offset, len, buf); | |
05d1431c PA |
469 | |
470 | return REG_VALID; | |
96309189 MS |
471 | } |
472 | ||
473 | ||
474 | /* Move the value of REG from CACHE to BUF. REG's value is the | |
475 | concatenation of the values of the registers REG->rx and REG->ry, | |
476 | with REG->rx contributing the more significant bits. */ | |
05d1431c | 477 | static enum register_status |
96309189 MS |
478 | m32c_cat_read (struct m32c_reg *reg, struct regcache *cache, void *buf) |
479 | { | |
480 | int high_bytes = TYPE_LENGTH (reg->rx->type); | |
481 | int low_bytes = TYPE_LENGTH (reg->ry->type); | |
482 | /* For address arithmetic. */ | |
483 | unsigned char *cbuf = buf; | |
05d1431c | 484 | enum register_status status; |
96309189 MS |
485 | |
486 | gdb_assert (TYPE_LENGTH (reg->type) == high_bytes + low_bytes); | |
487 | ||
488 | if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG) | |
489 | { | |
05d1431c PA |
490 | status = regcache_cooked_read (cache, reg->rx->num, cbuf); |
491 | if (status == REG_VALID) | |
492 | status = regcache_cooked_read (cache, reg->ry->num, cbuf + high_bytes); | |
96309189 MS |
493 | } |
494 | else | |
495 | { | |
05d1431c PA |
496 | status = regcache_cooked_read (cache, reg->rx->num, cbuf + low_bytes); |
497 | if (status == REG_VALID) | |
498 | status = regcache_cooked_read (cache, reg->ry->num, cbuf); | |
96309189 | 499 | } |
05d1431c PA |
500 | |
501 | return status; | |
96309189 MS |
502 | } |
503 | ||
504 | ||
505 | /* Move the value of REG from CACHE to BUF. REG's value is the | |
506 | concatenation of the values of the registers REG->rx and REG->ry, | |
507 | with REG->rx contributing the more significant bits. */ | |
05d1431c | 508 | static enum register_status |
96309189 MS |
509 | m32c_cat_write (struct m32c_reg *reg, struct regcache *cache, void *buf) |
510 | { | |
511 | int high_bytes = TYPE_LENGTH (reg->rx->type); | |
512 | int low_bytes = TYPE_LENGTH (reg->ry->type); | |
513 | /* For address arithmetic. */ | |
514 | unsigned char *cbuf = buf; | |
515 | ||
516 | gdb_assert (TYPE_LENGTH (reg->type) == high_bytes + low_bytes); | |
517 | ||
518 | if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG) | |
519 | { | |
520 | regcache_cooked_write (cache, reg->rx->num, cbuf); | |
521 | regcache_cooked_write (cache, reg->ry->num, cbuf + high_bytes); | |
522 | } | |
523 | else | |
524 | { | |
525 | regcache_cooked_write (cache, reg->rx->num, cbuf + low_bytes); | |
526 | regcache_cooked_write (cache, reg->ry->num, cbuf); | |
527 | } | |
05d1431c PA |
528 | |
529 | return REG_VALID; | |
96309189 MS |
530 | } |
531 | ||
532 | ||
533 | /* Copy the value of the raw register REG from CACHE to BUF. REG is | |
534 | the concatenation (from most significant to least) of r3, r2, r1, | |
535 | and r0. */ | |
05d1431c | 536 | static enum register_status |
96309189 MS |
537 | m32c_r3r2r1r0_read (struct m32c_reg *reg, struct regcache *cache, void *buf) |
538 | { | |
539 | struct gdbarch_tdep *tdep = gdbarch_tdep (reg->arch); | |
540 | int len = TYPE_LENGTH (tdep->r0->type); | |
05d1431c | 541 | enum register_status status; |
96309189 MS |
542 | |
543 | /* For address arithmetic. */ | |
544 | unsigned char *cbuf = buf; | |
545 | ||
546 | if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG) | |
547 | { | |
05d1431c PA |
548 | status = regcache_cooked_read (cache, tdep->r0->num, cbuf + len * 3); |
549 | if (status == REG_VALID) | |
550 | status = regcache_cooked_read (cache, tdep->r1->num, cbuf + len * 2); | |
551 | if (status == REG_VALID) | |
552 | status = regcache_cooked_read (cache, tdep->r2->num, cbuf + len * 1); | |
553 | if (status == REG_VALID) | |
554 | status = regcache_cooked_read (cache, tdep->r3->num, cbuf); | |
96309189 MS |
555 | } |
556 | else | |
557 | { | |
05d1431c PA |
558 | status = regcache_cooked_read (cache, tdep->r0->num, cbuf); |
559 | if (status == REG_VALID) | |
560 | status = regcache_cooked_read (cache, tdep->r1->num, cbuf + len * 1); | |
561 | if (status == REG_VALID) | |
562 | status = regcache_cooked_read (cache, tdep->r2->num, cbuf + len * 2); | |
563 | if (status == REG_VALID) | |
564 | status = regcache_cooked_read (cache, tdep->r3->num, cbuf + len * 3); | |
96309189 | 565 | } |
05d1431c PA |
566 | |
567 | return status; | |
96309189 MS |
568 | } |
569 | ||
570 | ||
571 | /* Copy the value of the raw register REG from BUF to CACHE. REG is | |
572 | the concatenation (from most significant to least) of r3, r2, r1, | |
573 | and r0. */ | |
05d1431c | 574 | static enum register_status |
96309189 MS |
575 | m32c_r3r2r1r0_write (struct m32c_reg *reg, struct regcache *cache, void *buf) |
576 | { | |
577 | struct gdbarch_tdep *tdep = gdbarch_tdep (reg->arch); | |
578 | int len = TYPE_LENGTH (tdep->r0->type); | |
579 | ||
580 | /* For address arithmetic. */ | |
581 | unsigned char *cbuf = buf; | |
582 | ||
583 | if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG) | |
584 | { | |
585 | regcache_cooked_write (cache, tdep->r0->num, cbuf + len * 3); | |
586 | regcache_cooked_write (cache, tdep->r1->num, cbuf + len * 2); | |
587 | regcache_cooked_write (cache, tdep->r2->num, cbuf + len * 1); | |
588 | regcache_cooked_write (cache, tdep->r3->num, cbuf); | |
589 | } | |
590 | else | |
591 | { | |
592 | regcache_cooked_write (cache, tdep->r0->num, cbuf); | |
593 | regcache_cooked_write (cache, tdep->r1->num, cbuf + len * 1); | |
594 | regcache_cooked_write (cache, tdep->r2->num, cbuf + len * 2); | |
595 | regcache_cooked_write (cache, tdep->r3->num, cbuf + len * 3); | |
596 | } | |
05d1431c PA |
597 | |
598 | return REG_VALID; | |
96309189 MS |
599 | } |
600 | ||
601 | ||
05d1431c | 602 | static enum register_status |
96309189 MS |
603 | m32c_pseudo_register_read (struct gdbarch *arch, |
604 | struct regcache *cache, | |
605 | int cookednum, | |
606 | gdb_byte *buf) | |
607 | { | |
608 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); | |
609 | struct m32c_reg *reg; | |
610 | ||
611 | gdb_assert (0 <= cookednum && cookednum < tdep->num_regs); | |
612 | gdb_assert (arch == get_regcache_arch (cache)); | |
613 | gdb_assert (arch == tdep->regs[cookednum].arch); | |
614 | reg = &tdep->regs[cookednum]; | |
615 | ||
05d1431c | 616 | return reg->read (reg, cache, buf); |
96309189 MS |
617 | } |
618 | ||
619 | ||
620 | static void | |
621 | m32c_pseudo_register_write (struct gdbarch *arch, | |
622 | struct regcache *cache, | |
623 | int cookednum, | |
624 | const gdb_byte *buf) | |
625 | { | |
626 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); | |
627 | struct m32c_reg *reg; | |
628 | ||
629 | gdb_assert (0 <= cookednum && cookednum < tdep->num_regs); | |
630 | gdb_assert (arch == get_regcache_arch (cache)); | |
631 | gdb_assert (arch == tdep->regs[cookednum].arch); | |
632 | reg = &tdep->regs[cookednum]; | |
633 | ||
634 | reg->write (reg, cache, (void *) buf); | |
635 | } | |
636 | ||
637 | ||
638 | /* Add a register with the given fields to the end of ARCH's table. | |
639 | Return a pointer to the newly added register. */ | |
640 | static struct m32c_reg * | |
641 | add_reg (struct gdbarch *arch, | |
642 | const char *name, | |
643 | struct type *type, | |
644 | int sim_num, | |
645 | m32c_move_reg_t *read, | |
646 | m32c_move_reg_t *write, | |
647 | struct m32c_reg *rx, | |
648 | struct m32c_reg *ry, | |
649 | int n) | |
650 | { | |
651 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); | |
652 | struct m32c_reg *r = &tdep->regs[tdep->num_regs]; | |
653 | ||
654 | gdb_assert (tdep->num_regs < M32C_MAX_NUM_REGS); | |
655 | ||
656 | r->name = name; | |
657 | r->type = type; | |
658 | r->arch = arch; | |
659 | r->num = tdep->num_regs; | |
660 | r->sim_num = sim_num; | |
661 | r->dwarf_num = -1; | |
662 | r->general_p = 0; | |
663 | r->dma_p = 0; | |
664 | r->system_p = 0; | |
665 | r->save_restore_p = 0; | |
666 | r->read = read; | |
667 | r->write = write; | |
668 | r->rx = rx; | |
669 | r->ry = ry; | |
670 | r->n = n; | |
671 | ||
672 | tdep->num_regs++; | |
673 | ||
674 | return r; | |
675 | } | |
676 | ||
677 | ||
678 | /* Record NUM as REG's DWARF register number. */ | |
679 | static void | |
680 | set_dwarf_regnum (struct m32c_reg *reg, int num) | |
681 | { | |
682 | gdb_assert (num < M32C_MAX_NUM_REGS); | |
683 | ||
684 | /* Update the reg->DWARF mapping. Only count the first number | |
685 | assigned to this register. */ | |
686 | if (reg->dwarf_num == -1) | |
687 | reg->dwarf_num = num; | |
688 | ||
689 | /* Update the DWARF->reg mapping. */ | |
690 | gdbarch_tdep (reg->arch)->dwarf_regs[num] = reg; | |
691 | } | |
692 | ||
693 | ||
694 | /* Mark REG as a general-purpose register, and return it. */ | |
695 | static struct m32c_reg * | |
696 | mark_general (struct m32c_reg *reg) | |
697 | { | |
698 | reg->general_p = 1; | |
699 | return reg; | |
700 | } | |
701 | ||
702 | ||
703 | /* Mark REG as a DMA register, and return it. */ | |
704 | static struct m32c_reg * | |
705 | mark_dma (struct m32c_reg *reg) | |
706 | { | |
707 | reg->dma_p = 1; | |
708 | return reg; | |
709 | } | |
710 | ||
711 | ||
712 | /* Mark REG as a SYSTEM register, and return it. */ | |
713 | static struct m32c_reg * | |
714 | mark_system (struct m32c_reg *reg) | |
715 | { | |
716 | reg->system_p = 1; | |
717 | return reg; | |
718 | } | |
719 | ||
720 | ||
721 | /* Mark REG as a save-restore register, and return it. */ | |
722 | static struct m32c_reg * | |
723 | mark_save_restore (struct m32c_reg *reg) | |
724 | { | |
725 | reg->save_restore_p = 1; | |
726 | return reg; | |
727 | } | |
728 | ||
729 | ||
730 | #define FLAGBIT_B 0x0010 | |
731 | #define FLAGBIT_U 0x0080 | |
732 | ||
733 | /* Handy macros for declaring registers. These all evaluate to | |
734 | pointers to the register declared. Macros that define two | |
735 | registers evaluate to a pointer to the first. */ | |
736 | ||
737 | /* A raw register named NAME, with type TYPE and sim number SIM_NUM. */ | |
738 | #define R(name, type, sim_num) \ | |
739 | (add_reg (arch, (name), (type), (sim_num), \ | |
740 | m32c_raw_read, m32c_raw_write, NULL, NULL, 0)) | |
741 | ||
742 | /* The simulator register number for a raw register named NAME. */ | |
743 | #define SIM(name) (m32c_sim_reg_ ## name) | |
744 | ||
745 | /* A raw unsigned 16-bit data register named NAME. | |
746 | NAME should be an identifier, not a string. */ | |
747 | #define R16U(name) \ | |
748 | (R(#name, tdep->uint16, SIM (name))) | |
749 | ||
750 | /* A raw data address register named NAME. | |
751 | NAME should be an identifier, not a string. */ | |
752 | #define RA(name) \ | |
753 | (R(#name, tdep->data_addr_reg_type, SIM (name))) | |
754 | ||
755 | /* A raw code address register named NAME. NAME should | |
756 | be an identifier, not a string. */ | |
757 | #define RC(name) \ | |
758 | (R(#name, tdep->code_addr_reg_type, SIM (name))) | |
759 | ||
760 | /* A pair of raw registers named NAME0 and NAME1, with type TYPE. | |
761 | NAME should be an identifier, not a string. */ | |
762 | #define RP(name, type) \ | |
763 | (R(#name "0", (type), SIM (name ## 0)), \ | |
764 | R(#name "1", (type), SIM (name ## 1)) - 1) | |
765 | ||
766 | /* A raw banked general-purpose data register named NAME. | |
767 | NAME should be an identifier, not a string. */ | |
768 | #define RBD(name) \ | |
769 | (R(NULL, tdep->int16, SIM (name ## _bank0)), \ | |
770 | R(NULL, tdep->int16, SIM (name ## _bank1)) - 1) | |
771 | ||
772 | /* A raw banked data address register named NAME. | |
773 | NAME should be an identifier, not a string. */ | |
774 | #define RBA(name) \ | |
775 | (R(NULL, tdep->data_addr_reg_type, SIM (name ## _bank0)), \ | |
776 | R(NULL, tdep->data_addr_reg_type, SIM (name ## _bank1)) - 1) | |
777 | ||
778 | /* A cooked register named NAME referring to a raw banked register | |
779 | from the bank selected by the current value of FLG. RAW_PAIR | |
780 | should be a pointer to the first register in the banked pair. | |
781 | NAME must be an identifier, not a string. */ | |
782 | #define CB(name, raw_pair) \ | |
783 | (add_reg (arch, #name, (raw_pair)->type, 0, \ | |
784 | m32c_banked_read, m32c_banked_write, \ | |
785 | (raw_pair), (raw_pair + 1), FLAGBIT_B)) | |
786 | ||
787 | /* A pair of registers named NAMEH and NAMEL, of type TYPE, that | |
788 | access the top and bottom halves of the register pointed to by | |
789 | NAME. NAME should be an identifier. */ | |
790 | #define CHL(name, type) \ | |
791 | (add_reg (arch, #name "h", (type), 0, \ | |
792 | m32c_part_read, m32c_part_write, name, NULL, 1), \ | |
793 | add_reg (arch, #name "l", (type), 0, \ | |
794 | m32c_part_read, m32c_part_write, name, NULL, 0) - 1) | |
795 | ||
796 | /* A register constructed by concatenating the two registers HIGH and | |
797 | LOW, whose name is HIGHLOW and whose type is TYPE. */ | |
798 | #define CCAT(high, low, type) \ | |
799 | (add_reg (arch, #high #low, (type), 0, \ | |
800 | m32c_cat_read, m32c_cat_write, (high), (low), 0)) | |
801 | ||
802 | /* Abbreviations for marking register group membership. */ | |
803 | #define G(reg) (mark_general (reg)) | |
804 | #define S(reg) (mark_system (reg)) | |
805 | #define DMA(reg) (mark_dma (reg)) | |
806 | ||
807 | ||
808 | /* Construct the register set for ARCH. */ | |
809 | static void | |
810 | make_regs (struct gdbarch *arch) | |
811 | { | |
812 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); | |
813 | int mach = gdbarch_bfd_arch_info (arch)->mach; | |
f79b9530 DJ |
814 | int num_raw_regs; |
815 | int num_cooked_regs; | |
816 | ||
817 | struct m32c_reg *r0; | |
818 | struct m32c_reg *r1; | |
819 | struct m32c_reg *r2; | |
820 | struct m32c_reg *r3; | |
821 | struct m32c_reg *a0; | |
822 | struct m32c_reg *a1; | |
823 | struct m32c_reg *fb; | |
824 | struct m32c_reg *sb; | |
825 | struct m32c_reg *sp; | |
826 | struct m32c_reg *r0hl; | |
827 | struct m32c_reg *r1hl; | |
828 | struct m32c_reg *r2hl; | |
829 | struct m32c_reg *r3hl; | |
830 | struct m32c_reg *intbhl; | |
831 | struct m32c_reg *r2r0; | |
832 | struct m32c_reg *r3r1; | |
833 | struct m32c_reg *r3r1r2r0; | |
834 | struct m32c_reg *r3r2r1r0; | |
835 | struct m32c_reg *a1a0; | |
96309189 MS |
836 | |
837 | struct m32c_reg *raw_r0_pair = RBD (r0); | |
838 | struct m32c_reg *raw_r1_pair = RBD (r1); | |
839 | struct m32c_reg *raw_r2_pair = RBD (r2); | |
840 | struct m32c_reg *raw_r3_pair = RBD (r3); | |
841 | struct m32c_reg *raw_a0_pair = RBA (a0); | |
842 | struct m32c_reg *raw_a1_pair = RBA (a1); | |
843 | struct m32c_reg *raw_fb_pair = RBA (fb); | |
844 | ||
845 | /* sb is banked on the bfd_mach_m32c, but not on bfd_mach_m16c. | |
846 | We always declare both raw registers, and deal with the distinction | |
847 | in the pseudoregister. */ | |
848 | struct m32c_reg *raw_sb_pair = RBA (sb); | |
849 | ||
850 | struct m32c_reg *usp = S (RA (usp)); | |
851 | struct m32c_reg *isp = S (RA (isp)); | |
852 | struct m32c_reg *intb = S (RC (intb)); | |
853 | struct m32c_reg *pc = G (RC (pc)); | |
854 | struct m32c_reg *flg = G (R16U (flg)); | |
855 | ||
856 | if (mach == bfd_mach_m32c) | |
857 | { | |
858 | struct m32c_reg *svf = S (R16U (svf)); | |
859 | struct m32c_reg *svp = S (RC (svp)); | |
860 | struct m32c_reg *vct = S (RC (vct)); | |
861 | ||
862 | struct m32c_reg *dmd01 = DMA (RP (dmd, tdep->uint8)); | |
863 | struct m32c_reg *dct01 = DMA (RP (dct, tdep->uint16)); | |
864 | struct m32c_reg *drc01 = DMA (RP (drc, tdep->uint16)); | |
865 | struct m32c_reg *dma01 = DMA (RP (dma, tdep->data_addr_reg_type)); | |
866 | struct m32c_reg *dsa01 = DMA (RP (dsa, tdep->data_addr_reg_type)); | |
867 | struct m32c_reg *dra01 = DMA (RP (dra, tdep->data_addr_reg_type)); | |
868 | } | |
869 | ||
f79b9530 | 870 | num_raw_regs = tdep->num_regs; |
96309189 | 871 | |
f79b9530 DJ |
872 | r0 = G (CB (r0, raw_r0_pair)); |
873 | r1 = G (CB (r1, raw_r1_pair)); | |
874 | r2 = G (CB (r2, raw_r2_pair)); | |
875 | r3 = G (CB (r3, raw_r3_pair)); | |
876 | a0 = G (CB (a0, raw_a0_pair)); | |
877 | a1 = G (CB (a1, raw_a1_pair)); | |
878 | fb = G (CB (fb, raw_fb_pair)); | |
96309189 MS |
879 | |
880 | /* sb is banked on the bfd_mach_m32c, but not on bfd_mach_m16c. | |
881 | Specify custom read/write functions that do the right thing. */ | |
f79b9530 DJ |
882 | sb = G (add_reg (arch, "sb", raw_sb_pair->type, 0, |
883 | m32c_sb_read, m32c_sb_write, | |
884 | raw_sb_pair, raw_sb_pair + 1, 0)); | |
96309189 MS |
885 | |
886 | /* The current sp is either usp or isp, depending on the value of | |
887 | the FLG register's U bit. */ | |
f79b9530 DJ |
888 | sp = G (add_reg (arch, "sp", usp->type, 0, |
889 | m32c_banked_read, m32c_banked_write, | |
890 | isp, usp, FLAGBIT_U)); | |
96309189 | 891 | |
f79b9530 DJ |
892 | r0hl = CHL (r0, tdep->int8); |
893 | r1hl = CHL (r1, tdep->int8); | |
894 | r2hl = CHL (r2, tdep->int8); | |
895 | r3hl = CHL (r3, tdep->int8); | |
896 | intbhl = CHL (intb, tdep->int16); | |
96309189 | 897 | |
f79b9530 DJ |
898 | r2r0 = CCAT (r2, r0, tdep->int32); |
899 | r3r1 = CCAT (r3, r1, tdep->int32); | |
900 | r3r1r2r0 = CCAT (r3r1, r2r0, tdep->int64); | |
96309189 | 901 | |
f79b9530 | 902 | r3r2r1r0 |
96309189 MS |
903 | = add_reg (arch, "r3r2r1r0", tdep->int64, 0, |
904 | m32c_r3r2r1r0_read, m32c_r3r2r1r0_write, NULL, NULL, 0); | |
905 | ||
96309189 MS |
906 | if (mach == bfd_mach_m16c) |
907 | a1a0 = CCAT (a1, a0, tdep->int32); | |
908 | else | |
909 | a1a0 = NULL; | |
910 | ||
f79b9530 | 911 | num_cooked_regs = tdep->num_regs - num_raw_regs; |
96309189 MS |
912 | |
913 | tdep->pc = pc; | |
914 | tdep->flg = flg; | |
915 | tdep->r0 = r0; | |
916 | tdep->r1 = r1; | |
917 | tdep->r2 = r2; | |
918 | tdep->r3 = r3; | |
919 | tdep->r2r0 = r2r0; | |
920 | tdep->r3r2r1r0 = r3r2r1r0; | |
921 | tdep->r3r1r2r0 = r3r1r2r0; | |
922 | tdep->a0 = a0; | |
923 | tdep->a1 = a1; | |
924 | tdep->sb = sb; | |
925 | tdep->fb = fb; | |
926 | tdep->sp = sp; | |
927 | ||
928 | /* Set up the DWARF register table. */ | |
929 | memset (tdep->dwarf_regs, 0, sizeof (tdep->dwarf_regs)); | |
930 | set_dwarf_regnum (r0hl + 1, 0x01); | |
931 | set_dwarf_regnum (r0hl + 0, 0x02); | |
932 | set_dwarf_regnum (r1hl + 1, 0x03); | |
933 | set_dwarf_regnum (r1hl + 0, 0x04); | |
934 | set_dwarf_regnum (r0, 0x05); | |
935 | set_dwarf_regnum (r1, 0x06); | |
936 | set_dwarf_regnum (r2, 0x07); | |
937 | set_dwarf_regnum (r3, 0x08); | |
938 | set_dwarf_regnum (a0, 0x09); | |
939 | set_dwarf_regnum (a1, 0x0a); | |
940 | set_dwarf_regnum (fb, 0x0b); | |
941 | set_dwarf_regnum (sp, 0x0c); | |
942 | set_dwarf_regnum (pc, 0x0d); /* GCC's invention */ | |
943 | set_dwarf_regnum (sb, 0x13); | |
944 | set_dwarf_regnum (r2r0, 0x15); | |
945 | set_dwarf_regnum (r3r1, 0x16); | |
946 | if (a1a0) | |
947 | set_dwarf_regnum (a1a0, 0x17); | |
948 | ||
949 | /* Enumerate the save/restore register group. | |
950 | ||
951 | The regcache_save and regcache_restore functions apply their read | |
952 | function to each register in this group. | |
953 | ||
954 | Since frame_pop supplies frame_unwind_register as its read | |
955 | function, the registers meaningful to the Dwarf unwinder need to | |
956 | be in this group. | |
957 | ||
958 | On the other hand, when we make inferior calls, save_inferior_status | |
959 | and restore_inferior_status use them to preserve the current register | |
960 | values across the inferior call. For this, you'd kind of like to | |
961 | preserve all the raw registers, to protect the interrupted code from | |
962 | any sort of bank switching the callee might have done. But we handle | |
963 | those cases so badly anyway --- for example, it matters whether we | |
964 | restore FLG before or after we restore the general-purpose registers, | |
965 | but there's no way to express that --- that it isn't worth worrying | |
966 | about. | |
967 | ||
968 | We omit control registers like inthl: if you call a function that | |
969 | changes those, it's probably because you wanted that change to be | |
970 | visible to the interrupted code. */ | |
971 | mark_save_restore (r0); | |
972 | mark_save_restore (r1); | |
973 | mark_save_restore (r2); | |
974 | mark_save_restore (r3); | |
975 | mark_save_restore (a0); | |
976 | mark_save_restore (a1); | |
977 | mark_save_restore (sb); | |
978 | mark_save_restore (fb); | |
979 | mark_save_restore (sp); | |
980 | mark_save_restore (pc); | |
981 | mark_save_restore (flg); | |
982 | ||
983 | set_gdbarch_num_regs (arch, num_raw_regs); | |
984 | set_gdbarch_num_pseudo_regs (arch, num_cooked_regs); | |
985 | set_gdbarch_pc_regnum (arch, pc->num); | |
986 | set_gdbarch_sp_regnum (arch, sp->num); | |
987 | set_gdbarch_register_name (arch, m32c_register_name); | |
988 | set_gdbarch_register_type (arch, m32c_register_type); | |
989 | set_gdbarch_pseudo_register_read (arch, m32c_pseudo_register_read); | |
990 | set_gdbarch_pseudo_register_write (arch, m32c_pseudo_register_write); | |
991 | set_gdbarch_register_sim_regno (arch, m32c_register_sim_regno); | |
992 | set_gdbarch_stab_reg_to_regnum (arch, m32c_debug_info_reg_to_regnum); | |
96309189 MS |
993 | set_gdbarch_dwarf2_reg_to_regnum (arch, m32c_debug_info_reg_to_regnum); |
994 | set_gdbarch_register_reggroup_p (arch, m32c_register_reggroup_p); | |
995 | ||
996 | reggroup_add (arch, general_reggroup); | |
997 | reggroup_add (arch, all_reggroup); | |
998 | reggroup_add (arch, save_reggroup); | |
999 | reggroup_add (arch, restore_reggroup); | |
1000 | reggroup_add (arch, system_reggroup); | |
1001 | reggroup_add (arch, m32c_dma_reggroup); | |
1002 | } | |
1003 | ||
1004 | ||
1005 | \f | |
1006 | /* Breakpoints. */ | |
1007 | ||
1008 | static const unsigned char * | |
67d57894 | 1009 | m32c_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) |
96309189 MS |
1010 | { |
1011 | static unsigned char break_insn[] = { 0x00 }; /* brk */ | |
1012 | ||
1013 | *len = sizeof (break_insn); | |
1014 | return break_insn; | |
1015 | } | |
1016 | ||
1017 | ||
1018 | \f | |
1019 | /* Prologue analysis. */ | |
1020 | ||
1021 | struct m32c_prologue | |
1022 | { | |
1023 | /* For consistency with the DWARF 2 .debug_frame info generated by | |
1024 | GCC, a frame's CFA is the address immediately after the saved | |
1025 | return address. */ | |
1026 | ||
1027 | /* The architecture for which we generated this prologue info. */ | |
1028 | struct gdbarch *arch; | |
1029 | ||
1030 | enum { | |
1031 | /* This function uses a frame pointer. */ | |
1032 | prologue_with_frame_ptr, | |
1033 | ||
1034 | /* This function has no frame pointer. */ | |
1035 | prologue_sans_frame_ptr, | |
1036 | ||
1037 | /* This function sets up the stack, so its frame is the first | |
1038 | frame on the stack. */ | |
1039 | prologue_first_frame | |
1040 | ||
1041 | } kind; | |
1042 | ||
1043 | /* If KIND is prologue_with_frame_ptr, this is the offset from the | |
1044 | CFA to where the frame pointer points. This is always zero or | |
1045 | negative. */ | |
1046 | LONGEST frame_ptr_offset; | |
1047 | ||
1048 | /* If KIND is prologue_sans_frame_ptr, the offset from the CFA to | |
1049 | the stack pointer --- always zero or negative. | |
1050 | ||
1051 | Calling this a "size" is a bit misleading, but given that the | |
1052 | stack grows downwards, using offsets for everything keeps one | |
1053 | from going completely sign-crazy: you never change anything's | |
1054 | sign for an ADD instruction; always change the second operand's | |
1055 | sign for a SUB instruction; and everything takes care of | |
1056 | itself. | |
1057 | ||
1058 | Functions that use alloca don't have a constant frame size. But | |
1059 | they always have frame pointers, so we must use that to find the | |
1060 | CFA (and perhaps to unwind the stack pointer). */ | |
1061 | LONGEST frame_size; | |
1062 | ||
1063 | /* The address of the first instruction at which the frame has been | |
1064 | set up and the arguments are where the debug info says they are | |
1065 | --- as best as we can tell. */ | |
1066 | CORE_ADDR prologue_end; | |
1067 | ||
1068 | /* reg_offset[R] is the offset from the CFA at which register R is | |
1069 | saved, or 1 if register R has not been saved. (Real values are | |
1070 | always zero or negative.) */ | |
1071 | LONGEST reg_offset[M32C_MAX_NUM_REGS]; | |
1072 | }; | |
1073 | ||
1074 | ||
1075 | /* The longest I've seen, anyway. */ | |
1076 | #define M32C_MAX_INSN_LEN (9) | |
1077 | ||
1078 | /* Processor state, for the prologue analyzer. */ | |
1079 | struct m32c_pv_state | |
1080 | { | |
1081 | struct gdbarch *arch; | |
1082 | pv_t r0, r1, r2, r3; | |
1083 | pv_t a0, a1; | |
1084 | pv_t sb, fb, sp; | |
1085 | pv_t pc; | |
1086 | struct pv_area *stack; | |
1087 | ||
1088 | /* Bytes from the current PC, the address they were read from, | |
1089 | and the address of the next unconsumed byte. */ | |
1090 | gdb_byte insn[M32C_MAX_INSN_LEN]; | |
1091 | CORE_ADDR scan_pc, next_addr; | |
1092 | }; | |
1093 | ||
1094 | ||
1095 | /* Push VALUE on STATE's stack, occupying SIZE bytes. Return zero if | |
1096 | all went well, or non-zero if simulating the action would trash our | |
1097 | state. */ | |
1098 | static int | |
1099 | m32c_pv_push (struct m32c_pv_state *state, pv_t value, int size) | |
1100 | { | |
1101 | if (pv_area_store_would_trash (state->stack, state->sp)) | |
1102 | return 1; | |
1103 | ||
1104 | state->sp = pv_add_constant (state->sp, -size); | |
1105 | pv_area_store (state->stack, state->sp, size, value); | |
1106 | ||
1107 | return 0; | |
1108 | } | |
1109 | ||
1110 | ||
1111 | /* A source or destination location for an m16c or m32c | |
1112 | instruction. */ | |
1113 | struct srcdest | |
1114 | { | |
1115 | /* If srcdest_reg, the location is a register pointed to by REG. | |
1116 | If srcdest_partial_reg, the location is part of a register pointed | |
1117 | to by REG. We don't try to handle this too well. | |
1118 | If srcdest_mem, the location is memory whose address is ADDR. */ | |
1119 | enum { srcdest_reg, srcdest_partial_reg, srcdest_mem } kind; | |
1120 | pv_t *reg, addr; | |
1121 | }; | |
1122 | ||
1123 | ||
1124 | /* Return the SIZE-byte value at LOC in STATE. */ | |
1125 | static pv_t | |
1126 | m32c_srcdest_fetch (struct m32c_pv_state *state, struct srcdest loc, int size) | |
1127 | { | |
1128 | if (loc.kind == srcdest_mem) | |
1129 | return pv_area_fetch (state->stack, loc.addr, size); | |
1130 | else if (loc.kind == srcdest_partial_reg) | |
1131 | return pv_unknown (); | |
1132 | else | |
1133 | return *loc.reg; | |
1134 | } | |
1135 | ||
1136 | ||
1137 | /* Write VALUE, a SIZE-byte value, to LOC in STATE. Return zero if | |
1138 | all went well, or non-zero if simulating the store would trash our | |
1139 | state. */ | |
1140 | static int | |
1141 | m32c_srcdest_store (struct m32c_pv_state *state, struct srcdest loc, | |
1142 | pv_t value, int size) | |
1143 | { | |
1144 | if (loc.kind == srcdest_mem) | |
1145 | { | |
1146 | if (pv_area_store_would_trash (state->stack, loc.addr)) | |
1147 | return 1; | |
1148 | pv_area_store (state->stack, loc.addr, size, value); | |
1149 | } | |
1150 | else if (loc.kind == srcdest_partial_reg) | |
1151 | *loc.reg = pv_unknown (); | |
1152 | else | |
1153 | *loc.reg = value; | |
1154 | ||
1155 | return 0; | |
1156 | } | |
1157 | ||
1158 | ||
1159 | static int | |
1160 | m32c_sign_ext (int v, int bits) | |
1161 | { | |
1162 | int mask = 1 << (bits - 1); | |
1163 | return (v ^ mask) - mask; | |
1164 | } | |
1165 | ||
1166 | static unsigned int | |
1167 | m32c_next_byte (struct m32c_pv_state *st) | |
1168 | { | |
1169 | gdb_assert (st->next_addr - st->scan_pc < sizeof (st->insn)); | |
1170 | return st->insn[st->next_addr++ - st->scan_pc]; | |
1171 | } | |
1172 | ||
1173 | static int | |
1174 | m32c_udisp8 (struct m32c_pv_state *st) | |
1175 | { | |
1176 | return m32c_next_byte (st); | |
1177 | } | |
1178 | ||
1179 | ||
1180 | static int | |
1181 | m32c_sdisp8 (struct m32c_pv_state *st) | |
1182 | { | |
1183 | return m32c_sign_ext (m32c_next_byte (st), 8); | |
1184 | } | |
1185 | ||
1186 | ||
1187 | static int | |
1188 | m32c_udisp16 (struct m32c_pv_state *st) | |
1189 | { | |
1190 | int low = m32c_next_byte (st); | |
1191 | int high = m32c_next_byte (st); | |
1192 | ||
1193 | return low + (high << 8); | |
1194 | } | |
1195 | ||
1196 | ||
1197 | static int | |
1198 | m32c_sdisp16 (struct m32c_pv_state *st) | |
1199 | { | |
1200 | int low = m32c_next_byte (st); | |
1201 | int high = m32c_next_byte (st); | |
1202 | ||
1203 | return m32c_sign_ext (low + (high << 8), 16); | |
1204 | } | |
1205 | ||
1206 | ||
1207 | static int | |
1208 | m32c_udisp24 (struct m32c_pv_state *st) | |
1209 | { | |
1210 | int low = m32c_next_byte (st); | |
1211 | int mid = m32c_next_byte (st); | |
1212 | int high = m32c_next_byte (st); | |
1213 | ||
1214 | return low + (mid << 8) + (high << 16); | |
1215 | } | |
1216 | ||
1217 | ||
1218 | /* Extract the 'source' field from an m32c MOV.size:G-format instruction. */ | |
1219 | static int | |
1220 | m32c_get_src23 (unsigned char *i) | |
1221 | { | |
1222 | return (((i[0] & 0x70) >> 2) | |
1223 | | ((i[1] & 0x30) >> 4)); | |
1224 | } | |
1225 | ||
1226 | ||
1227 | /* Extract the 'dest' field from an m32c MOV.size:G-format instruction. */ | |
1228 | static int | |
1229 | m32c_get_dest23 (unsigned char *i) | |
1230 | { | |
1231 | return (((i[0] & 0x0e) << 1) | |
1232 | | ((i[1] & 0xc0) >> 6)); | |
1233 | } | |
1234 | ||
1235 | ||
1236 | static struct srcdest | |
1237 | m32c_decode_srcdest4 (struct m32c_pv_state *st, | |
1238 | int code, int size) | |
1239 | { | |
1240 | struct srcdest sd; | |
1241 | ||
1242 | if (code < 6) | |
1243 | sd.kind = (size == 2 ? srcdest_reg : srcdest_partial_reg); | |
1244 | else | |
1245 | sd.kind = srcdest_mem; | |
1246 | ||
d56874a7 DD |
1247 | sd.addr = pv_unknown (); |
1248 | sd.reg = 0; | |
1249 | ||
96309189 MS |
1250 | switch (code) |
1251 | { | |
1252 | case 0x0: sd.reg = (size == 1 ? &st->r0 : &st->r0); break; | |
1253 | case 0x1: sd.reg = (size == 1 ? &st->r0 : &st->r1); break; | |
1254 | case 0x2: sd.reg = (size == 1 ? &st->r1 : &st->r2); break; | |
1255 | case 0x3: sd.reg = (size == 1 ? &st->r1 : &st->r3); break; | |
1256 | ||
1257 | case 0x4: sd.reg = &st->a0; break; | |
1258 | case 0x5: sd.reg = &st->a1; break; | |
1259 | ||
1260 | case 0x6: sd.addr = st->a0; break; | |
1261 | case 0x7: sd.addr = st->a1; break; | |
1262 | ||
1263 | case 0x8: sd.addr = pv_add_constant (st->a0, m32c_udisp8 (st)); break; | |
1264 | case 0x9: sd.addr = pv_add_constant (st->a1, m32c_udisp8 (st)); break; | |
1265 | case 0xa: sd.addr = pv_add_constant (st->sb, m32c_udisp8 (st)); break; | |
1266 | case 0xb: sd.addr = pv_add_constant (st->fb, m32c_sdisp8 (st)); break; | |
1267 | ||
1268 | case 0xc: sd.addr = pv_add_constant (st->a0, m32c_udisp16 (st)); break; | |
1269 | case 0xd: sd.addr = pv_add_constant (st->a1, m32c_udisp16 (st)); break; | |
1270 | case 0xe: sd.addr = pv_add_constant (st->sb, m32c_udisp16 (st)); break; | |
1271 | case 0xf: sd.addr = pv_constant (m32c_udisp16 (st)); break; | |
1272 | ||
1273 | default: | |
f3574227 | 1274 | gdb_assert_not_reached ("unexpected srcdest4"); |
96309189 MS |
1275 | } |
1276 | ||
1277 | return sd; | |
1278 | } | |
1279 | ||
1280 | ||
1281 | static struct srcdest | |
1282 | m32c_decode_sd23 (struct m32c_pv_state *st, int code, int size, int ind) | |
1283 | { | |
1284 | struct srcdest sd; | |
1285 | ||
d56874a7 DD |
1286 | sd.addr = pv_unknown (); |
1287 | sd.reg = 0; | |
1288 | ||
96309189 MS |
1289 | switch (code) |
1290 | { | |
1291 | case 0x12: | |
1292 | case 0x13: | |
1293 | case 0x10: | |
1294 | case 0x11: | |
1295 | sd.kind = (size == 1) ? srcdest_partial_reg : srcdest_reg; | |
1296 | break; | |
1297 | ||
1298 | case 0x02: | |
1299 | case 0x03: | |
1300 | sd.kind = (size == 4) ? srcdest_reg : srcdest_partial_reg; | |
1301 | break; | |
1302 | ||
1303 | default: | |
1304 | sd.kind = srcdest_mem; | |
1305 | break; | |
1306 | ||
1307 | } | |
1308 | ||
1309 | switch (code) | |
1310 | { | |
1311 | case 0x12: sd.reg = &st->r0; break; | |
1312 | case 0x13: sd.reg = &st->r1; break; | |
1313 | case 0x10: sd.reg = ((size == 1) ? &st->r0 : &st->r2); break; | |
1314 | case 0x11: sd.reg = ((size == 1) ? &st->r1 : &st->r3); break; | |
1315 | case 0x02: sd.reg = &st->a0; break; | |
1316 | case 0x03: sd.reg = &st->a1; break; | |
1317 | ||
1318 | case 0x00: sd.addr = st->a0; break; | |
1319 | case 0x01: sd.addr = st->a1; break; | |
1320 | case 0x04: sd.addr = pv_add_constant (st->a0, m32c_udisp8 (st)); break; | |
1321 | case 0x05: sd.addr = pv_add_constant (st->a1, m32c_udisp8 (st)); break; | |
1322 | case 0x06: sd.addr = pv_add_constant (st->sb, m32c_udisp8 (st)); break; | |
1323 | case 0x07: sd.addr = pv_add_constant (st->fb, m32c_sdisp8 (st)); break; | |
1324 | case 0x08: sd.addr = pv_add_constant (st->a0, m32c_udisp16 (st)); break; | |
1325 | case 0x09: sd.addr = pv_add_constant (st->a1, m32c_udisp16 (st)); break; | |
1326 | case 0x0a: sd.addr = pv_add_constant (st->sb, m32c_udisp16 (st)); break; | |
1327 | case 0x0b: sd.addr = pv_add_constant (st->fb, m32c_sdisp16 (st)); break; | |
1328 | case 0x0c: sd.addr = pv_add_constant (st->a0, m32c_udisp24 (st)); break; | |
1329 | case 0x0d: sd.addr = pv_add_constant (st->a1, m32c_udisp24 (st)); break; | |
1330 | case 0x0f: sd.addr = pv_constant (m32c_udisp16 (st)); break; | |
1331 | case 0x0e: sd.addr = pv_constant (m32c_udisp24 (st)); break; | |
1332 | default: | |
f3574227 | 1333 | gdb_assert_not_reached ("unexpected sd23"); |
96309189 MS |
1334 | } |
1335 | ||
1336 | if (ind) | |
1337 | { | |
1338 | sd.addr = m32c_srcdest_fetch (st, sd, 4); | |
1339 | sd.kind = srcdest_mem; | |
1340 | } | |
1341 | ||
1342 | return sd; | |
1343 | } | |
1344 | ||
1345 | ||
1346 | /* The r16c and r32c machines have instructions with similar | |
1347 | semantics, but completely different machine language encodings. So | |
1348 | we break out the semantics into their own functions, and leave | |
1349 | machine-specific decoding in m32c_analyze_prologue. | |
1350 | ||
1351 | The following functions all expect their arguments already decoded, | |
1352 | and they all return zero if analysis should continue past this | |
1353 | instruction, or non-zero if analysis should stop. */ | |
1354 | ||
1355 | ||
1356 | /* Simulate an 'enter SIZE' instruction in STATE. */ | |
1357 | static int | |
1358 | m32c_pv_enter (struct m32c_pv_state *state, int size) | |
1359 | { | |
1360 | struct gdbarch_tdep *tdep = gdbarch_tdep (state->arch); | |
1361 | ||
1362 | /* If simulating this store would require us to forget | |
1363 | everything we know about the stack frame in the name of | |
1364 | accuracy, it would be better to just quit now. */ | |
1365 | if (pv_area_store_would_trash (state->stack, state->sp)) | |
1366 | return 1; | |
1367 | ||
1368 | if (m32c_pv_push (state, state->fb, tdep->push_addr_bytes)) | |
1369 | return 1; | |
1370 | state->fb = state->sp; | |
1371 | state->sp = pv_add_constant (state->sp, -size); | |
1372 | ||
1373 | return 0; | |
1374 | } | |
1375 | ||
1376 | ||
1377 | static int | |
1378 | m32c_pv_pushm_one (struct m32c_pv_state *state, pv_t reg, | |
1379 | int bit, int src, int size) | |
1380 | { | |
1381 | if (bit & src) | |
1382 | { | |
1383 | if (m32c_pv_push (state, reg, size)) | |
1384 | return 1; | |
1385 | } | |
1386 | ||
1387 | return 0; | |
1388 | } | |
1389 | ||
1390 | ||
1391 | /* Simulate a 'pushm SRC' instruction in STATE. */ | |
1392 | static int | |
1393 | m32c_pv_pushm (struct m32c_pv_state *state, int src) | |
1394 | { | |
1395 | struct gdbarch_tdep *tdep = gdbarch_tdep (state->arch); | |
1396 | ||
1397 | /* The bits in SRC indicating which registers to save are: | |
1398 | r0 r1 r2 r3 a0 a1 sb fb */ | |
1399 | return | |
1400 | ( m32c_pv_pushm_one (state, state->fb, 0x01, src, tdep->push_addr_bytes) | |
1401 | || m32c_pv_pushm_one (state, state->sb, 0x02, src, tdep->push_addr_bytes) | |
1402 | || m32c_pv_pushm_one (state, state->a1, 0x04, src, tdep->push_addr_bytes) | |
1403 | || m32c_pv_pushm_one (state, state->a0, 0x08, src, tdep->push_addr_bytes) | |
1404 | || m32c_pv_pushm_one (state, state->r3, 0x10, src, 2) | |
1405 | || m32c_pv_pushm_one (state, state->r2, 0x20, src, 2) | |
1406 | || m32c_pv_pushm_one (state, state->r1, 0x40, src, 2) | |
1407 | || m32c_pv_pushm_one (state, state->r0, 0x80, src, 2)); | |
1408 | } | |
1409 | ||
1410 | /* Return non-zero if VALUE is the first incoming argument register. */ | |
1411 | ||
1412 | static int | |
1413 | m32c_is_1st_arg_reg (struct m32c_pv_state *state, pv_t value) | |
1414 | { | |
1415 | struct gdbarch_tdep *tdep = gdbarch_tdep (state->arch); | |
1416 | return (value.kind == pvk_register | |
1417 | && (gdbarch_bfd_arch_info (state->arch)->mach == bfd_mach_m16c | |
1418 | ? (value.reg == tdep->r1->num) | |
1419 | : (value.reg == tdep->r0->num)) | |
1420 | && value.k == 0); | |
1421 | } | |
1422 | ||
1423 | /* Return non-zero if VALUE is an incoming argument register. */ | |
1424 | ||
1425 | static int | |
1426 | m32c_is_arg_reg (struct m32c_pv_state *state, pv_t value) | |
1427 | { | |
1428 | struct gdbarch_tdep *tdep = gdbarch_tdep (state->arch); | |
1429 | return (value.kind == pvk_register | |
1430 | && (gdbarch_bfd_arch_info (state->arch)->mach == bfd_mach_m16c | |
1431 | ? (value.reg == tdep->r1->num || value.reg == tdep->r2->num) | |
1432 | : (value.reg == tdep->r0->num)) | |
1433 | && value.k == 0); | |
1434 | } | |
1435 | ||
1436 | /* Return non-zero if a store of VALUE to LOC is probably spilling an | |
1437 | argument register to its stack slot in STATE. Such instructions | |
1438 | should be included in the prologue, if possible. | |
1439 | ||
1440 | The store is a spill if: | |
1441 | - the value being stored is the original value of an argument register; | |
1442 | - the value has not already been stored somewhere in STACK; and | |
1443 | - LOC is a stack slot (e.g., a memory location whose address is | |
1444 | relative to the original value of the SP). */ | |
1445 | ||
1446 | static int | |
1447 | m32c_is_arg_spill (struct m32c_pv_state *st, | |
1448 | struct srcdest loc, | |
1449 | pv_t value) | |
1450 | { | |
1451 | struct gdbarch_tdep *tdep = gdbarch_tdep (st->arch); | |
1452 | ||
1453 | return (m32c_is_arg_reg (st, value) | |
1454 | && loc.kind == srcdest_mem | |
1455 | && pv_is_register (loc.addr, tdep->sp->num) | |
1456 | && ! pv_area_find_reg (st->stack, st->arch, value.reg, 0)); | |
1457 | } | |
1458 | ||
1459 | /* Return non-zero if a store of VALUE to LOC is probably | |
1460 | copying the struct return address into an address register | |
1461 | for immediate use. This is basically a "spill" into the | |
1462 | address register, instead of onto the stack. | |
1463 | ||
1464 | The prerequisites are: | |
1465 | - value being stored is original value of the FIRST arg register; | |
1466 | - value has not already been stored on stack; and | |
1467 | - LOC is an address register (a0 or a1). */ | |
1468 | ||
1469 | static int | |
1470 | m32c_is_struct_return (struct m32c_pv_state *st, | |
1471 | struct srcdest loc, | |
1472 | pv_t value) | |
1473 | { | |
1474 | struct gdbarch_tdep *tdep = gdbarch_tdep (st->arch); | |
1475 | ||
1476 | return (m32c_is_1st_arg_reg (st, value) | |
1477 | && !pv_area_find_reg (st->stack, st->arch, value.reg, 0) | |
1478 | && loc.kind == srcdest_reg | |
1479 | && (pv_is_register (*loc.reg, tdep->a0->num) | |
1480 | || pv_is_register (*loc.reg, tdep->a1->num))); | |
1481 | } | |
1482 | ||
1483 | /* Return non-zero if a 'pushm' saving the registers indicated by SRC | |
1484 | was a register save: | |
1485 | - all the named registers should have their original values, and | |
1486 | - the stack pointer should be at a constant offset from the | |
1487 | original stack pointer. */ | |
1488 | static int | |
1489 | m32c_pushm_is_reg_save (struct m32c_pv_state *st, int src) | |
1490 | { | |
1491 | struct gdbarch_tdep *tdep = gdbarch_tdep (st->arch); | |
1492 | /* The bits in SRC indicating which registers to save are: | |
1493 | r0 r1 r2 r3 a0 a1 sb fb */ | |
1494 | return | |
1495 | (pv_is_register (st->sp, tdep->sp->num) | |
1496 | && (! (src & 0x01) || pv_is_register_k (st->fb, tdep->fb->num, 0)) | |
1497 | && (! (src & 0x02) || pv_is_register_k (st->sb, tdep->sb->num, 0)) | |
1498 | && (! (src & 0x04) || pv_is_register_k (st->a1, tdep->a1->num, 0)) | |
1499 | && (! (src & 0x08) || pv_is_register_k (st->a0, tdep->a0->num, 0)) | |
1500 | && (! (src & 0x10) || pv_is_register_k (st->r3, tdep->r3->num, 0)) | |
1501 | && (! (src & 0x20) || pv_is_register_k (st->r2, tdep->r2->num, 0)) | |
1502 | && (! (src & 0x40) || pv_is_register_k (st->r1, tdep->r1->num, 0)) | |
1503 | && (! (src & 0x80) || pv_is_register_k (st->r0, tdep->r0->num, 0))); | |
1504 | } | |
1505 | ||
1506 | ||
1507 | /* Function for finding saved registers in a 'struct pv_area'; we pass | |
1508 | this to pv_area_scan. | |
1509 | ||
1510 | If VALUE is a saved register, ADDR says it was saved at a constant | |
1511 | offset from the frame base, and SIZE indicates that the whole | |
1512 | register was saved, record its offset in RESULT_UNTYPED. */ | |
1513 | static void | |
1514 | check_for_saved (void *prologue_untyped, pv_t addr, CORE_ADDR size, pv_t value) | |
1515 | { | |
1516 | struct m32c_prologue *prologue = (struct m32c_prologue *) prologue_untyped; | |
1517 | struct gdbarch *arch = prologue->arch; | |
1518 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); | |
1519 | ||
1520 | /* Is this the unchanged value of some register being saved on the | |
1521 | stack? */ | |
1522 | if (value.kind == pvk_register | |
1523 | && value.k == 0 | |
1524 | && pv_is_register (addr, tdep->sp->num)) | |
1525 | { | |
1526 | /* Some registers require special handling: they're saved as a | |
1527 | larger value than the register itself. */ | |
1528 | CORE_ADDR saved_size = register_size (arch, value.reg); | |
1529 | ||
1530 | if (value.reg == tdep->pc->num) | |
1531 | saved_size = tdep->ret_addr_bytes; | |
7b9ee6a8 | 1532 | else if (register_type (arch, value.reg) |
96309189 MS |
1533 | == tdep->data_addr_reg_type) |
1534 | saved_size = tdep->push_addr_bytes; | |
1535 | ||
1536 | if (size == saved_size) | |
1537 | { | |
1538 | /* Find which end of the saved value corresponds to our | |
1539 | register. */ | |
1540 | if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG) | |
1541 | prologue->reg_offset[value.reg] | |
1542 | = (addr.k + saved_size - register_size (arch, value.reg)); | |
1543 | else | |
1544 | prologue->reg_offset[value.reg] = addr.k; | |
1545 | } | |
1546 | } | |
1547 | } | |
1548 | ||
1549 | ||
1550 | /* Analyze the function prologue for ARCH at START, going no further | |
1551 | than LIMIT, and place a description of what we found in | |
1552 | PROLOGUE. */ | |
63807e1d | 1553 | static void |
96309189 MS |
1554 | m32c_analyze_prologue (struct gdbarch *arch, |
1555 | CORE_ADDR start, CORE_ADDR limit, | |
1556 | struct m32c_prologue *prologue) | |
1557 | { | |
1558 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); | |
1559 | unsigned long mach = gdbarch_bfd_arch_info (arch)->mach; | |
1560 | CORE_ADDR after_last_frame_related_insn; | |
1561 | struct cleanup *back_to; | |
1562 | struct m32c_pv_state st; | |
1563 | ||
1564 | st.arch = arch; | |
1565 | st.r0 = pv_register (tdep->r0->num, 0); | |
1566 | st.r1 = pv_register (tdep->r1->num, 0); | |
1567 | st.r2 = pv_register (tdep->r2->num, 0); | |
1568 | st.r3 = pv_register (tdep->r3->num, 0); | |
1569 | st.a0 = pv_register (tdep->a0->num, 0); | |
1570 | st.a1 = pv_register (tdep->a1->num, 0); | |
1571 | st.sb = pv_register (tdep->sb->num, 0); | |
1572 | st.fb = pv_register (tdep->fb->num, 0); | |
1573 | st.sp = pv_register (tdep->sp->num, 0); | |
1574 | st.pc = pv_register (tdep->pc->num, 0); | |
55f960e1 | 1575 | st.stack = make_pv_area (tdep->sp->num, gdbarch_addr_bit (arch)); |
96309189 MS |
1576 | back_to = make_cleanup_free_pv_area (st.stack); |
1577 | ||
1578 | /* Record that the call instruction has saved the return address on | |
1579 | the stack. */ | |
1580 | m32c_pv_push (&st, st.pc, tdep->ret_addr_bytes); | |
1581 | ||
1582 | memset (prologue, 0, sizeof (*prologue)); | |
1583 | prologue->arch = arch; | |
1584 | { | |
1585 | int i; | |
1586 | for (i = 0; i < M32C_MAX_NUM_REGS; i++) | |
1587 | prologue->reg_offset[i] = 1; | |
1588 | } | |
1589 | ||
1590 | st.scan_pc = after_last_frame_related_insn = start; | |
1591 | ||
1592 | while (st.scan_pc < limit) | |
1593 | { | |
1594 | pv_t pre_insn_fb = st.fb; | |
1595 | pv_t pre_insn_sp = st.sp; | |
1596 | ||
1597 | /* In theory we could get in trouble by trying to read ahead | |
1598 | here, when we only know we're expecting one byte. In | |
1599 | practice I doubt anyone will care, and it makes the rest of | |
1600 | the code easier. */ | |
1601 | if (target_read_memory (st.scan_pc, st.insn, sizeof (st.insn))) | |
1602 | /* If we can't fetch the instruction from memory, stop here | |
1603 | and hope for the best. */ | |
1604 | break; | |
1605 | st.next_addr = st.scan_pc; | |
1606 | ||
1607 | /* The assembly instructions are written as they appear in the | |
1608 | section of the processor manuals that describe the | |
1609 | instruction encodings. | |
1610 | ||
1611 | When a single assembly language instruction has several | |
1612 | different machine-language encodings, the manual | |
1613 | distinguishes them by a number in parens, before the | |
1614 | mnemonic. Those numbers are included, as well. | |
1615 | ||
1616 | The srcdest decoding instructions have the same names as the | |
1617 | analogous functions in the simulator. */ | |
1618 | if (mach == bfd_mach_m16c) | |
1619 | { | |
1620 | /* (1) ENTER #imm8 */ | |
1621 | if (st.insn[0] == 0x7c && st.insn[1] == 0xf2) | |
1622 | { | |
1623 | if (m32c_pv_enter (&st, st.insn[2])) | |
1624 | break; | |
1625 | st.next_addr += 3; | |
1626 | } | |
1627 | /* (1) PUSHM src */ | |
1628 | else if (st.insn[0] == 0xec) | |
1629 | { | |
1630 | int src = st.insn[1]; | |
1631 | if (m32c_pv_pushm (&st, src)) | |
1632 | break; | |
1633 | st.next_addr += 2; | |
1634 | ||
1635 | if (m32c_pushm_is_reg_save (&st, src)) | |
1636 | after_last_frame_related_insn = st.next_addr; | |
1637 | } | |
1638 | ||
1639 | /* (6) MOV.size:G src, dest */ | |
1640 | else if ((st.insn[0] & 0xfe) == 0x72) | |
1641 | { | |
1642 | int size = (st.insn[0] & 0x01) ? 2 : 1; | |
f79b9530 DJ |
1643 | struct srcdest src; |
1644 | struct srcdest dest; | |
1645 | pv_t src_value; | |
96309189 MS |
1646 | st.next_addr += 2; |
1647 | ||
f79b9530 | 1648 | src |
96309189 | 1649 | = m32c_decode_srcdest4 (&st, (st.insn[1] >> 4) & 0xf, size); |
f79b9530 | 1650 | dest |
96309189 | 1651 | = m32c_decode_srcdest4 (&st, st.insn[1] & 0xf, size); |
f79b9530 | 1652 | src_value = m32c_srcdest_fetch (&st, src, size); |
96309189 MS |
1653 | |
1654 | if (m32c_is_arg_spill (&st, dest, src_value)) | |
1655 | after_last_frame_related_insn = st.next_addr; | |
1656 | else if (m32c_is_struct_return (&st, dest, src_value)) | |
1657 | after_last_frame_related_insn = st.next_addr; | |
1658 | ||
1659 | if (m32c_srcdest_store (&st, dest, src_value, size)) | |
1660 | break; | |
1661 | } | |
1662 | ||
1663 | /* (1) LDC #IMM16, sp */ | |
1664 | else if (st.insn[0] == 0xeb | |
1665 | && st.insn[1] == 0x50) | |
1666 | { | |
1667 | st.next_addr += 2; | |
1668 | st.sp = pv_constant (m32c_udisp16 (&st)); | |
1669 | } | |
1670 | ||
1671 | else | |
1672 | /* We've hit some instruction we don't know how to simulate. | |
1673 | Strictly speaking, we should set every value we're | |
1674 | tracking to "unknown". But we'll be optimistic, assume | |
1675 | that we have enough information already, and stop | |
1676 | analysis here. */ | |
1677 | break; | |
1678 | } | |
1679 | else | |
1680 | { | |
1681 | int src_indirect = 0; | |
1682 | int dest_indirect = 0; | |
1683 | int i = 0; | |
1684 | ||
1685 | gdb_assert (mach == bfd_mach_m32c); | |
1686 | ||
1687 | /* Check for prefix bytes indicating indirect addressing. */ | |
1688 | if (st.insn[0] == 0x41) | |
1689 | { | |
1690 | src_indirect = 1; | |
1691 | i++; | |
1692 | } | |
1693 | else if (st.insn[0] == 0x09) | |
1694 | { | |
1695 | dest_indirect = 1; | |
1696 | i++; | |
1697 | } | |
1698 | else if (st.insn[0] == 0x49) | |
1699 | { | |
1700 | src_indirect = dest_indirect = 1; | |
1701 | i++; | |
1702 | } | |
1703 | ||
1704 | /* (1) ENTER #imm8 */ | |
1705 | if (st.insn[i] == 0xec) | |
1706 | { | |
1707 | if (m32c_pv_enter (&st, st.insn[i + 1])) | |
1708 | break; | |
1709 | st.next_addr += 2; | |
1710 | } | |
1711 | ||
1712 | /* (1) PUSHM src */ | |
1713 | else if (st.insn[i] == 0x8f) | |
1714 | { | |
1715 | int src = st.insn[i + 1]; | |
1716 | if (m32c_pv_pushm (&st, src)) | |
1717 | break; | |
1718 | st.next_addr += 2; | |
1719 | ||
1720 | if (m32c_pushm_is_reg_save (&st, src)) | |
1721 | after_last_frame_related_insn = st.next_addr; | |
1722 | } | |
1723 | ||
1724 | /* (7) MOV.size:G src, dest */ | |
1725 | else if ((st.insn[i] & 0x80) == 0x80 | |
1726 | && (st.insn[i + 1] & 0x0f) == 0x0b | |
1727 | && m32c_get_src23 (&st.insn[i]) < 20 | |
1728 | && m32c_get_dest23 (&st.insn[i]) < 20) | |
1729 | { | |
f79b9530 DJ |
1730 | struct srcdest src; |
1731 | struct srcdest dest; | |
1732 | pv_t src_value; | |
96309189 MS |
1733 | int bw = st.insn[i] & 0x01; |
1734 | int size = bw ? 2 : 1; | |
96309189 MS |
1735 | st.next_addr += 2; |
1736 | ||
f79b9530 | 1737 | src |
96309189 MS |
1738 | = m32c_decode_sd23 (&st, m32c_get_src23 (&st.insn[i]), |
1739 | size, src_indirect); | |
f79b9530 | 1740 | dest |
96309189 MS |
1741 | = m32c_decode_sd23 (&st, m32c_get_dest23 (&st.insn[i]), |
1742 | size, dest_indirect); | |
f79b9530 | 1743 | src_value = m32c_srcdest_fetch (&st, src, size); |
96309189 MS |
1744 | |
1745 | if (m32c_is_arg_spill (&st, dest, src_value)) | |
1746 | after_last_frame_related_insn = st.next_addr; | |
1747 | ||
1748 | if (m32c_srcdest_store (&st, dest, src_value, size)) | |
1749 | break; | |
1750 | } | |
1751 | /* (2) LDC #IMM24, sp */ | |
1752 | else if (st.insn[i] == 0xd5 | |
1753 | && st.insn[i + 1] == 0x29) | |
1754 | { | |
1755 | st.next_addr += 2; | |
1756 | st.sp = pv_constant (m32c_udisp24 (&st)); | |
1757 | } | |
1758 | else | |
1759 | /* We've hit some instruction we don't know how to simulate. | |
1760 | Strictly speaking, we should set every value we're | |
1761 | tracking to "unknown". But we'll be optimistic, assume | |
1762 | that we have enough information already, and stop | |
1763 | analysis here. */ | |
1764 | break; | |
1765 | } | |
1766 | ||
1767 | /* If this instruction changed the FB or decreased the SP (i.e., | |
1768 | allocated more stack space), then this may be a good place to | |
1769 | declare the prologue finished. However, there are some | |
1770 | exceptions: | |
1771 | ||
1772 | - If the instruction just changed the FB back to its original | |
1773 | value, then that's probably a restore instruction. The | |
1774 | prologue should definitely end before that. | |
1775 | ||
1776 | - If the instruction increased the value of the SP (that is, | |
1777 | shrunk the frame), then it's probably part of a frame | |
1778 | teardown sequence, and the prologue should end before | |
1779 | that. */ | |
1780 | ||
1781 | if (! pv_is_identical (st.fb, pre_insn_fb)) | |
1782 | { | |
1783 | if (! pv_is_register_k (st.fb, tdep->fb->num, 0)) | |
1784 | after_last_frame_related_insn = st.next_addr; | |
1785 | } | |
1786 | else if (! pv_is_identical (st.sp, pre_insn_sp)) | |
1787 | { | |
1788 | /* The comparison of the constants looks odd, there, because | |
1789 | .k is unsigned. All it really means is that the SP is | |
1790 | lower than it was before the instruction. */ | |
1791 | if ( pv_is_register (pre_insn_sp, tdep->sp->num) | |
1792 | && pv_is_register (st.sp, tdep->sp->num) | |
1793 | && ((pre_insn_sp.k - st.sp.k) < (st.sp.k - pre_insn_sp.k))) | |
1794 | after_last_frame_related_insn = st.next_addr; | |
1795 | } | |
1796 | ||
1797 | st.scan_pc = st.next_addr; | |
1798 | } | |
1799 | ||
1800 | /* Did we load a constant value into the stack pointer? */ | |
1801 | if (pv_is_constant (st.sp)) | |
1802 | prologue->kind = prologue_first_frame; | |
1803 | ||
1804 | /* Alternatively, did we initialize the frame pointer? Remember | |
1805 | that the CFA is the address after the return address. */ | |
1806 | if (pv_is_register (st.fb, tdep->sp->num)) | |
1807 | { | |
1808 | prologue->kind = prologue_with_frame_ptr; | |
1809 | prologue->frame_ptr_offset = st.fb.k; | |
1810 | } | |
1811 | ||
1812 | /* Is the frame size a known constant? Remember that frame_size is | |
1813 | actually the offset from the CFA to the SP (i.e., a negative | |
1814 | value). */ | |
1815 | else if (pv_is_register (st.sp, tdep->sp->num)) | |
1816 | { | |
1817 | prologue->kind = prologue_sans_frame_ptr; | |
1818 | prologue->frame_size = st.sp.k; | |
1819 | } | |
1820 | ||
1821 | /* We haven't been able to make sense of this function's frame. Treat | |
1822 | it as the first frame. */ | |
1823 | else | |
1824 | prologue->kind = prologue_first_frame; | |
1825 | ||
1826 | /* Record where all the registers were saved. */ | |
1827 | pv_area_scan (st.stack, check_for_saved, (void *) prologue); | |
1828 | ||
1829 | prologue->prologue_end = after_last_frame_related_insn; | |
1830 | ||
1831 | do_cleanups (back_to); | |
1832 | } | |
1833 | ||
1834 | ||
1835 | static CORE_ADDR | |
6093d2eb | 1836 | m32c_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR ip) |
96309189 MS |
1837 | { |
1838 | char *name; | |
1839 | CORE_ADDR func_addr, func_end, sal_end; | |
1840 | struct m32c_prologue p; | |
1841 | ||
1842 | /* Try to find the extent of the function that contains IP. */ | |
1843 | if (! find_pc_partial_function (ip, &name, &func_addr, &func_end)) | |
1844 | return ip; | |
1845 | ||
1846 | /* Find end by prologue analysis. */ | |
6093d2eb | 1847 | m32c_analyze_prologue (gdbarch, ip, func_end, &p); |
96309189 | 1848 | /* Find end by line info. */ |
d80b854b | 1849 | sal_end = skip_prologue_using_sal (gdbarch, ip); |
96309189 MS |
1850 | /* Return whichever is lower. */ |
1851 | if (sal_end != 0 && sal_end != ip && sal_end < p.prologue_end) | |
1852 | return sal_end; | |
1853 | else | |
1854 | return p.prologue_end; | |
1855 | } | |
1856 | ||
1857 | ||
1858 | \f | |
1859 | /* Stack unwinding. */ | |
1860 | ||
1861 | static struct m32c_prologue * | |
94afd7a6 | 1862 | m32c_analyze_frame_prologue (struct frame_info *this_frame, |
96309189 MS |
1863 | void **this_prologue_cache) |
1864 | { | |
1865 | if (! *this_prologue_cache) | |
1866 | { | |
94afd7a6 UW |
1867 | CORE_ADDR func_start = get_frame_func (this_frame); |
1868 | CORE_ADDR stop_addr = get_frame_pc (this_frame); | |
96309189 MS |
1869 | |
1870 | /* If we couldn't find any function containing the PC, then | |
1871 | just initialize the prologue cache, but don't do anything. */ | |
1872 | if (! func_start) | |
1873 | stop_addr = func_start; | |
1874 | ||
1875 | *this_prologue_cache = FRAME_OBSTACK_ZALLOC (struct m32c_prologue); | |
94afd7a6 | 1876 | m32c_analyze_prologue (get_frame_arch (this_frame), |
96309189 MS |
1877 | func_start, stop_addr, *this_prologue_cache); |
1878 | } | |
1879 | ||
1880 | return *this_prologue_cache; | |
1881 | } | |
1882 | ||
1883 | ||
1884 | static CORE_ADDR | |
94afd7a6 | 1885 | m32c_frame_base (struct frame_info *this_frame, |
96309189 MS |
1886 | void **this_prologue_cache) |
1887 | { | |
1888 | struct m32c_prologue *p | |
94afd7a6 UW |
1889 | = m32c_analyze_frame_prologue (this_frame, this_prologue_cache); |
1890 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); | |
96309189 MS |
1891 | |
1892 | /* In functions that use alloca, the distance between the stack | |
1893 | pointer and the frame base varies dynamically, so we can't use | |
1894 | the SP plus static information like prologue analysis to find the | |
1895 | frame base. However, such functions must have a frame pointer, | |
1896 | to be able to restore the SP on exit. So whenever we do have a | |
1897 | frame pointer, use that to find the base. */ | |
1898 | switch (p->kind) | |
1899 | { | |
1900 | case prologue_with_frame_ptr: | |
1901 | { | |
1902 | CORE_ADDR fb | |
94afd7a6 | 1903 | = get_frame_register_unsigned (this_frame, tdep->fb->num); |
96309189 MS |
1904 | return fb - p->frame_ptr_offset; |
1905 | } | |
1906 | ||
1907 | case prologue_sans_frame_ptr: | |
1908 | { | |
1909 | CORE_ADDR sp | |
94afd7a6 | 1910 | = get_frame_register_unsigned (this_frame, tdep->sp->num); |
96309189 MS |
1911 | return sp - p->frame_size; |
1912 | } | |
1913 | ||
1914 | case prologue_first_frame: | |
1915 | return 0; | |
1916 | ||
1917 | default: | |
f3574227 | 1918 | gdb_assert_not_reached ("unexpected prologue kind"); |
96309189 MS |
1919 | } |
1920 | } | |
1921 | ||
1922 | ||
1923 | static void | |
94afd7a6 | 1924 | m32c_this_id (struct frame_info *this_frame, |
96309189 MS |
1925 | void **this_prologue_cache, |
1926 | struct frame_id *this_id) | |
1927 | { | |
94afd7a6 | 1928 | CORE_ADDR base = m32c_frame_base (this_frame, this_prologue_cache); |
96309189 MS |
1929 | |
1930 | if (base) | |
94afd7a6 | 1931 | *this_id = frame_id_build (base, get_frame_func (this_frame)); |
96309189 MS |
1932 | /* Otherwise, leave it unset, and that will terminate the backtrace. */ |
1933 | } | |
1934 | ||
1935 | ||
94afd7a6 UW |
1936 | static struct value * |
1937 | m32c_prev_register (struct frame_info *this_frame, | |
1938 | void **this_prologue_cache, int regnum) | |
96309189 | 1939 | { |
94afd7a6 | 1940 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
96309189 | 1941 | struct m32c_prologue *p |
94afd7a6 UW |
1942 | = m32c_analyze_frame_prologue (this_frame, this_prologue_cache); |
1943 | CORE_ADDR frame_base = m32c_frame_base (this_frame, this_prologue_cache); | |
1944 | int reg_size = register_size (get_frame_arch (this_frame), regnum); | |
96309189 MS |
1945 | |
1946 | if (regnum == tdep->sp->num) | |
94afd7a6 | 1947 | return frame_unwind_got_constant (this_frame, regnum, frame_base); |
96309189 MS |
1948 | |
1949 | /* If prologue analysis says we saved this register somewhere, | |
1950 | return a description of the stack slot holding it. */ | |
94afd7a6 UW |
1951 | if (p->reg_offset[regnum] != 1) |
1952 | return frame_unwind_got_memory (this_frame, regnum, | |
1953 | frame_base + p->reg_offset[regnum]); | |
96309189 MS |
1954 | |
1955 | /* Otherwise, presume we haven't changed the value of this | |
1956 | register, and get it from the next frame. */ | |
94afd7a6 | 1957 | return frame_unwind_got_register (this_frame, regnum, regnum); |
96309189 MS |
1958 | } |
1959 | ||
1960 | ||
1961 | static const struct frame_unwind m32c_unwind = { | |
1962 | NORMAL_FRAME, | |
8fbca658 | 1963 | default_frame_unwind_stop_reason, |
96309189 | 1964 | m32c_this_id, |
94afd7a6 UW |
1965 | m32c_prev_register, |
1966 | NULL, | |
1967 | default_frame_sniffer | |
96309189 MS |
1968 | }; |
1969 | ||
1970 | ||
96309189 MS |
1971 | static CORE_ADDR |
1972 | m32c_unwind_pc (struct gdbarch *arch, struct frame_info *next_frame) | |
1973 | { | |
1974 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); | |
1975 | return frame_unwind_register_unsigned (next_frame, tdep->pc->num); | |
1976 | } | |
1977 | ||
1978 | ||
1979 | static CORE_ADDR | |
1980 | m32c_unwind_sp (struct gdbarch *arch, struct frame_info *next_frame) | |
1981 | { | |
1982 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); | |
1983 | return frame_unwind_register_unsigned (next_frame, tdep->sp->num); | |
1984 | } | |
1985 | ||
1986 | \f | |
1987 | /* Inferior calls. */ | |
1988 | ||
1989 | /* The calling conventions, according to GCC: | |
1990 | ||
1991 | r8c, m16c | |
1992 | --------- | |
1993 | First arg may be passed in r1l or r1 if it (1) fits (QImode or | |
1994 | HImode), (2) is named, and (3) is an integer or pointer type (no | |
1995 | structs, floats, etc). Otherwise, it's passed on the stack. | |
1996 | ||
1997 | Second arg may be passed in r2, same restrictions (but not QImode), | |
1998 | even if the first arg is passed on the stack. | |
1999 | ||
2000 | Third and further args are passed on the stack. No padding is | |
2001 | used, stack "alignment" is 8 bits. | |
2002 | ||
2003 | m32cm, m32c | |
2004 | ----------- | |
2005 | ||
2006 | First arg may be passed in r0l or r0, same restrictions as above. | |
2007 | ||
2008 | Second and further args are passed on the stack. Padding is used | |
2009 | after QImode parameters (i.e. lower-addressed byte is the value, | |
2010 | higher-addressed byte is the padding), stack "alignment" is 16 | |
2011 | bits. */ | |
2012 | ||
2013 | ||
2014 | /* Return true if TYPE is a type that can be passed in registers. (We | |
2015 | ignore the size, and pay attention only to the type code; | |
2016 | acceptable sizes depends on which register is being considered to | |
2017 | hold it.) */ | |
2018 | static int | |
2019 | m32c_reg_arg_type (struct type *type) | |
2020 | { | |
2021 | enum type_code code = TYPE_CODE (type); | |
2022 | ||
2023 | return (code == TYPE_CODE_INT | |
2024 | || code == TYPE_CODE_ENUM | |
2025 | || code == TYPE_CODE_PTR | |
2026 | || code == TYPE_CODE_REF | |
2027 | || code == TYPE_CODE_BOOL | |
2028 | || code == TYPE_CODE_CHAR); | |
2029 | } | |
2030 | ||
2031 | ||
2032 | static CORE_ADDR | |
2033 | m32c_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | |
2034 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
2035 | struct value **args, CORE_ADDR sp, int struct_return, | |
2036 | CORE_ADDR struct_addr) | |
2037 | { | |
2038 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
e17a4113 | 2039 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
96309189 MS |
2040 | unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach; |
2041 | CORE_ADDR cfa; | |
2042 | int i; | |
2043 | ||
2044 | /* The number of arguments given in this function's prototype, or | |
2045 | zero if it has a non-prototyped function type. The m32c ABI | |
2046 | passes arguments mentioned in the prototype differently from | |
2047 | those in the ellipsis of a varargs function, or from those passed | |
2048 | to a non-prototyped function. */ | |
2049 | int num_prototyped_args = 0; | |
2050 | ||
2051 | { | |
2052 | struct type *func_type = value_type (function); | |
2053 | ||
ed09d7da KB |
2054 | /* Dereference function pointer types. */ |
2055 | if (TYPE_CODE (func_type) == TYPE_CODE_PTR) | |
2056 | func_type = TYPE_TARGET_TYPE (func_type); | |
2057 | ||
96309189 MS |
2058 | gdb_assert (TYPE_CODE (func_type) == TYPE_CODE_FUNC || |
2059 | TYPE_CODE (func_type) == TYPE_CODE_METHOD); | |
2060 | ||
2061 | #if 0 | |
2062 | /* The ABI description in gcc/config/m32c/m32c.abi says that | |
2063 | we need to handle prototyped and non-prototyped functions | |
2064 | separately, but the code in GCC doesn't actually do so. */ | |
2065 | if (TYPE_PROTOTYPED (func_type)) | |
2066 | #endif | |
2067 | num_prototyped_args = TYPE_NFIELDS (func_type); | |
2068 | } | |
2069 | ||
2070 | /* First, if the function returns an aggregate by value, push a | |
2071 | pointer to a buffer for it. This doesn't affect the way | |
2072 | subsequent arguments are allocated to registers. */ | |
2073 | if (struct_return) | |
2074 | { | |
2075 | int ptr_len = TYPE_LENGTH (tdep->ptr_voyd); | |
2076 | sp -= ptr_len; | |
e17a4113 | 2077 | write_memory_unsigned_integer (sp, ptr_len, byte_order, struct_addr); |
96309189 MS |
2078 | } |
2079 | ||
2080 | /* Push the arguments. */ | |
2081 | for (i = nargs - 1; i >= 0; i--) | |
2082 | { | |
2083 | struct value *arg = args[i]; | |
2084 | const gdb_byte *arg_bits = value_contents (arg); | |
2085 | struct type *arg_type = value_type (arg); | |
2086 | ULONGEST arg_size = TYPE_LENGTH (arg_type); | |
2087 | ||
2088 | /* Can it go in r1 or r1l (for m16c) or r0 or r0l (for m32c)? */ | |
2089 | if (i == 0 | |
2090 | && arg_size <= 2 | |
2091 | && i < num_prototyped_args | |
2092 | && m32c_reg_arg_type (arg_type)) | |
2093 | { | |
2094 | /* Extract and re-store as an integer as a terse way to make | |
2095 | sure it ends up in the least significant end of r1. (GDB | |
2096 | should avoid assuming endianness, even on uni-endian | |
2097 | processors.) */ | |
e17a4113 UW |
2098 | ULONGEST u = extract_unsigned_integer (arg_bits, arg_size, |
2099 | byte_order); | |
96309189 MS |
2100 | struct m32c_reg *reg = (mach == bfd_mach_m16c) ? tdep->r1 : tdep->r0; |
2101 | regcache_cooked_write_unsigned (regcache, reg->num, u); | |
2102 | } | |
2103 | ||
2104 | /* Can it go in r2? */ | |
2105 | else if (mach == bfd_mach_m16c | |
2106 | && i == 1 | |
2107 | && arg_size == 2 | |
2108 | && i < num_prototyped_args | |
2109 | && m32c_reg_arg_type (arg_type)) | |
2110 | regcache_cooked_write (regcache, tdep->r2->num, arg_bits); | |
2111 | ||
2112 | /* Everything else goes on the stack. */ | |
2113 | else | |
2114 | { | |
2115 | sp -= arg_size; | |
2116 | ||
2117 | /* Align the stack. */ | |
2118 | if (mach == bfd_mach_m32c) | |
2119 | sp &= ~1; | |
2120 | ||
2121 | write_memory (sp, arg_bits, arg_size); | |
2122 | } | |
2123 | } | |
2124 | ||
2125 | /* This is the CFA we use to identify the dummy frame. */ | |
2126 | cfa = sp; | |
2127 | ||
2128 | /* Push the return address. */ | |
2129 | sp -= tdep->ret_addr_bytes; | |
e17a4113 UW |
2130 | write_memory_unsigned_integer (sp, tdep->ret_addr_bytes, byte_order, |
2131 | bp_addr); | |
96309189 MS |
2132 | |
2133 | /* Update the stack pointer. */ | |
2134 | regcache_cooked_write_unsigned (regcache, tdep->sp->num, sp); | |
2135 | ||
2136 | /* We need to borrow an odd trick from the i386 target here. | |
2137 | ||
2138 | The value we return from this function gets used as the stack | |
2139 | address (the CFA) for the dummy frame's ID. The obvious thing is | |
2140 | to return the new TOS. However, that points at the return | |
2141 | address, saved on the stack, which is inconsistent with the CFA's | |
2142 | described by GCC's DWARF 2 .debug_frame information: DWARF 2 | |
2143 | .debug_frame info uses the address immediately after the saved | |
2144 | return address. So you end up with a dummy frame whose CFA | |
2145 | points at the return address, but the frame for the function | |
2146 | being called has a CFA pointing after the return address: the | |
2147 | younger CFA is *greater than* the older CFA. The sanity checks | |
2148 | in frame.c don't like that. | |
2149 | ||
2150 | So we try to be consistent with the CFA's used by DWARF 2. | |
2151 | Having a dummy frame and a real frame with the *same* CFA is | |
2152 | tolerable. */ | |
2153 | return cfa; | |
2154 | } | |
2155 | ||
2156 | ||
2157 | static struct frame_id | |
94afd7a6 | 2158 | m32c_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
96309189 MS |
2159 | { |
2160 | /* This needs to return a frame ID whose PC is the return address | |
2161 | passed to m32c_push_dummy_call, and whose stack_addr is the SP | |
2162 | m32c_push_dummy_call returned. | |
2163 | ||
2164 | m32c_unwind_sp gives us the CFA, which is the value the SP had | |
2165 | before the return address was pushed. */ | |
94afd7a6 UW |
2166 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2167 | CORE_ADDR sp = get_frame_register_unsigned (this_frame, tdep->sp->num); | |
2168 | return frame_id_build (sp, get_frame_pc (this_frame)); | |
96309189 MS |
2169 | } |
2170 | ||
2171 | ||
2172 | \f | |
2173 | /* Return values. */ | |
2174 | ||
2175 | /* Return value conventions, according to GCC: | |
2176 | ||
2177 | r8c, m16c | |
2178 | --------- | |
2179 | ||
2180 | QImode in r0l | |
2181 | HImode in r0 | |
2182 | SImode in r2r0 | |
2183 | near pointer in r0 | |
2184 | far pointer in r2r0 | |
2185 | ||
2186 | Aggregate values (regardless of size) are returned by pushing a | |
2187 | pointer to a temporary area on the stack after the args are pushed. | |
2188 | The function fills in this area with the value. Note that this | |
2189 | pointer on the stack does not affect how register arguments, if any, | |
2190 | are configured. | |
2191 | ||
2192 | m32cm, m32c | |
2193 | ----------- | |
2194 | Same. */ | |
2195 | ||
2196 | /* Return non-zero if values of type TYPE are returned by storing them | |
2197 | in a buffer whose address is passed on the stack, ahead of the | |
2198 | other arguments. */ | |
2199 | static int | |
2200 | m32c_return_by_passed_buf (struct type *type) | |
2201 | { | |
2202 | enum type_code code = TYPE_CODE (type); | |
2203 | ||
2204 | return (code == TYPE_CODE_STRUCT | |
2205 | || code == TYPE_CODE_UNION); | |
2206 | } | |
2207 | ||
2208 | static enum return_value_convention | |
2209 | m32c_return_value (struct gdbarch *gdbarch, | |
c055b101 | 2210 | struct type *func_type, |
96309189 MS |
2211 | struct type *valtype, |
2212 | struct regcache *regcache, | |
2213 | gdb_byte *readbuf, | |
2214 | const gdb_byte *writebuf) | |
2215 | { | |
2216 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
e17a4113 | 2217 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
96309189 MS |
2218 | enum return_value_convention conv; |
2219 | ULONGEST valtype_len = TYPE_LENGTH (valtype); | |
2220 | ||
2221 | if (m32c_return_by_passed_buf (valtype)) | |
2222 | conv = RETURN_VALUE_STRUCT_CONVENTION; | |
2223 | else | |
2224 | conv = RETURN_VALUE_REGISTER_CONVENTION; | |
2225 | ||
2226 | if (readbuf) | |
2227 | { | |
2228 | /* We should never be called to find values being returned by | |
2229 | RETURN_VALUE_STRUCT_CONVENTION. Those can't be located, | |
2230 | unless we made the call ourselves. */ | |
2231 | gdb_assert (conv == RETURN_VALUE_REGISTER_CONVENTION); | |
2232 | ||
2233 | gdb_assert (valtype_len <= 8); | |
2234 | ||
2235 | /* Anything that fits in r0 is returned there. */ | |
2236 | if (valtype_len <= TYPE_LENGTH (tdep->r0->type)) | |
2237 | { | |
2238 | ULONGEST u; | |
2239 | regcache_cooked_read_unsigned (regcache, tdep->r0->num, &u); | |
e17a4113 | 2240 | store_unsigned_integer (readbuf, valtype_len, byte_order, u); |
96309189 MS |
2241 | } |
2242 | else | |
2243 | { | |
2244 | /* Everything else is passed in mem0, using as many bytes as | |
2245 | needed. This is not what the Renesas tools do, but it's | |
2246 | what GCC does at the moment. */ | |
2247 | struct minimal_symbol *mem0 | |
2248 | = lookup_minimal_symbol ("mem0", NULL, NULL); | |
2249 | ||
2250 | if (! mem0) | |
a73c6dcd MS |
2251 | error (_("The return value is stored in memory at 'mem0', " |
2252 | "but GDB cannot find\n" | |
2253 | "its address.")); | |
96309189 MS |
2254 | read_memory (SYMBOL_VALUE_ADDRESS (mem0), readbuf, valtype_len); |
2255 | } | |
2256 | } | |
2257 | ||
2258 | if (writebuf) | |
2259 | { | |
2260 | /* We should never be called to store values to be returned | |
2261 | using RETURN_VALUE_STRUCT_CONVENTION. We have no way of | |
2262 | finding the buffer, unless we made the call ourselves. */ | |
2263 | gdb_assert (conv == RETURN_VALUE_REGISTER_CONVENTION); | |
2264 | ||
2265 | gdb_assert (valtype_len <= 8); | |
2266 | ||
2267 | /* Anything that fits in r0 is returned there. */ | |
2268 | if (valtype_len <= TYPE_LENGTH (tdep->r0->type)) | |
2269 | { | |
e17a4113 UW |
2270 | ULONGEST u = extract_unsigned_integer (writebuf, valtype_len, |
2271 | byte_order); | |
96309189 MS |
2272 | regcache_cooked_write_unsigned (regcache, tdep->r0->num, u); |
2273 | } | |
2274 | else | |
2275 | { | |
2276 | /* Everything else is passed in mem0, using as many bytes as | |
2277 | needed. This is not what the Renesas tools do, but it's | |
2278 | what GCC does at the moment. */ | |
2279 | struct minimal_symbol *mem0 | |
2280 | = lookup_minimal_symbol ("mem0", NULL, NULL); | |
2281 | ||
2282 | if (! mem0) | |
a73c6dcd MS |
2283 | error (_("The return value is stored in memory at 'mem0', " |
2284 | "but GDB cannot find\n" | |
2285 | " its address.")); | |
96309189 MS |
2286 | write_memory (SYMBOL_VALUE_ADDRESS (mem0), |
2287 | (char *) writebuf, valtype_len); | |
2288 | } | |
2289 | } | |
2290 | ||
2291 | return conv; | |
2292 | } | |
2293 | ||
2294 | ||
2295 | \f | |
2296 | /* Trampolines. */ | |
2297 | ||
2298 | /* The m16c and m32c use a trampoline function for indirect function | |
2299 | calls. An indirect call looks like this: | |
2300 | ||
2301 | ... push arguments ... | |
2302 | ... push target function address ... | |
2303 | jsr.a m32c_jsri16 | |
2304 | ||
2305 | The code for m32c_jsri16 looks like this: | |
2306 | ||
2307 | m32c_jsri16: | |
2308 | ||
2309 | # Save return address. | |
2310 | pop.w m32c_jsri_ret | |
2311 | pop.b m32c_jsri_ret+2 | |
2312 | ||
2313 | # Store target function address. | |
2314 | pop.w m32c_jsri_addr | |
2315 | ||
2316 | # Re-push return address. | |
2317 | push.b m32c_jsri_ret+2 | |
2318 | push.w m32c_jsri_ret | |
2319 | ||
2320 | # Call the target function. | |
2321 | jmpi.a m32c_jsri_addr | |
2322 | ||
2323 | Without further information, GDB will treat calls to m32c_jsri16 | |
2324 | like calls to any other function. Since m32c_jsri16 doesn't have | |
2325 | debugging information, that normally means that GDB sets a step- | |
2326 | resume breakpoint and lets the program continue --- which is not | |
2327 | what the user wanted. (Giving the trampoline debugging info | |
2328 | doesn't help: the user expects the program to stop in the function | |
2329 | their program is calling, not in some trampoline code they've never | |
2330 | seen before.) | |
2331 | ||
e76f05fa | 2332 | The gdbarch_skip_trampoline_code method tells GDB how to step |
96309189 MS |
2333 | through such trampoline functions transparently to the user. When |
2334 | given the address of a trampoline function's first instruction, | |
e76f05fa | 2335 | gdbarch_skip_trampoline_code should return the address of the first |
96309189 MS |
2336 | instruction of the function really being called. If GDB decides it |
2337 | wants to step into that function, it will set a breakpoint there | |
2338 | and silently continue to it. | |
2339 | ||
2340 | We recognize the trampoline by name, and extract the target address | |
2341 | directly from the stack. This isn't great, but recognizing by its | |
2342 | code sequence seems more fragile. */ | |
2343 | ||
2344 | static CORE_ADDR | |
52f729a7 | 2345 | m32c_skip_trampoline_code (struct frame_info *frame, CORE_ADDR stop_pc) |
96309189 | 2346 | { |
e17a4113 UW |
2347 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2348 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2349 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
96309189 MS |
2350 | |
2351 | /* It would be nicer to simply look up the addresses of known | |
2352 | trampolines once, and then compare stop_pc with them. However, | |
2353 | we'd need to ensure that that cached address got invalidated when | |
2354 | someone loaded a new executable, and I'm not quite sure of the | |
2355 | best way to do that. find_pc_partial_function does do some | |
2356 | caching, so we'll see how this goes. */ | |
2357 | char *name; | |
2358 | CORE_ADDR start, end; | |
2359 | ||
2360 | if (find_pc_partial_function (stop_pc, &name, &start, &end)) | |
2361 | { | |
2362 | /* Are we stopped at the beginning of the trampoline function? */ | |
2363 | if (strcmp (name, "m32c_jsri16") == 0 | |
2364 | && stop_pc == start) | |
2365 | { | |
2366 | /* Get the stack pointer. The return address is at the top, | |
2367 | and the target function's address is just below that. We | |
2368 | know it's a two-byte address, since the trampoline is | |
2369 | m32c_jsri*16*. */ | |
2370 | CORE_ADDR sp = get_frame_sp (get_current_frame ()); | |
2371 | CORE_ADDR target | |
e17a4113 UW |
2372 | = read_memory_unsigned_integer (sp + tdep->ret_addr_bytes, |
2373 | 2, byte_order); | |
96309189 MS |
2374 | |
2375 | /* What we have now is the address of a jump instruction. | |
2376 | What we need is the destination of that jump. | |
025bb325 MS |
2377 | The opcode is 1 byte, and the destination is the next 3 bytes. */ |
2378 | ||
e17a4113 | 2379 | target = read_memory_unsigned_integer (target + 1, 3, byte_order); |
96309189 MS |
2380 | return target; |
2381 | } | |
2382 | } | |
2383 | ||
2384 | return 0; | |
2385 | } | |
2386 | ||
2387 | ||
2388 | /* Address/pointer conversions. */ | |
2389 | ||
2390 | /* On the m16c, there is a 24-bit address space, but only a very few | |
2391 | instructions can generate addresses larger than 0xffff: jumps, | |
2392 | jumps to subroutines, and the lde/std (load/store extended) | |
2393 | instructions. | |
2394 | ||
2395 | Since GCC can only support one size of pointer, we can't have | |
2396 | distinct 'near' and 'far' pointer types; we have to pick one size | |
2397 | for everything. If we wanted to use 24-bit pointers, then GCC | |
2398 | would have to use lde and ste for all memory references, which | |
2399 | would be terrible for performance and code size. So the GNU | |
2400 | toolchain uses 16-bit pointers for everything, and gives up the | |
2401 | ability to have pointers point outside the first 64k of memory. | |
2402 | ||
2403 | However, as a special hack, we let the linker place functions at | |
2404 | addresses above 0xffff, as long as it also places a trampoline in | |
2405 | the low 64k for every function whose address is taken. Each | |
2406 | trampoline consists of a single jmp.a instruction that jumps to the | |
2407 | function's real entry point. Pointers to functions can be 16 bits | |
2408 | long, even though the functions themselves are at higher addresses: | |
2409 | the pointers refer to the trampolines, not the functions. | |
2410 | ||
2411 | This complicates things for GDB, however: given the address of a | |
2412 | function (from debug info or linker symbols, say) which could be | |
2413 | anywhere in the 24-bit address space, how can we find an | |
2414 | appropriate 16-bit value to use as a pointer to it? | |
2415 | ||
2416 | If the linker has not generated a trampoline for the function, | |
2417 | we're out of luck. Well, I guess we could malloc some space and | |
2418 | write a jmp.a instruction to it, but I'm not going to get into that | |
2419 | at the moment. | |
2420 | ||
2421 | If the linker has generated a trampoline for the function, then it | |
2422 | also emitted a symbol for the trampoline: if the function's linker | |
2423 | symbol is named NAME, then the function's trampoline's linker | |
2424 | symbol is named NAME.plt. | |
2425 | ||
2426 | So, given a code address: | |
2427 | - We try to find a linker symbol at that address. | |
2428 | - If we find such a symbol named NAME, we look for a linker symbol | |
2429 | named NAME.plt. | |
2430 | - If we find such a symbol, we assume it is a trampoline, and use | |
2431 | its address as the pointer value. | |
2432 | ||
2433 | And, given a function pointer: | |
2434 | - We try to find a linker symbol at that address named NAME.plt. | |
2435 | - If we find such a symbol, we look for a linker symbol named NAME. | |
2436 | - If we find that, we provide that as the function's address. | |
2437 | - If any of the above steps fail, we return the original address | |
2438 | unchanged; it might really be a function in the low 64k. | |
2439 | ||
2440 | See? You *knew* there was a reason you wanted to be a computer | |
2441 | programmer! :) */ | |
2442 | ||
2443 | static void | |
9898f801 UW |
2444 | m32c_m16c_address_to_pointer (struct gdbarch *gdbarch, |
2445 | struct type *type, gdb_byte *buf, CORE_ADDR addr) | |
96309189 | 2446 | { |
e17a4113 | 2447 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
f79b9530 | 2448 | enum type_code target_code; |
96309189 MS |
2449 | gdb_assert (TYPE_CODE (type) == TYPE_CODE_PTR || |
2450 | TYPE_CODE (type) == TYPE_CODE_REF); | |
2451 | ||
f79b9530 | 2452 | target_code = TYPE_CODE (TYPE_TARGET_TYPE (type)); |
96309189 MS |
2453 | |
2454 | if (target_code == TYPE_CODE_FUNC || target_code == TYPE_CODE_METHOD) | |
2455 | { | |
f79b9530 DJ |
2456 | char *func_name; |
2457 | char *tramp_name; | |
2458 | struct minimal_symbol *tramp_msym; | |
2459 | ||
96309189 MS |
2460 | /* Try to find a linker symbol at this address. */ |
2461 | struct minimal_symbol *func_msym = lookup_minimal_symbol_by_pc (addr); | |
2462 | ||
2463 | if (! func_msym) | |
d77b48cf KB |
2464 | error (_("Cannot convert code address %s to function pointer:\n" |
2465 | "couldn't find a symbol at that address, to find trampoline."), | |
5af949e3 | 2466 | paddress (gdbarch, addr)); |
96309189 | 2467 | |
f79b9530 DJ |
2468 | func_name = SYMBOL_LINKAGE_NAME (func_msym); |
2469 | tramp_name = xmalloc (strlen (func_name) + 5); | |
96309189 MS |
2470 | strcpy (tramp_name, func_name); |
2471 | strcat (tramp_name, ".plt"); | |
2472 | ||
2473 | /* Try to find a linker symbol for the trampoline. */ | |
f79b9530 | 2474 | tramp_msym = lookup_minimal_symbol (tramp_name, NULL, NULL); |
96309189 MS |
2475 | |
2476 | /* We've either got another copy of the name now, or don't need | |
2477 | the name any more. */ | |
2478 | xfree (tramp_name); | |
2479 | ||
2480 | if (! tramp_msym) | |
d77b48cf KB |
2481 | { |
2482 | CORE_ADDR ptrval; | |
2483 | ||
2484 | /* No PLT entry found. Mask off the upper bits of the address | |
2485 | to make a pointer. As noted in the warning to the user | |
2486 | below, this value might be useful if converted back into | |
2487 | an address by GDB, but will otherwise, almost certainly, | |
2488 | be garbage. | |
2489 | ||
2490 | Using this masked result does seem to be useful | |
2491 | in gdb.cp/cplusfuncs.exp in which ~40 FAILs turn into | |
2492 | PASSes. These results appear to be correct as well. | |
2493 | ||
2494 | We print a warning here so that the user can make a | |
2495 | determination about whether the result is useful or not. */ | |
2496 | ptrval = addr & 0xffff; | |
2497 | ||
2498 | warning (_("Cannot convert code address %s to function pointer:\n" | |
2499 | "couldn't find trampoline named '%s.plt'.\n" | |
2500 | "Returning pointer value %s instead; this may produce\n" | |
2501 | "a useful result if converted back into an address by GDB,\n" | |
2502 | "but will most likely not be useful otherwise.\n"), | |
2503 | paddress (gdbarch, addr), func_name, | |
2504 | paddress (gdbarch, ptrval)); | |
2505 | ||
2506 | addr = ptrval; | |
96309189 | 2507 | |
d77b48cf KB |
2508 | } |
2509 | else | |
2510 | { | |
2511 | /* The trampoline's address is our pointer. */ | |
2512 | addr = SYMBOL_VALUE_ADDRESS (tramp_msym); | |
2513 | } | |
96309189 MS |
2514 | } |
2515 | ||
e17a4113 | 2516 | store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order, addr); |
96309189 MS |
2517 | } |
2518 | ||
2519 | ||
2520 | static CORE_ADDR | |
9898f801 UW |
2521 | m32c_m16c_pointer_to_address (struct gdbarch *gdbarch, |
2522 | struct type *type, const gdb_byte *buf) | |
96309189 | 2523 | { |
e17a4113 | 2524 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
f79b9530 DJ |
2525 | CORE_ADDR ptr; |
2526 | enum type_code target_code; | |
2527 | ||
96309189 MS |
2528 | gdb_assert (TYPE_CODE (type) == TYPE_CODE_PTR || |
2529 | TYPE_CODE (type) == TYPE_CODE_REF); | |
2530 | ||
e17a4113 | 2531 | ptr = extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order); |
96309189 | 2532 | |
f79b9530 | 2533 | target_code = TYPE_CODE (TYPE_TARGET_TYPE (type)); |
96309189 MS |
2534 | |
2535 | if (target_code == TYPE_CODE_FUNC || target_code == TYPE_CODE_METHOD) | |
2536 | { | |
2537 | /* See if there is a minimal symbol at that address whose name is | |
2538 | "NAME.plt". */ | |
2539 | struct minimal_symbol *ptr_msym = lookup_minimal_symbol_by_pc (ptr); | |
2540 | ||
2541 | if (ptr_msym) | |
2542 | { | |
2543 | char *ptr_msym_name = SYMBOL_LINKAGE_NAME (ptr_msym); | |
2544 | int len = strlen (ptr_msym_name); | |
2545 | ||
2546 | if (len > 4 | |
2547 | && strcmp (ptr_msym_name + len - 4, ".plt") == 0) | |
2548 | { | |
f79b9530 | 2549 | struct minimal_symbol *func_msym; |
96309189 MS |
2550 | /* We have a .plt symbol; try to find the symbol for the |
2551 | corresponding function. | |
2552 | ||
2553 | Since the trampoline contains a jump instruction, we | |
2554 | could also just extract the jump's target address. I | |
2555 | don't see much advantage one way or the other. */ | |
2556 | char *func_name = xmalloc (len - 4 + 1); | |
2557 | memcpy (func_name, ptr_msym_name, len - 4); | |
2558 | func_name[len - 4] = '\0'; | |
f79b9530 | 2559 | func_msym |
96309189 MS |
2560 | = lookup_minimal_symbol (func_name, NULL, NULL); |
2561 | ||
2562 | /* If we do have such a symbol, return its value as the | |
2563 | function's true address. */ | |
2564 | if (func_msym) | |
2565 | ptr = SYMBOL_VALUE_ADDRESS (func_msym); | |
2566 | } | |
2567 | } | |
d77b48cf KB |
2568 | else |
2569 | { | |
2570 | int aspace; | |
2571 | ||
2572 | for (aspace = 1; aspace <= 15; aspace++) | |
2573 | { | |
2574 | ptr_msym = lookup_minimal_symbol_by_pc ((aspace << 16) | ptr); | |
2575 | ||
2576 | if (ptr_msym) | |
2577 | ptr |= aspace << 16; | |
2578 | } | |
2579 | } | |
96309189 MS |
2580 | } |
2581 | ||
2582 | return ptr; | |
2583 | } | |
2584 | ||
63807e1d | 2585 | static void |
a54fba4c | 2586 | m32c_virtual_frame_pointer (struct gdbarch *gdbarch, CORE_ADDR pc, |
7830cb4f CV |
2587 | int *frame_regnum, |
2588 | LONGEST *frame_offset) | |
2589 | { | |
2590 | char *name; | |
2591 | CORE_ADDR func_addr, func_end, sal_end; | |
2592 | struct m32c_prologue p; | |
2593 | ||
594f7785 | 2594 | struct regcache *regcache = get_current_regcache (); |
a54fba4c | 2595 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7830cb4f CV |
2596 | |
2597 | if (!find_pc_partial_function (pc, &name, &func_addr, &func_end)) | |
025bb325 MS |
2598 | internal_error (__FILE__, __LINE__, |
2599 | _("No virtual frame pointer available")); | |
7830cb4f | 2600 | |
a54fba4c | 2601 | m32c_analyze_prologue (gdbarch, func_addr, pc, &p); |
7830cb4f CV |
2602 | switch (p.kind) |
2603 | { | |
2604 | case prologue_with_frame_ptr: | |
594f7785 | 2605 | *frame_regnum = m32c_banked_register (tdep->fb, regcache)->num; |
7830cb4f CV |
2606 | *frame_offset = p.frame_ptr_offset; |
2607 | break; | |
2608 | case prologue_sans_frame_ptr: | |
594f7785 | 2609 | *frame_regnum = m32c_banked_register (tdep->sp, regcache)->num; |
7830cb4f CV |
2610 | *frame_offset = p.frame_size; |
2611 | break; | |
2612 | default: | |
594f7785 | 2613 | *frame_regnum = m32c_banked_register (tdep->sp, regcache)->num; |
7830cb4f CV |
2614 | *frame_offset = 0; |
2615 | break; | |
2616 | } | |
2617 | /* Sanity check */ | |
a54fba4c | 2618 | if (*frame_regnum > gdbarch_num_regs (gdbarch)) |
025bb325 MS |
2619 | internal_error (__FILE__, __LINE__, |
2620 | _("No virtual frame pointer available")); | |
7830cb4f | 2621 | } |
96309189 MS |
2622 | |
2623 | \f | |
2624 | /* Initialization. */ | |
2625 | ||
2626 | static struct gdbarch * | |
2627 | m32c_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2628 | { | |
2629 | struct gdbarch *arch; | |
2630 | struct gdbarch_tdep *tdep; | |
2631 | unsigned long mach = info.bfd_arch_info->mach; | |
2632 | ||
2633 | /* Find a candidate among the list of architectures we've created | |
2634 | already. */ | |
2635 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
2636 | arches != NULL; | |
2637 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
2638 | return arches->gdbarch; | |
2639 | ||
2640 | tdep = xcalloc (1, sizeof (*tdep)); | |
2641 | arch = gdbarch_alloc (&info, tdep); | |
2642 | ||
2643 | /* Essential types. */ | |
2644 | make_types (arch); | |
2645 | ||
2646 | /* Address/pointer conversions. */ | |
2647 | if (mach == bfd_mach_m16c) | |
2648 | { | |
2649 | set_gdbarch_address_to_pointer (arch, m32c_m16c_address_to_pointer); | |
2650 | set_gdbarch_pointer_to_address (arch, m32c_m16c_pointer_to_address); | |
2651 | } | |
2652 | ||
2653 | /* Register set. */ | |
2654 | make_regs (arch); | |
2655 | ||
2656 | /* Disassembly. */ | |
2657 | set_gdbarch_print_insn (arch, print_insn_m32c); | |
2658 | ||
2659 | /* Breakpoints. */ | |
2660 | set_gdbarch_breakpoint_from_pc (arch, m32c_breakpoint_from_pc); | |
2661 | ||
2662 | /* Prologue analysis and unwinding. */ | |
2663 | set_gdbarch_inner_than (arch, core_addr_lessthan); | |
2664 | set_gdbarch_skip_prologue (arch, m32c_skip_prologue); | |
2665 | set_gdbarch_unwind_pc (arch, m32c_unwind_pc); | |
2666 | set_gdbarch_unwind_sp (arch, m32c_unwind_sp); | |
2667 | #if 0 | |
2668 | /* I'm dropping the dwarf2 sniffer because it has a few problems. | |
2669 | They may be in the dwarf2 cfi code in GDB, or they may be in | |
2670 | the debug info emitted by the upstream toolchain. I don't | |
2671 | know which, but I do know that the prologue analyzer works better. | |
025bb325 | 2672 | MVS 04/13/06 */ |
94afd7a6 | 2673 | dwarf2_append_sniffers (arch); |
96309189 | 2674 | #endif |
94afd7a6 | 2675 | frame_unwind_append_unwinder (arch, &m32c_unwind); |
96309189 MS |
2676 | |
2677 | /* Inferior calls. */ | |
2678 | set_gdbarch_push_dummy_call (arch, m32c_push_dummy_call); | |
2679 | set_gdbarch_return_value (arch, m32c_return_value); | |
94afd7a6 | 2680 | set_gdbarch_dummy_id (arch, m32c_dummy_id); |
96309189 MS |
2681 | |
2682 | /* Trampolines. */ | |
2683 | set_gdbarch_skip_trampoline_code (arch, m32c_skip_trampoline_code); | |
2684 | ||
7830cb4f CV |
2685 | set_gdbarch_virtual_frame_pointer (arch, m32c_virtual_frame_pointer); |
2686 | ||
ed09d7da KB |
2687 | /* m32c function boundary addresses are not necessarily even. |
2688 | Therefore, the `vbit', which indicates a pointer to a virtual | |
2689 | member function, is stored in the delta field, rather than as | |
025bb325 | 2690 | the low bit of a function pointer address. |
ed09d7da KB |
2691 | |
2692 | In order to verify this, see the definition of | |
2693 | TARGET_PTRMEMFUNC_VBIT_LOCATION in gcc/defaults.h along with the | |
2694 | definition of FUNCTION_BOUNDARY in gcc/config/m32c/m32c.h. */ | |
2695 | set_gdbarch_vbit_in_delta (arch, 1); | |
2696 | ||
96309189 MS |
2697 | return arch; |
2698 | } | |
2699 | ||
63807e1d PA |
2700 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
2701 | extern initialize_file_ftype _initialize_m32c_tdep; | |
96309189 MS |
2702 | |
2703 | void | |
2704 | _initialize_m32c_tdep (void) | |
2705 | { | |
2706 | register_gdbarch_init (bfd_arch_m32c, m32c_gdbarch_init); | |
2707 | ||
2708 | m32c_dma_reggroup = reggroup_new ("dma", USER_REGGROUP); | |
2709 | } |