Commit | Line | Data |
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d95a8903 AC |
1 | /* Target-dependent code for Renesas M32R, for GDB. |
2 | ||
e2882c85 | 3 | Copyright (C) 1996-2018 Free Software Foundation, Inc. |
d95a8903 AC |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
d95a8903 AC |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
d95a8903 AC |
19 | |
20 | #include "defs.h" | |
21 | #include "frame.h" | |
22 | #include "frame-unwind.h" | |
23 | #include "frame-base.h" | |
24 | #include "symtab.h" | |
25 | #include "gdbtypes.h" | |
26 | #include "gdbcmd.h" | |
27 | #include "gdbcore.h" | |
d95a8903 AC |
28 | #include "value.h" |
29 | #include "inferior.h" | |
30 | #include "symfile.h" | |
31 | #include "objfiles.h" | |
c46b0409 | 32 | #include "osabi.h" |
d95a8903 AC |
33 | #include "language.h" |
34 | #include "arch-utils.h" | |
35 | #include "regcache.h" | |
36 | #include "trad-frame.h" | |
73e8eb51 | 37 | #include "dis-asm.h" |
77e371c0 | 38 | #include "objfiles.h" |
9b32d526 | 39 | #include "m32r-tdep.h" |
325fac50 | 40 | #include <algorithm> |
d95a8903 | 41 | |
ab0538b8 AH |
42 | /* The size of the argument registers (r0 - r3) in bytes. */ |
43 | #define M32R_ARG_REGISTER_SIZE 4 | |
44 | ||
d95a8903 AC |
45 | /* Local functions */ |
46 | ||
d95a8903 AC |
47 | static CORE_ADDR |
48 | m32r_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
49 | { | |
50 | /* Align to the size of an instruction (so that they can safely be | |
51 | pushed onto the stack. */ | |
52 | return sp & ~3; | |
53 | } | |
54 | ||
d95a8903 | 55 | |
9f0b0322 KI |
56 | /* Breakpoints |
57 | ||
025bb325 | 58 | The little endian mode of M32R is unique. In most of architectures, |
9f0b0322 KI |
59 | two 16-bit instructions, A and B, are placed as the following: |
60 | ||
61 | Big endian: | |
62 | A0 A1 B0 B1 | |
63 | ||
64 | Little endian: | |
65 | A1 A0 B1 B0 | |
66 | ||
67 | In M32R, they are placed like this: | |
68 | ||
69 | Big endian: | |
70 | A0 A1 B0 B1 | |
71 | ||
72 | Little endian: | |
73 | B1 B0 A1 A0 | |
74 | ||
75 | This is because M32R always fetches instructions in 32-bit. | |
76 | ||
025bb325 | 77 | The following functions take care of this behavior. */ |
d95a8903 AC |
78 | |
79 | static int | |
ae4b2284 MD |
80 | m32r_memory_insert_breakpoint (struct gdbarch *gdbarch, |
81 | struct bp_target_info *bp_tgt) | |
d95a8903 | 82 | { |
0d5ed153 | 83 | CORE_ADDR addr = bp_tgt->placed_address = bp_tgt->reqstd_address; |
d95a8903 | 84 | int val; |
16ac4ab5 | 85 | gdb_byte buf[4]; |
35c63cd8 | 86 | gdb_byte contents_cache[4]; |
16ac4ab5 | 87 | gdb_byte bp_entry[] = { 0x10, 0xf1 }; /* dpt */ |
d95a8903 AC |
88 | |
89 | /* Save the memory contents. */ | |
9f0b0322 | 90 | val = target_read_memory (addr & 0xfffffffc, contents_cache, 4); |
d95a8903 AC |
91 | if (val != 0) |
92 | return val; /* return error */ | |
93 | ||
35c63cd8 | 94 | memcpy (bp_tgt->shadow_contents, contents_cache, 4); |
cd6c3b4f | 95 | bp_tgt->shadow_len = 4; |
8181d85f | 96 | |
d95a8903 | 97 | /* Determine appropriate breakpoint contents and size for this address. */ |
ae4b2284 | 98 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
d95a8903 | 99 | { |
9f0b0322 | 100 | if ((addr & 3) == 0) |
d95a8903 | 101 | { |
9f0b0322 KI |
102 | buf[0] = bp_entry[0]; |
103 | buf[1] = bp_entry[1]; | |
104 | buf[2] = contents_cache[2] & 0x7f; | |
105 | buf[3] = contents_cache[3]; | |
d95a8903 AC |
106 | } |
107 | else | |
108 | { | |
9f0b0322 KI |
109 | buf[0] = contents_cache[0]; |
110 | buf[1] = contents_cache[1]; | |
111 | buf[2] = bp_entry[0]; | |
112 | buf[3] = bp_entry[1]; | |
d95a8903 AC |
113 | } |
114 | } | |
9f0b0322 KI |
115 | else /* little-endian */ |
116 | { | |
117 | if ((addr & 3) == 0) | |
d95a8903 | 118 | { |
9f0b0322 KI |
119 | buf[0] = contents_cache[0]; |
120 | buf[1] = contents_cache[1] & 0x7f; | |
121 | buf[2] = bp_entry[1]; | |
122 | buf[3] = bp_entry[0]; | |
d95a8903 AC |
123 | } |
124 | else | |
125 | { | |
9f0b0322 KI |
126 | buf[0] = bp_entry[1]; |
127 | buf[1] = bp_entry[0]; | |
128 | buf[2] = contents_cache[2]; | |
129 | buf[3] = contents_cache[3]; | |
d95a8903 AC |
130 | } |
131 | } | |
132 | ||
133 | /* Write the breakpoint. */ | |
9f0b0322 | 134 | val = target_write_memory (addr & 0xfffffffc, buf, 4); |
d95a8903 AC |
135 | return val; |
136 | } | |
137 | ||
138 | static int | |
ae4b2284 MD |
139 | m32r_memory_remove_breakpoint (struct gdbarch *gdbarch, |
140 | struct bp_target_info *bp_tgt) | |
d95a8903 | 141 | { |
8181d85f | 142 | CORE_ADDR addr = bp_tgt->placed_address; |
d95a8903 | 143 | int val; |
16ac4ab5 | 144 | gdb_byte buf[4]; |
8181d85f | 145 | gdb_byte *contents_cache = bp_tgt->shadow_contents; |
d95a8903 | 146 | |
9f0b0322 KI |
147 | buf[0] = contents_cache[0]; |
148 | buf[1] = contents_cache[1]; | |
149 | buf[2] = contents_cache[2]; | |
150 | buf[3] = contents_cache[3]; | |
151 | ||
152 | /* Remove parallel bit. */ | |
ae4b2284 | 153 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
d95a8903 | 154 | { |
9f0b0322 KI |
155 | if ((buf[0] & 0x80) == 0 && (buf[2] & 0x80) != 0) |
156 | buf[2] &= 0x7f; | |
d95a8903 | 157 | } |
9f0b0322 | 158 | else /* little-endian */ |
d95a8903 | 159 | { |
9f0b0322 KI |
160 | if ((buf[3] & 0x80) == 0 && (buf[1] & 0x80) != 0) |
161 | buf[1] &= 0x7f; | |
d95a8903 AC |
162 | } |
163 | ||
164 | /* Write contents. */ | |
dd110abf | 165 | val = target_write_raw_memory (addr & 0xfffffffc, buf, 4); |
d95a8903 AC |
166 | return val; |
167 | } | |
168 | ||
cd6c3b4f YQ |
169 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ |
170 | ||
d19280ad YQ |
171 | static int |
172 | m32r_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
173 | { | |
174 | if ((*pcptr & 3) == 0) | |
175 | return 4; | |
176 | else | |
177 | return 2; | |
178 | } | |
179 | ||
cd6c3b4f YQ |
180 | /* Implement the sw_breakpoint_from_kind gdbarch method. */ |
181 | ||
16ac4ab5 | 182 | static const gdb_byte * |
d19280ad | 183 | m32r_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) |
d95a8903 | 184 | { |
025bb325 MS |
185 | static gdb_byte be_bp_entry[] = { |
186 | 0x10, 0xf1, 0x70, 0x00 | |
187 | }; /* dpt -> nop */ | |
188 | static gdb_byte le_bp_entry[] = { | |
189 | 0x00, 0x70, 0xf1, 0x10 | |
190 | }; /* dpt -> nop */ | |
d19280ad YQ |
191 | |
192 | *size = kind; | |
d95a8903 AC |
193 | |
194 | /* Determine appropriate breakpoint. */ | |
67d57894 | 195 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
d19280ad | 196 | return be_bp_entry; |
d95a8903 AC |
197 | else |
198 | { | |
d19280ad YQ |
199 | if (kind == 4) |
200 | return le_bp_entry; | |
d95a8903 | 201 | else |
d19280ad | 202 | return le_bp_entry + 2; |
d95a8903 | 203 | } |
d95a8903 AC |
204 | } |
205 | ||
a121b7c1 | 206 | static const char *m32r_register_names[] = { |
d95a8903 AC |
207 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
208 | "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp", | |
209 | "psw", "cbr", "spi", "spu", "bpc", "pc", "accl", "acch", | |
210 | "evb" | |
211 | }; | |
212 | ||
d95a8903 | 213 | static const char * |
d93859e2 | 214 | m32r_register_name (struct gdbarch *gdbarch, int reg_nr) |
d95a8903 AC |
215 | { |
216 | if (reg_nr < 0) | |
217 | return NULL; | |
9b32d526 | 218 | if (reg_nr >= M32R_NUM_REGS) |
d95a8903 AC |
219 | return NULL; |
220 | return m32r_register_names[reg_nr]; | |
221 | } | |
222 | ||
223 | ||
224 | /* Return the GDB type object for the "standard" data type | |
225 | of data in register N. */ | |
226 | ||
227 | static struct type * | |
228 | m32r_register_type (struct gdbarch *gdbarch, int reg_nr) | |
229 | { | |
230 | if (reg_nr == M32R_PC_REGNUM) | |
0dfff4cb | 231 | return builtin_type (gdbarch)->builtin_func_ptr; |
d95a8903 | 232 | else if (reg_nr == M32R_SP_REGNUM || reg_nr == M32R_FP_REGNUM) |
0dfff4cb | 233 | return builtin_type (gdbarch)->builtin_data_ptr; |
d95a8903 | 234 | else |
df4df182 | 235 | return builtin_type (gdbarch)->builtin_int32; |
d95a8903 AC |
236 | } |
237 | ||
238 | ||
239 | /* Write into appropriate registers a function return value | |
025bb325 | 240 | of type TYPE, given in virtual format. |
d95a8903 | 241 | |
025bb325 | 242 | Things always get returned in RET1_REGNUM, RET2_REGNUM. */ |
d95a8903 AC |
243 | |
244 | static void | |
245 | m32r_store_return_value (struct type *type, struct regcache *regcache, | |
7c543f7b | 246 | const gdb_byte *valbuf) |
d95a8903 | 247 | { |
ac7936df | 248 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 249 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d95a8903 AC |
250 | CORE_ADDR regval; |
251 | int len = TYPE_LENGTH (type); | |
252 | ||
e17a4113 | 253 | regval = extract_unsigned_integer (valbuf, len > 4 ? 4 : len, byte_order); |
d95a8903 AC |
254 | regcache_cooked_write_unsigned (regcache, RET1_REGNUM, regval); |
255 | ||
256 | if (len > 4) | |
257 | { | |
7c543f7b | 258 | regval = extract_unsigned_integer (valbuf + 4, |
e17a4113 | 259 | len - 4, byte_order); |
d95a8903 AC |
260 | regcache_cooked_write_unsigned (regcache, RET1_REGNUM + 1, regval); |
261 | } | |
262 | } | |
263 | ||
025bb325 | 264 | /* This is required by skip_prologue. The results of decoding a prologue |
d95a8903 AC |
265 | should be cached because this thrashing is getting nuts. */ |
266 | ||
cea15572 | 267 | static int |
e17a4113 UW |
268 | decode_prologue (struct gdbarch *gdbarch, |
269 | CORE_ADDR start_pc, CORE_ADDR scan_limit, | |
cea15572 | 270 | CORE_ADDR *pl_endptr, unsigned long *framelength) |
d95a8903 | 271 | { |
e17a4113 | 272 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d95a8903 AC |
273 | unsigned long framesize; |
274 | int insn; | |
275 | int op1; | |
d95a8903 | 276 | CORE_ADDR after_prologue = 0; |
cea15572 | 277 | CORE_ADDR after_push = 0; |
d95a8903 AC |
278 | CORE_ADDR after_stack_adjust = 0; |
279 | CORE_ADDR current_pc; | |
cea15572 | 280 | LONGEST return_value; |
d95a8903 AC |
281 | |
282 | framesize = 0; | |
283 | after_prologue = 0; | |
284 | ||
285 | for (current_pc = start_pc; current_pc < scan_limit; current_pc += 2) | |
286 | { | |
025bb325 | 287 | /* Check if current pc's location is readable. */ |
e17a4113 | 288 | if (!safe_read_memory_integer (current_pc, 2, byte_order, &return_value)) |
cea15572 KI |
289 | return -1; |
290 | ||
e17a4113 | 291 | insn = read_memory_unsigned_integer (current_pc, 2, byte_order); |
d95a8903 | 292 | |
cea15572 KI |
293 | if (insn == 0x0000) |
294 | break; | |
295 | ||
d95a8903 | 296 | /* If this is a 32 bit instruction, we dont want to examine its |
025bb325 | 297 | immediate data as though it were an instruction. */ |
d95a8903 AC |
298 | if (current_pc & 0x02) |
299 | { | |
025bb325 | 300 | /* Decode this instruction further. */ |
d95a8903 AC |
301 | insn &= 0x7fff; |
302 | } | |
303 | else | |
304 | { | |
d95a8903 AC |
305 | if (insn & 0x8000) |
306 | { | |
307 | if (current_pc == scan_limit) | |
308 | scan_limit += 2; /* extend the search */ | |
cea15572 | 309 | |
d95a8903 | 310 | current_pc += 2; /* skip the immediate data */ |
cea15572 | 311 | |
025bb325 | 312 | /* Check if current pc's location is readable. */ |
e17a4113 UW |
313 | if (!safe_read_memory_integer (current_pc, 2, byte_order, |
314 | &return_value)) | |
cea15572 KI |
315 | return -1; |
316 | ||
d95a8903 AC |
317 | if (insn == 0x8faf) /* add3 sp, sp, xxxx */ |
318 | /* add 16 bit sign-extended offset */ | |
319 | { | |
320 | framesize += | |
e17a4113 UW |
321 | -((short) read_memory_unsigned_integer (current_pc, |
322 | 2, byte_order)); | |
d95a8903 AC |
323 | } |
324 | else | |
325 | { | |
025bb325 | 326 | if (((insn >> 8) == 0xe4) /* ld24 r4, xxxxxx; sub sp, r4 */ |
e17a4113 UW |
327 | && safe_read_memory_integer (current_pc + 2, |
328 | 2, byte_order, | |
cea15572 | 329 | &return_value) |
7e3dd49e | 330 | && read_memory_unsigned_integer (current_pc + 2, |
e17a4113 UW |
331 | 2, byte_order) |
332 | == 0x0f24) | |
d95a8903 | 333 | { |
025bb325 | 334 | /* Subtract 24 bit sign-extended negative-offset. */ |
e17a4113 UW |
335 | insn = read_memory_unsigned_integer (current_pc - 2, |
336 | 4, byte_order); | |
d95a8903 AC |
337 | if (insn & 0x00800000) /* sign extend */ |
338 | insn |= 0xff000000; /* negative */ | |
339 | else | |
340 | insn &= 0x00ffffff; /* positive */ | |
341 | framesize += insn; | |
342 | } | |
343 | } | |
cea15572 | 344 | after_push = current_pc + 2; |
d95a8903 AC |
345 | continue; |
346 | } | |
347 | } | |
025bb325 | 348 | op1 = insn & 0xf000; /* Isolate just the first nibble. */ |
d95a8903 AC |
349 | |
350 | if ((insn & 0xf0ff) == 0x207f) | |
351 | { /* st reg, @-sp */ | |
d95a8903 | 352 | framesize += 4; |
d95a8903 AC |
353 | after_prologue = 0; |
354 | continue; | |
355 | } | |
356 | if ((insn >> 8) == 0x4f) /* addi sp, xx */ | |
025bb325 | 357 | /* Add 8 bit sign-extended offset. */ |
d95a8903 | 358 | { |
9ffbf372 | 359 | int stack_adjust = (signed char) (insn & 0xff); |
d95a8903 AC |
360 | |
361 | /* there are probably two of these stack adjustments: | |
362 | 1) A negative one in the prologue, and | |
363 | 2) A positive one in the epilogue. | |
364 | We are only interested in the first one. */ | |
365 | ||
366 | if (stack_adjust < 0) | |
367 | { | |
368 | framesize -= stack_adjust; | |
369 | after_prologue = 0; | |
370 | /* A frameless function may have no "mv fp, sp". | |
371 | In that case, this is the end of the prologue. */ | |
372 | after_stack_adjust = current_pc + 2; | |
373 | } | |
374 | continue; | |
375 | } | |
376 | if (insn == 0x1d8f) | |
377 | { /* mv fp, sp */ | |
378 | after_prologue = current_pc + 2; | |
379 | break; /* end of stack adjustments */ | |
380 | } | |
cea15572 | 381 | |
025bb325 | 382 | /* Nop looks like a branch, continue explicitly. */ |
d95a8903 AC |
383 | if (insn == 0x7000) |
384 | { | |
385 | after_prologue = current_pc + 2; | |
025bb325 | 386 | continue; /* nop occurs between pushes. */ |
d95a8903 | 387 | } |
025bb325 | 388 | /* End of prolog if any of these are trap instructions. */ |
cea15572 KI |
389 | if ((insn & 0xfff0) == 0x10f0) |
390 | { | |
391 | after_prologue = current_pc; | |
392 | break; | |
393 | } | |
025bb325 | 394 | /* End of prolog if any of these are branch instructions. */ |
d95a8903 AC |
395 | if ((op1 == 0x7000) || (op1 == 0xb000) || (op1 == 0xf000)) |
396 | { | |
397 | after_prologue = current_pc; | |
d95a8903 AC |
398 | continue; |
399 | } | |
025bb325 | 400 | /* Some of the branch instructions are mixed with other types. */ |
d95a8903 AC |
401 | if (op1 == 0x1000) |
402 | { | |
403 | int subop = insn & 0x0ff0; | |
404 | if ((subop == 0x0ec0) || (subop == 0x0fc0)) | |
405 | { | |
406 | after_prologue = current_pc; | |
d95a8903 AC |
407 | continue; /* jmp , jl */ |
408 | } | |
409 | } | |
410 | } | |
411 | ||
cea15572 KI |
412 | if (framelength) |
413 | *framelength = framesize; | |
414 | ||
d95a8903 AC |
415 | if (current_pc >= scan_limit) |
416 | { | |
417 | if (pl_endptr) | |
418 | { | |
419 | if (after_stack_adjust != 0) | |
420 | /* We did not find a "mv fp,sp", but we DID find | |
421 | a stack_adjust. Is it safe to use that as the | |
025bb325 | 422 | end of the prologue? I just don't know. */ |
d95a8903 AC |
423 | { |
424 | *pl_endptr = after_stack_adjust; | |
425 | } | |
cea15572 KI |
426 | else if (after_push != 0) |
427 | /* We did not find a "mv fp,sp", but we DID find | |
428 | a push. Is it safe to use that as the | |
025bb325 | 429 | end of the prologue? I just don't know. */ |
cea15572 KI |
430 | { |
431 | *pl_endptr = after_push; | |
432 | } | |
d95a8903 AC |
433 | else |
434 | /* We reached the end of the loop without finding the end | |
025bb325 MS |
435 | of the prologue. No way to win -- we should report |
436 | failure. The way we do that is to return the original | |
437 | start_pc. GDB will set a breakpoint at the start of | |
438 | the function (etc.) */ | |
d95a8903 AC |
439 | *pl_endptr = start_pc; |
440 | } | |
cea15572 | 441 | return 0; |
d95a8903 | 442 | } |
cea15572 | 443 | |
d95a8903 AC |
444 | if (after_prologue == 0) |
445 | after_prologue = current_pc; | |
446 | ||
447 | if (pl_endptr) | |
448 | *pl_endptr = after_prologue; | |
cea15572 KI |
449 | |
450 | return 0; | |
d95a8903 AC |
451 | } /* decode_prologue */ |
452 | ||
453 | /* Function: skip_prologue | |
025bb325 | 454 | Find end of function prologue. */ |
d95a8903 | 455 | |
cea15572 | 456 | #define DEFAULT_SEARCH_LIMIT 128 |
d95a8903 | 457 | |
63807e1d | 458 | static CORE_ADDR |
6093d2eb | 459 | m32r_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
d95a8903 | 460 | { |
e17a4113 | 461 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d95a8903 AC |
462 | CORE_ADDR func_addr, func_end; |
463 | struct symtab_and_line sal; | |
cea15572 | 464 | LONGEST return_value; |
d95a8903 | 465 | |
025bb325 | 466 | /* See what the symbol table says. */ |
d95a8903 AC |
467 | |
468 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
469 | { | |
470 | sal = find_pc_line (func_addr, 0); | |
471 | ||
472 | if (sal.line != 0 && sal.end <= func_end) | |
473 | { | |
474 | func_end = sal.end; | |
475 | } | |
476 | else | |
477 | /* Either there's no line info, or the line after the prologue is after | |
478 | the end of the function. In this case, there probably isn't a | |
479 | prologue. */ | |
480 | { | |
325fac50 | 481 | func_end = std::min (func_end, func_addr + DEFAULT_SEARCH_LIMIT); |
d95a8903 AC |
482 | } |
483 | } | |
484 | else | |
485 | func_end = pc + DEFAULT_SEARCH_LIMIT; | |
cea15572 | 486 | |
025bb325 | 487 | /* If pc's location is not readable, just quit. */ |
e17a4113 | 488 | if (!safe_read_memory_integer (pc, 4, byte_order, &return_value)) |
cea15572 KI |
489 | return pc; |
490 | ||
491 | /* Find the end of prologue. */ | |
e17a4113 | 492 | if (decode_prologue (gdbarch, pc, func_end, &sal.end, NULL) < 0) |
cea15572 KI |
493 | return pc; |
494 | ||
d95a8903 AC |
495 | return sal.end; |
496 | } | |
497 | ||
d95a8903 AC |
498 | struct m32r_unwind_cache |
499 | { | |
500 | /* The previous frame's inner most stack address. Used as this | |
501 | frame ID's stack_addr. */ | |
502 | CORE_ADDR prev_sp; | |
503 | /* The frame's base, optionally used by the high-level debug info. */ | |
504 | CORE_ADDR base; | |
505 | int size; | |
506 | /* How far the SP and r13 (FP) have been offset from the start of | |
507 | the stack frame (as defined by the previous frame's stack | |
508 | pointer). */ | |
509 | LONGEST sp_offset; | |
510 | LONGEST r13_offset; | |
511 | int uses_frame; | |
512 | /* Table indicating the location of each and every register. */ | |
513 | struct trad_frame_saved_reg *saved_regs; | |
514 | }; | |
515 | ||
516 | /* Put here the code to store, into fi->saved_regs, the addresses of | |
517 | the saved registers of frame described by FRAME_INFO. This | |
518 | includes special registers such as pc and fp saved in special ways | |
519 | in the stack frame. sp is even more special: the address we return | |
025bb325 | 520 | for it IS the sp for the next frame. */ |
d95a8903 AC |
521 | |
522 | static struct m32r_unwind_cache * | |
94afd7a6 | 523 | m32r_frame_unwind_cache (struct frame_info *this_frame, |
d95a8903 AC |
524 | void **this_prologue_cache) |
525 | { | |
cea15572 | 526 | CORE_ADDR pc, scan_limit; |
d95a8903 AC |
527 | ULONGEST prev_sp; |
528 | ULONGEST this_base; | |
22e048c9 | 529 | unsigned long op; |
d95a8903 AC |
530 | int i; |
531 | struct m32r_unwind_cache *info; | |
532 | ||
cea15572 | 533 | |
d95a8903 | 534 | if ((*this_prologue_cache)) |
9a3c8263 | 535 | return (struct m32r_unwind_cache *) (*this_prologue_cache); |
d95a8903 AC |
536 | |
537 | info = FRAME_OBSTACK_ZALLOC (struct m32r_unwind_cache); | |
538 | (*this_prologue_cache) = info; | |
94afd7a6 | 539 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
d95a8903 AC |
540 | |
541 | info->size = 0; | |
542 | info->sp_offset = 0; | |
d95a8903 | 543 | info->uses_frame = 0; |
cea15572 | 544 | |
94afd7a6 UW |
545 | scan_limit = get_frame_pc (this_frame); |
546 | for (pc = get_frame_func (this_frame); | |
cea15572 | 547 | pc > 0 && pc < scan_limit; pc += 2) |
d95a8903 AC |
548 | { |
549 | if ((pc & 2) == 0) | |
550 | { | |
94afd7a6 | 551 | op = get_frame_memory_unsigned (this_frame, pc, 4); |
d95a8903 AC |
552 | if ((op & 0x80000000) == 0x80000000) |
553 | { | |
554 | /* 32-bit instruction */ | |
555 | if ((op & 0xffff0000) == 0x8faf0000) | |
556 | { | |
557 | /* add3 sp,sp,xxxx */ | |
558 | short n = op & 0xffff; | |
559 | info->sp_offset += n; | |
560 | } | |
cea15572 | 561 | else if (((op >> 8) == 0xe4) |
94afd7a6 | 562 | && get_frame_memory_unsigned (this_frame, pc + 2, |
7e3dd49e | 563 | 2) == 0x0f24) |
d95a8903 | 564 | { |
cea15572 | 565 | /* ld24 r4, xxxxxx; sub sp, r4 */ |
d95a8903 AC |
566 | unsigned long n = op & 0xffffff; |
567 | info->sp_offset += n; | |
cea15572 | 568 | pc += 2; /* skip sub instruction */ |
d95a8903 | 569 | } |
d95a8903 | 570 | |
cea15572 KI |
571 | if (pc == scan_limit) |
572 | scan_limit += 2; /* extend the search */ | |
573 | pc += 2; /* skip the immediate data */ | |
d95a8903 AC |
574 | continue; |
575 | } | |
576 | } | |
577 | ||
578 | /* 16-bit instructions */ | |
94afd7a6 | 579 | op = get_frame_memory_unsigned (this_frame, pc, 2) & 0x7fff; |
d95a8903 AC |
580 | if ((op & 0xf0ff) == 0x207f) |
581 | { | |
582 | /* st rn, @-sp */ | |
583 | int regno = ((op >> 8) & 0xf); | |
584 | info->sp_offset -= 4; | |
585 | info->saved_regs[regno].addr = info->sp_offset; | |
586 | } | |
587 | else if ((op & 0xff00) == 0x4f00) | |
588 | { | |
589 | /* addi sp, xx */ | |
9ffbf372 | 590 | int n = (signed char) (op & 0xff); |
d95a8903 AC |
591 | info->sp_offset += n; |
592 | } | |
593 | else if (op == 0x1d8f) | |
594 | { | |
595 | /* mv fp, sp */ | |
596 | info->uses_frame = 1; | |
597 | info->r13_offset = info->sp_offset; | |
cea15572 KI |
598 | break; /* end of stack adjustments */ |
599 | } | |
600 | else if ((op & 0xfff0) == 0x10f0) | |
601 | { | |
025bb325 MS |
602 | /* End of prologue if this is a trap instruction. */ |
603 | break; /* End of stack adjustments. */ | |
d95a8903 | 604 | } |
d95a8903 AC |
605 | } |
606 | ||
607 | info->size = -info->sp_offset; | |
608 | ||
609 | /* Compute the previous frame's stack pointer (which is also the | |
610 | frame's ID's stack address), and this frame's base pointer. */ | |
611 | if (info->uses_frame) | |
612 | { | |
613 | /* The SP was moved to the FP. This indicates that a new frame | |
614 | was created. Get THIS frame's FP value by unwinding it from | |
615 | the next frame. */ | |
94afd7a6 | 616 | this_base = get_frame_register_unsigned (this_frame, M32R_FP_REGNUM); |
d95a8903 AC |
617 | /* The FP points at the last saved register. Adjust the FP back |
618 | to before the first saved register giving the SP. */ | |
619 | prev_sp = this_base + info->size; | |
620 | } | |
621 | else | |
622 | { | |
623 | /* Assume that the FP is this frame's SP but with that pushed | |
624 | stack space added back. */ | |
94afd7a6 | 625 | this_base = get_frame_register_unsigned (this_frame, M32R_SP_REGNUM); |
d95a8903 AC |
626 | prev_sp = this_base + info->size; |
627 | } | |
628 | ||
629 | /* Convert that SP/BASE into real addresses. */ | |
630 | info->prev_sp = prev_sp; | |
631 | info->base = this_base; | |
632 | ||
633 | /* Adjust all the saved registers so that they contain addresses and | |
634 | not offsets. */ | |
94afd7a6 | 635 | for (i = 0; i < gdbarch_num_regs (get_frame_arch (this_frame)) - 1; i++) |
d95a8903 AC |
636 | if (trad_frame_addr_p (info->saved_regs, i)) |
637 | info->saved_regs[i].addr = (info->prev_sp + info->saved_regs[i].addr); | |
638 | ||
639 | /* The call instruction moves the caller's PC in the callee's LR. | |
640 | Since this is an unwind, do the reverse. Copy the location of LR | |
641 | into PC (the address / regnum) so that a request for PC will be | |
642 | converted into a request for the LR. */ | |
643 | info->saved_regs[M32R_PC_REGNUM] = info->saved_regs[LR_REGNUM]; | |
644 | ||
645 | /* The previous frame's SP needed to be computed. Save the computed | |
646 | value. */ | |
647 | trad_frame_set_value (info->saved_regs, M32R_SP_REGNUM, prev_sp); | |
648 | ||
649 | return info; | |
650 | } | |
651 | ||
652 | static CORE_ADDR | |
61a1198a | 653 | m32r_read_pc (struct regcache *regcache) |
d95a8903 | 654 | { |
7e3dd49e | 655 | ULONGEST pc; |
61a1198a | 656 | regcache_cooked_read_unsigned (regcache, M32R_PC_REGNUM, &pc); |
d95a8903 AC |
657 | return pc; |
658 | } | |
659 | ||
d95a8903 AC |
660 | static CORE_ADDR |
661 | m32r_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
662 | { | |
7e3dd49e | 663 | return frame_unwind_register_unsigned (next_frame, M32R_SP_REGNUM); |
d95a8903 AC |
664 | } |
665 | ||
666 | ||
667 | static CORE_ADDR | |
7d9b040b | 668 | m32r_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
d95a8903 AC |
669 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
670 | struct value **args, CORE_ADDR sp, int struct_return, | |
671 | CORE_ADDR struct_addr) | |
672 | { | |
e17a4113 | 673 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d95a8903 AC |
674 | int stack_offset, stack_alloc; |
675 | int argreg = ARG1_REGNUM; | |
676 | int argnum; | |
677 | struct type *type; | |
678 | enum type_code typecode; | |
679 | CORE_ADDR regval; | |
16ac4ab5 | 680 | gdb_byte *val; |
ab0538b8 | 681 | gdb_byte valbuf[M32R_ARG_REGISTER_SIZE]; |
d95a8903 | 682 | int len; |
d95a8903 | 683 | |
025bb325 | 684 | /* First force sp to a 4-byte alignment. */ |
d95a8903 AC |
685 | sp = sp & ~3; |
686 | ||
687 | /* Set the return address. For the m32r, the return breakpoint is | |
688 | always at BP_ADDR. */ | |
689 | regcache_cooked_write_unsigned (regcache, LR_REGNUM, bp_addr); | |
690 | ||
691 | /* If STRUCT_RETURN is true, then the struct return address (in | |
692 | STRUCT_ADDR) will consume the first argument-passing register. | |
693 | Both adjust the register count and store that value. */ | |
694 | if (struct_return) | |
695 | { | |
696 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); | |
697 | argreg++; | |
698 | } | |
699 | ||
025bb325 | 700 | /* Now make sure there's space on the stack. */ |
d95a8903 | 701 | for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++) |
4991999e | 702 | stack_alloc += ((TYPE_LENGTH (value_type (args[argnum])) + 3) & ~3); |
025bb325 | 703 | sp -= stack_alloc; /* Make room on stack for args. */ |
d95a8903 AC |
704 | |
705 | for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++) | |
706 | { | |
4991999e | 707 | type = value_type (args[argnum]); |
d95a8903 AC |
708 | typecode = TYPE_CODE (type); |
709 | len = TYPE_LENGTH (type); | |
710 | ||
711 | memset (valbuf, 0, sizeof (valbuf)); | |
712 | ||
713 | /* Passes structures that do not fit in 2 registers by reference. */ | |
714 | if (len > 8 | |
715 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) | |
716 | { | |
e17a4113 UW |
717 | store_unsigned_integer (valbuf, 4, byte_order, |
718 | value_address (args[argnum])); | |
d95a8903 AC |
719 | typecode = TYPE_CODE_PTR; |
720 | len = 4; | |
721 | val = valbuf; | |
722 | } | |
723 | else if (len < 4) | |
724 | { | |
025bb325 | 725 | /* Value gets right-justified in the register or stack word. */ |
7e3dd49e | 726 | memcpy (valbuf + (register_size (gdbarch, argreg) - len), |
16ac4ab5 | 727 | (gdb_byte *) value_contents (args[argnum]), len); |
d95a8903 AC |
728 | val = valbuf; |
729 | } | |
730 | else | |
16ac4ab5 | 731 | val = (gdb_byte *) value_contents (args[argnum]); |
d95a8903 AC |
732 | |
733 | while (len > 0) | |
734 | { | |
735 | if (argreg > ARGN_REGNUM) | |
736 | { | |
025bb325 | 737 | /* Must go on the stack. */ |
d95a8903 AC |
738 | write_memory (sp + stack_offset, val, 4); |
739 | stack_offset += 4; | |
740 | } | |
741 | else if (argreg <= ARGN_REGNUM) | |
742 | { | |
025bb325 | 743 | /* There's room in a register. */ |
d95a8903 | 744 | regval = |
7e3dd49e | 745 | extract_unsigned_integer (val, |
e17a4113 UW |
746 | register_size (gdbarch, argreg), |
747 | byte_order); | |
d95a8903 AC |
748 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
749 | } | |
750 | ||
751 | /* Store the value 4 bytes at a time. This means that things | |
752 | larger than 4 bytes may go partly in registers and partly | |
753 | on the stack. */ | |
7e3dd49e AC |
754 | len -= register_size (gdbarch, argreg); |
755 | val += register_size (gdbarch, argreg); | |
d95a8903 AC |
756 | } |
757 | } | |
758 | ||
759 | /* Finally, update the SP register. */ | |
760 | regcache_cooked_write_unsigned (regcache, M32R_SP_REGNUM, sp); | |
761 | ||
762 | return sp; | |
763 | } | |
764 | ||
765 | ||
766 | /* Given a return value in `regbuf' with a type `valtype', | |
767 | extract and copy its value into `valbuf'. */ | |
768 | ||
769 | static void | |
770 | m32r_extract_return_value (struct type *type, struct regcache *regcache, | |
7c543f7b | 771 | gdb_byte *dst) |
d95a8903 | 772 | { |
ac7936df | 773 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 774 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d95a8903 AC |
775 | int len = TYPE_LENGTH (type); |
776 | ULONGEST tmp; | |
777 | ||
778 | /* By using store_unsigned_integer we avoid having to do | |
779 | anything special for small big-endian values. */ | |
780 | regcache_cooked_read_unsigned (regcache, RET1_REGNUM, &tmp); | |
7c543f7b | 781 | store_unsigned_integer (dst, (len > 4 ? len - 4 : len), byte_order, tmp); |
d95a8903 AC |
782 | |
783 | /* Ignore return values more than 8 bytes in size because the m32r | |
025bb325 | 784 | returns anything more than 8 bytes in the stack. */ |
d95a8903 AC |
785 | if (len > 4) |
786 | { | |
787 | regcache_cooked_read_unsigned (regcache, RET1_REGNUM + 1, &tmp); | |
7c543f7b | 788 | store_unsigned_integer (dst + len - 4, 4, byte_order, tmp); |
d95a8903 AC |
789 | } |
790 | } | |
791 | ||
63807e1d | 792 | static enum return_value_convention |
6a3a010b | 793 | m32r_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
794 | struct type *valtype, struct regcache *regcache, |
795 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
14588880 KI |
796 | { |
797 | if (TYPE_LENGTH (valtype) > 8) | |
798 | return RETURN_VALUE_STRUCT_CONVENTION; | |
799 | else | |
800 | { | |
801 | if (readbuf != NULL) | |
802 | m32r_extract_return_value (valtype, regcache, readbuf); | |
803 | if (writebuf != NULL) | |
804 | m32r_store_return_value (valtype, regcache, writebuf); | |
805 | return RETURN_VALUE_REGISTER_CONVENTION; | |
806 | } | |
807 | } | |
808 | ||
809 | ||
d95a8903 AC |
810 | |
811 | static CORE_ADDR | |
812 | m32r_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
813 | { | |
7e3dd49e | 814 | return frame_unwind_register_unsigned (next_frame, M32R_PC_REGNUM); |
d95a8903 AC |
815 | } |
816 | ||
817 | /* Given a GDB frame, determine the address of the calling function's | |
818 | frame. This will be used to create a new GDB frame struct. */ | |
819 | ||
820 | static void | |
94afd7a6 | 821 | m32r_frame_this_id (struct frame_info *this_frame, |
d95a8903 AC |
822 | void **this_prologue_cache, struct frame_id *this_id) |
823 | { | |
824 | struct m32r_unwind_cache *info | |
94afd7a6 | 825 | = m32r_frame_unwind_cache (this_frame, this_prologue_cache); |
d95a8903 AC |
826 | CORE_ADDR base; |
827 | CORE_ADDR func; | |
3b7344d5 | 828 | struct bound_minimal_symbol msym_stack; |
d95a8903 AC |
829 | struct frame_id id; |
830 | ||
831 | /* The FUNC is easy. */ | |
94afd7a6 | 832 | func = get_frame_func (this_frame); |
d95a8903 | 833 | |
d95a8903 AC |
834 | /* Check if the stack is empty. */ |
835 | msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL); | |
77e371c0 | 836 | if (msym_stack.minsym && info->base == BMSYMBOL_VALUE_ADDRESS (msym_stack)) |
d95a8903 AC |
837 | return; |
838 | ||
839 | /* Hopefully the prologue analysis either correctly determined the | |
840 | frame's base (which is the SP from the previous frame), or set | |
841 | that base to "NULL". */ | |
842 | base = info->prev_sp; | |
843 | if (base == 0) | |
844 | return; | |
845 | ||
846 | id = frame_id_build (base, func); | |
d95a8903 AC |
847 | (*this_id) = id; |
848 | } | |
849 | ||
94afd7a6 UW |
850 | static struct value * |
851 | m32r_frame_prev_register (struct frame_info *this_frame, | |
852 | void **this_prologue_cache, int regnum) | |
d95a8903 AC |
853 | { |
854 | struct m32r_unwind_cache *info | |
94afd7a6 UW |
855 | = m32r_frame_unwind_cache (this_frame, this_prologue_cache); |
856 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); | |
d95a8903 AC |
857 | } |
858 | ||
859 | static const struct frame_unwind m32r_frame_unwind = { | |
860 | NORMAL_FRAME, | |
8fbca658 | 861 | default_frame_unwind_stop_reason, |
d95a8903 | 862 | m32r_frame_this_id, |
94afd7a6 UW |
863 | m32r_frame_prev_register, |
864 | NULL, | |
865 | default_frame_sniffer | |
d95a8903 AC |
866 | }; |
867 | ||
d95a8903 | 868 | static CORE_ADDR |
94afd7a6 | 869 | m32r_frame_base_address (struct frame_info *this_frame, void **this_cache) |
d95a8903 AC |
870 | { |
871 | struct m32r_unwind_cache *info | |
94afd7a6 | 872 | = m32r_frame_unwind_cache (this_frame, this_cache); |
d95a8903 AC |
873 | return info->base; |
874 | } | |
875 | ||
876 | static const struct frame_base m32r_frame_base = { | |
877 | &m32r_frame_unwind, | |
878 | m32r_frame_base_address, | |
879 | m32r_frame_base_address, | |
880 | m32r_frame_base_address | |
881 | }; | |
882 | ||
94afd7a6 UW |
883 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy |
884 | frame. The frame ID's base needs to match the TOS value saved by | |
885 | save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */ | |
d95a8903 AC |
886 | |
887 | static struct frame_id | |
94afd7a6 | 888 | m32r_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
d95a8903 | 889 | { |
94afd7a6 UW |
890 | CORE_ADDR sp = get_frame_register_unsigned (this_frame, M32R_SP_REGNUM); |
891 | return frame_id_build (sp, get_frame_pc (this_frame)); | |
d95a8903 AC |
892 | } |
893 | ||
894 | ||
895 | static gdbarch_init_ftype m32r_gdbarch_init; | |
896 | ||
897 | static struct gdbarch * | |
898 | m32r_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
899 | { | |
900 | struct gdbarch *gdbarch; | |
901 | struct gdbarch_tdep *tdep; | |
902 | ||
903 | /* If there is already a candidate, use it. */ | |
904 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
905 | if (arches != NULL) | |
906 | return arches->gdbarch; | |
907 | ||
908 | /* Allocate space for the new architecture. */ | |
cdd238da | 909 | tdep = XCNEW (struct gdbarch_tdep); |
d95a8903 AC |
910 | gdbarch = gdbarch_alloc (&info, tdep); |
911 | ||
53375380 PA |
912 | set_gdbarch_wchar_bit (gdbarch, 16); |
913 | set_gdbarch_wchar_signed (gdbarch, 0); | |
914 | ||
d95a8903 | 915 | set_gdbarch_read_pc (gdbarch, m32r_read_pc); |
d95a8903 AC |
916 | set_gdbarch_unwind_sp (gdbarch, m32r_unwind_sp); |
917 | ||
e839132d | 918 | set_gdbarch_num_regs (gdbarch, M32R_NUM_REGS); |
d27b54ad | 919 | set_gdbarch_pc_regnum (gdbarch, M32R_PC_REGNUM); |
d95a8903 AC |
920 | set_gdbarch_sp_regnum (gdbarch, M32R_SP_REGNUM); |
921 | set_gdbarch_register_name (gdbarch, m32r_register_name); | |
922 | set_gdbarch_register_type (gdbarch, m32r_register_type); | |
923 | ||
d95a8903 | 924 | set_gdbarch_push_dummy_call (gdbarch, m32r_push_dummy_call); |
14588880 | 925 | set_gdbarch_return_value (gdbarch, m32r_return_value); |
d95a8903 AC |
926 | |
927 | set_gdbarch_skip_prologue (gdbarch, m32r_skip_prologue); | |
928 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
04180708 YQ |
929 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, m32r_breakpoint_kind_from_pc); |
930 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, m32r_sw_breakpoint_from_kind); | |
d95a8903 AC |
931 | set_gdbarch_memory_insert_breakpoint (gdbarch, |
932 | m32r_memory_insert_breakpoint); | |
933 | set_gdbarch_memory_remove_breakpoint (gdbarch, | |
934 | m32r_memory_remove_breakpoint); | |
935 | ||
d95a8903 AC |
936 | set_gdbarch_frame_align (gdbarch, m32r_frame_align); |
937 | ||
d95a8903 AC |
938 | frame_base_set_default (gdbarch, &m32r_frame_base); |
939 | ||
940 | /* Methods for saving / extracting a dummy frame's ID. The ID's | |
941 | stack address must match the SP value returned by | |
942 | PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */ | |
94afd7a6 | 943 | set_gdbarch_dummy_id (gdbarch, m32r_dummy_id); |
d95a8903 AC |
944 | |
945 | /* Return the unwound PC value. */ | |
946 | set_gdbarch_unwind_pc (gdbarch, m32r_unwind_pc); | |
947 | ||
c46b0409 KI |
948 | /* Hook in ABI-specific overrides, if they have been registered. */ |
949 | gdbarch_init_osabi (info, gdbarch); | |
950 | ||
951 | /* Hook in the default unwinders. */ | |
94afd7a6 | 952 | frame_unwind_append_unwinder (gdbarch, &m32r_frame_unwind); |
c46b0409 | 953 | |
1c772458 UW |
954 | /* Support simple overlay manager. */ |
955 | set_gdbarch_overlay_update (gdbarch, simple_overlay_update); | |
956 | ||
d95a8903 AC |
957 | return gdbarch; |
958 | } | |
959 | ||
960 | void | |
961 | _initialize_m32r_tdep (void) | |
962 | { | |
963 | register_gdbarch_init (bfd_arch_m32r, m32r_gdbarch_init); | |
964 | } |