Commit | Line | Data |
---|---|---|
d95a8903 AC |
1 | /* Target-dependent code for Renesas M32R, for GDB. |
2 | ||
0b302171 JB |
3 | Copyright (C) 1996, 1998-2005, 2007-2012 Free Software Foundation, |
4 | Inc. | |
d95a8903 AC |
5 | |
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 10 | the Free Software Foundation; either version 3 of the License, or |
d95a8903 AC |
11 | (at your option) any later version. |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
d95a8903 AC |
20 | |
21 | #include "defs.h" | |
22 | #include "frame.h" | |
23 | #include "frame-unwind.h" | |
24 | #include "frame-base.h" | |
25 | #include "symtab.h" | |
26 | #include "gdbtypes.h" | |
27 | #include "gdbcmd.h" | |
28 | #include "gdbcore.h" | |
29 | #include "gdb_string.h" | |
30 | #include "value.h" | |
31 | #include "inferior.h" | |
32 | #include "symfile.h" | |
33 | #include "objfiles.h" | |
c46b0409 | 34 | #include "osabi.h" |
d95a8903 AC |
35 | #include "language.h" |
36 | #include "arch-utils.h" | |
37 | #include "regcache.h" | |
38 | #include "trad-frame.h" | |
73e8eb51 | 39 | #include "dis-asm.h" |
d95a8903 AC |
40 | |
41 | #include "gdb_assert.h" | |
42 | ||
9b32d526 | 43 | #include "m32r-tdep.h" |
d95a8903 AC |
44 | |
45 | /* Local functions */ | |
46 | ||
47 | extern void _initialize_m32r_tdep (void); | |
48 | ||
49 | static CORE_ADDR | |
50 | m32r_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
51 | { | |
52 | /* Align to the size of an instruction (so that they can safely be | |
53 | pushed onto the stack. */ | |
54 | return sp & ~3; | |
55 | } | |
56 | ||
d95a8903 | 57 | |
9f0b0322 KI |
58 | /* Breakpoints |
59 | ||
025bb325 | 60 | The little endian mode of M32R is unique. In most of architectures, |
9f0b0322 KI |
61 | two 16-bit instructions, A and B, are placed as the following: |
62 | ||
63 | Big endian: | |
64 | A0 A1 B0 B1 | |
65 | ||
66 | Little endian: | |
67 | A1 A0 B1 B0 | |
68 | ||
69 | In M32R, they are placed like this: | |
70 | ||
71 | Big endian: | |
72 | A0 A1 B0 B1 | |
73 | ||
74 | Little endian: | |
75 | B1 B0 A1 A0 | |
76 | ||
77 | This is because M32R always fetches instructions in 32-bit. | |
78 | ||
025bb325 | 79 | The following functions take care of this behavior. */ |
d95a8903 AC |
80 | |
81 | static int | |
ae4b2284 MD |
82 | m32r_memory_insert_breakpoint (struct gdbarch *gdbarch, |
83 | struct bp_target_info *bp_tgt) | |
d95a8903 | 84 | { |
8181d85f | 85 | CORE_ADDR addr = bp_tgt->placed_address; |
d95a8903 | 86 | int val; |
16ac4ab5 | 87 | gdb_byte buf[4]; |
35c63cd8 | 88 | gdb_byte contents_cache[4]; |
16ac4ab5 | 89 | gdb_byte bp_entry[] = { 0x10, 0xf1 }; /* dpt */ |
d95a8903 AC |
90 | |
91 | /* Save the memory contents. */ | |
9f0b0322 | 92 | val = target_read_memory (addr & 0xfffffffc, contents_cache, 4); |
d95a8903 AC |
93 | if (val != 0) |
94 | return val; /* return error */ | |
95 | ||
35c63cd8 | 96 | memcpy (bp_tgt->shadow_contents, contents_cache, 4); |
8181d85f DJ |
97 | bp_tgt->placed_size = bp_tgt->shadow_len = 4; |
98 | ||
d95a8903 | 99 | /* Determine appropriate breakpoint contents and size for this address. */ |
ae4b2284 | 100 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
d95a8903 | 101 | { |
9f0b0322 | 102 | if ((addr & 3) == 0) |
d95a8903 | 103 | { |
9f0b0322 KI |
104 | buf[0] = bp_entry[0]; |
105 | buf[1] = bp_entry[1]; | |
106 | buf[2] = contents_cache[2] & 0x7f; | |
107 | buf[3] = contents_cache[3]; | |
d95a8903 AC |
108 | } |
109 | else | |
110 | { | |
9f0b0322 KI |
111 | buf[0] = contents_cache[0]; |
112 | buf[1] = contents_cache[1]; | |
113 | buf[2] = bp_entry[0]; | |
114 | buf[3] = bp_entry[1]; | |
d95a8903 AC |
115 | } |
116 | } | |
9f0b0322 KI |
117 | else /* little-endian */ |
118 | { | |
119 | if ((addr & 3) == 0) | |
d95a8903 | 120 | { |
9f0b0322 KI |
121 | buf[0] = contents_cache[0]; |
122 | buf[1] = contents_cache[1] & 0x7f; | |
123 | buf[2] = bp_entry[1]; | |
124 | buf[3] = bp_entry[0]; | |
d95a8903 AC |
125 | } |
126 | else | |
127 | { | |
9f0b0322 KI |
128 | buf[0] = bp_entry[1]; |
129 | buf[1] = bp_entry[0]; | |
130 | buf[2] = contents_cache[2]; | |
131 | buf[3] = contents_cache[3]; | |
d95a8903 AC |
132 | } |
133 | } | |
134 | ||
135 | /* Write the breakpoint. */ | |
9f0b0322 | 136 | val = target_write_memory (addr & 0xfffffffc, buf, 4); |
d95a8903 AC |
137 | return val; |
138 | } | |
139 | ||
140 | static int | |
ae4b2284 MD |
141 | m32r_memory_remove_breakpoint (struct gdbarch *gdbarch, |
142 | struct bp_target_info *bp_tgt) | |
d95a8903 | 143 | { |
8181d85f | 144 | CORE_ADDR addr = bp_tgt->placed_address; |
d95a8903 | 145 | int val; |
16ac4ab5 | 146 | gdb_byte buf[4]; |
8181d85f | 147 | gdb_byte *contents_cache = bp_tgt->shadow_contents; |
d95a8903 | 148 | |
9f0b0322 KI |
149 | buf[0] = contents_cache[0]; |
150 | buf[1] = contents_cache[1]; | |
151 | buf[2] = contents_cache[2]; | |
152 | buf[3] = contents_cache[3]; | |
153 | ||
154 | /* Remove parallel bit. */ | |
ae4b2284 | 155 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
d95a8903 | 156 | { |
9f0b0322 KI |
157 | if ((buf[0] & 0x80) == 0 && (buf[2] & 0x80) != 0) |
158 | buf[2] &= 0x7f; | |
d95a8903 | 159 | } |
9f0b0322 | 160 | else /* little-endian */ |
d95a8903 | 161 | { |
9f0b0322 KI |
162 | if ((buf[3] & 0x80) == 0 && (buf[1] & 0x80) != 0) |
163 | buf[1] &= 0x7f; | |
d95a8903 AC |
164 | } |
165 | ||
166 | /* Write contents. */ | |
dd110abf | 167 | val = target_write_raw_memory (addr & 0xfffffffc, buf, 4); |
d95a8903 AC |
168 | return val; |
169 | } | |
170 | ||
16ac4ab5 | 171 | static const gdb_byte * |
025bb325 MS |
172 | m32r_breakpoint_from_pc (struct gdbarch *gdbarch, |
173 | CORE_ADDR *pcptr, int *lenptr) | |
d95a8903 | 174 | { |
025bb325 MS |
175 | static gdb_byte be_bp_entry[] = { |
176 | 0x10, 0xf1, 0x70, 0x00 | |
177 | }; /* dpt -> nop */ | |
178 | static gdb_byte le_bp_entry[] = { | |
179 | 0x00, 0x70, 0xf1, 0x10 | |
180 | }; /* dpt -> nop */ | |
16ac4ab5 | 181 | gdb_byte *bp; |
d95a8903 AC |
182 | |
183 | /* Determine appropriate breakpoint. */ | |
67d57894 | 184 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
d95a8903 AC |
185 | { |
186 | if ((*pcptr & 3) == 0) | |
187 | { | |
9f0b0322 KI |
188 | bp = be_bp_entry; |
189 | *lenptr = 4; | |
d95a8903 AC |
190 | } |
191 | else | |
192 | { | |
9f0b0322 KI |
193 | bp = be_bp_entry; |
194 | *lenptr = 2; | |
d95a8903 AC |
195 | } |
196 | } | |
197 | else | |
198 | { | |
199 | if ((*pcptr & 3) == 0) | |
200 | { | |
9f0b0322 KI |
201 | bp = le_bp_entry; |
202 | *lenptr = 4; | |
d95a8903 AC |
203 | } |
204 | else | |
205 | { | |
9f0b0322 KI |
206 | bp = le_bp_entry + 2; |
207 | *lenptr = 2; | |
d95a8903 AC |
208 | } |
209 | } | |
210 | ||
211 | return bp; | |
212 | } | |
213 | ||
214 | ||
215 | char *m32r_register_names[] = { | |
216 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
217 | "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp", | |
218 | "psw", "cbr", "spi", "spu", "bpc", "pc", "accl", "acch", | |
219 | "evb" | |
220 | }; | |
221 | ||
d95a8903 | 222 | static const char * |
d93859e2 | 223 | m32r_register_name (struct gdbarch *gdbarch, int reg_nr) |
d95a8903 AC |
224 | { |
225 | if (reg_nr < 0) | |
226 | return NULL; | |
9b32d526 | 227 | if (reg_nr >= M32R_NUM_REGS) |
d95a8903 AC |
228 | return NULL; |
229 | return m32r_register_names[reg_nr]; | |
230 | } | |
231 | ||
232 | ||
233 | /* Return the GDB type object for the "standard" data type | |
234 | of data in register N. */ | |
235 | ||
236 | static struct type * | |
237 | m32r_register_type (struct gdbarch *gdbarch, int reg_nr) | |
238 | { | |
239 | if (reg_nr == M32R_PC_REGNUM) | |
0dfff4cb | 240 | return builtin_type (gdbarch)->builtin_func_ptr; |
d95a8903 | 241 | else if (reg_nr == M32R_SP_REGNUM || reg_nr == M32R_FP_REGNUM) |
0dfff4cb | 242 | return builtin_type (gdbarch)->builtin_data_ptr; |
d95a8903 | 243 | else |
df4df182 | 244 | return builtin_type (gdbarch)->builtin_int32; |
d95a8903 AC |
245 | } |
246 | ||
247 | ||
248 | /* Write into appropriate registers a function return value | |
025bb325 | 249 | of type TYPE, given in virtual format. |
d95a8903 | 250 | |
025bb325 | 251 | Things always get returned in RET1_REGNUM, RET2_REGNUM. */ |
d95a8903 AC |
252 | |
253 | static void | |
254 | m32r_store_return_value (struct type *type, struct regcache *regcache, | |
255 | const void *valbuf) | |
256 | { | |
e17a4113 UW |
257 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
258 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
d95a8903 AC |
259 | CORE_ADDR regval; |
260 | int len = TYPE_LENGTH (type); | |
261 | ||
e17a4113 | 262 | regval = extract_unsigned_integer (valbuf, len > 4 ? 4 : len, byte_order); |
d95a8903 AC |
263 | regcache_cooked_write_unsigned (regcache, RET1_REGNUM, regval); |
264 | ||
265 | if (len > 4) | |
266 | { | |
e17a4113 UW |
267 | regval = extract_unsigned_integer ((gdb_byte *) valbuf + 4, |
268 | len - 4, byte_order); | |
d95a8903 AC |
269 | regcache_cooked_write_unsigned (regcache, RET1_REGNUM + 1, regval); |
270 | } | |
271 | } | |
272 | ||
025bb325 | 273 | /* This is required by skip_prologue. The results of decoding a prologue |
d95a8903 AC |
274 | should be cached because this thrashing is getting nuts. */ |
275 | ||
cea15572 | 276 | static int |
e17a4113 UW |
277 | decode_prologue (struct gdbarch *gdbarch, |
278 | CORE_ADDR start_pc, CORE_ADDR scan_limit, | |
cea15572 | 279 | CORE_ADDR *pl_endptr, unsigned long *framelength) |
d95a8903 | 280 | { |
e17a4113 | 281 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d95a8903 AC |
282 | unsigned long framesize; |
283 | int insn; | |
284 | int op1; | |
d95a8903 | 285 | CORE_ADDR after_prologue = 0; |
cea15572 | 286 | CORE_ADDR after_push = 0; |
d95a8903 AC |
287 | CORE_ADDR after_stack_adjust = 0; |
288 | CORE_ADDR current_pc; | |
cea15572 | 289 | LONGEST return_value; |
d95a8903 AC |
290 | |
291 | framesize = 0; | |
292 | after_prologue = 0; | |
293 | ||
294 | for (current_pc = start_pc; current_pc < scan_limit; current_pc += 2) | |
295 | { | |
025bb325 | 296 | /* Check if current pc's location is readable. */ |
e17a4113 | 297 | if (!safe_read_memory_integer (current_pc, 2, byte_order, &return_value)) |
cea15572 KI |
298 | return -1; |
299 | ||
e17a4113 | 300 | insn = read_memory_unsigned_integer (current_pc, 2, byte_order); |
d95a8903 | 301 | |
cea15572 KI |
302 | if (insn == 0x0000) |
303 | break; | |
304 | ||
d95a8903 | 305 | /* If this is a 32 bit instruction, we dont want to examine its |
025bb325 | 306 | immediate data as though it were an instruction. */ |
d95a8903 AC |
307 | if (current_pc & 0x02) |
308 | { | |
025bb325 | 309 | /* Decode this instruction further. */ |
d95a8903 AC |
310 | insn &= 0x7fff; |
311 | } | |
312 | else | |
313 | { | |
d95a8903 AC |
314 | if (insn & 0x8000) |
315 | { | |
316 | if (current_pc == scan_limit) | |
317 | scan_limit += 2; /* extend the search */ | |
cea15572 | 318 | |
d95a8903 | 319 | current_pc += 2; /* skip the immediate data */ |
cea15572 | 320 | |
025bb325 | 321 | /* Check if current pc's location is readable. */ |
e17a4113 UW |
322 | if (!safe_read_memory_integer (current_pc, 2, byte_order, |
323 | &return_value)) | |
cea15572 KI |
324 | return -1; |
325 | ||
d95a8903 AC |
326 | if (insn == 0x8faf) /* add3 sp, sp, xxxx */ |
327 | /* add 16 bit sign-extended offset */ | |
328 | { | |
329 | framesize += | |
e17a4113 UW |
330 | -((short) read_memory_unsigned_integer (current_pc, |
331 | 2, byte_order)); | |
d95a8903 AC |
332 | } |
333 | else | |
334 | { | |
025bb325 | 335 | if (((insn >> 8) == 0xe4) /* ld24 r4, xxxxxx; sub sp, r4 */ |
e17a4113 UW |
336 | && safe_read_memory_integer (current_pc + 2, |
337 | 2, byte_order, | |
cea15572 | 338 | &return_value) |
7e3dd49e | 339 | && read_memory_unsigned_integer (current_pc + 2, |
e17a4113 UW |
340 | 2, byte_order) |
341 | == 0x0f24) | |
d95a8903 | 342 | { |
025bb325 | 343 | /* Subtract 24 bit sign-extended negative-offset. */ |
e17a4113 UW |
344 | insn = read_memory_unsigned_integer (current_pc - 2, |
345 | 4, byte_order); | |
d95a8903 AC |
346 | if (insn & 0x00800000) /* sign extend */ |
347 | insn |= 0xff000000; /* negative */ | |
348 | else | |
349 | insn &= 0x00ffffff; /* positive */ | |
350 | framesize += insn; | |
351 | } | |
352 | } | |
cea15572 | 353 | after_push = current_pc + 2; |
d95a8903 AC |
354 | continue; |
355 | } | |
356 | } | |
025bb325 | 357 | op1 = insn & 0xf000; /* Isolate just the first nibble. */ |
d95a8903 AC |
358 | |
359 | if ((insn & 0xf0ff) == 0x207f) | |
360 | { /* st reg, @-sp */ | |
361 | int regno; | |
362 | framesize += 4; | |
363 | regno = ((insn >> 8) & 0xf); | |
364 | after_prologue = 0; | |
365 | continue; | |
366 | } | |
367 | if ((insn >> 8) == 0x4f) /* addi sp, xx */ | |
025bb325 | 368 | /* Add 8 bit sign-extended offset. */ |
d95a8903 | 369 | { |
9ffbf372 | 370 | int stack_adjust = (signed char) (insn & 0xff); |
d95a8903 AC |
371 | |
372 | /* there are probably two of these stack adjustments: | |
373 | 1) A negative one in the prologue, and | |
374 | 2) A positive one in the epilogue. | |
375 | We are only interested in the first one. */ | |
376 | ||
377 | if (stack_adjust < 0) | |
378 | { | |
379 | framesize -= stack_adjust; | |
380 | after_prologue = 0; | |
381 | /* A frameless function may have no "mv fp, sp". | |
382 | In that case, this is the end of the prologue. */ | |
383 | after_stack_adjust = current_pc + 2; | |
384 | } | |
385 | continue; | |
386 | } | |
387 | if (insn == 0x1d8f) | |
388 | { /* mv fp, sp */ | |
389 | after_prologue = current_pc + 2; | |
390 | break; /* end of stack adjustments */ | |
391 | } | |
cea15572 | 392 | |
025bb325 | 393 | /* Nop looks like a branch, continue explicitly. */ |
d95a8903 AC |
394 | if (insn == 0x7000) |
395 | { | |
396 | after_prologue = current_pc + 2; | |
025bb325 | 397 | continue; /* nop occurs between pushes. */ |
d95a8903 | 398 | } |
025bb325 | 399 | /* End of prolog if any of these are trap instructions. */ |
cea15572 KI |
400 | if ((insn & 0xfff0) == 0x10f0) |
401 | { | |
402 | after_prologue = current_pc; | |
403 | break; | |
404 | } | |
025bb325 | 405 | /* End of prolog if any of these are branch instructions. */ |
d95a8903 AC |
406 | if ((op1 == 0x7000) || (op1 == 0xb000) || (op1 == 0xf000)) |
407 | { | |
408 | after_prologue = current_pc; | |
d95a8903 AC |
409 | continue; |
410 | } | |
025bb325 | 411 | /* Some of the branch instructions are mixed with other types. */ |
d95a8903 AC |
412 | if (op1 == 0x1000) |
413 | { | |
414 | int subop = insn & 0x0ff0; | |
415 | if ((subop == 0x0ec0) || (subop == 0x0fc0)) | |
416 | { | |
417 | after_prologue = current_pc; | |
d95a8903 AC |
418 | continue; /* jmp , jl */ |
419 | } | |
420 | } | |
421 | } | |
422 | ||
cea15572 KI |
423 | if (framelength) |
424 | *framelength = framesize; | |
425 | ||
d95a8903 AC |
426 | if (current_pc >= scan_limit) |
427 | { | |
428 | if (pl_endptr) | |
429 | { | |
430 | if (after_stack_adjust != 0) | |
431 | /* We did not find a "mv fp,sp", but we DID find | |
432 | a stack_adjust. Is it safe to use that as the | |
025bb325 | 433 | end of the prologue? I just don't know. */ |
d95a8903 AC |
434 | { |
435 | *pl_endptr = after_stack_adjust; | |
436 | } | |
cea15572 KI |
437 | else if (after_push != 0) |
438 | /* We did not find a "mv fp,sp", but we DID find | |
439 | a push. Is it safe to use that as the | |
025bb325 | 440 | end of the prologue? I just don't know. */ |
cea15572 KI |
441 | { |
442 | *pl_endptr = after_push; | |
443 | } | |
d95a8903 AC |
444 | else |
445 | /* We reached the end of the loop without finding the end | |
025bb325 MS |
446 | of the prologue. No way to win -- we should report |
447 | failure. The way we do that is to return the original | |
448 | start_pc. GDB will set a breakpoint at the start of | |
449 | the function (etc.) */ | |
d95a8903 AC |
450 | *pl_endptr = start_pc; |
451 | } | |
cea15572 | 452 | return 0; |
d95a8903 | 453 | } |
cea15572 | 454 | |
d95a8903 AC |
455 | if (after_prologue == 0) |
456 | after_prologue = current_pc; | |
457 | ||
458 | if (pl_endptr) | |
459 | *pl_endptr = after_prologue; | |
cea15572 KI |
460 | |
461 | return 0; | |
d95a8903 AC |
462 | } /* decode_prologue */ |
463 | ||
464 | /* Function: skip_prologue | |
025bb325 | 465 | Find end of function prologue. */ |
d95a8903 | 466 | |
cea15572 | 467 | #define DEFAULT_SEARCH_LIMIT 128 |
d95a8903 | 468 | |
63807e1d | 469 | static CORE_ADDR |
6093d2eb | 470 | m32r_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
d95a8903 | 471 | { |
e17a4113 | 472 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d95a8903 AC |
473 | CORE_ADDR func_addr, func_end; |
474 | struct symtab_and_line sal; | |
cea15572 | 475 | LONGEST return_value; |
d95a8903 | 476 | |
025bb325 | 477 | /* See what the symbol table says. */ |
d95a8903 AC |
478 | |
479 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
480 | { | |
481 | sal = find_pc_line (func_addr, 0); | |
482 | ||
483 | if (sal.line != 0 && sal.end <= func_end) | |
484 | { | |
485 | func_end = sal.end; | |
486 | } | |
487 | else | |
488 | /* Either there's no line info, or the line after the prologue is after | |
489 | the end of the function. In this case, there probably isn't a | |
490 | prologue. */ | |
491 | { | |
492 | func_end = min (func_end, func_addr + DEFAULT_SEARCH_LIMIT); | |
493 | } | |
494 | } | |
495 | else | |
496 | func_end = pc + DEFAULT_SEARCH_LIMIT; | |
cea15572 | 497 | |
025bb325 | 498 | /* If pc's location is not readable, just quit. */ |
e17a4113 | 499 | if (!safe_read_memory_integer (pc, 4, byte_order, &return_value)) |
cea15572 KI |
500 | return pc; |
501 | ||
502 | /* Find the end of prologue. */ | |
e17a4113 | 503 | if (decode_prologue (gdbarch, pc, func_end, &sal.end, NULL) < 0) |
cea15572 KI |
504 | return pc; |
505 | ||
d95a8903 AC |
506 | return sal.end; |
507 | } | |
508 | ||
d95a8903 AC |
509 | struct m32r_unwind_cache |
510 | { | |
511 | /* The previous frame's inner most stack address. Used as this | |
512 | frame ID's stack_addr. */ | |
513 | CORE_ADDR prev_sp; | |
514 | /* The frame's base, optionally used by the high-level debug info. */ | |
515 | CORE_ADDR base; | |
516 | int size; | |
517 | /* How far the SP and r13 (FP) have been offset from the start of | |
518 | the stack frame (as defined by the previous frame's stack | |
519 | pointer). */ | |
520 | LONGEST sp_offset; | |
521 | LONGEST r13_offset; | |
522 | int uses_frame; | |
523 | /* Table indicating the location of each and every register. */ | |
524 | struct trad_frame_saved_reg *saved_regs; | |
525 | }; | |
526 | ||
527 | /* Put here the code to store, into fi->saved_regs, the addresses of | |
528 | the saved registers of frame described by FRAME_INFO. This | |
529 | includes special registers such as pc and fp saved in special ways | |
530 | in the stack frame. sp is even more special: the address we return | |
025bb325 | 531 | for it IS the sp for the next frame. */ |
d95a8903 AC |
532 | |
533 | static struct m32r_unwind_cache * | |
94afd7a6 | 534 | m32r_frame_unwind_cache (struct frame_info *this_frame, |
d95a8903 AC |
535 | void **this_prologue_cache) |
536 | { | |
cea15572 | 537 | CORE_ADDR pc, scan_limit; |
d95a8903 AC |
538 | ULONGEST prev_sp; |
539 | ULONGEST this_base; | |
22e048c9 | 540 | unsigned long op; |
d95a8903 AC |
541 | int i; |
542 | struct m32r_unwind_cache *info; | |
543 | ||
cea15572 | 544 | |
d95a8903 AC |
545 | if ((*this_prologue_cache)) |
546 | return (*this_prologue_cache); | |
547 | ||
548 | info = FRAME_OBSTACK_ZALLOC (struct m32r_unwind_cache); | |
549 | (*this_prologue_cache) = info; | |
94afd7a6 | 550 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
d95a8903 AC |
551 | |
552 | info->size = 0; | |
553 | info->sp_offset = 0; | |
d95a8903 | 554 | info->uses_frame = 0; |
cea15572 | 555 | |
94afd7a6 UW |
556 | scan_limit = get_frame_pc (this_frame); |
557 | for (pc = get_frame_func (this_frame); | |
cea15572 | 558 | pc > 0 && pc < scan_limit; pc += 2) |
d95a8903 AC |
559 | { |
560 | if ((pc & 2) == 0) | |
561 | { | |
94afd7a6 | 562 | op = get_frame_memory_unsigned (this_frame, pc, 4); |
d95a8903 AC |
563 | if ((op & 0x80000000) == 0x80000000) |
564 | { | |
565 | /* 32-bit instruction */ | |
566 | if ((op & 0xffff0000) == 0x8faf0000) | |
567 | { | |
568 | /* add3 sp,sp,xxxx */ | |
569 | short n = op & 0xffff; | |
570 | info->sp_offset += n; | |
571 | } | |
cea15572 | 572 | else if (((op >> 8) == 0xe4) |
94afd7a6 | 573 | && get_frame_memory_unsigned (this_frame, pc + 2, |
7e3dd49e | 574 | 2) == 0x0f24) |
d95a8903 | 575 | { |
cea15572 | 576 | /* ld24 r4, xxxxxx; sub sp, r4 */ |
d95a8903 AC |
577 | unsigned long n = op & 0xffffff; |
578 | info->sp_offset += n; | |
cea15572 | 579 | pc += 2; /* skip sub instruction */ |
d95a8903 | 580 | } |
d95a8903 | 581 | |
cea15572 KI |
582 | if (pc == scan_limit) |
583 | scan_limit += 2; /* extend the search */ | |
584 | pc += 2; /* skip the immediate data */ | |
d95a8903 AC |
585 | continue; |
586 | } | |
587 | } | |
588 | ||
589 | /* 16-bit instructions */ | |
94afd7a6 | 590 | op = get_frame_memory_unsigned (this_frame, pc, 2) & 0x7fff; |
d95a8903 AC |
591 | if ((op & 0xf0ff) == 0x207f) |
592 | { | |
593 | /* st rn, @-sp */ | |
594 | int regno = ((op >> 8) & 0xf); | |
595 | info->sp_offset -= 4; | |
596 | info->saved_regs[regno].addr = info->sp_offset; | |
597 | } | |
598 | else if ((op & 0xff00) == 0x4f00) | |
599 | { | |
600 | /* addi sp, xx */ | |
9ffbf372 | 601 | int n = (signed char) (op & 0xff); |
d95a8903 AC |
602 | info->sp_offset += n; |
603 | } | |
604 | else if (op == 0x1d8f) | |
605 | { | |
606 | /* mv fp, sp */ | |
607 | info->uses_frame = 1; | |
608 | info->r13_offset = info->sp_offset; | |
cea15572 KI |
609 | break; /* end of stack adjustments */ |
610 | } | |
611 | else if ((op & 0xfff0) == 0x10f0) | |
612 | { | |
025bb325 MS |
613 | /* End of prologue if this is a trap instruction. */ |
614 | break; /* End of stack adjustments. */ | |
d95a8903 | 615 | } |
d95a8903 AC |
616 | } |
617 | ||
618 | info->size = -info->sp_offset; | |
619 | ||
620 | /* Compute the previous frame's stack pointer (which is also the | |
621 | frame's ID's stack address), and this frame's base pointer. */ | |
622 | if (info->uses_frame) | |
623 | { | |
624 | /* The SP was moved to the FP. This indicates that a new frame | |
625 | was created. Get THIS frame's FP value by unwinding it from | |
626 | the next frame. */ | |
94afd7a6 | 627 | this_base = get_frame_register_unsigned (this_frame, M32R_FP_REGNUM); |
d95a8903 AC |
628 | /* The FP points at the last saved register. Adjust the FP back |
629 | to before the first saved register giving the SP. */ | |
630 | prev_sp = this_base + info->size; | |
631 | } | |
632 | else | |
633 | { | |
634 | /* Assume that the FP is this frame's SP but with that pushed | |
635 | stack space added back. */ | |
94afd7a6 | 636 | this_base = get_frame_register_unsigned (this_frame, M32R_SP_REGNUM); |
d95a8903 AC |
637 | prev_sp = this_base + info->size; |
638 | } | |
639 | ||
640 | /* Convert that SP/BASE into real addresses. */ | |
641 | info->prev_sp = prev_sp; | |
642 | info->base = this_base; | |
643 | ||
644 | /* Adjust all the saved registers so that they contain addresses and | |
645 | not offsets. */ | |
94afd7a6 | 646 | for (i = 0; i < gdbarch_num_regs (get_frame_arch (this_frame)) - 1; i++) |
d95a8903 AC |
647 | if (trad_frame_addr_p (info->saved_regs, i)) |
648 | info->saved_regs[i].addr = (info->prev_sp + info->saved_regs[i].addr); | |
649 | ||
650 | /* The call instruction moves the caller's PC in the callee's LR. | |
651 | Since this is an unwind, do the reverse. Copy the location of LR | |
652 | into PC (the address / regnum) so that a request for PC will be | |
653 | converted into a request for the LR. */ | |
654 | info->saved_regs[M32R_PC_REGNUM] = info->saved_regs[LR_REGNUM]; | |
655 | ||
656 | /* The previous frame's SP needed to be computed. Save the computed | |
657 | value. */ | |
658 | trad_frame_set_value (info->saved_regs, M32R_SP_REGNUM, prev_sp); | |
659 | ||
660 | return info; | |
661 | } | |
662 | ||
663 | static CORE_ADDR | |
61a1198a | 664 | m32r_read_pc (struct regcache *regcache) |
d95a8903 | 665 | { |
7e3dd49e | 666 | ULONGEST pc; |
61a1198a | 667 | regcache_cooked_read_unsigned (regcache, M32R_PC_REGNUM, &pc); |
d95a8903 AC |
668 | return pc; |
669 | } | |
670 | ||
671 | static void | |
61a1198a | 672 | m32r_write_pc (struct regcache *regcache, CORE_ADDR val) |
d95a8903 | 673 | { |
61a1198a | 674 | regcache_cooked_write_unsigned (regcache, M32R_PC_REGNUM, val); |
d95a8903 AC |
675 | } |
676 | ||
677 | static CORE_ADDR | |
678 | m32r_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
679 | { | |
7e3dd49e | 680 | return frame_unwind_register_unsigned (next_frame, M32R_SP_REGNUM); |
d95a8903 AC |
681 | } |
682 | ||
683 | ||
684 | static CORE_ADDR | |
7d9b040b | 685 | m32r_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
d95a8903 AC |
686 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
687 | struct value **args, CORE_ADDR sp, int struct_return, | |
688 | CORE_ADDR struct_addr) | |
689 | { | |
e17a4113 | 690 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d95a8903 AC |
691 | int stack_offset, stack_alloc; |
692 | int argreg = ARG1_REGNUM; | |
693 | int argnum; | |
694 | struct type *type; | |
695 | enum type_code typecode; | |
696 | CORE_ADDR regval; | |
16ac4ab5 KI |
697 | gdb_byte *val; |
698 | gdb_byte valbuf[MAX_REGISTER_SIZE]; | |
d95a8903 | 699 | int len; |
d95a8903 | 700 | |
025bb325 | 701 | /* First force sp to a 4-byte alignment. */ |
d95a8903 AC |
702 | sp = sp & ~3; |
703 | ||
704 | /* Set the return address. For the m32r, the return breakpoint is | |
705 | always at BP_ADDR. */ | |
706 | regcache_cooked_write_unsigned (regcache, LR_REGNUM, bp_addr); | |
707 | ||
708 | /* If STRUCT_RETURN is true, then the struct return address (in | |
709 | STRUCT_ADDR) will consume the first argument-passing register. | |
710 | Both adjust the register count and store that value. */ | |
711 | if (struct_return) | |
712 | { | |
713 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); | |
714 | argreg++; | |
715 | } | |
716 | ||
025bb325 | 717 | /* Now make sure there's space on the stack. */ |
d95a8903 | 718 | for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++) |
4991999e | 719 | stack_alloc += ((TYPE_LENGTH (value_type (args[argnum])) + 3) & ~3); |
025bb325 | 720 | sp -= stack_alloc; /* Make room on stack for args. */ |
d95a8903 AC |
721 | |
722 | for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++) | |
723 | { | |
4991999e | 724 | type = value_type (args[argnum]); |
d95a8903 AC |
725 | typecode = TYPE_CODE (type); |
726 | len = TYPE_LENGTH (type); | |
727 | ||
728 | memset (valbuf, 0, sizeof (valbuf)); | |
729 | ||
730 | /* Passes structures that do not fit in 2 registers by reference. */ | |
731 | if (len > 8 | |
732 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) | |
733 | { | |
e17a4113 UW |
734 | store_unsigned_integer (valbuf, 4, byte_order, |
735 | value_address (args[argnum])); | |
d95a8903 AC |
736 | typecode = TYPE_CODE_PTR; |
737 | len = 4; | |
738 | val = valbuf; | |
739 | } | |
740 | else if (len < 4) | |
741 | { | |
025bb325 | 742 | /* Value gets right-justified in the register or stack word. */ |
7e3dd49e | 743 | memcpy (valbuf + (register_size (gdbarch, argreg) - len), |
16ac4ab5 | 744 | (gdb_byte *) value_contents (args[argnum]), len); |
d95a8903 AC |
745 | val = valbuf; |
746 | } | |
747 | else | |
16ac4ab5 | 748 | val = (gdb_byte *) value_contents (args[argnum]); |
d95a8903 AC |
749 | |
750 | while (len > 0) | |
751 | { | |
752 | if (argreg > ARGN_REGNUM) | |
753 | { | |
025bb325 | 754 | /* Must go on the stack. */ |
d95a8903 AC |
755 | write_memory (sp + stack_offset, val, 4); |
756 | stack_offset += 4; | |
757 | } | |
758 | else if (argreg <= ARGN_REGNUM) | |
759 | { | |
025bb325 | 760 | /* There's room in a register. */ |
d95a8903 | 761 | regval = |
7e3dd49e | 762 | extract_unsigned_integer (val, |
e17a4113 UW |
763 | register_size (gdbarch, argreg), |
764 | byte_order); | |
d95a8903 AC |
765 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
766 | } | |
767 | ||
768 | /* Store the value 4 bytes at a time. This means that things | |
769 | larger than 4 bytes may go partly in registers and partly | |
770 | on the stack. */ | |
7e3dd49e AC |
771 | len -= register_size (gdbarch, argreg); |
772 | val += register_size (gdbarch, argreg); | |
d95a8903 AC |
773 | } |
774 | } | |
775 | ||
776 | /* Finally, update the SP register. */ | |
777 | regcache_cooked_write_unsigned (regcache, M32R_SP_REGNUM, sp); | |
778 | ||
779 | return sp; | |
780 | } | |
781 | ||
782 | ||
783 | /* Given a return value in `regbuf' with a type `valtype', | |
784 | extract and copy its value into `valbuf'. */ | |
785 | ||
786 | static void | |
787 | m32r_extract_return_value (struct type *type, struct regcache *regcache, | |
788 | void *dst) | |
789 | { | |
e17a4113 UW |
790 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
791 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
d95a8903 AC |
792 | bfd_byte *valbuf = dst; |
793 | int len = TYPE_LENGTH (type); | |
794 | ULONGEST tmp; | |
795 | ||
796 | /* By using store_unsigned_integer we avoid having to do | |
797 | anything special for small big-endian values. */ | |
798 | regcache_cooked_read_unsigned (regcache, RET1_REGNUM, &tmp); | |
e17a4113 | 799 | store_unsigned_integer (valbuf, (len > 4 ? len - 4 : len), byte_order, tmp); |
d95a8903 AC |
800 | |
801 | /* Ignore return values more than 8 bytes in size because the m32r | |
025bb325 | 802 | returns anything more than 8 bytes in the stack. */ |
d95a8903 AC |
803 | if (len > 4) |
804 | { | |
805 | regcache_cooked_read_unsigned (regcache, RET1_REGNUM + 1, &tmp); | |
e17a4113 | 806 | store_unsigned_integer (valbuf + len - 4, 4, byte_order, tmp); |
d95a8903 AC |
807 | } |
808 | } | |
809 | ||
63807e1d | 810 | static enum return_value_convention |
6a3a010b | 811 | m32r_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
812 | struct type *valtype, struct regcache *regcache, |
813 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
14588880 KI |
814 | { |
815 | if (TYPE_LENGTH (valtype) > 8) | |
816 | return RETURN_VALUE_STRUCT_CONVENTION; | |
817 | else | |
818 | { | |
819 | if (readbuf != NULL) | |
820 | m32r_extract_return_value (valtype, regcache, readbuf); | |
821 | if (writebuf != NULL) | |
822 | m32r_store_return_value (valtype, regcache, writebuf); | |
823 | return RETURN_VALUE_REGISTER_CONVENTION; | |
824 | } | |
825 | } | |
826 | ||
827 | ||
d95a8903 AC |
828 | |
829 | static CORE_ADDR | |
830 | m32r_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
831 | { | |
7e3dd49e | 832 | return frame_unwind_register_unsigned (next_frame, M32R_PC_REGNUM); |
d95a8903 AC |
833 | } |
834 | ||
835 | /* Given a GDB frame, determine the address of the calling function's | |
836 | frame. This will be used to create a new GDB frame struct. */ | |
837 | ||
838 | static void | |
94afd7a6 | 839 | m32r_frame_this_id (struct frame_info *this_frame, |
d95a8903 AC |
840 | void **this_prologue_cache, struct frame_id *this_id) |
841 | { | |
842 | struct m32r_unwind_cache *info | |
94afd7a6 | 843 | = m32r_frame_unwind_cache (this_frame, this_prologue_cache); |
d95a8903 AC |
844 | CORE_ADDR base; |
845 | CORE_ADDR func; | |
846 | struct minimal_symbol *msym_stack; | |
847 | struct frame_id id; | |
848 | ||
849 | /* The FUNC is easy. */ | |
94afd7a6 | 850 | func = get_frame_func (this_frame); |
d95a8903 | 851 | |
d95a8903 AC |
852 | /* Check if the stack is empty. */ |
853 | msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL); | |
854 | if (msym_stack && info->base == SYMBOL_VALUE_ADDRESS (msym_stack)) | |
855 | return; | |
856 | ||
857 | /* Hopefully the prologue analysis either correctly determined the | |
858 | frame's base (which is the SP from the previous frame), or set | |
859 | that base to "NULL". */ | |
860 | base = info->prev_sp; | |
861 | if (base == 0) | |
862 | return; | |
863 | ||
864 | id = frame_id_build (base, func); | |
d95a8903 AC |
865 | (*this_id) = id; |
866 | } | |
867 | ||
94afd7a6 UW |
868 | static struct value * |
869 | m32r_frame_prev_register (struct frame_info *this_frame, | |
870 | void **this_prologue_cache, int regnum) | |
d95a8903 AC |
871 | { |
872 | struct m32r_unwind_cache *info | |
94afd7a6 UW |
873 | = m32r_frame_unwind_cache (this_frame, this_prologue_cache); |
874 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); | |
d95a8903 AC |
875 | } |
876 | ||
877 | static const struct frame_unwind m32r_frame_unwind = { | |
878 | NORMAL_FRAME, | |
8fbca658 | 879 | default_frame_unwind_stop_reason, |
d95a8903 | 880 | m32r_frame_this_id, |
94afd7a6 UW |
881 | m32r_frame_prev_register, |
882 | NULL, | |
883 | default_frame_sniffer | |
d95a8903 AC |
884 | }; |
885 | ||
d95a8903 | 886 | static CORE_ADDR |
94afd7a6 | 887 | m32r_frame_base_address (struct frame_info *this_frame, void **this_cache) |
d95a8903 AC |
888 | { |
889 | struct m32r_unwind_cache *info | |
94afd7a6 | 890 | = m32r_frame_unwind_cache (this_frame, this_cache); |
d95a8903 AC |
891 | return info->base; |
892 | } | |
893 | ||
894 | static const struct frame_base m32r_frame_base = { | |
895 | &m32r_frame_unwind, | |
896 | m32r_frame_base_address, | |
897 | m32r_frame_base_address, | |
898 | m32r_frame_base_address | |
899 | }; | |
900 | ||
94afd7a6 UW |
901 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy |
902 | frame. The frame ID's base needs to match the TOS value saved by | |
903 | save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */ | |
d95a8903 AC |
904 | |
905 | static struct frame_id | |
94afd7a6 | 906 | m32r_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
d95a8903 | 907 | { |
94afd7a6 UW |
908 | CORE_ADDR sp = get_frame_register_unsigned (this_frame, M32R_SP_REGNUM); |
909 | return frame_id_build (sp, get_frame_pc (this_frame)); | |
d95a8903 AC |
910 | } |
911 | ||
912 | ||
913 | static gdbarch_init_ftype m32r_gdbarch_init; | |
914 | ||
915 | static struct gdbarch * | |
916 | m32r_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
917 | { | |
918 | struct gdbarch *gdbarch; | |
919 | struct gdbarch_tdep *tdep; | |
920 | ||
921 | /* If there is already a candidate, use it. */ | |
922 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
923 | if (arches != NULL) | |
924 | return arches->gdbarch; | |
925 | ||
926 | /* Allocate space for the new architecture. */ | |
927 | tdep = XMALLOC (struct gdbarch_tdep); | |
928 | gdbarch = gdbarch_alloc (&info, tdep); | |
929 | ||
930 | set_gdbarch_read_pc (gdbarch, m32r_read_pc); | |
931 | set_gdbarch_write_pc (gdbarch, m32r_write_pc); | |
932 | set_gdbarch_unwind_sp (gdbarch, m32r_unwind_sp); | |
933 | ||
e839132d | 934 | set_gdbarch_num_regs (gdbarch, M32R_NUM_REGS); |
d95a8903 AC |
935 | set_gdbarch_sp_regnum (gdbarch, M32R_SP_REGNUM); |
936 | set_gdbarch_register_name (gdbarch, m32r_register_name); | |
937 | set_gdbarch_register_type (gdbarch, m32r_register_type); | |
938 | ||
d95a8903 | 939 | set_gdbarch_push_dummy_call (gdbarch, m32r_push_dummy_call); |
14588880 | 940 | set_gdbarch_return_value (gdbarch, m32r_return_value); |
d95a8903 AC |
941 | |
942 | set_gdbarch_skip_prologue (gdbarch, m32r_skip_prologue); | |
943 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
d95a8903 AC |
944 | set_gdbarch_breakpoint_from_pc (gdbarch, m32r_breakpoint_from_pc); |
945 | set_gdbarch_memory_insert_breakpoint (gdbarch, | |
946 | m32r_memory_insert_breakpoint); | |
947 | set_gdbarch_memory_remove_breakpoint (gdbarch, | |
948 | m32r_memory_remove_breakpoint); | |
949 | ||
d95a8903 AC |
950 | set_gdbarch_frame_align (gdbarch, m32r_frame_align); |
951 | ||
d95a8903 AC |
952 | frame_base_set_default (gdbarch, &m32r_frame_base); |
953 | ||
954 | /* Methods for saving / extracting a dummy frame's ID. The ID's | |
955 | stack address must match the SP value returned by | |
956 | PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */ | |
94afd7a6 | 957 | set_gdbarch_dummy_id (gdbarch, m32r_dummy_id); |
d95a8903 AC |
958 | |
959 | /* Return the unwound PC value. */ | |
960 | set_gdbarch_unwind_pc (gdbarch, m32r_unwind_pc); | |
961 | ||
962 | set_gdbarch_print_insn (gdbarch, print_insn_m32r); | |
963 | ||
c46b0409 KI |
964 | /* Hook in ABI-specific overrides, if they have been registered. */ |
965 | gdbarch_init_osabi (info, gdbarch); | |
966 | ||
967 | /* Hook in the default unwinders. */ | |
94afd7a6 | 968 | frame_unwind_append_unwinder (gdbarch, &m32r_frame_unwind); |
c46b0409 | 969 | |
1c772458 UW |
970 | /* Support simple overlay manager. */ |
971 | set_gdbarch_overlay_update (gdbarch, simple_overlay_update); | |
972 | ||
d95a8903 AC |
973 | return gdbarch; |
974 | } | |
975 | ||
976 | void | |
977 | _initialize_m32r_tdep (void) | |
978 | { | |
979 | register_gdbarch_init (bfd_arch_m32r, m32r_gdbarch_init); | |
980 | } |