Commit | Line | Data |
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d95a8903 AC |
1 | /* Target-dependent code for Renesas M32R, for GDB. |
2 | ||
61baf725 | 3 | Copyright (C) 1996-2017 Free Software Foundation, Inc. |
d95a8903 AC |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
d95a8903 AC |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
d95a8903 AC |
19 | |
20 | #include "defs.h" | |
21 | #include "frame.h" | |
22 | #include "frame-unwind.h" | |
23 | #include "frame-base.h" | |
24 | #include "symtab.h" | |
25 | #include "gdbtypes.h" | |
26 | #include "gdbcmd.h" | |
27 | #include "gdbcore.h" | |
d95a8903 AC |
28 | #include "value.h" |
29 | #include "inferior.h" | |
30 | #include "symfile.h" | |
31 | #include "objfiles.h" | |
c46b0409 | 32 | #include "osabi.h" |
d95a8903 AC |
33 | #include "language.h" |
34 | #include "arch-utils.h" | |
35 | #include "regcache.h" | |
36 | #include "trad-frame.h" | |
73e8eb51 | 37 | #include "dis-asm.h" |
77e371c0 | 38 | #include "objfiles.h" |
9b32d526 | 39 | #include "m32r-tdep.h" |
325fac50 | 40 | #include <algorithm> |
d95a8903 | 41 | |
ab0538b8 AH |
42 | /* The size of the argument registers (r0 - r3) in bytes. */ |
43 | #define M32R_ARG_REGISTER_SIZE 4 | |
44 | ||
d95a8903 AC |
45 | /* Local functions */ |
46 | ||
47 | extern void _initialize_m32r_tdep (void); | |
48 | ||
49 | static CORE_ADDR | |
50 | m32r_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
51 | { | |
52 | /* Align to the size of an instruction (so that they can safely be | |
53 | pushed onto the stack. */ | |
54 | return sp & ~3; | |
55 | } | |
56 | ||
d95a8903 | 57 | |
9f0b0322 KI |
58 | /* Breakpoints |
59 | ||
025bb325 | 60 | The little endian mode of M32R is unique. In most of architectures, |
9f0b0322 KI |
61 | two 16-bit instructions, A and B, are placed as the following: |
62 | ||
63 | Big endian: | |
64 | A0 A1 B0 B1 | |
65 | ||
66 | Little endian: | |
67 | A1 A0 B1 B0 | |
68 | ||
69 | In M32R, they are placed like this: | |
70 | ||
71 | Big endian: | |
72 | A0 A1 B0 B1 | |
73 | ||
74 | Little endian: | |
75 | B1 B0 A1 A0 | |
76 | ||
77 | This is because M32R always fetches instructions in 32-bit. | |
78 | ||
025bb325 | 79 | The following functions take care of this behavior. */ |
d95a8903 AC |
80 | |
81 | static int | |
ae4b2284 MD |
82 | m32r_memory_insert_breakpoint (struct gdbarch *gdbarch, |
83 | struct bp_target_info *bp_tgt) | |
d95a8903 | 84 | { |
0d5ed153 | 85 | CORE_ADDR addr = bp_tgt->placed_address = bp_tgt->reqstd_address; |
d95a8903 | 86 | int val; |
16ac4ab5 | 87 | gdb_byte buf[4]; |
35c63cd8 | 88 | gdb_byte contents_cache[4]; |
16ac4ab5 | 89 | gdb_byte bp_entry[] = { 0x10, 0xf1 }; /* dpt */ |
d95a8903 AC |
90 | |
91 | /* Save the memory contents. */ | |
9f0b0322 | 92 | val = target_read_memory (addr & 0xfffffffc, contents_cache, 4); |
d95a8903 AC |
93 | if (val != 0) |
94 | return val; /* return error */ | |
95 | ||
35c63cd8 | 96 | memcpy (bp_tgt->shadow_contents, contents_cache, 4); |
cd6c3b4f | 97 | bp_tgt->shadow_len = 4; |
8181d85f | 98 | |
d95a8903 | 99 | /* Determine appropriate breakpoint contents and size for this address. */ |
ae4b2284 | 100 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
d95a8903 | 101 | { |
9f0b0322 | 102 | if ((addr & 3) == 0) |
d95a8903 | 103 | { |
9f0b0322 KI |
104 | buf[0] = bp_entry[0]; |
105 | buf[1] = bp_entry[1]; | |
106 | buf[2] = contents_cache[2] & 0x7f; | |
107 | buf[3] = contents_cache[3]; | |
d95a8903 AC |
108 | } |
109 | else | |
110 | { | |
9f0b0322 KI |
111 | buf[0] = contents_cache[0]; |
112 | buf[1] = contents_cache[1]; | |
113 | buf[2] = bp_entry[0]; | |
114 | buf[3] = bp_entry[1]; | |
d95a8903 AC |
115 | } |
116 | } | |
9f0b0322 KI |
117 | else /* little-endian */ |
118 | { | |
119 | if ((addr & 3) == 0) | |
d95a8903 | 120 | { |
9f0b0322 KI |
121 | buf[0] = contents_cache[0]; |
122 | buf[1] = contents_cache[1] & 0x7f; | |
123 | buf[2] = bp_entry[1]; | |
124 | buf[3] = bp_entry[0]; | |
d95a8903 AC |
125 | } |
126 | else | |
127 | { | |
9f0b0322 KI |
128 | buf[0] = bp_entry[1]; |
129 | buf[1] = bp_entry[0]; | |
130 | buf[2] = contents_cache[2]; | |
131 | buf[3] = contents_cache[3]; | |
d95a8903 AC |
132 | } |
133 | } | |
134 | ||
135 | /* Write the breakpoint. */ | |
9f0b0322 | 136 | val = target_write_memory (addr & 0xfffffffc, buf, 4); |
d95a8903 AC |
137 | return val; |
138 | } | |
139 | ||
140 | static int | |
ae4b2284 MD |
141 | m32r_memory_remove_breakpoint (struct gdbarch *gdbarch, |
142 | struct bp_target_info *bp_tgt) | |
d95a8903 | 143 | { |
8181d85f | 144 | CORE_ADDR addr = bp_tgt->placed_address; |
d95a8903 | 145 | int val; |
16ac4ab5 | 146 | gdb_byte buf[4]; |
8181d85f | 147 | gdb_byte *contents_cache = bp_tgt->shadow_contents; |
d95a8903 | 148 | |
9f0b0322 KI |
149 | buf[0] = contents_cache[0]; |
150 | buf[1] = contents_cache[1]; | |
151 | buf[2] = contents_cache[2]; | |
152 | buf[3] = contents_cache[3]; | |
153 | ||
154 | /* Remove parallel bit. */ | |
ae4b2284 | 155 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
d95a8903 | 156 | { |
9f0b0322 KI |
157 | if ((buf[0] & 0x80) == 0 && (buf[2] & 0x80) != 0) |
158 | buf[2] &= 0x7f; | |
d95a8903 | 159 | } |
9f0b0322 | 160 | else /* little-endian */ |
d95a8903 | 161 | { |
9f0b0322 KI |
162 | if ((buf[3] & 0x80) == 0 && (buf[1] & 0x80) != 0) |
163 | buf[1] &= 0x7f; | |
d95a8903 AC |
164 | } |
165 | ||
166 | /* Write contents. */ | |
dd110abf | 167 | val = target_write_raw_memory (addr & 0xfffffffc, buf, 4); |
d95a8903 AC |
168 | return val; |
169 | } | |
170 | ||
cd6c3b4f YQ |
171 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ |
172 | ||
d19280ad YQ |
173 | static int |
174 | m32r_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
175 | { | |
176 | if ((*pcptr & 3) == 0) | |
177 | return 4; | |
178 | else | |
179 | return 2; | |
180 | } | |
181 | ||
cd6c3b4f YQ |
182 | /* Implement the sw_breakpoint_from_kind gdbarch method. */ |
183 | ||
16ac4ab5 | 184 | static const gdb_byte * |
d19280ad | 185 | m32r_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) |
d95a8903 | 186 | { |
025bb325 MS |
187 | static gdb_byte be_bp_entry[] = { |
188 | 0x10, 0xf1, 0x70, 0x00 | |
189 | }; /* dpt -> nop */ | |
190 | static gdb_byte le_bp_entry[] = { | |
191 | 0x00, 0x70, 0xf1, 0x10 | |
192 | }; /* dpt -> nop */ | |
d19280ad YQ |
193 | |
194 | *size = kind; | |
d95a8903 AC |
195 | |
196 | /* Determine appropriate breakpoint. */ | |
67d57894 | 197 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
d19280ad | 198 | return be_bp_entry; |
d95a8903 AC |
199 | else |
200 | { | |
d19280ad YQ |
201 | if (kind == 4) |
202 | return le_bp_entry; | |
d95a8903 | 203 | else |
d19280ad | 204 | return le_bp_entry + 2; |
d95a8903 | 205 | } |
d95a8903 AC |
206 | } |
207 | ||
a121b7c1 | 208 | static const char *m32r_register_names[] = { |
d95a8903 AC |
209 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
210 | "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp", | |
211 | "psw", "cbr", "spi", "spu", "bpc", "pc", "accl", "acch", | |
212 | "evb" | |
213 | }; | |
214 | ||
d95a8903 | 215 | static const char * |
d93859e2 | 216 | m32r_register_name (struct gdbarch *gdbarch, int reg_nr) |
d95a8903 AC |
217 | { |
218 | if (reg_nr < 0) | |
219 | return NULL; | |
9b32d526 | 220 | if (reg_nr >= M32R_NUM_REGS) |
d95a8903 AC |
221 | return NULL; |
222 | return m32r_register_names[reg_nr]; | |
223 | } | |
224 | ||
225 | ||
226 | /* Return the GDB type object for the "standard" data type | |
227 | of data in register N. */ | |
228 | ||
229 | static struct type * | |
230 | m32r_register_type (struct gdbarch *gdbarch, int reg_nr) | |
231 | { | |
232 | if (reg_nr == M32R_PC_REGNUM) | |
0dfff4cb | 233 | return builtin_type (gdbarch)->builtin_func_ptr; |
d95a8903 | 234 | else if (reg_nr == M32R_SP_REGNUM || reg_nr == M32R_FP_REGNUM) |
0dfff4cb | 235 | return builtin_type (gdbarch)->builtin_data_ptr; |
d95a8903 | 236 | else |
df4df182 | 237 | return builtin_type (gdbarch)->builtin_int32; |
d95a8903 AC |
238 | } |
239 | ||
240 | ||
241 | /* Write into appropriate registers a function return value | |
025bb325 | 242 | of type TYPE, given in virtual format. |
d95a8903 | 243 | |
025bb325 | 244 | Things always get returned in RET1_REGNUM, RET2_REGNUM. */ |
d95a8903 AC |
245 | |
246 | static void | |
247 | m32r_store_return_value (struct type *type, struct regcache *regcache, | |
7c543f7b | 248 | const gdb_byte *valbuf) |
d95a8903 | 249 | { |
e17a4113 UW |
250 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
251 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
d95a8903 AC |
252 | CORE_ADDR regval; |
253 | int len = TYPE_LENGTH (type); | |
254 | ||
e17a4113 | 255 | regval = extract_unsigned_integer (valbuf, len > 4 ? 4 : len, byte_order); |
d95a8903 AC |
256 | regcache_cooked_write_unsigned (regcache, RET1_REGNUM, regval); |
257 | ||
258 | if (len > 4) | |
259 | { | |
7c543f7b | 260 | regval = extract_unsigned_integer (valbuf + 4, |
e17a4113 | 261 | len - 4, byte_order); |
d95a8903 AC |
262 | regcache_cooked_write_unsigned (regcache, RET1_REGNUM + 1, regval); |
263 | } | |
264 | } | |
265 | ||
025bb325 | 266 | /* This is required by skip_prologue. The results of decoding a prologue |
d95a8903 AC |
267 | should be cached because this thrashing is getting nuts. */ |
268 | ||
cea15572 | 269 | static int |
e17a4113 UW |
270 | decode_prologue (struct gdbarch *gdbarch, |
271 | CORE_ADDR start_pc, CORE_ADDR scan_limit, | |
cea15572 | 272 | CORE_ADDR *pl_endptr, unsigned long *framelength) |
d95a8903 | 273 | { |
e17a4113 | 274 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d95a8903 AC |
275 | unsigned long framesize; |
276 | int insn; | |
277 | int op1; | |
d95a8903 | 278 | CORE_ADDR after_prologue = 0; |
cea15572 | 279 | CORE_ADDR after_push = 0; |
d95a8903 AC |
280 | CORE_ADDR after_stack_adjust = 0; |
281 | CORE_ADDR current_pc; | |
cea15572 | 282 | LONGEST return_value; |
d95a8903 AC |
283 | |
284 | framesize = 0; | |
285 | after_prologue = 0; | |
286 | ||
287 | for (current_pc = start_pc; current_pc < scan_limit; current_pc += 2) | |
288 | { | |
025bb325 | 289 | /* Check if current pc's location is readable. */ |
e17a4113 | 290 | if (!safe_read_memory_integer (current_pc, 2, byte_order, &return_value)) |
cea15572 KI |
291 | return -1; |
292 | ||
e17a4113 | 293 | insn = read_memory_unsigned_integer (current_pc, 2, byte_order); |
d95a8903 | 294 | |
cea15572 KI |
295 | if (insn == 0x0000) |
296 | break; | |
297 | ||
d95a8903 | 298 | /* If this is a 32 bit instruction, we dont want to examine its |
025bb325 | 299 | immediate data as though it were an instruction. */ |
d95a8903 AC |
300 | if (current_pc & 0x02) |
301 | { | |
025bb325 | 302 | /* Decode this instruction further. */ |
d95a8903 AC |
303 | insn &= 0x7fff; |
304 | } | |
305 | else | |
306 | { | |
d95a8903 AC |
307 | if (insn & 0x8000) |
308 | { | |
309 | if (current_pc == scan_limit) | |
310 | scan_limit += 2; /* extend the search */ | |
cea15572 | 311 | |
d95a8903 | 312 | current_pc += 2; /* skip the immediate data */ |
cea15572 | 313 | |
025bb325 | 314 | /* Check if current pc's location is readable. */ |
e17a4113 UW |
315 | if (!safe_read_memory_integer (current_pc, 2, byte_order, |
316 | &return_value)) | |
cea15572 KI |
317 | return -1; |
318 | ||
d95a8903 AC |
319 | if (insn == 0x8faf) /* add3 sp, sp, xxxx */ |
320 | /* add 16 bit sign-extended offset */ | |
321 | { | |
322 | framesize += | |
e17a4113 UW |
323 | -((short) read_memory_unsigned_integer (current_pc, |
324 | 2, byte_order)); | |
d95a8903 AC |
325 | } |
326 | else | |
327 | { | |
025bb325 | 328 | if (((insn >> 8) == 0xe4) /* ld24 r4, xxxxxx; sub sp, r4 */ |
e17a4113 UW |
329 | && safe_read_memory_integer (current_pc + 2, |
330 | 2, byte_order, | |
cea15572 | 331 | &return_value) |
7e3dd49e | 332 | && read_memory_unsigned_integer (current_pc + 2, |
e17a4113 UW |
333 | 2, byte_order) |
334 | == 0x0f24) | |
d95a8903 | 335 | { |
025bb325 | 336 | /* Subtract 24 bit sign-extended negative-offset. */ |
e17a4113 UW |
337 | insn = read_memory_unsigned_integer (current_pc - 2, |
338 | 4, byte_order); | |
d95a8903 AC |
339 | if (insn & 0x00800000) /* sign extend */ |
340 | insn |= 0xff000000; /* negative */ | |
341 | else | |
342 | insn &= 0x00ffffff; /* positive */ | |
343 | framesize += insn; | |
344 | } | |
345 | } | |
cea15572 | 346 | after_push = current_pc + 2; |
d95a8903 AC |
347 | continue; |
348 | } | |
349 | } | |
025bb325 | 350 | op1 = insn & 0xf000; /* Isolate just the first nibble. */ |
d95a8903 AC |
351 | |
352 | if ((insn & 0xf0ff) == 0x207f) | |
353 | { /* st reg, @-sp */ | |
d95a8903 | 354 | framesize += 4; |
d95a8903 AC |
355 | after_prologue = 0; |
356 | continue; | |
357 | } | |
358 | if ((insn >> 8) == 0x4f) /* addi sp, xx */ | |
025bb325 | 359 | /* Add 8 bit sign-extended offset. */ |
d95a8903 | 360 | { |
9ffbf372 | 361 | int stack_adjust = (signed char) (insn & 0xff); |
d95a8903 AC |
362 | |
363 | /* there are probably two of these stack adjustments: | |
364 | 1) A negative one in the prologue, and | |
365 | 2) A positive one in the epilogue. | |
366 | We are only interested in the first one. */ | |
367 | ||
368 | if (stack_adjust < 0) | |
369 | { | |
370 | framesize -= stack_adjust; | |
371 | after_prologue = 0; | |
372 | /* A frameless function may have no "mv fp, sp". | |
373 | In that case, this is the end of the prologue. */ | |
374 | after_stack_adjust = current_pc + 2; | |
375 | } | |
376 | continue; | |
377 | } | |
378 | if (insn == 0x1d8f) | |
379 | { /* mv fp, sp */ | |
380 | after_prologue = current_pc + 2; | |
381 | break; /* end of stack adjustments */ | |
382 | } | |
cea15572 | 383 | |
025bb325 | 384 | /* Nop looks like a branch, continue explicitly. */ |
d95a8903 AC |
385 | if (insn == 0x7000) |
386 | { | |
387 | after_prologue = current_pc + 2; | |
025bb325 | 388 | continue; /* nop occurs between pushes. */ |
d95a8903 | 389 | } |
025bb325 | 390 | /* End of prolog if any of these are trap instructions. */ |
cea15572 KI |
391 | if ((insn & 0xfff0) == 0x10f0) |
392 | { | |
393 | after_prologue = current_pc; | |
394 | break; | |
395 | } | |
025bb325 | 396 | /* End of prolog if any of these are branch instructions. */ |
d95a8903 AC |
397 | if ((op1 == 0x7000) || (op1 == 0xb000) || (op1 == 0xf000)) |
398 | { | |
399 | after_prologue = current_pc; | |
d95a8903 AC |
400 | continue; |
401 | } | |
025bb325 | 402 | /* Some of the branch instructions are mixed with other types. */ |
d95a8903 AC |
403 | if (op1 == 0x1000) |
404 | { | |
405 | int subop = insn & 0x0ff0; | |
406 | if ((subop == 0x0ec0) || (subop == 0x0fc0)) | |
407 | { | |
408 | after_prologue = current_pc; | |
d95a8903 AC |
409 | continue; /* jmp , jl */ |
410 | } | |
411 | } | |
412 | } | |
413 | ||
cea15572 KI |
414 | if (framelength) |
415 | *framelength = framesize; | |
416 | ||
d95a8903 AC |
417 | if (current_pc >= scan_limit) |
418 | { | |
419 | if (pl_endptr) | |
420 | { | |
421 | if (after_stack_adjust != 0) | |
422 | /* We did not find a "mv fp,sp", but we DID find | |
423 | a stack_adjust. Is it safe to use that as the | |
025bb325 | 424 | end of the prologue? I just don't know. */ |
d95a8903 AC |
425 | { |
426 | *pl_endptr = after_stack_adjust; | |
427 | } | |
cea15572 KI |
428 | else if (after_push != 0) |
429 | /* We did not find a "mv fp,sp", but we DID find | |
430 | a push. Is it safe to use that as the | |
025bb325 | 431 | end of the prologue? I just don't know. */ |
cea15572 KI |
432 | { |
433 | *pl_endptr = after_push; | |
434 | } | |
d95a8903 AC |
435 | else |
436 | /* We reached the end of the loop without finding the end | |
025bb325 MS |
437 | of the prologue. No way to win -- we should report |
438 | failure. The way we do that is to return the original | |
439 | start_pc. GDB will set a breakpoint at the start of | |
440 | the function (etc.) */ | |
d95a8903 AC |
441 | *pl_endptr = start_pc; |
442 | } | |
cea15572 | 443 | return 0; |
d95a8903 | 444 | } |
cea15572 | 445 | |
d95a8903 AC |
446 | if (after_prologue == 0) |
447 | after_prologue = current_pc; | |
448 | ||
449 | if (pl_endptr) | |
450 | *pl_endptr = after_prologue; | |
cea15572 KI |
451 | |
452 | return 0; | |
d95a8903 AC |
453 | } /* decode_prologue */ |
454 | ||
455 | /* Function: skip_prologue | |
025bb325 | 456 | Find end of function prologue. */ |
d95a8903 | 457 | |
cea15572 | 458 | #define DEFAULT_SEARCH_LIMIT 128 |
d95a8903 | 459 | |
63807e1d | 460 | static CORE_ADDR |
6093d2eb | 461 | m32r_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
d95a8903 | 462 | { |
e17a4113 | 463 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d95a8903 AC |
464 | CORE_ADDR func_addr, func_end; |
465 | struct symtab_and_line sal; | |
cea15572 | 466 | LONGEST return_value; |
d95a8903 | 467 | |
025bb325 | 468 | /* See what the symbol table says. */ |
d95a8903 AC |
469 | |
470 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
471 | { | |
472 | sal = find_pc_line (func_addr, 0); | |
473 | ||
474 | if (sal.line != 0 && sal.end <= func_end) | |
475 | { | |
476 | func_end = sal.end; | |
477 | } | |
478 | else | |
479 | /* Either there's no line info, or the line after the prologue is after | |
480 | the end of the function. In this case, there probably isn't a | |
481 | prologue. */ | |
482 | { | |
325fac50 | 483 | func_end = std::min (func_end, func_addr + DEFAULT_SEARCH_LIMIT); |
d95a8903 AC |
484 | } |
485 | } | |
486 | else | |
487 | func_end = pc + DEFAULT_SEARCH_LIMIT; | |
cea15572 | 488 | |
025bb325 | 489 | /* If pc's location is not readable, just quit. */ |
e17a4113 | 490 | if (!safe_read_memory_integer (pc, 4, byte_order, &return_value)) |
cea15572 KI |
491 | return pc; |
492 | ||
493 | /* Find the end of prologue. */ | |
e17a4113 | 494 | if (decode_prologue (gdbarch, pc, func_end, &sal.end, NULL) < 0) |
cea15572 KI |
495 | return pc; |
496 | ||
d95a8903 AC |
497 | return sal.end; |
498 | } | |
499 | ||
d95a8903 AC |
500 | struct m32r_unwind_cache |
501 | { | |
502 | /* The previous frame's inner most stack address. Used as this | |
503 | frame ID's stack_addr. */ | |
504 | CORE_ADDR prev_sp; | |
505 | /* The frame's base, optionally used by the high-level debug info. */ | |
506 | CORE_ADDR base; | |
507 | int size; | |
508 | /* How far the SP and r13 (FP) have been offset from the start of | |
509 | the stack frame (as defined by the previous frame's stack | |
510 | pointer). */ | |
511 | LONGEST sp_offset; | |
512 | LONGEST r13_offset; | |
513 | int uses_frame; | |
514 | /* Table indicating the location of each and every register. */ | |
515 | struct trad_frame_saved_reg *saved_regs; | |
516 | }; | |
517 | ||
518 | /* Put here the code to store, into fi->saved_regs, the addresses of | |
519 | the saved registers of frame described by FRAME_INFO. This | |
520 | includes special registers such as pc and fp saved in special ways | |
521 | in the stack frame. sp is even more special: the address we return | |
025bb325 | 522 | for it IS the sp for the next frame. */ |
d95a8903 AC |
523 | |
524 | static struct m32r_unwind_cache * | |
94afd7a6 | 525 | m32r_frame_unwind_cache (struct frame_info *this_frame, |
d95a8903 AC |
526 | void **this_prologue_cache) |
527 | { | |
cea15572 | 528 | CORE_ADDR pc, scan_limit; |
d95a8903 AC |
529 | ULONGEST prev_sp; |
530 | ULONGEST this_base; | |
22e048c9 | 531 | unsigned long op; |
d95a8903 AC |
532 | int i; |
533 | struct m32r_unwind_cache *info; | |
534 | ||
cea15572 | 535 | |
d95a8903 | 536 | if ((*this_prologue_cache)) |
9a3c8263 | 537 | return (struct m32r_unwind_cache *) (*this_prologue_cache); |
d95a8903 AC |
538 | |
539 | info = FRAME_OBSTACK_ZALLOC (struct m32r_unwind_cache); | |
540 | (*this_prologue_cache) = info; | |
94afd7a6 | 541 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
d95a8903 AC |
542 | |
543 | info->size = 0; | |
544 | info->sp_offset = 0; | |
d95a8903 | 545 | info->uses_frame = 0; |
cea15572 | 546 | |
94afd7a6 UW |
547 | scan_limit = get_frame_pc (this_frame); |
548 | for (pc = get_frame_func (this_frame); | |
cea15572 | 549 | pc > 0 && pc < scan_limit; pc += 2) |
d95a8903 AC |
550 | { |
551 | if ((pc & 2) == 0) | |
552 | { | |
94afd7a6 | 553 | op = get_frame_memory_unsigned (this_frame, pc, 4); |
d95a8903 AC |
554 | if ((op & 0x80000000) == 0x80000000) |
555 | { | |
556 | /* 32-bit instruction */ | |
557 | if ((op & 0xffff0000) == 0x8faf0000) | |
558 | { | |
559 | /* add3 sp,sp,xxxx */ | |
560 | short n = op & 0xffff; | |
561 | info->sp_offset += n; | |
562 | } | |
cea15572 | 563 | else if (((op >> 8) == 0xe4) |
94afd7a6 | 564 | && get_frame_memory_unsigned (this_frame, pc + 2, |
7e3dd49e | 565 | 2) == 0x0f24) |
d95a8903 | 566 | { |
cea15572 | 567 | /* ld24 r4, xxxxxx; sub sp, r4 */ |
d95a8903 AC |
568 | unsigned long n = op & 0xffffff; |
569 | info->sp_offset += n; | |
cea15572 | 570 | pc += 2; /* skip sub instruction */ |
d95a8903 | 571 | } |
d95a8903 | 572 | |
cea15572 KI |
573 | if (pc == scan_limit) |
574 | scan_limit += 2; /* extend the search */ | |
575 | pc += 2; /* skip the immediate data */ | |
d95a8903 AC |
576 | continue; |
577 | } | |
578 | } | |
579 | ||
580 | /* 16-bit instructions */ | |
94afd7a6 | 581 | op = get_frame_memory_unsigned (this_frame, pc, 2) & 0x7fff; |
d95a8903 AC |
582 | if ((op & 0xf0ff) == 0x207f) |
583 | { | |
584 | /* st rn, @-sp */ | |
585 | int regno = ((op >> 8) & 0xf); | |
586 | info->sp_offset -= 4; | |
587 | info->saved_regs[regno].addr = info->sp_offset; | |
588 | } | |
589 | else if ((op & 0xff00) == 0x4f00) | |
590 | { | |
591 | /* addi sp, xx */ | |
9ffbf372 | 592 | int n = (signed char) (op & 0xff); |
d95a8903 AC |
593 | info->sp_offset += n; |
594 | } | |
595 | else if (op == 0x1d8f) | |
596 | { | |
597 | /* mv fp, sp */ | |
598 | info->uses_frame = 1; | |
599 | info->r13_offset = info->sp_offset; | |
cea15572 KI |
600 | break; /* end of stack adjustments */ |
601 | } | |
602 | else if ((op & 0xfff0) == 0x10f0) | |
603 | { | |
025bb325 MS |
604 | /* End of prologue if this is a trap instruction. */ |
605 | break; /* End of stack adjustments. */ | |
d95a8903 | 606 | } |
d95a8903 AC |
607 | } |
608 | ||
609 | info->size = -info->sp_offset; | |
610 | ||
611 | /* Compute the previous frame's stack pointer (which is also the | |
612 | frame's ID's stack address), and this frame's base pointer. */ | |
613 | if (info->uses_frame) | |
614 | { | |
615 | /* The SP was moved to the FP. This indicates that a new frame | |
616 | was created. Get THIS frame's FP value by unwinding it from | |
617 | the next frame. */ | |
94afd7a6 | 618 | this_base = get_frame_register_unsigned (this_frame, M32R_FP_REGNUM); |
d95a8903 AC |
619 | /* The FP points at the last saved register. Adjust the FP back |
620 | to before the first saved register giving the SP. */ | |
621 | prev_sp = this_base + info->size; | |
622 | } | |
623 | else | |
624 | { | |
625 | /* Assume that the FP is this frame's SP but with that pushed | |
626 | stack space added back. */ | |
94afd7a6 | 627 | this_base = get_frame_register_unsigned (this_frame, M32R_SP_REGNUM); |
d95a8903 AC |
628 | prev_sp = this_base + info->size; |
629 | } | |
630 | ||
631 | /* Convert that SP/BASE into real addresses. */ | |
632 | info->prev_sp = prev_sp; | |
633 | info->base = this_base; | |
634 | ||
635 | /* Adjust all the saved registers so that they contain addresses and | |
636 | not offsets. */ | |
94afd7a6 | 637 | for (i = 0; i < gdbarch_num_regs (get_frame_arch (this_frame)) - 1; i++) |
d95a8903 AC |
638 | if (trad_frame_addr_p (info->saved_regs, i)) |
639 | info->saved_regs[i].addr = (info->prev_sp + info->saved_regs[i].addr); | |
640 | ||
641 | /* The call instruction moves the caller's PC in the callee's LR. | |
642 | Since this is an unwind, do the reverse. Copy the location of LR | |
643 | into PC (the address / regnum) so that a request for PC will be | |
644 | converted into a request for the LR. */ | |
645 | info->saved_regs[M32R_PC_REGNUM] = info->saved_regs[LR_REGNUM]; | |
646 | ||
647 | /* The previous frame's SP needed to be computed. Save the computed | |
648 | value. */ | |
649 | trad_frame_set_value (info->saved_regs, M32R_SP_REGNUM, prev_sp); | |
650 | ||
651 | return info; | |
652 | } | |
653 | ||
654 | static CORE_ADDR | |
61a1198a | 655 | m32r_read_pc (struct regcache *regcache) |
d95a8903 | 656 | { |
7e3dd49e | 657 | ULONGEST pc; |
61a1198a | 658 | regcache_cooked_read_unsigned (regcache, M32R_PC_REGNUM, &pc); |
d95a8903 AC |
659 | return pc; |
660 | } | |
661 | ||
d95a8903 AC |
662 | static CORE_ADDR |
663 | m32r_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
664 | { | |
7e3dd49e | 665 | return frame_unwind_register_unsigned (next_frame, M32R_SP_REGNUM); |
d95a8903 AC |
666 | } |
667 | ||
668 | ||
669 | static CORE_ADDR | |
7d9b040b | 670 | m32r_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
d95a8903 AC |
671 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
672 | struct value **args, CORE_ADDR sp, int struct_return, | |
673 | CORE_ADDR struct_addr) | |
674 | { | |
e17a4113 | 675 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d95a8903 AC |
676 | int stack_offset, stack_alloc; |
677 | int argreg = ARG1_REGNUM; | |
678 | int argnum; | |
679 | struct type *type; | |
680 | enum type_code typecode; | |
681 | CORE_ADDR regval; | |
16ac4ab5 | 682 | gdb_byte *val; |
ab0538b8 | 683 | gdb_byte valbuf[M32R_ARG_REGISTER_SIZE]; |
d95a8903 | 684 | int len; |
d95a8903 | 685 | |
025bb325 | 686 | /* First force sp to a 4-byte alignment. */ |
d95a8903 AC |
687 | sp = sp & ~3; |
688 | ||
689 | /* Set the return address. For the m32r, the return breakpoint is | |
690 | always at BP_ADDR. */ | |
691 | regcache_cooked_write_unsigned (regcache, LR_REGNUM, bp_addr); | |
692 | ||
693 | /* If STRUCT_RETURN is true, then the struct return address (in | |
694 | STRUCT_ADDR) will consume the first argument-passing register. | |
695 | Both adjust the register count and store that value. */ | |
696 | if (struct_return) | |
697 | { | |
698 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); | |
699 | argreg++; | |
700 | } | |
701 | ||
025bb325 | 702 | /* Now make sure there's space on the stack. */ |
d95a8903 | 703 | for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++) |
4991999e | 704 | stack_alloc += ((TYPE_LENGTH (value_type (args[argnum])) + 3) & ~3); |
025bb325 | 705 | sp -= stack_alloc; /* Make room on stack for args. */ |
d95a8903 AC |
706 | |
707 | for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++) | |
708 | { | |
4991999e | 709 | type = value_type (args[argnum]); |
d95a8903 AC |
710 | typecode = TYPE_CODE (type); |
711 | len = TYPE_LENGTH (type); | |
712 | ||
713 | memset (valbuf, 0, sizeof (valbuf)); | |
714 | ||
715 | /* Passes structures that do not fit in 2 registers by reference. */ | |
716 | if (len > 8 | |
717 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) | |
718 | { | |
e17a4113 UW |
719 | store_unsigned_integer (valbuf, 4, byte_order, |
720 | value_address (args[argnum])); | |
d95a8903 AC |
721 | typecode = TYPE_CODE_PTR; |
722 | len = 4; | |
723 | val = valbuf; | |
724 | } | |
725 | else if (len < 4) | |
726 | { | |
025bb325 | 727 | /* Value gets right-justified in the register or stack word. */ |
7e3dd49e | 728 | memcpy (valbuf + (register_size (gdbarch, argreg) - len), |
16ac4ab5 | 729 | (gdb_byte *) value_contents (args[argnum]), len); |
d95a8903 AC |
730 | val = valbuf; |
731 | } | |
732 | else | |
16ac4ab5 | 733 | val = (gdb_byte *) value_contents (args[argnum]); |
d95a8903 AC |
734 | |
735 | while (len > 0) | |
736 | { | |
737 | if (argreg > ARGN_REGNUM) | |
738 | { | |
025bb325 | 739 | /* Must go on the stack. */ |
d95a8903 AC |
740 | write_memory (sp + stack_offset, val, 4); |
741 | stack_offset += 4; | |
742 | } | |
743 | else if (argreg <= ARGN_REGNUM) | |
744 | { | |
025bb325 | 745 | /* There's room in a register. */ |
d95a8903 | 746 | regval = |
7e3dd49e | 747 | extract_unsigned_integer (val, |
e17a4113 UW |
748 | register_size (gdbarch, argreg), |
749 | byte_order); | |
d95a8903 AC |
750 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
751 | } | |
752 | ||
753 | /* Store the value 4 bytes at a time. This means that things | |
754 | larger than 4 bytes may go partly in registers and partly | |
755 | on the stack. */ | |
7e3dd49e AC |
756 | len -= register_size (gdbarch, argreg); |
757 | val += register_size (gdbarch, argreg); | |
d95a8903 AC |
758 | } |
759 | } | |
760 | ||
761 | /* Finally, update the SP register. */ | |
762 | regcache_cooked_write_unsigned (regcache, M32R_SP_REGNUM, sp); | |
763 | ||
764 | return sp; | |
765 | } | |
766 | ||
767 | ||
768 | /* Given a return value in `regbuf' with a type `valtype', | |
769 | extract and copy its value into `valbuf'. */ | |
770 | ||
771 | static void | |
772 | m32r_extract_return_value (struct type *type, struct regcache *regcache, | |
7c543f7b | 773 | gdb_byte *dst) |
d95a8903 | 774 | { |
e17a4113 UW |
775 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
776 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
d95a8903 AC |
777 | int len = TYPE_LENGTH (type); |
778 | ULONGEST tmp; | |
779 | ||
780 | /* By using store_unsigned_integer we avoid having to do | |
781 | anything special for small big-endian values. */ | |
782 | regcache_cooked_read_unsigned (regcache, RET1_REGNUM, &tmp); | |
7c543f7b | 783 | store_unsigned_integer (dst, (len > 4 ? len - 4 : len), byte_order, tmp); |
d95a8903 AC |
784 | |
785 | /* Ignore return values more than 8 bytes in size because the m32r | |
025bb325 | 786 | returns anything more than 8 bytes in the stack. */ |
d95a8903 AC |
787 | if (len > 4) |
788 | { | |
789 | regcache_cooked_read_unsigned (regcache, RET1_REGNUM + 1, &tmp); | |
7c543f7b | 790 | store_unsigned_integer (dst + len - 4, 4, byte_order, tmp); |
d95a8903 AC |
791 | } |
792 | } | |
793 | ||
63807e1d | 794 | static enum return_value_convention |
6a3a010b | 795 | m32r_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
796 | struct type *valtype, struct regcache *regcache, |
797 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
14588880 KI |
798 | { |
799 | if (TYPE_LENGTH (valtype) > 8) | |
800 | return RETURN_VALUE_STRUCT_CONVENTION; | |
801 | else | |
802 | { | |
803 | if (readbuf != NULL) | |
804 | m32r_extract_return_value (valtype, regcache, readbuf); | |
805 | if (writebuf != NULL) | |
806 | m32r_store_return_value (valtype, regcache, writebuf); | |
807 | return RETURN_VALUE_REGISTER_CONVENTION; | |
808 | } | |
809 | } | |
810 | ||
811 | ||
d95a8903 AC |
812 | |
813 | static CORE_ADDR | |
814 | m32r_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
815 | { | |
7e3dd49e | 816 | return frame_unwind_register_unsigned (next_frame, M32R_PC_REGNUM); |
d95a8903 AC |
817 | } |
818 | ||
819 | /* Given a GDB frame, determine the address of the calling function's | |
820 | frame. This will be used to create a new GDB frame struct. */ | |
821 | ||
822 | static void | |
94afd7a6 | 823 | m32r_frame_this_id (struct frame_info *this_frame, |
d95a8903 AC |
824 | void **this_prologue_cache, struct frame_id *this_id) |
825 | { | |
826 | struct m32r_unwind_cache *info | |
94afd7a6 | 827 | = m32r_frame_unwind_cache (this_frame, this_prologue_cache); |
d95a8903 AC |
828 | CORE_ADDR base; |
829 | CORE_ADDR func; | |
3b7344d5 | 830 | struct bound_minimal_symbol msym_stack; |
d95a8903 AC |
831 | struct frame_id id; |
832 | ||
833 | /* The FUNC is easy. */ | |
94afd7a6 | 834 | func = get_frame_func (this_frame); |
d95a8903 | 835 | |
d95a8903 AC |
836 | /* Check if the stack is empty. */ |
837 | msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL); | |
77e371c0 | 838 | if (msym_stack.minsym && info->base == BMSYMBOL_VALUE_ADDRESS (msym_stack)) |
d95a8903 AC |
839 | return; |
840 | ||
841 | /* Hopefully the prologue analysis either correctly determined the | |
842 | frame's base (which is the SP from the previous frame), or set | |
843 | that base to "NULL". */ | |
844 | base = info->prev_sp; | |
845 | if (base == 0) | |
846 | return; | |
847 | ||
848 | id = frame_id_build (base, func); | |
d95a8903 AC |
849 | (*this_id) = id; |
850 | } | |
851 | ||
94afd7a6 UW |
852 | static struct value * |
853 | m32r_frame_prev_register (struct frame_info *this_frame, | |
854 | void **this_prologue_cache, int regnum) | |
d95a8903 AC |
855 | { |
856 | struct m32r_unwind_cache *info | |
94afd7a6 UW |
857 | = m32r_frame_unwind_cache (this_frame, this_prologue_cache); |
858 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); | |
d95a8903 AC |
859 | } |
860 | ||
861 | static const struct frame_unwind m32r_frame_unwind = { | |
862 | NORMAL_FRAME, | |
8fbca658 | 863 | default_frame_unwind_stop_reason, |
d95a8903 | 864 | m32r_frame_this_id, |
94afd7a6 UW |
865 | m32r_frame_prev_register, |
866 | NULL, | |
867 | default_frame_sniffer | |
d95a8903 AC |
868 | }; |
869 | ||
d95a8903 | 870 | static CORE_ADDR |
94afd7a6 | 871 | m32r_frame_base_address (struct frame_info *this_frame, void **this_cache) |
d95a8903 AC |
872 | { |
873 | struct m32r_unwind_cache *info | |
94afd7a6 | 874 | = m32r_frame_unwind_cache (this_frame, this_cache); |
d95a8903 AC |
875 | return info->base; |
876 | } | |
877 | ||
878 | static const struct frame_base m32r_frame_base = { | |
879 | &m32r_frame_unwind, | |
880 | m32r_frame_base_address, | |
881 | m32r_frame_base_address, | |
882 | m32r_frame_base_address | |
883 | }; | |
884 | ||
94afd7a6 UW |
885 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy |
886 | frame. The frame ID's base needs to match the TOS value saved by | |
887 | save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */ | |
d95a8903 AC |
888 | |
889 | static struct frame_id | |
94afd7a6 | 890 | m32r_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
d95a8903 | 891 | { |
94afd7a6 UW |
892 | CORE_ADDR sp = get_frame_register_unsigned (this_frame, M32R_SP_REGNUM); |
893 | return frame_id_build (sp, get_frame_pc (this_frame)); | |
d95a8903 AC |
894 | } |
895 | ||
896 | ||
897 | static gdbarch_init_ftype m32r_gdbarch_init; | |
898 | ||
899 | static struct gdbarch * | |
900 | m32r_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
901 | { | |
902 | struct gdbarch *gdbarch; | |
903 | struct gdbarch_tdep *tdep; | |
904 | ||
905 | /* If there is already a candidate, use it. */ | |
906 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
907 | if (arches != NULL) | |
908 | return arches->gdbarch; | |
909 | ||
910 | /* Allocate space for the new architecture. */ | |
cdd238da | 911 | tdep = XCNEW (struct gdbarch_tdep); |
d95a8903 AC |
912 | gdbarch = gdbarch_alloc (&info, tdep); |
913 | ||
53375380 PA |
914 | set_gdbarch_wchar_bit (gdbarch, 16); |
915 | set_gdbarch_wchar_signed (gdbarch, 0); | |
916 | ||
d95a8903 | 917 | set_gdbarch_read_pc (gdbarch, m32r_read_pc); |
d95a8903 AC |
918 | set_gdbarch_unwind_sp (gdbarch, m32r_unwind_sp); |
919 | ||
e839132d | 920 | set_gdbarch_num_regs (gdbarch, M32R_NUM_REGS); |
d27b54ad | 921 | set_gdbarch_pc_regnum (gdbarch, M32R_PC_REGNUM); |
d95a8903 AC |
922 | set_gdbarch_sp_regnum (gdbarch, M32R_SP_REGNUM); |
923 | set_gdbarch_register_name (gdbarch, m32r_register_name); | |
924 | set_gdbarch_register_type (gdbarch, m32r_register_type); | |
925 | ||
d95a8903 | 926 | set_gdbarch_push_dummy_call (gdbarch, m32r_push_dummy_call); |
14588880 | 927 | set_gdbarch_return_value (gdbarch, m32r_return_value); |
d95a8903 AC |
928 | |
929 | set_gdbarch_skip_prologue (gdbarch, m32r_skip_prologue); | |
930 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
04180708 YQ |
931 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, m32r_breakpoint_kind_from_pc); |
932 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, m32r_sw_breakpoint_from_kind); | |
d95a8903 AC |
933 | set_gdbarch_memory_insert_breakpoint (gdbarch, |
934 | m32r_memory_insert_breakpoint); | |
935 | set_gdbarch_memory_remove_breakpoint (gdbarch, | |
936 | m32r_memory_remove_breakpoint); | |
937 | ||
d95a8903 AC |
938 | set_gdbarch_frame_align (gdbarch, m32r_frame_align); |
939 | ||
d95a8903 AC |
940 | frame_base_set_default (gdbarch, &m32r_frame_base); |
941 | ||
942 | /* Methods for saving / extracting a dummy frame's ID. The ID's | |
943 | stack address must match the SP value returned by | |
944 | PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */ | |
94afd7a6 | 945 | set_gdbarch_dummy_id (gdbarch, m32r_dummy_id); |
d95a8903 AC |
946 | |
947 | /* Return the unwound PC value. */ | |
948 | set_gdbarch_unwind_pc (gdbarch, m32r_unwind_pc); | |
949 | ||
c46b0409 KI |
950 | /* Hook in ABI-specific overrides, if they have been registered. */ |
951 | gdbarch_init_osabi (info, gdbarch); | |
952 | ||
953 | /* Hook in the default unwinders. */ | |
94afd7a6 | 954 | frame_unwind_append_unwinder (gdbarch, &m32r_frame_unwind); |
c46b0409 | 955 | |
1c772458 UW |
956 | /* Support simple overlay manager. */ |
957 | set_gdbarch_overlay_update (gdbarch, simple_overlay_update); | |
958 | ||
d95a8903 AC |
959 | return gdbarch; |
960 | } | |
961 | ||
962 | void | |
963 | _initialize_m32r_tdep (void) | |
964 | { | |
965 | register_gdbarch_init (bfd_arch_m32r, m32r_gdbarch_init); | |
966 | } |