Commit | Line | Data |
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d95a8903 AC |
1 | /* Target-dependent code for Renesas M32R, for GDB. |
2 | ||
b811d2c2 | 3 | Copyright (C) 1996-2020 Free Software Foundation, Inc. |
d95a8903 AC |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
d95a8903 AC |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
d95a8903 AC |
19 | |
20 | #include "defs.h" | |
21 | #include "frame.h" | |
22 | #include "frame-unwind.h" | |
23 | #include "frame-base.h" | |
24 | #include "symtab.h" | |
25 | #include "gdbtypes.h" | |
26 | #include "gdbcmd.h" | |
27 | #include "gdbcore.h" | |
d95a8903 AC |
28 | #include "value.h" |
29 | #include "inferior.h" | |
30 | #include "symfile.h" | |
31 | #include "objfiles.h" | |
c46b0409 | 32 | #include "osabi.h" |
d95a8903 AC |
33 | #include "language.h" |
34 | #include "arch-utils.h" | |
35 | #include "regcache.h" | |
36 | #include "trad-frame.h" | |
73e8eb51 | 37 | #include "dis-asm.h" |
9b32d526 | 38 | #include "m32r-tdep.h" |
325fac50 | 39 | #include <algorithm> |
d95a8903 | 40 | |
ab0538b8 AH |
41 | /* The size of the argument registers (r0 - r3) in bytes. */ |
42 | #define M32R_ARG_REGISTER_SIZE 4 | |
43 | ||
d95a8903 AC |
44 | /* Local functions */ |
45 | ||
d95a8903 AC |
46 | static CORE_ADDR |
47 | m32r_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
48 | { | |
49 | /* Align to the size of an instruction (so that they can safely be | |
50 | pushed onto the stack. */ | |
51 | return sp & ~3; | |
52 | } | |
53 | ||
d95a8903 | 54 | |
9f0b0322 KI |
55 | /* Breakpoints |
56 | ||
025bb325 | 57 | The little endian mode of M32R is unique. In most of architectures, |
9f0b0322 KI |
58 | two 16-bit instructions, A and B, are placed as the following: |
59 | ||
60 | Big endian: | |
61 | A0 A1 B0 B1 | |
62 | ||
63 | Little endian: | |
64 | A1 A0 B1 B0 | |
65 | ||
66 | In M32R, they are placed like this: | |
67 | ||
68 | Big endian: | |
69 | A0 A1 B0 B1 | |
70 | ||
71 | Little endian: | |
72 | B1 B0 A1 A0 | |
73 | ||
74 | This is because M32R always fetches instructions in 32-bit. | |
75 | ||
025bb325 | 76 | The following functions take care of this behavior. */ |
d95a8903 AC |
77 | |
78 | static int | |
ae4b2284 MD |
79 | m32r_memory_insert_breakpoint (struct gdbarch *gdbarch, |
80 | struct bp_target_info *bp_tgt) | |
d95a8903 | 81 | { |
0d5ed153 | 82 | CORE_ADDR addr = bp_tgt->placed_address = bp_tgt->reqstd_address; |
d95a8903 | 83 | int val; |
16ac4ab5 | 84 | gdb_byte buf[4]; |
35c63cd8 | 85 | gdb_byte contents_cache[4]; |
16ac4ab5 | 86 | gdb_byte bp_entry[] = { 0x10, 0xf1 }; /* dpt */ |
d95a8903 AC |
87 | |
88 | /* Save the memory contents. */ | |
9f0b0322 | 89 | val = target_read_memory (addr & 0xfffffffc, contents_cache, 4); |
d95a8903 AC |
90 | if (val != 0) |
91 | return val; /* return error */ | |
92 | ||
35c63cd8 | 93 | memcpy (bp_tgt->shadow_contents, contents_cache, 4); |
cd6c3b4f | 94 | bp_tgt->shadow_len = 4; |
8181d85f | 95 | |
d95a8903 | 96 | /* Determine appropriate breakpoint contents and size for this address. */ |
ae4b2284 | 97 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
d95a8903 | 98 | { |
9f0b0322 | 99 | if ((addr & 3) == 0) |
d95a8903 | 100 | { |
9f0b0322 KI |
101 | buf[0] = bp_entry[0]; |
102 | buf[1] = bp_entry[1]; | |
103 | buf[2] = contents_cache[2] & 0x7f; | |
104 | buf[3] = contents_cache[3]; | |
d95a8903 AC |
105 | } |
106 | else | |
107 | { | |
9f0b0322 KI |
108 | buf[0] = contents_cache[0]; |
109 | buf[1] = contents_cache[1]; | |
110 | buf[2] = bp_entry[0]; | |
111 | buf[3] = bp_entry[1]; | |
d95a8903 AC |
112 | } |
113 | } | |
9f0b0322 KI |
114 | else /* little-endian */ |
115 | { | |
116 | if ((addr & 3) == 0) | |
d95a8903 | 117 | { |
9f0b0322 KI |
118 | buf[0] = contents_cache[0]; |
119 | buf[1] = contents_cache[1] & 0x7f; | |
120 | buf[2] = bp_entry[1]; | |
121 | buf[3] = bp_entry[0]; | |
d95a8903 AC |
122 | } |
123 | else | |
124 | { | |
9f0b0322 KI |
125 | buf[0] = bp_entry[1]; |
126 | buf[1] = bp_entry[0]; | |
127 | buf[2] = contents_cache[2]; | |
128 | buf[3] = contents_cache[3]; | |
d95a8903 AC |
129 | } |
130 | } | |
131 | ||
132 | /* Write the breakpoint. */ | |
9f0b0322 | 133 | val = target_write_memory (addr & 0xfffffffc, buf, 4); |
d95a8903 AC |
134 | return val; |
135 | } | |
136 | ||
137 | static int | |
ae4b2284 MD |
138 | m32r_memory_remove_breakpoint (struct gdbarch *gdbarch, |
139 | struct bp_target_info *bp_tgt) | |
d95a8903 | 140 | { |
8181d85f | 141 | CORE_ADDR addr = bp_tgt->placed_address; |
d95a8903 | 142 | int val; |
16ac4ab5 | 143 | gdb_byte buf[4]; |
8181d85f | 144 | gdb_byte *contents_cache = bp_tgt->shadow_contents; |
d95a8903 | 145 | |
9f0b0322 KI |
146 | buf[0] = contents_cache[0]; |
147 | buf[1] = contents_cache[1]; | |
148 | buf[2] = contents_cache[2]; | |
149 | buf[3] = contents_cache[3]; | |
150 | ||
151 | /* Remove parallel bit. */ | |
ae4b2284 | 152 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
d95a8903 | 153 | { |
9f0b0322 KI |
154 | if ((buf[0] & 0x80) == 0 && (buf[2] & 0x80) != 0) |
155 | buf[2] &= 0x7f; | |
d95a8903 | 156 | } |
9f0b0322 | 157 | else /* little-endian */ |
d95a8903 | 158 | { |
9f0b0322 KI |
159 | if ((buf[3] & 0x80) == 0 && (buf[1] & 0x80) != 0) |
160 | buf[1] &= 0x7f; | |
d95a8903 AC |
161 | } |
162 | ||
163 | /* Write contents. */ | |
dd110abf | 164 | val = target_write_raw_memory (addr & 0xfffffffc, buf, 4); |
d95a8903 AC |
165 | return val; |
166 | } | |
167 | ||
cd6c3b4f YQ |
168 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ |
169 | ||
d19280ad YQ |
170 | static int |
171 | m32r_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
172 | { | |
173 | if ((*pcptr & 3) == 0) | |
174 | return 4; | |
175 | else | |
176 | return 2; | |
177 | } | |
178 | ||
cd6c3b4f YQ |
179 | /* Implement the sw_breakpoint_from_kind gdbarch method. */ |
180 | ||
16ac4ab5 | 181 | static const gdb_byte * |
d19280ad | 182 | m32r_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) |
d95a8903 | 183 | { |
025bb325 MS |
184 | static gdb_byte be_bp_entry[] = { |
185 | 0x10, 0xf1, 0x70, 0x00 | |
186 | }; /* dpt -> nop */ | |
187 | static gdb_byte le_bp_entry[] = { | |
188 | 0x00, 0x70, 0xf1, 0x10 | |
189 | }; /* dpt -> nop */ | |
d19280ad YQ |
190 | |
191 | *size = kind; | |
d95a8903 AC |
192 | |
193 | /* Determine appropriate breakpoint. */ | |
67d57894 | 194 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
d19280ad | 195 | return be_bp_entry; |
d95a8903 AC |
196 | else |
197 | { | |
d19280ad YQ |
198 | if (kind == 4) |
199 | return le_bp_entry; | |
d95a8903 | 200 | else |
d19280ad | 201 | return le_bp_entry + 2; |
d95a8903 | 202 | } |
d95a8903 AC |
203 | } |
204 | ||
a121b7c1 | 205 | static const char *m32r_register_names[] = { |
d95a8903 AC |
206 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
207 | "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp", | |
208 | "psw", "cbr", "spi", "spu", "bpc", "pc", "accl", "acch", | |
209 | "evb" | |
210 | }; | |
211 | ||
d95a8903 | 212 | static const char * |
d93859e2 | 213 | m32r_register_name (struct gdbarch *gdbarch, int reg_nr) |
d95a8903 AC |
214 | { |
215 | if (reg_nr < 0) | |
216 | return NULL; | |
9b32d526 | 217 | if (reg_nr >= M32R_NUM_REGS) |
d95a8903 AC |
218 | return NULL; |
219 | return m32r_register_names[reg_nr]; | |
220 | } | |
221 | ||
222 | ||
223 | /* Return the GDB type object for the "standard" data type | |
224 | of data in register N. */ | |
225 | ||
226 | static struct type * | |
227 | m32r_register_type (struct gdbarch *gdbarch, int reg_nr) | |
228 | { | |
229 | if (reg_nr == M32R_PC_REGNUM) | |
0dfff4cb | 230 | return builtin_type (gdbarch)->builtin_func_ptr; |
d95a8903 | 231 | else if (reg_nr == M32R_SP_REGNUM || reg_nr == M32R_FP_REGNUM) |
0dfff4cb | 232 | return builtin_type (gdbarch)->builtin_data_ptr; |
d95a8903 | 233 | else |
df4df182 | 234 | return builtin_type (gdbarch)->builtin_int32; |
d95a8903 AC |
235 | } |
236 | ||
237 | ||
238 | /* Write into appropriate registers a function return value | |
025bb325 | 239 | of type TYPE, given in virtual format. |
d95a8903 | 240 | |
025bb325 | 241 | Things always get returned in RET1_REGNUM, RET2_REGNUM. */ |
d95a8903 AC |
242 | |
243 | static void | |
244 | m32r_store_return_value (struct type *type, struct regcache *regcache, | |
7c543f7b | 245 | const gdb_byte *valbuf) |
d95a8903 | 246 | { |
ac7936df | 247 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 248 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d95a8903 AC |
249 | CORE_ADDR regval; |
250 | int len = TYPE_LENGTH (type); | |
251 | ||
e17a4113 | 252 | regval = extract_unsigned_integer (valbuf, len > 4 ? 4 : len, byte_order); |
d95a8903 AC |
253 | regcache_cooked_write_unsigned (regcache, RET1_REGNUM, regval); |
254 | ||
255 | if (len > 4) | |
256 | { | |
7c543f7b | 257 | regval = extract_unsigned_integer (valbuf + 4, |
e17a4113 | 258 | len - 4, byte_order); |
d95a8903 AC |
259 | regcache_cooked_write_unsigned (regcache, RET1_REGNUM + 1, regval); |
260 | } | |
261 | } | |
262 | ||
025bb325 | 263 | /* This is required by skip_prologue. The results of decoding a prologue |
d95a8903 AC |
264 | should be cached because this thrashing is getting nuts. */ |
265 | ||
cea15572 | 266 | static int |
e17a4113 UW |
267 | decode_prologue (struct gdbarch *gdbarch, |
268 | CORE_ADDR start_pc, CORE_ADDR scan_limit, | |
cea15572 | 269 | CORE_ADDR *pl_endptr, unsigned long *framelength) |
d95a8903 | 270 | { |
e17a4113 | 271 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d95a8903 AC |
272 | unsigned long framesize; |
273 | int insn; | |
274 | int op1; | |
d95a8903 | 275 | CORE_ADDR after_prologue = 0; |
cea15572 | 276 | CORE_ADDR after_push = 0; |
d95a8903 AC |
277 | CORE_ADDR after_stack_adjust = 0; |
278 | CORE_ADDR current_pc; | |
cea15572 | 279 | LONGEST return_value; |
d95a8903 AC |
280 | |
281 | framesize = 0; | |
282 | after_prologue = 0; | |
283 | ||
284 | for (current_pc = start_pc; current_pc < scan_limit; current_pc += 2) | |
285 | { | |
025bb325 | 286 | /* Check if current pc's location is readable. */ |
e17a4113 | 287 | if (!safe_read_memory_integer (current_pc, 2, byte_order, &return_value)) |
cea15572 KI |
288 | return -1; |
289 | ||
e17a4113 | 290 | insn = read_memory_unsigned_integer (current_pc, 2, byte_order); |
d95a8903 | 291 | |
cea15572 KI |
292 | if (insn == 0x0000) |
293 | break; | |
294 | ||
d95a8903 | 295 | /* If this is a 32 bit instruction, we dont want to examine its |
025bb325 | 296 | immediate data as though it were an instruction. */ |
d95a8903 AC |
297 | if (current_pc & 0x02) |
298 | { | |
025bb325 | 299 | /* Decode this instruction further. */ |
d95a8903 AC |
300 | insn &= 0x7fff; |
301 | } | |
302 | else | |
303 | { | |
d95a8903 AC |
304 | if (insn & 0x8000) |
305 | { | |
306 | if (current_pc == scan_limit) | |
307 | scan_limit += 2; /* extend the search */ | |
cea15572 | 308 | |
d95a8903 | 309 | current_pc += 2; /* skip the immediate data */ |
cea15572 | 310 | |
025bb325 | 311 | /* Check if current pc's location is readable. */ |
e17a4113 UW |
312 | if (!safe_read_memory_integer (current_pc, 2, byte_order, |
313 | &return_value)) | |
cea15572 KI |
314 | return -1; |
315 | ||
d95a8903 AC |
316 | if (insn == 0x8faf) /* add3 sp, sp, xxxx */ |
317 | /* add 16 bit sign-extended offset */ | |
318 | { | |
319 | framesize += | |
e17a4113 UW |
320 | -((short) read_memory_unsigned_integer (current_pc, |
321 | 2, byte_order)); | |
d95a8903 AC |
322 | } |
323 | else | |
324 | { | |
025bb325 | 325 | if (((insn >> 8) == 0xe4) /* ld24 r4, xxxxxx; sub sp, r4 */ |
e17a4113 UW |
326 | && safe_read_memory_integer (current_pc + 2, |
327 | 2, byte_order, | |
cea15572 | 328 | &return_value) |
7e3dd49e | 329 | && read_memory_unsigned_integer (current_pc + 2, |
e17a4113 UW |
330 | 2, byte_order) |
331 | == 0x0f24) | |
d95a8903 | 332 | { |
025bb325 | 333 | /* Subtract 24 bit sign-extended negative-offset. */ |
e17a4113 UW |
334 | insn = read_memory_unsigned_integer (current_pc - 2, |
335 | 4, byte_order); | |
d95a8903 AC |
336 | if (insn & 0x00800000) /* sign extend */ |
337 | insn |= 0xff000000; /* negative */ | |
338 | else | |
339 | insn &= 0x00ffffff; /* positive */ | |
340 | framesize += insn; | |
341 | } | |
342 | } | |
cea15572 | 343 | after_push = current_pc + 2; |
d95a8903 AC |
344 | continue; |
345 | } | |
346 | } | |
025bb325 | 347 | op1 = insn & 0xf000; /* Isolate just the first nibble. */ |
d95a8903 AC |
348 | |
349 | if ((insn & 0xf0ff) == 0x207f) | |
350 | { /* st reg, @-sp */ | |
d95a8903 | 351 | framesize += 4; |
d95a8903 AC |
352 | after_prologue = 0; |
353 | continue; | |
354 | } | |
355 | if ((insn >> 8) == 0x4f) /* addi sp, xx */ | |
025bb325 | 356 | /* Add 8 bit sign-extended offset. */ |
d95a8903 | 357 | { |
9ffbf372 | 358 | int stack_adjust = (signed char) (insn & 0xff); |
d95a8903 AC |
359 | |
360 | /* there are probably two of these stack adjustments: | |
361 | 1) A negative one in the prologue, and | |
362 | 2) A positive one in the epilogue. | |
363 | We are only interested in the first one. */ | |
364 | ||
365 | if (stack_adjust < 0) | |
366 | { | |
367 | framesize -= stack_adjust; | |
368 | after_prologue = 0; | |
369 | /* A frameless function may have no "mv fp, sp". | |
370 | In that case, this is the end of the prologue. */ | |
371 | after_stack_adjust = current_pc + 2; | |
372 | } | |
373 | continue; | |
374 | } | |
375 | if (insn == 0x1d8f) | |
376 | { /* mv fp, sp */ | |
377 | after_prologue = current_pc + 2; | |
378 | break; /* end of stack adjustments */ | |
379 | } | |
cea15572 | 380 | |
025bb325 | 381 | /* Nop looks like a branch, continue explicitly. */ |
d95a8903 AC |
382 | if (insn == 0x7000) |
383 | { | |
384 | after_prologue = current_pc + 2; | |
025bb325 | 385 | continue; /* nop occurs between pushes. */ |
d95a8903 | 386 | } |
025bb325 | 387 | /* End of prolog if any of these are trap instructions. */ |
cea15572 KI |
388 | if ((insn & 0xfff0) == 0x10f0) |
389 | { | |
390 | after_prologue = current_pc; | |
391 | break; | |
392 | } | |
025bb325 | 393 | /* End of prolog if any of these are branch instructions. */ |
d95a8903 AC |
394 | if ((op1 == 0x7000) || (op1 == 0xb000) || (op1 == 0xf000)) |
395 | { | |
396 | after_prologue = current_pc; | |
d95a8903 AC |
397 | continue; |
398 | } | |
025bb325 | 399 | /* Some of the branch instructions are mixed with other types. */ |
d95a8903 AC |
400 | if (op1 == 0x1000) |
401 | { | |
402 | int subop = insn & 0x0ff0; | |
403 | if ((subop == 0x0ec0) || (subop == 0x0fc0)) | |
404 | { | |
405 | after_prologue = current_pc; | |
d95a8903 AC |
406 | continue; /* jmp , jl */ |
407 | } | |
408 | } | |
409 | } | |
410 | ||
cea15572 KI |
411 | if (framelength) |
412 | *framelength = framesize; | |
413 | ||
d95a8903 AC |
414 | if (current_pc >= scan_limit) |
415 | { | |
416 | if (pl_endptr) | |
417 | { | |
418 | if (after_stack_adjust != 0) | |
419 | /* We did not find a "mv fp,sp", but we DID find | |
420 | a stack_adjust. Is it safe to use that as the | |
025bb325 | 421 | end of the prologue? I just don't know. */ |
d95a8903 AC |
422 | { |
423 | *pl_endptr = after_stack_adjust; | |
424 | } | |
cea15572 KI |
425 | else if (after_push != 0) |
426 | /* We did not find a "mv fp,sp", but we DID find | |
427 | a push. Is it safe to use that as the | |
025bb325 | 428 | end of the prologue? I just don't know. */ |
cea15572 KI |
429 | { |
430 | *pl_endptr = after_push; | |
431 | } | |
d95a8903 AC |
432 | else |
433 | /* We reached the end of the loop without finding the end | |
025bb325 MS |
434 | of the prologue. No way to win -- we should report |
435 | failure. The way we do that is to return the original | |
436 | start_pc. GDB will set a breakpoint at the start of | |
437 | the function (etc.) */ | |
d95a8903 AC |
438 | *pl_endptr = start_pc; |
439 | } | |
cea15572 | 440 | return 0; |
d95a8903 | 441 | } |
cea15572 | 442 | |
d95a8903 AC |
443 | if (after_prologue == 0) |
444 | after_prologue = current_pc; | |
445 | ||
446 | if (pl_endptr) | |
447 | *pl_endptr = after_prologue; | |
cea15572 KI |
448 | |
449 | return 0; | |
d95a8903 AC |
450 | } /* decode_prologue */ |
451 | ||
452 | /* Function: skip_prologue | |
025bb325 | 453 | Find end of function prologue. */ |
d95a8903 | 454 | |
cea15572 | 455 | #define DEFAULT_SEARCH_LIMIT 128 |
d95a8903 | 456 | |
63807e1d | 457 | static CORE_ADDR |
6093d2eb | 458 | m32r_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
d95a8903 | 459 | { |
e17a4113 | 460 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d95a8903 AC |
461 | CORE_ADDR func_addr, func_end; |
462 | struct symtab_and_line sal; | |
cea15572 | 463 | LONGEST return_value; |
d95a8903 | 464 | |
025bb325 | 465 | /* See what the symbol table says. */ |
d95a8903 AC |
466 | |
467 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
468 | { | |
469 | sal = find_pc_line (func_addr, 0); | |
470 | ||
471 | if (sal.line != 0 && sal.end <= func_end) | |
472 | { | |
473 | func_end = sal.end; | |
474 | } | |
475 | else | |
476 | /* Either there's no line info, or the line after the prologue is after | |
477 | the end of the function. In this case, there probably isn't a | |
478 | prologue. */ | |
479 | { | |
325fac50 | 480 | func_end = std::min (func_end, func_addr + DEFAULT_SEARCH_LIMIT); |
d95a8903 AC |
481 | } |
482 | } | |
483 | else | |
484 | func_end = pc + DEFAULT_SEARCH_LIMIT; | |
cea15572 | 485 | |
025bb325 | 486 | /* If pc's location is not readable, just quit. */ |
e17a4113 | 487 | if (!safe_read_memory_integer (pc, 4, byte_order, &return_value)) |
cea15572 KI |
488 | return pc; |
489 | ||
490 | /* Find the end of prologue. */ | |
e17a4113 | 491 | if (decode_prologue (gdbarch, pc, func_end, &sal.end, NULL) < 0) |
cea15572 KI |
492 | return pc; |
493 | ||
d95a8903 AC |
494 | return sal.end; |
495 | } | |
496 | ||
d95a8903 AC |
497 | struct m32r_unwind_cache |
498 | { | |
499 | /* The previous frame's inner most stack address. Used as this | |
500 | frame ID's stack_addr. */ | |
501 | CORE_ADDR prev_sp; | |
502 | /* The frame's base, optionally used by the high-level debug info. */ | |
503 | CORE_ADDR base; | |
504 | int size; | |
505 | /* How far the SP and r13 (FP) have been offset from the start of | |
506 | the stack frame (as defined by the previous frame's stack | |
507 | pointer). */ | |
508 | LONGEST sp_offset; | |
509 | LONGEST r13_offset; | |
510 | int uses_frame; | |
511 | /* Table indicating the location of each and every register. */ | |
512 | struct trad_frame_saved_reg *saved_regs; | |
513 | }; | |
514 | ||
515 | /* Put here the code to store, into fi->saved_regs, the addresses of | |
516 | the saved registers of frame described by FRAME_INFO. This | |
517 | includes special registers such as pc and fp saved in special ways | |
518 | in the stack frame. sp is even more special: the address we return | |
025bb325 | 519 | for it IS the sp for the next frame. */ |
d95a8903 AC |
520 | |
521 | static struct m32r_unwind_cache * | |
94afd7a6 | 522 | m32r_frame_unwind_cache (struct frame_info *this_frame, |
d95a8903 AC |
523 | void **this_prologue_cache) |
524 | { | |
cea15572 | 525 | CORE_ADDR pc, scan_limit; |
d95a8903 AC |
526 | ULONGEST prev_sp; |
527 | ULONGEST this_base; | |
22e048c9 | 528 | unsigned long op; |
d95a8903 AC |
529 | int i; |
530 | struct m32r_unwind_cache *info; | |
531 | ||
cea15572 | 532 | |
d95a8903 | 533 | if ((*this_prologue_cache)) |
9a3c8263 | 534 | return (struct m32r_unwind_cache *) (*this_prologue_cache); |
d95a8903 AC |
535 | |
536 | info = FRAME_OBSTACK_ZALLOC (struct m32r_unwind_cache); | |
537 | (*this_prologue_cache) = info; | |
94afd7a6 | 538 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
d95a8903 AC |
539 | |
540 | info->size = 0; | |
541 | info->sp_offset = 0; | |
d95a8903 | 542 | info->uses_frame = 0; |
cea15572 | 543 | |
94afd7a6 UW |
544 | scan_limit = get_frame_pc (this_frame); |
545 | for (pc = get_frame_func (this_frame); | |
cea15572 | 546 | pc > 0 && pc < scan_limit; pc += 2) |
d95a8903 AC |
547 | { |
548 | if ((pc & 2) == 0) | |
549 | { | |
94afd7a6 | 550 | op = get_frame_memory_unsigned (this_frame, pc, 4); |
d95a8903 AC |
551 | if ((op & 0x80000000) == 0x80000000) |
552 | { | |
553 | /* 32-bit instruction */ | |
554 | if ((op & 0xffff0000) == 0x8faf0000) | |
555 | { | |
556 | /* add3 sp,sp,xxxx */ | |
557 | short n = op & 0xffff; | |
558 | info->sp_offset += n; | |
559 | } | |
cea15572 | 560 | else if (((op >> 8) == 0xe4) |
94afd7a6 | 561 | && get_frame_memory_unsigned (this_frame, pc + 2, |
7e3dd49e | 562 | 2) == 0x0f24) |
d95a8903 | 563 | { |
cea15572 | 564 | /* ld24 r4, xxxxxx; sub sp, r4 */ |
d95a8903 AC |
565 | unsigned long n = op & 0xffffff; |
566 | info->sp_offset += n; | |
cea15572 | 567 | pc += 2; /* skip sub instruction */ |
d95a8903 | 568 | } |
d95a8903 | 569 | |
cea15572 KI |
570 | if (pc == scan_limit) |
571 | scan_limit += 2; /* extend the search */ | |
572 | pc += 2; /* skip the immediate data */ | |
d95a8903 AC |
573 | continue; |
574 | } | |
575 | } | |
576 | ||
577 | /* 16-bit instructions */ | |
94afd7a6 | 578 | op = get_frame_memory_unsigned (this_frame, pc, 2) & 0x7fff; |
d95a8903 AC |
579 | if ((op & 0xf0ff) == 0x207f) |
580 | { | |
581 | /* st rn, @-sp */ | |
582 | int regno = ((op >> 8) & 0xf); | |
583 | info->sp_offset -= 4; | |
584 | info->saved_regs[regno].addr = info->sp_offset; | |
585 | } | |
586 | else if ((op & 0xff00) == 0x4f00) | |
587 | { | |
588 | /* addi sp, xx */ | |
9ffbf372 | 589 | int n = (signed char) (op & 0xff); |
d95a8903 AC |
590 | info->sp_offset += n; |
591 | } | |
592 | else if (op == 0x1d8f) | |
593 | { | |
594 | /* mv fp, sp */ | |
595 | info->uses_frame = 1; | |
596 | info->r13_offset = info->sp_offset; | |
cea15572 KI |
597 | break; /* end of stack adjustments */ |
598 | } | |
599 | else if ((op & 0xfff0) == 0x10f0) | |
600 | { | |
025bb325 MS |
601 | /* End of prologue if this is a trap instruction. */ |
602 | break; /* End of stack adjustments. */ | |
d95a8903 | 603 | } |
d95a8903 AC |
604 | } |
605 | ||
606 | info->size = -info->sp_offset; | |
607 | ||
608 | /* Compute the previous frame's stack pointer (which is also the | |
609 | frame's ID's stack address), and this frame's base pointer. */ | |
610 | if (info->uses_frame) | |
611 | { | |
612 | /* The SP was moved to the FP. This indicates that a new frame | |
613 | was created. Get THIS frame's FP value by unwinding it from | |
614 | the next frame. */ | |
94afd7a6 | 615 | this_base = get_frame_register_unsigned (this_frame, M32R_FP_REGNUM); |
d95a8903 AC |
616 | /* The FP points at the last saved register. Adjust the FP back |
617 | to before the first saved register giving the SP. */ | |
618 | prev_sp = this_base + info->size; | |
619 | } | |
620 | else | |
621 | { | |
622 | /* Assume that the FP is this frame's SP but with that pushed | |
623 | stack space added back. */ | |
94afd7a6 | 624 | this_base = get_frame_register_unsigned (this_frame, M32R_SP_REGNUM); |
d95a8903 AC |
625 | prev_sp = this_base + info->size; |
626 | } | |
627 | ||
628 | /* Convert that SP/BASE into real addresses. */ | |
629 | info->prev_sp = prev_sp; | |
630 | info->base = this_base; | |
631 | ||
632 | /* Adjust all the saved registers so that they contain addresses and | |
633 | not offsets. */ | |
94afd7a6 | 634 | for (i = 0; i < gdbarch_num_regs (get_frame_arch (this_frame)) - 1; i++) |
d95a8903 AC |
635 | if (trad_frame_addr_p (info->saved_regs, i)) |
636 | info->saved_regs[i].addr = (info->prev_sp + info->saved_regs[i].addr); | |
637 | ||
638 | /* The call instruction moves the caller's PC in the callee's LR. | |
639 | Since this is an unwind, do the reverse. Copy the location of LR | |
640 | into PC (the address / regnum) so that a request for PC will be | |
641 | converted into a request for the LR. */ | |
642 | info->saved_regs[M32R_PC_REGNUM] = info->saved_regs[LR_REGNUM]; | |
643 | ||
644 | /* The previous frame's SP needed to be computed. Save the computed | |
645 | value. */ | |
646 | trad_frame_set_value (info->saved_regs, M32R_SP_REGNUM, prev_sp); | |
647 | ||
648 | return info; | |
649 | } | |
650 | ||
d95a8903 | 651 | static CORE_ADDR |
7d9b040b | 652 | m32r_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
d95a8903 | 653 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
cf84fa6b AH |
654 | struct value **args, CORE_ADDR sp, |
655 | function_call_return_method return_method, | |
d95a8903 AC |
656 | CORE_ADDR struct_addr) |
657 | { | |
e17a4113 | 658 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d95a8903 AC |
659 | int stack_offset, stack_alloc; |
660 | int argreg = ARG1_REGNUM; | |
661 | int argnum; | |
662 | struct type *type; | |
663 | enum type_code typecode; | |
664 | CORE_ADDR regval; | |
16ac4ab5 | 665 | gdb_byte *val; |
ab0538b8 | 666 | gdb_byte valbuf[M32R_ARG_REGISTER_SIZE]; |
d95a8903 | 667 | int len; |
d95a8903 | 668 | |
025bb325 | 669 | /* First force sp to a 4-byte alignment. */ |
d95a8903 AC |
670 | sp = sp & ~3; |
671 | ||
672 | /* Set the return address. For the m32r, the return breakpoint is | |
673 | always at BP_ADDR. */ | |
674 | regcache_cooked_write_unsigned (regcache, LR_REGNUM, bp_addr); | |
675 | ||
676 | /* If STRUCT_RETURN is true, then the struct return address (in | |
677 | STRUCT_ADDR) will consume the first argument-passing register. | |
678 | Both adjust the register count and store that value. */ | |
cf84fa6b | 679 | if (return_method == return_method_struct) |
d95a8903 AC |
680 | { |
681 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); | |
682 | argreg++; | |
683 | } | |
684 | ||
025bb325 | 685 | /* Now make sure there's space on the stack. */ |
d95a8903 | 686 | for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++) |
4991999e | 687 | stack_alloc += ((TYPE_LENGTH (value_type (args[argnum])) + 3) & ~3); |
025bb325 | 688 | sp -= stack_alloc; /* Make room on stack for args. */ |
d95a8903 AC |
689 | |
690 | for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++) | |
691 | { | |
4991999e | 692 | type = value_type (args[argnum]); |
d95a8903 AC |
693 | typecode = TYPE_CODE (type); |
694 | len = TYPE_LENGTH (type); | |
695 | ||
696 | memset (valbuf, 0, sizeof (valbuf)); | |
697 | ||
698 | /* Passes structures that do not fit in 2 registers by reference. */ | |
699 | if (len > 8 | |
700 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) | |
701 | { | |
e17a4113 UW |
702 | store_unsigned_integer (valbuf, 4, byte_order, |
703 | value_address (args[argnum])); | |
d95a8903 AC |
704 | typecode = TYPE_CODE_PTR; |
705 | len = 4; | |
706 | val = valbuf; | |
707 | } | |
708 | else if (len < 4) | |
709 | { | |
025bb325 | 710 | /* Value gets right-justified in the register or stack word. */ |
7e3dd49e | 711 | memcpy (valbuf + (register_size (gdbarch, argreg) - len), |
16ac4ab5 | 712 | (gdb_byte *) value_contents (args[argnum]), len); |
d95a8903 AC |
713 | val = valbuf; |
714 | } | |
715 | else | |
16ac4ab5 | 716 | val = (gdb_byte *) value_contents (args[argnum]); |
d95a8903 AC |
717 | |
718 | while (len > 0) | |
719 | { | |
720 | if (argreg > ARGN_REGNUM) | |
721 | { | |
025bb325 | 722 | /* Must go on the stack. */ |
d95a8903 AC |
723 | write_memory (sp + stack_offset, val, 4); |
724 | stack_offset += 4; | |
725 | } | |
726 | else if (argreg <= ARGN_REGNUM) | |
727 | { | |
025bb325 | 728 | /* There's room in a register. */ |
d95a8903 | 729 | regval = |
7e3dd49e | 730 | extract_unsigned_integer (val, |
e17a4113 UW |
731 | register_size (gdbarch, argreg), |
732 | byte_order); | |
d95a8903 AC |
733 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
734 | } | |
735 | ||
736 | /* Store the value 4 bytes at a time. This means that things | |
737 | larger than 4 bytes may go partly in registers and partly | |
738 | on the stack. */ | |
7e3dd49e AC |
739 | len -= register_size (gdbarch, argreg); |
740 | val += register_size (gdbarch, argreg); | |
d95a8903 AC |
741 | } |
742 | } | |
743 | ||
744 | /* Finally, update the SP register. */ | |
745 | regcache_cooked_write_unsigned (regcache, M32R_SP_REGNUM, sp); | |
746 | ||
747 | return sp; | |
748 | } | |
749 | ||
750 | ||
751 | /* Given a return value in `regbuf' with a type `valtype', | |
752 | extract and copy its value into `valbuf'. */ | |
753 | ||
754 | static void | |
755 | m32r_extract_return_value (struct type *type, struct regcache *regcache, | |
7c543f7b | 756 | gdb_byte *dst) |
d95a8903 | 757 | { |
ac7936df | 758 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 759 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d95a8903 AC |
760 | int len = TYPE_LENGTH (type); |
761 | ULONGEST tmp; | |
762 | ||
763 | /* By using store_unsigned_integer we avoid having to do | |
764 | anything special for small big-endian values. */ | |
765 | regcache_cooked_read_unsigned (regcache, RET1_REGNUM, &tmp); | |
7c543f7b | 766 | store_unsigned_integer (dst, (len > 4 ? len - 4 : len), byte_order, tmp); |
d95a8903 AC |
767 | |
768 | /* Ignore return values more than 8 bytes in size because the m32r | |
025bb325 | 769 | returns anything more than 8 bytes in the stack. */ |
d95a8903 AC |
770 | if (len > 4) |
771 | { | |
772 | regcache_cooked_read_unsigned (regcache, RET1_REGNUM + 1, &tmp); | |
7c543f7b | 773 | store_unsigned_integer (dst + len - 4, 4, byte_order, tmp); |
d95a8903 AC |
774 | } |
775 | } | |
776 | ||
63807e1d | 777 | static enum return_value_convention |
6a3a010b | 778 | m32r_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
779 | struct type *valtype, struct regcache *regcache, |
780 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
14588880 KI |
781 | { |
782 | if (TYPE_LENGTH (valtype) > 8) | |
783 | return RETURN_VALUE_STRUCT_CONVENTION; | |
784 | else | |
785 | { | |
786 | if (readbuf != NULL) | |
787 | m32r_extract_return_value (valtype, regcache, readbuf); | |
788 | if (writebuf != NULL) | |
789 | m32r_store_return_value (valtype, regcache, writebuf); | |
790 | return RETURN_VALUE_REGISTER_CONVENTION; | |
791 | } | |
792 | } | |
793 | ||
d95a8903 AC |
794 | /* Given a GDB frame, determine the address of the calling function's |
795 | frame. This will be used to create a new GDB frame struct. */ | |
796 | ||
797 | static void | |
94afd7a6 | 798 | m32r_frame_this_id (struct frame_info *this_frame, |
d95a8903 AC |
799 | void **this_prologue_cache, struct frame_id *this_id) |
800 | { | |
801 | struct m32r_unwind_cache *info | |
94afd7a6 | 802 | = m32r_frame_unwind_cache (this_frame, this_prologue_cache); |
d95a8903 AC |
803 | CORE_ADDR base; |
804 | CORE_ADDR func; | |
3b7344d5 | 805 | struct bound_minimal_symbol msym_stack; |
d95a8903 AC |
806 | struct frame_id id; |
807 | ||
808 | /* The FUNC is easy. */ | |
94afd7a6 | 809 | func = get_frame_func (this_frame); |
d95a8903 | 810 | |
d95a8903 AC |
811 | /* Check if the stack is empty. */ |
812 | msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL); | |
77e371c0 | 813 | if (msym_stack.minsym && info->base == BMSYMBOL_VALUE_ADDRESS (msym_stack)) |
d95a8903 AC |
814 | return; |
815 | ||
816 | /* Hopefully the prologue analysis either correctly determined the | |
817 | frame's base (which is the SP from the previous frame), or set | |
818 | that base to "NULL". */ | |
819 | base = info->prev_sp; | |
820 | if (base == 0) | |
821 | return; | |
822 | ||
823 | id = frame_id_build (base, func); | |
d95a8903 AC |
824 | (*this_id) = id; |
825 | } | |
826 | ||
94afd7a6 UW |
827 | static struct value * |
828 | m32r_frame_prev_register (struct frame_info *this_frame, | |
829 | void **this_prologue_cache, int regnum) | |
d95a8903 AC |
830 | { |
831 | struct m32r_unwind_cache *info | |
94afd7a6 UW |
832 | = m32r_frame_unwind_cache (this_frame, this_prologue_cache); |
833 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); | |
d95a8903 AC |
834 | } |
835 | ||
836 | static const struct frame_unwind m32r_frame_unwind = { | |
837 | NORMAL_FRAME, | |
8fbca658 | 838 | default_frame_unwind_stop_reason, |
d95a8903 | 839 | m32r_frame_this_id, |
94afd7a6 UW |
840 | m32r_frame_prev_register, |
841 | NULL, | |
842 | default_frame_sniffer | |
d95a8903 AC |
843 | }; |
844 | ||
d95a8903 | 845 | static CORE_ADDR |
94afd7a6 | 846 | m32r_frame_base_address (struct frame_info *this_frame, void **this_cache) |
d95a8903 AC |
847 | { |
848 | struct m32r_unwind_cache *info | |
94afd7a6 | 849 | = m32r_frame_unwind_cache (this_frame, this_cache); |
d95a8903 AC |
850 | return info->base; |
851 | } | |
852 | ||
853 | static const struct frame_base m32r_frame_base = { | |
854 | &m32r_frame_unwind, | |
855 | m32r_frame_base_address, | |
856 | m32r_frame_base_address, | |
857 | m32r_frame_base_address | |
858 | }; | |
859 | ||
d95a8903 AC |
860 | static gdbarch_init_ftype m32r_gdbarch_init; |
861 | ||
862 | static struct gdbarch * | |
863 | m32r_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
864 | { | |
865 | struct gdbarch *gdbarch; | |
866 | struct gdbarch_tdep *tdep; | |
867 | ||
868 | /* If there is already a candidate, use it. */ | |
869 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
870 | if (arches != NULL) | |
871 | return arches->gdbarch; | |
872 | ||
873 | /* Allocate space for the new architecture. */ | |
cdd238da | 874 | tdep = XCNEW (struct gdbarch_tdep); |
d95a8903 AC |
875 | gdbarch = gdbarch_alloc (&info, tdep); |
876 | ||
53375380 PA |
877 | set_gdbarch_wchar_bit (gdbarch, 16); |
878 | set_gdbarch_wchar_signed (gdbarch, 0); | |
879 | ||
e839132d | 880 | set_gdbarch_num_regs (gdbarch, M32R_NUM_REGS); |
d27b54ad | 881 | set_gdbarch_pc_regnum (gdbarch, M32R_PC_REGNUM); |
d95a8903 AC |
882 | set_gdbarch_sp_regnum (gdbarch, M32R_SP_REGNUM); |
883 | set_gdbarch_register_name (gdbarch, m32r_register_name); | |
884 | set_gdbarch_register_type (gdbarch, m32r_register_type); | |
885 | ||
d95a8903 | 886 | set_gdbarch_push_dummy_call (gdbarch, m32r_push_dummy_call); |
14588880 | 887 | set_gdbarch_return_value (gdbarch, m32r_return_value); |
d95a8903 AC |
888 | |
889 | set_gdbarch_skip_prologue (gdbarch, m32r_skip_prologue); | |
890 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
04180708 YQ |
891 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, m32r_breakpoint_kind_from_pc); |
892 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, m32r_sw_breakpoint_from_kind); | |
d95a8903 AC |
893 | set_gdbarch_memory_insert_breakpoint (gdbarch, |
894 | m32r_memory_insert_breakpoint); | |
895 | set_gdbarch_memory_remove_breakpoint (gdbarch, | |
896 | m32r_memory_remove_breakpoint); | |
897 | ||
d95a8903 AC |
898 | set_gdbarch_frame_align (gdbarch, m32r_frame_align); |
899 | ||
d95a8903 AC |
900 | frame_base_set_default (gdbarch, &m32r_frame_base); |
901 | ||
c46b0409 KI |
902 | /* Hook in ABI-specific overrides, if they have been registered. */ |
903 | gdbarch_init_osabi (info, gdbarch); | |
904 | ||
905 | /* Hook in the default unwinders. */ | |
94afd7a6 | 906 | frame_unwind_append_unwinder (gdbarch, &m32r_frame_unwind); |
c46b0409 | 907 | |
1c772458 UW |
908 | /* Support simple overlay manager. */ |
909 | set_gdbarch_overlay_update (gdbarch, simple_overlay_update); | |
910 | ||
d95a8903 AC |
911 | return gdbarch; |
912 | } | |
913 | ||
914 | void | |
915 | _initialize_m32r_tdep (void) | |
916 | { | |
917 | register_gdbarch_init (bfd_arch_m32r, m32r_gdbarch_init); | |
918 | } |