Commit | Line | Data |
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d95a8903 AC |
1 | /* Target-dependent code for Renesas M32R, for GDB. |
2 | ||
9b254dd1 | 3 | Copyright (C) 1996, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, |
0fb0cc75 | 4 | 2008, 2009 Free Software Foundation, Inc. |
d95a8903 AC |
5 | |
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 10 | the Free Software Foundation; either version 3 of the License, or |
d95a8903 AC |
11 | (at your option) any later version. |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
d95a8903 AC |
20 | |
21 | #include "defs.h" | |
22 | #include "frame.h" | |
23 | #include "frame-unwind.h" | |
24 | #include "frame-base.h" | |
25 | #include "symtab.h" | |
26 | #include "gdbtypes.h" | |
27 | #include "gdbcmd.h" | |
28 | #include "gdbcore.h" | |
29 | #include "gdb_string.h" | |
30 | #include "value.h" | |
31 | #include "inferior.h" | |
32 | #include "symfile.h" | |
33 | #include "objfiles.h" | |
c46b0409 | 34 | #include "osabi.h" |
d95a8903 AC |
35 | #include "language.h" |
36 | #include "arch-utils.h" | |
37 | #include "regcache.h" | |
38 | #include "trad-frame.h" | |
73e8eb51 | 39 | #include "dis-asm.h" |
d95a8903 AC |
40 | |
41 | #include "gdb_assert.h" | |
42 | ||
9b32d526 | 43 | #include "m32r-tdep.h" |
d95a8903 AC |
44 | |
45 | /* Local functions */ | |
46 | ||
47 | extern void _initialize_m32r_tdep (void); | |
48 | ||
49 | static CORE_ADDR | |
50 | m32r_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
51 | { | |
52 | /* Align to the size of an instruction (so that they can safely be | |
53 | pushed onto the stack. */ | |
54 | return sp & ~3; | |
55 | } | |
56 | ||
d95a8903 | 57 | |
9f0b0322 KI |
58 | /* Breakpoints |
59 | ||
60 | The little endian mode of M32R is unique. In most of architectures, | |
61 | two 16-bit instructions, A and B, are placed as the following: | |
62 | ||
63 | Big endian: | |
64 | A0 A1 B0 B1 | |
65 | ||
66 | Little endian: | |
67 | A1 A0 B1 B0 | |
68 | ||
69 | In M32R, they are placed like this: | |
70 | ||
71 | Big endian: | |
72 | A0 A1 B0 B1 | |
73 | ||
74 | Little endian: | |
75 | B1 B0 A1 A0 | |
76 | ||
77 | This is because M32R always fetches instructions in 32-bit. | |
78 | ||
79 | The following functions take care of this behavior. */ | |
d95a8903 AC |
80 | |
81 | static int | |
ae4b2284 MD |
82 | m32r_memory_insert_breakpoint (struct gdbarch *gdbarch, |
83 | struct bp_target_info *bp_tgt) | |
d95a8903 | 84 | { |
8181d85f | 85 | CORE_ADDR addr = bp_tgt->placed_address; |
d95a8903 | 86 | int val; |
16ac4ab5 | 87 | gdb_byte buf[4]; |
8181d85f | 88 | gdb_byte *contents_cache = bp_tgt->shadow_contents; |
16ac4ab5 | 89 | gdb_byte bp_entry[] = { 0x10, 0xf1 }; /* dpt */ |
d95a8903 AC |
90 | |
91 | /* Save the memory contents. */ | |
9f0b0322 | 92 | val = target_read_memory (addr & 0xfffffffc, contents_cache, 4); |
d95a8903 AC |
93 | if (val != 0) |
94 | return val; /* return error */ | |
95 | ||
8181d85f DJ |
96 | bp_tgt->placed_size = bp_tgt->shadow_len = 4; |
97 | ||
d95a8903 | 98 | /* Determine appropriate breakpoint contents and size for this address. */ |
ae4b2284 | 99 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
d95a8903 | 100 | { |
9f0b0322 | 101 | if ((addr & 3) == 0) |
d95a8903 | 102 | { |
9f0b0322 KI |
103 | buf[0] = bp_entry[0]; |
104 | buf[1] = bp_entry[1]; | |
105 | buf[2] = contents_cache[2] & 0x7f; | |
106 | buf[3] = contents_cache[3]; | |
d95a8903 AC |
107 | } |
108 | else | |
109 | { | |
9f0b0322 KI |
110 | buf[0] = contents_cache[0]; |
111 | buf[1] = contents_cache[1]; | |
112 | buf[2] = bp_entry[0]; | |
113 | buf[3] = bp_entry[1]; | |
d95a8903 AC |
114 | } |
115 | } | |
9f0b0322 KI |
116 | else /* little-endian */ |
117 | { | |
118 | if ((addr & 3) == 0) | |
d95a8903 | 119 | { |
9f0b0322 KI |
120 | buf[0] = contents_cache[0]; |
121 | buf[1] = contents_cache[1] & 0x7f; | |
122 | buf[2] = bp_entry[1]; | |
123 | buf[3] = bp_entry[0]; | |
d95a8903 AC |
124 | } |
125 | else | |
126 | { | |
9f0b0322 KI |
127 | buf[0] = bp_entry[1]; |
128 | buf[1] = bp_entry[0]; | |
129 | buf[2] = contents_cache[2]; | |
130 | buf[3] = contents_cache[3]; | |
d95a8903 AC |
131 | } |
132 | } | |
133 | ||
134 | /* Write the breakpoint. */ | |
9f0b0322 | 135 | val = target_write_memory (addr & 0xfffffffc, buf, 4); |
d95a8903 AC |
136 | return val; |
137 | } | |
138 | ||
139 | static int | |
ae4b2284 MD |
140 | m32r_memory_remove_breakpoint (struct gdbarch *gdbarch, |
141 | struct bp_target_info *bp_tgt) | |
d95a8903 | 142 | { |
8181d85f | 143 | CORE_ADDR addr = bp_tgt->placed_address; |
d95a8903 | 144 | int val; |
16ac4ab5 | 145 | gdb_byte buf[4]; |
8181d85f | 146 | gdb_byte *contents_cache = bp_tgt->shadow_contents; |
d95a8903 | 147 | |
9f0b0322 KI |
148 | buf[0] = contents_cache[0]; |
149 | buf[1] = contents_cache[1]; | |
150 | buf[2] = contents_cache[2]; | |
151 | buf[3] = contents_cache[3]; | |
152 | ||
153 | /* Remove parallel bit. */ | |
ae4b2284 | 154 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
d95a8903 | 155 | { |
9f0b0322 KI |
156 | if ((buf[0] & 0x80) == 0 && (buf[2] & 0x80) != 0) |
157 | buf[2] &= 0x7f; | |
d95a8903 | 158 | } |
9f0b0322 | 159 | else /* little-endian */ |
d95a8903 | 160 | { |
9f0b0322 KI |
161 | if ((buf[3] & 0x80) == 0 && (buf[1] & 0x80) != 0) |
162 | buf[1] &= 0x7f; | |
d95a8903 AC |
163 | } |
164 | ||
165 | /* Write contents. */ | |
9f0b0322 | 166 | val = target_write_memory (addr & 0xfffffffc, buf, 4); |
d95a8903 AC |
167 | return val; |
168 | } | |
169 | ||
16ac4ab5 | 170 | static const gdb_byte * |
67d57894 | 171 | m32r_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr) |
d95a8903 | 172 | { |
16ac4ab5 KI |
173 | static gdb_byte be_bp_entry[] = { 0x10, 0xf1, 0x70, 0x00 }; /* dpt -> nop */ |
174 | static gdb_byte le_bp_entry[] = { 0x00, 0x70, 0xf1, 0x10 }; /* dpt -> nop */ | |
175 | gdb_byte *bp; | |
d95a8903 AC |
176 | |
177 | /* Determine appropriate breakpoint. */ | |
67d57894 | 178 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
d95a8903 AC |
179 | { |
180 | if ((*pcptr & 3) == 0) | |
181 | { | |
9f0b0322 KI |
182 | bp = be_bp_entry; |
183 | *lenptr = 4; | |
d95a8903 AC |
184 | } |
185 | else | |
186 | { | |
9f0b0322 KI |
187 | bp = be_bp_entry; |
188 | *lenptr = 2; | |
d95a8903 AC |
189 | } |
190 | } | |
191 | else | |
192 | { | |
193 | if ((*pcptr & 3) == 0) | |
194 | { | |
9f0b0322 KI |
195 | bp = le_bp_entry; |
196 | *lenptr = 4; | |
d95a8903 AC |
197 | } |
198 | else | |
199 | { | |
9f0b0322 KI |
200 | bp = le_bp_entry + 2; |
201 | *lenptr = 2; | |
d95a8903 AC |
202 | } |
203 | } | |
204 | ||
205 | return bp; | |
206 | } | |
207 | ||
208 | ||
209 | char *m32r_register_names[] = { | |
210 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
211 | "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp", | |
212 | "psw", "cbr", "spi", "spu", "bpc", "pc", "accl", "acch", | |
213 | "evb" | |
214 | }; | |
215 | ||
d95a8903 | 216 | static const char * |
d93859e2 | 217 | m32r_register_name (struct gdbarch *gdbarch, int reg_nr) |
d95a8903 AC |
218 | { |
219 | if (reg_nr < 0) | |
220 | return NULL; | |
9b32d526 | 221 | if (reg_nr >= M32R_NUM_REGS) |
d95a8903 AC |
222 | return NULL; |
223 | return m32r_register_names[reg_nr]; | |
224 | } | |
225 | ||
226 | ||
227 | /* Return the GDB type object for the "standard" data type | |
228 | of data in register N. */ | |
229 | ||
230 | static struct type * | |
231 | m32r_register_type (struct gdbarch *gdbarch, int reg_nr) | |
232 | { | |
233 | if (reg_nr == M32R_PC_REGNUM) | |
0dfff4cb | 234 | return builtin_type (gdbarch)->builtin_func_ptr; |
d95a8903 | 235 | else if (reg_nr == M32R_SP_REGNUM || reg_nr == M32R_FP_REGNUM) |
0dfff4cb | 236 | return builtin_type (gdbarch)->builtin_data_ptr; |
d95a8903 | 237 | else |
df4df182 | 238 | return builtin_type (gdbarch)->builtin_int32; |
d95a8903 AC |
239 | } |
240 | ||
241 | ||
242 | /* Write into appropriate registers a function return value | |
243 | of type TYPE, given in virtual format. | |
244 | ||
245 | Things always get returned in RET1_REGNUM, RET2_REGNUM. */ | |
246 | ||
247 | static void | |
248 | m32r_store_return_value (struct type *type, struct regcache *regcache, | |
249 | const void *valbuf) | |
250 | { | |
e17a4113 UW |
251 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
252 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
d95a8903 AC |
253 | CORE_ADDR regval; |
254 | int len = TYPE_LENGTH (type); | |
255 | ||
e17a4113 | 256 | regval = extract_unsigned_integer (valbuf, len > 4 ? 4 : len, byte_order); |
d95a8903 AC |
257 | regcache_cooked_write_unsigned (regcache, RET1_REGNUM, regval); |
258 | ||
259 | if (len > 4) | |
260 | { | |
e17a4113 UW |
261 | regval = extract_unsigned_integer ((gdb_byte *) valbuf + 4, |
262 | len - 4, byte_order); | |
d95a8903 AC |
263 | regcache_cooked_write_unsigned (regcache, RET1_REGNUM + 1, regval); |
264 | } | |
265 | } | |
266 | ||
d95a8903 AC |
267 | /* This is required by skip_prologue. The results of decoding a prologue |
268 | should be cached because this thrashing is getting nuts. */ | |
269 | ||
cea15572 | 270 | static int |
e17a4113 UW |
271 | decode_prologue (struct gdbarch *gdbarch, |
272 | CORE_ADDR start_pc, CORE_ADDR scan_limit, | |
cea15572 | 273 | CORE_ADDR *pl_endptr, unsigned long *framelength) |
d95a8903 | 274 | { |
e17a4113 | 275 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d95a8903 AC |
276 | unsigned long framesize; |
277 | int insn; | |
278 | int op1; | |
d95a8903 | 279 | CORE_ADDR after_prologue = 0; |
cea15572 | 280 | CORE_ADDR after_push = 0; |
d95a8903 AC |
281 | CORE_ADDR after_stack_adjust = 0; |
282 | CORE_ADDR current_pc; | |
cea15572 | 283 | LONGEST return_value; |
d95a8903 AC |
284 | |
285 | framesize = 0; | |
286 | after_prologue = 0; | |
287 | ||
288 | for (current_pc = start_pc; current_pc < scan_limit; current_pc += 2) | |
289 | { | |
cea15572 | 290 | /* Check if current pc's location is readable. */ |
e17a4113 | 291 | if (!safe_read_memory_integer (current_pc, 2, byte_order, &return_value)) |
cea15572 KI |
292 | return -1; |
293 | ||
e17a4113 | 294 | insn = read_memory_unsigned_integer (current_pc, 2, byte_order); |
d95a8903 | 295 | |
cea15572 KI |
296 | if (insn == 0x0000) |
297 | break; | |
298 | ||
d95a8903 AC |
299 | /* If this is a 32 bit instruction, we dont want to examine its |
300 | immediate data as though it were an instruction */ | |
301 | if (current_pc & 0x02) | |
302 | { | |
d95a8903 AC |
303 | /* decode this instruction further */ |
304 | insn &= 0x7fff; | |
305 | } | |
306 | else | |
307 | { | |
d95a8903 AC |
308 | if (insn & 0x8000) |
309 | { | |
310 | if (current_pc == scan_limit) | |
311 | scan_limit += 2; /* extend the search */ | |
cea15572 | 312 | |
d95a8903 | 313 | current_pc += 2; /* skip the immediate data */ |
cea15572 KI |
314 | |
315 | /* Check if current pc's location is readable. */ | |
e17a4113 UW |
316 | if (!safe_read_memory_integer (current_pc, 2, byte_order, |
317 | &return_value)) | |
cea15572 KI |
318 | return -1; |
319 | ||
d95a8903 AC |
320 | if (insn == 0x8faf) /* add3 sp, sp, xxxx */ |
321 | /* add 16 bit sign-extended offset */ | |
322 | { | |
323 | framesize += | |
e17a4113 UW |
324 | -((short) read_memory_unsigned_integer (current_pc, |
325 | 2, byte_order)); | |
d95a8903 AC |
326 | } |
327 | else | |
328 | { | |
7e3dd49e | 329 | if (((insn >> 8) == 0xe4) /* ld24 r4, xxxxxx; sub sp, r4 */ |
e17a4113 UW |
330 | && safe_read_memory_integer (current_pc + 2, |
331 | 2, byte_order, | |
cea15572 | 332 | &return_value) |
7e3dd49e | 333 | && read_memory_unsigned_integer (current_pc + 2, |
e17a4113 UW |
334 | 2, byte_order) |
335 | == 0x0f24) | |
d95a8903 AC |
336 | /* subtract 24 bit sign-extended negative-offset */ |
337 | { | |
e17a4113 UW |
338 | insn = read_memory_unsigned_integer (current_pc - 2, |
339 | 4, byte_order); | |
d95a8903 AC |
340 | if (insn & 0x00800000) /* sign extend */ |
341 | insn |= 0xff000000; /* negative */ | |
342 | else | |
343 | insn &= 0x00ffffff; /* positive */ | |
344 | framesize += insn; | |
345 | } | |
346 | } | |
cea15572 | 347 | after_push = current_pc + 2; |
d95a8903 AC |
348 | continue; |
349 | } | |
350 | } | |
351 | op1 = insn & 0xf000; /* isolate just the first nibble */ | |
352 | ||
353 | if ((insn & 0xf0ff) == 0x207f) | |
354 | { /* st reg, @-sp */ | |
355 | int regno; | |
356 | framesize += 4; | |
357 | regno = ((insn >> 8) & 0xf); | |
358 | after_prologue = 0; | |
359 | continue; | |
360 | } | |
361 | if ((insn >> 8) == 0x4f) /* addi sp, xx */ | |
362 | /* add 8 bit sign-extended offset */ | |
363 | { | |
9ffbf372 | 364 | int stack_adjust = (signed char) (insn & 0xff); |
d95a8903 AC |
365 | |
366 | /* there are probably two of these stack adjustments: | |
367 | 1) A negative one in the prologue, and | |
368 | 2) A positive one in the epilogue. | |
369 | We are only interested in the first one. */ | |
370 | ||
371 | if (stack_adjust < 0) | |
372 | { | |
373 | framesize -= stack_adjust; | |
374 | after_prologue = 0; | |
375 | /* A frameless function may have no "mv fp, sp". | |
376 | In that case, this is the end of the prologue. */ | |
377 | after_stack_adjust = current_pc + 2; | |
378 | } | |
379 | continue; | |
380 | } | |
381 | if (insn == 0x1d8f) | |
382 | { /* mv fp, sp */ | |
383 | after_prologue = current_pc + 2; | |
384 | break; /* end of stack adjustments */ | |
385 | } | |
cea15572 | 386 | |
d95a8903 AC |
387 | /* Nop looks like a branch, continue explicitly */ |
388 | if (insn == 0x7000) | |
389 | { | |
390 | after_prologue = current_pc + 2; | |
391 | continue; /* nop occurs between pushes */ | |
392 | } | |
cea15572 KI |
393 | /* End of prolog if any of these are trap instructions */ |
394 | if ((insn & 0xfff0) == 0x10f0) | |
395 | { | |
396 | after_prologue = current_pc; | |
397 | break; | |
398 | } | |
d95a8903 AC |
399 | /* End of prolog if any of these are branch instructions */ |
400 | if ((op1 == 0x7000) || (op1 == 0xb000) || (op1 == 0xf000)) | |
401 | { | |
402 | after_prologue = current_pc; | |
d95a8903 AC |
403 | continue; |
404 | } | |
405 | /* Some of the branch instructions are mixed with other types */ | |
406 | if (op1 == 0x1000) | |
407 | { | |
408 | int subop = insn & 0x0ff0; | |
409 | if ((subop == 0x0ec0) || (subop == 0x0fc0)) | |
410 | { | |
411 | after_prologue = current_pc; | |
d95a8903 AC |
412 | continue; /* jmp , jl */ |
413 | } | |
414 | } | |
415 | } | |
416 | ||
cea15572 KI |
417 | if (framelength) |
418 | *framelength = framesize; | |
419 | ||
d95a8903 AC |
420 | if (current_pc >= scan_limit) |
421 | { | |
422 | if (pl_endptr) | |
423 | { | |
424 | if (after_stack_adjust != 0) | |
425 | /* We did not find a "mv fp,sp", but we DID find | |
426 | a stack_adjust. Is it safe to use that as the | |
427 | end of the prologue? I just don't know. */ | |
428 | { | |
429 | *pl_endptr = after_stack_adjust; | |
430 | } | |
cea15572 KI |
431 | else if (after_push != 0) |
432 | /* We did not find a "mv fp,sp", but we DID find | |
433 | a push. Is it safe to use that as the | |
434 | end of the prologue? I just don't know. */ | |
435 | { | |
436 | *pl_endptr = after_push; | |
437 | } | |
d95a8903 AC |
438 | else |
439 | /* We reached the end of the loop without finding the end | |
440 | of the prologue. No way to win -- we should report failure. | |
441 | The way we do that is to return the original start_pc. | |
442 | GDB will set a breakpoint at the start of the function (etc.) */ | |
443 | *pl_endptr = start_pc; | |
444 | } | |
cea15572 | 445 | return 0; |
d95a8903 | 446 | } |
cea15572 | 447 | |
d95a8903 AC |
448 | if (after_prologue == 0) |
449 | after_prologue = current_pc; | |
450 | ||
451 | if (pl_endptr) | |
452 | *pl_endptr = after_prologue; | |
cea15572 KI |
453 | |
454 | return 0; | |
d95a8903 AC |
455 | } /* decode_prologue */ |
456 | ||
457 | /* Function: skip_prologue | |
458 | Find end of function prologue */ | |
459 | ||
cea15572 | 460 | #define DEFAULT_SEARCH_LIMIT 128 |
d95a8903 | 461 | |
63807e1d | 462 | static CORE_ADDR |
6093d2eb | 463 | m32r_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
d95a8903 | 464 | { |
e17a4113 | 465 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d95a8903 AC |
466 | CORE_ADDR func_addr, func_end; |
467 | struct symtab_and_line sal; | |
cea15572 | 468 | LONGEST return_value; |
d95a8903 AC |
469 | |
470 | /* See what the symbol table says */ | |
471 | ||
472 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
473 | { | |
474 | sal = find_pc_line (func_addr, 0); | |
475 | ||
476 | if (sal.line != 0 && sal.end <= func_end) | |
477 | { | |
478 | func_end = sal.end; | |
479 | } | |
480 | else | |
481 | /* Either there's no line info, or the line after the prologue is after | |
482 | the end of the function. In this case, there probably isn't a | |
483 | prologue. */ | |
484 | { | |
485 | func_end = min (func_end, func_addr + DEFAULT_SEARCH_LIMIT); | |
486 | } | |
487 | } | |
488 | else | |
489 | func_end = pc + DEFAULT_SEARCH_LIMIT; | |
cea15572 KI |
490 | |
491 | /* If pc's location is not readable, just quit. */ | |
e17a4113 | 492 | if (!safe_read_memory_integer (pc, 4, byte_order, &return_value)) |
cea15572 KI |
493 | return pc; |
494 | ||
495 | /* Find the end of prologue. */ | |
e17a4113 | 496 | if (decode_prologue (gdbarch, pc, func_end, &sal.end, NULL) < 0) |
cea15572 KI |
497 | return pc; |
498 | ||
d95a8903 AC |
499 | return sal.end; |
500 | } | |
501 | ||
d95a8903 AC |
502 | struct m32r_unwind_cache |
503 | { | |
504 | /* The previous frame's inner most stack address. Used as this | |
505 | frame ID's stack_addr. */ | |
506 | CORE_ADDR prev_sp; | |
507 | /* The frame's base, optionally used by the high-level debug info. */ | |
508 | CORE_ADDR base; | |
509 | int size; | |
510 | /* How far the SP and r13 (FP) have been offset from the start of | |
511 | the stack frame (as defined by the previous frame's stack | |
512 | pointer). */ | |
513 | LONGEST sp_offset; | |
514 | LONGEST r13_offset; | |
515 | int uses_frame; | |
516 | /* Table indicating the location of each and every register. */ | |
517 | struct trad_frame_saved_reg *saved_regs; | |
518 | }; | |
519 | ||
520 | /* Put here the code to store, into fi->saved_regs, the addresses of | |
521 | the saved registers of frame described by FRAME_INFO. This | |
522 | includes special registers such as pc and fp saved in special ways | |
523 | in the stack frame. sp is even more special: the address we return | |
524 | for it IS the sp for the next frame. */ | |
525 | ||
526 | static struct m32r_unwind_cache * | |
94afd7a6 | 527 | m32r_frame_unwind_cache (struct frame_info *this_frame, |
d95a8903 AC |
528 | void **this_prologue_cache) |
529 | { | |
cea15572 | 530 | CORE_ADDR pc, scan_limit; |
d95a8903 AC |
531 | ULONGEST prev_sp; |
532 | ULONGEST this_base; | |
cea15572 | 533 | unsigned long op, op2; |
d95a8903 AC |
534 | int i; |
535 | struct m32r_unwind_cache *info; | |
536 | ||
cea15572 | 537 | |
d95a8903 AC |
538 | if ((*this_prologue_cache)) |
539 | return (*this_prologue_cache); | |
540 | ||
541 | info = FRAME_OBSTACK_ZALLOC (struct m32r_unwind_cache); | |
542 | (*this_prologue_cache) = info; | |
94afd7a6 | 543 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
d95a8903 AC |
544 | |
545 | info->size = 0; | |
546 | info->sp_offset = 0; | |
d95a8903 | 547 | info->uses_frame = 0; |
cea15572 | 548 | |
94afd7a6 UW |
549 | scan_limit = get_frame_pc (this_frame); |
550 | for (pc = get_frame_func (this_frame); | |
cea15572 | 551 | pc > 0 && pc < scan_limit; pc += 2) |
d95a8903 AC |
552 | { |
553 | if ((pc & 2) == 0) | |
554 | { | |
94afd7a6 | 555 | op = get_frame_memory_unsigned (this_frame, pc, 4); |
d95a8903 AC |
556 | if ((op & 0x80000000) == 0x80000000) |
557 | { | |
558 | /* 32-bit instruction */ | |
559 | if ((op & 0xffff0000) == 0x8faf0000) | |
560 | { | |
561 | /* add3 sp,sp,xxxx */ | |
562 | short n = op & 0xffff; | |
563 | info->sp_offset += n; | |
564 | } | |
cea15572 | 565 | else if (((op >> 8) == 0xe4) |
94afd7a6 | 566 | && get_frame_memory_unsigned (this_frame, pc + 2, |
7e3dd49e | 567 | 2) == 0x0f24) |
d95a8903 | 568 | { |
cea15572 | 569 | /* ld24 r4, xxxxxx; sub sp, r4 */ |
d95a8903 AC |
570 | unsigned long n = op & 0xffffff; |
571 | info->sp_offset += n; | |
cea15572 | 572 | pc += 2; /* skip sub instruction */ |
d95a8903 | 573 | } |
d95a8903 | 574 | |
cea15572 KI |
575 | if (pc == scan_limit) |
576 | scan_limit += 2; /* extend the search */ | |
577 | pc += 2; /* skip the immediate data */ | |
d95a8903 AC |
578 | continue; |
579 | } | |
580 | } | |
581 | ||
582 | /* 16-bit instructions */ | |
94afd7a6 | 583 | op = get_frame_memory_unsigned (this_frame, pc, 2) & 0x7fff; |
d95a8903 AC |
584 | if ((op & 0xf0ff) == 0x207f) |
585 | { | |
586 | /* st rn, @-sp */ | |
587 | int regno = ((op >> 8) & 0xf); | |
588 | info->sp_offset -= 4; | |
589 | info->saved_regs[regno].addr = info->sp_offset; | |
590 | } | |
591 | else if ((op & 0xff00) == 0x4f00) | |
592 | { | |
593 | /* addi sp, xx */ | |
9ffbf372 | 594 | int n = (signed char) (op & 0xff); |
d95a8903 AC |
595 | info->sp_offset += n; |
596 | } | |
597 | else if (op == 0x1d8f) | |
598 | { | |
599 | /* mv fp, sp */ | |
600 | info->uses_frame = 1; | |
601 | info->r13_offset = info->sp_offset; | |
cea15572 KI |
602 | break; /* end of stack adjustments */ |
603 | } | |
604 | else if ((op & 0xfff0) == 0x10f0) | |
605 | { | |
606 | /* end of prologue if this is a trap instruction */ | |
607 | break; /* end of stack adjustments */ | |
d95a8903 | 608 | } |
d95a8903 AC |
609 | } |
610 | ||
611 | info->size = -info->sp_offset; | |
612 | ||
613 | /* Compute the previous frame's stack pointer (which is also the | |
614 | frame's ID's stack address), and this frame's base pointer. */ | |
615 | if (info->uses_frame) | |
616 | { | |
617 | /* The SP was moved to the FP. This indicates that a new frame | |
618 | was created. Get THIS frame's FP value by unwinding it from | |
619 | the next frame. */ | |
94afd7a6 | 620 | this_base = get_frame_register_unsigned (this_frame, M32R_FP_REGNUM); |
d95a8903 AC |
621 | /* The FP points at the last saved register. Adjust the FP back |
622 | to before the first saved register giving the SP. */ | |
623 | prev_sp = this_base + info->size; | |
624 | } | |
625 | else | |
626 | { | |
627 | /* Assume that the FP is this frame's SP but with that pushed | |
628 | stack space added back. */ | |
94afd7a6 | 629 | this_base = get_frame_register_unsigned (this_frame, M32R_SP_REGNUM); |
d95a8903 AC |
630 | prev_sp = this_base + info->size; |
631 | } | |
632 | ||
633 | /* Convert that SP/BASE into real addresses. */ | |
634 | info->prev_sp = prev_sp; | |
635 | info->base = this_base; | |
636 | ||
637 | /* Adjust all the saved registers so that they contain addresses and | |
638 | not offsets. */ | |
94afd7a6 | 639 | for (i = 0; i < gdbarch_num_regs (get_frame_arch (this_frame)) - 1; i++) |
d95a8903 AC |
640 | if (trad_frame_addr_p (info->saved_regs, i)) |
641 | info->saved_regs[i].addr = (info->prev_sp + info->saved_regs[i].addr); | |
642 | ||
643 | /* The call instruction moves the caller's PC in the callee's LR. | |
644 | Since this is an unwind, do the reverse. Copy the location of LR | |
645 | into PC (the address / regnum) so that a request for PC will be | |
646 | converted into a request for the LR. */ | |
647 | info->saved_regs[M32R_PC_REGNUM] = info->saved_regs[LR_REGNUM]; | |
648 | ||
649 | /* The previous frame's SP needed to be computed. Save the computed | |
650 | value. */ | |
651 | trad_frame_set_value (info->saved_regs, M32R_SP_REGNUM, prev_sp); | |
652 | ||
653 | return info; | |
654 | } | |
655 | ||
656 | static CORE_ADDR | |
61a1198a | 657 | m32r_read_pc (struct regcache *regcache) |
d95a8903 | 658 | { |
7e3dd49e | 659 | ULONGEST pc; |
61a1198a | 660 | regcache_cooked_read_unsigned (regcache, M32R_PC_REGNUM, &pc); |
d95a8903 AC |
661 | return pc; |
662 | } | |
663 | ||
664 | static void | |
61a1198a | 665 | m32r_write_pc (struct regcache *regcache, CORE_ADDR val) |
d95a8903 | 666 | { |
61a1198a | 667 | regcache_cooked_write_unsigned (regcache, M32R_PC_REGNUM, val); |
d95a8903 AC |
668 | } |
669 | ||
670 | static CORE_ADDR | |
671 | m32r_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
672 | { | |
7e3dd49e | 673 | return frame_unwind_register_unsigned (next_frame, M32R_SP_REGNUM); |
d95a8903 AC |
674 | } |
675 | ||
676 | ||
677 | static CORE_ADDR | |
7d9b040b | 678 | m32r_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
d95a8903 AC |
679 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
680 | struct value **args, CORE_ADDR sp, int struct_return, | |
681 | CORE_ADDR struct_addr) | |
682 | { | |
e17a4113 | 683 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d95a8903 AC |
684 | int stack_offset, stack_alloc; |
685 | int argreg = ARG1_REGNUM; | |
686 | int argnum; | |
687 | struct type *type; | |
688 | enum type_code typecode; | |
689 | CORE_ADDR regval; | |
16ac4ab5 KI |
690 | gdb_byte *val; |
691 | gdb_byte valbuf[MAX_REGISTER_SIZE]; | |
d95a8903 AC |
692 | int len; |
693 | int odd_sized_struct; | |
694 | ||
695 | /* first force sp to a 4-byte alignment */ | |
696 | sp = sp & ~3; | |
697 | ||
698 | /* Set the return address. For the m32r, the return breakpoint is | |
699 | always at BP_ADDR. */ | |
700 | regcache_cooked_write_unsigned (regcache, LR_REGNUM, bp_addr); | |
701 | ||
702 | /* If STRUCT_RETURN is true, then the struct return address (in | |
703 | STRUCT_ADDR) will consume the first argument-passing register. | |
704 | Both adjust the register count and store that value. */ | |
705 | if (struct_return) | |
706 | { | |
707 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); | |
708 | argreg++; | |
709 | } | |
710 | ||
711 | /* Now make sure there's space on the stack */ | |
712 | for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++) | |
4991999e | 713 | stack_alloc += ((TYPE_LENGTH (value_type (args[argnum])) + 3) & ~3); |
d95a8903 AC |
714 | sp -= stack_alloc; /* make room on stack for args */ |
715 | ||
716 | for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++) | |
717 | { | |
4991999e | 718 | type = value_type (args[argnum]); |
d95a8903 AC |
719 | typecode = TYPE_CODE (type); |
720 | len = TYPE_LENGTH (type); | |
721 | ||
722 | memset (valbuf, 0, sizeof (valbuf)); | |
723 | ||
724 | /* Passes structures that do not fit in 2 registers by reference. */ | |
725 | if (len > 8 | |
726 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) | |
727 | { | |
e17a4113 UW |
728 | store_unsigned_integer (valbuf, 4, byte_order, |
729 | value_address (args[argnum])); | |
d95a8903 AC |
730 | typecode = TYPE_CODE_PTR; |
731 | len = 4; | |
732 | val = valbuf; | |
733 | } | |
734 | else if (len < 4) | |
735 | { | |
736 | /* value gets right-justified in the register or stack word */ | |
7e3dd49e | 737 | memcpy (valbuf + (register_size (gdbarch, argreg) - len), |
16ac4ab5 | 738 | (gdb_byte *) value_contents (args[argnum]), len); |
d95a8903 AC |
739 | val = valbuf; |
740 | } | |
741 | else | |
16ac4ab5 | 742 | val = (gdb_byte *) value_contents (args[argnum]); |
d95a8903 AC |
743 | |
744 | while (len > 0) | |
745 | { | |
746 | if (argreg > ARGN_REGNUM) | |
747 | { | |
748 | /* must go on the stack */ | |
749 | write_memory (sp + stack_offset, val, 4); | |
750 | stack_offset += 4; | |
751 | } | |
752 | else if (argreg <= ARGN_REGNUM) | |
753 | { | |
754 | /* there's room in a register */ | |
755 | regval = | |
7e3dd49e | 756 | extract_unsigned_integer (val, |
e17a4113 UW |
757 | register_size (gdbarch, argreg), |
758 | byte_order); | |
d95a8903 AC |
759 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
760 | } | |
761 | ||
762 | /* Store the value 4 bytes at a time. This means that things | |
763 | larger than 4 bytes may go partly in registers and partly | |
764 | on the stack. */ | |
7e3dd49e AC |
765 | len -= register_size (gdbarch, argreg); |
766 | val += register_size (gdbarch, argreg); | |
d95a8903 AC |
767 | } |
768 | } | |
769 | ||
770 | /* Finally, update the SP register. */ | |
771 | regcache_cooked_write_unsigned (regcache, M32R_SP_REGNUM, sp); | |
772 | ||
773 | return sp; | |
774 | } | |
775 | ||
776 | ||
777 | /* Given a return value in `regbuf' with a type `valtype', | |
778 | extract and copy its value into `valbuf'. */ | |
779 | ||
780 | static void | |
781 | m32r_extract_return_value (struct type *type, struct regcache *regcache, | |
782 | void *dst) | |
783 | { | |
e17a4113 UW |
784 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
785 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
d95a8903 AC |
786 | bfd_byte *valbuf = dst; |
787 | int len = TYPE_LENGTH (type); | |
788 | ULONGEST tmp; | |
789 | ||
790 | /* By using store_unsigned_integer we avoid having to do | |
791 | anything special for small big-endian values. */ | |
792 | regcache_cooked_read_unsigned (regcache, RET1_REGNUM, &tmp); | |
e17a4113 | 793 | store_unsigned_integer (valbuf, (len > 4 ? len - 4 : len), byte_order, tmp); |
d95a8903 AC |
794 | |
795 | /* Ignore return values more than 8 bytes in size because the m32r | |
796 | returns anything more than 8 bytes in the stack. */ | |
797 | if (len > 4) | |
798 | { | |
799 | regcache_cooked_read_unsigned (regcache, RET1_REGNUM + 1, &tmp); | |
e17a4113 | 800 | store_unsigned_integer (valbuf + len - 4, 4, byte_order, tmp); |
d95a8903 AC |
801 | } |
802 | } | |
803 | ||
63807e1d | 804 | static enum return_value_convention |
c055b101 CV |
805 | m32r_return_value (struct gdbarch *gdbarch, struct type *func_type, |
806 | struct type *valtype, struct regcache *regcache, | |
807 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
14588880 KI |
808 | { |
809 | if (TYPE_LENGTH (valtype) > 8) | |
810 | return RETURN_VALUE_STRUCT_CONVENTION; | |
811 | else | |
812 | { | |
813 | if (readbuf != NULL) | |
814 | m32r_extract_return_value (valtype, regcache, readbuf); | |
815 | if (writebuf != NULL) | |
816 | m32r_store_return_value (valtype, regcache, writebuf); | |
817 | return RETURN_VALUE_REGISTER_CONVENTION; | |
818 | } | |
819 | } | |
820 | ||
821 | ||
d95a8903 AC |
822 | |
823 | static CORE_ADDR | |
824 | m32r_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
825 | { | |
7e3dd49e | 826 | return frame_unwind_register_unsigned (next_frame, M32R_PC_REGNUM); |
d95a8903 AC |
827 | } |
828 | ||
829 | /* Given a GDB frame, determine the address of the calling function's | |
830 | frame. This will be used to create a new GDB frame struct. */ | |
831 | ||
832 | static void | |
94afd7a6 | 833 | m32r_frame_this_id (struct frame_info *this_frame, |
d95a8903 AC |
834 | void **this_prologue_cache, struct frame_id *this_id) |
835 | { | |
836 | struct m32r_unwind_cache *info | |
94afd7a6 | 837 | = m32r_frame_unwind_cache (this_frame, this_prologue_cache); |
d95a8903 AC |
838 | CORE_ADDR base; |
839 | CORE_ADDR func; | |
840 | struct minimal_symbol *msym_stack; | |
841 | struct frame_id id; | |
842 | ||
843 | /* The FUNC is easy. */ | |
94afd7a6 | 844 | func = get_frame_func (this_frame); |
d95a8903 | 845 | |
d95a8903 AC |
846 | /* Check if the stack is empty. */ |
847 | msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL); | |
848 | if (msym_stack && info->base == SYMBOL_VALUE_ADDRESS (msym_stack)) | |
849 | return; | |
850 | ||
851 | /* Hopefully the prologue analysis either correctly determined the | |
852 | frame's base (which is the SP from the previous frame), or set | |
853 | that base to "NULL". */ | |
854 | base = info->prev_sp; | |
855 | if (base == 0) | |
856 | return; | |
857 | ||
858 | id = frame_id_build (base, func); | |
d95a8903 AC |
859 | (*this_id) = id; |
860 | } | |
861 | ||
94afd7a6 UW |
862 | static struct value * |
863 | m32r_frame_prev_register (struct frame_info *this_frame, | |
864 | void **this_prologue_cache, int regnum) | |
d95a8903 AC |
865 | { |
866 | struct m32r_unwind_cache *info | |
94afd7a6 UW |
867 | = m32r_frame_unwind_cache (this_frame, this_prologue_cache); |
868 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); | |
d95a8903 AC |
869 | } |
870 | ||
871 | static const struct frame_unwind m32r_frame_unwind = { | |
872 | NORMAL_FRAME, | |
873 | m32r_frame_this_id, | |
94afd7a6 UW |
874 | m32r_frame_prev_register, |
875 | NULL, | |
876 | default_frame_sniffer | |
d95a8903 AC |
877 | }; |
878 | ||
d95a8903 | 879 | static CORE_ADDR |
94afd7a6 | 880 | m32r_frame_base_address (struct frame_info *this_frame, void **this_cache) |
d95a8903 AC |
881 | { |
882 | struct m32r_unwind_cache *info | |
94afd7a6 | 883 | = m32r_frame_unwind_cache (this_frame, this_cache); |
d95a8903 AC |
884 | return info->base; |
885 | } | |
886 | ||
887 | static const struct frame_base m32r_frame_base = { | |
888 | &m32r_frame_unwind, | |
889 | m32r_frame_base_address, | |
890 | m32r_frame_base_address, | |
891 | m32r_frame_base_address | |
892 | }; | |
893 | ||
94afd7a6 UW |
894 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy |
895 | frame. The frame ID's base needs to match the TOS value saved by | |
896 | save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */ | |
d95a8903 AC |
897 | |
898 | static struct frame_id | |
94afd7a6 | 899 | m32r_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
d95a8903 | 900 | { |
94afd7a6 UW |
901 | CORE_ADDR sp = get_frame_register_unsigned (this_frame, M32R_SP_REGNUM); |
902 | return frame_id_build (sp, get_frame_pc (this_frame)); | |
d95a8903 AC |
903 | } |
904 | ||
905 | ||
906 | static gdbarch_init_ftype m32r_gdbarch_init; | |
907 | ||
908 | static struct gdbarch * | |
909 | m32r_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
910 | { | |
911 | struct gdbarch *gdbarch; | |
912 | struct gdbarch_tdep *tdep; | |
913 | ||
914 | /* If there is already a candidate, use it. */ | |
915 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
916 | if (arches != NULL) | |
917 | return arches->gdbarch; | |
918 | ||
919 | /* Allocate space for the new architecture. */ | |
920 | tdep = XMALLOC (struct gdbarch_tdep); | |
921 | gdbarch = gdbarch_alloc (&info, tdep); | |
922 | ||
923 | set_gdbarch_read_pc (gdbarch, m32r_read_pc); | |
924 | set_gdbarch_write_pc (gdbarch, m32r_write_pc); | |
925 | set_gdbarch_unwind_sp (gdbarch, m32r_unwind_sp); | |
926 | ||
9b32d526 | 927 | set_gdbarch_num_regs (gdbarch, M32R_NUM_REGS); |
d95a8903 AC |
928 | set_gdbarch_sp_regnum (gdbarch, M32R_SP_REGNUM); |
929 | set_gdbarch_register_name (gdbarch, m32r_register_name); | |
930 | set_gdbarch_register_type (gdbarch, m32r_register_type); | |
931 | ||
d95a8903 | 932 | set_gdbarch_push_dummy_call (gdbarch, m32r_push_dummy_call); |
14588880 | 933 | set_gdbarch_return_value (gdbarch, m32r_return_value); |
d95a8903 AC |
934 | |
935 | set_gdbarch_skip_prologue (gdbarch, m32r_skip_prologue); | |
936 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
d95a8903 AC |
937 | set_gdbarch_breakpoint_from_pc (gdbarch, m32r_breakpoint_from_pc); |
938 | set_gdbarch_memory_insert_breakpoint (gdbarch, | |
939 | m32r_memory_insert_breakpoint); | |
940 | set_gdbarch_memory_remove_breakpoint (gdbarch, | |
941 | m32r_memory_remove_breakpoint); | |
942 | ||
d95a8903 AC |
943 | set_gdbarch_frame_align (gdbarch, m32r_frame_align); |
944 | ||
d95a8903 AC |
945 | frame_base_set_default (gdbarch, &m32r_frame_base); |
946 | ||
947 | /* Methods for saving / extracting a dummy frame's ID. The ID's | |
948 | stack address must match the SP value returned by | |
949 | PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */ | |
94afd7a6 | 950 | set_gdbarch_dummy_id (gdbarch, m32r_dummy_id); |
d95a8903 AC |
951 | |
952 | /* Return the unwound PC value. */ | |
953 | set_gdbarch_unwind_pc (gdbarch, m32r_unwind_pc); | |
954 | ||
955 | set_gdbarch_print_insn (gdbarch, print_insn_m32r); | |
956 | ||
c46b0409 KI |
957 | /* Hook in ABI-specific overrides, if they have been registered. */ |
958 | gdbarch_init_osabi (info, gdbarch); | |
959 | ||
960 | /* Hook in the default unwinders. */ | |
94afd7a6 | 961 | frame_unwind_append_unwinder (gdbarch, &m32r_frame_unwind); |
c46b0409 | 962 | |
1c772458 UW |
963 | /* Support simple overlay manager. */ |
964 | set_gdbarch_overlay_update (gdbarch, simple_overlay_update); | |
965 | ||
d95a8903 AC |
966 | return gdbarch; |
967 | } | |
968 | ||
969 | void | |
970 | _initialize_m32r_tdep (void) | |
971 | { | |
972 | register_gdbarch_init (bfd_arch_m32r, m32r_gdbarch_init); | |
973 | } |