Commit | Line | Data |
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d95a8903 AC |
1 | /* Target-dependent code for Renesas M32R, for GDB. |
2 | ||
618f726f | 3 | Copyright (C) 1996-2016 Free Software Foundation, Inc. |
d95a8903 AC |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
d95a8903 AC |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
d95a8903 AC |
19 | |
20 | #include "defs.h" | |
21 | #include "frame.h" | |
22 | #include "frame-unwind.h" | |
23 | #include "frame-base.h" | |
24 | #include "symtab.h" | |
25 | #include "gdbtypes.h" | |
26 | #include "gdbcmd.h" | |
27 | #include "gdbcore.h" | |
d95a8903 AC |
28 | #include "value.h" |
29 | #include "inferior.h" | |
30 | #include "symfile.h" | |
31 | #include "objfiles.h" | |
c46b0409 | 32 | #include "osabi.h" |
d95a8903 AC |
33 | #include "language.h" |
34 | #include "arch-utils.h" | |
35 | #include "regcache.h" | |
36 | #include "trad-frame.h" | |
73e8eb51 | 37 | #include "dis-asm.h" |
77e371c0 | 38 | #include "objfiles.h" |
d95a8903 | 39 | |
9b32d526 | 40 | #include "m32r-tdep.h" |
d95a8903 AC |
41 | |
42 | /* Local functions */ | |
43 | ||
44 | extern void _initialize_m32r_tdep (void); | |
45 | ||
46 | static CORE_ADDR | |
47 | m32r_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
48 | { | |
49 | /* Align to the size of an instruction (so that they can safely be | |
50 | pushed onto the stack. */ | |
51 | return sp & ~3; | |
52 | } | |
53 | ||
d95a8903 | 54 | |
9f0b0322 KI |
55 | /* Breakpoints |
56 | ||
025bb325 | 57 | The little endian mode of M32R is unique. In most of architectures, |
9f0b0322 KI |
58 | two 16-bit instructions, A and B, are placed as the following: |
59 | ||
60 | Big endian: | |
61 | A0 A1 B0 B1 | |
62 | ||
63 | Little endian: | |
64 | A1 A0 B1 B0 | |
65 | ||
66 | In M32R, they are placed like this: | |
67 | ||
68 | Big endian: | |
69 | A0 A1 B0 B1 | |
70 | ||
71 | Little endian: | |
72 | B1 B0 A1 A0 | |
73 | ||
74 | This is because M32R always fetches instructions in 32-bit. | |
75 | ||
025bb325 | 76 | The following functions take care of this behavior. */ |
d95a8903 AC |
77 | |
78 | static int | |
ae4b2284 MD |
79 | m32r_memory_insert_breakpoint (struct gdbarch *gdbarch, |
80 | struct bp_target_info *bp_tgt) | |
d95a8903 | 81 | { |
0d5ed153 | 82 | CORE_ADDR addr = bp_tgt->placed_address = bp_tgt->reqstd_address; |
d95a8903 | 83 | int val; |
16ac4ab5 | 84 | gdb_byte buf[4]; |
35c63cd8 | 85 | gdb_byte contents_cache[4]; |
16ac4ab5 | 86 | gdb_byte bp_entry[] = { 0x10, 0xf1 }; /* dpt */ |
d95a8903 AC |
87 | |
88 | /* Save the memory contents. */ | |
9f0b0322 | 89 | val = target_read_memory (addr & 0xfffffffc, contents_cache, 4); |
d95a8903 AC |
90 | if (val != 0) |
91 | return val; /* return error */ | |
92 | ||
35c63cd8 | 93 | memcpy (bp_tgt->shadow_contents, contents_cache, 4); |
8181d85f DJ |
94 | bp_tgt->placed_size = bp_tgt->shadow_len = 4; |
95 | ||
d95a8903 | 96 | /* Determine appropriate breakpoint contents and size for this address. */ |
ae4b2284 | 97 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
d95a8903 | 98 | { |
9f0b0322 | 99 | if ((addr & 3) == 0) |
d95a8903 | 100 | { |
9f0b0322 KI |
101 | buf[0] = bp_entry[0]; |
102 | buf[1] = bp_entry[1]; | |
103 | buf[2] = contents_cache[2] & 0x7f; | |
104 | buf[3] = contents_cache[3]; | |
d95a8903 AC |
105 | } |
106 | else | |
107 | { | |
9f0b0322 KI |
108 | buf[0] = contents_cache[0]; |
109 | buf[1] = contents_cache[1]; | |
110 | buf[2] = bp_entry[0]; | |
111 | buf[3] = bp_entry[1]; | |
d95a8903 AC |
112 | } |
113 | } | |
9f0b0322 KI |
114 | else /* little-endian */ |
115 | { | |
116 | if ((addr & 3) == 0) | |
d95a8903 | 117 | { |
9f0b0322 KI |
118 | buf[0] = contents_cache[0]; |
119 | buf[1] = contents_cache[1] & 0x7f; | |
120 | buf[2] = bp_entry[1]; | |
121 | buf[3] = bp_entry[0]; | |
d95a8903 AC |
122 | } |
123 | else | |
124 | { | |
9f0b0322 KI |
125 | buf[0] = bp_entry[1]; |
126 | buf[1] = bp_entry[0]; | |
127 | buf[2] = contents_cache[2]; | |
128 | buf[3] = contents_cache[3]; | |
d95a8903 AC |
129 | } |
130 | } | |
131 | ||
132 | /* Write the breakpoint. */ | |
9f0b0322 | 133 | val = target_write_memory (addr & 0xfffffffc, buf, 4); |
d95a8903 AC |
134 | return val; |
135 | } | |
136 | ||
137 | static int | |
ae4b2284 MD |
138 | m32r_memory_remove_breakpoint (struct gdbarch *gdbarch, |
139 | struct bp_target_info *bp_tgt) | |
d95a8903 | 140 | { |
8181d85f | 141 | CORE_ADDR addr = bp_tgt->placed_address; |
d95a8903 | 142 | int val; |
16ac4ab5 | 143 | gdb_byte buf[4]; |
8181d85f | 144 | gdb_byte *contents_cache = bp_tgt->shadow_contents; |
d95a8903 | 145 | |
9f0b0322 KI |
146 | buf[0] = contents_cache[0]; |
147 | buf[1] = contents_cache[1]; | |
148 | buf[2] = contents_cache[2]; | |
149 | buf[3] = contents_cache[3]; | |
150 | ||
151 | /* Remove parallel bit. */ | |
ae4b2284 | 152 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
d95a8903 | 153 | { |
9f0b0322 KI |
154 | if ((buf[0] & 0x80) == 0 && (buf[2] & 0x80) != 0) |
155 | buf[2] &= 0x7f; | |
d95a8903 | 156 | } |
9f0b0322 | 157 | else /* little-endian */ |
d95a8903 | 158 | { |
9f0b0322 KI |
159 | if ((buf[3] & 0x80) == 0 && (buf[1] & 0x80) != 0) |
160 | buf[1] &= 0x7f; | |
d95a8903 AC |
161 | } |
162 | ||
163 | /* Write contents. */ | |
dd110abf | 164 | val = target_write_raw_memory (addr & 0xfffffffc, buf, 4); |
d95a8903 AC |
165 | return val; |
166 | } | |
167 | ||
16ac4ab5 | 168 | static const gdb_byte * |
025bb325 MS |
169 | m32r_breakpoint_from_pc (struct gdbarch *gdbarch, |
170 | CORE_ADDR *pcptr, int *lenptr) | |
d95a8903 | 171 | { |
025bb325 MS |
172 | static gdb_byte be_bp_entry[] = { |
173 | 0x10, 0xf1, 0x70, 0x00 | |
174 | }; /* dpt -> nop */ | |
175 | static gdb_byte le_bp_entry[] = { | |
176 | 0x00, 0x70, 0xf1, 0x10 | |
177 | }; /* dpt -> nop */ | |
16ac4ab5 | 178 | gdb_byte *bp; |
d95a8903 AC |
179 | |
180 | /* Determine appropriate breakpoint. */ | |
67d57894 | 181 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
d95a8903 AC |
182 | { |
183 | if ((*pcptr & 3) == 0) | |
184 | { | |
9f0b0322 KI |
185 | bp = be_bp_entry; |
186 | *lenptr = 4; | |
d95a8903 AC |
187 | } |
188 | else | |
189 | { | |
9f0b0322 KI |
190 | bp = be_bp_entry; |
191 | *lenptr = 2; | |
d95a8903 AC |
192 | } |
193 | } | |
194 | else | |
195 | { | |
196 | if ((*pcptr & 3) == 0) | |
197 | { | |
9f0b0322 KI |
198 | bp = le_bp_entry; |
199 | *lenptr = 4; | |
d95a8903 AC |
200 | } |
201 | else | |
202 | { | |
9f0b0322 KI |
203 | bp = le_bp_entry + 2; |
204 | *lenptr = 2; | |
d95a8903 AC |
205 | } |
206 | } | |
207 | ||
208 | return bp; | |
209 | } | |
210 | ||
211 | ||
212 | char *m32r_register_names[] = { | |
213 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
214 | "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp", | |
215 | "psw", "cbr", "spi", "spu", "bpc", "pc", "accl", "acch", | |
216 | "evb" | |
217 | }; | |
218 | ||
d95a8903 | 219 | static const char * |
d93859e2 | 220 | m32r_register_name (struct gdbarch *gdbarch, int reg_nr) |
d95a8903 AC |
221 | { |
222 | if (reg_nr < 0) | |
223 | return NULL; | |
9b32d526 | 224 | if (reg_nr >= M32R_NUM_REGS) |
d95a8903 AC |
225 | return NULL; |
226 | return m32r_register_names[reg_nr]; | |
227 | } | |
228 | ||
229 | ||
230 | /* Return the GDB type object for the "standard" data type | |
231 | of data in register N. */ | |
232 | ||
233 | static struct type * | |
234 | m32r_register_type (struct gdbarch *gdbarch, int reg_nr) | |
235 | { | |
236 | if (reg_nr == M32R_PC_REGNUM) | |
0dfff4cb | 237 | return builtin_type (gdbarch)->builtin_func_ptr; |
d95a8903 | 238 | else if (reg_nr == M32R_SP_REGNUM || reg_nr == M32R_FP_REGNUM) |
0dfff4cb | 239 | return builtin_type (gdbarch)->builtin_data_ptr; |
d95a8903 | 240 | else |
df4df182 | 241 | return builtin_type (gdbarch)->builtin_int32; |
d95a8903 AC |
242 | } |
243 | ||
244 | ||
245 | /* Write into appropriate registers a function return value | |
025bb325 | 246 | of type TYPE, given in virtual format. |
d95a8903 | 247 | |
025bb325 | 248 | Things always get returned in RET1_REGNUM, RET2_REGNUM. */ |
d95a8903 AC |
249 | |
250 | static void | |
251 | m32r_store_return_value (struct type *type, struct regcache *regcache, | |
7c543f7b | 252 | const gdb_byte *valbuf) |
d95a8903 | 253 | { |
e17a4113 UW |
254 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
255 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
d95a8903 AC |
256 | CORE_ADDR regval; |
257 | int len = TYPE_LENGTH (type); | |
258 | ||
e17a4113 | 259 | regval = extract_unsigned_integer (valbuf, len > 4 ? 4 : len, byte_order); |
d95a8903 AC |
260 | regcache_cooked_write_unsigned (regcache, RET1_REGNUM, regval); |
261 | ||
262 | if (len > 4) | |
263 | { | |
7c543f7b | 264 | regval = extract_unsigned_integer (valbuf + 4, |
e17a4113 | 265 | len - 4, byte_order); |
d95a8903 AC |
266 | regcache_cooked_write_unsigned (regcache, RET1_REGNUM + 1, regval); |
267 | } | |
268 | } | |
269 | ||
025bb325 | 270 | /* This is required by skip_prologue. The results of decoding a prologue |
d95a8903 AC |
271 | should be cached because this thrashing is getting nuts. */ |
272 | ||
cea15572 | 273 | static int |
e17a4113 UW |
274 | decode_prologue (struct gdbarch *gdbarch, |
275 | CORE_ADDR start_pc, CORE_ADDR scan_limit, | |
cea15572 | 276 | CORE_ADDR *pl_endptr, unsigned long *framelength) |
d95a8903 | 277 | { |
e17a4113 | 278 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d95a8903 AC |
279 | unsigned long framesize; |
280 | int insn; | |
281 | int op1; | |
d95a8903 | 282 | CORE_ADDR after_prologue = 0; |
cea15572 | 283 | CORE_ADDR after_push = 0; |
d95a8903 AC |
284 | CORE_ADDR after_stack_adjust = 0; |
285 | CORE_ADDR current_pc; | |
cea15572 | 286 | LONGEST return_value; |
d95a8903 AC |
287 | |
288 | framesize = 0; | |
289 | after_prologue = 0; | |
290 | ||
291 | for (current_pc = start_pc; current_pc < scan_limit; current_pc += 2) | |
292 | { | |
025bb325 | 293 | /* Check if current pc's location is readable. */ |
e17a4113 | 294 | if (!safe_read_memory_integer (current_pc, 2, byte_order, &return_value)) |
cea15572 KI |
295 | return -1; |
296 | ||
e17a4113 | 297 | insn = read_memory_unsigned_integer (current_pc, 2, byte_order); |
d95a8903 | 298 | |
cea15572 KI |
299 | if (insn == 0x0000) |
300 | break; | |
301 | ||
d95a8903 | 302 | /* If this is a 32 bit instruction, we dont want to examine its |
025bb325 | 303 | immediate data as though it were an instruction. */ |
d95a8903 AC |
304 | if (current_pc & 0x02) |
305 | { | |
025bb325 | 306 | /* Decode this instruction further. */ |
d95a8903 AC |
307 | insn &= 0x7fff; |
308 | } | |
309 | else | |
310 | { | |
d95a8903 AC |
311 | if (insn & 0x8000) |
312 | { | |
313 | if (current_pc == scan_limit) | |
314 | scan_limit += 2; /* extend the search */ | |
cea15572 | 315 | |
d95a8903 | 316 | current_pc += 2; /* skip the immediate data */ |
cea15572 | 317 | |
025bb325 | 318 | /* Check if current pc's location is readable. */ |
e17a4113 UW |
319 | if (!safe_read_memory_integer (current_pc, 2, byte_order, |
320 | &return_value)) | |
cea15572 KI |
321 | return -1; |
322 | ||
d95a8903 AC |
323 | if (insn == 0x8faf) /* add3 sp, sp, xxxx */ |
324 | /* add 16 bit sign-extended offset */ | |
325 | { | |
326 | framesize += | |
e17a4113 UW |
327 | -((short) read_memory_unsigned_integer (current_pc, |
328 | 2, byte_order)); | |
d95a8903 AC |
329 | } |
330 | else | |
331 | { | |
025bb325 | 332 | if (((insn >> 8) == 0xe4) /* ld24 r4, xxxxxx; sub sp, r4 */ |
e17a4113 UW |
333 | && safe_read_memory_integer (current_pc + 2, |
334 | 2, byte_order, | |
cea15572 | 335 | &return_value) |
7e3dd49e | 336 | && read_memory_unsigned_integer (current_pc + 2, |
e17a4113 UW |
337 | 2, byte_order) |
338 | == 0x0f24) | |
d95a8903 | 339 | { |
025bb325 | 340 | /* Subtract 24 bit sign-extended negative-offset. */ |
e17a4113 UW |
341 | insn = read_memory_unsigned_integer (current_pc - 2, |
342 | 4, byte_order); | |
d95a8903 AC |
343 | if (insn & 0x00800000) /* sign extend */ |
344 | insn |= 0xff000000; /* negative */ | |
345 | else | |
346 | insn &= 0x00ffffff; /* positive */ | |
347 | framesize += insn; | |
348 | } | |
349 | } | |
cea15572 | 350 | after_push = current_pc + 2; |
d95a8903 AC |
351 | continue; |
352 | } | |
353 | } | |
025bb325 | 354 | op1 = insn & 0xf000; /* Isolate just the first nibble. */ |
d95a8903 AC |
355 | |
356 | if ((insn & 0xf0ff) == 0x207f) | |
357 | { /* st reg, @-sp */ | |
d95a8903 | 358 | framesize += 4; |
d95a8903 AC |
359 | after_prologue = 0; |
360 | continue; | |
361 | } | |
362 | if ((insn >> 8) == 0x4f) /* addi sp, xx */ | |
025bb325 | 363 | /* Add 8 bit sign-extended offset. */ |
d95a8903 | 364 | { |
9ffbf372 | 365 | int stack_adjust = (signed char) (insn & 0xff); |
d95a8903 AC |
366 | |
367 | /* there are probably two of these stack adjustments: | |
368 | 1) A negative one in the prologue, and | |
369 | 2) A positive one in the epilogue. | |
370 | We are only interested in the first one. */ | |
371 | ||
372 | if (stack_adjust < 0) | |
373 | { | |
374 | framesize -= stack_adjust; | |
375 | after_prologue = 0; | |
376 | /* A frameless function may have no "mv fp, sp". | |
377 | In that case, this is the end of the prologue. */ | |
378 | after_stack_adjust = current_pc + 2; | |
379 | } | |
380 | continue; | |
381 | } | |
382 | if (insn == 0x1d8f) | |
383 | { /* mv fp, sp */ | |
384 | after_prologue = current_pc + 2; | |
385 | break; /* end of stack adjustments */ | |
386 | } | |
cea15572 | 387 | |
025bb325 | 388 | /* Nop looks like a branch, continue explicitly. */ |
d95a8903 AC |
389 | if (insn == 0x7000) |
390 | { | |
391 | after_prologue = current_pc + 2; | |
025bb325 | 392 | continue; /* nop occurs between pushes. */ |
d95a8903 | 393 | } |
025bb325 | 394 | /* End of prolog if any of these are trap instructions. */ |
cea15572 KI |
395 | if ((insn & 0xfff0) == 0x10f0) |
396 | { | |
397 | after_prologue = current_pc; | |
398 | break; | |
399 | } | |
025bb325 | 400 | /* End of prolog if any of these are branch instructions. */ |
d95a8903 AC |
401 | if ((op1 == 0x7000) || (op1 == 0xb000) || (op1 == 0xf000)) |
402 | { | |
403 | after_prologue = current_pc; | |
d95a8903 AC |
404 | continue; |
405 | } | |
025bb325 | 406 | /* Some of the branch instructions are mixed with other types. */ |
d95a8903 AC |
407 | if (op1 == 0x1000) |
408 | { | |
409 | int subop = insn & 0x0ff0; | |
410 | if ((subop == 0x0ec0) || (subop == 0x0fc0)) | |
411 | { | |
412 | after_prologue = current_pc; | |
d95a8903 AC |
413 | continue; /* jmp , jl */ |
414 | } | |
415 | } | |
416 | } | |
417 | ||
cea15572 KI |
418 | if (framelength) |
419 | *framelength = framesize; | |
420 | ||
d95a8903 AC |
421 | if (current_pc >= scan_limit) |
422 | { | |
423 | if (pl_endptr) | |
424 | { | |
425 | if (after_stack_adjust != 0) | |
426 | /* We did not find a "mv fp,sp", but we DID find | |
427 | a stack_adjust. Is it safe to use that as the | |
025bb325 | 428 | end of the prologue? I just don't know. */ |
d95a8903 AC |
429 | { |
430 | *pl_endptr = after_stack_adjust; | |
431 | } | |
cea15572 KI |
432 | else if (after_push != 0) |
433 | /* We did not find a "mv fp,sp", but we DID find | |
434 | a push. Is it safe to use that as the | |
025bb325 | 435 | end of the prologue? I just don't know. */ |
cea15572 KI |
436 | { |
437 | *pl_endptr = after_push; | |
438 | } | |
d95a8903 AC |
439 | else |
440 | /* We reached the end of the loop without finding the end | |
025bb325 MS |
441 | of the prologue. No way to win -- we should report |
442 | failure. The way we do that is to return the original | |
443 | start_pc. GDB will set a breakpoint at the start of | |
444 | the function (etc.) */ | |
d95a8903 AC |
445 | *pl_endptr = start_pc; |
446 | } | |
cea15572 | 447 | return 0; |
d95a8903 | 448 | } |
cea15572 | 449 | |
d95a8903 AC |
450 | if (after_prologue == 0) |
451 | after_prologue = current_pc; | |
452 | ||
453 | if (pl_endptr) | |
454 | *pl_endptr = after_prologue; | |
cea15572 KI |
455 | |
456 | return 0; | |
d95a8903 AC |
457 | } /* decode_prologue */ |
458 | ||
459 | /* Function: skip_prologue | |
025bb325 | 460 | Find end of function prologue. */ |
d95a8903 | 461 | |
cea15572 | 462 | #define DEFAULT_SEARCH_LIMIT 128 |
d95a8903 | 463 | |
63807e1d | 464 | static CORE_ADDR |
6093d2eb | 465 | m32r_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
d95a8903 | 466 | { |
e17a4113 | 467 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d95a8903 AC |
468 | CORE_ADDR func_addr, func_end; |
469 | struct symtab_and_line sal; | |
cea15572 | 470 | LONGEST return_value; |
d95a8903 | 471 | |
025bb325 | 472 | /* See what the symbol table says. */ |
d95a8903 AC |
473 | |
474 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
475 | { | |
476 | sal = find_pc_line (func_addr, 0); | |
477 | ||
478 | if (sal.line != 0 && sal.end <= func_end) | |
479 | { | |
480 | func_end = sal.end; | |
481 | } | |
482 | else | |
483 | /* Either there's no line info, or the line after the prologue is after | |
484 | the end of the function. In this case, there probably isn't a | |
485 | prologue. */ | |
486 | { | |
487 | func_end = min (func_end, func_addr + DEFAULT_SEARCH_LIMIT); | |
488 | } | |
489 | } | |
490 | else | |
491 | func_end = pc + DEFAULT_SEARCH_LIMIT; | |
cea15572 | 492 | |
025bb325 | 493 | /* If pc's location is not readable, just quit. */ |
e17a4113 | 494 | if (!safe_read_memory_integer (pc, 4, byte_order, &return_value)) |
cea15572 KI |
495 | return pc; |
496 | ||
497 | /* Find the end of prologue. */ | |
e17a4113 | 498 | if (decode_prologue (gdbarch, pc, func_end, &sal.end, NULL) < 0) |
cea15572 KI |
499 | return pc; |
500 | ||
d95a8903 AC |
501 | return sal.end; |
502 | } | |
503 | ||
d95a8903 AC |
504 | struct m32r_unwind_cache |
505 | { | |
506 | /* The previous frame's inner most stack address. Used as this | |
507 | frame ID's stack_addr. */ | |
508 | CORE_ADDR prev_sp; | |
509 | /* The frame's base, optionally used by the high-level debug info. */ | |
510 | CORE_ADDR base; | |
511 | int size; | |
512 | /* How far the SP and r13 (FP) have been offset from the start of | |
513 | the stack frame (as defined by the previous frame's stack | |
514 | pointer). */ | |
515 | LONGEST sp_offset; | |
516 | LONGEST r13_offset; | |
517 | int uses_frame; | |
518 | /* Table indicating the location of each and every register. */ | |
519 | struct trad_frame_saved_reg *saved_regs; | |
520 | }; | |
521 | ||
522 | /* Put here the code to store, into fi->saved_regs, the addresses of | |
523 | the saved registers of frame described by FRAME_INFO. This | |
524 | includes special registers such as pc and fp saved in special ways | |
525 | in the stack frame. sp is even more special: the address we return | |
025bb325 | 526 | for it IS the sp for the next frame. */ |
d95a8903 AC |
527 | |
528 | static struct m32r_unwind_cache * | |
94afd7a6 | 529 | m32r_frame_unwind_cache (struct frame_info *this_frame, |
d95a8903 AC |
530 | void **this_prologue_cache) |
531 | { | |
cea15572 | 532 | CORE_ADDR pc, scan_limit; |
d95a8903 AC |
533 | ULONGEST prev_sp; |
534 | ULONGEST this_base; | |
22e048c9 | 535 | unsigned long op; |
d95a8903 AC |
536 | int i; |
537 | struct m32r_unwind_cache *info; | |
538 | ||
cea15572 | 539 | |
d95a8903 | 540 | if ((*this_prologue_cache)) |
9a3c8263 | 541 | return (struct m32r_unwind_cache *) (*this_prologue_cache); |
d95a8903 AC |
542 | |
543 | info = FRAME_OBSTACK_ZALLOC (struct m32r_unwind_cache); | |
544 | (*this_prologue_cache) = info; | |
94afd7a6 | 545 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
d95a8903 AC |
546 | |
547 | info->size = 0; | |
548 | info->sp_offset = 0; | |
d95a8903 | 549 | info->uses_frame = 0; |
cea15572 | 550 | |
94afd7a6 UW |
551 | scan_limit = get_frame_pc (this_frame); |
552 | for (pc = get_frame_func (this_frame); | |
cea15572 | 553 | pc > 0 && pc < scan_limit; pc += 2) |
d95a8903 AC |
554 | { |
555 | if ((pc & 2) == 0) | |
556 | { | |
94afd7a6 | 557 | op = get_frame_memory_unsigned (this_frame, pc, 4); |
d95a8903 AC |
558 | if ((op & 0x80000000) == 0x80000000) |
559 | { | |
560 | /* 32-bit instruction */ | |
561 | if ((op & 0xffff0000) == 0x8faf0000) | |
562 | { | |
563 | /* add3 sp,sp,xxxx */ | |
564 | short n = op & 0xffff; | |
565 | info->sp_offset += n; | |
566 | } | |
cea15572 | 567 | else if (((op >> 8) == 0xe4) |
94afd7a6 | 568 | && get_frame_memory_unsigned (this_frame, pc + 2, |
7e3dd49e | 569 | 2) == 0x0f24) |
d95a8903 | 570 | { |
cea15572 | 571 | /* ld24 r4, xxxxxx; sub sp, r4 */ |
d95a8903 AC |
572 | unsigned long n = op & 0xffffff; |
573 | info->sp_offset += n; | |
cea15572 | 574 | pc += 2; /* skip sub instruction */ |
d95a8903 | 575 | } |
d95a8903 | 576 | |
cea15572 KI |
577 | if (pc == scan_limit) |
578 | scan_limit += 2; /* extend the search */ | |
579 | pc += 2; /* skip the immediate data */ | |
d95a8903 AC |
580 | continue; |
581 | } | |
582 | } | |
583 | ||
584 | /* 16-bit instructions */ | |
94afd7a6 | 585 | op = get_frame_memory_unsigned (this_frame, pc, 2) & 0x7fff; |
d95a8903 AC |
586 | if ((op & 0xf0ff) == 0x207f) |
587 | { | |
588 | /* st rn, @-sp */ | |
589 | int regno = ((op >> 8) & 0xf); | |
590 | info->sp_offset -= 4; | |
591 | info->saved_regs[regno].addr = info->sp_offset; | |
592 | } | |
593 | else if ((op & 0xff00) == 0x4f00) | |
594 | { | |
595 | /* addi sp, xx */ | |
9ffbf372 | 596 | int n = (signed char) (op & 0xff); |
d95a8903 AC |
597 | info->sp_offset += n; |
598 | } | |
599 | else if (op == 0x1d8f) | |
600 | { | |
601 | /* mv fp, sp */ | |
602 | info->uses_frame = 1; | |
603 | info->r13_offset = info->sp_offset; | |
cea15572 KI |
604 | break; /* end of stack adjustments */ |
605 | } | |
606 | else if ((op & 0xfff0) == 0x10f0) | |
607 | { | |
025bb325 MS |
608 | /* End of prologue if this is a trap instruction. */ |
609 | break; /* End of stack adjustments. */ | |
d95a8903 | 610 | } |
d95a8903 AC |
611 | } |
612 | ||
613 | info->size = -info->sp_offset; | |
614 | ||
615 | /* Compute the previous frame's stack pointer (which is also the | |
616 | frame's ID's stack address), and this frame's base pointer. */ | |
617 | if (info->uses_frame) | |
618 | { | |
619 | /* The SP was moved to the FP. This indicates that a new frame | |
620 | was created. Get THIS frame's FP value by unwinding it from | |
621 | the next frame. */ | |
94afd7a6 | 622 | this_base = get_frame_register_unsigned (this_frame, M32R_FP_REGNUM); |
d95a8903 AC |
623 | /* The FP points at the last saved register. Adjust the FP back |
624 | to before the first saved register giving the SP. */ | |
625 | prev_sp = this_base + info->size; | |
626 | } | |
627 | else | |
628 | { | |
629 | /* Assume that the FP is this frame's SP but with that pushed | |
630 | stack space added back. */ | |
94afd7a6 | 631 | this_base = get_frame_register_unsigned (this_frame, M32R_SP_REGNUM); |
d95a8903 AC |
632 | prev_sp = this_base + info->size; |
633 | } | |
634 | ||
635 | /* Convert that SP/BASE into real addresses. */ | |
636 | info->prev_sp = prev_sp; | |
637 | info->base = this_base; | |
638 | ||
639 | /* Adjust all the saved registers so that they contain addresses and | |
640 | not offsets. */ | |
94afd7a6 | 641 | for (i = 0; i < gdbarch_num_regs (get_frame_arch (this_frame)) - 1; i++) |
d95a8903 AC |
642 | if (trad_frame_addr_p (info->saved_regs, i)) |
643 | info->saved_regs[i].addr = (info->prev_sp + info->saved_regs[i].addr); | |
644 | ||
645 | /* The call instruction moves the caller's PC in the callee's LR. | |
646 | Since this is an unwind, do the reverse. Copy the location of LR | |
647 | into PC (the address / regnum) so that a request for PC will be | |
648 | converted into a request for the LR. */ | |
649 | info->saved_regs[M32R_PC_REGNUM] = info->saved_regs[LR_REGNUM]; | |
650 | ||
651 | /* The previous frame's SP needed to be computed. Save the computed | |
652 | value. */ | |
653 | trad_frame_set_value (info->saved_regs, M32R_SP_REGNUM, prev_sp); | |
654 | ||
655 | return info; | |
656 | } | |
657 | ||
658 | static CORE_ADDR | |
61a1198a | 659 | m32r_read_pc (struct regcache *regcache) |
d95a8903 | 660 | { |
7e3dd49e | 661 | ULONGEST pc; |
61a1198a | 662 | regcache_cooked_read_unsigned (regcache, M32R_PC_REGNUM, &pc); |
d95a8903 AC |
663 | return pc; |
664 | } | |
665 | ||
d95a8903 AC |
666 | static CORE_ADDR |
667 | m32r_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
668 | { | |
7e3dd49e | 669 | return frame_unwind_register_unsigned (next_frame, M32R_SP_REGNUM); |
d95a8903 AC |
670 | } |
671 | ||
672 | ||
673 | static CORE_ADDR | |
7d9b040b | 674 | m32r_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
d95a8903 AC |
675 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
676 | struct value **args, CORE_ADDR sp, int struct_return, | |
677 | CORE_ADDR struct_addr) | |
678 | { | |
e17a4113 | 679 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d95a8903 AC |
680 | int stack_offset, stack_alloc; |
681 | int argreg = ARG1_REGNUM; | |
682 | int argnum; | |
683 | struct type *type; | |
684 | enum type_code typecode; | |
685 | CORE_ADDR regval; | |
16ac4ab5 KI |
686 | gdb_byte *val; |
687 | gdb_byte valbuf[MAX_REGISTER_SIZE]; | |
d95a8903 | 688 | int len; |
d95a8903 | 689 | |
025bb325 | 690 | /* First force sp to a 4-byte alignment. */ |
d95a8903 AC |
691 | sp = sp & ~3; |
692 | ||
693 | /* Set the return address. For the m32r, the return breakpoint is | |
694 | always at BP_ADDR. */ | |
695 | regcache_cooked_write_unsigned (regcache, LR_REGNUM, bp_addr); | |
696 | ||
697 | /* If STRUCT_RETURN is true, then the struct return address (in | |
698 | STRUCT_ADDR) will consume the first argument-passing register. | |
699 | Both adjust the register count and store that value. */ | |
700 | if (struct_return) | |
701 | { | |
702 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); | |
703 | argreg++; | |
704 | } | |
705 | ||
025bb325 | 706 | /* Now make sure there's space on the stack. */ |
d95a8903 | 707 | for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++) |
4991999e | 708 | stack_alloc += ((TYPE_LENGTH (value_type (args[argnum])) + 3) & ~3); |
025bb325 | 709 | sp -= stack_alloc; /* Make room on stack for args. */ |
d95a8903 AC |
710 | |
711 | for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++) | |
712 | { | |
4991999e | 713 | type = value_type (args[argnum]); |
d95a8903 AC |
714 | typecode = TYPE_CODE (type); |
715 | len = TYPE_LENGTH (type); | |
716 | ||
717 | memset (valbuf, 0, sizeof (valbuf)); | |
718 | ||
719 | /* Passes structures that do not fit in 2 registers by reference. */ | |
720 | if (len > 8 | |
721 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) | |
722 | { | |
e17a4113 UW |
723 | store_unsigned_integer (valbuf, 4, byte_order, |
724 | value_address (args[argnum])); | |
d95a8903 AC |
725 | typecode = TYPE_CODE_PTR; |
726 | len = 4; | |
727 | val = valbuf; | |
728 | } | |
729 | else if (len < 4) | |
730 | { | |
025bb325 | 731 | /* Value gets right-justified in the register or stack word. */ |
7e3dd49e | 732 | memcpy (valbuf + (register_size (gdbarch, argreg) - len), |
16ac4ab5 | 733 | (gdb_byte *) value_contents (args[argnum]), len); |
d95a8903 AC |
734 | val = valbuf; |
735 | } | |
736 | else | |
16ac4ab5 | 737 | val = (gdb_byte *) value_contents (args[argnum]); |
d95a8903 AC |
738 | |
739 | while (len > 0) | |
740 | { | |
741 | if (argreg > ARGN_REGNUM) | |
742 | { | |
025bb325 | 743 | /* Must go on the stack. */ |
d95a8903 AC |
744 | write_memory (sp + stack_offset, val, 4); |
745 | stack_offset += 4; | |
746 | } | |
747 | else if (argreg <= ARGN_REGNUM) | |
748 | { | |
025bb325 | 749 | /* There's room in a register. */ |
d95a8903 | 750 | regval = |
7e3dd49e | 751 | extract_unsigned_integer (val, |
e17a4113 UW |
752 | register_size (gdbarch, argreg), |
753 | byte_order); | |
d95a8903 AC |
754 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
755 | } | |
756 | ||
757 | /* Store the value 4 bytes at a time. This means that things | |
758 | larger than 4 bytes may go partly in registers and partly | |
759 | on the stack. */ | |
7e3dd49e AC |
760 | len -= register_size (gdbarch, argreg); |
761 | val += register_size (gdbarch, argreg); | |
d95a8903 AC |
762 | } |
763 | } | |
764 | ||
765 | /* Finally, update the SP register. */ | |
766 | regcache_cooked_write_unsigned (regcache, M32R_SP_REGNUM, sp); | |
767 | ||
768 | return sp; | |
769 | } | |
770 | ||
771 | ||
772 | /* Given a return value in `regbuf' with a type `valtype', | |
773 | extract and copy its value into `valbuf'. */ | |
774 | ||
775 | static void | |
776 | m32r_extract_return_value (struct type *type, struct regcache *regcache, | |
7c543f7b | 777 | gdb_byte *dst) |
d95a8903 | 778 | { |
e17a4113 UW |
779 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
780 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
d95a8903 AC |
781 | int len = TYPE_LENGTH (type); |
782 | ULONGEST tmp; | |
783 | ||
784 | /* By using store_unsigned_integer we avoid having to do | |
785 | anything special for small big-endian values. */ | |
786 | regcache_cooked_read_unsigned (regcache, RET1_REGNUM, &tmp); | |
7c543f7b | 787 | store_unsigned_integer (dst, (len > 4 ? len - 4 : len), byte_order, tmp); |
d95a8903 AC |
788 | |
789 | /* Ignore return values more than 8 bytes in size because the m32r | |
025bb325 | 790 | returns anything more than 8 bytes in the stack. */ |
d95a8903 AC |
791 | if (len > 4) |
792 | { | |
793 | regcache_cooked_read_unsigned (regcache, RET1_REGNUM + 1, &tmp); | |
7c543f7b | 794 | store_unsigned_integer (dst + len - 4, 4, byte_order, tmp); |
d95a8903 AC |
795 | } |
796 | } | |
797 | ||
63807e1d | 798 | static enum return_value_convention |
6a3a010b | 799 | m32r_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
800 | struct type *valtype, struct regcache *regcache, |
801 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
14588880 KI |
802 | { |
803 | if (TYPE_LENGTH (valtype) > 8) | |
804 | return RETURN_VALUE_STRUCT_CONVENTION; | |
805 | else | |
806 | { | |
807 | if (readbuf != NULL) | |
808 | m32r_extract_return_value (valtype, regcache, readbuf); | |
809 | if (writebuf != NULL) | |
810 | m32r_store_return_value (valtype, regcache, writebuf); | |
811 | return RETURN_VALUE_REGISTER_CONVENTION; | |
812 | } | |
813 | } | |
814 | ||
815 | ||
d95a8903 AC |
816 | |
817 | static CORE_ADDR | |
818 | m32r_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
819 | { | |
7e3dd49e | 820 | return frame_unwind_register_unsigned (next_frame, M32R_PC_REGNUM); |
d95a8903 AC |
821 | } |
822 | ||
823 | /* Given a GDB frame, determine the address of the calling function's | |
824 | frame. This will be used to create a new GDB frame struct. */ | |
825 | ||
826 | static void | |
94afd7a6 | 827 | m32r_frame_this_id (struct frame_info *this_frame, |
d95a8903 AC |
828 | void **this_prologue_cache, struct frame_id *this_id) |
829 | { | |
830 | struct m32r_unwind_cache *info | |
94afd7a6 | 831 | = m32r_frame_unwind_cache (this_frame, this_prologue_cache); |
d95a8903 AC |
832 | CORE_ADDR base; |
833 | CORE_ADDR func; | |
3b7344d5 | 834 | struct bound_minimal_symbol msym_stack; |
d95a8903 AC |
835 | struct frame_id id; |
836 | ||
837 | /* The FUNC is easy. */ | |
94afd7a6 | 838 | func = get_frame_func (this_frame); |
d95a8903 | 839 | |
d95a8903 AC |
840 | /* Check if the stack is empty. */ |
841 | msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL); | |
77e371c0 | 842 | if (msym_stack.minsym && info->base == BMSYMBOL_VALUE_ADDRESS (msym_stack)) |
d95a8903 AC |
843 | return; |
844 | ||
845 | /* Hopefully the prologue analysis either correctly determined the | |
846 | frame's base (which is the SP from the previous frame), or set | |
847 | that base to "NULL". */ | |
848 | base = info->prev_sp; | |
849 | if (base == 0) | |
850 | return; | |
851 | ||
852 | id = frame_id_build (base, func); | |
d95a8903 AC |
853 | (*this_id) = id; |
854 | } | |
855 | ||
94afd7a6 UW |
856 | static struct value * |
857 | m32r_frame_prev_register (struct frame_info *this_frame, | |
858 | void **this_prologue_cache, int regnum) | |
d95a8903 AC |
859 | { |
860 | struct m32r_unwind_cache *info | |
94afd7a6 UW |
861 | = m32r_frame_unwind_cache (this_frame, this_prologue_cache); |
862 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); | |
d95a8903 AC |
863 | } |
864 | ||
865 | static const struct frame_unwind m32r_frame_unwind = { | |
866 | NORMAL_FRAME, | |
8fbca658 | 867 | default_frame_unwind_stop_reason, |
d95a8903 | 868 | m32r_frame_this_id, |
94afd7a6 UW |
869 | m32r_frame_prev_register, |
870 | NULL, | |
871 | default_frame_sniffer | |
d95a8903 AC |
872 | }; |
873 | ||
d95a8903 | 874 | static CORE_ADDR |
94afd7a6 | 875 | m32r_frame_base_address (struct frame_info *this_frame, void **this_cache) |
d95a8903 AC |
876 | { |
877 | struct m32r_unwind_cache *info | |
94afd7a6 | 878 | = m32r_frame_unwind_cache (this_frame, this_cache); |
d95a8903 AC |
879 | return info->base; |
880 | } | |
881 | ||
882 | static const struct frame_base m32r_frame_base = { | |
883 | &m32r_frame_unwind, | |
884 | m32r_frame_base_address, | |
885 | m32r_frame_base_address, | |
886 | m32r_frame_base_address | |
887 | }; | |
888 | ||
94afd7a6 UW |
889 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy |
890 | frame. The frame ID's base needs to match the TOS value saved by | |
891 | save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */ | |
d95a8903 AC |
892 | |
893 | static struct frame_id | |
94afd7a6 | 894 | m32r_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
d95a8903 | 895 | { |
94afd7a6 UW |
896 | CORE_ADDR sp = get_frame_register_unsigned (this_frame, M32R_SP_REGNUM); |
897 | return frame_id_build (sp, get_frame_pc (this_frame)); | |
d95a8903 AC |
898 | } |
899 | ||
900 | ||
901 | static gdbarch_init_ftype m32r_gdbarch_init; | |
902 | ||
903 | static struct gdbarch * | |
904 | m32r_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
905 | { | |
906 | struct gdbarch *gdbarch; | |
907 | struct gdbarch_tdep *tdep; | |
908 | ||
909 | /* If there is already a candidate, use it. */ | |
910 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
911 | if (arches != NULL) | |
912 | return arches->gdbarch; | |
913 | ||
914 | /* Allocate space for the new architecture. */ | |
70ba0933 | 915 | tdep = XNEW (struct gdbarch_tdep); |
d95a8903 AC |
916 | gdbarch = gdbarch_alloc (&info, tdep); |
917 | ||
918 | set_gdbarch_read_pc (gdbarch, m32r_read_pc); | |
d95a8903 AC |
919 | set_gdbarch_unwind_sp (gdbarch, m32r_unwind_sp); |
920 | ||
e839132d | 921 | set_gdbarch_num_regs (gdbarch, M32R_NUM_REGS); |
d27b54ad | 922 | set_gdbarch_pc_regnum (gdbarch, M32R_PC_REGNUM); |
d95a8903 AC |
923 | set_gdbarch_sp_regnum (gdbarch, M32R_SP_REGNUM); |
924 | set_gdbarch_register_name (gdbarch, m32r_register_name); | |
925 | set_gdbarch_register_type (gdbarch, m32r_register_type); | |
926 | ||
d95a8903 | 927 | set_gdbarch_push_dummy_call (gdbarch, m32r_push_dummy_call); |
14588880 | 928 | set_gdbarch_return_value (gdbarch, m32r_return_value); |
d95a8903 AC |
929 | |
930 | set_gdbarch_skip_prologue (gdbarch, m32r_skip_prologue); | |
931 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
d95a8903 AC |
932 | set_gdbarch_breakpoint_from_pc (gdbarch, m32r_breakpoint_from_pc); |
933 | set_gdbarch_memory_insert_breakpoint (gdbarch, | |
934 | m32r_memory_insert_breakpoint); | |
935 | set_gdbarch_memory_remove_breakpoint (gdbarch, | |
936 | m32r_memory_remove_breakpoint); | |
937 | ||
d95a8903 AC |
938 | set_gdbarch_frame_align (gdbarch, m32r_frame_align); |
939 | ||
d95a8903 AC |
940 | frame_base_set_default (gdbarch, &m32r_frame_base); |
941 | ||
942 | /* Methods for saving / extracting a dummy frame's ID. The ID's | |
943 | stack address must match the SP value returned by | |
944 | PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */ | |
94afd7a6 | 945 | set_gdbarch_dummy_id (gdbarch, m32r_dummy_id); |
d95a8903 AC |
946 | |
947 | /* Return the unwound PC value. */ | |
948 | set_gdbarch_unwind_pc (gdbarch, m32r_unwind_pc); | |
949 | ||
950 | set_gdbarch_print_insn (gdbarch, print_insn_m32r); | |
951 | ||
c46b0409 KI |
952 | /* Hook in ABI-specific overrides, if they have been registered. */ |
953 | gdbarch_init_osabi (info, gdbarch); | |
954 | ||
955 | /* Hook in the default unwinders. */ | |
94afd7a6 | 956 | frame_unwind_append_unwinder (gdbarch, &m32r_frame_unwind); |
c46b0409 | 957 | |
1c772458 UW |
958 | /* Support simple overlay manager. */ |
959 | set_gdbarch_overlay_update (gdbarch, simple_overlay_update); | |
960 | ||
d95a8903 AC |
961 | return gdbarch; |
962 | } | |
963 | ||
964 | void | |
965 | _initialize_m32r_tdep (void) | |
966 | { | |
967 | register_gdbarch_init (bfd_arch_m32r, m32r_gdbarch_init); | |
968 | } |