Commit | Line | Data |
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d95a8903 AC |
1 | /* Target-dependent code for Renesas M32R, for GDB. |
2 | ||
3 | Copyright 1996, 1998, 1999, 2000, 2001, 2002, 2003 Free Software | |
4 | Foundation, Inc. | |
5 | ||
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
22 | ||
23 | #include "defs.h" | |
24 | #include "frame.h" | |
25 | #include "frame-unwind.h" | |
26 | #include "frame-base.h" | |
27 | #include "symtab.h" | |
28 | #include "gdbtypes.h" | |
29 | #include "gdbcmd.h" | |
30 | #include "gdbcore.h" | |
31 | #include "gdb_string.h" | |
32 | #include "value.h" | |
33 | #include "inferior.h" | |
34 | #include "symfile.h" | |
35 | #include "objfiles.h" | |
36 | #include "language.h" | |
37 | #include "arch-utils.h" | |
38 | #include "regcache.h" | |
39 | #include "trad-frame.h" | |
73e8eb51 | 40 | #include "dis-asm.h" |
d95a8903 AC |
41 | |
42 | #include "gdb_assert.h" | |
43 | ||
9b32d526 | 44 | #include "m32r-tdep.h" |
d95a8903 AC |
45 | |
46 | /* Local functions */ | |
47 | ||
48 | extern void _initialize_m32r_tdep (void); | |
49 | ||
50 | static CORE_ADDR | |
51 | m32r_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
52 | { | |
53 | /* Align to the size of an instruction (so that they can safely be | |
54 | pushed onto the stack. */ | |
55 | return sp & ~3; | |
56 | } | |
57 | ||
d95a8903 AC |
58 | |
59 | /* BREAKPOINT */ | |
60 | #define M32R_BE_BREAKPOINT32 {0x10, 0xf1, 0x70, 0x00} | |
61 | #define M32R_LE_BREAKPOINT32 {0xf1, 0x10, 0x00, 0x70} | |
62 | #define M32R_BE_BREAKPOINT16 {0x10, 0xf1} | |
63 | #define M32R_LE_BREAKPOINT16 {0xf1, 0x10} | |
64 | ||
65 | static int | |
66 | m32r_memory_insert_breakpoint (CORE_ADDR addr, char *contents_cache) | |
67 | { | |
68 | int val; | |
69 | unsigned char *bp; | |
70 | int bplen; | |
71 | ||
72 | bplen = (addr & 3) ? 2 : 4; | |
73 | ||
74 | /* Save the memory contents. */ | |
75 | val = target_read_memory (addr, contents_cache, bplen); | |
76 | if (val != 0) | |
77 | return val; /* return error */ | |
78 | ||
79 | /* Determine appropriate breakpoint contents and size for this address. */ | |
80 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
81 | { | |
7e3dd49e AC |
82 | if (((addr & 3) == 0) |
83 | && ((contents_cache[0] & 0x80) || (contents_cache[2] & 0x80))) | |
d95a8903 AC |
84 | { |
85 | static unsigned char insn[] = M32R_BE_BREAKPOINT32; | |
86 | bp = insn; | |
87 | bplen = sizeof (insn); | |
88 | } | |
89 | else | |
90 | { | |
91 | static unsigned char insn[] = M32R_BE_BREAKPOINT16; | |
92 | bp = insn; | |
93 | bplen = sizeof (insn); | |
94 | } | |
95 | } | |
96 | else | |
97 | { /* little-endian */ | |
7e3dd49e AC |
98 | if (((addr & 3) == 0) |
99 | && ((contents_cache[1] & 0x80) || (contents_cache[3] & 0x80))) | |
d95a8903 AC |
100 | { |
101 | static unsigned char insn[] = M32R_LE_BREAKPOINT32; | |
102 | bp = insn; | |
103 | bplen = sizeof (insn); | |
104 | } | |
105 | else | |
106 | { | |
107 | static unsigned char insn[] = M32R_LE_BREAKPOINT16; | |
108 | bp = insn; | |
109 | bplen = sizeof (insn); | |
110 | } | |
111 | } | |
112 | ||
113 | /* Write the breakpoint. */ | |
114 | val = target_write_memory (addr, (char *) bp, bplen); | |
115 | return val; | |
116 | } | |
117 | ||
118 | static int | |
119 | m32r_memory_remove_breakpoint (CORE_ADDR addr, char *contents_cache) | |
120 | { | |
121 | int val; | |
122 | int bplen; | |
123 | ||
124 | /* Determine appropriate breakpoint contents and size for this address. */ | |
125 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
126 | { | |
7e3dd49e AC |
127 | if (((addr & 3) == 0) |
128 | && ((contents_cache[0] & 0x80) || (contents_cache[2] & 0x80))) | |
d95a8903 AC |
129 | { |
130 | static unsigned char insn[] = M32R_BE_BREAKPOINT32; | |
131 | bplen = sizeof (insn); | |
132 | } | |
133 | else | |
134 | { | |
135 | static unsigned char insn[] = M32R_BE_BREAKPOINT16; | |
136 | bplen = sizeof (insn); | |
137 | } | |
138 | } | |
139 | else | |
140 | { | |
141 | /* little-endian */ | |
7e3dd49e AC |
142 | if (((addr & 3) == 0) |
143 | && ((contents_cache[1] & 0x80) || (contents_cache[3] & 0x80))) | |
d95a8903 AC |
144 | { |
145 | static unsigned char insn[] = M32R_BE_BREAKPOINT32; | |
146 | bplen = sizeof (insn); | |
147 | } | |
148 | else | |
149 | { | |
150 | static unsigned char insn[] = M32R_BE_BREAKPOINT16; | |
151 | bplen = sizeof (insn); | |
152 | } | |
153 | } | |
154 | ||
155 | /* Write contents. */ | |
156 | val = target_write_memory (addr, contents_cache, bplen); | |
157 | return val; | |
158 | } | |
159 | ||
160 | static const unsigned char * | |
161 | m32r_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) | |
162 | { | |
163 | unsigned char *bp; | |
164 | ||
165 | /* Determine appropriate breakpoint. */ | |
166 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
167 | { | |
168 | if ((*pcptr & 3) == 0) | |
169 | { | |
170 | static unsigned char insn[] = M32R_BE_BREAKPOINT32; | |
171 | bp = insn; | |
172 | *lenptr = sizeof (insn); | |
173 | } | |
174 | else | |
175 | { | |
176 | static unsigned char insn[] = M32R_BE_BREAKPOINT16; | |
177 | bp = insn; | |
178 | *lenptr = sizeof (insn); | |
179 | } | |
180 | } | |
181 | else | |
182 | { | |
183 | if ((*pcptr & 3) == 0) | |
184 | { | |
185 | static unsigned char insn[] = M32R_LE_BREAKPOINT32; | |
186 | bp = insn; | |
187 | *lenptr = sizeof (insn); | |
188 | } | |
189 | else | |
190 | { | |
191 | static unsigned char insn[] = M32R_LE_BREAKPOINT16; | |
192 | bp = insn; | |
193 | *lenptr = sizeof (insn); | |
194 | } | |
195 | } | |
196 | ||
197 | return bp; | |
198 | } | |
199 | ||
200 | ||
201 | char *m32r_register_names[] = { | |
202 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
203 | "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp", | |
204 | "psw", "cbr", "spi", "spu", "bpc", "pc", "accl", "acch", | |
205 | "evb" | |
206 | }; | |
207 | ||
d95a8903 AC |
208 | static const char * |
209 | m32r_register_name (int reg_nr) | |
210 | { | |
211 | if (reg_nr < 0) | |
212 | return NULL; | |
9b32d526 | 213 | if (reg_nr >= M32R_NUM_REGS) |
d95a8903 AC |
214 | return NULL; |
215 | return m32r_register_names[reg_nr]; | |
216 | } | |
217 | ||
218 | ||
219 | /* Return the GDB type object for the "standard" data type | |
220 | of data in register N. */ | |
221 | ||
222 | static struct type * | |
223 | m32r_register_type (struct gdbarch *gdbarch, int reg_nr) | |
224 | { | |
225 | if (reg_nr == M32R_PC_REGNUM) | |
226 | return builtin_type_void_func_ptr; | |
227 | else if (reg_nr == M32R_SP_REGNUM || reg_nr == M32R_FP_REGNUM) | |
228 | return builtin_type_void_data_ptr; | |
229 | else | |
230 | return builtin_type_int32; | |
231 | } | |
232 | ||
233 | ||
234 | /* Write into appropriate registers a function return value | |
235 | of type TYPE, given in virtual format. | |
236 | ||
237 | Things always get returned in RET1_REGNUM, RET2_REGNUM. */ | |
238 | ||
239 | static void | |
240 | m32r_store_return_value (struct type *type, struct regcache *regcache, | |
241 | const void *valbuf) | |
242 | { | |
243 | CORE_ADDR regval; | |
244 | int len = TYPE_LENGTH (type); | |
245 | ||
246 | regval = extract_unsigned_integer (valbuf, len > 4 ? 4 : len); | |
247 | regcache_cooked_write_unsigned (regcache, RET1_REGNUM, regval); | |
248 | ||
249 | if (len > 4) | |
250 | { | |
880bc914 | 251 | regval = extract_unsigned_integer ((char *) valbuf + 4, len - 4); |
d95a8903 AC |
252 | regcache_cooked_write_unsigned (regcache, RET1_REGNUM + 1, regval); |
253 | } | |
254 | } | |
255 | ||
d95a8903 AC |
256 | /* This is required by skip_prologue. The results of decoding a prologue |
257 | should be cached because this thrashing is getting nuts. */ | |
258 | ||
259 | static void | |
260 | decode_prologue (CORE_ADDR start_pc, CORE_ADDR scan_limit, | |
261 | CORE_ADDR *pl_endptr) | |
262 | { | |
263 | unsigned long framesize; | |
264 | int insn; | |
265 | int op1; | |
266 | int maybe_one_more = 0; | |
267 | CORE_ADDR after_prologue = 0; | |
268 | CORE_ADDR after_stack_adjust = 0; | |
269 | CORE_ADDR current_pc; | |
270 | ||
271 | framesize = 0; | |
272 | after_prologue = 0; | |
273 | ||
274 | for (current_pc = start_pc; current_pc < scan_limit; current_pc += 2) | |
275 | { | |
276 | insn = read_memory_unsigned_integer (current_pc, 2); | |
277 | ||
278 | /* If this is a 32 bit instruction, we dont want to examine its | |
279 | immediate data as though it were an instruction */ | |
280 | if (current_pc & 0x02) | |
281 | { | |
282 | /* Clear the parallel execution bit from 16 bit instruction */ | |
283 | if (maybe_one_more) | |
284 | { | |
285 | /* The last instruction was a branch, usually terminates | |
286 | the series, but if this is a parallel instruction, | |
287 | it may be a stack framing instruction */ | |
288 | if (!(insn & 0x8000)) | |
289 | { | |
290 | /* nope, we are really done */ | |
291 | break; | |
292 | } | |
293 | } | |
294 | /* decode this instruction further */ | |
295 | insn &= 0x7fff; | |
296 | } | |
297 | else | |
298 | { | |
299 | if (maybe_one_more) | |
300 | break; /* This isnt the one more */ | |
301 | if (insn & 0x8000) | |
302 | { | |
303 | if (current_pc == scan_limit) | |
304 | scan_limit += 2; /* extend the search */ | |
305 | current_pc += 2; /* skip the immediate data */ | |
306 | if (insn == 0x8faf) /* add3 sp, sp, xxxx */ | |
307 | /* add 16 bit sign-extended offset */ | |
308 | { | |
309 | framesize += | |
310 | -((short) read_memory_unsigned_integer (current_pc, 2)); | |
311 | } | |
312 | else | |
313 | { | |
7e3dd49e AC |
314 | if (((insn >> 8) == 0xe4) /* ld24 r4, xxxxxx; sub sp, r4 */ |
315 | && read_memory_unsigned_integer (current_pc + 2, | |
316 | 2) == 0x0f24) | |
d95a8903 AC |
317 | /* subtract 24 bit sign-extended negative-offset */ |
318 | { | |
319 | insn = read_memory_unsigned_integer (current_pc - 2, 4); | |
320 | if (insn & 0x00800000) /* sign extend */ | |
321 | insn |= 0xff000000; /* negative */ | |
322 | else | |
323 | insn &= 0x00ffffff; /* positive */ | |
324 | framesize += insn; | |
325 | } | |
326 | } | |
327 | after_prologue = current_pc; | |
328 | continue; | |
329 | } | |
330 | } | |
331 | op1 = insn & 0xf000; /* isolate just the first nibble */ | |
332 | ||
333 | if ((insn & 0xf0ff) == 0x207f) | |
334 | { /* st reg, @-sp */ | |
335 | int regno; | |
336 | framesize += 4; | |
337 | regno = ((insn >> 8) & 0xf); | |
338 | after_prologue = 0; | |
339 | continue; | |
340 | } | |
341 | if ((insn >> 8) == 0x4f) /* addi sp, xx */ | |
342 | /* add 8 bit sign-extended offset */ | |
343 | { | |
344 | int stack_adjust = (char) (insn & 0xff); | |
345 | ||
346 | /* there are probably two of these stack adjustments: | |
347 | 1) A negative one in the prologue, and | |
348 | 2) A positive one in the epilogue. | |
349 | We are only interested in the first one. */ | |
350 | ||
351 | if (stack_adjust < 0) | |
352 | { | |
353 | framesize -= stack_adjust; | |
354 | after_prologue = 0; | |
355 | /* A frameless function may have no "mv fp, sp". | |
356 | In that case, this is the end of the prologue. */ | |
357 | after_stack_adjust = current_pc + 2; | |
358 | } | |
359 | continue; | |
360 | } | |
361 | if (insn == 0x1d8f) | |
362 | { /* mv fp, sp */ | |
363 | after_prologue = current_pc + 2; | |
364 | break; /* end of stack adjustments */ | |
365 | } | |
366 | /* Nop looks like a branch, continue explicitly */ | |
367 | if (insn == 0x7000) | |
368 | { | |
369 | after_prologue = current_pc + 2; | |
370 | continue; /* nop occurs between pushes */ | |
371 | } | |
372 | /* End of prolog if any of these are branch instructions */ | |
373 | if ((op1 == 0x7000) || (op1 == 0xb000) || (op1 == 0xf000)) | |
374 | { | |
375 | after_prologue = current_pc; | |
376 | maybe_one_more = 1; | |
377 | continue; | |
378 | } | |
379 | /* Some of the branch instructions are mixed with other types */ | |
380 | if (op1 == 0x1000) | |
381 | { | |
382 | int subop = insn & 0x0ff0; | |
383 | if ((subop == 0x0ec0) || (subop == 0x0fc0)) | |
384 | { | |
385 | after_prologue = current_pc; | |
386 | maybe_one_more = 1; | |
387 | continue; /* jmp , jl */ | |
388 | } | |
389 | } | |
390 | } | |
391 | ||
392 | if (current_pc >= scan_limit) | |
393 | { | |
394 | if (pl_endptr) | |
395 | { | |
396 | if (after_stack_adjust != 0) | |
397 | /* We did not find a "mv fp,sp", but we DID find | |
398 | a stack_adjust. Is it safe to use that as the | |
399 | end of the prologue? I just don't know. */ | |
400 | { | |
401 | *pl_endptr = after_stack_adjust; | |
402 | } | |
403 | else | |
404 | /* We reached the end of the loop without finding the end | |
405 | of the prologue. No way to win -- we should report failure. | |
406 | The way we do that is to return the original start_pc. | |
407 | GDB will set a breakpoint at the start of the function (etc.) */ | |
408 | *pl_endptr = start_pc; | |
409 | } | |
410 | return; | |
411 | } | |
412 | if (after_prologue == 0) | |
413 | after_prologue = current_pc; | |
414 | ||
415 | if (pl_endptr) | |
416 | *pl_endptr = after_prologue; | |
417 | } /* decode_prologue */ | |
418 | ||
419 | /* Function: skip_prologue | |
420 | Find end of function prologue */ | |
421 | ||
422 | #define DEFAULT_SEARCH_LIMIT 44 | |
423 | ||
424 | CORE_ADDR | |
425 | m32r_skip_prologue (CORE_ADDR pc) | |
426 | { | |
427 | CORE_ADDR func_addr, func_end; | |
428 | struct symtab_and_line sal; | |
429 | ||
430 | /* See what the symbol table says */ | |
431 | ||
432 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
433 | { | |
434 | sal = find_pc_line (func_addr, 0); | |
435 | ||
436 | if (sal.line != 0 && sal.end <= func_end) | |
437 | { | |
438 | func_end = sal.end; | |
439 | } | |
440 | else | |
441 | /* Either there's no line info, or the line after the prologue is after | |
442 | the end of the function. In this case, there probably isn't a | |
443 | prologue. */ | |
444 | { | |
445 | func_end = min (func_end, func_addr + DEFAULT_SEARCH_LIMIT); | |
446 | } | |
447 | } | |
448 | else | |
449 | func_end = pc + DEFAULT_SEARCH_LIMIT; | |
450 | decode_prologue (pc, func_end, &sal.end); | |
451 | return sal.end; | |
452 | } | |
453 | ||
454 | ||
455 | struct m32r_unwind_cache | |
456 | { | |
457 | /* The previous frame's inner most stack address. Used as this | |
458 | frame ID's stack_addr. */ | |
459 | CORE_ADDR prev_sp; | |
460 | /* The frame's base, optionally used by the high-level debug info. */ | |
461 | CORE_ADDR base; | |
462 | int size; | |
463 | /* How far the SP and r13 (FP) have been offset from the start of | |
464 | the stack frame (as defined by the previous frame's stack | |
465 | pointer). */ | |
466 | LONGEST sp_offset; | |
467 | LONGEST r13_offset; | |
468 | int uses_frame; | |
469 | /* Table indicating the location of each and every register. */ | |
470 | struct trad_frame_saved_reg *saved_regs; | |
471 | }; | |
472 | ||
473 | /* Put here the code to store, into fi->saved_regs, the addresses of | |
474 | the saved registers of frame described by FRAME_INFO. This | |
475 | includes special registers such as pc and fp saved in special ways | |
476 | in the stack frame. sp is even more special: the address we return | |
477 | for it IS the sp for the next frame. */ | |
478 | ||
479 | static struct m32r_unwind_cache * | |
480 | m32r_frame_unwind_cache (struct frame_info *next_frame, | |
481 | void **this_prologue_cache) | |
482 | { | |
483 | CORE_ADDR pc; | |
484 | ULONGEST prev_sp; | |
485 | ULONGEST this_base; | |
486 | unsigned long op; | |
487 | int i; | |
488 | struct m32r_unwind_cache *info; | |
489 | ||
490 | if ((*this_prologue_cache)) | |
491 | return (*this_prologue_cache); | |
492 | ||
493 | info = FRAME_OBSTACK_ZALLOC (struct m32r_unwind_cache); | |
494 | (*this_prologue_cache) = info; | |
495 | info->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
496 | ||
497 | info->size = 0; | |
498 | info->sp_offset = 0; | |
499 | ||
500 | info->uses_frame = 0; | |
501 | for (pc = frame_func_unwind (next_frame); | |
502 | pc > 0 && pc < frame_pc_unwind (next_frame); pc += 2) | |
503 | { | |
504 | if ((pc & 2) == 0) | |
505 | { | |
506 | op = get_frame_memory_unsigned (next_frame, pc, 4); | |
507 | if ((op & 0x80000000) == 0x80000000) | |
508 | { | |
509 | /* 32-bit instruction */ | |
510 | if ((op & 0xffff0000) == 0x8faf0000) | |
511 | { | |
512 | /* add3 sp,sp,xxxx */ | |
513 | short n = op & 0xffff; | |
514 | info->sp_offset += n; | |
515 | } | |
7e3dd49e AC |
516 | else if (((op >> 8) == 0xe4) /* ld24 r4, xxxxxx; sub sp, r4 */ |
517 | && get_frame_memory_unsigned (next_frame, pc + 4, | |
518 | 2) == 0x0f24) | |
d95a8903 AC |
519 | { |
520 | unsigned long n = op & 0xffffff; | |
521 | info->sp_offset += n; | |
522 | pc += 2; | |
523 | } | |
524 | else | |
525 | break; | |
526 | ||
527 | pc += 2; | |
528 | continue; | |
529 | } | |
530 | } | |
531 | ||
532 | /* 16-bit instructions */ | |
533 | op = get_frame_memory_unsigned (next_frame, pc, 2) & 0x7fff; | |
534 | if ((op & 0xf0ff) == 0x207f) | |
535 | { | |
536 | /* st rn, @-sp */ | |
537 | int regno = ((op >> 8) & 0xf); | |
538 | info->sp_offset -= 4; | |
539 | info->saved_regs[regno].addr = info->sp_offset; | |
540 | } | |
541 | else if ((op & 0xff00) == 0x4f00) | |
542 | { | |
543 | /* addi sp, xx */ | |
544 | int n = (char) (op & 0xff); | |
545 | info->sp_offset += n; | |
546 | } | |
547 | else if (op == 0x1d8f) | |
548 | { | |
549 | /* mv fp, sp */ | |
550 | info->uses_frame = 1; | |
551 | info->r13_offset = info->sp_offset; | |
552 | } | |
553 | else if (op == 0x7000) | |
554 | /* nop */ | |
555 | continue; | |
556 | else | |
557 | break; | |
558 | } | |
559 | ||
560 | info->size = -info->sp_offset; | |
561 | ||
562 | /* Compute the previous frame's stack pointer (which is also the | |
563 | frame's ID's stack address), and this frame's base pointer. */ | |
564 | if (info->uses_frame) | |
565 | { | |
566 | /* The SP was moved to the FP. This indicates that a new frame | |
567 | was created. Get THIS frame's FP value by unwinding it from | |
568 | the next frame. */ | |
7e3dd49e | 569 | this_base = frame_unwind_register_unsigned (next_frame, M32R_FP_REGNUM); |
d95a8903 AC |
570 | /* The FP points at the last saved register. Adjust the FP back |
571 | to before the first saved register giving the SP. */ | |
572 | prev_sp = this_base + info->size; | |
573 | } | |
574 | else | |
575 | { | |
576 | /* Assume that the FP is this frame's SP but with that pushed | |
577 | stack space added back. */ | |
7e3dd49e | 578 | this_base = frame_unwind_register_unsigned (next_frame, M32R_SP_REGNUM); |
d95a8903 AC |
579 | prev_sp = this_base + info->size; |
580 | } | |
581 | ||
582 | /* Convert that SP/BASE into real addresses. */ | |
583 | info->prev_sp = prev_sp; | |
584 | info->base = this_base; | |
585 | ||
586 | /* Adjust all the saved registers so that they contain addresses and | |
587 | not offsets. */ | |
588 | for (i = 0; i < NUM_REGS - 1; i++) | |
589 | if (trad_frame_addr_p (info->saved_regs, i)) | |
590 | info->saved_regs[i].addr = (info->prev_sp + info->saved_regs[i].addr); | |
591 | ||
592 | /* The call instruction moves the caller's PC in the callee's LR. | |
593 | Since this is an unwind, do the reverse. Copy the location of LR | |
594 | into PC (the address / regnum) so that a request for PC will be | |
595 | converted into a request for the LR. */ | |
596 | info->saved_regs[M32R_PC_REGNUM] = info->saved_regs[LR_REGNUM]; | |
597 | ||
598 | /* The previous frame's SP needed to be computed. Save the computed | |
599 | value. */ | |
600 | trad_frame_set_value (info->saved_regs, M32R_SP_REGNUM, prev_sp); | |
601 | ||
602 | return info; | |
603 | } | |
604 | ||
605 | static CORE_ADDR | |
606 | m32r_read_pc (ptid_t ptid) | |
607 | { | |
608 | ptid_t save_ptid; | |
7e3dd49e | 609 | ULONGEST pc; |
d95a8903 AC |
610 | |
611 | save_ptid = inferior_ptid; | |
612 | inferior_ptid = ptid; | |
7e3dd49e | 613 | regcache_cooked_read_unsigned (current_regcache, M32R_PC_REGNUM, &pc); |
d95a8903 AC |
614 | inferior_ptid = save_ptid; |
615 | return pc; | |
616 | } | |
617 | ||
618 | static void | |
619 | m32r_write_pc (CORE_ADDR val, ptid_t ptid) | |
620 | { | |
621 | ptid_t save_ptid; | |
622 | ||
623 | save_ptid = inferior_ptid; | |
624 | inferior_ptid = ptid; | |
625 | write_register (M32R_PC_REGNUM, val); | |
626 | inferior_ptid = save_ptid; | |
627 | } | |
628 | ||
629 | static CORE_ADDR | |
630 | m32r_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
631 | { | |
7e3dd49e | 632 | return frame_unwind_register_unsigned (next_frame, M32R_SP_REGNUM); |
d95a8903 AC |
633 | } |
634 | ||
635 | ||
636 | static CORE_ADDR | |
7d9b040b | 637 | m32r_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
d95a8903 AC |
638 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
639 | struct value **args, CORE_ADDR sp, int struct_return, | |
640 | CORE_ADDR struct_addr) | |
641 | { | |
642 | int stack_offset, stack_alloc; | |
643 | int argreg = ARG1_REGNUM; | |
644 | int argnum; | |
645 | struct type *type; | |
646 | enum type_code typecode; | |
647 | CORE_ADDR regval; | |
648 | char *val; | |
649 | char valbuf[MAX_REGISTER_SIZE]; | |
650 | int len; | |
651 | int odd_sized_struct; | |
652 | ||
653 | /* first force sp to a 4-byte alignment */ | |
654 | sp = sp & ~3; | |
655 | ||
656 | /* Set the return address. For the m32r, the return breakpoint is | |
657 | always at BP_ADDR. */ | |
658 | regcache_cooked_write_unsigned (regcache, LR_REGNUM, bp_addr); | |
659 | ||
660 | /* If STRUCT_RETURN is true, then the struct return address (in | |
661 | STRUCT_ADDR) will consume the first argument-passing register. | |
662 | Both adjust the register count and store that value. */ | |
663 | if (struct_return) | |
664 | { | |
665 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); | |
666 | argreg++; | |
667 | } | |
668 | ||
669 | /* Now make sure there's space on the stack */ | |
670 | for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++) | |
671 | stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3); | |
672 | sp -= stack_alloc; /* make room on stack for args */ | |
673 | ||
674 | for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++) | |
675 | { | |
676 | type = VALUE_TYPE (args[argnum]); | |
677 | typecode = TYPE_CODE (type); | |
678 | len = TYPE_LENGTH (type); | |
679 | ||
680 | memset (valbuf, 0, sizeof (valbuf)); | |
681 | ||
682 | /* Passes structures that do not fit in 2 registers by reference. */ | |
683 | if (len > 8 | |
684 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) | |
685 | { | |
686 | store_unsigned_integer (valbuf, 4, VALUE_ADDRESS (args[argnum])); | |
687 | typecode = TYPE_CODE_PTR; | |
688 | len = 4; | |
689 | val = valbuf; | |
690 | } | |
691 | else if (len < 4) | |
692 | { | |
693 | /* value gets right-justified in the register or stack word */ | |
7e3dd49e | 694 | memcpy (valbuf + (register_size (gdbarch, argreg) - len), |
d95a8903 AC |
695 | (char *) VALUE_CONTENTS (args[argnum]), len); |
696 | val = valbuf; | |
697 | } | |
698 | else | |
699 | val = (char *) VALUE_CONTENTS (args[argnum]); | |
700 | ||
701 | while (len > 0) | |
702 | { | |
703 | if (argreg > ARGN_REGNUM) | |
704 | { | |
705 | /* must go on the stack */ | |
706 | write_memory (sp + stack_offset, val, 4); | |
707 | stack_offset += 4; | |
708 | } | |
709 | else if (argreg <= ARGN_REGNUM) | |
710 | { | |
711 | /* there's room in a register */ | |
712 | regval = | |
7e3dd49e AC |
713 | extract_unsigned_integer (val, |
714 | register_size (gdbarch, argreg)); | |
d95a8903 AC |
715 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
716 | } | |
717 | ||
718 | /* Store the value 4 bytes at a time. This means that things | |
719 | larger than 4 bytes may go partly in registers and partly | |
720 | on the stack. */ | |
7e3dd49e AC |
721 | len -= register_size (gdbarch, argreg); |
722 | val += register_size (gdbarch, argreg); | |
d95a8903 AC |
723 | } |
724 | } | |
725 | ||
726 | /* Finally, update the SP register. */ | |
727 | regcache_cooked_write_unsigned (regcache, M32R_SP_REGNUM, sp); | |
728 | ||
729 | return sp; | |
730 | } | |
731 | ||
732 | ||
733 | /* Given a return value in `regbuf' with a type `valtype', | |
734 | extract and copy its value into `valbuf'. */ | |
735 | ||
736 | static void | |
737 | m32r_extract_return_value (struct type *type, struct regcache *regcache, | |
738 | void *dst) | |
739 | { | |
740 | bfd_byte *valbuf = dst; | |
741 | int len = TYPE_LENGTH (type); | |
742 | ULONGEST tmp; | |
743 | ||
744 | /* By using store_unsigned_integer we avoid having to do | |
745 | anything special for small big-endian values. */ | |
746 | regcache_cooked_read_unsigned (regcache, RET1_REGNUM, &tmp); | |
747 | store_unsigned_integer (valbuf, (len > 4 ? len - 4 : len), tmp); | |
748 | ||
749 | /* Ignore return values more than 8 bytes in size because the m32r | |
750 | returns anything more than 8 bytes in the stack. */ | |
751 | if (len > 4) | |
752 | { | |
753 | regcache_cooked_read_unsigned (regcache, RET1_REGNUM + 1, &tmp); | |
754 | store_unsigned_integer (valbuf + len - 4, 4, tmp); | |
755 | } | |
756 | } | |
757 | ||
14588880 KI |
758 | enum return_value_convention |
759 | m32r_return_value (struct gdbarch *gdbarch, struct type *valtype, | |
760 | struct regcache *regcache, void *readbuf, | |
761 | const void *writebuf) | |
762 | { | |
763 | if (TYPE_LENGTH (valtype) > 8) | |
764 | return RETURN_VALUE_STRUCT_CONVENTION; | |
765 | else | |
766 | { | |
767 | if (readbuf != NULL) | |
768 | m32r_extract_return_value (valtype, regcache, readbuf); | |
769 | if (writebuf != NULL) | |
770 | m32r_store_return_value (valtype, regcache, writebuf); | |
771 | return RETURN_VALUE_REGISTER_CONVENTION; | |
772 | } | |
773 | } | |
774 | ||
775 | ||
d95a8903 AC |
776 | |
777 | static CORE_ADDR | |
778 | m32r_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
779 | { | |
7e3dd49e | 780 | return frame_unwind_register_unsigned (next_frame, M32R_PC_REGNUM); |
d95a8903 AC |
781 | } |
782 | ||
783 | /* Given a GDB frame, determine the address of the calling function's | |
784 | frame. This will be used to create a new GDB frame struct. */ | |
785 | ||
786 | static void | |
787 | m32r_frame_this_id (struct frame_info *next_frame, | |
788 | void **this_prologue_cache, struct frame_id *this_id) | |
789 | { | |
790 | struct m32r_unwind_cache *info | |
791 | = m32r_frame_unwind_cache (next_frame, this_prologue_cache); | |
792 | CORE_ADDR base; | |
793 | CORE_ADDR func; | |
794 | struct minimal_symbol *msym_stack; | |
795 | struct frame_id id; | |
796 | ||
797 | /* The FUNC is easy. */ | |
798 | func = frame_func_unwind (next_frame); | |
799 | ||
d95a8903 AC |
800 | /* Check if the stack is empty. */ |
801 | msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL); | |
802 | if (msym_stack && info->base == SYMBOL_VALUE_ADDRESS (msym_stack)) | |
803 | return; | |
804 | ||
805 | /* Hopefully the prologue analysis either correctly determined the | |
806 | frame's base (which is the SP from the previous frame), or set | |
807 | that base to "NULL". */ | |
808 | base = info->prev_sp; | |
809 | if (base == 0) | |
810 | return; | |
811 | ||
812 | id = frame_id_build (base, func); | |
d95a8903 AC |
813 | (*this_id) = id; |
814 | } | |
815 | ||
816 | static void | |
817 | m32r_frame_prev_register (struct frame_info *next_frame, | |
818 | void **this_prologue_cache, | |
819 | int regnum, int *optimizedp, | |
820 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
821 | int *realnump, void *bufferp) | |
822 | { | |
823 | struct m32r_unwind_cache *info | |
824 | = m32r_frame_unwind_cache (next_frame, this_prologue_cache); | |
1f67027d AC |
825 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, |
826 | optimizedp, lvalp, addrp, realnump, bufferp); | |
d95a8903 AC |
827 | } |
828 | ||
829 | static const struct frame_unwind m32r_frame_unwind = { | |
830 | NORMAL_FRAME, | |
831 | m32r_frame_this_id, | |
832 | m32r_frame_prev_register | |
833 | }; | |
834 | ||
835 | static const struct frame_unwind * | |
7e3dd49e | 836 | m32r_frame_sniffer (struct frame_info *next_frame) |
d95a8903 AC |
837 | { |
838 | return &m32r_frame_unwind; | |
839 | } | |
840 | ||
841 | static CORE_ADDR | |
842 | m32r_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
843 | { | |
844 | struct m32r_unwind_cache *info | |
845 | = m32r_frame_unwind_cache (next_frame, this_cache); | |
846 | return info->base; | |
847 | } | |
848 | ||
849 | static const struct frame_base m32r_frame_base = { | |
850 | &m32r_frame_unwind, | |
851 | m32r_frame_base_address, | |
852 | m32r_frame_base_address, | |
853 | m32r_frame_base_address | |
854 | }; | |
855 | ||
856 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that | |
857 | dummy frame. The frame ID's base needs to match the TOS value | |
858 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
859 | breakpoint. */ | |
860 | ||
861 | static struct frame_id | |
862 | m32r_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
863 | { | |
864 | return frame_id_build (m32r_unwind_sp (gdbarch, next_frame), | |
865 | frame_pc_unwind (next_frame)); | |
866 | } | |
867 | ||
868 | ||
869 | static gdbarch_init_ftype m32r_gdbarch_init; | |
870 | ||
871 | static struct gdbarch * | |
872 | m32r_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
873 | { | |
874 | struct gdbarch *gdbarch; | |
875 | struct gdbarch_tdep *tdep; | |
876 | ||
877 | /* If there is already a candidate, use it. */ | |
878 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
879 | if (arches != NULL) | |
880 | return arches->gdbarch; | |
881 | ||
882 | /* Allocate space for the new architecture. */ | |
883 | tdep = XMALLOC (struct gdbarch_tdep); | |
884 | gdbarch = gdbarch_alloc (&info, tdep); | |
885 | ||
886 | set_gdbarch_read_pc (gdbarch, m32r_read_pc); | |
887 | set_gdbarch_write_pc (gdbarch, m32r_write_pc); | |
888 | set_gdbarch_unwind_sp (gdbarch, m32r_unwind_sp); | |
889 | ||
9b32d526 | 890 | set_gdbarch_num_regs (gdbarch, M32R_NUM_REGS); |
d95a8903 AC |
891 | set_gdbarch_sp_regnum (gdbarch, M32R_SP_REGNUM); |
892 | set_gdbarch_register_name (gdbarch, m32r_register_name); | |
893 | set_gdbarch_register_type (gdbarch, m32r_register_type); | |
894 | ||
d95a8903 | 895 | set_gdbarch_push_dummy_call (gdbarch, m32r_push_dummy_call); |
14588880 | 896 | set_gdbarch_return_value (gdbarch, m32r_return_value); |
d95a8903 AC |
897 | |
898 | set_gdbarch_skip_prologue (gdbarch, m32r_skip_prologue); | |
899 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
d95a8903 AC |
900 | set_gdbarch_breakpoint_from_pc (gdbarch, m32r_breakpoint_from_pc); |
901 | set_gdbarch_memory_insert_breakpoint (gdbarch, | |
902 | m32r_memory_insert_breakpoint); | |
903 | set_gdbarch_memory_remove_breakpoint (gdbarch, | |
904 | m32r_memory_remove_breakpoint); | |
905 | ||
d95a8903 AC |
906 | set_gdbarch_frame_align (gdbarch, m32r_frame_align); |
907 | ||
7e3dd49e | 908 | frame_unwind_append_sniffer (gdbarch, m32r_frame_sniffer); |
d95a8903 AC |
909 | frame_base_set_default (gdbarch, &m32r_frame_base); |
910 | ||
911 | /* Methods for saving / extracting a dummy frame's ID. The ID's | |
912 | stack address must match the SP value returned by | |
913 | PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */ | |
914 | set_gdbarch_unwind_dummy_id (gdbarch, m32r_unwind_dummy_id); | |
915 | ||
916 | /* Return the unwound PC value. */ | |
917 | set_gdbarch_unwind_pc (gdbarch, m32r_unwind_pc); | |
918 | ||
919 | set_gdbarch_print_insn (gdbarch, print_insn_m32r); | |
920 | ||
921 | return gdbarch; | |
922 | } | |
923 | ||
924 | void | |
925 | _initialize_m32r_tdep (void) | |
926 | { | |
927 | register_gdbarch_init (bfd_arch_m32r, m32r_gdbarch_init); | |
928 | } |