Commit | Line | Data |
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908f682f | 1 | /* Target-dependent code for Motorola 68HC11 & 68HC12 |
931aecf5 | 2 | |
0fb0cc75 | 3 | Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 |
6aba47ca | 4 | Free Software Foundation, Inc. |
931aecf5 | 5 | |
ffe1f3ee | 6 | Contributed by Stephane Carrez, stcarrez@nerim.fr |
78073dd8 | 7 | |
a9762ec7 JB |
8 | This file is part of GDB. |
9 | ||
10 | This program is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 3 of the License, or | |
13 | (at your option) any later version. | |
14 | ||
15 | This program is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
78073dd8 | 22 | |
78073dd8 | 23 | |
82c230c2 SC |
24 | #include "defs.h" |
25 | #include "frame.h" | |
1ea653ae SC |
26 | #include "frame-unwind.h" |
27 | #include "frame-base.h" | |
28 | #include "dwarf2-frame.h" | |
29 | #include "trad-frame.h" | |
82c230c2 SC |
30 | #include "symtab.h" |
31 | #include "gdbtypes.h" | |
32 | #include "gdbcmd.h" | |
33 | #include "gdbcore.h" | |
34 | #include "gdb_string.h" | |
35 | #include "value.h" | |
36 | #include "inferior.h" | |
37 | #include "dis-asm.h" | |
38 | #include "symfile.h" | |
39 | #include "objfiles.h" | |
40 | #include "arch-utils.h" | |
4e052eda | 41 | #include "regcache.h" |
b631436b | 42 | #include "reggroups.h" |
78073dd8 | 43 | |
82c230c2 SC |
44 | #include "target.h" |
45 | #include "opcode/m68hc11.h" | |
81967506 SC |
46 | #include "elf/m68hc11.h" |
47 | #include "elf-bfd.h" | |
78073dd8 | 48 | |
7df11f59 SC |
49 | /* Macros for setting and testing a bit in a minimal symbol. |
50 | For 68HC11/68HC12 we have two flags that tell which return | |
51 | type the function is using. This is used for prologue and frame | |
52 | analysis to compute correct stack frame layout. | |
53 | ||
54 | The MSB of the minimal symbol's "info" field is used for this purpose. | |
7df11f59 SC |
55 | |
56 | MSYMBOL_SET_RTC Actually sets the "RTC" bit. | |
57 | MSYMBOL_SET_RTI Actually sets the "RTI" bit. | |
58 | MSYMBOL_IS_RTC Tests the "RTC" bit in a minimal symbol. | |
f594e5e9 | 59 | MSYMBOL_IS_RTI Tests the "RTC" bit in a minimal symbol. */ |
7df11f59 SC |
60 | |
61 | #define MSYMBOL_SET_RTC(msym) \ | |
b887350f | 62 | MSYMBOL_TARGET_FLAG_1 (msym) = 1 |
7df11f59 SC |
63 | |
64 | #define MSYMBOL_SET_RTI(msym) \ | |
b887350f | 65 | MSYMBOL_TARGET_FLAG_2 (msym) = 1 |
7df11f59 SC |
66 | |
67 | #define MSYMBOL_IS_RTC(msym) \ | |
b887350f | 68 | MSYMBOL_TARGET_FLAG_1 (msym) |
7df11f59 SC |
69 | |
70 | #define MSYMBOL_IS_RTI(msym) \ | |
b887350f | 71 | MSYMBOL_TARGET_FLAG_2 (msym) |
7df11f59 | 72 | |
7df11f59 SC |
73 | enum insn_return_kind { |
74 | RETURN_RTS, | |
75 | RETURN_RTC, | |
76 | RETURN_RTI | |
77 | }; | |
78 | ||
79 | ||
7157eed4 | 80 | /* Register numbers of various important registers. */ |
78073dd8 | 81 | |
82c230c2 SC |
82 | #define HARD_X_REGNUM 0 |
83 | #define HARD_D_REGNUM 1 | |
84 | #define HARD_Y_REGNUM 2 | |
85 | #define HARD_SP_REGNUM 3 | |
86 | #define HARD_PC_REGNUM 4 | |
87 | ||
88 | #define HARD_A_REGNUM 5 | |
89 | #define HARD_B_REGNUM 6 | |
90 | #define HARD_CCR_REGNUM 7 | |
5706502a SC |
91 | |
92 | /* 68HC12 page number register. | |
93 | Note: to keep a compatibility with gcc register naming, we must | |
94 | not have to rename FP and other soft registers. The page register | |
f57d151a | 95 | is a real hard register and must therefore be counted by gdbarch_num_regs. |
5706502a SC |
96 | For this it has the same number as Z register (which is not used). */ |
97 | #define HARD_PAGE_REGNUM 8 | |
98 | #define M68HC11_LAST_HARD_REG (HARD_PAGE_REGNUM) | |
82c230c2 SC |
99 | |
100 | /* Z is replaced by X or Y by gcc during machine reorg. | |
101 | ??? There is no way to get it and even know whether | |
102 | it's in X or Y or in ZS. */ | |
103 | #define SOFT_Z_REGNUM 8 | |
104 | ||
105 | /* Soft registers. These registers are special. There are treated | |
106 | like normal hard registers by gcc and gdb (ie, within dwarf2 info). | |
107 | They are physically located in memory. */ | |
108 | #define SOFT_FP_REGNUM 9 | |
109 | #define SOFT_TMP_REGNUM 10 | |
110 | #define SOFT_ZS_REGNUM 11 | |
111 | #define SOFT_XY_REGNUM 12 | |
f91a8b6b SC |
112 | #define SOFT_UNUSED_REGNUM 13 |
113 | #define SOFT_D1_REGNUM 14 | |
82c230c2 SC |
114 | #define SOFT_D32_REGNUM (SOFT_D1_REGNUM+31) |
115 | #define M68HC11_MAX_SOFT_REGS 32 | |
116 | ||
117 | #define M68HC11_NUM_REGS (8) | |
118 | #define M68HC11_NUM_PSEUDO_REGS (M68HC11_MAX_SOFT_REGS+5) | |
119 | #define M68HC11_ALL_REGS (M68HC11_NUM_REGS+M68HC11_NUM_PSEUDO_REGS) | |
120 | ||
121 | #define M68HC11_REG_SIZE (2) | |
122 | ||
548bcbec SC |
123 | #define M68HC12_NUM_REGS (9) |
124 | #define M68HC12_NUM_PSEUDO_REGS ((M68HC11_MAX_SOFT_REGS+5)+1-1) | |
125 | #define M68HC12_HARD_PC_REGNUM (SOFT_D32_REGNUM+1) | |
126 | ||
908f682f | 127 | struct insn_sequence; |
82c230c2 SC |
128 | struct gdbarch_tdep |
129 | { | |
5d1a66bd SC |
130 | /* Stack pointer correction value. For 68hc11, the stack pointer points |
131 | to the next push location. An offset of 1 must be applied to obtain | |
132 | the address where the last value is saved. For 68hc12, the stack | |
133 | pointer points to the last value pushed. No offset is necessary. */ | |
134 | int stack_correction; | |
908f682f SC |
135 | |
136 | /* Description of instructions in the prologue. */ | |
137 | struct insn_sequence *prologue; | |
81967506 | 138 | |
7df11f59 SC |
139 | /* True if the page memory bank register is available |
140 | and must be used. */ | |
141 | int use_page_register; | |
142 | ||
81967506 SC |
143 | /* ELF flags for ABI. */ |
144 | int elf_flags; | |
82c230c2 SC |
145 | }; |
146 | ||
be8626e0 MD |
147 | #define STACK_CORRECTION(gdbarch) (gdbarch_tdep (gdbarch)->stack_correction) |
148 | #define USE_PAGE_REGISTER(gdbarch) (gdbarch_tdep (gdbarch)->use_page_register) | |
5d1a66bd | 149 | |
1ea653ae SC |
150 | struct m68hc11_unwind_cache |
151 | { | |
152 | /* The previous frame's inner most stack address. Used as this | |
153 | frame ID's stack_addr. */ | |
154 | CORE_ADDR prev_sp; | |
155 | /* The frame's base, optionally used by the high-level debug info. */ | |
156 | CORE_ADDR base; | |
157 | CORE_ADDR pc; | |
158 | int size; | |
159 | int prologue_type; | |
160 | CORE_ADDR return_pc; | |
161 | CORE_ADDR sp_offset; | |
162 | int frameless; | |
163 | enum insn_return_kind return_kind; | |
164 | ||
165 | /* Table indicating the location of each and every register. */ | |
166 | struct trad_frame_saved_reg *saved_regs; | |
167 | }; | |
168 | ||
82c230c2 SC |
169 | /* Table of registers for 68HC11. This includes the hard registers |
170 | and the soft registers used by GCC. */ | |
171 | static char * | |
172 | m68hc11_register_names[] = | |
173 | { | |
174 | "x", "d", "y", "sp", "pc", "a", "b", | |
5706502a | 175 | "ccr", "page", "frame","tmp", "zs", "xy", 0, |
82c230c2 SC |
176 | "d1", "d2", "d3", "d4", "d5", "d6", "d7", |
177 | "d8", "d9", "d10", "d11", "d12", "d13", "d14", | |
178 | "d15", "d16", "d17", "d18", "d19", "d20", "d21", | |
179 | "d22", "d23", "d24", "d25", "d26", "d27", "d28", | |
180 | "d29", "d30", "d31", "d32" | |
181 | }; | |
78073dd8 | 182 | |
82c230c2 SC |
183 | struct m68hc11_soft_reg |
184 | { | |
185 | const char *name; | |
186 | CORE_ADDR addr; | |
187 | }; | |
78073dd8 | 188 | |
82c230c2 | 189 | static struct m68hc11_soft_reg soft_regs[M68HC11_ALL_REGS]; |
78073dd8 | 190 | |
82c230c2 | 191 | #define M68HC11_FP_ADDR soft_regs[SOFT_FP_REGNUM].addr |
78073dd8 | 192 | |
82c230c2 SC |
193 | static int soft_min_addr; |
194 | static int soft_max_addr; | |
195 | static int soft_reg_initialized = 0; | |
78073dd8 | 196 | |
82c230c2 SC |
197 | /* Look in the symbol table for the address of a pseudo register |
198 | in memory. If we don't find it, pretend the register is not used | |
199 | and not available. */ | |
200 | static void | |
201 | m68hc11_get_register_info (struct m68hc11_soft_reg *reg, const char *name) | |
202 | { | |
203 | struct minimal_symbol *msymbol; | |
78073dd8 | 204 | |
82c230c2 SC |
205 | msymbol = lookup_minimal_symbol (name, NULL, NULL); |
206 | if (msymbol) | |
207 | { | |
208 | reg->addr = SYMBOL_VALUE_ADDRESS (msymbol); | |
209 | reg->name = xstrdup (name); | |
210 | ||
211 | /* Keep track of the address range for soft registers. */ | |
212 | if (reg->addr < (CORE_ADDR) soft_min_addr) | |
213 | soft_min_addr = reg->addr; | |
214 | if (reg->addr > (CORE_ADDR) soft_max_addr) | |
215 | soft_max_addr = reg->addr; | |
216 | } | |
217 | else | |
218 | { | |
219 | reg->name = 0; | |
220 | reg->addr = 0; | |
221 | } | |
222 | } | |
78073dd8 | 223 | |
82c230c2 SC |
224 | /* Initialize the table of soft register addresses according |
225 | to the symbol table. */ | |
226 | static void | |
227 | m68hc11_initialize_register_info (void) | |
228 | { | |
229 | int i; | |
78073dd8 | 230 | |
82c230c2 SC |
231 | if (soft_reg_initialized) |
232 | return; | |
233 | ||
234 | soft_min_addr = INT_MAX; | |
235 | soft_max_addr = 0; | |
236 | for (i = 0; i < M68HC11_ALL_REGS; i++) | |
237 | { | |
238 | soft_regs[i].name = 0; | |
239 | } | |
240 | ||
241 | m68hc11_get_register_info (&soft_regs[SOFT_FP_REGNUM], "_.frame"); | |
242 | m68hc11_get_register_info (&soft_regs[SOFT_TMP_REGNUM], "_.tmp"); | |
243 | m68hc11_get_register_info (&soft_regs[SOFT_ZS_REGNUM], "_.z"); | |
244 | soft_regs[SOFT_Z_REGNUM] = soft_regs[SOFT_ZS_REGNUM]; | |
245 | m68hc11_get_register_info (&soft_regs[SOFT_XY_REGNUM], "_.xy"); | |
78073dd8 | 246 | |
82c230c2 SC |
247 | for (i = SOFT_D1_REGNUM; i < M68HC11_MAX_SOFT_REGS; i++) |
248 | { | |
249 | char buf[10]; | |
78073dd8 | 250 | |
82c230c2 SC |
251 | sprintf (buf, "_.d%d", i - SOFT_D1_REGNUM + 1); |
252 | m68hc11_get_register_info (&soft_regs[i], buf); | |
253 | } | |
78073dd8 | 254 | |
82c230c2 | 255 | if (soft_regs[SOFT_FP_REGNUM].name == 0) |
8a3fe4f8 AC |
256 | warning (_("No frame soft register found in the symbol table.\n" |
257 | "Stack backtrace will not work.")); | |
82c230c2 SC |
258 | soft_reg_initialized = 1; |
259 | } | |
78073dd8 | 260 | |
82c230c2 SC |
261 | /* Given an address in memory, return the soft register number if |
262 | that address corresponds to a soft register. Returns -1 if not. */ | |
263 | static int | |
264 | m68hc11_which_soft_register (CORE_ADDR addr) | |
265 | { | |
266 | int i; | |
267 | ||
268 | if (addr < soft_min_addr || addr > soft_max_addr) | |
269 | return -1; | |
270 | ||
271 | for (i = SOFT_FP_REGNUM; i < M68HC11_ALL_REGS; i++) | |
272 | { | |
273 | if (soft_regs[i].name && soft_regs[i].addr == addr) | |
274 | return i; | |
275 | } | |
276 | return -1; | |
277 | } | |
78073dd8 | 278 | |
82c230c2 SC |
279 | /* Fetch a pseudo register. The 68hc11 soft registers are treated like |
280 | pseudo registers. They are located in memory. Translate the register | |
281 | fetch into a memory read. */ | |
46ce284d AC |
282 | static void |
283 | m68hc11_pseudo_register_read (struct gdbarch *gdbarch, | |
284 | struct regcache *regcache, | |
ff1e98b9 | 285 | int regno, gdb_byte *buf) |
82c230c2 | 286 | { |
548bcbec SC |
287 | /* The PC is a pseudo reg only for 68HC12 with the memory bank |
288 | addressing mode. */ | |
289 | if (regno == M68HC12_HARD_PC_REGNUM) | |
290 | { | |
4db73d49 | 291 | ULONGEST pc; |
548bcbec | 292 | const int regsize = TYPE_LENGTH (builtin_type_uint32); |
548bcbec | 293 | |
4db73d49 | 294 | regcache_cooked_read_unsigned (regcache, HARD_PC_REGNUM, &pc); |
548bcbec SC |
295 | if (pc >= 0x8000 && pc < 0xc000) |
296 | { | |
4db73d49 SC |
297 | ULONGEST page; |
298 | ||
299 | regcache_cooked_read_unsigned (regcache, HARD_PAGE_REGNUM, &page); | |
548bcbec SC |
300 | pc -= 0x8000; |
301 | pc += (page << 14); | |
302 | pc += 0x1000000; | |
303 | } | |
304 | store_unsigned_integer (buf, regsize, pc); | |
305 | return; | |
306 | } | |
307 | ||
82c230c2 SC |
308 | m68hc11_initialize_register_info (); |
309 | ||
310 | /* Fetch a soft register: translate into a memory read. */ | |
311 | if (soft_regs[regno].name) | |
312 | { | |
313 | target_read_memory (soft_regs[regno].addr, buf, 2); | |
314 | } | |
315 | else | |
316 | { | |
317 | memset (buf, 0, 2); | |
318 | } | |
82c230c2 | 319 | } |
78073dd8 | 320 | |
82c230c2 SC |
321 | /* Store a pseudo register. Translate the register store |
322 | into a memory write. */ | |
323 | static void | |
46ce284d AC |
324 | m68hc11_pseudo_register_write (struct gdbarch *gdbarch, |
325 | struct regcache *regcache, | |
ff1e98b9 | 326 | int regno, const gdb_byte *buf) |
82c230c2 | 327 | { |
548bcbec SC |
328 | /* The PC is a pseudo reg only for 68HC12 with the memory bank |
329 | addressing mode. */ | |
330 | if (regno == M68HC12_HARD_PC_REGNUM) | |
331 | { | |
332 | const int regsize = TYPE_LENGTH (builtin_type_uint32); | |
333 | char *tmp = alloca (regsize); | |
334 | CORE_ADDR pc; | |
335 | ||
336 | memcpy (tmp, buf, regsize); | |
337 | pc = extract_unsigned_integer (tmp, regsize); | |
338 | if (pc >= 0x1000000) | |
339 | { | |
340 | pc -= 0x1000000; | |
4db73d49 SC |
341 | regcache_cooked_write_unsigned (regcache, HARD_PAGE_REGNUM, |
342 | (pc >> 14) & 0x0ff); | |
548bcbec | 343 | pc &= 0x03fff; |
4db73d49 SC |
344 | regcache_cooked_write_unsigned (regcache, HARD_PC_REGNUM, |
345 | pc + 0x8000); | |
548bcbec SC |
346 | } |
347 | else | |
4db73d49 | 348 | regcache_cooked_write_unsigned (regcache, HARD_PC_REGNUM, pc); |
548bcbec SC |
349 | return; |
350 | } | |
351 | ||
82c230c2 | 352 | m68hc11_initialize_register_info (); |
78073dd8 | 353 | |
82c230c2 SC |
354 | /* Store a soft register: translate into a memory write. */ |
355 | if (soft_regs[regno].name) | |
356 | { | |
46ce284d AC |
357 | const int regsize = 2; |
358 | char *tmp = alloca (regsize); | |
359 | memcpy (tmp, buf, regsize); | |
360 | target_write_memory (soft_regs[regno].addr, tmp, regsize); | |
82c230c2 SC |
361 | } |
362 | } | |
78073dd8 | 363 | |
fa88f677 | 364 | static const char * |
d93859e2 | 365 | m68hc11_register_name (struct gdbarch *gdbarch, int reg_nr) |
78073dd8 | 366 | { |
be8626e0 | 367 | if (reg_nr == M68HC12_HARD_PC_REGNUM && USE_PAGE_REGISTER (gdbarch)) |
548bcbec | 368 | return "pc"; |
be8626e0 | 369 | if (reg_nr == HARD_PC_REGNUM && USE_PAGE_REGISTER (gdbarch)) |
548bcbec SC |
370 | return "ppc"; |
371 | ||
82c230c2 SC |
372 | if (reg_nr < 0) |
373 | return NULL; | |
374 | if (reg_nr >= M68HC11_ALL_REGS) | |
375 | return NULL; | |
376 | ||
65760afb SC |
377 | m68hc11_initialize_register_info (); |
378 | ||
82c230c2 SC |
379 | /* If we don't know the address of a soft register, pretend it |
380 | does not exist. */ | |
381 | if (reg_nr > M68HC11_LAST_HARD_REG && soft_regs[reg_nr].name == 0) | |
382 | return NULL; | |
383 | return m68hc11_register_names[reg_nr]; | |
384 | } | |
78073dd8 | 385 | |
f4f9705a | 386 | static const unsigned char * |
67d57894 MD |
387 | m68hc11_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, |
388 | int *lenptr) | |
78073dd8 | 389 | { |
82c230c2 | 390 | static unsigned char breakpoint[] = {0x0}; |
67d57894 | 391 | |
82c230c2 SC |
392 | *lenptr = sizeof (breakpoint); |
393 | return breakpoint; | |
78073dd8 AC |
394 | } |
395 | ||
908f682f SC |
396 | \f |
397 | /* 68HC11 & 68HC12 prologue analysis. | |
398 | ||
399 | */ | |
400 | #define MAX_CODES 12 | |
401 | ||
402 | /* 68HC11 opcodes. */ | |
403 | #undef M6811_OP_PAGE2 | |
b94a41a1 SC |
404 | #define M6811_OP_PAGE2 (0x18) |
405 | #define M6811_OP_LDX (0xde) | |
406 | #define M6811_OP_LDX_EXT (0xfe) | |
407 | #define M6811_OP_PSHX (0x3c) | |
408 | #define M6811_OP_STS (0x9f) | |
409 | #define M6811_OP_STS_EXT (0xbf) | |
410 | #define M6811_OP_TSX (0x30) | |
411 | #define M6811_OP_XGDX (0x8f) | |
412 | #define M6811_OP_ADDD (0xc3) | |
413 | #define M6811_OP_TXS (0x35) | |
414 | #define M6811_OP_DES (0x34) | |
908f682f SC |
415 | |
416 | /* 68HC12 opcodes. */ | |
b94a41a1 SC |
417 | #define M6812_OP_PAGE2 (0x18) |
418 | #define M6812_OP_MOVW (0x01) | |
419 | #define M6812_PB_PSHW (0xae) | |
420 | #define M6812_OP_STS (0x5f) | |
421 | #define M6812_OP_STS_EXT (0x7f) | |
422 | #define M6812_OP_LEAS (0x1b) | |
423 | #define M6812_OP_PSHX (0x34) | |
424 | #define M6812_OP_PSHY (0x35) | |
908f682f SC |
425 | |
426 | /* Operand extraction. */ | |
427 | #define OP_DIRECT (0x100) /* 8-byte direct addressing. */ | |
428 | #define OP_IMM_LOW (0x200) /* Low part of 16-bit constant/address. */ | |
429 | #define OP_IMM_HIGH (0x300) /* High part of 16-bit constant/address. */ | |
430 | #define OP_PBYTE (0x400) /* 68HC12 indexed operand. */ | |
431 | ||
432 | /* Identification of the sequence. */ | |
433 | enum m6811_seq_type | |
434 | { | |
435 | P_LAST = 0, | |
436 | P_SAVE_REG, /* Save a register on the stack. */ | |
437 | P_SET_FRAME, /* Setup the frame pointer. */ | |
438 | P_LOCAL_1, /* Allocate 1 byte for locals. */ | |
439 | P_LOCAL_2, /* Allocate 2 bytes for locals. */ | |
440 | P_LOCAL_N /* Allocate N bytes for locals. */ | |
441 | }; | |
442 | ||
443 | struct insn_sequence { | |
444 | enum m6811_seq_type type; | |
445 | unsigned length; | |
446 | unsigned short code[MAX_CODES]; | |
447 | }; | |
448 | ||
449 | /* Sequence of instructions in the 68HC11 function prologue. */ | |
450 | static struct insn_sequence m6811_prologue[] = { | |
451 | /* Sequences to save a soft-register. */ | |
452 | { P_SAVE_REG, 3, { M6811_OP_LDX, OP_DIRECT, | |
453 | M6811_OP_PSHX } }, | |
454 | { P_SAVE_REG, 5, { M6811_OP_PAGE2, M6811_OP_LDX, OP_DIRECT, | |
455 | M6811_OP_PAGE2, M6811_OP_PSHX } }, | |
b94a41a1 SC |
456 | { P_SAVE_REG, 4, { M6811_OP_LDX_EXT, OP_IMM_HIGH, OP_IMM_LOW, |
457 | M6811_OP_PSHX } }, | |
458 | { P_SAVE_REG, 6, { M6811_OP_PAGE2, M6811_OP_LDX_EXT, OP_IMM_HIGH, OP_IMM_LOW, | |
459 | M6811_OP_PAGE2, M6811_OP_PSHX } }, | |
908f682f SC |
460 | |
461 | /* Sequences to allocate local variables. */ | |
462 | { P_LOCAL_N, 7, { M6811_OP_TSX, | |
463 | M6811_OP_XGDX, | |
464 | M6811_OP_ADDD, OP_IMM_HIGH, OP_IMM_LOW, | |
465 | M6811_OP_XGDX, | |
466 | M6811_OP_TXS } }, | |
467 | { P_LOCAL_N, 11, { M6811_OP_PAGE2, M6811_OP_TSX, | |
468 | M6811_OP_PAGE2, M6811_OP_XGDX, | |
469 | M6811_OP_ADDD, OP_IMM_HIGH, OP_IMM_LOW, | |
470 | M6811_OP_PAGE2, M6811_OP_XGDX, | |
471 | M6811_OP_PAGE2, M6811_OP_TXS } }, | |
472 | { P_LOCAL_1, 1, { M6811_OP_DES } }, | |
473 | { P_LOCAL_2, 1, { M6811_OP_PSHX } }, | |
474 | { P_LOCAL_2, 2, { M6811_OP_PAGE2, M6811_OP_PSHX } }, | |
475 | ||
476 | /* Initialize the frame pointer. */ | |
477 | { P_SET_FRAME, 2, { M6811_OP_STS, OP_DIRECT } }, | |
b94a41a1 | 478 | { P_SET_FRAME, 3, { M6811_OP_STS_EXT, OP_IMM_HIGH, OP_IMM_LOW } }, |
908f682f SC |
479 | { P_LAST, 0, { 0 } } |
480 | }; | |
481 | ||
482 | ||
483 | /* Sequence of instructions in the 68HC12 function prologue. */ | |
484 | static struct insn_sequence m6812_prologue[] = { | |
485 | { P_SAVE_REG, 5, { M6812_OP_PAGE2, M6812_OP_MOVW, M6812_PB_PSHW, | |
486 | OP_IMM_HIGH, OP_IMM_LOW } }, | |
b94a41a1 SC |
487 | { P_SET_FRAME, 2, { M6812_OP_STS, OP_DIRECT } }, |
488 | { P_SET_FRAME, 3, { M6812_OP_STS_EXT, OP_IMM_HIGH, OP_IMM_LOW } }, | |
908f682f | 489 | { P_LOCAL_N, 2, { M6812_OP_LEAS, OP_PBYTE } }, |
ffe1f3ee SC |
490 | { P_LOCAL_2, 1, { M6812_OP_PSHX } }, |
491 | { P_LOCAL_2, 1, { M6812_OP_PSHY } }, | |
908f682f SC |
492 | { P_LAST, 0 } |
493 | }; | |
494 | ||
495 | ||
496 | /* Analyze the sequence of instructions starting at the given address. | |
497 | Returns a pointer to the sequence when it is recognized and | |
c8a7f6ac | 498 | the optional value (constant/address) associated with it. */ |
908f682f | 499 | static struct insn_sequence * |
c8a7f6ac | 500 | m68hc11_analyze_instruction (struct insn_sequence *seq, CORE_ADDR pc, |
908f682f SC |
501 | CORE_ADDR *val) |
502 | { | |
503 | unsigned char buffer[MAX_CODES]; | |
504 | unsigned bufsize; | |
505 | unsigned j; | |
506 | CORE_ADDR cur_val; | |
507 | short v = 0; | |
508 | ||
509 | bufsize = 0; | |
510 | for (; seq->type != P_LAST; seq++) | |
511 | { | |
512 | cur_val = 0; | |
513 | for (j = 0; j < seq->length; j++) | |
514 | { | |
515 | if (bufsize < j + 1) | |
516 | { | |
c8a7f6ac | 517 | buffer[bufsize] = read_memory_unsigned_integer (pc + bufsize, |
908f682f SC |
518 | 1); |
519 | bufsize++; | |
520 | } | |
521 | /* Continue while we match the opcode. */ | |
522 | if (seq->code[j] == buffer[j]) | |
523 | continue; | |
524 | ||
525 | if ((seq->code[j] & 0xf00) == 0) | |
526 | break; | |
527 | ||
528 | /* Extract a sequence parameter (address or constant). */ | |
529 | switch (seq->code[j]) | |
530 | { | |
531 | case OP_DIRECT: | |
532 | cur_val = (CORE_ADDR) buffer[j]; | |
533 | break; | |
534 | ||
535 | case OP_IMM_HIGH: | |
536 | cur_val = cur_val & 0x0ff; | |
537 | cur_val |= (buffer[j] << 8); | |
538 | break; | |
539 | ||
540 | case OP_IMM_LOW: | |
541 | cur_val &= 0x0ff00; | |
542 | cur_val |= buffer[j]; | |
543 | break; | |
544 | ||
545 | case OP_PBYTE: | |
546 | if ((buffer[j] & 0xE0) == 0x80) | |
547 | { | |
548 | v = buffer[j] & 0x1f; | |
549 | if (v & 0x10) | |
550 | v |= 0xfff0; | |
551 | } | |
552 | else if ((buffer[j] & 0xfe) == 0xf0) | |
553 | { | |
c8a7f6ac | 554 | v = read_memory_unsigned_integer (pc + j + 1, 1); |
908f682f SC |
555 | if (buffer[j] & 1) |
556 | v |= 0xff00; | |
557 | } | |
558 | else if (buffer[j] == 0xf2) | |
559 | { | |
c8a7f6ac | 560 | v = read_memory_unsigned_integer (pc + j + 1, 2); |
908f682f SC |
561 | } |
562 | cur_val = v; | |
563 | break; | |
564 | } | |
565 | } | |
566 | ||
567 | /* We have a full match. */ | |
568 | if (j == seq->length) | |
569 | { | |
570 | *val = cur_val; | |
908f682f SC |
571 | return seq; |
572 | } | |
573 | } | |
574 | return 0; | |
575 | } | |
576 | ||
7df11f59 SC |
577 | /* Return the instruction that the function at the PC is using. */ |
578 | static enum insn_return_kind | |
579 | m68hc11_get_return_insn (CORE_ADDR pc) | |
580 | { | |
581 | struct minimal_symbol *sym; | |
582 | ||
583 | /* A flag indicating that this is a STO_M68HC12_FAR or STO_M68HC12_INTERRUPT | |
584 | function is stored by elfread.c in the high bit of the info field. | |
585 | Use this to decide which instruction the function uses to return. */ | |
586 | sym = lookup_minimal_symbol_by_pc (pc); | |
587 | if (sym == 0) | |
588 | return RETURN_RTS; | |
589 | ||
590 | if (MSYMBOL_IS_RTC (sym)) | |
591 | return RETURN_RTC; | |
592 | else if (MSYMBOL_IS_RTI (sym)) | |
593 | return RETURN_RTI; | |
594 | else | |
595 | return RETURN_RTS; | |
596 | } | |
597 | ||
78073dd8 AC |
598 | /* Analyze the function prologue to find some information |
599 | about the function: | |
600 | - the PC of the first line (for m68hc11_skip_prologue) | |
601 | - the offset of the previous frame saved address (from current frame) | |
602 | - the soft registers which are pushed. */ | |
1ea653ae | 603 | static CORE_ADDR |
be8626e0 MD |
604 | m68hc11_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, |
605 | CORE_ADDR current_pc, struct m68hc11_unwind_cache *info) | |
78073dd8 | 606 | { |
1ea653ae | 607 | LONGEST save_addr; |
78073dd8 | 608 | CORE_ADDR func_end; |
78073dd8 AC |
609 | int size; |
610 | int found_frame_point; | |
82c230c2 | 611 | int saved_reg; |
908f682f SC |
612 | int done = 0; |
613 | struct insn_sequence *seq_table; | |
1ea653ae SC |
614 | |
615 | info->size = 0; | |
616 | info->sp_offset = 0; | |
617 | if (pc >= current_pc) | |
618 | return current_pc; | |
619 | ||
78073dd8 AC |
620 | size = 0; |
621 | ||
82c230c2 | 622 | m68hc11_initialize_register_info (); |
1ea653ae | 623 | if (pc == 0) |
78073dd8 | 624 | { |
1ea653ae SC |
625 | info->size = 0; |
626 | return pc; | |
78073dd8 AC |
627 | } |
628 | ||
be8626e0 | 629 | seq_table = gdbarch_tdep (gdbarch)->prologue; |
908f682f | 630 | |
78073dd8 AC |
631 | /* The 68hc11 stack is as follows: |
632 | ||
633 | ||
634 | | | | |
635 | +-----------+ | |
636 | | | | |
637 | | args | | |
638 | | | | |
639 | +-----------+ | |
640 | | PC-return | | |
641 | +-----------+ | |
642 | | Old frame | | |
643 | +-----------+ | |
644 | | | | |
645 | | Locals | | |
646 | | | | |
647 | +-----------+ <--- current frame | |
648 | | | | |
649 | ||
650 | With most processors (like 68K) the previous frame can be computed | |
651 | easily because it is always at a fixed offset (see link/unlink). | |
652 | That is, locals are accessed with negative offsets, arguments are | |
653 | accessed with positive ones. Since 68hc11 only supports offsets | |
654 | in the range [0..255], the frame is defined at the bottom of | |
655 | locals (see picture). | |
656 | ||
657 | The purpose of the analysis made here is to find out the size | |
658 | of locals in this function. An alternative to this is to use | |
659 | DWARF2 info. This would be better but I don't know how to | |
660 | access dwarf2 debug from this function. | |
661 | ||
662 | Walk from the function entry point to the point where we save | |
663 | the frame. While walking instructions, compute the size of bytes | |
664 | which are pushed. This gives us the index to access the previous | |
665 | frame. | |
666 | ||
667 | We limit the search to 128 bytes so that the algorithm is bounded | |
668 | in case of random and wrong code. We also stop and abort if | |
669 | we find an instruction which is not supposed to appear in the | |
670 | prologue (as generated by gcc 2.95, 2.96). | |
671 | */ | |
78073dd8 | 672 | func_end = pc + 128; |
78073dd8 | 673 | found_frame_point = 0; |
1ea653ae SC |
674 | info->size = 0; |
675 | save_addr = 0; | |
908f682f | 676 | while (!done && pc + 2 < func_end) |
78073dd8 | 677 | { |
908f682f SC |
678 | struct insn_sequence *seq; |
679 | CORE_ADDR val; | |
1ea653ae | 680 | |
c8a7f6ac | 681 | seq = m68hc11_analyze_instruction (seq_table, pc, &val); |
908f682f SC |
682 | if (seq == 0) |
683 | break; | |
78073dd8 | 684 | |
c8a7f6ac SC |
685 | /* If we are within the instruction group, we can't advance the |
686 | pc nor the stack offset. Otherwise the caller's stack computed | |
687 | from the current stack can be wrong. */ | |
688 | if (pc + seq->length > current_pc) | |
689 | break; | |
690 | ||
691 | pc = pc + seq->length; | |
908f682f | 692 | if (seq->type == P_SAVE_REG) |
78073dd8 | 693 | { |
908f682f SC |
694 | if (found_frame_point) |
695 | { | |
696 | saved_reg = m68hc11_which_soft_register (val); | |
697 | if (saved_reg < 0) | |
698 | break; | |
78073dd8 | 699 | |
908f682f | 700 | save_addr -= 2; |
ff1e98b9 SC |
701 | if (info->saved_regs) |
702 | info->saved_regs[saved_reg].addr = save_addr; | |
908f682f SC |
703 | } |
704 | else | |
705 | { | |
706 | size += 2; | |
707 | } | |
78073dd8 | 708 | } |
908f682f | 709 | else if (seq->type == P_SET_FRAME) |
78073dd8 AC |
710 | { |
711 | found_frame_point = 1; | |
1ea653ae | 712 | info->size = size; |
78073dd8 | 713 | } |
908f682f | 714 | else if (seq->type == P_LOCAL_1) |
78073dd8 | 715 | { |
6148eca7 SC |
716 | size += 1; |
717 | } | |
908f682f | 718 | else if (seq->type == P_LOCAL_2) |
78073dd8 | 719 | { |
908f682f | 720 | size += 2; |
78073dd8 | 721 | } |
908f682f | 722 | else if (seq->type == P_LOCAL_N) |
78073dd8 | 723 | { |
908f682f SC |
724 | /* Stack pointer is decremented for the allocation. */ |
725 | if (val & 0x8000) | |
726 | size -= (int) (val) | 0xffff0000; | |
727 | else | |
728 | size -= val; | |
78073dd8 AC |
729 | } |
730 | } | |
1ea653ae SC |
731 | if (found_frame_point == 0) |
732 | info->sp_offset = size; | |
733 | else | |
734 | info->sp_offset = -1; | |
735 | return pc; | |
78073dd8 AC |
736 | } |
737 | ||
82c230c2 | 738 | static CORE_ADDR |
6093d2eb | 739 | m68hc11_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
78073dd8 AC |
740 | { |
741 | CORE_ADDR func_addr, func_end; | |
742 | struct symtab_and_line sal; | |
1ea653ae | 743 | struct m68hc11_unwind_cache tmp_cache = { 0 }; |
78073dd8 | 744 | |
82c230c2 SC |
745 | /* If we have line debugging information, then the end of the |
746 | prologue should be the first assembly instruction of the | |
78073dd8 AC |
747 | first source line. */ |
748 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
749 | { | |
750 | sal = find_pc_line (func_addr, 0); | |
751 | if (sal.end && sal.end < func_end) | |
752 | return sal.end; | |
753 | } | |
754 | ||
be8626e0 | 755 | pc = m68hc11_scan_prologue (gdbarch, pc, (CORE_ADDR) -1, &tmp_cache); |
78073dd8 AC |
756 | return pc; |
757 | } | |
758 | ||
1ea653ae SC |
759 | static CORE_ADDR |
760 | m68hc11_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
761 | { | |
762 | ULONGEST pc; | |
763 | ||
11411de3 | 764 | pc = frame_unwind_register_unsigned (next_frame, gdbarch_pc_regnum (gdbarch)); |
1ea653ae SC |
765 | return pc; |
766 | } | |
767 | ||
768 | /* Put here the code to store, into fi->saved_regs, the addresses of | |
769 | the saved registers of frame described by FRAME_INFO. This | |
770 | includes special registers such as pc and fp saved in special ways | |
771 | in the stack frame. sp is even more special: the address we return | |
772 | for it IS the sp for the next frame. */ | |
773 | ||
63807e1d | 774 | static struct m68hc11_unwind_cache * |
94afd7a6 | 775 | m68hc11_frame_unwind_cache (struct frame_info *this_frame, |
1ea653ae SC |
776 | void **this_prologue_cache) |
777 | { | |
94afd7a6 | 778 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1ea653ae SC |
779 | ULONGEST prev_sp; |
780 | ULONGEST this_base; | |
781 | struct m68hc11_unwind_cache *info; | |
782 | CORE_ADDR current_pc; | |
783 | int i; | |
784 | ||
785 | if ((*this_prologue_cache)) | |
786 | return (*this_prologue_cache); | |
787 | ||
788 | info = FRAME_OBSTACK_ZALLOC (struct m68hc11_unwind_cache); | |
789 | (*this_prologue_cache) = info; | |
94afd7a6 | 790 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
1ea653ae | 791 | |
94afd7a6 | 792 | info->pc = get_frame_func (this_frame); |
1ea653ae SC |
793 | |
794 | info->size = 0; | |
795 | info->return_kind = m68hc11_get_return_insn (info->pc); | |
796 | ||
797 | /* The SP was moved to the FP. This indicates that a new frame | |
798 | was created. Get THIS frame's FP value by unwinding it from | |
799 | the next frame. */ | |
94afd7a6 | 800 | this_base = get_frame_register_unsigned (this_frame, SOFT_FP_REGNUM); |
1ea653ae SC |
801 | if (this_base == 0) |
802 | { | |
803 | info->base = 0; | |
804 | return info; | |
805 | } | |
806 | ||
94afd7a6 | 807 | current_pc = get_frame_pc (this_frame); |
1ea653ae | 808 | if (info->pc != 0) |
be8626e0 | 809 | m68hc11_scan_prologue (gdbarch, info->pc, current_pc, info); |
1ea653ae SC |
810 | |
811 | info->saved_regs[HARD_PC_REGNUM].addr = info->size; | |
812 | ||
813 | if (info->sp_offset != (CORE_ADDR) -1) | |
814 | { | |
815 | info->saved_regs[HARD_PC_REGNUM].addr = info->sp_offset; | |
94afd7a6 | 816 | this_base = get_frame_register_unsigned (this_frame, HARD_SP_REGNUM); |
1ea653ae | 817 | prev_sp = this_base + info->sp_offset + 2; |
be8626e0 | 818 | this_base += STACK_CORRECTION (gdbarch); |
1ea653ae SC |
819 | } |
820 | else | |
821 | { | |
822 | /* The FP points at the last saved register. Adjust the FP back | |
823 | to before the first saved register giving the SP. */ | |
824 | prev_sp = this_base + info->size + 2; | |
825 | ||
be8626e0 | 826 | this_base += STACK_CORRECTION (gdbarch); |
1ea653ae SC |
827 | if (soft_regs[SOFT_FP_REGNUM].name) |
828 | info->saved_regs[SOFT_FP_REGNUM].addr = info->size - 2; | |
829 | } | |
830 | ||
831 | if (info->return_kind == RETURN_RTC) | |
832 | { | |
833 | prev_sp += 1; | |
834 | info->saved_regs[HARD_PAGE_REGNUM].addr = info->size; | |
835 | info->saved_regs[HARD_PC_REGNUM].addr = info->size + 1; | |
836 | } | |
837 | else if (info->return_kind == RETURN_RTI) | |
838 | { | |
839 | prev_sp += 7; | |
840 | info->saved_regs[HARD_CCR_REGNUM].addr = info->size; | |
841 | info->saved_regs[HARD_D_REGNUM].addr = info->size + 1; | |
842 | info->saved_regs[HARD_X_REGNUM].addr = info->size + 3; | |
843 | info->saved_regs[HARD_Y_REGNUM].addr = info->size + 5; | |
844 | info->saved_regs[HARD_PC_REGNUM].addr = info->size + 7; | |
845 | } | |
846 | ||
847 | /* Add 1 here to adjust for the post-decrement nature of the push | |
848 | instruction.*/ | |
849 | info->prev_sp = prev_sp; | |
850 | ||
851 | info->base = this_base; | |
852 | ||
853 | /* Adjust all the saved registers so that they contain addresses and not | |
854 | offsets. */ | |
f57d151a | 855 | for (i = 0; |
be8626e0 MD |
856 | i < gdbarch_num_regs (gdbarch) |
857 | + gdbarch_num_pseudo_regs (gdbarch) - 1; | |
f57d151a | 858 | i++) |
1ea653ae SC |
859 | if (trad_frame_addr_p (info->saved_regs, i)) |
860 | { | |
861 | info->saved_regs[i].addr += this_base; | |
862 | } | |
863 | ||
864 | /* The previous frame's SP needed to be computed. Save the computed | |
865 | value. */ | |
866 | trad_frame_set_value (info->saved_regs, HARD_SP_REGNUM, info->prev_sp); | |
867 | ||
868 | return info; | |
869 | } | |
870 | ||
871 | /* Given a GDB frame, determine the address of the calling function's | |
872 | frame. This will be used to create a new GDB frame struct. */ | |
873 | ||
874 | static void | |
94afd7a6 | 875 | m68hc11_frame_this_id (struct frame_info *this_frame, |
1ea653ae SC |
876 | void **this_prologue_cache, |
877 | struct frame_id *this_id) | |
878 | { | |
879 | struct m68hc11_unwind_cache *info | |
94afd7a6 | 880 | = m68hc11_frame_unwind_cache (this_frame, this_prologue_cache); |
1ea653ae SC |
881 | CORE_ADDR base; |
882 | CORE_ADDR func; | |
883 | struct frame_id id; | |
884 | ||
885 | /* The FUNC is easy. */ | |
94afd7a6 | 886 | func = get_frame_func (this_frame); |
1ea653ae | 887 | |
1ea653ae SC |
888 | /* Hopefully the prologue analysis either correctly determined the |
889 | frame's base (which is the SP from the previous frame), or set | |
890 | that base to "NULL". */ | |
891 | base = info->prev_sp; | |
892 | if (base == 0) | |
893 | return; | |
894 | ||
895 | id = frame_id_build (base, func); | |
1ea653ae SC |
896 | (*this_id) = id; |
897 | } | |
898 | ||
94afd7a6 UW |
899 | static struct value * |
900 | m68hc11_frame_prev_register (struct frame_info *this_frame, | |
901 | void **this_prologue_cache, int regnum) | |
1ea653ae | 902 | { |
94afd7a6 | 903 | struct value *value; |
1ea653ae | 904 | struct m68hc11_unwind_cache *info |
94afd7a6 | 905 | = m68hc11_frame_unwind_cache (this_frame, this_prologue_cache); |
1ea653ae | 906 | |
94afd7a6 | 907 | value = trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
1ea653ae | 908 | |
94afd7a6 UW |
909 | /* Take into account the 68HC12 specific call (PC + page). */ |
910 | if (regnum == HARD_PC_REGNUM | |
911 | && info->return_kind == RETURN_RTC | |
912 | && USE_PAGE_REGISTER (get_frame_arch (this_frame))) | |
1ea653ae | 913 | { |
94afd7a6 UW |
914 | CORE_ADDR pc = value_as_long (value); |
915 | if (pc >= 0x08000 && pc < 0x0c000) | |
1ea653ae | 916 | { |
1ea653ae SC |
917 | CORE_ADDR page; |
918 | ||
94afd7a6 UW |
919 | release_value (value); |
920 | value_free (value); | |
921 | ||
922 | value = trad_frame_get_prev_register (this_frame, info->saved_regs, | |
923 | HARD_PAGE_REGNUM); | |
924 | page = value_as_long (value); | |
925 | release_value (value); | |
926 | value_free (value); | |
927 | ||
928 | pc -= 0x08000; | |
929 | pc += ((page & 0x0ff) << 14); | |
930 | pc += 0x1000000; | |
931 | ||
932 | return frame_unwind_got_constant (this_frame, regnum, pc); | |
1ea653ae SC |
933 | } |
934 | } | |
94afd7a6 UW |
935 | |
936 | return value; | |
1ea653ae SC |
937 | } |
938 | ||
939 | static const struct frame_unwind m68hc11_frame_unwind = { | |
940 | NORMAL_FRAME, | |
941 | m68hc11_frame_this_id, | |
94afd7a6 UW |
942 | m68hc11_frame_prev_register, |
943 | NULL, | |
944 | default_frame_sniffer | |
1ea653ae SC |
945 | }; |
946 | ||
1ea653ae | 947 | static CORE_ADDR |
94afd7a6 | 948 | m68hc11_frame_base_address (struct frame_info *this_frame, void **this_cache) |
1ea653ae SC |
949 | { |
950 | struct m68hc11_unwind_cache *info | |
94afd7a6 | 951 | = m68hc11_frame_unwind_cache (this_frame, this_cache); |
1ea653ae SC |
952 | |
953 | return info->base; | |
954 | } | |
955 | ||
956 | static CORE_ADDR | |
94afd7a6 | 957 | m68hc11_frame_args_address (struct frame_info *this_frame, void **this_cache) |
1ea653ae SC |
958 | { |
959 | CORE_ADDR addr; | |
960 | struct m68hc11_unwind_cache *info | |
94afd7a6 | 961 | = m68hc11_frame_unwind_cache (this_frame, this_cache); |
1ea653ae SC |
962 | |
963 | addr = info->base + info->size; | |
964 | if (info->return_kind == RETURN_RTC) | |
965 | addr += 1; | |
966 | else if (info->return_kind == RETURN_RTI) | |
967 | addr += 7; | |
968 | ||
969 | return addr; | |
970 | } | |
971 | ||
972 | static const struct frame_base m68hc11_frame_base = { | |
973 | &m68hc11_frame_unwind, | |
974 | m68hc11_frame_base_address, | |
975 | m68hc11_frame_base_address, | |
976 | m68hc11_frame_args_address | |
977 | }; | |
978 | ||
979 | static CORE_ADDR | |
980 | m68hc11_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
981 | { | |
982 | ULONGEST sp; | |
11411de3 | 983 | sp = frame_unwind_register_unsigned (next_frame, HARD_SP_REGNUM); |
1ea653ae SC |
984 | return sp; |
985 | } | |
986 | ||
94afd7a6 UW |
987 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy |
988 | frame. The frame ID's base needs to match the TOS value saved by | |
989 | save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */ | |
1ea653ae SC |
990 | |
991 | static struct frame_id | |
94afd7a6 | 992 | m68hc11_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
1ea653ae SC |
993 | { |
994 | ULONGEST tos; | |
94afd7a6 | 995 | CORE_ADDR pc = get_frame_pc (this_frame); |
1ea653ae | 996 | |
94afd7a6 | 997 | tos = get_frame_register_unsigned (this_frame, SOFT_FP_REGNUM); |
1ea653ae SC |
998 | tos += 2; |
999 | return frame_id_build (tos, pc); | |
1000 | } | |
78073dd8 | 1001 | |
e286caf2 SC |
1002 | \f |
1003 | /* Get and print the register from the given frame. */ | |
78073dd8 | 1004 | static void |
e286caf2 SC |
1005 | m68hc11_print_register (struct gdbarch *gdbarch, struct ui_file *file, |
1006 | struct frame_info *frame, int regno) | |
78073dd8 | 1007 | { |
e286caf2 SC |
1008 | LONGEST rval; |
1009 | ||
1010 | if (regno == HARD_PC_REGNUM || regno == HARD_SP_REGNUM | |
1011 | || regno == SOFT_FP_REGNUM || regno == M68HC12_HARD_PC_REGNUM) | |
7f5f525d | 1012 | rval = get_frame_register_unsigned (frame, regno); |
e286caf2 | 1013 | else |
7f5f525d | 1014 | rval = get_frame_register_signed (frame, regno); |
e286caf2 SC |
1015 | |
1016 | if (regno == HARD_A_REGNUM || regno == HARD_B_REGNUM | |
1017 | || regno == HARD_CCR_REGNUM || regno == HARD_PAGE_REGNUM) | |
7df11f59 | 1018 | { |
e286caf2 SC |
1019 | fprintf_filtered (file, "0x%02x ", (unsigned char) rval); |
1020 | if (regno != HARD_CCR_REGNUM) | |
1021 | print_longest (file, 'd', 1, rval); | |
7df11f59 | 1022 | } |
e286caf2 SC |
1023 | else |
1024 | { | |
1025 | if (regno == HARD_PC_REGNUM && gdbarch_tdep (gdbarch)->use_page_register) | |
1026 | { | |
1027 | ULONGEST page; | |
7df11f59 | 1028 | |
7f5f525d | 1029 | page = get_frame_register_unsigned (frame, HARD_PAGE_REGNUM); |
e286caf2 SC |
1030 | fprintf_filtered (file, "0x%02x:%04x ", (unsigned) page, |
1031 | (unsigned) rval); | |
1032 | } | |
1033 | else | |
1034 | { | |
1035 | fprintf_filtered (file, "0x%04x ", (unsigned) rval); | |
1036 | if (regno != HARD_PC_REGNUM && regno != HARD_SP_REGNUM | |
1037 | && regno != SOFT_FP_REGNUM && regno != M68HC12_HARD_PC_REGNUM) | |
1038 | print_longest (file, 'd', 1, rval); | |
1039 | } | |
1040 | } | |
1041 | ||
1042 | if (regno == HARD_CCR_REGNUM) | |
78073dd8 | 1043 | { |
e286caf2 SC |
1044 | /* CCR register */ |
1045 | int C, Z, N, V; | |
1046 | unsigned char l = rval & 0xff; | |
1047 | ||
1048 | fprintf_filtered (file, "%c%c%c%c%c%c%c%c ", | |
1049 | l & M6811_S_BIT ? 'S' : '-', | |
1050 | l & M6811_X_BIT ? 'X' : '-', | |
1051 | l & M6811_H_BIT ? 'H' : '-', | |
1052 | l & M6811_I_BIT ? 'I' : '-', | |
1053 | l & M6811_N_BIT ? 'N' : '-', | |
1054 | l & M6811_Z_BIT ? 'Z' : '-', | |
1055 | l & M6811_V_BIT ? 'V' : '-', | |
1056 | l & M6811_C_BIT ? 'C' : '-'); | |
1057 | N = (l & M6811_N_BIT) != 0; | |
1058 | Z = (l & M6811_Z_BIT) != 0; | |
1059 | V = (l & M6811_V_BIT) != 0; | |
1060 | C = (l & M6811_C_BIT) != 0; | |
1061 | ||
1062 | /* Print flags following the h8300 */ | |
1063 | if ((C | Z) == 0) | |
1064 | fprintf_filtered (file, "u> "); | |
1065 | else if ((C | Z) == 1) | |
1066 | fprintf_filtered (file, "u<= "); | |
1067 | else if (C == 0) | |
1068 | fprintf_filtered (file, "u< "); | |
1069 | ||
1070 | if (Z == 0) | |
1071 | fprintf_filtered (file, "!= "); | |
1072 | else | |
1073 | fprintf_filtered (file, "== "); | |
1074 | ||
1075 | if ((N ^ V) == 0) | |
1076 | fprintf_filtered (file, ">= "); | |
1077 | else | |
1078 | fprintf_filtered (file, "< "); | |
1079 | ||
1080 | if ((Z | (N ^ V)) == 0) | |
1081 | fprintf_filtered (file, "> "); | |
78073dd8 | 1082 | else |
e286caf2 | 1083 | fprintf_filtered (file, "<= "); |
78073dd8 | 1084 | } |
e286caf2 SC |
1085 | } |
1086 | ||
1087 | /* Same as 'info reg' but prints the registers in a different way. */ | |
1088 | static void | |
1089 | m68hc11_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, | |
1090 | struct frame_info *frame, int regno, int cpregs) | |
1091 | { | |
1092 | if (regno >= 0) | |
1093 | { | |
1094 | const char *name = gdbarch_register_name (gdbarch, regno); | |
1095 | ||
1096 | if (!name || !*name) | |
1097 | return; | |
1098 | ||
1099 | fprintf_filtered (file, "%-10s ", name); | |
1100 | m68hc11_print_register (gdbarch, file, frame, regno); | |
1101 | fprintf_filtered (file, "\n"); | |
1102 | } | |
1103 | else | |
1104 | { | |
1105 | int i, nr; | |
1106 | ||
1107 | fprintf_filtered (file, "PC="); | |
1108 | m68hc11_print_register (gdbarch, file, frame, HARD_PC_REGNUM); | |
1109 | ||
1110 | fprintf_filtered (file, " SP="); | |
1111 | m68hc11_print_register (gdbarch, file, frame, HARD_SP_REGNUM); | |
1112 | ||
1113 | fprintf_filtered (file, " FP="); | |
1114 | m68hc11_print_register (gdbarch, file, frame, SOFT_FP_REGNUM); | |
1115 | ||
1116 | fprintf_filtered (file, "\nCCR="); | |
1117 | m68hc11_print_register (gdbarch, file, frame, HARD_CCR_REGNUM); | |
1118 | ||
1119 | fprintf_filtered (file, "\nD="); | |
1120 | m68hc11_print_register (gdbarch, file, frame, HARD_D_REGNUM); | |
1121 | ||
1122 | fprintf_filtered (file, " X="); | |
1123 | m68hc11_print_register (gdbarch, file, frame, HARD_X_REGNUM); | |
1124 | ||
1125 | fprintf_filtered (file, " Y="); | |
1126 | m68hc11_print_register (gdbarch, file, frame, HARD_Y_REGNUM); | |
1127 | ||
1128 | if (gdbarch_tdep (gdbarch)->use_page_register) | |
1129 | { | |
1130 | fprintf_filtered (file, "\nPage="); | |
1131 | m68hc11_print_register (gdbarch, file, frame, HARD_PAGE_REGNUM); | |
1132 | } | |
1133 | fprintf_filtered (file, "\n"); | |
1134 | ||
1135 | nr = 0; | |
1136 | for (i = SOFT_D1_REGNUM; i < M68HC11_ALL_REGS; i++) | |
1137 | { | |
1138 | /* Skip registers which are not defined in the symbol table. */ | |
1139 | if (soft_regs[i].name == 0) | |
1140 | continue; | |
1141 | ||
1142 | fprintf_filtered (file, "D%d=", i - SOFT_D1_REGNUM + 1); | |
1143 | m68hc11_print_register (gdbarch, file, frame, i); | |
1144 | nr++; | |
1145 | if ((nr % 8) == 7) | |
1146 | fprintf_filtered (file, "\n"); | |
1147 | else | |
1148 | fprintf_filtered (file, " "); | |
1149 | } | |
1150 | if (nr && (nr % 8) != 7) | |
1151 | fprintf_filtered (file, "\n"); | |
1152 | } | |
1153 | } | |
1154 | ||
82c230c2 | 1155 | static CORE_ADDR |
7d9b040b | 1156 | m68hc11_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
3dc990bf SC |
1157 | struct regcache *regcache, CORE_ADDR bp_addr, |
1158 | int nargs, struct value **args, CORE_ADDR sp, | |
1159 | int struct_return, CORE_ADDR struct_addr) | |
78073dd8 | 1160 | { |
82c230c2 SC |
1161 | int argnum; |
1162 | int first_stack_argnum; | |
82c230c2 SC |
1163 | struct type *type; |
1164 | char *val; | |
1165 | int len; | |
3dc990bf | 1166 | char buf[2]; |
82c230c2 | 1167 | |
82c230c2 SC |
1168 | first_stack_argnum = 0; |
1169 | if (struct_return) | |
1170 | { | |
ff1e98b9 | 1171 | regcache_cooked_write_unsigned (regcache, HARD_D_REGNUM, struct_addr); |
82c230c2 SC |
1172 | } |
1173 | else if (nargs > 0) | |
1174 | { | |
4991999e | 1175 | type = value_type (args[0]); |
82c230c2 | 1176 | len = TYPE_LENGTH (type); |
3dc990bf | 1177 | |
82c230c2 SC |
1178 | /* First argument is passed in D and X registers. */ |
1179 | if (len <= 4) | |
1180 | { | |
3dc990bf SC |
1181 | ULONGEST v; |
1182 | ||
0fd88904 | 1183 | v = extract_unsigned_integer (value_contents (args[0]), len); |
82c230c2 | 1184 | first_stack_argnum = 1; |
3dc990bf SC |
1185 | |
1186 | regcache_cooked_write_unsigned (regcache, HARD_D_REGNUM, v); | |
82c230c2 SC |
1187 | if (len > 2) |
1188 | { | |
1189 | v >>= 16; | |
3dc990bf | 1190 | regcache_cooked_write_unsigned (regcache, HARD_X_REGNUM, v); |
82c230c2 SC |
1191 | } |
1192 | } | |
1193 | } | |
82c230c2 | 1194 | |
3dc990bf | 1195 | for (argnum = nargs - 1; argnum >= first_stack_argnum; argnum--) |
82c230c2 | 1196 | { |
4991999e | 1197 | type = value_type (args[argnum]); |
82c230c2 SC |
1198 | len = TYPE_LENGTH (type); |
1199 | ||
22df305e SC |
1200 | if (len & 1) |
1201 | { | |
1202 | static char zero = 0; | |
1203 | ||
3dc990bf SC |
1204 | sp--; |
1205 | write_memory (sp, &zero, 1); | |
22df305e | 1206 | } |
0fd88904 | 1207 | val = (char*) value_contents (args[argnum]); |
3dc990bf SC |
1208 | sp -= len; |
1209 | write_memory (sp, val, len); | |
82c230c2 | 1210 | } |
3dc990bf SC |
1211 | |
1212 | /* Store return address. */ | |
1213 | sp -= 2; | |
1214 | store_unsigned_integer (buf, 2, bp_addr); | |
1215 | write_memory (sp, buf, 2); | |
1216 | ||
1217 | /* Finally, update the stack pointer... */ | |
be8626e0 | 1218 | sp -= STACK_CORRECTION (gdbarch); |
3dc990bf SC |
1219 | regcache_cooked_write_unsigned (regcache, HARD_SP_REGNUM, sp); |
1220 | ||
1221 | /* ...and fake a frame pointer. */ | |
1222 | regcache_cooked_write_unsigned (regcache, SOFT_FP_REGNUM, sp); | |
1223 | ||
1224 | /* DWARF2/GCC uses the stack address *before* the function call as a | |
1225 | frame's CFA. */ | |
1226 | return sp + 2; | |
78073dd8 AC |
1227 | } |
1228 | ||
1229 | ||
4db73d49 SC |
1230 | /* Return the GDB type object for the "standard" data type |
1231 | of data in register N. */ | |
1232 | ||
82c230c2 | 1233 | static struct type * |
4db73d49 | 1234 | m68hc11_register_type (struct gdbarch *gdbarch, int reg_nr) |
82c230c2 | 1235 | { |
5706502a SC |
1236 | switch (reg_nr) |
1237 | { | |
1238 | case HARD_PAGE_REGNUM: | |
1239 | case HARD_A_REGNUM: | |
1240 | case HARD_B_REGNUM: | |
1241 | case HARD_CCR_REGNUM: | |
1242 | return builtin_type_uint8; | |
1243 | ||
548bcbec SC |
1244 | case M68HC12_HARD_PC_REGNUM: |
1245 | return builtin_type_uint32; | |
1246 | ||
5706502a SC |
1247 | default: |
1248 | return builtin_type_uint16; | |
1249 | } | |
82c230c2 SC |
1250 | } |
1251 | ||
82c230c2 | 1252 | static void |
4db73d49 SC |
1253 | m68hc11_store_return_value (struct type *type, struct regcache *regcache, |
1254 | const void *valbuf) | |
82c230c2 | 1255 | { |
22df305e SC |
1256 | int len; |
1257 | ||
1258 | len = TYPE_LENGTH (type); | |
1259 | ||
1260 | /* First argument is passed in D and X registers. */ | |
4db73d49 SC |
1261 | if (len <= 2) |
1262 | regcache_raw_write_part (regcache, HARD_D_REGNUM, 2 - len, len, valbuf); | |
1263 | else if (len <= 4) | |
22df305e | 1264 | { |
4db73d49 SC |
1265 | regcache_raw_write_part (regcache, HARD_X_REGNUM, 4 - len, |
1266 | len - 2, valbuf); | |
1267 | regcache_raw_write (regcache, HARD_D_REGNUM, (char*) valbuf + (len - 2)); | |
22df305e SC |
1268 | } |
1269 | else | |
8a3fe4f8 | 1270 | error (_("return of value > 4 is not supported.")); |
82c230c2 SC |
1271 | } |
1272 | ||
1273 | ||
ef2b8fcd | 1274 | /* Given a return value in `regcache' with a type `type', |
78073dd8 AC |
1275 | extract and copy its value into `valbuf'. */ |
1276 | ||
82c230c2 | 1277 | static void |
ef2b8fcd SC |
1278 | m68hc11_extract_return_value (struct type *type, struct regcache *regcache, |
1279 | void *valbuf) | |
78073dd8 | 1280 | { |
82c230c2 | 1281 | int len = TYPE_LENGTH (type); |
ef2b8fcd SC |
1282 | char buf[M68HC11_REG_SIZE]; |
1283 | ||
1284 | regcache_raw_read (regcache, HARD_D_REGNUM, buf); | |
22df305e | 1285 | switch (len) |
82c230c2 | 1286 | { |
22df305e | 1287 | case 1: |
ef2b8fcd | 1288 | memcpy (valbuf, buf + 1, 1); |
22df305e | 1289 | break; |
ef2b8fcd | 1290 | |
22df305e | 1291 | case 2: |
ef2b8fcd | 1292 | memcpy (valbuf, buf, 2); |
22df305e | 1293 | break; |
ef2b8fcd | 1294 | |
22df305e | 1295 | case 3: |
ef2b8fcd SC |
1296 | memcpy ((char*) valbuf + 1, buf, 2); |
1297 | regcache_raw_read (regcache, HARD_X_REGNUM, buf); | |
1298 | memcpy (valbuf, buf + 1, 1); | |
22df305e | 1299 | break; |
ef2b8fcd | 1300 | |
22df305e | 1301 | case 4: |
ef2b8fcd SC |
1302 | memcpy ((char*) valbuf + 2, buf, 2); |
1303 | regcache_raw_read (regcache, HARD_X_REGNUM, buf); | |
1304 | memcpy (valbuf, buf, 2); | |
22df305e SC |
1305 | break; |
1306 | ||
1307 | default: | |
8a3fe4f8 | 1308 | error (_("bad size for return value")); |
82c230c2 SC |
1309 | } |
1310 | } | |
1311 | ||
63807e1d | 1312 | static enum return_value_convention |
c055b101 CV |
1313 | m68hc11_return_value (struct gdbarch *gdbarch, struct type *func_type, |
1314 | struct type *valtype, struct regcache *regcache, | |
1315 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
82c230c2 | 1316 | { |
97092415 AC |
1317 | if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT |
1318 | || TYPE_CODE (valtype) == TYPE_CODE_UNION | |
1319 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY | |
1320 | || TYPE_LENGTH (valtype) > 4) | |
1321 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1322 | else | |
1323 | { | |
1324 | if (readbuf != NULL) | |
1325 | m68hc11_extract_return_value (valtype, regcache, readbuf); | |
1326 | if (writebuf != NULL) | |
1327 | m68hc11_store_return_value (valtype, regcache, writebuf); | |
1328 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1329 | } | |
82c230c2 SC |
1330 | } |
1331 | ||
7df11f59 SC |
1332 | /* Test whether the ELF symbol corresponds to a function using rtc or |
1333 | rti to return. */ | |
1334 | ||
1335 | static void | |
1336 | m68hc11_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym) | |
1337 | { | |
1338 | unsigned char flags; | |
1339 | ||
1340 | flags = ((elf_symbol_type *)sym)->internal_elf_sym.st_other; | |
1341 | if (flags & STO_M68HC12_FAR) | |
1342 | MSYMBOL_SET_RTC (msym); | |
1343 | if (flags & STO_M68HC12_INTERRUPT) | |
1344 | MSYMBOL_SET_RTI (msym); | |
1345 | } | |
1346 | ||
ea3881d9 SC |
1347 | static int |
1348 | gdb_print_insn_m68hc11 (bfd_vma memaddr, disassemble_info *info) | |
1349 | { | |
9dae60cc | 1350 | if (info->arch == bfd_arch_m68hc11) |
ea3881d9 SC |
1351 | return print_insn_m68hc11 (memaddr, info); |
1352 | else | |
1353 | return print_insn_m68hc12 (memaddr, info); | |
1354 | } | |
1355 | ||
b631436b SC |
1356 | \f |
1357 | ||
1358 | /* 68HC11/68HC12 register groups. | |
1359 | Identify real hard registers and soft registers used by gcc. */ | |
1360 | ||
1361 | static struct reggroup *m68hc11_soft_reggroup; | |
1362 | static struct reggroup *m68hc11_hard_reggroup; | |
1363 | ||
1364 | static void | |
1365 | m68hc11_init_reggroups (void) | |
1366 | { | |
1367 | m68hc11_hard_reggroup = reggroup_new ("hard", USER_REGGROUP); | |
1368 | m68hc11_soft_reggroup = reggroup_new ("soft", USER_REGGROUP); | |
1369 | } | |
1370 | ||
1371 | static void | |
1372 | m68hc11_add_reggroups (struct gdbarch *gdbarch) | |
1373 | { | |
1374 | reggroup_add (gdbarch, m68hc11_hard_reggroup); | |
1375 | reggroup_add (gdbarch, m68hc11_soft_reggroup); | |
1376 | reggroup_add (gdbarch, general_reggroup); | |
1377 | reggroup_add (gdbarch, float_reggroup); | |
1378 | reggroup_add (gdbarch, all_reggroup); | |
1379 | reggroup_add (gdbarch, save_reggroup); | |
1380 | reggroup_add (gdbarch, restore_reggroup); | |
1381 | reggroup_add (gdbarch, vector_reggroup); | |
1382 | reggroup_add (gdbarch, system_reggroup); | |
1383 | } | |
1384 | ||
1385 | static int | |
1386 | m68hc11_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
1387 | struct reggroup *group) | |
1388 | { | |
1389 | /* We must save the real hard register as well as gcc | |
1390 | soft registers including the frame pointer. */ | |
1391 | if (group == save_reggroup || group == restore_reggroup) | |
1392 | { | |
1393 | return (regnum <= gdbarch_num_regs (gdbarch) | |
1394 | || ((regnum == SOFT_FP_REGNUM | |
1395 | || regnum == SOFT_TMP_REGNUM | |
1396 | || regnum == SOFT_ZS_REGNUM | |
1397 | || regnum == SOFT_XY_REGNUM) | |
d93859e2 | 1398 | && m68hc11_register_name (gdbarch, regnum))); |
b631436b SC |
1399 | } |
1400 | ||
1401 | /* Group to identify gcc soft registers (d1..dN). */ | |
1402 | if (group == m68hc11_soft_reggroup) | |
1403 | { | |
d93859e2 UW |
1404 | return regnum >= SOFT_D1_REGNUM |
1405 | && m68hc11_register_name (gdbarch, regnum); | |
b631436b SC |
1406 | } |
1407 | ||
1408 | if (group == m68hc11_hard_reggroup) | |
1409 | { | |
1410 | return regnum == HARD_PC_REGNUM || regnum == HARD_SP_REGNUM | |
1411 | || regnum == HARD_X_REGNUM || regnum == HARD_D_REGNUM | |
1412 | || regnum == HARD_Y_REGNUM || regnum == HARD_CCR_REGNUM; | |
1413 | } | |
1414 | return default_register_reggroup_p (gdbarch, regnum, group); | |
1415 | } | |
1416 | ||
82c230c2 SC |
1417 | static struct gdbarch * |
1418 | m68hc11_gdbarch_init (struct gdbarch_info info, | |
1419 | struct gdbarch_list *arches) | |
1420 | { | |
82c230c2 SC |
1421 | struct gdbarch *gdbarch; |
1422 | struct gdbarch_tdep *tdep; | |
81967506 | 1423 | int elf_flags; |
82c230c2 SC |
1424 | |
1425 | soft_reg_initialized = 0; | |
81967506 SC |
1426 | |
1427 | /* Extract the elf_flags if available. */ | |
1428 | if (info.abfd != NULL | |
1429 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
1430 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
1431 | else | |
1432 | elf_flags = 0; | |
1433 | ||
82c230c2 SC |
1434 | /* try to find a pre-existing architecture */ |
1435 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
1436 | arches != NULL; | |
1437 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
1438 | { | |
81967506 SC |
1439 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
1440 | continue; | |
1441 | ||
82c230c2 SC |
1442 | return arches->gdbarch; |
1443 | } | |
1444 | ||
1445 | /* Need a new architecture. Fill in a target specific vector. */ | |
1446 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); | |
1447 | gdbarch = gdbarch_alloc (&info, tdep); | |
81967506 | 1448 | tdep->elf_flags = elf_flags; |
ed99b3d0 | 1449 | |
5d1a66bd SC |
1450 | switch (info.bfd_arch_info->arch) |
1451 | { | |
1452 | case bfd_arch_m68hc11: | |
1453 | tdep->stack_correction = 1; | |
7df11f59 | 1454 | tdep->use_page_register = 0; |
908f682f | 1455 | tdep->prologue = m6811_prologue; |
548bcbec SC |
1456 | set_gdbarch_addr_bit (gdbarch, 16); |
1457 | set_gdbarch_num_pseudo_regs (gdbarch, M68HC11_NUM_PSEUDO_REGS); | |
1458 | set_gdbarch_pc_regnum (gdbarch, HARD_PC_REGNUM); | |
1459 | set_gdbarch_num_regs (gdbarch, M68HC11_NUM_REGS); | |
5d1a66bd | 1460 | break; |
82c230c2 | 1461 | |
5d1a66bd SC |
1462 | case bfd_arch_m68hc12: |
1463 | tdep->stack_correction = 0; | |
7df11f59 | 1464 | tdep->use_page_register = elf_flags & E_M68HC12_BANKS; |
908f682f | 1465 | tdep->prologue = m6812_prologue; |
548bcbec SC |
1466 | set_gdbarch_addr_bit (gdbarch, elf_flags & E_M68HC12_BANKS ? 32 : 16); |
1467 | set_gdbarch_num_pseudo_regs (gdbarch, | |
1468 | elf_flags & E_M68HC12_BANKS | |
1469 | ? M68HC12_NUM_PSEUDO_REGS | |
1470 | : M68HC11_NUM_PSEUDO_REGS); | |
1471 | set_gdbarch_pc_regnum (gdbarch, elf_flags & E_M68HC12_BANKS | |
1472 | ? M68HC12_HARD_PC_REGNUM : HARD_PC_REGNUM); | |
1473 | set_gdbarch_num_regs (gdbarch, elf_flags & E_M68HC12_BANKS | |
1474 | ? M68HC12_NUM_REGS : M68HC11_NUM_REGS); | |
5d1a66bd SC |
1475 | break; |
1476 | ||
1477 | default: | |
1478 | break; | |
1479 | } | |
7d32ba20 SC |
1480 | |
1481 | /* Initially set everything according to the ABI. | |
1482 | Use 16-bit integers since it will be the case for most | |
1483 | programs. The size of these types should normally be set | |
1484 | according to the dwarf2 debug information. */ | |
82c230c2 | 1485 | set_gdbarch_short_bit (gdbarch, 16); |
81967506 | 1486 | set_gdbarch_int_bit (gdbarch, elf_flags & E_M68HC11_I32 ? 32 : 16); |
82c230c2 | 1487 | set_gdbarch_float_bit (gdbarch, 32); |
81967506 | 1488 | set_gdbarch_double_bit (gdbarch, elf_flags & E_M68HC11_F64 ? 64 : 32); |
2417dd25 | 1489 | set_gdbarch_long_double_bit (gdbarch, 64); |
82c230c2 SC |
1490 | set_gdbarch_long_bit (gdbarch, 32); |
1491 | set_gdbarch_ptr_bit (gdbarch, 16); | |
1492 | set_gdbarch_long_long_bit (gdbarch, 64); | |
1493 | ||
b2a02dda SC |
1494 | /* Characters are unsigned. */ |
1495 | set_gdbarch_char_signed (gdbarch, 0); | |
1496 | ||
1ea653ae SC |
1497 | set_gdbarch_unwind_pc (gdbarch, m68hc11_unwind_pc); |
1498 | set_gdbarch_unwind_sp (gdbarch, m68hc11_unwind_sp); | |
1499 | ||
82c230c2 SC |
1500 | /* Set register info. */ |
1501 | set_gdbarch_fp0_regnum (gdbarch, -1); | |
82c230c2 | 1502 | |
82c230c2 | 1503 | set_gdbarch_sp_regnum (gdbarch, HARD_SP_REGNUM); |
82c230c2 | 1504 | set_gdbarch_register_name (gdbarch, m68hc11_register_name); |
4db73d49 | 1505 | set_gdbarch_register_type (gdbarch, m68hc11_register_type); |
46ce284d AC |
1506 | set_gdbarch_pseudo_register_read (gdbarch, m68hc11_pseudo_register_read); |
1507 | set_gdbarch_pseudo_register_write (gdbarch, m68hc11_pseudo_register_write); | |
82c230c2 | 1508 | |
3dc990bf SC |
1509 | set_gdbarch_push_dummy_call (gdbarch, m68hc11_push_dummy_call); |
1510 | ||
97092415 | 1511 | set_gdbarch_return_value (gdbarch, m68hc11_return_value); |
82c230c2 SC |
1512 | set_gdbarch_skip_prologue (gdbarch, m68hc11_skip_prologue); |
1513 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
82c230c2 | 1514 | set_gdbarch_breakpoint_from_pc (gdbarch, m68hc11_breakpoint_from_pc); |
70ed8774 | 1515 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_m68hc11); |
82c230c2 | 1516 | |
b631436b SC |
1517 | m68hc11_add_reggroups (gdbarch); |
1518 | set_gdbarch_register_reggroup_p (gdbarch, m68hc11_register_reggroup_p); | |
e286caf2 | 1519 | set_gdbarch_print_registers_info (gdbarch, m68hc11_print_registers_info); |
b631436b | 1520 | |
1ea653ae | 1521 | /* Hook in the DWARF CFI frame unwinder. */ |
94afd7a6 | 1522 | dwarf2_append_unwinders (gdbarch); |
1ea653ae | 1523 | |
94afd7a6 | 1524 | frame_unwind_append_unwinder (gdbarch, &m68hc11_frame_unwind); |
1ea653ae SC |
1525 | frame_base_set_default (gdbarch, &m68hc11_frame_base); |
1526 | ||
1527 | /* Methods for saving / extracting a dummy frame's ID. The ID's | |
1528 | stack address must match the SP value returned by | |
1529 | PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */ | |
94afd7a6 | 1530 | set_gdbarch_dummy_id (gdbarch, m68hc11_dummy_id); |
1ea653ae SC |
1531 | |
1532 | /* Return the unwound PC value. */ | |
1533 | set_gdbarch_unwind_pc (gdbarch, m68hc11_unwind_pc); | |
1534 | ||
7df11f59 SC |
1535 | /* Minsymbol frobbing. */ |
1536 | set_gdbarch_elf_make_msymbol_special (gdbarch, | |
1537 | m68hc11_elf_make_msymbol_special); | |
1538 | ||
82c230c2 | 1539 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
82c230c2 SC |
1540 | |
1541 | return gdbarch; | |
78073dd8 AC |
1542 | } |
1543 | ||
a78f21af AC |
1544 | extern initialize_file_ftype _initialize_m68hc11_tdep; /* -Wmissing-prototypes */ |
1545 | ||
78073dd8 | 1546 | void |
fba45db2 | 1547 | _initialize_m68hc11_tdep (void) |
78073dd8 | 1548 | { |
82c230c2 | 1549 | register_gdbarch_init (bfd_arch_m68hc11, m68hc11_gdbarch_init); |
ea3881d9 | 1550 | register_gdbarch_init (bfd_arch_m68hc12, m68hc11_gdbarch_init); |
b631436b | 1551 | m68hc11_init_reggroups (); |
78073dd8 AC |
1552 | } |
1553 |