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908f682f | 1 | /* Target-dependent code for Motorola 68HC11 & 68HC12 |
931aecf5 | 2 | |
e2882c85 | 3 | Copyright (C) 1999-2018 Free Software Foundation, Inc. |
931aecf5 | 4 | |
ffe1f3ee | 5 | Contributed by Stephane Carrez, stcarrez@nerim.fr |
78073dd8 | 6 | |
a9762ec7 JB |
7 | This file is part of GDB. |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3 of the License, or | |
12 | (at your option) any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
78073dd8 | 21 | |
78073dd8 | 22 | |
82c230c2 SC |
23 | #include "defs.h" |
24 | #include "frame.h" | |
1ea653ae SC |
25 | #include "frame-unwind.h" |
26 | #include "frame-base.h" | |
27 | #include "dwarf2-frame.h" | |
28 | #include "trad-frame.h" | |
82c230c2 SC |
29 | #include "symtab.h" |
30 | #include "gdbtypes.h" | |
31 | #include "gdbcmd.h" | |
32 | #include "gdbcore.h" | |
82c230c2 SC |
33 | #include "value.h" |
34 | #include "inferior.h" | |
35 | #include "dis-asm.h" | |
36 | #include "symfile.h" | |
37 | #include "objfiles.h" | |
38 | #include "arch-utils.h" | |
4e052eda | 39 | #include "regcache.h" |
b631436b | 40 | #include "reggroups.h" |
78073dd8 | 41 | |
82c230c2 SC |
42 | #include "target.h" |
43 | #include "opcode/m68hc11.h" | |
81967506 SC |
44 | #include "elf/m68hc11.h" |
45 | #include "elf-bfd.h" | |
78073dd8 | 46 | |
7df11f59 SC |
47 | /* Macros for setting and testing a bit in a minimal symbol. |
48 | For 68HC11/68HC12 we have two flags that tell which return | |
49 | type the function is using. This is used for prologue and frame | |
50 | analysis to compute correct stack frame layout. | |
51 | ||
52 | The MSB of the minimal symbol's "info" field is used for this purpose. | |
7df11f59 SC |
53 | |
54 | MSYMBOL_SET_RTC Actually sets the "RTC" bit. | |
55 | MSYMBOL_SET_RTI Actually sets the "RTI" bit. | |
56 | MSYMBOL_IS_RTC Tests the "RTC" bit in a minimal symbol. | |
f594e5e9 | 57 | MSYMBOL_IS_RTI Tests the "RTC" bit in a minimal symbol. */ |
7df11f59 | 58 | |
025bb325 | 59 | #define MSYMBOL_SET_RTC(msym) \ |
b887350f | 60 | MSYMBOL_TARGET_FLAG_1 (msym) = 1 |
7df11f59 | 61 | |
025bb325 | 62 | #define MSYMBOL_SET_RTI(msym) \ |
b887350f | 63 | MSYMBOL_TARGET_FLAG_2 (msym) = 1 |
7df11f59 SC |
64 | |
65 | #define MSYMBOL_IS_RTC(msym) \ | |
b887350f | 66 | MSYMBOL_TARGET_FLAG_1 (msym) |
7df11f59 SC |
67 | |
68 | #define MSYMBOL_IS_RTI(msym) \ | |
b887350f | 69 | MSYMBOL_TARGET_FLAG_2 (msym) |
7df11f59 | 70 | |
7df11f59 SC |
71 | enum insn_return_kind { |
72 | RETURN_RTS, | |
73 | RETURN_RTC, | |
74 | RETURN_RTI | |
75 | }; | |
76 | ||
77 | ||
7157eed4 | 78 | /* Register numbers of various important registers. */ |
78073dd8 | 79 | |
82c230c2 SC |
80 | #define HARD_X_REGNUM 0 |
81 | #define HARD_D_REGNUM 1 | |
82 | #define HARD_Y_REGNUM 2 | |
83 | #define HARD_SP_REGNUM 3 | |
84 | #define HARD_PC_REGNUM 4 | |
85 | ||
86 | #define HARD_A_REGNUM 5 | |
87 | #define HARD_B_REGNUM 6 | |
88 | #define HARD_CCR_REGNUM 7 | |
5706502a SC |
89 | |
90 | /* 68HC12 page number register. | |
91 | Note: to keep a compatibility with gcc register naming, we must | |
92 | not have to rename FP and other soft registers. The page register | |
f57d151a | 93 | is a real hard register and must therefore be counted by gdbarch_num_regs. |
5706502a SC |
94 | For this it has the same number as Z register (which is not used). */ |
95 | #define HARD_PAGE_REGNUM 8 | |
96 | #define M68HC11_LAST_HARD_REG (HARD_PAGE_REGNUM) | |
82c230c2 SC |
97 | |
98 | /* Z is replaced by X or Y by gcc during machine reorg. | |
99 | ??? There is no way to get it and even know whether | |
100 | it's in X or Y or in ZS. */ | |
101 | #define SOFT_Z_REGNUM 8 | |
102 | ||
103 | /* Soft registers. These registers are special. There are treated | |
104 | like normal hard registers by gcc and gdb (ie, within dwarf2 info). | |
105 | They are physically located in memory. */ | |
106 | #define SOFT_FP_REGNUM 9 | |
107 | #define SOFT_TMP_REGNUM 10 | |
108 | #define SOFT_ZS_REGNUM 11 | |
109 | #define SOFT_XY_REGNUM 12 | |
f91a8b6b SC |
110 | #define SOFT_UNUSED_REGNUM 13 |
111 | #define SOFT_D1_REGNUM 14 | |
82c230c2 SC |
112 | #define SOFT_D32_REGNUM (SOFT_D1_REGNUM+31) |
113 | #define M68HC11_MAX_SOFT_REGS 32 | |
114 | ||
a714b0d6 | 115 | #define M68HC11_NUM_REGS (M68HC11_LAST_HARD_REG + 1) |
82c230c2 SC |
116 | #define M68HC11_NUM_PSEUDO_REGS (M68HC11_MAX_SOFT_REGS+5) |
117 | #define M68HC11_ALL_REGS (M68HC11_NUM_REGS+M68HC11_NUM_PSEUDO_REGS) | |
118 | ||
119 | #define M68HC11_REG_SIZE (2) | |
120 | ||
548bcbec SC |
121 | #define M68HC12_NUM_REGS (9) |
122 | #define M68HC12_NUM_PSEUDO_REGS ((M68HC11_MAX_SOFT_REGS+5)+1-1) | |
123 | #define M68HC12_HARD_PC_REGNUM (SOFT_D32_REGNUM+1) | |
124 | ||
908f682f | 125 | struct insn_sequence; |
82c230c2 SC |
126 | struct gdbarch_tdep |
127 | { | |
5d1a66bd SC |
128 | /* Stack pointer correction value. For 68hc11, the stack pointer points |
129 | to the next push location. An offset of 1 must be applied to obtain | |
130 | the address where the last value is saved. For 68hc12, the stack | |
131 | pointer points to the last value pushed. No offset is necessary. */ | |
132 | int stack_correction; | |
908f682f SC |
133 | |
134 | /* Description of instructions in the prologue. */ | |
135 | struct insn_sequence *prologue; | |
81967506 | 136 | |
7df11f59 SC |
137 | /* True if the page memory bank register is available |
138 | and must be used. */ | |
139 | int use_page_register; | |
140 | ||
81967506 SC |
141 | /* ELF flags for ABI. */ |
142 | int elf_flags; | |
82c230c2 SC |
143 | }; |
144 | ||
be8626e0 MD |
145 | #define STACK_CORRECTION(gdbarch) (gdbarch_tdep (gdbarch)->stack_correction) |
146 | #define USE_PAGE_REGISTER(gdbarch) (gdbarch_tdep (gdbarch)->use_page_register) | |
5d1a66bd | 147 | |
1ea653ae SC |
148 | struct m68hc11_unwind_cache |
149 | { | |
150 | /* The previous frame's inner most stack address. Used as this | |
151 | frame ID's stack_addr. */ | |
152 | CORE_ADDR prev_sp; | |
153 | /* The frame's base, optionally used by the high-level debug info. */ | |
154 | CORE_ADDR base; | |
155 | CORE_ADDR pc; | |
156 | int size; | |
157 | int prologue_type; | |
158 | CORE_ADDR return_pc; | |
159 | CORE_ADDR sp_offset; | |
160 | int frameless; | |
161 | enum insn_return_kind return_kind; | |
162 | ||
163 | /* Table indicating the location of each and every register. */ | |
164 | struct trad_frame_saved_reg *saved_regs; | |
165 | }; | |
166 | ||
82c230c2 SC |
167 | /* Table of registers for 68HC11. This includes the hard registers |
168 | and the soft registers used by GCC. */ | |
a121b7c1 | 169 | static const char * |
82c230c2 SC |
170 | m68hc11_register_names[] = |
171 | { | |
172 | "x", "d", "y", "sp", "pc", "a", "b", | |
5706502a | 173 | "ccr", "page", "frame","tmp", "zs", "xy", 0, |
82c230c2 SC |
174 | "d1", "d2", "d3", "d4", "d5", "d6", "d7", |
175 | "d8", "d9", "d10", "d11", "d12", "d13", "d14", | |
176 | "d15", "d16", "d17", "d18", "d19", "d20", "d21", | |
177 | "d22", "d23", "d24", "d25", "d26", "d27", "d28", | |
178 | "d29", "d30", "d31", "d32" | |
179 | }; | |
78073dd8 | 180 | |
82c230c2 SC |
181 | struct m68hc11_soft_reg |
182 | { | |
183 | const char *name; | |
184 | CORE_ADDR addr; | |
185 | }; | |
78073dd8 | 186 | |
82c230c2 | 187 | static struct m68hc11_soft_reg soft_regs[M68HC11_ALL_REGS]; |
78073dd8 | 188 | |
82c230c2 | 189 | #define M68HC11_FP_ADDR soft_regs[SOFT_FP_REGNUM].addr |
78073dd8 | 190 | |
82c230c2 SC |
191 | static int soft_min_addr; |
192 | static int soft_max_addr; | |
193 | static int soft_reg_initialized = 0; | |
78073dd8 | 194 | |
82c230c2 SC |
195 | /* Look in the symbol table for the address of a pseudo register |
196 | in memory. If we don't find it, pretend the register is not used | |
197 | and not available. */ | |
198 | static void | |
199 | m68hc11_get_register_info (struct m68hc11_soft_reg *reg, const char *name) | |
200 | { | |
3b7344d5 | 201 | struct bound_minimal_symbol msymbol; |
78073dd8 | 202 | |
82c230c2 | 203 | msymbol = lookup_minimal_symbol (name, NULL, NULL); |
3b7344d5 | 204 | if (msymbol.minsym) |
82c230c2 | 205 | { |
77e371c0 | 206 | reg->addr = BMSYMBOL_VALUE_ADDRESS (msymbol); |
82c230c2 SC |
207 | reg->name = xstrdup (name); |
208 | ||
209 | /* Keep track of the address range for soft registers. */ | |
210 | if (reg->addr < (CORE_ADDR) soft_min_addr) | |
211 | soft_min_addr = reg->addr; | |
212 | if (reg->addr > (CORE_ADDR) soft_max_addr) | |
213 | soft_max_addr = reg->addr; | |
214 | } | |
215 | else | |
216 | { | |
217 | reg->name = 0; | |
218 | reg->addr = 0; | |
219 | } | |
220 | } | |
78073dd8 | 221 | |
82c230c2 SC |
222 | /* Initialize the table of soft register addresses according |
223 | to the symbol table. */ | |
224 | static void | |
225 | m68hc11_initialize_register_info (void) | |
226 | { | |
227 | int i; | |
78073dd8 | 228 | |
82c230c2 SC |
229 | if (soft_reg_initialized) |
230 | return; | |
231 | ||
232 | soft_min_addr = INT_MAX; | |
233 | soft_max_addr = 0; | |
234 | for (i = 0; i < M68HC11_ALL_REGS; i++) | |
235 | { | |
236 | soft_regs[i].name = 0; | |
237 | } | |
238 | ||
239 | m68hc11_get_register_info (&soft_regs[SOFT_FP_REGNUM], "_.frame"); | |
240 | m68hc11_get_register_info (&soft_regs[SOFT_TMP_REGNUM], "_.tmp"); | |
241 | m68hc11_get_register_info (&soft_regs[SOFT_ZS_REGNUM], "_.z"); | |
242 | soft_regs[SOFT_Z_REGNUM] = soft_regs[SOFT_ZS_REGNUM]; | |
243 | m68hc11_get_register_info (&soft_regs[SOFT_XY_REGNUM], "_.xy"); | |
78073dd8 | 244 | |
82c230c2 SC |
245 | for (i = SOFT_D1_REGNUM; i < M68HC11_MAX_SOFT_REGS; i++) |
246 | { | |
247 | char buf[10]; | |
78073dd8 | 248 | |
08850b56 | 249 | xsnprintf (buf, sizeof (buf), "_.d%d", i - SOFT_D1_REGNUM + 1); |
82c230c2 SC |
250 | m68hc11_get_register_info (&soft_regs[i], buf); |
251 | } | |
78073dd8 | 252 | |
82c230c2 | 253 | if (soft_regs[SOFT_FP_REGNUM].name == 0) |
8a3fe4f8 AC |
254 | warning (_("No frame soft register found in the symbol table.\n" |
255 | "Stack backtrace will not work.")); | |
82c230c2 SC |
256 | soft_reg_initialized = 1; |
257 | } | |
78073dd8 | 258 | |
82c230c2 SC |
259 | /* Given an address in memory, return the soft register number if |
260 | that address corresponds to a soft register. Returns -1 if not. */ | |
261 | static int | |
262 | m68hc11_which_soft_register (CORE_ADDR addr) | |
263 | { | |
264 | int i; | |
265 | ||
266 | if (addr < soft_min_addr || addr > soft_max_addr) | |
267 | return -1; | |
268 | ||
269 | for (i = SOFT_FP_REGNUM; i < M68HC11_ALL_REGS; i++) | |
270 | { | |
271 | if (soft_regs[i].name && soft_regs[i].addr == addr) | |
272 | return i; | |
273 | } | |
274 | return -1; | |
275 | } | |
78073dd8 | 276 | |
82c230c2 SC |
277 | /* Fetch a pseudo register. The 68hc11 soft registers are treated like |
278 | pseudo registers. They are located in memory. Translate the register | |
279 | fetch into a memory read. */ | |
05d1431c | 280 | static enum register_status |
46ce284d | 281 | m68hc11_pseudo_register_read (struct gdbarch *gdbarch, |
849d0ba8 | 282 | readable_regcache *regcache, |
ff1e98b9 | 283 | int regno, gdb_byte *buf) |
82c230c2 | 284 | { |
e17a4113 UW |
285 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
286 | ||
548bcbec SC |
287 | /* The PC is a pseudo reg only for 68HC12 with the memory bank |
288 | addressing mode. */ | |
289 | if (regno == M68HC12_HARD_PC_REGNUM) | |
290 | { | |
4db73d49 | 291 | ULONGEST pc; |
df4df182 | 292 | const int regsize = 4; |
05d1431c | 293 | enum register_status status; |
548bcbec | 294 | |
11f57cb6 | 295 | status = regcache->cooked_read (HARD_PC_REGNUM, &pc); |
05d1431c PA |
296 | if (status != REG_VALID) |
297 | return status; | |
548bcbec SC |
298 | if (pc >= 0x8000 && pc < 0xc000) |
299 | { | |
4db73d49 SC |
300 | ULONGEST page; |
301 | ||
11f57cb6 | 302 | regcache->cooked_read (HARD_PAGE_REGNUM, &page); |
548bcbec SC |
303 | pc -= 0x8000; |
304 | pc += (page << 14); | |
305 | pc += 0x1000000; | |
306 | } | |
e17a4113 | 307 | store_unsigned_integer (buf, regsize, byte_order, pc); |
05d1431c | 308 | return REG_VALID; |
548bcbec SC |
309 | } |
310 | ||
82c230c2 SC |
311 | m68hc11_initialize_register_info (); |
312 | ||
313 | /* Fetch a soft register: translate into a memory read. */ | |
314 | if (soft_regs[regno].name) | |
315 | { | |
316 | target_read_memory (soft_regs[regno].addr, buf, 2); | |
317 | } | |
318 | else | |
319 | { | |
320 | memset (buf, 0, 2); | |
321 | } | |
05d1431c PA |
322 | |
323 | return REG_VALID; | |
82c230c2 | 324 | } |
78073dd8 | 325 | |
82c230c2 SC |
326 | /* Store a pseudo register. Translate the register store |
327 | into a memory write. */ | |
328 | static void | |
46ce284d AC |
329 | m68hc11_pseudo_register_write (struct gdbarch *gdbarch, |
330 | struct regcache *regcache, | |
ff1e98b9 | 331 | int regno, const gdb_byte *buf) |
82c230c2 | 332 | { |
e17a4113 UW |
333 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
334 | ||
548bcbec SC |
335 | /* The PC is a pseudo reg only for 68HC12 with the memory bank |
336 | addressing mode. */ | |
337 | if (regno == M68HC12_HARD_PC_REGNUM) | |
338 | { | |
df4df182 | 339 | const int regsize = 4; |
224c3ddb | 340 | gdb_byte *tmp = (gdb_byte *) alloca (regsize); |
548bcbec SC |
341 | CORE_ADDR pc; |
342 | ||
343 | memcpy (tmp, buf, regsize); | |
e17a4113 | 344 | pc = extract_unsigned_integer (tmp, regsize, byte_order); |
548bcbec SC |
345 | if (pc >= 0x1000000) |
346 | { | |
347 | pc -= 0x1000000; | |
4db73d49 SC |
348 | regcache_cooked_write_unsigned (regcache, HARD_PAGE_REGNUM, |
349 | (pc >> 14) & 0x0ff); | |
548bcbec | 350 | pc &= 0x03fff; |
4db73d49 SC |
351 | regcache_cooked_write_unsigned (regcache, HARD_PC_REGNUM, |
352 | pc + 0x8000); | |
548bcbec SC |
353 | } |
354 | else | |
4db73d49 | 355 | regcache_cooked_write_unsigned (regcache, HARD_PC_REGNUM, pc); |
548bcbec SC |
356 | return; |
357 | } | |
358 | ||
82c230c2 | 359 | m68hc11_initialize_register_info (); |
78073dd8 | 360 | |
82c230c2 SC |
361 | /* Store a soft register: translate into a memory write. */ |
362 | if (soft_regs[regno].name) | |
363 | { | |
46ce284d | 364 | const int regsize = 2; |
224c3ddb | 365 | gdb_byte *tmp = (gdb_byte *) alloca (regsize); |
46ce284d AC |
366 | memcpy (tmp, buf, regsize); |
367 | target_write_memory (soft_regs[regno].addr, tmp, regsize); | |
82c230c2 SC |
368 | } |
369 | } | |
78073dd8 | 370 | |
fa88f677 | 371 | static const char * |
d93859e2 | 372 | m68hc11_register_name (struct gdbarch *gdbarch, int reg_nr) |
78073dd8 | 373 | { |
be8626e0 | 374 | if (reg_nr == M68HC12_HARD_PC_REGNUM && USE_PAGE_REGISTER (gdbarch)) |
548bcbec | 375 | return "pc"; |
be8626e0 | 376 | if (reg_nr == HARD_PC_REGNUM && USE_PAGE_REGISTER (gdbarch)) |
548bcbec SC |
377 | return "ppc"; |
378 | ||
82c230c2 SC |
379 | if (reg_nr < 0) |
380 | return NULL; | |
381 | if (reg_nr >= M68HC11_ALL_REGS) | |
382 | return NULL; | |
383 | ||
65760afb SC |
384 | m68hc11_initialize_register_info (); |
385 | ||
82c230c2 SC |
386 | /* If we don't know the address of a soft register, pretend it |
387 | does not exist. */ | |
388 | if (reg_nr > M68HC11_LAST_HARD_REG && soft_regs[reg_nr].name == 0) | |
389 | return NULL; | |
390 | return m68hc11_register_names[reg_nr]; | |
391 | } | |
78073dd8 | 392 | |
04180708 | 393 | constexpr gdb_byte m68hc11_break_insn[] = {0x0}; |
78073dd8 | 394 | |
04180708 | 395 | typedef BP_MANIPULATION (m68hc11_break_insn) m68hc11_breakpoint; |
908f682f | 396 | \f |
025bb325 | 397 | /* 68HC11 & 68HC12 prologue analysis. */ |
908f682f | 398 | |
908f682f SC |
399 | #define MAX_CODES 12 |
400 | ||
401 | /* 68HC11 opcodes. */ | |
402 | #undef M6811_OP_PAGE2 | |
b94a41a1 SC |
403 | #define M6811_OP_PAGE2 (0x18) |
404 | #define M6811_OP_LDX (0xde) | |
405 | #define M6811_OP_LDX_EXT (0xfe) | |
406 | #define M6811_OP_PSHX (0x3c) | |
407 | #define M6811_OP_STS (0x9f) | |
408 | #define M6811_OP_STS_EXT (0xbf) | |
409 | #define M6811_OP_TSX (0x30) | |
410 | #define M6811_OP_XGDX (0x8f) | |
411 | #define M6811_OP_ADDD (0xc3) | |
412 | #define M6811_OP_TXS (0x35) | |
413 | #define M6811_OP_DES (0x34) | |
908f682f SC |
414 | |
415 | /* 68HC12 opcodes. */ | |
b94a41a1 SC |
416 | #define M6812_OP_PAGE2 (0x18) |
417 | #define M6812_OP_MOVW (0x01) | |
418 | #define M6812_PB_PSHW (0xae) | |
419 | #define M6812_OP_STS (0x5f) | |
420 | #define M6812_OP_STS_EXT (0x7f) | |
421 | #define M6812_OP_LEAS (0x1b) | |
422 | #define M6812_OP_PSHX (0x34) | |
423 | #define M6812_OP_PSHY (0x35) | |
908f682f SC |
424 | |
425 | /* Operand extraction. */ | |
426 | #define OP_DIRECT (0x100) /* 8-byte direct addressing. */ | |
427 | #define OP_IMM_LOW (0x200) /* Low part of 16-bit constant/address. */ | |
428 | #define OP_IMM_HIGH (0x300) /* High part of 16-bit constant/address. */ | |
429 | #define OP_PBYTE (0x400) /* 68HC12 indexed operand. */ | |
430 | ||
431 | /* Identification of the sequence. */ | |
432 | enum m6811_seq_type | |
433 | { | |
434 | P_LAST = 0, | |
435 | P_SAVE_REG, /* Save a register on the stack. */ | |
436 | P_SET_FRAME, /* Setup the frame pointer. */ | |
437 | P_LOCAL_1, /* Allocate 1 byte for locals. */ | |
438 | P_LOCAL_2, /* Allocate 2 bytes for locals. */ | |
439 | P_LOCAL_N /* Allocate N bytes for locals. */ | |
440 | }; | |
441 | ||
442 | struct insn_sequence { | |
443 | enum m6811_seq_type type; | |
444 | unsigned length; | |
445 | unsigned short code[MAX_CODES]; | |
446 | }; | |
447 | ||
448 | /* Sequence of instructions in the 68HC11 function prologue. */ | |
449 | static struct insn_sequence m6811_prologue[] = { | |
450 | /* Sequences to save a soft-register. */ | |
451 | { P_SAVE_REG, 3, { M6811_OP_LDX, OP_DIRECT, | |
452 | M6811_OP_PSHX } }, | |
453 | { P_SAVE_REG, 5, { M6811_OP_PAGE2, M6811_OP_LDX, OP_DIRECT, | |
454 | M6811_OP_PAGE2, M6811_OP_PSHX } }, | |
b94a41a1 SC |
455 | { P_SAVE_REG, 4, { M6811_OP_LDX_EXT, OP_IMM_HIGH, OP_IMM_LOW, |
456 | M6811_OP_PSHX } }, | |
457 | { P_SAVE_REG, 6, { M6811_OP_PAGE2, M6811_OP_LDX_EXT, OP_IMM_HIGH, OP_IMM_LOW, | |
458 | M6811_OP_PAGE2, M6811_OP_PSHX } }, | |
908f682f SC |
459 | |
460 | /* Sequences to allocate local variables. */ | |
461 | { P_LOCAL_N, 7, { M6811_OP_TSX, | |
462 | M6811_OP_XGDX, | |
463 | M6811_OP_ADDD, OP_IMM_HIGH, OP_IMM_LOW, | |
464 | M6811_OP_XGDX, | |
465 | M6811_OP_TXS } }, | |
466 | { P_LOCAL_N, 11, { M6811_OP_PAGE2, M6811_OP_TSX, | |
467 | M6811_OP_PAGE2, M6811_OP_XGDX, | |
468 | M6811_OP_ADDD, OP_IMM_HIGH, OP_IMM_LOW, | |
469 | M6811_OP_PAGE2, M6811_OP_XGDX, | |
470 | M6811_OP_PAGE2, M6811_OP_TXS } }, | |
471 | { P_LOCAL_1, 1, { M6811_OP_DES } }, | |
472 | { P_LOCAL_2, 1, { M6811_OP_PSHX } }, | |
473 | { P_LOCAL_2, 2, { M6811_OP_PAGE2, M6811_OP_PSHX } }, | |
474 | ||
475 | /* Initialize the frame pointer. */ | |
476 | { P_SET_FRAME, 2, { M6811_OP_STS, OP_DIRECT } }, | |
b94a41a1 | 477 | { P_SET_FRAME, 3, { M6811_OP_STS_EXT, OP_IMM_HIGH, OP_IMM_LOW } }, |
908f682f SC |
478 | { P_LAST, 0, { 0 } } |
479 | }; | |
480 | ||
481 | ||
482 | /* Sequence of instructions in the 68HC12 function prologue. */ | |
483 | static struct insn_sequence m6812_prologue[] = { | |
484 | { P_SAVE_REG, 5, { M6812_OP_PAGE2, M6812_OP_MOVW, M6812_PB_PSHW, | |
485 | OP_IMM_HIGH, OP_IMM_LOW } }, | |
b94a41a1 SC |
486 | { P_SET_FRAME, 2, { M6812_OP_STS, OP_DIRECT } }, |
487 | { P_SET_FRAME, 3, { M6812_OP_STS_EXT, OP_IMM_HIGH, OP_IMM_LOW } }, | |
908f682f | 488 | { P_LOCAL_N, 2, { M6812_OP_LEAS, OP_PBYTE } }, |
ffe1f3ee SC |
489 | { P_LOCAL_2, 1, { M6812_OP_PSHX } }, |
490 | { P_LOCAL_2, 1, { M6812_OP_PSHY } }, | |
908f682f SC |
491 | { P_LAST, 0 } |
492 | }; | |
493 | ||
494 | ||
495 | /* Analyze the sequence of instructions starting at the given address. | |
496 | Returns a pointer to the sequence when it is recognized and | |
c8a7f6ac | 497 | the optional value (constant/address) associated with it. */ |
908f682f | 498 | static struct insn_sequence * |
e17a4113 UW |
499 | m68hc11_analyze_instruction (struct gdbarch *gdbarch, |
500 | struct insn_sequence *seq, CORE_ADDR pc, | |
908f682f SC |
501 | CORE_ADDR *val) |
502 | { | |
e17a4113 | 503 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
908f682f SC |
504 | unsigned char buffer[MAX_CODES]; |
505 | unsigned bufsize; | |
506 | unsigned j; | |
507 | CORE_ADDR cur_val; | |
508 | short v = 0; | |
509 | ||
510 | bufsize = 0; | |
511 | for (; seq->type != P_LAST; seq++) | |
512 | { | |
513 | cur_val = 0; | |
514 | for (j = 0; j < seq->length; j++) | |
515 | { | |
516 | if (bufsize < j + 1) | |
517 | { | |
c8a7f6ac | 518 | buffer[bufsize] = read_memory_unsigned_integer (pc + bufsize, |
e17a4113 | 519 | 1, byte_order); |
908f682f SC |
520 | bufsize++; |
521 | } | |
522 | /* Continue while we match the opcode. */ | |
523 | if (seq->code[j] == buffer[j]) | |
524 | continue; | |
525 | ||
526 | if ((seq->code[j] & 0xf00) == 0) | |
527 | break; | |
528 | ||
529 | /* Extract a sequence parameter (address or constant). */ | |
530 | switch (seq->code[j]) | |
531 | { | |
532 | case OP_DIRECT: | |
533 | cur_val = (CORE_ADDR) buffer[j]; | |
534 | break; | |
535 | ||
536 | case OP_IMM_HIGH: | |
537 | cur_val = cur_val & 0x0ff; | |
538 | cur_val |= (buffer[j] << 8); | |
539 | break; | |
540 | ||
541 | case OP_IMM_LOW: | |
542 | cur_val &= 0x0ff00; | |
543 | cur_val |= buffer[j]; | |
544 | break; | |
545 | ||
546 | case OP_PBYTE: | |
547 | if ((buffer[j] & 0xE0) == 0x80) | |
548 | { | |
549 | v = buffer[j] & 0x1f; | |
550 | if (v & 0x10) | |
551 | v |= 0xfff0; | |
552 | } | |
553 | else if ((buffer[j] & 0xfe) == 0xf0) | |
554 | { | |
e17a4113 | 555 | v = read_memory_unsigned_integer (pc + j + 1, 1, byte_order); |
908f682f SC |
556 | if (buffer[j] & 1) |
557 | v |= 0xff00; | |
558 | } | |
559 | else if (buffer[j] == 0xf2) | |
560 | { | |
e17a4113 | 561 | v = read_memory_unsigned_integer (pc + j + 1, 2, byte_order); |
908f682f SC |
562 | } |
563 | cur_val = v; | |
564 | break; | |
565 | } | |
566 | } | |
567 | ||
568 | /* We have a full match. */ | |
569 | if (j == seq->length) | |
570 | { | |
571 | *val = cur_val; | |
908f682f SC |
572 | return seq; |
573 | } | |
574 | } | |
575 | return 0; | |
576 | } | |
577 | ||
7df11f59 SC |
578 | /* Return the instruction that the function at the PC is using. */ |
579 | static enum insn_return_kind | |
580 | m68hc11_get_return_insn (CORE_ADDR pc) | |
581 | { | |
7cbd4a93 | 582 | struct bound_minimal_symbol sym; |
7df11f59 SC |
583 | |
584 | /* A flag indicating that this is a STO_M68HC12_FAR or STO_M68HC12_INTERRUPT | |
585 | function is stored by elfread.c in the high bit of the info field. | |
586 | Use this to decide which instruction the function uses to return. */ | |
587 | sym = lookup_minimal_symbol_by_pc (pc); | |
7cbd4a93 | 588 | if (sym.minsym == 0) |
7df11f59 SC |
589 | return RETURN_RTS; |
590 | ||
7cbd4a93 | 591 | if (MSYMBOL_IS_RTC (sym.minsym)) |
7df11f59 | 592 | return RETURN_RTC; |
7cbd4a93 | 593 | else if (MSYMBOL_IS_RTI (sym.minsym)) |
7df11f59 SC |
594 | return RETURN_RTI; |
595 | else | |
596 | return RETURN_RTS; | |
597 | } | |
598 | ||
78073dd8 AC |
599 | /* Analyze the function prologue to find some information |
600 | about the function: | |
601 | - the PC of the first line (for m68hc11_skip_prologue) | |
602 | - the offset of the previous frame saved address (from current frame) | |
603 | - the soft registers which are pushed. */ | |
1ea653ae | 604 | static CORE_ADDR |
be8626e0 MD |
605 | m68hc11_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, |
606 | CORE_ADDR current_pc, struct m68hc11_unwind_cache *info) | |
78073dd8 | 607 | { |
1ea653ae | 608 | LONGEST save_addr; |
78073dd8 | 609 | CORE_ADDR func_end; |
78073dd8 AC |
610 | int size; |
611 | int found_frame_point; | |
82c230c2 | 612 | int saved_reg; |
908f682f SC |
613 | int done = 0; |
614 | struct insn_sequence *seq_table; | |
1ea653ae SC |
615 | |
616 | info->size = 0; | |
617 | info->sp_offset = 0; | |
618 | if (pc >= current_pc) | |
619 | return current_pc; | |
620 | ||
78073dd8 AC |
621 | size = 0; |
622 | ||
82c230c2 | 623 | m68hc11_initialize_register_info (); |
1ea653ae | 624 | if (pc == 0) |
78073dd8 | 625 | { |
1ea653ae SC |
626 | info->size = 0; |
627 | return pc; | |
78073dd8 AC |
628 | } |
629 | ||
be8626e0 | 630 | seq_table = gdbarch_tdep (gdbarch)->prologue; |
908f682f | 631 | |
78073dd8 AC |
632 | /* The 68hc11 stack is as follows: |
633 | ||
634 | ||
635 | | | | |
636 | +-----------+ | |
637 | | | | |
638 | | args | | |
639 | | | | |
640 | +-----------+ | |
641 | | PC-return | | |
642 | +-----------+ | |
643 | | Old frame | | |
644 | +-----------+ | |
645 | | | | |
646 | | Locals | | |
647 | | | | |
648 | +-----------+ <--- current frame | |
649 | | | | |
650 | ||
651 | With most processors (like 68K) the previous frame can be computed | |
652 | easily because it is always at a fixed offset (see link/unlink). | |
653 | That is, locals are accessed with negative offsets, arguments are | |
654 | accessed with positive ones. Since 68hc11 only supports offsets | |
655 | in the range [0..255], the frame is defined at the bottom of | |
656 | locals (see picture). | |
657 | ||
658 | The purpose of the analysis made here is to find out the size | |
659 | of locals in this function. An alternative to this is to use | |
660 | DWARF2 info. This would be better but I don't know how to | |
661 | access dwarf2 debug from this function. | |
662 | ||
663 | Walk from the function entry point to the point where we save | |
664 | the frame. While walking instructions, compute the size of bytes | |
665 | which are pushed. This gives us the index to access the previous | |
666 | frame. | |
667 | ||
668 | We limit the search to 128 bytes so that the algorithm is bounded | |
669 | in case of random and wrong code. We also stop and abort if | |
670 | we find an instruction which is not supposed to appear in the | |
025bb325 MS |
671 | prologue (as generated by gcc 2.95, 2.96). */ |
672 | ||
78073dd8 | 673 | func_end = pc + 128; |
78073dd8 | 674 | found_frame_point = 0; |
1ea653ae SC |
675 | info->size = 0; |
676 | save_addr = 0; | |
908f682f | 677 | while (!done && pc + 2 < func_end) |
78073dd8 | 678 | { |
908f682f SC |
679 | struct insn_sequence *seq; |
680 | CORE_ADDR val; | |
1ea653ae | 681 | |
e17a4113 | 682 | seq = m68hc11_analyze_instruction (gdbarch, seq_table, pc, &val); |
908f682f SC |
683 | if (seq == 0) |
684 | break; | |
78073dd8 | 685 | |
c8a7f6ac SC |
686 | /* If we are within the instruction group, we can't advance the |
687 | pc nor the stack offset. Otherwise the caller's stack computed | |
688 | from the current stack can be wrong. */ | |
689 | if (pc + seq->length > current_pc) | |
690 | break; | |
691 | ||
692 | pc = pc + seq->length; | |
908f682f | 693 | if (seq->type == P_SAVE_REG) |
78073dd8 | 694 | { |
908f682f SC |
695 | if (found_frame_point) |
696 | { | |
697 | saved_reg = m68hc11_which_soft_register (val); | |
698 | if (saved_reg < 0) | |
699 | break; | |
78073dd8 | 700 | |
908f682f | 701 | save_addr -= 2; |
ff1e98b9 SC |
702 | if (info->saved_regs) |
703 | info->saved_regs[saved_reg].addr = save_addr; | |
908f682f SC |
704 | } |
705 | else | |
706 | { | |
707 | size += 2; | |
708 | } | |
78073dd8 | 709 | } |
908f682f | 710 | else if (seq->type == P_SET_FRAME) |
78073dd8 AC |
711 | { |
712 | found_frame_point = 1; | |
1ea653ae | 713 | info->size = size; |
78073dd8 | 714 | } |
908f682f | 715 | else if (seq->type == P_LOCAL_1) |
78073dd8 | 716 | { |
6148eca7 SC |
717 | size += 1; |
718 | } | |
908f682f | 719 | else if (seq->type == P_LOCAL_2) |
78073dd8 | 720 | { |
908f682f | 721 | size += 2; |
78073dd8 | 722 | } |
908f682f | 723 | else if (seq->type == P_LOCAL_N) |
78073dd8 | 724 | { |
908f682f SC |
725 | /* Stack pointer is decremented for the allocation. */ |
726 | if (val & 0x8000) | |
727 | size -= (int) (val) | 0xffff0000; | |
728 | else | |
729 | size -= val; | |
78073dd8 AC |
730 | } |
731 | } | |
1ea653ae SC |
732 | if (found_frame_point == 0) |
733 | info->sp_offset = size; | |
734 | else | |
735 | info->sp_offset = -1; | |
736 | return pc; | |
78073dd8 AC |
737 | } |
738 | ||
82c230c2 | 739 | static CORE_ADDR |
6093d2eb | 740 | m68hc11_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
78073dd8 AC |
741 | { |
742 | CORE_ADDR func_addr, func_end; | |
743 | struct symtab_and_line sal; | |
1ea653ae | 744 | struct m68hc11_unwind_cache tmp_cache = { 0 }; |
78073dd8 | 745 | |
82c230c2 SC |
746 | /* If we have line debugging information, then the end of the |
747 | prologue should be the first assembly instruction of the | |
78073dd8 AC |
748 | first source line. */ |
749 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
750 | { | |
751 | sal = find_pc_line (func_addr, 0); | |
752 | if (sal.end && sal.end < func_end) | |
753 | return sal.end; | |
754 | } | |
755 | ||
be8626e0 | 756 | pc = m68hc11_scan_prologue (gdbarch, pc, (CORE_ADDR) -1, &tmp_cache); |
78073dd8 AC |
757 | return pc; |
758 | } | |
759 | ||
1ea653ae SC |
760 | static CORE_ADDR |
761 | m68hc11_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
762 | { | |
763 | ULONGEST pc; | |
764 | ||
025bb325 MS |
765 | pc = frame_unwind_register_unsigned (next_frame, |
766 | gdbarch_pc_regnum (gdbarch)); | |
1ea653ae SC |
767 | return pc; |
768 | } | |
769 | ||
770 | /* Put here the code to store, into fi->saved_regs, the addresses of | |
771 | the saved registers of frame described by FRAME_INFO. This | |
772 | includes special registers such as pc and fp saved in special ways | |
773 | in the stack frame. sp is even more special: the address we return | |
025bb325 | 774 | for it IS the sp for the next frame. */ |
1ea653ae | 775 | |
63807e1d | 776 | static struct m68hc11_unwind_cache * |
94afd7a6 | 777 | m68hc11_frame_unwind_cache (struct frame_info *this_frame, |
1ea653ae SC |
778 | void **this_prologue_cache) |
779 | { | |
94afd7a6 | 780 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1ea653ae SC |
781 | ULONGEST prev_sp; |
782 | ULONGEST this_base; | |
783 | struct m68hc11_unwind_cache *info; | |
784 | CORE_ADDR current_pc; | |
785 | int i; | |
786 | ||
787 | if ((*this_prologue_cache)) | |
9a3c8263 | 788 | return (struct m68hc11_unwind_cache *) (*this_prologue_cache); |
1ea653ae SC |
789 | |
790 | info = FRAME_OBSTACK_ZALLOC (struct m68hc11_unwind_cache); | |
791 | (*this_prologue_cache) = info; | |
94afd7a6 | 792 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
1ea653ae | 793 | |
94afd7a6 | 794 | info->pc = get_frame_func (this_frame); |
1ea653ae SC |
795 | |
796 | info->size = 0; | |
797 | info->return_kind = m68hc11_get_return_insn (info->pc); | |
798 | ||
799 | /* The SP was moved to the FP. This indicates that a new frame | |
800 | was created. Get THIS frame's FP value by unwinding it from | |
801 | the next frame. */ | |
94afd7a6 | 802 | this_base = get_frame_register_unsigned (this_frame, SOFT_FP_REGNUM); |
1ea653ae SC |
803 | if (this_base == 0) |
804 | { | |
805 | info->base = 0; | |
806 | return info; | |
807 | } | |
808 | ||
94afd7a6 | 809 | current_pc = get_frame_pc (this_frame); |
1ea653ae | 810 | if (info->pc != 0) |
be8626e0 | 811 | m68hc11_scan_prologue (gdbarch, info->pc, current_pc, info); |
1ea653ae SC |
812 | |
813 | info->saved_regs[HARD_PC_REGNUM].addr = info->size; | |
814 | ||
815 | if (info->sp_offset != (CORE_ADDR) -1) | |
816 | { | |
817 | info->saved_regs[HARD_PC_REGNUM].addr = info->sp_offset; | |
94afd7a6 | 818 | this_base = get_frame_register_unsigned (this_frame, HARD_SP_REGNUM); |
1ea653ae | 819 | prev_sp = this_base + info->sp_offset + 2; |
be8626e0 | 820 | this_base += STACK_CORRECTION (gdbarch); |
1ea653ae SC |
821 | } |
822 | else | |
823 | { | |
824 | /* The FP points at the last saved register. Adjust the FP back | |
825 | to before the first saved register giving the SP. */ | |
826 | prev_sp = this_base + info->size + 2; | |
827 | ||
be8626e0 | 828 | this_base += STACK_CORRECTION (gdbarch); |
1ea653ae SC |
829 | if (soft_regs[SOFT_FP_REGNUM].name) |
830 | info->saved_regs[SOFT_FP_REGNUM].addr = info->size - 2; | |
831 | } | |
832 | ||
833 | if (info->return_kind == RETURN_RTC) | |
834 | { | |
835 | prev_sp += 1; | |
836 | info->saved_regs[HARD_PAGE_REGNUM].addr = info->size; | |
837 | info->saved_regs[HARD_PC_REGNUM].addr = info->size + 1; | |
838 | } | |
839 | else if (info->return_kind == RETURN_RTI) | |
840 | { | |
841 | prev_sp += 7; | |
842 | info->saved_regs[HARD_CCR_REGNUM].addr = info->size; | |
843 | info->saved_regs[HARD_D_REGNUM].addr = info->size + 1; | |
844 | info->saved_regs[HARD_X_REGNUM].addr = info->size + 3; | |
845 | info->saved_regs[HARD_Y_REGNUM].addr = info->size + 5; | |
846 | info->saved_regs[HARD_PC_REGNUM].addr = info->size + 7; | |
847 | } | |
848 | ||
849 | /* Add 1 here to adjust for the post-decrement nature of the push | |
025bb325 | 850 | instruction. */ |
1ea653ae SC |
851 | info->prev_sp = prev_sp; |
852 | ||
853 | info->base = this_base; | |
854 | ||
855 | /* Adjust all the saved registers so that they contain addresses and not | |
856 | offsets. */ | |
f57d151a | 857 | for (i = 0; |
be8626e0 MD |
858 | i < gdbarch_num_regs (gdbarch) |
859 | + gdbarch_num_pseudo_regs (gdbarch) - 1; | |
f57d151a | 860 | i++) |
1ea653ae SC |
861 | if (trad_frame_addr_p (info->saved_regs, i)) |
862 | { | |
863 | info->saved_regs[i].addr += this_base; | |
864 | } | |
865 | ||
866 | /* The previous frame's SP needed to be computed. Save the computed | |
867 | value. */ | |
868 | trad_frame_set_value (info->saved_regs, HARD_SP_REGNUM, info->prev_sp); | |
869 | ||
870 | return info; | |
871 | } | |
872 | ||
873 | /* Given a GDB frame, determine the address of the calling function's | |
874 | frame. This will be used to create a new GDB frame struct. */ | |
875 | ||
876 | static void | |
94afd7a6 | 877 | m68hc11_frame_this_id (struct frame_info *this_frame, |
1ea653ae SC |
878 | void **this_prologue_cache, |
879 | struct frame_id *this_id) | |
880 | { | |
881 | struct m68hc11_unwind_cache *info | |
94afd7a6 | 882 | = m68hc11_frame_unwind_cache (this_frame, this_prologue_cache); |
1ea653ae SC |
883 | CORE_ADDR base; |
884 | CORE_ADDR func; | |
885 | struct frame_id id; | |
886 | ||
887 | /* The FUNC is easy. */ | |
94afd7a6 | 888 | func = get_frame_func (this_frame); |
1ea653ae | 889 | |
1ea653ae SC |
890 | /* Hopefully the prologue analysis either correctly determined the |
891 | frame's base (which is the SP from the previous frame), or set | |
892 | that base to "NULL". */ | |
893 | base = info->prev_sp; | |
894 | if (base == 0) | |
895 | return; | |
896 | ||
897 | id = frame_id_build (base, func); | |
1ea653ae SC |
898 | (*this_id) = id; |
899 | } | |
900 | ||
94afd7a6 UW |
901 | static struct value * |
902 | m68hc11_frame_prev_register (struct frame_info *this_frame, | |
903 | void **this_prologue_cache, int regnum) | |
1ea653ae | 904 | { |
94afd7a6 | 905 | struct value *value; |
1ea653ae | 906 | struct m68hc11_unwind_cache *info |
94afd7a6 | 907 | = m68hc11_frame_unwind_cache (this_frame, this_prologue_cache); |
1ea653ae | 908 | |
94afd7a6 | 909 | value = trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
1ea653ae | 910 | |
94afd7a6 UW |
911 | /* Take into account the 68HC12 specific call (PC + page). */ |
912 | if (regnum == HARD_PC_REGNUM | |
913 | && info->return_kind == RETURN_RTC | |
914 | && USE_PAGE_REGISTER (get_frame_arch (this_frame))) | |
1ea653ae | 915 | { |
94afd7a6 UW |
916 | CORE_ADDR pc = value_as_long (value); |
917 | if (pc >= 0x08000 && pc < 0x0c000) | |
1ea653ae | 918 | { |
1ea653ae SC |
919 | CORE_ADDR page; |
920 | ||
94afd7a6 UW |
921 | release_value (value); |
922 | value_free (value); | |
923 | ||
924 | value = trad_frame_get_prev_register (this_frame, info->saved_regs, | |
925 | HARD_PAGE_REGNUM); | |
926 | page = value_as_long (value); | |
927 | release_value (value); | |
928 | value_free (value); | |
929 | ||
930 | pc -= 0x08000; | |
931 | pc += ((page & 0x0ff) << 14); | |
932 | pc += 0x1000000; | |
933 | ||
934 | return frame_unwind_got_constant (this_frame, regnum, pc); | |
1ea653ae SC |
935 | } |
936 | } | |
94afd7a6 UW |
937 | |
938 | return value; | |
1ea653ae SC |
939 | } |
940 | ||
941 | static const struct frame_unwind m68hc11_frame_unwind = { | |
942 | NORMAL_FRAME, | |
8fbca658 | 943 | default_frame_unwind_stop_reason, |
1ea653ae | 944 | m68hc11_frame_this_id, |
94afd7a6 UW |
945 | m68hc11_frame_prev_register, |
946 | NULL, | |
947 | default_frame_sniffer | |
1ea653ae SC |
948 | }; |
949 | ||
1ea653ae | 950 | static CORE_ADDR |
94afd7a6 | 951 | m68hc11_frame_base_address (struct frame_info *this_frame, void **this_cache) |
1ea653ae SC |
952 | { |
953 | struct m68hc11_unwind_cache *info | |
94afd7a6 | 954 | = m68hc11_frame_unwind_cache (this_frame, this_cache); |
1ea653ae SC |
955 | |
956 | return info->base; | |
957 | } | |
958 | ||
959 | static CORE_ADDR | |
94afd7a6 | 960 | m68hc11_frame_args_address (struct frame_info *this_frame, void **this_cache) |
1ea653ae SC |
961 | { |
962 | CORE_ADDR addr; | |
963 | struct m68hc11_unwind_cache *info | |
94afd7a6 | 964 | = m68hc11_frame_unwind_cache (this_frame, this_cache); |
1ea653ae SC |
965 | |
966 | addr = info->base + info->size; | |
967 | if (info->return_kind == RETURN_RTC) | |
968 | addr += 1; | |
969 | else if (info->return_kind == RETURN_RTI) | |
970 | addr += 7; | |
971 | ||
972 | return addr; | |
973 | } | |
974 | ||
975 | static const struct frame_base m68hc11_frame_base = { | |
976 | &m68hc11_frame_unwind, | |
977 | m68hc11_frame_base_address, | |
978 | m68hc11_frame_base_address, | |
979 | m68hc11_frame_args_address | |
980 | }; | |
981 | ||
982 | static CORE_ADDR | |
983 | m68hc11_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
984 | { | |
985 | ULONGEST sp; | |
11411de3 | 986 | sp = frame_unwind_register_unsigned (next_frame, HARD_SP_REGNUM); |
1ea653ae SC |
987 | return sp; |
988 | } | |
989 | ||
94afd7a6 UW |
990 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy |
991 | frame. The frame ID's base needs to match the TOS value saved by | |
992 | save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */ | |
1ea653ae SC |
993 | |
994 | static struct frame_id | |
94afd7a6 | 995 | m68hc11_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
1ea653ae SC |
996 | { |
997 | ULONGEST tos; | |
94afd7a6 | 998 | CORE_ADDR pc = get_frame_pc (this_frame); |
1ea653ae | 999 | |
94afd7a6 | 1000 | tos = get_frame_register_unsigned (this_frame, SOFT_FP_REGNUM); |
1ea653ae SC |
1001 | tos += 2; |
1002 | return frame_id_build (tos, pc); | |
1003 | } | |
78073dd8 | 1004 | |
e286caf2 SC |
1005 | \f |
1006 | /* Get and print the register from the given frame. */ | |
78073dd8 | 1007 | static void |
e286caf2 SC |
1008 | m68hc11_print_register (struct gdbarch *gdbarch, struct ui_file *file, |
1009 | struct frame_info *frame, int regno) | |
78073dd8 | 1010 | { |
e286caf2 SC |
1011 | LONGEST rval; |
1012 | ||
1013 | if (regno == HARD_PC_REGNUM || regno == HARD_SP_REGNUM | |
1014 | || regno == SOFT_FP_REGNUM || regno == M68HC12_HARD_PC_REGNUM) | |
7f5f525d | 1015 | rval = get_frame_register_unsigned (frame, regno); |
e286caf2 | 1016 | else |
7f5f525d | 1017 | rval = get_frame_register_signed (frame, regno); |
e286caf2 SC |
1018 | |
1019 | if (regno == HARD_A_REGNUM || regno == HARD_B_REGNUM | |
1020 | || regno == HARD_CCR_REGNUM || regno == HARD_PAGE_REGNUM) | |
7df11f59 | 1021 | { |
e286caf2 SC |
1022 | fprintf_filtered (file, "0x%02x ", (unsigned char) rval); |
1023 | if (regno != HARD_CCR_REGNUM) | |
1024 | print_longest (file, 'd', 1, rval); | |
7df11f59 | 1025 | } |
e286caf2 SC |
1026 | else |
1027 | { | |
1028 | if (regno == HARD_PC_REGNUM && gdbarch_tdep (gdbarch)->use_page_register) | |
1029 | { | |
1030 | ULONGEST page; | |
7df11f59 | 1031 | |
7f5f525d | 1032 | page = get_frame_register_unsigned (frame, HARD_PAGE_REGNUM); |
e286caf2 SC |
1033 | fprintf_filtered (file, "0x%02x:%04x ", (unsigned) page, |
1034 | (unsigned) rval); | |
1035 | } | |
1036 | else | |
1037 | { | |
1038 | fprintf_filtered (file, "0x%04x ", (unsigned) rval); | |
1039 | if (regno != HARD_PC_REGNUM && regno != HARD_SP_REGNUM | |
1040 | && regno != SOFT_FP_REGNUM && regno != M68HC12_HARD_PC_REGNUM) | |
1041 | print_longest (file, 'd', 1, rval); | |
1042 | } | |
1043 | } | |
1044 | ||
1045 | if (regno == HARD_CCR_REGNUM) | |
78073dd8 | 1046 | { |
e286caf2 SC |
1047 | /* CCR register */ |
1048 | int C, Z, N, V; | |
1049 | unsigned char l = rval & 0xff; | |
1050 | ||
1051 | fprintf_filtered (file, "%c%c%c%c%c%c%c%c ", | |
1052 | l & M6811_S_BIT ? 'S' : '-', | |
1053 | l & M6811_X_BIT ? 'X' : '-', | |
1054 | l & M6811_H_BIT ? 'H' : '-', | |
1055 | l & M6811_I_BIT ? 'I' : '-', | |
1056 | l & M6811_N_BIT ? 'N' : '-', | |
1057 | l & M6811_Z_BIT ? 'Z' : '-', | |
1058 | l & M6811_V_BIT ? 'V' : '-', | |
1059 | l & M6811_C_BIT ? 'C' : '-'); | |
1060 | N = (l & M6811_N_BIT) != 0; | |
1061 | Z = (l & M6811_Z_BIT) != 0; | |
1062 | V = (l & M6811_V_BIT) != 0; | |
1063 | C = (l & M6811_C_BIT) != 0; | |
1064 | ||
025bb325 | 1065 | /* Print flags following the h8300. */ |
e286caf2 SC |
1066 | if ((C | Z) == 0) |
1067 | fprintf_filtered (file, "u> "); | |
1068 | else if ((C | Z) == 1) | |
1069 | fprintf_filtered (file, "u<= "); | |
1070 | else if (C == 0) | |
1071 | fprintf_filtered (file, "u< "); | |
1072 | ||
1073 | if (Z == 0) | |
1074 | fprintf_filtered (file, "!= "); | |
1075 | else | |
1076 | fprintf_filtered (file, "== "); | |
1077 | ||
1078 | if ((N ^ V) == 0) | |
1079 | fprintf_filtered (file, ">= "); | |
1080 | else | |
1081 | fprintf_filtered (file, "< "); | |
1082 | ||
1083 | if ((Z | (N ^ V)) == 0) | |
1084 | fprintf_filtered (file, "> "); | |
78073dd8 | 1085 | else |
e286caf2 | 1086 | fprintf_filtered (file, "<= "); |
78073dd8 | 1087 | } |
e286caf2 SC |
1088 | } |
1089 | ||
1090 | /* Same as 'info reg' but prints the registers in a different way. */ | |
1091 | static void | |
1092 | m68hc11_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, | |
1093 | struct frame_info *frame, int regno, int cpregs) | |
1094 | { | |
1095 | if (regno >= 0) | |
1096 | { | |
1097 | const char *name = gdbarch_register_name (gdbarch, regno); | |
1098 | ||
1099 | if (!name || !*name) | |
1100 | return; | |
1101 | ||
1102 | fprintf_filtered (file, "%-10s ", name); | |
1103 | m68hc11_print_register (gdbarch, file, frame, regno); | |
1104 | fprintf_filtered (file, "\n"); | |
1105 | } | |
1106 | else | |
1107 | { | |
1108 | int i, nr; | |
1109 | ||
1110 | fprintf_filtered (file, "PC="); | |
1111 | m68hc11_print_register (gdbarch, file, frame, HARD_PC_REGNUM); | |
1112 | ||
1113 | fprintf_filtered (file, " SP="); | |
1114 | m68hc11_print_register (gdbarch, file, frame, HARD_SP_REGNUM); | |
1115 | ||
1116 | fprintf_filtered (file, " FP="); | |
1117 | m68hc11_print_register (gdbarch, file, frame, SOFT_FP_REGNUM); | |
1118 | ||
1119 | fprintf_filtered (file, "\nCCR="); | |
1120 | m68hc11_print_register (gdbarch, file, frame, HARD_CCR_REGNUM); | |
1121 | ||
1122 | fprintf_filtered (file, "\nD="); | |
1123 | m68hc11_print_register (gdbarch, file, frame, HARD_D_REGNUM); | |
1124 | ||
1125 | fprintf_filtered (file, " X="); | |
1126 | m68hc11_print_register (gdbarch, file, frame, HARD_X_REGNUM); | |
1127 | ||
1128 | fprintf_filtered (file, " Y="); | |
1129 | m68hc11_print_register (gdbarch, file, frame, HARD_Y_REGNUM); | |
1130 | ||
1131 | if (gdbarch_tdep (gdbarch)->use_page_register) | |
1132 | { | |
1133 | fprintf_filtered (file, "\nPage="); | |
1134 | m68hc11_print_register (gdbarch, file, frame, HARD_PAGE_REGNUM); | |
1135 | } | |
1136 | fprintf_filtered (file, "\n"); | |
1137 | ||
1138 | nr = 0; | |
1139 | for (i = SOFT_D1_REGNUM; i < M68HC11_ALL_REGS; i++) | |
1140 | { | |
1141 | /* Skip registers which are not defined in the symbol table. */ | |
1142 | if (soft_regs[i].name == 0) | |
1143 | continue; | |
1144 | ||
1145 | fprintf_filtered (file, "D%d=", i - SOFT_D1_REGNUM + 1); | |
1146 | m68hc11_print_register (gdbarch, file, frame, i); | |
1147 | nr++; | |
1148 | if ((nr % 8) == 7) | |
1149 | fprintf_filtered (file, "\n"); | |
1150 | else | |
1151 | fprintf_filtered (file, " "); | |
1152 | } | |
1153 | if (nr && (nr % 8) != 7) | |
1154 | fprintf_filtered (file, "\n"); | |
1155 | } | |
1156 | } | |
1157 | ||
82c230c2 | 1158 | static CORE_ADDR |
7d9b040b | 1159 | m68hc11_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
3dc990bf SC |
1160 | struct regcache *regcache, CORE_ADDR bp_addr, |
1161 | int nargs, struct value **args, CORE_ADDR sp, | |
1162 | int struct_return, CORE_ADDR struct_addr) | |
78073dd8 | 1163 | { |
e17a4113 | 1164 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
82c230c2 SC |
1165 | int argnum; |
1166 | int first_stack_argnum; | |
82c230c2 | 1167 | struct type *type; |
948f8e3d | 1168 | const gdb_byte *val; |
e362b510 | 1169 | gdb_byte buf[2]; |
82c230c2 | 1170 | |
82c230c2 SC |
1171 | first_stack_argnum = 0; |
1172 | if (struct_return) | |
1173 | { | |
ff1e98b9 | 1174 | regcache_cooked_write_unsigned (regcache, HARD_D_REGNUM, struct_addr); |
82c230c2 SC |
1175 | } |
1176 | else if (nargs > 0) | |
1177 | { | |
4991999e | 1178 | type = value_type (args[0]); |
3dc990bf | 1179 | |
82c230c2 | 1180 | /* First argument is passed in D and X registers. */ |
744a8059 | 1181 | if (TYPE_LENGTH (type) <= 4) |
82c230c2 | 1182 | { |
3dc990bf SC |
1183 | ULONGEST v; |
1184 | ||
e17a4113 | 1185 | v = extract_unsigned_integer (value_contents (args[0]), |
744a8059 | 1186 | TYPE_LENGTH (type), byte_order); |
82c230c2 | 1187 | first_stack_argnum = 1; |
3dc990bf SC |
1188 | |
1189 | regcache_cooked_write_unsigned (regcache, HARD_D_REGNUM, v); | |
744a8059 | 1190 | if (TYPE_LENGTH (type) > 2) |
82c230c2 SC |
1191 | { |
1192 | v >>= 16; | |
3dc990bf | 1193 | regcache_cooked_write_unsigned (regcache, HARD_X_REGNUM, v); |
82c230c2 SC |
1194 | } |
1195 | } | |
1196 | } | |
82c230c2 | 1197 | |
3dc990bf | 1198 | for (argnum = nargs - 1; argnum >= first_stack_argnum; argnum--) |
82c230c2 | 1199 | { |
4991999e | 1200 | type = value_type (args[argnum]); |
82c230c2 | 1201 | |
744a8059 | 1202 | if (TYPE_LENGTH (type) & 1) |
22df305e | 1203 | { |
948f8e3d | 1204 | static gdb_byte zero = 0; |
22df305e | 1205 | |
3dc990bf SC |
1206 | sp--; |
1207 | write_memory (sp, &zero, 1); | |
22df305e | 1208 | } |
948f8e3d | 1209 | val = value_contents (args[argnum]); |
744a8059 SP |
1210 | sp -= TYPE_LENGTH (type); |
1211 | write_memory (sp, val, TYPE_LENGTH (type)); | |
82c230c2 | 1212 | } |
3dc990bf SC |
1213 | |
1214 | /* Store return address. */ | |
1215 | sp -= 2; | |
e17a4113 | 1216 | store_unsigned_integer (buf, 2, byte_order, bp_addr); |
3dc990bf SC |
1217 | write_memory (sp, buf, 2); |
1218 | ||
1219 | /* Finally, update the stack pointer... */ | |
be8626e0 | 1220 | sp -= STACK_CORRECTION (gdbarch); |
3dc990bf SC |
1221 | regcache_cooked_write_unsigned (regcache, HARD_SP_REGNUM, sp); |
1222 | ||
1223 | /* ...and fake a frame pointer. */ | |
1224 | regcache_cooked_write_unsigned (regcache, SOFT_FP_REGNUM, sp); | |
1225 | ||
1226 | /* DWARF2/GCC uses the stack address *before* the function call as a | |
1227 | frame's CFA. */ | |
1228 | return sp + 2; | |
78073dd8 AC |
1229 | } |
1230 | ||
1231 | ||
4db73d49 SC |
1232 | /* Return the GDB type object for the "standard" data type |
1233 | of data in register N. */ | |
1234 | ||
82c230c2 | 1235 | static struct type * |
4db73d49 | 1236 | m68hc11_register_type (struct gdbarch *gdbarch, int reg_nr) |
82c230c2 | 1237 | { |
5706502a SC |
1238 | switch (reg_nr) |
1239 | { | |
1240 | case HARD_PAGE_REGNUM: | |
1241 | case HARD_A_REGNUM: | |
1242 | case HARD_B_REGNUM: | |
1243 | case HARD_CCR_REGNUM: | |
df4df182 | 1244 | return builtin_type (gdbarch)->builtin_uint8; |
5706502a | 1245 | |
548bcbec | 1246 | case M68HC12_HARD_PC_REGNUM: |
df4df182 | 1247 | return builtin_type (gdbarch)->builtin_uint32; |
548bcbec | 1248 | |
5706502a | 1249 | default: |
df4df182 | 1250 | return builtin_type (gdbarch)->builtin_uint16; |
5706502a | 1251 | } |
82c230c2 SC |
1252 | } |
1253 | ||
82c230c2 | 1254 | static void |
4db73d49 | 1255 | m68hc11_store_return_value (struct type *type, struct regcache *regcache, |
948f8e3d | 1256 | const gdb_byte *valbuf) |
82c230c2 | 1257 | { |
22df305e SC |
1258 | int len; |
1259 | ||
1260 | len = TYPE_LENGTH (type); | |
1261 | ||
1262 | /* First argument is passed in D and X registers. */ | |
4db73d49 SC |
1263 | if (len <= 2) |
1264 | regcache_raw_write_part (regcache, HARD_D_REGNUM, 2 - len, len, valbuf); | |
1265 | else if (len <= 4) | |
22df305e | 1266 | { |
4db73d49 SC |
1267 | regcache_raw_write_part (regcache, HARD_X_REGNUM, 4 - len, |
1268 | len - 2, valbuf); | |
948f8e3d | 1269 | regcache_raw_write (regcache, HARD_D_REGNUM, valbuf + (len - 2)); |
22df305e SC |
1270 | } |
1271 | else | |
8a3fe4f8 | 1272 | error (_("return of value > 4 is not supported.")); |
82c230c2 SC |
1273 | } |
1274 | ||
1275 | ||
ef2b8fcd | 1276 | /* Given a return value in `regcache' with a type `type', |
78073dd8 AC |
1277 | extract and copy its value into `valbuf'. */ |
1278 | ||
82c230c2 | 1279 | static void |
ef2b8fcd SC |
1280 | m68hc11_extract_return_value (struct type *type, struct regcache *regcache, |
1281 | void *valbuf) | |
78073dd8 | 1282 | { |
e362b510 | 1283 | gdb_byte buf[M68HC11_REG_SIZE]; |
ef2b8fcd SC |
1284 | |
1285 | regcache_raw_read (regcache, HARD_D_REGNUM, buf); | |
744a8059 | 1286 | switch (TYPE_LENGTH (type)) |
82c230c2 | 1287 | { |
22df305e | 1288 | case 1: |
ef2b8fcd | 1289 | memcpy (valbuf, buf + 1, 1); |
22df305e | 1290 | break; |
ef2b8fcd | 1291 | |
22df305e | 1292 | case 2: |
ef2b8fcd | 1293 | memcpy (valbuf, buf, 2); |
22df305e | 1294 | break; |
ef2b8fcd | 1295 | |
22df305e | 1296 | case 3: |
ef2b8fcd SC |
1297 | memcpy ((char*) valbuf + 1, buf, 2); |
1298 | regcache_raw_read (regcache, HARD_X_REGNUM, buf); | |
1299 | memcpy (valbuf, buf + 1, 1); | |
22df305e | 1300 | break; |
ef2b8fcd | 1301 | |
22df305e | 1302 | case 4: |
ef2b8fcd SC |
1303 | memcpy ((char*) valbuf + 2, buf, 2); |
1304 | regcache_raw_read (regcache, HARD_X_REGNUM, buf); | |
1305 | memcpy (valbuf, buf, 2); | |
22df305e SC |
1306 | break; |
1307 | ||
1308 | default: | |
8a3fe4f8 | 1309 | error (_("bad size for return value")); |
82c230c2 SC |
1310 | } |
1311 | } | |
1312 | ||
63807e1d | 1313 | static enum return_value_convention |
6a3a010b | 1314 | m68hc11_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
1315 | struct type *valtype, struct regcache *regcache, |
1316 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
82c230c2 | 1317 | { |
97092415 AC |
1318 | if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT |
1319 | || TYPE_CODE (valtype) == TYPE_CODE_UNION | |
1320 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY | |
1321 | || TYPE_LENGTH (valtype) > 4) | |
1322 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1323 | else | |
1324 | { | |
1325 | if (readbuf != NULL) | |
1326 | m68hc11_extract_return_value (valtype, regcache, readbuf); | |
1327 | if (writebuf != NULL) | |
1328 | m68hc11_store_return_value (valtype, regcache, writebuf); | |
1329 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1330 | } | |
82c230c2 SC |
1331 | } |
1332 | ||
7df11f59 SC |
1333 | /* Test whether the ELF symbol corresponds to a function using rtc or |
1334 | rti to return. */ | |
1335 | ||
1336 | static void | |
1337 | m68hc11_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym) | |
1338 | { | |
1339 | unsigned char flags; | |
1340 | ||
1341 | flags = ((elf_symbol_type *)sym)->internal_elf_sym.st_other; | |
1342 | if (flags & STO_M68HC12_FAR) | |
1343 | MSYMBOL_SET_RTC (msym); | |
1344 | if (flags & STO_M68HC12_INTERRUPT) | |
1345 | MSYMBOL_SET_RTI (msym); | |
1346 | } | |
b631436b SC |
1347 | \f |
1348 | ||
1349 | /* 68HC11/68HC12 register groups. | |
1350 | Identify real hard registers and soft registers used by gcc. */ | |
1351 | ||
1352 | static struct reggroup *m68hc11_soft_reggroup; | |
1353 | static struct reggroup *m68hc11_hard_reggroup; | |
1354 | ||
1355 | static void | |
1356 | m68hc11_init_reggroups (void) | |
1357 | { | |
1358 | m68hc11_hard_reggroup = reggroup_new ("hard", USER_REGGROUP); | |
1359 | m68hc11_soft_reggroup = reggroup_new ("soft", USER_REGGROUP); | |
1360 | } | |
1361 | ||
1362 | static void | |
1363 | m68hc11_add_reggroups (struct gdbarch *gdbarch) | |
1364 | { | |
1365 | reggroup_add (gdbarch, m68hc11_hard_reggroup); | |
1366 | reggroup_add (gdbarch, m68hc11_soft_reggroup); | |
1367 | reggroup_add (gdbarch, general_reggroup); | |
1368 | reggroup_add (gdbarch, float_reggroup); | |
1369 | reggroup_add (gdbarch, all_reggroup); | |
1370 | reggroup_add (gdbarch, save_reggroup); | |
1371 | reggroup_add (gdbarch, restore_reggroup); | |
1372 | reggroup_add (gdbarch, vector_reggroup); | |
1373 | reggroup_add (gdbarch, system_reggroup); | |
1374 | } | |
1375 | ||
1376 | static int | |
1377 | m68hc11_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
1378 | struct reggroup *group) | |
1379 | { | |
1380 | /* We must save the real hard register as well as gcc | |
1381 | soft registers including the frame pointer. */ | |
1382 | if (group == save_reggroup || group == restore_reggroup) | |
1383 | { | |
1384 | return (regnum <= gdbarch_num_regs (gdbarch) | |
1385 | || ((regnum == SOFT_FP_REGNUM | |
1386 | || regnum == SOFT_TMP_REGNUM | |
1387 | || regnum == SOFT_ZS_REGNUM | |
1388 | || regnum == SOFT_XY_REGNUM) | |
d93859e2 | 1389 | && m68hc11_register_name (gdbarch, regnum))); |
b631436b SC |
1390 | } |
1391 | ||
1392 | /* Group to identify gcc soft registers (d1..dN). */ | |
1393 | if (group == m68hc11_soft_reggroup) | |
1394 | { | |
d93859e2 UW |
1395 | return regnum >= SOFT_D1_REGNUM |
1396 | && m68hc11_register_name (gdbarch, regnum); | |
b631436b SC |
1397 | } |
1398 | ||
1399 | if (group == m68hc11_hard_reggroup) | |
1400 | { | |
1401 | return regnum == HARD_PC_REGNUM || regnum == HARD_SP_REGNUM | |
1402 | || regnum == HARD_X_REGNUM || regnum == HARD_D_REGNUM | |
1403 | || regnum == HARD_Y_REGNUM || regnum == HARD_CCR_REGNUM; | |
1404 | } | |
1405 | return default_register_reggroup_p (gdbarch, regnum, group); | |
1406 | } | |
1407 | ||
82c230c2 SC |
1408 | static struct gdbarch * |
1409 | m68hc11_gdbarch_init (struct gdbarch_info info, | |
1410 | struct gdbarch_list *arches) | |
1411 | { | |
82c230c2 SC |
1412 | struct gdbarch *gdbarch; |
1413 | struct gdbarch_tdep *tdep; | |
81967506 | 1414 | int elf_flags; |
82c230c2 SC |
1415 | |
1416 | soft_reg_initialized = 0; | |
81967506 SC |
1417 | |
1418 | /* Extract the elf_flags if available. */ | |
1419 | if (info.abfd != NULL | |
1420 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
1421 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
1422 | else | |
1423 | elf_flags = 0; | |
1424 | ||
025bb325 | 1425 | /* Try to find a pre-existing architecture. */ |
82c230c2 SC |
1426 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
1427 | arches != NULL; | |
1428 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
1429 | { | |
81967506 SC |
1430 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
1431 | continue; | |
1432 | ||
82c230c2 SC |
1433 | return arches->gdbarch; |
1434 | } | |
1435 | ||
025bb325 | 1436 | /* Need a new architecture. Fill in a target specific vector. */ |
cdd238da | 1437 | tdep = XCNEW (struct gdbarch_tdep); |
82c230c2 | 1438 | gdbarch = gdbarch_alloc (&info, tdep); |
81967506 | 1439 | tdep->elf_flags = elf_flags; |
ed99b3d0 | 1440 | |
5d1a66bd SC |
1441 | switch (info.bfd_arch_info->arch) |
1442 | { | |
1443 | case bfd_arch_m68hc11: | |
1444 | tdep->stack_correction = 1; | |
7df11f59 | 1445 | tdep->use_page_register = 0; |
908f682f | 1446 | tdep->prologue = m6811_prologue; |
548bcbec SC |
1447 | set_gdbarch_addr_bit (gdbarch, 16); |
1448 | set_gdbarch_num_pseudo_regs (gdbarch, M68HC11_NUM_PSEUDO_REGS); | |
1449 | set_gdbarch_pc_regnum (gdbarch, HARD_PC_REGNUM); | |
1450 | set_gdbarch_num_regs (gdbarch, M68HC11_NUM_REGS); | |
5d1a66bd | 1451 | break; |
82c230c2 | 1452 | |
5d1a66bd SC |
1453 | case bfd_arch_m68hc12: |
1454 | tdep->stack_correction = 0; | |
7df11f59 | 1455 | tdep->use_page_register = elf_flags & E_M68HC12_BANKS; |
908f682f | 1456 | tdep->prologue = m6812_prologue; |
548bcbec SC |
1457 | set_gdbarch_addr_bit (gdbarch, elf_flags & E_M68HC12_BANKS ? 32 : 16); |
1458 | set_gdbarch_num_pseudo_regs (gdbarch, | |
1459 | elf_flags & E_M68HC12_BANKS | |
1460 | ? M68HC12_NUM_PSEUDO_REGS | |
1461 | : M68HC11_NUM_PSEUDO_REGS); | |
1462 | set_gdbarch_pc_regnum (gdbarch, elf_flags & E_M68HC12_BANKS | |
1463 | ? M68HC12_HARD_PC_REGNUM : HARD_PC_REGNUM); | |
1464 | set_gdbarch_num_regs (gdbarch, elf_flags & E_M68HC12_BANKS | |
1465 | ? M68HC12_NUM_REGS : M68HC11_NUM_REGS); | |
5d1a66bd SC |
1466 | break; |
1467 | ||
1468 | default: | |
1469 | break; | |
1470 | } | |
7d32ba20 SC |
1471 | |
1472 | /* Initially set everything according to the ABI. | |
1473 | Use 16-bit integers since it will be the case for most | |
1474 | programs. The size of these types should normally be set | |
1475 | according to the dwarf2 debug information. */ | |
82c230c2 | 1476 | set_gdbarch_short_bit (gdbarch, 16); |
81967506 | 1477 | set_gdbarch_int_bit (gdbarch, elf_flags & E_M68HC11_I32 ? 32 : 16); |
82c230c2 | 1478 | set_gdbarch_float_bit (gdbarch, 32); |
f92589cb TS |
1479 | if (elf_flags & E_M68HC11_F64) |
1480 | { | |
1481 | set_gdbarch_double_bit (gdbarch, 64); | |
1482 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); | |
1483 | } | |
1484 | else | |
1485 | { | |
1486 | set_gdbarch_double_bit (gdbarch, 32); | |
1487 | set_gdbarch_double_format (gdbarch, floatformats_ieee_single); | |
1488 | } | |
2417dd25 | 1489 | set_gdbarch_long_double_bit (gdbarch, 64); |
82c230c2 SC |
1490 | set_gdbarch_long_bit (gdbarch, 32); |
1491 | set_gdbarch_ptr_bit (gdbarch, 16); | |
1492 | set_gdbarch_long_long_bit (gdbarch, 64); | |
1493 | ||
b2a02dda SC |
1494 | /* Characters are unsigned. */ |
1495 | set_gdbarch_char_signed (gdbarch, 0); | |
1496 | ||
1ea653ae SC |
1497 | set_gdbarch_unwind_pc (gdbarch, m68hc11_unwind_pc); |
1498 | set_gdbarch_unwind_sp (gdbarch, m68hc11_unwind_sp); | |
1499 | ||
82c230c2 SC |
1500 | /* Set register info. */ |
1501 | set_gdbarch_fp0_regnum (gdbarch, -1); | |
82c230c2 | 1502 | |
82c230c2 | 1503 | set_gdbarch_sp_regnum (gdbarch, HARD_SP_REGNUM); |
82c230c2 | 1504 | set_gdbarch_register_name (gdbarch, m68hc11_register_name); |
4db73d49 | 1505 | set_gdbarch_register_type (gdbarch, m68hc11_register_type); |
46ce284d AC |
1506 | set_gdbarch_pseudo_register_read (gdbarch, m68hc11_pseudo_register_read); |
1507 | set_gdbarch_pseudo_register_write (gdbarch, m68hc11_pseudo_register_write); | |
82c230c2 | 1508 | |
3dc990bf SC |
1509 | set_gdbarch_push_dummy_call (gdbarch, m68hc11_push_dummy_call); |
1510 | ||
97092415 | 1511 | set_gdbarch_return_value (gdbarch, m68hc11_return_value); |
82c230c2 SC |
1512 | set_gdbarch_skip_prologue (gdbarch, m68hc11_skip_prologue); |
1513 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
04180708 YQ |
1514 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, |
1515 | m68hc11_breakpoint::kind_from_pc); | |
1516 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, | |
1517 | m68hc11_breakpoint::bp_from_kind); | |
82c230c2 | 1518 | |
b631436b SC |
1519 | m68hc11_add_reggroups (gdbarch); |
1520 | set_gdbarch_register_reggroup_p (gdbarch, m68hc11_register_reggroup_p); | |
e286caf2 | 1521 | set_gdbarch_print_registers_info (gdbarch, m68hc11_print_registers_info); |
b631436b | 1522 | |
1ea653ae | 1523 | /* Hook in the DWARF CFI frame unwinder. */ |
94afd7a6 | 1524 | dwarf2_append_unwinders (gdbarch); |
1ea653ae | 1525 | |
94afd7a6 | 1526 | frame_unwind_append_unwinder (gdbarch, &m68hc11_frame_unwind); |
1ea653ae SC |
1527 | frame_base_set_default (gdbarch, &m68hc11_frame_base); |
1528 | ||
1529 | /* Methods for saving / extracting a dummy frame's ID. The ID's | |
1530 | stack address must match the SP value returned by | |
1531 | PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */ | |
94afd7a6 | 1532 | set_gdbarch_dummy_id (gdbarch, m68hc11_dummy_id); |
1ea653ae SC |
1533 | |
1534 | /* Return the unwound PC value. */ | |
1535 | set_gdbarch_unwind_pc (gdbarch, m68hc11_unwind_pc); | |
1536 | ||
7df11f59 SC |
1537 | /* Minsymbol frobbing. */ |
1538 | set_gdbarch_elf_make_msymbol_special (gdbarch, | |
1539 | m68hc11_elf_make_msymbol_special); | |
1540 | ||
82c230c2 | 1541 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
82c230c2 SC |
1542 | |
1543 | return gdbarch; | |
78073dd8 AC |
1544 | } |
1545 | ||
1546 | void | |
fba45db2 | 1547 | _initialize_m68hc11_tdep (void) |
78073dd8 | 1548 | { |
82c230c2 | 1549 | register_gdbarch_init (bfd_arch_m68hc11, m68hc11_gdbarch_init); |
ea3881d9 | 1550 | register_gdbarch_init (bfd_arch_m68hc12, m68hc11_gdbarch_init); |
b631436b | 1551 | m68hc11_init_reggroups (); |
78073dd8 AC |
1552 | } |
1553 |