Commit | Line | Data |
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908f682f | 1 | /* Target-dependent code for Motorola 68HC11 & 68HC12 |
931aecf5 AC |
2 | |
3 | Copyright 1999, 2000, 2001, 2002, 2003, 2004 Free Software | |
4 | Foundation, Inc. | |
5 | ||
ffe1f3ee | 6 | Contributed by Stephane Carrez, stcarrez@nerim.fr |
78073dd8 AC |
7 | |
8 | This file is part of GDB. | |
9 | ||
10 | This program is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2 of the License, or | |
13 | (at your option) any later version. | |
14 | ||
15 | This program is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with this program; if not, write to the Free Software | |
22 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
23 | ||
78073dd8 | 24 | |
82c230c2 SC |
25 | #include "defs.h" |
26 | #include "frame.h" | |
1ea653ae SC |
27 | #include "frame-unwind.h" |
28 | #include "frame-base.h" | |
29 | #include "dwarf2-frame.h" | |
30 | #include "trad-frame.h" | |
82c230c2 SC |
31 | #include "symtab.h" |
32 | #include "gdbtypes.h" | |
33 | #include "gdbcmd.h" | |
34 | #include "gdbcore.h" | |
35 | #include "gdb_string.h" | |
36 | #include "value.h" | |
37 | #include "inferior.h" | |
38 | #include "dis-asm.h" | |
39 | #include "symfile.h" | |
40 | #include "objfiles.h" | |
41 | #include "arch-utils.h" | |
4e052eda | 42 | #include "regcache.h" |
b631436b | 43 | #include "reggroups.h" |
78073dd8 | 44 | |
82c230c2 SC |
45 | #include "target.h" |
46 | #include "opcode/m68hc11.h" | |
81967506 SC |
47 | #include "elf/m68hc11.h" |
48 | #include "elf-bfd.h" | |
78073dd8 | 49 | |
7df11f59 SC |
50 | /* Macros for setting and testing a bit in a minimal symbol. |
51 | For 68HC11/68HC12 we have two flags that tell which return | |
52 | type the function is using. This is used for prologue and frame | |
53 | analysis to compute correct stack frame layout. | |
54 | ||
55 | The MSB of the minimal symbol's "info" field is used for this purpose. | |
7df11f59 SC |
56 | |
57 | MSYMBOL_SET_RTC Actually sets the "RTC" bit. | |
58 | MSYMBOL_SET_RTI Actually sets the "RTI" bit. | |
59 | MSYMBOL_IS_RTC Tests the "RTC" bit in a minimal symbol. | |
f594e5e9 | 60 | MSYMBOL_IS_RTI Tests the "RTC" bit in a minimal symbol. */ |
7df11f59 SC |
61 | |
62 | #define MSYMBOL_SET_RTC(msym) \ | |
63 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \ | |
64 | | 0x80000000) | |
65 | ||
66 | #define MSYMBOL_SET_RTI(msym) \ | |
67 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \ | |
68 | | 0x40000000) | |
69 | ||
70 | #define MSYMBOL_IS_RTC(msym) \ | |
71 | (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) | |
72 | ||
73 | #define MSYMBOL_IS_RTI(msym) \ | |
74 | (((long) MSYMBOL_INFO (msym) & 0x40000000) != 0) | |
75 | ||
7df11f59 SC |
76 | enum insn_return_kind { |
77 | RETURN_RTS, | |
78 | RETURN_RTC, | |
79 | RETURN_RTI | |
80 | }; | |
81 | ||
82 | ||
78073dd8 AC |
83 | /* Register numbers of various important registers. |
84 | Note that some of these values are "real" register numbers, | |
85 | and correspond to the general registers of the machine, | |
86 | and some are "phony" register numbers which are too large | |
87 | to be actual register numbers as far as the user is concerned | |
88 | but do serve to get the desired values when passed to read_register. */ | |
89 | ||
82c230c2 SC |
90 | #define HARD_X_REGNUM 0 |
91 | #define HARD_D_REGNUM 1 | |
92 | #define HARD_Y_REGNUM 2 | |
93 | #define HARD_SP_REGNUM 3 | |
94 | #define HARD_PC_REGNUM 4 | |
95 | ||
96 | #define HARD_A_REGNUM 5 | |
97 | #define HARD_B_REGNUM 6 | |
98 | #define HARD_CCR_REGNUM 7 | |
5706502a SC |
99 | |
100 | /* 68HC12 page number register. | |
101 | Note: to keep a compatibility with gcc register naming, we must | |
102 | not have to rename FP and other soft registers. The page register | |
103 | is a real hard register and must therefore be counted by NUM_REGS. | |
104 | For this it has the same number as Z register (which is not used). */ | |
105 | #define HARD_PAGE_REGNUM 8 | |
106 | #define M68HC11_LAST_HARD_REG (HARD_PAGE_REGNUM) | |
82c230c2 SC |
107 | |
108 | /* Z is replaced by X or Y by gcc during machine reorg. | |
109 | ??? There is no way to get it and even know whether | |
110 | it's in X or Y or in ZS. */ | |
111 | #define SOFT_Z_REGNUM 8 | |
112 | ||
113 | /* Soft registers. These registers are special. There are treated | |
114 | like normal hard registers by gcc and gdb (ie, within dwarf2 info). | |
115 | They are physically located in memory. */ | |
116 | #define SOFT_FP_REGNUM 9 | |
117 | #define SOFT_TMP_REGNUM 10 | |
118 | #define SOFT_ZS_REGNUM 11 | |
119 | #define SOFT_XY_REGNUM 12 | |
f91a8b6b SC |
120 | #define SOFT_UNUSED_REGNUM 13 |
121 | #define SOFT_D1_REGNUM 14 | |
82c230c2 SC |
122 | #define SOFT_D32_REGNUM (SOFT_D1_REGNUM+31) |
123 | #define M68HC11_MAX_SOFT_REGS 32 | |
124 | ||
125 | #define M68HC11_NUM_REGS (8) | |
126 | #define M68HC11_NUM_PSEUDO_REGS (M68HC11_MAX_SOFT_REGS+5) | |
127 | #define M68HC11_ALL_REGS (M68HC11_NUM_REGS+M68HC11_NUM_PSEUDO_REGS) | |
128 | ||
129 | #define M68HC11_REG_SIZE (2) | |
130 | ||
548bcbec SC |
131 | #define M68HC12_NUM_REGS (9) |
132 | #define M68HC12_NUM_PSEUDO_REGS ((M68HC11_MAX_SOFT_REGS+5)+1-1) | |
133 | #define M68HC12_HARD_PC_REGNUM (SOFT_D32_REGNUM+1) | |
134 | ||
908f682f | 135 | struct insn_sequence; |
82c230c2 SC |
136 | struct gdbarch_tdep |
137 | { | |
5d1a66bd SC |
138 | /* Stack pointer correction value. For 68hc11, the stack pointer points |
139 | to the next push location. An offset of 1 must be applied to obtain | |
140 | the address where the last value is saved. For 68hc12, the stack | |
141 | pointer points to the last value pushed. No offset is necessary. */ | |
142 | int stack_correction; | |
908f682f SC |
143 | |
144 | /* Description of instructions in the prologue. */ | |
145 | struct insn_sequence *prologue; | |
81967506 | 146 | |
7df11f59 SC |
147 | /* True if the page memory bank register is available |
148 | and must be used. */ | |
149 | int use_page_register; | |
150 | ||
81967506 SC |
151 | /* ELF flags for ABI. */ |
152 | int elf_flags; | |
82c230c2 SC |
153 | }; |
154 | ||
5d1a66bd SC |
155 | #define M6811_TDEP gdbarch_tdep (current_gdbarch) |
156 | #define STACK_CORRECTION (M6811_TDEP->stack_correction) | |
7df11f59 | 157 | #define USE_PAGE_REGISTER (M6811_TDEP->use_page_register) |
5d1a66bd | 158 | |
1ea653ae SC |
159 | struct m68hc11_unwind_cache |
160 | { | |
161 | /* The previous frame's inner most stack address. Used as this | |
162 | frame ID's stack_addr. */ | |
163 | CORE_ADDR prev_sp; | |
164 | /* The frame's base, optionally used by the high-level debug info. */ | |
165 | CORE_ADDR base; | |
166 | CORE_ADDR pc; | |
167 | int size; | |
168 | int prologue_type; | |
169 | CORE_ADDR return_pc; | |
170 | CORE_ADDR sp_offset; | |
171 | int frameless; | |
172 | enum insn_return_kind return_kind; | |
173 | ||
174 | /* Table indicating the location of each and every register. */ | |
175 | struct trad_frame_saved_reg *saved_regs; | |
176 | }; | |
177 | ||
82c230c2 SC |
178 | /* Table of registers for 68HC11. This includes the hard registers |
179 | and the soft registers used by GCC. */ | |
180 | static char * | |
181 | m68hc11_register_names[] = | |
182 | { | |
183 | "x", "d", "y", "sp", "pc", "a", "b", | |
5706502a | 184 | "ccr", "page", "frame","tmp", "zs", "xy", 0, |
82c230c2 SC |
185 | "d1", "d2", "d3", "d4", "d5", "d6", "d7", |
186 | "d8", "d9", "d10", "d11", "d12", "d13", "d14", | |
187 | "d15", "d16", "d17", "d18", "d19", "d20", "d21", | |
188 | "d22", "d23", "d24", "d25", "d26", "d27", "d28", | |
189 | "d29", "d30", "d31", "d32" | |
190 | }; | |
78073dd8 | 191 | |
82c230c2 SC |
192 | struct m68hc11_soft_reg |
193 | { | |
194 | const char *name; | |
195 | CORE_ADDR addr; | |
196 | }; | |
78073dd8 | 197 | |
82c230c2 | 198 | static struct m68hc11_soft_reg soft_regs[M68HC11_ALL_REGS]; |
78073dd8 | 199 | |
82c230c2 | 200 | #define M68HC11_FP_ADDR soft_regs[SOFT_FP_REGNUM].addr |
78073dd8 | 201 | |
82c230c2 SC |
202 | static int soft_min_addr; |
203 | static int soft_max_addr; | |
204 | static int soft_reg_initialized = 0; | |
78073dd8 | 205 | |
82c230c2 SC |
206 | /* Look in the symbol table for the address of a pseudo register |
207 | in memory. If we don't find it, pretend the register is not used | |
208 | and not available. */ | |
209 | static void | |
210 | m68hc11_get_register_info (struct m68hc11_soft_reg *reg, const char *name) | |
211 | { | |
212 | struct minimal_symbol *msymbol; | |
78073dd8 | 213 | |
82c230c2 SC |
214 | msymbol = lookup_minimal_symbol (name, NULL, NULL); |
215 | if (msymbol) | |
216 | { | |
217 | reg->addr = SYMBOL_VALUE_ADDRESS (msymbol); | |
218 | reg->name = xstrdup (name); | |
219 | ||
220 | /* Keep track of the address range for soft registers. */ | |
221 | if (reg->addr < (CORE_ADDR) soft_min_addr) | |
222 | soft_min_addr = reg->addr; | |
223 | if (reg->addr > (CORE_ADDR) soft_max_addr) | |
224 | soft_max_addr = reg->addr; | |
225 | } | |
226 | else | |
227 | { | |
228 | reg->name = 0; | |
229 | reg->addr = 0; | |
230 | } | |
231 | } | |
78073dd8 | 232 | |
82c230c2 SC |
233 | /* Initialize the table of soft register addresses according |
234 | to the symbol table. */ | |
235 | static void | |
236 | m68hc11_initialize_register_info (void) | |
237 | { | |
238 | int i; | |
78073dd8 | 239 | |
82c230c2 SC |
240 | if (soft_reg_initialized) |
241 | return; | |
242 | ||
243 | soft_min_addr = INT_MAX; | |
244 | soft_max_addr = 0; | |
245 | for (i = 0; i < M68HC11_ALL_REGS; i++) | |
246 | { | |
247 | soft_regs[i].name = 0; | |
248 | } | |
249 | ||
250 | m68hc11_get_register_info (&soft_regs[SOFT_FP_REGNUM], "_.frame"); | |
251 | m68hc11_get_register_info (&soft_regs[SOFT_TMP_REGNUM], "_.tmp"); | |
252 | m68hc11_get_register_info (&soft_regs[SOFT_ZS_REGNUM], "_.z"); | |
253 | soft_regs[SOFT_Z_REGNUM] = soft_regs[SOFT_ZS_REGNUM]; | |
254 | m68hc11_get_register_info (&soft_regs[SOFT_XY_REGNUM], "_.xy"); | |
78073dd8 | 255 | |
82c230c2 SC |
256 | for (i = SOFT_D1_REGNUM; i < M68HC11_MAX_SOFT_REGS; i++) |
257 | { | |
258 | char buf[10]; | |
78073dd8 | 259 | |
82c230c2 SC |
260 | sprintf (buf, "_.d%d", i - SOFT_D1_REGNUM + 1); |
261 | m68hc11_get_register_info (&soft_regs[i], buf); | |
262 | } | |
78073dd8 | 263 | |
82c230c2 SC |
264 | if (soft_regs[SOFT_FP_REGNUM].name == 0) |
265 | { | |
266 | warning ("No frame soft register found in the symbol table.\n"); | |
267 | warning ("Stack backtrace will not work.\n"); | |
268 | } | |
269 | soft_reg_initialized = 1; | |
270 | } | |
78073dd8 | 271 | |
82c230c2 SC |
272 | /* Given an address in memory, return the soft register number if |
273 | that address corresponds to a soft register. Returns -1 if not. */ | |
274 | static int | |
275 | m68hc11_which_soft_register (CORE_ADDR addr) | |
276 | { | |
277 | int i; | |
278 | ||
279 | if (addr < soft_min_addr || addr > soft_max_addr) | |
280 | return -1; | |
281 | ||
282 | for (i = SOFT_FP_REGNUM; i < M68HC11_ALL_REGS; i++) | |
283 | { | |
284 | if (soft_regs[i].name && soft_regs[i].addr == addr) | |
285 | return i; | |
286 | } | |
287 | return -1; | |
288 | } | |
78073dd8 | 289 | |
82c230c2 SC |
290 | /* Fetch a pseudo register. The 68hc11 soft registers are treated like |
291 | pseudo registers. They are located in memory. Translate the register | |
292 | fetch into a memory read. */ | |
46ce284d AC |
293 | static void |
294 | m68hc11_pseudo_register_read (struct gdbarch *gdbarch, | |
295 | struct regcache *regcache, | |
296 | int regno, void *buf) | |
82c230c2 | 297 | { |
548bcbec SC |
298 | /* The PC is a pseudo reg only for 68HC12 with the memory bank |
299 | addressing mode. */ | |
300 | if (regno == M68HC12_HARD_PC_REGNUM) | |
301 | { | |
4db73d49 | 302 | ULONGEST pc; |
548bcbec | 303 | const int regsize = TYPE_LENGTH (builtin_type_uint32); |
548bcbec | 304 | |
4db73d49 | 305 | regcache_cooked_read_unsigned (regcache, HARD_PC_REGNUM, &pc); |
548bcbec SC |
306 | if (pc >= 0x8000 && pc < 0xc000) |
307 | { | |
4db73d49 SC |
308 | ULONGEST page; |
309 | ||
310 | regcache_cooked_read_unsigned (regcache, HARD_PAGE_REGNUM, &page); | |
548bcbec SC |
311 | pc -= 0x8000; |
312 | pc += (page << 14); | |
313 | pc += 0x1000000; | |
314 | } | |
315 | store_unsigned_integer (buf, regsize, pc); | |
316 | return; | |
317 | } | |
318 | ||
82c230c2 SC |
319 | m68hc11_initialize_register_info (); |
320 | ||
321 | /* Fetch a soft register: translate into a memory read. */ | |
322 | if (soft_regs[regno].name) | |
323 | { | |
324 | target_read_memory (soft_regs[regno].addr, buf, 2); | |
325 | } | |
326 | else | |
327 | { | |
328 | memset (buf, 0, 2); | |
329 | } | |
82c230c2 | 330 | } |
78073dd8 | 331 | |
82c230c2 SC |
332 | /* Store a pseudo register. Translate the register store |
333 | into a memory write. */ | |
334 | static void | |
46ce284d AC |
335 | m68hc11_pseudo_register_write (struct gdbarch *gdbarch, |
336 | struct regcache *regcache, | |
337 | int regno, const void *buf) | |
82c230c2 | 338 | { |
548bcbec SC |
339 | /* The PC is a pseudo reg only for 68HC12 with the memory bank |
340 | addressing mode. */ | |
341 | if (regno == M68HC12_HARD_PC_REGNUM) | |
342 | { | |
343 | const int regsize = TYPE_LENGTH (builtin_type_uint32); | |
344 | char *tmp = alloca (regsize); | |
345 | CORE_ADDR pc; | |
346 | ||
347 | memcpy (tmp, buf, regsize); | |
348 | pc = extract_unsigned_integer (tmp, regsize); | |
349 | if (pc >= 0x1000000) | |
350 | { | |
351 | pc -= 0x1000000; | |
4db73d49 SC |
352 | regcache_cooked_write_unsigned (regcache, HARD_PAGE_REGNUM, |
353 | (pc >> 14) & 0x0ff); | |
548bcbec | 354 | pc &= 0x03fff; |
4db73d49 SC |
355 | regcache_cooked_write_unsigned (regcache, HARD_PC_REGNUM, |
356 | pc + 0x8000); | |
548bcbec SC |
357 | } |
358 | else | |
4db73d49 | 359 | regcache_cooked_write_unsigned (regcache, HARD_PC_REGNUM, pc); |
548bcbec SC |
360 | return; |
361 | } | |
362 | ||
82c230c2 | 363 | m68hc11_initialize_register_info (); |
78073dd8 | 364 | |
82c230c2 SC |
365 | /* Store a soft register: translate into a memory write. */ |
366 | if (soft_regs[regno].name) | |
367 | { | |
46ce284d AC |
368 | const int regsize = 2; |
369 | char *tmp = alloca (regsize); | |
370 | memcpy (tmp, buf, regsize); | |
371 | target_write_memory (soft_regs[regno].addr, tmp, regsize); | |
82c230c2 SC |
372 | } |
373 | } | |
78073dd8 | 374 | |
fa88f677 | 375 | static const char * |
82c230c2 | 376 | m68hc11_register_name (int reg_nr) |
78073dd8 | 377 | { |
548bcbec SC |
378 | if (reg_nr == M68HC12_HARD_PC_REGNUM && USE_PAGE_REGISTER) |
379 | return "pc"; | |
380 | if (reg_nr == HARD_PC_REGNUM && USE_PAGE_REGISTER) | |
381 | return "ppc"; | |
382 | ||
82c230c2 SC |
383 | if (reg_nr < 0) |
384 | return NULL; | |
385 | if (reg_nr >= M68HC11_ALL_REGS) | |
386 | return NULL; | |
387 | ||
388 | /* If we don't know the address of a soft register, pretend it | |
389 | does not exist. */ | |
390 | if (reg_nr > M68HC11_LAST_HARD_REG && soft_regs[reg_nr].name == 0) | |
391 | return NULL; | |
392 | return m68hc11_register_names[reg_nr]; | |
393 | } | |
78073dd8 | 394 | |
f4f9705a | 395 | static const unsigned char * |
82c230c2 | 396 | m68hc11_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
78073dd8 | 397 | { |
82c230c2 SC |
398 | static unsigned char breakpoint[] = {0x0}; |
399 | ||
400 | *lenptr = sizeof (breakpoint); | |
401 | return breakpoint; | |
78073dd8 AC |
402 | } |
403 | ||
908f682f SC |
404 | \f |
405 | /* 68HC11 & 68HC12 prologue analysis. | |
406 | ||
407 | */ | |
408 | #define MAX_CODES 12 | |
409 | ||
410 | /* 68HC11 opcodes. */ | |
411 | #undef M6811_OP_PAGE2 | |
b94a41a1 SC |
412 | #define M6811_OP_PAGE2 (0x18) |
413 | #define M6811_OP_LDX (0xde) | |
414 | #define M6811_OP_LDX_EXT (0xfe) | |
415 | #define M6811_OP_PSHX (0x3c) | |
416 | #define M6811_OP_STS (0x9f) | |
417 | #define M6811_OP_STS_EXT (0xbf) | |
418 | #define M6811_OP_TSX (0x30) | |
419 | #define M6811_OP_XGDX (0x8f) | |
420 | #define M6811_OP_ADDD (0xc3) | |
421 | #define M6811_OP_TXS (0x35) | |
422 | #define M6811_OP_DES (0x34) | |
908f682f SC |
423 | |
424 | /* 68HC12 opcodes. */ | |
b94a41a1 SC |
425 | #define M6812_OP_PAGE2 (0x18) |
426 | #define M6812_OP_MOVW (0x01) | |
427 | #define M6812_PB_PSHW (0xae) | |
428 | #define M6812_OP_STS (0x5f) | |
429 | #define M6812_OP_STS_EXT (0x7f) | |
430 | #define M6812_OP_LEAS (0x1b) | |
431 | #define M6812_OP_PSHX (0x34) | |
432 | #define M6812_OP_PSHY (0x35) | |
908f682f SC |
433 | |
434 | /* Operand extraction. */ | |
435 | #define OP_DIRECT (0x100) /* 8-byte direct addressing. */ | |
436 | #define OP_IMM_LOW (0x200) /* Low part of 16-bit constant/address. */ | |
437 | #define OP_IMM_HIGH (0x300) /* High part of 16-bit constant/address. */ | |
438 | #define OP_PBYTE (0x400) /* 68HC12 indexed operand. */ | |
439 | ||
440 | /* Identification of the sequence. */ | |
441 | enum m6811_seq_type | |
442 | { | |
443 | P_LAST = 0, | |
444 | P_SAVE_REG, /* Save a register on the stack. */ | |
445 | P_SET_FRAME, /* Setup the frame pointer. */ | |
446 | P_LOCAL_1, /* Allocate 1 byte for locals. */ | |
447 | P_LOCAL_2, /* Allocate 2 bytes for locals. */ | |
448 | P_LOCAL_N /* Allocate N bytes for locals. */ | |
449 | }; | |
450 | ||
451 | struct insn_sequence { | |
452 | enum m6811_seq_type type; | |
453 | unsigned length; | |
454 | unsigned short code[MAX_CODES]; | |
455 | }; | |
456 | ||
457 | /* Sequence of instructions in the 68HC11 function prologue. */ | |
458 | static struct insn_sequence m6811_prologue[] = { | |
459 | /* Sequences to save a soft-register. */ | |
460 | { P_SAVE_REG, 3, { M6811_OP_LDX, OP_DIRECT, | |
461 | M6811_OP_PSHX } }, | |
462 | { P_SAVE_REG, 5, { M6811_OP_PAGE2, M6811_OP_LDX, OP_DIRECT, | |
463 | M6811_OP_PAGE2, M6811_OP_PSHX } }, | |
b94a41a1 SC |
464 | { P_SAVE_REG, 4, { M6811_OP_LDX_EXT, OP_IMM_HIGH, OP_IMM_LOW, |
465 | M6811_OP_PSHX } }, | |
466 | { P_SAVE_REG, 6, { M6811_OP_PAGE2, M6811_OP_LDX_EXT, OP_IMM_HIGH, OP_IMM_LOW, | |
467 | M6811_OP_PAGE2, M6811_OP_PSHX } }, | |
908f682f SC |
468 | |
469 | /* Sequences to allocate local variables. */ | |
470 | { P_LOCAL_N, 7, { M6811_OP_TSX, | |
471 | M6811_OP_XGDX, | |
472 | M6811_OP_ADDD, OP_IMM_HIGH, OP_IMM_LOW, | |
473 | M6811_OP_XGDX, | |
474 | M6811_OP_TXS } }, | |
475 | { P_LOCAL_N, 11, { M6811_OP_PAGE2, M6811_OP_TSX, | |
476 | M6811_OP_PAGE2, M6811_OP_XGDX, | |
477 | M6811_OP_ADDD, OP_IMM_HIGH, OP_IMM_LOW, | |
478 | M6811_OP_PAGE2, M6811_OP_XGDX, | |
479 | M6811_OP_PAGE2, M6811_OP_TXS } }, | |
480 | { P_LOCAL_1, 1, { M6811_OP_DES } }, | |
481 | { P_LOCAL_2, 1, { M6811_OP_PSHX } }, | |
482 | { P_LOCAL_2, 2, { M6811_OP_PAGE2, M6811_OP_PSHX } }, | |
483 | ||
484 | /* Initialize the frame pointer. */ | |
485 | { P_SET_FRAME, 2, { M6811_OP_STS, OP_DIRECT } }, | |
b94a41a1 | 486 | { P_SET_FRAME, 3, { M6811_OP_STS_EXT, OP_IMM_HIGH, OP_IMM_LOW } }, |
908f682f SC |
487 | { P_LAST, 0, { 0 } } |
488 | }; | |
489 | ||
490 | ||
491 | /* Sequence of instructions in the 68HC12 function prologue. */ | |
492 | static struct insn_sequence m6812_prologue[] = { | |
493 | { P_SAVE_REG, 5, { M6812_OP_PAGE2, M6812_OP_MOVW, M6812_PB_PSHW, | |
494 | OP_IMM_HIGH, OP_IMM_LOW } }, | |
b94a41a1 SC |
495 | { P_SET_FRAME, 2, { M6812_OP_STS, OP_DIRECT } }, |
496 | { P_SET_FRAME, 3, { M6812_OP_STS_EXT, OP_IMM_HIGH, OP_IMM_LOW } }, | |
908f682f | 497 | { P_LOCAL_N, 2, { M6812_OP_LEAS, OP_PBYTE } }, |
ffe1f3ee SC |
498 | { P_LOCAL_2, 1, { M6812_OP_PSHX } }, |
499 | { P_LOCAL_2, 1, { M6812_OP_PSHY } }, | |
908f682f SC |
500 | { P_LAST, 0 } |
501 | }; | |
502 | ||
503 | ||
504 | /* Analyze the sequence of instructions starting at the given address. | |
505 | Returns a pointer to the sequence when it is recognized and | |
c8a7f6ac | 506 | the optional value (constant/address) associated with it. */ |
908f682f | 507 | static struct insn_sequence * |
c8a7f6ac | 508 | m68hc11_analyze_instruction (struct insn_sequence *seq, CORE_ADDR pc, |
908f682f SC |
509 | CORE_ADDR *val) |
510 | { | |
511 | unsigned char buffer[MAX_CODES]; | |
512 | unsigned bufsize; | |
513 | unsigned j; | |
514 | CORE_ADDR cur_val; | |
515 | short v = 0; | |
516 | ||
517 | bufsize = 0; | |
518 | for (; seq->type != P_LAST; seq++) | |
519 | { | |
520 | cur_val = 0; | |
521 | for (j = 0; j < seq->length; j++) | |
522 | { | |
523 | if (bufsize < j + 1) | |
524 | { | |
c8a7f6ac | 525 | buffer[bufsize] = read_memory_unsigned_integer (pc + bufsize, |
908f682f SC |
526 | 1); |
527 | bufsize++; | |
528 | } | |
529 | /* Continue while we match the opcode. */ | |
530 | if (seq->code[j] == buffer[j]) | |
531 | continue; | |
532 | ||
533 | if ((seq->code[j] & 0xf00) == 0) | |
534 | break; | |
535 | ||
536 | /* Extract a sequence parameter (address or constant). */ | |
537 | switch (seq->code[j]) | |
538 | { | |
539 | case OP_DIRECT: | |
540 | cur_val = (CORE_ADDR) buffer[j]; | |
541 | break; | |
542 | ||
543 | case OP_IMM_HIGH: | |
544 | cur_val = cur_val & 0x0ff; | |
545 | cur_val |= (buffer[j] << 8); | |
546 | break; | |
547 | ||
548 | case OP_IMM_LOW: | |
549 | cur_val &= 0x0ff00; | |
550 | cur_val |= buffer[j]; | |
551 | break; | |
552 | ||
553 | case OP_PBYTE: | |
554 | if ((buffer[j] & 0xE0) == 0x80) | |
555 | { | |
556 | v = buffer[j] & 0x1f; | |
557 | if (v & 0x10) | |
558 | v |= 0xfff0; | |
559 | } | |
560 | else if ((buffer[j] & 0xfe) == 0xf0) | |
561 | { | |
c8a7f6ac | 562 | v = read_memory_unsigned_integer (pc + j + 1, 1); |
908f682f SC |
563 | if (buffer[j] & 1) |
564 | v |= 0xff00; | |
565 | } | |
566 | else if (buffer[j] == 0xf2) | |
567 | { | |
c8a7f6ac | 568 | v = read_memory_unsigned_integer (pc + j + 1, 2); |
908f682f SC |
569 | } |
570 | cur_val = v; | |
571 | break; | |
572 | } | |
573 | } | |
574 | ||
575 | /* We have a full match. */ | |
576 | if (j == seq->length) | |
577 | { | |
578 | *val = cur_val; | |
908f682f SC |
579 | return seq; |
580 | } | |
581 | } | |
582 | return 0; | |
583 | } | |
584 | ||
7df11f59 SC |
585 | /* Return the instruction that the function at the PC is using. */ |
586 | static enum insn_return_kind | |
587 | m68hc11_get_return_insn (CORE_ADDR pc) | |
588 | { | |
589 | struct minimal_symbol *sym; | |
590 | ||
591 | /* A flag indicating that this is a STO_M68HC12_FAR or STO_M68HC12_INTERRUPT | |
592 | function is stored by elfread.c in the high bit of the info field. | |
593 | Use this to decide which instruction the function uses to return. */ | |
594 | sym = lookup_minimal_symbol_by_pc (pc); | |
595 | if (sym == 0) | |
596 | return RETURN_RTS; | |
597 | ||
598 | if (MSYMBOL_IS_RTC (sym)) | |
599 | return RETURN_RTC; | |
600 | else if (MSYMBOL_IS_RTI (sym)) | |
601 | return RETURN_RTI; | |
602 | else | |
603 | return RETURN_RTS; | |
604 | } | |
605 | ||
78073dd8 AC |
606 | /* Analyze the function prologue to find some information |
607 | about the function: | |
608 | - the PC of the first line (for m68hc11_skip_prologue) | |
609 | - the offset of the previous frame saved address (from current frame) | |
610 | - the soft registers which are pushed. */ | |
1ea653ae SC |
611 | static CORE_ADDR |
612 | m68hc11_scan_prologue (CORE_ADDR pc, CORE_ADDR current_pc, | |
613 | struct m68hc11_unwind_cache *info) | |
78073dd8 | 614 | { |
1ea653ae | 615 | LONGEST save_addr; |
78073dd8 | 616 | CORE_ADDR func_end; |
78073dd8 AC |
617 | int size; |
618 | int found_frame_point; | |
82c230c2 | 619 | int saved_reg; |
908f682f SC |
620 | int done = 0; |
621 | struct insn_sequence *seq_table; | |
1ea653ae SC |
622 | |
623 | info->size = 0; | |
624 | info->sp_offset = 0; | |
625 | if (pc >= current_pc) | |
626 | return current_pc; | |
627 | ||
78073dd8 AC |
628 | size = 0; |
629 | ||
82c230c2 | 630 | m68hc11_initialize_register_info (); |
1ea653ae | 631 | if (pc == 0) |
78073dd8 | 632 | { |
1ea653ae SC |
633 | info->size = 0; |
634 | return pc; | |
78073dd8 AC |
635 | } |
636 | ||
908f682f SC |
637 | seq_table = gdbarch_tdep (current_gdbarch)->prologue; |
638 | ||
78073dd8 AC |
639 | /* The 68hc11 stack is as follows: |
640 | ||
641 | ||
642 | | | | |
643 | +-----------+ | |
644 | | | | |
645 | | args | | |
646 | | | | |
647 | +-----------+ | |
648 | | PC-return | | |
649 | +-----------+ | |
650 | | Old frame | | |
651 | +-----------+ | |
652 | | | | |
653 | | Locals | | |
654 | | | | |
655 | +-----------+ <--- current frame | |
656 | | | | |
657 | ||
658 | With most processors (like 68K) the previous frame can be computed | |
659 | easily because it is always at a fixed offset (see link/unlink). | |
660 | That is, locals are accessed with negative offsets, arguments are | |
661 | accessed with positive ones. Since 68hc11 only supports offsets | |
662 | in the range [0..255], the frame is defined at the bottom of | |
663 | locals (see picture). | |
664 | ||
665 | The purpose of the analysis made here is to find out the size | |
666 | of locals in this function. An alternative to this is to use | |
667 | DWARF2 info. This would be better but I don't know how to | |
668 | access dwarf2 debug from this function. | |
669 | ||
670 | Walk from the function entry point to the point where we save | |
671 | the frame. While walking instructions, compute the size of bytes | |
672 | which are pushed. This gives us the index to access the previous | |
673 | frame. | |
674 | ||
675 | We limit the search to 128 bytes so that the algorithm is bounded | |
676 | in case of random and wrong code. We also stop and abort if | |
677 | we find an instruction which is not supposed to appear in the | |
678 | prologue (as generated by gcc 2.95, 2.96). | |
679 | */ | |
78073dd8 | 680 | func_end = pc + 128; |
78073dd8 | 681 | found_frame_point = 0; |
1ea653ae SC |
682 | info->size = 0; |
683 | save_addr = 0; | |
908f682f | 684 | while (!done && pc + 2 < func_end) |
78073dd8 | 685 | { |
908f682f SC |
686 | struct insn_sequence *seq; |
687 | CORE_ADDR val; | |
1ea653ae | 688 | |
c8a7f6ac | 689 | seq = m68hc11_analyze_instruction (seq_table, pc, &val); |
908f682f SC |
690 | if (seq == 0) |
691 | break; | |
78073dd8 | 692 | |
c8a7f6ac SC |
693 | /* If we are within the instruction group, we can't advance the |
694 | pc nor the stack offset. Otherwise the caller's stack computed | |
695 | from the current stack can be wrong. */ | |
696 | if (pc + seq->length > current_pc) | |
697 | break; | |
698 | ||
699 | pc = pc + seq->length; | |
908f682f | 700 | if (seq->type == P_SAVE_REG) |
78073dd8 | 701 | { |
908f682f SC |
702 | if (found_frame_point) |
703 | { | |
704 | saved_reg = m68hc11_which_soft_register (val); | |
705 | if (saved_reg < 0) | |
706 | break; | |
78073dd8 | 707 | |
908f682f | 708 | save_addr -= 2; |
1ea653ae | 709 | info->saved_regs[saved_reg].addr = save_addr; |
908f682f SC |
710 | } |
711 | else | |
712 | { | |
713 | size += 2; | |
714 | } | |
78073dd8 | 715 | } |
908f682f | 716 | else if (seq->type == P_SET_FRAME) |
78073dd8 AC |
717 | { |
718 | found_frame_point = 1; | |
1ea653ae | 719 | info->size = size; |
78073dd8 | 720 | } |
908f682f | 721 | else if (seq->type == P_LOCAL_1) |
78073dd8 | 722 | { |
6148eca7 SC |
723 | size += 1; |
724 | } | |
908f682f | 725 | else if (seq->type == P_LOCAL_2) |
78073dd8 | 726 | { |
908f682f | 727 | size += 2; |
78073dd8 | 728 | } |
908f682f | 729 | else if (seq->type == P_LOCAL_N) |
78073dd8 | 730 | { |
908f682f SC |
731 | /* Stack pointer is decremented for the allocation. */ |
732 | if (val & 0x8000) | |
733 | size -= (int) (val) | 0xffff0000; | |
734 | else | |
735 | size -= val; | |
78073dd8 AC |
736 | } |
737 | } | |
1ea653ae SC |
738 | if (found_frame_point == 0) |
739 | info->sp_offset = size; | |
740 | else | |
741 | info->sp_offset = -1; | |
742 | return pc; | |
78073dd8 AC |
743 | } |
744 | ||
82c230c2 | 745 | static CORE_ADDR |
78073dd8 AC |
746 | m68hc11_skip_prologue (CORE_ADDR pc) |
747 | { | |
748 | CORE_ADDR func_addr, func_end; | |
749 | struct symtab_and_line sal; | |
1ea653ae | 750 | struct m68hc11_unwind_cache tmp_cache = { 0 }; |
78073dd8 | 751 | |
82c230c2 SC |
752 | /* If we have line debugging information, then the end of the |
753 | prologue should be the first assembly instruction of the | |
78073dd8 AC |
754 | first source line. */ |
755 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
756 | { | |
757 | sal = find_pc_line (func_addr, 0); | |
758 | if (sal.end && sal.end < func_end) | |
759 | return sal.end; | |
760 | } | |
761 | ||
1ea653ae | 762 | pc = m68hc11_scan_prologue (pc, (CORE_ADDR) -1, &tmp_cache); |
78073dd8 AC |
763 | return pc; |
764 | } | |
765 | ||
1ea653ae SC |
766 | static CORE_ADDR |
767 | m68hc11_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
768 | { | |
769 | ULONGEST pc; | |
770 | ||
771 | frame_unwind_unsigned_register (next_frame, gdbarch_pc_regnum (gdbarch), | |
772 | &pc); | |
773 | return pc; | |
774 | } | |
775 | ||
776 | /* Put here the code to store, into fi->saved_regs, the addresses of | |
777 | the saved registers of frame described by FRAME_INFO. This | |
778 | includes special registers such as pc and fp saved in special ways | |
779 | in the stack frame. sp is even more special: the address we return | |
780 | for it IS the sp for the next frame. */ | |
781 | ||
782 | struct m68hc11_unwind_cache * | |
783 | m68hc11_frame_unwind_cache (struct frame_info *next_frame, | |
784 | void **this_prologue_cache) | |
785 | { | |
786 | ULONGEST prev_sp; | |
787 | ULONGEST this_base; | |
788 | struct m68hc11_unwind_cache *info; | |
789 | CORE_ADDR current_pc; | |
790 | int i; | |
791 | ||
792 | if ((*this_prologue_cache)) | |
793 | return (*this_prologue_cache); | |
794 | ||
795 | info = FRAME_OBSTACK_ZALLOC (struct m68hc11_unwind_cache); | |
796 | (*this_prologue_cache) = info; | |
797 | info->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
798 | ||
799 | info->pc = frame_func_unwind (next_frame); | |
800 | ||
801 | info->size = 0; | |
802 | info->return_kind = m68hc11_get_return_insn (info->pc); | |
803 | ||
804 | /* The SP was moved to the FP. This indicates that a new frame | |
805 | was created. Get THIS frame's FP value by unwinding it from | |
806 | the next frame. */ | |
807 | frame_unwind_unsigned_register (next_frame, SOFT_FP_REGNUM, &this_base); | |
808 | if (this_base == 0) | |
809 | { | |
810 | info->base = 0; | |
811 | return info; | |
812 | } | |
813 | ||
814 | current_pc = frame_pc_unwind (next_frame); | |
815 | if (info->pc != 0) | |
816 | m68hc11_scan_prologue (info->pc, current_pc, info); | |
817 | ||
818 | info->saved_regs[HARD_PC_REGNUM].addr = info->size; | |
819 | ||
820 | if (info->sp_offset != (CORE_ADDR) -1) | |
821 | { | |
822 | info->saved_regs[HARD_PC_REGNUM].addr = info->sp_offset; | |
823 | frame_unwind_unsigned_register (next_frame, HARD_SP_REGNUM, &this_base); | |
824 | prev_sp = this_base + info->sp_offset + 2; | |
825 | this_base += STACK_CORRECTION; | |
826 | } | |
827 | else | |
828 | { | |
829 | /* The FP points at the last saved register. Adjust the FP back | |
830 | to before the first saved register giving the SP. */ | |
831 | prev_sp = this_base + info->size + 2; | |
832 | ||
833 | this_base += STACK_CORRECTION; | |
834 | if (soft_regs[SOFT_FP_REGNUM].name) | |
835 | info->saved_regs[SOFT_FP_REGNUM].addr = info->size - 2; | |
836 | } | |
837 | ||
838 | if (info->return_kind == RETURN_RTC) | |
839 | { | |
840 | prev_sp += 1; | |
841 | info->saved_regs[HARD_PAGE_REGNUM].addr = info->size; | |
842 | info->saved_regs[HARD_PC_REGNUM].addr = info->size + 1; | |
843 | } | |
844 | else if (info->return_kind == RETURN_RTI) | |
845 | { | |
846 | prev_sp += 7; | |
847 | info->saved_regs[HARD_CCR_REGNUM].addr = info->size; | |
848 | info->saved_regs[HARD_D_REGNUM].addr = info->size + 1; | |
849 | info->saved_regs[HARD_X_REGNUM].addr = info->size + 3; | |
850 | info->saved_regs[HARD_Y_REGNUM].addr = info->size + 5; | |
851 | info->saved_regs[HARD_PC_REGNUM].addr = info->size + 7; | |
852 | } | |
853 | ||
854 | /* Add 1 here to adjust for the post-decrement nature of the push | |
855 | instruction.*/ | |
856 | info->prev_sp = prev_sp; | |
857 | ||
858 | info->base = this_base; | |
859 | ||
860 | /* Adjust all the saved registers so that they contain addresses and not | |
861 | offsets. */ | |
862 | for (i = 0; i < NUM_REGS + NUM_PSEUDO_REGS - 1; i++) | |
863 | if (trad_frame_addr_p (info->saved_regs, i)) | |
864 | { | |
865 | info->saved_regs[i].addr += this_base; | |
866 | } | |
867 | ||
868 | /* The previous frame's SP needed to be computed. Save the computed | |
869 | value. */ | |
870 | trad_frame_set_value (info->saved_regs, HARD_SP_REGNUM, info->prev_sp); | |
871 | ||
872 | return info; | |
873 | } | |
874 | ||
875 | /* Given a GDB frame, determine the address of the calling function's | |
876 | frame. This will be used to create a new GDB frame struct. */ | |
877 | ||
878 | static void | |
879 | m68hc11_frame_this_id (struct frame_info *next_frame, | |
880 | void **this_prologue_cache, | |
881 | struct frame_id *this_id) | |
882 | { | |
883 | struct m68hc11_unwind_cache *info | |
884 | = m68hc11_frame_unwind_cache (next_frame, this_prologue_cache); | |
885 | CORE_ADDR base; | |
886 | CORE_ADDR func; | |
887 | struct frame_id id; | |
888 | ||
889 | /* The FUNC is easy. */ | |
890 | func = frame_func_unwind (next_frame); | |
891 | ||
1ea653ae SC |
892 | /* Hopefully the prologue analysis either correctly determined the |
893 | frame's base (which is the SP from the previous frame), or set | |
894 | that base to "NULL". */ | |
895 | base = info->prev_sp; | |
896 | if (base == 0) | |
897 | return; | |
898 | ||
899 | id = frame_id_build (base, func); | |
900 | #if 0 | |
901 | /* Check that we're not going round in circles with the same frame | |
902 | ID (but avoid applying the test to sentinel frames which do go | |
903 | round in circles). Can't use frame_id_eq() as that doesn't yet | |
904 | compare the frame's PC value. */ | |
905 | if (frame_relative_level (next_frame) >= 0 | |
906 | && get_frame_type (next_frame) != DUMMY_FRAME | |
907 | && frame_id_eq (get_frame_id (next_frame), id)) | |
908 | return; | |
909 | #endif | |
910 | (*this_id) = id; | |
911 | } | |
912 | ||
913 | static void | |
914 | m68hc11_frame_prev_register (struct frame_info *next_frame, | |
915 | void **this_prologue_cache, | |
916 | int regnum, int *optimizedp, | |
917 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
918 | int *realnump, void *bufferp) | |
919 | { | |
920 | struct m68hc11_unwind_cache *info | |
921 | = m68hc11_frame_unwind_cache (next_frame, this_prologue_cache); | |
922 | ||
923 | trad_frame_prev_register (next_frame, info->saved_regs, regnum, | |
924 | optimizedp, lvalp, addrp, realnump, bufferp); | |
925 | ||
926 | if (regnum == HARD_PC_REGNUM) | |
927 | { | |
928 | /* Take into account the 68HC12 specific call (PC + page). */ | |
929 | if (info->return_kind == RETURN_RTC | |
930 | && *addrp >= 0x08000 && *addrp < 0x0c000 | |
931 | && USE_PAGE_REGISTER) | |
932 | { | |
933 | int page_optimized; | |
934 | ||
935 | CORE_ADDR page; | |
936 | ||
937 | trad_frame_prev_register (next_frame, info->saved_regs, | |
938 | HARD_PAGE_REGNUM, &page_optimized, | |
939 | 0, &page, 0, 0); | |
940 | *addrp -= 0x08000; | |
941 | *addrp += ((page & 0x0ff) << 14); | |
942 | *addrp += 0x1000000; | |
943 | } | |
944 | } | |
945 | } | |
946 | ||
947 | static const struct frame_unwind m68hc11_frame_unwind = { | |
948 | NORMAL_FRAME, | |
949 | m68hc11_frame_this_id, | |
950 | m68hc11_frame_prev_register | |
951 | }; | |
952 | ||
953 | const struct frame_unwind * | |
1a241548 | 954 | m68hc11_frame_sniffer (struct frame_info *next_frame) |
1ea653ae SC |
955 | { |
956 | return &m68hc11_frame_unwind; | |
957 | } | |
958 | ||
959 | static CORE_ADDR | |
960 | m68hc11_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
961 | { | |
962 | struct m68hc11_unwind_cache *info | |
963 | = m68hc11_frame_unwind_cache (next_frame, this_cache); | |
964 | ||
965 | return info->base; | |
966 | } | |
967 | ||
968 | static CORE_ADDR | |
969 | m68hc11_frame_args_address (struct frame_info *next_frame, void **this_cache) | |
970 | { | |
971 | CORE_ADDR addr; | |
972 | struct m68hc11_unwind_cache *info | |
973 | = m68hc11_frame_unwind_cache (next_frame, this_cache); | |
974 | ||
975 | addr = info->base + info->size; | |
976 | if (info->return_kind == RETURN_RTC) | |
977 | addr += 1; | |
978 | else if (info->return_kind == RETURN_RTI) | |
979 | addr += 7; | |
980 | ||
981 | return addr; | |
982 | } | |
983 | ||
984 | static const struct frame_base m68hc11_frame_base = { | |
985 | &m68hc11_frame_unwind, | |
986 | m68hc11_frame_base_address, | |
987 | m68hc11_frame_base_address, | |
988 | m68hc11_frame_args_address | |
989 | }; | |
990 | ||
991 | static CORE_ADDR | |
992 | m68hc11_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
993 | { | |
994 | ULONGEST sp; | |
995 | frame_unwind_unsigned_register (next_frame, HARD_SP_REGNUM, &sp); | |
996 | return sp; | |
997 | } | |
998 | ||
999 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that | |
1000 | dummy frame. The frame ID's base needs to match the TOS value | |
1001 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
1002 | breakpoint. */ | |
1003 | ||
1004 | static struct frame_id | |
1005 | m68hc11_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1006 | { | |
1007 | ULONGEST tos; | |
1008 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
1009 | ||
1010 | frame_unwind_unsigned_register (next_frame, SOFT_FP_REGNUM, &tos); | |
1011 | tos += 2; | |
1012 | return frame_id_build (tos, pc); | |
1013 | } | |
78073dd8 | 1014 | |
e286caf2 SC |
1015 | \f |
1016 | /* Get and print the register from the given frame. */ | |
78073dd8 | 1017 | static void |
e286caf2 SC |
1018 | m68hc11_print_register (struct gdbarch *gdbarch, struct ui_file *file, |
1019 | struct frame_info *frame, int regno) | |
78073dd8 | 1020 | { |
e286caf2 SC |
1021 | LONGEST rval; |
1022 | ||
1023 | if (regno == HARD_PC_REGNUM || regno == HARD_SP_REGNUM | |
1024 | || regno == SOFT_FP_REGNUM || regno == M68HC12_HARD_PC_REGNUM) | |
7f5f525d | 1025 | rval = get_frame_register_unsigned (frame, regno); |
e286caf2 | 1026 | else |
7f5f525d | 1027 | rval = get_frame_register_signed (frame, regno); |
e286caf2 SC |
1028 | |
1029 | if (regno == HARD_A_REGNUM || regno == HARD_B_REGNUM | |
1030 | || regno == HARD_CCR_REGNUM || regno == HARD_PAGE_REGNUM) | |
7df11f59 | 1031 | { |
e286caf2 SC |
1032 | fprintf_filtered (file, "0x%02x ", (unsigned char) rval); |
1033 | if (regno != HARD_CCR_REGNUM) | |
1034 | print_longest (file, 'd', 1, rval); | |
7df11f59 | 1035 | } |
e286caf2 SC |
1036 | else |
1037 | { | |
1038 | if (regno == HARD_PC_REGNUM && gdbarch_tdep (gdbarch)->use_page_register) | |
1039 | { | |
1040 | ULONGEST page; | |
7df11f59 | 1041 | |
7f5f525d | 1042 | page = get_frame_register_unsigned (frame, HARD_PAGE_REGNUM); |
e286caf2 SC |
1043 | fprintf_filtered (file, "0x%02x:%04x ", (unsigned) page, |
1044 | (unsigned) rval); | |
1045 | } | |
1046 | else | |
1047 | { | |
1048 | fprintf_filtered (file, "0x%04x ", (unsigned) rval); | |
1049 | if (regno != HARD_PC_REGNUM && regno != HARD_SP_REGNUM | |
1050 | && regno != SOFT_FP_REGNUM && regno != M68HC12_HARD_PC_REGNUM) | |
1051 | print_longest (file, 'd', 1, rval); | |
1052 | } | |
1053 | } | |
1054 | ||
1055 | if (regno == HARD_CCR_REGNUM) | |
78073dd8 | 1056 | { |
e286caf2 SC |
1057 | /* CCR register */ |
1058 | int C, Z, N, V; | |
1059 | unsigned char l = rval & 0xff; | |
1060 | ||
1061 | fprintf_filtered (file, "%c%c%c%c%c%c%c%c ", | |
1062 | l & M6811_S_BIT ? 'S' : '-', | |
1063 | l & M6811_X_BIT ? 'X' : '-', | |
1064 | l & M6811_H_BIT ? 'H' : '-', | |
1065 | l & M6811_I_BIT ? 'I' : '-', | |
1066 | l & M6811_N_BIT ? 'N' : '-', | |
1067 | l & M6811_Z_BIT ? 'Z' : '-', | |
1068 | l & M6811_V_BIT ? 'V' : '-', | |
1069 | l & M6811_C_BIT ? 'C' : '-'); | |
1070 | N = (l & M6811_N_BIT) != 0; | |
1071 | Z = (l & M6811_Z_BIT) != 0; | |
1072 | V = (l & M6811_V_BIT) != 0; | |
1073 | C = (l & M6811_C_BIT) != 0; | |
1074 | ||
1075 | /* Print flags following the h8300 */ | |
1076 | if ((C | Z) == 0) | |
1077 | fprintf_filtered (file, "u> "); | |
1078 | else if ((C | Z) == 1) | |
1079 | fprintf_filtered (file, "u<= "); | |
1080 | else if (C == 0) | |
1081 | fprintf_filtered (file, "u< "); | |
1082 | ||
1083 | if (Z == 0) | |
1084 | fprintf_filtered (file, "!= "); | |
1085 | else | |
1086 | fprintf_filtered (file, "== "); | |
1087 | ||
1088 | if ((N ^ V) == 0) | |
1089 | fprintf_filtered (file, ">= "); | |
1090 | else | |
1091 | fprintf_filtered (file, "< "); | |
1092 | ||
1093 | if ((Z | (N ^ V)) == 0) | |
1094 | fprintf_filtered (file, "> "); | |
78073dd8 | 1095 | else |
e286caf2 | 1096 | fprintf_filtered (file, "<= "); |
78073dd8 | 1097 | } |
e286caf2 SC |
1098 | } |
1099 | ||
1100 | /* Same as 'info reg' but prints the registers in a different way. */ | |
1101 | static void | |
1102 | m68hc11_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, | |
1103 | struct frame_info *frame, int regno, int cpregs) | |
1104 | { | |
1105 | if (regno >= 0) | |
1106 | { | |
1107 | const char *name = gdbarch_register_name (gdbarch, regno); | |
1108 | ||
1109 | if (!name || !*name) | |
1110 | return; | |
1111 | ||
1112 | fprintf_filtered (file, "%-10s ", name); | |
1113 | m68hc11_print_register (gdbarch, file, frame, regno); | |
1114 | fprintf_filtered (file, "\n"); | |
1115 | } | |
1116 | else | |
1117 | { | |
1118 | int i, nr; | |
1119 | ||
1120 | fprintf_filtered (file, "PC="); | |
1121 | m68hc11_print_register (gdbarch, file, frame, HARD_PC_REGNUM); | |
1122 | ||
1123 | fprintf_filtered (file, " SP="); | |
1124 | m68hc11_print_register (gdbarch, file, frame, HARD_SP_REGNUM); | |
1125 | ||
1126 | fprintf_filtered (file, " FP="); | |
1127 | m68hc11_print_register (gdbarch, file, frame, SOFT_FP_REGNUM); | |
1128 | ||
1129 | fprintf_filtered (file, "\nCCR="); | |
1130 | m68hc11_print_register (gdbarch, file, frame, HARD_CCR_REGNUM); | |
1131 | ||
1132 | fprintf_filtered (file, "\nD="); | |
1133 | m68hc11_print_register (gdbarch, file, frame, HARD_D_REGNUM); | |
1134 | ||
1135 | fprintf_filtered (file, " X="); | |
1136 | m68hc11_print_register (gdbarch, file, frame, HARD_X_REGNUM); | |
1137 | ||
1138 | fprintf_filtered (file, " Y="); | |
1139 | m68hc11_print_register (gdbarch, file, frame, HARD_Y_REGNUM); | |
1140 | ||
1141 | if (gdbarch_tdep (gdbarch)->use_page_register) | |
1142 | { | |
1143 | fprintf_filtered (file, "\nPage="); | |
1144 | m68hc11_print_register (gdbarch, file, frame, HARD_PAGE_REGNUM); | |
1145 | } | |
1146 | fprintf_filtered (file, "\n"); | |
1147 | ||
1148 | nr = 0; | |
1149 | for (i = SOFT_D1_REGNUM; i < M68HC11_ALL_REGS; i++) | |
1150 | { | |
1151 | /* Skip registers which are not defined in the symbol table. */ | |
1152 | if (soft_regs[i].name == 0) | |
1153 | continue; | |
1154 | ||
1155 | fprintf_filtered (file, "D%d=", i - SOFT_D1_REGNUM + 1); | |
1156 | m68hc11_print_register (gdbarch, file, frame, i); | |
1157 | nr++; | |
1158 | if ((nr % 8) == 7) | |
1159 | fprintf_filtered (file, "\n"); | |
1160 | else | |
1161 | fprintf_filtered (file, " "); | |
1162 | } | |
1163 | if (nr && (nr % 8) != 7) | |
1164 | fprintf_filtered (file, "\n"); | |
1165 | } | |
1166 | } | |
1167 | ||
1168 | /* Same as 'info reg' but prints the registers in a different way. */ | |
1169 | static void | |
1170 | show_regs (char *args, int from_tty) | |
1171 | { | |
1172 | m68hc11_print_registers_info (current_gdbarch, gdb_stdout, | |
1173 | get_current_frame (), -1, 1); | |
78073dd8 AC |
1174 | } |
1175 | ||
22df305e SC |
1176 | static CORE_ADDR |
1177 | m68hc11_stack_align (CORE_ADDR addr) | |
1178 | { | |
1179 | return ((addr + 1) & -2); | |
1180 | } | |
1181 | ||
82c230c2 | 1182 | static CORE_ADDR |
3dc990bf SC |
1183 | m68hc11_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
1184 | struct regcache *regcache, CORE_ADDR bp_addr, | |
1185 | int nargs, struct value **args, CORE_ADDR sp, | |
1186 | int struct_return, CORE_ADDR struct_addr) | |
78073dd8 | 1187 | { |
82c230c2 SC |
1188 | int argnum; |
1189 | int first_stack_argnum; | |
82c230c2 SC |
1190 | struct type *type; |
1191 | char *val; | |
1192 | int len; | |
3dc990bf | 1193 | char buf[2]; |
82c230c2 | 1194 | |
82c230c2 SC |
1195 | first_stack_argnum = 0; |
1196 | if (struct_return) | |
1197 | { | |
184651e3 SC |
1198 | /* The struct is allocated on the stack and gdb used the stack |
1199 | pointer for the address of that struct. We must apply the | |
1200 | stack offset on the address. */ | |
3dc990bf SC |
1201 | regcache_cooked_write_unsigned (regcache, HARD_D_REGNUM, |
1202 | struct_addr + STACK_CORRECTION); | |
82c230c2 SC |
1203 | } |
1204 | else if (nargs > 0) | |
1205 | { | |
1206 | type = VALUE_TYPE (args[0]); | |
1207 | len = TYPE_LENGTH (type); | |
3dc990bf | 1208 | |
82c230c2 SC |
1209 | /* First argument is passed in D and X registers. */ |
1210 | if (len <= 4) | |
1211 | { | |
3dc990bf SC |
1212 | ULONGEST v; |
1213 | ||
1214 | v = extract_unsigned_integer (VALUE_CONTENTS (args[0]), len); | |
82c230c2 | 1215 | first_stack_argnum = 1; |
3dc990bf SC |
1216 | |
1217 | regcache_cooked_write_unsigned (regcache, HARD_D_REGNUM, v); | |
82c230c2 SC |
1218 | if (len > 2) |
1219 | { | |
1220 | v >>= 16; | |
3dc990bf | 1221 | regcache_cooked_write_unsigned (regcache, HARD_X_REGNUM, v); |
82c230c2 SC |
1222 | } |
1223 | } | |
1224 | } | |
82c230c2 | 1225 | |
3dc990bf | 1226 | for (argnum = nargs - 1; argnum >= first_stack_argnum; argnum--) |
82c230c2 SC |
1227 | { |
1228 | type = VALUE_TYPE (args[argnum]); | |
1229 | len = TYPE_LENGTH (type); | |
1230 | ||
22df305e SC |
1231 | if (len & 1) |
1232 | { | |
1233 | static char zero = 0; | |
1234 | ||
3dc990bf SC |
1235 | sp--; |
1236 | write_memory (sp, &zero, 1); | |
22df305e | 1237 | } |
3dc990bf SC |
1238 | val = (char*) VALUE_CONTENTS (args[argnum]); |
1239 | sp -= len; | |
1240 | write_memory (sp, val, len); | |
82c230c2 | 1241 | } |
3dc990bf SC |
1242 | |
1243 | /* Store return address. */ | |
1244 | sp -= 2; | |
1245 | store_unsigned_integer (buf, 2, bp_addr); | |
1246 | write_memory (sp, buf, 2); | |
1247 | ||
1248 | /* Finally, update the stack pointer... */ | |
1249 | sp -= STACK_CORRECTION; | |
1250 | regcache_cooked_write_unsigned (regcache, HARD_SP_REGNUM, sp); | |
1251 | ||
1252 | /* ...and fake a frame pointer. */ | |
1253 | regcache_cooked_write_unsigned (regcache, SOFT_FP_REGNUM, sp); | |
1254 | ||
1255 | /* DWARF2/GCC uses the stack address *before* the function call as a | |
1256 | frame's CFA. */ | |
1257 | return sp + 2; | |
78073dd8 AC |
1258 | } |
1259 | ||
1260 | ||
4db73d49 SC |
1261 | /* Return the GDB type object for the "standard" data type |
1262 | of data in register N. */ | |
1263 | ||
82c230c2 | 1264 | static struct type * |
4db73d49 | 1265 | m68hc11_register_type (struct gdbarch *gdbarch, int reg_nr) |
82c230c2 | 1266 | { |
5706502a SC |
1267 | switch (reg_nr) |
1268 | { | |
1269 | case HARD_PAGE_REGNUM: | |
1270 | case HARD_A_REGNUM: | |
1271 | case HARD_B_REGNUM: | |
1272 | case HARD_CCR_REGNUM: | |
1273 | return builtin_type_uint8; | |
1274 | ||
548bcbec SC |
1275 | case M68HC12_HARD_PC_REGNUM: |
1276 | return builtin_type_uint32; | |
1277 | ||
5706502a SC |
1278 | default: |
1279 | return builtin_type_uint16; | |
1280 | } | |
82c230c2 SC |
1281 | } |
1282 | ||
82c230c2 | 1283 | static void |
4db73d49 SC |
1284 | m68hc11_store_return_value (struct type *type, struct regcache *regcache, |
1285 | const void *valbuf) | |
82c230c2 | 1286 | { |
22df305e SC |
1287 | int len; |
1288 | ||
1289 | len = TYPE_LENGTH (type); | |
1290 | ||
1291 | /* First argument is passed in D and X registers. */ | |
4db73d49 SC |
1292 | if (len <= 2) |
1293 | regcache_raw_write_part (regcache, HARD_D_REGNUM, 2 - len, len, valbuf); | |
1294 | else if (len <= 4) | |
22df305e | 1295 | { |
4db73d49 SC |
1296 | regcache_raw_write_part (regcache, HARD_X_REGNUM, 4 - len, |
1297 | len - 2, valbuf); | |
1298 | regcache_raw_write (regcache, HARD_D_REGNUM, (char*) valbuf + (len - 2)); | |
22df305e SC |
1299 | } |
1300 | else | |
1301 | error ("return of value > 4 is not supported."); | |
82c230c2 SC |
1302 | } |
1303 | ||
1304 | ||
ef2b8fcd | 1305 | /* Given a return value in `regcache' with a type `type', |
78073dd8 AC |
1306 | extract and copy its value into `valbuf'. */ |
1307 | ||
82c230c2 | 1308 | static void |
ef2b8fcd SC |
1309 | m68hc11_extract_return_value (struct type *type, struct regcache *regcache, |
1310 | void *valbuf) | |
78073dd8 | 1311 | { |
82c230c2 | 1312 | int len = TYPE_LENGTH (type); |
ef2b8fcd SC |
1313 | char buf[M68HC11_REG_SIZE]; |
1314 | ||
1315 | regcache_raw_read (regcache, HARD_D_REGNUM, buf); | |
22df305e | 1316 | switch (len) |
82c230c2 | 1317 | { |
22df305e | 1318 | case 1: |
ef2b8fcd | 1319 | memcpy (valbuf, buf + 1, 1); |
22df305e | 1320 | break; |
ef2b8fcd | 1321 | |
22df305e | 1322 | case 2: |
ef2b8fcd | 1323 | memcpy (valbuf, buf, 2); |
22df305e | 1324 | break; |
ef2b8fcd | 1325 | |
22df305e | 1326 | case 3: |
ef2b8fcd SC |
1327 | memcpy ((char*) valbuf + 1, buf, 2); |
1328 | regcache_raw_read (regcache, HARD_X_REGNUM, buf); | |
1329 | memcpy (valbuf, buf + 1, 1); | |
22df305e | 1330 | break; |
ef2b8fcd | 1331 | |
22df305e | 1332 | case 4: |
ef2b8fcd SC |
1333 | memcpy ((char*) valbuf + 2, buf, 2); |
1334 | regcache_raw_read (regcache, HARD_X_REGNUM, buf); | |
1335 | memcpy (valbuf, buf, 2); | |
22df305e SC |
1336 | break; |
1337 | ||
1338 | default: | |
82c230c2 SC |
1339 | error ("bad size for return value"); |
1340 | } | |
1341 | } | |
1342 | ||
1343 | /* Should call_function allocate stack space for a struct return? */ | |
1344 | static int | |
1345 | m68hc11_use_struct_convention (int gcc_p, struct type *type) | |
1346 | { | |
22df305e SC |
1347 | return (TYPE_CODE (type) == TYPE_CODE_STRUCT |
1348 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
1349 | || TYPE_LENGTH (type) > 4); | |
82c230c2 SC |
1350 | } |
1351 | ||
1352 | static int | |
1353 | m68hc11_return_value_on_stack (struct type *type) | |
1354 | { | |
22df305e | 1355 | return TYPE_LENGTH (type) > 4; |
82c230c2 SC |
1356 | } |
1357 | ||
1358 | /* Extract from an array REGBUF containing the (raw) register state | |
1359 | the address in which a function should return its structure value, | |
1360 | as a CORE_ADDR (or an expression that can be used as one). */ | |
1361 | static CORE_ADDR | |
4db73d49 | 1362 | m68hc11_extract_struct_value_address (struct regcache *regcache) |
82c230c2 | 1363 | { |
4db73d49 SC |
1364 | char buf[M68HC11_REG_SIZE]; |
1365 | ||
1366 | regcache_cooked_read (regcache, HARD_D_REGNUM, buf); | |
1367 | return extract_unsigned_integer (buf, M68HC11_REG_SIZE); | |
82c230c2 SC |
1368 | } |
1369 | ||
7df11f59 SC |
1370 | /* Test whether the ELF symbol corresponds to a function using rtc or |
1371 | rti to return. */ | |
1372 | ||
1373 | static void | |
1374 | m68hc11_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym) | |
1375 | { | |
1376 | unsigned char flags; | |
1377 | ||
1378 | flags = ((elf_symbol_type *)sym)->internal_elf_sym.st_other; | |
1379 | if (flags & STO_M68HC12_FAR) | |
1380 | MSYMBOL_SET_RTC (msym); | |
1381 | if (flags & STO_M68HC12_INTERRUPT) | |
1382 | MSYMBOL_SET_RTI (msym); | |
1383 | } | |
1384 | ||
ea3881d9 SC |
1385 | static int |
1386 | gdb_print_insn_m68hc11 (bfd_vma memaddr, disassemble_info *info) | |
1387 | { | |
1388 | if (TARGET_ARCHITECTURE->arch == bfd_arch_m68hc11) | |
1389 | return print_insn_m68hc11 (memaddr, info); | |
1390 | else | |
1391 | return print_insn_m68hc12 (memaddr, info); | |
1392 | } | |
1393 | ||
b631436b SC |
1394 | \f |
1395 | ||
1396 | /* 68HC11/68HC12 register groups. | |
1397 | Identify real hard registers and soft registers used by gcc. */ | |
1398 | ||
1399 | static struct reggroup *m68hc11_soft_reggroup; | |
1400 | static struct reggroup *m68hc11_hard_reggroup; | |
1401 | ||
1402 | static void | |
1403 | m68hc11_init_reggroups (void) | |
1404 | { | |
1405 | m68hc11_hard_reggroup = reggroup_new ("hard", USER_REGGROUP); | |
1406 | m68hc11_soft_reggroup = reggroup_new ("soft", USER_REGGROUP); | |
1407 | } | |
1408 | ||
1409 | static void | |
1410 | m68hc11_add_reggroups (struct gdbarch *gdbarch) | |
1411 | { | |
1412 | reggroup_add (gdbarch, m68hc11_hard_reggroup); | |
1413 | reggroup_add (gdbarch, m68hc11_soft_reggroup); | |
1414 | reggroup_add (gdbarch, general_reggroup); | |
1415 | reggroup_add (gdbarch, float_reggroup); | |
1416 | reggroup_add (gdbarch, all_reggroup); | |
1417 | reggroup_add (gdbarch, save_reggroup); | |
1418 | reggroup_add (gdbarch, restore_reggroup); | |
1419 | reggroup_add (gdbarch, vector_reggroup); | |
1420 | reggroup_add (gdbarch, system_reggroup); | |
1421 | } | |
1422 | ||
1423 | static int | |
1424 | m68hc11_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
1425 | struct reggroup *group) | |
1426 | { | |
1427 | /* We must save the real hard register as well as gcc | |
1428 | soft registers including the frame pointer. */ | |
1429 | if (group == save_reggroup || group == restore_reggroup) | |
1430 | { | |
1431 | return (regnum <= gdbarch_num_regs (gdbarch) | |
1432 | || ((regnum == SOFT_FP_REGNUM | |
1433 | || regnum == SOFT_TMP_REGNUM | |
1434 | || regnum == SOFT_ZS_REGNUM | |
1435 | || regnum == SOFT_XY_REGNUM) | |
1436 | && m68hc11_register_name (regnum))); | |
1437 | } | |
1438 | ||
1439 | /* Group to identify gcc soft registers (d1..dN). */ | |
1440 | if (group == m68hc11_soft_reggroup) | |
1441 | { | |
1442 | return regnum >= SOFT_D1_REGNUM && m68hc11_register_name (regnum); | |
1443 | } | |
1444 | ||
1445 | if (group == m68hc11_hard_reggroup) | |
1446 | { | |
1447 | return regnum == HARD_PC_REGNUM || regnum == HARD_SP_REGNUM | |
1448 | || regnum == HARD_X_REGNUM || regnum == HARD_D_REGNUM | |
1449 | || regnum == HARD_Y_REGNUM || regnum == HARD_CCR_REGNUM; | |
1450 | } | |
1451 | return default_register_reggroup_p (gdbarch, regnum, group); | |
1452 | } | |
1453 | ||
82c230c2 SC |
1454 | static struct gdbarch * |
1455 | m68hc11_gdbarch_init (struct gdbarch_info info, | |
1456 | struct gdbarch_list *arches) | |
1457 | { | |
82c230c2 SC |
1458 | struct gdbarch *gdbarch; |
1459 | struct gdbarch_tdep *tdep; | |
81967506 | 1460 | int elf_flags; |
82c230c2 SC |
1461 | |
1462 | soft_reg_initialized = 0; | |
81967506 SC |
1463 | |
1464 | /* Extract the elf_flags if available. */ | |
1465 | if (info.abfd != NULL | |
1466 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
1467 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
1468 | else | |
1469 | elf_flags = 0; | |
1470 | ||
82c230c2 SC |
1471 | /* try to find a pre-existing architecture */ |
1472 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
1473 | arches != NULL; | |
1474 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
1475 | { | |
81967506 SC |
1476 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
1477 | continue; | |
1478 | ||
82c230c2 SC |
1479 | return arches->gdbarch; |
1480 | } | |
1481 | ||
1482 | /* Need a new architecture. Fill in a target specific vector. */ | |
1483 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); | |
1484 | gdbarch = gdbarch_alloc (&info, tdep); | |
81967506 | 1485 | tdep->elf_flags = elf_flags; |
ed99b3d0 | 1486 | |
5d1a66bd SC |
1487 | switch (info.bfd_arch_info->arch) |
1488 | { | |
1489 | case bfd_arch_m68hc11: | |
1490 | tdep->stack_correction = 1; | |
7df11f59 | 1491 | tdep->use_page_register = 0; |
908f682f | 1492 | tdep->prologue = m6811_prologue; |
548bcbec SC |
1493 | set_gdbarch_addr_bit (gdbarch, 16); |
1494 | set_gdbarch_num_pseudo_regs (gdbarch, M68HC11_NUM_PSEUDO_REGS); | |
1495 | set_gdbarch_pc_regnum (gdbarch, HARD_PC_REGNUM); | |
1496 | set_gdbarch_num_regs (gdbarch, M68HC11_NUM_REGS); | |
5d1a66bd | 1497 | break; |
82c230c2 | 1498 | |
5d1a66bd SC |
1499 | case bfd_arch_m68hc12: |
1500 | tdep->stack_correction = 0; | |
7df11f59 | 1501 | tdep->use_page_register = elf_flags & E_M68HC12_BANKS; |
908f682f | 1502 | tdep->prologue = m6812_prologue; |
548bcbec SC |
1503 | set_gdbarch_addr_bit (gdbarch, elf_flags & E_M68HC12_BANKS ? 32 : 16); |
1504 | set_gdbarch_num_pseudo_regs (gdbarch, | |
1505 | elf_flags & E_M68HC12_BANKS | |
1506 | ? M68HC12_NUM_PSEUDO_REGS | |
1507 | : M68HC11_NUM_PSEUDO_REGS); | |
1508 | set_gdbarch_pc_regnum (gdbarch, elf_flags & E_M68HC12_BANKS | |
1509 | ? M68HC12_HARD_PC_REGNUM : HARD_PC_REGNUM); | |
1510 | set_gdbarch_num_regs (gdbarch, elf_flags & E_M68HC12_BANKS | |
1511 | ? M68HC12_NUM_REGS : M68HC11_NUM_REGS); | |
5d1a66bd SC |
1512 | break; |
1513 | ||
1514 | default: | |
1515 | break; | |
1516 | } | |
7d32ba20 SC |
1517 | |
1518 | /* Initially set everything according to the ABI. | |
1519 | Use 16-bit integers since it will be the case for most | |
1520 | programs. The size of these types should normally be set | |
1521 | according to the dwarf2 debug information. */ | |
82c230c2 | 1522 | set_gdbarch_short_bit (gdbarch, 16); |
81967506 | 1523 | set_gdbarch_int_bit (gdbarch, elf_flags & E_M68HC11_I32 ? 32 : 16); |
82c230c2 | 1524 | set_gdbarch_float_bit (gdbarch, 32); |
81967506 | 1525 | set_gdbarch_double_bit (gdbarch, elf_flags & E_M68HC11_F64 ? 64 : 32); |
2417dd25 | 1526 | set_gdbarch_long_double_bit (gdbarch, 64); |
82c230c2 SC |
1527 | set_gdbarch_long_bit (gdbarch, 32); |
1528 | set_gdbarch_ptr_bit (gdbarch, 16); | |
1529 | set_gdbarch_long_long_bit (gdbarch, 64); | |
1530 | ||
b2a02dda SC |
1531 | /* Characters are unsigned. */ |
1532 | set_gdbarch_char_signed (gdbarch, 0); | |
1533 | ||
1ea653ae SC |
1534 | set_gdbarch_unwind_pc (gdbarch, m68hc11_unwind_pc); |
1535 | set_gdbarch_unwind_sp (gdbarch, m68hc11_unwind_sp); | |
1536 | ||
82c230c2 SC |
1537 | /* Set register info. */ |
1538 | set_gdbarch_fp0_regnum (gdbarch, -1); | |
82c230c2 SC |
1539 | set_gdbarch_frame_args_skip (gdbarch, 0); |
1540 | ||
82c230c2 | 1541 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); |
82c230c2 | 1542 | |
82c230c2 | 1543 | set_gdbarch_sp_regnum (gdbarch, HARD_SP_REGNUM); |
82c230c2 | 1544 | set_gdbarch_register_name (gdbarch, m68hc11_register_name); |
4db73d49 | 1545 | set_gdbarch_register_type (gdbarch, m68hc11_register_type); |
46ce284d AC |
1546 | set_gdbarch_pseudo_register_read (gdbarch, m68hc11_pseudo_register_read); |
1547 | set_gdbarch_pseudo_register_write (gdbarch, m68hc11_pseudo_register_write); | |
82c230c2 | 1548 | |
3dc990bf SC |
1549 | set_gdbarch_push_dummy_call (gdbarch, m68hc11_push_dummy_call); |
1550 | ||
ef2b8fcd | 1551 | set_gdbarch_extract_return_value (gdbarch, m68hc11_extract_return_value); |
82c230c2 SC |
1552 | set_gdbarch_return_value_on_stack (gdbarch, m68hc11_return_value_on_stack); |
1553 | ||
4db73d49 | 1554 | set_gdbarch_store_return_value (gdbarch, m68hc11_store_return_value); |
0880807f | 1555 | set_gdbarch_store_return_value (gdbarch, m68hc11_store_return_value); |
74055713 | 1556 | set_gdbarch_deprecated_extract_struct_value_address (gdbarch, m68hc11_extract_struct_value_address); |
82c230c2 | 1557 | set_gdbarch_use_struct_convention (gdbarch, m68hc11_use_struct_convention); |
82c230c2 SC |
1558 | set_gdbarch_skip_prologue (gdbarch, m68hc11_skip_prologue); |
1559 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
82c230c2 | 1560 | set_gdbarch_breakpoint_from_pc (gdbarch, m68hc11_breakpoint_from_pc); |
f27dd7fd | 1561 | set_gdbarch_deprecated_stack_align (gdbarch, m68hc11_stack_align); |
70ed8774 | 1562 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_m68hc11); |
82c230c2 | 1563 | |
b631436b SC |
1564 | m68hc11_add_reggroups (gdbarch); |
1565 | set_gdbarch_register_reggroup_p (gdbarch, m68hc11_register_reggroup_p); | |
e286caf2 | 1566 | set_gdbarch_print_registers_info (gdbarch, m68hc11_print_registers_info); |
b631436b | 1567 | |
1ea653ae SC |
1568 | /* Hook in the DWARF CFI frame unwinder. */ |
1569 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); | |
1ea653ae | 1570 | |
1a241548 | 1571 | frame_unwind_append_sniffer (gdbarch, m68hc11_frame_sniffer); |
1ea653ae SC |
1572 | frame_base_set_default (gdbarch, &m68hc11_frame_base); |
1573 | ||
1574 | /* Methods for saving / extracting a dummy frame's ID. The ID's | |
1575 | stack address must match the SP value returned by | |
1576 | PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */ | |
1577 | set_gdbarch_unwind_dummy_id (gdbarch, m68hc11_unwind_dummy_id); | |
1578 | ||
1579 | /* Return the unwound PC value. */ | |
1580 | set_gdbarch_unwind_pc (gdbarch, m68hc11_unwind_pc); | |
1581 | ||
7df11f59 SC |
1582 | /* Minsymbol frobbing. */ |
1583 | set_gdbarch_elf_make_msymbol_special (gdbarch, | |
1584 | m68hc11_elf_make_msymbol_special); | |
1585 | ||
82c230c2 | 1586 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
82c230c2 SC |
1587 | |
1588 | return gdbarch; | |
78073dd8 AC |
1589 | } |
1590 | ||
a78f21af AC |
1591 | extern initialize_file_ftype _initialize_m68hc11_tdep; /* -Wmissing-prototypes */ |
1592 | ||
78073dd8 | 1593 | void |
fba45db2 | 1594 | _initialize_m68hc11_tdep (void) |
78073dd8 | 1595 | { |
82c230c2 | 1596 | register_gdbarch_init (bfd_arch_m68hc11, m68hc11_gdbarch_init); |
ea3881d9 | 1597 | register_gdbarch_init (bfd_arch_m68hc12, m68hc11_gdbarch_init); |
b631436b | 1598 | m68hc11_init_reggroups (); |
78073dd8 | 1599 | |
e286caf2 SC |
1600 | deprecate_cmd (add_com ("regs", class_vars, show_regs, |
1601 | "Print all registers"), | |
1602 | "info registers"); | |
78073dd8 AC |
1603 | } |
1604 |