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c906108c | 1 | /* Target-machine dependent code for Motorola 88000 series, for GDB. |
b6ba6518 KB |
2 | Copyright 1988, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1998, 2000, |
3 | 2001 Free Software Foundation, Inc. | |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
21 | |
22 | #include "defs.h" | |
23 | #include "frame.h" | |
24 | #include "inferior.h" | |
25 | #include "value.h" | |
26 | #include "gdbcore.h" | |
27 | #include "symtab.h" | |
28 | #include "setjmp.h" | |
29 | #include "value.h" | |
4e052eda | 30 | #include "regcache.h" |
c906108c SS |
31 | |
32 | /* Size of an instruction */ | |
33 | #define BYTES_PER_88K_INSN 4 | |
34 | ||
35 | void frame_find_saved_regs (); | |
36 | ||
37 | /* Is this target an m88110? Otherwise assume m88100. This has | |
38 | relevance for the ways in which we screw with instruction pointers. */ | |
39 | ||
40 | int target_is_m88110 = 0; | |
41 | ||
2c10d744 AC |
42 | /* The type of a register. */ |
43 | struct type * | |
44 | m88k_register_type (int regnum) | |
45 | { | |
46 | if (regnum >= XFP_REGNUM) | |
47 | return builtin_type_m88110_ext; | |
48 | else if (regnum == PC_REGNUM || regnum == FP_REGNUM || regnum == SP_REGNUM) | |
49 | return builtin_type_void_func_ptr; | |
50 | else | |
51 | return builtin_type_int32; | |
52 | } | |
53 | ||
54 | ||
c906108c SS |
55 | /* The m88k kernel aligns all instructions on 4-byte boundaries. The |
56 | kernel also uses the least significant two bits for its own hocus | |
57 | pocus. When gdb receives an address from the kernel, it needs to | |
58 | preserve those right-most two bits, but gdb also needs to be careful | |
59 | to realize that those two bits are not really a part of the address | |
60 | of an instruction. Shrug. */ | |
61 | ||
62 | CORE_ADDR | |
fba45db2 | 63 | m88k_addr_bits_remove (CORE_ADDR addr) |
c906108c SS |
64 | { |
65 | return ((addr) & ~3); | |
66 | } | |
67 | ||
68 | ||
69 | /* Given a GDB frame, determine the address of the calling function's frame. | |
70 | This will be used to create a new GDB frame struct, and then | |
71 | INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame. | |
72 | ||
73 | For us, the frame address is its stack pointer value, so we look up | |
74 | the function prologue to determine the caller's sp value, and return it. */ | |
75 | ||
76 | CORE_ADDR | |
fba45db2 | 77 | frame_chain (struct frame_info *thisframe) |
c906108c SS |
78 | { |
79 | ||
80 | frame_find_saved_regs (thisframe, (struct frame_saved_regs *) 0); | |
81 | /* NOTE: this depends on frame_find_saved_regs returning the VALUE, not | |
c5aa993b JM |
82 | the ADDRESS, of SP_REGNUM. It also depends on the cache of |
83 | frame_find_saved_regs results. */ | |
c906108c SS |
84 | if (thisframe->fsr->regs[SP_REGNUM]) |
85 | return thisframe->fsr->regs[SP_REGNUM]; | |
86 | else | |
87 | return thisframe->frame; /* Leaf fn -- next frame up has same SP. */ | |
88 | } | |
89 | ||
90 | int | |
fba45db2 | 91 | frameless_function_invocation (struct frame_info *frame) |
c906108c SS |
92 | { |
93 | ||
94 | frame_find_saved_regs (frame, (struct frame_saved_regs *) 0); | |
95 | /* NOTE: this depends on frame_find_saved_regs returning the VALUE, not | |
c5aa993b JM |
96 | the ADDRESS, of SP_REGNUM. It also depends on the cache of |
97 | frame_find_saved_regs results. */ | |
c906108c SS |
98 | if (frame->fsr->regs[SP_REGNUM]) |
99 | return 0; /* Frameful -- return addr saved somewhere */ | |
100 | else | |
101 | return 1; /* Frameless -- no saved return address */ | |
102 | } | |
103 | ||
104 | void | |
fba45db2 | 105 | init_extra_frame_info (int fromleaf, struct frame_info *frame) |
c906108c | 106 | { |
c5aa993b JM |
107 | frame->fsr = 0; /* Not yet allocated */ |
108 | frame->args_pointer = 0; /* Unknown */ | |
c906108c SS |
109 | frame->locals_pointer = 0; /* Unknown */ |
110 | } | |
111 | \f | |
112 | /* Examine an m88k function prologue, recording the addresses at which | |
113 | registers are saved explicitly by the prologue code, and returning | |
114 | the address of the first instruction after the prologue (but not | |
115 | after the instruction at address LIMIT, as explained below). | |
116 | ||
117 | LIMIT places an upper bound on addresses of the instructions to be | |
118 | examined. If the prologue code scan reaches LIMIT, the scan is | |
119 | aborted and LIMIT is returned. This is used, when examining the | |
120 | prologue for the current frame, to keep examine_prologue () from | |
121 | claiming that a given register has been saved when in fact the | |
122 | instruction that saves it has not yet been executed. LIMIT is used | |
123 | at other times to stop the scan when we hit code after the true | |
124 | function prologue (e.g. for the first source line) which might | |
125 | otherwise be mistaken for function prologue. | |
126 | ||
127 | The format of the function prologue matched by this routine is | |
128 | derived from examination of the source to gcc 1.95, particularly | |
129 | the routine output_prologue () in config/out-m88k.c. | |
130 | ||
c5aa993b | 131 | subu r31,r31,n # stack pointer update |
c906108c | 132 | |
c5aa993b | 133 | (st rn,r31,offset)? # save incoming regs |
c906108c SS |
134 | (st.d rn,r31,offset)? |
135 | ||
c5aa993b | 136 | (addu r30,r31,n)? # frame pointer update |
c906108c | 137 | |
c5aa993b | 138 | (pic sequence)? # PIC code prologue |
c906108c | 139 | |
c5aa993b JM |
140 | (or rn,rm,0)? # Move parameters to other regs |
141 | */ | |
c906108c SS |
142 | |
143 | /* Macros for extracting fields from instructions. */ | |
144 | ||
145 | #define BITMASK(pos, width) (((0x1 << (width)) - 1) << (pos)) | |
146 | #define EXTRACT_FIELD(val, pos, width) ((val) >> (pos) & BITMASK (0, width)) | |
147 | #define SUBU_OFFSET(x) ((unsigned)(x & 0xFFFF)) | |
148 | #define ST_OFFSET(x) ((unsigned)((x) & 0xFFFF)) | |
149 | #define ST_SRC(x) EXTRACT_FIELD ((x), 21, 5) | |
150 | #define ADDU_OFFSET(x) ((unsigned)(x & 0xFFFF)) | |
151 | ||
152 | /* | |
153 | * prologue_insn_tbl is a table of instructions which may comprise a | |
154 | * function prologue. Associated with each table entry (corresponding | |
155 | * to a single instruction or group of instructions), is an action. | |
156 | * This action is used by examine_prologue (below) to determine | |
157 | * the state of certain machine registers and where the stack frame lives. | |
158 | */ | |
159 | ||
c5aa993b JM |
160 | enum prologue_insn_action |
161 | { | |
c906108c SS |
162 | PIA_SKIP, /* don't care what the instruction does */ |
163 | PIA_NOTE_ST, /* note register stored and where */ | |
164 | PIA_NOTE_STD, /* note pair of registers stored and where */ | |
165 | PIA_NOTE_SP_ADJUSTMENT, /* note stack pointer adjustment */ | |
166 | PIA_NOTE_FP_ASSIGNMENT, /* note frame pointer assignment */ | |
167 | PIA_NOTE_PROLOGUE_END, /* no more prologue */ | |
168 | }; | |
169 | ||
c5aa993b JM |
170 | struct prologue_insns |
171 | { | |
c906108c SS |
172 | unsigned long insn; |
173 | unsigned long mask; | |
174 | enum prologue_insn_action action; | |
c5aa993b | 175 | }; |
c906108c | 176 | |
c5aa993b JM |
177 | struct prologue_insns prologue_insn_tbl[] = |
178 | { | |
c906108c | 179 | /* Various register move instructions */ |
c5aa993b JM |
180 | {0x58000000, 0xf800ffff, PIA_SKIP}, /* or/or.u with immed of 0 */ |
181 | {0xf4005800, 0xfc1fffe0, PIA_SKIP}, /* or rd, r0, rs */ | |
182 | {0xf4005800, 0xfc00ffff, PIA_SKIP}, /* or rd, rs, r0 */ | |
c906108c SS |
183 | |
184 | /* Stack pointer setup: "subu sp, sp, n" where n is a multiple of 8 */ | |
c5aa993b | 185 | {0x67ff0000, 0xffff0007, PIA_NOTE_SP_ADJUSTMENT}, |
c906108c SS |
186 | |
187 | /* Frame pointer assignment: "addu r30, r31, n" */ | |
c5aa993b | 188 | {0x63df0000, 0xffff0000, PIA_NOTE_FP_ASSIGNMENT}, |
c906108c SS |
189 | |
190 | /* Store to stack instructions; either "st rx, sp, n" or "st.d rx, sp, n" */ | |
c5aa993b JM |
191 | {0x241f0000, 0xfc1f0000, PIA_NOTE_ST}, /* st rx, sp, n */ |
192 | {0x201f0000, 0xfc1f0000, PIA_NOTE_STD}, /* st.d rs, sp, n */ | |
c906108c SS |
193 | |
194 | /* Instructions needed for setting up r25 for pic code. */ | |
c5aa993b JM |
195 | {0x5f200000, 0xffff0000, PIA_SKIP}, /* or.u r25, r0, offset_high */ |
196 | {0xcc000002, 0xffffffff, PIA_SKIP}, /* bsr.n Lab */ | |
197 | {0x5b390000, 0xffff0000, PIA_SKIP}, /* or r25, r25, offset_low */ | |
198 | {0xf7396001, 0xffffffff, PIA_SKIP}, /* Lab: addu r25, r25, r1 */ | |
c906108c SS |
199 | |
200 | /* Various branch or jump instructions which have a delay slot -- these | |
201 | do not form part of the prologue, but the instruction in the delay | |
202 | slot might be a store instruction which should be noted. */ | |
c5aa993b JM |
203 | {0xc4000000, 0xe4000000, PIA_NOTE_PROLOGUE_END}, |
204 | /* br.n, bsr.n, bb0.n, or bb1.n */ | |
205 | {0xec000000, 0xfc000000, PIA_NOTE_PROLOGUE_END}, /* bcnd.n */ | |
206 | {0xf400c400, 0xfffff7e0, PIA_NOTE_PROLOGUE_END} /* jmp.n or jsr.n */ | |
c906108c SS |
207 | |
208 | }; | |
209 | ||
210 | ||
211 | /* Fetch the instruction at ADDR, returning 0 if ADDR is beyond LIM or | |
212 | is not the address of a valid instruction, the address of the next | |
213 | instruction beyond ADDR otherwise. *PWORD1 receives the first word | |
214 | of the instruction. */ | |
215 | ||
216 | #define NEXT_PROLOGUE_INSN(addr, lim, pword1) \ | |
217 | (((addr) < (lim)) ? next_insn (addr, pword1) : 0) | |
218 | ||
219 | /* Read the m88k instruction at 'memaddr' and return the address of | |
220 | the next instruction after that, or 0 if 'memaddr' is not the | |
221 | address of a valid instruction. The instruction | |
222 | is stored at 'pword1'. */ | |
223 | ||
224 | CORE_ADDR | |
fba45db2 | 225 | next_insn (CORE_ADDR memaddr, unsigned long *pword1) |
c906108c SS |
226 | { |
227 | *pword1 = read_memory_integer (memaddr, BYTES_PER_88K_INSN); | |
228 | return memaddr + BYTES_PER_88K_INSN; | |
229 | } | |
230 | ||
231 | /* Read a register from frames called by us (or from the hardware regs). */ | |
232 | ||
233 | static int | |
fba45db2 | 234 | read_next_frame_reg (struct frame_info *frame, int regno) |
c906108c | 235 | { |
c5aa993b JM |
236 | for (; frame; frame = frame->next) |
237 | { | |
c906108c SS |
238 | if (regno == SP_REGNUM) |
239 | return FRAME_FP (frame); | |
240 | else if (frame->fsr->regs[regno]) | |
c5aa993b JM |
241 | return read_memory_integer (frame->fsr->regs[regno], 4); |
242 | } | |
243 | return read_register (regno); | |
c906108c SS |
244 | } |
245 | ||
246 | /* Examine the prologue of a function. `ip' points to the first instruction. | |
247 | `limit' is the limit of the prologue (e.g. the addr of the first | |
248 | linenumber, or perhaps the program counter if we're stepping through). | |
249 | `frame_sp' is the stack pointer value in use in this frame. | |
250 | `fsr' is a pointer to a frame_saved_regs structure into which we put | |
251 | info about the registers saved by this frame. | |
252 | `fi' is a struct frame_info pointer; we fill in various fields in it | |
253 | to reflect the offsets of the arg pointer and the locals pointer. */ | |
254 | ||
255 | static CORE_ADDR | |
fba45db2 KB |
256 | examine_prologue (register CORE_ADDR ip, register CORE_ADDR limit, |
257 | CORE_ADDR frame_sp, struct frame_saved_regs *fsr, | |
258 | struct frame_info *fi) | |
c906108c SS |
259 | { |
260 | register CORE_ADDR next_ip; | |
261 | register int src; | |
971ff545 | 262 | unsigned long insn; |
c906108c SS |
263 | int size, offset; |
264 | char must_adjust[32]; /* If set, must adjust offsets in fsr */ | |
265 | int sp_offset = -1; /* -1 means not set (valid must be mult of 8) */ | |
266 | int fp_offset = -1; /* -1 means not set */ | |
267 | CORE_ADDR frame_fp; | |
268 | CORE_ADDR prologue_end = 0; | |
269 | ||
270 | memset (must_adjust, '\0', sizeof (must_adjust)); | |
271 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn); | |
272 | ||
273 | while (next_ip) | |
274 | { | |
c5aa993b | 275 | struct prologue_insns *pip; |
c906108c | 276 | |
c5aa993b JM |
277 | for (pip = prologue_insn_tbl; (insn & pip->mask) != pip->insn;) |
278 | if (++pip >= prologue_insn_tbl + sizeof prologue_insn_tbl) | |
279 | goto end_of_prologue_found; /* not a prologue insn */ | |
c906108c SS |
280 | |
281 | switch (pip->action) | |
282 | { | |
c5aa993b JM |
283 | case PIA_NOTE_ST: |
284 | case PIA_NOTE_STD: | |
285 | if (sp_offset != -1) | |
286 | { | |
287 | src = ST_SRC (insn); | |
288 | offset = ST_OFFSET (insn); | |
289 | must_adjust[src] = 1; | |
290 | fsr->regs[src++] = offset; /* Will be adjusted later */ | |
291 | if (pip->action == PIA_NOTE_STD && src < 32) | |
292 | { | |
293 | offset += 4; | |
294 | must_adjust[src] = 1; | |
295 | fsr->regs[src++] = offset; | |
296 | } | |
c906108c | 297 | } |
c5aa993b JM |
298 | else |
299 | goto end_of_prologue_found; | |
300 | break; | |
301 | case PIA_NOTE_SP_ADJUSTMENT: | |
302 | if (sp_offset == -1) | |
303 | sp_offset = -SUBU_OFFSET (insn); | |
304 | else | |
305 | goto end_of_prologue_found; | |
306 | break; | |
307 | case PIA_NOTE_FP_ASSIGNMENT: | |
308 | if (fp_offset == -1) | |
309 | fp_offset = ADDU_OFFSET (insn); | |
310 | else | |
311 | goto end_of_prologue_found; | |
312 | break; | |
313 | case PIA_NOTE_PROLOGUE_END: | |
314 | if (!prologue_end) | |
315 | prologue_end = ip; | |
316 | break; | |
317 | case PIA_SKIP: | |
318 | default: | |
319 | /* Do nothing */ | |
320 | break; | |
c906108c SS |
321 | } |
322 | ||
323 | ip = next_ip; | |
324 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn); | |
325 | } | |
326 | ||
327 | end_of_prologue_found: | |
328 | ||
c5aa993b JM |
329 | if (prologue_end) |
330 | ip = prologue_end; | |
c906108c SS |
331 | |
332 | /* We're done with the prologue. If we don't care about the stack | |
333 | frame itself, just return. (Note that fsr->regs has been trashed, | |
334 | but the one caller who calls with fi==0 passes a dummy there.) */ | |
335 | ||
336 | if (fi == 0) | |
337 | return ip; | |
338 | ||
339 | /* | |
340 | OK, now we have: | |
341 | ||
c5aa993b JM |
342 | sp_offset original (before any alloca calls) displacement of SP |
343 | (will be negative). | |
c906108c | 344 | |
c5aa993b JM |
345 | fp_offset displacement from original SP to the FP for this frame |
346 | or -1. | |
c906108c | 347 | |
c5aa993b JM |
348 | fsr->regs[0..31] displacement from original SP to the stack |
349 | location where reg[0..31] is stored. | |
c906108c | 350 | |
c5aa993b | 351 | must_adjust[0..31] set if corresponding offset was set. |
c906108c SS |
352 | |
353 | If alloca has been called between the function prologue and the current | |
354 | IP, then the current SP (frame_sp) will not be the original SP as set by | |
355 | the function prologue. If the current SP is not the original SP, then the | |
356 | compiler will have allocated an FP for this frame, fp_offset will be set, | |
357 | and we can use it to calculate the original SP. | |
358 | ||
359 | Then, we figure out where the arguments and locals are, and relocate the | |
360 | offsets in fsr->regs to absolute addresses. */ | |
361 | ||
c5aa993b JM |
362 | if (fp_offset != -1) |
363 | { | |
364 | /* We have a frame pointer, so get it, and base our calc's on it. */ | |
365 | frame_fp = (CORE_ADDR) read_next_frame_reg (fi->next, ACTUAL_FP_REGNUM); | |
366 | frame_sp = frame_fp - fp_offset; | |
367 | } | |
368 | else | |
369 | { | |
370 | /* We have no frame pointer, therefore frame_sp is still the same value | |
371 | as set by prologue. But where is the frame itself? */ | |
372 | if (must_adjust[SRP_REGNUM]) | |
373 | { | |
374 | /* Function header saved SRP (r1), the return address. Frame starts | |
375 | 4 bytes down from where it was saved. */ | |
376 | frame_fp = frame_sp + fsr->regs[SRP_REGNUM] - 4; | |
377 | fi->locals_pointer = frame_fp; | |
378 | } | |
379 | else | |
380 | { | |
381 | /* Function header didn't save SRP (r1), so we are in a leaf fn or | |
382 | are otherwise confused. */ | |
383 | frame_fp = -1; | |
384 | } | |
c906108c | 385 | } |
c906108c SS |
386 | |
387 | /* The locals are relative to the FP (whether it exists as an allocated | |
388 | register, or just as an assumed offset from the SP) */ | |
389 | fi->locals_pointer = frame_fp; | |
390 | ||
391 | /* The arguments are just above the SP as it was before we adjusted it | |
392 | on entry. */ | |
393 | fi->args_pointer = frame_sp - sp_offset; | |
394 | ||
395 | /* Now that we know the SP value used by the prologue, we know where | |
396 | it saved all the registers. */ | |
397 | for (src = 0; src < 32; src++) | |
398 | if (must_adjust[src]) | |
399 | fsr->regs[src] += frame_sp; | |
c5aa993b | 400 | |
c906108c SS |
401 | /* The saved value of the SP is always known. */ |
402 | /* (we hope...) */ | |
c5aa993b JM |
403 | if (fsr->regs[SP_REGNUM] != 0 |
404 | && fsr->regs[SP_REGNUM] != frame_sp - sp_offset) | |
971ff545 | 405 | fprintf_unfiltered (gdb_stderr, "Bad saved SP value %lx != %lx, offset %x!\n", |
c5aa993b JM |
406 | fsr->regs[SP_REGNUM], |
407 | frame_sp - sp_offset, sp_offset); | |
c906108c SS |
408 | |
409 | fsr->regs[SP_REGNUM] = frame_sp - sp_offset; | |
410 | ||
411 | return (ip); | |
412 | } | |
413 | ||
414 | /* Given an ip value corresponding to the start of a function, | |
415 | return the ip of the first instruction after the function | |
416 | prologue. */ | |
417 | ||
418 | CORE_ADDR | |
afd64b4e | 419 | m88k_skip_prologue (CORE_ADDR ip) |
c906108c SS |
420 | { |
421 | struct frame_saved_regs saved_regs_dummy; | |
422 | struct symtab_and_line sal; | |
423 | CORE_ADDR limit; | |
424 | ||
425 | sal = find_pc_line (ip, 0); | |
426 | limit = (sal.end) ? sal.end : 0xffffffff; | |
427 | ||
428 | return (examine_prologue (ip, limit, (CORE_ADDR) 0, &saved_regs_dummy, | |
c5aa993b | 429 | (struct frame_info *) 0)); |
c906108c SS |
430 | } |
431 | ||
432 | /* Put here the code to store, into a struct frame_saved_regs, | |
433 | the addresses of the saved registers of frame described by FRAME_INFO. | |
434 | This includes special registers such as pc and fp saved in special | |
435 | ways in the stack frame. sp is even more special: | |
436 | the address we return for it IS the sp for the next frame. | |
437 | ||
438 | We cache the result of doing this in the frame_obstack, since it is | |
439 | fairly expensive. */ | |
440 | ||
441 | void | |
fba45db2 | 442 | frame_find_saved_regs (struct frame_info *fi, struct frame_saved_regs *fsr) |
c906108c SS |
443 | { |
444 | register struct frame_saved_regs *cache_fsr; | |
445 | CORE_ADDR ip; | |
446 | struct symtab_and_line sal; | |
447 | CORE_ADDR limit; | |
448 | ||
449 | if (!fi->fsr) | |
450 | { | |
451 | cache_fsr = (struct frame_saved_regs *) | |
452 | frame_obstack_alloc (sizeof (struct frame_saved_regs)); | |
453 | memset (cache_fsr, '\0', sizeof (struct frame_saved_regs)); | |
454 | fi->fsr = cache_fsr; | |
455 | ||
456 | /* Find the start and end of the function prologue. If the PC | |
c5aa993b JM |
457 | is in the function prologue, we only consider the part that |
458 | has executed already. In the case where the PC is not in | |
459 | the function prologue, we set limit to two instructions beyond | |
460 | where the prologue ends in case if any of the prologue instructions | |
461 | were moved into a delay slot of a branch instruction. */ | |
462 | ||
c906108c SS |
463 | ip = get_pc_function_start (fi->pc); |
464 | sal = find_pc_line (ip, 0); | |
c5aa993b JM |
465 | limit = (sal.end && sal.end < fi->pc) ? sal.end + 2 * BYTES_PER_88K_INSN |
466 | : fi->pc; | |
c906108c SS |
467 | |
468 | /* This will fill in fields in *fi as well as in cache_fsr. */ | |
469 | #ifdef SIGTRAMP_FRAME_FIXUP | |
470 | if (fi->signal_handler_caller) | |
c5aa993b | 471 | SIGTRAMP_FRAME_FIXUP (fi->frame); |
c906108c SS |
472 | #endif |
473 | examine_prologue (ip, limit, fi->frame, cache_fsr, fi); | |
474 | #ifdef SIGTRAMP_SP_FIXUP | |
475 | if (fi->signal_handler_caller && fi->fsr->regs[SP_REGNUM]) | |
c5aa993b | 476 | SIGTRAMP_SP_FIXUP (fi->fsr->regs[SP_REGNUM]); |
c906108c SS |
477 | #endif |
478 | } | |
479 | ||
480 | if (fsr) | |
481 | *fsr = *fi->fsr; | |
482 | } | |
483 | ||
484 | /* Return the address of the locals block for the frame | |
485 | described by FI. Returns 0 if the address is unknown. | |
486 | NOTE! Frame locals are referred to by negative offsets from the | |
487 | argument pointer, so this is the same as frame_args_address(). */ | |
488 | ||
489 | CORE_ADDR | |
fba45db2 | 490 | frame_locals_address (struct frame_info *fi) |
c906108c SS |
491 | { |
492 | struct frame_saved_regs fsr; | |
493 | ||
c5aa993b | 494 | if (fi->args_pointer) /* Cached value is likely there. */ |
c906108c SS |
495 | return fi->args_pointer; |
496 | ||
497 | /* Nope, generate it. */ | |
498 | ||
499 | get_frame_saved_regs (fi, &fsr); | |
500 | ||
501 | return fi->args_pointer; | |
502 | } | |
503 | ||
504 | /* Return the address of the argument block for the frame | |
505 | described by FI. Returns 0 if the address is unknown. */ | |
506 | ||
507 | CORE_ADDR | |
fba45db2 | 508 | frame_args_address (struct frame_info *fi) |
c906108c SS |
509 | { |
510 | struct frame_saved_regs fsr; | |
511 | ||
512 | if (fi->args_pointer) /* Cached value is likely there. */ | |
513 | return fi->args_pointer; | |
514 | ||
515 | /* Nope, generate it. */ | |
516 | ||
517 | get_frame_saved_regs (fi, &fsr); | |
518 | ||
519 | return fi->args_pointer; | |
520 | } | |
521 | ||
522 | /* Return the saved PC from this frame. | |
523 | ||
524 | If the frame has a memory copy of SRP_REGNUM, use that. If not, | |
525 | just use the register SRP_REGNUM itself. */ | |
526 | ||
527 | CORE_ADDR | |
fba45db2 | 528 | frame_saved_pc (struct frame_info *frame) |
c906108c | 529 | { |
c5aa993b | 530 | return read_next_frame_reg (frame, SRP_REGNUM); |
c906108c SS |
531 | } |
532 | ||
533 | ||
534 | #define DUMMY_FRAME_SIZE 192 | |
535 | ||
536 | static void | |
fba45db2 | 537 | write_word (CORE_ADDR sp, ULONGEST word) |
c906108c SS |
538 | { |
539 | register int len = REGISTER_SIZE; | |
540 | char buffer[MAX_REGISTER_RAW_SIZE]; | |
541 | ||
542 | store_unsigned_integer (buffer, len, word); | |
543 | write_memory (sp, buffer, len); | |
544 | } | |
545 | ||
546 | void | |
fba45db2 | 547 | m88k_push_dummy_frame (void) |
c906108c SS |
548 | { |
549 | register CORE_ADDR sp = read_register (SP_REGNUM); | |
550 | register int rn; | |
551 | int offset; | |
552 | ||
553 | sp -= DUMMY_FRAME_SIZE; /* allocate a bunch of space */ | |
554 | ||
c5aa993b JM |
555 | for (rn = 0, offset = 0; rn <= SP_REGNUM; rn++, offset += 4) |
556 | write_word (sp + offset, read_register (rn)); | |
557 | ||
558 | write_word (sp + offset, read_register (SXIP_REGNUM)); | |
c906108c SS |
559 | offset += 4; |
560 | ||
c5aa993b | 561 | write_word (sp + offset, read_register (SNIP_REGNUM)); |
c906108c SS |
562 | offset += 4; |
563 | ||
c5aa993b | 564 | write_word (sp + offset, read_register (SFIP_REGNUM)); |
c906108c SS |
565 | offset += 4; |
566 | ||
c5aa993b | 567 | write_word (sp + offset, read_register (PSR_REGNUM)); |
c906108c SS |
568 | offset += 4; |
569 | ||
c5aa993b | 570 | write_word (sp + offset, read_register (FPSR_REGNUM)); |
c906108c SS |
571 | offset += 4; |
572 | ||
c5aa993b | 573 | write_word (sp + offset, read_register (FPCR_REGNUM)); |
c906108c SS |
574 | offset += 4; |
575 | ||
576 | write_register (SP_REGNUM, sp); | |
577 | write_register (ACTUAL_FP_REGNUM, sp); | |
578 | } | |
579 | ||
580 | void | |
fba45db2 | 581 | pop_frame (void) |
c906108c SS |
582 | { |
583 | register struct frame_info *frame = get_current_frame (); | |
c906108c SS |
584 | register int regnum; |
585 | struct frame_saved_regs fsr; | |
586 | ||
c906108c SS |
587 | get_frame_saved_regs (frame, &fsr); |
588 | ||
971ff545 | 589 | if (PC_IN_CALL_DUMMY (read_pc (), read_register (SP_REGNUM), frame->frame)) |
c906108c SS |
590 | { |
591 | /* FIXME: I think get_frame_saved_regs should be handling this so | |
c5aa993b JM |
592 | that we can deal with the saved registers properly (e.g. frame |
593 | 1 is a call dummy, the user types "frame 2" and then "print $ps"). */ | |
c906108c SS |
594 | register CORE_ADDR sp = read_register (ACTUAL_FP_REGNUM); |
595 | int offset; | |
596 | ||
c5aa993b JM |
597 | for (regnum = 0, offset = 0; regnum <= SP_REGNUM; regnum++, offset += 4) |
598 | (void) write_register (regnum, read_memory_integer (sp + offset, 4)); | |
599 | ||
600 | write_register (SXIP_REGNUM, read_memory_integer (sp + offset, 4)); | |
c906108c SS |
601 | offset += 4; |
602 | ||
c5aa993b | 603 | write_register (SNIP_REGNUM, read_memory_integer (sp + offset, 4)); |
c906108c SS |
604 | offset += 4; |
605 | ||
c5aa993b | 606 | write_register (SFIP_REGNUM, read_memory_integer (sp + offset, 4)); |
c906108c SS |
607 | offset += 4; |
608 | ||
c5aa993b | 609 | write_register (PSR_REGNUM, read_memory_integer (sp + offset, 4)); |
c906108c SS |
610 | offset += 4; |
611 | ||
c5aa993b | 612 | write_register (FPSR_REGNUM, read_memory_integer (sp + offset, 4)); |
c906108c SS |
613 | offset += 4; |
614 | ||
c5aa993b | 615 | write_register (FPCR_REGNUM, read_memory_integer (sp + offset, 4)); |
c906108c SS |
616 | offset += 4; |
617 | ||
618 | } | |
c5aa993b | 619 | else |
c906108c | 620 | { |
c5aa993b JM |
621 | for (regnum = FP_REGNUM; regnum > 0; regnum--) |
622 | if (fsr.regs[regnum]) | |
623 | write_register (regnum, | |
624 | read_memory_integer (fsr.regs[regnum], 4)); | |
c906108c SS |
625 | write_pc (frame_saved_pc (frame)); |
626 | } | |
627 | reinit_frame_cache (); | |
628 | } | |
629 | ||
630 | void | |
fba45db2 | 631 | _initialize_m88k_tdep (void) |
c906108c SS |
632 | { |
633 | tm_print_insn = print_insn_m88k; | |
634 | } |