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1 | /* Target-dependent code for the Toshiba MeP for GDB, the GNU debugger. |
2 | ||
3 | Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007 | |
4 | Free Software Foundation, Inc. | |
5 | ||
6 | Contributed by Red Hat, Inc. | |
7 | ||
8 | This file is part of GDB. | |
9 | ||
10 | This program is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2 of the License, or | |
13 | (at your option) any later version. | |
14 | ||
15 | This program is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with this program; if not, write to the Free Software | |
22 | Foundation, Inc., 59 Temple Place - Suite 330, | |
23 | Boston, MA 02111-1307, USA. */ | |
24 | ||
25 | #include "defs.h" | |
26 | #include "frame.h" | |
27 | #include "frame-unwind.h" | |
28 | #include "frame-base.h" | |
29 | #include "symtab.h" | |
30 | #include "gdbtypes.h" | |
31 | #include "gdbcmd.h" | |
32 | #include "gdbcore.h" | |
33 | #include "gdb_string.h" | |
34 | #include "value.h" | |
35 | #include "inferior.h" | |
36 | #include "dis-asm.h" | |
37 | #include "symfile.h" | |
38 | #include "objfiles.h" | |
39 | #include "language.h" | |
40 | #include "arch-utils.h" | |
41 | #include "regcache.h" | |
42 | #include "remote.h" | |
43 | #include "floatformat.h" | |
44 | #include "sim-regno.h" | |
45 | #include "disasm.h" | |
46 | #include "trad-frame.h" | |
47 | #include "reggroups.h" | |
48 | #include "elf-bfd.h" | |
49 | #include "elf/mep.h" | |
50 | #include "prologue-value.h" | |
51 | #include "opcode/cgen-bitset.h" | |
52 | #include "infcall.h" | |
53 | ||
54 | #include "gdb_assert.h" | |
55 | ||
56 | /* Get the user's customized MeP coprocessor register names from | |
57 | libopcodes. */ | |
58 | #include "opcodes/mep-desc.h" | |
59 | #include "opcodes/mep-opc.h" | |
60 | ||
61 | \f | |
62 | /* The gdbarch_tdep structure. */ | |
63 | ||
64 | /* A quick recap for GDB hackers not familiar with the whole Toshiba | |
65 | Media Processor story: | |
66 | ||
67 | The MeP media engine is a configureable processor: users can design | |
68 | their own coprocessors, implement custom instructions, adjust cache | |
69 | sizes, select optional standard facilities like add-and-saturate | |
70 | instructions, and so on. Then, they can build custom versions of | |
71 | the GNU toolchain to support their customized chips. The | |
72 | MeP-Integrator program (see utils/mep) takes a GNU toolchain source | |
73 | tree, and a config file pointing to various files provided by the | |
74 | user describing their customizations, and edits the source tree to | |
75 | produce a compiler that can generate their custom instructions, an | |
76 | assembler that can assemble them and recognize their custom | |
77 | register names, and so on. | |
78 | ||
79 | Furthermore, the user can actually specify several of these custom | |
80 | configurations, called 'me_modules', and get a toolchain which can | |
81 | produce code for any of them, given a compiler/assembler switch; | |
82 | you say something like 'gcc -mconfig=mm_max' to generate code for | |
83 | the me_module named 'mm_max'. | |
84 | ||
85 | GDB, in particular, needs to: | |
86 | ||
87 | - use the coprocessor control register names provided by the user | |
88 | in their hardware description, in expressions, 'info register' | |
89 | output, and disassembly, | |
90 | ||
91 | - know the number, names, and types of the coprocessor's | |
92 | general-purpose registers, adjust the 'info all-registers' output | |
93 | accordingly, and print error messages if the user refers to one | |
94 | that doesn't exist | |
95 | ||
96 | - allow access to the control bus space only when the configuration | |
97 | actually has a control bus, and recognize which regions of the | |
98 | control bus space are actually populated, | |
99 | ||
100 | - disassemble using the user's provided mnemonics for their custom | |
101 | instructions, and | |
102 | ||
103 | - recognize whether the $hi and $lo registers are present, and | |
104 | allow access to them only when they are actually there. | |
105 | ||
106 | There are three sources of information about what sort of me_module | |
107 | we're actually dealing with: | |
108 | ||
109 | - A MeP executable file indicates which me_module it was compiled | |
110 | for, and libopcodes has tables describing each module. So, given | |
111 | an executable file, we can find out about the processor it was | |
112 | compiled for. | |
113 | ||
114 | - There are SID command-line options to select a particular | |
115 | me_module, overriding the one specified in the ELF file. SID | |
116 | provides GDB with a fake read-only register, 'module', which | |
117 | indicates which me_module GDB is communicating with an instance | |
118 | of. | |
119 | ||
120 | - There are SID command-line options to enable or disable certain | |
121 | optional processor features, overriding the defaults for the | |
122 | selected me_module. The MeP $OPT register indicates which | |
123 | options are present on the current processor. */ | |
124 | ||
125 | ||
126 | struct gdbarch_tdep | |
127 | { | |
128 | /* A CGEN cpu descriptor for this BFD architecture and machine. | |
129 | ||
130 | Note: this is *not* customized for any particular me_module; the | |
131 | MeP libopcodes machinery actually puts off module-specific | |
132 | customization until the last minute. So this contains | |
133 | information about all supported me_modules. */ | |
134 | CGEN_CPU_DESC cpu_desc; | |
135 | ||
136 | /* The me_module index from the ELF file we used to select this | |
137 | architecture, or CONFIG_NONE if there was none. | |
138 | ||
139 | Note that we should prefer to use the me_module number available | |
140 | via the 'module' register, whenever we're actually talking to a | |
141 | real target. | |
142 | ||
143 | In the absence of live information, we'd like to get the | |
144 | me_module number from the ELF file. But which ELF file: the | |
145 | executable file, the core file, ... ? The answer is, "the last | |
146 | ELF file we used to set the current architecture". Thus, we | |
147 | create a separate instance of the gdbarch structure for each | |
148 | me_module value mep_gdbarch_init sees, and store the me_module | |
149 | value from the ELF file here. */ | |
150 | CONFIG_ATTR me_module; | |
151 | }; | |
152 | ||
153 | ||
154 | \f | |
155 | /* Getting me_module information from the CGEN tables. */ | |
156 | ||
157 | ||
158 | /* Find an entry in the DESC's hardware table whose name begins with | |
159 | PREFIX, and whose ISA mask intersects COPRO_ISA_MASK, but does not | |
160 | intersect with GENERIC_ISA_MASK. If there is no matching entry, | |
161 | return zero. */ | |
162 | static const CGEN_HW_ENTRY * | |
163 | find_hw_entry_by_prefix_and_isa (CGEN_CPU_DESC desc, | |
164 | const char *prefix, | |
165 | CGEN_BITSET *copro_isa_mask, | |
166 | CGEN_BITSET *generic_isa_mask) | |
167 | { | |
168 | int prefix_len = strlen (prefix); | |
169 | int i; | |
170 | ||
171 | for (i = 0; i < desc->hw_table.num_entries; i++) | |
172 | { | |
173 | const CGEN_HW_ENTRY *hw = desc->hw_table.entries[i]; | |
174 | if (strncmp (prefix, hw->name, prefix_len) == 0) | |
175 | { | |
176 | CGEN_BITSET *hw_isa_mask | |
177 | = ((CGEN_BITSET *) | |
178 | &CGEN_ATTR_CGEN_HW_ISA_VALUE (CGEN_HW_ATTRS (hw))); | |
179 | ||
180 | if (cgen_bitset_intersect_p (hw_isa_mask, copro_isa_mask) | |
181 | && ! cgen_bitset_intersect_p (hw_isa_mask, generic_isa_mask)) | |
182 | return hw; | |
183 | } | |
184 | } | |
185 | ||
186 | return 0; | |
187 | } | |
188 | ||
189 | ||
190 | /* Find an entry in DESC's hardware table whose type is TYPE. Return | |
191 | zero if there is none. */ | |
192 | static const CGEN_HW_ENTRY * | |
193 | find_hw_entry_by_type (CGEN_CPU_DESC desc, CGEN_HW_TYPE type) | |
194 | { | |
195 | int i; | |
196 | ||
197 | for (i = 0; i < desc->hw_table.num_entries; i++) | |
198 | { | |
199 | const CGEN_HW_ENTRY *hw = desc->hw_table.entries[i]; | |
200 | ||
201 | if (hw->type == type) | |
202 | return hw; | |
203 | } | |
204 | ||
205 | return 0; | |
206 | } | |
207 | ||
208 | ||
209 | /* Return the CGEN hardware table entry for the coprocessor register | |
210 | set for ME_MODULE, whose name prefix is PREFIX. If ME_MODULE has | |
211 | no such register set, return zero. If ME_MODULE is the generic | |
212 | me_module CONFIG_NONE, return the table entry for the register set | |
213 | whose hardware type is GENERIC_TYPE. */ | |
214 | static const CGEN_HW_ENTRY * | |
215 | me_module_register_set (CONFIG_ATTR me_module, | |
216 | const char *prefix, | |
217 | CGEN_HW_TYPE generic_type) | |
218 | { | |
219 | /* This is kind of tricky, because the hardware table is constructed | |
220 | in a way that isn't very helpful. Perhaps we can fix that, but | |
221 | here's how it works at the moment: | |
222 | ||
223 | The configuration map, `mep_config_map', is indexed by me_module | |
224 | number, and indicates which coprocessor and core ISAs that | |
225 | me_module supports. The 'core_isa' mask includes all the core | |
226 | ISAs, and the 'cop_isa' mask includes all the coprocessor ISAs. | |
227 | The entry for the generic me_module, CONFIG_NONE, has an empty | |
228 | 'cop_isa', and its 'core_isa' selects only the standard MeP | |
229 | instruction set. | |
230 | ||
231 | The CGEN CPU descriptor's hardware table, desc->hw_table, has | |
232 | entries for all the register sets, for all me_modules. Each | |
233 | entry has a mask indicating which ISAs use that register set. | |
234 | So, if an me_module supports some coprocessor ISA, we can find | |
235 | applicable register sets by scanning the hardware table for | |
236 | register sets whose masks include (at least some of) those ISAs. | |
237 | ||
238 | Each hardware table entry also has a name, whose prefix says | |
239 | whether it's a general-purpose ("h-cr") or control ("h-ccr") | |
240 | coprocessor register set. It might be nicer to have an attribute | |
241 | indicating what sort of register set it was, that we could use | |
242 | instead of pattern-matching on the name. | |
243 | ||
244 | When there is no hardware table entry whose mask includes a | |
245 | particular coprocessor ISA and whose name starts with a given | |
246 | prefix, then that means that that coprocessor doesn't have any | |
247 | registers of that type. In such cases, this function must return | |
248 | a null pointer. | |
249 | ||
250 | Coprocessor register sets' masks may or may not include the core | |
251 | ISA for the me_module they belong to. Those generated by a2cgen | |
252 | do, but the sample me_module included in the unconfigured tree, | |
253 | 'ccfx', does not. | |
254 | ||
255 | There are generic coprocessor register sets, intended only for | |
256 | use with the generic me_module. Unfortunately, their masks | |
257 | include *all* ISAs --- even those for coprocessors that don't | |
258 | have such register sets. This makes detecting the case where a | |
259 | coprocessor lacks a particular register set more complicated. | |
260 | ||
261 | So, here's the approach we take: | |
262 | ||
263 | - For CONFIG_NONE, we return the generic coprocessor register set. | |
264 | ||
265 | - For any other me_module, we search for a register set whose | |
266 | mask contains any of the me_module's coprocessor ISAs, | |
267 | specifically excluding the generic coprocessor register sets. */ | |
268 | ||
269 | CGEN_CPU_DESC desc = gdbarch_tdep (current_gdbarch)->cpu_desc; | |
270 | const CGEN_HW_ENTRY *hw; | |
271 | ||
272 | if (me_module == CONFIG_NONE) | |
273 | hw = find_hw_entry_by_type (desc, generic_type); | |
274 | else | |
275 | { | |
276 | CGEN_BITSET *cop = &mep_config_map[me_module].cop_isa; | |
277 | CGEN_BITSET *core = &mep_config_map[me_module].core_isa; | |
278 | CGEN_BITSET *generic = &mep_config_map[CONFIG_NONE].core_isa; | |
279 | CGEN_BITSET *cop_and_core; | |
280 | ||
281 | /* The coprocessor ISAs include the ISA for the specific core which | |
282 | has that coprocessor. */ | |
283 | cop_and_core = cgen_bitset_copy (cop); | |
284 | cgen_bitset_union (cop, core, cop_and_core); | |
285 | hw = find_hw_entry_by_prefix_and_isa (desc, prefix, cop_and_core, generic); | |
286 | } | |
287 | ||
288 | return hw; | |
289 | } | |
290 | ||
291 | ||
292 | /* Given a hardware table entry HW representing a register set, return | |
293 | a pointer to the keyword table with all the register names. If HW | |
294 | is NULL, return NULL, to propage the "no such register set" info | |
295 | along. */ | |
296 | static CGEN_KEYWORD * | |
297 | register_set_keyword_table (const CGEN_HW_ENTRY *hw) | |
298 | { | |
299 | if (! hw) | |
300 | return NULL; | |
301 | ||
302 | /* Check that HW is actually a keyword table. */ | |
303 | gdb_assert (hw->asm_type == CGEN_ASM_KEYWORD); | |
304 | ||
305 | /* The 'asm_data' field of a register set's hardware table entry | |
306 | refers to a keyword table. */ | |
307 | return (CGEN_KEYWORD *) hw->asm_data; | |
308 | } | |
309 | ||
310 | ||
311 | /* Given a keyword table KEYWORD and a register number REGNUM, return | |
312 | the name of the register, or "" if KEYWORD contains no register | |
313 | whose number is REGNUM. */ | |
314 | static char * | |
315 | register_name_from_keyword (CGEN_KEYWORD *keyword_table, int regnum) | |
316 | { | |
317 | const CGEN_KEYWORD_ENTRY *entry | |
318 | = cgen_keyword_lookup_value (keyword_table, regnum); | |
319 | ||
320 | if (entry) | |
321 | { | |
322 | char *name = entry->name; | |
323 | ||
324 | /* The CGEN keyword entries for register names include the | |
325 | leading $, which appears in MeP assembly as well as in GDB. | |
326 | But we don't want to return that; GDB core code adds that | |
327 | itself. */ | |
328 | if (name[0] == '$') | |
329 | name++; | |
330 | ||
331 | return name; | |
332 | } | |
333 | else | |
334 | return ""; | |
335 | } | |
336 | ||
337 | ||
338 | /* Masks for option bits in the OPT special-purpose register. */ | |
339 | enum { | |
340 | MEP_OPT_DIV = 1 << 25, /* 32-bit divide instruction option */ | |
341 | MEP_OPT_MUL = 1 << 24, /* 32-bit multiply instruction option */ | |
342 | MEP_OPT_BIT = 1 << 23, /* bit manipulation instruction option */ | |
343 | MEP_OPT_SAT = 1 << 22, /* saturation instruction option */ | |
344 | MEP_OPT_CLP = 1 << 21, /* clip instruction option */ | |
345 | MEP_OPT_MIN = 1 << 20, /* min/max instruction option */ | |
346 | MEP_OPT_AVE = 1 << 19, /* average instruction option */ | |
347 | MEP_OPT_ABS = 1 << 18, /* absolute difference instruction option */ | |
348 | MEP_OPT_LDZ = 1 << 16, /* leading zero instruction option */ | |
349 | MEP_OPT_VL64 = 1 << 6, /* 64-bit VLIW operation mode option */ | |
350 | MEP_OPT_VL32 = 1 << 5, /* 32-bit VLIW operation mode option */ | |
351 | MEP_OPT_COP = 1 << 4, /* coprocessor option */ | |
352 | MEP_OPT_DSP = 1 << 2, /* DSP option */ | |
353 | MEP_OPT_UCI = 1 << 1, /* UCI option */ | |
354 | MEP_OPT_DBG = 1 << 0, /* DBG function option */ | |
355 | }; | |
356 | ||
357 | ||
358 | /* Given the option_mask value for a particular entry in | |
359 | mep_config_map, produce the value the processor's OPT register | |
360 | would use to represent the same set of options. */ | |
361 | static unsigned int | |
362 | opt_from_option_mask (unsigned int option_mask) | |
363 | { | |
364 | /* A table mapping OPT register bits onto CGEN config map option | |
365 | bits. */ | |
366 | struct { | |
367 | unsigned int opt_bit, option_mask_bit; | |
368 | } bits[] = { | |
369 | { MEP_OPT_DIV, 1 << CGEN_INSN_OPTIONAL_DIV_INSN }, | |
370 | { MEP_OPT_MUL, 1 << CGEN_INSN_OPTIONAL_MUL_INSN }, | |
371 | { MEP_OPT_DIV, 1 << CGEN_INSN_OPTIONAL_DIV_INSN }, | |
372 | { MEP_OPT_DBG, 1 << CGEN_INSN_OPTIONAL_DEBUG_INSN }, | |
373 | { MEP_OPT_LDZ, 1 << CGEN_INSN_OPTIONAL_LDZ_INSN }, | |
374 | { MEP_OPT_ABS, 1 << CGEN_INSN_OPTIONAL_ABS_INSN }, | |
375 | { MEP_OPT_AVE, 1 << CGEN_INSN_OPTIONAL_AVE_INSN }, | |
376 | { MEP_OPT_MIN, 1 << CGEN_INSN_OPTIONAL_MINMAX_INSN }, | |
377 | { MEP_OPT_CLP, 1 << CGEN_INSN_OPTIONAL_CLIP_INSN }, | |
378 | { MEP_OPT_SAT, 1 << CGEN_INSN_OPTIONAL_SAT_INSN }, | |
379 | { MEP_OPT_UCI, 1 << CGEN_INSN_OPTIONAL_UCI_INSN }, | |
380 | { MEP_OPT_DSP, 1 << CGEN_INSN_OPTIONAL_DSP_INSN }, | |
381 | { MEP_OPT_COP, 1 << CGEN_INSN_OPTIONAL_CP_INSN }, | |
382 | }; | |
383 | ||
384 | int i; | |
385 | unsigned int opt = 0; | |
386 | ||
387 | for (i = 0; i < (sizeof (bits) / sizeof (bits[0])); i++) | |
388 | if (option_mask & bits[i].option_mask_bit) | |
389 | opt |= bits[i].opt_bit; | |
390 | ||
391 | return opt; | |
392 | } | |
393 | ||
394 | ||
395 | /* Return the value the $OPT register would use to represent the set | |
396 | of options for ME_MODULE. */ | |
397 | static unsigned int | |
398 | me_module_opt (CONFIG_ATTR me_module) | |
399 | { | |
400 | return opt_from_option_mask (mep_config_map[me_module].option_mask); | |
401 | } | |
402 | ||
403 | ||
404 | /* Return the width of ME_MODULE's coprocessor data bus, in bits. | |
405 | This is either 32 or 64. */ | |
406 | static int | |
407 | me_module_cop_data_bus_width (CONFIG_ATTR me_module) | |
408 | { | |
409 | if (mep_config_map[me_module].option_mask | |
410 | & (1 << CGEN_INSN_OPTIONAL_CP64_INSN)) | |
411 | return 64; | |
412 | else | |
413 | return 32; | |
414 | } | |
415 | ||
416 | ||
417 | /* Return true if ME_MODULE is big-endian, false otherwise. */ | |
418 | static int | |
419 | me_module_big_endian (CONFIG_ATTR me_module) | |
420 | { | |
421 | return mep_config_map[me_module].big_endian; | |
422 | } | |
423 | ||
424 | ||
425 | /* Return the name of ME_MODULE, or NULL if it has no name. */ | |
426 | static const char * | |
427 | me_module_name (CONFIG_ATTR me_module) | |
428 | { | |
429 | /* The default me_module has "" as its name, but it's easier for our | |
430 | callers to test for NULL. */ | |
431 | if (! mep_config_map[me_module].name | |
432 | || mep_config_map[me_module].name[0] == '\0') | |
433 | return NULL; | |
434 | else | |
435 | return mep_config_map[me_module].name; | |
436 | } | |
437 | \f | |
438 | /* Register set. */ | |
439 | ||
440 | ||
441 | /* The MeP spec defines the following registers: | |
442 | 16 general purpose registers (r0-r15) | |
443 | 32 control/special registers (csr0-csr31) | |
444 | 32 coprocessor general-purpose registers (c0 -- c31) | |
445 | 64 coprocessor control registers (ccr0 -- ccr63) | |
446 | ||
447 | For the raw registers, we assign numbers here explicitly, instead | |
448 | of letting the enum assign them for us; the numbers are a matter of | |
449 | external protocol, and shouldn't shift around as things are edited. | |
450 | ||
451 | We access the control/special registers via pseudoregisters, to | |
452 | enforce read-only portions that some registers have. | |
453 | ||
454 | We access the coprocessor general purpose and control registers via | |
455 | pseudoregisters, to make sure they appear in the proper order in | |
456 | the 'info all-registers' command (which uses the register number | |
457 | ordering), and also to allow them to be renamed and resized | |
458 | depending on the me_module in use. | |
459 | ||
460 | The MeP allows coprocessor general-purpose registers to be either | |
461 | 32 or 64 bits long, depending on the configuration. Since we don't | |
462 | want the format of the 'g' packet to vary from one core to another, | |
463 | the raw coprocessor GPRs are always 64 bits. GDB doesn't allow the | |
464 | types of registers to change (see the implementation of | |
465 | register_type), so we have four banks of pseudoregisters for the | |
466 | coprocessor gprs --- 32-bit vs. 64-bit, and integer | |
467 | vs. floating-point --- and we show or hide them depending on the | |
468 | configuration. */ | |
469 | enum | |
470 | { | |
471 | MEP_FIRST_RAW_REGNUM = 0, | |
472 | ||
473 | MEP_FIRST_GPR_REGNUM = 0, | |
474 | MEP_R0_REGNUM = 0, | |
475 | MEP_R1_REGNUM = 1, | |
476 | MEP_R2_REGNUM = 2, | |
477 | MEP_R3_REGNUM = 3, | |
478 | MEP_R4_REGNUM = 4, | |
479 | MEP_R5_REGNUM = 5, | |
480 | MEP_R6_REGNUM = 6, | |
481 | MEP_R7_REGNUM = 7, | |
482 | MEP_R8_REGNUM = 8, | |
483 | MEP_R9_REGNUM = 9, | |
484 | MEP_R10_REGNUM = 10, | |
485 | MEP_R11_REGNUM = 11, | |
486 | MEP_R12_REGNUM = 12, | |
487 | MEP_FP_REGNUM = MEP_R8_REGNUM, | |
488 | MEP_R13_REGNUM = 13, | |
489 | MEP_TP_REGNUM = MEP_R13_REGNUM, /* (r13) Tiny data pointer */ | |
490 | MEP_R14_REGNUM = 14, | |
491 | MEP_GP_REGNUM = MEP_R14_REGNUM, /* (r14) Global pointer */ | |
492 | MEP_R15_REGNUM = 15, | |
493 | MEP_SP_REGNUM = MEP_R15_REGNUM, /* (r15) Stack pointer */ | |
494 | MEP_LAST_GPR_REGNUM = MEP_R15_REGNUM, | |
495 | ||
496 | /* The raw control registers. These are the values as received via | |
497 | the remote protocol, directly from the target; we only let user | |
498 | code touch the via the pseudoregisters, which enforce read-only | |
499 | bits. */ | |
500 | MEP_FIRST_RAW_CSR_REGNUM = 16, | |
501 | MEP_RAW_PC_REGNUM = 16, /* Program counter */ | |
502 | MEP_RAW_LP_REGNUM = 17, /* Link pointer */ | |
503 | MEP_RAW_SAR_REGNUM = 18, /* Raw shift amount */ | |
504 | MEP_RAW_CSR3_REGNUM = 19, /* csr3: reserved */ | |
505 | MEP_RAW_RPB_REGNUM = 20, /* Raw repeat begin address */ | |
506 | MEP_RAW_RPE_REGNUM = 21, /* Repeat end address */ | |
507 | MEP_RAW_RPC_REGNUM = 22, /* Repeat count */ | |
508 | MEP_RAW_HI_REGNUM = 23, /* Upper 32 bits of result of 64 bit mult/div */ | |
509 | MEP_RAW_LO_REGNUM = 24, /* Lower 32 bits of result of 64 bit mult/div */ | |
510 | MEP_RAW_CSR9_REGNUM = 25, /* csr3: reserved */ | |
511 | MEP_RAW_CSR10_REGNUM = 26, /* csr3: reserved */ | |
512 | MEP_RAW_CSR11_REGNUM = 27, /* csr3: reserved */ | |
513 | MEP_RAW_MB0_REGNUM = 28, /* Raw modulo begin address 0 */ | |
514 | MEP_RAW_ME0_REGNUM = 29, /* Raw modulo end address 0 */ | |
515 | MEP_RAW_MB1_REGNUM = 30, /* Raw modulo begin address 1 */ | |
516 | MEP_RAW_ME1_REGNUM = 31, /* Raw modulo end address 1 */ | |
517 | MEP_RAW_PSW_REGNUM = 32, /* Raw program status word */ | |
518 | MEP_RAW_ID_REGNUM = 33, /* Raw processor ID/revision */ | |
519 | MEP_RAW_TMP_REGNUM = 34, /* Temporary */ | |
520 | MEP_RAW_EPC_REGNUM = 35, /* Exception program counter */ | |
521 | MEP_RAW_EXC_REGNUM = 36, /* Raw exception cause */ | |
522 | MEP_RAW_CFG_REGNUM = 37, /* Raw processor configuration*/ | |
523 | MEP_RAW_CSR22_REGNUM = 38, /* csr3: reserved */ | |
524 | MEP_RAW_NPC_REGNUM = 39, /* Nonmaskable interrupt PC */ | |
525 | MEP_RAW_DBG_REGNUM = 40, /* Raw debug */ | |
526 | MEP_RAW_DEPC_REGNUM = 41, /* Debug exception PC */ | |
527 | MEP_RAW_OPT_REGNUM = 42, /* Raw options */ | |
528 | MEP_RAW_RCFG_REGNUM = 43, /* Raw local ram config */ | |
529 | MEP_RAW_CCFG_REGNUM = 44, /* Raw cache config */ | |
530 | MEP_RAW_CSR29_REGNUM = 45, /* csr3: reserved */ | |
531 | MEP_RAW_CSR30_REGNUM = 46, /* csr3: reserved */ | |
532 | MEP_RAW_CSR31_REGNUM = 47, /* csr3: reserved */ | |
533 | MEP_LAST_RAW_CSR_REGNUM = MEP_RAW_CSR31_REGNUM, | |
534 | ||
535 | /* The raw coprocessor general-purpose registers. These are all 64 | |
536 | bits wide. */ | |
537 | MEP_FIRST_RAW_CR_REGNUM = 48, | |
538 | MEP_LAST_RAW_CR_REGNUM = MEP_FIRST_RAW_CR_REGNUM + 31, | |
539 | ||
540 | MEP_FIRST_RAW_CCR_REGNUM = 80, | |
541 | MEP_LAST_RAW_CCR_REGNUM = MEP_FIRST_RAW_CCR_REGNUM + 63, | |
542 | ||
543 | /* The module number register. This is the index of the me_module | |
544 | of which the current target is an instance. (This is not a real | |
545 | MeP-specified register; it's provided by SID.) */ | |
546 | MEP_MODULE_REGNUM, | |
547 | ||
548 | MEP_LAST_RAW_REGNUM = MEP_MODULE_REGNUM, | |
549 | ||
550 | MEP_NUM_RAW_REGS = MEP_LAST_RAW_REGNUM + 1, | |
551 | ||
552 | /* Pseudoregisters. See mep_pseudo_register_read and | |
553 | mep_pseudo_register_write. */ | |
554 | MEP_FIRST_PSEUDO_REGNUM = MEP_NUM_RAW_REGS, | |
555 | ||
556 | /* We have a pseudoregister for every control/special register, to | |
557 | implement registers with read-only bits. */ | |
558 | MEP_FIRST_CSR_REGNUM = MEP_FIRST_PSEUDO_REGNUM, | |
559 | MEP_PC_REGNUM = MEP_FIRST_CSR_REGNUM, /* Program counter */ | |
560 | MEP_LP_REGNUM, /* Link pointer */ | |
561 | MEP_SAR_REGNUM, /* shift amount */ | |
562 | MEP_CSR3_REGNUM, /* csr3: reserved */ | |
563 | MEP_RPB_REGNUM, /* repeat begin address */ | |
564 | MEP_RPE_REGNUM, /* Repeat end address */ | |
565 | MEP_RPC_REGNUM, /* Repeat count */ | |
566 | MEP_HI_REGNUM, /* Upper 32 bits of the result of 64 bit mult/div */ | |
567 | MEP_LO_REGNUM, /* Lower 32 bits of the result of 64 bit mult/div */ | |
568 | MEP_CSR9_REGNUM, /* csr3: reserved */ | |
569 | MEP_CSR10_REGNUM, /* csr3: reserved */ | |
570 | MEP_CSR11_REGNUM, /* csr3: reserved */ | |
571 | MEP_MB0_REGNUM, /* modulo begin address 0 */ | |
572 | MEP_ME0_REGNUM, /* modulo end address 0 */ | |
573 | MEP_MB1_REGNUM, /* modulo begin address 1 */ | |
574 | MEP_ME1_REGNUM, /* modulo end address 1 */ | |
575 | MEP_PSW_REGNUM, /* program status word */ | |
576 | MEP_ID_REGNUM, /* processor ID/revision */ | |
577 | MEP_TMP_REGNUM, /* Temporary */ | |
578 | MEP_EPC_REGNUM, /* Exception program counter */ | |
579 | MEP_EXC_REGNUM, /* exception cause */ | |
580 | MEP_CFG_REGNUM, /* processor configuration*/ | |
581 | MEP_CSR22_REGNUM, /* csr3: reserved */ | |
582 | MEP_NPC_REGNUM, /* Nonmaskable interrupt PC */ | |
583 | MEP_DBG_REGNUM, /* debug */ | |
584 | MEP_DEPC_REGNUM, /* Debug exception PC */ | |
585 | MEP_OPT_REGNUM, /* options */ | |
586 | MEP_RCFG_REGNUM, /* local ram config */ | |
587 | MEP_CCFG_REGNUM, /* cache config */ | |
588 | MEP_CSR29_REGNUM, /* csr3: reserved */ | |
589 | MEP_CSR30_REGNUM, /* csr3: reserved */ | |
590 | MEP_CSR31_REGNUM, /* csr3: reserved */ | |
591 | MEP_LAST_CSR_REGNUM = MEP_CSR31_REGNUM, | |
592 | ||
593 | /* The 32-bit integer view of the coprocessor GPR's. */ | |
594 | MEP_FIRST_CR32_REGNUM, | |
595 | MEP_LAST_CR32_REGNUM = MEP_FIRST_CR32_REGNUM + 31, | |
596 | ||
597 | /* The 32-bit floating-point view of the coprocessor GPR's. */ | |
598 | MEP_FIRST_FP_CR32_REGNUM, | |
599 | MEP_LAST_FP_CR32_REGNUM = MEP_FIRST_FP_CR32_REGNUM + 31, | |
600 | ||
601 | /* The 64-bit integer view of the coprocessor GPR's. */ | |
602 | MEP_FIRST_CR64_REGNUM, | |
603 | MEP_LAST_CR64_REGNUM = MEP_FIRST_CR64_REGNUM + 31, | |
604 | ||
605 | /* The 64-bit floating-point view of the coprocessor GPR's. */ | |
606 | MEP_FIRST_FP_CR64_REGNUM, | |
607 | MEP_LAST_FP_CR64_REGNUM = MEP_FIRST_FP_CR64_REGNUM + 31, | |
608 | ||
609 | MEP_FIRST_CCR_REGNUM, | |
610 | MEP_LAST_CCR_REGNUM = MEP_FIRST_CCR_REGNUM + 63, | |
611 | ||
612 | MEP_LAST_PSEUDO_REGNUM = MEP_LAST_CCR_REGNUM, | |
613 | ||
614 | MEP_NUM_PSEUDO_REGS = (MEP_LAST_PSEUDO_REGNUM - MEP_LAST_RAW_REGNUM), | |
615 | ||
616 | MEP_NUM_REGS = MEP_NUM_RAW_REGS + MEP_NUM_PSEUDO_REGS | |
617 | }; | |
618 | ||
619 | ||
620 | #define IN_SET(set, n) \ | |
621 | (MEP_FIRST_ ## set ## _REGNUM <= (n) && (n) <= MEP_LAST_ ## set ## _REGNUM) | |
622 | ||
623 | #define IS_GPR_REGNUM(n) (IN_SET (GPR, (n))) | |
624 | #define IS_RAW_CSR_REGNUM(n) (IN_SET (RAW_CSR, (n))) | |
625 | #define IS_RAW_CR_REGNUM(n) (IN_SET (RAW_CR, (n))) | |
626 | #define IS_RAW_CCR_REGNUM(n) (IN_SET (RAW_CCR, (n))) | |
627 | ||
628 | #define IS_CSR_REGNUM(n) (IN_SET (CSR, (n))) | |
629 | #define IS_CR32_REGNUM(n) (IN_SET (CR32, (n))) | |
630 | #define IS_FP_CR32_REGNUM(n) (IN_SET (FP_CR32, (n))) | |
631 | #define IS_CR64_REGNUM(n) (IN_SET (CR64, (n))) | |
632 | #define IS_FP_CR64_REGNUM(n) (IN_SET (FP_CR64, (n))) | |
633 | #define IS_CR_REGNUM(n) (IS_CR32_REGNUM (n) || IS_FP_CR32_REGNUM (n) \ | |
634 | || IS_CR64_REGNUM (n) || IS_FP_CR64_REGNUM (n)) | |
635 | #define IS_CCR_REGNUM(n) (IN_SET (CCR, (n))) | |
636 | ||
637 | #define IS_RAW_REGNUM(n) (IN_SET (RAW, (n))) | |
638 | #define IS_PSEUDO_REGNUM(n) (IN_SET (PSEUDO, (n))) | |
639 | ||
640 | #define NUM_REGS_IN_SET(set) \ | |
641 | (MEP_LAST_ ## set ## _REGNUM - MEP_FIRST_ ## set ## _REGNUM + 1) | |
642 | ||
643 | #define MEP_GPR_SIZE (4) /* Size of a MeP general-purpose register. */ | |
644 | #define MEP_PSW_SIZE (4) /* Size of the PSW register. */ | |
645 | #define MEP_LP_SIZE (4) /* Size of the LP register. */ | |
646 | ||
647 | ||
648 | /* Many of the control/special registers contain bits that cannot be | |
649 | written to; some are entirely read-only. So we present them all as | |
650 | pseudoregisters. | |
651 | ||
652 | The following table describes the special properties of each CSR. */ | |
653 | struct mep_csr_register | |
654 | { | |
655 | /* The number of this CSR's raw register. */ | |
656 | int raw; | |
657 | ||
658 | /* The number of this CSR's pseudoregister. */ | |
659 | int pseudo; | |
660 | ||
661 | /* A mask of the bits that are writeable: if a bit is set here, then | |
662 | it can be modified; if the bit is clear, then it cannot. */ | |
663 | LONGEST writeable_bits; | |
664 | }; | |
665 | ||
666 | ||
667 | /* mep_csr_registers[i] describes the i'th CSR. | |
668 | We just list the register numbers here explicitly to help catch | |
669 | typos. */ | |
670 | #define CSR(name) MEP_RAW_ ## name ## _REGNUM, MEP_ ## name ## _REGNUM | |
671 | struct mep_csr_register mep_csr_registers[] = { | |
672 | { CSR(PC), 0xffffffff }, /* manual says r/o, but we can write it */ | |
673 | { CSR(LP), 0xffffffff }, | |
674 | { CSR(SAR), 0x0000003f }, | |
675 | { CSR(CSR3), 0xffffffff }, | |
676 | { CSR(RPB), 0xfffffffe }, | |
677 | { CSR(RPE), 0xffffffff }, | |
678 | { CSR(RPC), 0xffffffff }, | |
679 | { CSR(HI), 0xffffffff }, | |
680 | { CSR(LO), 0xffffffff }, | |
681 | { CSR(CSR9), 0xffffffff }, | |
682 | { CSR(CSR10), 0xffffffff }, | |
683 | { CSR(CSR11), 0xffffffff }, | |
684 | { CSR(MB0), 0x0000ffff }, | |
685 | { CSR(ME0), 0x0000ffff }, | |
686 | { CSR(MB1), 0x0000ffff }, | |
687 | { CSR(ME1), 0x0000ffff }, | |
688 | { CSR(PSW), 0x000003ff }, | |
689 | { CSR(ID), 0x00000000 }, | |
690 | { CSR(TMP), 0xffffffff }, | |
691 | { CSR(EPC), 0xffffffff }, | |
692 | { CSR(EXC), 0x000030f0 }, | |
693 | { CSR(CFG), 0x00c0001b }, | |
694 | { CSR(CSR22), 0xffffffff }, | |
695 | { CSR(NPC), 0xffffffff }, | |
696 | { CSR(DBG), 0x00000580 }, | |
697 | { CSR(DEPC), 0xffffffff }, | |
698 | { CSR(OPT), 0x00000000 }, | |
699 | { CSR(RCFG), 0x00000000 }, | |
700 | { CSR(CCFG), 0x00000000 }, | |
701 | { CSR(CSR29), 0xffffffff }, | |
702 | { CSR(CSR30), 0xffffffff }, | |
703 | { CSR(CSR31), 0xffffffff }, | |
704 | }; | |
705 | ||
706 | ||
707 | /* If R is the number of a raw register, then mep_raw_to_pseudo[R] is | |
708 | the number of the corresponding pseudoregister. Otherwise, | |
709 | mep_raw_to_pseudo[R] == R. */ | |
710 | static int mep_raw_to_pseudo[MEP_NUM_REGS]; | |
711 | ||
712 | /* If R is the number of a pseudoregister, then mep_pseudo_to_raw[R] | |
713 | is the number of the underlying raw register. Otherwise | |
714 | mep_pseudo_to_raw[R] == R. */ | |
715 | static int mep_pseudo_to_raw[MEP_NUM_REGS]; | |
716 | ||
717 | static void | |
718 | mep_init_pseudoregister_maps (void) | |
719 | { | |
720 | int i; | |
721 | ||
722 | /* Verify that mep_csr_registers covers all the CSRs, in order. */ | |
723 | gdb_assert (ARRAY_SIZE (mep_csr_registers) == NUM_REGS_IN_SET (CSR)); | |
724 | gdb_assert (ARRAY_SIZE (mep_csr_registers) == NUM_REGS_IN_SET (RAW_CSR)); | |
725 | ||
726 | /* Verify that the raw and pseudo ranges have matching sizes. */ | |
727 | gdb_assert (NUM_REGS_IN_SET (RAW_CSR) == NUM_REGS_IN_SET (CSR)); | |
728 | gdb_assert (NUM_REGS_IN_SET (RAW_CR) == NUM_REGS_IN_SET (CR32)); | |
729 | gdb_assert (NUM_REGS_IN_SET (RAW_CR) == NUM_REGS_IN_SET (CR64)); | |
730 | gdb_assert (NUM_REGS_IN_SET (RAW_CCR) == NUM_REGS_IN_SET (CCR)); | |
731 | ||
732 | for (i = 0; i < ARRAY_SIZE (mep_csr_registers); i++) | |
733 | { | |
734 | struct mep_csr_register *r = &mep_csr_registers[i]; | |
735 | ||
736 | gdb_assert (r->pseudo == MEP_FIRST_CSR_REGNUM + i); | |
737 | gdb_assert (r->raw == MEP_FIRST_RAW_CSR_REGNUM + i); | |
738 | } | |
739 | ||
740 | /* Set up the initial raw<->pseudo mappings. */ | |
741 | for (i = 0; i < MEP_NUM_REGS; i++) | |
742 | { | |
743 | mep_raw_to_pseudo[i] = i; | |
744 | mep_pseudo_to_raw[i] = i; | |
745 | } | |
746 | ||
747 | /* Add the CSR raw<->pseudo mappings. */ | |
748 | for (i = 0; i < ARRAY_SIZE (mep_csr_registers); i++) | |
749 | { | |
750 | struct mep_csr_register *r = &mep_csr_registers[i]; | |
751 | ||
752 | mep_raw_to_pseudo[r->raw] = r->pseudo; | |
753 | mep_pseudo_to_raw[r->pseudo] = r->raw; | |
754 | } | |
755 | ||
756 | /* Add the CR raw<->pseudo mappings. */ | |
757 | for (i = 0; i < NUM_REGS_IN_SET (RAW_CR); i++) | |
758 | { | |
759 | int raw = MEP_FIRST_RAW_CR_REGNUM + i; | |
760 | int pseudo32 = MEP_FIRST_CR32_REGNUM + i; | |
761 | int pseudofp32 = MEP_FIRST_FP_CR32_REGNUM + i; | |
762 | int pseudo64 = MEP_FIRST_CR64_REGNUM + i; | |
763 | int pseudofp64 = MEP_FIRST_FP_CR64_REGNUM + i; | |
764 | ||
765 | /* Truly, the raw->pseudo mapping depends on the current module. | |
766 | But we use the raw->pseudo mapping when we read the debugging | |
767 | info; at that point, we don't know what module we'll actually | |
768 | be running yet. So, we always supply the 64-bit register | |
769 | numbers; GDB knows how to pick a smaller value out of a | |
770 | larger register properly. */ | |
771 | mep_raw_to_pseudo[raw] = pseudo64; | |
772 | mep_pseudo_to_raw[pseudo32] = raw; | |
773 | mep_pseudo_to_raw[pseudofp32] = raw; | |
774 | mep_pseudo_to_raw[pseudo64] = raw; | |
775 | mep_pseudo_to_raw[pseudofp64] = raw; | |
776 | } | |
777 | ||
778 | /* Add the CCR raw<->pseudo mappings. */ | |
779 | for (i = 0; i < NUM_REGS_IN_SET (CCR); i++) | |
780 | { | |
781 | int raw = MEP_FIRST_RAW_CCR_REGNUM + i; | |
782 | int pseudo = MEP_FIRST_CCR_REGNUM + i; | |
783 | mep_raw_to_pseudo[raw] = pseudo; | |
784 | mep_pseudo_to_raw[pseudo] = raw; | |
785 | } | |
786 | } | |
787 | ||
788 | ||
789 | static int | |
790 | mep_debug_reg_to_regnum (int debug_reg) | |
791 | { | |
792 | /* The debug info uses the raw register numbers. */ | |
793 | return mep_raw_to_pseudo[debug_reg]; | |
794 | } | |
795 | ||
796 | ||
797 | /* Return the size, in bits, of the coprocessor pseudoregister | |
798 | numbered PSEUDO. */ | |
799 | static int | |
800 | mep_pseudo_cr_size (int pseudo) | |
801 | { | |
802 | if (IS_CR32_REGNUM (pseudo) | |
803 | || IS_FP_CR32_REGNUM (pseudo)) | |
804 | return 32; | |
805 | else if (IS_CR64_REGNUM (pseudo) | |
806 | || IS_FP_CR64_REGNUM (pseudo)) | |
807 | return 64; | |
808 | else | |
809 | gdb_assert (0); | |
810 | } | |
811 | ||
812 | ||
813 | /* If the coprocessor pseudoregister numbered PSEUDO is a | |
814 | floating-point register, return non-zero; if it is an integer | |
815 | register, return zero. */ | |
816 | static int | |
817 | mep_pseudo_cr_is_float (int pseudo) | |
818 | { | |
819 | return (IS_FP_CR32_REGNUM (pseudo) | |
820 | || IS_FP_CR64_REGNUM (pseudo)); | |
821 | } | |
822 | ||
823 | ||
824 | /* Given a coprocessor GPR pseudoregister number, return its index | |
825 | within that register bank. */ | |
826 | static int | |
827 | mep_pseudo_cr_index (int pseudo) | |
828 | { | |
829 | if (IS_CR32_REGNUM (pseudo)) | |
830 | return pseudo - MEP_FIRST_CR32_REGNUM; | |
831 | else if (IS_FP_CR32_REGNUM (pseudo)) | |
832 | return pseudo - MEP_FIRST_FP_CR32_REGNUM; | |
833 | else if (IS_CR64_REGNUM (pseudo)) | |
834 | return pseudo - MEP_FIRST_CR64_REGNUM; | |
835 | else if (IS_FP_CR64_REGNUM (pseudo)) | |
836 | return pseudo - MEP_FIRST_FP_CR64_REGNUM; | |
837 | else | |
838 | gdb_assert (0); | |
839 | } | |
840 | ||
841 | ||
842 | /* Return the me_module index describing the current target. | |
843 | ||
844 | If the current target has registers (e.g., simulator, remote | |
845 | target), then this uses the value of the 'module' register, raw | |
846 | register MEP_MODULE_REGNUM. Otherwise, this retrieves the value | |
847 | from the ELF header's e_flags field of the current executable | |
848 | file. */ | |
849 | static CONFIG_ATTR | |
850 | current_me_module () | |
851 | { | |
852 | if (target_has_registers) | |
853 | return read_register (MEP_MODULE_REGNUM); | |
854 | else | |
855 | return gdbarch_tdep (current_gdbarch)->me_module; | |
856 | } | |
857 | ||
858 | ||
859 | /* Return the set of options for the current target, in the form that | |
860 | the OPT register would use. | |
861 | ||
862 | If the current target has registers (e.g., simulator, remote | |
863 | target), then this is the actual value of the OPT register. If the | |
864 | current target does not have registers (e.g., an executable file), | |
865 | then use the 'module_opt' field we computed when we build the | |
866 | gdbarch object for this module. */ | |
867 | static unsigned int | |
868 | current_options () | |
869 | { | |
870 | if (target_has_registers) | |
871 | return read_register (MEP_OPT_REGNUM); | |
872 | else | |
873 | return me_module_opt (current_me_module ()); | |
874 | } | |
875 | ||
876 | ||
877 | /* Return the width of the current me_module's coprocessor data bus, | |
878 | in bits. This is either 32 or 64. */ | |
879 | static int | |
880 | current_cop_data_bus_width () | |
881 | { | |
882 | return me_module_cop_data_bus_width (current_me_module ()); | |
883 | } | |
884 | ||
885 | ||
886 | /* Return the keyword table of coprocessor general-purpose register | |
887 | names appropriate for the me_module we're dealing with. */ | |
888 | static CGEN_KEYWORD * | |
889 | current_cr_names () | |
890 | { | |
891 | const CGEN_HW_ENTRY *hw | |
892 | = me_module_register_set (current_me_module (), "h-cr-", HW_H_CR); | |
893 | ||
894 | return register_set_keyword_table (hw); | |
895 | } | |
896 | ||
897 | ||
898 | /* Return non-zero if the coprocessor general-purpose registers are | |
899 | floating-point values, zero otherwise. */ | |
900 | static int | |
901 | current_cr_is_float () | |
902 | { | |
903 | const CGEN_HW_ENTRY *hw | |
904 | = me_module_register_set (current_me_module (), "h-cr-", HW_H_CR); | |
905 | ||
906 | return CGEN_ATTR_CGEN_HW_IS_FLOAT_VALUE (CGEN_HW_ATTRS (hw)); | |
907 | } | |
908 | ||
909 | ||
910 | /* Return the keyword table of coprocessor control register names | |
911 | appropriate for the me_module we're dealing with. */ | |
912 | static CGEN_KEYWORD * | |
913 | current_ccr_names () | |
914 | { | |
915 | const CGEN_HW_ENTRY *hw | |
916 | = me_module_register_set (current_me_module (), "h-ccr-", HW_H_CCR); | |
917 | ||
918 | return register_set_keyword_table (hw); | |
919 | } | |
920 | ||
921 | ||
922 | static const char * | |
923 | mep_register_name (int regnr) | |
924 | { | |
925 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
926 | ||
927 | /* General-purpose registers. */ | |
928 | static const char *gpr_names[] = { | |
929 | "r0", "r1", "r2", "r3", /* 0 */ | |
930 | "r4", "r5", "r6", "r7", /* 4 */ | |
931 | "fp", "r9", "r10", "r11", /* 8 */ | |
932 | "r12", "tp", "gp", "sp" /* 12 */ | |
933 | }; | |
934 | ||
935 | /* Special-purpose registers. */ | |
936 | static const char *csr_names[] = { | |
937 | "pc", "lp", "sar", "", /* 0 csr3: reserved */ | |
938 | "rpb", "rpe", "rpc", "hi", /* 4 */ | |
939 | "lo", "", "", "", /* 8 csr9-csr11: reserved */ | |
940 | "mb0", "me0", "mb1", "me1", /* 12 */ | |
941 | ||
942 | "psw", "id", "tmp", "epc", /* 16 */ | |
943 | "exc", "cfg", "", "npc", /* 20 csr22: reserved */ | |
944 | "dbg", "depc", "opt", "rcfg", /* 24 */ | |
945 | "ccfg", "", "", "" /* 28 csr29-csr31: reserved */ | |
946 | }; | |
947 | ||
948 | if (IS_GPR_REGNUM (regnr)) | |
949 | return gpr_names[regnr - MEP_R0_REGNUM]; | |
950 | else if (IS_CSR_REGNUM (regnr)) | |
951 | { | |
952 | /* The 'hi' and 'lo' registers are only present on processors | |
953 | that have the 'MUL' or 'DIV' instructions enabled. */ | |
954 | if ((regnr == MEP_HI_REGNUM || regnr == MEP_LO_REGNUM) | |
955 | && (! (current_options () & (MEP_OPT_MUL | MEP_OPT_DIV)))) | |
956 | return ""; | |
957 | ||
958 | return csr_names[regnr - MEP_FIRST_CSR_REGNUM]; | |
959 | } | |
960 | else if (IS_CR_REGNUM (regnr)) | |
961 | { | |
962 | CGEN_KEYWORD *names; | |
963 | int cr_size; | |
964 | int cr_is_float; | |
965 | ||
966 | /* Does this module have a coprocessor at all? */ | |
967 | if (! (current_options () & MEP_OPT_COP)) | |
968 | return ""; | |
969 | ||
970 | names = current_cr_names (); | |
971 | if (! names) | |
972 | /* This module's coprocessor has no general-purpose registers. */ | |
973 | return ""; | |
974 | ||
975 | cr_size = current_cop_data_bus_width (); | |
976 | if (cr_size != mep_pseudo_cr_size (regnr)) | |
977 | /* This module's coprocessor's GPR's are of a different size. */ | |
978 | return ""; | |
979 | ||
980 | cr_is_float = current_cr_is_float (); | |
981 | /* The extra ! operators ensure we get boolean equality, not | |
982 | numeric equality. */ | |
983 | if (! cr_is_float != ! mep_pseudo_cr_is_float (regnr)) | |
984 | /* This module's coprocessor's GPR's are of a different type. */ | |
985 | return ""; | |
986 | ||
987 | return register_name_from_keyword (names, mep_pseudo_cr_index (regnr)); | |
988 | } | |
989 | else if (IS_CCR_REGNUM (regnr)) | |
990 | { | |
991 | /* Does this module have a coprocessor at all? */ | |
992 | if (! (current_options () & MEP_OPT_COP)) | |
993 | return ""; | |
994 | ||
995 | { | |
996 | CGEN_KEYWORD *names = current_ccr_names (); | |
997 | ||
998 | if (! names) | |
999 | /* This me_module's coprocessor has no control registers. */ | |
1000 | return ""; | |
1001 | ||
1002 | return register_name_from_keyword (names, regnr-MEP_FIRST_CCR_REGNUM); | |
1003 | } | |
1004 | } | |
1005 | ||
1006 | /* It might be nice to give the 'module' register a name, but that | |
1007 | would affect the output of 'info all-registers', which would | |
1008 | disturb the test suites. So we leave it invisible. */ | |
1009 | else | |
1010 | return NULL; | |
1011 | } | |
1012 | ||
1013 | ||
1014 | /* Custom register groups for the MeP. */ | |
1015 | static struct reggroup *mep_csr_reggroup; /* control/special */ | |
1016 | static struct reggroup *mep_cr_reggroup; /* coprocessor general-purpose */ | |
1017 | static struct reggroup *mep_ccr_reggroup; /* coprocessor control */ | |
1018 | ||
1019 | ||
1020 | static int | |
1021 | mep_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
1022 | struct reggroup *group) | |
1023 | { | |
1024 | /* Filter reserved or unused register numbers. */ | |
1025 | { | |
1026 | const char *name = mep_register_name (regnum); | |
1027 | ||
1028 | if (! name || name[0] == '\0') | |
1029 | return 0; | |
1030 | } | |
1031 | ||
1032 | /* We could separate the GPRs and the CSRs. Toshiba has approved of | |
1033 | the existing behavior, so we'd want to run that by them. */ | |
1034 | if (group == general_reggroup) | |
1035 | return (IS_GPR_REGNUM (regnum) | |
1036 | || IS_CSR_REGNUM (regnum)); | |
1037 | ||
1038 | /* Everything is in the 'all' reggroup, except for the raw CSR's. */ | |
1039 | else if (group == all_reggroup) | |
1040 | return (IS_GPR_REGNUM (regnum) | |
1041 | || IS_CSR_REGNUM (regnum) | |
1042 | || IS_CR_REGNUM (regnum) | |
1043 | || IS_CCR_REGNUM (regnum)); | |
1044 | ||
1045 | /* All registers should be saved and restored, except for the raw | |
1046 | CSR's. | |
1047 | ||
1048 | This is probably right if the coprocessor is something like a | |
1049 | floating-point unit, but would be wrong if the coprocessor is | |
1050 | something that does I/O, where register accesses actually cause | |
1051 | externally-visible actions. But I get the impression that the | |
1052 | coprocessor isn't supposed to do things like that --- you'd use a | |
1053 | hardware engine, perhaps. */ | |
1054 | else if (group == save_reggroup || group == restore_reggroup) | |
1055 | return (IS_GPR_REGNUM (regnum) | |
1056 | || IS_CSR_REGNUM (regnum) | |
1057 | || IS_CR_REGNUM (regnum) | |
1058 | || IS_CCR_REGNUM (regnum)); | |
1059 | ||
1060 | else if (group == mep_csr_reggroup) | |
1061 | return IS_CSR_REGNUM (regnum); | |
1062 | else if (group == mep_cr_reggroup) | |
1063 | return IS_CR_REGNUM (regnum); | |
1064 | else if (group == mep_ccr_reggroup) | |
1065 | return IS_CCR_REGNUM (regnum); | |
1066 | else | |
1067 | return 0; | |
1068 | } | |
1069 | ||
1070 | ||
1071 | static struct type * | |
1072 | mep_register_type (struct gdbarch *gdbarch, int reg_nr) | |
1073 | { | |
1074 | /* Coprocessor general-purpose registers may be either 32 or 64 bits | |
1075 | long. So for them, the raw registers are always 64 bits long (to | |
1076 | keep the 'g' packet format fixed), and the pseudoregisters vary | |
1077 | in length. */ | |
1078 | if (IS_RAW_CR_REGNUM (reg_nr)) | |
1079 | return builtin_type_uint64; | |
1080 | ||
1081 | /* Since GDB doesn't allow registers to change type, we have two | |
1082 | banks of pseudoregisters for the coprocessor general-purpose | |
1083 | registers: one that gives a 32-bit view, and one that gives a | |
1084 | 64-bit view. We hide or show one or the other depending on the | |
1085 | current module. */ | |
1086 | if (IS_CR_REGNUM (reg_nr)) | |
1087 | { | |
1088 | int size = mep_pseudo_cr_size (reg_nr); | |
1089 | if (size == 32) | |
1090 | { | |
1091 | if (mep_pseudo_cr_is_float (reg_nr)) | |
1092 | return builtin_type_float; | |
1093 | else | |
1094 | return builtin_type_uint32; | |
1095 | } | |
1096 | else if (size == 64) | |
1097 | { | |
1098 | if (mep_pseudo_cr_is_float (reg_nr)) | |
1099 | return builtin_type_double; | |
1100 | else | |
1101 | return builtin_type_uint64; | |
1102 | } | |
1103 | else | |
1104 | gdb_assert (0); | |
1105 | } | |
1106 | ||
1107 | /* All other registers are 32 bits long. */ | |
1108 | else | |
1109 | return builtin_type_uint32; | |
1110 | } | |
1111 | ||
1112 | ||
1113 | static CORE_ADDR | |
1114 | mep_read_pc (ptid_t ptid) | |
1115 | { | |
1116 | ptid_t saved_ptid; | |
1117 | CORE_ADDR pc; | |
1118 | ||
1119 | saved_ptid = inferior_ptid; | |
1120 | inferior_ptid = ptid; | |
1121 | ||
1122 | pc = read_register (MEP_PC_REGNUM); | |
1123 | ||
1124 | inferior_ptid = saved_ptid; | |
1125 | return pc; | |
1126 | } | |
1127 | ||
1128 | static void | |
1129 | mep_write_pc (CORE_ADDR pc, ptid_t ptid) | |
1130 | { | |
1131 | ptid_t saved_ptid; | |
1132 | ||
1133 | saved_ptid = inferior_ptid; | |
1134 | inferior_ptid = ptid; | |
1135 | ||
1136 | write_register (MEP_PC_REGNUM, pc); | |
1137 | ||
1138 | inferior_ptid = saved_ptid; | |
1139 | } | |
1140 | ||
1141 | ||
1142 | static void | |
1143 | mep_pseudo_cr32_read (struct gdbarch *gdbarch, | |
1144 | struct regcache *regcache, | |
1145 | int cookednum, | |
1146 | void *buf) | |
1147 | { | |
1148 | /* Read the raw register into a 64-bit buffer, and then return the | |
1149 | appropriate end of that buffer. */ | |
1150 | int rawnum = mep_pseudo_to_raw[cookednum]; | |
1151 | char buf64[8]; | |
1152 | ||
1153 | gdb_assert (TYPE_LENGTH (register_type (gdbarch, rawnum)) == sizeof (buf64)); | |
1154 | gdb_assert (TYPE_LENGTH (register_type (gdbarch, cookednum)) == 4); | |
1155 | regcache_raw_read (regcache, rawnum, buf64); | |
1156 | /* Slow, but legible. */ | |
1157 | store_unsigned_integer (buf, 4, extract_unsigned_integer (buf64, 8)); | |
1158 | } | |
1159 | ||
1160 | ||
1161 | static void | |
1162 | mep_pseudo_cr64_read (struct gdbarch *gdbarch, | |
1163 | struct regcache *regcache, | |
1164 | int cookednum, | |
1165 | void *buf) | |
1166 | { | |
1167 | regcache_raw_read (regcache, mep_pseudo_to_raw[cookednum], buf); | |
1168 | } | |
1169 | ||
1170 | ||
1171 | static void | |
1172 | mep_pseudo_register_read (struct gdbarch *gdbarch, | |
1173 | struct regcache *regcache, | |
1174 | int cookednum, | |
1175 | gdb_byte *buf) | |
1176 | { | |
1177 | if (IS_CSR_REGNUM (cookednum) | |
1178 | || IS_CCR_REGNUM (cookednum)) | |
1179 | regcache_raw_read (regcache, mep_pseudo_to_raw[cookednum], buf); | |
1180 | else if (IS_CR32_REGNUM (cookednum) | |
1181 | || IS_FP_CR32_REGNUM (cookednum)) | |
1182 | mep_pseudo_cr32_read (gdbarch, regcache, cookednum, buf); | |
1183 | else if (IS_CR64_REGNUM (cookednum) | |
1184 | || IS_FP_CR64_REGNUM (cookednum)) | |
1185 | mep_pseudo_cr64_read (gdbarch, regcache, cookednum, buf); | |
1186 | else | |
1187 | gdb_assert (0); | |
1188 | } | |
1189 | ||
1190 | ||
1191 | static void | |
1192 | mep_pseudo_csr_write (struct gdbarch *gdbarch, | |
1193 | struct regcache *regcache, | |
1194 | int cookednum, | |
1195 | const void *buf) | |
1196 | { | |
1197 | int size = register_size (gdbarch, cookednum); | |
1198 | struct mep_csr_register *r | |
1199 | = &mep_csr_registers[cookednum - MEP_FIRST_CSR_REGNUM]; | |
1200 | ||
1201 | if (r->writeable_bits == 0) | |
1202 | /* A completely read-only register; avoid the read-modify- | |
1203 | write cycle, and juts ignore the entire write. */ | |
1204 | ; | |
1205 | else | |
1206 | { | |
1207 | /* A partially writeable register; do a read-modify-write cycle. */ | |
1208 | ULONGEST old_bits; | |
1209 | ULONGEST new_bits; | |
1210 | ULONGEST mixed_bits; | |
1211 | ||
1212 | regcache_raw_read_unsigned (regcache, r->raw, &old_bits); | |
1213 | new_bits = extract_unsigned_integer (buf, size); | |
1214 | mixed_bits = ((r->writeable_bits & new_bits) | |
1215 | | (~r->writeable_bits & old_bits)); | |
1216 | regcache_raw_write_unsigned (regcache, r->raw, mixed_bits); | |
1217 | } | |
1218 | } | |
1219 | ||
1220 | ||
1221 | static void | |
1222 | mep_pseudo_cr32_write (struct gdbarch *gdbarch, | |
1223 | struct regcache *regcache, | |
1224 | int cookednum, | |
1225 | const void *buf) | |
1226 | { | |
1227 | /* Expand the 32-bit value into a 64-bit value, and write that to | |
1228 | the pseudoregister. */ | |
1229 | int rawnum = mep_pseudo_to_raw[cookednum]; | |
1230 | char buf64[8]; | |
1231 | ||
1232 | gdb_assert (TYPE_LENGTH (register_type (gdbarch, rawnum)) == sizeof (buf64)); | |
1233 | gdb_assert (TYPE_LENGTH (register_type (gdbarch, cookednum)) == 4); | |
1234 | /* Slow, but legible. */ | |
1235 | store_unsigned_integer (buf64, 8, extract_unsigned_integer (buf, 4)); | |
1236 | regcache_raw_write (regcache, rawnum, buf64); | |
1237 | } | |
1238 | ||
1239 | ||
1240 | static void | |
1241 | mep_pseudo_cr64_write (struct gdbarch *gdbarch, | |
1242 | struct regcache *regcache, | |
1243 | int cookednum, | |
1244 | const void *buf) | |
1245 | { | |
1246 | regcache_raw_write (regcache, mep_pseudo_to_raw[cookednum], buf); | |
1247 | } | |
1248 | ||
1249 | ||
1250 | static void | |
1251 | mep_pseudo_register_write (struct gdbarch *gdbarch, | |
1252 | struct regcache *regcache, | |
1253 | int cookednum, | |
1254 | const gdb_byte *buf) | |
1255 | { | |
1256 | if (IS_CSR_REGNUM (cookednum)) | |
1257 | mep_pseudo_csr_write (gdbarch, regcache, cookednum, buf); | |
1258 | else if (IS_CR32_REGNUM (cookednum) | |
1259 | || IS_FP_CR32_REGNUM (cookednum)) | |
1260 | mep_pseudo_cr32_write (gdbarch, regcache, cookednum, buf); | |
1261 | else if (IS_CR64_REGNUM (cookednum) | |
1262 | || IS_FP_CR64_REGNUM (cookednum)) | |
1263 | mep_pseudo_cr64_write (gdbarch, regcache, cookednum, buf); | |
1264 | else if (IS_CCR_REGNUM (cookednum)) | |
1265 | regcache_raw_write (regcache, mep_pseudo_to_raw[cookednum], buf); | |
1266 | else | |
1267 | gdb_assert (0); | |
1268 | } | |
1269 | ||
1270 | ||
1271 | \f | |
1272 | /* Disassembly. */ | |
1273 | ||
1274 | /* The mep disassembler needs to know about the section in order to | |
1275 | work correctly. */ | |
1276 | int | |
1277 | mep_gdb_print_insn (bfd_vma pc, disassemble_info * info) | |
1278 | { | |
1279 | struct obj_section * s = find_pc_section (pc); | |
1280 | ||
1281 | if (s) | |
1282 | { | |
1283 | /* The libopcodes disassembly code uses the section to find the | |
1284 | BFD, the BFD to find the ELF header, the ELF header to find | |
1285 | the me_module index, and the me_module index to select the | |
1286 | right instructions to print. */ | |
1287 | info->section = s->the_bfd_section; | |
1288 | info->arch = bfd_arch_mep; | |
1289 | ||
1290 | return print_insn_mep (pc, info); | |
1291 | } | |
1292 | ||
1293 | return 0; | |
1294 | } | |
1295 | ||
1296 | \f | |
1297 | /* Prologue analysis. */ | |
1298 | ||
1299 | ||
1300 | /* The MeP has two classes of instructions: "core" instructions, which | |
1301 | are pretty normal RISC chip stuff, and "coprocessor" instructions, | |
1302 | which are mostly concerned with moving data in and out of | |
1303 | coprocessor registers, and branching on coprocessor condition | |
1304 | codes. There's space in the instruction set for custom coprocessor | |
1305 | instructions, too. | |
1306 | ||
1307 | Instructions can be 16 or 32 bits long; the top two bits of the | |
1308 | first byte indicate the length. The coprocessor instructions are | |
1309 | mixed in with the core instructions, and there's no easy way to | |
1310 | distinguish them; you have to completely decode them to tell one | |
1311 | from the other. | |
1312 | ||
1313 | The MeP also supports a "VLIW" operation mode, where instructions | |
1314 | always occur in fixed-width bundles. The bundles are either 32 | |
1315 | bits or 64 bits long, depending on a fixed configuration flag. You | |
1316 | decode the first part of the bundle as normal; if it's a core | |
1317 | instruction, and there's any space left in the bundle, the | |
1318 | remainder of the bundle is a coprocessor instruction, which will | |
1319 | execute in parallel with the core instruction. If the first part | |
1320 | of the bundle is a coprocessor instruction, it occupies the entire | |
1321 | bundle. | |
1322 | ||
1323 | So, here are all the cases: | |
1324 | ||
1325 | - 32-bit VLIW mode: | |
1326 | Every bundle is four bytes long, and naturally aligned, and can hold | |
1327 | one or two instructions: | |
1328 | - 16-bit core instruction; 16-bit coprocessor instruction | |
1329 | These execute in parallel. | |
1330 | - 32-bit core instruction | |
1331 | - 32-bit coprocessor instruction | |
1332 | ||
1333 | - 64-bit VLIW mode: | |
1334 | Every bundle is eight bytes long, and naturally aligned, and can hold | |
1335 | one or two instructions: | |
1336 | - 16-bit core instruction; 48-bit (!) coprocessor instruction | |
1337 | These execute in parallel. | |
1338 | - 32-bit core instruction; 32-bit coprocessor instruction | |
1339 | These execute in parallel. | |
1340 | - 64-bit coprocessor instruction | |
1341 | ||
1342 | Now, the MeP manual doesn't define any 48- or 64-bit coprocessor | |
1343 | instruction, so I don't really know what's up there; perhaps these | |
1344 | are always the user-defined coprocessor instructions. */ | |
1345 | ||
1346 | ||
1347 | /* Return non-zero if PC is in a VLIW code section, zero | |
1348 | otherwise. */ | |
1349 | static int | |
1350 | mep_pc_in_vliw_section (CORE_ADDR pc) | |
1351 | { | |
1352 | struct obj_section *s = find_pc_section (pc); | |
1353 | if (s) | |
1354 | return (s->the_bfd_section->flags & SEC_MEP_VLIW); | |
1355 | return 0; | |
1356 | } | |
1357 | ||
1358 | ||
1359 | /* Set *INSN to the next core instruction at PC, and return the | |
1360 | address of the next instruction. | |
1361 | ||
1362 | The MeP instruction encoding is endian-dependent. 16- and 32-bit | |
1363 | instructions are encoded as one or two two-byte parts, and each | |
1364 | part is byte-swapped independently. Thus: | |
1365 | ||
1366 | void | |
1367 | foo (void) | |
1368 | { | |
1369 | asm ("movu $1, 0x123456"); | |
1370 | asm ("sb $1,0x5678($2)"); | |
1371 | asm ("clip $1, 19"); | |
1372 | } | |
1373 | ||
1374 | compiles to this big-endian code: | |
1375 | ||
1376 | 0: d1 56 12 34 movu $1,0x123456 | |
1377 | 4: c1 28 56 78 sb $1,22136($2) | |
1378 | 8: f1 01 10 98 clip $1,0x13 | |
1379 | c: 70 02 ret | |
1380 | ||
1381 | and this little-endian code: | |
1382 | ||
1383 | 0: 56 d1 34 12 movu $1,0x123456 | |
1384 | 4: 28 c1 78 56 sb $1,22136($2) | |
1385 | 8: 01 f1 98 10 clip $1,0x13 | |
1386 | c: 02 70 ret | |
1387 | ||
1388 | Instructions are returned in *INSN in an endian-independent form: a | |
1389 | given instruction always appears in *INSN the same way, regardless | |
1390 | of whether the instruction stream is big-endian or little-endian. | |
1391 | ||
1392 | *INSN's most significant 16 bits are the first (i.e., at lower | |
1393 | addresses) 16 bit part of the instruction. Its least significant | |
1394 | 16 bits are the second (i.e., higher-addressed) 16 bit part of the | |
1395 | instruction, or zero for a 16-bit instruction. Both 16-bit parts | |
1396 | are fetched using the current endianness. | |
1397 | ||
1398 | So, the *INSN values for the instruction sequence above would be | |
1399 | the following, in either endianness: | |
1400 | ||
1401 | 0xd1561234 movu $1,0x123456 | |
1402 | 0xc1285678 sb $1,22136($2) | |
1403 | 0xf1011098 clip $1,0x13 | |
1404 | 0x70020000 ret | |
1405 | ||
1406 | (In a sense, it would be more natural to return 16-bit instructions | |
1407 | in the least significant 16 bits of *INSN, but that would be | |
1408 | ambiguous. In order to tell whether you're looking at a 16- or a | |
1409 | 32-bit instruction, you have to consult the major opcode field --- | |
1410 | the most significant four bits of the instruction's first 16-bit | |
1411 | part. But if we put 16-bit instructions at the least significant | |
1412 | end of *INSN, then you don't know where to find the major opcode | |
1413 | field until you know if it's a 16- or a 32-bit instruction --- | |
1414 | which is where we started.) | |
1415 | ||
1416 | If PC points to a core / coprocessor bundle in a VLIW section, set | |
1417 | *INSN to the core instruction, and return the address of the next | |
1418 | bundle. This has the effect of skipping the bundled coprocessor | |
1419 | instruction. That's okay, since coprocessor instructions aren't | |
1420 | significant to prologue analysis --- for the time being, | |
1421 | anyway. */ | |
1422 | ||
1423 | static CORE_ADDR | |
1424 | mep_get_insn (CORE_ADDR pc, long *insn) | |
1425 | { | |
1426 | int pc_in_vliw_section; | |
1427 | int vliw_mode; | |
1428 | int insn_len; | |
1429 | char buf[2]; | |
1430 | ||
1431 | *insn = 0; | |
1432 | ||
1433 | /* Are we in a VLIW section? */ | |
1434 | pc_in_vliw_section = mep_pc_in_vliw_section (pc); | |
1435 | if (pc_in_vliw_section) | |
1436 | { | |
1437 | /* Yes, find out which bundle size. */ | |
1438 | vliw_mode = current_options () & (MEP_OPT_VL32 | MEP_OPT_VL64); | |
1439 | ||
1440 | /* If PC is in a VLIW section, but the current core doesn't say | |
1441 | that it supports either VLIW mode, then we don't have enough | |
1442 | information to parse the instruction stream it contains. | |
1443 | Since the "undifferentiated" standard core doesn't have | |
1444 | either VLIW mode bit set, this could happen. | |
1445 | ||
1446 | But it shouldn't be an error to (say) set a breakpoint in a | |
1447 | VLIW section, if you know you'll never reach it. (Perhaps | |
1448 | you have a script that sets a bunch of standard breakpoints.) | |
1449 | ||
1450 | So we'll just return zero here, and hope for the best. */ | |
1451 | if (! (vliw_mode & (MEP_OPT_VL32 | MEP_OPT_VL64))) | |
1452 | return 0; | |
1453 | ||
1454 | /* If both VL32 and VL64 are set, that's bogus, too. */ | |
1455 | if (vliw_mode == (MEP_OPT_VL32 | MEP_OPT_VL64)) | |
1456 | return 0; | |
1457 | } | |
1458 | else | |
1459 | vliw_mode = 0; | |
1460 | ||
1461 | read_memory (pc, buf, sizeof (buf)); | |
1462 | *insn = extract_unsigned_integer (buf, 2) << 16; | |
1463 | ||
1464 | /* The major opcode --- the top four bits of the first 16-bit | |
1465 | part --- indicates whether this instruction is 16 or 32 bits | |
1466 | long. All 32-bit instructions have a major opcode whose top | |
1467 | two bits are 11; all the rest are 16-bit instructions. */ | |
1468 | if ((*insn & 0xc0000000) == 0xc0000000) | |
1469 | { | |
1470 | /* Fetch the second 16-bit part of the instruction. */ | |
1471 | read_memory (pc + 2, buf, sizeof (buf)); | |
1472 | *insn = *insn | extract_unsigned_integer (buf, 2); | |
1473 | } | |
1474 | ||
1475 | /* If we're in VLIW code, then the VLIW width determines the address | |
1476 | of the next instruction. */ | |
1477 | if (vliw_mode) | |
1478 | { | |
1479 | /* In 32-bit VLIW code, all bundles are 32 bits long. We ignore the | |
1480 | coprocessor half of a core / copro bundle. */ | |
1481 | if (vliw_mode == MEP_OPT_VL32) | |
1482 | insn_len = 4; | |
1483 | ||
1484 | /* In 64-bit VLIW code, all bundles are 64 bits long. We ignore the | |
1485 | coprocessor half of a core / copro bundle. */ | |
1486 | else if (vliw_mode == MEP_OPT_VL64) | |
1487 | insn_len = 8; | |
1488 | ||
1489 | /* We'd better be in either core, 32-bit VLIW, or 64-bit VLIW mode. */ | |
1490 | else | |
1491 | gdb_assert (0); | |
1492 | } | |
1493 | ||
1494 | /* Otherwise, the top two bits of the major opcode are (again) what | |
1495 | we need to check. */ | |
1496 | else if ((*insn & 0xc0000000) == 0xc0000000) | |
1497 | insn_len = 4; | |
1498 | else | |
1499 | insn_len = 2; | |
1500 | ||
1501 | return pc + insn_len; | |
1502 | } | |
1503 | ||
1504 | ||
1505 | /* Sign-extend the LEN-bit value N. */ | |
1506 | #define SEXT(n, len) ((((int) (n)) ^ (1 << ((len) - 1))) - (1 << ((len) - 1))) | |
1507 | ||
1508 | /* Return the LEN-bit field at POS from I. */ | |
1509 | #define FIELD(i, pos, len) (((i) >> (pos)) & ((1 << (len)) - 1)) | |
1510 | ||
1511 | /* Like FIELD, but sign-extend the field's value. */ | |
1512 | #define SFIELD(i, pos, len) (SEXT (FIELD ((i), (pos), (len)), (len))) | |
1513 | ||
1514 | ||
1515 | /* Macros for decoding instructions. | |
1516 | ||
1517 | Remember that 16-bit instructions are placed in bits 16..31 of i, | |
1518 | not at the least significant end; this means that the major opcode | |
1519 | field is always in the same place, regardless of the width of the | |
1520 | instruction. As a reminder of this, we show the lower 16 bits of a | |
1521 | 16-bit instruction as xxxx_xxxx_xxxx_xxxx. */ | |
1522 | ||
1523 | /* SB Rn,(Rm) 0000_nnnn_mmmm_1000 */ | |
1524 | /* SH Rn,(Rm) 0000_nnnn_mmmm_1001 */ | |
1525 | /* SW Rn,(Rm) 0000_nnnn_mmmm_1010 */ | |
1526 | ||
1527 | /* SW Rn,disp16(Rm) 1100_nnnn_mmmm_1010 dddd_dddd_dddd_dddd */ | |
1528 | #define IS_SW(i) (((i) & 0xf00f0000) == 0xc00a0000) | |
1529 | /* SB Rn,disp16(Rm) 1100_nnnn_mmmm_1000 dddd_dddd_dddd_dddd */ | |
1530 | #define IS_SB(i) (((i) & 0xf00f0000) == 0xc0080000) | |
1531 | /* SH Rn,disp16(Rm) 1100_nnnn_mmmm_1001 dddd_dddd_dddd_dddd */ | |
1532 | #define IS_SH(i) (((i) & 0xf00f0000) == 0xc0090000) | |
1533 | #define SWBH_32_BASE(i) (FIELD (i, 20, 4)) | |
1534 | #define SWBH_32_SOURCE(i) (FIELD (i, 24, 4)) | |
1535 | #define SWBH_32_OFFSET(i) (SFIELD (i, 0, 16)) | |
1536 | ||
1537 | /* SW Rn,disp7.align4(SP) 0100_nnnn_0ddd_dd10 xxxx_xxxx_xxxx_xxxx */ | |
1538 | #define IS_SW_IMMD(i) (((i) & 0xf0830000) == 0x40020000) | |
1539 | #define SW_IMMD_SOURCE(i) (FIELD (i, 24, 4)) | |
1540 | #define SW_IMMD_OFFSET(i) (FIELD (i, 18, 5) << 2) | |
1541 | ||
1542 | /* SW Rn,(Rm) 0000_nnnn_mmmm_1010 xxxx_xxxx_xxxx_xxxx */ | |
1543 | #define IS_SW_REG(i) (((i) & 0xf00f0000) == 0x000a0000) | |
1544 | #define SW_REG_SOURCE(i) (FIELD (i, 24, 4)) | |
1545 | #define SW_REG_BASE(i) (FIELD (i, 20, 4)) | |
1546 | ||
1547 | /* ADD3 Rl,Rn,Rm 1001_nnnn_mmmm_llll xxxx_xxxx_xxxx_xxxx */ | |
1548 | #define IS_ADD3_16_REG(i) (((i) & 0xf0000000) == 0x90000000) | |
1549 | #define ADD3_16_REG_SRC1(i) (FIELD (i, 20, 4)) /* n */ | |
1550 | #define ADD3_16_REG_SRC2(i) (FIELD (i, 24, 4)) /* m */ | |
1551 | ||
1552 | /* ADD3 Rn,Rm,imm16 1100_nnnn_mmmm_0000 iiii_iiii_iiii_iiii */ | |
1553 | #define IS_ADD3_32(i) (((i) & 0xf00f0000) == 0xc0000000) | |
1554 | #define ADD3_32_TARGET(i) (FIELD (i, 24, 4)) | |
1555 | #define ADD3_32_SOURCE(i) (FIELD (i, 20, 4)) | |
1556 | #define ADD3_32_OFFSET(i) (SFIELD (i, 0, 16)) | |
1557 | ||
1558 | /* ADD3 Rn,SP,imm7.align4 0100_nnnn_0iii_ii00 xxxx_xxxx_xxxx_xxxx */ | |
1559 | #define IS_ADD3_16(i) (((i) & 0xf0830000) == 0x40000000) | |
1560 | #define ADD3_16_TARGET(i) (FIELD (i, 24, 4)) | |
1561 | #define ADD3_16_OFFSET(i) (FIELD (i, 18, 5) << 2) | |
1562 | ||
1563 | /* ADD Rn,imm6 0110_nnnn_iiii_ii00 xxxx_xxxx_xxxx_xxxx */ | |
1564 | #define IS_ADD(i) (((i) & 0xf0030000) == 0x60000000) | |
1565 | #define ADD_TARGET(i) (FIELD (i, 24, 4)) | |
1566 | #define ADD_OFFSET(i) (SFIELD (i, 18, 6)) | |
1567 | ||
1568 | /* LDC Rn,imm5 0111_nnnn_iiii_101I xxxx_xxxx_xxxx_xxxx | |
1569 | imm5 = I||i[7:4] */ | |
1570 | #define IS_LDC(i) (((i) & 0xf00e0000) == 0x700a0000) | |
1571 | #define LDC_IMM(i) ((FIELD (i, 16, 1) << 4) | FIELD (i, 20, 4)) | |
1572 | #define LDC_TARGET(i) (FIELD (i, 24, 4)) | |
1573 | ||
1574 | /* LW Rn,disp16(Rm) 1100_nnnn_mmmm_1110 dddd_dddd_dddd_dddd */ | |
1575 | #define IS_LW(i) (((i) & 0xf00f0000) == 0xc00e0000) | |
1576 | #define LW_TARGET(i) (FIELD (i, 24, 4)) | |
1577 | #define LW_BASE(i) (FIELD (i, 20, 4)) | |
1578 | #define LW_OFFSET(i) (SFIELD (i, 0, 16)) | |
1579 | ||
1580 | /* MOV Rn,Rm 0000_nnnn_mmmm_0000 xxxx_xxxx_xxxx_xxxx */ | |
1581 | #define IS_MOV(i) (((i) & 0xf00f0000) == 0x00000000) | |
1582 | #define MOV_TARGET(i) (FIELD (i, 24, 4)) | |
1583 | #define MOV_SOURCE(i) (FIELD (i, 20, 4)) | |
1584 | ||
1585 | ||
1586 | /* This structure holds the results of a prologue analysis. */ | |
1587 | struct mep_prologue | |
1588 | { | |
1589 | /* The offset from the frame base to the stack pointer --- always | |
1590 | zero or negative. | |
1591 | ||
1592 | Calling this a "size" is a bit misleading, but given that the | |
1593 | stack grows downwards, using offsets for everything keeps one | |
1594 | from going completely sign-crazy: you never change anything's | |
1595 | sign for an ADD instruction; always change the second operand's | |
1596 | sign for a SUB instruction; and everything takes care of | |
1597 | itself. */ | |
1598 | int frame_size; | |
1599 | ||
1600 | /* Non-zero if this function has initialized the frame pointer from | |
1601 | the stack pointer, zero otherwise. */ | |
1602 | int has_frame_ptr; | |
1603 | ||
1604 | /* If has_frame_ptr is non-zero, this is the offset from the frame | |
1605 | base to where the frame pointer points. This is always zero or | |
1606 | negative. */ | |
1607 | int frame_ptr_offset; | |
1608 | ||
1609 | /* The address of the first instruction at which the frame has been | |
1610 | set up and the arguments are where the debug info says they are | |
1611 | --- as best as we can tell. */ | |
1612 | CORE_ADDR prologue_end; | |
1613 | ||
1614 | /* reg_offset[R] is the offset from the CFA at which register R is | |
1615 | saved, or 1 if register R has not been saved. (Real values are | |
1616 | always zero or negative.) */ | |
1617 | int reg_offset[MEP_NUM_REGS]; | |
1618 | }; | |
1619 | ||
1620 | /* Return non-zero if VALUE is an incoming argument register. */ | |
1621 | ||
1622 | static int | |
1623 | is_arg_reg (pv_t value) | |
1624 | { | |
1625 | return (value.kind == pvk_register | |
1626 | && MEP_R1_REGNUM <= value.reg && value.reg <= MEP_R4_REGNUM | |
1627 | && value.k == 0); | |
1628 | } | |
1629 | ||
1630 | /* Return non-zero if a store of REG's current value VALUE to ADDR is | |
1631 | probably spilling an argument register to its stack slot in STACK. | |
1632 | Such instructions should be included in the prologue, if possible. | |
1633 | ||
1634 | The store is a spill if: | |
1635 | - the value being stored is REG's original value; | |
1636 | - the value has not already been stored somewhere in STACK; and | |
1637 | - ADDR is a stack slot's address (e.g., relative to the original | |
1638 | value of the SP). */ | |
1639 | static int | |
1640 | is_arg_spill (pv_t value, pv_t addr, struct pv_area *stack) | |
1641 | { | |
1642 | return (is_arg_reg (value) | |
1643 | && pv_is_register (addr, MEP_SP_REGNUM) | |
1644 | && ! pv_area_find_reg (stack, current_gdbarch, value.reg, 0)); | |
1645 | } | |
1646 | ||
1647 | ||
1648 | /* Function for finding saved registers in a 'struct pv_area'; we pass | |
1649 | this to pv_area_scan. | |
1650 | ||
1651 | If VALUE is a saved register, ADDR says it was saved at a constant | |
1652 | offset from the frame base, and SIZE indicates that the whole | |
1653 | register was saved, record its offset in RESULT_UNTYPED. */ | |
1654 | static void | |
1655 | check_for_saved (void *result_untyped, pv_t addr, CORE_ADDR size, pv_t value) | |
1656 | { | |
1657 | struct mep_prologue *result = (struct mep_prologue *) result_untyped; | |
1658 | ||
1659 | if (value.kind == pvk_register | |
1660 | && value.k == 0 | |
1661 | && pv_is_register (addr, MEP_SP_REGNUM) | |
1662 | && size == register_size (current_gdbarch, value.reg)) | |
1663 | result->reg_offset[value.reg] = addr.k; | |
1664 | } | |
1665 | ||
1666 | ||
1667 | /* Analyze a prologue starting at START_PC, going no further than | |
1668 | LIMIT_PC. Fill in RESULT as appropriate. */ | |
1669 | static void | |
1670 | mep_analyze_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
1671 | struct mep_prologue *result) | |
1672 | { | |
1673 | CORE_ADDR pc; | |
1674 | unsigned long insn; | |
1675 | int rn; | |
1676 | int found_lp = 0; | |
1677 | pv_t reg[MEP_NUM_REGS]; | |
1678 | struct pv_area *stack; | |
1679 | struct cleanup *back_to; | |
1680 | CORE_ADDR after_last_frame_setup_insn = start_pc; | |
1681 | ||
1682 | memset (result, 0, sizeof (*result)); | |
1683 | ||
1684 | for (rn = 0; rn < MEP_NUM_REGS; rn++) | |
1685 | { | |
1686 | reg[rn] = pv_register (rn, 0); | |
1687 | result->reg_offset[rn] = 1; | |
1688 | } | |
1689 | ||
1690 | stack = make_pv_area (MEP_SP_REGNUM); | |
1691 | back_to = make_cleanup_free_pv_area (stack); | |
1692 | ||
1693 | pc = start_pc; | |
1694 | while (pc < limit_pc) | |
1695 | { | |
1696 | CORE_ADDR next_pc; | |
1697 | pv_t pre_insn_fp, pre_insn_sp; | |
1698 | ||
1699 | next_pc = mep_get_insn (pc, &insn); | |
1700 | ||
1701 | /* A zero return from mep_get_insn means that either we weren't | |
1702 | able to read the instruction from memory, or that we don't | |
1703 | have enough information to be able to reliably decode it. So | |
1704 | we'll store here and hope for the best. */ | |
1705 | if (! next_pc) | |
1706 | break; | |
1707 | ||
1708 | /* Note the current values of the SP and FP, so we can tell if | |
1709 | this instruction changed them, below. */ | |
1710 | pre_insn_fp = reg[MEP_FP_REGNUM]; | |
1711 | pre_insn_sp = reg[MEP_SP_REGNUM]; | |
1712 | ||
1713 | if (IS_ADD (insn)) | |
1714 | { | |
1715 | int rn = ADD_TARGET (insn); | |
1716 | CORE_ADDR imm6 = ADD_OFFSET (insn); | |
1717 | ||
1718 | reg[rn] = pv_add_constant (reg[rn], imm6); | |
1719 | } | |
1720 | else if (IS_ADD3_16 (insn)) | |
1721 | { | |
1722 | int rn = ADD3_16_TARGET (insn); | |
1723 | int imm7 = ADD3_16_OFFSET (insn); | |
1724 | ||
1725 | reg[rn] = pv_add_constant (reg[MEP_SP_REGNUM], imm7); | |
1726 | } | |
1727 | else if (IS_ADD3_32 (insn)) | |
1728 | { | |
1729 | int rn = ADD3_32_TARGET (insn); | |
1730 | int rm = ADD3_32_SOURCE (insn); | |
1731 | int imm16 = ADD3_32_OFFSET (insn); | |
1732 | ||
1733 | reg[rn] = pv_add_constant (reg[rm], imm16); | |
1734 | } | |
1735 | else if (IS_SW_REG (insn)) | |
1736 | { | |
1737 | int rn = SW_REG_SOURCE (insn); | |
1738 | int rm = SW_REG_BASE (insn); | |
1739 | ||
1740 | /* If simulating this store would require us to forget | |
1741 | everything we know about the stack frame in the name of | |
1742 | accuracy, it would be better to just quit now. */ | |
1743 | if (pv_area_store_would_trash (stack, reg[rm])) | |
1744 | break; | |
1745 | ||
1746 | if (is_arg_spill (reg[rn], reg[rm], stack)) | |
1747 | after_last_frame_setup_insn = next_pc; | |
1748 | ||
1749 | pv_area_store (stack, reg[rm], 4, reg[rn]); | |
1750 | } | |
1751 | else if (IS_SW_IMMD (insn)) | |
1752 | { | |
1753 | int rn = SW_IMMD_SOURCE (insn); | |
1754 | int offset = SW_IMMD_OFFSET (insn); | |
1755 | pv_t addr = pv_add_constant (reg[MEP_SP_REGNUM], offset); | |
1756 | ||
1757 | /* If simulating this store would require us to forget | |
1758 | everything we know about the stack frame in the name of | |
1759 | accuracy, it would be better to just quit now. */ | |
1760 | if (pv_area_store_would_trash (stack, addr)) | |
1761 | break; | |
1762 | ||
1763 | if (is_arg_spill (reg[rn], addr, stack)) | |
1764 | after_last_frame_setup_insn = next_pc; | |
1765 | ||
1766 | pv_area_store (stack, addr, 4, reg[rn]); | |
1767 | } | |
1768 | else if (IS_MOV (insn)) | |
1769 | { | |
1770 | int rn = MOV_TARGET (insn); | |
1771 | int rm = MOV_SOURCE (insn); | |
1772 | ||
1773 | reg[rn] = reg[rm]; | |
1774 | ||
1775 | if (pv_is_register (reg[rm], rm) && is_arg_reg (reg[rm])) | |
1776 | after_last_frame_setup_insn = next_pc; | |
1777 | } | |
1778 | else if (IS_SB (insn) || IS_SH (insn) || IS_SW (insn)) | |
1779 | { | |
1780 | int rn = SWBH_32_SOURCE (insn); | |
1781 | int rm = SWBH_32_BASE (insn); | |
1782 | int disp = SWBH_32_OFFSET (insn); | |
1783 | int size = (IS_SB (insn) ? 1 | |
1784 | : IS_SH (insn) ? 2 | |
1785 | : IS_SW (insn) ? 4 | |
1786 | : (gdb_assert (0), 1)); | |
1787 | pv_t addr = pv_add_constant (reg[rm], disp); | |
1788 | ||
1789 | if (pv_area_store_would_trash (stack, addr)) | |
1790 | break; | |
1791 | ||
1792 | if (is_arg_spill (reg[rn], addr, stack)) | |
1793 | after_last_frame_setup_insn = next_pc; | |
1794 | ||
1795 | pv_area_store (stack, addr, size, reg[rn]); | |
1796 | } | |
1797 | else if (IS_LDC (insn)) | |
1798 | { | |
1799 | int rn = LDC_TARGET (insn); | |
1800 | int cr = LDC_IMM (insn) + MEP_FIRST_CSR_REGNUM; | |
1801 | ||
1802 | reg[rn] = reg[cr]; | |
1803 | } | |
1804 | else if (IS_LW (insn)) | |
1805 | { | |
1806 | int rn = LW_TARGET (insn); | |
1807 | int rm = LW_BASE (insn); | |
1808 | int offset = LW_OFFSET (insn); | |
1809 | pv_t addr = pv_add_constant (reg[rm], offset); | |
1810 | ||
1811 | reg[rn] = pv_area_fetch (stack, addr, 4); | |
1812 | } | |
1813 | else | |
1814 | /* We've hit some instruction we don't know how to simulate. | |
1815 | Strictly speaking, we should set every value we're | |
1816 | tracking to "unknown". But we'll be optimistic, assume | |
1817 | that we have enough information already, and stop | |
1818 | analysis here. */ | |
1819 | break; | |
1820 | ||
1821 | /* If this instruction changed the FP or decreased the SP (i.e., | |
1822 | allocated more stack space), then this may be a good place to | |
1823 | declare the prologue finished. However, there are some | |
1824 | exceptions: | |
1825 | ||
1826 | - If the instruction just changed the FP back to its original | |
1827 | value, then that's probably a restore instruction. The | |
1828 | prologue should definitely end before that. | |
1829 | ||
1830 | - If the instruction increased the value of the SP (that is, | |
1831 | shrunk the frame), then it's probably part of a frame | |
1832 | teardown sequence, and the prologue should end before that. */ | |
1833 | ||
1834 | if (! pv_is_identical (reg[MEP_FP_REGNUM], pre_insn_fp)) | |
1835 | { | |
1836 | if (! pv_is_register_k (reg[MEP_FP_REGNUM], MEP_FP_REGNUM, 0)) | |
1837 | after_last_frame_setup_insn = next_pc; | |
1838 | } | |
1839 | else if (! pv_is_identical (reg[MEP_SP_REGNUM], pre_insn_sp)) | |
1840 | { | |
1841 | /* The comparison of constants looks odd, there, because .k | |
1842 | is unsigned. All it really means is that the new value | |
1843 | is lower than it was before the instruction. */ | |
1844 | if (pv_is_register (pre_insn_sp, MEP_SP_REGNUM) | |
1845 | && pv_is_register (reg[MEP_SP_REGNUM], MEP_SP_REGNUM) | |
1846 | && ((pre_insn_sp.k - reg[MEP_SP_REGNUM].k) | |
1847 | < (reg[MEP_SP_REGNUM].k - pre_insn_sp.k))) | |
1848 | after_last_frame_setup_insn = next_pc; | |
1849 | } | |
1850 | ||
1851 | pc = next_pc; | |
1852 | } | |
1853 | ||
1854 | /* Is the frame size (offset, really) a known constant? */ | |
1855 | if (pv_is_register (reg[MEP_SP_REGNUM], MEP_SP_REGNUM)) | |
1856 | result->frame_size = reg[MEP_SP_REGNUM].k; | |
1857 | ||
1858 | /* Was the frame pointer initialized? */ | |
1859 | if (pv_is_register (reg[MEP_FP_REGNUM], MEP_SP_REGNUM)) | |
1860 | { | |
1861 | result->has_frame_ptr = 1; | |
1862 | result->frame_ptr_offset = reg[MEP_FP_REGNUM].k; | |
1863 | } | |
1864 | ||
1865 | /* Record where all the registers were saved. */ | |
1866 | pv_area_scan (stack, check_for_saved, (void *) result); | |
1867 | ||
1868 | result->prologue_end = after_last_frame_setup_insn; | |
1869 | ||
1870 | do_cleanups (back_to); | |
1871 | } | |
1872 | ||
1873 | ||
1874 | static CORE_ADDR | |
1875 | mep_skip_prologue (CORE_ADDR pc) | |
1876 | { | |
1877 | char *name; | |
1878 | CORE_ADDR func_addr, func_end; | |
1879 | struct mep_prologue p; | |
1880 | ||
1881 | /* Try to find the extent of the function that contains PC. */ | |
1882 | if (! find_pc_partial_function (pc, &name, &func_addr, &func_end)) | |
1883 | return pc; | |
1884 | ||
1885 | mep_analyze_prologue (pc, func_end, &p); | |
1886 | return p.prologue_end; | |
1887 | } | |
1888 | ||
1889 | ||
1890 | \f | |
1891 | /* Breakpoints. */ | |
1892 | ||
1893 | static const unsigned char * | |
1894 | mep_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr) | |
1895 | { | |
1896 | static unsigned char breakpoint[] = { 0x70, 0x32 }; | |
1897 | *lenptr = sizeof (breakpoint); | |
1898 | return breakpoint; | |
1899 | } | |
1900 | ||
1901 | ||
1902 | \f | |
1903 | /* Frames and frame unwinding. */ | |
1904 | ||
1905 | ||
1906 | static struct mep_prologue * | |
1907 | mep_analyze_frame_prologue (struct frame_info *next_frame, | |
1908 | void **this_prologue_cache) | |
1909 | { | |
1910 | if (! *this_prologue_cache) | |
1911 | { | |
1912 | CORE_ADDR func_start, stop_addr; | |
1913 | ||
1914 | *this_prologue_cache | |
1915 | = FRAME_OBSTACK_ZALLOC (struct mep_prologue); | |
1916 | ||
1c86fa97 | 1917 | func_start = frame_func_unwind (next_frame, NORMAL_FRAME); |
aeb43123 KB |
1918 | stop_addr = frame_pc_unwind (next_frame); |
1919 | ||
1920 | /* If we couldn't find any function containing the PC, then | |
1921 | just initialize the prologue cache, but don't do anything. */ | |
1922 | if (! func_start) | |
1923 | stop_addr = func_start; | |
1924 | ||
1925 | mep_analyze_prologue (func_start, stop_addr, *this_prologue_cache); | |
1926 | } | |
1927 | ||
1928 | return *this_prologue_cache; | |
1929 | } | |
1930 | ||
1931 | ||
1932 | /* Given the next frame and a prologue cache, return this frame's | |
1933 | base. */ | |
1934 | static CORE_ADDR | |
1935 | mep_frame_base (struct frame_info *next_frame, | |
1936 | void **this_prologue_cache) | |
1937 | { | |
1938 | struct mep_prologue *p | |
1939 | = mep_analyze_frame_prologue (next_frame, this_prologue_cache); | |
1940 | ||
1941 | /* In functions that use alloca, the distance between the stack | |
1942 | pointer and the frame base varies dynamically, so we can't use | |
1943 | the SP plus static information like prologue analysis to find the | |
1944 | frame base. However, such functions must have a frame pointer, | |
1945 | to be able to restore the SP on exit. So whenever we do have a | |
1946 | frame pointer, use that to find the base. */ | |
1947 | if (p->has_frame_ptr) | |
1948 | { | |
1949 | CORE_ADDR fp | |
1950 | = frame_unwind_register_unsigned (next_frame, MEP_FP_REGNUM); | |
1951 | return fp - p->frame_ptr_offset; | |
1952 | } | |
1953 | else | |
1954 | { | |
1955 | CORE_ADDR sp | |
1956 | = frame_unwind_register_unsigned (next_frame, MEP_SP_REGNUM); | |
1957 | return sp - p->frame_size; | |
1958 | } | |
1959 | } | |
1960 | ||
1961 | ||
1962 | static void | |
1963 | mep_frame_this_id (struct frame_info *next_frame, | |
1964 | void **this_prologue_cache, | |
1965 | struct frame_id *this_id) | |
1966 | { | |
1967 | *this_id = frame_id_build (mep_frame_base (next_frame, this_prologue_cache), | |
1c86fa97 | 1968 | frame_func_unwind (next_frame, NORMAL_FRAME)); |
aeb43123 KB |
1969 | } |
1970 | ||
1971 | ||
1972 | static void | |
1973 | mep_frame_prev_register (struct frame_info *next_frame, | |
1974 | void **this_prologue_cache, | |
1975 | int regnum, int *optimizedp, | |
1976 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1977 | int *realnump, gdb_byte *bufferp) | |
1978 | { | |
1979 | struct mep_prologue *p | |
1980 | = mep_analyze_frame_prologue (next_frame, this_prologue_cache); | |
1981 | ||
1982 | /* There are a number of complications in unwinding registers on the | |
1983 | MeP, having to do with core functions calling VLIW functions and | |
1984 | vice versa. | |
1985 | ||
1986 | The least significant bit of the link register, LP.LTOM, is the | |
1987 | VLIW mode toggle bit: it's set if a core function called a VLIW | |
1988 | function, or vice versa, and clear when the caller and callee | |
1989 | were both in the same mode. | |
1990 | ||
1991 | So, if we're asked to unwind the PC, then we really want to | |
1992 | unwind the LP and clear the least significant bit. (Real return | |
1993 | addresses are always even.) And if we want to unwind the program | |
1994 | status word (PSW), we need to toggle PSW.OM if LP.LTOM is set. | |
1995 | ||
1996 | Tweaking the register values we return in this way means that the | |
1997 | bits in BUFFERP[] are not the same as the bits you'd find at | |
1998 | ADDRP in the inferior, so we make sure lvalp is not_lval when we | |
1999 | do this. */ | |
2000 | if (regnum == MEP_PC_REGNUM) | |
2001 | { | |
2002 | mep_frame_prev_register (next_frame, this_prologue_cache, MEP_LP_REGNUM, | |
2003 | optimizedp, lvalp, addrp, realnump, bufferp); | |
2004 | store_unsigned_integer (bufferp, MEP_LP_SIZE, | |
2005 | (extract_unsigned_integer (bufferp, MEP_LP_SIZE) | |
2006 | & ~1)); | |
2007 | *lvalp = not_lval; | |
2008 | } | |
2009 | else | |
2010 | { | |
2011 | CORE_ADDR frame_base = mep_frame_base (next_frame, this_prologue_cache); | |
2012 | int reg_size = register_size (get_frame_arch (next_frame), regnum); | |
2013 | ||
2014 | /* Our caller's SP is our frame base. */ | |
2015 | if (regnum == MEP_SP_REGNUM) | |
2016 | { | |
2017 | *optimizedp = 0; | |
2018 | *lvalp = not_lval; | |
2019 | *addrp = 0; | |
2020 | *realnump = -1; | |
2021 | if (bufferp) | |
2022 | store_unsigned_integer (bufferp, reg_size, frame_base); | |
2023 | } | |
2024 | ||
2025 | /* If prologue analysis says we saved this register somewhere, | |
2026 | return a description of the stack slot holding it. */ | |
2027 | else if (p->reg_offset[regnum] != 1) | |
2028 | { | |
2029 | *optimizedp = 0; | |
2030 | *lvalp = lval_memory; | |
2031 | *addrp = frame_base + p->reg_offset[regnum]; | |
2032 | *realnump = -1; | |
2033 | if (bufferp) | |
2034 | get_frame_memory (next_frame, *addrp, bufferp, reg_size); | |
2035 | } | |
2036 | ||
2037 | /* Otherwise, presume we haven't changed the value of this | |
2038 | register, and get it from the next frame. */ | |
2039 | else | |
2040 | frame_register_unwind (next_frame, regnum, | |
2041 | optimizedp, lvalp, addrp, realnump, bufferp); | |
2042 | ||
2043 | /* If we need to toggle the operating mode, do so. */ | |
2044 | if (regnum == MEP_PSW_REGNUM) | |
2045 | { | |
2046 | int lp_optimized; | |
2047 | enum lval_type lp_lval; | |
2048 | CORE_ADDR lp_addr; | |
2049 | int lp_realnum; | |
2050 | char lp_buffer[MEP_LP_SIZE]; | |
2051 | ||
2052 | /* Get the LP's value, too. */ | |
2053 | frame_register_unwind (next_frame, MEP_LP_REGNUM, | |
2054 | &lp_optimized, &lp_lval, &lp_addr, | |
2055 | &lp_realnum, lp_buffer); | |
2056 | ||
2057 | /* If LP.LTOM is set, then toggle PSW.OM. */ | |
2058 | if (extract_unsigned_integer (lp_buffer, MEP_LP_SIZE) & 0x1) | |
2059 | store_unsigned_integer | |
2060 | (bufferp, MEP_PSW_SIZE, | |
2061 | (extract_unsigned_integer (bufferp, MEP_PSW_SIZE) ^ 0x1000)); | |
2062 | *lvalp = not_lval; | |
2063 | } | |
2064 | } | |
2065 | } | |
2066 | ||
2067 | ||
2068 | static const struct frame_unwind mep_frame_unwind = { | |
2069 | NORMAL_FRAME, | |
2070 | mep_frame_this_id, | |
2071 | mep_frame_prev_register | |
2072 | }; | |
2073 | ||
2074 | ||
2075 | static const struct frame_unwind * | |
2076 | mep_frame_sniffer (struct frame_info *next_frame) | |
2077 | { | |
2078 | return &mep_frame_unwind; | |
2079 | } | |
2080 | ||
2081 | ||
2082 | /* Our general unwinding function can handle unwinding the PC. */ | |
2083 | static CORE_ADDR | |
2084 | mep_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2085 | { | |
2086 | return frame_unwind_register_unsigned (next_frame, MEP_PC_REGNUM); | |
2087 | } | |
2088 | ||
2089 | ||
2090 | /* Our general unwinding function can handle unwinding the SP. */ | |
2091 | static CORE_ADDR | |
2092 | mep_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2093 | { | |
2094 | return frame_unwind_register_unsigned (next_frame, MEP_SP_REGNUM); | |
2095 | } | |
2096 | ||
2097 | ||
2098 | \f | |
2099 | /* Return values. */ | |
2100 | ||
2101 | ||
2102 | static int | |
2103 | mep_use_struct_convention (struct type *type) | |
2104 | { | |
2105 | return (TYPE_LENGTH (type) > MEP_GPR_SIZE); | |
2106 | } | |
2107 | ||
2108 | ||
2109 | static void | |
2110 | mep_extract_return_value (struct gdbarch *arch, | |
2111 | struct type *type, | |
2112 | struct regcache *regcache, | |
2113 | gdb_byte *valbuf) | |
2114 | { | |
2115 | int byte_order = gdbarch_byte_order (arch); | |
2116 | ||
2117 | /* Values that don't occupy a full register appear at the less | |
2118 | significant end of the value. This is the offset to where the | |
2119 | value starts. */ | |
2120 | int offset; | |
2121 | ||
2122 | /* Return values > MEP_GPR_SIZE bytes are returned in memory, | |
2123 | pointed to by R0. */ | |
2124 | gdb_assert (TYPE_LENGTH (type) <= MEP_GPR_SIZE); | |
2125 | ||
2126 | if (byte_order == BFD_ENDIAN_BIG) | |
2127 | offset = MEP_GPR_SIZE - TYPE_LENGTH (type); | |
2128 | else | |
2129 | offset = 0; | |
2130 | ||
2131 | /* Return values that do fit in a single register are returned in R0. */ | |
2132 | regcache_cooked_read_part (regcache, MEP_R0_REGNUM, | |
2133 | offset, TYPE_LENGTH (type), | |
2134 | valbuf); | |
2135 | } | |
2136 | ||
2137 | ||
2138 | static void | |
2139 | mep_store_return_value (struct gdbarch *arch, | |
2140 | struct type *type, | |
2141 | struct regcache *regcache, | |
2142 | const gdb_byte *valbuf) | |
2143 | { | |
2144 | int byte_order = gdbarch_byte_order (arch); | |
2145 | ||
2146 | /* Values that fit in a single register go in R0. */ | |
2147 | if (TYPE_LENGTH (type) <= MEP_GPR_SIZE) | |
2148 | { | |
2149 | /* Values that don't occupy a full register appear at the least | |
2150 | significant end of the value. This is the offset to where the | |
2151 | value starts. */ | |
2152 | int offset; | |
2153 | ||
2154 | if (byte_order == BFD_ENDIAN_BIG) | |
2155 | offset = MEP_GPR_SIZE - TYPE_LENGTH (type); | |
2156 | else | |
2157 | offset = 0; | |
2158 | ||
2159 | regcache_cooked_write_part (regcache, MEP_R0_REGNUM, | |
2160 | offset, TYPE_LENGTH (type), | |
2161 | valbuf); | |
2162 | } | |
2163 | ||
2164 | /* Return values larger than a single register are returned in | |
2165 | memory, pointed to by R0. Unfortunately, we can't count on R0 | |
2166 | pointing to the return buffer, so we raise an error here. */ | |
2167 | else | |
2168 | error ("GDB cannot set return values larger than four bytes; " | |
2169 | "the Media Processor's\n" | |
2170 | "calling conventions do not provide enough information " | |
2171 | "to do this.\n" | |
2172 | "Try using the 'return' command with no argument."); | |
2173 | } | |
2174 | ||
2175 | enum return_value_convention | |
2176 | mep_return_value (struct gdbarch *gdbarch, struct type *type, | |
2177 | struct regcache *regcache, gdb_byte *readbuf, | |
2178 | const gdb_byte *writebuf) | |
2179 | { | |
2180 | if (mep_use_struct_convention (type)) | |
2181 | { | |
2182 | if (readbuf) | |
2183 | { | |
2184 | ULONGEST addr; | |
2185 | /* Although the address of the struct buffer gets passed in R1, it's | |
2186 | returned in R0. Fetch R0's value and then read the memory | |
2187 | at that address. */ | |
2188 | regcache_raw_read_unsigned (regcache, MEP_R0_REGNUM, &addr); | |
2189 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
2190 | } | |
2191 | if (writebuf) | |
2192 | { | |
2193 | /* Return values larger than a single register are returned in | |
2194 | memory, pointed to by R0. Unfortunately, we can't count on R0 | |
2195 | pointing to the return buffer, so we raise an error here. */ | |
2196 | error ("GDB cannot set return values larger than four bytes; " | |
2197 | "the Media Processor's\n" | |
2198 | "calling conventions do not provide enough information " | |
2199 | "to do this.\n" | |
2200 | "Try using the 'return' command with no argument."); | |
2201 | } | |
2202 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
2203 | } | |
2204 | ||
2205 | if (readbuf) | |
2206 | mep_extract_return_value (gdbarch, type, regcache, readbuf); | |
2207 | if (writebuf) | |
2208 | mep_store_return_value (gdbarch, type, regcache, writebuf); | |
2209 | ||
2210 | return RETURN_VALUE_REGISTER_CONVENTION; | |
2211 | } | |
2212 | ||
2213 | \f | |
2214 | /* Inferior calls. */ | |
2215 | ||
2216 | ||
2217 | static CORE_ADDR | |
2218 | mep_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
2219 | { | |
2220 | /* Require word alignment. */ | |
2221 | return sp & -4; | |
2222 | } | |
2223 | ||
2224 | ||
2225 | /* From "lang_spec2.txt": | |
2226 | ||
2227 | 4.2 Calling conventions | |
2228 | ||
2229 | 4.2.1 Core register conventions | |
2230 | ||
2231 | - Parameters should be evaluated from left to right, and they | |
2232 | should be held in $1,$2,$3,$4 in order. The fifth parameter or | |
2233 | after should be held in the stack. If the size is larger than 4 | |
2234 | bytes in the first four parameters, the pointer should be held in | |
2235 | the registers instead. If the size is larger than 4 bytes in the | |
2236 | fifth parameter or after, the pointer should be held in the stack. | |
2237 | ||
2238 | - Return value of a function should be held in register $0. If the | |
2239 | size of return value is larger than 4 bytes, $1 should hold the | |
2240 | pointer pointing memory that would hold the return value. In this | |
2241 | case, the first parameter should be held in $2, the second one in | |
2242 | $3, and the third one in $4, and the forth parameter or after | |
2243 | should be held in the stack. | |
2244 | ||
2245 | [This doesn't say so, but arguments shorter than four bytes are | |
2246 | passed in the least significant end of a four-byte word when | |
2247 | they're passed on the stack.] */ | |
2248 | ||
2249 | ||
2250 | /* Traverse the list of ARGC arguments ARGV; for every ARGV[i] too | |
2251 | large to fit in a register, save it on the stack, and place its | |
2252 | address in COPY[i]. SP is the initial stack pointer; return the | |
2253 | new stack pointer. */ | |
2254 | static CORE_ADDR | |
2255 | push_large_arguments (CORE_ADDR sp, int argc, struct value **argv, | |
2256 | CORE_ADDR copy[]) | |
2257 | { | |
2258 | int i; | |
2259 | ||
2260 | for (i = 0; i < argc; i++) | |
2261 | { | |
2262 | unsigned arg_len = TYPE_LENGTH (value_type (argv[i])); | |
2263 | ||
2264 | if (arg_len > MEP_GPR_SIZE) | |
2265 | { | |
2266 | /* Reserve space for the copy, and then round the SP down, to | |
2267 | make sure it's all aligned properly. */ | |
2268 | sp = (sp - arg_len) & -4; | |
2269 | write_memory (sp, value_contents (argv[i]), arg_len); | |
2270 | copy[i] = sp; | |
2271 | } | |
2272 | } | |
2273 | ||
2274 | return sp; | |
2275 | } | |
2276 | ||
2277 | ||
2278 | static CORE_ADDR | |
2279 | mep_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | |
2280 | struct regcache *regcache, CORE_ADDR bp_addr, | |
2281 | int argc, struct value **argv, CORE_ADDR sp, | |
2282 | int struct_return, | |
2283 | CORE_ADDR struct_addr) | |
2284 | { | |
2285 | CORE_ADDR *copy = (CORE_ADDR *) alloca (argc * sizeof (copy[0])); | |
2286 | CORE_ADDR func_addr = find_function_addr (function, NULL); | |
2287 | int i; | |
2288 | ||
2289 | /* The number of the next register available to hold an argument. */ | |
2290 | int arg_reg; | |
2291 | ||
2292 | /* The address of the next stack slot available to hold an argument. */ | |
2293 | CORE_ADDR arg_stack; | |
2294 | ||
2295 | /* The address of the end of the stack area for arguments. This is | |
2296 | just for error checking. */ | |
2297 | CORE_ADDR arg_stack_end; | |
2298 | ||
2299 | sp = push_large_arguments (sp, argc, argv, copy); | |
2300 | ||
2301 | /* Reserve space for the stack arguments, if any. */ | |
2302 | arg_stack_end = sp; | |
2303 | if (argc + (struct_addr ? 1 : 0) > 4) | |
2304 | sp -= ((argc + (struct_addr ? 1 : 0)) - 4) * MEP_GPR_SIZE; | |
2305 | ||
2306 | arg_reg = MEP_R1_REGNUM; | |
2307 | arg_stack = sp; | |
2308 | ||
2309 | /* If we're returning a structure by value, push the pointer to the | |
2310 | buffer as the first argument. */ | |
2311 | if (struct_return) | |
2312 | { | |
2313 | regcache_cooked_write_unsigned (regcache, arg_reg, struct_addr); | |
2314 | arg_reg++; | |
2315 | } | |
2316 | ||
2317 | for (i = 0; i < argc; i++) | |
2318 | { | |
2319 | unsigned arg_size = TYPE_LENGTH (value_type (argv[i])); | |
2320 | ULONGEST value; | |
2321 | ||
2322 | /* Arguments that fit in a GPR get expanded to fill the GPR. */ | |
2323 | if (arg_size <= MEP_GPR_SIZE) | |
2324 | value = extract_unsigned_integer (value_contents (argv[i]), | |
2325 | TYPE_LENGTH (value_type (argv[i]))); | |
2326 | ||
2327 | /* Arguments too large to fit in a GPR get copied to the stack, | |
2328 | and we pass a pointer to the copy. */ | |
2329 | else | |
2330 | value = copy[i]; | |
2331 | ||
2332 | /* We use $1 -- $4 for passing arguments, then use the stack. */ | |
2333 | if (arg_reg <= MEP_R4_REGNUM) | |
2334 | { | |
2335 | regcache_cooked_write_unsigned (regcache, arg_reg, value); | |
2336 | arg_reg++; | |
2337 | } | |
2338 | else | |
2339 | { | |
2340 | char buf[MEP_GPR_SIZE]; | |
2341 | store_unsigned_integer (buf, MEP_GPR_SIZE, value); | |
2342 | write_memory (arg_stack, buf, MEP_GPR_SIZE); | |
2343 | arg_stack += MEP_GPR_SIZE; | |
2344 | } | |
2345 | } | |
2346 | ||
2347 | gdb_assert (arg_stack <= arg_stack_end); | |
2348 | ||
2349 | /* Set the return address. */ | |
2350 | regcache_cooked_write_unsigned (regcache, MEP_LP_REGNUM, bp_addr); | |
2351 | ||
2352 | /* Update the stack pointer. */ | |
2353 | regcache_cooked_write_unsigned (regcache, MEP_SP_REGNUM, sp); | |
2354 | ||
2355 | return sp; | |
2356 | } | |
2357 | ||
2358 | ||
2359 | static struct frame_id | |
2360 | mep_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2361 | { | |
2362 | return frame_id_build (mep_unwind_sp (gdbarch, next_frame), | |
2363 | frame_pc_unwind (next_frame)); | |
2364 | } | |
2365 | ||
2366 | ||
2367 | \f | |
2368 | /* Initialization. */ | |
2369 | ||
2370 | ||
2371 | static struct gdbarch * | |
2372 | mep_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2373 | { | |
2374 | struct gdbarch *gdbarch; | |
2375 | struct gdbarch_tdep *tdep; | |
2376 | ||
2377 | /* Which me_module are we building a gdbarch object for? */ | |
2378 | CONFIG_ATTR me_module; | |
2379 | ||
2380 | /* If we have a BFD in hand, figure out which me_module it was built | |
2381 | for. Otherwise, use the no-particular-me_module code. */ | |
2382 | if (info.abfd) | |
2383 | { | |
2384 | /* The way to get the me_module code depends on the object file | |
2385 | format. At the moment, we only know how to handle ELF. */ | |
2386 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
2387 | me_module = elf_elfheader (info.abfd)->e_flags & EF_MEP_INDEX_MASK; | |
2388 | else | |
2389 | me_module = CONFIG_NONE; | |
2390 | } | |
2391 | else | |
2392 | me_module = CONFIG_NONE; | |
2393 | ||
2394 | /* If we're setting the architecture from a file, check the | |
2395 | endianness of the file against that of the me_module. */ | |
2396 | if (info.abfd) | |
2397 | { | |
2398 | /* The negations on either side make the comparison treat all | |
2399 | non-zero (true) values as equal. */ | |
2400 | if (! bfd_big_endian (info.abfd) != ! me_module_big_endian (me_module)) | |
2401 | { | |
2402 | const char *module_name = me_module_name (me_module); | |
2403 | const char *module_endianness | |
2404 | = me_module_big_endian (me_module) ? "big" : "little"; | |
2405 | const char *file_name = bfd_get_filename (info.abfd); | |
2406 | const char *file_endianness | |
2407 | = bfd_big_endian (info.abfd) ? "big" : "little"; | |
2408 | ||
2409 | fputc_unfiltered ('\n', gdb_stderr); | |
2410 | if (module_name) | |
2411 | warning ("the MeP module '%s' is %s-endian, but the executable\n" | |
2412 | "%s is %s-endian.", | |
2413 | module_name, module_endianness, | |
2414 | file_name, file_endianness); | |
2415 | else | |
2416 | warning ("the selected MeP module is %s-endian, but the " | |
2417 | "executable\n" | |
2418 | "%s is %s-endian.", | |
2419 | module_endianness, file_name, file_endianness); | |
2420 | } | |
2421 | } | |
2422 | ||
2423 | /* Find a candidate among the list of architectures we've created | |
2424 | already. info->bfd_arch_info needs to match, but we also want | |
2425 | the right me_module: the ELF header's e_flags field needs to | |
2426 | match as well. */ | |
2427 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
2428 | arches != NULL; | |
2429 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
2430 | if (gdbarch_tdep (arches->gdbarch)->me_module == me_module) | |
2431 | return arches->gdbarch; | |
2432 | ||
2433 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); | |
2434 | gdbarch = gdbarch_alloc (&info, tdep); | |
2435 | ||
2436 | /* Get a CGEN CPU descriptor for this architecture. */ | |
2437 | { | |
2438 | const char *mach_name = info.bfd_arch_info->printable_name; | |
2439 | enum cgen_endian endian = (info.byte_order == BFD_ENDIAN_BIG | |
2440 | ? CGEN_ENDIAN_BIG | |
2441 | : CGEN_ENDIAN_LITTLE); | |
2442 | ||
2443 | tdep->cpu_desc = mep_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, | |
2444 | CGEN_CPU_OPEN_ENDIAN, endian, | |
2445 | CGEN_CPU_OPEN_END); | |
2446 | } | |
2447 | ||
2448 | tdep->me_module = me_module; | |
2449 | ||
2450 | /* Register set. */ | |
2451 | set_gdbarch_read_pc (gdbarch, mep_read_pc); | |
2452 | set_gdbarch_write_pc (gdbarch, mep_write_pc); | |
2453 | set_gdbarch_num_regs (gdbarch, MEP_NUM_RAW_REGS); | |
2454 | set_gdbarch_sp_regnum (gdbarch, MEP_SP_REGNUM); | |
2455 | set_gdbarch_register_name (gdbarch, mep_register_name); | |
2456 | set_gdbarch_register_type (gdbarch, mep_register_type); | |
2457 | set_gdbarch_num_pseudo_regs (gdbarch, MEP_NUM_PSEUDO_REGS); | |
2458 | set_gdbarch_pseudo_register_read (gdbarch, mep_pseudo_register_read); | |
2459 | set_gdbarch_pseudo_register_write (gdbarch, mep_pseudo_register_write); | |
2460 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, mep_debug_reg_to_regnum); | |
2461 | set_gdbarch_stab_reg_to_regnum (gdbarch, mep_debug_reg_to_regnum); | |
2462 | ||
2463 | set_gdbarch_register_reggroup_p (gdbarch, mep_register_reggroup_p); | |
2464 | reggroup_add (gdbarch, all_reggroup); | |
2465 | reggroup_add (gdbarch, general_reggroup); | |
2466 | reggroup_add (gdbarch, save_reggroup); | |
2467 | reggroup_add (gdbarch, restore_reggroup); | |
2468 | reggroup_add (gdbarch, mep_csr_reggroup); | |
2469 | reggroup_add (gdbarch, mep_cr_reggroup); | |
2470 | reggroup_add (gdbarch, mep_ccr_reggroup); | |
2471 | ||
2472 | /* Disassembly. */ | |
2473 | set_gdbarch_print_insn (gdbarch, mep_gdb_print_insn); | |
2474 | ||
2475 | /* Breakpoints. */ | |
2476 | set_gdbarch_breakpoint_from_pc (gdbarch, mep_breakpoint_from_pc); | |
2477 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
2478 | set_gdbarch_skip_prologue (gdbarch, mep_skip_prologue); | |
2479 | ||
2480 | /* Frames and frame unwinding. */ | |
2481 | frame_unwind_append_sniffer (gdbarch, mep_frame_sniffer); | |
2482 | set_gdbarch_unwind_pc (gdbarch, mep_unwind_pc); | |
2483 | set_gdbarch_unwind_sp (gdbarch, mep_unwind_sp); | |
2484 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2485 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
2486 | ||
2487 | /* Return values. */ | |
2488 | set_gdbarch_return_value (gdbarch, mep_return_value); | |
2489 | ||
2490 | /* Inferior function calls. */ | |
2491 | set_gdbarch_frame_align (gdbarch, mep_frame_align); | |
2492 | set_gdbarch_push_dummy_call (gdbarch, mep_push_dummy_call); | |
2493 | set_gdbarch_unwind_dummy_id (gdbarch, mep_unwind_dummy_id); | |
2494 | ||
2495 | return gdbarch; | |
2496 | } | |
2497 | ||
2498 | ||
2499 | void | |
2500 | _initialize_mep_tdep (void) | |
2501 | { | |
2502 | mep_csr_reggroup = reggroup_new ("csr", USER_REGGROUP); | |
2503 | mep_cr_reggroup = reggroup_new ("cr", USER_REGGROUP); | |
2504 | mep_ccr_reggroup = reggroup_new ("ccr", USER_REGGROUP); | |
2505 | ||
2506 | register_gdbarch_init (bfd_arch_mep, mep_gdbarch_init); | |
2507 | ||
2508 | mep_init_pseudoregister_maps (); | |
2509 | } |