Commit | Line | Data |
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75c9abc6 | 1 | /* Native-dependent code for GNU/Linux on MIPS processors. |
a094c6fb | 2 | |
7b6bb8da JB |
3 | Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, |
4 | 2011 Free Software Foundation, Inc. | |
2aa830e4 DJ |
5 | |
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 10 | the Free Software Foundation; either version 3 of the License, or |
2aa830e4 DJ |
11 | (at your option) any later version. |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
2aa830e4 DJ |
20 | |
21 | #include "defs.h" | |
b9412953 DD |
22 | #include "command.h" |
23 | #include "gdbcmd.h" | |
24 | #include "gdb_assert.h" | |
d37eb719 | 25 | #include "inferior.h" |
6b753f60 | 26 | #include "mips-tdep.h" |
10d6c8cd | 27 | #include "target.h" |
28f5035f | 28 | #include "regcache.h" |
10d6c8cd | 29 | #include "linux-nat.h" |
d37eb719 | 30 | #include "mips-linux-tdep.h" |
822b6570 | 31 | #include "target-descriptions.h" |
2aa830e4 | 32 | |
dc60ece8 | 33 | #include "gdb_proc_service.h" |
3e00823e | 34 | #include "gregset.h" |
dc60ece8 | 35 | |
822b6570 | 36 | #include <sgidefs.h> |
d37eb719 DJ |
37 | #include <sys/ptrace.h> |
38 | ||
81adfced DJ |
39 | #include "features/mips-linux.c" |
40 | #include "features/mips64-linux.c" | |
41 | ||
dc60ece8 DJ |
42 | #ifndef PTRACE_GET_THREAD_AREA |
43 | #define PTRACE_GET_THREAD_AREA 25 | |
44 | #endif | |
45 | ||
d37eb719 DJ |
46 | /* Assume that we have PTRACE_GETREGS et al. support. If we do not, |
47 | we'll clear this and use PTRACE_PEEKUSER instead. */ | |
48 | static int have_ptrace_regsets = 1; | |
49 | ||
b9412953 DD |
50 | /* Whether or not to print the mirrored debug registers. */ |
51 | ||
52 | static int maint_show_dr; | |
53 | ||
d37eb719 DJ |
54 | /* Saved function pointers to fetch and store a single register using |
55 | PTRACE_PEEKUSER and PTRACE_POKEUSER. */ | |
56 | ||
b9412953 DD |
57 | static void (*super_fetch_registers) (struct target_ops *, |
58 | struct regcache *, int); | |
59 | static void (*super_store_registers) (struct target_ops *, | |
60 | struct regcache *, int); | |
61 | ||
62 | static void (*super_close) (int); | |
d37eb719 | 63 | |
dda0c97e | 64 | /* Map gdb internal register number to ptrace ``address''. |
7714d83a UW |
65 | These ``addresses'' are normally defined in <asm/ptrace.h>. |
66 | ||
67 | ptrace does not provide a way to read (or set) MIPS_PS_REGNUM, | |
68 | and there's no point in reading or setting MIPS_ZERO_REGNUM. | |
69 | We also can not set BADVADDR, CAUSE, or FCRIR via ptrace(). */ | |
dda0c97e UW |
70 | |
71 | static CORE_ADDR | |
7714d83a | 72 | mips_linux_register_addr (struct gdbarch *gdbarch, int regno, int store) |
dda0c97e | 73 | { |
7714d83a | 74 | CORE_ADDR regaddr; |
dda0c97e | 75 | |
2eb4d78b | 76 | if (regno < 0 || regno >= gdbarch_num_regs (gdbarch)) |
dda0c97e UW |
77 | error (_("Bogon register number %d."), regno); |
78 | ||
7714d83a | 79 | if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32) |
dda0c97e | 80 | regaddr = regno; |
7714d83a UW |
81 | else if ((regno >= mips_regnum (gdbarch)->fp0) |
82 | && (regno < mips_regnum (gdbarch)->fp0 + 32)) | |
83 | regaddr = FPR_BASE + (regno - mips_regnum (gdbarch)->fp0); | |
84 | else if (regno == mips_regnum (gdbarch)->pc) | |
dda0c97e | 85 | regaddr = PC; |
7714d83a UW |
86 | else if (regno == mips_regnum (gdbarch)->cause) |
87 | regaddr = store? (CORE_ADDR) -1 : CAUSE; | |
88 | else if (regno == mips_regnum (gdbarch)->badvaddr) | |
89 | regaddr = store? (CORE_ADDR) -1 : BADVADDR; | |
90 | else if (regno == mips_regnum (gdbarch)->lo) | |
dda0c97e | 91 | regaddr = MMLO; |
7714d83a | 92 | else if (regno == mips_regnum (gdbarch)->hi) |
dda0c97e | 93 | regaddr = MMHI; |
7714d83a | 94 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
dda0c97e | 95 | regaddr = FPC_CSR; |
7714d83a UW |
96 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
97 | regaddr = store? (CORE_ADDR) -1 : FPC_EIR; | |
822b6570 DJ |
98 | else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM) |
99 | regaddr = 0; | |
dda0c97e | 100 | else |
7714d83a | 101 | regaddr = (CORE_ADDR) -1; |
dda0c97e UW |
102 | |
103 | return regaddr; | |
104 | } | |
105 | ||
106 | static CORE_ADDR | |
7714d83a | 107 | mips64_linux_register_addr (struct gdbarch *gdbarch, int regno, int store) |
dda0c97e | 108 | { |
7714d83a | 109 | CORE_ADDR regaddr; |
dda0c97e | 110 | |
2eb4d78b | 111 | if (regno < 0 || regno >= gdbarch_num_regs (gdbarch)) |
dda0c97e UW |
112 | error (_("Bogon register number %d."), regno); |
113 | ||
7714d83a | 114 | if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32) |
dda0c97e | 115 | regaddr = regno; |
7714d83a UW |
116 | else if ((regno >= mips_regnum (gdbarch)->fp0) |
117 | && (regno < mips_regnum (gdbarch)->fp0 + 32)) | |
2eb4d78b | 118 | regaddr = MIPS64_FPR_BASE + (regno - gdbarch_fp0_regnum (gdbarch)); |
7714d83a | 119 | else if (regno == mips_regnum (gdbarch)->pc) |
dda0c97e | 120 | regaddr = MIPS64_PC; |
7714d83a UW |
121 | else if (regno == mips_regnum (gdbarch)->cause) |
122 | regaddr = store? (CORE_ADDR) -1 : MIPS64_CAUSE; | |
123 | else if (regno == mips_regnum (gdbarch)->badvaddr) | |
124 | regaddr = store? (CORE_ADDR) -1 : MIPS64_BADVADDR; | |
125 | else if (regno == mips_regnum (gdbarch)->lo) | |
dda0c97e | 126 | regaddr = MIPS64_MMLO; |
7714d83a | 127 | else if (regno == mips_regnum (gdbarch)->hi) |
dda0c97e | 128 | regaddr = MIPS64_MMHI; |
7714d83a | 129 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
dda0c97e | 130 | regaddr = MIPS64_FPC_CSR; |
7714d83a UW |
131 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
132 | regaddr = store? (CORE_ADDR) -1 : MIPS64_FPC_EIR; | |
822b6570 DJ |
133 | else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM) |
134 | regaddr = 0; | |
dda0c97e | 135 | else |
7714d83a | 136 | regaddr = (CORE_ADDR) -1; |
dda0c97e UW |
137 | |
138 | return regaddr; | |
139 | } | |
140 | ||
dc60ece8 DJ |
141 | /* Fetch the thread-local storage pointer for libthread_db. */ |
142 | ||
143 | ps_err_e | |
144 | ps_get_thread_area (const struct ps_prochandle *ph, | |
145 | lwpid_t lwpid, int idx, void **base) | |
146 | { | |
147 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
148 | return PS_ERR; | |
149 | ||
150 | /* IDX is the bias from the thread pointer to the beginning of the | |
151 | thread descriptor. It has to be subtracted due to implementation | |
152 | quirks in libthread_db. */ | |
153 | *base = (void *) ((char *)*base - idx); | |
154 | ||
155 | return PS_OK; | |
156 | } | |
157 | ||
3e00823e UW |
158 | /* Wrapper functions. These are only used by libthread_db. */ |
159 | ||
160 | void | |
7f7fe91e | 161 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
3e00823e | 162 | { |
2eb4d78b | 163 | if (mips_isa_regsize (get_regcache_arch (regcache)) == 4) |
7f7fe91e | 164 | mips_supply_gregset (regcache, (const mips_elf_gregset_t *) gregsetp); |
3e00823e | 165 | else |
7f7fe91e | 166 | mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *) gregsetp); |
3e00823e UW |
167 | } |
168 | ||
169 | void | |
7f7fe91e UW |
170 | fill_gregset (const struct regcache *regcache, |
171 | gdb_gregset_t *gregsetp, int regno) | |
3e00823e | 172 | { |
2eb4d78b | 173 | if (mips_isa_regsize (get_regcache_arch (regcache)) == 4) |
7f7fe91e | 174 | mips_fill_gregset (regcache, (mips_elf_gregset_t *) gregsetp, regno); |
3e00823e | 175 | else |
7f7fe91e | 176 | mips64_fill_gregset (regcache, (mips64_elf_gregset_t *) gregsetp, regno); |
3e00823e UW |
177 | } |
178 | ||
179 | void | |
7f7fe91e | 180 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) |
3e00823e | 181 | { |
2eb4d78b | 182 | if (mips_isa_regsize (get_regcache_arch (regcache)) == 4) |
7f7fe91e | 183 | mips_supply_fpregset (regcache, (const mips_elf_fpregset_t *) fpregsetp); |
3e00823e | 184 | else |
025bb325 MS |
185 | mips64_supply_fpregset (regcache, |
186 | (const mips64_elf_fpregset_t *) fpregsetp); | |
3e00823e UW |
187 | } |
188 | ||
189 | void | |
7f7fe91e UW |
190 | fill_fpregset (const struct regcache *regcache, |
191 | gdb_fpregset_t *fpregsetp, int regno) | |
3e00823e | 192 | { |
2eb4d78b | 193 | if (mips_isa_regsize (get_regcache_arch (regcache)) == 4) |
7f7fe91e | 194 | mips_fill_fpregset (regcache, (mips_elf_fpregset_t *) fpregsetp, regno); |
3e00823e | 195 | else |
025bb325 MS |
196 | mips64_fill_fpregset (regcache, |
197 | (mips64_elf_fpregset_t *) fpregsetp, regno); | |
3e00823e UW |
198 | } |
199 | ||
200 | ||
d37eb719 DJ |
201 | /* Fetch REGNO (or all registers if REGNO == -1) from the target |
202 | using PTRACE_GETREGS et al. */ | |
203 | ||
204 | static void | |
56be3814 | 205 | mips64_linux_regsets_fetch_registers (struct regcache *regcache, int regno) |
d37eb719 | 206 | { |
2eb4d78b | 207 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
d37eb719 DJ |
208 | int is_fp; |
209 | int tid; | |
210 | ||
2eb4d78b UW |
211 | if (regno >= mips_regnum (gdbarch)->fp0 |
212 | && regno <= mips_regnum (gdbarch)->fp0 + 32) | |
d37eb719 | 213 | is_fp = 1; |
2eb4d78b | 214 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
d37eb719 | 215 | is_fp = 1; |
2eb4d78b | 216 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
d37eb719 DJ |
217 | is_fp = 1; |
218 | else | |
219 | is_fp = 0; | |
220 | ||
221 | tid = ptid_get_lwp (inferior_ptid); | |
222 | if (tid == 0) | |
223 | tid = ptid_get_pid (inferior_ptid); | |
224 | ||
225 | if (regno == -1 || !is_fp) | |
226 | { | |
227 | mips64_elf_gregset_t regs; | |
228 | ||
229 | if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1) | |
230 | { | |
231 | if (errno == EIO) | |
232 | { | |
233 | have_ptrace_regsets = 0; | |
234 | return; | |
235 | } | |
236 | perror_with_name (_("Couldn't get registers")); | |
237 | } | |
238 | ||
56be3814 | 239 | mips64_supply_gregset (regcache, |
28f5035f | 240 | (const mips64_elf_gregset_t *) ®s); |
d37eb719 DJ |
241 | } |
242 | ||
243 | if (regno == -1 || is_fp) | |
244 | { | |
245 | mips64_elf_fpregset_t fp_regs; | |
246 | ||
247 | if (ptrace (PTRACE_GETFPREGS, tid, 0L, | |
248 | (PTRACE_TYPE_ARG3) &fp_regs) == -1) | |
249 | { | |
250 | if (errno == EIO) | |
251 | { | |
252 | have_ptrace_regsets = 0; | |
253 | return; | |
254 | } | |
255 | perror_with_name (_("Couldn't get FP registers")); | |
256 | } | |
257 | ||
56be3814 | 258 | mips64_supply_fpregset (regcache, |
28f5035f | 259 | (const mips64_elf_fpregset_t *) &fp_regs); |
d37eb719 DJ |
260 | } |
261 | } | |
262 | ||
263 | /* Store REGNO (or all registers if REGNO == -1) to the target | |
264 | using PTRACE_SETREGS et al. */ | |
265 | ||
266 | static void | |
025bb325 MS |
267 | mips64_linux_regsets_store_registers (const struct regcache *regcache, |
268 | int regno) | |
d37eb719 | 269 | { |
2eb4d78b | 270 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
d37eb719 DJ |
271 | int is_fp; |
272 | int tid; | |
273 | ||
2eb4d78b UW |
274 | if (regno >= mips_regnum (gdbarch)->fp0 |
275 | && regno <= mips_regnum (gdbarch)->fp0 + 32) | |
d37eb719 | 276 | is_fp = 1; |
2eb4d78b | 277 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
d37eb719 | 278 | is_fp = 1; |
2eb4d78b | 279 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
d37eb719 DJ |
280 | is_fp = 1; |
281 | else | |
282 | is_fp = 0; | |
283 | ||
284 | tid = ptid_get_lwp (inferior_ptid); | |
285 | if (tid == 0) | |
286 | tid = ptid_get_pid (inferior_ptid); | |
287 | ||
288 | if (regno == -1 || !is_fp) | |
289 | { | |
290 | mips64_elf_gregset_t regs; | |
291 | ||
292 | if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1) | |
293 | perror_with_name (_("Couldn't get registers")); | |
294 | ||
56be3814 | 295 | mips64_fill_gregset (regcache, ®s, regno); |
d37eb719 DJ |
296 | |
297 | if (ptrace (PTRACE_SETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1) | |
298 | perror_with_name (_("Couldn't set registers")); | |
299 | } | |
300 | ||
301 | if (regno == -1 || is_fp) | |
302 | { | |
303 | mips64_elf_fpregset_t fp_regs; | |
304 | ||
305 | if (ptrace (PTRACE_GETFPREGS, tid, 0L, | |
306 | (PTRACE_TYPE_ARG3) &fp_regs) == -1) | |
307 | perror_with_name (_("Couldn't get FP registers")); | |
308 | ||
56be3814 | 309 | mips64_fill_fpregset (regcache, &fp_regs, regno); |
d37eb719 DJ |
310 | |
311 | if (ptrace (PTRACE_SETFPREGS, tid, 0L, | |
312 | (PTRACE_TYPE_ARG3) &fp_regs) == -1) | |
313 | perror_with_name (_("Couldn't set FP registers")); | |
314 | } | |
315 | } | |
316 | ||
317 | /* Fetch REGNO (or all registers if REGNO == -1) from the target | |
318 | using any working method. */ | |
319 | ||
320 | static void | |
28439f5e PA |
321 | mips64_linux_fetch_registers (struct target_ops *ops, |
322 | struct regcache *regcache, int regnum) | |
d37eb719 DJ |
323 | { |
324 | /* Unless we already know that PTRACE_GETREGS does not work, try it. */ | |
325 | if (have_ptrace_regsets) | |
56be3814 | 326 | mips64_linux_regsets_fetch_registers (regcache, regnum); |
d37eb719 DJ |
327 | |
328 | /* If we know, or just found out, that PTRACE_GETREGS does not work, fall | |
329 | back to PTRACE_PEEKUSER. */ | |
330 | if (!have_ptrace_regsets) | |
a0740d21 | 331 | super_fetch_registers (ops, regcache, regnum); |
d37eb719 DJ |
332 | } |
333 | ||
334 | /* Store REGNO (or all registers if REGNO == -1) to the target | |
335 | using any working method. */ | |
336 | ||
337 | static void | |
28439f5e PA |
338 | mips64_linux_store_registers (struct target_ops *ops, |
339 | struct regcache *regcache, int regnum) | |
d37eb719 DJ |
340 | { |
341 | /* Unless we already know that PTRACE_GETREGS does not work, try it. */ | |
342 | if (have_ptrace_regsets) | |
56be3814 | 343 | mips64_linux_regsets_store_registers (regcache, regnum); |
d37eb719 DJ |
344 | |
345 | /* If we know, or just found out, that PTRACE_GETREGS does not work, fall | |
346 | back to PTRACE_PEEKUSER. */ | |
347 | if (!have_ptrace_regsets) | |
a0740d21 | 348 | super_store_registers (ops, regcache, regnum); |
d37eb719 DJ |
349 | } |
350 | ||
910122bf UW |
351 | /* Return the address in the core dump or inferior of register |
352 | REGNO. */ | |
353 | ||
354 | static CORE_ADDR | |
7714d83a | 355 | mips_linux_register_u_offset (struct gdbarch *gdbarch, int regno, int store_p) |
910122bf | 356 | { |
7714d83a UW |
357 | if (mips_abi_regsize (gdbarch) == 8) |
358 | return mips64_linux_register_addr (gdbarch, regno, store_p); | |
dda0c97e | 359 | else |
7714d83a | 360 | return mips_linux_register_addr (gdbarch, regno, store_p); |
910122bf UW |
361 | } |
362 | ||
81adfced DJ |
363 | static const struct target_desc * |
364 | mips_linux_read_description (struct target_ops *ops) | |
822b6570 | 365 | { |
81adfced DJ |
366 | /* Report that target registers are a size we know for sure |
367 | that we can get from ptrace. */ | |
368 | if (_MIPS_SIM == _ABIO32) | |
369 | return tdesc_mips_linux; | |
370 | else | |
371 | return tdesc_mips64_linux; | |
822b6570 DJ |
372 | } |
373 | ||
b9412953 DD |
374 | #ifndef PTRACE_GET_WATCH_REGS |
375 | # define PTRACE_GET_WATCH_REGS 0xd0 | |
376 | #endif | |
377 | ||
378 | #ifndef PTRACE_SET_WATCH_REGS | |
379 | # define PTRACE_SET_WATCH_REGS 0xd1 | |
380 | #endif | |
381 | ||
382 | #define W_BIT 0 | |
383 | #define R_BIT 1 | |
384 | #define I_BIT 2 | |
385 | ||
386 | #define W_MASK (1 << W_BIT) | |
387 | #define R_MASK (1 << R_BIT) | |
388 | #define I_MASK (1 << I_BIT) | |
389 | ||
390 | #define IRW_MASK (I_MASK | R_MASK | W_MASK) | |
391 | ||
392 | enum pt_watch_style { | |
393 | pt_watch_style_mips32, | |
394 | pt_watch_style_mips64 | |
395 | }; | |
396 | ||
397 | #define MAX_DEBUG_REGISTER 8 | |
398 | ||
025bb325 | 399 | /* A value of zero in a watchlo indicates that it is available. */ |
b9412953 DD |
400 | |
401 | struct mips32_watch_regs | |
402 | { | |
403 | uint32_t watchlo[MAX_DEBUG_REGISTER]; | |
025bb325 | 404 | /* Lower 16 bits of watchhi. */ |
b9412953 DD |
405 | uint16_t watchhi[MAX_DEBUG_REGISTER]; |
406 | /* Valid mask and I R W bits. | |
407 | * bit 0 -- 1 if W bit is usable. | |
408 | * bit 1 -- 1 if R bit is usable. | |
409 | * bit 2 -- 1 if I bit is usable. | |
410 | * bits 3 - 11 -- Valid watchhi mask bits. | |
411 | */ | |
412 | uint16_t watch_masks[MAX_DEBUG_REGISTER]; | |
413 | /* The number of valid watch register pairs. */ | |
414 | uint32_t num_valid; | |
415 | /* There is confusion across gcc versions about structure alignment, | |
416 | so we force 8 byte alignment for these structures so they match | |
417 | the kernel even if it was build with a different gcc version. */ | |
418 | } __attribute__ ((aligned (8))); | |
419 | ||
420 | struct mips64_watch_regs | |
421 | { | |
422 | uint64_t watchlo[MAX_DEBUG_REGISTER]; | |
423 | uint16_t watchhi[MAX_DEBUG_REGISTER]; | |
424 | uint16_t watch_masks[MAX_DEBUG_REGISTER]; | |
425 | uint32_t num_valid; | |
426 | } __attribute__ ((aligned (8))); | |
427 | ||
428 | struct pt_watch_regs | |
429 | { | |
430 | enum pt_watch_style style; | |
431 | union | |
432 | { | |
433 | struct mips32_watch_regs mips32; | |
434 | struct mips64_watch_regs mips64; | |
435 | }; | |
436 | }; | |
437 | ||
438 | /* -1 if the kernel and/or CPU do not support watch registers. | |
439 | 1 if watch_readback is valid and we can read style, num_valid | |
440 | and the masks. | |
441 | 0 if we need to read the watch_readback. */ | |
442 | ||
443 | static int watch_readback_valid; | |
444 | ||
445 | /* Cached watch register read values. */ | |
446 | ||
447 | static struct pt_watch_regs watch_readback; | |
448 | ||
449 | /* We keep list of all watchpoints we should install and calculate the | |
450 | watch register values each time the list changes. This allows for | |
451 | easy sharing of watch registers for more than one watchpoint. */ | |
452 | ||
453 | struct mips_watchpoint | |
454 | { | |
455 | CORE_ADDR addr; | |
456 | int len; | |
457 | int type; | |
458 | struct mips_watchpoint *next; | |
459 | }; | |
460 | ||
461 | static struct mips_watchpoint *current_watches; | |
462 | ||
463 | /* The current set of watch register values for writing the | |
464 | registers. */ | |
465 | ||
466 | static struct pt_watch_regs watch_mirror; | |
467 | ||
468 | /* Assuming usable watch registers, return the irw_mask. */ | |
469 | ||
470 | static uint32_t | |
471 | get_irw_mask (struct pt_watch_regs *regs, int set) | |
472 | { | |
473 | switch (regs->style) | |
474 | { | |
475 | case pt_watch_style_mips32: | |
476 | return regs->mips32.watch_masks[set] & IRW_MASK; | |
477 | case pt_watch_style_mips64: | |
478 | return regs->mips64.watch_masks[set] & IRW_MASK; | |
479 | default: | |
480 | internal_error (__FILE__, __LINE__, | |
481 | _("Unrecognized watch register style")); | |
482 | } | |
483 | } | |
484 | ||
485 | /* Assuming usable watch registers, return the reg_mask. */ | |
486 | ||
487 | static uint32_t | |
488 | get_reg_mask (struct pt_watch_regs *regs, int set) | |
489 | { | |
490 | switch (regs->style) | |
491 | { | |
492 | case pt_watch_style_mips32: | |
493 | return regs->mips32.watch_masks[set] & ~IRW_MASK; | |
494 | case pt_watch_style_mips64: | |
495 | return regs->mips64.watch_masks[set] & ~IRW_MASK; | |
496 | default: | |
497 | internal_error (__FILE__, __LINE__, | |
498 | _("Unrecognized watch register style")); | |
499 | } | |
500 | } | |
501 | ||
502 | /* Assuming usable watch registers, return the num_valid. */ | |
503 | ||
504 | static uint32_t | |
505 | get_num_valid (struct pt_watch_regs *regs) | |
506 | { | |
507 | switch (regs->style) | |
508 | { | |
509 | case pt_watch_style_mips32: | |
510 | return regs->mips32.num_valid; | |
511 | case pt_watch_style_mips64: | |
512 | return regs->mips64.num_valid; | |
513 | default: | |
514 | internal_error (__FILE__, __LINE__, | |
515 | _("Unrecognized watch register style")); | |
516 | } | |
517 | } | |
518 | ||
519 | /* Assuming usable watch registers, return the watchlo. */ | |
520 | ||
521 | static CORE_ADDR | |
522 | get_watchlo (struct pt_watch_regs *regs, int set) | |
523 | { | |
524 | switch (regs->style) | |
525 | { | |
526 | case pt_watch_style_mips32: | |
527 | return regs->mips32.watchlo[set]; | |
528 | case pt_watch_style_mips64: | |
529 | return regs->mips64.watchlo[set]; | |
530 | default: | |
531 | internal_error (__FILE__, __LINE__, | |
532 | _("Unrecognized watch register style")); | |
533 | } | |
534 | } | |
535 | ||
536 | /* Assuming usable watch registers, set a watchlo value. */ | |
537 | ||
538 | static void | |
539 | set_watchlo (struct pt_watch_regs *regs, int set, CORE_ADDR value) | |
540 | { | |
541 | switch (regs->style) | |
542 | { | |
543 | case pt_watch_style_mips32: | |
544 | /* The cast will never throw away bits as 64 bit addresses can | |
545 | never be used on a 32 bit kernel. */ | |
546 | regs->mips32.watchlo[set] = (uint32_t)value; | |
547 | break; | |
548 | case pt_watch_style_mips64: | |
549 | regs->mips64.watchlo[set] = value; | |
550 | break; | |
551 | default: | |
552 | internal_error (__FILE__, __LINE__, | |
553 | _("Unrecognized watch register style")); | |
554 | } | |
555 | } | |
556 | ||
557 | /* Assuming usable watch registers, return the watchhi. */ | |
558 | ||
559 | static uint32_t | |
560 | get_watchhi (struct pt_watch_regs *regs, int n) | |
561 | { | |
562 | switch (regs->style) | |
563 | { | |
564 | case pt_watch_style_mips32: | |
565 | return regs->mips32.watchhi[n]; | |
566 | case pt_watch_style_mips64: | |
567 | return regs->mips64.watchhi[n]; | |
568 | default: | |
569 | internal_error (__FILE__, __LINE__, | |
570 | _("Unrecognized watch register style")); | |
571 | } | |
572 | } | |
573 | ||
574 | /* Assuming usable watch registers, set a watchhi value. */ | |
575 | ||
576 | static void | |
577 | set_watchhi (struct pt_watch_regs *regs, int n, uint16_t value) | |
578 | { | |
579 | switch (regs->style) | |
580 | { | |
581 | case pt_watch_style_mips32: | |
582 | regs->mips32.watchhi[n] = value; | |
583 | break; | |
584 | case pt_watch_style_mips64: | |
585 | regs->mips64.watchhi[n] = value; | |
586 | break; | |
587 | default: | |
588 | internal_error (__FILE__, __LINE__, | |
589 | _("Unrecognized watch register style")); | |
590 | } | |
591 | } | |
592 | ||
593 | static void | |
594 | mips_show_dr (const char *func, CORE_ADDR addr, | |
595 | int len, enum target_hw_bp_type type) | |
596 | { | |
597 | int i; | |
598 | ||
599 | puts_unfiltered (func); | |
600 | if (addr || len) | |
5af949e3 UW |
601 | printf_unfiltered (" (addr=%s, len=%d, type=%s)", |
602 | paddress (target_gdbarch, addr), len, | |
b9412953 DD |
603 | type == hw_write ? "data-write" |
604 | : (type == hw_read ? "data-read" | |
605 | : (type == hw_access ? "data-read/write" | |
606 | : (type == hw_execute ? "instruction-execute" | |
607 | : "??unknown??")))); | |
608 | puts_unfiltered (":\n"); | |
609 | ||
610 | for (i = 0; i < MAX_DEBUG_REGISTER; i++) | |
5af949e3 UW |
611 | printf_unfiltered ("\tDR%d: lo=%s, hi=%s\n", i, |
612 | paddress (target_gdbarch, | |
613 | get_watchlo (&watch_mirror, i)), | |
614 | paddress (target_gdbarch, | |
615 | get_watchhi (&watch_mirror, i))); | |
b9412953 DD |
616 | } |
617 | ||
618 | /* Return 1 if watch registers are usable. Cached information is used | |
619 | unless force is true. */ | |
620 | ||
621 | static int | |
622 | mips_linux_read_watch_registers (int force) | |
623 | { | |
624 | int tid; | |
625 | ||
626 | if (force || watch_readback_valid == 0) | |
627 | { | |
628 | tid = ptid_get_lwp (inferior_ptid); | |
629 | if (ptrace (PTRACE_GET_WATCH_REGS, tid, &watch_readback) == -1) | |
630 | { | |
631 | watch_readback_valid = -1; | |
632 | return 0; | |
633 | } | |
634 | switch (watch_readback.style) | |
635 | { | |
636 | case pt_watch_style_mips32: | |
637 | if (watch_readback.mips32.num_valid == 0) | |
638 | { | |
639 | watch_readback_valid = -1; | |
640 | return 0; | |
641 | } | |
642 | break; | |
643 | case pt_watch_style_mips64: | |
644 | if (watch_readback.mips64.num_valid == 0) | |
645 | { | |
646 | watch_readback_valid = -1; | |
647 | return 0; | |
648 | } | |
649 | break; | |
650 | default: | |
651 | watch_readback_valid = -1; | |
652 | return 0; | |
653 | } | |
654 | /* Watch registers appear to be usable. */ | |
655 | watch_readback_valid = 1; | |
656 | } | |
657 | return (watch_readback_valid == 1) ? 1 : 0; | |
658 | } | |
659 | ||
660 | /* Convert GDB's type to an IRW mask. */ | |
661 | ||
662 | static unsigned | |
663 | type_to_irw (int type) | |
664 | { | |
665 | switch (type) | |
666 | { | |
667 | case hw_write: | |
668 | return W_MASK; | |
669 | case hw_read: | |
670 | return R_MASK; | |
671 | case hw_access: | |
672 | return (W_MASK | R_MASK); | |
673 | default: | |
674 | return 0; | |
675 | } | |
676 | } | |
677 | ||
678 | /* Target to_can_use_hw_breakpoint implementation. Return 1 if we can | |
679 | handle the specified watch type. */ | |
680 | ||
681 | static int | |
682 | mips_linux_can_use_hw_breakpoint (int type, int cnt, int ot) | |
683 | { | |
684 | int i; | |
685 | uint32_t wanted_mask, irw_mask; | |
686 | ||
687 | if (!mips_linux_read_watch_registers (0)) | |
688 | return 0; | |
689 | ||
690 | switch (type) | |
691 | { | |
692 | case bp_hardware_watchpoint: | |
693 | wanted_mask = W_MASK; | |
694 | break; | |
695 | case bp_read_watchpoint: | |
696 | wanted_mask = R_MASK; | |
697 | break; | |
698 | case bp_access_watchpoint: | |
699 | wanted_mask = R_MASK | W_MASK; | |
700 | break; | |
701 | default: | |
702 | return 0; | |
703 | } | |
704 | ||
705 | for (i = 0; i < get_num_valid (&watch_readback) && cnt; i++) | |
706 | { | |
707 | irw_mask = get_irw_mask (&watch_readback, i); | |
708 | if ((irw_mask & wanted_mask) == wanted_mask) | |
709 | cnt--; | |
710 | } | |
711 | return (cnt == 0) ? 1 : 0; | |
712 | } | |
713 | ||
714 | /* Target to_stopped_by_watchpoint implementation. Return 1 if | |
715 | stopped by watchpoint. The watchhi R and W bits indicate the watch | |
025bb325 | 716 | register triggered. */ |
b9412953 DD |
717 | |
718 | static int | |
719 | mips_linux_stopped_by_watchpoint (void) | |
720 | { | |
721 | int n; | |
722 | int num_valid; | |
723 | ||
724 | if (!mips_linux_read_watch_registers (1)) | |
725 | return 0; | |
726 | ||
727 | num_valid = get_num_valid (&watch_readback); | |
728 | ||
729 | for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++) | |
730 | if (get_watchhi (&watch_readback, n) & (R_MASK | W_MASK)) | |
731 | return 1; | |
732 | ||
733 | return 0; | |
734 | } | |
735 | ||
736 | /* Target to_stopped_data_address implementation. Set the address | |
737 | where the watch triggered (if known). Return 1 if the address was | |
738 | known. */ | |
739 | ||
740 | static int | |
741 | mips_linux_stopped_data_address (struct target_ops *t, CORE_ADDR *paddr) | |
742 | { | |
743 | /* On mips we don't know the low order 3 bits of the data address, | |
744 | so we must return false. */ | |
745 | return 0; | |
746 | } | |
747 | ||
748 | /* Set any low order bits in mask that are not set. */ | |
749 | ||
750 | static CORE_ADDR | |
751 | fill_mask (CORE_ADDR mask) | |
752 | { | |
753 | CORE_ADDR f = 1; | |
754 | while (f && f < mask) | |
755 | { | |
756 | mask |= f; | |
757 | f <<= 1; | |
758 | } | |
759 | return mask; | |
760 | } | |
761 | ||
762 | /* Try to add a single watch to the specified registers. Return 1 on | |
763 | success, 0 on failure. */ | |
764 | ||
765 | static int | |
766 | try_one_watch (struct pt_watch_regs *regs, CORE_ADDR addr, | |
767 | int len, unsigned irw) | |
768 | { | |
769 | CORE_ADDR base_addr, last_byte, break_addr, segment_len; | |
770 | CORE_ADDR mask_bits, t_low, t_low_end; | |
771 | uint16_t t_hi; | |
772 | int i, free_watches; | |
773 | struct pt_watch_regs regs_copy; | |
774 | ||
775 | if (len <= 0) | |
776 | return 0; | |
777 | ||
778 | last_byte = addr + len - 1; | |
779 | mask_bits = fill_mask (addr ^ last_byte) | IRW_MASK; | |
780 | base_addr = addr & ~mask_bits; | |
781 | ||
782 | /* Check to see if it is covered by current registers. */ | |
783 | for (i = 0; i < get_num_valid (regs); i++) | |
784 | { | |
785 | t_low = get_watchlo (regs, i); | |
786 | if (t_low != 0 && irw == ((unsigned)t_low & irw)) | |
787 | { | |
788 | t_hi = get_watchhi (regs, i) | IRW_MASK; | |
789 | t_low &= ~(CORE_ADDR)t_hi; | |
790 | if (addr >= t_low && last_byte <= (t_low + t_hi)) | |
791 | return 1; | |
792 | } | |
793 | } | |
794 | /* Try to find an empty register. */ | |
795 | free_watches = 0; | |
796 | for (i = 0; i < get_num_valid (regs); i++) | |
797 | { | |
798 | t_low = get_watchlo (regs, i); | |
799 | if (t_low == 0 && irw == (get_irw_mask (regs, i) & irw)) | |
800 | { | |
801 | if (mask_bits <= (get_reg_mask (regs, i) | IRW_MASK)) | |
802 | { | |
803 | /* It fits, we'll take it. */ | |
804 | set_watchlo (regs, i, base_addr | irw); | |
805 | set_watchhi (regs, i, mask_bits & ~IRW_MASK); | |
806 | return 1; | |
807 | } | |
808 | else | |
809 | { | |
810 | /* It doesn't fit, but has the proper IRW capabilities. */ | |
811 | free_watches++; | |
812 | } | |
813 | } | |
814 | } | |
815 | if (free_watches > 1) | |
816 | { | |
817 | /* Try to split it across several registers. */ | |
818 | regs_copy = *regs; | |
819 | for (i = 0; i < get_num_valid (®s_copy); i++) | |
820 | { | |
821 | t_low = get_watchlo (®s_copy, i); | |
822 | t_hi = get_reg_mask (®s_copy, i) | IRW_MASK; | |
823 | if (t_low == 0 && irw == (t_hi & irw)) | |
824 | { | |
825 | t_low = addr & ~(CORE_ADDR)t_hi; | |
826 | break_addr = t_low + t_hi + 1; | |
827 | if (break_addr >= addr + len) | |
828 | segment_len = len; | |
829 | else | |
830 | segment_len = break_addr - addr; | |
831 | mask_bits = fill_mask (addr ^ (addr + segment_len - 1)); | |
832 | set_watchlo (®s_copy, i, (addr & ~mask_bits) | irw); | |
833 | set_watchhi (®s_copy, i, mask_bits & ~IRW_MASK); | |
834 | if (break_addr >= addr + len) | |
835 | { | |
836 | *regs = regs_copy; | |
837 | return 1; | |
838 | } | |
839 | len = addr + len - break_addr; | |
840 | addr = break_addr; | |
841 | } | |
842 | } | |
843 | } | |
844 | /* It didn't fit anywhere, we failed. */ | |
845 | return 0; | |
846 | } | |
847 | ||
848 | /* Target to_region_ok_for_hw_watchpoint implementation. Return 1 if | |
849 | the specified region can be covered by the watch registers. */ | |
850 | ||
851 | static int | |
852 | mips_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) | |
853 | { | |
854 | struct pt_watch_regs dummy_regs; | |
855 | int i; | |
856 | ||
857 | if (!mips_linux_read_watch_registers (0)) | |
858 | return 0; | |
859 | ||
860 | dummy_regs = watch_readback; | |
861 | /* Clear them out. */ | |
862 | for (i = 0; i < get_num_valid (&dummy_regs); i++) | |
863 | set_watchlo (&dummy_regs, i, 0); | |
864 | return try_one_watch (&dummy_regs, addr, len, 0); | |
865 | } | |
866 | ||
867 | ||
868 | /* Write the mirrored watch register values for each thread. */ | |
869 | ||
870 | static int | |
871 | write_watchpoint_regs (void) | |
872 | { | |
873 | struct lwp_info *lp; | |
874 | ptid_t ptid; | |
875 | int tid; | |
876 | ||
877 | ALL_LWPS (lp, ptid) | |
878 | { | |
879 | tid = ptid_get_lwp (ptid); | |
880 | if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror) == -1) | |
881 | perror_with_name (_("Couldn't write debug register")); | |
882 | } | |
883 | return 0; | |
884 | } | |
885 | ||
886 | /* linux_nat new_thread implementation. Write the mirrored watch | |
887 | register values for the new thread. */ | |
888 | ||
889 | static void | |
890 | mips_linux_new_thread (ptid_t ptid) | |
891 | { | |
892 | int tid; | |
893 | ||
894 | if (!mips_linux_read_watch_registers (0)) | |
895 | return; | |
896 | ||
897 | tid = ptid_get_lwp (ptid); | |
898 | if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror) == -1) | |
899 | perror_with_name (_("Couldn't write debug register")); | |
900 | } | |
901 | ||
902 | /* Fill in the watch registers with the currently cached watches. */ | |
903 | ||
904 | static void | |
905 | populate_regs_from_watches (struct pt_watch_regs *regs) | |
906 | { | |
907 | struct mips_watchpoint *w; | |
908 | int i; | |
909 | ||
910 | /* Clear them out. */ | |
911 | for (i = 0; i < get_num_valid (regs); i++) | |
912 | { | |
913 | set_watchlo (regs, i, 0); | |
914 | set_watchhi (regs, i, 0); | |
915 | } | |
916 | ||
917 | w = current_watches; | |
918 | while (w) | |
919 | { | |
920 | i = try_one_watch (regs, w->addr, w->len, type_to_irw (w->type)); | |
921 | /* They must all fit, because we previously calculated that they | |
922 | would. */ | |
923 | gdb_assert (i); | |
924 | w = w->next; | |
925 | } | |
926 | } | |
927 | ||
928 | /* Target to_insert_watchpoint implementation. Try to insert a new | |
929 | watch. Return zero on success. */ | |
930 | ||
931 | static int | |
0cf6dd15 TJB |
932 | mips_linux_insert_watchpoint (CORE_ADDR addr, int len, int type, |
933 | struct expression *cond) | |
b9412953 DD |
934 | { |
935 | struct pt_watch_regs regs; | |
936 | struct mips_watchpoint *new_watch; | |
937 | struct mips_watchpoint **pw; | |
938 | ||
939 | int i; | |
940 | int retval; | |
941 | ||
942 | if (!mips_linux_read_watch_registers (0)) | |
943 | return -1; | |
944 | ||
945 | if (len <= 0) | |
946 | return -1; | |
947 | ||
948 | regs = watch_readback; | |
949 | /* Add the current watches. */ | |
950 | populate_regs_from_watches (®s); | |
951 | ||
952 | /* Now try to add the new watch. */ | |
953 | if (!try_one_watch (®s, addr, len, type_to_irw (type))) | |
954 | return -1; | |
955 | ||
956 | /* It fit. Stick it on the end of the list. */ | |
957 | new_watch = (struct mips_watchpoint *) | |
958 | xmalloc (sizeof (struct mips_watchpoint)); | |
959 | new_watch->addr = addr; | |
960 | new_watch->len = len; | |
961 | new_watch->type = type; | |
962 | new_watch->next = NULL; | |
963 | ||
964 | pw = ¤t_watches; | |
965 | while (*pw != NULL) | |
966 | pw = &(*pw)->next; | |
967 | *pw = new_watch; | |
968 | ||
969 | watch_mirror = regs; | |
970 | retval = write_watchpoint_regs (); | |
971 | ||
972 | if (maint_show_dr) | |
973 | mips_show_dr ("insert_watchpoint", addr, len, type); | |
974 | ||
975 | return retval; | |
976 | } | |
977 | ||
978 | /* Target to_remove_watchpoint implementation. Try to remove a watch. | |
979 | Return zero on success. */ | |
980 | ||
981 | static int | |
0cf6dd15 TJB |
982 | mips_linux_remove_watchpoint (CORE_ADDR addr, int len, int type, |
983 | struct expression *cond) | |
b9412953 DD |
984 | { |
985 | int retval; | |
986 | int deleted_one; | |
987 | ||
988 | struct mips_watchpoint **pw; | |
989 | struct mips_watchpoint *w; | |
990 | ||
991 | /* Search for a known watch that matches. Then unlink and free | |
992 | it. */ | |
993 | deleted_one = 0; | |
994 | pw = ¤t_watches; | |
995 | while ((w = *pw)) | |
996 | { | |
997 | if (w->addr == addr && w->len == len && w->type == type) | |
998 | { | |
999 | *pw = w->next; | |
1000 | xfree (w); | |
1001 | deleted_one = 1; | |
1002 | break; | |
1003 | } | |
1004 | pw = &(w->next); | |
1005 | } | |
1006 | ||
1007 | if (!deleted_one) | |
1008 | return -1; /* We don't know about it, fail doing nothing. */ | |
1009 | ||
1010 | /* At this point watch_readback is known to be valid because we | |
1011 | could not have added the watch without reading it. */ | |
1012 | gdb_assert (watch_readback_valid == 1); | |
1013 | ||
1014 | watch_mirror = watch_readback; | |
1015 | populate_regs_from_watches (&watch_mirror); | |
1016 | ||
1017 | retval = write_watchpoint_regs (); | |
1018 | ||
1019 | if (maint_show_dr) | |
1020 | mips_show_dr ("remove_watchpoint", addr, len, type); | |
1021 | ||
1022 | return retval; | |
1023 | } | |
1024 | ||
1025 | /* Target to_close implementation. Free any watches and call the | |
1026 | super implementation. */ | |
1027 | ||
1028 | static void | |
1029 | mips_linux_close (int quitting) | |
1030 | { | |
1031 | struct mips_watchpoint *w; | |
1032 | struct mips_watchpoint *nw; | |
1033 | ||
1034 | /* Clean out the current_watches list. */ | |
1035 | w = current_watches; | |
1036 | while (w) | |
1037 | { | |
1038 | nw = w->next; | |
1039 | xfree (w); | |
1040 | w = nw; | |
1041 | } | |
1042 | current_watches = NULL; | |
1043 | ||
1044 | if (super_close) | |
1045 | super_close (quitting); | |
1046 | } | |
1047 | ||
10d6c8cd DJ |
1048 | void _initialize_mips_linux_nat (void); |
1049 | ||
1050 | void | |
1051 | _initialize_mips_linux_nat (void) | |
1052 | { | |
b9412953 DD |
1053 | struct target_ops *t; |
1054 | ||
cbe54154 PA |
1055 | add_setshow_boolean_cmd ("show-debug-regs", class_maintenance, |
1056 | &maint_show_dr, _("\ | |
1057 | Set whether to show variables that mirror the mips debug registers."), _("\ | |
1058 | Show whether to show variables that mirror the mips debug registers."), _("\ | |
b9412953 DD |
1059 | Use \"on\" to enable, \"off\" to disable.\n\ |
1060 | If enabled, the debug registers values are shown when GDB inserts\n\ | |
1061 | or removes a hardware breakpoint or watchpoint, and when the inferior\n\ | |
1062 | triggers a breakpoint or watchpoint."), | |
cbe54154 PA |
1063 | NULL, |
1064 | NULL, | |
1065 | &maintenance_set_cmdlist, | |
1066 | &maintenance_show_cmdlist); | |
b9412953 DD |
1067 | |
1068 | t = linux_trad_target (mips_linux_register_u_offset); | |
1069 | ||
1070 | super_close = t->to_close; | |
1071 | t->to_close = mips_linux_close; | |
d37eb719 DJ |
1072 | |
1073 | super_fetch_registers = t->to_fetch_registers; | |
1074 | super_store_registers = t->to_store_registers; | |
1075 | ||
1076 | t->to_fetch_registers = mips64_linux_fetch_registers; | |
1077 | t->to_store_registers = mips64_linux_store_registers; | |
1078 | ||
b9412953 DD |
1079 | t->to_can_use_hw_breakpoint = mips_linux_can_use_hw_breakpoint; |
1080 | t->to_remove_watchpoint = mips_linux_remove_watchpoint; | |
1081 | t->to_insert_watchpoint = mips_linux_insert_watchpoint; | |
1082 | t->to_stopped_by_watchpoint = mips_linux_stopped_by_watchpoint; | |
1083 | t->to_stopped_data_address = mips_linux_stopped_data_address; | |
1084 | t->to_region_ok_for_hw_watchpoint = mips_linux_region_ok_for_hw_watchpoint; | |
1085 | ||
81adfced | 1086 | t->to_read_description = mips_linux_read_description; |
822b6570 | 1087 | |
f973ed9c | 1088 | linux_nat_add_target (t); |
b9412953 | 1089 | linux_nat_set_new_thread (t, mips_linux_new_thread); |
81adfced DJ |
1090 | |
1091 | /* Initialize the standard target descriptions. */ | |
1092 | initialize_tdesc_mips_linux (); | |
1093 | initialize_tdesc_mips64_linux (); | |
10d6c8cd | 1094 | } |