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75c9abc6 | 1 | /* Native-dependent code for GNU/Linux on MIPS processors. |
a094c6fb | 2 | |
ecd75fc8 | 3 | Copyright (C) 2001-2014 Free Software Foundation, Inc. |
2aa830e4 DJ |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
2aa830e4 DJ |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
2aa830e4 DJ |
19 | |
20 | #include "defs.h" | |
b9412953 DD |
21 | #include "command.h" |
22 | #include "gdbcmd.h" | |
23 | #include "gdb_assert.h" | |
d37eb719 | 24 | #include "inferior.h" |
6b753f60 | 25 | #include "mips-tdep.h" |
10d6c8cd | 26 | #include "target.h" |
28f5035f | 27 | #include "regcache.h" |
10d6c8cd | 28 | #include "linux-nat.h" |
d37eb719 | 29 | #include "mips-linux-tdep.h" |
822b6570 | 30 | #include "target-descriptions.h" |
2aa830e4 | 31 | |
dc60ece8 | 32 | #include "gdb_proc_service.h" |
3e00823e | 33 | #include "gregset.h" |
dc60ece8 | 34 | |
822b6570 | 35 | #include <sgidefs.h> |
d37eb719 | 36 | #include <sys/ptrace.h> |
9be14b81 | 37 | #include <asm/ptrace.h> |
d37eb719 | 38 | |
aaee2056 YQ |
39 | #include "mips-linux-watch.h" |
40 | ||
81adfced | 41 | #include "features/mips-linux.c" |
1faeff08 | 42 | #include "features/mips-dsp-linux.c" |
81adfced | 43 | #include "features/mips64-linux.c" |
1faeff08 | 44 | #include "features/mips64-dsp-linux.c" |
81adfced | 45 | |
dc60ece8 DJ |
46 | #ifndef PTRACE_GET_THREAD_AREA |
47 | #define PTRACE_GET_THREAD_AREA 25 | |
48 | #endif | |
49 | ||
d37eb719 DJ |
50 | /* Assume that we have PTRACE_GETREGS et al. support. If we do not, |
51 | we'll clear this and use PTRACE_PEEKUSER instead. */ | |
52 | static int have_ptrace_regsets = 1; | |
53 | ||
b9412953 DD |
54 | /* Whether or not to print the mirrored debug registers. */ |
55 | ||
56 | static int maint_show_dr; | |
57 | ||
d37eb719 DJ |
58 | /* Saved function pointers to fetch and store a single register using |
59 | PTRACE_PEEKUSER and PTRACE_POKEUSER. */ | |
60 | ||
b9412953 DD |
61 | static void (*super_fetch_registers) (struct target_ops *, |
62 | struct regcache *, int); | |
63 | static void (*super_store_registers) (struct target_ops *, | |
64 | struct regcache *, int); | |
65 | ||
93063aa6 | 66 | static void (*super_close) (struct target_ops *); |
d37eb719 | 67 | |
dda0c97e | 68 | /* Map gdb internal register number to ptrace ``address''. |
7714d83a UW |
69 | These ``addresses'' are normally defined in <asm/ptrace.h>. |
70 | ||
71 | ptrace does not provide a way to read (or set) MIPS_PS_REGNUM, | |
72 | and there's no point in reading or setting MIPS_ZERO_REGNUM. | |
73 | We also can not set BADVADDR, CAUSE, or FCRIR via ptrace(). */ | |
dda0c97e UW |
74 | |
75 | static CORE_ADDR | |
7714d83a | 76 | mips_linux_register_addr (struct gdbarch *gdbarch, int regno, int store) |
dda0c97e | 77 | { |
7714d83a | 78 | CORE_ADDR regaddr; |
dda0c97e | 79 | |
2eb4d78b | 80 | if (regno < 0 || regno >= gdbarch_num_regs (gdbarch)) |
dda0c97e UW |
81 | error (_("Bogon register number %d."), regno); |
82 | ||
7714d83a | 83 | if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32) |
dda0c97e | 84 | regaddr = regno; |
7714d83a UW |
85 | else if ((regno >= mips_regnum (gdbarch)->fp0) |
86 | && (regno < mips_regnum (gdbarch)->fp0 + 32)) | |
87 | regaddr = FPR_BASE + (regno - mips_regnum (gdbarch)->fp0); | |
88 | else if (regno == mips_regnum (gdbarch)->pc) | |
dda0c97e | 89 | regaddr = PC; |
7714d83a UW |
90 | else if (regno == mips_regnum (gdbarch)->cause) |
91 | regaddr = store? (CORE_ADDR) -1 : CAUSE; | |
92 | else if (regno == mips_regnum (gdbarch)->badvaddr) | |
93 | regaddr = store? (CORE_ADDR) -1 : BADVADDR; | |
94 | else if (regno == mips_regnum (gdbarch)->lo) | |
dda0c97e | 95 | regaddr = MMLO; |
7714d83a | 96 | else if (regno == mips_regnum (gdbarch)->hi) |
dda0c97e | 97 | regaddr = MMHI; |
7714d83a | 98 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
dda0c97e | 99 | regaddr = FPC_CSR; |
7714d83a UW |
100 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
101 | regaddr = store? (CORE_ADDR) -1 : FPC_EIR; | |
1faeff08 MR |
102 | else if (mips_regnum (gdbarch)->dspacc != -1 |
103 | && regno >= mips_regnum (gdbarch)->dspacc | |
104 | && regno < mips_regnum (gdbarch)->dspacc + 6) | |
105 | regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc); | |
106 | else if (regno == mips_regnum (gdbarch)->dspctl) | |
107 | regaddr = DSP_CONTROL; | |
822b6570 DJ |
108 | else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM) |
109 | regaddr = 0; | |
dda0c97e | 110 | else |
7714d83a | 111 | regaddr = (CORE_ADDR) -1; |
dda0c97e UW |
112 | |
113 | return regaddr; | |
114 | } | |
115 | ||
116 | static CORE_ADDR | |
7714d83a | 117 | mips64_linux_register_addr (struct gdbarch *gdbarch, int regno, int store) |
dda0c97e | 118 | { |
7714d83a | 119 | CORE_ADDR regaddr; |
dda0c97e | 120 | |
2eb4d78b | 121 | if (regno < 0 || regno >= gdbarch_num_regs (gdbarch)) |
dda0c97e UW |
122 | error (_("Bogon register number %d."), regno); |
123 | ||
7714d83a | 124 | if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32) |
dda0c97e | 125 | regaddr = regno; |
7714d83a UW |
126 | else if ((regno >= mips_regnum (gdbarch)->fp0) |
127 | && (regno < mips_regnum (gdbarch)->fp0 + 32)) | |
2eb4d78b | 128 | regaddr = MIPS64_FPR_BASE + (regno - gdbarch_fp0_regnum (gdbarch)); |
7714d83a | 129 | else if (regno == mips_regnum (gdbarch)->pc) |
dda0c97e | 130 | regaddr = MIPS64_PC; |
7714d83a UW |
131 | else if (regno == mips_regnum (gdbarch)->cause) |
132 | regaddr = store? (CORE_ADDR) -1 : MIPS64_CAUSE; | |
133 | else if (regno == mips_regnum (gdbarch)->badvaddr) | |
134 | regaddr = store? (CORE_ADDR) -1 : MIPS64_BADVADDR; | |
135 | else if (regno == mips_regnum (gdbarch)->lo) | |
dda0c97e | 136 | regaddr = MIPS64_MMLO; |
7714d83a | 137 | else if (regno == mips_regnum (gdbarch)->hi) |
dda0c97e | 138 | regaddr = MIPS64_MMHI; |
7714d83a | 139 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
dda0c97e | 140 | regaddr = MIPS64_FPC_CSR; |
7714d83a UW |
141 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
142 | regaddr = store? (CORE_ADDR) -1 : MIPS64_FPC_EIR; | |
1faeff08 MR |
143 | else if (mips_regnum (gdbarch)->dspacc != -1 |
144 | && regno >= mips_regnum (gdbarch)->dspacc | |
145 | && regno < mips_regnum (gdbarch)->dspacc + 6) | |
146 | regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc); | |
147 | else if (regno == mips_regnum (gdbarch)->dspctl) | |
148 | regaddr = DSP_CONTROL; | |
822b6570 DJ |
149 | else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM) |
150 | regaddr = 0; | |
dda0c97e | 151 | else |
7714d83a | 152 | regaddr = (CORE_ADDR) -1; |
dda0c97e UW |
153 | |
154 | return regaddr; | |
155 | } | |
156 | ||
dc60ece8 DJ |
157 | /* Fetch the thread-local storage pointer for libthread_db. */ |
158 | ||
159 | ps_err_e | |
160 | ps_get_thread_area (const struct ps_prochandle *ph, | |
161 | lwpid_t lwpid, int idx, void **base) | |
162 | { | |
163 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
164 | return PS_ERR; | |
165 | ||
166 | /* IDX is the bias from the thread pointer to the beginning of the | |
167 | thread descriptor. It has to be subtracted due to implementation | |
168 | quirks in libthread_db. */ | |
169 | *base = (void *) ((char *)*base - idx); | |
170 | ||
171 | return PS_OK; | |
172 | } | |
173 | ||
3e00823e UW |
174 | /* Wrapper functions. These are only used by libthread_db. */ |
175 | ||
176 | void | |
7f7fe91e | 177 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
3e00823e | 178 | { |
2eb4d78b | 179 | if (mips_isa_regsize (get_regcache_arch (regcache)) == 4) |
7f7fe91e | 180 | mips_supply_gregset (regcache, (const mips_elf_gregset_t *) gregsetp); |
3e00823e | 181 | else |
7f7fe91e | 182 | mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *) gregsetp); |
3e00823e UW |
183 | } |
184 | ||
185 | void | |
7f7fe91e UW |
186 | fill_gregset (const struct regcache *regcache, |
187 | gdb_gregset_t *gregsetp, int regno) | |
3e00823e | 188 | { |
2eb4d78b | 189 | if (mips_isa_regsize (get_regcache_arch (regcache)) == 4) |
7f7fe91e | 190 | mips_fill_gregset (regcache, (mips_elf_gregset_t *) gregsetp, regno); |
3e00823e | 191 | else |
7f7fe91e | 192 | mips64_fill_gregset (regcache, (mips64_elf_gregset_t *) gregsetp, regno); |
3e00823e UW |
193 | } |
194 | ||
195 | void | |
7f7fe91e | 196 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) |
3e00823e | 197 | { |
2eb4d78b | 198 | if (mips_isa_regsize (get_regcache_arch (regcache)) == 4) |
7f7fe91e | 199 | mips_supply_fpregset (regcache, (const mips_elf_fpregset_t *) fpregsetp); |
3e00823e | 200 | else |
025bb325 MS |
201 | mips64_supply_fpregset (regcache, |
202 | (const mips64_elf_fpregset_t *) fpregsetp); | |
3e00823e UW |
203 | } |
204 | ||
205 | void | |
7f7fe91e UW |
206 | fill_fpregset (const struct regcache *regcache, |
207 | gdb_fpregset_t *fpregsetp, int regno) | |
3e00823e | 208 | { |
2eb4d78b | 209 | if (mips_isa_regsize (get_regcache_arch (regcache)) == 4) |
7f7fe91e | 210 | mips_fill_fpregset (regcache, (mips_elf_fpregset_t *) fpregsetp, regno); |
3e00823e | 211 | else |
025bb325 MS |
212 | mips64_fill_fpregset (regcache, |
213 | (mips64_elf_fpregset_t *) fpregsetp, regno); | |
3e00823e UW |
214 | } |
215 | ||
216 | ||
d37eb719 DJ |
217 | /* Fetch REGNO (or all registers if REGNO == -1) from the target |
218 | using PTRACE_GETREGS et al. */ | |
219 | ||
220 | static void | |
1faeff08 MR |
221 | mips64_linux_regsets_fetch_registers (struct target_ops *ops, |
222 | struct regcache *regcache, int regno) | |
d37eb719 | 223 | { |
2eb4d78b | 224 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1faeff08 MR |
225 | int is_fp, is_dsp; |
226 | int have_dsp; | |
227 | int regi; | |
d37eb719 DJ |
228 | int tid; |
229 | ||
2eb4d78b UW |
230 | if (regno >= mips_regnum (gdbarch)->fp0 |
231 | && regno <= mips_regnum (gdbarch)->fp0 + 32) | |
d37eb719 | 232 | is_fp = 1; |
2eb4d78b | 233 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
d37eb719 | 234 | is_fp = 1; |
2eb4d78b | 235 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
d37eb719 DJ |
236 | is_fp = 1; |
237 | else | |
238 | is_fp = 0; | |
239 | ||
1faeff08 MR |
240 | /* DSP registers are optional and not a part of any set. */ |
241 | have_dsp = mips_regnum (gdbarch)->dspctl != -1; | |
242 | if (!have_dsp) | |
243 | is_dsp = 0; | |
244 | else if (regno >= mips_regnum (gdbarch)->dspacc | |
245 | && regno < mips_regnum (gdbarch)->dspacc + 6) | |
246 | is_dsp = 1; | |
247 | else if (regno == mips_regnum (gdbarch)->dspctl) | |
248 | is_dsp = 1; | |
249 | else | |
250 | is_dsp = 0; | |
251 | ||
d37eb719 DJ |
252 | tid = ptid_get_lwp (inferior_ptid); |
253 | if (tid == 0) | |
254 | tid = ptid_get_pid (inferior_ptid); | |
255 | ||
1faeff08 | 256 | if (regno == -1 || (!is_fp && !is_dsp)) |
d37eb719 DJ |
257 | { |
258 | mips64_elf_gregset_t regs; | |
259 | ||
260 | if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1) | |
261 | { | |
262 | if (errno == EIO) | |
263 | { | |
264 | have_ptrace_regsets = 0; | |
265 | return; | |
266 | } | |
267 | perror_with_name (_("Couldn't get registers")); | |
268 | } | |
269 | ||
56be3814 | 270 | mips64_supply_gregset (regcache, |
28f5035f | 271 | (const mips64_elf_gregset_t *) ®s); |
d37eb719 DJ |
272 | } |
273 | ||
274 | if (regno == -1 || is_fp) | |
275 | { | |
276 | mips64_elf_fpregset_t fp_regs; | |
277 | ||
278 | if (ptrace (PTRACE_GETFPREGS, tid, 0L, | |
279 | (PTRACE_TYPE_ARG3) &fp_regs) == -1) | |
280 | { | |
281 | if (errno == EIO) | |
282 | { | |
283 | have_ptrace_regsets = 0; | |
284 | return; | |
285 | } | |
286 | perror_with_name (_("Couldn't get FP registers")); | |
287 | } | |
288 | ||
56be3814 | 289 | mips64_supply_fpregset (regcache, |
28f5035f | 290 | (const mips64_elf_fpregset_t *) &fp_regs); |
d37eb719 | 291 | } |
1faeff08 MR |
292 | |
293 | if (is_dsp) | |
294 | super_fetch_registers (ops, regcache, regno); | |
295 | else if (regno == -1 && have_dsp) | |
296 | { | |
297 | for (regi = mips_regnum (gdbarch)->dspacc; | |
298 | regi < mips_regnum (gdbarch)->dspacc + 6; | |
299 | regi++) | |
300 | super_fetch_registers (ops, regcache, regi); | |
301 | super_fetch_registers (ops, regcache, mips_regnum (gdbarch)->dspctl); | |
302 | } | |
d37eb719 DJ |
303 | } |
304 | ||
305 | /* Store REGNO (or all registers if REGNO == -1) to the target | |
306 | using PTRACE_SETREGS et al. */ | |
307 | ||
308 | static void | |
1faeff08 MR |
309 | mips64_linux_regsets_store_registers (struct target_ops *ops, |
310 | struct regcache *regcache, int regno) | |
d37eb719 | 311 | { |
2eb4d78b | 312 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1faeff08 MR |
313 | int is_fp, is_dsp; |
314 | int have_dsp; | |
315 | int regi; | |
d37eb719 DJ |
316 | int tid; |
317 | ||
2eb4d78b UW |
318 | if (regno >= mips_regnum (gdbarch)->fp0 |
319 | && regno <= mips_regnum (gdbarch)->fp0 + 32) | |
d37eb719 | 320 | is_fp = 1; |
2eb4d78b | 321 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
d37eb719 | 322 | is_fp = 1; |
2eb4d78b | 323 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
d37eb719 DJ |
324 | is_fp = 1; |
325 | else | |
326 | is_fp = 0; | |
327 | ||
1faeff08 MR |
328 | /* DSP registers are optional and not a part of any set. */ |
329 | have_dsp = mips_regnum (gdbarch)->dspctl != -1; | |
330 | if (!have_dsp) | |
331 | is_dsp = 0; | |
6ce4c112 | 332 | else if (regno >= mips_regnum (gdbarch)->dspacc |
1faeff08 MR |
333 | && regno < mips_regnum (gdbarch)->dspacc + 6) |
334 | is_dsp = 1; | |
335 | else if (regno == mips_regnum (gdbarch)->dspctl) | |
336 | is_dsp = 1; | |
337 | else | |
338 | is_dsp = 0; | |
339 | ||
d37eb719 DJ |
340 | tid = ptid_get_lwp (inferior_ptid); |
341 | if (tid == 0) | |
342 | tid = ptid_get_pid (inferior_ptid); | |
343 | ||
1faeff08 | 344 | if (regno == -1 || (!is_fp && !is_dsp)) |
d37eb719 DJ |
345 | { |
346 | mips64_elf_gregset_t regs; | |
347 | ||
348 | if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1) | |
349 | perror_with_name (_("Couldn't get registers")); | |
350 | ||
56be3814 | 351 | mips64_fill_gregset (regcache, ®s, regno); |
d37eb719 DJ |
352 | |
353 | if (ptrace (PTRACE_SETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1) | |
354 | perror_with_name (_("Couldn't set registers")); | |
355 | } | |
356 | ||
357 | if (regno == -1 || is_fp) | |
358 | { | |
359 | mips64_elf_fpregset_t fp_regs; | |
360 | ||
361 | if (ptrace (PTRACE_GETFPREGS, tid, 0L, | |
362 | (PTRACE_TYPE_ARG3) &fp_regs) == -1) | |
363 | perror_with_name (_("Couldn't get FP registers")); | |
364 | ||
56be3814 | 365 | mips64_fill_fpregset (regcache, &fp_regs, regno); |
d37eb719 DJ |
366 | |
367 | if (ptrace (PTRACE_SETFPREGS, tid, 0L, | |
368 | (PTRACE_TYPE_ARG3) &fp_regs) == -1) | |
369 | perror_with_name (_("Couldn't set FP registers")); | |
370 | } | |
1faeff08 MR |
371 | |
372 | if (is_dsp) | |
373 | super_store_registers (ops, regcache, regno); | |
374 | else if (regno == -1 && have_dsp) | |
375 | { | |
376 | for (regi = mips_regnum (gdbarch)->dspacc; | |
377 | regi < mips_regnum (gdbarch)->dspacc + 6; | |
378 | regi++) | |
379 | super_store_registers (ops, regcache, regi); | |
380 | super_store_registers (ops, regcache, mips_regnum (gdbarch)->dspctl); | |
381 | } | |
d37eb719 DJ |
382 | } |
383 | ||
384 | /* Fetch REGNO (or all registers if REGNO == -1) from the target | |
385 | using any working method. */ | |
386 | ||
387 | static void | |
28439f5e PA |
388 | mips64_linux_fetch_registers (struct target_ops *ops, |
389 | struct regcache *regcache, int regnum) | |
d37eb719 DJ |
390 | { |
391 | /* Unless we already know that PTRACE_GETREGS does not work, try it. */ | |
392 | if (have_ptrace_regsets) | |
1faeff08 | 393 | mips64_linux_regsets_fetch_registers (ops, regcache, regnum); |
d37eb719 DJ |
394 | |
395 | /* If we know, or just found out, that PTRACE_GETREGS does not work, fall | |
396 | back to PTRACE_PEEKUSER. */ | |
397 | if (!have_ptrace_regsets) | |
a0740d21 | 398 | super_fetch_registers (ops, regcache, regnum); |
d37eb719 DJ |
399 | } |
400 | ||
401 | /* Store REGNO (or all registers if REGNO == -1) to the target | |
402 | using any working method. */ | |
403 | ||
404 | static void | |
28439f5e PA |
405 | mips64_linux_store_registers (struct target_ops *ops, |
406 | struct regcache *regcache, int regnum) | |
d37eb719 DJ |
407 | { |
408 | /* Unless we already know that PTRACE_GETREGS does not work, try it. */ | |
409 | if (have_ptrace_regsets) | |
1faeff08 | 410 | mips64_linux_regsets_store_registers (ops, regcache, regnum); |
d37eb719 DJ |
411 | |
412 | /* If we know, or just found out, that PTRACE_GETREGS does not work, fall | |
413 | back to PTRACE_PEEKUSER. */ | |
414 | if (!have_ptrace_regsets) | |
a0740d21 | 415 | super_store_registers (ops, regcache, regnum); |
d37eb719 DJ |
416 | } |
417 | ||
910122bf UW |
418 | /* Return the address in the core dump or inferior of register |
419 | REGNO. */ | |
420 | ||
421 | static CORE_ADDR | |
7714d83a | 422 | mips_linux_register_u_offset (struct gdbarch *gdbarch, int regno, int store_p) |
910122bf | 423 | { |
7714d83a UW |
424 | if (mips_abi_regsize (gdbarch) == 8) |
425 | return mips64_linux_register_addr (gdbarch, regno, store_p); | |
dda0c97e | 426 | else |
7714d83a | 427 | return mips_linux_register_addr (gdbarch, regno, store_p); |
910122bf UW |
428 | } |
429 | ||
81adfced DJ |
430 | static const struct target_desc * |
431 | mips_linux_read_description (struct target_ops *ops) | |
822b6570 | 432 | { |
1faeff08 MR |
433 | static int have_dsp = -1; |
434 | ||
435 | if (have_dsp < 0) | |
436 | { | |
437 | int tid; | |
438 | ||
439 | tid = ptid_get_lwp (inferior_ptid); | |
440 | if (tid == 0) | |
441 | tid = ptid_get_pid (inferior_ptid); | |
442 | ||
443 | ptrace (PTRACE_PEEKUSER, tid, DSP_CONTROL, 0); | |
444 | switch (errno) | |
445 | { | |
446 | case 0: | |
447 | have_dsp = 1; | |
448 | break; | |
449 | case EIO: | |
450 | have_dsp = 0; | |
451 | break; | |
452 | default: | |
837a1b32 | 453 | perror_with_name (_("Couldn't check DSP support")); |
1faeff08 MR |
454 | break; |
455 | } | |
456 | } | |
457 | ||
81adfced DJ |
458 | /* Report that target registers are a size we know for sure |
459 | that we can get from ptrace. */ | |
460 | if (_MIPS_SIM == _ABIO32) | |
1faeff08 | 461 | return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux; |
81adfced | 462 | else |
1faeff08 | 463 | return have_dsp ? tdesc_mips64_dsp_linux : tdesc_mips64_linux; |
822b6570 DJ |
464 | } |
465 | ||
b9412953 DD |
466 | /* -1 if the kernel and/or CPU do not support watch registers. |
467 | 1 if watch_readback is valid and we can read style, num_valid | |
468 | and the masks. | |
469 | 0 if we need to read the watch_readback. */ | |
470 | ||
471 | static int watch_readback_valid; | |
472 | ||
473 | /* Cached watch register read values. */ | |
474 | ||
475 | static struct pt_watch_regs watch_readback; | |
476 | ||
b9412953 DD |
477 | static struct mips_watchpoint *current_watches; |
478 | ||
479 | /* The current set of watch register values for writing the | |
480 | registers. */ | |
481 | ||
482 | static struct pt_watch_regs watch_mirror; | |
483 | ||
b9412953 DD |
484 | static void |
485 | mips_show_dr (const char *func, CORE_ADDR addr, | |
486 | int len, enum target_hw_bp_type type) | |
487 | { | |
488 | int i; | |
489 | ||
490 | puts_unfiltered (func); | |
491 | if (addr || len) | |
5af949e3 | 492 | printf_unfiltered (" (addr=%s, len=%d, type=%s)", |
f5656ead | 493 | paddress (target_gdbarch (), addr), len, |
b9412953 DD |
494 | type == hw_write ? "data-write" |
495 | : (type == hw_read ? "data-read" | |
496 | : (type == hw_access ? "data-read/write" | |
497 | : (type == hw_execute ? "instruction-execute" | |
498 | : "??unknown??")))); | |
499 | puts_unfiltered (":\n"); | |
500 | ||
501 | for (i = 0; i < MAX_DEBUG_REGISTER; i++) | |
5af949e3 | 502 | printf_unfiltered ("\tDR%d: lo=%s, hi=%s\n", i, |
f5656ead | 503 | paddress (target_gdbarch (), |
b3436450 YQ |
504 | mips_linux_watch_get_watchlo (&watch_mirror, |
505 | i)), | |
f5656ead | 506 | paddress (target_gdbarch (), |
b3436450 YQ |
507 | mips_linux_watch_get_watchhi (&watch_mirror, |
508 | i))); | |
b9412953 DD |
509 | } |
510 | ||
b9412953 DD |
511 | /* Target to_can_use_hw_breakpoint implementation. Return 1 if we can |
512 | handle the specified watch type. */ | |
513 | ||
514 | static int | |
5461485a TT |
515 | mips_linux_can_use_hw_breakpoint (struct target_ops *self, |
516 | int type, int cnt, int ot) | |
b9412953 DD |
517 | { |
518 | int i; | |
519 | uint32_t wanted_mask, irw_mask; | |
520 | ||
b3436450 YQ |
521 | if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid), |
522 | &watch_readback, | |
523 | &watch_readback_valid, 0)) | |
b9412953 DD |
524 | return 0; |
525 | ||
526 | switch (type) | |
527 | { | |
528 | case bp_hardware_watchpoint: | |
529 | wanted_mask = W_MASK; | |
530 | break; | |
531 | case bp_read_watchpoint: | |
532 | wanted_mask = R_MASK; | |
533 | break; | |
534 | case bp_access_watchpoint: | |
535 | wanted_mask = R_MASK | W_MASK; | |
536 | break; | |
537 | default: | |
538 | return 0; | |
539 | } | |
540 | ||
b3436450 YQ |
541 | for (i = 0; |
542 | i < mips_linux_watch_get_num_valid (&watch_readback) && cnt; | |
543 | i++) | |
b9412953 | 544 | { |
b3436450 | 545 | irw_mask = mips_linux_watch_get_irw_mask (&watch_readback, i); |
b9412953 DD |
546 | if ((irw_mask & wanted_mask) == wanted_mask) |
547 | cnt--; | |
548 | } | |
549 | return (cnt == 0) ? 1 : 0; | |
550 | } | |
551 | ||
552 | /* Target to_stopped_by_watchpoint implementation. Return 1 if | |
553 | stopped by watchpoint. The watchhi R and W bits indicate the watch | |
025bb325 | 554 | register triggered. */ |
b9412953 DD |
555 | |
556 | static int | |
6a109b6b | 557 | mips_linux_stopped_by_watchpoint (struct target_ops *ops) |
b9412953 DD |
558 | { |
559 | int n; | |
560 | int num_valid; | |
561 | ||
b3436450 YQ |
562 | if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid), |
563 | &watch_readback, | |
564 | &watch_readback_valid, 1)) | |
b9412953 DD |
565 | return 0; |
566 | ||
b3436450 | 567 | num_valid = mips_linux_watch_get_num_valid (&watch_readback); |
b9412953 DD |
568 | |
569 | for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++) | |
b3436450 | 570 | if (mips_linux_watch_get_watchhi (&watch_readback, n) & (R_MASK | W_MASK)) |
b9412953 DD |
571 | return 1; |
572 | ||
573 | return 0; | |
574 | } | |
575 | ||
576 | /* Target to_stopped_data_address implementation. Set the address | |
577 | where the watch triggered (if known). Return 1 if the address was | |
578 | known. */ | |
579 | ||
580 | static int | |
581 | mips_linux_stopped_data_address (struct target_ops *t, CORE_ADDR *paddr) | |
582 | { | |
583 | /* On mips we don't know the low order 3 bits of the data address, | |
584 | so we must return false. */ | |
585 | return 0; | |
586 | } | |
587 | ||
b9412953 DD |
588 | /* Target to_region_ok_for_hw_watchpoint implementation. Return 1 if |
589 | the specified region can be covered by the watch registers. */ | |
590 | ||
591 | static int | |
31568a15 TT |
592 | mips_linux_region_ok_for_hw_watchpoint (struct target_ops *self, |
593 | CORE_ADDR addr, int len) | |
b9412953 DD |
594 | { |
595 | struct pt_watch_regs dummy_regs; | |
596 | int i; | |
597 | ||
b3436450 YQ |
598 | if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid), |
599 | &watch_readback, | |
600 | &watch_readback_valid, 0)) | |
b9412953 DD |
601 | return 0; |
602 | ||
603 | dummy_regs = watch_readback; | |
604 | /* Clear them out. */ | |
b3436450 YQ |
605 | for (i = 0; i < mips_linux_watch_get_num_valid (&dummy_regs); i++) |
606 | mips_linux_watch_set_watchlo (&dummy_regs, i, 0); | |
607 | return mips_linux_watch_try_one_watch (&dummy_regs, addr, len, 0); | |
b9412953 DD |
608 | } |
609 | ||
b9412953 DD |
610 | /* Write the mirrored watch register values for each thread. */ |
611 | ||
612 | static int | |
613 | write_watchpoint_regs (void) | |
614 | { | |
615 | struct lwp_info *lp; | |
b9412953 DD |
616 | int tid; |
617 | ||
4c38200f | 618 | ALL_LWPS (lp) |
b9412953 | 619 | { |
4c38200f | 620 | tid = ptid_get_lwp (lp->ptid); |
b9412953 DD |
621 | if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror) == -1) |
622 | perror_with_name (_("Couldn't write debug register")); | |
623 | } | |
624 | return 0; | |
625 | } | |
626 | ||
627 | /* linux_nat new_thread implementation. Write the mirrored watch | |
628 | register values for the new thread. */ | |
629 | ||
630 | static void | |
7b50312a | 631 | mips_linux_new_thread (struct lwp_info *lp) |
b9412953 DD |
632 | { |
633 | int tid; | |
634 | ||
b3436450 YQ |
635 | if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid), |
636 | &watch_readback, | |
637 | &watch_readback_valid, 0)) | |
b9412953 DD |
638 | return; |
639 | ||
7b50312a | 640 | tid = ptid_get_lwp (lp->ptid); |
b9412953 DD |
641 | if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror) == -1) |
642 | perror_with_name (_("Couldn't write debug register")); | |
643 | } | |
644 | ||
b9412953 DD |
645 | /* Target to_insert_watchpoint implementation. Try to insert a new |
646 | watch. Return zero on success. */ | |
647 | ||
648 | static int | |
7bb99c53 TT |
649 | mips_linux_insert_watchpoint (struct target_ops *self, |
650 | CORE_ADDR addr, int len, int type, | |
0cf6dd15 | 651 | struct expression *cond) |
b9412953 DD |
652 | { |
653 | struct pt_watch_regs regs; | |
654 | struct mips_watchpoint *new_watch; | |
655 | struct mips_watchpoint **pw; | |
656 | ||
657 | int i; | |
658 | int retval; | |
659 | ||
b3436450 YQ |
660 | if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid), |
661 | &watch_readback, | |
662 | &watch_readback_valid, 0)) | |
b9412953 DD |
663 | return -1; |
664 | ||
665 | if (len <= 0) | |
666 | return -1; | |
667 | ||
668 | regs = watch_readback; | |
669 | /* Add the current watches. */ | |
b3436450 | 670 | mips_linux_watch_populate_regs (current_watches, ®s); |
b9412953 DD |
671 | |
672 | /* Now try to add the new watch. */ | |
b3436450 YQ |
673 | if (!mips_linux_watch_try_one_watch (®s, addr, len, |
674 | mips_linux_watch_type_to_irw (type))) | |
b9412953 DD |
675 | return -1; |
676 | ||
677 | /* It fit. Stick it on the end of the list. */ | |
678 | new_watch = (struct mips_watchpoint *) | |
679 | xmalloc (sizeof (struct mips_watchpoint)); | |
680 | new_watch->addr = addr; | |
681 | new_watch->len = len; | |
682 | new_watch->type = type; | |
683 | new_watch->next = NULL; | |
684 | ||
685 | pw = ¤t_watches; | |
686 | while (*pw != NULL) | |
687 | pw = &(*pw)->next; | |
688 | *pw = new_watch; | |
689 | ||
690 | watch_mirror = regs; | |
691 | retval = write_watchpoint_regs (); | |
692 | ||
693 | if (maint_show_dr) | |
694 | mips_show_dr ("insert_watchpoint", addr, len, type); | |
695 | ||
696 | return retval; | |
697 | } | |
698 | ||
699 | /* Target to_remove_watchpoint implementation. Try to remove a watch. | |
700 | Return zero on success. */ | |
701 | ||
702 | static int | |
11b5219a TT |
703 | mips_linux_remove_watchpoint (struct target_ops *self, |
704 | CORE_ADDR addr, int len, int type, | |
0cf6dd15 | 705 | struct expression *cond) |
b9412953 DD |
706 | { |
707 | int retval; | |
708 | int deleted_one; | |
709 | ||
710 | struct mips_watchpoint **pw; | |
711 | struct mips_watchpoint *w; | |
712 | ||
713 | /* Search for a known watch that matches. Then unlink and free | |
714 | it. */ | |
715 | deleted_one = 0; | |
716 | pw = ¤t_watches; | |
717 | while ((w = *pw)) | |
718 | { | |
719 | if (w->addr == addr && w->len == len && w->type == type) | |
720 | { | |
721 | *pw = w->next; | |
722 | xfree (w); | |
723 | deleted_one = 1; | |
724 | break; | |
725 | } | |
726 | pw = &(w->next); | |
727 | } | |
728 | ||
729 | if (!deleted_one) | |
730 | return -1; /* We don't know about it, fail doing nothing. */ | |
731 | ||
732 | /* At this point watch_readback is known to be valid because we | |
733 | could not have added the watch without reading it. */ | |
734 | gdb_assert (watch_readback_valid == 1); | |
735 | ||
736 | watch_mirror = watch_readback; | |
b3436450 | 737 | mips_linux_watch_populate_regs (current_watches, &watch_mirror); |
b9412953 DD |
738 | |
739 | retval = write_watchpoint_regs (); | |
740 | ||
741 | if (maint_show_dr) | |
742 | mips_show_dr ("remove_watchpoint", addr, len, type); | |
743 | ||
744 | return retval; | |
745 | } | |
746 | ||
747 | /* Target to_close implementation. Free any watches and call the | |
748 | super implementation. */ | |
749 | ||
750 | static void | |
de90e03d | 751 | mips_linux_close (struct target_ops *self) |
b9412953 DD |
752 | { |
753 | struct mips_watchpoint *w; | |
754 | struct mips_watchpoint *nw; | |
755 | ||
756 | /* Clean out the current_watches list. */ | |
757 | w = current_watches; | |
758 | while (w) | |
759 | { | |
760 | nw = w->next; | |
761 | xfree (w); | |
762 | w = nw; | |
763 | } | |
764 | current_watches = NULL; | |
765 | ||
766 | if (super_close) | |
93063aa6 | 767 | super_close (self); |
b9412953 DD |
768 | } |
769 | ||
10d6c8cd DJ |
770 | void _initialize_mips_linux_nat (void); |
771 | ||
772 | void | |
773 | _initialize_mips_linux_nat (void) | |
774 | { | |
b9412953 DD |
775 | struct target_ops *t; |
776 | ||
cbe54154 PA |
777 | add_setshow_boolean_cmd ("show-debug-regs", class_maintenance, |
778 | &maint_show_dr, _("\ | |
779 | Set whether to show variables that mirror the mips debug registers."), _("\ | |
780 | Show whether to show variables that mirror the mips debug registers."), _("\ | |
b9412953 DD |
781 | Use \"on\" to enable, \"off\" to disable.\n\ |
782 | If enabled, the debug registers values are shown when GDB inserts\n\ | |
783 | or removes a hardware breakpoint or watchpoint, and when the inferior\n\ | |
784 | triggers a breakpoint or watchpoint."), | |
cbe54154 PA |
785 | NULL, |
786 | NULL, | |
787 | &maintenance_set_cmdlist, | |
788 | &maintenance_show_cmdlist); | |
b9412953 DD |
789 | |
790 | t = linux_trad_target (mips_linux_register_u_offset); | |
791 | ||
792 | super_close = t->to_close; | |
793 | t->to_close = mips_linux_close; | |
d37eb719 DJ |
794 | |
795 | super_fetch_registers = t->to_fetch_registers; | |
796 | super_store_registers = t->to_store_registers; | |
797 | ||
798 | t->to_fetch_registers = mips64_linux_fetch_registers; | |
799 | t->to_store_registers = mips64_linux_store_registers; | |
800 | ||
b9412953 DD |
801 | t->to_can_use_hw_breakpoint = mips_linux_can_use_hw_breakpoint; |
802 | t->to_remove_watchpoint = mips_linux_remove_watchpoint; | |
803 | t->to_insert_watchpoint = mips_linux_insert_watchpoint; | |
804 | t->to_stopped_by_watchpoint = mips_linux_stopped_by_watchpoint; | |
805 | t->to_stopped_data_address = mips_linux_stopped_data_address; | |
806 | t->to_region_ok_for_hw_watchpoint = mips_linux_region_ok_for_hw_watchpoint; | |
807 | ||
81adfced | 808 | t->to_read_description = mips_linux_read_description; |
822b6570 | 809 | |
f973ed9c | 810 | linux_nat_add_target (t); |
b9412953 | 811 | linux_nat_set_new_thread (t, mips_linux_new_thread); |
81adfced DJ |
812 | |
813 | /* Initialize the standard target descriptions. */ | |
814 | initialize_tdesc_mips_linux (); | |
1faeff08 | 815 | initialize_tdesc_mips_dsp_linux (); |
81adfced | 816 | initialize_tdesc_mips64_linux (); |
1faeff08 | 817 | initialize_tdesc_mips64_dsp_linux (); |
10d6c8cd | 818 | } |