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75c9abc6 | 1 | /* Native-dependent code for GNU/Linux on MIPS processors. |
a094c6fb | 2 | |
0b302171 | 3 | Copyright (C) 2001-2012 Free Software Foundation, Inc. |
2aa830e4 DJ |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
2aa830e4 DJ |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
2aa830e4 DJ |
19 | |
20 | #include "defs.h" | |
b9412953 DD |
21 | #include "command.h" |
22 | #include "gdbcmd.h" | |
23 | #include "gdb_assert.h" | |
d37eb719 | 24 | #include "inferior.h" |
6b753f60 | 25 | #include "mips-tdep.h" |
10d6c8cd | 26 | #include "target.h" |
28f5035f | 27 | #include "regcache.h" |
10d6c8cd | 28 | #include "linux-nat.h" |
d37eb719 | 29 | #include "mips-linux-tdep.h" |
822b6570 | 30 | #include "target-descriptions.h" |
2aa830e4 | 31 | |
dc60ece8 | 32 | #include "gdb_proc_service.h" |
3e00823e | 33 | #include "gregset.h" |
dc60ece8 | 34 | |
822b6570 | 35 | #include <sgidefs.h> |
d37eb719 DJ |
36 | #include <sys/ptrace.h> |
37 | ||
81adfced | 38 | #include "features/mips-linux.c" |
1faeff08 | 39 | #include "features/mips-dsp-linux.c" |
81adfced | 40 | #include "features/mips64-linux.c" |
1faeff08 | 41 | #include "features/mips64-dsp-linux.c" |
81adfced | 42 | |
dc60ece8 DJ |
43 | #ifndef PTRACE_GET_THREAD_AREA |
44 | #define PTRACE_GET_THREAD_AREA 25 | |
45 | #endif | |
46 | ||
d37eb719 DJ |
47 | /* Assume that we have PTRACE_GETREGS et al. support. If we do not, |
48 | we'll clear this and use PTRACE_PEEKUSER instead. */ | |
49 | static int have_ptrace_regsets = 1; | |
50 | ||
b9412953 DD |
51 | /* Whether or not to print the mirrored debug registers. */ |
52 | ||
53 | static int maint_show_dr; | |
54 | ||
d37eb719 DJ |
55 | /* Saved function pointers to fetch and store a single register using |
56 | PTRACE_PEEKUSER and PTRACE_POKEUSER. */ | |
57 | ||
b9412953 DD |
58 | static void (*super_fetch_registers) (struct target_ops *, |
59 | struct regcache *, int); | |
60 | static void (*super_store_registers) (struct target_ops *, | |
61 | struct regcache *, int); | |
62 | ||
63 | static void (*super_close) (int); | |
d37eb719 | 64 | |
dda0c97e | 65 | /* Map gdb internal register number to ptrace ``address''. |
7714d83a UW |
66 | These ``addresses'' are normally defined in <asm/ptrace.h>. |
67 | ||
68 | ptrace does not provide a way to read (or set) MIPS_PS_REGNUM, | |
69 | and there's no point in reading or setting MIPS_ZERO_REGNUM. | |
70 | We also can not set BADVADDR, CAUSE, or FCRIR via ptrace(). */ | |
dda0c97e UW |
71 | |
72 | static CORE_ADDR | |
7714d83a | 73 | mips_linux_register_addr (struct gdbarch *gdbarch, int regno, int store) |
dda0c97e | 74 | { |
7714d83a | 75 | CORE_ADDR regaddr; |
dda0c97e | 76 | |
2eb4d78b | 77 | if (regno < 0 || regno >= gdbarch_num_regs (gdbarch)) |
dda0c97e UW |
78 | error (_("Bogon register number %d."), regno); |
79 | ||
7714d83a | 80 | if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32) |
dda0c97e | 81 | regaddr = regno; |
7714d83a UW |
82 | else if ((regno >= mips_regnum (gdbarch)->fp0) |
83 | && (regno < mips_regnum (gdbarch)->fp0 + 32)) | |
84 | regaddr = FPR_BASE + (regno - mips_regnum (gdbarch)->fp0); | |
85 | else if (regno == mips_regnum (gdbarch)->pc) | |
dda0c97e | 86 | regaddr = PC; |
7714d83a UW |
87 | else if (regno == mips_regnum (gdbarch)->cause) |
88 | regaddr = store? (CORE_ADDR) -1 : CAUSE; | |
89 | else if (regno == mips_regnum (gdbarch)->badvaddr) | |
90 | regaddr = store? (CORE_ADDR) -1 : BADVADDR; | |
91 | else if (regno == mips_regnum (gdbarch)->lo) | |
dda0c97e | 92 | regaddr = MMLO; |
7714d83a | 93 | else if (regno == mips_regnum (gdbarch)->hi) |
dda0c97e | 94 | regaddr = MMHI; |
7714d83a | 95 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
dda0c97e | 96 | regaddr = FPC_CSR; |
7714d83a UW |
97 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
98 | regaddr = store? (CORE_ADDR) -1 : FPC_EIR; | |
1faeff08 MR |
99 | else if (mips_regnum (gdbarch)->dspacc != -1 |
100 | && regno >= mips_regnum (gdbarch)->dspacc | |
101 | && regno < mips_regnum (gdbarch)->dspacc + 6) | |
102 | regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc); | |
103 | else if (regno == mips_regnum (gdbarch)->dspctl) | |
104 | regaddr = DSP_CONTROL; | |
822b6570 DJ |
105 | else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM) |
106 | regaddr = 0; | |
dda0c97e | 107 | else |
7714d83a | 108 | regaddr = (CORE_ADDR) -1; |
dda0c97e UW |
109 | |
110 | return regaddr; | |
111 | } | |
112 | ||
113 | static CORE_ADDR | |
7714d83a | 114 | mips64_linux_register_addr (struct gdbarch *gdbarch, int regno, int store) |
dda0c97e | 115 | { |
7714d83a | 116 | CORE_ADDR regaddr; |
dda0c97e | 117 | |
2eb4d78b | 118 | if (regno < 0 || regno >= gdbarch_num_regs (gdbarch)) |
dda0c97e UW |
119 | error (_("Bogon register number %d."), regno); |
120 | ||
7714d83a | 121 | if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32) |
dda0c97e | 122 | regaddr = regno; |
7714d83a UW |
123 | else if ((regno >= mips_regnum (gdbarch)->fp0) |
124 | && (regno < mips_regnum (gdbarch)->fp0 + 32)) | |
2eb4d78b | 125 | regaddr = MIPS64_FPR_BASE + (regno - gdbarch_fp0_regnum (gdbarch)); |
7714d83a | 126 | else if (regno == mips_regnum (gdbarch)->pc) |
dda0c97e | 127 | regaddr = MIPS64_PC; |
7714d83a UW |
128 | else if (regno == mips_regnum (gdbarch)->cause) |
129 | regaddr = store? (CORE_ADDR) -1 : MIPS64_CAUSE; | |
130 | else if (regno == mips_regnum (gdbarch)->badvaddr) | |
131 | regaddr = store? (CORE_ADDR) -1 : MIPS64_BADVADDR; | |
132 | else if (regno == mips_regnum (gdbarch)->lo) | |
dda0c97e | 133 | regaddr = MIPS64_MMLO; |
7714d83a | 134 | else if (regno == mips_regnum (gdbarch)->hi) |
dda0c97e | 135 | regaddr = MIPS64_MMHI; |
7714d83a | 136 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
dda0c97e | 137 | regaddr = MIPS64_FPC_CSR; |
7714d83a UW |
138 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
139 | regaddr = store? (CORE_ADDR) -1 : MIPS64_FPC_EIR; | |
1faeff08 MR |
140 | else if (mips_regnum (gdbarch)->dspacc != -1 |
141 | && regno >= mips_regnum (gdbarch)->dspacc | |
142 | && regno < mips_regnum (gdbarch)->dspacc + 6) | |
143 | regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc); | |
144 | else if (regno == mips_regnum (gdbarch)->dspctl) | |
145 | regaddr = DSP_CONTROL; | |
822b6570 DJ |
146 | else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM) |
147 | regaddr = 0; | |
dda0c97e | 148 | else |
7714d83a | 149 | regaddr = (CORE_ADDR) -1; |
dda0c97e UW |
150 | |
151 | return regaddr; | |
152 | } | |
153 | ||
dc60ece8 DJ |
154 | /* Fetch the thread-local storage pointer for libthread_db. */ |
155 | ||
156 | ps_err_e | |
157 | ps_get_thread_area (const struct ps_prochandle *ph, | |
158 | lwpid_t lwpid, int idx, void **base) | |
159 | { | |
160 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
161 | return PS_ERR; | |
162 | ||
163 | /* IDX is the bias from the thread pointer to the beginning of the | |
164 | thread descriptor. It has to be subtracted due to implementation | |
165 | quirks in libthread_db. */ | |
166 | *base = (void *) ((char *)*base - idx); | |
167 | ||
168 | return PS_OK; | |
169 | } | |
170 | ||
3e00823e UW |
171 | /* Wrapper functions. These are only used by libthread_db. */ |
172 | ||
173 | void | |
7f7fe91e | 174 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
3e00823e | 175 | { |
2eb4d78b | 176 | if (mips_isa_regsize (get_regcache_arch (regcache)) == 4) |
7f7fe91e | 177 | mips_supply_gregset (regcache, (const mips_elf_gregset_t *) gregsetp); |
3e00823e | 178 | else |
7f7fe91e | 179 | mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *) gregsetp); |
3e00823e UW |
180 | } |
181 | ||
182 | void | |
7f7fe91e UW |
183 | fill_gregset (const struct regcache *regcache, |
184 | gdb_gregset_t *gregsetp, int regno) | |
3e00823e | 185 | { |
2eb4d78b | 186 | if (mips_isa_regsize (get_regcache_arch (regcache)) == 4) |
7f7fe91e | 187 | mips_fill_gregset (regcache, (mips_elf_gregset_t *) gregsetp, regno); |
3e00823e | 188 | else |
7f7fe91e | 189 | mips64_fill_gregset (regcache, (mips64_elf_gregset_t *) gregsetp, regno); |
3e00823e UW |
190 | } |
191 | ||
192 | void | |
7f7fe91e | 193 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) |
3e00823e | 194 | { |
2eb4d78b | 195 | if (mips_isa_regsize (get_regcache_arch (regcache)) == 4) |
7f7fe91e | 196 | mips_supply_fpregset (regcache, (const mips_elf_fpregset_t *) fpregsetp); |
3e00823e | 197 | else |
025bb325 MS |
198 | mips64_supply_fpregset (regcache, |
199 | (const mips64_elf_fpregset_t *) fpregsetp); | |
3e00823e UW |
200 | } |
201 | ||
202 | void | |
7f7fe91e UW |
203 | fill_fpregset (const struct regcache *regcache, |
204 | gdb_fpregset_t *fpregsetp, int regno) | |
3e00823e | 205 | { |
2eb4d78b | 206 | if (mips_isa_regsize (get_regcache_arch (regcache)) == 4) |
7f7fe91e | 207 | mips_fill_fpregset (regcache, (mips_elf_fpregset_t *) fpregsetp, regno); |
3e00823e | 208 | else |
025bb325 MS |
209 | mips64_fill_fpregset (regcache, |
210 | (mips64_elf_fpregset_t *) fpregsetp, regno); | |
3e00823e UW |
211 | } |
212 | ||
213 | ||
d37eb719 DJ |
214 | /* Fetch REGNO (or all registers if REGNO == -1) from the target |
215 | using PTRACE_GETREGS et al. */ | |
216 | ||
217 | static void | |
1faeff08 MR |
218 | mips64_linux_regsets_fetch_registers (struct target_ops *ops, |
219 | struct regcache *regcache, int regno) | |
d37eb719 | 220 | { |
2eb4d78b | 221 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1faeff08 MR |
222 | int is_fp, is_dsp; |
223 | int have_dsp; | |
224 | int regi; | |
d37eb719 DJ |
225 | int tid; |
226 | ||
2eb4d78b UW |
227 | if (regno >= mips_regnum (gdbarch)->fp0 |
228 | && regno <= mips_regnum (gdbarch)->fp0 + 32) | |
d37eb719 | 229 | is_fp = 1; |
2eb4d78b | 230 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
d37eb719 | 231 | is_fp = 1; |
2eb4d78b | 232 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
d37eb719 DJ |
233 | is_fp = 1; |
234 | else | |
235 | is_fp = 0; | |
236 | ||
1faeff08 MR |
237 | /* DSP registers are optional and not a part of any set. */ |
238 | have_dsp = mips_regnum (gdbarch)->dspctl != -1; | |
239 | if (!have_dsp) | |
240 | is_dsp = 0; | |
241 | else if (regno >= mips_regnum (gdbarch)->dspacc | |
242 | && regno < mips_regnum (gdbarch)->dspacc + 6) | |
243 | is_dsp = 1; | |
244 | else if (regno == mips_regnum (gdbarch)->dspctl) | |
245 | is_dsp = 1; | |
246 | else | |
247 | is_dsp = 0; | |
248 | ||
d37eb719 DJ |
249 | tid = ptid_get_lwp (inferior_ptid); |
250 | if (tid == 0) | |
251 | tid = ptid_get_pid (inferior_ptid); | |
252 | ||
1faeff08 | 253 | if (regno == -1 || (!is_fp && !is_dsp)) |
d37eb719 DJ |
254 | { |
255 | mips64_elf_gregset_t regs; | |
256 | ||
257 | if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1) | |
258 | { | |
259 | if (errno == EIO) | |
260 | { | |
261 | have_ptrace_regsets = 0; | |
262 | return; | |
263 | } | |
264 | perror_with_name (_("Couldn't get registers")); | |
265 | } | |
266 | ||
56be3814 | 267 | mips64_supply_gregset (regcache, |
28f5035f | 268 | (const mips64_elf_gregset_t *) ®s); |
d37eb719 DJ |
269 | } |
270 | ||
271 | if (regno == -1 || is_fp) | |
272 | { | |
273 | mips64_elf_fpregset_t fp_regs; | |
274 | ||
275 | if (ptrace (PTRACE_GETFPREGS, tid, 0L, | |
276 | (PTRACE_TYPE_ARG3) &fp_regs) == -1) | |
277 | { | |
278 | if (errno == EIO) | |
279 | { | |
280 | have_ptrace_regsets = 0; | |
281 | return; | |
282 | } | |
283 | perror_with_name (_("Couldn't get FP registers")); | |
284 | } | |
285 | ||
56be3814 | 286 | mips64_supply_fpregset (regcache, |
28f5035f | 287 | (const mips64_elf_fpregset_t *) &fp_regs); |
d37eb719 | 288 | } |
1faeff08 MR |
289 | |
290 | if (is_dsp) | |
291 | super_fetch_registers (ops, regcache, regno); | |
292 | else if (regno == -1 && have_dsp) | |
293 | { | |
294 | for (regi = mips_regnum (gdbarch)->dspacc; | |
295 | regi < mips_regnum (gdbarch)->dspacc + 6; | |
296 | regi++) | |
297 | super_fetch_registers (ops, regcache, regi); | |
298 | super_fetch_registers (ops, regcache, mips_regnum (gdbarch)->dspctl); | |
299 | } | |
d37eb719 DJ |
300 | } |
301 | ||
302 | /* Store REGNO (or all registers if REGNO == -1) to the target | |
303 | using PTRACE_SETREGS et al. */ | |
304 | ||
305 | static void | |
1faeff08 MR |
306 | mips64_linux_regsets_store_registers (struct target_ops *ops, |
307 | struct regcache *regcache, int regno) | |
d37eb719 | 308 | { |
2eb4d78b | 309 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1faeff08 MR |
310 | int is_fp, is_dsp; |
311 | int have_dsp; | |
312 | int regi; | |
d37eb719 DJ |
313 | int tid; |
314 | ||
2eb4d78b UW |
315 | if (regno >= mips_regnum (gdbarch)->fp0 |
316 | && regno <= mips_regnum (gdbarch)->fp0 + 32) | |
d37eb719 | 317 | is_fp = 1; |
2eb4d78b | 318 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
d37eb719 | 319 | is_fp = 1; |
2eb4d78b | 320 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
d37eb719 DJ |
321 | is_fp = 1; |
322 | else | |
323 | is_fp = 0; | |
324 | ||
1faeff08 MR |
325 | /* DSP registers are optional and not a part of any set. */ |
326 | have_dsp = mips_regnum (gdbarch)->dspctl != -1; | |
327 | if (!have_dsp) | |
328 | is_dsp = 0; | |
329 | if (regno >= mips_regnum (gdbarch)->dspacc | |
330 | && regno < mips_regnum (gdbarch)->dspacc + 6) | |
331 | is_dsp = 1; | |
332 | else if (regno == mips_regnum (gdbarch)->dspctl) | |
333 | is_dsp = 1; | |
334 | else | |
335 | is_dsp = 0; | |
336 | ||
d37eb719 DJ |
337 | tid = ptid_get_lwp (inferior_ptid); |
338 | if (tid == 0) | |
339 | tid = ptid_get_pid (inferior_ptid); | |
340 | ||
1faeff08 | 341 | if (regno == -1 || (!is_fp && !is_dsp)) |
d37eb719 DJ |
342 | { |
343 | mips64_elf_gregset_t regs; | |
344 | ||
345 | if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1) | |
346 | perror_with_name (_("Couldn't get registers")); | |
347 | ||
56be3814 | 348 | mips64_fill_gregset (regcache, ®s, regno); |
d37eb719 DJ |
349 | |
350 | if (ptrace (PTRACE_SETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1) | |
351 | perror_with_name (_("Couldn't set registers")); | |
352 | } | |
353 | ||
354 | if (regno == -1 || is_fp) | |
355 | { | |
356 | mips64_elf_fpregset_t fp_regs; | |
357 | ||
358 | if (ptrace (PTRACE_GETFPREGS, tid, 0L, | |
359 | (PTRACE_TYPE_ARG3) &fp_regs) == -1) | |
360 | perror_with_name (_("Couldn't get FP registers")); | |
361 | ||
56be3814 | 362 | mips64_fill_fpregset (regcache, &fp_regs, regno); |
d37eb719 DJ |
363 | |
364 | if (ptrace (PTRACE_SETFPREGS, tid, 0L, | |
365 | (PTRACE_TYPE_ARG3) &fp_regs) == -1) | |
366 | perror_with_name (_("Couldn't set FP registers")); | |
367 | } | |
1faeff08 MR |
368 | |
369 | if (is_dsp) | |
370 | super_store_registers (ops, regcache, regno); | |
371 | else if (regno == -1 && have_dsp) | |
372 | { | |
373 | for (regi = mips_regnum (gdbarch)->dspacc; | |
374 | regi < mips_regnum (gdbarch)->dspacc + 6; | |
375 | regi++) | |
376 | super_store_registers (ops, regcache, regi); | |
377 | super_store_registers (ops, regcache, mips_regnum (gdbarch)->dspctl); | |
378 | } | |
d37eb719 DJ |
379 | } |
380 | ||
381 | /* Fetch REGNO (or all registers if REGNO == -1) from the target | |
382 | using any working method. */ | |
383 | ||
384 | static void | |
28439f5e PA |
385 | mips64_linux_fetch_registers (struct target_ops *ops, |
386 | struct regcache *regcache, int regnum) | |
d37eb719 DJ |
387 | { |
388 | /* Unless we already know that PTRACE_GETREGS does not work, try it. */ | |
389 | if (have_ptrace_regsets) | |
1faeff08 | 390 | mips64_linux_regsets_fetch_registers (ops, regcache, regnum); |
d37eb719 DJ |
391 | |
392 | /* If we know, or just found out, that PTRACE_GETREGS does not work, fall | |
393 | back to PTRACE_PEEKUSER. */ | |
394 | if (!have_ptrace_regsets) | |
a0740d21 | 395 | super_fetch_registers (ops, regcache, regnum); |
d37eb719 DJ |
396 | } |
397 | ||
398 | /* Store REGNO (or all registers if REGNO == -1) to the target | |
399 | using any working method. */ | |
400 | ||
401 | static void | |
28439f5e PA |
402 | mips64_linux_store_registers (struct target_ops *ops, |
403 | struct regcache *regcache, int regnum) | |
d37eb719 DJ |
404 | { |
405 | /* Unless we already know that PTRACE_GETREGS does not work, try it. */ | |
406 | if (have_ptrace_regsets) | |
1faeff08 | 407 | mips64_linux_regsets_store_registers (ops, regcache, regnum); |
d37eb719 DJ |
408 | |
409 | /* If we know, or just found out, that PTRACE_GETREGS does not work, fall | |
410 | back to PTRACE_PEEKUSER. */ | |
411 | if (!have_ptrace_regsets) | |
a0740d21 | 412 | super_store_registers (ops, regcache, regnum); |
d37eb719 DJ |
413 | } |
414 | ||
910122bf UW |
415 | /* Return the address in the core dump or inferior of register |
416 | REGNO. */ | |
417 | ||
418 | static CORE_ADDR | |
7714d83a | 419 | mips_linux_register_u_offset (struct gdbarch *gdbarch, int regno, int store_p) |
910122bf | 420 | { |
7714d83a UW |
421 | if (mips_abi_regsize (gdbarch) == 8) |
422 | return mips64_linux_register_addr (gdbarch, regno, store_p); | |
dda0c97e | 423 | else |
7714d83a | 424 | return mips_linux_register_addr (gdbarch, regno, store_p); |
910122bf UW |
425 | } |
426 | ||
81adfced DJ |
427 | static const struct target_desc * |
428 | mips_linux_read_description (struct target_ops *ops) | |
822b6570 | 429 | { |
1faeff08 MR |
430 | static int have_dsp = -1; |
431 | ||
432 | if (have_dsp < 0) | |
433 | { | |
434 | int tid; | |
435 | ||
436 | tid = ptid_get_lwp (inferior_ptid); | |
437 | if (tid == 0) | |
438 | tid = ptid_get_pid (inferior_ptid); | |
439 | ||
440 | ptrace (PTRACE_PEEKUSER, tid, DSP_CONTROL, 0); | |
441 | switch (errno) | |
442 | { | |
443 | case 0: | |
444 | have_dsp = 1; | |
445 | break; | |
446 | case EIO: | |
447 | have_dsp = 0; | |
448 | break; | |
449 | default: | |
837a1b32 | 450 | perror_with_name (_("Couldn't check DSP support")); |
1faeff08 MR |
451 | break; |
452 | } | |
453 | } | |
454 | ||
81adfced DJ |
455 | /* Report that target registers are a size we know for sure |
456 | that we can get from ptrace. */ | |
457 | if (_MIPS_SIM == _ABIO32) | |
1faeff08 | 458 | return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux; |
81adfced | 459 | else |
1faeff08 | 460 | return have_dsp ? tdesc_mips64_dsp_linux : tdesc_mips64_linux; |
822b6570 DJ |
461 | } |
462 | ||
b9412953 DD |
463 | #ifndef PTRACE_GET_WATCH_REGS |
464 | # define PTRACE_GET_WATCH_REGS 0xd0 | |
465 | #endif | |
466 | ||
467 | #ifndef PTRACE_SET_WATCH_REGS | |
468 | # define PTRACE_SET_WATCH_REGS 0xd1 | |
469 | #endif | |
470 | ||
471 | #define W_BIT 0 | |
472 | #define R_BIT 1 | |
473 | #define I_BIT 2 | |
474 | ||
475 | #define W_MASK (1 << W_BIT) | |
476 | #define R_MASK (1 << R_BIT) | |
477 | #define I_MASK (1 << I_BIT) | |
478 | ||
479 | #define IRW_MASK (I_MASK | R_MASK | W_MASK) | |
480 | ||
481 | enum pt_watch_style { | |
482 | pt_watch_style_mips32, | |
483 | pt_watch_style_mips64 | |
484 | }; | |
485 | ||
486 | #define MAX_DEBUG_REGISTER 8 | |
487 | ||
025bb325 | 488 | /* A value of zero in a watchlo indicates that it is available. */ |
b9412953 DD |
489 | |
490 | struct mips32_watch_regs | |
491 | { | |
492 | uint32_t watchlo[MAX_DEBUG_REGISTER]; | |
025bb325 | 493 | /* Lower 16 bits of watchhi. */ |
b9412953 DD |
494 | uint16_t watchhi[MAX_DEBUG_REGISTER]; |
495 | /* Valid mask and I R W bits. | |
496 | * bit 0 -- 1 if W bit is usable. | |
497 | * bit 1 -- 1 if R bit is usable. | |
498 | * bit 2 -- 1 if I bit is usable. | |
499 | * bits 3 - 11 -- Valid watchhi mask bits. | |
500 | */ | |
501 | uint16_t watch_masks[MAX_DEBUG_REGISTER]; | |
502 | /* The number of valid watch register pairs. */ | |
503 | uint32_t num_valid; | |
504 | /* There is confusion across gcc versions about structure alignment, | |
505 | so we force 8 byte alignment for these structures so they match | |
506 | the kernel even if it was build with a different gcc version. */ | |
507 | } __attribute__ ((aligned (8))); | |
508 | ||
509 | struct mips64_watch_regs | |
510 | { | |
511 | uint64_t watchlo[MAX_DEBUG_REGISTER]; | |
512 | uint16_t watchhi[MAX_DEBUG_REGISTER]; | |
513 | uint16_t watch_masks[MAX_DEBUG_REGISTER]; | |
514 | uint32_t num_valid; | |
515 | } __attribute__ ((aligned (8))); | |
516 | ||
517 | struct pt_watch_regs | |
518 | { | |
519 | enum pt_watch_style style; | |
520 | union | |
521 | { | |
522 | struct mips32_watch_regs mips32; | |
523 | struct mips64_watch_regs mips64; | |
524 | }; | |
525 | }; | |
526 | ||
527 | /* -1 if the kernel and/or CPU do not support watch registers. | |
528 | 1 if watch_readback is valid and we can read style, num_valid | |
529 | and the masks. | |
530 | 0 if we need to read the watch_readback. */ | |
531 | ||
532 | static int watch_readback_valid; | |
533 | ||
534 | /* Cached watch register read values. */ | |
535 | ||
536 | static struct pt_watch_regs watch_readback; | |
537 | ||
538 | /* We keep list of all watchpoints we should install and calculate the | |
539 | watch register values each time the list changes. This allows for | |
540 | easy sharing of watch registers for more than one watchpoint. */ | |
541 | ||
542 | struct mips_watchpoint | |
543 | { | |
544 | CORE_ADDR addr; | |
545 | int len; | |
546 | int type; | |
547 | struct mips_watchpoint *next; | |
548 | }; | |
549 | ||
550 | static struct mips_watchpoint *current_watches; | |
551 | ||
552 | /* The current set of watch register values for writing the | |
553 | registers. */ | |
554 | ||
555 | static struct pt_watch_regs watch_mirror; | |
556 | ||
557 | /* Assuming usable watch registers, return the irw_mask. */ | |
558 | ||
559 | static uint32_t | |
560 | get_irw_mask (struct pt_watch_regs *regs, int set) | |
561 | { | |
562 | switch (regs->style) | |
563 | { | |
564 | case pt_watch_style_mips32: | |
565 | return regs->mips32.watch_masks[set] & IRW_MASK; | |
566 | case pt_watch_style_mips64: | |
567 | return regs->mips64.watch_masks[set] & IRW_MASK; | |
568 | default: | |
569 | internal_error (__FILE__, __LINE__, | |
570 | _("Unrecognized watch register style")); | |
571 | } | |
572 | } | |
573 | ||
574 | /* Assuming usable watch registers, return the reg_mask. */ | |
575 | ||
576 | static uint32_t | |
577 | get_reg_mask (struct pt_watch_regs *regs, int set) | |
578 | { | |
579 | switch (regs->style) | |
580 | { | |
581 | case pt_watch_style_mips32: | |
582 | return regs->mips32.watch_masks[set] & ~IRW_MASK; | |
583 | case pt_watch_style_mips64: | |
584 | return regs->mips64.watch_masks[set] & ~IRW_MASK; | |
585 | default: | |
586 | internal_error (__FILE__, __LINE__, | |
587 | _("Unrecognized watch register style")); | |
588 | } | |
589 | } | |
590 | ||
591 | /* Assuming usable watch registers, return the num_valid. */ | |
592 | ||
593 | static uint32_t | |
594 | get_num_valid (struct pt_watch_regs *regs) | |
595 | { | |
596 | switch (regs->style) | |
597 | { | |
598 | case pt_watch_style_mips32: | |
599 | return regs->mips32.num_valid; | |
600 | case pt_watch_style_mips64: | |
601 | return regs->mips64.num_valid; | |
602 | default: | |
603 | internal_error (__FILE__, __LINE__, | |
604 | _("Unrecognized watch register style")); | |
605 | } | |
606 | } | |
607 | ||
608 | /* Assuming usable watch registers, return the watchlo. */ | |
609 | ||
610 | static CORE_ADDR | |
611 | get_watchlo (struct pt_watch_regs *regs, int set) | |
612 | { | |
613 | switch (regs->style) | |
614 | { | |
615 | case pt_watch_style_mips32: | |
616 | return regs->mips32.watchlo[set]; | |
617 | case pt_watch_style_mips64: | |
618 | return regs->mips64.watchlo[set]; | |
619 | default: | |
620 | internal_error (__FILE__, __LINE__, | |
621 | _("Unrecognized watch register style")); | |
622 | } | |
623 | } | |
624 | ||
625 | /* Assuming usable watch registers, set a watchlo value. */ | |
626 | ||
627 | static void | |
628 | set_watchlo (struct pt_watch_regs *regs, int set, CORE_ADDR value) | |
629 | { | |
630 | switch (regs->style) | |
631 | { | |
632 | case pt_watch_style_mips32: | |
633 | /* The cast will never throw away bits as 64 bit addresses can | |
634 | never be used on a 32 bit kernel. */ | |
635 | regs->mips32.watchlo[set] = (uint32_t)value; | |
636 | break; | |
637 | case pt_watch_style_mips64: | |
638 | regs->mips64.watchlo[set] = value; | |
639 | break; | |
640 | default: | |
641 | internal_error (__FILE__, __LINE__, | |
642 | _("Unrecognized watch register style")); | |
643 | } | |
644 | } | |
645 | ||
646 | /* Assuming usable watch registers, return the watchhi. */ | |
647 | ||
648 | static uint32_t | |
649 | get_watchhi (struct pt_watch_regs *regs, int n) | |
650 | { | |
651 | switch (regs->style) | |
652 | { | |
653 | case pt_watch_style_mips32: | |
654 | return regs->mips32.watchhi[n]; | |
655 | case pt_watch_style_mips64: | |
656 | return regs->mips64.watchhi[n]; | |
657 | default: | |
658 | internal_error (__FILE__, __LINE__, | |
659 | _("Unrecognized watch register style")); | |
660 | } | |
661 | } | |
662 | ||
663 | /* Assuming usable watch registers, set a watchhi value. */ | |
664 | ||
665 | static void | |
666 | set_watchhi (struct pt_watch_regs *regs, int n, uint16_t value) | |
667 | { | |
668 | switch (regs->style) | |
669 | { | |
670 | case pt_watch_style_mips32: | |
671 | regs->mips32.watchhi[n] = value; | |
672 | break; | |
673 | case pt_watch_style_mips64: | |
674 | regs->mips64.watchhi[n] = value; | |
675 | break; | |
676 | default: | |
677 | internal_error (__FILE__, __LINE__, | |
678 | _("Unrecognized watch register style")); | |
679 | } | |
680 | } | |
681 | ||
682 | static void | |
683 | mips_show_dr (const char *func, CORE_ADDR addr, | |
684 | int len, enum target_hw_bp_type type) | |
685 | { | |
686 | int i; | |
687 | ||
688 | puts_unfiltered (func); | |
689 | if (addr || len) | |
5af949e3 UW |
690 | printf_unfiltered (" (addr=%s, len=%d, type=%s)", |
691 | paddress (target_gdbarch, addr), len, | |
b9412953 DD |
692 | type == hw_write ? "data-write" |
693 | : (type == hw_read ? "data-read" | |
694 | : (type == hw_access ? "data-read/write" | |
695 | : (type == hw_execute ? "instruction-execute" | |
696 | : "??unknown??")))); | |
697 | puts_unfiltered (":\n"); | |
698 | ||
699 | for (i = 0; i < MAX_DEBUG_REGISTER; i++) | |
5af949e3 UW |
700 | printf_unfiltered ("\tDR%d: lo=%s, hi=%s\n", i, |
701 | paddress (target_gdbarch, | |
702 | get_watchlo (&watch_mirror, i)), | |
703 | paddress (target_gdbarch, | |
704 | get_watchhi (&watch_mirror, i))); | |
b9412953 DD |
705 | } |
706 | ||
707 | /* Return 1 if watch registers are usable. Cached information is used | |
708 | unless force is true. */ | |
709 | ||
710 | static int | |
711 | mips_linux_read_watch_registers (int force) | |
712 | { | |
713 | int tid; | |
714 | ||
715 | if (force || watch_readback_valid == 0) | |
716 | { | |
717 | tid = ptid_get_lwp (inferior_ptid); | |
718 | if (ptrace (PTRACE_GET_WATCH_REGS, tid, &watch_readback) == -1) | |
719 | { | |
720 | watch_readback_valid = -1; | |
721 | return 0; | |
722 | } | |
723 | switch (watch_readback.style) | |
724 | { | |
725 | case pt_watch_style_mips32: | |
726 | if (watch_readback.mips32.num_valid == 0) | |
727 | { | |
728 | watch_readback_valid = -1; | |
729 | return 0; | |
730 | } | |
731 | break; | |
732 | case pt_watch_style_mips64: | |
733 | if (watch_readback.mips64.num_valid == 0) | |
734 | { | |
735 | watch_readback_valid = -1; | |
736 | return 0; | |
737 | } | |
738 | break; | |
739 | default: | |
740 | watch_readback_valid = -1; | |
741 | return 0; | |
742 | } | |
743 | /* Watch registers appear to be usable. */ | |
744 | watch_readback_valid = 1; | |
745 | } | |
746 | return (watch_readback_valid == 1) ? 1 : 0; | |
747 | } | |
748 | ||
749 | /* Convert GDB's type to an IRW mask. */ | |
750 | ||
751 | static unsigned | |
752 | type_to_irw (int type) | |
753 | { | |
754 | switch (type) | |
755 | { | |
756 | case hw_write: | |
757 | return W_MASK; | |
758 | case hw_read: | |
759 | return R_MASK; | |
760 | case hw_access: | |
761 | return (W_MASK | R_MASK); | |
762 | default: | |
763 | return 0; | |
764 | } | |
765 | } | |
766 | ||
767 | /* Target to_can_use_hw_breakpoint implementation. Return 1 if we can | |
768 | handle the specified watch type. */ | |
769 | ||
770 | static int | |
771 | mips_linux_can_use_hw_breakpoint (int type, int cnt, int ot) | |
772 | { | |
773 | int i; | |
774 | uint32_t wanted_mask, irw_mask; | |
775 | ||
776 | if (!mips_linux_read_watch_registers (0)) | |
777 | return 0; | |
778 | ||
779 | switch (type) | |
780 | { | |
781 | case bp_hardware_watchpoint: | |
782 | wanted_mask = W_MASK; | |
783 | break; | |
784 | case bp_read_watchpoint: | |
785 | wanted_mask = R_MASK; | |
786 | break; | |
787 | case bp_access_watchpoint: | |
788 | wanted_mask = R_MASK | W_MASK; | |
789 | break; | |
790 | default: | |
791 | return 0; | |
792 | } | |
793 | ||
794 | for (i = 0; i < get_num_valid (&watch_readback) && cnt; i++) | |
795 | { | |
796 | irw_mask = get_irw_mask (&watch_readback, i); | |
797 | if ((irw_mask & wanted_mask) == wanted_mask) | |
798 | cnt--; | |
799 | } | |
800 | return (cnt == 0) ? 1 : 0; | |
801 | } | |
802 | ||
803 | /* Target to_stopped_by_watchpoint implementation. Return 1 if | |
804 | stopped by watchpoint. The watchhi R and W bits indicate the watch | |
025bb325 | 805 | register triggered. */ |
b9412953 DD |
806 | |
807 | static int | |
808 | mips_linux_stopped_by_watchpoint (void) | |
809 | { | |
810 | int n; | |
811 | int num_valid; | |
812 | ||
813 | if (!mips_linux_read_watch_registers (1)) | |
814 | return 0; | |
815 | ||
816 | num_valid = get_num_valid (&watch_readback); | |
817 | ||
818 | for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++) | |
819 | if (get_watchhi (&watch_readback, n) & (R_MASK | W_MASK)) | |
820 | return 1; | |
821 | ||
822 | return 0; | |
823 | } | |
824 | ||
825 | /* Target to_stopped_data_address implementation. Set the address | |
826 | where the watch triggered (if known). Return 1 if the address was | |
827 | known. */ | |
828 | ||
829 | static int | |
830 | mips_linux_stopped_data_address (struct target_ops *t, CORE_ADDR *paddr) | |
831 | { | |
832 | /* On mips we don't know the low order 3 bits of the data address, | |
833 | so we must return false. */ | |
834 | return 0; | |
835 | } | |
836 | ||
837 | /* Set any low order bits in mask that are not set. */ | |
838 | ||
839 | static CORE_ADDR | |
840 | fill_mask (CORE_ADDR mask) | |
841 | { | |
842 | CORE_ADDR f = 1; | |
843 | while (f && f < mask) | |
844 | { | |
845 | mask |= f; | |
846 | f <<= 1; | |
847 | } | |
848 | return mask; | |
849 | } | |
850 | ||
851 | /* Try to add a single watch to the specified registers. Return 1 on | |
852 | success, 0 on failure. */ | |
853 | ||
854 | static int | |
855 | try_one_watch (struct pt_watch_regs *regs, CORE_ADDR addr, | |
856 | int len, unsigned irw) | |
857 | { | |
858 | CORE_ADDR base_addr, last_byte, break_addr, segment_len; | |
859 | CORE_ADDR mask_bits, t_low, t_low_end; | |
860 | uint16_t t_hi; | |
861 | int i, free_watches; | |
862 | struct pt_watch_regs regs_copy; | |
863 | ||
864 | if (len <= 0) | |
865 | return 0; | |
866 | ||
867 | last_byte = addr + len - 1; | |
868 | mask_bits = fill_mask (addr ^ last_byte) | IRW_MASK; | |
869 | base_addr = addr & ~mask_bits; | |
870 | ||
871 | /* Check to see if it is covered by current registers. */ | |
872 | for (i = 0; i < get_num_valid (regs); i++) | |
873 | { | |
874 | t_low = get_watchlo (regs, i); | |
875 | if (t_low != 0 && irw == ((unsigned)t_low & irw)) | |
876 | { | |
877 | t_hi = get_watchhi (regs, i) | IRW_MASK; | |
878 | t_low &= ~(CORE_ADDR)t_hi; | |
879 | if (addr >= t_low && last_byte <= (t_low + t_hi)) | |
880 | return 1; | |
881 | } | |
882 | } | |
883 | /* Try to find an empty register. */ | |
884 | free_watches = 0; | |
885 | for (i = 0; i < get_num_valid (regs); i++) | |
886 | { | |
887 | t_low = get_watchlo (regs, i); | |
888 | if (t_low == 0 && irw == (get_irw_mask (regs, i) & irw)) | |
889 | { | |
890 | if (mask_bits <= (get_reg_mask (regs, i) | IRW_MASK)) | |
891 | { | |
892 | /* It fits, we'll take it. */ | |
893 | set_watchlo (regs, i, base_addr | irw); | |
894 | set_watchhi (regs, i, mask_bits & ~IRW_MASK); | |
895 | return 1; | |
896 | } | |
897 | else | |
898 | { | |
899 | /* It doesn't fit, but has the proper IRW capabilities. */ | |
900 | free_watches++; | |
901 | } | |
902 | } | |
903 | } | |
904 | if (free_watches > 1) | |
905 | { | |
906 | /* Try to split it across several registers. */ | |
907 | regs_copy = *regs; | |
908 | for (i = 0; i < get_num_valid (®s_copy); i++) | |
909 | { | |
910 | t_low = get_watchlo (®s_copy, i); | |
911 | t_hi = get_reg_mask (®s_copy, i) | IRW_MASK; | |
912 | if (t_low == 0 && irw == (t_hi & irw)) | |
913 | { | |
914 | t_low = addr & ~(CORE_ADDR)t_hi; | |
915 | break_addr = t_low + t_hi + 1; | |
916 | if (break_addr >= addr + len) | |
917 | segment_len = len; | |
918 | else | |
919 | segment_len = break_addr - addr; | |
920 | mask_bits = fill_mask (addr ^ (addr + segment_len - 1)); | |
921 | set_watchlo (®s_copy, i, (addr & ~mask_bits) | irw); | |
922 | set_watchhi (®s_copy, i, mask_bits & ~IRW_MASK); | |
923 | if (break_addr >= addr + len) | |
924 | { | |
925 | *regs = regs_copy; | |
926 | return 1; | |
927 | } | |
928 | len = addr + len - break_addr; | |
929 | addr = break_addr; | |
930 | } | |
931 | } | |
932 | } | |
933 | /* It didn't fit anywhere, we failed. */ | |
934 | return 0; | |
935 | } | |
936 | ||
937 | /* Target to_region_ok_for_hw_watchpoint implementation. Return 1 if | |
938 | the specified region can be covered by the watch registers. */ | |
939 | ||
940 | static int | |
941 | mips_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) | |
942 | { | |
943 | struct pt_watch_regs dummy_regs; | |
944 | int i; | |
945 | ||
946 | if (!mips_linux_read_watch_registers (0)) | |
947 | return 0; | |
948 | ||
949 | dummy_regs = watch_readback; | |
950 | /* Clear them out. */ | |
951 | for (i = 0; i < get_num_valid (&dummy_regs); i++) | |
952 | set_watchlo (&dummy_regs, i, 0); | |
953 | return try_one_watch (&dummy_regs, addr, len, 0); | |
954 | } | |
955 | ||
956 | ||
957 | /* Write the mirrored watch register values for each thread. */ | |
958 | ||
959 | static int | |
960 | write_watchpoint_regs (void) | |
961 | { | |
962 | struct lwp_info *lp; | |
b9412953 DD |
963 | int tid; |
964 | ||
4c38200f | 965 | ALL_LWPS (lp) |
b9412953 | 966 | { |
4c38200f | 967 | tid = ptid_get_lwp (lp->ptid); |
b9412953 DD |
968 | if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror) == -1) |
969 | perror_with_name (_("Couldn't write debug register")); | |
970 | } | |
971 | return 0; | |
972 | } | |
973 | ||
974 | /* linux_nat new_thread implementation. Write the mirrored watch | |
975 | register values for the new thread. */ | |
976 | ||
977 | static void | |
7b50312a | 978 | mips_linux_new_thread (struct lwp_info *lp) |
b9412953 DD |
979 | { |
980 | int tid; | |
981 | ||
982 | if (!mips_linux_read_watch_registers (0)) | |
983 | return; | |
984 | ||
7b50312a | 985 | tid = ptid_get_lwp (lp->ptid); |
b9412953 DD |
986 | if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror) == -1) |
987 | perror_with_name (_("Couldn't write debug register")); | |
988 | } | |
989 | ||
990 | /* Fill in the watch registers with the currently cached watches. */ | |
991 | ||
992 | static void | |
993 | populate_regs_from_watches (struct pt_watch_regs *regs) | |
994 | { | |
995 | struct mips_watchpoint *w; | |
996 | int i; | |
997 | ||
998 | /* Clear them out. */ | |
999 | for (i = 0; i < get_num_valid (regs); i++) | |
1000 | { | |
1001 | set_watchlo (regs, i, 0); | |
1002 | set_watchhi (regs, i, 0); | |
1003 | } | |
1004 | ||
1005 | w = current_watches; | |
1006 | while (w) | |
1007 | { | |
1008 | i = try_one_watch (regs, w->addr, w->len, type_to_irw (w->type)); | |
1009 | /* They must all fit, because we previously calculated that they | |
1010 | would. */ | |
1011 | gdb_assert (i); | |
1012 | w = w->next; | |
1013 | } | |
1014 | } | |
1015 | ||
1016 | /* Target to_insert_watchpoint implementation. Try to insert a new | |
1017 | watch. Return zero on success. */ | |
1018 | ||
1019 | static int | |
0cf6dd15 TJB |
1020 | mips_linux_insert_watchpoint (CORE_ADDR addr, int len, int type, |
1021 | struct expression *cond) | |
b9412953 DD |
1022 | { |
1023 | struct pt_watch_regs regs; | |
1024 | struct mips_watchpoint *new_watch; | |
1025 | struct mips_watchpoint **pw; | |
1026 | ||
1027 | int i; | |
1028 | int retval; | |
1029 | ||
1030 | if (!mips_linux_read_watch_registers (0)) | |
1031 | return -1; | |
1032 | ||
1033 | if (len <= 0) | |
1034 | return -1; | |
1035 | ||
1036 | regs = watch_readback; | |
1037 | /* Add the current watches. */ | |
1038 | populate_regs_from_watches (®s); | |
1039 | ||
1040 | /* Now try to add the new watch. */ | |
1041 | if (!try_one_watch (®s, addr, len, type_to_irw (type))) | |
1042 | return -1; | |
1043 | ||
1044 | /* It fit. Stick it on the end of the list. */ | |
1045 | new_watch = (struct mips_watchpoint *) | |
1046 | xmalloc (sizeof (struct mips_watchpoint)); | |
1047 | new_watch->addr = addr; | |
1048 | new_watch->len = len; | |
1049 | new_watch->type = type; | |
1050 | new_watch->next = NULL; | |
1051 | ||
1052 | pw = ¤t_watches; | |
1053 | while (*pw != NULL) | |
1054 | pw = &(*pw)->next; | |
1055 | *pw = new_watch; | |
1056 | ||
1057 | watch_mirror = regs; | |
1058 | retval = write_watchpoint_regs (); | |
1059 | ||
1060 | if (maint_show_dr) | |
1061 | mips_show_dr ("insert_watchpoint", addr, len, type); | |
1062 | ||
1063 | return retval; | |
1064 | } | |
1065 | ||
1066 | /* Target to_remove_watchpoint implementation. Try to remove a watch. | |
1067 | Return zero on success. */ | |
1068 | ||
1069 | static int | |
0cf6dd15 TJB |
1070 | mips_linux_remove_watchpoint (CORE_ADDR addr, int len, int type, |
1071 | struct expression *cond) | |
b9412953 DD |
1072 | { |
1073 | int retval; | |
1074 | int deleted_one; | |
1075 | ||
1076 | struct mips_watchpoint **pw; | |
1077 | struct mips_watchpoint *w; | |
1078 | ||
1079 | /* Search for a known watch that matches. Then unlink and free | |
1080 | it. */ | |
1081 | deleted_one = 0; | |
1082 | pw = ¤t_watches; | |
1083 | while ((w = *pw)) | |
1084 | { | |
1085 | if (w->addr == addr && w->len == len && w->type == type) | |
1086 | { | |
1087 | *pw = w->next; | |
1088 | xfree (w); | |
1089 | deleted_one = 1; | |
1090 | break; | |
1091 | } | |
1092 | pw = &(w->next); | |
1093 | } | |
1094 | ||
1095 | if (!deleted_one) | |
1096 | return -1; /* We don't know about it, fail doing nothing. */ | |
1097 | ||
1098 | /* At this point watch_readback is known to be valid because we | |
1099 | could not have added the watch without reading it. */ | |
1100 | gdb_assert (watch_readback_valid == 1); | |
1101 | ||
1102 | watch_mirror = watch_readback; | |
1103 | populate_regs_from_watches (&watch_mirror); | |
1104 | ||
1105 | retval = write_watchpoint_regs (); | |
1106 | ||
1107 | if (maint_show_dr) | |
1108 | mips_show_dr ("remove_watchpoint", addr, len, type); | |
1109 | ||
1110 | return retval; | |
1111 | } | |
1112 | ||
1113 | /* Target to_close implementation. Free any watches and call the | |
1114 | super implementation. */ | |
1115 | ||
1116 | static void | |
1117 | mips_linux_close (int quitting) | |
1118 | { | |
1119 | struct mips_watchpoint *w; | |
1120 | struct mips_watchpoint *nw; | |
1121 | ||
1122 | /* Clean out the current_watches list. */ | |
1123 | w = current_watches; | |
1124 | while (w) | |
1125 | { | |
1126 | nw = w->next; | |
1127 | xfree (w); | |
1128 | w = nw; | |
1129 | } | |
1130 | current_watches = NULL; | |
1131 | ||
1132 | if (super_close) | |
1133 | super_close (quitting); | |
1134 | } | |
1135 | ||
10d6c8cd DJ |
1136 | void _initialize_mips_linux_nat (void); |
1137 | ||
1138 | void | |
1139 | _initialize_mips_linux_nat (void) | |
1140 | { | |
b9412953 DD |
1141 | struct target_ops *t; |
1142 | ||
cbe54154 PA |
1143 | add_setshow_boolean_cmd ("show-debug-regs", class_maintenance, |
1144 | &maint_show_dr, _("\ | |
1145 | Set whether to show variables that mirror the mips debug registers."), _("\ | |
1146 | Show whether to show variables that mirror the mips debug registers."), _("\ | |
b9412953 DD |
1147 | Use \"on\" to enable, \"off\" to disable.\n\ |
1148 | If enabled, the debug registers values are shown when GDB inserts\n\ | |
1149 | or removes a hardware breakpoint or watchpoint, and when the inferior\n\ | |
1150 | triggers a breakpoint or watchpoint."), | |
cbe54154 PA |
1151 | NULL, |
1152 | NULL, | |
1153 | &maintenance_set_cmdlist, | |
1154 | &maintenance_show_cmdlist); | |
b9412953 DD |
1155 | |
1156 | t = linux_trad_target (mips_linux_register_u_offset); | |
1157 | ||
1158 | super_close = t->to_close; | |
1159 | t->to_close = mips_linux_close; | |
d37eb719 DJ |
1160 | |
1161 | super_fetch_registers = t->to_fetch_registers; | |
1162 | super_store_registers = t->to_store_registers; | |
1163 | ||
1164 | t->to_fetch_registers = mips64_linux_fetch_registers; | |
1165 | t->to_store_registers = mips64_linux_store_registers; | |
1166 | ||
b9412953 DD |
1167 | t->to_can_use_hw_breakpoint = mips_linux_can_use_hw_breakpoint; |
1168 | t->to_remove_watchpoint = mips_linux_remove_watchpoint; | |
1169 | t->to_insert_watchpoint = mips_linux_insert_watchpoint; | |
1170 | t->to_stopped_by_watchpoint = mips_linux_stopped_by_watchpoint; | |
1171 | t->to_stopped_data_address = mips_linux_stopped_data_address; | |
1172 | t->to_region_ok_for_hw_watchpoint = mips_linux_region_ok_for_hw_watchpoint; | |
1173 | ||
81adfced | 1174 | t->to_read_description = mips_linux_read_description; |
822b6570 | 1175 | |
f973ed9c | 1176 | linux_nat_add_target (t); |
b9412953 | 1177 | linux_nat_set_new_thread (t, mips_linux_new_thread); |
81adfced DJ |
1178 | |
1179 | /* Initialize the standard target descriptions. */ | |
1180 | initialize_tdesc_mips_linux (); | |
1faeff08 | 1181 | initialize_tdesc_mips_dsp_linux (); |
81adfced | 1182 | initialize_tdesc_mips64_linux (); |
1faeff08 | 1183 | initialize_tdesc_mips64_dsp_linux (); |
10d6c8cd | 1184 | } |