Commit | Line | Data |
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75c9abc6 | 1 | /* Native-dependent code for GNU/Linux on MIPS processors. |
a094c6fb | 2 | |
0b302171 | 3 | Copyright (C) 2001-2012 Free Software Foundation, Inc. |
2aa830e4 DJ |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
2aa830e4 DJ |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
2aa830e4 DJ |
19 | |
20 | #include "defs.h" | |
b9412953 DD |
21 | #include "command.h" |
22 | #include "gdbcmd.h" | |
23 | #include "gdb_assert.h" | |
d37eb719 | 24 | #include "inferior.h" |
6b753f60 | 25 | #include "mips-tdep.h" |
10d6c8cd | 26 | #include "target.h" |
28f5035f | 27 | #include "regcache.h" |
10d6c8cd | 28 | #include "linux-nat.h" |
d37eb719 | 29 | #include "mips-linux-tdep.h" |
822b6570 | 30 | #include "target-descriptions.h" |
2aa830e4 | 31 | |
dc60ece8 | 32 | #include "gdb_proc_service.h" |
3e00823e | 33 | #include "gregset.h" |
dc60ece8 | 34 | |
822b6570 | 35 | #include <sgidefs.h> |
d37eb719 DJ |
36 | #include <sys/ptrace.h> |
37 | ||
81adfced DJ |
38 | #include "features/mips-linux.c" |
39 | #include "features/mips64-linux.c" | |
40 | ||
dc60ece8 DJ |
41 | #ifndef PTRACE_GET_THREAD_AREA |
42 | #define PTRACE_GET_THREAD_AREA 25 | |
43 | #endif | |
44 | ||
d37eb719 DJ |
45 | /* Assume that we have PTRACE_GETREGS et al. support. If we do not, |
46 | we'll clear this and use PTRACE_PEEKUSER instead. */ | |
47 | static int have_ptrace_regsets = 1; | |
48 | ||
b9412953 DD |
49 | /* Whether or not to print the mirrored debug registers. */ |
50 | ||
51 | static int maint_show_dr; | |
52 | ||
d37eb719 DJ |
53 | /* Saved function pointers to fetch and store a single register using |
54 | PTRACE_PEEKUSER and PTRACE_POKEUSER. */ | |
55 | ||
b9412953 DD |
56 | static void (*super_fetch_registers) (struct target_ops *, |
57 | struct regcache *, int); | |
58 | static void (*super_store_registers) (struct target_ops *, | |
59 | struct regcache *, int); | |
60 | ||
61 | static void (*super_close) (int); | |
d37eb719 | 62 | |
dda0c97e | 63 | /* Map gdb internal register number to ptrace ``address''. |
7714d83a UW |
64 | These ``addresses'' are normally defined in <asm/ptrace.h>. |
65 | ||
66 | ptrace does not provide a way to read (or set) MIPS_PS_REGNUM, | |
67 | and there's no point in reading or setting MIPS_ZERO_REGNUM. | |
68 | We also can not set BADVADDR, CAUSE, or FCRIR via ptrace(). */ | |
dda0c97e UW |
69 | |
70 | static CORE_ADDR | |
7714d83a | 71 | mips_linux_register_addr (struct gdbarch *gdbarch, int regno, int store) |
dda0c97e | 72 | { |
7714d83a | 73 | CORE_ADDR regaddr; |
dda0c97e | 74 | |
2eb4d78b | 75 | if (regno < 0 || regno >= gdbarch_num_regs (gdbarch)) |
dda0c97e UW |
76 | error (_("Bogon register number %d."), regno); |
77 | ||
7714d83a | 78 | if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32) |
dda0c97e | 79 | regaddr = regno; |
7714d83a UW |
80 | else if ((regno >= mips_regnum (gdbarch)->fp0) |
81 | && (regno < mips_regnum (gdbarch)->fp0 + 32)) | |
82 | regaddr = FPR_BASE + (regno - mips_regnum (gdbarch)->fp0); | |
83 | else if (regno == mips_regnum (gdbarch)->pc) | |
dda0c97e | 84 | regaddr = PC; |
7714d83a UW |
85 | else if (regno == mips_regnum (gdbarch)->cause) |
86 | regaddr = store? (CORE_ADDR) -1 : CAUSE; | |
87 | else if (regno == mips_regnum (gdbarch)->badvaddr) | |
88 | regaddr = store? (CORE_ADDR) -1 : BADVADDR; | |
89 | else if (regno == mips_regnum (gdbarch)->lo) | |
dda0c97e | 90 | regaddr = MMLO; |
7714d83a | 91 | else if (regno == mips_regnum (gdbarch)->hi) |
dda0c97e | 92 | regaddr = MMHI; |
7714d83a | 93 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
dda0c97e | 94 | regaddr = FPC_CSR; |
7714d83a UW |
95 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
96 | regaddr = store? (CORE_ADDR) -1 : FPC_EIR; | |
822b6570 DJ |
97 | else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM) |
98 | regaddr = 0; | |
dda0c97e | 99 | else |
7714d83a | 100 | regaddr = (CORE_ADDR) -1; |
dda0c97e UW |
101 | |
102 | return regaddr; | |
103 | } | |
104 | ||
105 | static CORE_ADDR | |
7714d83a | 106 | mips64_linux_register_addr (struct gdbarch *gdbarch, int regno, int store) |
dda0c97e | 107 | { |
7714d83a | 108 | CORE_ADDR regaddr; |
dda0c97e | 109 | |
2eb4d78b | 110 | if (regno < 0 || regno >= gdbarch_num_regs (gdbarch)) |
dda0c97e UW |
111 | error (_("Bogon register number %d."), regno); |
112 | ||
7714d83a | 113 | if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32) |
dda0c97e | 114 | regaddr = regno; |
7714d83a UW |
115 | else if ((regno >= mips_regnum (gdbarch)->fp0) |
116 | && (regno < mips_regnum (gdbarch)->fp0 + 32)) | |
2eb4d78b | 117 | regaddr = MIPS64_FPR_BASE + (regno - gdbarch_fp0_regnum (gdbarch)); |
7714d83a | 118 | else if (regno == mips_regnum (gdbarch)->pc) |
dda0c97e | 119 | regaddr = MIPS64_PC; |
7714d83a UW |
120 | else if (regno == mips_regnum (gdbarch)->cause) |
121 | regaddr = store? (CORE_ADDR) -1 : MIPS64_CAUSE; | |
122 | else if (regno == mips_regnum (gdbarch)->badvaddr) | |
123 | regaddr = store? (CORE_ADDR) -1 : MIPS64_BADVADDR; | |
124 | else if (regno == mips_regnum (gdbarch)->lo) | |
dda0c97e | 125 | regaddr = MIPS64_MMLO; |
7714d83a | 126 | else if (regno == mips_regnum (gdbarch)->hi) |
dda0c97e | 127 | regaddr = MIPS64_MMHI; |
7714d83a | 128 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
dda0c97e | 129 | regaddr = MIPS64_FPC_CSR; |
7714d83a UW |
130 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
131 | regaddr = store? (CORE_ADDR) -1 : MIPS64_FPC_EIR; | |
822b6570 DJ |
132 | else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM) |
133 | regaddr = 0; | |
dda0c97e | 134 | else |
7714d83a | 135 | regaddr = (CORE_ADDR) -1; |
dda0c97e UW |
136 | |
137 | return regaddr; | |
138 | } | |
139 | ||
dc60ece8 DJ |
140 | /* Fetch the thread-local storage pointer for libthread_db. */ |
141 | ||
142 | ps_err_e | |
143 | ps_get_thread_area (const struct ps_prochandle *ph, | |
144 | lwpid_t lwpid, int idx, void **base) | |
145 | { | |
146 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
147 | return PS_ERR; | |
148 | ||
149 | /* IDX is the bias from the thread pointer to the beginning of the | |
150 | thread descriptor. It has to be subtracted due to implementation | |
151 | quirks in libthread_db. */ | |
152 | *base = (void *) ((char *)*base - idx); | |
153 | ||
154 | return PS_OK; | |
155 | } | |
156 | ||
3e00823e UW |
157 | /* Wrapper functions. These are only used by libthread_db. */ |
158 | ||
159 | void | |
7f7fe91e | 160 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
3e00823e | 161 | { |
2eb4d78b | 162 | if (mips_isa_regsize (get_regcache_arch (regcache)) == 4) |
7f7fe91e | 163 | mips_supply_gregset (regcache, (const mips_elf_gregset_t *) gregsetp); |
3e00823e | 164 | else |
7f7fe91e | 165 | mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *) gregsetp); |
3e00823e UW |
166 | } |
167 | ||
168 | void | |
7f7fe91e UW |
169 | fill_gregset (const struct regcache *regcache, |
170 | gdb_gregset_t *gregsetp, int regno) | |
3e00823e | 171 | { |
2eb4d78b | 172 | if (mips_isa_regsize (get_regcache_arch (regcache)) == 4) |
7f7fe91e | 173 | mips_fill_gregset (regcache, (mips_elf_gregset_t *) gregsetp, regno); |
3e00823e | 174 | else |
7f7fe91e | 175 | mips64_fill_gregset (regcache, (mips64_elf_gregset_t *) gregsetp, regno); |
3e00823e UW |
176 | } |
177 | ||
178 | void | |
7f7fe91e | 179 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) |
3e00823e | 180 | { |
2eb4d78b | 181 | if (mips_isa_regsize (get_regcache_arch (regcache)) == 4) |
7f7fe91e | 182 | mips_supply_fpregset (regcache, (const mips_elf_fpregset_t *) fpregsetp); |
3e00823e | 183 | else |
025bb325 MS |
184 | mips64_supply_fpregset (regcache, |
185 | (const mips64_elf_fpregset_t *) fpregsetp); | |
3e00823e UW |
186 | } |
187 | ||
188 | void | |
7f7fe91e UW |
189 | fill_fpregset (const struct regcache *regcache, |
190 | gdb_fpregset_t *fpregsetp, int regno) | |
3e00823e | 191 | { |
2eb4d78b | 192 | if (mips_isa_regsize (get_regcache_arch (regcache)) == 4) |
7f7fe91e | 193 | mips_fill_fpregset (regcache, (mips_elf_fpregset_t *) fpregsetp, regno); |
3e00823e | 194 | else |
025bb325 MS |
195 | mips64_fill_fpregset (regcache, |
196 | (mips64_elf_fpregset_t *) fpregsetp, regno); | |
3e00823e UW |
197 | } |
198 | ||
199 | ||
d37eb719 DJ |
200 | /* Fetch REGNO (or all registers if REGNO == -1) from the target |
201 | using PTRACE_GETREGS et al. */ | |
202 | ||
203 | static void | |
56be3814 | 204 | mips64_linux_regsets_fetch_registers (struct regcache *regcache, int regno) |
d37eb719 | 205 | { |
2eb4d78b | 206 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
d37eb719 DJ |
207 | int is_fp; |
208 | int tid; | |
209 | ||
2eb4d78b UW |
210 | if (regno >= mips_regnum (gdbarch)->fp0 |
211 | && regno <= mips_regnum (gdbarch)->fp0 + 32) | |
d37eb719 | 212 | is_fp = 1; |
2eb4d78b | 213 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
d37eb719 | 214 | is_fp = 1; |
2eb4d78b | 215 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
d37eb719 DJ |
216 | is_fp = 1; |
217 | else | |
218 | is_fp = 0; | |
219 | ||
220 | tid = ptid_get_lwp (inferior_ptid); | |
221 | if (tid == 0) | |
222 | tid = ptid_get_pid (inferior_ptid); | |
223 | ||
224 | if (regno == -1 || !is_fp) | |
225 | { | |
226 | mips64_elf_gregset_t regs; | |
227 | ||
228 | if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1) | |
229 | { | |
230 | if (errno == EIO) | |
231 | { | |
232 | have_ptrace_regsets = 0; | |
233 | return; | |
234 | } | |
235 | perror_with_name (_("Couldn't get registers")); | |
236 | } | |
237 | ||
56be3814 | 238 | mips64_supply_gregset (regcache, |
28f5035f | 239 | (const mips64_elf_gregset_t *) ®s); |
d37eb719 DJ |
240 | } |
241 | ||
242 | if (regno == -1 || is_fp) | |
243 | { | |
244 | mips64_elf_fpregset_t fp_regs; | |
245 | ||
246 | if (ptrace (PTRACE_GETFPREGS, tid, 0L, | |
247 | (PTRACE_TYPE_ARG3) &fp_regs) == -1) | |
248 | { | |
249 | if (errno == EIO) | |
250 | { | |
251 | have_ptrace_regsets = 0; | |
252 | return; | |
253 | } | |
254 | perror_with_name (_("Couldn't get FP registers")); | |
255 | } | |
256 | ||
56be3814 | 257 | mips64_supply_fpregset (regcache, |
28f5035f | 258 | (const mips64_elf_fpregset_t *) &fp_regs); |
d37eb719 DJ |
259 | } |
260 | } | |
261 | ||
262 | /* Store REGNO (or all registers if REGNO == -1) to the target | |
263 | using PTRACE_SETREGS et al. */ | |
264 | ||
265 | static void | |
025bb325 MS |
266 | mips64_linux_regsets_store_registers (const struct regcache *regcache, |
267 | int regno) | |
d37eb719 | 268 | { |
2eb4d78b | 269 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
d37eb719 DJ |
270 | int is_fp; |
271 | int tid; | |
272 | ||
2eb4d78b UW |
273 | if (regno >= mips_regnum (gdbarch)->fp0 |
274 | && regno <= mips_regnum (gdbarch)->fp0 + 32) | |
d37eb719 | 275 | is_fp = 1; |
2eb4d78b | 276 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
d37eb719 | 277 | is_fp = 1; |
2eb4d78b | 278 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
d37eb719 DJ |
279 | is_fp = 1; |
280 | else | |
281 | is_fp = 0; | |
282 | ||
283 | tid = ptid_get_lwp (inferior_ptid); | |
284 | if (tid == 0) | |
285 | tid = ptid_get_pid (inferior_ptid); | |
286 | ||
287 | if (regno == -1 || !is_fp) | |
288 | { | |
289 | mips64_elf_gregset_t regs; | |
290 | ||
291 | if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1) | |
292 | perror_with_name (_("Couldn't get registers")); | |
293 | ||
56be3814 | 294 | mips64_fill_gregset (regcache, ®s, regno); |
d37eb719 DJ |
295 | |
296 | if (ptrace (PTRACE_SETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1) | |
297 | perror_with_name (_("Couldn't set registers")); | |
298 | } | |
299 | ||
300 | if (regno == -1 || is_fp) | |
301 | { | |
302 | mips64_elf_fpregset_t fp_regs; | |
303 | ||
304 | if (ptrace (PTRACE_GETFPREGS, tid, 0L, | |
305 | (PTRACE_TYPE_ARG3) &fp_regs) == -1) | |
306 | perror_with_name (_("Couldn't get FP registers")); | |
307 | ||
56be3814 | 308 | mips64_fill_fpregset (regcache, &fp_regs, regno); |
d37eb719 DJ |
309 | |
310 | if (ptrace (PTRACE_SETFPREGS, tid, 0L, | |
311 | (PTRACE_TYPE_ARG3) &fp_regs) == -1) | |
312 | perror_with_name (_("Couldn't set FP registers")); | |
313 | } | |
314 | } | |
315 | ||
316 | /* Fetch REGNO (or all registers if REGNO == -1) from the target | |
317 | using any working method. */ | |
318 | ||
319 | static void | |
28439f5e PA |
320 | mips64_linux_fetch_registers (struct target_ops *ops, |
321 | struct regcache *regcache, int regnum) | |
d37eb719 DJ |
322 | { |
323 | /* Unless we already know that PTRACE_GETREGS does not work, try it. */ | |
324 | if (have_ptrace_regsets) | |
56be3814 | 325 | mips64_linux_regsets_fetch_registers (regcache, regnum); |
d37eb719 DJ |
326 | |
327 | /* If we know, or just found out, that PTRACE_GETREGS does not work, fall | |
328 | back to PTRACE_PEEKUSER. */ | |
329 | if (!have_ptrace_regsets) | |
a0740d21 | 330 | super_fetch_registers (ops, regcache, regnum); |
d37eb719 DJ |
331 | } |
332 | ||
333 | /* Store REGNO (or all registers if REGNO == -1) to the target | |
334 | using any working method. */ | |
335 | ||
336 | static void | |
28439f5e PA |
337 | mips64_linux_store_registers (struct target_ops *ops, |
338 | struct regcache *regcache, int regnum) | |
d37eb719 DJ |
339 | { |
340 | /* Unless we already know that PTRACE_GETREGS does not work, try it. */ | |
341 | if (have_ptrace_regsets) | |
56be3814 | 342 | mips64_linux_regsets_store_registers (regcache, regnum); |
d37eb719 DJ |
343 | |
344 | /* If we know, or just found out, that PTRACE_GETREGS does not work, fall | |
345 | back to PTRACE_PEEKUSER. */ | |
346 | if (!have_ptrace_regsets) | |
a0740d21 | 347 | super_store_registers (ops, regcache, regnum); |
d37eb719 DJ |
348 | } |
349 | ||
910122bf UW |
350 | /* Return the address in the core dump or inferior of register |
351 | REGNO. */ | |
352 | ||
353 | static CORE_ADDR | |
7714d83a | 354 | mips_linux_register_u_offset (struct gdbarch *gdbarch, int regno, int store_p) |
910122bf | 355 | { |
7714d83a UW |
356 | if (mips_abi_regsize (gdbarch) == 8) |
357 | return mips64_linux_register_addr (gdbarch, regno, store_p); | |
dda0c97e | 358 | else |
7714d83a | 359 | return mips_linux_register_addr (gdbarch, regno, store_p); |
910122bf UW |
360 | } |
361 | ||
81adfced DJ |
362 | static const struct target_desc * |
363 | mips_linux_read_description (struct target_ops *ops) | |
822b6570 | 364 | { |
81adfced DJ |
365 | /* Report that target registers are a size we know for sure |
366 | that we can get from ptrace. */ | |
367 | if (_MIPS_SIM == _ABIO32) | |
368 | return tdesc_mips_linux; | |
369 | else | |
370 | return tdesc_mips64_linux; | |
822b6570 DJ |
371 | } |
372 | ||
b9412953 DD |
373 | #ifndef PTRACE_GET_WATCH_REGS |
374 | # define PTRACE_GET_WATCH_REGS 0xd0 | |
375 | #endif | |
376 | ||
377 | #ifndef PTRACE_SET_WATCH_REGS | |
378 | # define PTRACE_SET_WATCH_REGS 0xd1 | |
379 | #endif | |
380 | ||
381 | #define W_BIT 0 | |
382 | #define R_BIT 1 | |
383 | #define I_BIT 2 | |
384 | ||
385 | #define W_MASK (1 << W_BIT) | |
386 | #define R_MASK (1 << R_BIT) | |
387 | #define I_MASK (1 << I_BIT) | |
388 | ||
389 | #define IRW_MASK (I_MASK | R_MASK | W_MASK) | |
390 | ||
391 | enum pt_watch_style { | |
392 | pt_watch_style_mips32, | |
393 | pt_watch_style_mips64 | |
394 | }; | |
395 | ||
396 | #define MAX_DEBUG_REGISTER 8 | |
397 | ||
025bb325 | 398 | /* A value of zero in a watchlo indicates that it is available. */ |
b9412953 DD |
399 | |
400 | struct mips32_watch_regs | |
401 | { | |
402 | uint32_t watchlo[MAX_DEBUG_REGISTER]; | |
025bb325 | 403 | /* Lower 16 bits of watchhi. */ |
b9412953 DD |
404 | uint16_t watchhi[MAX_DEBUG_REGISTER]; |
405 | /* Valid mask and I R W bits. | |
406 | * bit 0 -- 1 if W bit is usable. | |
407 | * bit 1 -- 1 if R bit is usable. | |
408 | * bit 2 -- 1 if I bit is usable. | |
409 | * bits 3 - 11 -- Valid watchhi mask bits. | |
410 | */ | |
411 | uint16_t watch_masks[MAX_DEBUG_REGISTER]; | |
412 | /* The number of valid watch register pairs. */ | |
413 | uint32_t num_valid; | |
414 | /* There is confusion across gcc versions about structure alignment, | |
415 | so we force 8 byte alignment for these structures so they match | |
416 | the kernel even if it was build with a different gcc version. */ | |
417 | } __attribute__ ((aligned (8))); | |
418 | ||
419 | struct mips64_watch_regs | |
420 | { | |
421 | uint64_t watchlo[MAX_DEBUG_REGISTER]; | |
422 | uint16_t watchhi[MAX_DEBUG_REGISTER]; | |
423 | uint16_t watch_masks[MAX_DEBUG_REGISTER]; | |
424 | uint32_t num_valid; | |
425 | } __attribute__ ((aligned (8))); | |
426 | ||
427 | struct pt_watch_regs | |
428 | { | |
429 | enum pt_watch_style style; | |
430 | union | |
431 | { | |
432 | struct mips32_watch_regs mips32; | |
433 | struct mips64_watch_regs mips64; | |
434 | }; | |
435 | }; | |
436 | ||
437 | /* -1 if the kernel and/or CPU do not support watch registers. | |
438 | 1 if watch_readback is valid and we can read style, num_valid | |
439 | and the masks. | |
440 | 0 if we need to read the watch_readback. */ | |
441 | ||
442 | static int watch_readback_valid; | |
443 | ||
444 | /* Cached watch register read values. */ | |
445 | ||
446 | static struct pt_watch_regs watch_readback; | |
447 | ||
448 | /* We keep list of all watchpoints we should install and calculate the | |
449 | watch register values each time the list changes. This allows for | |
450 | easy sharing of watch registers for more than one watchpoint. */ | |
451 | ||
452 | struct mips_watchpoint | |
453 | { | |
454 | CORE_ADDR addr; | |
455 | int len; | |
456 | int type; | |
457 | struct mips_watchpoint *next; | |
458 | }; | |
459 | ||
460 | static struct mips_watchpoint *current_watches; | |
461 | ||
462 | /* The current set of watch register values for writing the | |
463 | registers. */ | |
464 | ||
465 | static struct pt_watch_regs watch_mirror; | |
466 | ||
467 | /* Assuming usable watch registers, return the irw_mask. */ | |
468 | ||
469 | static uint32_t | |
470 | get_irw_mask (struct pt_watch_regs *regs, int set) | |
471 | { | |
472 | switch (regs->style) | |
473 | { | |
474 | case pt_watch_style_mips32: | |
475 | return regs->mips32.watch_masks[set] & IRW_MASK; | |
476 | case pt_watch_style_mips64: | |
477 | return regs->mips64.watch_masks[set] & IRW_MASK; | |
478 | default: | |
479 | internal_error (__FILE__, __LINE__, | |
480 | _("Unrecognized watch register style")); | |
481 | } | |
482 | } | |
483 | ||
484 | /* Assuming usable watch registers, return the reg_mask. */ | |
485 | ||
486 | static uint32_t | |
487 | get_reg_mask (struct pt_watch_regs *regs, int set) | |
488 | { | |
489 | switch (regs->style) | |
490 | { | |
491 | case pt_watch_style_mips32: | |
492 | return regs->mips32.watch_masks[set] & ~IRW_MASK; | |
493 | case pt_watch_style_mips64: | |
494 | return regs->mips64.watch_masks[set] & ~IRW_MASK; | |
495 | default: | |
496 | internal_error (__FILE__, __LINE__, | |
497 | _("Unrecognized watch register style")); | |
498 | } | |
499 | } | |
500 | ||
501 | /* Assuming usable watch registers, return the num_valid. */ | |
502 | ||
503 | static uint32_t | |
504 | get_num_valid (struct pt_watch_regs *regs) | |
505 | { | |
506 | switch (regs->style) | |
507 | { | |
508 | case pt_watch_style_mips32: | |
509 | return regs->mips32.num_valid; | |
510 | case pt_watch_style_mips64: | |
511 | return regs->mips64.num_valid; | |
512 | default: | |
513 | internal_error (__FILE__, __LINE__, | |
514 | _("Unrecognized watch register style")); | |
515 | } | |
516 | } | |
517 | ||
518 | /* Assuming usable watch registers, return the watchlo. */ | |
519 | ||
520 | static CORE_ADDR | |
521 | get_watchlo (struct pt_watch_regs *regs, int set) | |
522 | { | |
523 | switch (regs->style) | |
524 | { | |
525 | case pt_watch_style_mips32: | |
526 | return regs->mips32.watchlo[set]; | |
527 | case pt_watch_style_mips64: | |
528 | return regs->mips64.watchlo[set]; | |
529 | default: | |
530 | internal_error (__FILE__, __LINE__, | |
531 | _("Unrecognized watch register style")); | |
532 | } | |
533 | } | |
534 | ||
535 | /* Assuming usable watch registers, set a watchlo value. */ | |
536 | ||
537 | static void | |
538 | set_watchlo (struct pt_watch_regs *regs, int set, CORE_ADDR value) | |
539 | { | |
540 | switch (regs->style) | |
541 | { | |
542 | case pt_watch_style_mips32: | |
543 | /* The cast will never throw away bits as 64 bit addresses can | |
544 | never be used on a 32 bit kernel. */ | |
545 | regs->mips32.watchlo[set] = (uint32_t)value; | |
546 | break; | |
547 | case pt_watch_style_mips64: | |
548 | regs->mips64.watchlo[set] = value; | |
549 | break; | |
550 | default: | |
551 | internal_error (__FILE__, __LINE__, | |
552 | _("Unrecognized watch register style")); | |
553 | } | |
554 | } | |
555 | ||
556 | /* Assuming usable watch registers, return the watchhi. */ | |
557 | ||
558 | static uint32_t | |
559 | get_watchhi (struct pt_watch_regs *regs, int n) | |
560 | { | |
561 | switch (regs->style) | |
562 | { | |
563 | case pt_watch_style_mips32: | |
564 | return regs->mips32.watchhi[n]; | |
565 | case pt_watch_style_mips64: | |
566 | return regs->mips64.watchhi[n]; | |
567 | default: | |
568 | internal_error (__FILE__, __LINE__, | |
569 | _("Unrecognized watch register style")); | |
570 | } | |
571 | } | |
572 | ||
573 | /* Assuming usable watch registers, set a watchhi value. */ | |
574 | ||
575 | static void | |
576 | set_watchhi (struct pt_watch_regs *regs, int n, uint16_t value) | |
577 | { | |
578 | switch (regs->style) | |
579 | { | |
580 | case pt_watch_style_mips32: | |
581 | regs->mips32.watchhi[n] = value; | |
582 | break; | |
583 | case pt_watch_style_mips64: | |
584 | regs->mips64.watchhi[n] = value; | |
585 | break; | |
586 | default: | |
587 | internal_error (__FILE__, __LINE__, | |
588 | _("Unrecognized watch register style")); | |
589 | } | |
590 | } | |
591 | ||
592 | static void | |
593 | mips_show_dr (const char *func, CORE_ADDR addr, | |
594 | int len, enum target_hw_bp_type type) | |
595 | { | |
596 | int i; | |
597 | ||
598 | puts_unfiltered (func); | |
599 | if (addr || len) | |
5af949e3 UW |
600 | printf_unfiltered (" (addr=%s, len=%d, type=%s)", |
601 | paddress (target_gdbarch, addr), len, | |
b9412953 DD |
602 | type == hw_write ? "data-write" |
603 | : (type == hw_read ? "data-read" | |
604 | : (type == hw_access ? "data-read/write" | |
605 | : (type == hw_execute ? "instruction-execute" | |
606 | : "??unknown??")))); | |
607 | puts_unfiltered (":\n"); | |
608 | ||
609 | for (i = 0; i < MAX_DEBUG_REGISTER; i++) | |
5af949e3 UW |
610 | printf_unfiltered ("\tDR%d: lo=%s, hi=%s\n", i, |
611 | paddress (target_gdbarch, | |
612 | get_watchlo (&watch_mirror, i)), | |
613 | paddress (target_gdbarch, | |
614 | get_watchhi (&watch_mirror, i))); | |
b9412953 DD |
615 | } |
616 | ||
617 | /* Return 1 if watch registers are usable. Cached information is used | |
618 | unless force is true. */ | |
619 | ||
620 | static int | |
621 | mips_linux_read_watch_registers (int force) | |
622 | { | |
623 | int tid; | |
624 | ||
625 | if (force || watch_readback_valid == 0) | |
626 | { | |
627 | tid = ptid_get_lwp (inferior_ptid); | |
628 | if (ptrace (PTRACE_GET_WATCH_REGS, tid, &watch_readback) == -1) | |
629 | { | |
630 | watch_readback_valid = -1; | |
631 | return 0; | |
632 | } | |
633 | switch (watch_readback.style) | |
634 | { | |
635 | case pt_watch_style_mips32: | |
636 | if (watch_readback.mips32.num_valid == 0) | |
637 | { | |
638 | watch_readback_valid = -1; | |
639 | return 0; | |
640 | } | |
641 | break; | |
642 | case pt_watch_style_mips64: | |
643 | if (watch_readback.mips64.num_valid == 0) | |
644 | { | |
645 | watch_readback_valid = -1; | |
646 | return 0; | |
647 | } | |
648 | break; | |
649 | default: | |
650 | watch_readback_valid = -1; | |
651 | return 0; | |
652 | } | |
653 | /* Watch registers appear to be usable. */ | |
654 | watch_readback_valid = 1; | |
655 | } | |
656 | return (watch_readback_valid == 1) ? 1 : 0; | |
657 | } | |
658 | ||
659 | /* Convert GDB's type to an IRW mask. */ | |
660 | ||
661 | static unsigned | |
662 | type_to_irw (int type) | |
663 | { | |
664 | switch (type) | |
665 | { | |
666 | case hw_write: | |
667 | return W_MASK; | |
668 | case hw_read: | |
669 | return R_MASK; | |
670 | case hw_access: | |
671 | return (W_MASK | R_MASK); | |
672 | default: | |
673 | return 0; | |
674 | } | |
675 | } | |
676 | ||
677 | /* Target to_can_use_hw_breakpoint implementation. Return 1 if we can | |
678 | handle the specified watch type. */ | |
679 | ||
680 | static int | |
681 | mips_linux_can_use_hw_breakpoint (int type, int cnt, int ot) | |
682 | { | |
683 | int i; | |
684 | uint32_t wanted_mask, irw_mask; | |
685 | ||
686 | if (!mips_linux_read_watch_registers (0)) | |
687 | return 0; | |
688 | ||
689 | switch (type) | |
690 | { | |
691 | case bp_hardware_watchpoint: | |
692 | wanted_mask = W_MASK; | |
693 | break; | |
694 | case bp_read_watchpoint: | |
695 | wanted_mask = R_MASK; | |
696 | break; | |
697 | case bp_access_watchpoint: | |
698 | wanted_mask = R_MASK | W_MASK; | |
699 | break; | |
700 | default: | |
701 | return 0; | |
702 | } | |
703 | ||
704 | for (i = 0; i < get_num_valid (&watch_readback) && cnt; i++) | |
705 | { | |
706 | irw_mask = get_irw_mask (&watch_readback, i); | |
707 | if ((irw_mask & wanted_mask) == wanted_mask) | |
708 | cnt--; | |
709 | } | |
710 | return (cnt == 0) ? 1 : 0; | |
711 | } | |
712 | ||
713 | /* Target to_stopped_by_watchpoint implementation. Return 1 if | |
714 | stopped by watchpoint. The watchhi R and W bits indicate the watch | |
025bb325 | 715 | register triggered. */ |
b9412953 DD |
716 | |
717 | static int | |
718 | mips_linux_stopped_by_watchpoint (void) | |
719 | { | |
720 | int n; | |
721 | int num_valid; | |
722 | ||
723 | if (!mips_linux_read_watch_registers (1)) | |
724 | return 0; | |
725 | ||
726 | num_valid = get_num_valid (&watch_readback); | |
727 | ||
728 | for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++) | |
729 | if (get_watchhi (&watch_readback, n) & (R_MASK | W_MASK)) | |
730 | return 1; | |
731 | ||
732 | return 0; | |
733 | } | |
734 | ||
735 | /* Target to_stopped_data_address implementation. Set the address | |
736 | where the watch triggered (if known). Return 1 if the address was | |
737 | known. */ | |
738 | ||
739 | static int | |
740 | mips_linux_stopped_data_address (struct target_ops *t, CORE_ADDR *paddr) | |
741 | { | |
742 | /* On mips we don't know the low order 3 bits of the data address, | |
743 | so we must return false. */ | |
744 | return 0; | |
745 | } | |
746 | ||
747 | /* Set any low order bits in mask that are not set. */ | |
748 | ||
749 | static CORE_ADDR | |
750 | fill_mask (CORE_ADDR mask) | |
751 | { | |
752 | CORE_ADDR f = 1; | |
753 | while (f && f < mask) | |
754 | { | |
755 | mask |= f; | |
756 | f <<= 1; | |
757 | } | |
758 | return mask; | |
759 | } | |
760 | ||
761 | /* Try to add a single watch to the specified registers. Return 1 on | |
762 | success, 0 on failure. */ | |
763 | ||
764 | static int | |
765 | try_one_watch (struct pt_watch_regs *regs, CORE_ADDR addr, | |
766 | int len, unsigned irw) | |
767 | { | |
768 | CORE_ADDR base_addr, last_byte, break_addr, segment_len; | |
769 | CORE_ADDR mask_bits, t_low, t_low_end; | |
770 | uint16_t t_hi; | |
771 | int i, free_watches; | |
772 | struct pt_watch_regs regs_copy; | |
773 | ||
774 | if (len <= 0) | |
775 | return 0; | |
776 | ||
777 | last_byte = addr + len - 1; | |
778 | mask_bits = fill_mask (addr ^ last_byte) | IRW_MASK; | |
779 | base_addr = addr & ~mask_bits; | |
780 | ||
781 | /* Check to see if it is covered by current registers. */ | |
782 | for (i = 0; i < get_num_valid (regs); i++) | |
783 | { | |
784 | t_low = get_watchlo (regs, i); | |
785 | if (t_low != 0 && irw == ((unsigned)t_low & irw)) | |
786 | { | |
787 | t_hi = get_watchhi (regs, i) | IRW_MASK; | |
788 | t_low &= ~(CORE_ADDR)t_hi; | |
789 | if (addr >= t_low && last_byte <= (t_low + t_hi)) | |
790 | return 1; | |
791 | } | |
792 | } | |
793 | /* Try to find an empty register. */ | |
794 | free_watches = 0; | |
795 | for (i = 0; i < get_num_valid (regs); i++) | |
796 | { | |
797 | t_low = get_watchlo (regs, i); | |
798 | if (t_low == 0 && irw == (get_irw_mask (regs, i) & irw)) | |
799 | { | |
800 | if (mask_bits <= (get_reg_mask (regs, i) | IRW_MASK)) | |
801 | { | |
802 | /* It fits, we'll take it. */ | |
803 | set_watchlo (regs, i, base_addr | irw); | |
804 | set_watchhi (regs, i, mask_bits & ~IRW_MASK); | |
805 | return 1; | |
806 | } | |
807 | else | |
808 | { | |
809 | /* It doesn't fit, but has the proper IRW capabilities. */ | |
810 | free_watches++; | |
811 | } | |
812 | } | |
813 | } | |
814 | if (free_watches > 1) | |
815 | { | |
816 | /* Try to split it across several registers. */ | |
817 | regs_copy = *regs; | |
818 | for (i = 0; i < get_num_valid (®s_copy); i++) | |
819 | { | |
820 | t_low = get_watchlo (®s_copy, i); | |
821 | t_hi = get_reg_mask (®s_copy, i) | IRW_MASK; | |
822 | if (t_low == 0 && irw == (t_hi & irw)) | |
823 | { | |
824 | t_low = addr & ~(CORE_ADDR)t_hi; | |
825 | break_addr = t_low + t_hi + 1; | |
826 | if (break_addr >= addr + len) | |
827 | segment_len = len; | |
828 | else | |
829 | segment_len = break_addr - addr; | |
830 | mask_bits = fill_mask (addr ^ (addr + segment_len - 1)); | |
831 | set_watchlo (®s_copy, i, (addr & ~mask_bits) | irw); | |
832 | set_watchhi (®s_copy, i, mask_bits & ~IRW_MASK); | |
833 | if (break_addr >= addr + len) | |
834 | { | |
835 | *regs = regs_copy; | |
836 | return 1; | |
837 | } | |
838 | len = addr + len - break_addr; | |
839 | addr = break_addr; | |
840 | } | |
841 | } | |
842 | } | |
843 | /* It didn't fit anywhere, we failed. */ | |
844 | return 0; | |
845 | } | |
846 | ||
847 | /* Target to_region_ok_for_hw_watchpoint implementation. Return 1 if | |
848 | the specified region can be covered by the watch registers. */ | |
849 | ||
850 | static int | |
851 | mips_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) | |
852 | { | |
853 | struct pt_watch_regs dummy_regs; | |
854 | int i; | |
855 | ||
856 | if (!mips_linux_read_watch_registers (0)) | |
857 | return 0; | |
858 | ||
859 | dummy_regs = watch_readback; | |
860 | /* Clear them out. */ | |
861 | for (i = 0; i < get_num_valid (&dummy_regs); i++) | |
862 | set_watchlo (&dummy_regs, i, 0); | |
863 | return try_one_watch (&dummy_regs, addr, len, 0); | |
864 | } | |
865 | ||
866 | ||
867 | /* Write the mirrored watch register values for each thread. */ | |
868 | ||
869 | static int | |
870 | write_watchpoint_regs (void) | |
871 | { | |
872 | struct lwp_info *lp; | |
b9412953 DD |
873 | int tid; |
874 | ||
4c38200f | 875 | ALL_LWPS (lp) |
b9412953 | 876 | { |
4c38200f | 877 | tid = ptid_get_lwp (lp->ptid); |
b9412953 DD |
878 | if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror) == -1) |
879 | perror_with_name (_("Couldn't write debug register")); | |
880 | } | |
881 | return 0; | |
882 | } | |
883 | ||
884 | /* linux_nat new_thread implementation. Write the mirrored watch | |
885 | register values for the new thread. */ | |
886 | ||
887 | static void | |
7b50312a | 888 | mips_linux_new_thread (struct lwp_info *lp) |
b9412953 DD |
889 | { |
890 | int tid; | |
891 | ||
892 | if (!mips_linux_read_watch_registers (0)) | |
893 | return; | |
894 | ||
7b50312a | 895 | tid = ptid_get_lwp (lp->ptid); |
b9412953 DD |
896 | if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror) == -1) |
897 | perror_with_name (_("Couldn't write debug register")); | |
898 | } | |
899 | ||
900 | /* Fill in the watch registers with the currently cached watches. */ | |
901 | ||
902 | static void | |
903 | populate_regs_from_watches (struct pt_watch_regs *regs) | |
904 | { | |
905 | struct mips_watchpoint *w; | |
906 | int i; | |
907 | ||
908 | /* Clear them out. */ | |
909 | for (i = 0; i < get_num_valid (regs); i++) | |
910 | { | |
911 | set_watchlo (regs, i, 0); | |
912 | set_watchhi (regs, i, 0); | |
913 | } | |
914 | ||
915 | w = current_watches; | |
916 | while (w) | |
917 | { | |
918 | i = try_one_watch (regs, w->addr, w->len, type_to_irw (w->type)); | |
919 | /* They must all fit, because we previously calculated that they | |
920 | would. */ | |
921 | gdb_assert (i); | |
922 | w = w->next; | |
923 | } | |
924 | } | |
925 | ||
926 | /* Target to_insert_watchpoint implementation. Try to insert a new | |
927 | watch. Return zero on success. */ | |
928 | ||
929 | static int | |
0cf6dd15 TJB |
930 | mips_linux_insert_watchpoint (CORE_ADDR addr, int len, int type, |
931 | struct expression *cond) | |
b9412953 DD |
932 | { |
933 | struct pt_watch_regs regs; | |
934 | struct mips_watchpoint *new_watch; | |
935 | struct mips_watchpoint **pw; | |
936 | ||
937 | int i; | |
938 | int retval; | |
939 | ||
940 | if (!mips_linux_read_watch_registers (0)) | |
941 | return -1; | |
942 | ||
943 | if (len <= 0) | |
944 | return -1; | |
945 | ||
946 | regs = watch_readback; | |
947 | /* Add the current watches. */ | |
948 | populate_regs_from_watches (®s); | |
949 | ||
950 | /* Now try to add the new watch. */ | |
951 | if (!try_one_watch (®s, addr, len, type_to_irw (type))) | |
952 | return -1; | |
953 | ||
954 | /* It fit. Stick it on the end of the list. */ | |
955 | new_watch = (struct mips_watchpoint *) | |
956 | xmalloc (sizeof (struct mips_watchpoint)); | |
957 | new_watch->addr = addr; | |
958 | new_watch->len = len; | |
959 | new_watch->type = type; | |
960 | new_watch->next = NULL; | |
961 | ||
962 | pw = ¤t_watches; | |
963 | while (*pw != NULL) | |
964 | pw = &(*pw)->next; | |
965 | *pw = new_watch; | |
966 | ||
967 | watch_mirror = regs; | |
968 | retval = write_watchpoint_regs (); | |
969 | ||
970 | if (maint_show_dr) | |
971 | mips_show_dr ("insert_watchpoint", addr, len, type); | |
972 | ||
973 | return retval; | |
974 | } | |
975 | ||
976 | /* Target to_remove_watchpoint implementation. Try to remove a watch. | |
977 | Return zero on success. */ | |
978 | ||
979 | static int | |
0cf6dd15 TJB |
980 | mips_linux_remove_watchpoint (CORE_ADDR addr, int len, int type, |
981 | struct expression *cond) | |
b9412953 DD |
982 | { |
983 | int retval; | |
984 | int deleted_one; | |
985 | ||
986 | struct mips_watchpoint **pw; | |
987 | struct mips_watchpoint *w; | |
988 | ||
989 | /* Search for a known watch that matches. Then unlink and free | |
990 | it. */ | |
991 | deleted_one = 0; | |
992 | pw = ¤t_watches; | |
993 | while ((w = *pw)) | |
994 | { | |
995 | if (w->addr == addr && w->len == len && w->type == type) | |
996 | { | |
997 | *pw = w->next; | |
998 | xfree (w); | |
999 | deleted_one = 1; | |
1000 | break; | |
1001 | } | |
1002 | pw = &(w->next); | |
1003 | } | |
1004 | ||
1005 | if (!deleted_one) | |
1006 | return -1; /* We don't know about it, fail doing nothing. */ | |
1007 | ||
1008 | /* At this point watch_readback is known to be valid because we | |
1009 | could not have added the watch without reading it. */ | |
1010 | gdb_assert (watch_readback_valid == 1); | |
1011 | ||
1012 | watch_mirror = watch_readback; | |
1013 | populate_regs_from_watches (&watch_mirror); | |
1014 | ||
1015 | retval = write_watchpoint_regs (); | |
1016 | ||
1017 | if (maint_show_dr) | |
1018 | mips_show_dr ("remove_watchpoint", addr, len, type); | |
1019 | ||
1020 | return retval; | |
1021 | } | |
1022 | ||
1023 | /* Target to_close implementation. Free any watches and call the | |
1024 | super implementation. */ | |
1025 | ||
1026 | static void | |
1027 | mips_linux_close (int quitting) | |
1028 | { | |
1029 | struct mips_watchpoint *w; | |
1030 | struct mips_watchpoint *nw; | |
1031 | ||
1032 | /* Clean out the current_watches list. */ | |
1033 | w = current_watches; | |
1034 | while (w) | |
1035 | { | |
1036 | nw = w->next; | |
1037 | xfree (w); | |
1038 | w = nw; | |
1039 | } | |
1040 | current_watches = NULL; | |
1041 | ||
1042 | if (super_close) | |
1043 | super_close (quitting); | |
1044 | } | |
1045 | ||
10d6c8cd DJ |
1046 | void _initialize_mips_linux_nat (void); |
1047 | ||
1048 | void | |
1049 | _initialize_mips_linux_nat (void) | |
1050 | { | |
b9412953 DD |
1051 | struct target_ops *t; |
1052 | ||
cbe54154 PA |
1053 | add_setshow_boolean_cmd ("show-debug-regs", class_maintenance, |
1054 | &maint_show_dr, _("\ | |
1055 | Set whether to show variables that mirror the mips debug registers."), _("\ | |
1056 | Show whether to show variables that mirror the mips debug registers."), _("\ | |
b9412953 DD |
1057 | Use \"on\" to enable, \"off\" to disable.\n\ |
1058 | If enabled, the debug registers values are shown when GDB inserts\n\ | |
1059 | or removes a hardware breakpoint or watchpoint, and when the inferior\n\ | |
1060 | triggers a breakpoint or watchpoint."), | |
cbe54154 PA |
1061 | NULL, |
1062 | NULL, | |
1063 | &maintenance_set_cmdlist, | |
1064 | &maintenance_show_cmdlist); | |
b9412953 DD |
1065 | |
1066 | t = linux_trad_target (mips_linux_register_u_offset); | |
1067 | ||
1068 | super_close = t->to_close; | |
1069 | t->to_close = mips_linux_close; | |
d37eb719 DJ |
1070 | |
1071 | super_fetch_registers = t->to_fetch_registers; | |
1072 | super_store_registers = t->to_store_registers; | |
1073 | ||
1074 | t->to_fetch_registers = mips64_linux_fetch_registers; | |
1075 | t->to_store_registers = mips64_linux_store_registers; | |
1076 | ||
b9412953 DD |
1077 | t->to_can_use_hw_breakpoint = mips_linux_can_use_hw_breakpoint; |
1078 | t->to_remove_watchpoint = mips_linux_remove_watchpoint; | |
1079 | t->to_insert_watchpoint = mips_linux_insert_watchpoint; | |
1080 | t->to_stopped_by_watchpoint = mips_linux_stopped_by_watchpoint; | |
1081 | t->to_stopped_data_address = mips_linux_stopped_data_address; | |
1082 | t->to_region_ok_for_hw_watchpoint = mips_linux_region_ok_for_hw_watchpoint; | |
1083 | ||
81adfced | 1084 | t->to_read_description = mips_linux_read_description; |
822b6570 | 1085 | |
f973ed9c | 1086 | linux_nat_add_target (t); |
b9412953 | 1087 | linux_nat_set_new_thread (t, mips_linux_new_thread); |
81adfced DJ |
1088 | |
1089 | /* Initialize the standard target descriptions. */ | |
1090 | initialize_tdesc_mips_linux (); | |
1091 | initialize_tdesc_mips64_linux (); | |
10d6c8cd | 1092 | } |