Commit | Line | Data |
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75c9abc6 | 1 | /* Target-dependent code for GNU/Linux on MIPS processors. |
a094c6fb | 2 | |
6aba47ca | 3 | Copyright (C) 2001, 2002, 2004, 2005, 2006, 2007 |
76a9d10f | 4 | Free Software Foundation, Inc. |
2aa830e4 DJ |
5 | |
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
197e01b6 EZ |
20 | Foundation, Inc., 51 Franklin Street, Fifth Floor, |
21 | Boston, MA 02110-1301, USA. */ | |
2aa830e4 DJ |
22 | |
23 | #include "defs.h" | |
24 | #include "gdbcore.h" | |
25 | #include "target.h" | |
26 | #include "solib-svr4.h" | |
19ed69dd | 27 | #include "osabi.h" |
96f026fc | 28 | #include "mips-tdep.h" |
19ed69dd | 29 | #include "gdb_string.h" |
96f026fc | 30 | #include "gdb_assert.h" |
6de918a6 | 31 | #include "frame.h" |
2fdf551c | 32 | #include "regcache.h" |
5792a79b DJ |
33 | #include "trad-frame.h" |
34 | #include "tramp-frame.h" | |
e6bb342a | 35 | #include "gdbtypes.h" |
5ea03926 | 36 | #include "solib.h" |
7d522c90 DJ |
37 | #include "solib-svr4.h" |
38 | #include "solist.h" | |
982e9687 | 39 | #include "symtab.h" |
822b6570 | 40 | #include "target-descriptions.h" |
d37eb719 | 41 | #include "mips-linux-tdep.h" |
2aa830e4 | 42 | |
7d522c90 DJ |
43 | static struct target_so_ops mips_svr4_so_ops; |
44 | ||
2aa830e4 | 45 | /* Figure out where the longjmp will land. |
295093a4 MS |
46 | We expect the first arg to be a pointer to the jmp_buf structure |
47 | from which we extract the pc (MIPS_LINUX_JB_PC) that we will land | |
48 | at. The pc is copied into PC. This routine returns 1 on | |
49 | success. */ | |
2aa830e4 | 50 | |
19ed69dd KB |
51 | #define MIPS_LINUX_JB_ELEMENT_SIZE 4 |
52 | #define MIPS_LINUX_JB_PC 0 | |
53 | ||
54 | static int | |
60ade65d | 55 | mips_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
2aa830e4 DJ |
56 | { |
57 | CORE_ADDR jb_addr; | |
819844ad | 58 | char buf[gdbarch_ptr_bit (current_gdbarch) / TARGET_CHAR_BIT]; |
2aa830e4 | 59 | |
60ade65d | 60 | jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM); |
2aa830e4 | 61 | |
bf072999 | 62 | if (target_read_memory (jb_addr |
819844ad UW |
63 | + MIPS_LINUX_JB_PC * MIPS_LINUX_JB_ELEMENT_SIZE, |
64 | buf, | |
65 | gdbarch_ptr_bit (current_gdbarch) / TARGET_CHAR_BIT)) | |
2aa830e4 DJ |
66 | return 0; |
67 | ||
819844ad UW |
68 | *pc = extract_unsigned_integer (buf, |
69 | gdbarch_ptr_bit (current_gdbarch) | |
70 | / TARGET_CHAR_BIT); | |
2aa830e4 DJ |
71 | |
72 | return 1; | |
73 | } | |
74 | ||
4246e332 | 75 | /* Transform the bits comprising a 32-bit register to the right size |
23a6d369 AC |
76 | for regcache_raw_supply(). This is needed when mips_isa_regsize() |
77 | is 8. */ | |
96f026fc KB |
78 | |
79 | static void | |
28f5035f | 80 | supply_32bit_reg (struct regcache *regcache, int regnum, const void *addr) |
96f026fc | 81 | { |
d37eb719 | 82 | gdb_byte buf[MAX_REGISTER_SIZE]; |
3acba339 | 83 | store_signed_integer (buf, register_size (current_gdbarch, regnum), |
96f026fc | 84 | extract_signed_integer (addr, 4)); |
28f5035f | 85 | regcache_raw_supply (regcache, regnum, buf); |
96f026fc KB |
86 | } |
87 | ||
2aa830e4 DJ |
88 | /* Unpack an elf_gregset_t into GDB's register cache. */ |
89 | ||
d37eb719 | 90 | void |
28f5035f UW |
91 | mips_supply_gregset (struct regcache *regcache, |
92 | const mips_elf_gregset_t *gregsetp) | |
2aa830e4 DJ |
93 | { |
94 | int regi; | |
28f5035f | 95 | const mips_elf_greg_t *regp = *gregsetp; |
d9d9c31f | 96 | char zerobuf[MAX_REGISTER_SIZE]; |
bf072999 | 97 | |
d9d9c31f | 98 | memset (zerobuf, 0, MAX_REGISTER_SIZE); |
2aa830e4 | 99 | |
822b6570 | 100 | for (regi = EF_REG0 + 1; regi <= EF_REG31; regi++) |
28f5035f | 101 | supply_32bit_reg (regcache, regi - EF_REG0, regp + regi); |
2aa830e4 | 102 | |
822b6570 DJ |
103 | if (mips_linux_restart_reg_p (current_gdbarch)) |
104 | supply_32bit_reg (regcache, MIPS_RESTART_REGNUM, regp + EF_REG0); | |
105 | ||
28f5035f UW |
106 | supply_32bit_reg (regcache, mips_regnum (current_gdbarch)->lo, |
107 | regp + EF_LO); | |
108 | supply_32bit_reg (regcache, mips_regnum (current_gdbarch)->hi, | |
109 | regp + EF_HI); | |
56cea623 | 110 | |
28f5035f UW |
111 | supply_32bit_reg (regcache, mips_regnum (current_gdbarch)->pc, |
112 | regp + EF_CP0_EPC); | |
113 | supply_32bit_reg (regcache, mips_regnum (current_gdbarch)->badvaddr, | |
114 | regp + EF_CP0_BADVADDR); | |
115 | supply_32bit_reg (regcache, MIPS_PS_REGNUM, regp + EF_CP0_STATUS); | |
116 | supply_32bit_reg (regcache, mips_regnum (current_gdbarch)->cause, | |
117 | regp + EF_CP0_CAUSE); | |
2aa830e4 DJ |
118 | |
119 | /* Fill inaccessible registers with zero. */ | |
822b6570 | 120 | regcache_raw_supply (regcache, MIPS_ZERO_REGNUM, zerobuf); |
28f5035f | 121 | regcache_raw_supply (regcache, MIPS_UNUSED_REGNUM, zerobuf); |
295093a4 | 122 | for (regi = MIPS_FIRST_EMBED_REGNUM; |
822b6570 | 123 | regi <= MIPS_LAST_EMBED_REGNUM; |
295093a4 | 124 | regi++) |
28f5035f | 125 | regcache_raw_supply (regcache, regi, zerobuf); |
2aa830e4 DJ |
126 | } |
127 | ||
128 | /* Pack our registers (or one register) into an elf_gregset_t. */ | |
129 | ||
d37eb719 | 130 | void |
28f5035f UW |
131 | mips_fill_gregset (const struct regcache *regcache, |
132 | mips_elf_gregset_t *gregsetp, int regno) | |
2aa830e4 DJ |
133 | { |
134 | int regaddr, regi; | |
d37eb719 | 135 | mips_elf_greg_t *regp = *gregsetp; |
96f026fc | 136 | void *dst; |
2aa830e4 DJ |
137 | |
138 | if (regno == -1) | |
139 | { | |
d37eb719 | 140 | memset (regp, 0, sizeof (mips_elf_gregset_t)); |
822b6570 | 141 | for (regi = 1; regi < 32; regi++) |
28f5035f UW |
142 | mips_fill_gregset (regcache, gregsetp, regi); |
143 | mips_fill_gregset (regcache, gregsetp, | |
144 | mips_regnum (current_gdbarch)->lo); | |
145 | mips_fill_gregset (regcache, gregsetp, | |
146 | mips_regnum (current_gdbarch)->hi); | |
147 | mips_fill_gregset (regcache, gregsetp, | |
148 | mips_regnum (current_gdbarch)->pc); | |
149 | mips_fill_gregset (regcache, gregsetp, | |
150 | mips_regnum (current_gdbarch)->badvaddr); | |
151 | mips_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM); | |
152 | mips_fill_gregset (regcache, gregsetp, | |
153 | mips_regnum (current_gdbarch)->cause); | |
822b6570 | 154 | mips_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM); |
2aa830e4 DJ |
155 | return; |
156 | } | |
157 | ||
822b6570 | 158 | if (regno > 0 && regno < 32) |
2aa830e4 | 159 | { |
2aa830e4 | 160 | dst = regp + regno + EF_REG0; |
28f5035f | 161 | regcache_raw_collect (regcache, regno, dst); |
2aa830e4 DJ |
162 | return; |
163 | } | |
164 | ||
56cea623 AC |
165 | if (regno == mips_regnum (current_gdbarch)->lo) |
166 | regaddr = EF_LO; | |
167 | else if (regno == mips_regnum (current_gdbarch)->hi) | |
168 | regaddr = EF_HI; | |
169 | else if (regno == mips_regnum (current_gdbarch)->pc) | |
170 | regaddr = EF_CP0_EPC; | |
171 | else if (regno == mips_regnum (current_gdbarch)->badvaddr) | |
172 | regaddr = EF_CP0_BADVADDR; | |
24e05951 | 173 | else if (regno == MIPS_PS_REGNUM) |
56cea623 AC |
174 | regaddr = EF_CP0_STATUS; |
175 | else if (regno == mips_regnum (current_gdbarch)->cause) | |
176 | regaddr = EF_CP0_CAUSE; | |
822b6570 DJ |
177 | else if (mips_linux_restart_reg_p (current_gdbarch) |
178 | && regno == MIPS_RESTART_REGNUM) | |
179 | regaddr = EF_REG0; | |
56cea623 AC |
180 | else |
181 | regaddr = -1; | |
2aa830e4 DJ |
182 | |
183 | if (regaddr != -1) | |
184 | { | |
2aa830e4 | 185 | dst = regp + regaddr; |
28f5035f | 186 | regcache_raw_collect (regcache, regno, dst); |
2aa830e4 DJ |
187 | } |
188 | } | |
189 | ||
190 | /* Likewise, unpack an elf_fpregset_t. */ | |
191 | ||
d37eb719 | 192 | void |
28f5035f UW |
193 | mips_supply_fpregset (struct regcache *regcache, |
194 | const mips_elf_fpregset_t *fpregsetp) | |
2aa830e4 | 195 | { |
52f0bd74 | 196 | int regi; |
d9d9c31f | 197 | char zerobuf[MAX_REGISTER_SIZE]; |
bf072999 | 198 | |
d9d9c31f | 199 | memset (zerobuf, 0, MAX_REGISTER_SIZE); |
2aa830e4 DJ |
200 | |
201 | for (regi = 0; regi < 32; regi++) | |
3e8c568d UW |
202 | regcache_raw_supply (regcache, |
203 | gdbarch_fp0_regnum (current_gdbarch) + regi, | |
204 | *fpregsetp + regi); | |
2aa830e4 | 205 | |
28f5035f | 206 | regcache_raw_supply (regcache, |
23a6d369 | 207 | mips_regnum (current_gdbarch)->fp_control_status, |
28f5035f | 208 | *fpregsetp + 32); |
2aa830e4 | 209 | |
295093a4 | 210 | /* FIXME: how can we supply FCRIR? The ABI doesn't tell us. */ |
28f5035f | 211 | regcache_raw_supply (regcache, |
23a6d369 AC |
212 | mips_regnum (current_gdbarch)->fp_implementation_revision, |
213 | zerobuf); | |
2aa830e4 DJ |
214 | } |
215 | ||
216 | /* Likewise, pack one or all floating point registers into an | |
217 | elf_fpregset_t. */ | |
218 | ||
d37eb719 | 219 | void |
28f5035f UW |
220 | mips_fill_fpregset (const struct regcache *regcache, |
221 | mips_elf_fpregset_t *fpregsetp, int regno) | |
2aa830e4 DJ |
222 | { |
223 | char *from, *to; | |
224 | ||
3e8c568d UW |
225 | if ((regno >= gdbarch_fp0_regnum (current_gdbarch)) |
226 | && (regno < gdbarch_fp0_regnum (current_gdbarch) + 32)) | |
2aa830e4 | 227 | { |
3e8c568d | 228 | to = (char *) (*fpregsetp + regno - gdbarch_fp0_regnum (current_gdbarch)); |
28f5035f | 229 | regcache_raw_collect (regcache, regno, to); |
2aa830e4 | 230 | } |
56cea623 | 231 | else if (regno == mips_regnum (current_gdbarch)->fp_control_status) |
2aa830e4 | 232 | { |
2aa830e4 | 233 | to = (char *) (*fpregsetp + 32); |
28f5035f | 234 | regcache_raw_collect (regcache, regno, to); |
2aa830e4 DJ |
235 | } |
236 | else if (regno == -1) | |
237 | { | |
238 | int regi; | |
239 | ||
240 | for (regi = 0; regi < 32; regi++) | |
3e8c568d UW |
241 | mips_fill_fpregset (regcache, fpregsetp, |
242 | gdbarch_fp0_regnum (current_gdbarch) + regi); | |
28f5035f | 243 | mips_fill_fpregset (regcache, fpregsetp, |
9f62d0e2 | 244 | mips_regnum (current_gdbarch)->fp_control_status); |
2aa830e4 DJ |
245 | } |
246 | } | |
247 | ||
96f026fc KB |
248 | /* Support for 64-bit ABIs. */ |
249 | ||
96f026fc | 250 | /* Figure out where the longjmp will land. |
295093a4 MS |
251 | We expect the first arg to be a pointer to the jmp_buf structure |
252 | from which we extract the pc (MIPS_LINUX_JB_PC) that we will land | |
253 | at. The pc is copied into PC. This routine returns 1 on | |
254 | success. */ | |
96f026fc KB |
255 | |
256 | /* Details about jmp_buf. */ | |
257 | ||
258 | #define MIPS64_LINUX_JB_PC 0 | |
259 | ||
260 | static int | |
60ade65d | 261 | mips64_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
96f026fc KB |
262 | { |
263 | CORE_ADDR jb_addr; | |
819844ad UW |
264 | void *buf = alloca (gdbarch_ptr_bit (current_gdbarch) / TARGET_CHAR_BIT); |
265 | int element_size = gdbarch_ptr_bit (current_gdbarch) == 32 ? 4 : 8; | |
96f026fc | 266 | |
60ade65d | 267 | jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM); |
96f026fc KB |
268 | |
269 | if (target_read_memory (jb_addr + MIPS64_LINUX_JB_PC * element_size, | |
819844ad UW |
270 | buf, |
271 | gdbarch_ptr_bit (current_gdbarch) / TARGET_CHAR_BIT)) | |
96f026fc KB |
272 | return 0; |
273 | ||
819844ad UW |
274 | *pc = extract_unsigned_integer (buf, |
275 | gdbarch_ptr_bit (current_gdbarch) | |
276 | / TARGET_CHAR_BIT); | |
96f026fc KB |
277 | |
278 | return 1; | |
279 | } | |
280 | ||
d37eb719 DJ |
281 | /* Register set support functions. These operate on standard 64-bit |
282 | regsets, but work whether the target is 32-bit or 64-bit. A 32-bit | |
283 | target will still use the 64-bit format for PTRACE_GETREGS. */ | |
284 | ||
285 | /* Supply a 64-bit register. */ | |
96f026fc | 286 | |
d37eb719 | 287 | void |
28f5035f UW |
288 | supply_64bit_reg (struct regcache *regcache, int regnum, |
289 | const gdb_byte *buf) | |
d37eb719 DJ |
290 | { |
291 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG | |
292 | && register_size (current_gdbarch, regnum) == 4) | |
28f5035f | 293 | regcache_raw_supply (regcache, regnum, buf + 4); |
d37eb719 | 294 | else |
28f5035f | 295 | regcache_raw_supply (regcache, regnum, buf); |
d37eb719 DJ |
296 | } |
297 | ||
298 | /* Unpack a 64-bit elf_gregset_t into GDB's register cache. */ | |
299 | ||
300 | void | |
28f5035f UW |
301 | mips64_supply_gregset (struct regcache *regcache, |
302 | const mips64_elf_gregset_t *gregsetp) | |
96f026fc KB |
303 | { |
304 | int regi; | |
28f5035f | 305 | const mips64_elf_greg_t *regp = *gregsetp; |
d37eb719 | 306 | gdb_byte zerobuf[MAX_REGISTER_SIZE]; |
96f026fc | 307 | |
d9d9c31f | 308 | memset (zerobuf, 0, MAX_REGISTER_SIZE); |
96f026fc | 309 | |
822b6570 | 310 | for (regi = MIPS64_EF_REG0 + 1; regi <= MIPS64_EF_REG31; regi++) |
28f5035f UW |
311 | supply_64bit_reg (regcache, regi - MIPS64_EF_REG0, |
312 | (const gdb_byte *)(regp + regi)); | |
313 | ||
822b6570 DJ |
314 | if (mips_linux_restart_reg_p (current_gdbarch)) |
315 | supply_64bit_reg (regcache, MIPS_RESTART_REGNUM, | |
316 | (const gdb_byte *)(regp + MIPS64_EF_REG0)); | |
317 | ||
28f5035f UW |
318 | supply_64bit_reg (regcache, mips_regnum (current_gdbarch)->lo, |
319 | (const gdb_byte *) (regp + MIPS64_EF_LO)); | |
320 | supply_64bit_reg (regcache, mips_regnum (current_gdbarch)->hi, | |
321 | (const gdb_byte *) (regp + MIPS64_EF_HI)); | |
322 | ||
323 | supply_64bit_reg (regcache, mips_regnum (current_gdbarch)->pc, | |
324 | (const gdb_byte *) (regp + MIPS64_EF_CP0_EPC)); | |
325 | supply_64bit_reg (regcache, mips_regnum (current_gdbarch)->badvaddr, | |
326 | (const gdb_byte *) (regp + MIPS64_EF_CP0_BADVADDR)); | |
327 | supply_64bit_reg (regcache, MIPS_PS_REGNUM, | |
328 | (const gdb_byte *) (regp + MIPS64_EF_CP0_STATUS)); | |
329 | supply_64bit_reg (regcache, mips_regnum (current_gdbarch)->cause, | |
330 | (const gdb_byte *) (regp + MIPS64_EF_CP0_CAUSE)); | |
96f026fc KB |
331 | |
332 | /* Fill inaccessible registers with zero. */ | |
822b6570 | 333 | regcache_raw_supply (regcache, MIPS_ZERO_REGNUM, zerobuf); |
28f5035f | 334 | regcache_raw_supply (regcache, MIPS_UNUSED_REGNUM, zerobuf); |
295093a4 | 335 | for (regi = MIPS_FIRST_EMBED_REGNUM; |
822b6570 | 336 | regi <= MIPS_LAST_EMBED_REGNUM; |
295093a4 | 337 | regi++) |
28f5035f | 338 | regcache_raw_supply (regcache, regi, zerobuf); |
96f026fc KB |
339 | } |
340 | ||
d37eb719 | 341 | /* Pack our registers (or one register) into a 64-bit elf_gregset_t. */ |
96f026fc | 342 | |
d37eb719 | 343 | void |
28f5035f UW |
344 | mips64_fill_gregset (const struct regcache *regcache, |
345 | mips64_elf_gregset_t *gregsetp, int regno) | |
96f026fc KB |
346 | { |
347 | int regaddr, regi; | |
348 | mips64_elf_greg_t *regp = *gregsetp; | |
349 | void *src, *dst; | |
350 | ||
351 | if (regno == -1) | |
352 | { | |
353 | memset (regp, 0, sizeof (mips64_elf_gregset_t)); | |
822b6570 | 354 | for (regi = 1; regi < 32; regi++) |
28f5035f UW |
355 | mips64_fill_gregset (regcache, gregsetp, regi); |
356 | mips64_fill_gregset (regcache, gregsetp, | |
357 | mips_regnum (current_gdbarch)->lo); | |
358 | mips64_fill_gregset (regcache, gregsetp, | |
359 | mips_regnum (current_gdbarch)->hi); | |
360 | mips64_fill_gregset (regcache, gregsetp, | |
361 | mips_regnum (current_gdbarch)->pc); | |
362 | mips64_fill_gregset (regcache, gregsetp, | |
295093a4 | 363 | mips_regnum (current_gdbarch)->badvaddr); |
28f5035f UW |
364 | mips64_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM); |
365 | mips64_fill_gregset (regcache, gregsetp, | |
295093a4 | 366 | mips_regnum (current_gdbarch)->cause); |
822b6570 | 367 | mips64_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM); |
96f026fc KB |
368 | return; |
369 | } | |
370 | ||
822b6570 | 371 | if (regno > 0 && regno < 32) |
d37eb719 DJ |
372 | regaddr = regno + MIPS64_EF_REG0; |
373 | else if (regno == mips_regnum (current_gdbarch)->lo) | |
56cea623 AC |
374 | regaddr = MIPS64_EF_LO; |
375 | else if (regno == mips_regnum (current_gdbarch)->hi) | |
376 | regaddr = MIPS64_EF_HI; | |
377 | else if (regno == mips_regnum (current_gdbarch)->pc) | |
378 | regaddr = MIPS64_EF_CP0_EPC; | |
379 | else if (regno == mips_regnum (current_gdbarch)->badvaddr) | |
380 | regaddr = MIPS64_EF_CP0_BADVADDR; | |
24e05951 | 381 | else if (regno == MIPS_PS_REGNUM) |
56cea623 AC |
382 | regaddr = MIPS64_EF_CP0_STATUS; |
383 | else if (regno == mips_regnum (current_gdbarch)->cause) | |
384 | regaddr = MIPS64_EF_CP0_CAUSE; | |
822b6570 DJ |
385 | else if (mips_linux_restart_reg_p (current_gdbarch) |
386 | && regno == MIPS_RESTART_REGNUM) | |
387 | regaddr = MIPS64_EF_REG0; | |
56cea623 AC |
388 | else |
389 | regaddr = -1; | |
96f026fc KB |
390 | |
391 | if (regaddr != -1) | |
392 | { | |
d37eb719 DJ |
393 | gdb_byte buf[MAX_REGISTER_SIZE]; |
394 | LONGEST val; | |
395 | ||
28f5035f | 396 | regcache_raw_collect (regcache, regno, buf); |
d37eb719 DJ |
397 | val = extract_signed_integer (buf, |
398 | register_size (current_gdbarch, regno)); | |
96f026fc | 399 | dst = regp + regaddr; |
d37eb719 | 400 | store_signed_integer (dst, 8, val); |
96f026fc KB |
401 | } |
402 | } | |
403 | ||
404 | /* Likewise, unpack an elf_fpregset_t. */ | |
405 | ||
d37eb719 | 406 | void |
28f5035f UW |
407 | mips64_supply_fpregset (struct regcache *regcache, |
408 | const mips64_elf_fpregset_t *fpregsetp) | |
96f026fc | 409 | { |
52f0bd74 | 410 | int regi; |
96f026fc | 411 | |
d37eb719 DJ |
412 | /* See mips_linux_o32_sigframe_init for a description of the |
413 | peculiar FP register layout. */ | |
3e8c568d UW |
414 | if (register_size (current_gdbarch, |
415 | gdbarch_fp0_regnum (current_gdbarch)) == 4) | |
d37eb719 DJ |
416 | for (regi = 0; regi < 32; regi++) |
417 | { | |
28f5035f | 418 | const gdb_byte *reg_ptr = (const gdb_byte *)(*fpregsetp + (regi & ~1)); |
4c6b5505 UW |
419 | if ((gdbarch_byte_order (current_gdbarch) |
420 | == BFD_ENDIAN_BIG) != (regi & 1)) | |
d37eb719 | 421 | reg_ptr += 4; |
3e8c568d UW |
422 | regcache_raw_supply (regcache, |
423 | gdbarch_fp0_regnum (current_gdbarch) + regi, | |
424 | reg_ptr); | |
d37eb719 DJ |
425 | } |
426 | else | |
427 | for (regi = 0; regi < 32; regi++) | |
3e8c568d UW |
428 | regcache_raw_supply (regcache, |
429 | gdbarch_fp0_regnum (current_gdbarch) + regi, | |
28f5035f | 430 | (const char *)(*fpregsetp + regi)); |
d37eb719 | 431 | |
28f5035f UW |
432 | supply_32bit_reg (regcache, mips_regnum (current_gdbarch)->fp_control_status, |
433 | (const gdb_byte *)(*fpregsetp + 32)); | |
d37eb719 DJ |
434 | |
435 | /* The ABI doesn't tell us how to supply FCRIR, and core dumps don't | |
436 | include it - but the result of PTRACE_GETFPREGS does. The best we | |
437 | can do is to assume that its value is present. */ | |
28f5035f UW |
438 | supply_32bit_reg (regcache, |
439 | mips_regnum (current_gdbarch)->fp_implementation_revision, | |
440 | (const gdb_byte *)(*fpregsetp + 32) + 4); | |
96f026fc KB |
441 | } |
442 | ||
443 | /* Likewise, pack one or all floating point registers into an | |
444 | elf_fpregset_t. */ | |
445 | ||
d37eb719 | 446 | void |
28f5035f UW |
447 | mips64_fill_fpregset (const struct regcache *regcache, |
448 | mips64_elf_fpregset_t *fpregsetp, int regno) | |
96f026fc | 449 | { |
d37eb719 | 450 | gdb_byte *to; |
96f026fc | 451 | |
3e8c568d UW |
452 | if ((regno >= gdbarch_fp0_regnum (current_gdbarch)) |
453 | && (regno < gdbarch_fp0_regnum (current_gdbarch) + 32)) | |
96f026fc | 454 | { |
d37eb719 DJ |
455 | /* See mips_linux_o32_sigframe_init for a description of the |
456 | peculiar FP register layout. */ | |
457 | if (register_size (current_gdbarch, regno) == 4) | |
458 | { | |
3e8c568d | 459 | int regi = regno - gdbarch_fp0_regnum (current_gdbarch); |
d37eb719 DJ |
460 | |
461 | to = (gdb_byte *) (*fpregsetp + (regi & ~1)); | |
4c6b5505 UW |
462 | if ((gdbarch_byte_order (current_gdbarch) |
463 | == BFD_ENDIAN_BIG) != (regi & 1)) | |
d37eb719 | 464 | to += 4; |
28f5035f | 465 | regcache_raw_collect (regcache, regno, to); |
d37eb719 DJ |
466 | } |
467 | else | |
468 | { | |
3e8c568d UW |
469 | to = (gdb_byte *) (*fpregsetp + regno |
470 | - gdbarch_fp0_regnum (current_gdbarch)); | |
28f5035f | 471 | regcache_raw_collect (regcache, regno, to); |
d37eb719 | 472 | } |
96f026fc | 473 | } |
56cea623 | 474 | else if (regno == mips_regnum (current_gdbarch)->fp_control_status) |
96f026fc | 475 | { |
d37eb719 DJ |
476 | gdb_byte buf[MAX_REGISTER_SIZE]; |
477 | LONGEST val; | |
478 | ||
28f5035f | 479 | regcache_raw_collect (regcache, regno, buf); |
d37eb719 DJ |
480 | val = extract_signed_integer (buf, |
481 | register_size (current_gdbarch, regno)); | |
482 | to = (gdb_byte *) (*fpregsetp + 32); | |
483 | store_signed_integer (to, 4, val); | |
484 | } | |
485 | else if (regno == mips_regnum (current_gdbarch)->fp_implementation_revision) | |
486 | { | |
487 | gdb_byte buf[MAX_REGISTER_SIZE]; | |
488 | LONGEST val; | |
489 | ||
28f5035f | 490 | regcache_raw_collect (regcache, regno, buf); |
d37eb719 DJ |
491 | val = extract_signed_integer (buf, |
492 | register_size (current_gdbarch, regno)); | |
493 | to = (gdb_byte *) (*fpregsetp + 32) + 4; | |
494 | store_signed_integer (to, 4, val); | |
96f026fc KB |
495 | } |
496 | else if (regno == -1) | |
497 | { | |
498 | int regi; | |
499 | ||
500 | for (regi = 0; regi < 32; regi++) | |
3e8c568d UW |
501 | mips64_fill_fpregset (regcache, fpregsetp, |
502 | gdbarch_fp0_regnum (current_gdbarch) + regi); | |
28f5035f | 503 | mips64_fill_fpregset (regcache, fpregsetp, |
d37eb719 | 504 | mips_regnum (current_gdbarch)->fp_control_status); |
28f5035f UW |
505 | mips64_fill_fpregset (regcache, fpregsetp, |
506 | (mips_regnum (current_gdbarch) | |
507 | ->fp_implementation_revision)); | |
96f026fc KB |
508 | } |
509 | } | |
510 | ||
511 | ||
2aa830e4 DJ |
512 | /* Use a local version of this function to get the correct types for |
513 | regsets, until multi-arch core support is ready. */ | |
514 | ||
515 | static void | |
9eefc95f UW |
516 | fetch_core_registers (struct regcache *regcache, |
517 | char *core_reg_sect, unsigned core_reg_size, | |
2aa830e4 DJ |
518 | int which, CORE_ADDR reg_addr) |
519 | { | |
d37eb719 DJ |
520 | mips_elf_gregset_t gregset; |
521 | mips_elf_fpregset_t fpregset; | |
96f026fc KB |
522 | mips64_elf_gregset_t gregset64; |
523 | mips64_elf_fpregset_t fpregset64; | |
2aa830e4 DJ |
524 | |
525 | if (which == 0) | |
526 | { | |
96f026fc | 527 | if (core_reg_size == sizeof (gregset)) |
2aa830e4 | 528 | { |
96f026fc | 529 | memcpy ((char *) &gregset, core_reg_sect, sizeof (gregset)); |
9eefc95f | 530 | mips_supply_gregset (regcache, |
28f5035f | 531 | (const mips_elf_gregset_t *) &gregset); |
96f026fc KB |
532 | } |
533 | else if (core_reg_size == sizeof (gregset64)) | |
534 | { | |
535 | memcpy ((char *) &gregset64, core_reg_sect, sizeof (gregset64)); | |
9eefc95f | 536 | mips64_supply_gregset (regcache, |
28f5035f | 537 | (const mips64_elf_gregset_t *) &gregset64); |
2aa830e4 DJ |
538 | } |
539 | else | |
540 | { | |
8a3fe4f8 | 541 | warning (_("wrong size gregset struct in core file")); |
2aa830e4 DJ |
542 | } |
543 | } | |
544 | else if (which == 2) | |
545 | { | |
96f026fc | 546 | if (core_reg_size == sizeof (fpregset)) |
2aa830e4 | 547 | { |
96f026fc | 548 | memcpy ((char *) &fpregset, core_reg_sect, sizeof (fpregset)); |
9eefc95f | 549 | mips_supply_fpregset (regcache, |
28f5035f | 550 | (const mips_elf_fpregset_t *) &fpregset); |
96f026fc KB |
551 | } |
552 | else if (core_reg_size == sizeof (fpregset64)) | |
553 | { | |
295093a4 MS |
554 | memcpy ((char *) &fpregset64, core_reg_sect, |
555 | sizeof (fpregset64)); | |
9eefc95f | 556 | mips64_supply_fpregset (regcache, |
28f5035f | 557 | (const mips64_elf_fpregset_t *) &fpregset64); |
2aa830e4 DJ |
558 | } |
559 | else | |
560 | { | |
8a3fe4f8 | 561 | warning (_("wrong size fpregset struct in core file")); |
2aa830e4 DJ |
562 | } |
563 | } | |
564 | } | |
565 | ||
566 | /* Register that we are able to handle ELF file formats using standard | |
567 | procfs "regset" structures. */ | |
568 | ||
569 | static struct core_fns regset_core_fns = | |
570 | { | |
571 | bfd_target_elf_flavour, /* core_flavour */ | |
572 | default_check_format, /* check_format */ | |
573 | default_core_sniffer, /* core_sniffer */ | |
574 | fetch_core_registers, /* core_read_registers */ | |
575 | NULL /* next */ | |
576 | }; | |
577 | ||
96f026fc | 578 | |
295093a4 MS |
579 | /* Check the code at PC for a dynamic linker lazy resolution stub. |
580 | Because they aren't in the .plt section, we pattern-match on the | |
581 | code generated by GNU ld. They look like this: | |
6de918a6 DJ |
582 | |
583 | lw t9,0x8010(gp) | |
584 | addu t7,ra | |
585 | jalr t9,ra | |
586 | addiu t8,zero,INDEX | |
587 | ||
295093a4 MS |
588 | (with the appropriate doubleword instructions for N64). Also |
589 | return the dynamic symbol index used in the last instruction. */ | |
6de918a6 DJ |
590 | |
591 | static int | |
592 | mips_linux_in_dynsym_stub (CORE_ADDR pc, char *name) | |
593 | { | |
594 | unsigned char buf[28], *p; | |
595 | ULONGEST insn, insn1; | |
596 | int n64 = (mips_abi (current_gdbarch) == MIPS_ABI_N64); | |
597 | ||
598 | read_memory (pc - 12, buf, 28); | |
599 | ||
600 | if (n64) | |
601 | { | |
602 | /* ld t9,0x8010(gp) */ | |
603 | insn1 = 0xdf998010; | |
604 | } | |
605 | else | |
606 | { | |
607 | /* lw t9,0x8010(gp) */ | |
608 | insn1 = 0x8f998010; | |
609 | } | |
610 | ||
611 | p = buf + 12; | |
612 | while (p >= buf) | |
613 | { | |
614 | insn = extract_unsigned_integer (p, 4); | |
615 | if (insn == insn1) | |
616 | break; | |
617 | p -= 4; | |
618 | } | |
619 | if (p < buf) | |
620 | return 0; | |
621 | ||
622 | insn = extract_unsigned_integer (p + 4, 4); | |
623 | if (n64) | |
624 | { | |
625 | /* daddu t7,ra */ | |
626 | if (insn != 0x03e0782d) | |
627 | return 0; | |
628 | } | |
629 | else | |
630 | { | |
631 | /* addu t7,ra */ | |
632 | if (insn != 0x03e07821) | |
633 | return 0; | |
634 | } | |
295093a4 | 635 | |
6de918a6 DJ |
636 | insn = extract_unsigned_integer (p + 8, 4); |
637 | /* jalr t9,ra */ | |
638 | if (insn != 0x0320f809) | |
639 | return 0; | |
640 | ||
641 | insn = extract_unsigned_integer (p + 12, 4); | |
642 | if (n64) | |
643 | { | |
644 | /* daddiu t8,zero,0 */ | |
645 | if ((insn & 0xffff0000) != 0x64180000) | |
646 | return 0; | |
647 | } | |
648 | else | |
649 | { | |
650 | /* addiu t8,zero,0 */ | |
651 | if ((insn & 0xffff0000) != 0x24180000) | |
652 | return 0; | |
653 | } | |
654 | ||
655 | return (insn & 0xffff); | |
656 | } | |
657 | ||
295093a4 MS |
658 | /* Return non-zero iff PC belongs to the dynamic linker resolution |
659 | code or to a stub. */ | |
6de918a6 | 660 | |
7d522c90 | 661 | static int |
6de918a6 DJ |
662 | mips_linux_in_dynsym_resolve_code (CORE_ADDR pc) |
663 | { | |
295093a4 MS |
664 | /* Check whether PC is in the dynamic linker. This also checks |
665 | whether it is in the .plt section, which MIPS does not use. */ | |
7d522c90 | 666 | if (svr4_in_dynsym_resolve_code (pc)) |
6de918a6 DJ |
667 | return 1; |
668 | ||
295093a4 MS |
669 | /* Pattern match for the stub. It would be nice if there were a |
670 | more efficient way to avoid this check. */ | |
6de918a6 DJ |
671 | if (mips_linux_in_dynsym_stub (pc, NULL)) |
672 | return 1; | |
673 | ||
674 | return 0; | |
675 | } | |
676 | ||
677 | /* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c, | |
678 | and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc | |
679 | implementation of this triggers at "fixup" from the same objfile as | |
c4c5b7ba AC |
680 | "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at |
681 | "__dl_runtime_resolve" directly. An unresolved PLT entry will | |
682 | point to _dl_runtime_resolve, which will first call | |
683 | __dl_runtime_resolve, and then pass control to the resolved | |
684 | function. */ | |
6de918a6 DJ |
685 | |
686 | static CORE_ADDR | |
687 | mips_linux_skip_resolver (struct gdbarch *gdbarch, CORE_ADDR pc) | |
688 | { | |
689 | struct minimal_symbol *resolver; | |
690 | ||
691 | resolver = lookup_minimal_symbol ("__dl_runtime_resolve", NULL, NULL); | |
692 | ||
693 | if (resolver && SYMBOL_VALUE_ADDRESS (resolver) == pc) | |
295093a4 | 694 | return frame_pc_unwind (get_current_frame ()); |
6de918a6 DJ |
695 | |
696 | return 0; | |
295093a4 | 697 | } |
6de918a6 | 698 | |
5792a79b DJ |
699 | /* Signal trampoline support. There are four supported layouts for a |
700 | signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and | |
701 | n64 rt_sigframe. We handle them all independently; not the most | |
702 | efficient way, but simplest. First, declare all the unwinders. */ | |
703 | ||
704 | static void mips_linux_o32_sigframe_init (const struct tramp_frame *self, | |
705 | struct frame_info *next_frame, | |
706 | struct trad_frame_cache *this_cache, | |
707 | CORE_ADDR func); | |
708 | ||
709 | static void mips_linux_n32n64_sigframe_init (const struct tramp_frame *self, | |
710 | struct frame_info *next_frame, | |
711 | struct trad_frame_cache *this_cache, | |
712 | CORE_ADDR func); | |
713 | ||
714 | #define MIPS_NR_LINUX 4000 | |
715 | #define MIPS_NR_N64_LINUX 5000 | |
716 | #define MIPS_NR_N32_LINUX 6000 | |
717 | ||
718 | #define MIPS_NR_sigreturn MIPS_NR_LINUX + 119 | |
719 | #define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193 | |
720 | #define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211 | |
721 | #define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211 | |
722 | ||
723 | #define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn | |
724 | #define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn | |
725 | #define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn | |
726 | #define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn | |
727 | #define MIPS_INST_SYSCALL 0x0000000c | |
728 | ||
2cd8546d AC |
729 | static const struct tramp_frame mips_linux_o32_sigframe = { |
730 | SIGTRAMP_FRAME, | |
5792a79b | 731 | 4, |
2cd8546d AC |
732 | { |
733 | { MIPS_INST_LI_V0_SIGRETURN, -1 }, | |
734 | { MIPS_INST_SYSCALL, -1 }, | |
735 | { TRAMP_SENTINEL_INSN, -1 } | |
736 | }, | |
5792a79b DJ |
737 | mips_linux_o32_sigframe_init |
738 | }; | |
739 | ||
2cd8546d AC |
740 | static const struct tramp_frame mips_linux_o32_rt_sigframe = { |
741 | SIGTRAMP_FRAME, | |
5792a79b | 742 | 4, |
2cd8546d AC |
743 | { |
744 | { MIPS_INST_LI_V0_RT_SIGRETURN, -1 }, | |
745 | { MIPS_INST_SYSCALL, -1 }, | |
746 | { TRAMP_SENTINEL_INSN, -1 } }, | |
5792a79b DJ |
747 | mips_linux_o32_sigframe_init |
748 | }; | |
749 | ||
2cd8546d AC |
750 | static const struct tramp_frame mips_linux_n32_rt_sigframe = { |
751 | SIGTRAMP_FRAME, | |
5792a79b | 752 | 4, |
2cd8546d AC |
753 | { |
754 | { MIPS_INST_LI_V0_N32_RT_SIGRETURN, -1 }, | |
755 | { MIPS_INST_SYSCALL, -1 }, | |
756 | { TRAMP_SENTINEL_INSN, -1 } | |
757 | }, | |
5792a79b DJ |
758 | mips_linux_n32n64_sigframe_init |
759 | }; | |
760 | ||
2cd8546d AC |
761 | static const struct tramp_frame mips_linux_n64_rt_sigframe = { |
762 | SIGTRAMP_FRAME, | |
5792a79b | 763 | 4, |
fcbd8a5c TS |
764 | { |
765 | { MIPS_INST_LI_V0_N64_RT_SIGRETURN, -1 }, | |
766 | { MIPS_INST_SYSCALL, -1 }, | |
767 | { TRAMP_SENTINEL_INSN, -1 } | |
768 | }, | |
5792a79b DJ |
769 | mips_linux_n32n64_sigframe_init |
770 | }; | |
771 | ||
772 | /* *INDENT-OFF* */ | |
773 | /* The unwinder for o32 signal frames. The legacy structures look | |
774 | like this: | |
775 | ||
776 | struct sigframe { | |
777 | u32 sf_ass[4]; [argument save space for o32] | |
778 | u32 sf_code[2]; [signal trampoline] | |
779 | struct sigcontext sf_sc; | |
780 | sigset_t sf_mask; | |
781 | }; | |
782 | ||
783 | struct sigcontext { | |
784 | unsigned int sc_regmask; [Unused] | |
785 | unsigned int sc_status; | |
786 | unsigned long long sc_pc; | |
787 | unsigned long long sc_regs[32]; | |
788 | unsigned long long sc_fpregs[32]; | |
789 | unsigned int sc_ownedfp; | |
790 | unsigned int sc_fpc_csr; | |
791 | unsigned int sc_fpc_eir; [Unused] | |
792 | unsigned int sc_used_math; | |
793 | unsigned int sc_ssflags; [Unused] | |
794 | [Alignment hole of four bytes] | |
795 | unsigned long long sc_mdhi; | |
796 | unsigned long long sc_mdlo; | |
797 | ||
798 | unsigned int sc_cause; [Unused] | |
799 | unsigned int sc_badvaddr; [Unused] | |
800 | ||
801 | unsigned long sc_sigset[4]; [kernel's sigset_t] | |
802 | }; | |
803 | ||
804 | The RT signal frames look like this: | |
805 | ||
806 | struct rt_sigframe { | |
807 | u32 rs_ass[4]; [argument save space for o32] | |
808 | u32 rs_code[2] [signal trampoline] | |
809 | struct siginfo rs_info; | |
810 | struct ucontext rs_uc; | |
811 | }; | |
812 | ||
813 | struct ucontext { | |
814 | unsigned long uc_flags; | |
815 | struct ucontext *uc_link; | |
816 | stack_t uc_stack; | |
817 | [Alignment hole of four bytes] | |
818 | struct sigcontext uc_mcontext; | |
819 | sigset_t uc_sigmask; | |
820 | }; */ | |
821 | /* *INDENT-ON* */ | |
822 | ||
823 | #define SIGFRAME_CODE_OFFSET (4 * 4) | |
824 | #define SIGFRAME_SIGCONTEXT_OFFSET (6 * 4) | |
825 | ||
826 | #define RTSIGFRAME_SIGINFO_SIZE 128 | |
827 | #define STACK_T_SIZE (3 * 4) | |
828 | #define UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + STACK_T_SIZE + 4) | |
829 | #define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ | |
830 | + RTSIGFRAME_SIGINFO_SIZE \ | |
831 | + UCONTEXT_SIGCONTEXT_OFFSET) | |
832 | ||
833 | #define SIGCONTEXT_PC (1 * 8) | |
834 | #define SIGCONTEXT_REGS (2 * 8) | |
835 | #define SIGCONTEXT_FPREGS (34 * 8) | |
836 | #define SIGCONTEXT_FPCSR (66 * 8 + 4) | |
837 | #define SIGCONTEXT_HI (69 * 8) | |
838 | #define SIGCONTEXT_LO (70 * 8) | |
839 | #define SIGCONTEXT_CAUSE (71 * 8 + 0) | |
840 | #define SIGCONTEXT_BADVADDR (71 * 8 + 4) | |
841 | ||
842 | #define SIGCONTEXT_REG_SIZE 8 | |
843 | ||
844 | static void | |
845 | mips_linux_o32_sigframe_init (const struct tramp_frame *self, | |
846 | struct frame_info *next_frame, | |
847 | struct trad_frame_cache *this_cache, | |
848 | CORE_ADDR func) | |
849 | { | |
850 | int ireg, reg_position; | |
851 | CORE_ADDR sigcontext_base = func - SIGFRAME_CODE_OFFSET; | |
852 | const struct mips_regnum *regs = mips_regnum (current_gdbarch); | |
37c4d197 | 853 | CORE_ADDR regs_base; |
5792a79b DJ |
854 | |
855 | if (self == &mips_linux_o32_sigframe) | |
856 | sigcontext_base += SIGFRAME_SIGCONTEXT_OFFSET; | |
857 | else | |
858 | sigcontext_base += RTSIGFRAME_SIGCONTEXT_OFFSET; | |
295093a4 MS |
859 | |
860 | /* I'm not proud of this hack. Eventually we will have the | |
861 | infrastructure to indicate the size of saved registers on a | |
862 | per-frame basis, but right now we don't; the kernel saves eight | |
37c4d197 DJ |
863 | bytes but we only want four. Use regs_base to access any |
864 | 64-bit fields. */ | |
4c6b5505 | 865 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
37c4d197 DJ |
866 | regs_base = sigcontext_base + 4; |
867 | else | |
868 | regs_base = sigcontext_base; | |
5792a79b | 869 | |
822b6570 DJ |
870 | if (mips_linux_restart_reg_p (current_gdbarch)) |
871 | trad_frame_set_reg_addr (this_cache, | |
872 | (MIPS_RESTART_REGNUM | |
873 | + gdbarch_num_regs (current_gdbarch)), | |
874 | regs_base + SIGCONTEXT_REGS); | |
5792a79b DJ |
875 | |
876 | for (ireg = 1; ireg < 32; ireg++) | |
295093a4 | 877 | trad_frame_set_reg_addr (this_cache, |
f57d151a UW |
878 | ireg + MIPS_ZERO_REGNUM |
879 | + gdbarch_num_regs (current_gdbarch), | |
37c4d197 | 880 | regs_base + SIGCONTEXT_REGS |
5792a79b DJ |
881 | + ireg * SIGCONTEXT_REG_SIZE); |
882 | ||
37c4d197 DJ |
883 | /* The way that floating point registers are saved, unfortunately, |
884 | depends on the architecture the kernel is built for. For the r3000 and | |
885 | tx39, four bytes of each register are at the beginning of each of the | |
886 | 32 eight byte slots. For everything else, the registers are saved | |
887 | using double precision; only the even-numbered slots are initialized, | |
888 | and the high bits are the odd-numbered register. Assume the latter | |
889 | layout, since we can't tell, and it's much more common. Which bits are | |
890 | the "high" bits depends on endianness. */ | |
5792a79b | 891 | for (ireg = 0; ireg < 32; ireg++) |
4c6b5505 | 892 | if ((gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) != (ireg & 1)) |
f57d151a UW |
893 | trad_frame_set_reg_addr (this_cache, |
894 | ireg + regs->fp0 + | |
895 | gdbarch_num_regs (current_gdbarch), | |
37c4d197 DJ |
896 | sigcontext_base + SIGCONTEXT_FPREGS + 4 |
897 | + (ireg & ~1) * SIGCONTEXT_REG_SIZE); | |
898 | else | |
f57d151a UW |
899 | trad_frame_set_reg_addr (this_cache, |
900 | ireg + regs->fp0 | |
901 | + gdbarch_num_regs (current_gdbarch), | |
37c4d197 DJ |
902 | sigcontext_base + SIGCONTEXT_FPREGS |
903 | + (ireg & ~1) * SIGCONTEXT_REG_SIZE); | |
5792a79b | 904 | |
f57d151a UW |
905 | trad_frame_set_reg_addr (this_cache, |
906 | regs->pc + gdbarch_num_regs (current_gdbarch), | |
37c4d197 | 907 | regs_base + SIGCONTEXT_PC); |
5792a79b | 908 | |
295093a4 | 909 | trad_frame_set_reg_addr (this_cache, |
f57d151a UW |
910 | regs->fp_control_status |
911 | + gdbarch_num_regs (current_gdbarch), | |
5792a79b | 912 | sigcontext_base + SIGCONTEXT_FPCSR); |
f57d151a UW |
913 | trad_frame_set_reg_addr (this_cache, |
914 | regs->hi + gdbarch_num_regs (current_gdbarch), | |
37c4d197 | 915 | regs_base + SIGCONTEXT_HI); |
f57d151a UW |
916 | trad_frame_set_reg_addr (this_cache, |
917 | regs->lo + gdbarch_num_regs (current_gdbarch), | |
37c4d197 | 918 | regs_base + SIGCONTEXT_LO); |
f57d151a UW |
919 | trad_frame_set_reg_addr (this_cache, |
920 | regs->cause + gdbarch_num_regs (current_gdbarch), | |
5792a79b | 921 | sigcontext_base + SIGCONTEXT_CAUSE); |
f57d151a UW |
922 | trad_frame_set_reg_addr (this_cache, |
923 | regs->badvaddr + gdbarch_num_regs (current_gdbarch), | |
5792a79b DJ |
924 | sigcontext_base + SIGCONTEXT_BADVADDR); |
925 | ||
926 | /* Choice of the bottom of the sigframe is somewhat arbitrary. */ | |
927 | trad_frame_set_id (this_cache, | |
295093a4 MS |
928 | frame_id_build (func - SIGFRAME_CODE_OFFSET, |
929 | func)); | |
5792a79b DJ |
930 | } |
931 | ||
932 | /* *INDENT-OFF* */ | |
933 | /* For N32/N64 things look different. There is no non-rt signal frame. | |
934 | ||
935 | struct rt_sigframe_n32 { | |
936 | u32 rs_ass[4]; [ argument save space for o32 ] | |
937 | u32 rs_code[2]; [ signal trampoline ] | |
938 | struct siginfo rs_info; | |
939 | struct ucontextn32 rs_uc; | |
940 | }; | |
941 | ||
942 | struct ucontextn32 { | |
943 | u32 uc_flags; | |
944 | s32 uc_link; | |
945 | stack32_t uc_stack; | |
946 | struct sigcontext uc_mcontext; | |
947 | sigset_t uc_sigmask; [ mask last for extensibility ] | |
948 | }; | |
295093a4 | 949 | |
5792a79b DJ |
950 | struct rt_sigframe_n32 { |
951 | u32 rs_ass[4]; [ argument save space for o32 ] | |
952 | u32 rs_code[2]; [ signal trampoline ] | |
953 | struct siginfo rs_info; | |
954 | struct ucontext rs_uc; | |
955 | }; | |
956 | ||
957 | struct ucontext { | |
958 | unsigned long uc_flags; | |
959 | struct ucontext *uc_link; | |
960 | stack_t uc_stack; | |
961 | struct sigcontext uc_mcontext; | |
962 | sigset_t uc_sigmask; [ mask last for extensibility ] | |
963 | }; | |
964 | ||
965 | And the sigcontext is different (this is for both n32 and n64): | |
966 | ||
967 | struct sigcontext { | |
968 | unsigned long long sc_regs[32]; | |
969 | unsigned long long sc_fpregs[32]; | |
970 | unsigned long long sc_mdhi; | |
971 | unsigned long long sc_mdlo; | |
972 | unsigned long long sc_pc; | |
973 | unsigned int sc_status; | |
974 | unsigned int sc_fpc_csr; | |
975 | unsigned int sc_fpc_eir; | |
976 | unsigned int sc_used_math; | |
977 | unsigned int sc_cause; | |
978 | unsigned int sc_badvaddr; | |
979 | }; */ | |
980 | /* *INDENT-ON* */ | |
981 | ||
982 | #define N32_STACK_T_SIZE STACK_T_SIZE | |
983 | #define N64_STACK_T_SIZE (2 * 8 + 4) | |
984 | #define N32_UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + N32_STACK_T_SIZE + 4) | |
985 | #define N64_UCONTEXT_SIGCONTEXT_OFFSET (2 * 8 + N64_STACK_T_SIZE + 4) | |
986 | #define N32_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ | |
987 | + RTSIGFRAME_SIGINFO_SIZE \ | |
988 | + N32_UCONTEXT_SIGCONTEXT_OFFSET) | |
989 | #define N64_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ | |
990 | + RTSIGFRAME_SIGINFO_SIZE \ | |
991 | + N64_UCONTEXT_SIGCONTEXT_OFFSET) | |
992 | ||
993 | #define N64_SIGCONTEXT_REGS (0 * 8) | |
994 | #define N64_SIGCONTEXT_FPREGS (32 * 8) | |
995 | #define N64_SIGCONTEXT_HI (64 * 8) | |
996 | #define N64_SIGCONTEXT_LO (65 * 8) | |
997 | #define N64_SIGCONTEXT_PC (66 * 8) | |
998 | #define N64_SIGCONTEXT_FPCSR (67 * 8 + 1 * 4) | |
999 | #define N64_SIGCONTEXT_FIR (67 * 8 + 2 * 4) | |
1000 | #define N64_SIGCONTEXT_CAUSE (67 * 8 + 4 * 4) | |
1001 | #define N64_SIGCONTEXT_BADVADDR (67 * 8 + 5 * 4) | |
1002 | ||
1003 | #define N64_SIGCONTEXT_REG_SIZE 8 | |
295093a4 | 1004 | |
5792a79b DJ |
1005 | static void |
1006 | mips_linux_n32n64_sigframe_init (const struct tramp_frame *self, | |
1007 | struct frame_info *next_frame, | |
1008 | struct trad_frame_cache *this_cache, | |
1009 | CORE_ADDR func) | |
1010 | { | |
1011 | int ireg, reg_position; | |
1012 | CORE_ADDR sigcontext_base = func - SIGFRAME_CODE_OFFSET; | |
1013 | const struct mips_regnum *regs = mips_regnum (current_gdbarch); | |
1014 | ||
1015 | if (self == &mips_linux_n32_rt_sigframe) | |
1016 | sigcontext_base += N32_SIGFRAME_SIGCONTEXT_OFFSET; | |
1017 | else | |
1018 | sigcontext_base += N64_SIGFRAME_SIGCONTEXT_OFFSET; | |
295093a4 | 1019 | |
822b6570 DJ |
1020 | if (mips_linux_restart_reg_p (current_gdbarch)) |
1021 | trad_frame_set_reg_addr (this_cache, | |
1022 | (MIPS_RESTART_REGNUM | |
1023 | + gdbarch_num_regs (current_gdbarch)), | |
1024 | sigcontext_base + N64_SIGCONTEXT_REGS); | |
5792a79b DJ |
1025 | |
1026 | for (ireg = 1; ireg < 32; ireg++) | |
295093a4 | 1027 | trad_frame_set_reg_addr (this_cache, |
f57d151a UW |
1028 | ireg + MIPS_ZERO_REGNUM |
1029 | + gdbarch_num_regs (current_gdbarch), | |
5792a79b DJ |
1030 | sigcontext_base + N64_SIGCONTEXT_REGS |
1031 | + ireg * N64_SIGCONTEXT_REG_SIZE); | |
1032 | ||
1033 | for (ireg = 0; ireg < 32; ireg++) | |
f57d151a UW |
1034 | trad_frame_set_reg_addr (this_cache, |
1035 | ireg + regs->fp0 | |
1036 | + gdbarch_num_regs (current_gdbarch), | |
5792a79b DJ |
1037 | sigcontext_base + N64_SIGCONTEXT_FPREGS |
1038 | + ireg * N64_SIGCONTEXT_REG_SIZE); | |
1039 | ||
f57d151a UW |
1040 | trad_frame_set_reg_addr (this_cache, |
1041 | regs->pc + gdbarch_num_regs (current_gdbarch), | |
5792a79b DJ |
1042 | sigcontext_base + N64_SIGCONTEXT_PC); |
1043 | ||
295093a4 | 1044 | trad_frame_set_reg_addr (this_cache, |
f57d151a UW |
1045 | regs->fp_control_status |
1046 | + gdbarch_num_regs (current_gdbarch), | |
5792a79b | 1047 | sigcontext_base + N64_SIGCONTEXT_FPCSR); |
f57d151a UW |
1048 | trad_frame_set_reg_addr (this_cache, |
1049 | regs->hi + gdbarch_num_regs (current_gdbarch), | |
5792a79b | 1050 | sigcontext_base + N64_SIGCONTEXT_HI); |
f57d151a UW |
1051 | trad_frame_set_reg_addr (this_cache, |
1052 | regs->lo + gdbarch_num_regs (current_gdbarch), | |
5792a79b | 1053 | sigcontext_base + N64_SIGCONTEXT_LO); |
f57d151a UW |
1054 | trad_frame_set_reg_addr (this_cache, |
1055 | regs->cause + gdbarch_num_regs (current_gdbarch), | |
5792a79b | 1056 | sigcontext_base + N64_SIGCONTEXT_CAUSE); |
f57d151a UW |
1057 | trad_frame_set_reg_addr (this_cache, |
1058 | regs->badvaddr + gdbarch_num_regs (current_gdbarch), | |
5792a79b DJ |
1059 | sigcontext_base + N64_SIGCONTEXT_BADVADDR); |
1060 | ||
1061 | /* Choice of the bottom of the sigframe is somewhat arbitrary. */ | |
1062 | trad_frame_set_id (this_cache, | |
295093a4 MS |
1063 | frame_id_build (func - SIGFRAME_CODE_OFFSET, |
1064 | func)); | |
5792a79b DJ |
1065 | } |
1066 | ||
822b6570 | 1067 | static void |
61a1198a | 1068 | mips_linux_write_pc (struct regcache *regcache, CORE_ADDR pc) |
822b6570 | 1069 | { |
3e8c568d UW |
1070 | regcache_cooked_write_unsigned (regcache, |
1071 | gdbarch_pc_regnum (current_gdbarch), pc); | |
822b6570 DJ |
1072 | |
1073 | /* Clear the syscall restart flag. */ | |
1074 | if (mips_linux_restart_reg_p (current_gdbarch)) | |
61a1198a | 1075 | regcache_cooked_write_unsigned (regcache, MIPS_RESTART_REGNUM, 0); |
822b6570 DJ |
1076 | } |
1077 | ||
1078 | /* Return 1 if MIPS_RESTART_REGNUM is usable. */ | |
1079 | ||
1080 | int | |
1081 | mips_linux_restart_reg_p (struct gdbarch *gdbarch) | |
1082 | { | |
1083 | /* If we do not have a target description with registers, then | |
1084 | MIPS_RESTART_REGNUM will not be included in the register set. */ | |
1085 | if (!tdesc_has_registers (gdbarch_target_desc (gdbarch))) | |
1086 | return 0; | |
1087 | ||
1088 | /* If we do, then MIPS_RESTART_REGNUM is safe to check; it will | |
1089 | either be GPR-sized or missing. */ | |
1090 | return register_size (gdbarch, MIPS_RESTART_REGNUM) > 0; | |
1091 | } | |
9f62d0e2 | 1092 | |
5792a79b DJ |
1093 | /* Initialize one of the GNU/Linux OS ABIs. */ |
1094 | ||
19ed69dd | 1095 | static void |
295093a4 MS |
1096 | mips_linux_init_abi (struct gdbarch_info info, |
1097 | struct gdbarch *gdbarch) | |
19ed69dd | 1098 | { |
96f026fc KB |
1099 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1100 | enum mips_abi abi = mips_abi (gdbarch); | |
822b6570 | 1101 | struct tdesc_arch_data *tdesc_data = (void *) info.tdep_info; |
96f026fc KB |
1102 | |
1103 | switch (abi) | |
1104 | { | |
1105 | case MIPS_ABI_O32: | |
1106 | set_gdbarch_get_longjmp_target (gdbarch, | |
1107 | mips_linux_get_longjmp_target); | |
1108 | set_solib_svr4_fetch_link_map_offsets | |
76a9d10f | 1109 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); |
fb2be677 AC |
1110 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_sigframe); |
1111 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_rt_sigframe); | |
96f026fc KB |
1112 | break; |
1113 | case MIPS_ABI_N32: | |
1114 | set_gdbarch_get_longjmp_target (gdbarch, | |
1115 | mips_linux_get_longjmp_target); | |
1116 | set_solib_svr4_fetch_link_map_offsets | |
76a9d10f | 1117 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); |
d05f6826 DJ |
1118 | set_gdbarch_long_double_bit (gdbarch, 128); |
1119 | /* These floatformats should probably be renamed. MIPS uses | |
1120 | the same 128-bit IEEE floating point format that IA-64 uses, | |
1121 | except that the quiet/signalling NaN bit is reversed (GDB | |
1122 | does not distinguish between quiet and signalling NaNs). */ | |
8da61cc4 | 1123 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); |
fb2be677 | 1124 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n32_rt_sigframe); |
96f026fc KB |
1125 | break; |
1126 | case MIPS_ABI_N64: | |
1127 | set_gdbarch_get_longjmp_target (gdbarch, | |
1128 | mips64_linux_get_longjmp_target); | |
1129 | set_solib_svr4_fetch_link_map_offsets | |
76a9d10f | 1130 | (gdbarch, svr4_lp64_fetch_link_map_offsets); |
d05f6826 DJ |
1131 | set_gdbarch_long_double_bit (gdbarch, 128); |
1132 | /* These floatformats should probably be renamed. MIPS uses | |
1133 | the same 128-bit IEEE floating point format that IA-64 uses, | |
1134 | except that the quiet/signalling NaN bit is reversed (GDB | |
1135 | does not distinguish between quiet and signalling NaNs). */ | |
8da61cc4 | 1136 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); |
fb2be677 | 1137 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n64_rt_sigframe); |
96f026fc KB |
1138 | break; |
1139 | default: | |
e2e0b3e5 | 1140 | internal_error (__FILE__, __LINE__, _("can't handle ABI")); |
96f026fc KB |
1141 | break; |
1142 | } | |
6de918a6 | 1143 | |
982e9687 | 1144 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
6de918a6 DJ |
1145 | set_gdbarch_skip_solib_resolver (gdbarch, mips_linux_skip_resolver); |
1146 | ||
0d0266c6 | 1147 | set_gdbarch_software_single_step (gdbarch, mips_software_single_step); |
b2756930 KB |
1148 | |
1149 | /* Enable TLS support. */ | |
1150 | set_gdbarch_fetch_tls_load_module_address (gdbarch, | |
1151 | svr4_fetch_objfile_link_map); | |
7d522c90 DJ |
1152 | |
1153 | /* Initialize this lazily, to avoid an initialization order | |
1154 | dependency on solib-svr4.c's _initialize routine. */ | |
1155 | if (mips_svr4_so_ops.in_dynsym_resolve_code == NULL) | |
1156 | { | |
1157 | mips_svr4_so_ops = svr4_so_ops; | |
1158 | mips_svr4_so_ops.in_dynsym_resolve_code | |
1159 | = mips_linux_in_dynsym_resolve_code; | |
1160 | } | |
1161 | set_solib_ops (gdbarch, &mips_svr4_so_ops); | |
822b6570 DJ |
1162 | |
1163 | set_gdbarch_write_pc (gdbarch, mips_linux_write_pc); | |
1164 | ||
1165 | if (tdesc_data) | |
1166 | { | |
1167 | const struct tdesc_feature *feature; | |
1168 | ||
1169 | /* If we have target-described registers, then we can safely | |
1170 | reserve a number for MIPS_RESTART_REGNUM (whether it is | |
1171 | described or not). */ | |
1172 | gdb_assert (gdbarch_num_regs (gdbarch) <= MIPS_RESTART_REGNUM); | |
1173 | set_gdbarch_num_regs (gdbarch, MIPS_RESTART_REGNUM + 1); | |
1174 | ||
1175 | /* If it's present, then assign it to the reserved number. */ | |
1176 | feature = tdesc_find_feature (info.target_desc, | |
1177 | "org.gnu.gdb.mips.linux"); | |
1178 | if (feature != NULL) | |
1179 | tdesc_numbered_register (feature, tdesc_data, MIPS_RESTART_REGNUM, | |
1180 | "restart"); | |
1181 | } | |
19ed69dd KB |
1182 | } |
1183 | ||
2aa830e4 | 1184 | void |
d1bacddc | 1185 | _initialize_mips_linux_tdep (void) |
2aa830e4 | 1186 | { |
96f026fc KB |
1187 | const struct bfd_arch_info *arch_info; |
1188 | ||
96f026fc KB |
1189 | for (arch_info = bfd_lookup_arch (bfd_arch_mips, 0); |
1190 | arch_info != NULL; | |
1191 | arch_info = arch_info->next) | |
1192 | { | |
295093a4 MS |
1193 | gdbarch_register_osabi (bfd_arch_mips, arch_info->mach, |
1194 | GDB_OSABI_LINUX, | |
96f026fc KB |
1195 | mips_linux_init_abi); |
1196 | } | |
1197 | ||
00e32a35 | 1198 | deprecated_add_core_fns (®set_core_fns); |
2aa830e4 | 1199 | } |