Commit | Line | Data |
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75c9abc6 | 1 | /* Target-dependent code for GNU/Linux on MIPS processors. |
a094c6fb | 2 | |
b811d2c2 | 3 | Copyright (C) 2001-2020 Free Software Foundation, Inc. |
2aa830e4 DJ |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
2aa830e4 DJ |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
2aa830e4 DJ |
19 | |
20 | #include "defs.h" | |
21 | #include "gdbcore.h" | |
22 | #include "target.h" | |
23 | #include "solib-svr4.h" | |
19ed69dd | 24 | #include "osabi.h" |
96f026fc | 25 | #include "mips-tdep.h" |
6de918a6 | 26 | #include "frame.h" |
2fdf551c | 27 | #include "regcache.h" |
5792a79b DJ |
28 | #include "trad-frame.h" |
29 | #include "tramp-frame.h" | |
e6bb342a | 30 | #include "gdbtypes.h" |
3e5d3a5a | 31 | #include "objfiles.h" |
5ea03926 | 32 | #include "solib.h" |
7d522c90 | 33 | #include "solist.h" |
982e9687 | 34 | #include "symtab.h" |
822b6570 | 35 | #include "target-descriptions.h" |
50e8a0d5 | 36 | #include "regset.h" |
d37eb719 | 37 | #include "mips-linux-tdep.h" |
db5f024e | 38 | #include "glibc-tdep.h" |
a5ee0f0c | 39 | #include "linux-tdep.h" |
385203ed | 40 | #include "xml-syscall.h" |
268a13a5 | 41 | #include "gdbsupport/gdb_signals.h" |
2aa830e4 | 42 | |
032bb6ea YQ |
43 | #include "features/mips-linux.c" |
44 | #include "features/mips-dsp-linux.c" | |
45 | #include "features/mips64-linux.c" | |
46 | #include "features/mips64-dsp-linux.c" | |
47 | ||
7d522c90 DJ |
48 | static struct target_so_ops mips_svr4_so_ops; |
49 | ||
eb14d406 SDJ |
50 | /* This enum represents the signals' numbers on the MIPS |
51 | architecture. It just contains the signal definitions which are | |
52 | different from the generic implementation. | |
53 | ||
54 | It is derived from the file <arch/mips/include/uapi/asm/signal.h>, | |
55 | from the Linux kernel tree. */ | |
56 | ||
57 | enum | |
58 | { | |
59 | MIPS_LINUX_SIGEMT = 7, | |
60 | MIPS_LINUX_SIGBUS = 10, | |
61 | MIPS_LINUX_SIGSYS = 12, | |
62 | MIPS_LINUX_SIGUSR1 = 16, | |
63 | MIPS_LINUX_SIGUSR2 = 17, | |
64 | MIPS_LINUX_SIGCHLD = 18, | |
65 | MIPS_LINUX_SIGCLD = MIPS_LINUX_SIGCHLD, | |
66 | MIPS_LINUX_SIGPWR = 19, | |
67 | MIPS_LINUX_SIGWINCH = 20, | |
68 | MIPS_LINUX_SIGURG = 21, | |
69 | MIPS_LINUX_SIGIO = 22, | |
70 | MIPS_LINUX_SIGPOLL = MIPS_LINUX_SIGIO, | |
71 | MIPS_LINUX_SIGSTOP = 23, | |
72 | MIPS_LINUX_SIGTSTP = 24, | |
73 | MIPS_LINUX_SIGCONT = 25, | |
74 | MIPS_LINUX_SIGTTIN = 26, | |
75 | MIPS_LINUX_SIGTTOU = 27, | |
76 | MIPS_LINUX_SIGVTALRM = 28, | |
77 | MIPS_LINUX_SIGPROF = 29, | |
78 | MIPS_LINUX_SIGXCPU = 30, | |
79 | MIPS_LINUX_SIGXFSZ = 31, | |
80 | ||
81 | MIPS_LINUX_SIGRTMIN = 32, | |
82 | MIPS_LINUX_SIGRT64 = 64, | |
83 | MIPS_LINUX_SIGRTMAX = 127, | |
84 | }; | |
85 | ||
2aa830e4 | 86 | /* Figure out where the longjmp will land. |
295093a4 MS |
87 | We expect the first arg to be a pointer to the jmp_buf structure |
88 | from which we extract the pc (MIPS_LINUX_JB_PC) that we will land | |
89 | at. The pc is copied into PC. This routine returns 1 on | |
90 | success. */ | |
2aa830e4 | 91 | |
19ed69dd KB |
92 | #define MIPS_LINUX_JB_ELEMENT_SIZE 4 |
93 | #define MIPS_LINUX_JB_PC 0 | |
94 | ||
95 | static int | |
60ade65d | 96 | mips_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
2aa830e4 DJ |
97 | { |
98 | CORE_ADDR jb_addr; | |
2eb4d78b | 99 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 100 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
e362b510 | 101 | gdb_byte buf[gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT]; |
2aa830e4 | 102 | |
60ade65d | 103 | jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM); |
2aa830e4 | 104 | |
7d266584 MR |
105 | if (target_read_memory ((jb_addr |
106 | + MIPS_LINUX_JB_PC * MIPS_LINUX_JB_ELEMENT_SIZE), | |
2eb4d78b | 107 | buf, gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT)) |
2aa830e4 DJ |
108 | return 0; |
109 | ||
819844ad | 110 | *pc = extract_unsigned_integer (buf, |
e17a4113 UW |
111 | gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT, |
112 | byte_order); | |
2aa830e4 DJ |
113 | |
114 | return 1; | |
115 | } | |
116 | ||
4246e332 | 117 | /* Transform the bits comprising a 32-bit register to the right size |
23a6d369 AC |
118 | for regcache_raw_supply(). This is needed when mips_isa_regsize() |
119 | is 8. */ | |
96f026fc KB |
120 | |
121 | static void | |
28f5035f | 122 | supply_32bit_reg (struct regcache *regcache, int regnum, const void *addr) |
96f026fc | 123 | { |
b057297a | 124 | regcache->raw_supply_integer (regnum, (const gdb_byte *) addr, 4, true); |
96f026fc KB |
125 | } |
126 | ||
2aa830e4 DJ |
127 | /* Unpack an elf_gregset_t into GDB's register cache. */ |
128 | ||
d37eb719 | 129 | void |
28f5035f UW |
130 | mips_supply_gregset (struct regcache *regcache, |
131 | const mips_elf_gregset_t *gregsetp) | |
2aa830e4 DJ |
132 | { |
133 | int regi; | |
28f5035f | 134 | const mips_elf_greg_t *regp = *gregsetp; |
ac7936df | 135 | struct gdbarch *gdbarch = regcache->arch (); |
bf072999 | 136 | |
822b6570 | 137 | for (regi = EF_REG0 + 1; regi <= EF_REG31; regi++) |
28f5035f | 138 | supply_32bit_reg (regcache, regi - EF_REG0, regp + regi); |
2aa830e4 | 139 | |
2eb4d78b | 140 | if (mips_linux_restart_reg_p (gdbarch)) |
822b6570 DJ |
141 | supply_32bit_reg (regcache, MIPS_RESTART_REGNUM, regp + EF_REG0); |
142 | ||
2eb4d78b UW |
143 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->lo, regp + EF_LO); |
144 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->hi, regp + EF_HI); | |
56cea623 | 145 | |
2eb4d78b | 146 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->pc, |
28f5035f | 147 | regp + EF_CP0_EPC); |
2eb4d78b | 148 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->badvaddr, |
28f5035f UW |
149 | regp + EF_CP0_BADVADDR); |
150 | supply_32bit_reg (regcache, MIPS_PS_REGNUM, regp + EF_CP0_STATUS); | |
2eb4d78b | 151 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->cause, |
28f5035f | 152 | regp + EF_CP0_CAUSE); |
2aa830e4 | 153 | |
1faeff08 | 154 | /* Fill the inaccessible zero register with zero. */ |
27bfc1d1 | 155 | regcache->raw_supply_zeroed (MIPS_ZERO_REGNUM); |
2aa830e4 DJ |
156 | } |
157 | ||
50e8a0d5 HZ |
158 | static void |
159 | mips_supply_gregset_wrapper (const struct regset *regset, | |
7d266584 MR |
160 | struct regcache *regcache, |
161 | int regnum, const void *gregs, size_t len) | |
50e8a0d5 | 162 | { |
1528345d | 163 | gdb_assert (len >= sizeof (mips_elf_gregset_t)); |
50e8a0d5 HZ |
164 | |
165 | mips_supply_gregset (regcache, (const mips_elf_gregset_t *)gregs); | |
166 | } | |
167 | ||
2aa830e4 DJ |
168 | /* Pack our registers (or one register) into an elf_gregset_t. */ |
169 | ||
d37eb719 | 170 | void |
28f5035f UW |
171 | mips_fill_gregset (const struct regcache *regcache, |
172 | mips_elf_gregset_t *gregsetp, int regno) | |
2aa830e4 | 173 | { |
ac7936df | 174 | struct gdbarch *gdbarch = regcache->arch (); |
2aa830e4 | 175 | int regaddr, regi; |
d37eb719 | 176 | mips_elf_greg_t *regp = *gregsetp; |
96f026fc | 177 | void *dst; |
2aa830e4 DJ |
178 | |
179 | if (regno == -1) | |
180 | { | |
d37eb719 | 181 | memset (regp, 0, sizeof (mips_elf_gregset_t)); |
822b6570 | 182 | for (regi = 1; regi < 32; regi++) |
28f5035f | 183 | mips_fill_gregset (regcache, gregsetp, regi); |
2eb4d78b UW |
184 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->lo); |
185 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->hi); | |
186 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->pc); | |
187 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->badvaddr); | |
28f5035f | 188 | mips_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM); |
2eb4d78b | 189 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->cause); |
822b6570 | 190 | mips_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM); |
2aa830e4 DJ |
191 | return; |
192 | } | |
193 | ||
822b6570 | 194 | if (regno > 0 && regno < 32) |
2aa830e4 | 195 | { |
2aa830e4 | 196 | dst = regp + regno + EF_REG0; |
34a79281 | 197 | regcache->raw_collect (regno, dst); |
2aa830e4 DJ |
198 | return; |
199 | } | |
200 | ||
2eb4d78b UW |
201 | if (regno == mips_regnum (gdbarch)->lo) |
202 | regaddr = EF_LO; | |
203 | else if (regno == mips_regnum (gdbarch)->hi) | |
56cea623 | 204 | regaddr = EF_HI; |
2eb4d78b | 205 | else if (regno == mips_regnum (gdbarch)->pc) |
56cea623 | 206 | regaddr = EF_CP0_EPC; |
2eb4d78b | 207 | else if (regno == mips_regnum (gdbarch)->badvaddr) |
56cea623 | 208 | regaddr = EF_CP0_BADVADDR; |
24e05951 | 209 | else if (regno == MIPS_PS_REGNUM) |
56cea623 | 210 | regaddr = EF_CP0_STATUS; |
2eb4d78b | 211 | else if (regno == mips_regnum (gdbarch)->cause) |
56cea623 | 212 | regaddr = EF_CP0_CAUSE; |
2eb4d78b | 213 | else if (mips_linux_restart_reg_p (gdbarch) |
822b6570 DJ |
214 | && regno == MIPS_RESTART_REGNUM) |
215 | regaddr = EF_REG0; | |
56cea623 AC |
216 | else |
217 | regaddr = -1; | |
2aa830e4 DJ |
218 | |
219 | if (regaddr != -1) | |
220 | { | |
2aa830e4 | 221 | dst = regp + regaddr; |
34a79281 | 222 | regcache->raw_collect (regno, dst); |
2aa830e4 DJ |
223 | } |
224 | } | |
225 | ||
50e8a0d5 HZ |
226 | static void |
227 | mips_fill_gregset_wrapper (const struct regset *regset, | |
228 | const struct regcache *regcache, | |
229 | int regnum, void *gregs, size_t len) | |
230 | { | |
1528345d | 231 | gdb_assert (len >= sizeof (mips_elf_gregset_t)); |
50e8a0d5 HZ |
232 | |
233 | mips_fill_gregset (regcache, (mips_elf_gregset_t *)gregs, regnum); | |
234 | } | |
235 | ||
96f026fc KB |
236 | /* Support for 64-bit ABIs. */ |
237 | ||
96f026fc | 238 | /* Figure out where the longjmp will land. |
295093a4 MS |
239 | We expect the first arg to be a pointer to the jmp_buf structure |
240 | from which we extract the pc (MIPS_LINUX_JB_PC) that we will land | |
241 | at. The pc is copied into PC. This routine returns 1 on | |
242 | success. */ | |
96f026fc KB |
243 | |
244 | /* Details about jmp_buf. */ | |
245 | ||
246 | #define MIPS64_LINUX_JB_PC 0 | |
247 | ||
248 | static int | |
60ade65d | 249 | mips64_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
96f026fc KB |
250 | { |
251 | CORE_ADDR jb_addr; | |
2eb4d78b | 252 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 253 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
709476c3 SM |
254 | gdb_byte *buf |
255 | = (gdb_byte *) alloca (gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT); | |
2eb4d78b | 256 | int element_size = gdbarch_ptr_bit (gdbarch) == 32 ? 4 : 8; |
96f026fc | 257 | |
60ade65d | 258 | jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM); |
96f026fc KB |
259 | |
260 | if (target_read_memory (jb_addr + MIPS64_LINUX_JB_PC * element_size, | |
819844ad | 261 | buf, |
2eb4d78b | 262 | gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT)) |
96f026fc KB |
263 | return 0; |
264 | ||
819844ad | 265 | *pc = extract_unsigned_integer (buf, |
e17a4113 UW |
266 | gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT, |
267 | byte_order); | |
96f026fc KB |
268 | |
269 | return 1; | |
270 | } | |
271 | ||
d37eb719 DJ |
272 | /* Register set support functions. These operate on standard 64-bit |
273 | regsets, but work whether the target is 32-bit or 64-bit. A 32-bit | |
274 | target will still use the 64-bit format for PTRACE_GETREGS. */ | |
275 | ||
276 | /* Supply a 64-bit register. */ | |
96f026fc | 277 | |
63807e1d | 278 | static void |
28f5035f UW |
279 | supply_64bit_reg (struct regcache *regcache, int regnum, |
280 | const gdb_byte *buf) | |
d37eb719 | 281 | { |
ac7936df | 282 | struct gdbarch *gdbarch = regcache->arch (); |
2eb4d78b UW |
283 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
284 | && register_size (gdbarch, regnum) == 4) | |
73e1c03f | 285 | regcache->raw_supply (regnum, buf + 4); |
d37eb719 | 286 | else |
73e1c03f | 287 | regcache->raw_supply (regnum, buf); |
d37eb719 DJ |
288 | } |
289 | ||
290 | /* Unpack a 64-bit elf_gregset_t into GDB's register cache. */ | |
291 | ||
292 | void | |
28f5035f UW |
293 | mips64_supply_gregset (struct regcache *regcache, |
294 | const mips64_elf_gregset_t *gregsetp) | |
96f026fc KB |
295 | { |
296 | int regi; | |
28f5035f | 297 | const mips64_elf_greg_t *regp = *gregsetp; |
ac7936df | 298 | struct gdbarch *gdbarch = regcache->arch (); |
96f026fc | 299 | |
822b6570 | 300 | for (regi = MIPS64_EF_REG0 + 1; regi <= MIPS64_EF_REG31; regi++) |
28f5035f | 301 | supply_64bit_reg (regcache, regi - MIPS64_EF_REG0, |
7d266584 | 302 | (const gdb_byte *) (regp + regi)); |
28f5035f | 303 | |
2eb4d78b | 304 | if (mips_linux_restart_reg_p (gdbarch)) |
822b6570 | 305 | supply_64bit_reg (regcache, MIPS_RESTART_REGNUM, |
7d266584 | 306 | (const gdb_byte *) (regp + MIPS64_EF_REG0)); |
822b6570 | 307 | |
2eb4d78b | 308 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->lo, |
28f5035f | 309 | (const gdb_byte *) (regp + MIPS64_EF_LO)); |
2eb4d78b | 310 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->hi, |
28f5035f UW |
311 | (const gdb_byte *) (regp + MIPS64_EF_HI)); |
312 | ||
2eb4d78b | 313 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->pc, |
28f5035f | 314 | (const gdb_byte *) (regp + MIPS64_EF_CP0_EPC)); |
2eb4d78b | 315 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->badvaddr, |
28f5035f UW |
316 | (const gdb_byte *) (regp + MIPS64_EF_CP0_BADVADDR)); |
317 | supply_64bit_reg (regcache, MIPS_PS_REGNUM, | |
318 | (const gdb_byte *) (regp + MIPS64_EF_CP0_STATUS)); | |
2eb4d78b | 319 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->cause, |
28f5035f | 320 | (const gdb_byte *) (regp + MIPS64_EF_CP0_CAUSE)); |
96f026fc | 321 | |
1faeff08 | 322 | /* Fill the inaccessible zero register with zero. */ |
27bfc1d1 | 323 | regcache->raw_supply_zeroed (MIPS_ZERO_REGNUM); |
96f026fc KB |
324 | } |
325 | ||
50e8a0d5 HZ |
326 | static void |
327 | mips64_supply_gregset_wrapper (const struct regset *regset, | |
7d266584 MR |
328 | struct regcache *regcache, |
329 | int regnum, const void *gregs, size_t len) | |
50e8a0d5 | 330 | { |
1528345d | 331 | gdb_assert (len >= sizeof (mips64_elf_gregset_t)); |
50e8a0d5 HZ |
332 | |
333 | mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *)gregs); | |
334 | } | |
335 | ||
d37eb719 | 336 | /* Pack our registers (or one register) into a 64-bit elf_gregset_t. */ |
96f026fc | 337 | |
d37eb719 | 338 | void |
28f5035f UW |
339 | mips64_fill_gregset (const struct regcache *regcache, |
340 | mips64_elf_gregset_t *gregsetp, int regno) | |
96f026fc | 341 | { |
ac7936df | 342 | struct gdbarch *gdbarch = regcache->arch (); |
96f026fc KB |
343 | int regaddr, regi; |
344 | mips64_elf_greg_t *regp = *gregsetp; | |
2ba93934 | 345 | void *dst; |
96f026fc KB |
346 | |
347 | if (regno == -1) | |
348 | { | |
349 | memset (regp, 0, sizeof (mips64_elf_gregset_t)); | |
822b6570 | 350 | for (regi = 1; regi < 32; regi++) |
7d266584 | 351 | mips64_fill_gregset (regcache, gregsetp, regi); |
2eb4d78b UW |
352 | mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->lo); |
353 | mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->hi); | |
354 | mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->pc); | |
025bb325 MS |
355 | mips64_fill_gregset (regcache, gregsetp, |
356 | mips_regnum (gdbarch)->badvaddr); | |
28f5035f | 357 | mips64_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM); |
2eb4d78b | 358 | mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->cause); |
822b6570 | 359 | mips64_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM); |
96f026fc KB |
360 | return; |
361 | } | |
362 | ||
822b6570 | 363 | if (regno > 0 && regno < 32) |
d37eb719 | 364 | regaddr = regno + MIPS64_EF_REG0; |
2eb4d78b | 365 | else if (regno == mips_regnum (gdbarch)->lo) |
56cea623 | 366 | regaddr = MIPS64_EF_LO; |
2eb4d78b | 367 | else if (regno == mips_regnum (gdbarch)->hi) |
56cea623 | 368 | regaddr = MIPS64_EF_HI; |
2eb4d78b | 369 | else if (regno == mips_regnum (gdbarch)->pc) |
56cea623 | 370 | regaddr = MIPS64_EF_CP0_EPC; |
2eb4d78b | 371 | else if (regno == mips_regnum (gdbarch)->badvaddr) |
56cea623 | 372 | regaddr = MIPS64_EF_CP0_BADVADDR; |
24e05951 | 373 | else if (regno == MIPS_PS_REGNUM) |
56cea623 | 374 | regaddr = MIPS64_EF_CP0_STATUS; |
2eb4d78b | 375 | else if (regno == mips_regnum (gdbarch)->cause) |
56cea623 | 376 | regaddr = MIPS64_EF_CP0_CAUSE; |
2eb4d78b | 377 | else if (mips_linux_restart_reg_p (gdbarch) |
822b6570 DJ |
378 | && regno == MIPS_RESTART_REGNUM) |
379 | regaddr = MIPS64_EF_REG0; | |
56cea623 AC |
380 | else |
381 | regaddr = -1; | |
96f026fc KB |
382 | |
383 | if (regaddr != -1) | |
384 | { | |
385 | dst = regp + regaddr; | |
b057297a | 386 | regcache->raw_collect_integer (regno, (gdb_byte *) dst, 8, true); |
96f026fc KB |
387 | } |
388 | } | |
389 | ||
50e8a0d5 HZ |
390 | static void |
391 | mips64_fill_gregset_wrapper (const struct regset *regset, | |
392 | const struct regcache *regcache, | |
393 | int regnum, void *gregs, size_t len) | |
394 | { | |
1528345d | 395 | gdb_assert (len >= sizeof (mips64_elf_gregset_t)); |
50e8a0d5 HZ |
396 | |
397 | mips64_fill_gregset (regcache, (mips64_elf_gregset_t *)gregs, regnum); | |
398 | } | |
399 | ||
d8dab6c3 MR |
400 | /* Likewise, unpack an elf_fpregset_t. Linux only uses even-numbered |
401 | FPR slots in the Status.FR=0 mode, storing even-odd FPR pairs as the | |
402 | SDC1 instruction would. When run on MIPS I architecture processors | |
403 | all FPR slots used to be used, unusually, holding the respective FPRs | |
404 | in the first 4 bytes, but that was corrected for consistency, with | |
405 | `linux-mips.org' (LMO) commit 42533948caac ("Major pile of FP emulator | |
406 | changes."), the fix corrected with LMO commit 849fa7a50dff ("R3k FPU | |
407 | ptrace() handling fixes."), and then broken and fixed over and over | |
408 | again, until last time fixed with commit 80cbfad79096 ("MIPS: Correct | |
409 | MIPS I FP context layout"). */ | |
96f026fc | 410 | |
d37eb719 | 411 | void |
28f5035f UW |
412 | mips64_supply_fpregset (struct regcache *regcache, |
413 | const mips64_elf_fpregset_t *fpregsetp) | |
96f026fc | 414 | { |
ac7936df | 415 | struct gdbarch *gdbarch = regcache->arch (); |
52f0bd74 | 416 | int regi; |
96f026fc | 417 | |
2eb4d78b | 418 | if (register_size (gdbarch, gdbarch_fp0_regnum (gdbarch)) == 4) |
d37eb719 DJ |
419 | for (regi = 0; regi < 32; regi++) |
420 | { | |
7d266584 MR |
421 | const gdb_byte *reg_ptr |
422 | = (const gdb_byte *) (*fpregsetp + (regi & ~1)); | |
2eb4d78b | 423 | if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (regi & 1)) |
d37eb719 | 424 | reg_ptr += 4; |
73e1c03f | 425 | regcache->raw_supply (gdbarch_fp0_regnum (gdbarch) + regi, reg_ptr); |
d37eb719 DJ |
426 | } |
427 | else | |
428 | for (regi = 0; regi < 32; regi++) | |
73e1c03f SM |
429 | regcache->raw_supply (gdbarch_fp0_regnum (gdbarch) + regi, |
430 | (const char *) (*fpregsetp + regi)); | |
d37eb719 | 431 | |
2eb4d78b | 432 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->fp_control_status, |
7d266584 | 433 | (const gdb_byte *) (*fpregsetp + 32)); |
d37eb719 DJ |
434 | |
435 | /* The ABI doesn't tell us how to supply FCRIR, and core dumps don't | |
436 | include it - but the result of PTRACE_GETFPREGS does. The best we | |
437 | can do is to assume that its value is present. */ | |
28f5035f | 438 | supply_32bit_reg (regcache, |
2eb4d78b | 439 | mips_regnum (gdbarch)->fp_implementation_revision, |
7d266584 | 440 | (const gdb_byte *) (*fpregsetp + 32) + 4); |
96f026fc KB |
441 | } |
442 | ||
50e8a0d5 HZ |
443 | static void |
444 | mips64_supply_fpregset_wrapper (const struct regset *regset, | |
7d266584 MR |
445 | struct regcache *regcache, |
446 | int regnum, const void *gregs, size_t len) | |
50e8a0d5 | 447 | { |
1528345d | 448 | gdb_assert (len >= sizeof (mips64_elf_fpregset_t)); |
50e8a0d5 HZ |
449 | |
450 | mips64_supply_fpregset (regcache, (const mips64_elf_fpregset_t *)gregs); | |
451 | } | |
452 | ||
96f026fc | 453 | /* Likewise, pack one or all floating point registers into an |
d8dab6c3 MR |
454 | elf_fpregset_t. See `mips_supply_fpregset' for an explanation |
455 | of the layout. */ | |
96f026fc | 456 | |
d37eb719 | 457 | void |
28f5035f UW |
458 | mips64_fill_fpregset (const struct regcache *regcache, |
459 | mips64_elf_fpregset_t *fpregsetp, int regno) | |
96f026fc | 460 | { |
ac7936df | 461 | struct gdbarch *gdbarch = regcache->arch (); |
d37eb719 | 462 | gdb_byte *to; |
96f026fc | 463 | |
2eb4d78b UW |
464 | if ((regno >= gdbarch_fp0_regnum (gdbarch)) |
465 | && (regno < gdbarch_fp0_regnum (gdbarch) + 32)) | |
96f026fc | 466 | { |
2eb4d78b | 467 | if (register_size (gdbarch, regno) == 4) |
d37eb719 | 468 | { |
2eb4d78b | 469 | int regi = regno - gdbarch_fp0_regnum (gdbarch); |
d37eb719 DJ |
470 | |
471 | to = (gdb_byte *) (*fpregsetp + (regi & ~1)); | |
2eb4d78b | 472 | if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (regi & 1)) |
d37eb719 | 473 | to += 4; |
34a79281 | 474 | regcache->raw_collect (regno, to); |
d37eb719 DJ |
475 | } |
476 | else | |
477 | { | |
025bb325 MS |
478 | to = (gdb_byte *) (*fpregsetp + regno |
479 | - gdbarch_fp0_regnum (gdbarch)); | |
34a79281 | 480 | regcache->raw_collect (regno, to); |
d37eb719 | 481 | } |
96f026fc | 482 | } |
2eb4d78b | 483 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
96f026fc | 484 | { |
d37eb719 | 485 | to = (gdb_byte *) (*fpregsetp + 32); |
b057297a | 486 | regcache->raw_collect_integer (regno, to, 4, true); |
d37eb719 | 487 | } |
2eb4d78b | 488 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
d37eb719 | 489 | { |
d37eb719 | 490 | to = (gdb_byte *) (*fpregsetp + 32) + 4; |
b057297a | 491 | regcache->raw_collect_integer (regno, to, 4, true); |
96f026fc KB |
492 | } |
493 | else if (regno == -1) | |
494 | { | |
495 | int regi; | |
496 | ||
497 | for (regi = 0; regi < 32; regi++) | |
3e8c568d | 498 | mips64_fill_fpregset (regcache, fpregsetp, |
2eb4d78b | 499 | gdbarch_fp0_regnum (gdbarch) + regi); |
28f5035f | 500 | mips64_fill_fpregset (regcache, fpregsetp, |
2eb4d78b | 501 | mips_regnum (gdbarch)->fp_control_status); |
28f5035f | 502 | mips64_fill_fpregset (regcache, fpregsetp, |
7d266584 | 503 | mips_regnum (gdbarch)->fp_implementation_revision); |
96f026fc KB |
504 | } |
505 | } | |
506 | ||
50e8a0d5 HZ |
507 | static void |
508 | mips64_fill_fpregset_wrapper (const struct regset *regset, | |
509 | const struct regcache *regcache, | |
510 | int regnum, void *gregs, size_t len) | |
511 | { | |
1528345d | 512 | gdb_assert (len >= sizeof (mips64_elf_fpregset_t)); |
96f026fc | 513 | |
50e8a0d5 HZ |
514 | mips64_fill_fpregset (regcache, (mips64_elf_fpregset_t *)gregs, regnum); |
515 | } | |
2aa830e4 | 516 | |
b7195f27 AA |
517 | static const struct regset mips_linux_gregset = |
518 | { | |
519 | NULL, mips_supply_gregset_wrapper, mips_fill_gregset_wrapper | |
520 | }; | |
521 | ||
522 | static const struct regset mips64_linux_gregset = | |
523 | { | |
524 | NULL, mips64_supply_gregset_wrapper, mips64_fill_gregset_wrapper | |
525 | }; | |
526 | ||
b7195f27 AA |
527 | static const struct regset mips64_linux_fpregset = |
528 | { | |
529 | NULL, mips64_supply_fpregset_wrapper, mips64_fill_fpregset_wrapper | |
530 | }; | |
531 | ||
d4036235 AA |
532 | static void |
533 | mips_linux_iterate_over_regset_sections (struct gdbarch *gdbarch, | |
534 | iterate_over_regset_sections_cb *cb, | |
535 | void *cb_data, | |
536 | const struct regcache *regcache) | |
2aa830e4 | 537 | { |
d4036235 | 538 | if (register_size (gdbarch, MIPS_ZERO_REGNUM) == 4) |
2aa830e4 | 539 | { |
a616bb94 AH |
540 | cb (".reg", sizeof (mips_elf_gregset_t), sizeof (mips_elf_gregset_t), |
541 | &mips_linux_gregset, NULL, cb_data); | |
542 | cb (".reg2", sizeof (mips64_elf_fpregset_t), | |
543 | sizeof (mips64_elf_fpregset_t), &mips64_linux_fpregset, | |
d4036235 | 544 | NULL, cb_data); |
2aa830e4 | 545 | } |
d4036235 | 546 | else |
2aa830e4 | 547 | { |
a616bb94 AH |
548 | cb (".reg", sizeof (mips64_elf_gregset_t), sizeof (mips64_elf_gregset_t), |
549 | &mips64_linux_gregset, NULL, cb_data); | |
550 | cb (".reg2", sizeof (mips64_elf_fpregset_t), | |
551 | sizeof (mips64_elf_fpregset_t), &mips64_linux_fpregset, | |
d4036235 | 552 | NULL, cb_data); |
2aa830e4 | 553 | } |
50e8a0d5 | 554 | } |
2aa830e4 | 555 | |
4eb0ad19 DJ |
556 | static const struct target_desc * |
557 | mips_linux_core_read_description (struct gdbarch *gdbarch, | |
558 | struct target_ops *target, | |
559 | bfd *abfd) | |
560 | { | |
561 | asection *section = bfd_get_section_by_name (abfd, ".reg"); | |
562 | if (! section) | |
563 | return NULL; | |
564 | ||
fd361982 | 565 | switch (bfd_section_size (section)) |
4eb0ad19 DJ |
566 | { |
567 | case sizeof (mips_elf_gregset_t): | |
568 | return mips_tdesc_gp32; | |
569 | ||
570 | case sizeof (mips64_elf_gregset_t): | |
571 | return mips_tdesc_gp64; | |
572 | ||
573 | default: | |
574 | return NULL; | |
575 | } | |
576 | } | |
577 | ||
96f026fc | 578 | |
295093a4 | 579 | /* Check the code at PC for a dynamic linker lazy resolution stub. |
3e5d3a5a MR |
580 | GNU ld for MIPS has put lazy resolution stubs into a ".MIPS.stubs" |
581 | section uniformly since version 2.15. If the pc is in that section, | |
582 | then we are in such a stub. Before that ".stub" was used in 32-bit | |
583 | ELF binaries, however we do not bother checking for that since we | |
584 | have never had and that case should be extremely rare these days. | |
585 | Instead we pattern-match on the code generated by GNU ld. They look | |
586 | like this: | |
6de918a6 DJ |
587 | |
588 | lw t9,0x8010(gp) | |
589 | addu t7,ra | |
590 | jalr t9,ra | |
591 | addiu t8,zero,INDEX | |
592 | ||
3e5d3a5a MR |
593 | (with the appropriate doubleword instructions for N64). As any lazy |
594 | resolution stubs in microMIPS binaries will always be in a | |
595 | ".MIPS.stubs" section we only ever verify standard MIPS patterns. */ | |
6de918a6 DJ |
596 | |
597 | static int | |
3e5d3a5a | 598 | mips_linux_in_dynsym_stub (CORE_ADDR pc) |
6de918a6 | 599 | { |
e362b510 | 600 | gdb_byte buf[28], *p; |
6de918a6 | 601 | ULONGEST insn, insn1; |
f5656ead TT |
602 | int n64 = (mips_abi (target_gdbarch ()) == MIPS_ABI_N64); |
603 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); | |
6de918a6 | 604 | |
3e5d3a5a MR |
605 | if (in_mips_stubs_section (pc)) |
606 | return 1; | |
607 | ||
6de918a6 DJ |
608 | read_memory (pc - 12, buf, 28); |
609 | ||
610 | if (n64) | |
611 | { | |
612 | /* ld t9,0x8010(gp) */ | |
613 | insn1 = 0xdf998010; | |
614 | } | |
615 | else | |
616 | { | |
617 | /* lw t9,0x8010(gp) */ | |
618 | insn1 = 0x8f998010; | |
619 | } | |
620 | ||
621 | p = buf + 12; | |
622 | while (p >= buf) | |
623 | { | |
e17a4113 | 624 | insn = extract_unsigned_integer (p, 4, byte_order); |
6de918a6 DJ |
625 | if (insn == insn1) |
626 | break; | |
627 | p -= 4; | |
628 | } | |
629 | if (p < buf) | |
630 | return 0; | |
631 | ||
e17a4113 | 632 | insn = extract_unsigned_integer (p + 4, 4, byte_order); |
6de918a6 DJ |
633 | if (n64) |
634 | { | |
93084fcd | 635 | /* 'daddu t7,ra' or 'or t7, ra, zero'*/ |
59f7bd8d | 636 | if (insn != 0x03e0782d && insn != 0x03e07825) |
6de918a6 DJ |
637 | return 0; |
638 | } | |
639 | else | |
640 | { | |
93084fcd | 641 | /* 'addu t7,ra' or 'or t7, ra, zero'*/ |
59f7bd8d | 642 | if (insn != 0x03e07821 && insn != 0x03e07825) |
6de918a6 DJ |
643 | return 0; |
644 | } | |
295093a4 | 645 | |
e17a4113 | 646 | insn = extract_unsigned_integer (p + 8, 4, byte_order); |
6de918a6 DJ |
647 | /* jalr t9,ra */ |
648 | if (insn != 0x0320f809) | |
649 | return 0; | |
650 | ||
e17a4113 | 651 | insn = extract_unsigned_integer (p + 12, 4, byte_order); |
6de918a6 DJ |
652 | if (n64) |
653 | { | |
654 | /* daddiu t8,zero,0 */ | |
655 | if ((insn & 0xffff0000) != 0x64180000) | |
656 | return 0; | |
657 | } | |
658 | else | |
659 | { | |
660 | /* addiu t8,zero,0 */ | |
661 | if ((insn & 0xffff0000) != 0x24180000) | |
662 | return 0; | |
663 | } | |
664 | ||
3e5d3a5a | 665 | return 1; |
6de918a6 DJ |
666 | } |
667 | ||
295093a4 | 668 | /* Return non-zero iff PC belongs to the dynamic linker resolution |
db5f024e | 669 | code, a PLT entry, or a lazy binding stub. */ |
6de918a6 | 670 | |
7d522c90 | 671 | static int |
6de918a6 DJ |
672 | mips_linux_in_dynsym_resolve_code (CORE_ADDR pc) |
673 | { | |
295093a4 | 674 | /* Check whether PC is in the dynamic linker. This also checks |
db5f024e | 675 | whether it is in the .plt section, used by non-PIC executables. */ |
7d522c90 | 676 | if (svr4_in_dynsym_resolve_code (pc)) |
6de918a6 DJ |
677 | return 1; |
678 | ||
3e5d3a5a MR |
679 | /* Likewise for the stubs. They live in the .MIPS.stubs section these |
680 | days, so we check if the PC is within, than fall back to a pattern | |
681 | match. */ | |
682 | if (mips_linux_in_dynsym_stub (pc)) | |
6de918a6 DJ |
683 | return 1; |
684 | ||
685 | return 0; | |
686 | } | |
687 | ||
688 | /* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c, | |
689 | and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc | |
690 | implementation of this triggers at "fixup" from the same objfile as | |
c4c5b7ba | 691 | "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at |
db5f024e DJ |
692 | "__dl_runtime_resolve" directly. An unresolved lazy binding |
693 | stub will point to _dl_runtime_resolve, which will first call | |
c4c5b7ba AC |
694 | __dl_runtime_resolve, and then pass control to the resolved |
695 | function. */ | |
6de918a6 DJ |
696 | |
697 | static CORE_ADDR | |
698 | mips_linux_skip_resolver (struct gdbarch *gdbarch, CORE_ADDR pc) | |
699 | { | |
3b7344d5 | 700 | struct bound_minimal_symbol resolver; |
6de918a6 DJ |
701 | |
702 | resolver = lookup_minimal_symbol ("__dl_runtime_resolve", NULL, NULL); | |
703 | ||
77e371c0 | 704 | if (resolver.minsym && BMSYMBOL_VALUE_ADDRESS (resolver) == pc) |
c7ce8faa | 705 | return frame_unwind_caller_pc (get_current_frame ()); |
6de918a6 | 706 | |
db5f024e | 707 | return glibc_skip_solib_resolver (gdbarch, pc); |
295093a4 | 708 | } |
6de918a6 | 709 | |
5792a79b DJ |
710 | /* Signal trampoline support. There are four supported layouts for a |
711 | signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and | |
712 | n64 rt_sigframe. We handle them all independently; not the most | |
713 | efficient way, but simplest. First, declare all the unwinders. */ | |
714 | ||
715 | static void mips_linux_o32_sigframe_init (const struct tramp_frame *self, | |
b8a22b94 | 716 | struct frame_info *this_frame, |
5792a79b DJ |
717 | struct trad_frame_cache *this_cache, |
718 | CORE_ADDR func); | |
719 | ||
720 | static void mips_linux_n32n64_sigframe_init (const struct tramp_frame *self, | |
b8a22b94 | 721 | struct frame_info *this_frame, |
5792a79b DJ |
722 | struct trad_frame_cache *this_cache, |
723 | CORE_ADDR func); | |
724 | ||
858339f2 MR |
725 | static int mips_linux_sigframe_validate (const struct tramp_frame *self, |
726 | struct frame_info *this_frame, | |
727 | CORE_ADDR *pc); | |
728 | ||
729 | static int micromips_linux_sigframe_validate (const struct tramp_frame *self, | |
730 | struct frame_info *this_frame, | |
731 | CORE_ADDR *pc); | |
732 | ||
5792a79b DJ |
733 | #define MIPS_NR_LINUX 4000 |
734 | #define MIPS_NR_N64_LINUX 5000 | |
735 | #define MIPS_NR_N32_LINUX 6000 | |
736 | ||
737 | #define MIPS_NR_sigreturn MIPS_NR_LINUX + 119 | |
738 | #define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193 | |
739 | #define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211 | |
740 | #define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211 | |
741 | ||
742 | #define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn | |
743 | #define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn | |
744 | #define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn | |
745 | #define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn | |
746 | #define MIPS_INST_SYSCALL 0x0000000c | |
747 | ||
858339f2 MR |
748 | #define MICROMIPS_INST_LI_V0 0x3040 |
749 | #define MICROMIPS_INST_POOL32A 0x0000 | |
750 | #define MICROMIPS_INST_SYSCALL 0x8b7c | |
751 | ||
2cd8546d AC |
752 | static const struct tramp_frame mips_linux_o32_sigframe = { |
753 | SIGTRAMP_FRAME, | |
5792a79b | 754 | 4, |
2cd8546d | 755 | { |
7bc02706 TT |
756 | { MIPS_INST_LI_V0_SIGRETURN, ULONGEST_MAX }, |
757 | { MIPS_INST_SYSCALL, ULONGEST_MAX }, | |
758 | { TRAMP_SENTINEL_INSN, ULONGEST_MAX } | |
2cd8546d | 759 | }, |
858339f2 MR |
760 | mips_linux_o32_sigframe_init, |
761 | mips_linux_sigframe_validate | |
5792a79b DJ |
762 | }; |
763 | ||
2cd8546d AC |
764 | static const struct tramp_frame mips_linux_o32_rt_sigframe = { |
765 | SIGTRAMP_FRAME, | |
5792a79b | 766 | 4, |
2cd8546d | 767 | { |
7bc02706 TT |
768 | { MIPS_INST_LI_V0_RT_SIGRETURN, ULONGEST_MAX }, |
769 | { MIPS_INST_SYSCALL, ULONGEST_MAX }, | |
770 | { TRAMP_SENTINEL_INSN, ULONGEST_MAX } }, | |
858339f2 MR |
771 | mips_linux_o32_sigframe_init, |
772 | mips_linux_sigframe_validate | |
5792a79b DJ |
773 | }; |
774 | ||
2cd8546d AC |
775 | static const struct tramp_frame mips_linux_n32_rt_sigframe = { |
776 | SIGTRAMP_FRAME, | |
5792a79b | 777 | 4, |
2cd8546d | 778 | { |
7bc02706 TT |
779 | { MIPS_INST_LI_V0_N32_RT_SIGRETURN, ULONGEST_MAX }, |
780 | { MIPS_INST_SYSCALL, ULONGEST_MAX }, | |
781 | { TRAMP_SENTINEL_INSN, ULONGEST_MAX } | |
2cd8546d | 782 | }, |
858339f2 MR |
783 | mips_linux_n32n64_sigframe_init, |
784 | mips_linux_sigframe_validate | |
5792a79b DJ |
785 | }; |
786 | ||
2cd8546d AC |
787 | static const struct tramp_frame mips_linux_n64_rt_sigframe = { |
788 | SIGTRAMP_FRAME, | |
5792a79b | 789 | 4, |
fcbd8a5c | 790 | { |
7bc02706 TT |
791 | { MIPS_INST_LI_V0_N64_RT_SIGRETURN, ULONGEST_MAX }, |
792 | { MIPS_INST_SYSCALL, ULONGEST_MAX }, | |
793 | { TRAMP_SENTINEL_INSN, ULONGEST_MAX } | |
fcbd8a5c | 794 | }, |
858339f2 MR |
795 | mips_linux_n32n64_sigframe_init, |
796 | mips_linux_sigframe_validate | |
797 | }; | |
798 | ||
799 | static const struct tramp_frame micromips_linux_o32_sigframe = { | |
800 | SIGTRAMP_FRAME, | |
801 | 2, | |
802 | { | |
7bc02706 TT |
803 | { MICROMIPS_INST_LI_V0, ULONGEST_MAX }, |
804 | { MIPS_NR_sigreturn, ULONGEST_MAX }, | |
805 | { MICROMIPS_INST_POOL32A, ULONGEST_MAX }, | |
806 | { MICROMIPS_INST_SYSCALL, ULONGEST_MAX }, | |
807 | { TRAMP_SENTINEL_INSN, ULONGEST_MAX } | |
858339f2 MR |
808 | }, |
809 | mips_linux_o32_sigframe_init, | |
810 | micromips_linux_sigframe_validate | |
811 | }; | |
812 | ||
813 | static const struct tramp_frame micromips_linux_o32_rt_sigframe = { | |
814 | SIGTRAMP_FRAME, | |
815 | 2, | |
816 | { | |
7bc02706 TT |
817 | { MICROMIPS_INST_LI_V0, ULONGEST_MAX }, |
818 | { MIPS_NR_rt_sigreturn, ULONGEST_MAX }, | |
819 | { MICROMIPS_INST_POOL32A, ULONGEST_MAX }, | |
820 | { MICROMIPS_INST_SYSCALL, ULONGEST_MAX }, | |
821 | { TRAMP_SENTINEL_INSN, ULONGEST_MAX } | |
858339f2 MR |
822 | }, |
823 | mips_linux_o32_sigframe_init, | |
824 | micromips_linux_sigframe_validate | |
825 | }; | |
826 | ||
827 | static const struct tramp_frame micromips_linux_n32_rt_sigframe = { | |
828 | SIGTRAMP_FRAME, | |
829 | 2, | |
830 | { | |
7bc02706 TT |
831 | { MICROMIPS_INST_LI_V0, ULONGEST_MAX }, |
832 | { MIPS_NR_N32_rt_sigreturn, ULONGEST_MAX }, | |
833 | { MICROMIPS_INST_POOL32A, ULONGEST_MAX }, | |
834 | { MICROMIPS_INST_SYSCALL, ULONGEST_MAX }, | |
835 | { TRAMP_SENTINEL_INSN, ULONGEST_MAX } | |
858339f2 MR |
836 | }, |
837 | mips_linux_n32n64_sigframe_init, | |
838 | micromips_linux_sigframe_validate | |
839 | }; | |
840 | ||
841 | static const struct tramp_frame micromips_linux_n64_rt_sigframe = { | |
842 | SIGTRAMP_FRAME, | |
843 | 2, | |
844 | { | |
7bc02706 TT |
845 | { MICROMIPS_INST_LI_V0, ULONGEST_MAX }, |
846 | { MIPS_NR_N64_rt_sigreturn, ULONGEST_MAX }, | |
847 | { MICROMIPS_INST_POOL32A, ULONGEST_MAX }, | |
848 | { MICROMIPS_INST_SYSCALL, ULONGEST_MAX }, | |
849 | { TRAMP_SENTINEL_INSN, ULONGEST_MAX } | |
858339f2 MR |
850 | }, |
851 | mips_linux_n32n64_sigframe_init, | |
852 | micromips_linux_sigframe_validate | |
5792a79b DJ |
853 | }; |
854 | ||
855 | /* *INDENT-OFF* */ | |
856 | /* The unwinder for o32 signal frames. The legacy structures look | |
857 | like this: | |
858 | ||
859 | struct sigframe { | |
860 | u32 sf_ass[4]; [argument save space for o32] | |
eb195664 | 861 | u32 sf_code[2]; [signal trampoline or fill] |
5792a79b DJ |
862 | struct sigcontext sf_sc; |
863 | sigset_t sf_mask; | |
864 | }; | |
865 | ||
d0e64392 MR |
866 | Pre-2.6.12 sigcontext: |
867 | ||
5792a79b DJ |
868 | struct sigcontext { |
869 | unsigned int sc_regmask; [Unused] | |
870 | unsigned int sc_status; | |
871 | unsigned long long sc_pc; | |
872 | unsigned long long sc_regs[32]; | |
873 | unsigned long long sc_fpregs[32]; | |
874 | unsigned int sc_ownedfp; | |
875 | unsigned int sc_fpc_csr; | |
876 | unsigned int sc_fpc_eir; [Unused] | |
877 | unsigned int sc_used_math; | |
878 | unsigned int sc_ssflags; [Unused] | |
879 | [Alignment hole of four bytes] | |
880 | unsigned long long sc_mdhi; | |
881 | unsigned long long sc_mdlo; | |
882 | ||
883 | unsigned int sc_cause; [Unused] | |
884 | unsigned int sc_badvaddr; [Unused] | |
885 | ||
886 | unsigned long sc_sigset[4]; [kernel's sigset_t] | |
887 | }; | |
888 | ||
d0e64392 MR |
889 | Post-2.6.12 sigcontext (SmartMIPS/DSP support added): |
890 | ||
891 | struct sigcontext { | |
892 | unsigned int sc_regmask; [Unused] | |
893 | unsigned int sc_status; [Unused] | |
894 | unsigned long long sc_pc; | |
895 | unsigned long long sc_regs[32]; | |
896 | unsigned long long sc_fpregs[32]; | |
897 | unsigned int sc_acx; | |
898 | unsigned int sc_fpc_csr; | |
899 | unsigned int sc_fpc_eir; [Unused] | |
900 | unsigned int sc_used_math; | |
901 | unsigned int sc_dsp; | |
902 | [Alignment hole of four bytes] | |
903 | unsigned long long sc_mdhi; | |
904 | unsigned long long sc_mdlo; | |
905 | unsigned long sc_hi1; | |
906 | unsigned long sc_lo1; | |
907 | unsigned long sc_hi2; | |
908 | unsigned long sc_lo2; | |
909 | unsigned long sc_hi3; | |
910 | unsigned long sc_lo3; | |
911 | }; | |
912 | ||
5792a79b DJ |
913 | The RT signal frames look like this: |
914 | ||
915 | struct rt_sigframe { | |
916 | u32 rs_ass[4]; [argument save space for o32] | |
eb195664 | 917 | u32 rs_code[2] [signal trampoline or fill] |
5792a79b DJ |
918 | struct siginfo rs_info; |
919 | struct ucontext rs_uc; | |
920 | }; | |
921 | ||
922 | struct ucontext { | |
923 | unsigned long uc_flags; | |
924 | struct ucontext *uc_link; | |
925 | stack_t uc_stack; | |
926 | [Alignment hole of four bytes] | |
927 | struct sigcontext uc_mcontext; | |
928 | sigset_t uc_sigmask; | |
929 | }; */ | |
930 | /* *INDENT-ON* */ | |
931 | ||
5792a79b DJ |
932 | #define SIGFRAME_SIGCONTEXT_OFFSET (6 * 4) |
933 | ||
934 | #define RTSIGFRAME_SIGINFO_SIZE 128 | |
935 | #define STACK_T_SIZE (3 * 4) | |
936 | #define UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + STACK_T_SIZE + 4) | |
937 | #define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ | |
938 | + RTSIGFRAME_SIGINFO_SIZE \ | |
939 | + UCONTEXT_SIGCONTEXT_OFFSET) | |
940 | ||
941 | #define SIGCONTEXT_PC (1 * 8) | |
942 | #define SIGCONTEXT_REGS (2 * 8) | |
943 | #define SIGCONTEXT_FPREGS (34 * 8) | |
944 | #define SIGCONTEXT_FPCSR (66 * 8 + 4) | |
d0e64392 | 945 | #define SIGCONTEXT_DSPCTL (68 * 8 + 0) |
5792a79b DJ |
946 | #define SIGCONTEXT_HI (69 * 8) |
947 | #define SIGCONTEXT_LO (70 * 8) | |
948 | #define SIGCONTEXT_CAUSE (71 * 8 + 0) | |
949 | #define SIGCONTEXT_BADVADDR (71 * 8 + 4) | |
d0e64392 MR |
950 | #define SIGCONTEXT_HI1 (71 * 8 + 0) |
951 | #define SIGCONTEXT_LO1 (71 * 8 + 4) | |
952 | #define SIGCONTEXT_HI2 (72 * 8 + 0) | |
953 | #define SIGCONTEXT_LO2 (72 * 8 + 4) | |
954 | #define SIGCONTEXT_HI3 (73 * 8 + 0) | |
955 | #define SIGCONTEXT_LO3 (73 * 8 + 4) | |
5792a79b DJ |
956 | |
957 | #define SIGCONTEXT_REG_SIZE 8 | |
958 | ||
959 | static void | |
960 | mips_linux_o32_sigframe_init (const struct tramp_frame *self, | |
b8a22b94 | 961 | struct frame_info *this_frame, |
5792a79b DJ |
962 | struct trad_frame_cache *this_cache, |
963 | CORE_ADDR func) | |
964 | { | |
b8a22b94 | 965 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
22e048c9 | 966 | int ireg; |
eb195664 DD |
967 | CORE_ADDR frame_sp = get_frame_sp (this_frame); |
968 | CORE_ADDR sigcontext_base; | |
2eb4d78b | 969 | const struct mips_regnum *regs = mips_regnum (gdbarch); |
37c4d197 | 970 | CORE_ADDR regs_base; |
5792a79b | 971 | |
858339f2 MR |
972 | if (self == &mips_linux_o32_sigframe |
973 | || self == µmips_linux_o32_sigframe) | |
eb195664 | 974 | sigcontext_base = frame_sp + SIGFRAME_SIGCONTEXT_OFFSET; |
5792a79b | 975 | else |
eb195664 | 976 | sigcontext_base = frame_sp + RTSIGFRAME_SIGCONTEXT_OFFSET; |
295093a4 MS |
977 | |
978 | /* I'm not proud of this hack. Eventually we will have the | |
979 | infrastructure to indicate the size of saved registers on a | |
980 | per-frame basis, but right now we don't; the kernel saves eight | |
37c4d197 DJ |
981 | bytes but we only want four. Use regs_base to access any |
982 | 64-bit fields. */ | |
2eb4d78b | 983 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
37c4d197 DJ |
984 | regs_base = sigcontext_base + 4; |
985 | else | |
986 | regs_base = sigcontext_base; | |
5792a79b | 987 | |
2eb4d78b | 988 | if (mips_linux_restart_reg_p (gdbarch)) |
822b6570 DJ |
989 | trad_frame_set_reg_addr (this_cache, |
990 | (MIPS_RESTART_REGNUM | |
2eb4d78b | 991 | + gdbarch_num_regs (gdbarch)), |
822b6570 | 992 | regs_base + SIGCONTEXT_REGS); |
5792a79b DJ |
993 | |
994 | for (ireg = 1; ireg < 32; ireg++) | |
295093a4 | 995 | trad_frame_set_reg_addr (this_cache, |
7d266584 MR |
996 | (ireg + MIPS_ZERO_REGNUM |
997 | + gdbarch_num_regs (gdbarch)), | |
998 | (regs_base + SIGCONTEXT_REGS | |
999 | + ireg * SIGCONTEXT_REG_SIZE)); | |
5792a79b DJ |
1000 | |
1001 | for (ireg = 0; ireg < 32; ireg++) | |
2eb4d78b | 1002 | if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (ireg & 1)) |
f57d151a | 1003 | trad_frame_set_reg_addr (this_cache, |
7d266584 MR |
1004 | ireg + regs->fp0 + gdbarch_num_regs (gdbarch), |
1005 | (sigcontext_base + SIGCONTEXT_FPREGS + 4 | |
1006 | + (ireg & ~1) * SIGCONTEXT_REG_SIZE)); | |
37c4d197 | 1007 | else |
f57d151a | 1008 | trad_frame_set_reg_addr (this_cache, |
7d266584 MR |
1009 | ireg + regs->fp0 + gdbarch_num_regs (gdbarch), |
1010 | (sigcontext_base + SIGCONTEXT_FPREGS | |
1011 | + (ireg & ~1) * SIGCONTEXT_REG_SIZE)); | |
5792a79b | 1012 | |
f57d151a | 1013 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1014 | regs->pc + gdbarch_num_regs (gdbarch), |
37c4d197 | 1015 | regs_base + SIGCONTEXT_PC); |
5792a79b | 1016 | |
295093a4 | 1017 | trad_frame_set_reg_addr (this_cache, |
7d266584 MR |
1018 | (regs->fp_control_status |
1019 | + gdbarch_num_regs (gdbarch)), | |
5792a79b | 1020 | sigcontext_base + SIGCONTEXT_FPCSR); |
d0e64392 MR |
1021 | |
1022 | if (regs->dspctl != -1) | |
1023 | trad_frame_set_reg_addr (this_cache, | |
1024 | regs->dspctl + gdbarch_num_regs (gdbarch), | |
1025 | sigcontext_base + SIGCONTEXT_DSPCTL); | |
1026 | ||
f57d151a | 1027 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1028 | regs->hi + gdbarch_num_regs (gdbarch), |
37c4d197 | 1029 | regs_base + SIGCONTEXT_HI); |
f57d151a | 1030 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1031 | regs->lo + gdbarch_num_regs (gdbarch), |
37c4d197 | 1032 | regs_base + SIGCONTEXT_LO); |
d0e64392 MR |
1033 | |
1034 | if (regs->dspacc != -1) | |
1035 | { | |
1036 | trad_frame_set_reg_addr (this_cache, | |
1037 | regs->dspacc + 0 + gdbarch_num_regs (gdbarch), | |
1038 | sigcontext_base + SIGCONTEXT_HI1); | |
1039 | trad_frame_set_reg_addr (this_cache, | |
1040 | regs->dspacc + 1 + gdbarch_num_regs (gdbarch), | |
1041 | sigcontext_base + SIGCONTEXT_LO1); | |
1042 | trad_frame_set_reg_addr (this_cache, | |
1043 | regs->dspacc + 2 + gdbarch_num_regs (gdbarch), | |
1044 | sigcontext_base + SIGCONTEXT_HI2); | |
1045 | trad_frame_set_reg_addr (this_cache, | |
1046 | regs->dspacc + 3 + gdbarch_num_regs (gdbarch), | |
1047 | sigcontext_base + SIGCONTEXT_LO2); | |
1048 | trad_frame_set_reg_addr (this_cache, | |
1049 | regs->dspacc + 4 + gdbarch_num_regs (gdbarch), | |
1050 | sigcontext_base + SIGCONTEXT_HI3); | |
1051 | trad_frame_set_reg_addr (this_cache, | |
1052 | regs->dspacc + 5 + gdbarch_num_regs (gdbarch), | |
1053 | sigcontext_base + SIGCONTEXT_LO3); | |
1054 | } | |
1055 | else | |
1056 | { | |
1057 | trad_frame_set_reg_addr (this_cache, | |
1058 | regs->cause + gdbarch_num_regs (gdbarch), | |
1059 | sigcontext_base + SIGCONTEXT_CAUSE); | |
1060 | trad_frame_set_reg_addr (this_cache, | |
1061 | regs->badvaddr + gdbarch_num_regs (gdbarch), | |
1062 | sigcontext_base + SIGCONTEXT_BADVADDR); | |
1063 | } | |
5792a79b DJ |
1064 | |
1065 | /* Choice of the bottom of the sigframe is somewhat arbitrary. */ | |
eb195664 | 1066 | trad_frame_set_id (this_cache, frame_id_build (frame_sp, func)); |
5792a79b DJ |
1067 | } |
1068 | ||
1069 | /* *INDENT-OFF* */ | |
1070 | /* For N32/N64 things look different. There is no non-rt signal frame. | |
1071 | ||
1072 | struct rt_sigframe_n32 { | |
1073 | u32 rs_ass[4]; [ argument save space for o32 ] | |
eb195664 | 1074 | u32 rs_code[2]; [ signal trampoline or fill ] |
5792a79b DJ |
1075 | struct siginfo rs_info; |
1076 | struct ucontextn32 rs_uc; | |
1077 | }; | |
1078 | ||
1079 | struct ucontextn32 { | |
1080 | u32 uc_flags; | |
1081 | s32 uc_link; | |
1082 | stack32_t uc_stack; | |
1083 | struct sigcontext uc_mcontext; | |
1084 | sigset_t uc_sigmask; [ mask last for extensibility ] | |
1085 | }; | |
295093a4 | 1086 | |
e741f4d4 | 1087 | struct rt_sigframe { |
5792a79b DJ |
1088 | u32 rs_ass[4]; [ argument save space for o32 ] |
1089 | u32 rs_code[2]; [ signal trampoline ] | |
1090 | struct siginfo rs_info; | |
1091 | struct ucontext rs_uc; | |
1092 | }; | |
1093 | ||
1094 | struct ucontext { | |
1095 | unsigned long uc_flags; | |
1096 | struct ucontext *uc_link; | |
1097 | stack_t uc_stack; | |
1098 | struct sigcontext uc_mcontext; | |
1099 | sigset_t uc_sigmask; [ mask last for extensibility ] | |
1100 | }; | |
1101 | ||
1102 | And the sigcontext is different (this is for both n32 and n64): | |
1103 | ||
1104 | struct sigcontext { | |
1105 | unsigned long long sc_regs[32]; | |
1106 | unsigned long long sc_fpregs[32]; | |
1107 | unsigned long long sc_mdhi; | |
e741f4d4 DJ |
1108 | unsigned long long sc_hi1; |
1109 | unsigned long long sc_hi2; | |
1110 | unsigned long long sc_hi3; | |
5792a79b | 1111 | unsigned long long sc_mdlo; |
e741f4d4 DJ |
1112 | unsigned long long sc_lo1; |
1113 | unsigned long long sc_lo2; | |
1114 | unsigned long long sc_lo3; | |
5792a79b | 1115 | unsigned long long sc_pc; |
5792a79b | 1116 | unsigned int sc_fpc_csr; |
5792a79b | 1117 | unsigned int sc_used_math; |
e741f4d4 DJ |
1118 | unsigned int sc_dsp; |
1119 | unsigned int sc_reserved; | |
1120 | }; | |
1121 | ||
1122 | That is the post-2.6.12 definition of the 64-bit sigcontext; before | |
1123 | then, there were no hi1-hi3 or lo1-lo3. Cause and badvaddr were | |
1124 | included too. */ | |
5792a79b DJ |
1125 | /* *INDENT-ON* */ |
1126 | ||
1127 | #define N32_STACK_T_SIZE STACK_T_SIZE | |
1128 | #define N64_STACK_T_SIZE (2 * 8 + 4) | |
1129 | #define N32_UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + N32_STACK_T_SIZE + 4) | |
1130 | #define N64_UCONTEXT_SIGCONTEXT_OFFSET (2 * 8 + N64_STACK_T_SIZE + 4) | |
1131 | #define N32_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ | |
1132 | + RTSIGFRAME_SIGINFO_SIZE \ | |
1133 | + N32_UCONTEXT_SIGCONTEXT_OFFSET) | |
1134 | #define N64_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ | |
1135 | + RTSIGFRAME_SIGINFO_SIZE \ | |
1136 | + N64_UCONTEXT_SIGCONTEXT_OFFSET) | |
1137 | ||
1138 | #define N64_SIGCONTEXT_REGS (0 * 8) | |
1139 | #define N64_SIGCONTEXT_FPREGS (32 * 8) | |
1140 | #define N64_SIGCONTEXT_HI (64 * 8) | |
d0e64392 MR |
1141 | #define N64_SIGCONTEXT_HI1 (65 * 8) |
1142 | #define N64_SIGCONTEXT_HI2 (66 * 8) | |
1143 | #define N64_SIGCONTEXT_HI3 (67 * 8) | |
e741f4d4 | 1144 | #define N64_SIGCONTEXT_LO (68 * 8) |
d0e64392 MR |
1145 | #define N64_SIGCONTEXT_LO1 (69 * 8) |
1146 | #define N64_SIGCONTEXT_LO2 (70 * 8) | |
1147 | #define N64_SIGCONTEXT_LO3 (71 * 8) | |
e741f4d4 | 1148 | #define N64_SIGCONTEXT_PC (72 * 8) |
d0e64392 MR |
1149 | #define N64_SIGCONTEXT_FPCSR (73 * 8 + 0) |
1150 | #define N64_SIGCONTEXT_DSPCTL (74 * 8 + 0) | |
5792a79b DJ |
1151 | |
1152 | #define N64_SIGCONTEXT_REG_SIZE 8 | |
295093a4 | 1153 | |
5792a79b DJ |
1154 | static void |
1155 | mips_linux_n32n64_sigframe_init (const struct tramp_frame *self, | |
b8a22b94 | 1156 | struct frame_info *this_frame, |
5792a79b DJ |
1157 | struct trad_frame_cache *this_cache, |
1158 | CORE_ADDR func) | |
1159 | { | |
b8a22b94 | 1160 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
22e048c9 | 1161 | int ireg; |
eb195664 DD |
1162 | CORE_ADDR frame_sp = get_frame_sp (this_frame); |
1163 | CORE_ADDR sigcontext_base; | |
2eb4d78b | 1164 | const struct mips_regnum *regs = mips_regnum (gdbarch); |
5792a79b | 1165 | |
858339f2 MR |
1166 | if (self == &mips_linux_n32_rt_sigframe |
1167 | || self == µmips_linux_n32_rt_sigframe) | |
eb195664 | 1168 | sigcontext_base = frame_sp + N32_SIGFRAME_SIGCONTEXT_OFFSET; |
5792a79b | 1169 | else |
eb195664 | 1170 | sigcontext_base = frame_sp + N64_SIGFRAME_SIGCONTEXT_OFFSET; |
295093a4 | 1171 | |
2eb4d78b | 1172 | if (mips_linux_restart_reg_p (gdbarch)) |
822b6570 DJ |
1173 | trad_frame_set_reg_addr (this_cache, |
1174 | (MIPS_RESTART_REGNUM | |
2eb4d78b | 1175 | + gdbarch_num_regs (gdbarch)), |
822b6570 | 1176 | sigcontext_base + N64_SIGCONTEXT_REGS); |
5792a79b DJ |
1177 | |
1178 | for (ireg = 1; ireg < 32; ireg++) | |
295093a4 | 1179 | trad_frame_set_reg_addr (this_cache, |
7d266584 MR |
1180 | (ireg + MIPS_ZERO_REGNUM |
1181 | + gdbarch_num_regs (gdbarch)), | |
1182 | (sigcontext_base + N64_SIGCONTEXT_REGS | |
1183 | + ireg * N64_SIGCONTEXT_REG_SIZE)); | |
5792a79b DJ |
1184 | |
1185 | for (ireg = 0; ireg < 32; ireg++) | |
f57d151a | 1186 | trad_frame_set_reg_addr (this_cache, |
7d266584 MR |
1187 | ireg + regs->fp0 + gdbarch_num_regs (gdbarch), |
1188 | (sigcontext_base + N64_SIGCONTEXT_FPREGS | |
1189 | + ireg * N64_SIGCONTEXT_REG_SIZE)); | |
5792a79b | 1190 | |
f57d151a | 1191 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1192 | regs->pc + gdbarch_num_regs (gdbarch), |
5792a79b DJ |
1193 | sigcontext_base + N64_SIGCONTEXT_PC); |
1194 | ||
295093a4 | 1195 | trad_frame_set_reg_addr (this_cache, |
7d266584 MR |
1196 | (regs->fp_control_status |
1197 | + gdbarch_num_regs (gdbarch)), | |
5792a79b | 1198 | sigcontext_base + N64_SIGCONTEXT_FPCSR); |
d0e64392 | 1199 | |
f57d151a | 1200 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1201 | regs->hi + gdbarch_num_regs (gdbarch), |
5792a79b | 1202 | sigcontext_base + N64_SIGCONTEXT_HI); |
f57d151a | 1203 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1204 | regs->lo + gdbarch_num_regs (gdbarch), |
5792a79b | 1205 | sigcontext_base + N64_SIGCONTEXT_LO); |
5792a79b | 1206 | |
d0e64392 MR |
1207 | if (regs->dspacc != -1) |
1208 | { | |
1209 | trad_frame_set_reg_addr (this_cache, | |
1210 | regs->dspacc + 0 + gdbarch_num_regs (gdbarch), | |
1211 | sigcontext_base + N64_SIGCONTEXT_HI1); | |
1212 | trad_frame_set_reg_addr (this_cache, | |
1213 | regs->dspacc + 1 + gdbarch_num_regs (gdbarch), | |
1214 | sigcontext_base + N64_SIGCONTEXT_LO1); | |
1215 | trad_frame_set_reg_addr (this_cache, | |
1216 | regs->dspacc + 2 + gdbarch_num_regs (gdbarch), | |
1217 | sigcontext_base + N64_SIGCONTEXT_HI2); | |
1218 | trad_frame_set_reg_addr (this_cache, | |
1219 | regs->dspacc + 3 + gdbarch_num_regs (gdbarch), | |
1220 | sigcontext_base + N64_SIGCONTEXT_LO2); | |
1221 | trad_frame_set_reg_addr (this_cache, | |
1222 | regs->dspacc + 4 + gdbarch_num_regs (gdbarch), | |
1223 | sigcontext_base + N64_SIGCONTEXT_HI3); | |
1224 | trad_frame_set_reg_addr (this_cache, | |
1225 | regs->dspacc + 5 + gdbarch_num_regs (gdbarch), | |
1226 | sigcontext_base + N64_SIGCONTEXT_LO3); | |
1227 | } | |
1228 | if (regs->dspctl != -1) | |
1229 | trad_frame_set_reg_addr (this_cache, | |
1230 | regs->dspctl + gdbarch_num_regs (gdbarch), | |
1231 | sigcontext_base + N64_SIGCONTEXT_DSPCTL); | |
1232 | ||
5792a79b | 1233 | /* Choice of the bottom of the sigframe is somewhat arbitrary. */ |
eb195664 | 1234 | trad_frame_set_id (this_cache, frame_id_build (frame_sp, func)); |
5792a79b DJ |
1235 | } |
1236 | ||
858339f2 MR |
1237 | /* Implement struct tramp_frame's "validate" method for standard MIPS code. */ |
1238 | ||
1239 | static int | |
1240 | mips_linux_sigframe_validate (const struct tramp_frame *self, | |
1241 | struct frame_info *this_frame, | |
1242 | CORE_ADDR *pc) | |
1243 | { | |
1244 | return mips_pc_is_mips (*pc); | |
1245 | } | |
1246 | ||
1247 | /* Implement struct tramp_frame's "validate" method for microMIPS code. */ | |
1248 | ||
1249 | static int | |
1250 | micromips_linux_sigframe_validate (const struct tramp_frame *self, | |
1251 | struct frame_info *this_frame, | |
1252 | CORE_ADDR *pc) | |
1253 | { | |
3e29f34a MR |
1254 | if (mips_pc_is_micromips (get_frame_arch (this_frame), *pc)) |
1255 | { | |
1256 | *pc = mips_unmake_compact_addr (*pc); | |
1257 | return 1; | |
1258 | } | |
1259 | else | |
1260 | return 0; | |
858339f2 MR |
1261 | } |
1262 | ||
5a439849 MR |
1263 | /* Implement the "write_pc" gdbarch method. */ |
1264 | ||
822b6570 | 1265 | static void |
61a1198a | 1266 | mips_linux_write_pc (struct regcache *regcache, CORE_ADDR pc) |
822b6570 | 1267 | { |
ac7936df | 1268 | struct gdbarch *gdbarch = regcache->arch (); |
5a439849 MR |
1269 | |
1270 | mips_write_pc (regcache, pc); | |
822b6570 DJ |
1271 | |
1272 | /* Clear the syscall restart flag. */ | |
2eb4d78b | 1273 | if (mips_linux_restart_reg_p (gdbarch)) |
61a1198a | 1274 | regcache_cooked_write_unsigned (regcache, MIPS_RESTART_REGNUM, 0); |
822b6570 DJ |
1275 | } |
1276 | ||
1277 | /* Return 1 if MIPS_RESTART_REGNUM is usable. */ | |
1278 | ||
1279 | int | |
1280 | mips_linux_restart_reg_p (struct gdbarch *gdbarch) | |
1281 | { | |
1282 | /* If we do not have a target description with registers, then | |
1283 | MIPS_RESTART_REGNUM will not be included in the register set. */ | |
1284 | if (!tdesc_has_registers (gdbarch_target_desc (gdbarch))) | |
1285 | return 0; | |
1286 | ||
1287 | /* If we do, then MIPS_RESTART_REGNUM is safe to check; it will | |
1288 | either be GPR-sized or missing. */ | |
1289 | return register_size (gdbarch, MIPS_RESTART_REGNUM) > 0; | |
1290 | } | |
9f62d0e2 | 1291 | |
e38d4e1a DJ |
1292 | /* When FRAME is at a syscall instruction, return the PC of the next |
1293 | instruction to be executed. */ | |
1294 | ||
63807e1d | 1295 | static CORE_ADDR |
e38d4e1a DJ |
1296 | mips_linux_syscall_next_pc (struct frame_info *frame) |
1297 | { | |
1298 | CORE_ADDR pc = get_frame_pc (frame); | |
1299 | ULONGEST v0 = get_frame_register_unsigned (frame, MIPS_V0_REGNUM); | |
1300 | ||
1301 | /* If we are about to make a sigreturn syscall, use the unwinder to | |
1302 | decode the signal frame. */ | |
1303 | if (v0 == MIPS_NR_sigreturn | |
1304 | || v0 == MIPS_NR_rt_sigreturn | |
1305 | || v0 == MIPS_NR_N64_rt_sigreturn | |
1306 | || v0 == MIPS_NR_N32_rt_sigreturn) | |
c7ce8faa | 1307 | return frame_unwind_caller_pc (get_current_frame ()); |
e38d4e1a DJ |
1308 | |
1309 | return pc + 4; | |
1310 | } | |
1311 | ||
385203ed DD |
1312 | /* Return the current system call's number present in the |
1313 | v0 register. When the function fails, it returns -1. */ | |
1314 | ||
1315 | static LONGEST | |
1316 | mips_linux_get_syscall_number (struct gdbarch *gdbarch, | |
00431a78 | 1317 | thread_info *thread) |
385203ed | 1318 | { |
00431a78 | 1319 | struct regcache *regcache = get_thread_regcache (thread); |
385203ed DD |
1320 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1321 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1322 | int regsize = register_size (gdbarch, MIPS_V0_REGNUM); | |
1323 | /* The content of a register */ | |
1324 | gdb_byte buf[8]; | |
1325 | /* The result */ | |
1326 | LONGEST ret; | |
1327 | ||
1328 | /* Make sure we're in a known ABI */ | |
1329 | gdb_assert (tdep->mips_abi == MIPS_ABI_O32 | |
1330 | || tdep->mips_abi == MIPS_ABI_N32 | |
1331 | || tdep->mips_abi == MIPS_ABI_N64); | |
1332 | ||
1333 | gdb_assert (regsize <= sizeof (buf)); | |
1334 | ||
1335 | /* Getting the system call number from the register. | |
1336 | syscall number is in v0 or $2. */ | |
dca08e1f | 1337 | regcache->cooked_read (MIPS_V0_REGNUM, buf); |
385203ed DD |
1338 | |
1339 | ret = extract_signed_integer (buf, regsize, byte_order); | |
1340 | ||
1341 | return ret; | |
1342 | } | |
1343 | ||
eb14d406 SDJ |
1344 | /* Implementation of `gdbarch_gdb_signal_to_target', as defined in |
1345 | gdbarch.h. */ | |
1346 | ||
1347 | static int | |
1348 | mips_gdb_signal_to_target (struct gdbarch *gdbarch, | |
1349 | enum gdb_signal signal) | |
1350 | { | |
1351 | switch (signal) | |
1352 | { | |
1353 | case GDB_SIGNAL_EMT: | |
1354 | return MIPS_LINUX_SIGEMT; | |
1355 | ||
1356 | case GDB_SIGNAL_BUS: | |
1357 | return MIPS_LINUX_SIGBUS; | |
1358 | ||
1359 | case GDB_SIGNAL_SYS: | |
1360 | return MIPS_LINUX_SIGSYS; | |
1361 | ||
1362 | case GDB_SIGNAL_USR1: | |
1363 | return MIPS_LINUX_SIGUSR1; | |
1364 | ||
1365 | case GDB_SIGNAL_USR2: | |
1366 | return MIPS_LINUX_SIGUSR2; | |
1367 | ||
1368 | case GDB_SIGNAL_CHLD: | |
1369 | return MIPS_LINUX_SIGCHLD; | |
1370 | ||
1371 | case GDB_SIGNAL_PWR: | |
1372 | return MIPS_LINUX_SIGPWR; | |
1373 | ||
1374 | case GDB_SIGNAL_WINCH: | |
1375 | return MIPS_LINUX_SIGWINCH; | |
1376 | ||
1377 | case GDB_SIGNAL_URG: | |
1378 | return MIPS_LINUX_SIGURG; | |
1379 | ||
1380 | case GDB_SIGNAL_IO: | |
1381 | return MIPS_LINUX_SIGIO; | |
1382 | ||
1383 | case GDB_SIGNAL_POLL: | |
1384 | return MIPS_LINUX_SIGPOLL; | |
1385 | ||
1386 | case GDB_SIGNAL_STOP: | |
1387 | return MIPS_LINUX_SIGSTOP; | |
1388 | ||
1389 | case GDB_SIGNAL_TSTP: | |
1390 | return MIPS_LINUX_SIGTSTP; | |
1391 | ||
1392 | case GDB_SIGNAL_CONT: | |
1393 | return MIPS_LINUX_SIGCONT; | |
1394 | ||
1395 | case GDB_SIGNAL_TTIN: | |
1396 | return MIPS_LINUX_SIGTTIN; | |
1397 | ||
1398 | case GDB_SIGNAL_TTOU: | |
1399 | return MIPS_LINUX_SIGTTOU; | |
1400 | ||
1401 | case GDB_SIGNAL_VTALRM: | |
1402 | return MIPS_LINUX_SIGVTALRM; | |
1403 | ||
1404 | case GDB_SIGNAL_PROF: | |
1405 | return MIPS_LINUX_SIGPROF; | |
1406 | ||
1407 | case GDB_SIGNAL_XCPU: | |
1408 | return MIPS_LINUX_SIGXCPU; | |
1409 | ||
1410 | case GDB_SIGNAL_XFSZ: | |
1411 | return MIPS_LINUX_SIGXFSZ; | |
1412 | ||
1413 | /* GDB_SIGNAL_REALTIME_32 is not continuous in <gdb/signals.def>, | |
1414 | therefore we have to handle it here. */ | |
1415 | case GDB_SIGNAL_REALTIME_32: | |
1416 | return MIPS_LINUX_SIGRTMIN; | |
1417 | } | |
1418 | ||
1419 | if (signal >= GDB_SIGNAL_REALTIME_33 | |
1420 | && signal <= GDB_SIGNAL_REALTIME_63) | |
1421 | { | |
1422 | int offset = signal - GDB_SIGNAL_REALTIME_33; | |
1423 | ||
1424 | return MIPS_LINUX_SIGRTMIN + 1 + offset; | |
1425 | } | |
1426 | else if (signal >= GDB_SIGNAL_REALTIME_64 | |
1427 | && signal <= GDB_SIGNAL_REALTIME_127) | |
1428 | { | |
1429 | int offset = signal - GDB_SIGNAL_REALTIME_64; | |
1430 | ||
1431 | return MIPS_LINUX_SIGRT64 + offset; | |
1432 | } | |
1433 | ||
1434 | return linux_gdb_signal_to_target (gdbarch, signal); | |
1435 | } | |
1436 | ||
7d266584 | 1437 | /* Translate signals based on MIPS signal values. |
268a13a5 | 1438 | Adapted from gdb/gdbsupport/signals.c. */ |
232b8704 ME |
1439 | |
1440 | static enum gdb_signal | |
eb14d406 | 1441 | mips_gdb_signal_from_target (struct gdbarch *gdbarch, int signal) |
232b8704 | 1442 | { |
eb14d406 | 1443 | switch (signal) |
232b8704 | 1444 | { |
eb14d406 | 1445 | case MIPS_LINUX_SIGEMT: |
232b8704 | 1446 | return GDB_SIGNAL_EMT; |
eb14d406 SDJ |
1447 | |
1448 | case MIPS_LINUX_SIGBUS: | |
232b8704 | 1449 | return GDB_SIGNAL_BUS; |
eb14d406 SDJ |
1450 | |
1451 | case MIPS_LINUX_SIGSYS: | |
232b8704 | 1452 | return GDB_SIGNAL_SYS; |
eb14d406 SDJ |
1453 | |
1454 | case MIPS_LINUX_SIGUSR1: | |
232b8704 | 1455 | return GDB_SIGNAL_USR1; |
eb14d406 SDJ |
1456 | |
1457 | case MIPS_LINUX_SIGUSR2: | |
232b8704 | 1458 | return GDB_SIGNAL_USR2; |
eb14d406 SDJ |
1459 | |
1460 | case MIPS_LINUX_SIGCHLD: | |
232b8704 | 1461 | return GDB_SIGNAL_CHLD; |
eb14d406 SDJ |
1462 | |
1463 | case MIPS_LINUX_SIGPWR: | |
232b8704 | 1464 | return GDB_SIGNAL_PWR; |
eb14d406 SDJ |
1465 | |
1466 | case MIPS_LINUX_SIGWINCH: | |
232b8704 | 1467 | return GDB_SIGNAL_WINCH; |
eb14d406 SDJ |
1468 | |
1469 | case MIPS_LINUX_SIGURG: | |
232b8704 | 1470 | return GDB_SIGNAL_URG; |
eb14d406 SDJ |
1471 | |
1472 | /* No way to differentiate between SIGIO and SIGPOLL. | |
1473 | Therefore, we just handle the first one. */ | |
1474 | case MIPS_LINUX_SIGIO: | |
1475 | return GDB_SIGNAL_IO; | |
1476 | ||
1477 | case MIPS_LINUX_SIGSTOP: | |
232b8704 | 1478 | return GDB_SIGNAL_STOP; |
eb14d406 SDJ |
1479 | |
1480 | case MIPS_LINUX_SIGTSTP: | |
232b8704 | 1481 | return GDB_SIGNAL_TSTP; |
eb14d406 SDJ |
1482 | |
1483 | case MIPS_LINUX_SIGCONT: | |
232b8704 | 1484 | return GDB_SIGNAL_CONT; |
eb14d406 SDJ |
1485 | |
1486 | case MIPS_LINUX_SIGTTIN: | |
232b8704 | 1487 | return GDB_SIGNAL_TTIN; |
eb14d406 SDJ |
1488 | |
1489 | case MIPS_LINUX_SIGTTOU: | |
232b8704 | 1490 | return GDB_SIGNAL_TTOU; |
eb14d406 SDJ |
1491 | |
1492 | case MIPS_LINUX_SIGVTALRM: | |
232b8704 | 1493 | return GDB_SIGNAL_VTALRM; |
eb14d406 SDJ |
1494 | |
1495 | case MIPS_LINUX_SIGPROF: | |
232b8704 | 1496 | return GDB_SIGNAL_PROF; |
eb14d406 SDJ |
1497 | |
1498 | case MIPS_LINUX_SIGXCPU: | |
232b8704 | 1499 | return GDB_SIGNAL_XCPU; |
eb14d406 SDJ |
1500 | |
1501 | case MIPS_LINUX_SIGXFSZ: | |
232b8704 | 1502 | return GDB_SIGNAL_XFSZ; |
eb14d406 | 1503 | } |
232b8704 | 1504 | |
eb14d406 | 1505 | if (signal >= MIPS_LINUX_SIGRTMIN && signal <= MIPS_LINUX_SIGRTMAX) |
232b8704 ME |
1506 | { |
1507 | /* GDB_SIGNAL_REALTIME values are not contiguous, map parts of | |
1508 | the MIPS block to the respective GDB_SIGNAL_REALTIME blocks. */ | |
eb14d406 SDJ |
1509 | int offset = signal - MIPS_LINUX_SIGRTMIN; |
1510 | ||
1511 | if (offset == 0) | |
232b8704 | 1512 | return GDB_SIGNAL_REALTIME_32; |
eb14d406 SDJ |
1513 | else if (offset < 32) |
1514 | return (enum gdb_signal) (offset - 1 | |
1515 | + (int) GDB_SIGNAL_REALTIME_33); | |
232b8704 | 1516 | else |
eb14d406 SDJ |
1517 | return (enum gdb_signal) (offset - 32 |
1518 | + (int) GDB_SIGNAL_REALTIME_64); | |
232b8704 ME |
1519 | } |
1520 | ||
eb14d406 | 1521 | return linux_gdb_signal_from_target (gdbarch, signal); |
232b8704 ME |
1522 | } |
1523 | ||
5792a79b DJ |
1524 | /* Initialize one of the GNU/Linux OS ABIs. */ |
1525 | ||
19ed69dd | 1526 | static void |
295093a4 MS |
1527 | mips_linux_init_abi (struct gdbarch_info info, |
1528 | struct gdbarch *gdbarch) | |
19ed69dd | 1529 | { |
96f026fc KB |
1530 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1531 | enum mips_abi abi = mips_abi (gdbarch); | |
0dba2a6c | 1532 | struct tdesc_arch_data *tdesc_data = info.tdesc_data; |
96f026fc | 1533 | |
a5ee0f0c PA |
1534 | linux_init_abi (info, gdbarch); |
1535 | ||
385203ed DD |
1536 | /* Get the syscall number from the arch's register. */ |
1537 | set_gdbarch_get_syscall_number (gdbarch, mips_linux_get_syscall_number); | |
1538 | ||
96f026fc KB |
1539 | switch (abi) |
1540 | { | |
1541 | case MIPS_ABI_O32: | |
1542 | set_gdbarch_get_longjmp_target (gdbarch, | |
7d266584 | 1543 | mips_linux_get_longjmp_target); |
96f026fc | 1544 | set_solib_svr4_fetch_link_map_offsets |
76a9d10f | 1545 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); |
858339f2 MR |
1546 | tramp_frame_prepend_unwinder (gdbarch, µmips_linux_o32_sigframe); |
1547 | tramp_frame_prepend_unwinder (gdbarch, | |
1548 | µmips_linux_o32_rt_sigframe); | |
fb2be677 AC |
1549 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_sigframe); |
1550 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_rt_sigframe); | |
458c8db8 | 1551 | set_xml_syscall_file_name (gdbarch, "syscalls/mips-o32-linux.xml"); |
96f026fc KB |
1552 | break; |
1553 | case MIPS_ABI_N32: | |
1554 | set_gdbarch_get_longjmp_target (gdbarch, | |
7d266584 | 1555 | mips_linux_get_longjmp_target); |
96f026fc | 1556 | set_solib_svr4_fetch_link_map_offsets |
76a9d10f | 1557 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); |
d05f6826 DJ |
1558 | set_gdbarch_long_double_bit (gdbarch, 128); |
1559 | /* These floatformats should probably be renamed. MIPS uses | |
1560 | the same 128-bit IEEE floating point format that IA-64 uses, | |
1561 | except that the quiet/signalling NaN bit is reversed (GDB | |
1562 | does not distinguish between quiet and signalling NaNs). */ | |
8da61cc4 | 1563 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); |
858339f2 MR |
1564 | tramp_frame_prepend_unwinder (gdbarch, |
1565 | µmips_linux_n32_rt_sigframe); | |
fb2be677 | 1566 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n32_rt_sigframe); |
458c8db8 | 1567 | set_xml_syscall_file_name (gdbarch, "syscalls/mips-n32-linux.xml"); |
96f026fc KB |
1568 | break; |
1569 | case MIPS_ABI_N64: | |
1570 | set_gdbarch_get_longjmp_target (gdbarch, | |
7d266584 | 1571 | mips64_linux_get_longjmp_target); |
96f026fc | 1572 | set_solib_svr4_fetch_link_map_offsets |
76a9d10f | 1573 | (gdbarch, svr4_lp64_fetch_link_map_offsets); |
d05f6826 DJ |
1574 | set_gdbarch_long_double_bit (gdbarch, 128); |
1575 | /* These floatformats should probably be renamed. MIPS uses | |
1576 | the same 128-bit IEEE floating point format that IA-64 uses, | |
1577 | except that the quiet/signalling NaN bit is reversed (GDB | |
1578 | does not distinguish between quiet and signalling NaNs). */ | |
8da61cc4 | 1579 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); |
858339f2 MR |
1580 | tramp_frame_prepend_unwinder (gdbarch, |
1581 | µmips_linux_n64_rt_sigframe); | |
fb2be677 | 1582 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n64_rt_sigframe); |
458c8db8 | 1583 | set_xml_syscall_file_name (gdbarch, "syscalls/mips-n64-linux.xml"); |
96f026fc KB |
1584 | break; |
1585 | default: | |
96f026fc KB |
1586 | break; |
1587 | } | |
6de918a6 DJ |
1588 | |
1589 | set_gdbarch_skip_solib_resolver (gdbarch, mips_linux_skip_resolver); | |
1590 | ||
0d0266c6 | 1591 | set_gdbarch_software_single_step (gdbarch, mips_software_single_step); |
b2756930 KB |
1592 | |
1593 | /* Enable TLS support. */ | |
1594 | set_gdbarch_fetch_tls_load_module_address (gdbarch, | |
7d266584 | 1595 | svr4_fetch_objfile_link_map); |
7d522c90 DJ |
1596 | |
1597 | /* Initialize this lazily, to avoid an initialization order | |
1598 | dependency on solib-svr4.c's _initialize routine. */ | |
1599 | if (mips_svr4_so_ops.in_dynsym_resolve_code == NULL) | |
1600 | { | |
1601 | mips_svr4_so_ops = svr4_so_ops; | |
1602 | mips_svr4_so_ops.in_dynsym_resolve_code | |
1603 | = mips_linux_in_dynsym_resolve_code; | |
1604 | } | |
1605 | set_solib_ops (gdbarch, &mips_svr4_so_ops); | |
822b6570 DJ |
1606 | |
1607 | set_gdbarch_write_pc (gdbarch, mips_linux_write_pc); | |
1608 | ||
4eb0ad19 DJ |
1609 | set_gdbarch_core_read_description (gdbarch, |
1610 | mips_linux_core_read_description); | |
1611 | ||
d4036235 AA |
1612 | set_gdbarch_iterate_over_regset_sections |
1613 | (gdbarch, mips_linux_iterate_over_regset_sections); | |
50e8a0d5 | 1614 | |
232b8704 ME |
1615 | set_gdbarch_gdb_signal_from_target (gdbarch, |
1616 | mips_gdb_signal_from_target); | |
1617 | ||
eb14d406 SDJ |
1618 | set_gdbarch_gdb_signal_to_target (gdbarch, |
1619 | mips_gdb_signal_to_target); | |
1620 | ||
e38d4e1a DJ |
1621 | tdep->syscall_next_pc = mips_linux_syscall_next_pc; |
1622 | ||
822b6570 DJ |
1623 | if (tdesc_data) |
1624 | { | |
1625 | const struct tdesc_feature *feature; | |
1626 | ||
1627 | /* If we have target-described registers, then we can safely | |
1628 | reserve a number for MIPS_RESTART_REGNUM (whether it is | |
1629 | described or not). */ | |
1630 | gdb_assert (gdbarch_num_regs (gdbarch) <= MIPS_RESTART_REGNUM); | |
1631 | set_gdbarch_num_regs (gdbarch, MIPS_RESTART_REGNUM + 1); | |
cf233303 | 1632 | set_gdbarch_num_pseudo_regs (gdbarch, MIPS_RESTART_REGNUM + 1); |
822b6570 DJ |
1633 | |
1634 | /* If it's present, then assign it to the reserved number. */ | |
1635 | feature = tdesc_find_feature (info.target_desc, | |
1636 | "org.gnu.gdb.mips.linux"); | |
1637 | if (feature != NULL) | |
1638 | tdesc_numbered_register (feature, tdesc_data, MIPS_RESTART_REGNUM, | |
1639 | "restart"); | |
1640 | } | |
19ed69dd KB |
1641 | } |
1642 | ||
6c265988 | 1643 | void _initialize_mips_linux_tdep (); |
2aa830e4 | 1644 | void |
6c265988 | 1645 | _initialize_mips_linux_tdep () |
2aa830e4 | 1646 | { |
96f026fc KB |
1647 | const struct bfd_arch_info *arch_info; |
1648 | ||
96f026fc KB |
1649 | for (arch_info = bfd_lookup_arch (bfd_arch_mips, 0); |
1650 | arch_info != NULL; | |
1651 | arch_info = arch_info->next) | |
1652 | { | |
295093a4 MS |
1653 | gdbarch_register_osabi (bfd_arch_mips, arch_info->mach, |
1654 | GDB_OSABI_LINUX, | |
96f026fc KB |
1655 | mips_linux_init_abi); |
1656 | } | |
032bb6ea YQ |
1657 | |
1658 | /* Initialize the standard target descriptions. */ | |
1659 | initialize_tdesc_mips_linux (); | |
1660 | initialize_tdesc_mips_dsp_linux (); | |
1661 | initialize_tdesc_mips64_linux (); | |
1662 | initialize_tdesc_mips64_dsp_linux (); | |
2aa830e4 | 1663 | } |