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75c9abc6 | 1 | /* Target-dependent code for GNU/Linux on MIPS processors. |
a094c6fb | 2 | |
ecd75fc8 | 3 | Copyright (C) 2001-2014 Free Software Foundation, Inc. |
2aa830e4 DJ |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
2aa830e4 DJ |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
2aa830e4 DJ |
19 | |
20 | #include "defs.h" | |
21 | #include "gdbcore.h" | |
22 | #include "target.h" | |
23 | #include "solib-svr4.h" | |
19ed69dd | 24 | #include "osabi.h" |
96f026fc | 25 | #include "mips-tdep.h" |
6de918a6 | 26 | #include "frame.h" |
2fdf551c | 27 | #include "regcache.h" |
5792a79b DJ |
28 | #include "trad-frame.h" |
29 | #include "tramp-frame.h" | |
e6bb342a | 30 | #include "gdbtypes.h" |
3e5d3a5a | 31 | #include "objfiles.h" |
5ea03926 | 32 | #include "solib.h" |
7d522c90 | 33 | #include "solist.h" |
982e9687 | 34 | #include "symtab.h" |
822b6570 | 35 | #include "target-descriptions.h" |
50e8a0d5 | 36 | #include "regset.h" |
d37eb719 | 37 | #include "mips-linux-tdep.h" |
db5f024e | 38 | #include "glibc-tdep.h" |
a5ee0f0c | 39 | #include "linux-tdep.h" |
385203ed | 40 | #include "xml-syscall.h" |
232b8704 | 41 | #include "gdb_signals.h" |
2aa830e4 | 42 | |
7d522c90 DJ |
43 | static struct target_so_ops mips_svr4_so_ops; |
44 | ||
eb14d406 SDJ |
45 | /* This enum represents the signals' numbers on the MIPS |
46 | architecture. It just contains the signal definitions which are | |
47 | different from the generic implementation. | |
48 | ||
49 | It is derived from the file <arch/mips/include/uapi/asm/signal.h>, | |
50 | from the Linux kernel tree. */ | |
51 | ||
52 | enum | |
53 | { | |
54 | MIPS_LINUX_SIGEMT = 7, | |
55 | MIPS_LINUX_SIGBUS = 10, | |
56 | MIPS_LINUX_SIGSYS = 12, | |
57 | MIPS_LINUX_SIGUSR1 = 16, | |
58 | MIPS_LINUX_SIGUSR2 = 17, | |
59 | MIPS_LINUX_SIGCHLD = 18, | |
60 | MIPS_LINUX_SIGCLD = MIPS_LINUX_SIGCHLD, | |
61 | MIPS_LINUX_SIGPWR = 19, | |
62 | MIPS_LINUX_SIGWINCH = 20, | |
63 | MIPS_LINUX_SIGURG = 21, | |
64 | MIPS_LINUX_SIGIO = 22, | |
65 | MIPS_LINUX_SIGPOLL = MIPS_LINUX_SIGIO, | |
66 | MIPS_LINUX_SIGSTOP = 23, | |
67 | MIPS_LINUX_SIGTSTP = 24, | |
68 | MIPS_LINUX_SIGCONT = 25, | |
69 | MIPS_LINUX_SIGTTIN = 26, | |
70 | MIPS_LINUX_SIGTTOU = 27, | |
71 | MIPS_LINUX_SIGVTALRM = 28, | |
72 | MIPS_LINUX_SIGPROF = 29, | |
73 | MIPS_LINUX_SIGXCPU = 30, | |
74 | MIPS_LINUX_SIGXFSZ = 31, | |
75 | ||
76 | MIPS_LINUX_SIGRTMIN = 32, | |
77 | MIPS_LINUX_SIGRT64 = 64, | |
78 | MIPS_LINUX_SIGRTMAX = 127, | |
79 | }; | |
80 | ||
2aa830e4 | 81 | /* Figure out where the longjmp will land. |
295093a4 MS |
82 | We expect the first arg to be a pointer to the jmp_buf structure |
83 | from which we extract the pc (MIPS_LINUX_JB_PC) that we will land | |
84 | at. The pc is copied into PC. This routine returns 1 on | |
85 | success. */ | |
2aa830e4 | 86 | |
19ed69dd KB |
87 | #define MIPS_LINUX_JB_ELEMENT_SIZE 4 |
88 | #define MIPS_LINUX_JB_PC 0 | |
89 | ||
90 | static int | |
60ade65d | 91 | mips_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
2aa830e4 DJ |
92 | { |
93 | CORE_ADDR jb_addr; | |
2eb4d78b | 94 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 95 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
e362b510 | 96 | gdb_byte buf[gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT]; |
2aa830e4 | 97 | |
60ade65d | 98 | jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM); |
2aa830e4 | 99 | |
7d266584 MR |
100 | if (target_read_memory ((jb_addr |
101 | + MIPS_LINUX_JB_PC * MIPS_LINUX_JB_ELEMENT_SIZE), | |
2eb4d78b | 102 | buf, gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT)) |
2aa830e4 DJ |
103 | return 0; |
104 | ||
819844ad | 105 | *pc = extract_unsigned_integer (buf, |
e17a4113 UW |
106 | gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT, |
107 | byte_order); | |
2aa830e4 DJ |
108 | |
109 | return 1; | |
110 | } | |
111 | ||
4246e332 | 112 | /* Transform the bits comprising a 32-bit register to the right size |
23a6d369 AC |
113 | for regcache_raw_supply(). This is needed when mips_isa_regsize() |
114 | is 8. */ | |
96f026fc KB |
115 | |
116 | static void | |
28f5035f | 117 | supply_32bit_reg (struct regcache *regcache, int regnum, const void *addr) |
96f026fc | 118 | { |
e17a4113 UW |
119 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
120 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
d37eb719 | 121 | gdb_byte buf[MAX_REGISTER_SIZE]; |
e17a4113 | 122 | store_signed_integer (buf, register_size (gdbarch, regnum), byte_order, |
7d266584 | 123 | extract_signed_integer (addr, 4, byte_order)); |
28f5035f | 124 | regcache_raw_supply (regcache, regnum, buf); |
96f026fc KB |
125 | } |
126 | ||
2aa830e4 DJ |
127 | /* Unpack an elf_gregset_t into GDB's register cache. */ |
128 | ||
d37eb719 | 129 | void |
28f5035f UW |
130 | mips_supply_gregset (struct regcache *regcache, |
131 | const mips_elf_gregset_t *gregsetp) | |
2aa830e4 DJ |
132 | { |
133 | int regi; | |
28f5035f | 134 | const mips_elf_greg_t *regp = *gregsetp; |
d9d9c31f | 135 | char zerobuf[MAX_REGISTER_SIZE]; |
2eb4d78b | 136 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
bf072999 | 137 | |
d9d9c31f | 138 | memset (zerobuf, 0, MAX_REGISTER_SIZE); |
2aa830e4 | 139 | |
822b6570 | 140 | for (regi = EF_REG0 + 1; regi <= EF_REG31; regi++) |
28f5035f | 141 | supply_32bit_reg (regcache, regi - EF_REG0, regp + regi); |
2aa830e4 | 142 | |
2eb4d78b | 143 | if (mips_linux_restart_reg_p (gdbarch)) |
822b6570 DJ |
144 | supply_32bit_reg (regcache, MIPS_RESTART_REGNUM, regp + EF_REG0); |
145 | ||
2eb4d78b UW |
146 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->lo, regp + EF_LO); |
147 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->hi, regp + EF_HI); | |
56cea623 | 148 | |
2eb4d78b | 149 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->pc, |
28f5035f | 150 | regp + EF_CP0_EPC); |
2eb4d78b | 151 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->badvaddr, |
28f5035f UW |
152 | regp + EF_CP0_BADVADDR); |
153 | supply_32bit_reg (regcache, MIPS_PS_REGNUM, regp + EF_CP0_STATUS); | |
2eb4d78b | 154 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->cause, |
28f5035f | 155 | regp + EF_CP0_CAUSE); |
2aa830e4 | 156 | |
1faeff08 | 157 | /* Fill the inaccessible zero register with zero. */ |
822b6570 | 158 | regcache_raw_supply (regcache, MIPS_ZERO_REGNUM, zerobuf); |
2aa830e4 DJ |
159 | } |
160 | ||
50e8a0d5 HZ |
161 | static void |
162 | mips_supply_gregset_wrapper (const struct regset *regset, | |
7d266584 MR |
163 | struct regcache *regcache, |
164 | int regnum, const void *gregs, size_t len) | |
50e8a0d5 HZ |
165 | { |
166 | gdb_assert (len == sizeof (mips_elf_gregset_t)); | |
167 | ||
168 | mips_supply_gregset (regcache, (const mips_elf_gregset_t *)gregs); | |
169 | } | |
170 | ||
2aa830e4 DJ |
171 | /* Pack our registers (or one register) into an elf_gregset_t. */ |
172 | ||
d37eb719 | 173 | void |
28f5035f UW |
174 | mips_fill_gregset (const struct regcache *regcache, |
175 | mips_elf_gregset_t *gregsetp, int regno) | |
2aa830e4 | 176 | { |
2eb4d78b | 177 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
2aa830e4 | 178 | int regaddr, regi; |
d37eb719 | 179 | mips_elf_greg_t *regp = *gregsetp; |
96f026fc | 180 | void *dst; |
2aa830e4 DJ |
181 | |
182 | if (regno == -1) | |
183 | { | |
d37eb719 | 184 | memset (regp, 0, sizeof (mips_elf_gregset_t)); |
822b6570 | 185 | for (regi = 1; regi < 32; regi++) |
28f5035f | 186 | mips_fill_gregset (regcache, gregsetp, regi); |
2eb4d78b UW |
187 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->lo); |
188 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->hi); | |
189 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->pc); | |
190 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->badvaddr); | |
28f5035f | 191 | mips_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM); |
2eb4d78b | 192 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->cause); |
822b6570 | 193 | mips_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM); |
2aa830e4 DJ |
194 | return; |
195 | } | |
196 | ||
822b6570 | 197 | if (regno > 0 && regno < 32) |
2aa830e4 | 198 | { |
2aa830e4 | 199 | dst = regp + regno + EF_REG0; |
28f5035f | 200 | regcache_raw_collect (regcache, regno, dst); |
2aa830e4 DJ |
201 | return; |
202 | } | |
203 | ||
2eb4d78b UW |
204 | if (regno == mips_regnum (gdbarch)->lo) |
205 | regaddr = EF_LO; | |
206 | else if (regno == mips_regnum (gdbarch)->hi) | |
56cea623 | 207 | regaddr = EF_HI; |
2eb4d78b | 208 | else if (regno == mips_regnum (gdbarch)->pc) |
56cea623 | 209 | regaddr = EF_CP0_EPC; |
2eb4d78b | 210 | else if (regno == mips_regnum (gdbarch)->badvaddr) |
56cea623 | 211 | regaddr = EF_CP0_BADVADDR; |
24e05951 | 212 | else if (regno == MIPS_PS_REGNUM) |
56cea623 | 213 | regaddr = EF_CP0_STATUS; |
2eb4d78b | 214 | else if (regno == mips_regnum (gdbarch)->cause) |
56cea623 | 215 | regaddr = EF_CP0_CAUSE; |
2eb4d78b | 216 | else if (mips_linux_restart_reg_p (gdbarch) |
822b6570 DJ |
217 | && regno == MIPS_RESTART_REGNUM) |
218 | regaddr = EF_REG0; | |
56cea623 AC |
219 | else |
220 | regaddr = -1; | |
2aa830e4 DJ |
221 | |
222 | if (regaddr != -1) | |
223 | { | |
2aa830e4 | 224 | dst = regp + regaddr; |
28f5035f | 225 | regcache_raw_collect (regcache, regno, dst); |
2aa830e4 DJ |
226 | } |
227 | } | |
228 | ||
50e8a0d5 HZ |
229 | static void |
230 | mips_fill_gregset_wrapper (const struct regset *regset, | |
231 | const struct regcache *regcache, | |
232 | int regnum, void *gregs, size_t len) | |
233 | { | |
234 | gdb_assert (len == sizeof (mips_elf_gregset_t)); | |
235 | ||
236 | mips_fill_gregset (regcache, (mips_elf_gregset_t *)gregs, regnum); | |
237 | } | |
238 | ||
2aa830e4 DJ |
239 | /* Likewise, unpack an elf_fpregset_t. */ |
240 | ||
d37eb719 | 241 | void |
28f5035f UW |
242 | mips_supply_fpregset (struct regcache *regcache, |
243 | const mips_elf_fpregset_t *fpregsetp) | |
2aa830e4 | 244 | { |
2eb4d78b | 245 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
52f0bd74 | 246 | int regi; |
d9d9c31f | 247 | char zerobuf[MAX_REGISTER_SIZE]; |
bf072999 | 248 | |
d9d9c31f | 249 | memset (zerobuf, 0, MAX_REGISTER_SIZE); |
2aa830e4 DJ |
250 | |
251 | for (regi = 0; regi < 32; regi++) | |
3e8c568d | 252 | regcache_raw_supply (regcache, |
2eb4d78b | 253 | gdbarch_fp0_regnum (gdbarch) + regi, |
3e8c568d | 254 | *fpregsetp + regi); |
2aa830e4 | 255 | |
28f5035f | 256 | regcache_raw_supply (regcache, |
2eb4d78b | 257 | mips_regnum (gdbarch)->fp_control_status, |
28f5035f | 258 | *fpregsetp + 32); |
2aa830e4 | 259 | |
295093a4 | 260 | /* FIXME: how can we supply FCRIR? The ABI doesn't tell us. */ |
28f5035f | 261 | regcache_raw_supply (regcache, |
2eb4d78b | 262 | mips_regnum (gdbarch)->fp_implementation_revision, |
23a6d369 | 263 | zerobuf); |
2aa830e4 DJ |
264 | } |
265 | ||
50e8a0d5 HZ |
266 | static void |
267 | mips_supply_fpregset_wrapper (const struct regset *regset, | |
7d266584 MR |
268 | struct regcache *regcache, |
269 | int regnum, const void *gregs, size_t len) | |
50e8a0d5 HZ |
270 | { |
271 | gdb_assert (len == sizeof (mips_elf_fpregset_t)); | |
272 | ||
273 | mips_supply_fpregset (regcache, (const mips_elf_fpregset_t *)gregs); | |
274 | } | |
275 | ||
2aa830e4 DJ |
276 | /* Likewise, pack one or all floating point registers into an |
277 | elf_fpregset_t. */ | |
278 | ||
d37eb719 | 279 | void |
28f5035f UW |
280 | mips_fill_fpregset (const struct regcache *regcache, |
281 | mips_elf_fpregset_t *fpregsetp, int regno) | |
2aa830e4 | 282 | { |
2eb4d78b | 283 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
22e048c9 | 284 | char *to; |
2aa830e4 | 285 | |
2eb4d78b UW |
286 | if ((regno >= gdbarch_fp0_regnum (gdbarch)) |
287 | && (regno < gdbarch_fp0_regnum (gdbarch) + 32)) | |
2aa830e4 | 288 | { |
2eb4d78b | 289 | to = (char *) (*fpregsetp + regno - gdbarch_fp0_regnum (gdbarch)); |
28f5035f | 290 | regcache_raw_collect (regcache, regno, to); |
2aa830e4 | 291 | } |
2eb4d78b | 292 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
2aa830e4 | 293 | { |
2aa830e4 | 294 | to = (char *) (*fpregsetp + 32); |
28f5035f | 295 | regcache_raw_collect (regcache, regno, to); |
2aa830e4 DJ |
296 | } |
297 | else if (regno == -1) | |
298 | { | |
299 | int regi; | |
300 | ||
301 | for (regi = 0; regi < 32; regi++) | |
3e8c568d | 302 | mips_fill_fpregset (regcache, fpregsetp, |
2eb4d78b | 303 | gdbarch_fp0_regnum (gdbarch) + regi); |
28f5035f | 304 | mips_fill_fpregset (regcache, fpregsetp, |
2eb4d78b | 305 | mips_regnum (gdbarch)->fp_control_status); |
2aa830e4 DJ |
306 | } |
307 | } | |
308 | ||
50e8a0d5 HZ |
309 | static void |
310 | mips_fill_fpregset_wrapper (const struct regset *regset, | |
311 | const struct regcache *regcache, | |
312 | int regnum, void *gregs, size_t len) | |
313 | { | |
314 | gdb_assert (len == sizeof (mips_elf_fpregset_t)); | |
315 | ||
316 | mips_fill_fpregset (regcache, (mips_elf_fpregset_t *)gregs, regnum); | |
317 | } | |
318 | ||
96f026fc KB |
319 | /* Support for 64-bit ABIs. */ |
320 | ||
96f026fc | 321 | /* Figure out where the longjmp will land. |
295093a4 MS |
322 | We expect the first arg to be a pointer to the jmp_buf structure |
323 | from which we extract the pc (MIPS_LINUX_JB_PC) that we will land | |
324 | at. The pc is copied into PC. This routine returns 1 on | |
325 | success. */ | |
96f026fc KB |
326 | |
327 | /* Details about jmp_buf. */ | |
328 | ||
329 | #define MIPS64_LINUX_JB_PC 0 | |
330 | ||
331 | static int | |
60ade65d | 332 | mips64_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
96f026fc KB |
333 | { |
334 | CORE_ADDR jb_addr; | |
2eb4d78b | 335 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 336 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2eb4d78b UW |
337 | void *buf = alloca (gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT); |
338 | int element_size = gdbarch_ptr_bit (gdbarch) == 32 ? 4 : 8; | |
96f026fc | 339 | |
60ade65d | 340 | jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM); |
96f026fc KB |
341 | |
342 | if (target_read_memory (jb_addr + MIPS64_LINUX_JB_PC * element_size, | |
819844ad | 343 | buf, |
2eb4d78b | 344 | gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT)) |
96f026fc KB |
345 | return 0; |
346 | ||
819844ad | 347 | *pc = extract_unsigned_integer (buf, |
e17a4113 UW |
348 | gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT, |
349 | byte_order); | |
96f026fc KB |
350 | |
351 | return 1; | |
352 | } | |
353 | ||
d37eb719 DJ |
354 | /* Register set support functions. These operate on standard 64-bit |
355 | regsets, but work whether the target is 32-bit or 64-bit. A 32-bit | |
356 | target will still use the 64-bit format for PTRACE_GETREGS. */ | |
357 | ||
358 | /* Supply a 64-bit register. */ | |
96f026fc | 359 | |
63807e1d | 360 | static void |
28f5035f UW |
361 | supply_64bit_reg (struct regcache *regcache, int regnum, |
362 | const gdb_byte *buf) | |
d37eb719 | 363 | { |
2eb4d78b UW |
364 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
365 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG | |
366 | && register_size (gdbarch, regnum) == 4) | |
28f5035f | 367 | regcache_raw_supply (regcache, regnum, buf + 4); |
d37eb719 | 368 | else |
28f5035f | 369 | regcache_raw_supply (regcache, regnum, buf); |
d37eb719 DJ |
370 | } |
371 | ||
372 | /* Unpack a 64-bit elf_gregset_t into GDB's register cache. */ | |
373 | ||
374 | void | |
28f5035f UW |
375 | mips64_supply_gregset (struct regcache *regcache, |
376 | const mips64_elf_gregset_t *gregsetp) | |
96f026fc KB |
377 | { |
378 | int regi; | |
28f5035f | 379 | const mips64_elf_greg_t *regp = *gregsetp; |
d37eb719 | 380 | gdb_byte zerobuf[MAX_REGISTER_SIZE]; |
2eb4d78b | 381 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
96f026fc | 382 | |
d9d9c31f | 383 | memset (zerobuf, 0, MAX_REGISTER_SIZE); |
96f026fc | 384 | |
822b6570 | 385 | for (regi = MIPS64_EF_REG0 + 1; regi <= MIPS64_EF_REG31; regi++) |
28f5035f | 386 | supply_64bit_reg (regcache, regi - MIPS64_EF_REG0, |
7d266584 | 387 | (const gdb_byte *) (regp + regi)); |
28f5035f | 388 | |
2eb4d78b | 389 | if (mips_linux_restart_reg_p (gdbarch)) |
822b6570 | 390 | supply_64bit_reg (regcache, MIPS_RESTART_REGNUM, |
7d266584 | 391 | (const gdb_byte *) (regp + MIPS64_EF_REG0)); |
822b6570 | 392 | |
2eb4d78b | 393 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->lo, |
28f5035f | 394 | (const gdb_byte *) (regp + MIPS64_EF_LO)); |
2eb4d78b | 395 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->hi, |
28f5035f UW |
396 | (const gdb_byte *) (regp + MIPS64_EF_HI)); |
397 | ||
2eb4d78b | 398 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->pc, |
28f5035f | 399 | (const gdb_byte *) (regp + MIPS64_EF_CP0_EPC)); |
2eb4d78b | 400 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->badvaddr, |
28f5035f UW |
401 | (const gdb_byte *) (regp + MIPS64_EF_CP0_BADVADDR)); |
402 | supply_64bit_reg (regcache, MIPS_PS_REGNUM, | |
403 | (const gdb_byte *) (regp + MIPS64_EF_CP0_STATUS)); | |
2eb4d78b | 404 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->cause, |
28f5035f | 405 | (const gdb_byte *) (regp + MIPS64_EF_CP0_CAUSE)); |
96f026fc | 406 | |
1faeff08 | 407 | /* Fill the inaccessible zero register with zero. */ |
822b6570 | 408 | regcache_raw_supply (regcache, MIPS_ZERO_REGNUM, zerobuf); |
96f026fc KB |
409 | } |
410 | ||
50e8a0d5 HZ |
411 | static void |
412 | mips64_supply_gregset_wrapper (const struct regset *regset, | |
7d266584 MR |
413 | struct regcache *regcache, |
414 | int regnum, const void *gregs, size_t len) | |
50e8a0d5 HZ |
415 | { |
416 | gdb_assert (len == sizeof (mips64_elf_gregset_t)); | |
417 | ||
418 | mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *)gregs); | |
419 | } | |
420 | ||
d37eb719 | 421 | /* Pack our registers (or one register) into a 64-bit elf_gregset_t. */ |
96f026fc | 422 | |
d37eb719 | 423 | void |
28f5035f UW |
424 | mips64_fill_gregset (const struct regcache *regcache, |
425 | mips64_elf_gregset_t *gregsetp, int regno) | |
96f026fc | 426 | { |
2eb4d78b | 427 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
e17a4113 | 428 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
96f026fc KB |
429 | int regaddr, regi; |
430 | mips64_elf_greg_t *regp = *gregsetp; | |
2ba93934 | 431 | void *dst; |
96f026fc KB |
432 | |
433 | if (regno == -1) | |
434 | { | |
435 | memset (regp, 0, sizeof (mips64_elf_gregset_t)); | |
822b6570 | 436 | for (regi = 1; regi < 32; regi++) |
7d266584 | 437 | mips64_fill_gregset (regcache, gregsetp, regi); |
2eb4d78b UW |
438 | mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->lo); |
439 | mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->hi); | |
440 | mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->pc); | |
025bb325 MS |
441 | mips64_fill_gregset (regcache, gregsetp, |
442 | mips_regnum (gdbarch)->badvaddr); | |
28f5035f | 443 | mips64_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM); |
2eb4d78b | 444 | mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->cause); |
822b6570 | 445 | mips64_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM); |
96f026fc KB |
446 | return; |
447 | } | |
448 | ||
822b6570 | 449 | if (regno > 0 && regno < 32) |
d37eb719 | 450 | regaddr = regno + MIPS64_EF_REG0; |
2eb4d78b | 451 | else if (regno == mips_regnum (gdbarch)->lo) |
56cea623 | 452 | regaddr = MIPS64_EF_LO; |
2eb4d78b | 453 | else if (regno == mips_regnum (gdbarch)->hi) |
56cea623 | 454 | regaddr = MIPS64_EF_HI; |
2eb4d78b | 455 | else if (regno == mips_regnum (gdbarch)->pc) |
56cea623 | 456 | regaddr = MIPS64_EF_CP0_EPC; |
2eb4d78b | 457 | else if (regno == mips_regnum (gdbarch)->badvaddr) |
56cea623 | 458 | regaddr = MIPS64_EF_CP0_BADVADDR; |
24e05951 | 459 | else if (regno == MIPS_PS_REGNUM) |
56cea623 | 460 | regaddr = MIPS64_EF_CP0_STATUS; |
2eb4d78b | 461 | else if (regno == mips_regnum (gdbarch)->cause) |
56cea623 | 462 | regaddr = MIPS64_EF_CP0_CAUSE; |
2eb4d78b | 463 | else if (mips_linux_restart_reg_p (gdbarch) |
822b6570 DJ |
464 | && regno == MIPS_RESTART_REGNUM) |
465 | regaddr = MIPS64_EF_REG0; | |
56cea623 AC |
466 | else |
467 | regaddr = -1; | |
96f026fc KB |
468 | |
469 | if (regaddr != -1) | |
470 | { | |
d37eb719 DJ |
471 | gdb_byte buf[MAX_REGISTER_SIZE]; |
472 | LONGEST val; | |
473 | ||
28f5035f | 474 | regcache_raw_collect (regcache, regno, buf); |
e17a4113 UW |
475 | val = extract_signed_integer (buf, register_size (gdbarch, regno), |
476 | byte_order); | |
96f026fc | 477 | dst = regp + regaddr; |
e17a4113 | 478 | store_signed_integer (dst, 8, byte_order, val); |
96f026fc KB |
479 | } |
480 | } | |
481 | ||
50e8a0d5 HZ |
482 | static void |
483 | mips64_fill_gregset_wrapper (const struct regset *regset, | |
484 | const struct regcache *regcache, | |
485 | int regnum, void *gregs, size_t len) | |
486 | { | |
487 | gdb_assert (len == sizeof (mips64_elf_gregset_t)); | |
488 | ||
489 | mips64_fill_gregset (regcache, (mips64_elf_gregset_t *)gregs, regnum); | |
490 | } | |
491 | ||
96f026fc KB |
492 | /* Likewise, unpack an elf_fpregset_t. */ |
493 | ||
d37eb719 | 494 | void |
28f5035f UW |
495 | mips64_supply_fpregset (struct regcache *regcache, |
496 | const mips64_elf_fpregset_t *fpregsetp) | |
96f026fc | 497 | { |
2eb4d78b | 498 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
52f0bd74 | 499 | int regi; |
96f026fc | 500 | |
d37eb719 DJ |
501 | /* See mips_linux_o32_sigframe_init for a description of the |
502 | peculiar FP register layout. */ | |
2eb4d78b | 503 | if (register_size (gdbarch, gdbarch_fp0_regnum (gdbarch)) == 4) |
d37eb719 DJ |
504 | for (regi = 0; regi < 32; regi++) |
505 | { | |
7d266584 MR |
506 | const gdb_byte *reg_ptr |
507 | = (const gdb_byte *) (*fpregsetp + (regi & ~1)); | |
2eb4d78b | 508 | if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (regi & 1)) |
d37eb719 | 509 | reg_ptr += 4; |
3e8c568d | 510 | regcache_raw_supply (regcache, |
2eb4d78b | 511 | gdbarch_fp0_regnum (gdbarch) + regi, |
3e8c568d | 512 | reg_ptr); |
d37eb719 DJ |
513 | } |
514 | else | |
515 | for (regi = 0; regi < 32; regi++) | |
3e8c568d | 516 | regcache_raw_supply (regcache, |
2eb4d78b | 517 | gdbarch_fp0_regnum (gdbarch) + regi, |
7d266584 | 518 | (const char *) (*fpregsetp + regi)); |
d37eb719 | 519 | |
2eb4d78b | 520 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->fp_control_status, |
7d266584 | 521 | (const gdb_byte *) (*fpregsetp + 32)); |
d37eb719 DJ |
522 | |
523 | /* The ABI doesn't tell us how to supply FCRIR, and core dumps don't | |
524 | include it - but the result of PTRACE_GETFPREGS does. The best we | |
525 | can do is to assume that its value is present. */ | |
28f5035f | 526 | supply_32bit_reg (regcache, |
2eb4d78b | 527 | mips_regnum (gdbarch)->fp_implementation_revision, |
7d266584 | 528 | (const gdb_byte *) (*fpregsetp + 32) + 4); |
96f026fc KB |
529 | } |
530 | ||
50e8a0d5 HZ |
531 | static void |
532 | mips64_supply_fpregset_wrapper (const struct regset *regset, | |
7d266584 MR |
533 | struct regcache *regcache, |
534 | int regnum, const void *gregs, size_t len) | |
50e8a0d5 HZ |
535 | { |
536 | gdb_assert (len == sizeof (mips64_elf_fpregset_t)); | |
537 | ||
538 | mips64_supply_fpregset (regcache, (const mips64_elf_fpregset_t *)gregs); | |
539 | } | |
540 | ||
96f026fc KB |
541 | /* Likewise, pack one or all floating point registers into an |
542 | elf_fpregset_t. */ | |
543 | ||
d37eb719 | 544 | void |
28f5035f UW |
545 | mips64_fill_fpregset (const struct regcache *regcache, |
546 | mips64_elf_fpregset_t *fpregsetp, int regno) | |
96f026fc | 547 | { |
2eb4d78b | 548 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
e17a4113 | 549 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d37eb719 | 550 | gdb_byte *to; |
96f026fc | 551 | |
2eb4d78b UW |
552 | if ((regno >= gdbarch_fp0_regnum (gdbarch)) |
553 | && (regno < gdbarch_fp0_regnum (gdbarch) + 32)) | |
96f026fc | 554 | { |
d37eb719 DJ |
555 | /* See mips_linux_o32_sigframe_init for a description of the |
556 | peculiar FP register layout. */ | |
2eb4d78b | 557 | if (register_size (gdbarch, regno) == 4) |
d37eb719 | 558 | { |
2eb4d78b | 559 | int regi = regno - gdbarch_fp0_regnum (gdbarch); |
d37eb719 DJ |
560 | |
561 | to = (gdb_byte *) (*fpregsetp + (regi & ~1)); | |
2eb4d78b | 562 | if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (regi & 1)) |
d37eb719 | 563 | to += 4; |
28f5035f | 564 | regcache_raw_collect (regcache, regno, to); |
d37eb719 DJ |
565 | } |
566 | else | |
567 | { | |
025bb325 MS |
568 | to = (gdb_byte *) (*fpregsetp + regno |
569 | - gdbarch_fp0_regnum (gdbarch)); | |
28f5035f | 570 | regcache_raw_collect (regcache, regno, to); |
d37eb719 | 571 | } |
96f026fc | 572 | } |
2eb4d78b | 573 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
96f026fc | 574 | { |
d37eb719 DJ |
575 | gdb_byte buf[MAX_REGISTER_SIZE]; |
576 | LONGEST val; | |
577 | ||
28f5035f | 578 | regcache_raw_collect (regcache, regno, buf); |
e17a4113 UW |
579 | val = extract_signed_integer (buf, register_size (gdbarch, regno), |
580 | byte_order); | |
d37eb719 | 581 | to = (gdb_byte *) (*fpregsetp + 32); |
e17a4113 | 582 | store_signed_integer (to, 4, byte_order, val); |
d37eb719 | 583 | } |
2eb4d78b | 584 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
d37eb719 DJ |
585 | { |
586 | gdb_byte buf[MAX_REGISTER_SIZE]; | |
587 | LONGEST val; | |
588 | ||
28f5035f | 589 | regcache_raw_collect (regcache, regno, buf); |
e17a4113 UW |
590 | val = extract_signed_integer (buf, register_size (gdbarch, regno), |
591 | byte_order); | |
d37eb719 | 592 | to = (gdb_byte *) (*fpregsetp + 32) + 4; |
e17a4113 | 593 | store_signed_integer (to, 4, byte_order, val); |
96f026fc KB |
594 | } |
595 | else if (regno == -1) | |
596 | { | |
597 | int regi; | |
598 | ||
599 | for (regi = 0; regi < 32; regi++) | |
3e8c568d | 600 | mips64_fill_fpregset (regcache, fpregsetp, |
2eb4d78b | 601 | gdbarch_fp0_regnum (gdbarch) + regi); |
28f5035f | 602 | mips64_fill_fpregset (regcache, fpregsetp, |
2eb4d78b | 603 | mips_regnum (gdbarch)->fp_control_status); |
28f5035f | 604 | mips64_fill_fpregset (regcache, fpregsetp, |
7d266584 | 605 | mips_regnum (gdbarch)->fp_implementation_revision); |
96f026fc KB |
606 | } |
607 | } | |
608 | ||
50e8a0d5 HZ |
609 | static void |
610 | mips64_fill_fpregset_wrapper (const struct regset *regset, | |
611 | const struct regcache *regcache, | |
612 | int regnum, void *gregs, size_t len) | |
613 | { | |
614 | gdb_assert (len == sizeof (mips64_elf_fpregset_t)); | |
96f026fc | 615 | |
50e8a0d5 HZ |
616 | mips64_fill_fpregset (regcache, (mips64_elf_fpregset_t *)gregs, regnum); |
617 | } | |
2aa830e4 | 618 | |
b7195f27 AA |
619 | static const struct regset mips_linux_gregset = |
620 | { | |
621 | NULL, mips_supply_gregset_wrapper, mips_fill_gregset_wrapper | |
622 | }; | |
623 | ||
624 | static const struct regset mips64_linux_gregset = | |
625 | { | |
626 | NULL, mips64_supply_gregset_wrapper, mips64_fill_gregset_wrapper | |
627 | }; | |
628 | ||
629 | static const struct regset mips_linux_fpregset = | |
630 | { | |
631 | NULL, mips_supply_fpregset_wrapper, mips_fill_fpregset_wrapper | |
632 | }; | |
633 | ||
634 | static const struct regset mips64_linux_fpregset = | |
635 | { | |
636 | NULL, mips64_supply_fpregset_wrapper, mips64_fill_fpregset_wrapper | |
637 | }; | |
638 | ||
693be288 | 639 | static const struct regset * |
50e8a0d5 | 640 | mips_linux_regset_from_core_section (struct gdbarch *gdbarch, |
7d266584 | 641 | const char *sect_name, size_t sect_size) |
2aa830e4 | 642 | { |
d37eb719 DJ |
643 | mips_elf_gregset_t gregset; |
644 | mips_elf_fpregset_t fpregset; | |
96f026fc KB |
645 | mips64_elf_gregset_t gregset64; |
646 | mips64_elf_fpregset_t fpregset64; | |
2aa830e4 | 647 | |
50e8a0d5 | 648 | if (strcmp (sect_name, ".reg") == 0) |
2aa830e4 | 649 | { |
50e8a0d5 | 650 | if (sect_size == sizeof (gregset)) |
b7195f27 | 651 | return &mips_linux_gregset; |
50e8a0d5 | 652 | else if (sect_size == sizeof (gregset64)) |
b7195f27 | 653 | return &mips64_linux_gregset; |
2aa830e4 DJ |
654 | else |
655 | { | |
8a3fe4f8 | 656 | warning (_("wrong size gregset struct in core file")); |
2aa830e4 DJ |
657 | } |
658 | } | |
50e8a0d5 | 659 | else if (strcmp (sect_name, ".reg2") == 0) |
2aa830e4 | 660 | { |
50e8a0d5 | 661 | if (sect_size == sizeof (fpregset)) |
b7195f27 | 662 | return &mips_linux_fpregset; |
50e8a0d5 | 663 | else if (sect_size == sizeof (fpregset64)) |
b7195f27 | 664 | return &mips64_linux_fpregset; |
2aa830e4 DJ |
665 | else |
666 | { | |
8a3fe4f8 | 667 | warning (_("wrong size fpregset struct in core file")); |
2aa830e4 DJ |
668 | } |
669 | } | |
2aa830e4 | 670 | |
50e8a0d5 HZ |
671 | return NULL; |
672 | } | |
2aa830e4 | 673 | |
4eb0ad19 DJ |
674 | static const struct target_desc * |
675 | mips_linux_core_read_description (struct gdbarch *gdbarch, | |
676 | struct target_ops *target, | |
677 | bfd *abfd) | |
678 | { | |
679 | asection *section = bfd_get_section_by_name (abfd, ".reg"); | |
680 | if (! section) | |
681 | return NULL; | |
682 | ||
683 | switch (bfd_section_size (abfd, section)) | |
684 | { | |
685 | case sizeof (mips_elf_gregset_t): | |
686 | return mips_tdesc_gp32; | |
687 | ||
688 | case sizeof (mips64_elf_gregset_t): | |
689 | return mips_tdesc_gp64; | |
690 | ||
691 | default: | |
692 | return NULL; | |
693 | } | |
694 | } | |
695 | ||
96f026fc | 696 | |
295093a4 | 697 | /* Check the code at PC for a dynamic linker lazy resolution stub. |
3e5d3a5a MR |
698 | GNU ld for MIPS has put lazy resolution stubs into a ".MIPS.stubs" |
699 | section uniformly since version 2.15. If the pc is in that section, | |
700 | then we are in such a stub. Before that ".stub" was used in 32-bit | |
701 | ELF binaries, however we do not bother checking for that since we | |
702 | have never had and that case should be extremely rare these days. | |
703 | Instead we pattern-match on the code generated by GNU ld. They look | |
704 | like this: | |
6de918a6 DJ |
705 | |
706 | lw t9,0x8010(gp) | |
707 | addu t7,ra | |
708 | jalr t9,ra | |
709 | addiu t8,zero,INDEX | |
710 | ||
3e5d3a5a MR |
711 | (with the appropriate doubleword instructions for N64). As any lazy |
712 | resolution stubs in microMIPS binaries will always be in a | |
713 | ".MIPS.stubs" section we only ever verify standard MIPS patterns. */ | |
6de918a6 DJ |
714 | |
715 | static int | |
3e5d3a5a | 716 | mips_linux_in_dynsym_stub (CORE_ADDR pc) |
6de918a6 | 717 | { |
e362b510 | 718 | gdb_byte buf[28], *p; |
6de918a6 | 719 | ULONGEST insn, insn1; |
f5656ead TT |
720 | int n64 = (mips_abi (target_gdbarch ()) == MIPS_ABI_N64); |
721 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); | |
6de918a6 | 722 | |
3e5d3a5a MR |
723 | if (in_mips_stubs_section (pc)) |
724 | return 1; | |
725 | ||
6de918a6 DJ |
726 | read_memory (pc - 12, buf, 28); |
727 | ||
728 | if (n64) | |
729 | { | |
730 | /* ld t9,0x8010(gp) */ | |
731 | insn1 = 0xdf998010; | |
732 | } | |
733 | else | |
734 | { | |
735 | /* lw t9,0x8010(gp) */ | |
736 | insn1 = 0x8f998010; | |
737 | } | |
738 | ||
739 | p = buf + 12; | |
740 | while (p >= buf) | |
741 | { | |
e17a4113 | 742 | insn = extract_unsigned_integer (p, 4, byte_order); |
6de918a6 DJ |
743 | if (insn == insn1) |
744 | break; | |
745 | p -= 4; | |
746 | } | |
747 | if (p < buf) | |
748 | return 0; | |
749 | ||
e17a4113 | 750 | insn = extract_unsigned_integer (p + 4, 4, byte_order); |
6de918a6 DJ |
751 | if (n64) |
752 | { | |
753 | /* daddu t7,ra */ | |
754 | if (insn != 0x03e0782d) | |
755 | return 0; | |
756 | } | |
757 | else | |
758 | { | |
759 | /* addu t7,ra */ | |
760 | if (insn != 0x03e07821) | |
761 | return 0; | |
762 | } | |
295093a4 | 763 | |
e17a4113 | 764 | insn = extract_unsigned_integer (p + 8, 4, byte_order); |
6de918a6 DJ |
765 | /* jalr t9,ra */ |
766 | if (insn != 0x0320f809) | |
767 | return 0; | |
768 | ||
e17a4113 | 769 | insn = extract_unsigned_integer (p + 12, 4, byte_order); |
6de918a6 DJ |
770 | if (n64) |
771 | { | |
772 | /* daddiu t8,zero,0 */ | |
773 | if ((insn & 0xffff0000) != 0x64180000) | |
774 | return 0; | |
775 | } | |
776 | else | |
777 | { | |
778 | /* addiu t8,zero,0 */ | |
779 | if ((insn & 0xffff0000) != 0x24180000) | |
780 | return 0; | |
781 | } | |
782 | ||
3e5d3a5a | 783 | return 1; |
6de918a6 DJ |
784 | } |
785 | ||
295093a4 | 786 | /* Return non-zero iff PC belongs to the dynamic linker resolution |
db5f024e | 787 | code, a PLT entry, or a lazy binding stub. */ |
6de918a6 | 788 | |
7d522c90 | 789 | static int |
6de918a6 DJ |
790 | mips_linux_in_dynsym_resolve_code (CORE_ADDR pc) |
791 | { | |
295093a4 | 792 | /* Check whether PC is in the dynamic linker. This also checks |
db5f024e | 793 | whether it is in the .plt section, used by non-PIC executables. */ |
7d522c90 | 794 | if (svr4_in_dynsym_resolve_code (pc)) |
6de918a6 DJ |
795 | return 1; |
796 | ||
3e5d3a5a MR |
797 | /* Likewise for the stubs. They live in the .MIPS.stubs section these |
798 | days, so we check if the PC is within, than fall back to a pattern | |
799 | match. */ | |
800 | if (mips_linux_in_dynsym_stub (pc)) | |
6de918a6 DJ |
801 | return 1; |
802 | ||
803 | return 0; | |
804 | } | |
805 | ||
806 | /* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c, | |
807 | and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc | |
808 | implementation of this triggers at "fixup" from the same objfile as | |
c4c5b7ba | 809 | "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at |
db5f024e DJ |
810 | "__dl_runtime_resolve" directly. An unresolved lazy binding |
811 | stub will point to _dl_runtime_resolve, which will first call | |
c4c5b7ba AC |
812 | __dl_runtime_resolve, and then pass control to the resolved |
813 | function. */ | |
6de918a6 DJ |
814 | |
815 | static CORE_ADDR | |
816 | mips_linux_skip_resolver (struct gdbarch *gdbarch, CORE_ADDR pc) | |
817 | { | |
3b7344d5 | 818 | struct bound_minimal_symbol resolver; |
6de918a6 DJ |
819 | |
820 | resolver = lookup_minimal_symbol ("__dl_runtime_resolve", NULL, NULL); | |
821 | ||
77e371c0 | 822 | if (resolver.minsym && BMSYMBOL_VALUE_ADDRESS (resolver) == pc) |
c7ce8faa | 823 | return frame_unwind_caller_pc (get_current_frame ()); |
6de918a6 | 824 | |
db5f024e | 825 | return glibc_skip_solib_resolver (gdbarch, pc); |
295093a4 | 826 | } |
6de918a6 | 827 | |
5792a79b DJ |
828 | /* Signal trampoline support. There are four supported layouts for a |
829 | signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and | |
830 | n64 rt_sigframe. We handle them all independently; not the most | |
831 | efficient way, but simplest. First, declare all the unwinders. */ | |
832 | ||
833 | static void mips_linux_o32_sigframe_init (const struct tramp_frame *self, | |
b8a22b94 | 834 | struct frame_info *this_frame, |
5792a79b DJ |
835 | struct trad_frame_cache *this_cache, |
836 | CORE_ADDR func); | |
837 | ||
838 | static void mips_linux_n32n64_sigframe_init (const struct tramp_frame *self, | |
b8a22b94 | 839 | struct frame_info *this_frame, |
5792a79b DJ |
840 | struct trad_frame_cache *this_cache, |
841 | CORE_ADDR func); | |
842 | ||
843 | #define MIPS_NR_LINUX 4000 | |
844 | #define MIPS_NR_N64_LINUX 5000 | |
845 | #define MIPS_NR_N32_LINUX 6000 | |
846 | ||
847 | #define MIPS_NR_sigreturn MIPS_NR_LINUX + 119 | |
848 | #define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193 | |
849 | #define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211 | |
850 | #define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211 | |
851 | ||
852 | #define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn | |
853 | #define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn | |
854 | #define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn | |
855 | #define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn | |
856 | #define MIPS_INST_SYSCALL 0x0000000c | |
857 | ||
2cd8546d AC |
858 | static const struct tramp_frame mips_linux_o32_sigframe = { |
859 | SIGTRAMP_FRAME, | |
5792a79b | 860 | 4, |
2cd8546d AC |
861 | { |
862 | { MIPS_INST_LI_V0_SIGRETURN, -1 }, | |
863 | { MIPS_INST_SYSCALL, -1 }, | |
864 | { TRAMP_SENTINEL_INSN, -1 } | |
865 | }, | |
5792a79b DJ |
866 | mips_linux_o32_sigframe_init |
867 | }; | |
868 | ||
2cd8546d AC |
869 | static const struct tramp_frame mips_linux_o32_rt_sigframe = { |
870 | SIGTRAMP_FRAME, | |
5792a79b | 871 | 4, |
2cd8546d AC |
872 | { |
873 | { MIPS_INST_LI_V0_RT_SIGRETURN, -1 }, | |
874 | { MIPS_INST_SYSCALL, -1 }, | |
875 | { TRAMP_SENTINEL_INSN, -1 } }, | |
5792a79b DJ |
876 | mips_linux_o32_sigframe_init |
877 | }; | |
878 | ||
2cd8546d AC |
879 | static const struct tramp_frame mips_linux_n32_rt_sigframe = { |
880 | SIGTRAMP_FRAME, | |
5792a79b | 881 | 4, |
2cd8546d AC |
882 | { |
883 | { MIPS_INST_LI_V0_N32_RT_SIGRETURN, -1 }, | |
884 | { MIPS_INST_SYSCALL, -1 }, | |
885 | { TRAMP_SENTINEL_INSN, -1 } | |
886 | }, | |
5792a79b DJ |
887 | mips_linux_n32n64_sigframe_init |
888 | }; | |
889 | ||
2cd8546d AC |
890 | static const struct tramp_frame mips_linux_n64_rt_sigframe = { |
891 | SIGTRAMP_FRAME, | |
5792a79b | 892 | 4, |
fcbd8a5c TS |
893 | { |
894 | { MIPS_INST_LI_V0_N64_RT_SIGRETURN, -1 }, | |
895 | { MIPS_INST_SYSCALL, -1 }, | |
896 | { TRAMP_SENTINEL_INSN, -1 } | |
897 | }, | |
5792a79b DJ |
898 | mips_linux_n32n64_sigframe_init |
899 | }; | |
900 | ||
901 | /* *INDENT-OFF* */ | |
902 | /* The unwinder for o32 signal frames. The legacy structures look | |
903 | like this: | |
904 | ||
905 | struct sigframe { | |
906 | u32 sf_ass[4]; [argument save space for o32] | |
eb195664 | 907 | u32 sf_code[2]; [signal trampoline or fill] |
5792a79b DJ |
908 | struct sigcontext sf_sc; |
909 | sigset_t sf_mask; | |
910 | }; | |
911 | ||
d0e64392 MR |
912 | Pre-2.6.12 sigcontext: |
913 | ||
5792a79b DJ |
914 | struct sigcontext { |
915 | unsigned int sc_regmask; [Unused] | |
916 | unsigned int sc_status; | |
917 | unsigned long long sc_pc; | |
918 | unsigned long long sc_regs[32]; | |
919 | unsigned long long sc_fpregs[32]; | |
920 | unsigned int sc_ownedfp; | |
921 | unsigned int sc_fpc_csr; | |
922 | unsigned int sc_fpc_eir; [Unused] | |
923 | unsigned int sc_used_math; | |
924 | unsigned int sc_ssflags; [Unused] | |
925 | [Alignment hole of four bytes] | |
926 | unsigned long long sc_mdhi; | |
927 | unsigned long long sc_mdlo; | |
928 | ||
929 | unsigned int sc_cause; [Unused] | |
930 | unsigned int sc_badvaddr; [Unused] | |
931 | ||
932 | unsigned long sc_sigset[4]; [kernel's sigset_t] | |
933 | }; | |
934 | ||
d0e64392 MR |
935 | Post-2.6.12 sigcontext (SmartMIPS/DSP support added): |
936 | ||
937 | struct sigcontext { | |
938 | unsigned int sc_regmask; [Unused] | |
939 | unsigned int sc_status; [Unused] | |
940 | unsigned long long sc_pc; | |
941 | unsigned long long sc_regs[32]; | |
942 | unsigned long long sc_fpregs[32]; | |
943 | unsigned int sc_acx; | |
944 | unsigned int sc_fpc_csr; | |
945 | unsigned int sc_fpc_eir; [Unused] | |
946 | unsigned int sc_used_math; | |
947 | unsigned int sc_dsp; | |
948 | [Alignment hole of four bytes] | |
949 | unsigned long long sc_mdhi; | |
950 | unsigned long long sc_mdlo; | |
951 | unsigned long sc_hi1; | |
952 | unsigned long sc_lo1; | |
953 | unsigned long sc_hi2; | |
954 | unsigned long sc_lo2; | |
955 | unsigned long sc_hi3; | |
956 | unsigned long sc_lo3; | |
957 | }; | |
958 | ||
5792a79b DJ |
959 | The RT signal frames look like this: |
960 | ||
961 | struct rt_sigframe { | |
962 | u32 rs_ass[4]; [argument save space for o32] | |
eb195664 | 963 | u32 rs_code[2] [signal trampoline or fill] |
5792a79b DJ |
964 | struct siginfo rs_info; |
965 | struct ucontext rs_uc; | |
966 | }; | |
967 | ||
968 | struct ucontext { | |
969 | unsigned long uc_flags; | |
970 | struct ucontext *uc_link; | |
971 | stack_t uc_stack; | |
972 | [Alignment hole of four bytes] | |
973 | struct sigcontext uc_mcontext; | |
974 | sigset_t uc_sigmask; | |
975 | }; */ | |
976 | /* *INDENT-ON* */ | |
977 | ||
5792a79b DJ |
978 | #define SIGFRAME_SIGCONTEXT_OFFSET (6 * 4) |
979 | ||
980 | #define RTSIGFRAME_SIGINFO_SIZE 128 | |
981 | #define STACK_T_SIZE (3 * 4) | |
982 | #define UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + STACK_T_SIZE + 4) | |
983 | #define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ | |
984 | + RTSIGFRAME_SIGINFO_SIZE \ | |
985 | + UCONTEXT_SIGCONTEXT_OFFSET) | |
986 | ||
987 | #define SIGCONTEXT_PC (1 * 8) | |
988 | #define SIGCONTEXT_REGS (2 * 8) | |
989 | #define SIGCONTEXT_FPREGS (34 * 8) | |
990 | #define SIGCONTEXT_FPCSR (66 * 8 + 4) | |
d0e64392 | 991 | #define SIGCONTEXT_DSPCTL (68 * 8 + 0) |
5792a79b DJ |
992 | #define SIGCONTEXT_HI (69 * 8) |
993 | #define SIGCONTEXT_LO (70 * 8) | |
994 | #define SIGCONTEXT_CAUSE (71 * 8 + 0) | |
995 | #define SIGCONTEXT_BADVADDR (71 * 8 + 4) | |
d0e64392 MR |
996 | #define SIGCONTEXT_HI1 (71 * 8 + 0) |
997 | #define SIGCONTEXT_LO1 (71 * 8 + 4) | |
998 | #define SIGCONTEXT_HI2 (72 * 8 + 0) | |
999 | #define SIGCONTEXT_LO2 (72 * 8 + 4) | |
1000 | #define SIGCONTEXT_HI3 (73 * 8 + 0) | |
1001 | #define SIGCONTEXT_LO3 (73 * 8 + 4) | |
5792a79b DJ |
1002 | |
1003 | #define SIGCONTEXT_REG_SIZE 8 | |
1004 | ||
1005 | static void | |
1006 | mips_linux_o32_sigframe_init (const struct tramp_frame *self, | |
b8a22b94 | 1007 | struct frame_info *this_frame, |
5792a79b DJ |
1008 | struct trad_frame_cache *this_cache, |
1009 | CORE_ADDR func) | |
1010 | { | |
b8a22b94 | 1011 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
22e048c9 | 1012 | int ireg; |
eb195664 DD |
1013 | CORE_ADDR frame_sp = get_frame_sp (this_frame); |
1014 | CORE_ADDR sigcontext_base; | |
2eb4d78b | 1015 | const struct mips_regnum *regs = mips_regnum (gdbarch); |
37c4d197 | 1016 | CORE_ADDR regs_base; |
5792a79b DJ |
1017 | |
1018 | if (self == &mips_linux_o32_sigframe) | |
eb195664 | 1019 | sigcontext_base = frame_sp + SIGFRAME_SIGCONTEXT_OFFSET; |
5792a79b | 1020 | else |
eb195664 | 1021 | sigcontext_base = frame_sp + RTSIGFRAME_SIGCONTEXT_OFFSET; |
295093a4 MS |
1022 | |
1023 | /* I'm not proud of this hack. Eventually we will have the | |
1024 | infrastructure to indicate the size of saved registers on a | |
1025 | per-frame basis, but right now we don't; the kernel saves eight | |
37c4d197 DJ |
1026 | bytes but we only want four. Use regs_base to access any |
1027 | 64-bit fields. */ | |
2eb4d78b | 1028 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
37c4d197 DJ |
1029 | regs_base = sigcontext_base + 4; |
1030 | else | |
1031 | regs_base = sigcontext_base; | |
5792a79b | 1032 | |
2eb4d78b | 1033 | if (mips_linux_restart_reg_p (gdbarch)) |
822b6570 DJ |
1034 | trad_frame_set_reg_addr (this_cache, |
1035 | (MIPS_RESTART_REGNUM | |
2eb4d78b | 1036 | + gdbarch_num_regs (gdbarch)), |
822b6570 | 1037 | regs_base + SIGCONTEXT_REGS); |
5792a79b DJ |
1038 | |
1039 | for (ireg = 1; ireg < 32; ireg++) | |
295093a4 | 1040 | trad_frame_set_reg_addr (this_cache, |
7d266584 MR |
1041 | (ireg + MIPS_ZERO_REGNUM |
1042 | + gdbarch_num_regs (gdbarch)), | |
1043 | (regs_base + SIGCONTEXT_REGS | |
1044 | + ireg * SIGCONTEXT_REG_SIZE)); | |
5792a79b | 1045 | |
37c4d197 DJ |
1046 | /* The way that floating point registers are saved, unfortunately, |
1047 | depends on the architecture the kernel is built for. For the r3000 and | |
1048 | tx39, four bytes of each register are at the beginning of each of the | |
1049 | 32 eight byte slots. For everything else, the registers are saved | |
1050 | using double precision; only the even-numbered slots are initialized, | |
1051 | and the high bits are the odd-numbered register. Assume the latter | |
1052 | layout, since we can't tell, and it's much more common. Which bits are | |
1053 | the "high" bits depends on endianness. */ | |
5792a79b | 1054 | for (ireg = 0; ireg < 32; ireg++) |
2eb4d78b | 1055 | if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (ireg & 1)) |
f57d151a | 1056 | trad_frame_set_reg_addr (this_cache, |
7d266584 MR |
1057 | ireg + regs->fp0 + gdbarch_num_regs (gdbarch), |
1058 | (sigcontext_base + SIGCONTEXT_FPREGS + 4 | |
1059 | + (ireg & ~1) * SIGCONTEXT_REG_SIZE)); | |
37c4d197 | 1060 | else |
f57d151a | 1061 | trad_frame_set_reg_addr (this_cache, |
7d266584 MR |
1062 | ireg + regs->fp0 + gdbarch_num_regs (gdbarch), |
1063 | (sigcontext_base + SIGCONTEXT_FPREGS | |
1064 | + (ireg & ~1) * SIGCONTEXT_REG_SIZE)); | |
5792a79b | 1065 | |
f57d151a | 1066 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1067 | regs->pc + gdbarch_num_regs (gdbarch), |
37c4d197 | 1068 | regs_base + SIGCONTEXT_PC); |
5792a79b | 1069 | |
295093a4 | 1070 | trad_frame_set_reg_addr (this_cache, |
7d266584 MR |
1071 | (regs->fp_control_status |
1072 | + gdbarch_num_regs (gdbarch)), | |
5792a79b | 1073 | sigcontext_base + SIGCONTEXT_FPCSR); |
d0e64392 MR |
1074 | |
1075 | if (regs->dspctl != -1) | |
1076 | trad_frame_set_reg_addr (this_cache, | |
1077 | regs->dspctl + gdbarch_num_regs (gdbarch), | |
1078 | sigcontext_base + SIGCONTEXT_DSPCTL); | |
1079 | ||
f57d151a | 1080 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1081 | regs->hi + gdbarch_num_regs (gdbarch), |
37c4d197 | 1082 | regs_base + SIGCONTEXT_HI); |
f57d151a | 1083 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1084 | regs->lo + gdbarch_num_regs (gdbarch), |
37c4d197 | 1085 | regs_base + SIGCONTEXT_LO); |
d0e64392 MR |
1086 | |
1087 | if (regs->dspacc != -1) | |
1088 | { | |
1089 | trad_frame_set_reg_addr (this_cache, | |
1090 | regs->dspacc + 0 + gdbarch_num_regs (gdbarch), | |
1091 | sigcontext_base + SIGCONTEXT_HI1); | |
1092 | trad_frame_set_reg_addr (this_cache, | |
1093 | regs->dspacc + 1 + gdbarch_num_regs (gdbarch), | |
1094 | sigcontext_base + SIGCONTEXT_LO1); | |
1095 | trad_frame_set_reg_addr (this_cache, | |
1096 | regs->dspacc + 2 + gdbarch_num_regs (gdbarch), | |
1097 | sigcontext_base + SIGCONTEXT_HI2); | |
1098 | trad_frame_set_reg_addr (this_cache, | |
1099 | regs->dspacc + 3 + gdbarch_num_regs (gdbarch), | |
1100 | sigcontext_base + SIGCONTEXT_LO2); | |
1101 | trad_frame_set_reg_addr (this_cache, | |
1102 | regs->dspacc + 4 + gdbarch_num_regs (gdbarch), | |
1103 | sigcontext_base + SIGCONTEXT_HI3); | |
1104 | trad_frame_set_reg_addr (this_cache, | |
1105 | regs->dspacc + 5 + gdbarch_num_regs (gdbarch), | |
1106 | sigcontext_base + SIGCONTEXT_LO3); | |
1107 | } | |
1108 | else | |
1109 | { | |
1110 | trad_frame_set_reg_addr (this_cache, | |
1111 | regs->cause + gdbarch_num_regs (gdbarch), | |
1112 | sigcontext_base + SIGCONTEXT_CAUSE); | |
1113 | trad_frame_set_reg_addr (this_cache, | |
1114 | regs->badvaddr + gdbarch_num_regs (gdbarch), | |
1115 | sigcontext_base + SIGCONTEXT_BADVADDR); | |
1116 | } | |
5792a79b DJ |
1117 | |
1118 | /* Choice of the bottom of the sigframe is somewhat arbitrary. */ | |
eb195664 | 1119 | trad_frame_set_id (this_cache, frame_id_build (frame_sp, func)); |
5792a79b DJ |
1120 | } |
1121 | ||
1122 | /* *INDENT-OFF* */ | |
1123 | /* For N32/N64 things look different. There is no non-rt signal frame. | |
1124 | ||
1125 | struct rt_sigframe_n32 { | |
1126 | u32 rs_ass[4]; [ argument save space for o32 ] | |
eb195664 | 1127 | u32 rs_code[2]; [ signal trampoline or fill ] |
5792a79b DJ |
1128 | struct siginfo rs_info; |
1129 | struct ucontextn32 rs_uc; | |
1130 | }; | |
1131 | ||
1132 | struct ucontextn32 { | |
1133 | u32 uc_flags; | |
1134 | s32 uc_link; | |
1135 | stack32_t uc_stack; | |
1136 | struct sigcontext uc_mcontext; | |
1137 | sigset_t uc_sigmask; [ mask last for extensibility ] | |
1138 | }; | |
295093a4 | 1139 | |
e741f4d4 | 1140 | struct rt_sigframe { |
5792a79b DJ |
1141 | u32 rs_ass[4]; [ argument save space for o32 ] |
1142 | u32 rs_code[2]; [ signal trampoline ] | |
1143 | struct siginfo rs_info; | |
1144 | struct ucontext rs_uc; | |
1145 | }; | |
1146 | ||
1147 | struct ucontext { | |
1148 | unsigned long uc_flags; | |
1149 | struct ucontext *uc_link; | |
1150 | stack_t uc_stack; | |
1151 | struct sigcontext uc_mcontext; | |
1152 | sigset_t uc_sigmask; [ mask last for extensibility ] | |
1153 | }; | |
1154 | ||
1155 | And the sigcontext is different (this is for both n32 and n64): | |
1156 | ||
1157 | struct sigcontext { | |
1158 | unsigned long long sc_regs[32]; | |
1159 | unsigned long long sc_fpregs[32]; | |
1160 | unsigned long long sc_mdhi; | |
e741f4d4 DJ |
1161 | unsigned long long sc_hi1; |
1162 | unsigned long long sc_hi2; | |
1163 | unsigned long long sc_hi3; | |
5792a79b | 1164 | unsigned long long sc_mdlo; |
e741f4d4 DJ |
1165 | unsigned long long sc_lo1; |
1166 | unsigned long long sc_lo2; | |
1167 | unsigned long long sc_lo3; | |
5792a79b | 1168 | unsigned long long sc_pc; |
5792a79b | 1169 | unsigned int sc_fpc_csr; |
5792a79b | 1170 | unsigned int sc_used_math; |
e741f4d4 DJ |
1171 | unsigned int sc_dsp; |
1172 | unsigned int sc_reserved; | |
1173 | }; | |
1174 | ||
1175 | That is the post-2.6.12 definition of the 64-bit sigcontext; before | |
1176 | then, there were no hi1-hi3 or lo1-lo3. Cause and badvaddr were | |
1177 | included too. */ | |
5792a79b DJ |
1178 | /* *INDENT-ON* */ |
1179 | ||
1180 | #define N32_STACK_T_SIZE STACK_T_SIZE | |
1181 | #define N64_STACK_T_SIZE (2 * 8 + 4) | |
1182 | #define N32_UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + N32_STACK_T_SIZE + 4) | |
1183 | #define N64_UCONTEXT_SIGCONTEXT_OFFSET (2 * 8 + N64_STACK_T_SIZE + 4) | |
1184 | #define N32_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ | |
1185 | + RTSIGFRAME_SIGINFO_SIZE \ | |
1186 | + N32_UCONTEXT_SIGCONTEXT_OFFSET) | |
1187 | #define N64_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ | |
1188 | + RTSIGFRAME_SIGINFO_SIZE \ | |
1189 | + N64_UCONTEXT_SIGCONTEXT_OFFSET) | |
1190 | ||
1191 | #define N64_SIGCONTEXT_REGS (0 * 8) | |
1192 | #define N64_SIGCONTEXT_FPREGS (32 * 8) | |
1193 | #define N64_SIGCONTEXT_HI (64 * 8) | |
d0e64392 MR |
1194 | #define N64_SIGCONTEXT_HI1 (65 * 8) |
1195 | #define N64_SIGCONTEXT_HI2 (66 * 8) | |
1196 | #define N64_SIGCONTEXT_HI3 (67 * 8) | |
e741f4d4 | 1197 | #define N64_SIGCONTEXT_LO (68 * 8) |
d0e64392 MR |
1198 | #define N64_SIGCONTEXT_LO1 (69 * 8) |
1199 | #define N64_SIGCONTEXT_LO2 (70 * 8) | |
1200 | #define N64_SIGCONTEXT_LO3 (71 * 8) | |
e741f4d4 | 1201 | #define N64_SIGCONTEXT_PC (72 * 8) |
d0e64392 MR |
1202 | #define N64_SIGCONTEXT_FPCSR (73 * 8 + 0) |
1203 | #define N64_SIGCONTEXT_DSPCTL (74 * 8 + 0) | |
5792a79b DJ |
1204 | |
1205 | #define N64_SIGCONTEXT_REG_SIZE 8 | |
295093a4 | 1206 | |
5792a79b DJ |
1207 | static void |
1208 | mips_linux_n32n64_sigframe_init (const struct tramp_frame *self, | |
b8a22b94 | 1209 | struct frame_info *this_frame, |
5792a79b DJ |
1210 | struct trad_frame_cache *this_cache, |
1211 | CORE_ADDR func) | |
1212 | { | |
b8a22b94 | 1213 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
22e048c9 | 1214 | int ireg; |
eb195664 DD |
1215 | CORE_ADDR frame_sp = get_frame_sp (this_frame); |
1216 | CORE_ADDR sigcontext_base; | |
2eb4d78b | 1217 | const struct mips_regnum *regs = mips_regnum (gdbarch); |
5792a79b DJ |
1218 | |
1219 | if (self == &mips_linux_n32_rt_sigframe) | |
eb195664 | 1220 | sigcontext_base = frame_sp + N32_SIGFRAME_SIGCONTEXT_OFFSET; |
5792a79b | 1221 | else |
eb195664 | 1222 | sigcontext_base = frame_sp + N64_SIGFRAME_SIGCONTEXT_OFFSET; |
295093a4 | 1223 | |
2eb4d78b | 1224 | if (mips_linux_restart_reg_p (gdbarch)) |
822b6570 DJ |
1225 | trad_frame_set_reg_addr (this_cache, |
1226 | (MIPS_RESTART_REGNUM | |
2eb4d78b | 1227 | + gdbarch_num_regs (gdbarch)), |
822b6570 | 1228 | sigcontext_base + N64_SIGCONTEXT_REGS); |
5792a79b DJ |
1229 | |
1230 | for (ireg = 1; ireg < 32; ireg++) | |
295093a4 | 1231 | trad_frame_set_reg_addr (this_cache, |
7d266584 MR |
1232 | (ireg + MIPS_ZERO_REGNUM |
1233 | + gdbarch_num_regs (gdbarch)), | |
1234 | (sigcontext_base + N64_SIGCONTEXT_REGS | |
1235 | + ireg * N64_SIGCONTEXT_REG_SIZE)); | |
5792a79b DJ |
1236 | |
1237 | for (ireg = 0; ireg < 32; ireg++) | |
f57d151a | 1238 | trad_frame_set_reg_addr (this_cache, |
7d266584 MR |
1239 | ireg + regs->fp0 + gdbarch_num_regs (gdbarch), |
1240 | (sigcontext_base + N64_SIGCONTEXT_FPREGS | |
1241 | + ireg * N64_SIGCONTEXT_REG_SIZE)); | |
5792a79b | 1242 | |
f57d151a | 1243 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1244 | regs->pc + gdbarch_num_regs (gdbarch), |
5792a79b DJ |
1245 | sigcontext_base + N64_SIGCONTEXT_PC); |
1246 | ||
295093a4 | 1247 | trad_frame_set_reg_addr (this_cache, |
7d266584 MR |
1248 | (regs->fp_control_status |
1249 | + gdbarch_num_regs (gdbarch)), | |
5792a79b | 1250 | sigcontext_base + N64_SIGCONTEXT_FPCSR); |
d0e64392 | 1251 | |
f57d151a | 1252 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1253 | regs->hi + gdbarch_num_regs (gdbarch), |
5792a79b | 1254 | sigcontext_base + N64_SIGCONTEXT_HI); |
f57d151a | 1255 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1256 | regs->lo + gdbarch_num_regs (gdbarch), |
5792a79b | 1257 | sigcontext_base + N64_SIGCONTEXT_LO); |
5792a79b | 1258 | |
d0e64392 MR |
1259 | if (regs->dspacc != -1) |
1260 | { | |
1261 | trad_frame_set_reg_addr (this_cache, | |
1262 | regs->dspacc + 0 + gdbarch_num_regs (gdbarch), | |
1263 | sigcontext_base + N64_SIGCONTEXT_HI1); | |
1264 | trad_frame_set_reg_addr (this_cache, | |
1265 | regs->dspacc + 1 + gdbarch_num_regs (gdbarch), | |
1266 | sigcontext_base + N64_SIGCONTEXT_LO1); | |
1267 | trad_frame_set_reg_addr (this_cache, | |
1268 | regs->dspacc + 2 + gdbarch_num_regs (gdbarch), | |
1269 | sigcontext_base + N64_SIGCONTEXT_HI2); | |
1270 | trad_frame_set_reg_addr (this_cache, | |
1271 | regs->dspacc + 3 + gdbarch_num_regs (gdbarch), | |
1272 | sigcontext_base + N64_SIGCONTEXT_LO2); | |
1273 | trad_frame_set_reg_addr (this_cache, | |
1274 | regs->dspacc + 4 + gdbarch_num_regs (gdbarch), | |
1275 | sigcontext_base + N64_SIGCONTEXT_HI3); | |
1276 | trad_frame_set_reg_addr (this_cache, | |
1277 | regs->dspacc + 5 + gdbarch_num_regs (gdbarch), | |
1278 | sigcontext_base + N64_SIGCONTEXT_LO3); | |
1279 | } | |
1280 | if (regs->dspctl != -1) | |
1281 | trad_frame_set_reg_addr (this_cache, | |
1282 | regs->dspctl + gdbarch_num_regs (gdbarch), | |
1283 | sigcontext_base + N64_SIGCONTEXT_DSPCTL); | |
1284 | ||
5792a79b | 1285 | /* Choice of the bottom of the sigframe is somewhat arbitrary. */ |
eb195664 | 1286 | trad_frame_set_id (this_cache, frame_id_build (frame_sp, func)); |
5792a79b DJ |
1287 | } |
1288 | ||
5a439849 MR |
1289 | /* Implement the "write_pc" gdbarch method. */ |
1290 | ||
822b6570 | 1291 | static void |
61a1198a | 1292 | mips_linux_write_pc (struct regcache *regcache, CORE_ADDR pc) |
822b6570 | 1293 | { |
2eb4d78b | 1294 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
5a439849 MR |
1295 | |
1296 | mips_write_pc (regcache, pc); | |
822b6570 DJ |
1297 | |
1298 | /* Clear the syscall restart flag. */ | |
2eb4d78b | 1299 | if (mips_linux_restart_reg_p (gdbarch)) |
61a1198a | 1300 | regcache_cooked_write_unsigned (regcache, MIPS_RESTART_REGNUM, 0); |
822b6570 DJ |
1301 | } |
1302 | ||
1303 | /* Return 1 if MIPS_RESTART_REGNUM is usable. */ | |
1304 | ||
1305 | int | |
1306 | mips_linux_restart_reg_p (struct gdbarch *gdbarch) | |
1307 | { | |
1308 | /* If we do not have a target description with registers, then | |
1309 | MIPS_RESTART_REGNUM will not be included in the register set. */ | |
1310 | if (!tdesc_has_registers (gdbarch_target_desc (gdbarch))) | |
1311 | return 0; | |
1312 | ||
1313 | /* If we do, then MIPS_RESTART_REGNUM is safe to check; it will | |
1314 | either be GPR-sized or missing. */ | |
1315 | return register_size (gdbarch, MIPS_RESTART_REGNUM) > 0; | |
1316 | } | |
9f62d0e2 | 1317 | |
e38d4e1a DJ |
1318 | /* When FRAME is at a syscall instruction, return the PC of the next |
1319 | instruction to be executed. */ | |
1320 | ||
63807e1d | 1321 | static CORE_ADDR |
e38d4e1a DJ |
1322 | mips_linux_syscall_next_pc (struct frame_info *frame) |
1323 | { | |
1324 | CORE_ADDR pc = get_frame_pc (frame); | |
1325 | ULONGEST v0 = get_frame_register_unsigned (frame, MIPS_V0_REGNUM); | |
1326 | ||
1327 | /* If we are about to make a sigreturn syscall, use the unwinder to | |
1328 | decode the signal frame. */ | |
1329 | if (v0 == MIPS_NR_sigreturn | |
1330 | || v0 == MIPS_NR_rt_sigreturn | |
1331 | || v0 == MIPS_NR_N64_rt_sigreturn | |
1332 | || v0 == MIPS_NR_N32_rt_sigreturn) | |
c7ce8faa | 1333 | return frame_unwind_caller_pc (get_current_frame ()); |
e38d4e1a DJ |
1334 | |
1335 | return pc + 4; | |
1336 | } | |
1337 | ||
385203ed DD |
1338 | /* Return the current system call's number present in the |
1339 | v0 register. When the function fails, it returns -1. */ | |
1340 | ||
1341 | static LONGEST | |
1342 | mips_linux_get_syscall_number (struct gdbarch *gdbarch, | |
1343 | ptid_t ptid) | |
1344 | { | |
1345 | struct regcache *regcache = get_thread_regcache (ptid); | |
1346 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1347 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1348 | int regsize = register_size (gdbarch, MIPS_V0_REGNUM); | |
1349 | /* The content of a register */ | |
1350 | gdb_byte buf[8]; | |
1351 | /* The result */ | |
1352 | LONGEST ret; | |
1353 | ||
1354 | /* Make sure we're in a known ABI */ | |
1355 | gdb_assert (tdep->mips_abi == MIPS_ABI_O32 | |
1356 | || tdep->mips_abi == MIPS_ABI_N32 | |
1357 | || tdep->mips_abi == MIPS_ABI_N64); | |
1358 | ||
1359 | gdb_assert (regsize <= sizeof (buf)); | |
1360 | ||
1361 | /* Getting the system call number from the register. | |
1362 | syscall number is in v0 or $2. */ | |
1363 | regcache_cooked_read (regcache, MIPS_V0_REGNUM, buf); | |
1364 | ||
1365 | ret = extract_signed_integer (buf, regsize, byte_order); | |
1366 | ||
1367 | return ret; | |
1368 | } | |
1369 | ||
eb14d406 SDJ |
1370 | /* Implementation of `gdbarch_gdb_signal_to_target', as defined in |
1371 | gdbarch.h. */ | |
1372 | ||
1373 | static int | |
1374 | mips_gdb_signal_to_target (struct gdbarch *gdbarch, | |
1375 | enum gdb_signal signal) | |
1376 | { | |
1377 | switch (signal) | |
1378 | { | |
1379 | case GDB_SIGNAL_EMT: | |
1380 | return MIPS_LINUX_SIGEMT; | |
1381 | ||
1382 | case GDB_SIGNAL_BUS: | |
1383 | return MIPS_LINUX_SIGBUS; | |
1384 | ||
1385 | case GDB_SIGNAL_SYS: | |
1386 | return MIPS_LINUX_SIGSYS; | |
1387 | ||
1388 | case GDB_SIGNAL_USR1: | |
1389 | return MIPS_LINUX_SIGUSR1; | |
1390 | ||
1391 | case GDB_SIGNAL_USR2: | |
1392 | return MIPS_LINUX_SIGUSR2; | |
1393 | ||
1394 | case GDB_SIGNAL_CHLD: | |
1395 | return MIPS_LINUX_SIGCHLD; | |
1396 | ||
1397 | case GDB_SIGNAL_PWR: | |
1398 | return MIPS_LINUX_SIGPWR; | |
1399 | ||
1400 | case GDB_SIGNAL_WINCH: | |
1401 | return MIPS_LINUX_SIGWINCH; | |
1402 | ||
1403 | case GDB_SIGNAL_URG: | |
1404 | return MIPS_LINUX_SIGURG; | |
1405 | ||
1406 | case GDB_SIGNAL_IO: | |
1407 | return MIPS_LINUX_SIGIO; | |
1408 | ||
1409 | case GDB_SIGNAL_POLL: | |
1410 | return MIPS_LINUX_SIGPOLL; | |
1411 | ||
1412 | case GDB_SIGNAL_STOP: | |
1413 | return MIPS_LINUX_SIGSTOP; | |
1414 | ||
1415 | case GDB_SIGNAL_TSTP: | |
1416 | return MIPS_LINUX_SIGTSTP; | |
1417 | ||
1418 | case GDB_SIGNAL_CONT: | |
1419 | return MIPS_LINUX_SIGCONT; | |
1420 | ||
1421 | case GDB_SIGNAL_TTIN: | |
1422 | return MIPS_LINUX_SIGTTIN; | |
1423 | ||
1424 | case GDB_SIGNAL_TTOU: | |
1425 | return MIPS_LINUX_SIGTTOU; | |
1426 | ||
1427 | case GDB_SIGNAL_VTALRM: | |
1428 | return MIPS_LINUX_SIGVTALRM; | |
1429 | ||
1430 | case GDB_SIGNAL_PROF: | |
1431 | return MIPS_LINUX_SIGPROF; | |
1432 | ||
1433 | case GDB_SIGNAL_XCPU: | |
1434 | return MIPS_LINUX_SIGXCPU; | |
1435 | ||
1436 | case GDB_SIGNAL_XFSZ: | |
1437 | return MIPS_LINUX_SIGXFSZ; | |
1438 | ||
1439 | /* GDB_SIGNAL_REALTIME_32 is not continuous in <gdb/signals.def>, | |
1440 | therefore we have to handle it here. */ | |
1441 | case GDB_SIGNAL_REALTIME_32: | |
1442 | return MIPS_LINUX_SIGRTMIN; | |
1443 | } | |
1444 | ||
1445 | if (signal >= GDB_SIGNAL_REALTIME_33 | |
1446 | && signal <= GDB_SIGNAL_REALTIME_63) | |
1447 | { | |
1448 | int offset = signal - GDB_SIGNAL_REALTIME_33; | |
1449 | ||
1450 | return MIPS_LINUX_SIGRTMIN + 1 + offset; | |
1451 | } | |
1452 | else if (signal >= GDB_SIGNAL_REALTIME_64 | |
1453 | && signal <= GDB_SIGNAL_REALTIME_127) | |
1454 | { | |
1455 | int offset = signal - GDB_SIGNAL_REALTIME_64; | |
1456 | ||
1457 | return MIPS_LINUX_SIGRT64 + offset; | |
1458 | } | |
1459 | ||
1460 | return linux_gdb_signal_to_target (gdbarch, signal); | |
1461 | } | |
1462 | ||
7d266584 | 1463 | /* Translate signals based on MIPS signal values. |
232b8704 ME |
1464 | Adapted from gdb/common/signals.c. */ |
1465 | ||
1466 | static enum gdb_signal | |
eb14d406 | 1467 | mips_gdb_signal_from_target (struct gdbarch *gdbarch, int signal) |
232b8704 | 1468 | { |
eb14d406 | 1469 | switch (signal) |
232b8704 | 1470 | { |
eb14d406 | 1471 | case MIPS_LINUX_SIGEMT: |
232b8704 | 1472 | return GDB_SIGNAL_EMT; |
eb14d406 SDJ |
1473 | |
1474 | case MIPS_LINUX_SIGBUS: | |
232b8704 | 1475 | return GDB_SIGNAL_BUS; |
eb14d406 SDJ |
1476 | |
1477 | case MIPS_LINUX_SIGSYS: | |
232b8704 | 1478 | return GDB_SIGNAL_SYS; |
eb14d406 SDJ |
1479 | |
1480 | case MIPS_LINUX_SIGUSR1: | |
232b8704 | 1481 | return GDB_SIGNAL_USR1; |
eb14d406 SDJ |
1482 | |
1483 | case MIPS_LINUX_SIGUSR2: | |
232b8704 | 1484 | return GDB_SIGNAL_USR2; |
eb14d406 SDJ |
1485 | |
1486 | case MIPS_LINUX_SIGCHLD: | |
232b8704 | 1487 | return GDB_SIGNAL_CHLD; |
eb14d406 SDJ |
1488 | |
1489 | case MIPS_LINUX_SIGPWR: | |
232b8704 | 1490 | return GDB_SIGNAL_PWR; |
eb14d406 SDJ |
1491 | |
1492 | case MIPS_LINUX_SIGWINCH: | |
232b8704 | 1493 | return GDB_SIGNAL_WINCH; |
eb14d406 SDJ |
1494 | |
1495 | case MIPS_LINUX_SIGURG: | |
232b8704 | 1496 | return GDB_SIGNAL_URG; |
eb14d406 SDJ |
1497 | |
1498 | /* No way to differentiate between SIGIO and SIGPOLL. | |
1499 | Therefore, we just handle the first one. */ | |
1500 | case MIPS_LINUX_SIGIO: | |
1501 | return GDB_SIGNAL_IO; | |
1502 | ||
1503 | case MIPS_LINUX_SIGSTOP: | |
232b8704 | 1504 | return GDB_SIGNAL_STOP; |
eb14d406 SDJ |
1505 | |
1506 | case MIPS_LINUX_SIGTSTP: | |
232b8704 | 1507 | return GDB_SIGNAL_TSTP; |
eb14d406 SDJ |
1508 | |
1509 | case MIPS_LINUX_SIGCONT: | |
232b8704 | 1510 | return GDB_SIGNAL_CONT; |
eb14d406 SDJ |
1511 | |
1512 | case MIPS_LINUX_SIGTTIN: | |
232b8704 | 1513 | return GDB_SIGNAL_TTIN; |
eb14d406 SDJ |
1514 | |
1515 | case MIPS_LINUX_SIGTTOU: | |
232b8704 | 1516 | return GDB_SIGNAL_TTOU; |
eb14d406 SDJ |
1517 | |
1518 | case MIPS_LINUX_SIGVTALRM: | |
232b8704 | 1519 | return GDB_SIGNAL_VTALRM; |
eb14d406 SDJ |
1520 | |
1521 | case MIPS_LINUX_SIGPROF: | |
232b8704 | 1522 | return GDB_SIGNAL_PROF; |
eb14d406 SDJ |
1523 | |
1524 | case MIPS_LINUX_SIGXCPU: | |
232b8704 | 1525 | return GDB_SIGNAL_XCPU; |
eb14d406 SDJ |
1526 | |
1527 | case MIPS_LINUX_SIGXFSZ: | |
232b8704 | 1528 | return GDB_SIGNAL_XFSZ; |
eb14d406 | 1529 | } |
232b8704 | 1530 | |
eb14d406 | 1531 | if (signal >= MIPS_LINUX_SIGRTMIN && signal <= MIPS_LINUX_SIGRTMAX) |
232b8704 ME |
1532 | { |
1533 | /* GDB_SIGNAL_REALTIME values are not contiguous, map parts of | |
1534 | the MIPS block to the respective GDB_SIGNAL_REALTIME blocks. */ | |
eb14d406 SDJ |
1535 | int offset = signal - MIPS_LINUX_SIGRTMIN; |
1536 | ||
1537 | if (offset == 0) | |
232b8704 | 1538 | return GDB_SIGNAL_REALTIME_32; |
eb14d406 SDJ |
1539 | else if (offset < 32) |
1540 | return (enum gdb_signal) (offset - 1 | |
1541 | + (int) GDB_SIGNAL_REALTIME_33); | |
232b8704 | 1542 | else |
eb14d406 SDJ |
1543 | return (enum gdb_signal) (offset - 32 |
1544 | + (int) GDB_SIGNAL_REALTIME_64); | |
232b8704 ME |
1545 | } |
1546 | ||
eb14d406 | 1547 | return linux_gdb_signal_from_target (gdbarch, signal); |
232b8704 ME |
1548 | } |
1549 | ||
5792a79b DJ |
1550 | /* Initialize one of the GNU/Linux OS ABIs. */ |
1551 | ||
19ed69dd | 1552 | static void |
295093a4 MS |
1553 | mips_linux_init_abi (struct gdbarch_info info, |
1554 | struct gdbarch *gdbarch) | |
19ed69dd | 1555 | { |
96f026fc KB |
1556 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1557 | enum mips_abi abi = mips_abi (gdbarch); | |
822b6570 | 1558 | struct tdesc_arch_data *tdesc_data = (void *) info.tdep_info; |
96f026fc | 1559 | |
a5ee0f0c PA |
1560 | linux_init_abi (info, gdbarch); |
1561 | ||
385203ed DD |
1562 | /* Get the syscall number from the arch's register. */ |
1563 | set_gdbarch_get_syscall_number (gdbarch, mips_linux_get_syscall_number); | |
1564 | ||
96f026fc KB |
1565 | switch (abi) |
1566 | { | |
1567 | case MIPS_ABI_O32: | |
1568 | set_gdbarch_get_longjmp_target (gdbarch, | |
7d266584 | 1569 | mips_linux_get_longjmp_target); |
96f026fc | 1570 | set_solib_svr4_fetch_link_map_offsets |
76a9d10f | 1571 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); |
fb2be677 AC |
1572 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_sigframe); |
1573 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_rt_sigframe); | |
385203ed | 1574 | set_xml_syscall_file_name ("syscalls/mips-o32-linux.xml"); |
96f026fc KB |
1575 | break; |
1576 | case MIPS_ABI_N32: | |
1577 | set_gdbarch_get_longjmp_target (gdbarch, | |
7d266584 | 1578 | mips_linux_get_longjmp_target); |
96f026fc | 1579 | set_solib_svr4_fetch_link_map_offsets |
76a9d10f | 1580 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); |
d05f6826 DJ |
1581 | set_gdbarch_long_double_bit (gdbarch, 128); |
1582 | /* These floatformats should probably be renamed. MIPS uses | |
1583 | the same 128-bit IEEE floating point format that IA-64 uses, | |
1584 | except that the quiet/signalling NaN bit is reversed (GDB | |
1585 | does not distinguish between quiet and signalling NaNs). */ | |
8da61cc4 | 1586 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); |
fb2be677 | 1587 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n32_rt_sigframe); |
385203ed | 1588 | set_xml_syscall_file_name ("syscalls/mips-n32-linux.xml"); |
96f026fc KB |
1589 | break; |
1590 | case MIPS_ABI_N64: | |
1591 | set_gdbarch_get_longjmp_target (gdbarch, | |
7d266584 | 1592 | mips64_linux_get_longjmp_target); |
96f026fc | 1593 | set_solib_svr4_fetch_link_map_offsets |
76a9d10f | 1594 | (gdbarch, svr4_lp64_fetch_link_map_offsets); |
d05f6826 DJ |
1595 | set_gdbarch_long_double_bit (gdbarch, 128); |
1596 | /* These floatformats should probably be renamed. MIPS uses | |
1597 | the same 128-bit IEEE floating point format that IA-64 uses, | |
1598 | except that the quiet/signalling NaN bit is reversed (GDB | |
1599 | does not distinguish between quiet and signalling NaNs). */ | |
8da61cc4 | 1600 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); |
fb2be677 | 1601 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n64_rt_sigframe); |
385203ed | 1602 | set_xml_syscall_file_name ("syscalls/mips-n64-linux.xml"); |
96f026fc KB |
1603 | break; |
1604 | default: | |
96f026fc KB |
1605 | break; |
1606 | } | |
6de918a6 DJ |
1607 | |
1608 | set_gdbarch_skip_solib_resolver (gdbarch, mips_linux_skip_resolver); | |
1609 | ||
0d0266c6 | 1610 | set_gdbarch_software_single_step (gdbarch, mips_software_single_step); |
b2756930 KB |
1611 | |
1612 | /* Enable TLS support. */ | |
1613 | set_gdbarch_fetch_tls_load_module_address (gdbarch, | |
7d266584 | 1614 | svr4_fetch_objfile_link_map); |
7d522c90 DJ |
1615 | |
1616 | /* Initialize this lazily, to avoid an initialization order | |
1617 | dependency on solib-svr4.c's _initialize routine. */ | |
1618 | if (mips_svr4_so_ops.in_dynsym_resolve_code == NULL) | |
1619 | { | |
1620 | mips_svr4_so_ops = svr4_so_ops; | |
1621 | mips_svr4_so_ops.in_dynsym_resolve_code | |
1622 | = mips_linux_in_dynsym_resolve_code; | |
1623 | } | |
1624 | set_solib_ops (gdbarch, &mips_svr4_so_ops); | |
822b6570 DJ |
1625 | |
1626 | set_gdbarch_write_pc (gdbarch, mips_linux_write_pc); | |
1627 | ||
4eb0ad19 DJ |
1628 | set_gdbarch_core_read_description (gdbarch, |
1629 | mips_linux_core_read_description); | |
1630 | ||
50e8a0d5 HZ |
1631 | set_gdbarch_regset_from_core_section (gdbarch, |
1632 | mips_linux_regset_from_core_section); | |
1633 | ||
232b8704 ME |
1634 | set_gdbarch_gdb_signal_from_target (gdbarch, |
1635 | mips_gdb_signal_from_target); | |
1636 | ||
eb14d406 SDJ |
1637 | set_gdbarch_gdb_signal_to_target (gdbarch, |
1638 | mips_gdb_signal_to_target); | |
1639 | ||
e38d4e1a DJ |
1640 | tdep->syscall_next_pc = mips_linux_syscall_next_pc; |
1641 | ||
822b6570 DJ |
1642 | if (tdesc_data) |
1643 | { | |
1644 | const struct tdesc_feature *feature; | |
1645 | ||
1646 | /* If we have target-described registers, then we can safely | |
1647 | reserve a number for MIPS_RESTART_REGNUM (whether it is | |
1648 | described or not). */ | |
1649 | gdb_assert (gdbarch_num_regs (gdbarch) <= MIPS_RESTART_REGNUM); | |
1650 | set_gdbarch_num_regs (gdbarch, MIPS_RESTART_REGNUM + 1); | |
cf233303 | 1651 | set_gdbarch_num_pseudo_regs (gdbarch, MIPS_RESTART_REGNUM + 1); |
822b6570 DJ |
1652 | |
1653 | /* If it's present, then assign it to the reserved number. */ | |
1654 | feature = tdesc_find_feature (info.target_desc, | |
1655 | "org.gnu.gdb.mips.linux"); | |
1656 | if (feature != NULL) | |
1657 | tdesc_numbered_register (feature, tdesc_data, MIPS_RESTART_REGNUM, | |
1658 | "restart"); | |
1659 | } | |
19ed69dd KB |
1660 | } |
1661 | ||
63807e1d PA |
1662 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
1663 | extern initialize_file_ftype _initialize_mips_linux_tdep; | |
1664 | ||
2aa830e4 | 1665 | void |
d1bacddc | 1666 | _initialize_mips_linux_tdep (void) |
2aa830e4 | 1667 | { |
96f026fc KB |
1668 | const struct bfd_arch_info *arch_info; |
1669 | ||
96f026fc KB |
1670 | for (arch_info = bfd_lookup_arch (bfd_arch_mips, 0); |
1671 | arch_info != NULL; | |
1672 | arch_info = arch_info->next) | |
1673 | { | |
295093a4 MS |
1674 | gdbarch_register_osabi (bfd_arch_mips, arch_info->mach, |
1675 | GDB_OSABI_LINUX, | |
96f026fc KB |
1676 | mips_linux_init_abi); |
1677 | } | |
2aa830e4 | 1678 | } |