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75c9abc6 | 1 | /* Target-dependent code for GNU/Linux on MIPS processors. |
a094c6fb | 2 | |
ecd75fc8 | 3 | Copyright (C) 2001-2014 Free Software Foundation, Inc. |
2aa830e4 DJ |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
2aa830e4 DJ |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
2aa830e4 DJ |
19 | |
20 | #include "defs.h" | |
21 | #include "gdbcore.h" | |
22 | #include "target.h" | |
23 | #include "solib-svr4.h" | |
19ed69dd | 24 | #include "osabi.h" |
96f026fc | 25 | #include "mips-tdep.h" |
0e9f083f | 26 | #include <string.h> |
96f026fc | 27 | #include "gdb_assert.h" |
6de918a6 | 28 | #include "frame.h" |
2fdf551c | 29 | #include "regcache.h" |
5792a79b DJ |
30 | #include "trad-frame.h" |
31 | #include "tramp-frame.h" | |
e6bb342a | 32 | #include "gdbtypes.h" |
3e5d3a5a | 33 | #include "objfiles.h" |
5ea03926 | 34 | #include "solib.h" |
7d522c90 | 35 | #include "solist.h" |
982e9687 | 36 | #include "symtab.h" |
822b6570 | 37 | #include "target-descriptions.h" |
50e8a0d5 | 38 | #include "regset.h" |
d37eb719 | 39 | #include "mips-linux-tdep.h" |
db5f024e | 40 | #include "glibc-tdep.h" |
a5ee0f0c | 41 | #include "linux-tdep.h" |
385203ed | 42 | #include "xml-syscall.h" |
232b8704 | 43 | #include "gdb_signals.h" |
2aa830e4 | 44 | |
7d522c90 DJ |
45 | static struct target_so_ops mips_svr4_so_ops; |
46 | ||
eb14d406 SDJ |
47 | /* This enum represents the signals' numbers on the MIPS |
48 | architecture. It just contains the signal definitions which are | |
49 | different from the generic implementation. | |
50 | ||
51 | It is derived from the file <arch/mips/include/uapi/asm/signal.h>, | |
52 | from the Linux kernel tree. */ | |
53 | ||
54 | enum | |
55 | { | |
56 | MIPS_LINUX_SIGEMT = 7, | |
57 | MIPS_LINUX_SIGBUS = 10, | |
58 | MIPS_LINUX_SIGSYS = 12, | |
59 | MIPS_LINUX_SIGUSR1 = 16, | |
60 | MIPS_LINUX_SIGUSR2 = 17, | |
61 | MIPS_LINUX_SIGCHLD = 18, | |
62 | MIPS_LINUX_SIGCLD = MIPS_LINUX_SIGCHLD, | |
63 | MIPS_LINUX_SIGPWR = 19, | |
64 | MIPS_LINUX_SIGWINCH = 20, | |
65 | MIPS_LINUX_SIGURG = 21, | |
66 | MIPS_LINUX_SIGIO = 22, | |
67 | MIPS_LINUX_SIGPOLL = MIPS_LINUX_SIGIO, | |
68 | MIPS_LINUX_SIGSTOP = 23, | |
69 | MIPS_LINUX_SIGTSTP = 24, | |
70 | MIPS_LINUX_SIGCONT = 25, | |
71 | MIPS_LINUX_SIGTTIN = 26, | |
72 | MIPS_LINUX_SIGTTOU = 27, | |
73 | MIPS_LINUX_SIGVTALRM = 28, | |
74 | MIPS_LINUX_SIGPROF = 29, | |
75 | MIPS_LINUX_SIGXCPU = 30, | |
76 | MIPS_LINUX_SIGXFSZ = 31, | |
77 | ||
78 | MIPS_LINUX_SIGRTMIN = 32, | |
79 | MIPS_LINUX_SIGRT64 = 64, | |
80 | MIPS_LINUX_SIGRTMAX = 127, | |
81 | }; | |
82 | ||
2aa830e4 | 83 | /* Figure out where the longjmp will land. |
295093a4 MS |
84 | We expect the first arg to be a pointer to the jmp_buf structure |
85 | from which we extract the pc (MIPS_LINUX_JB_PC) that we will land | |
86 | at. The pc is copied into PC. This routine returns 1 on | |
87 | success. */ | |
2aa830e4 | 88 | |
19ed69dd KB |
89 | #define MIPS_LINUX_JB_ELEMENT_SIZE 4 |
90 | #define MIPS_LINUX_JB_PC 0 | |
91 | ||
92 | static int | |
60ade65d | 93 | mips_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
2aa830e4 DJ |
94 | { |
95 | CORE_ADDR jb_addr; | |
2eb4d78b | 96 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 97 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
e362b510 | 98 | gdb_byte buf[gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT]; |
2aa830e4 | 99 | |
60ade65d | 100 | jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM); |
2aa830e4 | 101 | |
7d266584 MR |
102 | if (target_read_memory ((jb_addr |
103 | + MIPS_LINUX_JB_PC * MIPS_LINUX_JB_ELEMENT_SIZE), | |
2eb4d78b | 104 | buf, gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT)) |
2aa830e4 DJ |
105 | return 0; |
106 | ||
819844ad | 107 | *pc = extract_unsigned_integer (buf, |
e17a4113 UW |
108 | gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT, |
109 | byte_order); | |
2aa830e4 DJ |
110 | |
111 | return 1; | |
112 | } | |
113 | ||
4246e332 | 114 | /* Transform the bits comprising a 32-bit register to the right size |
23a6d369 AC |
115 | for regcache_raw_supply(). This is needed when mips_isa_regsize() |
116 | is 8. */ | |
96f026fc KB |
117 | |
118 | static void | |
28f5035f | 119 | supply_32bit_reg (struct regcache *regcache, int regnum, const void *addr) |
96f026fc | 120 | { |
e17a4113 UW |
121 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
122 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
d37eb719 | 123 | gdb_byte buf[MAX_REGISTER_SIZE]; |
e17a4113 | 124 | store_signed_integer (buf, register_size (gdbarch, regnum), byte_order, |
7d266584 | 125 | extract_signed_integer (addr, 4, byte_order)); |
28f5035f | 126 | regcache_raw_supply (regcache, regnum, buf); |
96f026fc KB |
127 | } |
128 | ||
2aa830e4 DJ |
129 | /* Unpack an elf_gregset_t into GDB's register cache. */ |
130 | ||
d37eb719 | 131 | void |
28f5035f UW |
132 | mips_supply_gregset (struct regcache *regcache, |
133 | const mips_elf_gregset_t *gregsetp) | |
2aa830e4 DJ |
134 | { |
135 | int regi; | |
28f5035f | 136 | const mips_elf_greg_t *regp = *gregsetp; |
d9d9c31f | 137 | char zerobuf[MAX_REGISTER_SIZE]; |
2eb4d78b | 138 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
bf072999 | 139 | |
d9d9c31f | 140 | memset (zerobuf, 0, MAX_REGISTER_SIZE); |
2aa830e4 | 141 | |
822b6570 | 142 | for (regi = EF_REG0 + 1; regi <= EF_REG31; regi++) |
28f5035f | 143 | supply_32bit_reg (regcache, regi - EF_REG0, regp + regi); |
2aa830e4 | 144 | |
2eb4d78b | 145 | if (mips_linux_restart_reg_p (gdbarch)) |
822b6570 DJ |
146 | supply_32bit_reg (regcache, MIPS_RESTART_REGNUM, regp + EF_REG0); |
147 | ||
2eb4d78b UW |
148 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->lo, regp + EF_LO); |
149 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->hi, regp + EF_HI); | |
56cea623 | 150 | |
2eb4d78b | 151 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->pc, |
28f5035f | 152 | regp + EF_CP0_EPC); |
2eb4d78b | 153 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->badvaddr, |
28f5035f UW |
154 | regp + EF_CP0_BADVADDR); |
155 | supply_32bit_reg (regcache, MIPS_PS_REGNUM, regp + EF_CP0_STATUS); | |
2eb4d78b | 156 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->cause, |
28f5035f | 157 | regp + EF_CP0_CAUSE); |
2aa830e4 | 158 | |
1faeff08 | 159 | /* Fill the inaccessible zero register with zero. */ |
822b6570 | 160 | regcache_raw_supply (regcache, MIPS_ZERO_REGNUM, zerobuf); |
2aa830e4 DJ |
161 | } |
162 | ||
50e8a0d5 HZ |
163 | static void |
164 | mips_supply_gregset_wrapper (const struct regset *regset, | |
7d266584 MR |
165 | struct regcache *regcache, |
166 | int regnum, const void *gregs, size_t len) | |
50e8a0d5 HZ |
167 | { |
168 | gdb_assert (len == sizeof (mips_elf_gregset_t)); | |
169 | ||
170 | mips_supply_gregset (regcache, (const mips_elf_gregset_t *)gregs); | |
171 | } | |
172 | ||
2aa830e4 DJ |
173 | /* Pack our registers (or one register) into an elf_gregset_t. */ |
174 | ||
d37eb719 | 175 | void |
28f5035f UW |
176 | mips_fill_gregset (const struct regcache *regcache, |
177 | mips_elf_gregset_t *gregsetp, int regno) | |
2aa830e4 | 178 | { |
2eb4d78b | 179 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
2aa830e4 | 180 | int regaddr, regi; |
d37eb719 | 181 | mips_elf_greg_t *regp = *gregsetp; |
96f026fc | 182 | void *dst; |
2aa830e4 DJ |
183 | |
184 | if (regno == -1) | |
185 | { | |
d37eb719 | 186 | memset (regp, 0, sizeof (mips_elf_gregset_t)); |
822b6570 | 187 | for (regi = 1; regi < 32; regi++) |
28f5035f | 188 | mips_fill_gregset (regcache, gregsetp, regi); |
2eb4d78b UW |
189 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->lo); |
190 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->hi); | |
191 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->pc); | |
192 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->badvaddr); | |
28f5035f | 193 | mips_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM); |
2eb4d78b | 194 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->cause); |
822b6570 | 195 | mips_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM); |
2aa830e4 DJ |
196 | return; |
197 | } | |
198 | ||
822b6570 | 199 | if (regno > 0 && regno < 32) |
2aa830e4 | 200 | { |
2aa830e4 | 201 | dst = regp + regno + EF_REG0; |
28f5035f | 202 | regcache_raw_collect (regcache, regno, dst); |
2aa830e4 DJ |
203 | return; |
204 | } | |
205 | ||
2eb4d78b UW |
206 | if (regno == mips_regnum (gdbarch)->lo) |
207 | regaddr = EF_LO; | |
208 | else if (regno == mips_regnum (gdbarch)->hi) | |
56cea623 | 209 | regaddr = EF_HI; |
2eb4d78b | 210 | else if (regno == mips_regnum (gdbarch)->pc) |
56cea623 | 211 | regaddr = EF_CP0_EPC; |
2eb4d78b | 212 | else if (regno == mips_regnum (gdbarch)->badvaddr) |
56cea623 | 213 | regaddr = EF_CP0_BADVADDR; |
24e05951 | 214 | else if (regno == MIPS_PS_REGNUM) |
56cea623 | 215 | regaddr = EF_CP0_STATUS; |
2eb4d78b | 216 | else if (regno == mips_regnum (gdbarch)->cause) |
56cea623 | 217 | regaddr = EF_CP0_CAUSE; |
2eb4d78b | 218 | else if (mips_linux_restart_reg_p (gdbarch) |
822b6570 DJ |
219 | && regno == MIPS_RESTART_REGNUM) |
220 | regaddr = EF_REG0; | |
56cea623 AC |
221 | else |
222 | regaddr = -1; | |
2aa830e4 DJ |
223 | |
224 | if (regaddr != -1) | |
225 | { | |
2aa830e4 | 226 | dst = regp + regaddr; |
28f5035f | 227 | regcache_raw_collect (regcache, regno, dst); |
2aa830e4 DJ |
228 | } |
229 | } | |
230 | ||
50e8a0d5 HZ |
231 | static void |
232 | mips_fill_gregset_wrapper (const struct regset *regset, | |
233 | const struct regcache *regcache, | |
234 | int regnum, void *gregs, size_t len) | |
235 | { | |
236 | gdb_assert (len == sizeof (mips_elf_gregset_t)); | |
237 | ||
238 | mips_fill_gregset (regcache, (mips_elf_gregset_t *)gregs, regnum); | |
239 | } | |
240 | ||
2aa830e4 DJ |
241 | /* Likewise, unpack an elf_fpregset_t. */ |
242 | ||
d37eb719 | 243 | void |
28f5035f UW |
244 | mips_supply_fpregset (struct regcache *regcache, |
245 | const mips_elf_fpregset_t *fpregsetp) | |
2aa830e4 | 246 | { |
2eb4d78b | 247 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
52f0bd74 | 248 | int regi; |
d9d9c31f | 249 | char zerobuf[MAX_REGISTER_SIZE]; |
bf072999 | 250 | |
d9d9c31f | 251 | memset (zerobuf, 0, MAX_REGISTER_SIZE); |
2aa830e4 DJ |
252 | |
253 | for (regi = 0; regi < 32; regi++) | |
3e8c568d | 254 | regcache_raw_supply (regcache, |
2eb4d78b | 255 | gdbarch_fp0_regnum (gdbarch) + regi, |
3e8c568d | 256 | *fpregsetp + regi); |
2aa830e4 | 257 | |
28f5035f | 258 | regcache_raw_supply (regcache, |
2eb4d78b | 259 | mips_regnum (gdbarch)->fp_control_status, |
28f5035f | 260 | *fpregsetp + 32); |
2aa830e4 | 261 | |
295093a4 | 262 | /* FIXME: how can we supply FCRIR? The ABI doesn't tell us. */ |
28f5035f | 263 | regcache_raw_supply (regcache, |
2eb4d78b | 264 | mips_regnum (gdbarch)->fp_implementation_revision, |
23a6d369 | 265 | zerobuf); |
2aa830e4 DJ |
266 | } |
267 | ||
50e8a0d5 HZ |
268 | static void |
269 | mips_supply_fpregset_wrapper (const struct regset *regset, | |
7d266584 MR |
270 | struct regcache *regcache, |
271 | int regnum, const void *gregs, size_t len) | |
50e8a0d5 HZ |
272 | { |
273 | gdb_assert (len == sizeof (mips_elf_fpregset_t)); | |
274 | ||
275 | mips_supply_fpregset (regcache, (const mips_elf_fpregset_t *)gregs); | |
276 | } | |
277 | ||
2aa830e4 DJ |
278 | /* Likewise, pack one or all floating point registers into an |
279 | elf_fpregset_t. */ | |
280 | ||
d37eb719 | 281 | void |
28f5035f UW |
282 | mips_fill_fpregset (const struct regcache *regcache, |
283 | mips_elf_fpregset_t *fpregsetp, int regno) | |
2aa830e4 | 284 | { |
2eb4d78b | 285 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
22e048c9 | 286 | char *to; |
2aa830e4 | 287 | |
2eb4d78b UW |
288 | if ((regno >= gdbarch_fp0_regnum (gdbarch)) |
289 | && (regno < gdbarch_fp0_regnum (gdbarch) + 32)) | |
2aa830e4 | 290 | { |
2eb4d78b | 291 | to = (char *) (*fpregsetp + regno - gdbarch_fp0_regnum (gdbarch)); |
28f5035f | 292 | regcache_raw_collect (regcache, regno, to); |
2aa830e4 | 293 | } |
2eb4d78b | 294 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
2aa830e4 | 295 | { |
2aa830e4 | 296 | to = (char *) (*fpregsetp + 32); |
28f5035f | 297 | regcache_raw_collect (regcache, regno, to); |
2aa830e4 DJ |
298 | } |
299 | else if (regno == -1) | |
300 | { | |
301 | int regi; | |
302 | ||
303 | for (regi = 0; regi < 32; regi++) | |
3e8c568d | 304 | mips_fill_fpregset (regcache, fpregsetp, |
2eb4d78b | 305 | gdbarch_fp0_regnum (gdbarch) + regi); |
28f5035f | 306 | mips_fill_fpregset (regcache, fpregsetp, |
2eb4d78b | 307 | mips_regnum (gdbarch)->fp_control_status); |
2aa830e4 DJ |
308 | } |
309 | } | |
310 | ||
50e8a0d5 HZ |
311 | static void |
312 | mips_fill_fpregset_wrapper (const struct regset *regset, | |
313 | const struct regcache *regcache, | |
314 | int regnum, void *gregs, size_t len) | |
315 | { | |
316 | gdb_assert (len == sizeof (mips_elf_fpregset_t)); | |
317 | ||
318 | mips_fill_fpregset (regcache, (mips_elf_fpregset_t *)gregs, regnum); | |
319 | } | |
320 | ||
96f026fc KB |
321 | /* Support for 64-bit ABIs. */ |
322 | ||
96f026fc | 323 | /* Figure out where the longjmp will land. |
295093a4 MS |
324 | We expect the first arg to be a pointer to the jmp_buf structure |
325 | from which we extract the pc (MIPS_LINUX_JB_PC) that we will land | |
326 | at. The pc is copied into PC. This routine returns 1 on | |
327 | success. */ | |
96f026fc KB |
328 | |
329 | /* Details about jmp_buf. */ | |
330 | ||
331 | #define MIPS64_LINUX_JB_PC 0 | |
332 | ||
333 | static int | |
60ade65d | 334 | mips64_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
96f026fc KB |
335 | { |
336 | CORE_ADDR jb_addr; | |
2eb4d78b | 337 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 338 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2eb4d78b UW |
339 | void *buf = alloca (gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT); |
340 | int element_size = gdbarch_ptr_bit (gdbarch) == 32 ? 4 : 8; | |
96f026fc | 341 | |
60ade65d | 342 | jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM); |
96f026fc KB |
343 | |
344 | if (target_read_memory (jb_addr + MIPS64_LINUX_JB_PC * element_size, | |
819844ad | 345 | buf, |
2eb4d78b | 346 | gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT)) |
96f026fc KB |
347 | return 0; |
348 | ||
819844ad | 349 | *pc = extract_unsigned_integer (buf, |
e17a4113 UW |
350 | gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT, |
351 | byte_order); | |
96f026fc KB |
352 | |
353 | return 1; | |
354 | } | |
355 | ||
d37eb719 DJ |
356 | /* Register set support functions. These operate on standard 64-bit |
357 | regsets, but work whether the target is 32-bit or 64-bit. A 32-bit | |
358 | target will still use the 64-bit format for PTRACE_GETREGS. */ | |
359 | ||
360 | /* Supply a 64-bit register. */ | |
96f026fc | 361 | |
63807e1d | 362 | static void |
28f5035f UW |
363 | supply_64bit_reg (struct regcache *regcache, int regnum, |
364 | const gdb_byte *buf) | |
d37eb719 | 365 | { |
2eb4d78b UW |
366 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
367 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG | |
368 | && register_size (gdbarch, regnum) == 4) | |
28f5035f | 369 | regcache_raw_supply (regcache, regnum, buf + 4); |
d37eb719 | 370 | else |
28f5035f | 371 | regcache_raw_supply (regcache, regnum, buf); |
d37eb719 DJ |
372 | } |
373 | ||
374 | /* Unpack a 64-bit elf_gregset_t into GDB's register cache. */ | |
375 | ||
376 | void | |
28f5035f UW |
377 | mips64_supply_gregset (struct regcache *regcache, |
378 | const mips64_elf_gregset_t *gregsetp) | |
96f026fc KB |
379 | { |
380 | int regi; | |
28f5035f | 381 | const mips64_elf_greg_t *regp = *gregsetp; |
d37eb719 | 382 | gdb_byte zerobuf[MAX_REGISTER_SIZE]; |
2eb4d78b | 383 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
96f026fc | 384 | |
d9d9c31f | 385 | memset (zerobuf, 0, MAX_REGISTER_SIZE); |
96f026fc | 386 | |
822b6570 | 387 | for (regi = MIPS64_EF_REG0 + 1; regi <= MIPS64_EF_REG31; regi++) |
28f5035f | 388 | supply_64bit_reg (regcache, regi - MIPS64_EF_REG0, |
7d266584 | 389 | (const gdb_byte *) (regp + regi)); |
28f5035f | 390 | |
2eb4d78b | 391 | if (mips_linux_restart_reg_p (gdbarch)) |
822b6570 | 392 | supply_64bit_reg (regcache, MIPS_RESTART_REGNUM, |
7d266584 | 393 | (const gdb_byte *) (regp + MIPS64_EF_REG0)); |
822b6570 | 394 | |
2eb4d78b | 395 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->lo, |
28f5035f | 396 | (const gdb_byte *) (regp + MIPS64_EF_LO)); |
2eb4d78b | 397 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->hi, |
28f5035f UW |
398 | (const gdb_byte *) (regp + MIPS64_EF_HI)); |
399 | ||
2eb4d78b | 400 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->pc, |
28f5035f | 401 | (const gdb_byte *) (regp + MIPS64_EF_CP0_EPC)); |
2eb4d78b | 402 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->badvaddr, |
28f5035f UW |
403 | (const gdb_byte *) (regp + MIPS64_EF_CP0_BADVADDR)); |
404 | supply_64bit_reg (regcache, MIPS_PS_REGNUM, | |
405 | (const gdb_byte *) (regp + MIPS64_EF_CP0_STATUS)); | |
2eb4d78b | 406 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->cause, |
28f5035f | 407 | (const gdb_byte *) (regp + MIPS64_EF_CP0_CAUSE)); |
96f026fc | 408 | |
1faeff08 | 409 | /* Fill the inaccessible zero register with zero. */ |
822b6570 | 410 | regcache_raw_supply (regcache, MIPS_ZERO_REGNUM, zerobuf); |
96f026fc KB |
411 | } |
412 | ||
50e8a0d5 HZ |
413 | static void |
414 | mips64_supply_gregset_wrapper (const struct regset *regset, | |
7d266584 MR |
415 | struct regcache *regcache, |
416 | int regnum, const void *gregs, size_t len) | |
50e8a0d5 HZ |
417 | { |
418 | gdb_assert (len == sizeof (mips64_elf_gregset_t)); | |
419 | ||
420 | mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *)gregs); | |
421 | } | |
422 | ||
d37eb719 | 423 | /* Pack our registers (or one register) into a 64-bit elf_gregset_t. */ |
96f026fc | 424 | |
d37eb719 | 425 | void |
28f5035f UW |
426 | mips64_fill_gregset (const struct regcache *regcache, |
427 | mips64_elf_gregset_t *gregsetp, int regno) | |
96f026fc | 428 | { |
2eb4d78b | 429 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
e17a4113 | 430 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
96f026fc KB |
431 | int regaddr, regi; |
432 | mips64_elf_greg_t *regp = *gregsetp; | |
2ba93934 | 433 | void *dst; |
96f026fc KB |
434 | |
435 | if (regno == -1) | |
436 | { | |
437 | memset (regp, 0, sizeof (mips64_elf_gregset_t)); | |
822b6570 | 438 | for (regi = 1; regi < 32; regi++) |
7d266584 | 439 | mips64_fill_gregset (regcache, gregsetp, regi); |
2eb4d78b UW |
440 | mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->lo); |
441 | mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->hi); | |
442 | mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->pc); | |
025bb325 MS |
443 | mips64_fill_gregset (regcache, gregsetp, |
444 | mips_regnum (gdbarch)->badvaddr); | |
28f5035f | 445 | mips64_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM); |
2eb4d78b | 446 | mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->cause); |
822b6570 | 447 | mips64_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM); |
96f026fc KB |
448 | return; |
449 | } | |
450 | ||
822b6570 | 451 | if (regno > 0 && regno < 32) |
d37eb719 | 452 | regaddr = regno + MIPS64_EF_REG0; |
2eb4d78b | 453 | else if (regno == mips_regnum (gdbarch)->lo) |
56cea623 | 454 | regaddr = MIPS64_EF_LO; |
2eb4d78b | 455 | else if (regno == mips_regnum (gdbarch)->hi) |
56cea623 | 456 | regaddr = MIPS64_EF_HI; |
2eb4d78b | 457 | else if (regno == mips_regnum (gdbarch)->pc) |
56cea623 | 458 | regaddr = MIPS64_EF_CP0_EPC; |
2eb4d78b | 459 | else if (regno == mips_regnum (gdbarch)->badvaddr) |
56cea623 | 460 | regaddr = MIPS64_EF_CP0_BADVADDR; |
24e05951 | 461 | else if (regno == MIPS_PS_REGNUM) |
56cea623 | 462 | regaddr = MIPS64_EF_CP0_STATUS; |
2eb4d78b | 463 | else if (regno == mips_regnum (gdbarch)->cause) |
56cea623 | 464 | regaddr = MIPS64_EF_CP0_CAUSE; |
2eb4d78b | 465 | else if (mips_linux_restart_reg_p (gdbarch) |
822b6570 DJ |
466 | && regno == MIPS_RESTART_REGNUM) |
467 | regaddr = MIPS64_EF_REG0; | |
56cea623 AC |
468 | else |
469 | regaddr = -1; | |
96f026fc KB |
470 | |
471 | if (regaddr != -1) | |
472 | { | |
d37eb719 DJ |
473 | gdb_byte buf[MAX_REGISTER_SIZE]; |
474 | LONGEST val; | |
475 | ||
28f5035f | 476 | regcache_raw_collect (regcache, regno, buf); |
e17a4113 UW |
477 | val = extract_signed_integer (buf, register_size (gdbarch, regno), |
478 | byte_order); | |
96f026fc | 479 | dst = regp + regaddr; |
e17a4113 | 480 | store_signed_integer (dst, 8, byte_order, val); |
96f026fc KB |
481 | } |
482 | } | |
483 | ||
50e8a0d5 HZ |
484 | static void |
485 | mips64_fill_gregset_wrapper (const struct regset *regset, | |
486 | const struct regcache *regcache, | |
487 | int regnum, void *gregs, size_t len) | |
488 | { | |
489 | gdb_assert (len == sizeof (mips64_elf_gregset_t)); | |
490 | ||
491 | mips64_fill_gregset (regcache, (mips64_elf_gregset_t *)gregs, regnum); | |
492 | } | |
493 | ||
96f026fc KB |
494 | /* Likewise, unpack an elf_fpregset_t. */ |
495 | ||
d37eb719 | 496 | void |
28f5035f UW |
497 | mips64_supply_fpregset (struct regcache *regcache, |
498 | const mips64_elf_fpregset_t *fpregsetp) | |
96f026fc | 499 | { |
2eb4d78b | 500 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
52f0bd74 | 501 | int regi; |
96f026fc | 502 | |
d37eb719 DJ |
503 | /* See mips_linux_o32_sigframe_init for a description of the |
504 | peculiar FP register layout. */ | |
2eb4d78b | 505 | if (register_size (gdbarch, gdbarch_fp0_regnum (gdbarch)) == 4) |
d37eb719 DJ |
506 | for (regi = 0; regi < 32; regi++) |
507 | { | |
7d266584 MR |
508 | const gdb_byte *reg_ptr |
509 | = (const gdb_byte *) (*fpregsetp + (regi & ~1)); | |
2eb4d78b | 510 | if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (regi & 1)) |
d37eb719 | 511 | reg_ptr += 4; |
3e8c568d | 512 | regcache_raw_supply (regcache, |
2eb4d78b | 513 | gdbarch_fp0_regnum (gdbarch) + regi, |
3e8c568d | 514 | reg_ptr); |
d37eb719 DJ |
515 | } |
516 | else | |
517 | for (regi = 0; regi < 32; regi++) | |
3e8c568d | 518 | regcache_raw_supply (regcache, |
2eb4d78b | 519 | gdbarch_fp0_regnum (gdbarch) + regi, |
7d266584 | 520 | (const char *) (*fpregsetp + regi)); |
d37eb719 | 521 | |
2eb4d78b | 522 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->fp_control_status, |
7d266584 | 523 | (const gdb_byte *) (*fpregsetp + 32)); |
d37eb719 DJ |
524 | |
525 | /* The ABI doesn't tell us how to supply FCRIR, and core dumps don't | |
526 | include it - but the result of PTRACE_GETFPREGS does. The best we | |
527 | can do is to assume that its value is present. */ | |
28f5035f | 528 | supply_32bit_reg (regcache, |
2eb4d78b | 529 | mips_regnum (gdbarch)->fp_implementation_revision, |
7d266584 | 530 | (const gdb_byte *) (*fpregsetp + 32) + 4); |
96f026fc KB |
531 | } |
532 | ||
50e8a0d5 HZ |
533 | static void |
534 | mips64_supply_fpregset_wrapper (const struct regset *regset, | |
7d266584 MR |
535 | struct regcache *regcache, |
536 | int regnum, const void *gregs, size_t len) | |
50e8a0d5 HZ |
537 | { |
538 | gdb_assert (len == sizeof (mips64_elf_fpregset_t)); | |
539 | ||
540 | mips64_supply_fpregset (regcache, (const mips64_elf_fpregset_t *)gregs); | |
541 | } | |
542 | ||
96f026fc KB |
543 | /* Likewise, pack one or all floating point registers into an |
544 | elf_fpregset_t. */ | |
545 | ||
d37eb719 | 546 | void |
28f5035f UW |
547 | mips64_fill_fpregset (const struct regcache *regcache, |
548 | mips64_elf_fpregset_t *fpregsetp, int regno) | |
96f026fc | 549 | { |
2eb4d78b | 550 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
e17a4113 | 551 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d37eb719 | 552 | gdb_byte *to; |
96f026fc | 553 | |
2eb4d78b UW |
554 | if ((regno >= gdbarch_fp0_regnum (gdbarch)) |
555 | && (regno < gdbarch_fp0_regnum (gdbarch) + 32)) | |
96f026fc | 556 | { |
d37eb719 DJ |
557 | /* See mips_linux_o32_sigframe_init for a description of the |
558 | peculiar FP register layout. */ | |
2eb4d78b | 559 | if (register_size (gdbarch, regno) == 4) |
d37eb719 | 560 | { |
2eb4d78b | 561 | int regi = regno - gdbarch_fp0_regnum (gdbarch); |
d37eb719 DJ |
562 | |
563 | to = (gdb_byte *) (*fpregsetp + (regi & ~1)); | |
2eb4d78b | 564 | if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (regi & 1)) |
d37eb719 | 565 | to += 4; |
28f5035f | 566 | regcache_raw_collect (regcache, regno, to); |
d37eb719 DJ |
567 | } |
568 | else | |
569 | { | |
025bb325 MS |
570 | to = (gdb_byte *) (*fpregsetp + regno |
571 | - gdbarch_fp0_regnum (gdbarch)); | |
28f5035f | 572 | regcache_raw_collect (regcache, regno, to); |
d37eb719 | 573 | } |
96f026fc | 574 | } |
2eb4d78b | 575 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
96f026fc | 576 | { |
d37eb719 DJ |
577 | gdb_byte buf[MAX_REGISTER_SIZE]; |
578 | LONGEST val; | |
579 | ||
28f5035f | 580 | regcache_raw_collect (regcache, regno, buf); |
e17a4113 UW |
581 | val = extract_signed_integer (buf, register_size (gdbarch, regno), |
582 | byte_order); | |
d37eb719 | 583 | to = (gdb_byte *) (*fpregsetp + 32); |
e17a4113 | 584 | store_signed_integer (to, 4, byte_order, val); |
d37eb719 | 585 | } |
2eb4d78b | 586 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
d37eb719 DJ |
587 | { |
588 | gdb_byte buf[MAX_REGISTER_SIZE]; | |
589 | LONGEST val; | |
590 | ||
28f5035f | 591 | regcache_raw_collect (regcache, regno, buf); |
e17a4113 UW |
592 | val = extract_signed_integer (buf, register_size (gdbarch, regno), |
593 | byte_order); | |
d37eb719 | 594 | to = (gdb_byte *) (*fpregsetp + 32) + 4; |
e17a4113 | 595 | store_signed_integer (to, 4, byte_order, val); |
96f026fc KB |
596 | } |
597 | else if (regno == -1) | |
598 | { | |
599 | int regi; | |
600 | ||
601 | for (regi = 0; regi < 32; regi++) | |
3e8c568d | 602 | mips64_fill_fpregset (regcache, fpregsetp, |
2eb4d78b | 603 | gdbarch_fp0_regnum (gdbarch) + regi); |
28f5035f | 604 | mips64_fill_fpregset (regcache, fpregsetp, |
2eb4d78b | 605 | mips_regnum (gdbarch)->fp_control_status); |
28f5035f | 606 | mips64_fill_fpregset (regcache, fpregsetp, |
7d266584 | 607 | mips_regnum (gdbarch)->fp_implementation_revision); |
96f026fc KB |
608 | } |
609 | } | |
610 | ||
50e8a0d5 HZ |
611 | static void |
612 | mips64_fill_fpregset_wrapper (const struct regset *regset, | |
613 | const struct regcache *regcache, | |
614 | int regnum, void *gregs, size_t len) | |
615 | { | |
616 | gdb_assert (len == sizeof (mips64_elf_fpregset_t)); | |
96f026fc | 617 | |
50e8a0d5 HZ |
618 | mips64_fill_fpregset (regcache, (mips64_elf_fpregset_t *)gregs, regnum); |
619 | } | |
2aa830e4 | 620 | |
693be288 | 621 | static const struct regset * |
50e8a0d5 | 622 | mips_linux_regset_from_core_section (struct gdbarch *gdbarch, |
7d266584 | 623 | const char *sect_name, size_t sect_size) |
2aa830e4 | 624 | { |
50e8a0d5 | 625 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
d37eb719 DJ |
626 | mips_elf_gregset_t gregset; |
627 | mips_elf_fpregset_t fpregset; | |
96f026fc KB |
628 | mips64_elf_gregset_t gregset64; |
629 | mips64_elf_fpregset_t fpregset64; | |
2aa830e4 | 630 | |
50e8a0d5 | 631 | if (strcmp (sect_name, ".reg") == 0) |
2aa830e4 | 632 | { |
50e8a0d5 | 633 | if (sect_size == sizeof (gregset)) |
2aa830e4 | 634 | { |
50e8a0d5 HZ |
635 | if (tdep->gregset == NULL) |
636 | tdep->gregset = regset_alloc (gdbarch, | |
7d266584 MR |
637 | mips_supply_gregset_wrapper, |
638 | mips_fill_gregset_wrapper); | |
50e8a0d5 | 639 | return tdep->gregset; |
96f026fc | 640 | } |
50e8a0d5 | 641 | else if (sect_size == sizeof (gregset64)) |
96f026fc | 642 | { |
50e8a0d5 HZ |
643 | if (tdep->gregset64 == NULL) |
644 | tdep->gregset64 = regset_alloc (gdbarch, | |
7d266584 MR |
645 | mips64_supply_gregset_wrapper, |
646 | mips64_fill_gregset_wrapper); | |
50e8a0d5 | 647 | return tdep->gregset64; |
2aa830e4 DJ |
648 | } |
649 | else | |
650 | { | |
8a3fe4f8 | 651 | warning (_("wrong size gregset struct in core file")); |
2aa830e4 DJ |
652 | } |
653 | } | |
50e8a0d5 | 654 | else if (strcmp (sect_name, ".reg2") == 0) |
2aa830e4 | 655 | { |
50e8a0d5 | 656 | if (sect_size == sizeof (fpregset)) |
2aa830e4 | 657 | { |
50e8a0d5 HZ |
658 | if (tdep->fpregset == NULL) |
659 | tdep->fpregset = regset_alloc (gdbarch, | |
7d266584 MR |
660 | mips_supply_fpregset_wrapper, |
661 | mips_fill_fpregset_wrapper); | |
50e8a0d5 | 662 | return tdep->fpregset; |
96f026fc | 663 | } |
50e8a0d5 | 664 | else if (sect_size == sizeof (fpregset64)) |
96f026fc | 665 | { |
50e8a0d5 HZ |
666 | if (tdep->fpregset64 == NULL) |
667 | tdep->fpregset64 = regset_alloc (gdbarch, | |
7d266584 MR |
668 | mips64_supply_fpregset_wrapper, |
669 | mips64_fill_fpregset_wrapper); | |
50e8a0d5 | 670 | return tdep->fpregset64; |
2aa830e4 DJ |
671 | } |
672 | else | |
673 | { | |
8a3fe4f8 | 674 | warning (_("wrong size fpregset struct in core file")); |
2aa830e4 DJ |
675 | } |
676 | } | |
2aa830e4 | 677 | |
50e8a0d5 HZ |
678 | return NULL; |
679 | } | |
2aa830e4 | 680 | |
4eb0ad19 DJ |
681 | static const struct target_desc * |
682 | mips_linux_core_read_description (struct gdbarch *gdbarch, | |
683 | struct target_ops *target, | |
684 | bfd *abfd) | |
685 | { | |
686 | asection *section = bfd_get_section_by_name (abfd, ".reg"); | |
687 | if (! section) | |
688 | return NULL; | |
689 | ||
690 | switch (bfd_section_size (abfd, section)) | |
691 | { | |
692 | case sizeof (mips_elf_gregset_t): | |
693 | return mips_tdesc_gp32; | |
694 | ||
695 | case sizeof (mips64_elf_gregset_t): | |
696 | return mips_tdesc_gp64; | |
697 | ||
698 | default: | |
699 | return NULL; | |
700 | } | |
701 | } | |
702 | ||
96f026fc | 703 | |
295093a4 | 704 | /* Check the code at PC for a dynamic linker lazy resolution stub. |
3e5d3a5a MR |
705 | GNU ld for MIPS has put lazy resolution stubs into a ".MIPS.stubs" |
706 | section uniformly since version 2.15. If the pc is in that section, | |
707 | then we are in such a stub. Before that ".stub" was used in 32-bit | |
708 | ELF binaries, however we do not bother checking for that since we | |
709 | have never had and that case should be extremely rare these days. | |
710 | Instead we pattern-match on the code generated by GNU ld. They look | |
711 | like this: | |
6de918a6 DJ |
712 | |
713 | lw t9,0x8010(gp) | |
714 | addu t7,ra | |
715 | jalr t9,ra | |
716 | addiu t8,zero,INDEX | |
717 | ||
3e5d3a5a MR |
718 | (with the appropriate doubleword instructions for N64). As any lazy |
719 | resolution stubs in microMIPS binaries will always be in a | |
720 | ".MIPS.stubs" section we only ever verify standard MIPS patterns. */ | |
6de918a6 DJ |
721 | |
722 | static int | |
3e5d3a5a | 723 | mips_linux_in_dynsym_stub (CORE_ADDR pc) |
6de918a6 | 724 | { |
e362b510 | 725 | gdb_byte buf[28], *p; |
6de918a6 | 726 | ULONGEST insn, insn1; |
f5656ead TT |
727 | int n64 = (mips_abi (target_gdbarch ()) == MIPS_ABI_N64); |
728 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); | |
6de918a6 | 729 | |
3e5d3a5a MR |
730 | if (in_mips_stubs_section (pc)) |
731 | return 1; | |
732 | ||
6de918a6 DJ |
733 | read_memory (pc - 12, buf, 28); |
734 | ||
735 | if (n64) | |
736 | { | |
737 | /* ld t9,0x8010(gp) */ | |
738 | insn1 = 0xdf998010; | |
739 | } | |
740 | else | |
741 | { | |
742 | /* lw t9,0x8010(gp) */ | |
743 | insn1 = 0x8f998010; | |
744 | } | |
745 | ||
746 | p = buf + 12; | |
747 | while (p >= buf) | |
748 | { | |
e17a4113 | 749 | insn = extract_unsigned_integer (p, 4, byte_order); |
6de918a6 DJ |
750 | if (insn == insn1) |
751 | break; | |
752 | p -= 4; | |
753 | } | |
754 | if (p < buf) | |
755 | return 0; | |
756 | ||
e17a4113 | 757 | insn = extract_unsigned_integer (p + 4, 4, byte_order); |
6de918a6 DJ |
758 | if (n64) |
759 | { | |
760 | /* daddu t7,ra */ | |
761 | if (insn != 0x03e0782d) | |
762 | return 0; | |
763 | } | |
764 | else | |
765 | { | |
766 | /* addu t7,ra */ | |
767 | if (insn != 0x03e07821) | |
768 | return 0; | |
769 | } | |
295093a4 | 770 | |
e17a4113 | 771 | insn = extract_unsigned_integer (p + 8, 4, byte_order); |
6de918a6 DJ |
772 | /* jalr t9,ra */ |
773 | if (insn != 0x0320f809) | |
774 | return 0; | |
775 | ||
e17a4113 | 776 | insn = extract_unsigned_integer (p + 12, 4, byte_order); |
6de918a6 DJ |
777 | if (n64) |
778 | { | |
779 | /* daddiu t8,zero,0 */ | |
780 | if ((insn & 0xffff0000) != 0x64180000) | |
781 | return 0; | |
782 | } | |
783 | else | |
784 | { | |
785 | /* addiu t8,zero,0 */ | |
786 | if ((insn & 0xffff0000) != 0x24180000) | |
787 | return 0; | |
788 | } | |
789 | ||
3e5d3a5a | 790 | return 1; |
6de918a6 DJ |
791 | } |
792 | ||
295093a4 | 793 | /* Return non-zero iff PC belongs to the dynamic linker resolution |
db5f024e | 794 | code, a PLT entry, or a lazy binding stub. */ |
6de918a6 | 795 | |
7d522c90 | 796 | static int |
6de918a6 DJ |
797 | mips_linux_in_dynsym_resolve_code (CORE_ADDR pc) |
798 | { | |
295093a4 | 799 | /* Check whether PC is in the dynamic linker. This also checks |
db5f024e | 800 | whether it is in the .plt section, used by non-PIC executables. */ |
7d522c90 | 801 | if (svr4_in_dynsym_resolve_code (pc)) |
6de918a6 DJ |
802 | return 1; |
803 | ||
3e5d3a5a MR |
804 | /* Likewise for the stubs. They live in the .MIPS.stubs section these |
805 | days, so we check if the PC is within, than fall back to a pattern | |
806 | match. */ | |
807 | if (mips_linux_in_dynsym_stub (pc)) | |
6de918a6 DJ |
808 | return 1; |
809 | ||
810 | return 0; | |
811 | } | |
812 | ||
813 | /* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c, | |
814 | and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc | |
815 | implementation of this triggers at "fixup" from the same objfile as | |
c4c5b7ba | 816 | "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at |
db5f024e DJ |
817 | "__dl_runtime_resolve" directly. An unresolved lazy binding |
818 | stub will point to _dl_runtime_resolve, which will first call | |
c4c5b7ba AC |
819 | __dl_runtime_resolve, and then pass control to the resolved |
820 | function. */ | |
6de918a6 DJ |
821 | |
822 | static CORE_ADDR | |
823 | mips_linux_skip_resolver (struct gdbarch *gdbarch, CORE_ADDR pc) | |
824 | { | |
825 | struct minimal_symbol *resolver; | |
826 | ||
827 | resolver = lookup_minimal_symbol ("__dl_runtime_resolve", NULL, NULL); | |
828 | ||
829 | if (resolver && SYMBOL_VALUE_ADDRESS (resolver) == pc) | |
c7ce8faa | 830 | return frame_unwind_caller_pc (get_current_frame ()); |
6de918a6 | 831 | |
db5f024e | 832 | return glibc_skip_solib_resolver (gdbarch, pc); |
295093a4 | 833 | } |
6de918a6 | 834 | |
5792a79b DJ |
835 | /* Signal trampoline support. There are four supported layouts for a |
836 | signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and | |
837 | n64 rt_sigframe. We handle them all independently; not the most | |
838 | efficient way, but simplest. First, declare all the unwinders. */ | |
839 | ||
840 | static void mips_linux_o32_sigframe_init (const struct tramp_frame *self, | |
b8a22b94 | 841 | struct frame_info *this_frame, |
5792a79b DJ |
842 | struct trad_frame_cache *this_cache, |
843 | CORE_ADDR func); | |
844 | ||
845 | static void mips_linux_n32n64_sigframe_init (const struct tramp_frame *self, | |
b8a22b94 | 846 | struct frame_info *this_frame, |
5792a79b DJ |
847 | struct trad_frame_cache *this_cache, |
848 | CORE_ADDR func); | |
849 | ||
850 | #define MIPS_NR_LINUX 4000 | |
851 | #define MIPS_NR_N64_LINUX 5000 | |
852 | #define MIPS_NR_N32_LINUX 6000 | |
853 | ||
854 | #define MIPS_NR_sigreturn MIPS_NR_LINUX + 119 | |
855 | #define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193 | |
856 | #define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211 | |
857 | #define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211 | |
858 | ||
859 | #define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn | |
860 | #define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn | |
861 | #define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn | |
862 | #define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn | |
863 | #define MIPS_INST_SYSCALL 0x0000000c | |
864 | ||
2cd8546d AC |
865 | static const struct tramp_frame mips_linux_o32_sigframe = { |
866 | SIGTRAMP_FRAME, | |
5792a79b | 867 | 4, |
2cd8546d AC |
868 | { |
869 | { MIPS_INST_LI_V0_SIGRETURN, -1 }, | |
870 | { MIPS_INST_SYSCALL, -1 }, | |
871 | { TRAMP_SENTINEL_INSN, -1 } | |
872 | }, | |
5792a79b DJ |
873 | mips_linux_o32_sigframe_init |
874 | }; | |
875 | ||
2cd8546d AC |
876 | static const struct tramp_frame mips_linux_o32_rt_sigframe = { |
877 | SIGTRAMP_FRAME, | |
5792a79b | 878 | 4, |
2cd8546d AC |
879 | { |
880 | { MIPS_INST_LI_V0_RT_SIGRETURN, -1 }, | |
881 | { MIPS_INST_SYSCALL, -1 }, | |
882 | { TRAMP_SENTINEL_INSN, -1 } }, | |
5792a79b DJ |
883 | mips_linux_o32_sigframe_init |
884 | }; | |
885 | ||
2cd8546d AC |
886 | static const struct tramp_frame mips_linux_n32_rt_sigframe = { |
887 | SIGTRAMP_FRAME, | |
5792a79b | 888 | 4, |
2cd8546d AC |
889 | { |
890 | { MIPS_INST_LI_V0_N32_RT_SIGRETURN, -1 }, | |
891 | { MIPS_INST_SYSCALL, -1 }, | |
892 | { TRAMP_SENTINEL_INSN, -1 } | |
893 | }, | |
5792a79b DJ |
894 | mips_linux_n32n64_sigframe_init |
895 | }; | |
896 | ||
2cd8546d AC |
897 | static const struct tramp_frame mips_linux_n64_rt_sigframe = { |
898 | SIGTRAMP_FRAME, | |
5792a79b | 899 | 4, |
fcbd8a5c TS |
900 | { |
901 | { MIPS_INST_LI_V0_N64_RT_SIGRETURN, -1 }, | |
902 | { MIPS_INST_SYSCALL, -1 }, | |
903 | { TRAMP_SENTINEL_INSN, -1 } | |
904 | }, | |
5792a79b DJ |
905 | mips_linux_n32n64_sigframe_init |
906 | }; | |
907 | ||
908 | /* *INDENT-OFF* */ | |
909 | /* The unwinder for o32 signal frames. The legacy structures look | |
910 | like this: | |
911 | ||
912 | struct sigframe { | |
913 | u32 sf_ass[4]; [argument save space for o32] | |
eb195664 | 914 | u32 sf_code[2]; [signal trampoline or fill] |
5792a79b DJ |
915 | struct sigcontext sf_sc; |
916 | sigset_t sf_mask; | |
917 | }; | |
918 | ||
d0e64392 MR |
919 | Pre-2.6.12 sigcontext: |
920 | ||
5792a79b DJ |
921 | struct sigcontext { |
922 | unsigned int sc_regmask; [Unused] | |
923 | unsigned int sc_status; | |
924 | unsigned long long sc_pc; | |
925 | unsigned long long sc_regs[32]; | |
926 | unsigned long long sc_fpregs[32]; | |
927 | unsigned int sc_ownedfp; | |
928 | unsigned int sc_fpc_csr; | |
929 | unsigned int sc_fpc_eir; [Unused] | |
930 | unsigned int sc_used_math; | |
931 | unsigned int sc_ssflags; [Unused] | |
932 | [Alignment hole of four bytes] | |
933 | unsigned long long sc_mdhi; | |
934 | unsigned long long sc_mdlo; | |
935 | ||
936 | unsigned int sc_cause; [Unused] | |
937 | unsigned int sc_badvaddr; [Unused] | |
938 | ||
939 | unsigned long sc_sigset[4]; [kernel's sigset_t] | |
940 | }; | |
941 | ||
d0e64392 MR |
942 | Post-2.6.12 sigcontext (SmartMIPS/DSP support added): |
943 | ||
944 | struct sigcontext { | |
945 | unsigned int sc_regmask; [Unused] | |
946 | unsigned int sc_status; [Unused] | |
947 | unsigned long long sc_pc; | |
948 | unsigned long long sc_regs[32]; | |
949 | unsigned long long sc_fpregs[32]; | |
950 | unsigned int sc_acx; | |
951 | unsigned int sc_fpc_csr; | |
952 | unsigned int sc_fpc_eir; [Unused] | |
953 | unsigned int sc_used_math; | |
954 | unsigned int sc_dsp; | |
955 | [Alignment hole of four bytes] | |
956 | unsigned long long sc_mdhi; | |
957 | unsigned long long sc_mdlo; | |
958 | unsigned long sc_hi1; | |
959 | unsigned long sc_lo1; | |
960 | unsigned long sc_hi2; | |
961 | unsigned long sc_lo2; | |
962 | unsigned long sc_hi3; | |
963 | unsigned long sc_lo3; | |
964 | }; | |
965 | ||
5792a79b DJ |
966 | The RT signal frames look like this: |
967 | ||
968 | struct rt_sigframe { | |
969 | u32 rs_ass[4]; [argument save space for o32] | |
eb195664 | 970 | u32 rs_code[2] [signal trampoline or fill] |
5792a79b DJ |
971 | struct siginfo rs_info; |
972 | struct ucontext rs_uc; | |
973 | }; | |
974 | ||
975 | struct ucontext { | |
976 | unsigned long uc_flags; | |
977 | struct ucontext *uc_link; | |
978 | stack_t uc_stack; | |
979 | [Alignment hole of four bytes] | |
980 | struct sigcontext uc_mcontext; | |
981 | sigset_t uc_sigmask; | |
982 | }; */ | |
983 | /* *INDENT-ON* */ | |
984 | ||
5792a79b DJ |
985 | #define SIGFRAME_SIGCONTEXT_OFFSET (6 * 4) |
986 | ||
987 | #define RTSIGFRAME_SIGINFO_SIZE 128 | |
988 | #define STACK_T_SIZE (3 * 4) | |
989 | #define UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + STACK_T_SIZE + 4) | |
990 | #define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ | |
991 | + RTSIGFRAME_SIGINFO_SIZE \ | |
992 | + UCONTEXT_SIGCONTEXT_OFFSET) | |
993 | ||
994 | #define SIGCONTEXT_PC (1 * 8) | |
995 | #define SIGCONTEXT_REGS (2 * 8) | |
996 | #define SIGCONTEXT_FPREGS (34 * 8) | |
997 | #define SIGCONTEXT_FPCSR (66 * 8 + 4) | |
d0e64392 | 998 | #define SIGCONTEXT_DSPCTL (68 * 8 + 0) |
5792a79b DJ |
999 | #define SIGCONTEXT_HI (69 * 8) |
1000 | #define SIGCONTEXT_LO (70 * 8) | |
1001 | #define SIGCONTEXT_CAUSE (71 * 8 + 0) | |
1002 | #define SIGCONTEXT_BADVADDR (71 * 8 + 4) | |
d0e64392 MR |
1003 | #define SIGCONTEXT_HI1 (71 * 8 + 0) |
1004 | #define SIGCONTEXT_LO1 (71 * 8 + 4) | |
1005 | #define SIGCONTEXT_HI2 (72 * 8 + 0) | |
1006 | #define SIGCONTEXT_LO2 (72 * 8 + 4) | |
1007 | #define SIGCONTEXT_HI3 (73 * 8 + 0) | |
1008 | #define SIGCONTEXT_LO3 (73 * 8 + 4) | |
5792a79b DJ |
1009 | |
1010 | #define SIGCONTEXT_REG_SIZE 8 | |
1011 | ||
1012 | static void | |
1013 | mips_linux_o32_sigframe_init (const struct tramp_frame *self, | |
b8a22b94 | 1014 | struct frame_info *this_frame, |
5792a79b DJ |
1015 | struct trad_frame_cache *this_cache, |
1016 | CORE_ADDR func) | |
1017 | { | |
b8a22b94 | 1018 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
22e048c9 | 1019 | int ireg; |
eb195664 DD |
1020 | CORE_ADDR frame_sp = get_frame_sp (this_frame); |
1021 | CORE_ADDR sigcontext_base; | |
2eb4d78b | 1022 | const struct mips_regnum *regs = mips_regnum (gdbarch); |
37c4d197 | 1023 | CORE_ADDR regs_base; |
5792a79b DJ |
1024 | |
1025 | if (self == &mips_linux_o32_sigframe) | |
eb195664 | 1026 | sigcontext_base = frame_sp + SIGFRAME_SIGCONTEXT_OFFSET; |
5792a79b | 1027 | else |
eb195664 | 1028 | sigcontext_base = frame_sp + RTSIGFRAME_SIGCONTEXT_OFFSET; |
295093a4 MS |
1029 | |
1030 | /* I'm not proud of this hack. Eventually we will have the | |
1031 | infrastructure to indicate the size of saved registers on a | |
1032 | per-frame basis, but right now we don't; the kernel saves eight | |
37c4d197 DJ |
1033 | bytes but we only want four. Use regs_base to access any |
1034 | 64-bit fields. */ | |
2eb4d78b | 1035 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
37c4d197 DJ |
1036 | regs_base = sigcontext_base + 4; |
1037 | else | |
1038 | regs_base = sigcontext_base; | |
5792a79b | 1039 | |
2eb4d78b | 1040 | if (mips_linux_restart_reg_p (gdbarch)) |
822b6570 DJ |
1041 | trad_frame_set_reg_addr (this_cache, |
1042 | (MIPS_RESTART_REGNUM | |
2eb4d78b | 1043 | + gdbarch_num_regs (gdbarch)), |
822b6570 | 1044 | regs_base + SIGCONTEXT_REGS); |
5792a79b DJ |
1045 | |
1046 | for (ireg = 1; ireg < 32; ireg++) | |
295093a4 | 1047 | trad_frame_set_reg_addr (this_cache, |
7d266584 MR |
1048 | (ireg + MIPS_ZERO_REGNUM |
1049 | + gdbarch_num_regs (gdbarch)), | |
1050 | (regs_base + SIGCONTEXT_REGS | |
1051 | + ireg * SIGCONTEXT_REG_SIZE)); | |
5792a79b | 1052 | |
37c4d197 DJ |
1053 | /* The way that floating point registers are saved, unfortunately, |
1054 | depends on the architecture the kernel is built for. For the r3000 and | |
1055 | tx39, four bytes of each register are at the beginning of each of the | |
1056 | 32 eight byte slots. For everything else, the registers are saved | |
1057 | using double precision; only the even-numbered slots are initialized, | |
1058 | and the high bits are the odd-numbered register. Assume the latter | |
1059 | layout, since we can't tell, and it's much more common. Which bits are | |
1060 | the "high" bits depends on endianness. */ | |
5792a79b | 1061 | for (ireg = 0; ireg < 32; ireg++) |
2eb4d78b | 1062 | if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (ireg & 1)) |
f57d151a | 1063 | trad_frame_set_reg_addr (this_cache, |
7d266584 MR |
1064 | ireg + regs->fp0 + gdbarch_num_regs (gdbarch), |
1065 | (sigcontext_base + SIGCONTEXT_FPREGS + 4 | |
1066 | + (ireg & ~1) * SIGCONTEXT_REG_SIZE)); | |
37c4d197 | 1067 | else |
f57d151a | 1068 | trad_frame_set_reg_addr (this_cache, |
7d266584 MR |
1069 | ireg + regs->fp0 + gdbarch_num_regs (gdbarch), |
1070 | (sigcontext_base + SIGCONTEXT_FPREGS | |
1071 | + (ireg & ~1) * SIGCONTEXT_REG_SIZE)); | |
5792a79b | 1072 | |
f57d151a | 1073 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1074 | regs->pc + gdbarch_num_regs (gdbarch), |
37c4d197 | 1075 | regs_base + SIGCONTEXT_PC); |
5792a79b | 1076 | |
295093a4 | 1077 | trad_frame_set_reg_addr (this_cache, |
7d266584 MR |
1078 | (regs->fp_control_status |
1079 | + gdbarch_num_regs (gdbarch)), | |
5792a79b | 1080 | sigcontext_base + SIGCONTEXT_FPCSR); |
d0e64392 MR |
1081 | |
1082 | if (regs->dspctl != -1) | |
1083 | trad_frame_set_reg_addr (this_cache, | |
1084 | regs->dspctl + gdbarch_num_regs (gdbarch), | |
1085 | sigcontext_base + SIGCONTEXT_DSPCTL); | |
1086 | ||
f57d151a | 1087 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1088 | regs->hi + gdbarch_num_regs (gdbarch), |
37c4d197 | 1089 | regs_base + SIGCONTEXT_HI); |
f57d151a | 1090 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1091 | regs->lo + gdbarch_num_regs (gdbarch), |
37c4d197 | 1092 | regs_base + SIGCONTEXT_LO); |
d0e64392 MR |
1093 | |
1094 | if (regs->dspacc != -1) | |
1095 | { | |
1096 | trad_frame_set_reg_addr (this_cache, | |
1097 | regs->dspacc + 0 + gdbarch_num_regs (gdbarch), | |
1098 | sigcontext_base + SIGCONTEXT_HI1); | |
1099 | trad_frame_set_reg_addr (this_cache, | |
1100 | regs->dspacc + 1 + gdbarch_num_regs (gdbarch), | |
1101 | sigcontext_base + SIGCONTEXT_LO1); | |
1102 | trad_frame_set_reg_addr (this_cache, | |
1103 | regs->dspacc + 2 + gdbarch_num_regs (gdbarch), | |
1104 | sigcontext_base + SIGCONTEXT_HI2); | |
1105 | trad_frame_set_reg_addr (this_cache, | |
1106 | regs->dspacc + 3 + gdbarch_num_regs (gdbarch), | |
1107 | sigcontext_base + SIGCONTEXT_LO2); | |
1108 | trad_frame_set_reg_addr (this_cache, | |
1109 | regs->dspacc + 4 + gdbarch_num_regs (gdbarch), | |
1110 | sigcontext_base + SIGCONTEXT_HI3); | |
1111 | trad_frame_set_reg_addr (this_cache, | |
1112 | regs->dspacc + 5 + gdbarch_num_regs (gdbarch), | |
1113 | sigcontext_base + SIGCONTEXT_LO3); | |
1114 | } | |
1115 | else | |
1116 | { | |
1117 | trad_frame_set_reg_addr (this_cache, | |
1118 | regs->cause + gdbarch_num_regs (gdbarch), | |
1119 | sigcontext_base + SIGCONTEXT_CAUSE); | |
1120 | trad_frame_set_reg_addr (this_cache, | |
1121 | regs->badvaddr + gdbarch_num_regs (gdbarch), | |
1122 | sigcontext_base + SIGCONTEXT_BADVADDR); | |
1123 | } | |
5792a79b DJ |
1124 | |
1125 | /* Choice of the bottom of the sigframe is somewhat arbitrary. */ | |
eb195664 | 1126 | trad_frame_set_id (this_cache, frame_id_build (frame_sp, func)); |
5792a79b DJ |
1127 | } |
1128 | ||
1129 | /* *INDENT-OFF* */ | |
1130 | /* For N32/N64 things look different. There is no non-rt signal frame. | |
1131 | ||
1132 | struct rt_sigframe_n32 { | |
1133 | u32 rs_ass[4]; [ argument save space for o32 ] | |
eb195664 | 1134 | u32 rs_code[2]; [ signal trampoline or fill ] |
5792a79b DJ |
1135 | struct siginfo rs_info; |
1136 | struct ucontextn32 rs_uc; | |
1137 | }; | |
1138 | ||
1139 | struct ucontextn32 { | |
1140 | u32 uc_flags; | |
1141 | s32 uc_link; | |
1142 | stack32_t uc_stack; | |
1143 | struct sigcontext uc_mcontext; | |
1144 | sigset_t uc_sigmask; [ mask last for extensibility ] | |
1145 | }; | |
295093a4 | 1146 | |
e741f4d4 | 1147 | struct rt_sigframe { |
5792a79b DJ |
1148 | u32 rs_ass[4]; [ argument save space for o32 ] |
1149 | u32 rs_code[2]; [ signal trampoline ] | |
1150 | struct siginfo rs_info; | |
1151 | struct ucontext rs_uc; | |
1152 | }; | |
1153 | ||
1154 | struct ucontext { | |
1155 | unsigned long uc_flags; | |
1156 | struct ucontext *uc_link; | |
1157 | stack_t uc_stack; | |
1158 | struct sigcontext uc_mcontext; | |
1159 | sigset_t uc_sigmask; [ mask last for extensibility ] | |
1160 | }; | |
1161 | ||
1162 | And the sigcontext is different (this is for both n32 and n64): | |
1163 | ||
1164 | struct sigcontext { | |
1165 | unsigned long long sc_regs[32]; | |
1166 | unsigned long long sc_fpregs[32]; | |
1167 | unsigned long long sc_mdhi; | |
e741f4d4 DJ |
1168 | unsigned long long sc_hi1; |
1169 | unsigned long long sc_hi2; | |
1170 | unsigned long long sc_hi3; | |
5792a79b | 1171 | unsigned long long sc_mdlo; |
e741f4d4 DJ |
1172 | unsigned long long sc_lo1; |
1173 | unsigned long long sc_lo2; | |
1174 | unsigned long long sc_lo3; | |
5792a79b | 1175 | unsigned long long sc_pc; |
5792a79b | 1176 | unsigned int sc_fpc_csr; |
5792a79b | 1177 | unsigned int sc_used_math; |
e741f4d4 DJ |
1178 | unsigned int sc_dsp; |
1179 | unsigned int sc_reserved; | |
1180 | }; | |
1181 | ||
1182 | That is the post-2.6.12 definition of the 64-bit sigcontext; before | |
1183 | then, there were no hi1-hi3 or lo1-lo3. Cause and badvaddr were | |
1184 | included too. */ | |
5792a79b DJ |
1185 | /* *INDENT-ON* */ |
1186 | ||
1187 | #define N32_STACK_T_SIZE STACK_T_SIZE | |
1188 | #define N64_STACK_T_SIZE (2 * 8 + 4) | |
1189 | #define N32_UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + N32_STACK_T_SIZE + 4) | |
1190 | #define N64_UCONTEXT_SIGCONTEXT_OFFSET (2 * 8 + N64_STACK_T_SIZE + 4) | |
1191 | #define N32_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ | |
1192 | + RTSIGFRAME_SIGINFO_SIZE \ | |
1193 | + N32_UCONTEXT_SIGCONTEXT_OFFSET) | |
1194 | #define N64_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ | |
1195 | + RTSIGFRAME_SIGINFO_SIZE \ | |
1196 | + N64_UCONTEXT_SIGCONTEXT_OFFSET) | |
1197 | ||
1198 | #define N64_SIGCONTEXT_REGS (0 * 8) | |
1199 | #define N64_SIGCONTEXT_FPREGS (32 * 8) | |
1200 | #define N64_SIGCONTEXT_HI (64 * 8) | |
d0e64392 MR |
1201 | #define N64_SIGCONTEXT_HI1 (65 * 8) |
1202 | #define N64_SIGCONTEXT_HI2 (66 * 8) | |
1203 | #define N64_SIGCONTEXT_HI3 (67 * 8) | |
e741f4d4 | 1204 | #define N64_SIGCONTEXT_LO (68 * 8) |
d0e64392 MR |
1205 | #define N64_SIGCONTEXT_LO1 (69 * 8) |
1206 | #define N64_SIGCONTEXT_LO2 (70 * 8) | |
1207 | #define N64_SIGCONTEXT_LO3 (71 * 8) | |
e741f4d4 | 1208 | #define N64_SIGCONTEXT_PC (72 * 8) |
d0e64392 MR |
1209 | #define N64_SIGCONTEXT_FPCSR (73 * 8 + 0) |
1210 | #define N64_SIGCONTEXT_DSPCTL (74 * 8 + 0) | |
5792a79b DJ |
1211 | |
1212 | #define N64_SIGCONTEXT_REG_SIZE 8 | |
295093a4 | 1213 | |
5792a79b DJ |
1214 | static void |
1215 | mips_linux_n32n64_sigframe_init (const struct tramp_frame *self, | |
b8a22b94 | 1216 | struct frame_info *this_frame, |
5792a79b DJ |
1217 | struct trad_frame_cache *this_cache, |
1218 | CORE_ADDR func) | |
1219 | { | |
b8a22b94 | 1220 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
22e048c9 | 1221 | int ireg; |
eb195664 DD |
1222 | CORE_ADDR frame_sp = get_frame_sp (this_frame); |
1223 | CORE_ADDR sigcontext_base; | |
2eb4d78b | 1224 | const struct mips_regnum *regs = mips_regnum (gdbarch); |
5792a79b DJ |
1225 | |
1226 | if (self == &mips_linux_n32_rt_sigframe) | |
eb195664 | 1227 | sigcontext_base = frame_sp + N32_SIGFRAME_SIGCONTEXT_OFFSET; |
5792a79b | 1228 | else |
eb195664 | 1229 | sigcontext_base = frame_sp + N64_SIGFRAME_SIGCONTEXT_OFFSET; |
295093a4 | 1230 | |
2eb4d78b | 1231 | if (mips_linux_restart_reg_p (gdbarch)) |
822b6570 DJ |
1232 | trad_frame_set_reg_addr (this_cache, |
1233 | (MIPS_RESTART_REGNUM | |
2eb4d78b | 1234 | + gdbarch_num_regs (gdbarch)), |
822b6570 | 1235 | sigcontext_base + N64_SIGCONTEXT_REGS); |
5792a79b DJ |
1236 | |
1237 | for (ireg = 1; ireg < 32; ireg++) | |
295093a4 | 1238 | trad_frame_set_reg_addr (this_cache, |
7d266584 MR |
1239 | (ireg + MIPS_ZERO_REGNUM |
1240 | + gdbarch_num_regs (gdbarch)), | |
1241 | (sigcontext_base + N64_SIGCONTEXT_REGS | |
1242 | + ireg * N64_SIGCONTEXT_REG_SIZE)); | |
5792a79b DJ |
1243 | |
1244 | for (ireg = 0; ireg < 32; ireg++) | |
f57d151a | 1245 | trad_frame_set_reg_addr (this_cache, |
7d266584 MR |
1246 | ireg + regs->fp0 + gdbarch_num_regs (gdbarch), |
1247 | (sigcontext_base + N64_SIGCONTEXT_FPREGS | |
1248 | + ireg * N64_SIGCONTEXT_REG_SIZE)); | |
5792a79b | 1249 | |
f57d151a | 1250 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1251 | regs->pc + gdbarch_num_regs (gdbarch), |
5792a79b DJ |
1252 | sigcontext_base + N64_SIGCONTEXT_PC); |
1253 | ||
295093a4 | 1254 | trad_frame_set_reg_addr (this_cache, |
7d266584 MR |
1255 | (regs->fp_control_status |
1256 | + gdbarch_num_regs (gdbarch)), | |
5792a79b | 1257 | sigcontext_base + N64_SIGCONTEXT_FPCSR); |
d0e64392 | 1258 | |
f57d151a | 1259 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1260 | regs->hi + gdbarch_num_regs (gdbarch), |
5792a79b | 1261 | sigcontext_base + N64_SIGCONTEXT_HI); |
f57d151a | 1262 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1263 | regs->lo + gdbarch_num_regs (gdbarch), |
5792a79b | 1264 | sigcontext_base + N64_SIGCONTEXT_LO); |
5792a79b | 1265 | |
d0e64392 MR |
1266 | if (regs->dspacc != -1) |
1267 | { | |
1268 | trad_frame_set_reg_addr (this_cache, | |
1269 | regs->dspacc + 0 + gdbarch_num_regs (gdbarch), | |
1270 | sigcontext_base + N64_SIGCONTEXT_HI1); | |
1271 | trad_frame_set_reg_addr (this_cache, | |
1272 | regs->dspacc + 1 + gdbarch_num_regs (gdbarch), | |
1273 | sigcontext_base + N64_SIGCONTEXT_LO1); | |
1274 | trad_frame_set_reg_addr (this_cache, | |
1275 | regs->dspacc + 2 + gdbarch_num_regs (gdbarch), | |
1276 | sigcontext_base + N64_SIGCONTEXT_HI2); | |
1277 | trad_frame_set_reg_addr (this_cache, | |
1278 | regs->dspacc + 3 + gdbarch_num_regs (gdbarch), | |
1279 | sigcontext_base + N64_SIGCONTEXT_LO2); | |
1280 | trad_frame_set_reg_addr (this_cache, | |
1281 | regs->dspacc + 4 + gdbarch_num_regs (gdbarch), | |
1282 | sigcontext_base + N64_SIGCONTEXT_HI3); | |
1283 | trad_frame_set_reg_addr (this_cache, | |
1284 | regs->dspacc + 5 + gdbarch_num_regs (gdbarch), | |
1285 | sigcontext_base + N64_SIGCONTEXT_LO3); | |
1286 | } | |
1287 | if (regs->dspctl != -1) | |
1288 | trad_frame_set_reg_addr (this_cache, | |
1289 | regs->dspctl + gdbarch_num_regs (gdbarch), | |
1290 | sigcontext_base + N64_SIGCONTEXT_DSPCTL); | |
1291 | ||
5792a79b | 1292 | /* Choice of the bottom of the sigframe is somewhat arbitrary. */ |
eb195664 | 1293 | trad_frame_set_id (this_cache, frame_id_build (frame_sp, func)); |
5792a79b DJ |
1294 | } |
1295 | ||
5a439849 MR |
1296 | /* Implement the "write_pc" gdbarch method. */ |
1297 | ||
822b6570 | 1298 | static void |
61a1198a | 1299 | mips_linux_write_pc (struct regcache *regcache, CORE_ADDR pc) |
822b6570 | 1300 | { |
2eb4d78b | 1301 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
5a439849 MR |
1302 | |
1303 | mips_write_pc (regcache, pc); | |
822b6570 DJ |
1304 | |
1305 | /* Clear the syscall restart flag. */ | |
2eb4d78b | 1306 | if (mips_linux_restart_reg_p (gdbarch)) |
61a1198a | 1307 | regcache_cooked_write_unsigned (regcache, MIPS_RESTART_REGNUM, 0); |
822b6570 DJ |
1308 | } |
1309 | ||
1310 | /* Return 1 if MIPS_RESTART_REGNUM is usable. */ | |
1311 | ||
1312 | int | |
1313 | mips_linux_restart_reg_p (struct gdbarch *gdbarch) | |
1314 | { | |
1315 | /* If we do not have a target description with registers, then | |
1316 | MIPS_RESTART_REGNUM will not be included in the register set. */ | |
1317 | if (!tdesc_has_registers (gdbarch_target_desc (gdbarch))) | |
1318 | return 0; | |
1319 | ||
1320 | /* If we do, then MIPS_RESTART_REGNUM is safe to check; it will | |
1321 | either be GPR-sized or missing. */ | |
1322 | return register_size (gdbarch, MIPS_RESTART_REGNUM) > 0; | |
1323 | } | |
9f62d0e2 | 1324 | |
e38d4e1a DJ |
1325 | /* When FRAME is at a syscall instruction, return the PC of the next |
1326 | instruction to be executed. */ | |
1327 | ||
63807e1d | 1328 | static CORE_ADDR |
e38d4e1a DJ |
1329 | mips_linux_syscall_next_pc (struct frame_info *frame) |
1330 | { | |
1331 | CORE_ADDR pc = get_frame_pc (frame); | |
1332 | ULONGEST v0 = get_frame_register_unsigned (frame, MIPS_V0_REGNUM); | |
1333 | ||
1334 | /* If we are about to make a sigreturn syscall, use the unwinder to | |
1335 | decode the signal frame. */ | |
1336 | if (v0 == MIPS_NR_sigreturn | |
1337 | || v0 == MIPS_NR_rt_sigreturn | |
1338 | || v0 == MIPS_NR_N64_rt_sigreturn | |
1339 | || v0 == MIPS_NR_N32_rt_sigreturn) | |
c7ce8faa | 1340 | return frame_unwind_caller_pc (get_current_frame ()); |
e38d4e1a DJ |
1341 | |
1342 | return pc + 4; | |
1343 | } | |
1344 | ||
385203ed DD |
1345 | /* Return the current system call's number present in the |
1346 | v0 register. When the function fails, it returns -1. */ | |
1347 | ||
1348 | static LONGEST | |
1349 | mips_linux_get_syscall_number (struct gdbarch *gdbarch, | |
1350 | ptid_t ptid) | |
1351 | { | |
1352 | struct regcache *regcache = get_thread_regcache (ptid); | |
1353 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1354 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1355 | int regsize = register_size (gdbarch, MIPS_V0_REGNUM); | |
1356 | /* The content of a register */ | |
1357 | gdb_byte buf[8]; | |
1358 | /* The result */ | |
1359 | LONGEST ret; | |
1360 | ||
1361 | /* Make sure we're in a known ABI */ | |
1362 | gdb_assert (tdep->mips_abi == MIPS_ABI_O32 | |
1363 | || tdep->mips_abi == MIPS_ABI_N32 | |
1364 | || tdep->mips_abi == MIPS_ABI_N64); | |
1365 | ||
1366 | gdb_assert (regsize <= sizeof (buf)); | |
1367 | ||
1368 | /* Getting the system call number from the register. | |
1369 | syscall number is in v0 or $2. */ | |
1370 | regcache_cooked_read (regcache, MIPS_V0_REGNUM, buf); | |
1371 | ||
1372 | ret = extract_signed_integer (buf, regsize, byte_order); | |
1373 | ||
1374 | return ret; | |
1375 | } | |
1376 | ||
eb14d406 SDJ |
1377 | /* Implementation of `gdbarch_gdb_signal_to_target', as defined in |
1378 | gdbarch.h. */ | |
1379 | ||
1380 | static int | |
1381 | mips_gdb_signal_to_target (struct gdbarch *gdbarch, | |
1382 | enum gdb_signal signal) | |
1383 | { | |
1384 | switch (signal) | |
1385 | { | |
1386 | case GDB_SIGNAL_EMT: | |
1387 | return MIPS_LINUX_SIGEMT; | |
1388 | ||
1389 | case GDB_SIGNAL_BUS: | |
1390 | return MIPS_LINUX_SIGBUS; | |
1391 | ||
1392 | case GDB_SIGNAL_SYS: | |
1393 | return MIPS_LINUX_SIGSYS; | |
1394 | ||
1395 | case GDB_SIGNAL_USR1: | |
1396 | return MIPS_LINUX_SIGUSR1; | |
1397 | ||
1398 | case GDB_SIGNAL_USR2: | |
1399 | return MIPS_LINUX_SIGUSR2; | |
1400 | ||
1401 | case GDB_SIGNAL_CHLD: | |
1402 | return MIPS_LINUX_SIGCHLD; | |
1403 | ||
1404 | case GDB_SIGNAL_PWR: | |
1405 | return MIPS_LINUX_SIGPWR; | |
1406 | ||
1407 | case GDB_SIGNAL_WINCH: | |
1408 | return MIPS_LINUX_SIGWINCH; | |
1409 | ||
1410 | case GDB_SIGNAL_URG: | |
1411 | return MIPS_LINUX_SIGURG; | |
1412 | ||
1413 | case GDB_SIGNAL_IO: | |
1414 | return MIPS_LINUX_SIGIO; | |
1415 | ||
1416 | case GDB_SIGNAL_POLL: | |
1417 | return MIPS_LINUX_SIGPOLL; | |
1418 | ||
1419 | case GDB_SIGNAL_STOP: | |
1420 | return MIPS_LINUX_SIGSTOP; | |
1421 | ||
1422 | case GDB_SIGNAL_TSTP: | |
1423 | return MIPS_LINUX_SIGTSTP; | |
1424 | ||
1425 | case GDB_SIGNAL_CONT: | |
1426 | return MIPS_LINUX_SIGCONT; | |
1427 | ||
1428 | case GDB_SIGNAL_TTIN: | |
1429 | return MIPS_LINUX_SIGTTIN; | |
1430 | ||
1431 | case GDB_SIGNAL_TTOU: | |
1432 | return MIPS_LINUX_SIGTTOU; | |
1433 | ||
1434 | case GDB_SIGNAL_VTALRM: | |
1435 | return MIPS_LINUX_SIGVTALRM; | |
1436 | ||
1437 | case GDB_SIGNAL_PROF: | |
1438 | return MIPS_LINUX_SIGPROF; | |
1439 | ||
1440 | case GDB_SIGNAL_XCPU: | |
1441 | return MIPS_LINUX_SIGXCPU; | |
1442 | ||
1443 | case GDB_SIGNAL_XFSZ: | |
1444 | return MIPS_LINUX_SIGXFSZ; | |
1445 | ||
1446 | /* GDB_SIGNAL_REALTIME_32 is not continuous in <gdb/signals.def>, | |
1447 | therefore we have to handle it here. */ | |
1448 | case GDB_SIGNAL_REALTIME_32: | |
1449 | return MIPS_LINUX_SIGRTMIN; | |
1450 | } | |
1451 | ||
1452 | if (signal >= GDB_SIGNAL_REALTIME_33 | |
1453 | && signal <= GDB_SIGNAL_REALTIME_63) | |
1454 | { | |
1455 | int offset = signal - GDB_SIGNAL_REALTIME_33; | |
1456 | ||
1457 | return MIPS_LINUX_SIGRTMIN + 1 + offset; | |
1458 | } | |
1459 | else if (signal >= GDB_SIGNAL_REALTIME_64 | |
1460 | && signal <= GDB_SIGNAL_REALTIME_127) | |
1461 | { | |
1462 | int offset = signal - GDB_SIGNAL_REALTIME_64; | |
1463 | ||
1464 | return MIPS_LINUX_SIGRT64 + offset; | |
1465 | } | |
1466 | ||
1467 | return linux_gdb_signal_to_target (gdbarch, signal); | |
1468 | } | |
1469 | ||
7d266584 | 1470 | /* Translate signals based on MIPS signal values. |
232b8704 ME |
1471 | Adapted from gdb/common/signals.c. */ |
1472 | ||
1473 | static enum gdb_signal | |
eb14d406 | 1474 | mips_gdb_signal_from_target (struct gdbarch *gdbarch, int signal) |
232b8704 | 1475 | { |
eb14d406 | 1476 | switch (signal) |
232b8704 | 1477 | { |
eb14d406 | 1478 | case MIPS_LINUX_SIGEMT: |
232b8704 | 1479 | return GDB_SIGNAL_EMT; |
eb14d406 SDJ |
1480 | |
1481 | case MIPS_LINUX_SIGBUS: | |
232b8704 | 1482 | return GDB_SIGNAL_BUS; |
eb14d406 SDJ |
1483 | |
1484 | case MIPS_LINUX_SIGSYS: | |
232b8704 | 1485 | return GDB_SIGNAL_SYS; |
eb14d406 SDJ |
1486 | |
1487 | case MIPS_LINUX_SIGUSR1: | |
232b8704 | 1488 | return GDB_SIGNAL_USR1; |
eb14d406 SDJ |
1489 | |
1490 | case MIPS_LINUX_SIGUSR2: | |
232b8704 | 1491 | return GDB_SIGNAL_USR2; |
eb14d406 SDJ |
1492 | |
1493 | case MIPS_LINUX_SIGCHLD: | |
232b8704 | 1494 | return GDB_SIGNAL_CHLD; |
eb14d406 SDJ |
1495 | |
1496 | case MIPS_LINUX_SIGPWR: | |
232b8704 | 1497 | return GDB_SIGNAL_PWR; |
eb14d406 SDJ |
1498 | |
1499 | case MIPS_LINUX_SIGWINCH: | |
232b8704 | 1500 | return GDB_SIGNAL_WINCH; |
eb14d406 SDJ |
1501 | |
1502 | case MIPS_LINUX_SIGURG: | |
232b8704 | 1503 | return GDB_SIGNAL_URG; |
eb14d406 SDJ |
1504 | |
1505 | /* No way to differentiate between SIGIO and SIGPOLL. | |
1506 | Therefore, we just handle the first one. */ | |
1507 | case MIPS_LINUX_SIGIO: | |
1508 | return GDB_SIGNAL_IO; | |
1509 | ||
1510 | case MIPS_LINUX_SIGSTOP: | |
232b8704 | 1511 | return GDB_SIGNAL_STOP; |
eb14d406 SDJ |
1512 | |
1513 | case MIPS_LINUX_SIGTSTP: | |
232b8704 | 1514 | return GDB_SIGNAL_TSTP; |
eb14d406 SDJ |
1515 | |
1516 | case MIPS_LINUX_SIGCONT: | |
232b8704 | 1517 | return GDB_SIGNAL_CONT; |
eb14d406 SDJ |
1518 | |
1519 | case MIPS_LINUX_SIGTTIN: | |
232b8704 | 1520 | return GDB_SIGNAL_TTIN; |
eb14d406 SDJ |
1521 | |
1522 | case MIPS_LINUX_SIGTTOU: | |
232b8704 | 1523 | return GDB_SIGNAL_TTOU; |
eb14d406 SDJ |
1524 | |
1525 | case MIPS_LINUX_SIGVTALRM: | |
232b8704 | 1526 | return GDB_SIGNAL_VTALRM; |
eb14d406 SDJ |
1527 | |
1528 | case MIPS_LINUX_SIGPROF: | |
232b8704 | 1529 | return GDB_SIGNAL_PROF; |
eb14d406 SDJ |
1530 | |
1531 | case MIPS_LINUX_SIGXCPU: | |
232b8704 | 1532 | return GDB_SIGNAL_XCPU; |
eb14d406 SDJ |
1533 | |
1534 | case MIPS_LINUX_SIGXFSZ: | |
232b8704 | 1535 | return GDB_SIGNAL_XFSZ; |
eb14d406 | 1536 | } |
232b8704 | 1537 | |
eb14d406 | 1538 | if (signal >= MIPS_LINUX_SIGRTMIN && signal <= MIPS_LINUX_SIGRTMAX) |
232b8704 ME |
1539 | { |
1540 | /* GDB_SIGNAL_REALTIME values are not contiguous, map parts of | |
1541 | the MIPS block to the respective GDB_SIGNAL_REALTIME blocks. */ | |
eb14d406 SDJ |
1542 | int offset = signal - MIPS_LINUX_SIGRTMIN; |
1543 | ||
1544 | if (offset == 0) | |
232b8704 | 1545 | return GDB_SIGNAL_REALTIME_32; |
eb14d406 SDJ |
1546 | else if (offset < 32) |
1547 | return (enum gdb_signal) (offset - 1 | |
1548 | + (int) GDB_SIGNAL_REALTIME_33); | |
232b8704 | 1549 | else |
eb14d406 SDJ |
1550 | return (enum gdb_signal) (offset - 32 |
1551 | + (int) GDB_SIGNAL_REALTIME_64); | |
232b8704 ME |
1552 | } |
1553 | ||
eb14d406 | 1554 | return linux_gdb_signal_from_target (gdbarch, signal); |
232b8704 ME |
1555 | } |
1556 | ||
5792a79b DJ |
1557 | /* Initialize one of the GNU/Linux OS ABIs. */ |
1558 | ||
19ed69dd | 1559 | static void |
295093a4 MS |
1560 | mips_linux_init_abi (struct gdbarch_info info, |
1561 | struct gdbarch *gdbarch) | |
19ed69dd | 1562 | { |
96f026fc KB |
1563 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1564 | enum mips_abi abi = mips_abi (gdbarch); | |
822b6570 | 1565 | struct tdesc_arch_data *tdesc_data = (void *) info.tdep_info; |
96f026fc | 1566 | |
a5ee0f0c PA |
1567 | linux_init_abi (info, gdbarch); |
1568 | ||
385203ed DD |
1569 | /* Get the syscall number from the arch's register. */ |
1570 | set_gdbarch_get_syscall_number (gdbarch, mips_linux_get_syscall_number); | |
1571 | ||
96f026fc KB |
1572 | switch (abi) |
1573 | { | |
1574 | case MIPS_ABI_O32: | |
1575 | set_gdbarch_get_longjmp_target (gdbarch, | |
7d266584 | 1576 | mips_linux_get_longjmp_target); |
96f026fc | 1577 | set_solib_svr4_fetch_link_map_offsets |
76a9d10f | 1578 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); |
fb2be677 AC |
1579 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_sigframe); |
1580 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_rt_sigframe); | |
385203ed | 1581 | set_xml_syscall_file_name ("syscalls/mips-o32-linux.xml"); |
96f026fc KB |
1582 | break; |
1583 | case MIPS_ABI_N32: | |
1584 | set_gdbarch_get_longjmp_target (gdbarch, | |
7d266584 | 1585 | mips_linux_get_longjmp_target); |
96f026fc | 1586 | set_solib_svr4_fetch_link_map_offsets |
76a9d10f | 1587 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); |
d05f6826 DJ |
1588 | set_gdbarch_long_double_bit (gdbarch, 128); |
1589 | /* These floatformats should probably be renamed. MIPS uses | |
1590 | the same 128-bit IEEE floating point format that IA-64 uses, | |
1591 | except that the quiet/signalling NaN bit is reversed (GDB | |
1592 | does not distinguish between quiet and signalling NaNs). */ | |
8da61cc4 | 1593 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); |
fb2be677 | 1594 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n32_rt_sigframe); |
385203ed | 1595 | set_xml_syscall_file_name ("syscalls/mips-n32-linux.xml"); |
96f026fc KB |
1596 | break; |
1597 | case MIPS_ABI_N64: | |
1598 | set_gdbarch_get_longjmp_target (gdbarch, | |
7d266584 | 1599 | mips64_linux_get_longjmp_target); |
96f026fc | 1600 | set_solib_svr4_fetch_link_map_offsets |
76a9d10f | 1601 | (gdbarch, svr4_lp64_fetch_link_map_offsets); |
d05f6826 DJ |
1602 | set_gdbarch_long_double_bit (gdbarch, 128); |
1603 | /* These floatformats should probably be renamed. MIPS uses | |
1604 | the same 128-bit IEEE floating point format that IA-64 uses, | |
1605 | except that the quiet/signalling NaN bit is reversed (GDB | |
1606 | does not distinguish between quiet and signalling NaNs). */ | |
8da61cc4 | 1607 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); |
fb2be677 | 1608 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n64_rt_sigframe); |
385203ed | 1609 | set_xml_syscall_file_name ("syscalls/mips-n64-linux.xml"); |
96f026fc KB |
1610 | break; |
1611 | default: | |
96f026fc KB |
1612 | break; |
1613 | } | |
6de918a6 DJ |
1614 | |
1615 | set_gdbarch_skip_solib_resolver (gdbarch, mips_linux_skip_resolver); | |
1616 | ||
0d0266c6 | 1617 | set_gdbarch_software_single_step (gdbarch, mips_software_single_step); |
b2756930 KB |
1618 | |
1619 | /* Enable TLS support. */ | |
1620 | set_gdbarch_fetch_tls_load_module_address (gdbarch, | |
7d266584 | 1621 | svr4_fetch_objfile_link_map); |
7d522c90 DJ |
1622 | |
1623 | /* Initialize this lazily, to avoid an initialization order | |
1624 | dependency on solib-svr4.c's _initialize routine. */ | |
1625 | if (mips_svr4_so_ops.in_dynsym_resolve_code == NULL) | |
1626 | { | |
1627 | mips_svr4_so_ops = svr4_so_ops; | |
1628 | mips_svr4_so_ops.in_dynsym_resolve_code | |
1629 | = mips_linux_in_dynsym_resolve_code; | |
1630 | } | |
1631 | set_solib_ops (gdbarch, &mips_svr4_so_ops); | |
822b6570 DJ |
1632 | |
1633 | set_gdbarch_write_pc (gdbarch, mips_linux_write_pc); | |
1634 | ||
4eb0ad19 DJ |
1635 | set_gdbarch_core_read_description (gdbarch, |
1636 | mips_linux_core_read_description); | |
1637 | ||
50e8a0d5 HZ |
1638 | set_gdbarch_regset_from_core_section (gdbarch, |
1639 | mips_linux_regset_from_core_section); | |
1640 | ||
232b8704 ME |
1641 | set_gdbarch_gdb_signal_from_target (gdbarch, |
1642 | mips_gdb_signal_from_target); | |
1643 | ||
eb14d406 SDJ |
1644 | set_gdbarch_gdb_signal_to_target (gdbarch, |
1645 | mips_gdb_signal_to_target); | |
1646 | ||
e38d4e1a DJ |
1647 | tdep->syscall_next_pc = mips_linux_syscall_next_pc; |
1648 | ||
822b6570 DJ |
1649 | if (tdesc_data) |
1650 | { | |
1651 | const struct tdesc_feature *feature; | |
1652 | ||
1653 | /* If we have target-described registers, then we can safely | |
1654 | reserve a number for MIPS_RESTART_REGNUM (whether it is | |
1655 | described or not). */ | |
1656 | gdb_assert (gdbarch_num_regs (gdbarch) <= MIPS_RESTART_REGNUM); | |
1657 | set_gdbarch_num_regs (gdbarch, MIPS_RESTART_REGNUM + 1); | |
cf233303 | 1658 | set_gdbarch_num_pseudo_regs (gdbarch, MIPS_RESTART_REGNUM + 1); |
822b6570 DJ |
1659 | |
1660 | /* If it's present, then assign it to the reserved number. */ | |
1661 | feature = tdesc_find_feature (info.target_desc, | |
1662 | "org.gnu.gdb.mips.linux"); | |
1663 | if (feature != NULL) | |
1664 | tdesc_numbered_register (feature, tdesc_data, MIPS_RESTART_REGNUM, | |
1665 | "restart"); | |
1666 | } | |
19ed69dd KB |
1667 | } |
1668 | ||
63807e1d PA |
1669 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
1670 | extern initialize_file_ftype _initialize_mips_linux_tdep; | |
1671 | ||
2aa830e4 | 1672 | void |
d1bacddc | 1673 | _initialize_mips_linux_tdep (void) |
2aa830e4 | 1674 | { |
96f026fc KB |
1675 | const struct bfd_arch_info *arch_info; |
1676 | ||
96f026fc KB |
1677 | for (arch_info = bfd_lookup_arch (bfd_arch_mips, 0); |
1678 | arch_info != NULL; | |
1679 | arch_info = arch_info->next) | |
1680 | { | |
295093a4 MS |
1681 | gdbarch_register_osabi (bfd_arch_mips, arch_info->mach, |
1682 | GDB_OSABI_LINUX, | |
96f026fc KB |
1683 | mips_linux_init_abi); |
1684 | } | |
2aa830e4 | 1685 | } |