Commit | Line | Data |
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75c9abc6 | 1 | /* Target-dependent code for GNU/Linux on MIPS processors. |
a094c6fb | 2 | |
6aba47ca | 3 | Copyright (C) 2001, 2002, 2004, 2005, 2006, 2007 |
76a9d10f | 4 | Free Software Foundation, Inc. |
2aa830e4 DJ |
5 | |
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 10 | the Free Software Foundation; either version 3 of the License, or |
2aa830e4 DJ |
11 | (at your option) any later version. |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
2aa830e4 DJ |
20 | |
21 | #include "defs.h" | |
22 | #include "gdbcore.h" | |
23 | #include "target.h" | |
24 | #include "solib-svr4.h" | |
19ed69dd | 25 | #include "osabi.h" |
96f026fc | 26 | #include "mips-tdep.h" |
19ed69dd | 27 | #include "gdb_string.h" |
96f026fc | 28 | #include "gdb_assert.h" |
6de918a6 | 29 | #include "frame.h" |
2fdf551c | 30 | #include "regcache.h" |
5792a79b DJ |
31 | #include "trad-frame.h" |
32 | #include "tramp-frame.h" | |
e6bb342a | 33 | #include "gdbtypes.h" |
5ea03926 | 34 | #include "solib.h" |
7d522c90 DJ |
35 | #include "solib-svr4.h" |
36 | #include "solist.h" | |
982e9687 | 37 | #include "symtab.h" |
822b6570 | 38 | #include "target-descriptions.h" |
d37eb719 | 39 | #include "mips-linux-tdep.h" |
2aa830e4 | 40 | |
7d522c90 DJ |
41 | static struct target_so_ops mips_svr4_so_ops; |
42 | ||
2aa830e4 | 43 | /* Figure out where the longjmp will land. |
295093a4 MS |
44 | We expect the first arg to be a pointer to the jmp_buf structure |
45 | from which we extract the pc (MIPS_LINUX_JB_PC) that we will land | |
46 | at. The pc is copied into PC. This routine returns 1 on | |
47 | success. */ | |
2aa830e4 | 48 | |
19ed69dd KB |
49 | #define MIPS_LINUX_JB_ELEMENT_SIZE 4 |
50 | #define MIPS_LINUX_JB_PC 0 | |
51 | ||
52 | static int | |
60ade65d | 53 | mips_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
2aa830e4 DJ |
54 | { |
55 | CORE_ADDR jb_addr; | |
819844ad | 56 | char buf[gdbarch_ptr_bit (current_gdbarch) / TARGET_CHAR_BIT]; |
2aa830e4 | 57 | |
60ade65d | 58 | jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM); |
2aa830e4 | 59 | |
bf072999 | 60 | if (target_read_memory (jb_addr |
819844ad UW |
61 | + MIPS_LINUX_JB_PC * MIPS_LINUX_JB_ELEMENT_SIZE, |
62 | buf, | |
63 | gdbarch_ptr_bit (current_gdbarch) / TARGET_CHAR_BIT)) | |
2aa830e4 DJ |
64 | return 0; |
65 | ||
819844ad UW |
66 | *pc = extract_unsigned_integer (buf, |
67 | gdbarch_ptr_bit (current_gdbarch) | |
68 | / TARGET_CHAR_BIT); | |
2aa830e4 DJ |
69 | |
70 | return 1; | |
71 | } | |
72 | ||
4246e332 | 73 | /* Transform the bits comprising a 32-bit register to the right size |
23a6d369 AC |
74 | for regcache_raw_supply(). This is needed when mips_isa_regsize() |
75 | is 8. */ | |
96f026fc KB |
76 | |
77 | static void | |
28f5035f | 78 | supply_32bit_reg (struct regcache *regcache, int regnum, const void *addr) |
96f026fc | 79 | { |
d37eb719 | 80 | gdb_byte buf[MAX_REGISTER_SIZE]; |
3acba339 | 81 | store_signed_integer (buf, register_size (current_gdbarch, regnum), |
96f026fc | 82 | extract_signed_integer (addr, 4)); |
28f5035f | 83 | regcache_raw_supply (regcache, regnum, buf); |
96f026fc KB |
84 | } |
85 | ||
2aa830e4 DJ |
86 | /* Unpack an elf_gregset_t into GDB's register cache. */ |
87 | ||
d37eb719 | 88 | void |
28f5035f UW |
89 | mips_supply_gregset (struct regcache *regcache, |
90 | const mips_elf_gregset_t *gregsetp) | |
2aa830e4 DJ |
91 | { |
92 | int regi; | |
28f5035f | 93 | const mips_elf_greg_t *regp = *gregsetp; |
d9d9c31f | 94 | char zerobuf[MAX_REGISTER_SIZE]; |
bf072999 | 95 | |
d9d9c31f | 96 | memset (zerobuf, 0, MAX_REGISTER_SIZE); |
2aa830e4 | 97 | |
822b6570 | 98 | for (regi = EF_REG0 + 1; regi <= EF_REG31; regi++) |
28f5035f | 99 | supply_32bit_reg (regcache, regi - EF_REG0, regp + regi); |
2aa830e4 | 100 | |
822b6570 DJ |
101 | if (mips_linux_restart_reg_p (current_gdbarch)) |
102 | supply_32bit_reg (regcache, MIPS_RESTART_REGNUM, regp + EF_REG0); | |
103 | ||
28f5035f UW |
104 | supply_32bit_reg (regcache, mips_regnum (current_gdbarch)->lo, |
105 | regp + EF_LO); | |
106 | supply_32bit_reg (regcache, mips_regnum (current_gdbarch)->hi, | |
107 | regp + EF_HI); | |
56cea623 | 108 | |
28f5035f UW |
109 | supply_32bit_reg (regcache, mips_regnum (current_gdbarch)->pc, |
110 | regp + EF_CP0_EPC); | |
111 | supply_32bit_reg (regcache, mips_regnum (current_gdbarch)->badvaddr, | |
112 | regp + EF_CP0_BADVADDR); | |
113 | supply_32bit_reg (regcache, MIPS_PS_REGNUM, regp + EF_CP0_STATUS); | |
114 | supply_32bit_reg (regcache, mips_regnum (current_gdbarch)->cause, | |
115 | regp + EF_CP0_CAUSE); | |
2aa830e4 DJ |
116 | |
117 | /* Fill inaccessible registers with zero. */ | |
822b6570 | 118 | regcache_raw_supply (regcache, MIPS_ZERO_REGNUM, zerobuf); |
28f5035f | 119 | regcache_raw_supply (regcache, MIPS_UNUSED_REGNUM, zerobuf); |
295093a4 | 120 | for (regi = MIPS_FIRST_EMBED_REGNUM; |
822b6570 | 121 | regi <= MIPS_LAST_EMBED_REGNUM; |
295093a4 | 122 | regi++) |
28f5035f | 123 | regcache_raw_supply (regcache, regi, zerobuf); |
2aa830e4 DJ |
124 | } |
125 | ||
126 | /* Pack our registers (or one register) into an elf_gregset_t. */ | |
127 | ||
d37eb719 | 128 | void |
28f5035f UW |
129 | mips_fill_gregset (const struct regcache *regcache, |
130 | mips_elf_gregset_t *gregsetp, int regno) | |
2aa830e4 DJ |
131 | { |
132 | int regaddr, regi; | |
d37eb719 | 133 | mips_elf_greg_t *regp = *gregsetp; |
96f026fc | 134 | void *dst; |
2aa830e4 DJ |
135 | |
136 | if (regno == -1) | |
137 | { | |
d37eb719 | 138 | memset (regp, 0, sizeof (mips_elf_gregset_t)); |
822b6570 | 139 | for (regi = 1; regi < 32; regi++) |
28f5035f UW |
140 | mips_fill_gregset (regcache, gregsetp, regi); |
141 | mips_fill_gregset (regcache, gregsetp, | |
142 | mips_regnum (current_gdbarch)->lo); | |
143 | mips_fill_gregset (regcache, gregsetp, | |
144 | mips_regnum (current_gdbarch)->hi); | |
145 | mips_fill_gregset (regcache, gregsetp, | |
146 | mips_regnum (current_gdbarch)->pc); | |
147 | mips_fill_gregset (regcache, gregsetp, | |
148 | mips_regnum (current_gdbarch)->badvaddr); | |
149 | mips_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM); | |
150 | mips_fill_gregset (regcache, gregsetp, | |
151 | mips_regnum (current_gdbarch)->cause); | |
822b6570 | 152 | mips_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM); |
2aa830e4 DJ |
153 | return; |
154 | } | |
155 | ||
822b6570 | 156 | if (regno > 0 && regno < 32) |
2aa830e4 | 157 | { |
2aa830e4 | 158 | dst = regp + regno + EF_REG0; |
28f5035f | 159 | regcache_raw_collect (regcache, regno, dst); |
2aa830e4 DJ |
160 | return; |
161 | } | |
162 | ||
56cea623 AC |
163 | if (regno == mips_regnum (current_gdbarch)->lo) |
164 | regaddr = EF_LO; | |
165 | else if (regno == mips_regnum (current_gdbarch)->hi) | |
166 | regaddr = EF_HI; | |
167 | else if (regno == mips_regnum (current_gdbarch)->pc) | |
168 | regaddr = EF_CP0_EPC; | |
169 | else if (regno == mips_regnum (current_gdbarch)->badvaddr) | |
170 | regaddr = EF_CP0_BADVADDR; | |
24e05951 | 171 | else if (regno == MIPS_PS_REGNUM) |
56cea623 AC |
172 | regaddr = EF_CP0_STATUS; |
173 | else if (regno == mips_regnum (current_gdbarch)->cause) | |
174 | regaddr = EF_CP0_CAUSE; | |
822b6570 DJ |
175 | else if (mips_linux_restart_reg_p (current_gdbarch) |
176 | && regno == MIPS_RESTART_REGNUM) | |
177 | regaddr = EF_REG0; | |
56cea623 AC |
178 | else |
179 | regaddr = -1; | |
2aa830e4 DJ |
180 | |
181 | if (regaddr != -1) | |
182 | { | |
2aa830e4 | 183 | dst = regp + regaddr; |
28f5035f | 184 | regcache_raw_collect (regcache, regno, dst); |
2aa830e4 DJ |
185 | } |
186 | } | |
187 | ||
188 | /* Likewise, unpack an elf_fpregset_t. */ | |
189 | ||
d37eb719 | 190 | void |
28f5035f UW |
191 | mips_supply_fpregset (struct regcache *regcache, |
192 | const mips_elf_fpregset_t *fpregsetp) | |
2aa830e4 | 193 | { |
52f0bd74 | 194 | int regi; |
d9d9c31f | 195 | char zerobuf[MAX_REGISTER_SIZE]; |
bf072999 | 196 | |
d9d9c31f | 197 | memset (zerobuf, 0, MAX_REGISTER_SIZE); |
2aa830e4 DJ |
198 | |
199 | for (regi = 0; regi < 32; regi++) | |
3e8c568d UW |
200 | regcache_raw_supply (regcache, |
201 | gdbarch_fp0_regnum (current_gdbarch) + regi, | |
202 | *fpregsetp + regi); | |
2aa830e4 | 203 | |
28f5035f | 204 | regcache_raw_supply (regcache, |
23a6d369 | 205 | mips_regnum (current_gdbarch)->fp_control_status, |
28f5035f | 206 | *fpregsetp + 32); |
2aa830e4 | 207 | |
295093a4 | 208 | /* FIXME: how can we supply FCRIR? The ABI doesn't tell us. */ |
28f5035f | 209 | regcache_raw_supply (regcache, |
23a6d369 AC |
210 | mips_regnum (current_gdbarch)->fp_implementation_revision, |
211 | zerobuf); | |
2aa830e4 DJ |
212 | } |
213 | ||
214 | /* Likewise, pack one or all floating point registers into an | |
215 | elf_fpregset_t. */ | |
216 | ||
d37eb719 | 217 | void |
28f5035f UW |
218 | mips_fill_fpregset (const struct regcache *regcache, |
219 | mips_elf_fpregset_t *fpregsetp, int regno) | |
2aa830e4 DJ |
220 | { |
221 | char *from, *to; | |
222 | ||
3e8c568d UW |
223 | if ((regno >= gdbarch_fp0_regnum (current_gdbarch)) |
224 | && (regno < gdbarch_fp0_regnum (current_gdbarch) + 32)) | |
2aa830e4 | 225 | { |
3e8c568d | 226 | to = (char *) (*fpregsetp + regno - gdbarch_fp0_regnum (current_gdbarch)); |
28f5035f | 227 | regcache_raw_collect (regcache, regno, to); |
2aa830e4 | 228 | } |
56cea623 | 229 | else if (regno == mips_regnum (current_gdbarch)->fp_control_status) |
2aa830e4 | 230 | { |
2aa830e4 | 231 | to = (char *) (*fpregsetp + 32); |
28f5035f | 232 | regcache_raw_collect (regcache, regno, to); |
2aa830e4 DJ |
233 | } |
234 | else if (regno == -1) | |
235 | { | |
236 | int regi; | |
237 | ||
238 | for (regi = 0; regi < 32; regi++) | |
3e8c568d UW |
239 | mips_fill_fpregset (regcache, fpregsetp, |
240 | gdbarch_fp0_regnum (current_gdbarch) + regi); | |
28f5035f | 241 | mips_fill_fpregset (regcache, fpregsetp, |
9f62d0e2 | 242 | mips_regnum (current_gdbarch)->fp_control_status); |
2aa830e4 DJ |
243 | } |
244 | } | |
245 | ||
96f026fc KB |
246 | /* Support for 64-bit ABIs. */ |
247 | ||
96f026fc | 248 | /* Figure out where the longjmp will land. |
295093a4 MS |
249 | We expect the first arg to be a pointer to the jmp_buf structure |
250 | from which we extract the pc (MIPS_LINUX_JB_PC) that we will land | |
251 | at. The pc is copied into PC. This routine returns 1 on | |
252 | success. */ | |
96f026fc KB |
253 | |
254 | /* Details about jmp_buf. */ | |
255 | ||
256 | #define MIPS64_LINUX_JB_PC 0 | |
257 | ||
258 | static int | |
60ade65d | 259 | mips64_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
96f026fc KB |
260 | { |
261 | CORE_ADDR jb_addr; | |
819844ad UW |
262 | void *buf = alloca (gdbarch_ptr_bit (current_gdbarch) / TARGET_CHAR_BIT); |
263 | int element_size = gdbarch_ptr_bit (current_gdbarch) == 32 ? 4 : 8; | |
96f026fc | 264 | |
60ade65d | 265 | jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM); |
96f026fc KB |
266 | |
267 | if (target_read_memory (jb_addr + MIPS64_LINUX_JB_PC * element_size, | |
819844ad UW |
268 | buf, |
269 | gdbarch_ptr_bit (current_gdbarch) / TARGET_CHAR_BIT)) | |
96f026fc KB |
270 | return 0; |
271 | ||
819844ad UW |
272 | *pc = extract_unsigned_integer (buf, |
273 | gdbarch_ptr_bit (current_gdbarch) | |
274 | / TARGET_CHAR_BIT); | |
96f026fc KB |
275 | |
276 | return 1; | |
277 | } | |
278 | ||
d37eb719 DJ |
279 | /* Register set support functions. These operate on standard 64-bit |
280 | regsets, but work whether the target is 32-bit or 64-bit. A 32-bit | |
281 | target will still use the 64-bit format for PTRACE_GETREGS. */ | |
282 | ||
283 | /* Supply a 64-bit register. */ | |
96f026fc | 284 | |
d37eb719 | 285 | void |
28f5035f UW |
286 | supply_64bit_reg (struct regcache *regcache, int regnum, |
287 | const gdb_byte *buf) | |
d37eb719 DJ |
288 | { |
289 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG | |
290 | && register_size (current_gdbarch, regnum) == 4) | |
28f5035f | 291 | regcache_raw_supply (regcache, regnum, buf + 4); |
d37eb719 | 292 | else |
28f5035f | 293 | regcache_raw_supply (regcache, regnum, buf); |
d37eb719 DJ |
294 | } |
295 | ||
296 | /* Unpack a 64-bit elf_gregset_t into GDB's register cache. */ | |
297 | ||
298 | void | |
28f5035f UW |
299 | mips64_supply_gregset (struct regcache *regcache, |
300 | const mips64_elf_gregset_t *gregsetp) | |
96f026fc KB |
301 | { |
302 | int regi; | |
28f5035f | 303 | const mips64_elf_greg_t *regp = *gregsetp; |
d37eb719 | 304 | gdb_byte zerobuf[MAX_REGISTER_SIZE]; |
96f026fc | 305 | |
d9d9c31f | 306 | memset (zerobuf, 0, MAX_REGISTER_SIZE); |
96f026fc | 307 | |
822b6570 | 308 | for (regi = MIPS64_EF_REG0 + 1; regi <= MIPS64_EF_REG31; regi++) |
28f5035f UW |
309 | supply_64bit_reg (regcache, regi - MIPS64_EF_REG0, |
310 | (const gdb_byte *)(regp + regi)); | |
311 | ||
822b6570 DJ |
312 | if (mips_linux_restart_reg_p (current_gdbarch)) |
313 | supply_64bit_reg (regcache, MIPS_RESTART_REGNUM, | |
314 | (const gdb_byte *)(regp + MIPS64_EF_REG0)); | |
315 | ||
28f5035f UW |
316 | supply_64bit_reg (regcache, mips_regnum (current_gdbarch)->lo, |
317 | (const gdb_byte *) (regp + MIPS64_EF_LO)); | |
318 | supply_64bit_reg (regcache, mips_regnum (current_gdbarch)->hi, | |
319 | (const gdb_byte *) (regp + MIPS64_EF_HI)); | |
320 | ||
321 | supply_64bit_reg (regcache, mips_regnum (current_gdbarch)->pc, | |
322 | (const gdb_byte *) (regp + MIPS64_EF_CP0_EPC)); | |
323 | supply_64bit_reg (regcache, mips_regnum (current_gdbarch)->badvaddr, | |
324 | (const gdb_byte *) (regp + MIPS64_EF_CP0_BADVADDR)); | |
325 | supply_64bit_reg (regcache, MIPS_PS_REGNUM, | |
326 | (const gdb_byte *) (regp + MIPS64_EF_CP0_STATUS)); | |
327 | supply_64bit_reg (regcache, mips_regnum (current_gdbarch)->cause, | |
328 | (const gdb_byte *) (regp + MIPS64_EF_CP0_CAUSE)); | |
96f026fc KB |
329 | |
330 | /* Fill inaccessible registers with zero. */ | |
822b6570 | 331 | regcache_raw_supply (regcache, MIPS_ZERO_REGNUM, zerobuf); |
28f5035f | 332 | regcache_raw_supply (regcache, MIPS_UNUSED_REGNUM, zerobuf); |
295093a4 | 333 | for (regi = MIPS_FIRST_EMBED_REGNUM; |
822b6570 | 334 | regi <= MIPS_LAST_EMBED_REGNUM; |
295093a4 | 335 | regi++) |
28f5035f | 336 | regcache_raw_supply (regcache, regi, zerobuf); |
96f026fc KB |
337 | } |
338 | ||
d37eb719 | 339 | /* Pack our registers (or one register) into a 64-bit elf_gregset_t. */ |
96f026fc | 340 | |
d37eb719 | 341 | void |
28f5035f UW |
342 | mips64_fill_gregset (const struct regcache *regcache, |
343 | mips64_elf_gregset_t *gregsetp, int regno) | |
96f026fc KB |
344 | { |
345 | int regaddr, regi; | |
346 | mips64_elf_greg_t *regp = *gregsetp; | |
347 | void *src, *dst; | |
348 | ||
349 | if (regno == -1) | |
350 | { | |
351 | memset (regp, 0, sizeof (mips64_elf_gregset_t)); | |
822b6570 | 352 | for (regi = 1; regi < 32; regi++) |
28f5035f UW |
353 | mips64_fill_gregset (regcache, gregsetp, regi); |
354 | mips64_fill_gregset (regcache, gregsetp, | |
355 | mips_regnum (current_gdbarch)->lo); | |
356 | mips64_fill_gregset (regcache, gregsetp, | |
357 | mips_regnum (current_gdbarch)->hi); | |
358 | mips64_fill_gregset (regcache, gregsetp, | |
359 | mips_regnum (current_gdbarch)->pc); | |
360 | mips64_fill_gregset (regcache, gregsetp, | |
295093a4 | 361 | mips_regnum (current_gdbarch)->badvaddr); |
28f5035f UW |
362 | mips64_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM); |
363 | mips64_fill_gregset (regcache, gregsetp, | |
295093a4 | 364 | mips_regnum (current_gdbarch)->cause); |
822b6570 | 365 | mips64_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM); |
96f026fc KB |
366 | return; |
367 | } | |
368 | ||
822b6570 | 369 | if (regno > 0 && regno < 32) |
d37eb719 DJ |
370 | regaddr = regno + MIPS64_EF_REG0; |
371 | else if (regno == mips_regnum (current_gdbarch)->lo) | |
56cea623 AC |
372 | regaddr = MIPS64_EF_LO; |
373 | else if (regno == mips_regnum (current_gdbarch)->hi) | |
374 | regaddr = MIPS64_EF_HI; | |
375 | else if (regno == mips_regnum (current_gdbarch)->pc) | |
376 | regaddr = MIPS64_EF_CP0_EPC; | |
377 | else if (regno == mips_regnum (current_gdbarch)->badvaddr) | |
378 | regaddr = MIPS64_EF_CP0_BADVADDR; | |
24e05951 | 379 | else if (regno == MIPS_PS_REGNUM) |
56cea623 AC |
380 | regaddr = MIPS64_EF_CP0_STATUS; |
381 | else if (regno == mips_regnum (current_gdbarch)->cause) | |
382 | regaddr = MIPS64_EF_CP0_CAUSE; | |
822b6570 DJ |
383 | else if (mips_linux_restart_reg_p (current_gdbarch) |
384 | && regno == MIPS_RESTART_REGNUM) | |
385 | regaddr = MIPS64_EF_REG0; | |
56cea623 AC |
386 | else |
387 | regaddr = -1; | |
96f026fc KB |
388 | |
389 | if (regaddr != -1) | |
390 | { | |
d37eb719 DJ |
391 | gdb_byte buf[MAX_REGISTER_SIZE]; |
392 | LONGEST val; | |
393 | ||
28f5035f | 394 | regcache_raw_collect (regcache, regno, buf); |
d37eb719 DJ |
395 | val = extract_signed_integer (buf, |
396 | register_size (current_gdbarch, regno)); | |
96f026fc | 397 | dst = regp + regaddr; |
d37eb719 | 398 | store_signed_integer (dst, 8, val); |
96f026fc KB |
399 | } |
400 | } | |
401 | ||
402 | /* Likewise, unpack an elf_fpregset_t. */ | |
403 | ||
d37eb719 | 404 | void |
28f5035f UW |
405 | mips64_supply_fpregset (struct regcache *regcache, |
406 | const mips64_elf_fpregset_t *fpregsetp) | |
96f026fc | 407 | { |
52f0bd74 | 408 | int regi; |
96f026fc | 409 | |
d37eb719 DJ |
410 | /* See mips_linux_o32_sigframe_init for a description of the |
411 | peculiar FP register layout. */ | |
3e8c568d UW |
412 | if (register_size (current_gdbarch, |
413 | gdbarch_fp0_regnum (current_gdbarch)) == 4) | |
d37eb719 DJ |
414 | for (regi = 0; regi < 32; regi++) |
415 | { | |
28f5035f | 416 | const gdb_byte *reg_ptr = (const gdb_byte *)(*fpregsetp + (regi & ~1)); |
4c6b5505 UW |
417 | if ((gdbarch_byte_order (current_gdbarch) |
418 | == BFD_ENDIAN_BIG) != (regi & 1)) | |
d37eb719 | 419 | reg_ptr += 4; |
3e8c568d UW |
420 | regcache_raw_supply (regcache, |
421 | gdbarch_fp0_regnum (current_gdbarch) + regi, | |
422 | reg_ptr); | |
d37eb719 DJ |
423 | } |
424 | else | |
425 | for (regi = 0; regi < 32; regi++) | |
3e8c568d UW |
426 | regcache_raw_supply (regcache, |
427 | gdbarch_fp0_regnum (current_gdbarch) + regi, | |
28f5035f | 428 | (const char *)(*fpregsetp + regi)); |
d37eb719 | 429 | |
28f5035f UW |
430 | supply_32bit_reg (regcache, mips_regnum (current_gdbarch)->fp_control_status, |
431 | (const gdb_byte *)(*fpregsetp + 32)); | |
d37eb719 DJ |
432 | |
433 | /* The ABI doesn't tell us how to supply FCRIR, and core dumps don't | |
434 | include it - but the result of PTRACE_GETFPREGS does. The best we | |
435 | can do is to assume that its value is present. */ | |
28f5035f UW |
436 | supply_32bit_reg (regcache, |
437 | mips_regnum (current_gdbarch)->fp_implementation_revision, | |
438 | (const gdb_byte *)(*fpregsetp + 32) + 4); | |
96f026fc KB |
439 | } |
440 | ||
441 | /* Likewise, pack one or all floating point registers into an | |
442 | elf_fpregset_t. */ | |
443 | ||
d37eb719 | 444 | void |
28f5035f UW |
445 | mips64_fill_fpregset (const struct regcache *regcache, |
446 | mips64_elf_fpregset_t *fpregsetp, int regno) | |
96f026fc | 447 | { |
d37eb719 | 448 | gdb_byte *to; |
96f026fc | 449 | |
3e8c568d UW |
450 | if ((regno >= gdbarch_fp0_regnum (current_gdbarch)) |
451 | && (regno < gdbarch_fp0_regnum (current_gdbarch) + 32)) | |
96f026fc | 452 | { |
d37eb719 DJ |
453 | /* See mips_linux_o32_sigframe_init for a description of the |
454 | peculiar FP register layout. */ | |
455 | if (register_size (current_gdbarch, regno) == 4) | |
456 | { | |
3e8c568d | 457 | int regi = regno - gdbarch_fp0_regnum (current_gdbarch); |
d37eb719 DJ |
458 | |
459 | to = (gdb_byte *) (*fpregsetp + (regi & ~1)); | |
4c6b5505 UW |
460 | if ((gdbarch_byte_order (current_gdbarch) |
461 | == BFD_ENDIAN_BIG) != (regi & 1)) | |
d37eb719 | 462 | to += 4; |
28f5035f | 463 | regcache_raw_collect (regcache, regno, to); |
d37eb719 DJ |
464 | } |
465 | else | |
466 | { | |
3e8c568d UW |
467 | to = (gdb_byte *) (*fpregsetp + regno |
468 | - gdbarch_fp0_regnum (current_gdbarch)); | |
28f5035f | 469 | regcache_raw_collect (regcache, regno, to); |
d37eb719 | 470 | } |
96f026fc | 471 | } |
56cea623 | 472 | else if (regno == mips_regnum (current_gdbarch)->fp_control_status) |
96f026fc | 473 | { |
d37eb719 DJ |
474 | gdb_byte buf[MAX_REGISTER_SIZE]; |
475 | LONGEST val; | |
476 | ||
28f5035f | 477 | regcache_raw_collect (regcache, regno, buf); |
d37eb719 DJ |
478 | val = extract_signed_integer (buf, |
479 | register_size (current_gdbarch, regno)); | |
480 | to = (gdb_byte *) (*fpregsetp + 32); | |
481 | store_signed_integer (to, 4, val); | |
482 | } | |
483 | else if (regno == mips_regnum (current_gdbarch)->fp_implementation_revision) | |
484 | { | |
485 | gdb_byte buf[MAX_REGISTER_SIZE]; | |
486 | LONGEST val; | |
487 | ||
28f5035f | 488 | regcache_raw_collect (regcache, regno, buf); |
d37eb719 DJ |
489 | val = extract_signed_integer (buf, |
490 | register_size (current_gdbarch, regno)); | |
491 | to = (gdb_byte *) (*fpregsetp + 32) + 4; | |
492 | store_signed_integer (to, 4, val); | |
96f026fc KB |
493 | } |
494 | else if (regno == -1) | |
495 | { | |
496 | int regi; | |
497 | ||
498 | for (regi = 0; regi < 32; regi++) | |
3e8c568d UW |
499 | mips64_fill_fpregset (regcache, fpregsetp, |
500 | gdbarch_fp0_regnum (current_gdbarch) + regi); | |
28f5035f | 501 | mips64_fill_fpregset (regcache, fpregsetp, |
d37eb719 | 502 | mips_regnum (current_gdbarch)->fp_control_status); |
28f5035f UW |
503 | mips64_fill_fpregset (regcache, fpregsetp, |
504 | (mips_regnum (current_gdbarch) | |
505 | ->fp_implementation_revision)); | |
96f026fc KB |
506 | } |
507 | } | |
508 | ||
509 | ||
2aa830e4 DJ |
510 | /* Use a local version of this function to get the correct types for |
511 | regsets, until multi-arch core support is ready. */ | |
512 | ||
513 | static void | |
9eefc95f UW |
514 | fetch_core_registers (struct regcache *regcache, |
515 | char *core_reg_sect, unsigned core_reg_size, | |
2aa830e4 DJ |
516 | int which, CORE_ADDR reg_addr) |
517 | { | |
d37eb719 DJ |
518 | mips_elf_gregset_t gregset; |
519 | mips_elf_fpregset_t fpregset; | |
96f026fc KB |
520 | mips64_elf_gregset_t gregset64; |
521 | mips64_elf_fpregset_t fpregset64; | |
2aa830e4 DJ |
522 | |
523 | if (which == 0) | |
524 | { | |
96f026fc | 525 | if (core_reg_size == sizeof (gregset)) |
2aa830e4 | 526 | { |
96f026fc | 527 | memcpy ((char *) &gregset, core_reg_sect, sizeof (gregset)); |
9eefc95f | 528 | mips_supply_gregset (regcache, |
28f5035f | 529 | (const mips_elf_gregset_t *) &gregset); |
96f026fc KB |
530 | } |
531 | else if (core_reg_size == sizeof (gregset64)) | |
532 | { | |
533 | memcpy ((char *) &gregset64, core_reg_sect, sizeof (gregset64)); | |
9eefc95f | 534 | mips64_supply_gregset (regcache, |
28f5035f | 535 | (const mips64_elf_gregset_t *) &gregset64); |
2aa830e4 DJ |
536 | } |
537 | else | |
538 | { | |
8a3fe4f8 | 539 | warning (_("wrong size gregset struct in core file")); |
2aa830e4 DJ |
540 | } |
541 | } | |
542 | else if (which == 2) | |
543 | { | |
96f026fc | 544 | if (core_reg_size == sizeof (fpregset)) |
2aa830e4 | 545 | { |
96f026fc | 546 | memcpy ((char *) &fpregset, core_reg_sect, sizeof (fpregset)); |
9eefc95f | 547 | mips_supply_fpregset (regcache, |
28f5035f | 548 | (const mips_elf_fpregset_t *) &fpregset); |
96f026fc KB |
549 | } |
550 | else if (core_reg_size == sizeof (fpregset64)) | |
551 | { | |
295093a4 MS |
552 | memcpy ((char *) &fpregset64, core_reg_sect, |
553 | sizeof (fpregset64)); | |
9eefc95f | 554 | mips64_supply_fpregset (regcache, |
28f5035f | 555 | (const mips64_elf_fpregset_t *) &fpregset64); |
2aa830e4 DJ |
556 | } |
557 | else | |
558 | { | |
8a3fe4f8 | 559 | warning (_("wrong size fpregset struct in core file")); |
2aa830e4 DJ |
560 | } |
561 | } | |
562 | } | |
563 | ||
564 | /* Register that we are able to handle ELF file formats using standard | |
565 | procfs "regset" structures. */ | |
566 | ||
567 | static struct core_fns regset_core_fns = | |
568 | { | |
569 | bfd_target_elf_flavour, /* core_flavour */ | |
570 | default_check_format, /* check_format */ | |
571 | default_core_sniffer, /* core_sniffer */ | |
572 | fetch_core_registers, /* core_read_registers */ | |
573 | NULL /* next */ | |
574 | }; | |
575 | ||
4eb0ad19 DJ |
576 | static const struct target_desc * |
577 | mips_linux_core_read_description (struct gdbarch *gdbarch, | |
578 | struct target_ops *target, | |
579 | bfd *abfd) | |
580 | { | |
581 | asection *section = bfd_get_section_by_name (abfd, ".reg"); | |
582 | if (! section) | |
583 | return NULL; | |
584 | ||
585 | switch (bfd_section_size (abfd, section)) | |
586 | { | |
587 | case sizeof (mips_elf_gregset_t): | |
588 | return mips_tdesc_gp32; | |
589 | ||
590 | case sizeof (mips64_elf_gregset_t): | |
591 | return mips_tdesc_gp64; | |
592 | ||
593 | default: | |
594 | return NULL; | |
595 | } | |
596 | } | |
597 | ||
96f026fc | 598 | |
295093a4 MS |
599 | /* Check the code at PC for a dynamic linker lazy resolution stub. |
600 | Because they aren't in the .plt section, we pattern-match on the | |
601 | code generated by GNU ld. They look like this: | |
6de918a6 DJ |
602 | |
603 | lw t9,0x8010(gp) | |
604 | addu t7,ra | |
605 | jalr t9,ra | |
606 | addiu t8,zero,INDEX | |
607 | ||
295093a4 MS |
608 | (with the appropriate doubleword instructions for N64). Also |
609 | return the dynamic symbol index used in the last instruction. */ | |
6de918a6 DJ |
610 | |
611 | static int | |
612 | mips_linux_in_dynsym_stub (CORE_ADDR pc, char *name) | |
613 | { | |
614 | unsigned char buf[28], *p; | |
615 | ULONGEST insn, insn1; | |
616 | int n64 = (mips_abi (current_gdbarch) == MIPS_ABI_N64); | |
617 | ||
618 | read_memory (pc - 12, buf, 28); | |
619 | ||
620 | if (n64) | |
621 | { | |
622 | /* ld t9,0x8010(gp) */ | |
623 | insn1 = 0xdf998010; | |
624 | } | |
625 | else | |
626 | { | |
627 | /* lw t9,0x8010(gp) */ | |
628 | insn1 = 0x8f998010; | |
629 | } | |
630 | ||
631 | p = buf + 12; | |
632 | while (p >= buf) | |
633 | { | |
634 | insn = extract_unsigned_integer (p, 4); | |
635 | if (insn == insn1) | |
636 | break; | |
637 | p -= 4; | |
638 | } | |
639 | if (p < buf) | |
640 | return 0; | |
641 | ||
642 | insn = extract_unsigned_integer (p + 4, 4); | |
643 | if (n64) | |
644 | { | |
645 | /* daddu t7,ra */ | |
646 | if (insn != 0x03e0782d) | |
647 | return 0; | |
648 | } | |
649 | else | |
650 | { | |
651 | /* addu t7,ra */ | |
652 | if (insn != 0x03e07821) | |
653 | return 0; | |
654 | } | |
295093a4 | 655 | |
6de918a6 DJ |
656 | insn = extract_unsigned_integer (p + 8, 4); |
657 | /* jalr t9,ra */ | |
658 | if (insn != 0x0320f809) | |
659 | return 0; | |
660 | ||
661 | insn = extract_unsigned_integer (p + 12, 4); | |
662 | if (n64) | |
663 | { | |
664 | /* daddiu t8,zero,0 */ | |
665 | if ((insn & 0xffff0000) != 0x64180000) | |
666 | return 0; | |
667 | } | |
668 | else | |
669 | { | |
670 | /* addiu t8,zero,0 */ | |
671 | if ((insn & 0xffff0000) != 0x24180000) | |
672 | return 0; | |
673 | } | |
674 | ||
675 | return (insn & 0xffff); | |
676 | } | |
677 | ||
295093a4 MS |
678 | /* Return non-zero iff PC belongs to the dynamic linker resolution |
679 | code or to a stub. */ | |
6de918a6 | 680 | |
7d522c90 | 681 | static int |
6de918a6 DJ |
682 | mips_linux_in_dynsym_resolve_code (CORE_ADDR pc) |
683 | { | |
295093a4 MS |
684 | /* Check whether PC is in the dynamic linker. This also checks |
685 | whether it is in the .plt section, which MIPS does not use. */ | |
7d522c90 | 686 | if (svr4_in_dynsym_resolve_code (pc)) |
6de918a6 DJ |
687 | return 1; |
688 | ||
295093a4 MS |
689 | /* Pattern match for the stub. It would be nice if there were a |
690 | more efficient way to avoid this check. */ | |
6de918a6 DJ |
691 | if (mips_linux_in_dynsym_stub (pc, NULL)) |
692 | return 1; | |
693 | ||
694 | return 0; | |
695 | } | |
696 | ||
697 | /* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c, | |
698 | and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc | |
699 | implementation of this triggers at "fixup" from the same objfile as | |
c4c5b7ba AC |
700 | "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at |
701 | "__dl_runtime_resolve" directly. An unresolved PLT entry will | |
702 | point to _dl_runtime_resolve, which will first call | |
703 | __dl_runtime_resolve, and then pass control to the resolved | |
704 | function. */ | |
6de918a6 DJ |
705 | |
706 | static CORE_ADDR | |
707 | mips_linux_skip_resolver (struct gdbarch *gdbarch, CORE_ADDR pc) | |
708 | { | |
709 | struct minimal_symbol *resolver; | |
710 | ||
711 | resolver = lookup_minimal_symbol ("__dl_runtime_resolve", NULL, NULL); | |
712 | ||
713 | if (resolver && SYMBOL_VALUE_ADDRESS (resolver) == pc) | |
295093a4 | 714 | return frame_pc_unwind (get_current_frame ()); |
6de918a6 DJ |
715 | |
716 | return 0; | |
295093a4 | 717 | } |
6de918a6 | 718 | |
5792a79b DJ |
719 | /* Signal trampoline support. There are four supported layouts for a |
720 | signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and | |
721 | n64 rt_sigframe. We handle them all independently; not the most | |
722 | efficient way, but simplest. First, declare all the unwinders. */ | |
723 | ||
724 | static void mips_linux_o32_sigframe_init (const struct tramp_frame *self, | |
725 | struct frame_info *next_frame, | |
726 | struct trad_frame_cache *this_cache, | |
727 | CORE_ADDR func); | |
728 | ||
729 | static void mips_linux_n32n64_sigframe_init (const struct tramp_frame *self, | |
730 | struct frame_info *next_frame, | |
731 | struct trad_frame_cache *this_cache, | |
732 | CORE_ADDR func); | |
733 | ||
734 | #define MIPS_NR_LINUX 4000 | |
735 | #define MIPS_NR_N64_LINUX 5000 | |
736 | #define MIPS_NR_N32_LINUX 6000 | |
737 | ||
738 | #define MIPS_NR_sigreturn MIPS_NR_LINUX + 119 | |
739 | #define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193 | |
740 | #define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211 | |
741 | #define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211 | |
742 | ||
743 | #define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn | |
744 | #define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn | |
745 | #define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn | |
746 | #define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn | |
747 | #define MIPS_INST_SYSCALL 0x0000000c | |
748 | ||
2cd8546d AC |
749 | static const struct tramp_frame mips_linux_o32_sigframe = { |
750 | SIGTRAMP_FRAME, | |
5792a79b | 751 | 4, |
2cd8546d AC |
752 | { |
753 | { MIPS_INST_LI_V0_SIGRETURN, -1 }, | |
754 | { MIPS_INST_SYSCALL, -1 }, | |
755 | { TRAMP_SENTINEL_INSN, -1 } | |
756 | }, | |
5792a79b DJ |
757 | mips_linux_o32_sigframe_init |
758 | }; | |
759 | ||
2cd8546d AC |
760 | static const struct tramp_frame mips_linux_o32_rt_sigframe = { |
761 | SIGTRAMP_FRAME, | |
5792a79b | 762 | 4, |
2cd8546d AC |
763 | { |
764 | { MIPS_INST_LI_V0_RT_SIGRETURN, -1 }, | |
765 | { MIPS_INST_SYSCALL, -1 }, | |
766 | { TRAMP_SENTINEL_INSN, -1 } }, | |
5792a79b DJ |
767 | mips_linux_o32_sigframe_init |
768 | }; | |
769 | ||
2cd8546d AC |
770 | static const struct tramp_frame mips_linux_n32_rt_sigframe = { |
771 | SIGTRAMP_FRAME, | |
5792a79b | 772 | 4, |
2cd8546d AC |
773 | { |
774 | { MIPS_INST_LI_V0_N32_RT_SIGRETURN, -1 }, | |
775 | { MIPS_INST_SYSCALL, -1 }, | |
776 | { TRAMP_SENTINEL_INSN, -1 } | |
777 | }, | |
5792a79b DJ |
778 | mips_linux_n32n64_sigframe_init |
779 | }; | |
780 | ||
2cd8546d AC |
781 | static const struct tramp_frame mips_linux_n64_rt_sigframe = { |
782 | SIGTRAMP_FRAME, | |
5792a79b | 783 | 4, |
fcbd8a5c TS |
784 | { |
785 | { MIPS_INST_LI_V0_N64_RT_SIGRETURN, -1 }, | |
786 | { MIPS_INST_SYSCALL, -1 }, | |
787 | { TRAMP_SENTINEL_INSN, -1 } | |
788 | }, | |
5792a79b DJ |
789 | mips_linux_n32n64_sigframe_init |
790 | }; | |
791 | ||
792 | /* *INDENT-OFF* */ | |
793 | /* The unwinder for o32 signal frames. The legacy structures look | |
794 | like this: | |
795 | ||
796 | struct sigframe { | |
797 | u32 sf_ass[4]; [argument save space for o32] | |
798 | u32 sf_code[2]; [signal trampoline] | |
799 | struct sigcontext sf_sc; | |
800 | sigset_t sf_mask; | |
801 | }; | |
802 | ||
803 | struct sigcontext { | |
804 | unsigned int sc_regmask; [Unused] | |
805 | unsigned int sc_status; | |
806 | unsigned long long sc_pc; | |
807 | unsigned long long sc_regs[32]; | |
808 | unsigned long long sc_fpregs[32]; | |
809 | unsigned int sc_ownedfp; | |
810 | unsigned int sc_fpc_csr; | |
811 | unsigned int sc_fpc_eir; [Unused] | |
812 | unsigned int sc_used_math; | |
813 | unsigned int sc_ssflags; [Unused] | |
814 | [Alignment hole of four bytes] | |
815 | unsigned long long sc_mdhi; | |
816 | unsigned long long sc_mdlo; | |
817 | ||
818 | unsigned int sc_cause; [Unused] | |
819 | unsigned int sc_badvaddr; [Unused] | |
820 | ||
821 | unsigned long sc_sigset[4]; [kernel's sigset_t] | |
822 | }; | |
823 | ||
824 | The RT signal frames look like this: | |
825 | ||
826 | struct rt_sigframe { | |
827 | u32 rs_ass[4]; [argument save space for o32] | |
828 | u32 rs_code[2] [signal trampoline] | |
829 | struct siginfo rs_info; | |
830 | struct ucontext rs_uc; | |
831 | }; | |
832 | ||
833 | struct ucontext { | |
834 | unsigned long uc_flags; | |
835 | struct ucontext *uc_link; | |
836 | stack_t uc_stack; | |
837 | [Alignment hole of four bytes] | |
838 | struct sigcontext uc_mcontext; | |
839 | sigset_t uc_sigmask; | |
840 | }; */ | |
841 | /* *INDENT-ON* */ | |
842 | ||
843 | #define SIGFRAME_CODE_OFFSET (4 * 4) | |
844 | #define SIGFRAME_SIGCONTEXT_OFFSET (6 * 4) | |
845 | ||
846 | #define RTSIGFRAME_SIGINFO_SIZE 128 | |
847 | #define STACK_T_SIZE (3 * 4) | |
848 | #define UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + STACK_T_SIZE + 4) | |
849 | #define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ | |
850 | + RTSIGFRAME_SIGINFO_SIZE \ | |
851 | + UCONTEXT_SIGCONTEXT_OFFSET) | |
852 | ||
853 | #define SIGCONTEXT_PC (1 * 8) | |
854 | #define SIGCONTEXT_REGS (2 * 8) | |
855 | #define SIGCONTEXT_FPREGS (34 * 8) | |
856 | #define SIGCONTEXT_FPCSR (66 * 8 + 4) | |
857 | #define SIGCONTEXT_HI (69 * 8) | |
858 | #define SIGCONTEXT_LO (70 * 8) | |
859 | #define SIGCONTEXT_CAUSE (71 * 8 + 0) | |
860 | #define SIGCONTEXT_BADVADDR (71 * 8 + 4) | |
861 | ||
862 | #define SIGCONTEXT_REG_SIZE 8 | |
863 | ||
864 | static void | |
865 | mips_linux_o32_sigframe_init (const struct tramp_frame *self, | |
866 | struct frame_info *next_frame, | |
867 | struct trad_frame_cache *this_cache, | |
868 | CORE_ADDR func) | |
869 | { | |
870 | int ireg, reg_position; | |
871 | CORE_ADDR sigcontext_base = func - SIGFRAME_CODE_OFFSET; | |
872 | const struct mips_regnum *regs = mips_regnum (current_gdbarch); | |
37c4d197 | 873 | CORE_ADDR regs_base; |
5792a79b DJ |
874 | |
875 | if (self == &mips_linux_o32_sigframe) | |
876 | sigcontext_base += SIGFRAME_SIGCONTEXT_OFFSET; | |
877 | else | |
878 | sigcontext_base += RTSIGFRAME_SIGCONTEXT_OFFSET; | |
295093a4 MS |
879 | |
880 | /* I'm not proud of this hack. Eventually we will have the | |
881 | infrastructure to indicate the size of saved registers on a | |
882 | per-frame basis, but right now we don't; the kernel saves eight | |
37c4d197 DJ |
883 | bytes but we only want four. Use regs_base to access any |
884 | 64-bit fields. */ | |
4c6b5505 | 885 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
37c4d197 DJ |
886 | regs_base = sigcontext_base + 4; |
887 | else | |
888 | regs_base = sigcontext_base; | |
5792a79b | 889 | |
822b6570 DJ |
890 | if (mips_linux_restart_reg_p (current_gdbarch)) |
891 | trad_frame_set_reg_addr (this_cache, | |
892 | (MIPS_RESTART_REGNUM | |
893 | + gdbarch_num_regs (current_gdbarch)), | |
894 | regs_base + SIGCONTEXT_REGS); | |
5792a79b DJ |
895 | |
896 | for (ireg = 1; ireg < 32; ireg++) | |
295093a4 | 897 | trad_frame_set_reg_addr (this_cache, |
f57d151a UW |
898 | ireg + MIPS_ZERO_REGNUM |
899 | + gdbarch_num_regs (current_gdbarch), | |
37c4d197 | 900 | regs_base + SIGCONTEXT_REGS |
5792a79b DJ |
901 | + ireg * SIGCONTEXT_REG_SIZE); |
902 | ||
37c4d197 DJ |
903 | /* The way that floating point registers are saved, unfortunately, |
904 | depends on the architecture the kernel is built for. For the r3000 and | |
905 | tx39, four bytes of each register are at the beginning of each of the | |
906 | 32 eight byte slots. For everything else, the registers are saved | |
907 | using double precision; only the even-numbered slots are initialized, | |
908 | and the high bits are the odd-numbered register. Assume the latter | |
909 | layout, since we can't tell, and it's much more common. Which bits are | |
910 | the "high" bits depends on endianness. */ | |
5792a79b | 911 | for (ireg = 0; ireg < 32; ireg++) |
4c6b5505 | 912 | if ((gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) != (ireg & 1)) |
f57d151a UW |
913 | trad_frame_set_reg_addr (this_cache, |
914 | ireg + regs->fp0 + | |
915 | gdbarch_num_regs (current_gdbarch), | |
37c4d197 DJ |
916 | sigcontext_base + SIGCONTEXT_FPREGS + 4 |
917 | + (ireg & ~1) * SIGCONTEXT_REG_SIZE); | |
918 | else | |
f57d151a UW |
919 | trad_frame_set_reg_addr (this_cache, |
920 | ireg + regs->fp0 | |
921 | + gdbarch_num_regs (current_gdbarch), | |
37c4d197 DJ |
922 | sigcontext_base + SIGCONTEXT_FPREGS |
923 | + (ireg & ~1) * SIGCONTEXT_REG_SIZE); | |
5792a79b | 924 | |
f57d151a UW |
925 | trad_frame_set_reg_addr (this_cache, |
926 | regs->pc + gdbarch_num_regs (current_gdbarch), | |
37c4d197 | 927 | regs_base + SIGCONTEXT_PC); |
5792a79b | 928 | |
295093a4 | 929 | trad_frame_set_reg_addr (this_cache, |
f57d151a UW |
930 | regs->fp_control_status |
931 | + gdbarch_num_regs (current_gdbarch), | |
5792a79b | 932 | sigcontext_base + SIGCONTEXT_FPCSR); |
f57d151a UW |
933 | trad_frame_set_reg_addr (this_cache, |
934 | regs->hi + gdbarch_num_regs (current_gdbarch), | |
37c4d197 | 935 | regs_base + SIGCONTEXT_HI); |
f57d151a UW |
936 | trad_frame_set_reg_addr (this_cache, |
937 | regs->lo + gdbarch_num_regs (current_gdbarch), | |
37c4d197 | 938 | regs_base + SIGCONTEXT_LO); |
f57d151a UW |
939 | trad_frame_set_reg_addr (this_cache, |
940 | regs->cause + gdbarch_num_regs (current_gdbarch), | |
5792a79b | 941 | sigcontext_base + SIGCONTEXT_CAUSE); |
f57d151a UW |
942 | trad_frame_set_reg_addr (this_cache, |
943 | regs->badvaddr + gdbarch_num_regs (current_gdbarch), | |
5792a79b DJ |
944 | sigcontext_base + SIGCONTEXT_BADVADDR); |
945 | ||
946 | /* Choice of the bottom of the sigframe is somewhat arbitrary. */ | |
947 | trad_frame_set_id (this_cache, | |
295093a4 MS |
948 | frame_id_build (func - SIGFRAME_CODE_OFFSET, |
949 | func)); | |
5792a79b DJ |
950 | } |
951 | ||
952 | /* *INDENT-OFF* */ | |
953 | /* For N32/N64 things look different. There is no non-rt signal frame. | |
954 | ||
955 | struct rt_sigframe_n32 { | |
956 | u32 rs_ass[4]; [ argument save space for o32 ] | |
957 | u32 rs_code[2]; [ signal trampoline ] | |
958 | struct siginfo rs_info; | |
959 | struct ucontextn32 rs_uc; | |
960 | }; | |
961 | ||
962 | struct ucontextn32 { | |
963 | u32 uc_flags; | |
964 | s32 uc_link; | |
965 | stack32_t uc_stack; | |
966 | struct sigcontext uc_mcontext; | |
967 | sigset_t uc_sigmask; [ mask last for extensibility ] | |
968 | }; | |
295093a4 | 969 | |
5792a79b DJ |
970 | struct rt_sigframe_n32 { |
971 | u32 rs_ass[4]; [ argument save space for o32 ] | |
972 | u32 rs_code[2]; [ signal trampoline ] | |
973 | struct siginfo rs_info; | |
974 | struct ucontext rs_uc; | |
975 | }; | |
976 | ||
977 | struct ucontext { | |
978 | unsigned long uc_flags; | |
979 | struct ucontext *uc_link; | |
980 | stack_t uc_stack; | |
981 | struct sigcontext uc_mcontext; | |
982 | sigset_t uc_sigmask; [ mask last for extensibility ] | |
983 | }; | |
984 | ||
985 | And the sigcontext is different (this is for both n32 and n64): | |
986 | ||
987 | struct sigcontext { | |
988 | unsigned long long sc_regs[32]; | |
989 | unsigned long long sc_fpregs[32]; | |
990 | unsigned long long sc_mdhi; | |
991 | unsigned long long sc_mdlo; | |
992 | unsigned long long sc_pc; | |
993 | unsigned int sc_status; | |
994 | unsigned int sc_fpc_csr; | |
995 | unsigned int sc_fpc_eir; | |
996 | unsigned int sc_used_math; | |
997 | unsigned int sc_cause; | |
998 | unsigned int sc_badvaddr; | |
999 | }; */ | |
1000 | /* *INDENT-ON* */ | |
1001 | ||
1002 | #define N32_STACK_T_SIZE STACK_T_SIZE | |
1003 | #define N64_STACK_T_SIZE (2 * 8 + 4) | |
1004 | #define N32_UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + N32_STACK_T_SIZE + 4) | |
1005 | #define N64_UCONTEXT_SIGCONTEXT_OFFSET (2 * 8 + N64_STACK_T_SIZE + 4) | |
1006 | #define N32_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ | |
1007 | + RTSIGFRAME_SIGINFO_SIZE \ | |
1008 | + N32_UCONTEXT_SIGCONTEXT_OFFSET) | |
1009 | #define N64_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ | |
1010 | + RTSIGFRAME_SIGINFO_SIZE \ | |
1011 | + N64_UCONTEXT_SIGCONTEXT_OFFSET) | |
1012 | ||
1013 | #define N64_SIGCONTEXT_REGS (0 * 8) | |
1014 | #define N64_SIGCONTEXT_FPREGS (32 * 8) | |
1015 | #define N64_SIGCONTEXT_HI (64 * 8) | |
1016 | #define N64_SIGCONTEXT_LO (65 * 8) | |
1017 | #define N64_SIGCONTEXT_PC (66 * 8) | |
1018 | #define N64_SIGCONTEXT_FPCSR (67 * 8 + 1 * 4) | |
1019 | #define N64_SIGCONTEXT_FIR (67 * 8 + 2 * 4) | |
1020 | #define N64_SIGCONTEXT_CAUSE (67 * 8 + 4 * 4) | |
1021 | #define N64_SIGCONTEXT_BADVADDR (67 * 8 + 5 * 4) | |
1022 | ||
1023 | #define N64_SIGCONTEXT_REG_SIZE 8 | |
295093a4 | 1024 | |
5792a79b DJ |
1025 | static void |
1026 | mips_linux_n32n64_sigframe_init (const struct tramp_frame *self, | |
1027 | struct frame_info *next_frame, | |
1028 | struct trad_frame_cache *this_cache, | |
1029 | CORE_ADDR func) | |
1030 | { | |
1031 | int ireg, reg_position; | |
1032 | CORE_ADDR sigcontext_base = func - SIGFRAME_CODE_OFFSET; | |
1033 | const struct mips_regnum *regs = mips_regnum (current_gdbarch); | |
1034 | ||
1035 | if (self == &mips_linux_n32_rt_sigframe) | |
1036 | sigcontext_base += N32_SIGFRAME_SIGCONTEXT_OFFSET; | |
1037 | else | |
1038 | sigcontext_base += N64_SIGFRAME_SIGCONTEXT_OFFSET; | |
295093a4 | 1039 | |
822b6570 DJ |
1040 | if (mips_linux_restart_reg_p (current_gdbarch)) |
1041 | trad_frame_set_reg_addr (this_cache, | |
1042 | (MIPS_RESTART_REGNUM | |
1043 | + gdbarch_num_regs (current_gdbarch)), | |
1044 | sigcontext_base + N64_SIGCONTEXT_REGS); | |
5792a79b DJ |
1045 | |
1046 | for (ireg = 1; ireg < 32; ireg++) | |
295093a4 | 1047 | trad_frame_set_reg_addr (this_cache, |
f57d151a UW |
1048 | ireg + MIPS_ZERO_REGNUM |
1049 | + gdbarch_num_regs (current_gdbarch), | |
5792a79b DJ |
1050 | sigcontext_base + N64_SIGCONTEXT_REGS |
1051 | + ireg * N64_SIGCONTEXT_REG_SIZE); | |
1052 | ||
1053 | for (ireg = 0; ireg < 32; ireg++) | |
f57d151a UW |
1054 | trad_frame_set_reg_addr (this_cache, |
1055 | ireg + regs->fp0 | |
1056 | + gdbarch_num_regs (current_gdbarch), | |
5792a79b DJ |
1057 | sigcontext_base + N64_SIGCONTEXT_FPREGS |
1058 | + ireg * N64_SIGCONTEXT_REG_SIZE); | |
1059 | ||
f57d151a UW |
1060 | trad_frame_set_reg_addr (this_cache, |
1061 | regs->pc + gdbarch_num_regs (current_gdbarch), | |
5792a79b DJ |
1062 | sigcontext_base + N64_SIGCONTEXT_PC); |
1063 | ||
295093a4 | 1064 | trad_frame_set_reg_addr (this_cache, |
f57d151a UW |
1065 | regs->fp_control_status |
1066 | + gdbarch_num_regs (current_gdbarch), | |
5792a79b | 1067 | sigcontext_base + N64_SIGCONTEXT_FPCSR); |
f57d151a UW |
1068 | trad_frame_set_reg_addr (this_cache, |
1069 | regs->hi + gdbarch_num_regs (current_gdbarch), | |
5792a79b | 1070 | sigcontext_base + N64_SIGCONTEXT_HI); |
f57d151a UW |
1071 | trad_frame_set_reg_addr (this_cache, |
1072 | regs->lo + gdbarch_num_regs (current_gdbarch), | |
5792a79b | 1073 | sigcontext_base + N64_SIGCONTEXT_LO); |
f57d151a UW |
1074 | trad_frame_set_reg_addr (this_cache, |
1075 | regs->cause + gdbarch_num_regs (current_gdbarch), | |
5792a79b | 1076 | sigcontext_base + N64_SIGCONTEXT_CAUSE); |
f57d151a UW |
1077 | trad_frame_set_reg_addr (this_cache, |
1078 | regs->badvaddr + gdbarch_num_regs (current_gdbarch), | |
5792a79b DJ |
1079 | sigcontext_base + N64_SIGCONTEXT_BADVADDR); |
1080 | ||
1081 | /* Choice of the bottom of the sigframe is somewhat arbitrary. */ | |
1082 | trad_frame_set_id (this_cache, | |
295093a4 MS |
1083 | frame_id_build (func - SIGFRAME_CODE_OFFSET, |
1084 | func)); | |
5792a79b DJ |
1085 | } |
1086 | ||
822b6570 | 1087 | static void |
61a1198a | 1088 | mips_linux_write_pc (struct regcache *regcache, CORE_ADDR pc) |
822b6570 | 1089 | { |
3e8c568d UW |
1090 | regcache_cooked_write_unsigned (regcache, |
1091 | gdbarch_pc_regnum (current_gdbarch), pc); | |
822b6570 DJ |
1092 | |
1093 | /* Clear the syscall restart flag. */ | |
1094 | if (mips_linux_restart_reg_p (current_gdbarch)) | |
61a1198a | 1095 | regcache_cooked_write_unsigned (regcache, MIPS_RESTART_REGNUM, 0); |
822b6570 DJ |
1096 | } |
1097 | ||
1098 | /* Return 1 if MIPS_RESTART_REGNUM is usable. */ | |
1099 | ||
1100 | int | |
1101 | mips_linux_restart_reg_p (struct gdbarch *gdbarch) | |
1102 | { | |
1103 | /* If we do not have a target description with registers, then | |
1104 | MIPS_RESTART_REGNUM will not be included in the register set. */ | |
1105 | if (!tdesc_has_registers (gdbarch_target_desc (gdbarch))) | |
1106 | return 0; | |
1107 | ||
1108 | /* If we do, then MIPS_RESTART_REGNUM is safe to check; it will | |
1109 | either be GPR-sized or missing. */ | |
1110 | return register_size (gdbarch, MIPS_RESTART_REGNUM) > 0; | |
1111 | } | |
9f62d0e2 | 1112 | |
5792a79b DJ |
1113 | /* Initialize one of the GNU/Linux OS ABIs. */ |
1114 | ||
19ed69dd | 1115 | static void |
295093a4 MS |
1116 | mips_linux_init_abi (struct gdbarch_info info, |
1117 | struct gdbarch *gdbarch) | |
19ed69dd | 1118 | { |
96f026fc KB |
1119 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1120 | enum mips_abi abi = mips_abi (gdbarch); | |
822b6570 | 1121 | struct tdesc_arch_data *tdesc_data = (void *) info.tdep_info; |
96f026fc KB |
1122 | |
1123 | switch (abi) | |
1124 | { | |
1125 | case MIPS_ABI_O32: | |
1126 | set_gdbarch_get_longjmp_target (gdbarch, | |
1127 | mips_linux_get_longjmp_target); | |
1128 | set_solib_svr4_fetch_link_map_offsets | |
76a9d10f | 1129 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); |
fb2be677 AC |
1130 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_sigframe); |
1131 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_rt_sigframe); | |
96f026fc KB |
1132 | break; |
1133 | case MIPS_ABI_N32: | |
1134 | set_gdbarch_get_longjmp_target (gdbarch, | |
1135 | mips_linux_get_longjmp_target); | |
1136 | set_solib_svr4_fetch_link_map_offsets | |
76a9d10f | 1137 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); |
d05f6826 DJ |
1138 | set_gdbarch_long_double_bit (gdbarch, 128); |
1139 | /* These floatformats should probably be renamed. MIPS uses | |
1140 | the same 128-bit IEEE floating point format that IA-64 uses, | |
1141 | except that the quiet/signalling NaN bit is reversed (GDB | |
1142 | does not distinguish between quiet and signalling NaNs). */ | |
8da61cc4 | 1143 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); |
fb2be677 | 1144 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n32_rt_sigframe); |
96f026fc KB |
1145 | break; |
1146 | case MIPS_ABI_N64: | |
1147 | set_gdbarch_get_longjmp_target (gdbarch, | |
1148 | mips64_linux_get_longjmp_target); | |
1149 | set_solib_svr4_fetch_link_map_offsets | |
76a9d10f | 1150 | (gdbarch, svr4_lp64_fetch_link_map_offsets); |
d05f6826 DJ |
1151 | set_gdbarch_long_double_bit (gdbarch, 128); |
1152 | /* These floatformats should probably be renamed. MIPS uses | |
1153 | the same 128-bit IEEE floating point format that IA-64 uses, | |
1154 | except that the quiet/signalling NaN bit is reversed (GDB | |
1155 | does not distinguish between quiet and signalling NaNs). */ | |
8da61cc4 | 1156 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); |
fb2be677 | 1157 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n64_rt_sigframe); |
96f026fc KB |
1158 | break; |
1159 | default: | |
e2e0b3e5 | 1160 | internal_error (__FILE__, __LINE__, _("can't handle ABI")); |
96f026fc KB |
1161 | break; |
1162 | } | |
6de918a6 | 1163 | |
982e9687 | 1164 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
6de918a6 DJ |
1165 | set_gdbarch_skip_solib_resolver (gdbarch, mips_linux_skip_resolver); |
1166 | ||
0d0266c6 | 1167 | set_gdbarch_software_single_step (gdbarch, mips_software_single_step); |
b2756930 KB |
1168 | |
1169 | /* Enable TLS support. */ | |
1170 | set_gdbarch_fetch_tls_load_module_address (gdbarch, | |
1171 | svr4_fetch_objfile_link_map); | |
7d522c90 DJ |
1172 | |
1173 | /* Initialize this lazily, to avoid an initialization order | |
1174 | dependency on solib-svr4.c's _initialize routine. */ | |
1175 | if (mips_svr4_so_ops.in_dynsym_resolve_code == NULL) | |
1176 | { | |
1177 | mips_svr4_so_ops = svr4_so_ops; | |
1178 | mips_svr4_so_ops.in_dynsym_resolve_code | |
1179 | = mips_linux_in_dynsym_resolve_code; | |
1180 | } | |
1181 | set_solib_ops (gdbarch, &mips_svr4_so_ops); | |
822b6570 DJ |
1182 | |
1183 | set_gdbarch_write_pc (gdbarch, mips_linux_write_pc); | |
1184 | ||
4eb0ad19 DJ |
1185 | set_gdbarch_core_read_description (gdbarch, |
1186 | mips_linux_core_read_description); | |
1187 | ||
822b6570 DJ |
1188 | if (tdesc_data) |
1189 | { | |
1190 | const struct tdesc_feature *feature; | |
1191 | ||
1192 | /* If we have target-described registers, then we can safely | |
1193 | reserve a number for MIPS_RESTART_REGNUM (whether it is | |
1194 | described or not). */ | |
1195 | gdb_assert (gdbarch_num_regs (gdbarch) <= MIPS_RESTART_REGNUM); | |
1196 | set_gdbarch_num_regs (gdbarch, MIPS_RESTART_REGNUM + 1); | |
1197 | ||
1198 | /* If it's present, then assign it to the reserved number. */ | |
1199 | feature = tdesc_find_feature (info.target_desc, | |
1200 | "org.gnu.gdb.mips.linux"); | |
1201 | if (feature != NULL) | |
1202 | tdesc_numbered_register (feature, tdesc_data, MIPS_RESTART_REGNUM, | |
1203 | "restart"); | |
1204 | } | |
19ed69dd KB |
1205 | } |
1206 | ||
2aa830e4 | 1207 | void |
d1bacddc | 1208 | _initialize_mips_linux_tdep (void) |
2aa830e4 | 1209 | { |
96f026fc KB |
1210 | const struct bfd_arch_info *arch_info; |
1211 | ||
96f026fc KB |
1212 | for (arch_info = bfd_lookup_arch (bfd_arch_mips, 0); |
1213 | arch_info != NULL; | |
1214 | arch_info = arch_info->next) | |
1215 | { | |
295093a4 MS |
1216 | gdbarch_register_osabi (bfd_arch_mips, arch_info->mach, |
1217 | GDB_OSABI_LINUX, | |
96f026fc KB |
1218 | mips_linux_init_abi); |
1219 | } | |
1220 | ||
00e32a35 | 1221 | deprecated_add_core_fns (®set_core_fns); |
2aa830e4 | 1222 | } |