Commit | Line | Data |
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75c9abc6 | 1 | /* Target-dependent code for GNU/Linux on MIPS processors. |
a094c6fb | 2 | |
0b302171 | 3 | Copyright (C) 2001-2002, 2004-2012 Free Software Foundation, Inc. |
2aa830e4 DJ |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
2aa830e4 DJ |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
2aa830e4 DJ |
19 | |
20 | #include "defs.h" | |
21 | #include "gdbcore.h" | |
22 | #include "target.h" | |
23 | #include "solib-svr4.h" | |
19ed69dd | 24 | #include "osabi.h" |
96f026fc | 25 | #include "mips-tdep.h" |
19ed69dd | 26 | #include "gdb_string.h" |
96f026fc | 27 | #include "gdb_assert.h" |
6de918a6 | 28 | #include "frame.h" |
2fdf551c | 29 | #include "regcache.h" |
5792a79b DJ |
30 | #include "trad-frame.h" |
31 | #include "tramp-frame.h" | |
e6bb342a | 32 | #include "gdbtypes.h" |
5ea03926 | 33 | #include "solib.h" |
7d522c90 DJ |
34 | #include "solib-svr4.h" |
35 | #include "solist.h" | |
982e9687 | 36 | #include "symtab.h" |
822b6570 | 37 | #include "target-descriptions.h" |
50e8a0d5 | 38 | #include "regset.h" |
d37eb719 | 39 | #include "mips-linux-tdep.h" |
db5f024e | 40 | #include "glibc-tdep.h" |
a5ee0f0c | 41 | #include "linux-tdep.h" |
385203ed | 42 | #include "xml-syscall.h" |
2aa830e4 | 43 | |
7d522c90 DJ |
44 | static struct target_so_ops mips_svr4_so_ops; |
45 | ||
2aa830e4 | 46 | /* Figure out where the longjmp will land. |
295093a4 MS |
47 | We expect the first arg to be a pointer to the jmp_buf structure |
48 | from which we extract the pc (MIPS_LINUX_JB_PC) that we will land | |
49 | at. The pc is copied into PC. This routine returns 1 on | |
50 | success. */ | |
2aa830e4 | 51 | |
19ed69dd KB |
52 | #define MIPS_LINUX_JB_ELEMENT_SIZE 4 |
53 | #define MIPS_LINUX_JB_PC 0 | |
54 | ||
55 | static int | |
60ade65d | 56 | mips_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
2aa830e4 DJ |
57 | { |
58 | CORE_ADDR jb_addr; | |
2eb4d78b | 59 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 60 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2eb4d78b | 61 | char buf[gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT]; |
2aa830e4 | 62 | |
60ade65d | 63 | jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM); |
2aa830e4 | 64 | |
bf072999 | 65 | if (target_read_memory (jb_addr |
819844ad | 66 | + MIPS_LINUX_JB_PC * MIPS_LINUX_JB_ELEMENT_SIZE, |
2eb4d78b | 67 | buf, gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT)) |
2aa830e4 DJ |
68 | return 0; |
69 | ||
819844ad | 70 | *pc = extract_unsigned_integer (buf, |
e17a4113 UW |
71 | gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT, |
72 | byte_order); | |
2aa830e4 DJ |
73 | |
74 | return 1; | |
75 | } | |
76 | ||
4246e332 | 77 | /* Transform the bits comprising a 32-bit register to the right size |
23a6d369 AC |
78 | for regcache_raw_supply(). This is needed when mips_isa_regsize() |
79 | is 8. */ | |
96f026fc KB |
80 | |
81 | static void | |
28f5035f | 82 | supply_32bit_reg (struct regcache *regcache, int regnum, const void *addr) |
96f026fc | 83 | { |
e17a4113 UW |
84 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
85 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
d37eb719 | 86 | gdb_byte buf[MAX_REGISTER_SIZE]; |
e17a4113 UW |
87 | store_signed_integer (buf, register_size (gdbarch, regnum), byte_order, |
88 | extract_signed_integer (addr, 4, byte_order)); | |
28f5035f | 89 | regcache_raw_supply (regcache, regnum, buf); |
96f026fc KB |
90 | } |
91 | ||
2aa830e4 DJ |
92 | /* Unpack an elf_gregset_t into GDB's register cache. */ |
93 | ||
d37eb719 | 94 | void |
28f5035f UW |
95 | mips_supply_gregset (struct regcache *regcache, |
96 | const mips_elf_gregset_t *gregsetp) | |
2aa830e4 DJ |
97 | { |
98 | int regi; | |
28f5035f | 99 | const mips_elf_greg_t *regp = *gregsetp; |
d9d9c31f | 100 | char zerobuf[MAX_REGISTER_SIZE]; |
2eb4d78b | 101 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
bf072999 | 102 | |
d9d9c31f | 103 | memset (zerobuf, 0, MAX_REGISTER_SIZE); |
2aa830e4 | 104 | |
822b6570 | 105 | for (regi = EF_REG0 + 1; regi <= EF_REG31; regi++) |
28f5035f | 106 | supply_32bit_reg (regcache, regi - EF_REG0, regp + regi); |
2aa830e4 | 107 | |
2eb4d78b | 108 | if (mips_linux_restart_reg_p (gdbarch)) |
822b6570 DJ |
109 | supply_32bit_reg (regcache, MIPS_RESTART_REGNUM, regp + EF_REG0); |
110 | ||
2eb4d78b UW |
111 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->lo, regp + EF_LO); |
112 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->hi, regp + EF_HI); | |
56cea623 | 113 | |
2eb4d78b | 114 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->pc, |
28f5035f | 115 | regp + EF_CP0_EPC); |
2eb4d78b | 116 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->badvaddr, |
28f5035f UW |
117 | regp + EF_CP0_BADVADDR); |
118 | supply_32bit_reg (regcache, MIPS_PS_REGNUM, regp + EF_CP0_STATUS); | |
2eb4d78b | 119 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->cause, |
28f5035f | 120 | regp + EF_CP0_CAUSE); |
2aa830e4 DJ |
121 | |
122 | /* Fill inaccessible registers with zero. */ | |
822b6570 | 123 | regcache_raw_supply (regcache, MIPS_ZERO_REGNUM, zerobuf); |
28f5035f | 124 | regcache_raw_supply (regcache, MIPS_UNUSED_REGNUM, zerobuf); |
295093a4 | 125 | for (regi = MIPS_FIRST_EMBED_REGNUM; |
822b6570 | 126 | regi <= MIPS_LAST_EMBED_REGNUM; |
295093a4 | 127 | regi++) |
28f5035f | 128 | regcache_raw_supply (regcache, regi, zerobuf); |
2aa830e4 DJ |
129 | } |
130 | ||
50e8a0d5 HZ |
131 | static void |
132 | mips_supply_gregset_wrapper (const struct regset *regset, | |
133 | struct regcache *regcache, | |
134 | int regnum, const void *gregs, size_t len) | |
135 | { | |
136 | gdb_assert (len == sizeof (mips_elf_gregset_t)); | |
137 | ||
138 | mips_supply_gregset (regcache, (const mips_elf_gregset_t *)gregs); | |
139 | } | |
140 | ||
2aa830e4 DJ |
141 | /* Pack our registers (or one register) into an elf_gregset_t. */ |
142 | ||
d37eb719 | 143 | void |
28f5035f UW |
144 | mips_fill_gregset (const struct regcache *regcache, |
145 | mips_elf_gregset_t *gregsetp, int regno) | |
2aa830e4 | 146 | { |
2eb4d78b | 147 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
2aa830e4 | 148 | int regaddr, regi; |
d37eb719 | 149 | mips_elf_greg_t *regp = *gregsetp; |
96f026fc | 150 | void *dst; |
2aa830e4 DJ |
151 | |
152 | if (regno == -1) | |
153 | { | |
d37eb719 | 154 | memset (regp, 0, sizeof (mips_elf_gregset_t)); |
822b6570 | 155 | for (regi = 1; regi < 32; regi++) |
28f5035f | 156 | mips_fill_gregset (regcache, gregsetp, regi); |
2eb4d78b UW |
157 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->lo); |
158 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->hi); | |
159 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->pc); | |
160 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->badvaddr); | |
28f5035f | 161 | mips_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM); |
2eb4d78b | 162 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->cause); |
822b6570 | 163 | mips_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM); |
2aa830e4 DJ |
164 | return; |
165 | } | |
166 | ||
822b6570 | 167 | if (regno > 0 && regno < 32) |
2aa830e4 | 168 | { |
2aa830e4 | 169 | dst = regp + regno + EF_REG0; |
28f5035f | 170 | regcache_raw_collect (regcache, regno, dst); |
2aa830e4 DJ |
171 | return; |
172 | } | |
173 | ||
2eb4d78b UW |
174 | if (regno == mips_regnum (gdbarch)->lo) |
175 | regaddr = EF_LO; | |
176 | else if (regno == mips_regnum (gdbarch)->hi) | |
56cea623 | 177 | regaddr = EF_HI; |
2eb4d78b | 178 | else if (regno == mips_regnum (gdbarch)->pc) |
56cea623 | 179 | regaddr = EF_CP0_EPC; |
2eb4d78b | 180 | else if (regno == mips_regnum (gdbarch)->badvaddr) |
56cea623 | 181 | regaddr = EF_CP0_BADVADDR; |
24e05951 | 182 | else if (regno == MIPS_PS_REGNUM) |
56cea623 | 183 | regaddr = EF_CP0_STATUS; |
2eb4d78b | 184 | else if (regno == mips_regnum (gdbarch)->cause) |
56cea623 | 185 | regaddr = EF_CP0_CAUSE; |
2eb4d78b | 186 | else if (mips_linux_restart_reg_p (gdbarch) |
822b6570 DJ |
187 | && regno == MIPS_RESTART_REGNUM) |
188 | regaddr = EF_REG0; | |
56cea623 AC |
189 | else |
190 | regaddr = -1; | |
2aa830e4 DJ |
191 | |
192 | if (regaddr != -1) | |
193 | { | |
2aa830e4 | 194 | dst = regp + regaddr; |
28f5035f | 195 | regcache_raw_collect (regcache, regno, dst); |
2aa830e4 DJ |
196 | } |
197 | } | |
198 | ||
50e8a0d5 HZ |
199 | static void |
200 | mips_fill_gregset_wrapper (const struct regset *regset, | |
201 | const struct regcache *regcache, | |
202 | int regnum, void *gregs, size_t len) | |
203 | { | |
204 | gdb_assert (len == sizeof (mips_elf_gregset_t)); | |
205 | ||
206 | mips_fill_gregset (regcache, (mips_elf_gregset_t *)gregs, regnum); | |
207 | } | |
208 | ||
2aa830e4 DJ |
209 | /* Likewise, unpack an elf_fpregset_t. */ |
210 | ||
d37eb719 | 211 | void |
28f5035f UW |
212 | mips_supply_fpregset (struct regcache *regcache, |
213 | const mips_elf_fpregset_t *fpregsetp) | |
2aa830e4 | 214 | { |
2eb4d78b | 215 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
52f0bd74 | 216 | int regi; |
d9d9c31f | 217 | char zerobuf[MAX_REGISTER_SIZE]; |
bf072999 | 218 | |
d9d9c31f | 219 | memset (zerobuf, 0, MAX_REGISTER_SIZE); |
2aa830e4 DJ |
220 | |
221 | for (regi = 0; regi < 32; regi++) | |
3e8c568d | 222 | regcache_raw_supply (regcache, |
2eb4d78b | 223 | gdbarch_fp0_regnum (gdbarch) + regi, |
3e8c568d | 224 | *fpregsetp + regi); |
2aa830e4 | 225 | |
28f5035f | 226 | regcache_raw_supply (regcache, |
2eb4d78b | 227 | mips_regnum (gdbarch)->fp_control_status, |
28f5035f | 228 | *fpregsetp + 32); |
2aa830e4 | 229 | |
295093a4 | 230 | /* FIXME: how can we supply FCRIR? The ABI doesn't tell us. */ |
28f5035f | 231 | regcache_raw_supply (regcache, |
2eb4d78b | 232 | mips_regnum (gdbarch)->fp_implementation_revision, |
23a6d369 | 233 | zerobuf); |
2aa830e4 DJ |
234 | } |
235 | ||
50e8a0d5 HZ |
236 | static void |
237 | mips_supply_fpregset_wrapper (const struct regset *regset, | |
238 | struct regcache *regcache, | |
239 | int regnum, const void *gregs, size_t len) | |
240 | { | |
241 | gdb_assert (len == sizeof (mips_elf_fpregset_t)); | |
242 | ||
243 | mips_supply_fpregset (regcache, (const mips_elf_fpregset_t *)gregs); | |
244 | } | |
245 | ||
2aa830e4 DJ |
246 | /* Likewise, pack one or all floating point registers into an |
247 | elf_fpregset_t. */ | |
248 | ||
d37eb719 | 249 | void |
28f5035f UW |
250 | mips_fill_fpregset (const struct regcache *regcache, |
251 | mips_elf_fpregset_t *fpregsetp, int regno) | |
2aa830e4 | 252 | { |
2eb4d78b | 253 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
2aa830e4 DJ |
254 | char *from, *to; |
255 | ||
2eb4d78b UW |
256 | if ((regno >= gdbarch_fp0_regnum (gdbarch)) |
257 | && (regno < gdbarch_fp0_regnum (gdbarch) + 32)) | |
2aa830e4 | 258 | { |
2eb4d78b | 259 | to = (char *) (*fpregsetp + regno - gdbarch_fp0_regnum (gdbarch)); |
28f5035f | 260 | regcache_raw_collect (regcache, regno, to); |
2aa830e4 | 261 | } |
2eb4d78b | 262 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
2aa830e4 | 263 | { |
2aa830e4 | 264 | to = (char *) (*fpregsetp + 32); |
28f5035f | 265 | regcache_raw_collect (regcache, regno, to); |
2aa830e4 DJ |
266 | } |
267 | else if (regno == -1) | |
268 | { | |
269 | int regi; | |
270 | ||
271 | for (regi = 0; regi < 32; regi++) | |
3e8c568d | 272 | mips_fill_fpregset (regcache, fpregsetp, |
2eb4d78b | 273 | gdbarch_fp0_regnum (gdbarch) + regi); |
28f5035f | 274 | mips_fill_fpregset (regcache, fpregsetp, |
2eb4d78b | 275 | mips_regnum (gdbarch)->fp_control_status); |
2aa830e4 DJ |
276 | } |
277 | } | |
278 | ||
50e8a0d5 HZ |
279 | static void |
280 | mips_fill_fpregset_wrapper (const struct regset *regset, | |
281 | const struct regcache *regcache, | |
282 | int regnum, void *gregs, size_t len) | |
283 | { | |
284 | gdb_assert (len == sizeof (mips_elf_fpregset_t)); | |
285 | ||
286 | mips_fill_fpregset (regcache, (mips_elf_fpregset_t *)gregs, regnum); | |
287 | } | |
288 | ||
96f026fc KB |
289 | /* Support for 64-bit ABIs. */ |
290 | ||
96f026fc | 291 | /* Figure out where the longjmp will land. |
295093a4 MS |
292 | We expect the first arg to be a pointer to the jmp_buf structure |
293 | from which we extract the pc (MIPS_LINUX_JB_PC) that we will land | |
294 | at. The pc is copied into PC. This routine returns 1 on | |
295 | success. */ | |
96f026fc KB |
296 | |
297 | /* Details about jmp_buf. */ | |
298 | ||
299 | #define MIPS64_LINUX_JB_PC 0 | |
300 | ||
301 | static int | |
60ade65d | 302 | mips64_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
96f026fc KB |
303 | { |
304 | CORE_ADDR jb_addr; | |
2eb4d78b | 305 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 306 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2eb4d78b UW |
307 | void *buf = alloca (gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT); |
308 | int element_size = gdbarch_ptr_bit (gdbarch) == 32 ? 4 : 8; | |
96f026fc | 309 | |
60ade65d | 310 | jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM); |
96f026fc KB |
311 | |
312 | if (target_read_memory (jb_addr + MIPS64_LINUX_JB_PC * element_size, | |
819844ad | 313 | buf, |
2eb4d78b | 314 | gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT)) |
96f026fc KB |
315 | return 0; |
316 | ||
819844ad | 317 | *pc = extract_unsigned_integer (buf, |
e17a4113 UW |
318 | gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT, |
319 | byte_order); | |
96f026fc KB |
320 | |
321 | return 1; | |
322 | } | |
323 | ||
d37eb719 DJ |
324 | /* Register set support functions. These operate on standard 64-bit |
325 | regsets, but work whether the target is 32-bit or 64-bit. A 32-bit | |
326 | target will still use the 64-bit format for PTRACE_GETREGS. */ | |
327 | ||
328 | /* Supply a 64-bit register. */ | |
96f026fc | 329 | |
63807e1d | 330 | static void |
28f5035f UW |
331 | supply_64bit_reg (struct regcache *regcache, int regnum, |
332 | const gdb_byte *buf) | |
d37eb719 | 333 | { |
2eb4d78b UW |
334 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
335 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG | |
336 | && register_size (gdbarch, regnum) == 4) | |
28f5035f | 337 | regcache_raw_supply (regcache, regnum, buf + 4); |
d37eb719 | 338 | else |
28f5035f | 339 | regcache_raw_supply (regcache, regnum, buf); |
d37eb719 DJ |
340 | } |
341 | ||
342 | /* Unpack a 64-bit elf_gregset_t into GDB's register cache. */ | |
343 | ||
344 | void | |
28f5035f UW |
345 | mips64_supply_gregset (struct regcache *regcache, |
346 | const mips64_elf_gregset_t *gregsetp) | |
96f026fc KB |
347 | { |
348 | int regi; | |
28f5035f | 349 | const mips64_elf_greg_t *regp = *gregsetp; |
d37eb719 | 350 | gdb_byte zerobuf[MAX_REGISTER_SIZE]; |
2eb4d78b | 351 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
96f026fc | 352 | |
d9d9c31f | 353 | memset (zerobuf, 0, MAX_REGISTER_SIZE); |
96f026fc | 354 | |
822b6570 | 355 | for (regi = MIPS64_EF_REG0 + 1; regi <= MIPS64_EF_REG31; regi++) |
28f5035f UW |
356 | supply_64bit_reg (regcache, regi - MIPS64_EF_REG0, |
357 | (const gdb_byte *)(regp + regi)); | |
358 | ||
2eb4d78b | 359 | if (mips_linux_restart_reg_p (gdbarch)) |
822b6570 DJ |
360 | supply_64bit_reg (regcache, MIPS_RESTART_REGNUM, |
361 | (const gdb_byte *)(regp + MIPS64_EF_REG0)); | |
362 | ||
2eb4d78b | 363 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->lo, |
28f5035f | 364 | (const gdb_byte *) (regp + MIPS64_EF_LO)); |
2eb4d78b | 365 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->hi, |
28f5035f UW |
366 | (const gdb_byte *) (regp + MIPS64_EF_HI)); |
367 | ||
2eb4d78b | 368 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->pc, |
28f5035f | 369 | (const gdb_byte *) (regp + MIPS64_EF_CP0_EPC)); |
2eb4d78b | 370 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->badvaddr, |
28f5035f UW |
371 | (const gdb_byte *) (regp + MIPS64_EF_CP0_BADVADDR)); |
372 | supply_64bit_reg (regcache, MIPS_PS_REGNUM, | |
373 | (const gdb_byte *) (regp + MIPS64_EF_CP0_STATUS)); | |
2eb4d78b | 374 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->cause, |
28f5035f | 375 | (const gdb_byte *) (regp + MIPS64_EF_CP0_CAUSE)); |
96f026fc KB |
376 | |
377 | /* Fill inaccessible registers with zero. */ | |
822b6570 | 378 | regcache_raw_supply (regcache, MIPS_ZERO_REGNUM, zerobuf); |
28f5035f | 379 | regcache_raw_supply (regcache, MIPS_UNUSED_REGNUM, zerobuf); |
295093a4 | 380 | for (regi = MIPS_FIRST_EMBED_REGNUM; |
822b6570 | 381 | regi <= MIPS_LAST_EMBED_REGNUM; |
295093a4 | 382 | regi++) |
28f5035f | 383 | regcache_raw_supply (regcache, regi, zerobuf); |
96f026fc KB |
384 | } |
385 | ||
50e8a0d5 HZ |
386 | static void |
387 | mips64_supply_gregset_wrapper (const struct regset *regset, | |
388 | struct regcache *regcache, | |
389 | int regnum, const void *gregs, size_t len) | |
390 | { | |
391 | gdb_assert (len == sizeof (mips64_elf_gregset_t)); | |
392 | ||
393 | mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *)gregs); | |
394 | } | |
395 | ||
d37eb719 | 396 | /* Pack our registers (or one register) into a 64-bit elf_gregset_t. */ |
96f026fc | 397 | |
d37eb719 | 398 | void |
28f5035f UW |
399 | mips64_fill_gregset (const struct regcache *regcache, |
400 | mips64_elf_gregset_t *gregsetp, int regno) | |
96f026fc | 401 | { |
2eb4d78b | 402 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
e17a4113 | 403 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
96f026fc KB |
404 | int regaddr, regi; |
405 | mips64_elf_greg_t *regp = *gregsetp; | |
2ba93934 | 406 | void *dst; |
96f026fc KB |
407 | |
408 | if (regno == -1) | |
409 | { | |
410 | memset (regp, 0, sizeof (mips64_elf_gregset_t)); | |
822b6570 | 411 | for (regi = 1; regi < 32; regi++) |
28f5035f | 412 | mips64_fill_gregset (regcache, gregsetp, regi); |
2eb4d78b UW |
413 | mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->lo); |
414 | mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->hi); | |
415 | mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->pc); | |
025bb325 MS |
416 | mips64_fill_gregset (regcache, gregsetp, |
417 | mips_regnum (gdbarch)->badvaddr); | |
28f5035f | 418 | mips64_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM); |
2eb4d78b | 419 | mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->cause); |
822b6570 | 420 | mips64_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM); |
96f026fc KB |
421 | return; |
422 | } | |
423 | ||
822b6570 | 424 | if (regno > 0 && regno < 32) |
d37eb719 | 425 | regaddr = regno + MIPS64_EF_REG0; |
2eb4d78b | 426 | else if (regno == mips_regnum (gdbarch)->lo) |
56cea623 | 427 | regaddr = MIPS64_EF_LO; |
2eb4d78b | 428 | else if (regno == mips_regnum (gdbarch)->hi) |
56cea623 | 429 | regaddr = MIPS64_EF_HI; |
2eb4d78b | 430 | else if (regno == mips_regnum (gdbarch)->pc) |
56cea623 | 431 | regaddr = MIPS64_EF_CP0_EPC; |
2eb4d78b | 432 | else if (regno == mips_regnum (gdbarch)->badvaddr) |
56cea623 | 433 | regaddr = MIPS64_EF_CP0_BADVADDR; |
24e05951 | 434 | else if (regno == MIPS_PS_REGNUM) |
56cea623 | 435 | regaddr = MIPS64_EF_CP0_STATUS; |
2eb4d78b | 436 | else if (regno == mips_regnum (gdbarch)->cause) |
56cea623 | 437 | regaddr = MIPS64_EF_CP0_CAUSE; |
2eb4d78b | 438 | else if (mips_linux_restart_reg_p (gdbarch) |
822b6570 DJ |
439 | && regno == MIPS_RESTART_REGNUM) |
440 | regaddr = MIPS64_EF_REG0; | |
56cea623 AC |
441 | else |
442 | regaddr = -1; | |
96f026fc KB |
443 | |
444 | if (regaddr != -1) | |
445 | { | |
d37eb719 DJ |
446 | gdb_byte buf[MAX_REGISTER_SIZE]; |
447 | LONGEST val; | |
448 | ||
28f5035f | 449 | regcache_raw_collect (regcache, regno, buf); |
e17a4113 UW |
450 | val = extract_signed_integer (buf, register_size (gdbarch, regno), |
451 | byte_order); | |
96f026fc | 452 | dst = regp + regaddr; |
e17a4113 | 453 | store_signed_integer (dst, 8, byte_order, val); |
96f026fc KB |
454 | } |
455 | } | |
456 | ||
50e8a0d5 HZ |
457 | static void |
458 | mips64_fill_gregset_wrapper (const struct regset *regset, | |
459 | const struct regcache *regcache, | |
460 | int regnum, void *gregs, size_t len) | |
461 | { | |
462 | gdb_assert (len == sizeof (mips64_elf_gregset_t)); | |
463 | ||
464 | mips64_fill_gregset (regcache, (mips64_elf_gregset_t *)gregs, regnum); | |
465 | } | |
466 | ||
96f026fc KB |
467 | /* Likewise, unpack an elf_fpregset_t. */ |
468 | ||
d37eb719 | 469 | void |
28f5035f UW |
470 | mips64_supply_fpregset (struct regcache *regcache, |
471 | const mips64_elf_fpregset_t *fpregsetp) | |
96f026fc | 472 | { |
2eb4d78b | 473 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
52f0bd74 | 474 | int regi; |
96f026fc | 475 | |
d37eb719 DJ |
476 | /* See mips_linux_o32_sigframe_init for a description of the |
477 | peculiar FP register layout. */ | |
2eb4d78b | 478 | if (register_size (gdbarch, gdbarch_fp0_regnum (gdbarch)) == 4) |
d37eb719 DJ |
479 | for (regi = 0; regi < 32; regi++) |
480 | { | |
28f5035f | 481 | const gdb_byte *reg_ptr = (const gdb_byte *)(*fpregsetp + (regi & ~1)); |
2eb4d78b | 482 | if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (regi & 1)) |
d37eb719 | 483 | reg_ptr += 4; |
3e8c568d | 484 | regcache_raw_supply (regcache, |
2eb4d78b | 485 | gdbarch_fp0_regnum (gdbarch) + regi, |
3e8c568d | 486 | reg_ptr); |
d37eb719 DJ |
487 | } |
488 | else | |
489 | for (regi = 0; regi < 32; regi++) | |
3e8c568d | 490 | regcache_raw_supply (regcache, |
2eb4d78b | 491 | gdbarch_fp0_regnum (gdbarch) + regi, |
28f5035f | 492 | (const char *)(*fpregsetp + regi)); |
d37eb719 | 493 | |
2eb4d78b | 494 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->fp_control_status, |
28f5035f | 495 | (const gdb_byte *)(*fpregsetp + 32)); |
d37eb719 DJ |
496 | |
497 | /* The ABI doesn't tell us how to supply FCRIR, and core dumps don't | |
498 | include it - but the result of PTRACE_GETFPREGS does. The best we | |
499 | can do is to assume that its value is present. */ | |
28f5035f | 500 | supply_32bit_reg (regcache, |
2eb4d78b | 501 | mips_regnum (gdbarch)->fp_implementation_revision, |
28f5035f | 502 | (const gdb_byte *)(*fpregsetp + 32) + 4); |
96f026fc KB |
503 | } |
504 | ||
50e8a0d5 HZ |
505 | static void |
506 | mips64_supply_fpregset_wrapper (const struct regset *regset, | |
507 | struct regcache *regcache, | |
508 | int regnum, const void *gregs, size_t len) | |
509 | { | |
510 | gdb_assert (len == sizeof (mips64_elf_fpregset_t)); | |
511 | ||
512 | mips64_supply_fpregset (regcache, (const mips64_elf_fpregset_t *)gregs); | |
513 | } | |
514 | ||
96f026fc KB |
515 | /* Likewise, pack one or all floating point registers into an |
516 | elf_fpregset_t. */ | |
517 | ||
d37eb719 | 518 | void |
28f5035f UW |
519 | mips64_fill_fpregset (const struct regcache *regcache, |
520 | mips64_elf_fpregset_t *fpregsetp, int regno) | |
96f026fc | 521 | { |
2eb4d78b | 522 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
e17a4113 | 523 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d37eb719 | 524 | gdb_byte *to; |
96f026fc | 525 | |
2eb4d78b UW |
526 | if ((regno >= gdbarch_fp0_regnum (gdbarch)) |
527 | && (regno < gdbarch_fp0_regnum (gdbarch) + 32)) | |
96f026fc | 528 | { |
d37eb719 DJ |
529 | /* See mips_linux_o32_sigframe_init for a description of the |
530 | peculiar FP register layout. */ | |
2eb4d78b | 531 | if (register_size (gdbarch, regno) == 4) |
d37eb719 | 532 | { |
2eb4d78b | 533 | int regi = regno - gdbarch_fp0_regnum (gdbarch); |
d37eb719 DJ |
534 | |
535 | to = (gdb_byte *) (*fpregsetp + (regi & ~1)); | |
2eb4d78b | 536 | if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (regi & 1)) |
d37eb719 | 537 | to += 4; |
28f5035f | 538 | regcache_raw_collect (regcache, regno, to); |
d37eb719 DJ |
539 | } |
540 | else | |
541 | { | |
025bb325 MS |
542 | to = (gdb_byte *) (*fpregsetp + regno |
543 | - gdbarch_fp0_regnum (gdbarch)); | |
28f5035f | 544 | regcache_raw_collect (regcache, regno, to); |
d37eb719 | 545 | } |
96f026fc | 546 | } |
2eb4d78b | 547 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
96f026fc | 548 | { |
d37eb719 DJ |
549 | gdb_byte buf[MAX_REGISTER_SIZE]; |
550 | LONGEST val; | |
551 | ||
28f5035f | 552 | regcache_raw_collect (regcache, regno, buf); |
e17a4113 UW |
553 | val = extract_signed_integer (buf, register_size (gdbarch, regno), |
554 | byte_order); | |
d37eb719 | 555 | to = (gdb_byte *) (*fpregsetp + 32); |
e17a4113 | 556 | store_signed_integer (to, 4, byte_order, val); |
d37eb719 | 557 | } |
2eb4d78b | 558 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
d37eb719 DJ |
559 | { |
560 | gdb_byte buf[MAX_REGISTER_SIZE]; | |
561 | LONGEST val; | |
562 | ||
28f5035f | 563 | regcache_raw_collect (regcache, regno, buf); |
e17a4113 UW |
564 | val = extract_signed_integer (buf, register_size (gdbarch, regno), |
565 | byte_order); | |
d37eb719 | 566 | to = (gdb_byte *) (*fpregsetp + 32) + 4; |
e17a4113 | 567 | store_signed_integer (to, 4, byte_order, val); |
96f026fc KB |
568 | } |
569 | else if (regno == -1) | |
570 | { | |
571 | int regi; | |
572 | ||
573 | for (regi = 0; regi < 32; regi++) | |
3e8c568d | 574 | mips64_fill_fpregset (regcache, fpregsetp, |
2eb4d78b | 575 | gdbarch_fp0_regnum (gdbarch) + regi); |
28f5035f | 576 | mips64_fill_fpregset (regcache, fpregsetp, |
2eb4d78b | 577 | mips_regnum (gdbarch)->fp_control_status); |
28f5035f | 578 | mips64_fill_fpregset (regcache, fpregsetp, |
2eb4d78b UW |
579 | (mips_regnum (gdbarch) |
580 | ->fp_implementation_revision)); | |
96f026fc KB |
581 | } |
582 | } | |
583 | ||
50e8a0d5 HZ |
584 | static void |
585 | mips64_fill_fpregset_wrapper (const struct regset *regset, | |
586 | const struct regcache *regcache, | |
587 | int regnum, void *gregs, size_t len) | |
588 | { | |
589 | gdb_assert (len == sizeof (mips64_elf_fpregset_t)); | |
96f026fc | 590 | |
50e8a0d5 HZ |
591 | mips64_fill_fpregset (regcache, (mips64_elf_fpregset_t *)gregs, regnum); |
592 | } | |
2aa830e4 | 593 | |
50e8a0d5 HZ |
594 | const struct regset * |
595 | mips_linux_regset_from_core_section (struct gdbarch *gdbarch, | |
596 | const char *sect_name, size_t sect_size) | |
2aa830e4 | 597 | { |
50e8a0d5 | 598 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
d37eb719 DJ |
599 | mips_elf_gregset_t gregset; |
600 | mips_elf_fpregset_t fpregset; | |
96f026fc KB |
601 | mips64_elf_gregset_t gregset64; |
602 | mips64_elf_fpregset_t fpregset64; | |
2aa830e4 | 603 | |
50e8a0d5 | 604 | if (strcmp (sect_name, ".reg") == 0) |
2aa830e4 | 605 | { |
50e8a0d5 | 606 | if (sect_size == sizeof (gregset)) |
2aa830e4 | 607 | { |
50e8a0d5 HZ |
608 | if (tdep->gregset == NULL) |
609 | tdep->gregset = regset_alloc (gdbarch, | |
610 | mips_supply_gregset_wrapper, | |
611 | mips_fill_gregset_wrapper); | |
612 | return tdep->gregset; | |
96f026fc | 613 | } |
50e8a0d5 | 614 | else if (sect_size == sizeof (gregset64)) |
96f026fc | 615 | { |
50e8a0d5 HZ |
616 | if (tdep->gregset64 == NULL) |
617 | tdep->gregset64 = regset_alloc (gdbarch, | |
618 | mips64_supply_gregset_wrapper, | |
619 | mips64_fill_gregset_wrapper); | |
620 | return tdep->gregset64; | |
2aa830e4 DJ |
621 | } |
622 | else | |
623 | { | |
8a3fe4f8 | 624 | warning (_("wrong size gregset struct in core file")); |
2aa830e4 DJ |
625 | } |
626 | } | |
50e8a0d5 | 627 | else if (strcmp (sect_name, ".reg2") == 0) |
2aa830e4 | 628 | { |
50e8a0d5 | 629 | if (sect_size == sizeof (fpregset)) |
2aa830e4 | 630 | { |
50e8a0d5 HZ |
631 | if (tdep->fpregset == NULL) |
632 | tdep->fpregset = regset_alloc (gdbarch, | |
633 | mips_supply_fpregset_wrapper, | |
634 | mips_fill_fpregset_wrapper); | |
635 | return tdep->fpregset; | |
96f026fc | 636 | } |
50e8a0d5 | 637 | else if (sect_size == sizeof (fpregset64)) |
96f026fc | 638 | { |
50e8a0d5 HZ |
639 | if (tdep->fpregset64 == NULL) |
640 | tdep->fpregset64 = regset_alloc (gdbarch, | |
641 | mips64_supply_fpregset_wrapper, | |
642 | mips64_fill_fpregset_wrapper); | |
643 | return tdep->fpregset64; | |
2aa830e4 DJ |
644 | } |
645 | else | |
646 | { | |
8a3fe4f8 | 647 | warning (_("wrong size fpregset struct in core file")); |
2aa830e4 DJ |
648 | } |
649 | } | |
2aa830e4 | 650 | |
50e8a0d5 HZ |
651 | return NULL; |
652 | } | |
2aa830e4 | 653 | |
4eb0ad19 DJ |
654 | static const struct target_desc * |
655 | mips_linux_core_read_description (struct gdbarch *gdbarch, | |
656 | struct target_ops *target, | |
657 | bfd *abfd) | |
658 | { | |
659 | asection *section = bfd_get_section_by_name (abfd, ".reg"); | |
660 | if (! section) | |
661 | return NULL; | |
662 | ||
663 | switch (bfd_section_size (abfd, section)) | |
664 | { | |
665 | case sizeof (mips_elf_gregset_t): | |
666 | return mips_tdesc_gp32; | |
667 | ||
668 | case sizeof (mips64_elf_gregset_t): | |
669 | return mips_tdesc_gp64; | |
670 | ||
671 | default: | |
672 | return NULL; | |
673 | } | |
674 | } | |
675 | ||
96f026fc | 676 | |
295093a4 MS |
677 | /* Check the code at PC for a dynamic linker lazy resolution stub. |
678 | Because they aren't in the .plt section, we pattern-match on the | |
679 | code generated by GNU ld. They look like this: | |
6de918a6 DJ |
680 | |
681 | lw t9,0x8010(gp) | |
682 | addu t7,ra | |
683 | jalr t9,ra | |
684 | addiu t8,zero,INDEX | |
685 | ||
295093a4 MS |
686 | (with the appropriate doubleword instructions for N64). Also |
687 | return the dynamic symbol index used in the last instruction. */ | |
6de918a6 DJ |
688 | |
689 | static int | |
690 | mips_linux_in_dynsym_stub (CORE_ADDR pc, char *name) | |
691 | { | |
692 | unsigned char buf[28], *p; | |
693 | ULONGEST insn, insn1; | |
1cf3db46 | 694 | int n64 = (mips_abi (target_gdbarch) == MIPS_ABI_N64); |
e17a4113 | 695 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch); |
6de918a6 DJ |
696 | |
697 | read_memory (pc - 12, buf, 28); | |
698 | ||
699 | if (n64) | |
700 | { | |
701 | /* ld t9,0x8010(gp) */ | |
702 | insn1 = 0xdf998010; | |
703 | } | |
704 | else | |
705 | { | |
706 | /* lw t9,0x8010(gp) */ | |
707 | insn1 = 0x8f998010; | |
708 | } | |
709 | ||
710 | p = buf + 12; | |
711 | while (p >= buf) | |
712 | { | |
e17a4113 | 713 | insn = extract_unsigned_integer (p, 4, byte_order); |
6de918a6 DJ |
714 | if (insn == insn1) |
715 | break; | |
716 | p -= 4; | |
717 | } | |
718 | if (p < buf) | |
719 | return 0; | |
720 | ||
e17a4113 | 721 | insn = extract_unsigned_integer (p + 4, 4, byte_order); |
6de918a6 DJ |
722 | if (n64) |
723 | { | |
724 | /* daddu t7,ra */ | |
725 | if (insn != 0x03e0782d) | |
726 | return 0; | |
727 | } | |
728 | else | |
729 | { | |
730 | /* addu t7,ra */ | |
731 | if (insn != 0x03e07821) | |
732 | return 0; | |
733 | } | |
295093a4 | 734 | |
e17a4113 | 735 | insn = extract_unsigned_integer (p + 8, 4, byte_order); |
6de918a6 DJ |
736 | /* jalr t9,ra */ |
737 | if (insn != 0x0320f809) | |
738 | return 0; | |
739 | ||
e17a4113 | 740 | insn = extract_unsigned_integer (p + 12, 4, byte_order); |
6de918a6 DJ |
741 | if (n64) |
742 | { | |
743 | /* daddiu t8,zero,0 */ | |
744 | if ((insn & 0xffff0000) != 0x64180000) | |
745 | return 0; | |
746 | } | |
747 | else | |
748 | { | |
749 | /* addiu t8,zero,0 */ | |
750 | if ((insn & 0xffff0000) != 0x24180000) | |
751 | return 0; | |
752 | } | |
753 | ||
754 | return (insn & 0xffff); | |
755 | } | |
756 | ||
295093a4 | 757 | /* Return non-zero iff PC belongs to the dynamic linker resolution |
db5f024e | 758 | code, a PLT entry, or a lazy binding stub. */ |
6de918a6 | 759 | |
7d522c90 | 760 | static int |
6de918a6 DJ |
761 | mips_linux_in_dynsym_resolve_code (CORE_ADDR pc) |
762 | { | |
295093a4 | 763 | /* Check whether PC is in the dynamic linker. This also checks |
db5f024e | 764 | whether it is in the .plt section, used by non-PIC executables. */ |
7d522c90 | 765 | if (svr4_in_dynsym_resolve_code (pc)) |
6de918a6 DJ |
766 | return 1; |
767 | ||
295093a4 MS |
768 | /* Pattern match for the stub. It would be nice if there were a |
769 | more efficient way to avoid this check. */ | |
6de918a6 DJ |
770 | if (mips_linux_in_dynsym_stub (pc, NULL)) |
771 | return 1; | |
772 | ||
773 | return 0; | |
774 | } | |
775 | ||
776 | /* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c, | |
777 | and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc | |
778 | implementation of this triggers at "fixup" from the same objfile as | |
c4c5b7ba | 779 | "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at |
db5f024e DJ |
780 | "__dl_runtime_resolve" directly. An unresolved lazy binding |
781 | stub will point to _dl_runtime_resolve, which will first call | |
c4c5b7ba AC |
782 | __dl_runtime_resolve, and then pass control to the resolved |
783 | function. */ | |
6de918a6 DJ |
784 | |
785 | static CORE_ADDR | |
786 | mips_linux_skip_resolver (struct gdbarch *gdbarch, CORE_ADDR pc) | |
787 | { | |
788 | struct minimal_symbol *resolver; | |
789 | ||
790 | resolver = lookup_minimal_symbol ("__dl_runtime_resolve", NULL, NULL); | |
791 | ||
792 | if (resolver && SYMBOL_VALUE_ADDRESS (resolver) == pc) | |
c7ce8faa | 793 | return frame_unwind_caller_pc (get_current_frame ()); |
6de918a6 | 794 | |
db5f024e | 795 | return glibc_skip_solib_resolver (gdbarch, pc); |
295093a4 | 796 | } |
6de918a6 | 797 | |
5792a79b DJ |
798 | /* Signal trampoline support. There are four supported layouts for a |
799 | signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and | |
800 | n64 rt_sigframe. We handle them all independently; not the most | |
801 | efficient way, but simplest. First, declare all the unwinders. */ | |
802 | ||
803 | static void mips_linux_o32_sigframe_init (const struct tramp_frame *self, | |
b8a22b94 | 804 | struct frame_info *this_frame, |
5792a79b DJ |
805 | struct trad_frame_cache *this_cache, |
806 | CORE_ADDR func); | |
807 | ||
808 | static void mips_linux_n32n64_sigframe_init (const struct tramp_frame *self, | |
b8a22b94 | 809 | struct frame_info *this_frame, |
5792a79b DJ |
810 | struct trad_frame_cache *this_cache, |
811 | CORE_ADDR func); | |
812 | ||
813 | #define MIPS_NR_LINUX 4000 | |
814 | #define MIPS_NR_N64_LINUX 5000 | |
815 | #define MIPS_NR_N32_LINUX 6000 | |
816 | ||
817 | #define MIPS_NR_sigreturn MIPS_NR_LINUX + 119 | |
818 | #define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193 | |
819 | #define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211 | |
820 | #define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211 | |
821 | ||
822 | #define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn | |
823 | #define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn | |
824 | #define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn | |
825 | #define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn | |
826 | #define MIPS_INST_SYSCALL 0x0000000c | |
827 | ||
2cd8546d AC |
828 | static const struct tramp_frame mips_linux_o32_sigframe = { |
829 | SIGTRAMP_FRAME, | |
5792a79b | 830 | 4, |
2cd8546d AC |
831 | { |
832 | { MIPS_INST_LI_V0_SIGRETURN, -1 }, | |
833 | { MIPS_INST_SYSCALL, -1 }, | |
834 | { TRAMP_SENTINEL_INSN, -1 } | |
835 | }, | |
5792a79b DJ |
836 | mips_linux_o32_sigframe_init |
837 | }; | |
838 | ||
2cd8546d AC |
839 | static const struct tramp_frame mips_linux_o32_rt_sigframe = { |
840 | SIGTRAMP_FRAME, | |
5792a79b | 841 | 4, |
2cd8546d AC |
842 | { |
843 | { MIPS_INST_LI_V0_RT_SIGRETURN, -1 }, | |
844 | { MIPS_INST_SYSCALL, -1 }, | |
845 | { TRAMP_SENTINEL_INSN, -1 } }, | |
5792a79b DJ |
846 | mips_linux_o32_sigframe_init |
847 | }; | |
848 | ||
2cd8546d AC |
849 | static const struct tramp_frame mips_linux_n32_rt_sigframe = { |
850 | SIGTRAMP_FRAME, | |
5792a79b | 851 | 4, |
2cd8546d AC |
852 | { |
853 | { MIPS_INST_LI_V0_N32_RT_SIGRETURN, -1 }, | |
854 | { MIPS_INST_SYSCALL, -1 }, | |
855 | { TRAMP_SENTINEL_INSN, -1 } | |
856 | }, | |
5792a79b DJ |
857 | mips_linux_n32n64_sigframe_init |
858 | }; | |
859 | ||
2cd8546d AC |
860 | static const struct tramp_frame mips_linux_n64_rt_sigframe = { |
861 | SIGTRAMP_FRAME, | |
5792a79b | 862 | 4, |
fcbd8a5c TS |
863 | { |
864 | { MIPS_INST_LI_V0_N64_RT_SIGRETURN, -1 }, | |
865 | { MIPS_INST_SYSCALL, -1 }, | |
866 | { TRAMP_SENTINEL_INSN, -1 } | |
867 | }, | |
5792a79b DJ |
868 | mips_linux_n32n64_sigframe_init |
869 | }; | |
870 | ||
871 | /* *INDENT-OFF* */ | |
872 | /* The unwinder for o32 signal frames. The legacy structures look | |
873 | like this: | |
874 | ||
875 | struct sigframe { | |
876 | u32 sf_ass[4]; [argument save space for o32] | |
eb195664 | 877 | u32 sf_code[2]; [signal trampoline or fill] |
5792a79b DJ |
878 | struct sigcontext sf_sc; |
879 | sigset_t sf_mask; | |
880 | }; | |
881 | ||
882 | struct sigcontext { | |
883 | unsigned int sc_regmask; [Unused] | |
884 | unsigned int sc_status; | |
885 | unsigned long long sc_pc; | |
886 | unsigned long long sc_regs[32]; | |
887 | unsigned long long sc_fpregs[32]; | |
888 | unsigned int sc_ownedfp; | |
889 | unsigned int sc_fpc_csr; | |
890 | unsigned int sc_fpc_eir; [Unused] | |
891 | unsigned int sc_used_math; | |
892 | unsigned int sc_ssflags; [Unused] | |
893 | [Alignment hole of four bytes] | |
894 | unsigned long long sc_mdhi; | |
895 | unsigned long long sc_mdlo; | |
896 | ||
897 | unsigned int sc_cause; [Unused] | |
898 | unsigned int sc_badvaddr; [Unused] | |
899 | ||
900 | unsigned long sc_sigset[4]; [kernel's sigset_t] | |
901 | }; | |
902 | ||
903 | The RT signal frames look like this: | |
904 | ||
905 | struct rt_sigframe { | |
906 | u32 rs_ass[4]; [argument save space for o32] | |
eb195664 | 907 | u32 rs_code[2] [signal trampoline or fill] |
5792a79b DJ |
908 | struct siginfo rs_info; |
909 | struct ucontext rs_uc; | |
910 | }; | |
911 | ||
912 | struct ucontext { | |
913 | unsigned long uc_flags; | |
914 | struct ucontext *uc_link; | |
915 | stack_t uc_stack; | |
916 | [Alignment hole of four bytes] | |
917 | struct sigcontext uc_mcontext; | |
918 | sigset_t uc_sigmask; | |
919 | }; */ | |
920 | /* *INDENT-ON* */ | |
921 | ||
5792a79b DJ |
922 | #define SIGFRAME_SIGCONTEXT_OFFSET (6 * 4) |
923 | ||
924 | #define RTSIGFRAME_SIGINFO_SIZE 128 | |
925 | #define STACK_T_SIZE (3 * 4) | |
926 | #define UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + STACK_T_SIZE + 4) | |
927 | #define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ | |
928 | + RTSIGFRAME_SIGINFO_SIZE \ | |
929 | + UCONTEXT_SIGCONTEXT_OFFSET) | |
930 | ||
931 | #define SIGCONTEXT_PC (1 * 8) | |
932 | #define SIGCONTEXT_REGS (2 * 8) | |
933 | #define SIGCONTEXT_FPREGS (34 * 8) | |
934 | #define SIGCONTEXT_FPCSR (66 * 8 + 4) | |
935 | #define SIGCONTEXT_HI (69 * 8) | |
936 | #define SIGCONTEXT_LO (70 * 8) | |
937 | #define SIGCONTEXT_CAUSE (71 * 8 + 0) | |
938 | #define SIGCONTEXT_BADVADDR (71 * 8 + 4) | |
939 | ||
940 | #define SIGCONTEXT_REG_SIZE 8 | |
941 | ||
942 | static void | |
943 | mips_linux_o32_sigframe_init (const struct tramp_frame *self, | |
b8a22b94 | 944 | struct frame_info *this_frame, |
5792a79b DJ |
945 | struct trad_frame_cache *this_cache, |
946 | CORE_ADDR func) | |
947 | { | |
b8a22b94 | 948 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
5792a79b | 949 | int ireg, reg_position; |
eb195664 DD |
950 | CORE_ADDR frame_sp = get_frame_sp (this_frame); |
951 | CORE_ADDR sigcontext_base; | |
2eb4d78b | 952 | const struct mips_regnum *regs = mips_regnum (gdbarch); |
37c4d197 | 953 | CORE_ADDR regs_base; |
5792a79b DJ |
954 | |
955 | if (self == &mips_linux_o32_sigframe) | |
eb195664 | 956 | sigcontext_base = frame_sp + SIGFRAME_SIGCONTEXT_OFFSET; |
5792a79b | 957 | else |
eb195664 | 958 | sigcontext_base = frame_sp + RTSIGFRAME_SIGCONTEXT_OFFSET; |
295093a4 MS |
959 | |
960 | /* I'm not proud of this hack. Eventually we will have the | |
961 | infrastructure to indicate the size of saved registers on a | |
962 | per-frame basis, but right now we don't; the kernel saves eight | |
37c4d197 DJ |
963 | bytes but we only want four. Use regs_base to access any |
964 | 64-bit fields. */ | |
2eb4d78b | 965 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
37c4d197 DJ |
966 | regs_base = sigcontext_base + 4; |
967 | else | |
968 | regs_base = sigcontext_base; | |
5792a79b | 969 | |
2eb4d78b | 970 | if (mips_linux_restart_reg_p (gdbarch)) |
822b6570 DJ |
971 | trad_frame_set_reg_addr (this_cache, |
972 | (MIPS_RESTART_REGNUM | |
2eb4d78b | 973 | + gdbarch_num_regs (gdbarch)), |
822b6570 | 974 | regs_base + SIGCONTEXT_REGS); |
5792a79b DJ |
975 | |
976 | for (ireg = 1; ireg < 32; ireg++) | |
295093a4 | 977 | trad_frame_set_reg_addr (this_cache, |
f57d151a | 978 | ireg + MIPS_ZERO_REGNUM |
2eb4d78b | 979 | + gdbarch_num_regs (gdbarch), |
37c4d197 | 980 | regs_base + SIGCONTEXT_REGS |
5792a79b DJ |
981 | + ireg * SIGCONTEXT_REG_SIZE); |
982 | ||
37c4d197 DJ |
983 | /* The way that floating point registers are saved, unfortunately, |
984 | depends on the architecture the kernel is built for. For the r3000 and | |
985 | tx39, four bytes of each register are at the beginning of each of the | |
986 | 32 eight byte slots. For everything else, the registers are saved | |
987 | using double precision; only the even-numbered slots are initialized, | |
988 | and the high bits are the odd-numbered register. Assume the latter | |
989 | layout, since we can't tell, and it's much more common. Which bits are | |
990 | the "high" bits depends on endianness. */ | |
5792a79b | 991 | for (ireg = 0; ireg < 32; ireg++) |
2eb4d78b | 992 | if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (ireg & 1)) |
f57d151a UW |
993 | trad_frame_set_reg_addr (this_cache, |
994 | ireg + regs->fp0 + | |
2eb4d78b | 995 | gdbarch_num_regs (gdbarch), |
37c4d197 DJ |
996 | sigcontext_base + SIGCONTEXT_FPREGS + 4 |
997 | + (ireg & ~1) * SIGCONTEXT_REG_SIZE); | |
998 | else | |
f57d151a UW |
999 | trad_frame_set_reg_addr (this_cache, |
1000 | ireg + regs->fp0 | |
2eb4d78b | 1001 | + gdbarch_num_regs (gdbarch), |
37c4d197 DJ |
1002 | sigcontext_base + SIGCONTEXT_FPREGS |
1003 | + (ireg & ~1) * SIGCONTEXT_REG_SIZE); | |
5792a79b | 1004 | |
f57d151a | 1005 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1006 | regs->pc + gdbarch_num_regs (gdbarch), |
37c4d197 | 1007 | regs_base + SIGCONTEXT_PC); |
5792a79b | 1008 | |
295093a4 | 1009 | trad_frame_set_reg_addr (this_cache, |
f57d151a | 1010 | regs->fp_control_status |
2eb4d78b | 1011 | + gdbarch_num_regs (gdbarch), |
5792a79b | 1012 | sigcontext_base + SIGCONTEXT_FPCSR); |
f57d151a | 1013 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1014 | regs->hi + gdbarch_num_regs (gdbarch), |
37c4d197 | 1015 | regs_base + SIGCONTEXT_HI); |
f57d151a | 1016 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1017 | regs->lo + gdbarch_num_regs (gdbarch), |
37c4d197 | 1018 | regs_base + SIGCONTEXT_LO); |
f57d151a | 1019 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1020 | regs->cause + gdbarch_num_regs (gdbarch), |
5792a79b | 1021 | sigcontext_base + SIGCONTEXT_CAUSE); |
f57d151a | 1022 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1023 | regs->badvaddr + gdbarch_num_regs (gdbarch), |
5792a79b DJ |
1024 | sigcontext_base + SIGCONTEXT_BADVADDR); |
1025 | ||
1026 | /* Choice of the bottom of the sigframe is somewhat arbitrary. */ | |
eb195664 | 1027 | trad_frame_set_id (this_cache, frame_id_build (frame_sp, func)); |
5792a79b DJ |
1028 | } |
1029 | ||
1030 | /* *INDENT-OFF* */ | |
1031 | /* For N32/N64 things look different. There is no non-rt signal frame. | |
1032 | ||
1033 | struct rt_sigframe_n32 { | |
1034 | u32 rs_ass[4]; [ argument save space for o32 ] | |
eb195664 | 1035 | u32 rs_code[2]; [ signal trampoline or fill ] |
5792a79b DJ |
1036 | struct siginfo rs_info; |
1037 | struct ucontextn32 rs_uc; | |
1038 | }; | |
1039 | ||
1040 | struct ucontextn32 { | |
1041 | u32 uc_flags; | |
1042 | s32 uc_link; | |
1043 | stack32_t uc_stack; | |
1044 | struct sigcontext uc_mcontext; | |
1045 | sigset_t uc_sigmask; [ mask last for extensibility ] | |
1046 | }; | |
295093a4 | 1047 | |
e741f4d4 | 1048 | struct rt_sigframe { |
5792a79b DJ |
1049 | u32 rs_ass[4]; [ argument save space for o32 ] |
1050 | u32 rs_code[2]; [ signal trampoline ] | |
1051 | struct siginfo rs_info; | |
1052 | struct ucontext rs_uc; | |
1053 | }; | |
1054 | ||
1055 | struct ucontext { | |
1056 | unsigned long uc_flags; | |
1057 | struct ucontext *uc_link; | |
1058 | stack_t uc_stack; | |
1059 | struct sigcontext uc_mcontext; | |
1060 | sigset_t uc_sigmask; [ mask last for extensibility ] | |
1061 | }; | |
1062 | ||
1063 | And the sigcontext is different (this is for both n32 and n64): | |
1064 | ||
1065 | struct sigcontext { | |
1066 | unsigned long long sc_regs[32]; | |
1067 | unsigned long long sc_fpregs[32]; | |
1068 | unsigned long long sc_mdhi; | |
e741f4d4 DJ |
1069 | unsigned long long sc_hi1; |
1070 | unsigned long long sc_hi2; | |
1071 | unsigned long long sc_hi3; | |
5792a79b | 1072 | unsigned long long sc_mdlo; |
e741f4d4 DJ |
1073 | unsigned long long sc_lo1; |
1074 | unsigned long long sc_lo2; | |
1075 | unsigned long long sc_lo3; | |
5792a79b | 1076 | unsigned long long sc_pc; |
5792a79b | 1077 | unsigned int sc_fpc_csr; |
5792a79b | 1078 | unsigned int sc_used_math; |
e741f4d4 DJ |
1079 | unsigned int sc_dsp; |
1080 | unsigned int sc_reserved; | |
1081 | }; | |
1082 | ||
1083 | That is the post-2.6.12 definition of the 64-bit sigcontext; before | |
1084 | then, there were no hi1-hi3 or lo1-lo3. Cause and badvaddr were | |
1085 | included too. */ | |
5792a79b DJ |
1086 | /* *INDENT-ON* */ |
1087 | ||
1088 | #define N32_STACK_T_SIZE STACK_T_SIZE | |
1089 | #define N64_STACK_T_SIZE (2 * 8 + 4) | |
1090 | #define N32_UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + N32_STACK_T_SIZE + 4) | |
1091 | #define N64_UCONTEXT_SIGCONTEXT_OFFSET (2 * 8 + N64_STACK_T_SIZE + 4) | |
1092 | #define N32_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ | |
1093 | + RTSIGFRAME_SIGINFO_SIZE \ | |
1094 | + N32_UCONTEXT_SIGCONTEXT_OFFSET) | |
1095 | #define N64_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ | |
1096 | + RTSIGFRAME_SIGINFO_SIZE \ | |
1097 | + N64_UCONTEXT_SIGCONTEXT_OFFSET) | |
1098 | ||
1099 | #define N64_SIGCONTEXT_REGS (0 * 8) | |
1100 | #define N64_SIGCONTEXT_FPREGS (32 * 8) | |
1101 | #define N64_SIGCONTEXT_HI (64 * 8) | |
e741f4d4 DJ |
1102 | #define N64_SIGCONTEXT_LO (68 * 8) |
1103 | #define N64_SIGCONTEXT_PC (72 * 8) | |
1104 | #define N64_SIGCONTEXT_FPCSR (73 * 8) | |
5792a79b DJ |
1105 | |
1106 | #define N64_SIGCONTEXT_REG_SIZE 8 | |
295093a4 | 1107 | |
5792a79b DJ |
1108 | static void |
1109 | mips_linux_n32n64_sigframe_init (const struct tramp_frame *self, | |
b8a22b94 | 1110 | struct frame_info *this_frame, |
5792a79b DJ |
1111 | struct trad_frame_cache *this_cache, |
1112 | CORE_ADDR func) | |
1113 | { | |
b8a22b94 | 1114 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
5792a79b | 1115 | int ireg, reg_position; |
eb195664 DD |
1116 | CORE_ADDR frame_sp = get_frame_sp (this_frame); |
1117 | CORE_ADDR sigcontext_base; | |
2eb4d78b | 1118 | const struct mips_regnum *regs = mips_regnum (gdbarch); |
5792a79b DJ |
1119 | |
1120 | if (self == &mips_linux_n32_rt_sigframe) | |
eb195664 | 1121 | sigcontext_base = frame_sp + N32_SIGFRAME_SIGCONTEXT_OFFSET; |
5792a79b | 1122 | else |
eb195664 | 1123 | sigcontext_base = frame_sp + N64_SIGFRAME_SIGCONTEXT_OFFSET; |
295093a4 | 1124 | |
2eb4d78b | 1125 | if (mips_linux_restart_reg_p (gdbarch)) |
822b6570 DJ |
1126 | trad_frame_set_reg_addr (this_cache, |
1127 | (MIPS_RESTART_REGNUM | |
2eb4d78b | 1128 | + gdbarch_num_regs (gdbarch)), |
822b6570 | 1129 | sigcontext_base + N64_SIGCONTEXT_REGS); |
5792a79b DJ |
1130 | |
1131 | for (ireg = 1; ireg < 32; ireg++) | |
295093a4 | 1132 | trad_frame_set_reg_addr (this_cache, |
f57d151a | 1133 | ireg + MIPS_ZERO_REGNUM |
2eb4d78b | 1134 | + gdbarch_num_regs (gdbarch), |
5792a79b DJ |
1135 | sigcontext_base + N64_SIGCONTEXT_REGS |
1136 | + ireg * N64_SIGCONTEXT_REG_SIZE); | |
1137 | ||
1138 | for (ireg = 0; ireg < 32; ireg++) | |
f57d151a UW |
1139 | trad_frame_set_reg_addr (this_cache, |
1140 | ireg + regs->fp0 | |
2eb4d78b | 1141 | + gdbarch_num_regs (gdbarch), |
5792a79b DJ |
1142 | sigcontext_base + N64_SIGCONTEXT_FPREGS |
1143 | + ireg * N64_SIGCONTEXT_REG_SIZE); | |
1144 | ||
f57d151a | 1145 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1146 | regs->pc + gdbarch_num_regs (gdbarch), |
5792a79b DJ |
1147 | sigcontext_base + N64_SIGCONTEXT_PC); |
1148 | ||
295093a4 | 1149 | trad_frame_set_reg_addr (this_cache, |
f57d151a | 1150 | regs->fp_control_status |
2eb4d78b | 1151 | + gdbarch_num_regs (gdbarch), |
5792a79b | 1152 | sigcontext_base + N64_SIGCONTEXT_FPCSR); |
f57d151a | 1153 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1154 | regs->hi + gdbarch_num_regs (gdbarch), |
5792a79b | 1155 | sigcontext_base + N64_SIGCONTEXT_HI); |
f57d151a | 1156 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1157 | regs->lo + gdbarch_num_regs (gdbarch), |
5792a79b | 1158 | sigcontext_base + N64_SIGCONTEXT_LO); |
5792a79b DJ |
1159 | |
1160 | /* Choice of the bottom of the sigframe is somewhat arbitrary. */ | |
eb195664 | 1161 | trad_frame_set_id (this_cache, frame_id_build (frame_sp, func)); |
5792a79b DJ |
1162 | } |
1163 | ||
822b6570 | 1164 | static void |
61a1198a | 1165 | mips_linux_write_pc (struct regcache *regcache, CORE_ADDR pc) |
822b6570 | 1166 | { |
2eb4d78b UW |
1167 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1168 | regcache_cooked_write_unsigned (regcache, gdbarch_pc_regnum (gdbarch), pc); | |
822b6570 DJ |
1169 | |
1170 | /* Clear the syscall restart flag. */ | |
2eb4d78b | 1171 | if (mips_linux_restart_reg_p (gdbarch)) |
61a1198a | 1172 | regcache_cooked_write_unsigned (regcache, MIPS_RESTART_REGNUM, 0); |
822b6570 DJ |
1173 | } |
1174 | ||
1175 | /* Return 1 if MIPS_RESTART_REGNUM is usable. */ | |
1176 | ||
1177 | int | |
1178 | mips_linux_restart_reg_p (struct gdbarch *gdbarch) | |
1179 | { | |
1180 | /* If we do not have a target description with registers, then | |
1181 | MIPS_RESTART_REGNUM will not be included in the register set. */ | |
1182 | if (!tdesc_has_registers (gdbarch_target_desc (gdbarch))) | |
1183 | return 0; | |
1184 | ||
1185 | /* If we do, then MIPS_RESTART_REGNUM is safe to check; it will | |
1186 | either be GPR-sized or missing. */ | |
1187 | return register_size (gdbarch, MIPS_RESTART_REGNUM) > 0; | |
1188 | } | |
9f62d0e2 | 1189 | |
e38d4e1a DJ |
1190 | /* When FRAME is at a syscall instruction, return the PC of the next |
1191 | instruction to be executed. */ | |
1192 | ||
63807e1d | 1193 | static CORE_ADDR |
e38d4e1a DJ |
1194 | mips_linux_syscall_next_pc (struct frame_info *frame) |
1195 | { | |
1196 | CORE_ADDR pc = get_frame_pc (frame); | |
1197 | ULONGEST v0 = get_frame_register_unsigned (frame, MIPS_V0_REGNUM); | |
1198 | ||
1199 | /* If we are about to make a sigreturn syscall, use the unwinder to | |
1200 | decode the signal frame. */ | |
1201 | if (v0 == MIPS_NR_sigreturn | |
1202 | || v0 == MIPS_NR_rt_sigreturn | |
1203 | || v0 == MIPS_NR_N64_rt_sigreturn | |
1204 | || v0 == MIPS_NR_N32_rt_sigreturn) | |
c7ce8faa | 1205 | return frame_unwind_caller_pc (get_current_frame ()); |
e38d4e1a DJ |
1206 | |
1207 | return pc + 4; | |
1208 | } | |
1209 | ||
385203ed DD |
1210 | /* Return the current system call's number present in the |
1211 | v0 register. When the function fails, it returns -1. */ | |
1212 | ||
1213 | static LONGEST | |
1214 | mips_linux_get_syscall_number (struct gdbarch *gdbarch, | |
1215 | ptid_t ptid) | |
1216 | { | |
1217 | struct regcache *regcache = get_thread_regcache (ptid); | |
1218 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1219 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1220 | int regsize = register_size (gdbarch, MIPS_V0_REGNUM); | |
1221 | /* The content of a register */ | |
1222 | gdb_byte buf[8]; | |
1223 | /* The result */ | |
1224 | LONGEST ret; | |
1225 | ||
1226 | /* Make sure we're in a known ABI */ | |
1227 | gdb_assert (tdep->mips_abi == MIPS_ABI_O32 | |
1228 | || tdep->mips_abi == MIPS_ABI_N32 | |
1229 | || tdep->mips_abi == MIPS_ABI_N64); | |
1230 | ||
1231 | gdb_assert (regsize <= sizeof (buf)); | |
1232 | ||
1233 | /* Getting the system call number from the register. | |
1234 | syscall number is in v0 or $2. */ | |
1235 | regcache_cooked_read (regcache, MIPS_V0_REGNUM, buf); | |
1236 | ||
1237 | ret = extract_signed_integer (buf, regsize, byte_order); | |
1238 | ||
1239 | return ret; | |
1240 | } | |
1241 | ||
5792a79b DJ |
1242 | /* Initialize one of the GNU/Linux OS ABIs. */ |
1243 | ||
19ed69dd | 1244 | static void |
295093a4 MS |
1245 | mips_linux_init_abi (struct gdbarch_info info, |
1246 | struct gdbarch *gdbarch) | |
19ed69dd | 1247 | { |
96f026fc KB |
1248 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1249 | enum mips_abi abi = mips_abi (gdbarch); | |
822b6570 | 1250 | struct tdesc_arch_data *tdesc_data = (void *) info.tdep_info; |
96f026fc | 1251 | |
a5ee0f0c PA |
1252 | linux_init_abi (info, gdbarch); |
1253 | ||
385203ed DD |
1254 | /* Get the syscall number from the arch's register. */ |
1255 | set_gdbarch_get_syscall_number (gdbarch, mips_linux_get_syscall_number); | |
1256 | ||
96f026fc KB |
1257 | switch (abi) |
1258 | { | |
1259 | case MIPS_ABI_O32: | |
1260 | set_gdbarch_get_longjmp_target (gdbarch, | |
1261 | mips_linux_get_longjmp_target); | |
1262 | set_solib_svr4_fetch_link_map_offsets | |
76a9d10f | 1263 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); |
fb2be677 AC |
1264 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_sigframe); |
1265 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_rt_sigframe); | |
385203ed | 1266 | set_xml_syscall_file_name ("syscalls/mips-o32-linux.xml"); |
96f026fc KB |
1267 | break; |
1268 | case MIPS_ABI_N32: | |
1269 | set_gdbarch_get_longjmp_target (gdbarch, | |
1270 | mips_linux_get_longjmp_target); | |
1271 | set_solib_svr4_fetch_link_map_offsets | |
76a9d10f | 1272 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); |
d05f6826 DJ |
1273 | set_gdbarch_long_double_bit (gdbarch, 128); |
1274 | /* These floatformats should probably be renamed. MIPS uses | |
1275 | the same 128-bit IEEE floating point format that IA-64 uses, | |
1276 | except that the quiet/signalling NaN bit is reversed (GDB | |
1277 | does not distinguish between quiet and signalling NaNs). */ | |
8da61cc4 | 1278 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); |
fb2be677 | 1279 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n32_rt_sigframe); |
385203ed | 1280 | set_xml_syscall_file_name ("syscalls/mips-n32-linux.xml"); |
96f026fc KB |
1281 | break; |
1282 | case MIPS_ABI_N64: | |
1283 | set_gdbarch_get_longjmp_target (gdbarch, | |
1284 | mips64_linux_get_longjmp_target); | |
1285 | set_solib_svr4_fetch_link_map_offsets | |
76a9d10f | 1286 | (gdbarch, svr4_lp64_fetch_link_map_offsets); |
d05f6826 DJ |
1287 | set_gdbarch_long_double_bit (gdbarch, 128); |
1288 | /* These floatformats should probably be renamed. MIPS uses | |
1289 | the same 128-bit IEEE floating point format that IA-64 uses, | |
1290 | except that the quiet/signalling NaN bit is reversed (GDB | |
1291 | does not distinguish between quiet and signalling NaNs). */ | |
8da61cc4 | 1292 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); |
fb2be677 | 1293 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n64_rt_sigframe); |
385203ed | 1294 | set_xml_syscall_file_name ("syscalls/mips-n64-linux.xml"); |
96f026fc KB |
1295 | break; |
1296 | default: | |
96f026fc KB |
1297 | break; |
1298 | } | |
6de918a6 DJ |
1299 | |
1300 | set_gdbarch_skip_solib_resolver (gdbarch, mips_linux_skip_resolver); | |
1301 | ||
0d0266c6 | 1302 | set_gdbarch_software_single_step (gdbarch, mips_software_single_step); |
b2756930 KB |
1303 | |
1304 | /* Enable TLS support. */ | |
1305 | set_gdbarch_fetch_tls_load_module_address (gdbarch, | |
1306 | svr4_fetch_objfile_link_map); | |
7d522c90 DJ |
1307 | |
1308 | /* Initialize this lazily, to avoid an initialization order | |
1309 | dependency on solib-svr4.c's _initialize routine. */ | |
1310 | if (mips_svr4_so_ops.in_dynsym_resolve_code == NULL) | |
1311 | { | |
1312 | mips_svr4_so_ops = svr4_so_ops; | |
1313 | mips_svr4_so_ops.in_dynsym_resolve_code | |
1314 | = mips_linux_in_dynsym_resolve_code; | |
1315 | } | |
1316 | set_solib_ops (gdbarch, &mips_svr4_so_ops); | |
822b6570 DJ |
1317 | |
1318 | set_gdbarch_write_pc (gdbarch, mips_linux_write_pc); | |
1319 | ||
4eb0ad19 DJ |
1320 | set_gdbarch_core_read_description (gdbarch, |
1321 | mips_linux_core_read_description); | |
1322 | ||
50e8a0d5 HZ |
1323 | set_gdbarch_regset_from_core_section (gdbarch, |
1324 | mips_linux_regset_from_core_section); | |
1325 | ||
e38d4e1a DJ |
1326 | tdep->syscall_next_pc = mips_linux_syscall_next_pc; |
1327 | ||
822b6570 DJ |
1328 | if (tdesc_data) |
1329 | { | |
1330 | const struct tdesc_feature *feature; | |
1331 | ||
1332 | /* If we have target-described registers, then we can safely | |
1333 | reserve a number for MIPS_RESTART_REGNUM (whether it is | |
1334 | described or not). */ | |
1335 | gdb_assert (gdbarch_num_regs (gdbarch) <= MIPS_RESTART_REGNUM); | |
1336 | set_gdbarch_num_regs (gdbarch, MIPS_RESTART_REGNUM + 1); | |
1337 | ||
1338 | /* If it's present, then assign it to the reserved number. */ | |
1339 | feature = tdesc_find_feature (info.target_desc, | |
1340 | "org.gnu.gdb.mips.linux"); | |
1341 | if (feature != NULL) | |
1342 | tdesc_numbered_register (feature, tdesc_data, MIPS_RESTART_REGNUM, | |
1343 | "restart"); | |
1344 | } | |
19ed69dd KB |
1345 | } |
1346 | ||
63807e1d PA |
1347 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
1348 | extern initialize_file_ftype _initialize_mips_linux_tdep; | |
1349 | ||
2aa830e4 | 1350 | void |
d1bacddc | 1351 | _initialize_mips_linux_tdep (void) |
2aa830e4 | 1352 | { |
96f026fc KB |
1353 | const struct bfd_arch_info *arch_info; |
1354 | ||
96f026fc KB |
1355 | for (arch_info = bfd_lookup_arch (bfd_arch_mips, 0); |
1356 | arch_info != NULL; | |
1357 | arch_info = arch_info->next) | |
1358 | { | |
295093a4 MS |
1359 | gdbarch_register_osabi (bfd_arch_mips, arch_info->mach, |
1360 | GDB_OSABI_LINUX, | |
96f026fc KB |
1361 | mips_linux_init_abi); |
1362 | } | |
2aa830e4 | 1363 | } |