Commit | Line | Data |
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75c9abc6 | 1 | /* Target-dependent code for GNU/Linux on MIPS processors. |
a094c6fb | 2 | |
7b6bb8da | 3 | Copyright (C) 2001, 2002, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 |
76a9d10f | 4 | Free Software Foundation, Inc. |
2aa830e4 DJ |
5 | |
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 10 | the Free Software Foundation; either version 3 of the License, or |
2aa830e4 DJ |
11 | (at your option) any later version. |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
2aa830e4 DJ |
20 | |
21 | #include "defs.h" | |
22 | #include "gdbcore.h" | |
23 | #include "target.h" | |
24 | #include "solib-svr4.h" | |
19ed69dd | 25 | #include "osabi.h" |
96f026fc | 26 | #include "mips-tdep.h" |
19ed69dd | 27 | #include "gdb_string.h" |
96f026fc | 28 | #include "gdb_assert.h" |
6de918a6 | 29 | #include "frame.h" |
2fdf551c | 30 | #include "regcache.h" |
5792a79b DJ |
31 | #include "trad-frame.h" |
32 | #include "tramp-frame.h" | |
e6bb342a | 33 | #include "gdbtypes.h" |
5ea03926 | 34 | #include "solib.h" |
7d522c90 DJ |
35 | #include "solib-svr4.h" |
36 | #include "solist.h" | |
982e9687 | 37 | #include "symtab.h" |
822b6570 | 38 | #include "target-descriptions.h" |
50e8a0d5 | 39 | #include "regset.h" |
d37eb719 | 40 | #include "mips-linux-tdep.h" |
db5f024e | 41 | #include "glibc-tdep.h" |
a5ee0f0c | 42 | #include "linux-tdep.h" |
385203ed | 43 | #include "xml-syscall.h" |
2aa830e4 | 44 | |
7d522c90 DJ |
45 | static struct target_so_ops mips_svr4_so_ops; |
46 | ||
2aa830e4 | 47 | /* Figure out where the longjmp will land. |
295093a4 MS |
48 | We expect the first arg to be a pointer to the jmp_buf structure |
49 | from which we extract the pc (MIPS_LINUX_JB_PC) that we will land | |
50 | at. The pc is copied into PC. This routine returns 1 on | |
51 | success. */ | |
2aa830e4 | 52 | |
19ed69dd KB |
53 | #define MIPS_LINUX_JB_ELEMENT_SIZE 4 |
54 | #define MIPS_LINUX_JB_PC 0 | |
55 | ||
56 | static int | |
60ade65d | 57 | mips_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
2aa830e4 DJ |
58 | { |
59 | CORE_ADDR jb_addr; | |
2eb4d78b | 60 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 61 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2eb4d78b | 62 | char buf[gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT]; |
2aa830e4 | 63 | |
60ade65d | 64 | jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM); |
2aa830e4 | 65 | |
bf072999 | 66 | if (target_read_memory (jb_addr |
819844ad | 67 | + MIPS_LINUX_JB_PC * MIPS_LINUX_JB_ELEMENT_SIZE, |
2eb4d78b | 68 | buf, gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT)) |
2aa830e4 DJ |
69 | return 0; |
70 | ||
819844ad | 71 | *pc = extract_unsigned_integer (buf, |
e17a4113 UW |
72 | gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT, |
73 | byte_order); | |
2aa830e4 DJ |
74 | |
75 | return 1; | |
76 | } | |
77 | ||
4246e332 | 78 | /* Transform the bits comprising a 32-bit register to the right size |
23a6d369 AC |
79 | for regcache_raw_supply(). This is needed when mips_isa_regsize() |
80 | is 8. */ | |
96f026fc KB |
81 | |
82 | static void | |
28f5035f | 83 | supply_32bit_reg (struct regcache *regcache, int regnum, const void *addr) |
96f026fc | 84 | { |
e17a4113 UW |
85 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
86 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
d37eb719 | 87 | gdb_byte buf[MAX_REGISTER_SIZE]; |
e17a4113 UW |
88 | store_signed_integer (buf, register_size (gdbarch, regnum), byte_order, |
89 | extract_signed_integer (addr, 4, byte_order)); | |
28f5035f | 90 | regcache_raw_supply (regcache, regnum, buf); |
96f026fc KB |
91 | } |
92 | ||
2aa830e4 DJ |
93 | /* Unpack an elf_gregset_t into GDB's register cache. */ |
94 | ||
d37eb719 | 95 | void |
28f5035f UW |
96 | mips_supply_gregset (struct regcache *regcache, |
97 | const mips_elf_gregset_t *gregsetp) | |
2aa830e4 DJ |
98 | { |
99 | int regi; | |
28f5035f | 100 | const mips_elf_greg_t *regp = *gregsetp; |
d9d9c31f | 101 | char zerobuf[MAX_REGISTER_SIZE]; |
2eb4d78b | 102 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
bf072999 | 103 | |
d9d9c31f | 104 | memset (zerobuf, 0, MAX_REGISTER_SIZE); |
2aa830e4 | 105 | |
822b6570 | 106 | for (regi = EF_REG0 + 1; regi <= EF_REG31; regi++) |
28f5035f | 107 | supply_32bit_reg (regcache, regi - EF_REG0, regp + regi); |
2aa830e4 | 108 | |
2eb4d78b | 109 | if (mips_linux_restart_reg_p (gdbarch)) |
822b6570 DJ |
110 | supply_32bit_reg (regcache, MIPS_RESTART_REGNUM, regp + EF_REG0); |
111 | ||
2eb4d78b UW |
112 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->lo, regp + EF_LO); |
113 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->hi, regp + EF_HI); | |
56cea623 | 114 | |
2eb4d78b | 115 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->pc, |
28f5035f | 116 | regp + EF_CP0_EPC); |
2eb4d78b | 117 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->badvaddr, |
28f5035f UW |
118 | regp + EF_CP0_BADVADDR); |
119 | supply_32bit_reg (regcache, MIPS_PS_REGNUM, regp + EF_CP0_STATUS); | |
2eb4d78b | 120 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->cause, |
28f5035f | 121 | regp + EF_CP0_CAUSE); |
2aa830e4 DJ |
122 | |
123 | /* Fill inaccessible registers with zero. */ | |
822b6570 | 124 | regcache_raw_supply (regcache, MIPS_ZERO_REGNUM, zerobuf); |
28f5035f | 125 | regcache_raw_supply (regcache, MIPS_UNUSED_REGNUM, zerobuf); |
295093a4 | 126 | for (regi = MIPS_FIRST_EMBED_REGNUM; |
822b6570 | 127 | regi <= MIPS_LAST_EMBED_REGNUM; |
295093a4 | 128 | regi++) |
28f5035f | 129 | regcache_raw_supply (regcache, regi, zerobuf); |
2aa830e4 DJ |
130 | } |
131 | ||
50e8a0d5 HZ |
132 | static void |
133 | mips_supply_gregset_wrapper (const struct regset *regset, | |
134 | struct regcache *regcache, | |
135 | int regnum, const void *gregs, size_t len) | |
136 | { | |
137 | gdb_assert (len == sizeof (mips_elf_gregset_t)); | |
138 | ||
139 | mips_supply_gregset (regcache, (const mips_elf_gregset_t *)gregs); | |
140 | } | |
141 | ||
2aa830e4 DJ |
142 | /* Pack our registers (or one register) into an elf_gregset_t. */ |
143 | ||
d37eb719 | 144 | void |
28f5035f UW |
145 | mips_fill_gregset (const struct regcache *regcache, |
146 | mips_elf_gregset_t *gregsetp, int regno) | |
2aa830e4 | 147 | { |
2eb4d78b | 148 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
2aa830e4 | 149 | int regaddr, regi; |
d37eb719 | 150 | mips_elf_greg_t *regp = *gregsetp; |
96f026fc | 151 | void *dst; |
2aa830e4 DJ |
152 | |
153 | if (regno == -1) | |
154 | { | |
d37eb719 | 155 | memset (regp, 0, sizeof (mips_elf_gregset_t)); |
822b6570 | 156 | for (regi = 1; regi < 32; regi++) |
28f5035f | 157 | mips_fill_gregset (regcache, gregsetp, regi); |
2eb4d78b UW |
158 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->lo); |
159 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->hi); | |
160 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->pc); | |
161 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->badvaddr); | |
28f5035f | 162 | mips_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM); |
2eb4d78b | 163 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->cause); |
822b6570 | 164 | mips_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM); |
2aa830e4 DJ |
165 | return; |
166 | } | |
167 | ||
822b6570 | 168 | if (regno > 0 && regno < 32) |
2aa830e4 | 169 | { |
2aa830e4 | 170 | dst = regp + regno + EF_REG0; |
28f5035f | 171 | regcache_raw_collect (regcache, regno, dst); |
2aa830e4 DJ |
172 | return; |
173 | } | |
174 | ||
2eb4d78b UW |
175 | if (regno == mips_regnum (gdbarch)->lo) |
176 | regaddr = EF_LO; | |
177 | else if (regno == mips_regnum (gdbarch)->hi) | |
56cea623 | 178 | regaddr = EF_HI; |
2eb4d78b | 179 | else if (regno == mips_regnum (gdbarch)->pc) |
56cea623 | 180 | regaddr = EF_CP0_EPC; |
2eb4d78b | 181 | else if (regno == mips_regnum (gdbarch)->badvaddr) |
56cea623 | 182 | regaddr = EF_CP0_BADVADDR; |
24e05951 | 183 | else if (regno == MIPS_PS_REGNUM) |
56cea623 | 184 | regaddr = EF_CP0_STATUS; |
2eb4d78b | 185 | else if (regno == mips_regnum (gdbarch)->cause) |
56cea623 | 186 | regaddr = EF_CP0_CAUSE; |
2eb4d78b | 187 | else if (mips_linux_restart_reg_p (gdbarch) |
822b6570 DJ |
188 | && regno == MIPS_RESTART_REGNUM) |
189 | regaddr = EF_REG0; | |
56cea623 AC |
190 | else |
191 | regaddr = -1; | |
2aa830e4 DJ |
192 | |
193 | if (regaddr != -1) | |
194 | { | |
2aa830e4 | 195 | dst = regp + regaddr; |
28f5035f | 196 | regcache_raw_collect (regcache, regno, dst); |
2aa830e4 DJ |
197 | } |
198 | } | |
199 | ||
50e8a0d5 HZ |
200 | static void |
201 | mips_fill_gregset_wrapper (const struct regset *regset, | |
202 | const struct regcache *regcache, | |
203 | int regnum, void *gregs, size_t len) | |
204 | { | |
205 | gdb_assert (len == sizeof (mips_elf_gregset_t)); | |
206 | ||
207 | mips_fill_gregset (regcache, (mips_elf_gregset_t *)gregs, regnum); | |
208 | } | |
209 | ||
2aa830e4 DJ |
210 | /* Likewise, unpack an elf_fpregset_t. */ |
211 | ||
d37eb719 | 212 | void |
28f5035f UW |
213 | mips_supply_fpregset (struct regcache *regcache, |
214 | const mips_elf_fpregset_t *fpregsetp) | |
2aa830e4 | 215 | { |
2eb4d78b | 216 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
52f0bd74 | 217 | int regi; |
d9d9c31f | 218 | char zerobuf[MAX_REGISTER_SIZE]; |
bf072999 | 219 | |
d9d9c31f | 220 | memset (zerobuf, 0, MAX_REGISTER_SIZE); |
2aa830e4 DJ |
221 | |
222 | for (regi = 0; regi < 32; regi++) | |
3e8c568d | 223 | regcache_raw_supply (regcache, |
2eb4d78b | 224 | gdbarch_fp0_regnum (gdbarch) + regi, |
3e8c568d | 225 | *fpregsetp + regi); |
2aa830e4 | 226 | |
28f5035f | 227 | regcache_raw_supply (regcache, |
2eb4d78b | 228 | mips_regnum (gdbarch)->fp_control_status, |
28f5035f | 229 | *fpregsetp + 32); |
2aa830e4 | 230 | |
295093a4 | 231 | /* FIXME: how can we supply FCRIR? The ABI doesn't tell us. */ |
28f5035f | 232 | regcache_raw_supply (regcache, |
2eb4d78b | 233 | mips_regnum (gdbarch)->fp_implementation_revision, |
23a6d369 | 234 | zerobuf); |
2aa830e4 DJ |
235 | } |
236 | ||
50e8a0d5 HZ |
237 | static void |
238 | mips_supply_fpregset_wrapper (const struct regset *regset, | |
239 | struct regcache *regcache, | |
240 | int regnum, const void *gregs, size_t len) | |
241 | { | |
242 | gdb_assert (len == sizeof (mips_elf_fpregset_t)); | |
243 | ||
244 | mips_supply_fpregset (regcache, (const mips_elf_fpregset_t *)gregs); | |
245 | } | |
246 | ||
2aa830e4 DJ |
247 | /* Likewise, pack one or all floating point registers into an |
248 | elf_fpregset_t. */ | |
249 | ||
d37eb719 | 250 | void |
28f5035f UW |
251 | mips_fill_fpregset (const struct regcache *regcache, |
252 | mips_elf_fpregset_t *fpregsetp, int regno) | |
2aa830e4 | 253 | { |
2eb4d78b | 254 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
2aa830e4 DJ |
255 | char *from, *to; |
256 | ||
2eb4d78b UW |
257 | if ((regno >= gdbarch_fp0_regnum (gdbarch)) |
258 | && (regno < gdbarch_fp0_regnum (gdbarch) + 32)) | |
2aa830e4 | 259 | { |
2eb4d78b | 260 | to = (char *) (*fpregsetp + regno - gdbarch_fp0_regnum (gdbarch)); |
28f5035f | 261 | regcache_raw_collect (regcache, regno, to); |
2aa830e4 | 262 | } |
2eb4d78b | 263 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
2aa830e4 | 264 | { |
2aa830e4 | 265 | to = (char *) (*fpregsetp + 32); |
28f5035f | 266 | regcache_raw_collect (regcache, regno, to); |
2aa830e4 DJ |
267 | } |
268 | else if (regno == -1) | |
269 | { | |
270 | int regi; | |
271 | ||
272 | for (regi = 0; regi < 32; regi++) | |
3e8c568d | 273 | mips_fill_fpregset (regcache, fpregsetp, |
2eb4d78b | 274 | gdbarch_fp0_regnum (gdbarch) + regi); |
28f5035f | 275 | mips_fill_fpregset (regcache, fpregsetp, |
2eb4d78b | 276 | mips_regnum (gdbarch)->fp_control_status); |
2aa830e4 DJ |
277 | } |
278 | } | |
279 | ||
50e8a0d5 HZ |
280 | static void |
281 | mips_fill_fpregset_wrapper (const struct regset *regset, | |
282 | const struct regcache *regcache, | |
283 | int regnum, void *gregs, size_t len) | |
284 | { | |
285 | gdb_assert (len == sizeof (mips_elf_fpregset_t)); | |
286 | ||
287 | mips_fill_fpregset (regcache, (mips_elf_fpregset_t *)gregs, regnum); | |
288 | } | |
289 | ||
96f026fc KB |
290 | /* Support for 64-bit ABIs. */ |
291 | ||
96f026fc | 292 | /* Figure out where the longjmp will land. |
295093a4 MS |
293 | We expect the first arg to be a pointer to the jmp_buf structure |
294 | from which we extract the pc (MIPS_LINUX_JB_PC) that we will land | |
295 | at. The pc is copied into PC. This routine returns 1 on | |
296 | success. */ | |
96f026fc KB |
297 | |
298 | /* Details about jmp_buf. */ | |
299 | ||
300 | #define MIPS64_LINUX_JB_PC 0 | |
301 | ||
302 | static int | |
60ade65d | 303 | mips64_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
96f026fc KB |
304 | { |
305 | CORE_ADDR jb_addr; | |
2eb4d78b | 306 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 307 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2eb4d78b UW |
308 | void *buf = alloca (gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT); |
309 | int element_size = gdbarch_ptr_bit (gdbarch) == 32 ? 4 : 8; | |
96f026fc | 310 | |
60ade65d | 311 | jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM); |
96f026fc KB |
312 | |
313 | if (target_read_memory (jb_addr + MIPS64_LINUX_JB_PC * element_size, | |
819844ad | 314 | buf, |
2eb4d78b | 315 | gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT)) |
96f026fc KB |
316 | return 0; |
317 | ||
819844ad | 318 | *pc = extract_unsigned_integer (buf, |
e17a4113 UW |
319 | gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT, |
320 | byte_order); | |
96f026fc KB |
321 | |
322 | return 1; | |
323 | } | |
324 | ||
d37eb719 DJ |
325 | /* Register set support functions. These operate on standard 64-bit |
326 | regsets, but work whether the target is 32-bit or 64-bit. A 32-bit | |
327 | target will still use the 64-bit format for PTRACE_GETREGS. */ | |
328 | ||
329 | /* Supply a 64-bit register. */ | |
96f026fc | 330 | |
63807e1d | 331 | static void |
28f5035f UW |
332 | supply_64bit_reg (struct regcache *regcache, int regnum, |
333 | const gdb_byte *buf) | |
d37eb719 | 334 | { |
2eb4d78b UW |
335 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
336 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG | |
337 | && register_size (gdbarch, regnum) == 4) | |
28f5035f | 338 | regcache_raw_supply (regcache, regnum, buf + 4); |
d37eb719 | 339 | else |
28f5035f | 340 | regcache_raw_supply (regcache, regnum, buf); |
d37eb719 DJ |
341 | } |
342 | ||
343 | /* Unpack a 64-bit elf_gregset_t into GDB's register cache. */ | |
344 | ||
345 | void | |
28f5035f UW |
346 | mips64_supply_gregset (struct regcache *regcache, |
347 | const mips64_elf_gregset_t *gregsetp) | |
96f026fc KB |
348 | { |
349 | int regi; | |
28f5035f | 350 | const mips64_elf_greg_t *regp = *gregsetp; |
d37eb719 | 351 | gdb_byte zerobuf[MAX_REGISTER_SIZE]; |
2eb4d78b | 352 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
96f026fc | 353 | |
d9d9c31f | 354 | memset (zerobuf, 0, MAX_REGISTER_SIZE); |
96f026fc | 355 | |
822b6570 | 356 | for (regi = MIPS64_EF_REG0 + 1; regi <= MIPS64_EF_REG31; regi++) |
28f5035f UW |
357 | supply_64bit_reg (regcache, regi - MIPS64_EF_REG0, |
358 | (const gdb_byte *)(regp + regi)); | |
359 | ||
2eb4d78b | 360 | if (mips_linux_restart_reg_p (gdbarch)) |
822b6570 DJ |
361 | supply_64bit_reg (regcache, MIPS_RESTART_REGNUM, |
362 | (const gdb_byte *)(regp + MIPS64_EF_REG0)); | |
363 | ||
2eb4d78b | 364 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->lo, |
28f5035f | 365 | (const gdb_byte *) (regp + MIPS64_EF_LO)); |
2eb4d78b | 366 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->hi, |
28f5035f UW |
367 | (const gdb_byte *) (regp + MIPS64_EF_HI)); |
368 | ||
2eb4d78b | 369 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->pc, |
28f5035f | 370 | (const gdb_byte *) (regp + MIPS64_EF_CP0_EPC)); |
2eb4d78b | 371 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->badvaddr, |
28f5035f UW |
372 | (const gdb_byte *) (regp + MIPS64_EF_CP0_BADVADDR)); |
373 | supply_64bit_reg (regcache, MIPS_PS_REGNUM, | |
374 | (const gdb_byte *) (regp + MIPS64_EF_CP0_STATUS)); | |
2eb4d78b | 375 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->cause, |
28f5035f | 376 | (const gdb_byte *) (regp + MIPS64_EF_CP0_CAUSE)); |
96f026fc KB |
377 | |
378 | /* Fill inaccessible registers with zero. */ | |
822b6570 | 379 | regcache_raw_supply (regcache, MIPS_ZERO_REGNUM, zerobuf); |
28f5035f | 380 | regcache_raw_supply (regcache, MIPS_UNUSED_REGNUM, zerobuf); |
295093a4 | 381 | for (regi = MIPS_FIRST_EMBED_REGNUM; |
822b6570 | 382 | regi <= MIPS_LAST_EMBED_REGNUM; |
295093a4 | 383 | regi++) |
28f5035f | 384 | regcache_raw_supply (regcache, regi, zerobuf); |
96f026fc KB |
385 | } |
386 | ||
50e8a0d5 HZ |
387 | static void |
388 | mips64_supply_gregset_wrapper (const struct regset *regset, | |
389 | struct regcache *regcache, | |
390 | int regnum, const void *gregs, size_t len) | |
391 | { | |
392 | gdb_assert (len == sizeof (mips64_elf_gregset_t)); | |
393 | ||
394 | mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *)gregs); | |
395 | } | |
396 | ||
d37eb719 | 397 | /* Pack our registers (or one register) into a 64-bit elf_gregset_t. */ |
96f026fc | 398 | |
d37eb719 | 399 | void |
28f5035f UW |
400 | mips64_fill_gregset (const struct regcache *regcache, |
401 | mips64_elf_gregset_t *gregsetp, int regno) | |
96f026fc | 402 | { |
2eb4d78b | 403 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
e17a4113 | 404 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
96f026fc KB |
405 | int regaddr, regi; |
406 | mips64_elf_greg_t *regp = *gregsetp; | |
2ba93934 | 407 | void *dst; |
96f026fc KB |
408 | |
409 | if (regno == -1) | |
410 | { | |
411 | memset (regp, 0, sizeof (mips64_elf_gregset_t)); | |
822b6570 | 412 | for (regi = 1; regi < 32; regi++) |
28f5035f | 413 | mips64_fill_gregset (regcache, gregsetp, regi); |
2eb4d78b UW |
414 | mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->lo); |
415 | mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->hi); | |
416 | mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->pc); | |
025bb325 MS |
417 | mips64_fill_gregset (regcache, gregsetp, |
418 | mips_regnum (gdbarch)->badvaddr); | |
28f5035f | 419 | mips64_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM); |
2eb4d78b | 420 | mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->cause); |
822b6570 | 421 | mips64_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM); |
96f026fc KB |
422 | return; |
423 | } | |
424 | ||
822b6570 | 425 | if (regno > 0 && regno < 32) |
d37eb719 | 426 | regaddr = regno + MIPS64_EF_REG0; |
2eb4d78b | 427 | else if (regno == mips_regnum (gdbarch)->lo) |
56cea623 | 428 | regaddr = MIPS64_EF_LO; |
2eb4d78b | 429 | else if (regno == mips_regnum (gdbarch)->hi) |
56cea623 | 430 | regaddr = MIPS64_EF_HI; |
2eb4d78b | 431 | else if (regno == mips_regnum (gdbarch)->pc) |
56cea623 | 432 | regaddr = MIPS64_EF_CP0_EPC; |
2eb4d78b | 433 | else if (regno == mips_regnum (gdbarch)->badvaddr) |
56cea623 | 434 | regaddr = MIPS64_EF_CP0_BADVADDR; |
24e05951 | 435 | else if (regno == MIPS_PS_REGNUM) |
56cea623 | 436 | regaddr = MIPS64_EF_CP0_STATUS; |
2eb4d78b | 437 | else if (regno == mips_regnum (gdbarch)->cause) |
56cea623 | 438 | regaddr = MIPS64_EF_CP0_CAUSE; |
2eb4d78b | 439 | else if (mips_linux_restart_reg_p (gdbarch) |
822b6570 DJ |
440 | && regno == MIPS_RESTART_REGNUM) |
441 | regaddr = MIPS64_EF_REG0; | |
56cea623 AC |
442 | else |
443 | regaddr = -1; | |
96f026fc KB |
444 | |
445 | if (regaddr != -1) | |
446 | { | |
d37eb719 DJ |
447 | gdb_byte buf[MAX_REGISTER_SIZE]; |
448 | LONGEST val; | |
449 | ||
28f5035f | 450 | regcache_raw_collect (regcache, regno, buf); |
e17a4113 UW |
451 | val = extract_signed_integer (buf, register_size (gdbarch, regno), |
452 | byte_order); | |
96f026fc | 453 | dst = regp + regaddr; |
e17a4113 | 454 | store_signed_integer (dst, 8, byte_order, val); |
96f026fc KB |
455 | } |
456 | } | |
457 | ||
50e8a0d5 HZ |
458 | static void |
459 | mips64_fill_gregset_wrapper (const struct regset *regset, | |
460 | const struct regcache *regcache, | |
461 | int regnum, void *gregs, size_t len) | |
462 | { | |
463 | gdb_assert (len == sizeof (mips64_elf_gregset_t)); | |
464 | ||
465 | mips64_fill_gregset (regcache, (mips64_elf_gregset_t *)gregs, regnum); | |
466 | } | |
467 | ||
96f026fc KB |
468 | /* Likewise, unpack an elf_fpregset_t. */ |
469 | ||
d37eb719 | 470 | void |
28f5035f UW |
471 | mips64_supply_fpregset (struct regcache *regcache, |
472 | const mips64_elf_fpregset_t *fpregsetp) | |
96f026fc | 473 | { |
2eb4d78b | 474 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
52f0bd74 | 475 | int regi; |
96f026fc | 476 | |
d37eb719 DJ |
477 | /* See mips_linux_o32_sigframe_init for a description of the |
478 | peculiar FP register layout. */ | |
2eb4d78b | 479 | if (register_size (gdbarch, gdbarch_fp0_regnum (gdbarch)) == 4) |
d37eb719 DJ |
480 | for (regi = 0; regi < 32; regi++) |
481 | { | |
28f5035f | 482 | const gdb_byte *reg_ptr = (const gdb_byte *)(*fpregsetp + (regi & ~1)); |
2eb4d78b | 483 | if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (regi & 1)) |
d37eb719 | 484 | reg_ptr += 4; |
3e8c568d | 485 | regcache_raw_supply (regcache, |
2eb4d78b | 486 | gdbarch_fp0_regnum (gdbarch) + regi, |
3e8c568d | 487 | reg_ptr); |
d37eb719 DJ |
488 | } |
489 | else | |
490 | for (regi = 0; regi < 32; regi++) | |
3e8c568d | 491 | regcache_raw_supply (regcache, |
2eb4d78b | 492 | gdbarch_fp0_regnum (gdbarch) + regi, |
28f5035f | 493 | (const char *)(*fpregsetp + regi)); |
d37eb719 | 494 | |
2eb4d78b | 495 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->fp_control_status, |
28f5035f | 496 | (const gdb_byte *)(*fpregsetp + 32)); |
d37eb719 DJ |
497 | |
498 | /* The ABI doesn't tell us how to supply FCRIR, and core dumps don't | |
499 | include it - but the result of PTRACE_GETFPREGS does. The best we | |
500 | can do is to assume that its value is present. */ | |
28f5035f | 501 | supply_32bit_reg (regcache, |
2eb4d78b | 502 | mips_regnum (gdbarch)->fp_implementation_revision, |
28f5035f | 503 | (const gdb_byte *)(*fpregsetp + 32) + 4); |
96f026fc KB |
504 | } |
505 | ||
50e8a0d5 HZ |
506 | static void |
507 | mips64_supply_fpregset_wrapper (const struct regset *regset, | |
508 | struct regcache *regcache, | |
509 | int regnum, const void *gregs, size_t len) | |
510 | { | |
511 | gdb_assert (len == sizeof (mips64_elf_fpregset_t)); | |
512 | ||
513 | mips64_supply_fpregset (regcache, (const mips64_elf_fpregset_t *)gregs); | |
514 | } | |
515 | ||
96f026fc KB |
516 | /* Likewise, pack one or all floating point registers into an |
517 | elf_fpregset_t. */ | |
518 | ||
d37eb719 | 519 | void |
28f5035f UW |
520 | mips64_fill_fpregset (const struct regcache *regcache, |
521 | mips64_elf_fpregset_t *fpregsetp, int regno) | |
96f026fc | 522 | { |
2eb4d78b | 523 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
e17a4113 | 524 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d37eb719 | 525 | gdb_byte *to; |
96f026fc | 526 | |
2eb4d78b UW |
527 | if ((regno >= gdbarch_fp0_regnum (gdbarch)) |
528 | && (regno < gdbarch_fp0_regnum (gdbarch) + 32)) | |
96f026fc | 529 | { |
d37eb719 DJ |
530 | /* See mips_linux_o32_sigframe_init for a description of the |
531 | peculiar FP register layout. */ | |
2eb4d78b | 532 | if (register_size (gdbarch, regno) == 4) |
d37eb719 | 533 | { |
2eb4d78b | 534 | int regi = regno - gdbarch_fp0_regnum (gdbarch); |
d37eb719 DJ |
535 | |
536 | to = (gdb_byte *) (*fpregsetp + (regi & ~1)); | |
2eb4d78b | 537 | if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (regi & 1)) |
d37eb719 | 538 | to += 4; |
28f5035f | 539 | regcache_raw_collect (regcache, regno, to); |
d37eb719 DJ |
540 | } |
541 | else | |
542 | { | |
025bb325 MS |
543 | to = (gdb_byte *) (*fpregsetp + regno |
544 | - gdbarch_fp0_regnum (gdbarch)); | |
28f5035f | 545 | regcache_raw_collect (regcache, regno, to); |
d37eb719 | 546 | } |
96f026fc | 547 | } |
2eb4d78b | 548 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
96f026fc | 549 | { |
d37eb719 DJ |
550 | gdb_byte buf[MAX_REGISTER_SIZE]; |
551 | LONGEST val; | |
552 | ||
28f5035f | 553 | regcache_raw_collect (regcache, regno, buf); |
e17a4113 UW |
554 | val = extract_signed_integer (buf, register_size (gdbarch, regno), |
555 | byte_order); | |
d37eb719 | 556 | to = (gdb_byte *) (*fpregsetp + 32); |
e17a4113 | 557 | store_signed_integer (to, 4, byte_order, val); |
d37eb719 | 558 | } |
2eb4d78b | 559 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
d37eb719 DJ |
560 | { |
561 | gdb_byte buf[MAX_REGISTER_SIZE]; | |
562 | LONGEST val; | |
563 | ||
28f5035f | 564 | regcache_raw_collect (regcache, regno, buf); |
e17a4113 UW |
565 | val = extract_signed_integer (buf, register_size (gdbarch, regno), |
566 | byte_order); | |
d37eb719 | 567 | to = (gdb_byte *) (*fpregsetp + 32) + 4; |
e17a4113 | 568 | store_signed_integer (to, 4, byte_order, val); |
96f026fc KB |
569 | } |
570 | else if (regno == -1) | |
571 | { | |
572 | int regi; | |
573 | ||
574 | for (regi = 0; regi < 32; regi++) | |
3e8c568d | 575 | mips64_fill_fpregset (regcache, fpregsetp, |
2eb4d78b | 576 | gdbarch_fp0_regnum (gdbarch) + regi); |
28f5035f | 577 | mips64_fill_fpregset (regcache, fpregsetp, |
2eb4d78b | 578 | mips_regnum (gdbarch)->fp_control_status); |
28f5035f | 579 | mips64_fill_fpregset (regcache, fpregsetp, |
2eb4d78b UW |
580 | (mips_regnum (gdbarch) |
581 | ->fp_implementation_revision)); | |
96f026fc KB |
582 | } |
583 | } | |
584 | ||
50e8a0d5 HZ |
585 | static void |
586 | mips64_fill_fpregset_wrapper (const struct regset *regset, | |
587 | const struct regcache *regcache, | |
588 | int regnum, void *gregs, size_t len) | |
589 | { | |
590 | gdb_assert (len == sizeof (mips64_elf_fpregset_t)); | |
96f026fc | 591 | |
50e8a0d5 HZ |
592 | mips64_fill_fpregset (regcache, (mips64_elf_fpregset_t *)gregs, regnum); |
593 | } | |
2aa830e4 | 594 | |
50e8a0d5 HZ |
595 | const struct regset * |
596 | mips_linux_regset_from_core_section (struct gdbarch *gdbarch, | |
597 | const char *sect_name, size_t sect_size) | |
2aa830e4 | 598 | { |
50e8a0d5 | 599 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
d37eb719 DJ |
600 | mips_elf_gregset_t gregset; |
601 | mips_elf_fpregset_t fpregset; | |
96f026fc KB |
602 | mips64_elf_gregset_t gregset64; |
603 | mips64_elf_fpregset_t fpregset64; | |
2aa830e4 | 604 | |
50e8a0d5 | 605 | if (strcmp (sect_name, ".reg") == 0) |
2aa830e4 | 606 | { |
50e8a0d5 | 607 | if (sect_size == sizeof (gregset)) |
2aa830e4 | 608 | { |
50e8a0d5 HZ |
609 | if (tdep->gregset == NULL) |
610 | tdep->gregset = regset_alloc (gdbarch, | |
611 | mips_supply_gregset_wrapper, | |
612 | mips_fill_gregset_wrapper); | |
613 | return tdep->gregset; | |
96f026fc | 614 | } |
50e8a0d5 | 615 | else if (sect_size == sizeof (gregset64)) |
96f026fc | 616 | { |
50e8a0d5 HZ |
617 | if (tdep->gregset64 == NULL) |
618 | tdep->gregset64 = regset_alloc (gdbarch, | |
619 | mips64_supply_gregset_wrapper, | |
620 | mips64_fill_gregset_wrapper); | |
621 | return tdep->gregset64; | |
2aa830e4 DJ |
622 | } |
623 | else | |
624 | { | |
8a3fe4f8 | 625 | warning (_("wrong size gregset struct in core file")); |
2aa830e4 DJ |
626 | } |
627 | } | |
50e8a0d5 | 628 | else if (strcmp (sect_name, ".reg2") == 0) |
2aa830e4 | 629 | { |
50e8a0d5 | 630 | if (sect_size == sizeof (fpregset)) |
2aa830e4 | 631 | { |
50e8a0d5 HZ |
632 | if (tdep->fpregset == NULL) |
633 | tdep->fpregset = regset_alloc (gdbarch, | |
634 | mips_supply_fpregset_wrapper, | |
635 | mips_fill_fpregset_wrapper); | |
636 | return tdep->fpregset; | |
96f026fc | 637 | } |
50e8a0d5 | 638 | else if (sect_size == sizeof (fpregset64)) |
96f026fc | 639 | { |
50e8a0d5 HZ |
640 | if (tdep->fpregset64 == NULL) |
641 | tdep->fpregset64 = regset_alloc (gdbarch, | |
642 | mips64_supply_fpregset_wrapper, | |
643 | mips64_fill_fpregset_wrapper); | |
644 | return tdep->fpregset64; | |
2aa830e4 DJ |
645 | } |
646 | else | |
647 | { | |
8a3fe4f8 | 648 | warning (_("wrong size fpregset struct in core file")); |
2aa830e4 DJ |
649 | } |
650 | } | |
2aa830e4 | 651 | |
50e8a0d5 HZ |
652 | return NULL; |
653 | } | |
2aa830e4 | 654 | |
4eb0ad19 DJ |
655 | static const struct target_desc * |
656 | mips_linux_core_read_description (struct gdbarch *gdbarch, | |
657 | struct target_ops *target, | |
658 | bfd *abfd) | |
659 | { | |
660 | asection *section = bfd_get_section_by_name (abfd, ".reg"); | |
661 | if (! section) | |
662 | return NULL; | |
663 | ||
664 | switch (bfd_section_size (abfd, section)) | |
665 | { | |
666 | case sizeof (mips_elf_gregset_t): | |
667 | return mips_tdesc_gp32; | |
668 | ||
669 | case sizeof (mips64_elf_gregset_t): | |
670 | return mips_tdesc_gp64; | |
671 | ||
672 | default: | |
673 | return NULL; | |
674 | } | |
675 | } | |
676 | ||
96f026fc | 677 | |
295093a4 MS |
678 | /* Check the code at PC for a dynamic linker lazy resolution stub. |
679 | Because they aren't in the .plt section, we pattern-match on the | |
680 | code generated by GNU ld. They look like this: | |
6de918a6 DJ |
681 | |
682 | lw t9,0x8010(gp) | |
683 | addu t7,ra | |
684 | jalr t9,ra | |
685 | addiu t8,zero,INDEX | |
686 | ||
295093a4 MS |
687 | (with the appropriate doubleword instructions for N64). Also |
688 | return the dynamic symbol index used in the last instruction. */ | |
6de918a6 DJ |
689 | |
690 | static int | |
691 | mips_linux_in_dynsym_stub (CORE_ADDR pc, char *name) | |
692 | { | |
693 | unsigned char buf[28], *p; | |
694 | ULONGEST insn, insn1; | |
1cf3db46 | 695 | int n64 = (mips_abi (target_gdbarch) == MIPS_ABI_N64); |
e17a4113 | 696 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch); |
6de918a6 DJ |
697 | |
698 | read_memory (pc - 12, buf, 28); | |
699 | ||
700 | if (n64) | |
701 | { | |
702 | /* ld t9,0x8010(gp) */ | |
703 | insn1 = 0xdf998010; | |
704 | } | |
705 | else | |
706 | { | |
707 | /* lw t9,0x8010(gp) */ | |
708 | insn1 = 0x8f998010; | |
709 | } | |
710 | ||
711 | p = buf + 12; | |
712 | while (p >= buf) | |
713 | { | |
e17a4113 | 714 | insn = extract_unsigned_integer (p, 4, byte_order); |
6de918a6 DJ |
715 | if (insn == insn1) |
716 | break; | |
717 | p -= 4; | |
718 | } | |
719 | if (p < buf) | |
720 | return 0; | |
721 | ||
e17a4113 | 722 | insn = extract_unsigned_integer (p + 4, 4, byte_order); |
6de918a6 DJ |
723 | if (n64) |
724 | { | |
725 | /* daddu t7,ra */ | |
726 | if (insn != 0x03e0782d) | |
727 | return 0; | |
728 | } | |
729 | else | |
730 | { | |
731 | /* addu t7,ra */ | |
732 | if (insn != 0x03e07821) | |
733 | return 0; | |
734 | } | |
295093a4 | 735 | |
e17a4113 | 736 | insn = extract_unsigned_integer (p + 8, 4, byte_order); |
6de918a6 DJ |
737 | /* jalr t9,ra */ |
738 | if (insn != 0x0320f809) | |
739 | return 0; | |
740 | ||
e17a4113 | 741 | insn = extract_unsigned_integer (p + 12, 4, byte_order); |
6de918a6 DJ |
742 | if (n64) |
743 | { | |
744 | /* daddiu t8,zero,0 */ | |
745 | if ((insn & 0xffff0000) != 0x64180000) | |
746 | return 0; | |
747 | } | |
748 | else | |
749 | { | |
750 | /* addiu t8,zero,0 */ | |
751 | if ((insn & 0xffff0000) != 0x24180000) | |
752 | return 0; | |
753 | } | |
754 | ||
755 | return (insn & 0xffff); | |
756 | } | |
757 | ||
295093a4 | 758 | /* Return non-zero iff PC belongs to the dynamic linker resolution |
db5f024e | 759 | code, a PLT entry, or a lazy binding stub. */ |
6de918a6 | 760 | |
7d522c90 | 761 | static int |
6de918a6 DJ |
762 | mips_linux_in_dynsym_resolve_code (CORE_ADDR pc) |
763 | { | |
295093a4 | 764 | /* Check whether PC is in the dynamic linker. This also checks |
db5f024e | 765 | whether it is in the .plt section, used by non-PIC executables. */ |
7d522c90 | 766 | if (svr4_in_dynsym_resolve_code (pc)) |
6de918a6 DJ |
767 | return 1; |
768 | ||
295093a4 MS |
769 | /* Pattern match for the stub. It would be nice if there were a |
770 | more efficient way to avoid this check. */ | |
6de918a6 DJ |
771 | if (mips_linux_in_dynsym_stub (pc, NULL)) |
772 | return 1; | |
773 | ||
774 | return 0; | |
775 | } | |
776 | ||
777 | /* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c, | |
778 | and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc | |
779 | implementation of this triggers at "fixup" from the same objfile as | |
c4c5b7ba | 780 | "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at |
db5f024e DJ |
781 | "__dl_runtime_resolve" directly. An unresolved lazy binding |
782 | stub will point to _dl_runtime_resolve, which will first call | |
c4c5b7ba AC |
783 | __dl_runtime_resolve, and then pass control to the resolved |
784 | function. */ | |
6de918a6 DJ |
785 | |
786 | static CORE_ADDR | |
787 | mips_linux_skip_resolver (struct gdbarch *gdbarch, CORE_ADDR pc) | |
788 | { | |
789 | struct minimal_symbol *resolver; | |
790 | ||
791 | resolver = lookup_minimal_symbol ("__dl_runtime_resolve", NULL, NULL); | |
792 | ||
793 | if (resolver && SYMBOL_VALUE_ADDRESS (resolver) == pc) | |
c7ce8faa | 794 | return frame_unwind_caller_pc (get_current_frame ()); |
6de918a6 | 795 | |
db5f024e | 796 | return glibc_skip_solib_resolver (gdbarch, pc); |
295093a4 | 797 | } |
6de918a6 | 798 | |
5792a79b DJ |
799 | /* Signal trampoline support. There are four supported layouts for a |
800 | signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and | |
801 | n64 rt_sigframe. We handle them all independently; not the most | |
802 | efficient way, but simplest. First, declare all the unwinders. */ | |
803 | ||
804 | static void mips_linux_o32_sigframe_init (const struct tramp_frame *self, | |
b8a22b94 | 805 | struct frame_info *this_frame, |
5792a79b DJ |
806 | struct trad_frame_cache *this_cache, |
807 | CORE_ADDR func); | |
808 | ||
809 | static void mips_linux_n32n64_sigframe_init (const struct tramp_frame *self, | |
b8a22b94 | 810 | struct frame_info *this_frame, |
5792a79b DJ |
811 | struct trad_frame_cache *this_cache, |
812 | CORE_ADDR func); | |
813 | ||
814 | #define MIPS_NR_LINUX 4000 | |
815 | #define MIPS_NR_N64_LINUX 5000 | |
816 | #define MIPS_NR_N32_LINUX 6000 | |
817 | ||
818 | #define MIPS_NR_sigreturn MIPS_NR_LINUX + 119 | |
819 | #define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193 | |
820 | #define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211 | |
821 | #define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211 | |
822 | ||
823 | #define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn | |
824 | #define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn | |
825 | #define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn | |
826 | #define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn | |
827 | #define MIPS_INST_SYSCALL 0x0000000c | |
828 | ||
2cd8546d AC |
829 | static const struct tramp_frame mips_linux_o32_sigframe = { |
830 | SIGTRAMP_FRAME, | |
5792a79b | 831 | 4, |
2cd8546d AC |
832 | { |
833 | { MIPS_INST_LI_V0_SIGRETURN, -1 }, | |
834 | { MIPS_INST_SYSCALL, -1 }, | |
835 | { TRAMP_SENTINEL_INSN, -1 } | |
836 | }, | |
5792a79b DJ |
837 | mips_linux_o32_sigframe_init |
838 | }; | |
839 | ||
2cd8546d AC |
840 | static const struct tramp_frame mips_linux_o32_rt_sigframe = { |
841 | SIGTRAMP_FRAME, | |
5792a79b | 842 | 4, |
2cd8546d AC |
843 | { |
844 | { MIPS_INST_LI_V0_RT_SIGRETURN, -1 }, | |
845 | { MIPS_INST_SYSCALL, -1 }, | |
846 | { TRAMP_SENTINEL_INSN, -1 } }, | |
5792a79b DJ |
847 | mips_linux_o32_sigframe_init |
848 | }; | |
849 | ||
2cd8546d AC |
850 | static const struct tramp_frame mips_linux_n32_rt_sigframe = { |
851 | SIGTRAMP_FRAME, | |
5792a79b | 852 | 4, |
2cd8546d AC |
853 | { |
854 | { MIPS_INST_LI_V0_N32_RT_SIGRETURN, -1 }, | |
855 | { MIPS_INST_SYSCALL, -1 }, | |
856 | { TRAMP_SENTINEL_INSN, -1 } | |
857 | }, | |
5792a79b DJ |
858 | mips_linux_n32n64_sigframe_init |
859 | }; | |
860 | ||
2cd8546d AC |
861 | static const struct tramp_frame mips_linux_n64_rt_sigframe = { |
862 | SIGTRAMP_FRAME, | |
5792a79b | 863 | 4, |
fcbd8a5c TS |
864 | { |
865 | { MIPS_INST_LI_V0_N64_RT_SIGRETURN, -1 }, | |
866 | { MIPS_INST_SYSCALL, -1 }, | |
867 | { TRAMP_SENTINEL_INSN, -1 } | |
868 | }, | |
5792a79b DJ |
869 | mips_linux_n32n64_sigframe_init |
870 | }; | |
871 | ||
872 | /* *INDENT-OFF* */ | |
873 | /* The unwinder for o32 signal frames. The legacy structures look | |
874 | like this: | |
875 | ||
876 | struct sigframe { | |
877 | u32 sf_ass[4]; [argument save space for o32] | |
eb195664 | 878 | u32 sf_code[2]; [signal trampoline or fill] |
5792a79b DJ |
879 | struct sigcontext sf_sc; |
880 | sigset_t sf_mask; | |
881 | }; | |
882 | ||
883 | struct sigcontext { | |
884 | unsigned int sc_regmask; [Unused] | |
885 | unsigned int sc_status; | |
886 | unsigned long long sc_pc; | |
887 | unsigned long long sc_regs[32]; | |
888 | unsigned long long sc_fpregs[32]; | |
889 | unsigned int sc_ownedfp; | |
890 | unsigned int sc_fpc_csr; | |
891 | unsigned int sc_fpc_eir; [Unused] | |
892 | unsigned int sc_used_math; | |
893 | unsigned int sc_ssflags; [Unused] | |
894 | [Alignment hole of four bytes] | |
895 | unsigned long long sc_mdhi; | |
896 | unsigned long long sc_mdlo; | |
897 | ||
898 | unsigned int sc_cause; [Unused] | |
899 | unsigned int sc_badvaddr; [Unused] | |
900 | ||
901 | unsigned long sc_sigset[4]; [kernel's sigset_t] | |
902 | }; | |
903 | ||
904 | The RT signal frames look like this: | |
905 | ||
906 | struct rt_sigframe { | |
907 | u32 rs_ass[4]; [argument save space for o32] | |
eb195664 | 908 | u32 rs_code[2] [signal trampoline or fill] |
5792a79b DJ |
909 | struct siginfo rs_info; |
910 | struct ucontext rs_uc; | |
911 | }; | |
912 | ||
913 | struct ucontext { | |
914 | unsigned long uc_flags; | |
915 | struct ucontext *uc_link; | |
916 | stack_t uc_stack; | |
917 | [Alignment hole of four bytes] | |
918 | struct sigcontext uc_mcontext; | |
919 | sigset_t uc_sigmask; | |
920 | }; */ | |
921 | /* *INDENT-ON* */ | |
922 | ||
5792a79b DJ |
923 | #define SIGFRAME_SIGCONTEXT_OFFSET (6 * 4) |
924 | ||
925 | #define RTSIGFRAME_SIGINFO_SIZE 128 | |
926 | #define STACK_T_SIZE (3 * 4) | |
927 | #define UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + STACK_T_SIZE + 4) | |
928 | #define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ | |
929 | + RTSIGFRAME_SIGINFO_SIZE \ | |
930 | + UCONTEXT_SIGCONTEXT_OFFSET) | |
931 | ||
932 | #define SIGCONTEXT_PC (1 * 8) | |
933 | #define SIGCONTEXT_REGS (2 * 8) | |
934 | #define SIGCONTEXT_FPREGS (34 * 8) | |
935 | #define SIGCONTEXT_FPCSR (66 * 8 + 4) | |
936 | #define SIGCONTEXT_HI (69 * 8) | |
937 | #define SIGCONTEXT_LO (70 * 8) | |
938 | #define SIGCONTEXT_CAUSE (71 * 8 + 0) | |
939 | #define SIGCONTEXT_BADVADDR (71 * 8 + 4) | |
940 | ||
941 | #define SIGCONTEXT_REG_SIZE 8 | |
942 | ||
943 | static void | |
944 | mips_linux_o32_sigframe_init (const struct tramp_frame *self, | |
b8a22b94 | 945 | struct frame_info *this_frame, |
5792a79b DJ |
946 | struct trad_frame_cache *this_cache, |
947 | CORE_ADDR func) | |
948 | { | |
b8a22b94 | 949 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
5792a79b | 950 | int ireg, reg_position; |
eb195664 DD |
951 | CORE_ADDR frame_sp = get_frame_sp (this_frame); |
952 | CORE_ADDR sigcontext_base; | |
2eb4d78b | 953 | const struct mips_regnum *regs = mips_regnum (gdbarch); |
37c4d197 | 954 | CORE_ADDR regs_base; |
5792a79b DJ |
955 | |
956 | if (self == &mips_linux_o32_sigframe) | |
eb195664 | 957 | sigcontext_base = frame_sp + SIGFRAME_SIGCONTEXT_OFFSET; |
5792a79b | 958 | else |
eb195664 | 959 | sigcontext_base = frame_sp + RTSIGFRAME_SIGCONTEXT_OFFSET; |
295093a4 MS |
960 | |
961 | /* I'm not proud of this hack. Eventually we will have the | |
962 | infrastructure to indicate the size of saved registers on a | |
963 | per-frame basis, but right now we don't; the kernel saves eight | |
37c4d197 DJ |
964 | bytes but we only want four. Use regs_base to access any |
965 | 64-bit fields. */ | |
2eb4d78b | 966 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
37c4d197 DJ |
967 | regs_base = sigcontext_base + 4; |
968 | else | |
969 | regs_base = sigcontext_base; | |
5792a79b | 970 | |
2eb4d78b | 971 | if (mips_linux_restart_reg_p (gdbarch)) |
822b6570 DJ |
972 | trad_frame_set_reg_addr (this_cache, |
973 | (MIPS_RESTART_REGNUM | |
2eb4d78b | 974 | + gdbarch_num_regs (gdbarch)), |
822b6570 | 975 | regs_base + SIGCONTEXT_REGS); |
5792a79b DJ |
976 | |
977 | for (ireg = 1; ireg < 32; ireg++) | |
295093a4 | 978 | trad_frame_set_reg_addr (this_cache, |
f57d151a | 979 | ireg + MIPS_ZERO_REGNUM |
2eb4d78b | 980 | + gdbarch_num_regs (gdbarch), |
37c4d197 | 981 | regs_base + SIGCONTEXT_REGS |
5792a79b DJ |
982 | + ireg * SIGCONTEXT_REG_SIZE); |
983 | ||
37c4d197 DJ |
984 | /* The way that floating point registers are saved, unfortunately, |
985 | depends on the architecture the kernel is built for. For the r3000 and | |
986 | tx39, four bytes of each register are at the beginning of each of the | |
987 | 32 eight byte slots. For everything else, the registers are saved | |
988 | using double precision; only the even-numbered slots are initialized, | |
989 | and the high bits are the odd-numbered register. Assume the latter | |
990 | layout, since we can't tell, and it's much more common. Which bits are | |
991 | the "high" bits depends on endianness. */ | |
5792a79b | 992 | for (ireg = 0; ireg < 32; ireg++) |
2eb4d78b | 993 | if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (ireg & 1)) |
f57d151a UW |
994 | trad_frame_set_reg_addr (this_cache, |
995 | ireg + regs->fp0 + | |
2eb4d78b | 996 | gdbarch_num_regs (gdbarch), |
37c4d197 DJ |
997 | sigcontext_base + SIGCONTEXT_FPREGS + 4 |
998 | + (ireg & ~1) * SIGCONTEXT_REG_SIZE); | |
999 | else | |
f57d151a UW |
1000 | trad_frame_set_reg_addr (this_cache, |
1001 | ireg + regs->fp0 | |
2eb4d78b | 1002 | + gdbarch_num_regs (gdbarch), |
37c4d197 DJ |
1003 | sigcontext_base + SIGCONTEXT_FPREGS |
1004 | + (ireg & ~1) * SIGCONTEXT_REG_SIZE); | |
5792a79b | 1005 | |
f57d151a | 1006 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1007 | regs->pc + gdbarch_num_regs (gdbarch), |
37c4d197 | 1008 | regs_base + SIGCONTEXT_PC); |
5792a79b | 1009 | |
295093a4 | 1010 | trad_frame_set_reg_addr (this_cache, |
f57d151a | 1011 | regs->fp_control_status |
2eb4d78b | 1012 | + gdbarch_num_regs (gdbarch), |
5792a79b | 1013 | sigcontext_base + SIGCONTEXT_FPCSR); |
f57d151a | 1014 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1015 | regs->hi + gdbarch_num_regs (gdbarch), |
37c4d197 | 1016 | regs_base + SIGCONTEXT_HI); |
f57d151a | 1017 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1018 | regs->lo + gdbarch_num_regs (gdbarch), |
37c4d197 | 1019 | regs_base + SIGCONTEXT_LO); |
f57d151a | 1020 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1021 | regs->cause + gdbarch_num_regs (gdbarch), |
5792a79b | 1022 | sigcontext_base + SIGCONTEXT_CAUSE); |
f57d151a | 1023 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1024 | regs->badvaddr + gdbarch_num_regs (gdbarch), |
5792a79b DJ |
1025 | sigcontext_base + SIGCONTEXT_BADVADDR); |
1026 | ||
1027 | /* Choice of the bottom of the sigframe is somewhat arbitrary. */ | |
eb195664 | 1028 | trad_frame_set_id (this_cache, frame_id_build (frame_sp, func)); |
5792a79b DJ |
1029 | } |
1030 | ||
1031 | /* *INDENT-OFF* */ | |
1032 | /* For N32/N64 things look different. There is no non-rt signal frame. | |
1033 | ||
1034 | struct rt_sigframe_n32 { | |
1035 | u32 rs_ass[4]; [ argument save space for o32 ] | |
eb195664 | 1036 | u32 rs_code[2]; [ signal trampoline or fill ] |
5792a79b DJ |
1037 | struct siginfo rs_info; |
1038 | struct ucontextn32 rs_uc; | |
1039 | }; | |
1040 | ||
1041 | struct ucontextn32 { | |
1042 | u32 uc_flags; | |
1043 | s32 uc_link; | |
1044 | stack32_t uc_stack; | |
1045 | struct sigcontext uc_mcontext; | |
1046 | sigset_t uc_sigmask; [ mask last for extensibility ] | |
1047 | }; | |
295093a4 | 1048 | |
e741f4d4 | 1049 | struct rt_sigframe { |
5792a79b DJ |
1050 | u32 rs_ass[4]; [ argument save space for o32 ] |
1051 | u32 rs_code[2]; [ signal trampoline ] | |
1052 | struct siginfo rs_info; | |
1053 | struct ucontext rs_uc; | |
1054 | }; | |
1055 | ||
1056 | struct ucontext { | |
1057 | unsigned long uc_flags; | |
1058 | struct ucontext *uc_link; | |
1059 | stack_t uc_stack; | |
1060 | struct sigcontext uc_mcontext; | |
1061 | sigset_t uc_sigmask; [ mask last for extensibility ] | |
1062 | }; | |
1063 | ||
1064 | And the sigcontext is different (this is for both n32 and n64): | |
1065 | ||
1066 | struct sigcontext { | |
1067 | unsigned long long sc_regs[32]; | |
1068 | unsigned long long sc_fpregs[32]; | |
1069 | unsigned long long sc_mdhi; | |
e741f4d4 DJ |
1070 | unsigned long long sc_hi1; |
1071 | unsigned long long sc_hi2; | |
1072 | unsigned long long sc_hi3; | |
5792a79b | 1073 | unsigned long long sc_mdlo; |
e741f4d4 DJ |
1074 | unsigned long long sc_lo1; |
1075 | unsigned long long sc_lo2; | |
1076 | unsigned long long sc_lo3; | |
5792a79b | 1077 | unsigned long long sc_pc; |
5792a79b | 1078 | unsigned int sc_fpc_csr; |
5792a79b | 1079 | unsigned int sc_used_math; |
e741f4d4 DJ |
1080 | unsigned int sc_dsp; |
1081 | unsigned int sc_reserved; | |
1082 | }; | |
1083 | ||
1084 | That is the post-2.6.12 definition of the 64-bit sigcontext; before | |
1085 | then, there were no hi1-hi3 or lo1-lo3. Cause and badvaddr were | |
1086 | included too. */ | |
5792a79b DJ |
1087 | /* *INDENT-ON* */ |
1088 | ||
1089 | #define N32_STACK_T_SIZE STACK_T_SIZE | |
1090 | #define N64_STACK_T_SIZE (2 * 8 + 4) | |
1091 | #define N32_UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + N32_STACK_T_SIZE + 4) | |
1092 | #define N64_UCONTEXT_SIGCONTEXT_OFFSET (2 * 8 + N64_STACK_T_SIZE + 4) | |
1093 | #define N32_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ | |
1094 | + RTSIGFRAME_SIGINFO_SIZE \ | |
1095 | + N32_UCONTEXT_SIGCONTEXT_OFFSET) | |
1096 | #define N64_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ | |
1097 | + RTSIGFRAME_SIGINFO_SIZE \ | |
1098 | + N64_UCONTEXT_SIGCONTEXT_OFFSET) | |
1099 | ||
1100 | #define N64_SIGCONTEXT_REGS (0 * 8) | |
1101 | #define N64_SIGCONTEXT_FPREGS (32 * 8) | |
1102 | #define N64_SIGCONTEXT_HI (64 * 8) | |
e741f4d4 DJ |
1103 | #define N64_SIGCONTEXT_LO (68 * 8) |
1104 | #define N64_SIGCONTEXT_PC (72 * 8) | |
1105 | #define N64_SIGCONTEXT_FPCSR (73 * 8) | |
5792a79b DJ |
1106 | |
1107 | #define N64_SIGCONTEXT_REG_SIZE 8 | |
295093a4 | 1108 | |
5792a79b DJ |
1109 | static void |
1110 | mips_linux_n32n64_sigframe_init (const struct tramp_frame *self, | |
b8a22b94 | 1111 | struct frame_info *this_frame, |
5792a79b DJ |
1112 | struct trad_frame_cache *this_cache, |
1113 | CORE_ADDR func) | |
1114 | { | |
b8a22b94 | 1115 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
5792a79b | 1116 | int ireg, reg_position; |
eb195664 DD |
1117 | CORE_ADDR frame_sp = get_frame_sp (this_frame); |
1118 | CORE_ADDR sigcontext_base; | |
2eb4d78b | 1119 | const struct mips_regnum *regs = mips_regnum (gdbarch); |
5792a79b DJ |
1120 | |
1121 | if (self == &mips_linux_n32_rt_sigframe) | |
eb195664 | 1122 | sigcontext_base = frame_sp + N32_SIGFRAME_SIGCONTEXT_OFFSET; |
5792a79b | 1123 | else |
eb195664 | 1124 | sigcontext_base = frame_sp + N64_SIGFRAME_SIGCONTEXT_OFFSET; |
295093a4 | 1125 | |
2eb4d78b | 1126 | if (mips_linux_restart_reg_p (gdbarch)) |
822b6570 DJ |
1127 | trad_frame_set_reg_addr (this_cache, |
1128 | (MIPS_RESTART_REGNUM | |
2eb4d78b | 1129 | + gdbarch_num_regs (gdbarch)), |
822b6570 | 1130 | sigcontext_base + N64_SIGCONTEXT_REGS); |
5792a79b DJ |
1131 | |
1132 | for (ireg = 1; ireg < 32; ireg++) | |
295093a4 | 1133 | trad_frame_set_reg_addr (this_cache, |
f57d151a | 1134 | ireg + MIPS_ZERO_REGNUM |
2eb4d78b | 1135 | + gdbarch_num_regs (gdbarch), |
5792a79b DJ |
1136 | sigcontext_base + N64_SIGCONTEXT_REGS |
1137 | + ireg * N64_SIGCONTEXT_REG_SIZE); | |
1138 | ||
1139 | for (ireg = 0; ireg < 32; ireg++) | |
f57d151a UW |
1140 | trad_frame_set_reg_addr (this_cache, |
1141 | ireg + regs->fp0 | |
2eb4d78b | 1142 | + gdbarch_num_regs (gdbarch), |
5792a79b DJ |
1143 | sigcontext_base + N64_SIGCONTEXT_FPREGS |
1144 | + ireg * N64_SIGCONTEXT_REG_SIZE); | |
1145 | ||
f57d151a | 1146 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1147 | regs->pc + gdbarch_num_regs (gdbarch), |
5792a79b DJ |
1148 | sigcontext_base + N64_SIGCONTEXT_PC); |
1149 | ||
295093a4 | 1150 | trad_frame_set_reg_addr (this_cache, |
f57d151a | 1151 | regs->fp_control_status |
2eb4d78b | 1152 | + gdbarch_num_regs (gdbarch), |
5792a79b | 1153 | sigcontext_base + N64_SIGCONTEXT_FPCSR); |
f57d151a | 1154 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1155 | regs->hi + gdbarch_num_regs (gdbarch), |
5792a79b | 1156 | sigcontext_base + N64_SIGCONTEXT_HI); |
f57d151a | 1157 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1158 | regs->lo + gdbarch_num_regs (gdbarch), |
5792a79b | 1159 | sigcontext_base + N64_SIGCONTEXT_LO); |
5792a79b DJ |
1160 | |
1161 | /* Choice of the bottom of the sigframe is somewhat arbitrary. */ | |
eb195664 | 1162 | trad_frame_set_id (this_cache, frame_id_build (frame_sp, func)); |
5792a79b DJ |
1163 | } |
1164 | ||
822b6570 | 1165 | static void |
61a1198a | 1166 | mips_linux_write_pc (struct regcache *regcache, CORE_ADDR pc) |
822b6570 | 1167 | { |
2eb4d78b UW |
1168 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1169 | regcache_cooked_write_unsigned (regcache, gdbarch_pc_regnum (gdbarch), pc); | |
822b6570 DJ |
1170 | |
1171 | /* Clear the syscall restart flag. */ | |
2eb4d78b | 1172 | if (mips_linux_restart_reg_p (gdbarch)) |
61a1198a | 1173 | regcache_cooked_write_unsigned (regcache, MIPS_RESTART_REGNUM, 0); |
822b6570 DJ |
1174 | } |
1175 | ||
1176 | /* Return 1 if MIPS_RESTART_REGNUM is usable. */ | |
1177 | ||
1178 | int | |
1179 | mips_linux_restart_reg_p (struct gdbarch *gdbarch) | |
1180 | { | |
1181 | /* If we do not have a target description with registers, then | |
1182 | MIPS_RESTART_REGNUM will not be included in the register set. */ | |
1183 | if (!tdesc_has_registers (gdbarch_target_desc (gdbarch))) | |
1184 | return 0; | |
1185 | ||
1186 | /* If we do, then MIPS_RESTART_REGNUM is safe to check; it will | |
1187 | either be GPR-sized or missing. */ | |
1188 | return register_size (gdbarch, MIPS_RESTART_REGNUM) > 0; | |
1189 | } | |
9f62d0e2 | 1190 | |
e38d4e1a DJ |
1191 | /* When FRAME is at a syscall instruction, return the PC of the next |
1192 | instruction to be executed. */ | |
1193 | ||
63807e1d | 1194 | static CORE_ADDR |
e38d4e1a DJ |
1195 | mips_linux_syscall_next_pc (struct frame_info *frame) |
1196 | { | |
1197 | CORE_ADDR pc = get_frame_pc (frame); | |
1198 | ULONGEST v0 = get_frame_register_unsigned (frame, MIPS_V0_REGNUM); | |
1199 | ||
1200 | /* If we are about to make a sigreturn syscall, use the unwinder to | |
1201 | decode the signal frame. */ | |
1202 | if (v0 == MIPS_NR_sigreturn | |
1203 | || v0 == MIPS_NR_rt_sigreturn | |
1204 | || v0 == MIPS_NR_N64_rt_sigreturn | |
1205 | || v0 == MIPS_NR_N32_rt_sigreturn) | |
c7ce8faa | 1206 | return frame_unwind_caller_pc (get_current_frame ()); |
e38d4e1a DJ |
1207 | |
1208 | return pc + 4; | |
1209 | } | |
1210 | ||
385203ed DD |
1211 | /* Return the current system call's number present in the |
1212 | v0 register. When the function fails, it returns -1. */ | |
1213 | ||
1214 | static LONGEST | |
1215 | mips_linux_get_syscall_number (struct gdbarch *gdbarch, | |
1216 | ptid_t ptid) | |
1217 | { | |
1218 | struct regcache *regcache = get_thread_regcache (ptid); | |
1219 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1220 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1221 | int regsize = register_size (gdbarch, MIPS_V0_REGNUM); | |
1222 | /* The content of a register */ | |
1223 | gdb_byte buf[8]; | |
1224 | /* The result */ | |
1225 | LONGEST ret; | |
1226 | ||
1227 | /* Make sure we're in a known ABI */ | |
1228 | gdb_assert (tdep->mips_abi == MIPS_ABI_O32 | |
1229 | || tdep->mips_abi == MIPS_ABI_N32 | |
1230 | || tdep->mips_abi == MIPS_ABI_N64); | |
1231 | ||
1232 | gdb_assert (regsize <= sizeof (buf)); | |
1233 | ||
1234 | /* Getting the system call number from the register. | |
1235 | syscall number is in v0 or $2. */ | |
1236 | regcache_cooked_read (regcache, MIPS_V0_REGNUM, buf); | |
1237 | ||
1238 | ret = extract_signed_integer (buf, regsize, byte_order); | |
1239 | ||
1240 | return ret; | |
1241 | } | |
1242 | ||
5792a79b DJ |
1243 | /* Initialize one of the GNU/Linux OS ABIs. */ |
1244 | ||
19ed69dd | 1245 | static void |
295093a4 MS |
1246 | mips_linux_init_abi (struct gdbarch_info info, |
1247 | struct gdbarch *gdbarch) | |
19ed69dd | 1248 | { |
96f026fc KB |
1249 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1250 | enum mips_abi abi = mips_abi (gdbarch); | |
822b6570 | 1251 | struct tdesc_arch_data *tdesc_data = (void *) info.tdep_info; |
96f026fc | 1252 | |
a5ee0f0c PA |
1253 | linux_init_abi (info, gdbarch); |
1254 | ||
385203ed DD |
1255 | /* Get the syscall number from the arch's register. */ |
1256 | set_gdbarch_get_syscall_number (gdbarch, mips_linux_get_syscall_number); | |
1257 | ||
96f026fc KB |
1258 | switch (abi) |
1259 | { | |
1260 | case MIPS_ABI_O32: | |
1261 | set_gdbarch_get_longjmp_target (gdbarch, | |
1262 | mips_linux_get_longjmp_target); | |
1263 | set_solib_svr4_fetch_link_map_offsets | |
76a9d10f | 1264 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); |
fb2be677 AC |
1265 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_sigframe); |
1266 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_rt_sigframe); | |
385203ed | 1267 | set_xml_syscall_file_name ("syscalls/mips-o32-linux.xml"); |
96f026fc KB |
1268 | break; |
1269 | case MIPS_ABI_N32: | |
1270 | set_gdbarch_get_longjmp_target (gdbarch, | |
1271 | mips_linux_get_longjmp_target); | |
1272 | set_solib_svr4_fetch_link_map_offsets | |
76a9d10f | 1273 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); |
d05f6826 DJ |
1274 | set_gdbarch_long_double_bit (gdbarch, 128); |
1275 | /* These floatformats should probably be renamed. MIPS uses | |
1276 | the same 128-bit IEEE floating point format that IA-64 uses, | |
1277 | except that the quiet/signalling NaN bit is reversed (GDB | |
1278 | does not distinguish between quiet and signalling NaNs). */ | |
8da61cc4 | 1279 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); |
fb2be677 | 1280 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n32_rt_sigframe); |
385203ed | 1281 | set_xml_syscall_file_name ("syscalls/mips-n32-linux.xml"); |
96f026fc KB |
1282 | break; |
1283 | case MIPS_ABI_N64: | |
1284 | set_gdbarch_get_longjmp_target (gdbarch, | |
1285 | mips64_linux_get_longjmp_target); | |
1286 | set_solib_svr4_fetch_link_map_offsets | |
76a9d10f | 1287 | (gdbarch, svr4_lp64_fetch_link_map_offsets); |
d05f6826 DJ |
1288 | set_gdbarch_long_double_bit (gdbarch, 128); |
1289 | /* These floatformats should probably be renamed. MIPS uses | |
1290 | the same 128-bit IEEE floating point format that IA-64 uses, | |
1291 | except that the quiet/signalling NaN bit is reversed (GDB | |
1292 | does not distinguish between quiet and signalling NaNs). */ | |
8da61cc4 | 1293 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); |
fb2be677 | 1294 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n64_rt_sigframe); |
385203ed | 1295 | set_xml_syscall_file_name ("syscalls/mips-n64-linux.xml"); |
96f026fc KB |
1296 | break; |
1297 | default: | |
96f026fc KB |
1298 | break; |
1299 | } | |
6de918a6 DJ |
1300 | |
1301 | set_gdbarch_skip_solib_resolver (gdbarch, mips_linux_skip_resolver); | |
1302 | ||
0d0266c6 | 1303 | set_gdbarch_software_single_step (gdbarch, mips_software_single_step); |
b2756930 KB |
1304 | |
1305 | /* Enable TLS support. */ | |
1306 | set_gdbarch_fetch_tls_load_module_address (gdbarch, | |
1307 | svr4_fetch_objfile_link_map); | |
7d522c90 DJ |
1308 | |
1309 | /* Initialize this lazily, to avoid an initialization order | |
1310 | dependency on solib-svr4.c's _initialize routine. */ | |
1311 | if (mips_svr4_so_ops.in_dynsym_resolve_code == NULL) | |
1312 | { | |
1313 | mips_svr4_so_ops = svr4_so_ops; | |
1314 | mips_svr4_so_ops.in_dynsym_resolve_code | |
1315 | = mips_linux_in_dynsym_resolve_code; | |
1316 | } | |
1317 | set_solib_ops (gdbarch, &mips_svr4_so_ops); | |
822b6570 DJ |
1318 | |
1319 | set_gdbarch_write_pc (gdbarch, mips_linux_write_pc); | |
1320 | ||
4eb0ad19 DJ |
1321 | set_gdbarch_core_read_description (gdbarch, |
1322 | mips_linux_core_read_description); | |
1323 | ||
50e8a0d5 HZ |
1324 | set_gdbarch_regset_from_core_section (gdbarch, |
1325 | mips_linux_regset_from_core_section); | |
1326 | ||
e38d4e1a DJ |
1327 | tdep->syscall_next_pc = mips_linux_syscall_next_pc; |
1328 | ||
822b6570 DJ |
1329 | if (tdesc_data) |
1330 | { | |
1331 | const struct tdesc_feature *feature; | |
1332 | ||
1333 | /* If we have target-described registers, then we can safely | |
1334 | reserve a number for MIPS_RESTART_REGNUM (whether it is | |
1335 | described or not). */ | |
1336 | gdb_assert (gdbarch_num_regs (gdbarch) <= MIPS_RESTART_REGNUM); | |
1337 | set_gdbarch_num_regs (gdbarch, MIPS_RESTART_REGNUM + 1); | |
1338 | ||
1339 | /* If it's present, then assign it to the reserved number. */ | |
1340 | feature = tdesc_find_feature (info.target_desc, | |
1341 | "org.gnu.gdb.mips.linux"); | |
1342 | if (feature != NULL) | |
1343 | tdesc_numbered_register (feature, tdesc_data, MIPS_RESTART_REGNUM, | |
1344 | "restart"); | |
1345 | } | |
19ed69dd KB |
1346 | } |
1347 | ||
63807e1d PA |
1348 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
1349 | extern initialize_file_ftype _initialize_mips_linux_tdep; | |
1350 | ||
2aa830e4 | 1351 | void |
d1bacddc | 1352 | _initialize_mips_linux_tdep (void) |
2aa830e4 | 1353 | { |
96f026fc KB |
1354 | const struct bfd_arch_info *arch_info; |
1355 | ||
96f026fc KB |
1356 | for (arch_info = bfd_lookup_arch (bfd_arch_mips, 0); |
1357 | arch_info != NULL; | |
1358 | arch_info = arch_info->next) | |
1359 | { | |
295093a4 MS |
1360 | gdbarch_register_osabi (bfd_arch_mips, arch_info->mach, |
1361 | GDB_OSABI_LINUX, | |
96f026fc KB |
1362 | mips_linux_init_abi); |
1363 | } | |
2aa830e4 | 1364 | } |