Commit | Line | Data |
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75c9abc6 | 1 | /* Target-dependent code for GNU/Linux on MIPS processors. |
a094c6fb | 2 | |
61baf725 | 3 | Copyright (C) 2001-2017 Free Software Foundation, Inc. |
2aa830e4 DJ |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
2aa830e4 DJ |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
2aa830e4 DJ |
19 | |
20 | #include "defs.h" | |
21 | #include "gdbcore.h" | |
22 | #include "target.h" | |
23 | #include "solib-svr4.h" | |
19ed69dd | 24 | #include "osabi.h" |
96f026fc | 25 | #include "mips-tdep.h" |
6de918a6 | 26 | #include "frame.h" |
2fdf551c | 27 | #include "regcache.h" |
5792a79b DJ |
28 | #include "trad-frame.h" |
29 | #include "tramp-frame.h" | |
e6bb342a | 30 | #include "gdbtypes.h" |
3e5d3a5a | 31 | #include "objfiles.h" |
5ea03926 | 32 | #include "solib.h" |
7d522c90 | 33 | #include "solist.h" |
982e9687 | 34 | #include "symtab.h" |
822b6570 | 35 | #include "target-descriptions.h" |
50e8a0d5 | 36 | #include "regset.h" |
d37eb719 | 37 | #include "mips-linux-tdep.h" |
db5f024e | 38 | #include "glibc-tdep.h" |
a5ee0f0c | 39 | #include "linux-tdep.h" |
385203ed | 40 | #include "xml-syscall.h" |
232b8704 | 41 | #include "gdb_signals.h" |
2aa830e4 | 42 | |
032bb6ea YQ |
43 | #include "features/mips-linux.c" |
44 | #include "features/mips-dsp-linux.c" | |
45 | #include "features/mips64-linux.c" | |
46 | #include "features/mips64-dsp-linux.c" | |
47 | ||
7d522c90 DJ |
48 | static struct target_so_ops mips_svr4_so_ops; |
49 | ||
eb14d406 SDJ |
50 | /* This enum represents the signals' numbers on the MIPS |
51 | architecture. It just contains the signal definitions which are | |
52 | different from the generic implementation. | |
53 | ||
54 | It is derived from the file <arch/mips/include/uapi/asm/signal.h>, | |
55 | from the Linux kernel tree. */ | |
56 | ||
57 | enum | |
58 | { | |
59 | MIPS_LINUX_SIGEMT = 7, | |
60 | MIPS_LINUX_SIGBUS = 10, | |
61 | MIPS_LINUX_SIGSYS = 12, | |
62 | MIPS_LINUX_SIGUSR1 = 16, | |
63 | MIPS_LINUX_SIGUSR2 = 17, | |
64 | MIPS_LINUX_SIGCHLD = 18, | |
65 | MIPS_LINUX_SIGCLD = MIPS_LINUX_SIGCHLD, | |
66 | MIPS_LINUX_SIGPWR = 19, | |
67 | MIPS_LINUX_SIGWINCH = 20, | |
68 | MIPS_LINUX_SIGURG = 21, | |
69 | MIPS_LINUX_SIGIO = 22, | |
70 | MIPS_LINUX_SIGPOLL = MIPS_LINUX_SIGIO, | |
71 | MIPS_LINUX_SIGSTOP = 23, | |
72 | MIPS_LINUX_SIGTSTP = 24, | |
73 | MIPS_LINUX_SIGCONT = 25, | |
74 | MIPS_LINUX_SIGTTIN = 26, | |
75 | MIPS_LINUX_SIGTTOU = 27, | |
76 | MIPS_LINUX_SIGVTALRM = 28, | |
77 | MIPS_LINUX_SIGPROF = 29, | |
78 | MIPS_LINUX_SIGXCPU = 30, | |
79 | MIPS_LINUX_SIGXFSZ = 31, | |
80 | ||
81 | MIPS_LINUX_SIGRTMIN = 32, | |
82 | MIPS_LINUX_SIGRT64 = 64, | |
83 | MIPS_LINUX_SIGRTMAX = 127, | |
84 | }; | |
85 | ||
2aa830e4 | 86 | /* Figure out where the longjmp will land. |
295093a4 MS |
87 | We expect the first arg to be a pointer to the jmp_buf structure |
88 | from which we extract the pc (MIPS_LINUX_JB_PC) that we will land | |
89 | at. The pc is copied into PC. This routine returns 1 on | |
90 | success. */ | |
2aa830e4 | 91 | |
19ed69dd KB |
92 | #define MIPS_LINUX_JB_ELEMENT_SIZE 4 |
93 | #define MIPS_LINUX_JB_PC 0 | |
94 | ||
95 | static int | |
60ade65d | 96 | mips_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
2aa830e4 DJ |
97 | { |
98 | CORE_ADDR jb_addr; | |
2eb4d78b | 99 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 100 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
e362b510 | 101 | gdb_byte buf[gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT]; |
2aa830e4 | 102 | |
60ade65d | 103 | jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM); |
2aa830e4 | 104 | |
7d266584 MR |
105 | if (target_read_memory ((jb_addr |
106 | + MIPS_LINUX_JB_PC * MIPS_LINUX_JB_ELEMENT_SIZE), | |
2eb4d78b | 107 | buf, gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT)) |
2aa830e4 DJ |
108 | return 0; |
109 | ||
819844ad | 110 | *pc = extract_unsigned_integer (buf, |
e17a4113 UW |
111 | gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT, |
112 | byte_order); | |
2aa830e4 DJ |
113 | |
114 | return 1; | |
115 | } | |
116 | ||
4246e332 | 117 | /* Transform the bits comprising a 32-bit register to the right size |
23a6d369 AC |
118 | for regcache_raw_supply(). This is needed when mips_isa_regsize() |
119 | is 8. */ | |
96f026fc KB |
120 | |
121 | static void | |
28f5035f | 122 | supply_32bit_reg (struct regcache *regcache, int regnum, const void *addr) |
96f026fc | 123 | { |
b057297a | 124 | regcache->raw_supply_integer (regnum, (const gdb_byte *) addr, 4, true); |
96f026fc KB |
125 | } |
126 | ||
2aa830e4 DJ |
127 | /* Unpack an elf_gregset_t into GDB's register cache. */ |
128 | ||
d37eb719 | 129 | void |
28f5035f UW |
130 | mips_supply_gregset (struct regcache *regcache, |
131 | const mips_elf_gregset_t *gregsetp) | |
2aa830e4 DJ |
132 | { |
133 | int regi; | |
28f5035f | 134 | const mips_elf_greg_t *regp = *gregsetp; |
ac7936df | 135 | struct gdbarch *gdbarch = regcache->arch (); |
bf072999 | 136 | |
822b6570 | 137 | for (regi = EF_REG0 + 1; regi <= EF_REG31; regi++) |
28f5035f | 138 | supply_32bit_reg (regcache, regi - EF_REG0, regp + regi); |
2aa830e4 | 139 | |
2eb4d78b | 140 | if (mips_linux_restart_reg_p (gdbarch)) |
822b6570 DJ |
141 | supply_32bit_reg (regcache, MIPS_RESTART_REGNUM, regp + EF_REG0); |
142 | ||
2eb4d78b UW |
143 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->lo, regp + EF_LO); |
144 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->hi, regp + EF_HI); | |
56cea623 | 145 | |
2eb4d78b | 146 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->pc, |
28f5035f | 147 | regp + EF_CP0_EPC); |
2eb4d78b | 148 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->badvaddr, |
28f5035f UW |
149 | regp + EF_CP0_BADVADDR); |
150 | supply_32bit_reg (regcache, MIPS_PS_REGNUM, regp + EF_CP0_STATUS); | |
2eb4d78b | 151 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->cause, |
28f5035f | 152 | regp + EF_CP0_CAUSE); |
2aa830e4 | 153 | |
1faeff08 | 154 | /* Fill the inaccessible zero register with zero. */ |
27bfc1d1 | 155 | regcache->raw_supply_zeroed (MIPS_ZERO_REGNUM); |
2aa830e4 DJ |
156 | } |
157 | ||
50e8a0d5 HZ |
158 | static void |
159 | mips_supply_gregset_wrapper (const struct regset *regset, | |
7d266584 MR |
160 | struct regcache *regcache, |
161 | int regnum, const void *gregs, size_t len) | |
50e8a0d5 | 162 | { |
1528345d | 163 | gdb_assert (len >= sizeof (mips_elf_gregset_t)); |
50e8a0d5 HZ |
164 | |
165 | mips_supply_gregset (regcache, (const mips_elf_gregset_t *)gregs); | |
166 | } | |
167 | ||
2aa830e4 DJ |
168 | /* Pack our registers (or one register) into an elf_gregset_t. */ |
169 | ||
d37eb719 | 170 | void |
28f5035f UW |
171 | mips_fill_gregset (const struct regcache *regcache, |
172 | mips_elf_gregset_t *gregsetp, int regno) | |
2aa830e4 | 173 | { |
ac7936df | 174 | struct gdbarch *gdbarch = regcache->arch (); |
2aa830e4 | 175 | int regaddr, regi; |
d37eb719 | 176 | mips_elf_greg_t *regp = *gregsetp; |
96f026fc | 177 | void *dst; |
2aa830e4 DJ |
178 | |
179 | if (regno == -1) | |
180 | { | |
d37eb719 | 181 | memset (regp, 0, sizeof (mips_elf_gregset_t)); |
822b6570 | 182 | for (regi = 1; regi < 32; regi++) |
28f5035f | 183 | mips_fill_gregset (regcache, gregsetp, regi); |
2eb4d78b UW |
184 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->lo); |
185 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->hi); | |
186 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->pc); | |
187 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->badvaddr); | |
28f5035f | 188 | mips_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM); |
2eb4d78b | 189 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->cause); |
822b6570 | 190 | mips_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM); |
2aa830e4 DJ |
191 | return; |
192 | } | |
193 | ||
822b6570 | 194 | if (regno > 0 && regno < 32) |
2aa830e4 | 195 | { |
2aa830e4 | 196 | dst = regp + regno + EF_REG0; |
28f5035f | 197 | regcache_raw_collect (regcache, regno, dst); |
2aa830e4 DJ |
198 | return; |
199 | } | |
200 | ||
2eb4d78b UW |
201 | if (regno == mips_regnum (gdbarch)->lo) |
202 | regaddr = EF_LO; | |
203 | else if (regno == mips_regnum (gdbarch)->hi) | |
56cea623 | 204 | regaddr = EF_HI; |
2eb4d78b | 205 | else if (regno == mips_regnum (gdbarch)->pc) |
56cea623 | 206 | regaddr = EF_CP0_EPC; |
2eb4d78b | 207 | else if (regno == mips_regnum (gdbarch)->badvaddr) |
56cea623 | 208 | regaddr = EF_CP0_BADVADDR; |
24e05951 | 209 | else if (regno == MIPS_PS_REGNUM) |
56cea623 | 210 | regaddr = EF_CP0_STATUS; |
2eb4d78b | 211 | else if (regno == mips_regnum (gdbarch)->cause) |
56cea623 | 212 | regaddr = EF_CP0_CAUSE; |
2eb4d78b | 213 | else if (mips_linux_restart_reg_p (gdbarch) |
822b6570 DJ |
214 | && regno == MIPS_RESTART_REGNUM) |
215 | regaddr = EF_REG0; | |
56cea623 AC |
216 | else |
217 | regaddr = -1; | |
2aa830e4 DJ |
218 | |
219 | if (regaddr != -1) | |
220 | { | |
2aa830e4 | 221 | dst = regp + regaddr; |
28f5035f | 222 | regcache_raw_collect (regcache, regno, dst); |
2aa830e4 DJ |
223 | } |
224 | } | |
225 | ||
50e8a0d5 HZ |
226 | static void |
227 | mips_fill_gregset_wrapper (const struct regset *regset, | |
228 | const struct regcache *regcache, | |
229 | int regnum, void *gregs, size_t len) | |
230 | { | |
1528345d | 231 | gdb_assert (len >= sizeof (mips_elf_gregset_t)); |
50e8a0d5 HZ |
232 | |
233 | mips_fill_gregset (regcache, (mips_elf_gregset_t *)gregs, regnum); | |
234 | } | |
235 | ||
2aa830e4 DJ |
236 | /* Likewise, unpack an elf_fpregset_t. */ |
237 | ||
d37eb719 | 238 | void |
28f5035f UW |
239 | mips_supply_fpregset (struct regcache *regcache, |
240 | const mips_elf_fpregset_t *fpregsetp) | |
2aa830e4 | 241 | { |
ac7936df | 242 | struct gdbarch *gdbarch = regcache->arch (); |
52f0bd74 | 243 | int regi; |
2aa830e4 DJ |
244 | |
245 | for (regi = 0; regi < 32; regi++) | |
3e8c568d | 246 | regcache_raw_supply (regcache, |
2eb4d78b | 247 | gdbarch_fp0_regnum (gdbarch) + regi, |
3e8c568d | 248 | *fpregsetp + regi); |
2aa830e4 | 249 | |
28f5035f | 250 | regcache_raw_supply (regcache, |
2eb4d78b | 251 | mips_regnum (gdbarch)->fp_control_status, |
28f5035f | 252 | *fpregsetp + 32); |
2aa830e4 | 253 | |
295093a4 | 254 | /* FIXME: how can we supply FCRIR? The ABI doesn't tell us. */ |
27bfc1d1 AH |
255 | regcache->raw_supply_zeroed |
256 | (mips_regnum (gdbarch)->fp_implementation_revision); | |
2aa830e4 DJ |
257 | } |
258 | ||
50e8a0d5 HZ |
259 | static void |
260 | mips_supply_fpregset_wrapper (const struct regset *regset, | |
7d266584 MR |
261 | struct regcache *regcache, |
262 | int regnum, const void *gregs, size_t len) | |
50e8a0d5 | 263 | { |
1528345d | 264 | gdb_assert (len >= sizeof (mips_elf_fpregset_t)); |
50e8a0d5 HZ |
265 | |
266 | mips_supply_fpregset (regcache, (const mips_elf_fpregset_t *)gregs); | |
267 | } | |
268 | ||
2aa830e4 DJ |
269 | /* Likewise, pack one or all floating point registers into an |
270 | elf_fpregset_t. */ | |
271 | ||
d37eb719 | 272 | void |
28f5035f UW |
273 | mips_fill_fpregset (const struct regcache *regcache, |
274 | mips_elf_fpregset_t *fpregsetp, int regno) | |
2aa830e4 | 275 | { |
ac7936df | 276 | struct gdbarch *gdbarch = regcache->arch (); |
22e048c9 | 277 | char *to; |
2aa830e4 | 278 | |
2eb4d78b UW |
279 | if ((regno >= gdbarch_fp0_regnum (gdbarch)) |
280 | && (regno < gdbarch_fp0_regnum (gdbarch) + 32)) | |
2aa830e4 | 281 | { |
2eb4d78b | 282 | to = (char *) (*fpregsetp + regno - gdbarch_fp0_regnum (gdbarch)); |
28f5035f | 283 | regcache_raw_collect (regcache, regno, to); |
2aa830e4 | 284 | } |
2eb4d78b | 285 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
2aa830e4 | 286 | { |
2aa830e4 | 287 | to = (char *) (*fpregsetp + 32); |
28f5035f | 288 | regcache_raw_collect (regcache, regno, to); |
2aa830e4 DJ |
289 | } |
290 | else if (regno == -1) | |
291 | { | |
292 | int regi; | |
293 | ||
294 | for (regi = 0; regi < 32; regi++) | |
3e8c568d | 295 | mips_fill_fpregset (regcache, fpregsetp, |
2eb4d78b | 296 | gdbarch_fp0_regnum (gdbarch) + regi); |
28f5035f | 297 | mips_fill_fpregset (regcache, fpregsetp, |
2eb4d78b | 298 | mips_regnum (gdbarch)->fp_control_status); |
2aa830e4 DJ |
299 | } |
300 | } | |
301 | ||
50e8a0d5 HZ |
302 | static void |
303 | mips_fill_fpregset_wrapper (const struct regset *regset, | |
304 | const struct regcache *regcache, | |
305 | int regnum, void *gregs, size_t len) | |
306 | { | |
1528345d | 307 | gdb_assert (len >= sizeof (mips_elf_fpregset_t)); |
50e8a0d5 HZ |
308 | |
309 | mips_fill_fpregset (regcache, (mips_elf_fpregset_t *)gregs, regnum); | |
310 | } | |
311 | ||
96f026fc KB |
312 | /* Support for 64-bit ABIs. */ |
313 | ||
96f026fc | 314 | /* Figure out where the longjmp will land. |
295093a4 MS |
315 | We expect the first arg to be a pointer to the jmp_buf structure |
316 | from which we extract the pc (MIPS_LINUX_JB_PC) that we will land | |
317 | at. The pc is copied into PC. This routine returns 1 on | |
318 | success. */ | |
96f026fc KB |
319 | |
320 | /* Details about jmp_buf. */ | |
321 | ||
322 | #define MIPS64_LINUX_JB_PC 0 | |
323 | ||
324 | static int | |
60ade65d | 325 | mips64_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
96f026fc KB |
326 | { |
327 | CORE_ADDR jb_addr; | |
2eb4d78b | 328 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 329 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
709476c3 SM |
330 | gdb_byte *buf |
331 | = (gdb_byte *) alloca (gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT); | |
2eb4d78b | 332 | int element_size = gdbarch_ptr_bit (gdbarch) == 32 ? 4 : 8; |
96f026fc | 333 | |
60ade65d | 334 | jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM); |
96f026fc KB |
335 | |
336 | if (target_read_memory (jb_addr + MIPS64_LINUX_JB_PC * element_size, | |
819844ad | 337 | buf, |
2eb4d78b | 338 | gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT)) |
96f026fc KB |
339 | return 0; |
340 | ||
819844ad | 341 | *pc = extract_unsigned_integer (buf, |
e17a4113 UW |
342 | gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT, |
343 | byte_order); | |
96f026fc KB |
344 | |
345 | return 1; | |
346 | } | |
347 | ||
d37eb719 DJ |
348 | /* Register set support functions. These operate on standard 64-bit |
349 | regsets, but work whether the target is 32-bit or 64-bit. A 32-bit | |
350 | target will still use the 64-bit format for PTRACE_GETREGS. */ | |
351 | ||
352 | /* Supply a 64-bit register. */ | |
96f026fc | 353 | |
63807e1d | 354 | static void |
28f5035f UW |
355 | supply_64bit_reg (struct regcache *regcache, int regnum, |
356 | const gdb_byte *buf) | |
d37eb719 | 357 | { |
ac7936df | 358 | struct gdbarch *gdbarch = regcache->arch (); |
2eb4d78b UW |
359 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
360 | && register_size (gdbarch, regnum) == 4) | |
28f5035f | 361 | regcache_raw_supply (regcache, regnum, buf + 4); |
d37eb719 | 362 | else |
28f5035f | 363 | regcache_raw_supply (regcache, regnum, buf); |
d37eb719 DJ |
364 | } |
365 | ||
366 | /* Unpack a 64-bit elf_gregset_t into GDB's register cache. */ | |
367 | ||
368 | void | |
28f5035f UW |
369 | mips64_supply_gregset (struct regcache *regcache, |
370 | const mips64_elf_gregset_t *gregsetp) | |
96f026fc KB |
371 | { |
372 | int regi; | |
28f5035f | 373 | const mips64_elf_greg_t *regp = *gregsetp; |
ac7936df | 374 | struct gdbarch *gdbarch = regcache->arch (); |
96f026fc | 375 | |
822b6570 | 376 | for (regi = MIPS64_EF_REG0 + 1; regi <= MIPS64_EF_REG31; regi++) |
28f5035f | 377 | supply_64bit_reg (regcache, regi - MIPS64_EF_REG0, |
7d266584 | 378 | (const gdb_byte *) (regp + regi)); |
28f5035f | 379 | |
2eb4d78b | 380 | if (mips_linux_restart_reg_p (gdbarch)) |
822b6570 | 381 | supply_64bit_reg (regcache, MIPS_RESTART_REGNUM, |
7d266584 | 382 | (const gdb_byte *) (regp + MIPS64_EF_REG0)); |
822b6570 | 383 | |
2eb4d78b | 384 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->lo, |
28f5035f | 385 | (const gdb_byte *) (regp + MIPS64_EF_LO)); |
2eb4d78b | 386 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->hi, |
28f5035f UW |
387 | (const gdb_byte *) (regp + MIPS64_EF_HI)); |
388 | ||
2eb4d78b | 389 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->pc, |
28f5035f | 390 | (const gdb_byte *) (regp + MIPS64_EF_CP0_EPC)); |
2eb4d78b | 391 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->badvaddr, |
28f5035f UW |
392 | (const gdb_byte *) (regp + MIPS64_EF_CP0_BADVADDR)); |
393 | supply_64bit_reg (regcache, MIPS_PS_REGNUM, | |
394 | (const gdb_byte *) (regp + MIPS64_EF_CP0_STATUS)); | |
2eb4d78b | 395 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->cause, |
28f5035f | 396 | (const gdb_byte *) (regp + MIPS64_EF_CP0_CAUSE)); |
96f026fc | 397 | |
1faeff08 | 398 | /* Fill the inaccessible zero register with zero. */ |
27bfc1d1 | 399 | regcache->raw_supply_zeroed (MIPS_ZERO_REGNUM); |
96f026fc KB |
400 | } |
401 | ||
50e8a0d5 HZ |
402 | static void |
403 | mips64_supply_gregset_wrapper (const struct regset *regset, | |
7d266584 MR |
404 | struct regcache *regcache, |
405 | int regnum, const void *gregs, size_t len) | |
50e8a0d5 | 406 | { |
1528345d | 407 | gdb_assert (len >= sizeof (mips64_elf_gregset_t)); |
50e8a0d5 HZ |
408 | |
409 | mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *)gregs); | |
410 | } | |
411 | ||
d37eb719 | 412 | /* Pack our registers (or one register) into a 64-bit elf_gregset_t. */ |
96f026fc | 413 | |
d37eb719 | 414 | void |
28f5035f UW |
415 | mips64_fill_gregset (const struct regcache *regcache, |
416 | mips64_elf_gregset_t *gregsetp, int regno) | |
96f026fc | 417 | { |
ac7936df | 418 | struct gdbarch *gdbarch = regcache->arch (); |
96f026fc KB |
419 | int regaddr, regi; |
420 | mips64_elf_greg_t *regp = *gregsetp; | |
2ba93934 | 421 | void *dst; |
96f026fc KB |
422 | |
423 | if (regno == -1) | |
424 | { | |
425 | memset (regp, 0, sizeof (mips64_elf_gregset_t)); | |
822b6570 | 426 | for (regi = 1; regi < 32; regi++) |
7d266584 | 427 | mips64_fill_gregset (regcache, gregsetp, regi); |
2eb4d78b UW |
428 | mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->lo); |
429 | mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->hi); | |
430 | mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->pc); | |
025bb325 MS |
431 | mips64_fill_gregset (regcache, gregsetp, |
432 | mips_regnum (gdbarch)->badvaddr); | |
28f5035f | 433 | mips64_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM); |
2eb4d78b | 434 | mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->cause); |
822b6570 | 435 | mips64_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM); |
96f026fc KB |
436 | return; |
437 | } | |
438 | ||
822b6570 | 439 | if (regno > 0 && regno < 32) |
d37eb719 | 440 | regaddr = regno + MIPS64_EF_REG0; |
2eb4d78b | 441 | else if (regno == mips_regnum (gdbarch)->lo) |
56cea623 | 442 | regaddr = MIPS64_EF_LO; |
2eb4d78b | 443 | else if (regno == mips_regnum (gdbarch)->hi) |
56cea623 | 444 | regaddr = MIPS64_EF_HI; |
2eb4d78b | 445 | else if (regno == mips_regnum (gdbarch)->pc) |
56cea623 | 446 | regaddr = MIPS64_EF_CP0_EPC; |
2eb4d78b | 447 | else if (regno == mips_regnum (gdbarch)->badvaddr) |
56cea623 | 448 | regaddr = MIPS64_EF_CP0_BADVADDR; |
24e05951 | 449 | else if (regno == MIPS_PS_REGNUM) |
56cea623 | 450 | regaddr = MIPS64_EF_CP0_STATUS; |
2eb4d78b | 451 | else if (regno == mips_regnum (gdbarch)->cause) |
56cea623 | 452 | regaddr = MIPS64_EF_CP0_CAUSE; |
2eb4d78b | 453 | else if (mips_linux_restart_reg_p (gdbarch) |
822b6570 DJ |
454 | && regno == MIPS_RESTART_REGNUM) |
455 | regaddr = MIPS64_EF_REG0; | |
56cea623 AC |
456 | else |
457 | regaddr = -1; | |
96f026fc KB |
458 | |
459 | if (regaddr != -1) | |
460 | { | |
461 | dst = regp + regaddr; | |
b057297a | 462 | regcache->raw_collect_integer (regno, (gdb_byte *) dst, 8, true); |
96f026fc KB |
463 | } |
464 | } | |
465 | ||
50e8a0d5 HZ |
466 | static void |
467 | mips64_fill_gregset_wrapper (const struct regset *regset, | |
468 | const struct regcache *regcache, | |
469 | int regnum, void *gregs, size_t len) | |
470 | { | |
1528345d | 471 | gdb_assert (len >= sizeof (mips64_elf_gregset_t)); |
50e8a0d5 HZ |
472 | |
473 | mips64_fill_gregset (regcache, (mips64_elf_gregset_t *)gregs, regnum); | |
474 | } | |
475 | ||
96f026fc KB |
476 | /* Likewise, unpack an elf_fpregset_t. */ |
477 | ||
d37eb719 | 478 | void |
28f5035f UW |
479 | mips64_supply_fpregset (struct regcache *regcache, |
480 | const mips64_elf_fpregset_t *fpregsetp) | |
96f026fc | 481 | { |
ac7936df | 482 | struct gdbarch *gdbarch = regcache->arch (); |
52f0bd74 | 483 | int regi; |
96f026fc | 484 | |
d37eb719 DJ |
485 | /* See mips_linux_o32_sigframe_init for a description of the |
486 | peculiar FP register layout. */ | |
2eb4d78b | 487 | if (register_size (gdbarch, gdbarch_fp0_regnum (gdbarch)) == 4) |
d37eb719 DJ |
488 | for (regi = 0; regi < 32; regi++) |
489 | { | |
7d266584 MR |
490 | const gdb_byte *reg_ptr |
491 | = (const gdb_byte *) (*fpregsetp + (regi & ~1)); | |
2eb4d78b | 492 | if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (regi & 1)) |
d37eb719 | 493 | reg_ptr += 4; |
3e8c568d | 494 | regcache_raw_supply (regcache, |
2eb4d78b | 495 | gdbarch_fp0_regnum (gdbarch) + regi, |
3e8c568d | 496 | reg_ptr); |
d37eb719 DJ |
497 | } |
498 | else | |
499 | for (regi = 0; regi < 32; regi++) | |
3e8c568d | 500 | regcache_raw_supply (regcache, |
2eb4d78b | 501 | gdbarch_fp0_regnum (gdbarch) + regi, |
7d266584 | 502 | (const char *) (*fpregsetp + regi)); |
d37eb719 | 503 | |
2eb4d78b | 504 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->fp_control_status, |
7d266584 | 505 | (const gdb_byte *) (*fpregsetp + 32)); |
d37eb719 DJ |
506 | |
507 | /* The ABI doesn't tell us how to supply FCRIR, and core dumps don't | |
508 | include it - but the result of PTRACE_GETFPREGS does. The best we | |
509 | can do is to assume that its value is present. */ | |
28f5035f | 510 | supply_32bit_reg (regcache, |
2eb4d78b | 511 | mips_regnum (gdbarch)->fp_implementation_revision, |
7d266584 | 512 | (const gdb_byte *) (*fpregsetp + 32) + 4); |
96f026fc KB |
513 | } |
514 | ||
50e8a0d5 HZ |
515 | static void |
516 | mips64_supply_fpregset_wrapper (const struct regset *regset, | |
7d266584 MR |
517 | struct regcache *regcache, |
518 | int regnum, const void *gregs, size_t len) | |
50e8a0d5 | 519 | { |
1528345d | 520 | gdb_assert (len >= sizeof (mips64_elf_fpregset_t)); |
50e8a0d5 HZ |
521 | |
522 | mips64_supply_fpregset (regcache, (const mips64_elf_fpregset_t *)gregs); | |
523 | } | |
524 | ||
96f026fc KB |
525 | /* Likewise, pack one or all floating point registers into an |
526 | elf_fpregset_t. */ | |
527 | ||
d37eb719 | 528 | void |
28f5035f UW |
529 | mips64_fill_fpregset (const struct regcache *regcache, |
530 | mips64_elf_fpregset_t *fpregsetp, int regno) | |
96f026fc | 531 | { |
ac7936df | 532 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 533 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d37eb719 | 534 | gdb_byte *to; |
96f026fc | 535 | |
2eb4d78b UW |
536 | if ((regno >= gdbarch_fp0_regnum (gdbarch)) |
537 | && (regno < gdbarch_fp0_regnum (gdbarch) + 32)) | |
96f026fc | 538 | { |
d37eb719 DJ |
539 | /* See mips_linux_o32_sigframe_init for a description of the |
540 | peculiar FP register layout. */ | |
2eb4d78b | 541 | if (register_size (gdbarch, regno) == 4) |
d37eb719 | 542 | { |
2eb4d78b | 543 | int regi = regno - gdbarch_fp0_regnum (gdbarch); |
d37eb719 DJ |
544 | |
545 | to = (gdb_byte *) (*fpregsetp + (regi & ~1)); | |
2eb4d78b | 546 | if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (regi & 1)) |
d37eb719 | 547 | to += 4; |
28f5035f | 548 | regcache_raw_collect (regcache, regno, to); |
d37eb719 DJ |
549 | } |
550 | else | |
551 | { | |
025bb325 MS |
552 | to = (gdb_byte *) (*fpregsetp + regno |
553 | - gdbarch_fp0_regnum (gdbarch)); | |
28f5035f | 554 | regcache_raw_collect (regcache, regno, to); |
d37eb719 | 555 | } |
96f026fc | 556 | } |
2eb4d78b | 557 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
96f026fc | 558 | { |
d37eb719 | 559 | to = (gdb_byte *) (*fpregsetp + 32); |
b057297a | 560 | regcache->raw_collect_integer (regno, to, 4, true); |
d37eb719 | 561 | } |
2eb4d78b | 562 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
d37eb719 | 563 | { |
d37eb719 | 564 | to = (gdb_byte *) (*fpregsetp + 32) + 4; |
b057297a | 565 | regcache->raw_collect_integer (regno, to, 4, true); |
96f026fc KB |
566 | } |
567 | else if (regno == -1) | |
568 | { | |
569 | int regi; | |
570 | ||
571 | for (regi = 0; regi < 32; regi++) | |
3e8c568d | 572 | mips64_fill_fpregset (regcache, fpregsetp, |
2eb4d78b | 573 | gdbarch_fp0_regnum (gdbarch) + regi); |
28f5035f | 574 | mips64_fill_fpregset (regcache, fpregsetp, |
2eb4d78b | 575 | mips_regnum (gdbarch)->fp_control_status); |
28f5035f | 576 | mips64_fill_fpregset (regcache, fpregsetp, |
7d266584 | 577 | mips_regnum (gdbarch)->fp_implementation_revision); |
96f026fc KB |
578 | } |
579 | } | |
580 | ||
50e8a0d5 HZ |
581 | static void |
582 | mips64_fill_fpregset_wrapper (const struct regset *regset, | |
583 | const struct regcache *regcache, | |
584 | int regnum, void *gregs, size_t len) | |
585 | { | |
1528345d | 586 | gdb_assert (len >= sizeof (mips64_elf_fpregset_t)); |
96f026fc | 587 | |
50e8a0d5 HZ |
588 | mips64_fill_fpregset (regcache, (mips64_elf_fpregset_t *)gregs, regnum); |
589 | } | |
2aa830e4 | 590 | |
b7195f27 AA |
591 | static const struct regset mips_linux_gregset = |
592 | { | |
593 | NULL, mips_supply_gregset_wrapper, mips_fill_gregset_wrapper | |
594 | }; | |
595 | ||
596 | static const struct regset mips64_linux_gregset = | |
597 | { | |
598 | NULL, mips64_supply_gregset_wrapper, mips64_fill_gregset_wrapper | |
599 | }; | |
600 | ||
601 | static const struct regset mips_linux_fpregset = | |
602 | { | |
603 | NULL, mips_supply_fpregset_wrapper, mips_fill_fpregset_wrapper | |
604 | }; | |
605 | ||
606 | static const struct regset mips64_linux_fpregset = | |
607 | { | |
608 | NULL, mips64_supply_fpregset_wrapper, mips64_fill_fpregset_wrapper | |
609 | }; | |
610 | ||
d4036235 AA |
611 | static void |
612 | mips_linux_iterate_over_regset_sections (struct gdbarch *gdbarch, | |
613 | iterate_over_regset_sections_cb *cb, | |
614 | void *cb_data, | |
615 | const struct regcache *regcache) | |
2aa830e4 | 616 | { |
d4036235 | 617 | if (register_size (gdbarch, MIPS_ZERO_REGNUM) == 4) |
2aa830e4 | 618 | { |
d4036235 AA |
619 | cb (".reg", sizeof (mips_elf_gregset_t), &mips_linux_gregset, |
620 | NULL, cb_data); | |
621 | cb (".reg2", sizeof (mips_elf_fpregset_t), &mips_linux_fpregset, | |
622 | NULL, cb_data); | |
2aa830e4 | 623 | } |
d4036235 | 624 | else |
2aa830e4 | 625 | { |
d4036235 AA |
626 | cb (".reg", sizeof (mips64_elf_gregset_t), &mips64_linux_gregset, |
627 | NULL, cb_data); | |
628 | cb (".reg2", sizeof (mips64_elf_fpregset_t), &mips64_linux_fpregset, | |
629 | NULL, cb_data); | |
2aa830e4 | 630 | } |
50e8a0d5 | 631 | } |
2aa830e4 | 632 | |
4eb0ad19 DJ |
633 | static const struct target_desc * |
634 | mips_linux_core_read_description (struct gdbarch *gdbarch, | |
635 | struct target_ops *target, | |
636 | bfd *abfd) | |
637 | { | |
638 | asection *section = bfd_get_section_by_name (abfd, ".reg"); | |
639 | if (! section) | |
640 | return NULL; | |
641 | ||
642 | switch (bfd_section_size (abfd, section)) | |
643 | { | |
644 | case sizeof (mips_elf_gregset_t): | |
645 | return mips_tdesc_gp32; | |
646 | ||
647 | case sizeof (mips64_elf_gregset_t): | |
648 | return mips_tdesc_gp64; | |
649 | ||
650 | default: | |
651 | return NULL; | |
652 | } | |
653 | } | |
654 | ||
96f026fc | 655 | |
295093a4 | 656 | /* Check the code at PC for a dynamic linker lazy resolution stub. |
3e5d3a5a MR |
657 | GNU ld for MIPS has put lazy resolution stubs into a ".MIPS.stubs" |
658 | section uniformly since version 2.15. If the pc is in that section, | |
659 | then we are in such a stub. Before that ".stub" was used in 32-bit | |
660 | ELF binaries, however we do not bother checking for that since we | |
661 | have never had and that case should be extremely rare these days. | |
662 | Instead we pattern-match on the code generated by GNU ld. They look | |
663 | like this: | |
6de918a6 DJ |
664 | |
665 | lw t9,0x8010(gp) | |
666 | addu t7,ra | |
667 | jalr t9,ra | |
668 | addiu t8,zero,INDEX | |
669 | ||
3e5d3a5a MR |
670 | (with the appropriate doubleword instructions for N64). As any lazy |
671 | resolution stubs in microMIPS binaries will always be in a | |
672 | ".MIPS.stubs" section we only ever verify standard MIPS patterns. */ | |
6de918a6 DJ |
673 | |
674 | static int | |
3e5d3a5a | 675 | mips_linux_in_dynsym_stub (CORE_ADDR pc) |
6de918a6 | 676 | { |
e362b510 | 677 | gdb_byte buf[28], *p; |
6de918a6 | 678 | ULONGEST insn, insn1; |
f5656ead TT |
679 | int n64 = (mips_abi (target_gdbarch ()) == MIPS_ABI_N64); |
680 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); | |
6de918a6 | 681 | |
3e5d3a5a MR |
682 | if (in_mips_stubs_section (pc)) |
683 | return 1; | |
684 | ||
6de918a6 DJ |
685 | read_memory (pc - 12, buf, 28); |
686 | ||
687 | if (n64) | |
688 | { | |
689 | /* ld t9,0x8010(gp) */ | |
690 | insn1 = 0xdf998010; | |
691 | } | |
692 | else | |
693 | { | |
694 | /* lw t9,0x8010(gp) */ | |
695 | insn1 = 0x8f998010; | |
696 | } | |
697 | ||
698 | p = buf + 12; | |
699 | while (p >= buf) | |
700 | { | |
e17a4113 | 701 | insn = extract_unsigned_integer (p, 4, byte_order); |
6de918a6 DJ |
702 | if (insn == insn1) |
703 | break; | |
704 | p -= 4; | |
705 | } | |
706 | if (p < buf) | |
707 | return 0; | |
708 | ||
e17a4113 | 709 | insn = extract_unsigned_integer (p + 4, 4, byte_order); |
6de918a6 DJ |
710 | if (n64) |
711 | { | |
93084fcd SD |
712 | /* 'daddu t7,ra' or 'or t7, ra, zero'*/ |
713 | if (insn != 0x03e0782d || insn != 0x03e07825) | |
6de918a6 | 714 | return 0; |
93084fcd | 715 | |
6de918a6 DJ |
716 | } |
717 | else | |
718 | { | |
93084fcd SD |
719 | /* 'addu t7,ra' or 'or t7, ra, zero'*/ |
720 | if (insn != 0x03e07821 || insn != 0x03e07825) | |
6de918a6 | 721 | return 0; |
93084fcd | 722 | |
6de918a6 | 723 | } |
295093a4 | 724 | |
e17a4113 | 725 | insn = extract_unsigned_integer (p + 8, 4, byte_order); |
6de918a6 DJ |
726 | /* jalr t9,ra */ |
727 | if (insn != 0x0320f809) | |
728 | return 0; | |
729 | ||
e17a4113 | 730 | insn = extract_unsigned_integer (p + 12, 4, byte_order); |
6de918a6 DJ |
731 | if (n64) |
732 | { | |
733 | /* daddiu t8,zero,0 */ | |
734 | if ((insn & 0xffff0000) != 0x64180000) | |
735 | return 0; | |
736 | } | |
737 | else | |
738 | { | |
739 | /* addiu t8,zero,0 */ | |
740 | if ((insn & 0xffff0000) != 0x24180000) | |
741 | return 0; | |
742 | } | |
743 | ||
3e5d3a5a | 744 | return 1; |
6de918a6 DJ |
745 | } |
746 | ||
295093a4 | 747 | /* Return non-zero iff PC belongs to the dynamic linker resolution |
db5f024e | 748 | code, a PLT entry, or a lazy binding stub. */ |
6de918a6 | 749 | |
7d522c90 | 750 | static int |
6de918a6 DJ |
751 | mips_linux_in_dynsym_resolve_code (CORE_ADDR pc) |
752 | { | |
295093a4 | 753 | /* Check whether PC is in the dynamic linker. This also checks |
db5f024e | 754 | whether it is in the .plt section, used by non-PIC executables. */ |
7d522c90 | 755 | if (svr4_in_dynsym_resolve_code (pc)) |
6de918a6 DJ |
756 | return 1; |
757 | ||
3e5d3a5a MR |
758 | /* Likewise for the stubs. They live in the .MIPS.stubs section these |
759 | days, so we check if the PC is within, than fall back to a pattern | |
760 | match. */ | |
761 | if (mips_linux_in_dynsym_stub (pc)) | |
6de918a6 DJ |
762 | return 1; |
763 | ||
764 | return 0; | |
765 | } | |
766 | ||
767 | /* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c, | |
768 | and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc | |
769 | implementation of this triggers at "fixup" from the same objfile as | |
c4c5b7ba | 770 | "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at |
db5f024e DJ |
771 | "__dl_runtime_resolve" directly. An unresolved lazy binding |
772 | stub will point to _dl_runtime_resolve, which will first call | |
c4c5b7ba AC |
773 | __dl_runtime_resolve, and then pass control to the resolved |
774 | function. */ | |
6de918a6 DJ |
775 | |
776 | static CORE_ADDR | |
777 | mips_linux_skip_resolver (struct gdbarch *gdbarch, CORE_ADDR pc) | |
778 | { | |
3b7344d5 | 779 | struct bound_minimal_symbol resolver; |
6de918a6 DJ |
780 | |
781 | resolver = lookup_minimal_symbol ("__dl_runtime_resolve", NULL, NULL); | |
782 | ||
77e371c0 | 783 | if (resolver.minsym && BMSYMBOL_VALUE_ADDRESS (resolver) == pc) |
c7ce8faa | 784 | return frame_unwind_caller_pc (get_current_frame ()); |
6de918a6 | 785 | |
db5f024e | 786 | return glibc_skip_solib_resolver (gdbarch, pc); |
295093a4 | 787 | } |
6de918a6 | 788 | |
5792a79b DJ |
789 | /* Signal trampoline support. There are four supported layouts for a |
790 | signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and | |
791 | n64 rt_sigframe. We handle them all independently; not the most | |
792 | efficient way, but simplest. First, declare all the unwinders. */ | |
793 | ||
794 | static void mips_linux_o32_sigframe_init (const struct tramp_frame *self, | |
b8a22b94 | 795 | struct frame_info *this_frame, |
5792a79b DJ |
796 | struct trad_frame_cache *this_cache, |
797 | CORE_ADDR func); | |
798 | ||
799 | static void mips_linux_n32n64_sigframe_init (const struct tramp_frame *self, | |
b8a22b94 | 800 | struct frame_info *this_frame, |
5792a79b DJ |
801 | struct trad_frame_cache *this_cache, |
802 | CORE_ADDR func); | |
803 | ||
858339f2 MR |
804 | static int mips_linux_sigframe_validate (const struct tramp_frame *self, |
805 | struct frame_info *this_frame, | |
806 | CORE_ADDR *pc); | |
807 | ||
808 | static int micromips_linux_sigframe_validate (const struct tramp_frame *self, | |
809 | struct frame_info *this_frame, | |
810 | CORE_ADDR *pc); | |
811 | ||
5792a79b DJ |
812 | #define MIPS_NR_LINUX 4000 |
813 | #define MIPS_NR_N64_LINUX 5000 | |
814 | #define MIPS_NR_N32_LINUX 6000 | |
815 | ||
816 | #define MIPS_NR_sigreturn MIPS_NR_LINUX + 119 | |
817 | #define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193 | |
818 | #define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211 | |
819 | #define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211 | |
820 | ||
821 | #define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn | |
822 | #define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn | |
823 | #define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn | |
824 | #define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn | |
825 | #define MIPS_INST_SYSCALL 0x0000000c | |
826 | ||
858339f2 MR |
827 | #define MICROMIPS_INST_LI_V0 0x3040 |
828 | #define MICROMIPS_INST_POOL32A 0x0000 | |
829 | #define MICROMIPS_INST_SYSCALL 0x8b7c | |
830 | ||
2cd8546d AC |
831 | static const struct tramp_frame mips_linux_o32_sigframe = { |
832 | SIGTRAMP_FRAME, | |
5792a79b | 833 | 4, |
2cd8546d AC |
834 | { |
835 | { MIPS_INST_LI_V0_SIGRETURN, -1 }, | |
836 | { MIPS_INST_SYSCALL, -1 }, | |
837 | { TRAMP_SENTINEL_INSN, -1 } | |
838 | }, | |
858339f2 MR |
839 | mips_linux_o32_sigframe_init, |
840 | mips_linux_sigframe_validate | |
5792a79b DJ |
841 | }; |
842 | ||
2cd8546d AC |
843 | static const struct tramp_frame mips_linux_o32_rt_sigframe = { |
844 | SIGTRAMP_FRAME, | |
5792a79b | 845 | 4, |
2cd8546d AC |
846 | { |
847 | { MIPS_INST_LI_V0_RT_SIGRETURN, -1 }, | |
848 | { MIPS_INST_SYSCALL, -1 }, | |
849 | { TRAMP_SENTINEL_INSN, -1 } }, | |
858339f2 MR |
850 | mips_linux_o32_sigframe_init, |
851 | mips_linux_sigframe_validate | |
5792a79b DJ |
852 | }; |
853 | ||
2cd8546d AC |
854 | static const struct tramp_frame mips_linux_n32_rt_sigframe = { |
855 | SIGTRAMP_FRAME, | |
5792a79b | 856 | 4, |
2cd8546d AC |
857 | { |
858 | { MIPS_INST_LI_V0_N32_RT_SIGRETURN, -1 }, | |
859 | { MIPS_INST_SYSCALL, -1 }, | |
860 | { TRAMP_SENTINEL_INSN, -1 } | |
861 | }, | |
858339f2 MR |
862 | mips_linux_n32n64_sigframe_init, |
863 | mips_linux_sigframe_validate | |
5792a79b DJ |
864 | }; |
865 | ||
2cd8546d AC |
866 | static const struct tramp_frame mips_linux_n64_rt_sigframe = { |
867 | SIGTRAMP_FRAME, | |
5792a79b | 868 | 4, |
fcbd8a5c TS |
869 | { |
870 | { MIPS_INST_LI_V0_N64_RT_SIGRETURN, -1 }, | |
871 | { MIPS_INST_SYSCALL, -1 }, | |
872 | { TRAMP_SENTINEL_INSN, -1 } | |
873 | }, | |
858339f2 MR |
874 | mips_linux_n32n64_sigframe_init, |
875 | mips_linux_sigframe_validate | |
876 | }; | |
877 | ||
878 | static const struct tramp_frame micromips_linux_o32_sigframe = { | |
879 | SIGTRAMP_FRAME, | |
880 | 2, | |
881 | { | |
882 | { MICROMIPS_INST_LI_V0, -1 }, | |
883 | { MIPS_NR_sigreturn, -1 }, | |
884 | { MICROMIPS_INST_POOL32A, -1 }, | |
885 | { MICROMIPS_INST_SYSCALL, -1 }, | |
886 | { TRAMP_SENTINEL_INSN, -1 } | |
887 | }, | |
888 | mips_linux_o32_sigframe_init, | |
889 | micromips_linux_sigframe_validate | |
890 | }; | |
891 | ||
892 | static const struct tramp_frame micromips_linux_o32_rt_sigframe = { | |
893 | SIGTRAMP_FRAME, | |
894 | 2, | |
895 | { | |
896 | { MICROMIPS_INST_LI_V0, -1 }, | |
897 | { MIPS_NR_rt_sigreturn, -1 }, | |
898 | { MICROMIPS_INST_POOL32A, -1 }, | |
899 | { MICROMIPS_INST_SYSCALL, -1 }, | |
900 | { TRAMP_SENTINEL_INSN, -1 } | |
901 | }, | |
902 | mips_linux_o32_sigframe_init, | |
903 | micromips_linux_sigframe_validate | |
904 | }; | |
905 | ||
906 | static const struct tramp_frame micromips_linux_n32_rt_sigframe = { | |
907 | SIGTRAMP_FRAME, | |
908 | 2, | |
909 | { | |
910 | { MICROMIPS_INST_LI_V0, -1 }, | |
911 | { MIPS_NR_N32_rt_sigreturn, -1 }, | |
912 | { MICROMIPS_INST_POOL32A, -1 }, | |
913 | { MICROMIPS_INST_SYSCALL, -1 }, | |
914 | { TRAMP_SENTINEL_INSN, -1 } | |
915 | }, | |
916 | mips_linux_n32n64_sigframe_init, | |
917 | micromips_linux_sigframe_validate | |
918 | }; | |
919 | ||
920 | static const struct tramp_frame micromips_linux_n64_rt_sigframe = { | |
921 | SIGTRAMP_FRAME, | |
922 | 2, | |
923 | { | |
924 | { MICROMIPS_INST_LI_V0, -1 }, | |
925 | { MIPS_NR_N64_rt_sigreturn, -1 }, | |
926 | { MICROMIPS_INST_POOL32A, -1 }, | |
927 | { MICROMIPS_INST_SYSCALL, -1 }, | |
928 | { TRAMP_SENTINEL_INSN, -1 } | |
929 | }, | |
930 | mips_linux_n32n64_sigframe_init, | |
931 | micromips_linux_sigframe_validate | |
5792a79b DJ |
932 | }; |
933 | ||
934 | /* *INDENT-OFF* */ | |
935 | /* The unwinder for o32 signal frames. The legacy structures look | |
936 | like this: | |
937 | ||
938 | struct sigframe { | |
939 | u32 sf_ass[4]; [argument save space for o32] | |
eb195664 | 940 | u32 sf_code[2]; [signal trampoline or fill] |
5792a79b DJ |
941 | struct sigcontext sf_sc; |
942 | sigset_t sf_mask; | |
943 | }; | |
944 | ||
d0e64392 MR |
945 | Pre-2.6.12 sigcontext: |
946 | ||
5792a79b DJ |
947 | struct sigcontext { |
948 | unsigned int sc_regmask; [Unused] | |
949 | unsigned int sc_status; | |
950 | unsigned long long sc_pc; | |
951 | unsigned long long sc_regs[32]; | |
952 | unsigned long long sc_fpregs[32]; | |
953 | unsigned int sc_ownedfp; | |
954 | unsigned int sc_fpc_csr; | |
955 | unsigned int sc_fpc_eir; [Unused] | |
956 | unsigned int sc_used_math; | |
957 | unsigned int sc_ssflags; [Unused] | |
958 | [Alignment hole of four bytes] | |
959 | unsigned long long sc_mdhi; | |
960 | unsigned long long sc_mdlo; | |
961 | ||
962 | unsigned int sc_cause; [Unused] | |
963 | unsigned int sc_badvaddr; [Unused] | |
964 | ||
965 | unsigned long sc_sigset[4]; [kernel's sigset_t] | |
966 | }; | |
967 | ||
d0e64392 MR |
968 | Post-2.6.12 sigcontext (SmartMIPS/DSP support added): |
969 | ||
970 | struct sigcontext { | |
971 | unsigned int sc_regmask; [Unused] | |
972 | unsigned int sc_status; [Unused] | |
973 | unsigned long long sc_pc; | |
974 | unsigned long long sc_regs[32]; | |
975 | unsigned long long sc_fpregs[32]; | |
976 | unsigned int sc_acx; | |
977 | unsigned int sc_fpc_csr; | |
978 | unsigned int sc_fpc_eir; [Unused] | |
979 | unsigned int sc_used_math; | |
980 | unsigned int sc_dsp; | |
981 | [Alignment hole of four bytes] | |
982 | unsigned long long sc_mdhi; | |
983 | unsigned long long sc_mdlo; | |
984 | unsigned long sc_hi1; | |
985 | unsigned long sc_lo1; | |
986 | unsigned long sc_hi2; | |
987 | unsigned long sc_lo2; | |
988 | unsigned long sc_hi3; | |
989 | unsigned long sc_lo3; | |
990 | }; | |
991 | ||
5792a79b DJ |
992 | The RT signal frames look like this: |
993 | ||
994 | struct rt_sigframe { | |
995 | u32 rs_ass[4]; [argument save space for o32] | |
eb195664 | 996 | u32 rs_code[2] [signal trampoline or fill] |
5792a79b DJ |
997 | struct siginfo rs_info; |
998 | struct ucontext rs_uc; | |
999 | }; | |
1000 | ||
1001 | struct ucontext { | |
1002 | unsigned long uc_flags; | |
1003 | struct ucontext *uc_link; | |
1004 | stack_t uc_stack; | |
1005 | [Alignment hole of four bytes] | |
1006 | struct sigcontext uc_mcontext; | |
1007 | sigset_t uc_sigmask; | |
1008 | }; */ | |
1009 | /* *INDENT-ON* */ | |
1010 | ||
5792a79b DJ |
1011 | #define SIGFRAME_SIGCONTEXT_OFFSET (6 * 4) |
1012 | ||
1013 | #define RTSIGFRAME_SIGINFO_SIZE 128 | |
1014 | #define STACK_T_SIZE (3 * 4) | |
1015 | #define UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + STACK_T_SIZE + 4) | |
1016 | #define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ | |
1017 | + RTSIGFRAME_SIGINFO_SIZE \ | |
1018 | + UCONTEXT_SIGCONTEXT_OFFSET) | |
1019 | ||
1020 | #define SIGCONTEXT_PC (1 * 8) | |
1021 | #define SIGCONTEXT_REGS (2 * 8) | |
1022 | #define SIGCONTEXT_FPREGS (34 * 8) | |
1023 | #define SIGCONTEXT_FPCSR (66 * 8 + 4) | |
d0e64392 | 1024 | #define SIGCONTEXT_DSPCTL (68 * 8 + 0) |
5792a79b DJ |
1025 | #define SIGCONTEXT_HI (69 * 8) |
1026 | #define SIGCONTEXT_LO (70 * 8) | |
1027 | #define SIGCONTEXT_CAUSE (71 * 8 + 0) | |
1028 | #define SIGCONTEXT_BADVADDR (71 * 8 + 4) | |
d0e64392 MR |
1029 | #define SIGCONTEXT_HI1 (71 * 8 + 0) |
1030 | #define SIGCONTEXT_LO1 (71 * 8 + 4) | |
1031 | #define SIGCONTEXT_HI2 (72 * 8 + 0) | |
1032 | #define SIGCONTEXT_LO2 (72 * 8 + 4) | |
1033 | #define SIGCONTEXT_HI3 (73 * 8 + 0) | |
1034 | #define SIGCONTEXT_LO3 (73 * 8 + 4) | |
5792a79b DJ |
1035 | |
1036 | #define SIGCONTEXT_REG_SIZE 8 | |
1037 | ||
1038 | static void | |
1039 | mips_linux_o32_sigframe_init (const struct tramp_frame *self, | |
b8a22b94 | 1040 | struct frame_info *this_frame, |
5792a79b DJ |
1041 | struct trad_frame_cache *this_cache, |
1042 | CORE_ADDR func) | |
1043 | { | |
b8a22b94 | 1044 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
22e048c9 | 1045 | int ireg; |
eb195664 DD |
1046 | CORE_ADDR frame_sp = get_frame_sp (this_frame); |
1047 | CORE_ADDR sigcontext_base; | |
2eb4d78b | 1048 | const struct mips_regnum *regs = mips_regnum (gdbarch); |
37c4d197 | 1049 | CORE_ADDR regs_base; |
5792a79b | 1050 | |
858339f2 MR |
1051 | if (self == &mips_linux_o32_sigframe |
1052 | || self == µmips_linux_o32_sigframe) | |
eb195664 | 1053 | sigcontext_base = frame_sp + SIGFRAME_SIGCONTEXT_OFFSET; |
5792a79b | 1054 | else |
eb195664 | 1055 | sigcontext_base = frame_sp + RTSIGFRAME_SIGCONTEXT_OFFSET; |
295093a4 MS |
1056 | |
1057 | /* I'm not proud of this hack. Eventually we will have the | |
1058 | infrastructure to indicate the size of saved registers on a | |
1059 | per-frame basis, but right now we don't; the kernel saves eight | |
37c4d197 DJ |
1060 | bytes but we only want four. Use regs_base to access any |
1061 | 64-bit fields. */ | |
2eb4d78b | 1062 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
37c4d197 DJ |
1063 | regs_base = sigcontext_base + 4; |
1064 | else | |
1065 | regs_base = sigcontext_base; | |
5792a79b | 1066 | |
2eb4d78b | 1067 | if (mips_linux_restart_reg_p (gdbarch)) |
822b6570 DJ |
1068 | trad_frame_set_reg_addr (this_cache, |
1069 | (MIPS_RESTART_REGNUM | |
2eb4d78b | 1070 | + gdbarch_num_regs (gdbarch)), |
822b6570 | 1071 | regs_base + SIGCONTEXT_REGS); |
5792a79b DJ |
1072 | |
1073 | for (ireg = 1; ireg < 32; ireg++) | |
295093a4 | 1074 | trad_frame_set_reg_addr (this_cache, |
7d266584 MR |
1075 | (ireg + MIPS_ZERO_REGNUM |
1076 | + gdbarch_num_regs (gdbarch)), | |
1077 | (regs_base + SIGCONTEXT_REGS | |
1078 | + ireg * SIGCONTEXT_REG_SIZE)); | |
5792a79b | 1079 | |
37c4d197 DJ |
1080 | /* The way that floating point registers are saved, unfortunately, |
1081 | depends on the architecture the kernel is built for. For the r3000 and | |
1082 | tx39, four bytes of each register are at the beginning of each of the | |
1083 | 32 eight byte slots. For everything else, the registers are saved | |
1084 | using double precision; only the even-numbered slots are initialized, | |
1085 | and the high bits are the odd-numbered register. Assume the latter | |
1086 | layout, since we can't tell, and it's much more common. Which bits are | |
1087 | the "high" bits depends on endianness. */ | |
5792a79b | 1088 | for (ireg = 0; ireg < 32; ireg++) |
2eb4d78b | 1089 | if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (ireg & 1)) |
f57d151a | 1090 | trad_frame_set_reg_addr (this_cache, |
7d266584 MR |
1091 | ireg + regs->fp0 + gdbarch_num_regs (gdbarch), |
1092 | (sigcontext_base + SIGCONTEXT_FPREGS + 4 | |
1093 | + (ireg & ~1) * SIGCONTEXT_REG_SIZE)); | |
37c4d197 | 1094 | else |
f57d151a | 1095 | trad_frame_set_reg_addr (this_cache, |
7d266584 MR |
1096 | ireg + regs->fp0 + gdbarch_num_regs (gdbarch), |
1097 | (sigcontext_base + SIGCONTEXT_FPREGS | |
1098 | + (ireg & ~1) * SIGCONTEXT_REG_SIZE)); | |
5792a79b | 1099 | |
f57d151a | 1100 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1101 | regs->pc + gdbarch_num_regs (gdbarch), |
37c4d197 | 1102 | regs_base + SIGCONTEXT_PC); |
5792a79b | 1103 | |
295093a4 | 1104 | trad_frame_set_reg_addr (this_cache, |
7d266584 MR |
1105 | (regs->fp_control_status |
1106 | + gdbarch_num_regs (gdbarch)), | |
5792a79b | 1107 | sigcontext_base + SIGCONTEXT_FPCSR); |
d0e64392 MR |
1108 | |
1109 | if (regs->dspctl != -1) | |
1110 | trad_frame_set_reg_addr (this_cache, | |
1111 | regs->dspctl + gdbarch_num_regs (gdbarch), | |
1112 | sigcontext_base + SIGCONTEXT_DSPCTL); | |
1113 | ||
f57d151a | 1114 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1115 | regs->hi + gdbarch_num_regs (gdbarch), |
37c4d197 | 1116 | regs_base + SIGCONTEXT_HI); |
f57d151a | 1117 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1118 | regs->lo + gdbarch_num_regs (gdbarch), |
37c4d197 | 1119 | regs_base + SIGCONTEXT_LO); |
d0e64392 MR |
1120 | |
1121 | if (regs->dspacc != -1) | |
1122 | { | |
1123 | trad_frame_set_reg_addr (this_cache, | |
1124 | regs->dspacc + 0 + gdbarch_num_regs (gdbarch), | |
1125 | sigcontext_base + SIGCONTEXT_HI1); | |
1126 | trad_frame_set_reg_addr (this_cache, | |
1127 | regs->dspacc + 1 + gdbarch_num_regs (gdbarch), | |
1128 | sigcontext_base + SIGCONTEXT_LO1); | |
1129 | trad_frame_set_reg_addr (this_cache, | |
1130 | regs->dspacc + 2 + gdbarch_num_regs (gdbarch), | |
1131 | sigcontext_base + SIGCONTEXT_HI2); | |
1132 | trad_frame_set_reg_addr (this_cache, | |
1133 | regs->dspacc + 3 + gdbarch_num_regs (gdbarch), | |
1134 | sigcontext_base + SIGCONTEXT_LO2); | |
1135 | trad_frame_set_reg_addr (this_cache, | |
1136 | regs->dspacc + 4 + gdbarch_num_regs (gdbarch), | |
1137 | sigcontext_base + SIGCONTEXT_HI3); | |
1138 | trad_frame_set_reg_addr (this_cache, | |
1139 | regs->dspacc + 5 + gdbarch_num_regs (gdbarch), | |
1140 | sigcontext_base + SIGCONTEXT_LO3); | |
1141 | } | |
1142 | else | |
1143 | { | |
1144 | trad_frame_set_reg_addr (this_cache, | |
1145 | regs->cause + gdbarch_num_regs (gdbarch), | |
1146 | sigcontext_base + SIGCONTEXT_CAUSE); | |
1147 | trad_frame_set_reg_addr (this_cache, | |
1148 | regs->badvaddr + gdbarch_num_regs (gdbarch), | |
1149 | sigcontext_base + SIGCONTEXT_BADVADDR); | |
1150 | } | |
5792a79b DJ |
1151 | |
1152 | /* Choice of the bottom of the sigframe is somewhat arbitrary. */ | |
eb195664 | 1153 | trad_frame_set_id (this_cache, frame_id_build (frame_sp, func)); |
5792a79b DJ |
1154 | } |
1155 | ||
1156 | /* *INDENT-OFF* */ | |
1157 | /* For N32/N64 things look different. There is no non-rt signal frame. | |
1158 | ||
1159 | struct rt_sigframe_n32 { | |
1160 | u32 rs_ass[4]; [ argument save space for o32 ] | |
eb195664 | 1161 | u32 rs_code[2]; [ signal trampoline or fill ] |
5792a79b DJ |
1162 | struct siginfo rs_info; |
1163 | struct ucontextn32 rs_uc; | |
1164 | }; | |
1165 | ||
1166 | struct ucontextn32 { | |
1167 | u32 uc_flags; | |
1168 | s32 uc_link; | |
1169 | stack32_t uc_stack; | |
1170 | struct sigcontext uc_mcontext; | |
1171 | sigset_t uc_sigmask; [ mask last for extensibility ] | |
1172 | }; | |
295093a4 | 1173 | |
e741f4d4 | 1174 | struct rt_sigframe { |
5792a79b DJ |
1175 | u32 rs_ass[4]; [ argument save space for o32 ] |
1176 | u32 rs_code[2]; [ signal trampoline ] | |
1177 | struct siginfo rs_info; | |
1178 | struct ucontext rs_uc; | |
1179 | }; | |
1180 | ||
1181 | struct ucontext { | |
1182 | unsigned long uc_flags; | |
1183 | struct ucontext *uc_link; | |
1184 | stack_t uc_stack; | |
1185 | struct sigcontext uc_mcontext; | |
1186 | sigset_t uc_sigmask; [ mask last for extensibility ] | |
1187 | }; | |
1188 | ||
1189 | And the sigcontext is different (this is for both n32 and n64): | |
1190 | ||
1191 | struct sigcontext { | |
1192 | unsigned long long sc_regs[32]; | |
1193 | unsigned long long sc_fpregs[32]; | |
1194 | unsigned long long sc_mdhi; | |
e741f4d4 DJ |
1195 | unsigned long long sc_hi1; |
1196 | unsigned long long sc_hi2; | |
1197 | unsigned long long sc_hi3; | |
5792a79b | 1198 | unsigned long long sc_mdlo; |
e741f4d4 DJ |
1199 | unsigned long long sc_lo1; |
1200 | unsigned long long sc_lo2; | |
1201 | unsigned long long sc_lo3; | |
5792a79b | 1202 | unsigned long long sc_pc; |
5792a79b | 1203 | unsigned int sc_fpc_csr; |
5792a79b | 1204 | unsigned int sc_used_math; |
e741f4d4 DJ |
1205 | unsigned int sc_dsp; |
1206 | unsigned int sc_reserved; | |
1207 | }; | |
1208 | ||
1209 | That is the post-2.6.12 definition of the 64-bit sigcontext; before | |
1210 | then, there were no hi1-hi3 or lo1-lo3. Cause and badvaddr were | |
1211 | included too. */ | |
5792a79b DJ |
1212 | /* *INDENT-ON* */ |
1213 | ||
1214 | #define N32_STACK_T_SIZE STACK_T_SIZE | |
1215 | #define N64_STACK_T_SIZE (2 * 8 + 4) | |
1216 | #define N32_UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + N32_STACK_T_SIZE + 4) | |
1217 | #define N64_UCONTEXT_SIGCONTEXT_OFFSET (2 * 8 + N64_STACK_T_SIZE + 4) | |
1218 | #define N32_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ | |
1219 | + RTSIGFRAME_SIGINFO_SIZE \ | |
1220 | + N32_UCONTEXT_SIGCONTEXT_OFFSET) | |
1221 | #define N64_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ | |
1222 | + RTSIGFRAME_SIGINFO_SIZE \ | |
1223 | + N64_UCONTEXT_SIGCONTEXT_OFFSET) | |
1224 | ||
1225 | #define N64_SIGCONTEXT_REGS (0 * 8) | |
1226 | #define N64_SIGCONTEXT_FPREGS (32 * 8) | |
1227 | #define N64_SIGCONTEXT_HI (64 * 8) | |
d0e64392 MR |
1228 | #define N64_SIGCONTEXT_HI1 (65 * 8) |
1229 | #define N64_SIGCONTEXT_HI2 (66 * 8) | |
1230 | #define N64_SIGCONTEXT_HI3 (67 * 8) | |
e741f4d4 | 1231 | #define N64_SIGCONTEXT_LO (68 * 8) |
d0e64392 MR |
1232 | #define N64_SIGCONTEXT_LO1 (69 * 8) |
1233 | #define N64_SIGCONTEXT_LO2 (70 * 8) | |
1234 | #define N64_SIGCONTEXT_LO3 (71 * 8) | |
e741f4d4 | 1235 | #define N64_SIGCONTEXT_PC (72 * 8) |
d0e64392 MR |
1236 | #define N64_SIGCONTEXT_FPCSR (73 * 8 + 0) |
1237 | #define N64_SIGCONTEXT_DSPCTL (74 * 8 + 0) | |
5792a79b DJ |
1238 | |
1239 | #define N64_SIGCONTEXT_REG_SIZE 8 | |
295093a4 | 1240 | |
5792a79b DJ |
1241 | static void |
1242 | mips_linux_n32n64_sigframe_init (const struct tramp_frame *self, | |
b8a22b94 | 1243 | struct frame_info *this_frame, |
5792a79b DJ |
1244 | struct trad_frame_cache *this_cache, |
1245 | CORE_ADDR func) | |
1246 | { | |
b8a22b94 | 1247 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
22e048c9 | 1248 | int ireg; |
eb195664 DD |
1249 | CORE_ADDR frame_sp = get_frame_sp (this_frame); |
1250 | CORE_ADDR sigcontext_base; | |
2eb4d78b | 1251 | const struct mips_regnum *regs = mips_regnum (gdbarch); |
5792a79b | 1252 | |
858339f2 MR |
1253 | if (self == &mips_linux_n32_rt_sigframe |
1254 | || self == µmips_linux_n32_rt_sigframe) | |
eb195664 | 1255 | sigcontext_base = frame_sp + N32_SIGFRAME_SIGCONTEXT_OFFSET; |
5792a79b | 1256 | else |
eb195664 | 1257 | sigcontext_base = frame_sp + N64_SIGFRAME_SIGCONTEXT_OFFSET; |
295093a4 | 1258 | |
2eb4d78b | 1259 | if (mips_linux_restart_reg_p (gdbarch)) |
822b6570 DJ |
1260 | trad_frame_set_reg_addr (this_cache, |
1261 | (MIPS_RESTART_REGNUM | |
2eb4d78b | 1262 | + gdbarch_num_regs (gdbarch)), |
822b6570 | 1263 | sigcontext_base + N64_SIGCONTEXT_REGS); |
5792a79b DJ |
1264 | |
1265 | for (ireg = 1; ireg < 32; ireg++) | |
295093a4 | 1266 | trad_frame_set_reg_addr (this_cache, |
7d266584 MR |
1267 | (ireg + MIPS_ZERO_REGNUM |
1268 | + gdbarch_num_regs (gdbarch)), | |
1269 | (sigcontext_base + N64_SIGCONTEXT_REGS | |
1270 | + ireg * N64_SIGCONTEXT_REG_SIZE)); | |
5792a79b DJ |
1271 | |
1272 | for (ireg = 0; ireg < 32; ireg++) | |
f57d151a | 1273 | trad_frame_set_reg_addr (this_cache, |
7d266584 MR |
1274 | ireg + regs->fp0 + gdbarch_num_regs (gdbarch), |
1275 | (sigcontext_base + N64_SIGCONTEXT_FPREGS | |
1276 | + ireg * N64_SIGCONTEXT_REG_SIZE)); | |
5792a79b | 1277 | |
f57d151a | 1278 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1279 | regs->pc + gdbarch_num_regs (gdbarch), |
5792a79b DJ |
1280 | sigcontext_base + N64_SIGCONTEXT_PC); |
1281 | ||
295093a4 | 1282 | trad_frame_set_reg_addr (this_cache, |
7d266584 MR |
1283 | (regs->fp_control_status |
1284 | + gdbarch_num_regs (gdbarch)), | |
5792a79b | 1285 | sigcontext_base + N64_SIGCONTEXT_FPCSR); |
d0e64392 | 1286 | |
f57d151a | 1287 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1288 | regs->hi + gdbarch_num_regs (gdbarch), |
5792a79b | 1289 | sigcontext_base + N64_SIGCONTEXT_HI); |
f57d151a | 1290 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1291 | regs->lo + gdbarch_num_regs (gdbarch), |
5792a79b | 1292 | sigcontext_base + N64_SIGCONTEXT_LO); |
5792a79b | 1293 | |
d0e64392 MR |
1294 | if (regs->dspacc != -1) |
1295 | { | |
1296 | trad_frame_set_reg_addr (this_cache, | |
1297 | regs->dspacc + 0 + gdbarch_num_regs (gdbarch), | |
1298 | sigcontext_base + N64_SIGCONTEXT_HI1); | |
1299 | trad_frame_set_reg_addr (this_cache, | |
1300 | regs->dspacc + 1 + gdbarch_num_regs (gdbarch), | |
1301 | sigcontext_base + N64_SIGCONTEXT_LO1); | |
1302 | trad_frame_set_reg_addr (this_cache, | |
1303 | regs->dspacc + 2 + gdbarch_num_regs (gdbarch), | |
1304 | sigcontext_base + N64_SIGCONTEXT_HI2); | |
1305 | trad_frame_set_reg_addr (this_cache, | |
1306 | regs->dspacc + 3 + gdbarch_num_regs (gdbarch), | |
1307 | sigcontext_base + N64_SIGCONTEXT_LO2); | |
1308 | trad_frame_set_reg_addr (this_cache, | |
1309 | regs->dspacc + 4 + gdbarch_num_regs (gdbarch), | |
1310 | sigcontext_base + N64_SIGCONTEXT_HI3); | |
1311 | trad_frame_set_reg_addr (this_cache, | |
1312 | regs->dspacc + 5 + gdbarch_num_regs (gdbarch), | |
1313 | sigcontext_base + N64_SIGCONTEXT_LO3); | |
1314 | } | |
1315 | if (regs->dspctl != -1) | |
1316 | trad_frame_set_reg_addr (this_cache, | |
1317 | regs->dspctl + gdbarch_num_regs (gdbarch), | |
1318 | sigcontext_base + N64_SIGCONTEXT_DSPCTL); | |
1319 | ||
5792a79b | 1320 | /* Choice of the bottom of the sigframe is somewhat arbitrary. */ |
eb195664 | 1321 | trad_frame_set_id (this_cache, frame_id_build (frame_sp, func)); |
5792a79b DJ |
1322 | } |
1323 | ||
858339f2 MR |
1324 | /* Implement struct tramp_frame's "validate" method for standard MIPS code. */ |
1325 | ||
1326 | static int | |
1327 | mips_linux_sigframe_validate (const struct tramp_frame *self, | |
1328 | struct frame_info *this_frame, | |
1329 | CORE_ADDR *pc) | |
1330 | { | |
1331 | return mips_pc_is_mips (*pc); | |
1332 | } | |
1333 | ||
1334 | /* Implement struct tramp_frame's "validate" method for microMIPS code. */ | |
1335 | ||
1336 | static int | |
1337 | micromips_linux_sigframe_validate (const struct tramp_frame *self, | |
1338 | struct frame_info *this_frame, | |
1339 | CORE_ADDR *pc) | |
1340 | { | |
3e29f34a MR |
1341 | if (mips_pc_is_micromips (get_frame_arch (this_frame), *pc)) |
1342 | { | |
1343 | *pc = mips_unmake_compact_addr (*pc); | |
1344 | return 1; | |
1345 | } | |
1346 | else | |
1347 | return 0; | |
858339f2 MR |
1348 | } |
1349 | ||
5a439849 MR |
1350 | /* Implement the "write_pc" gdbarch method. */ |
1351 | ||
822b6570 | 1352 | static void |
61a1198a | 1353 | mips_linux_write_pc (struct regcache *regcache, CORE_ADDR pc) |
822b6570 | 1354 | { |
ac7936df | 1355 | struct gdbarch *gdbarch = regcache->arch (); |
5a439849 MR |
1356 | |
1357 | mips_write_pc (regcache, pc); | |
822b6570 DJ |
1358 | |
1359 | /* Clear the syscall restart flag. */ | |
2eb4d78b | 1360 | if (mips_linux_restart_reg_p (gdbarch)) |
61a1198a | 1361 | regcache_cooked_write_unsigned (regcache, MIPS_RESTART_REGNUM, 0); |
822b6570 DJ |
1362 | } |
1363 | ||
1364 | /* Return 1 if MIPS_RESTART_REGNUM is usable. */ | |
1365 | ||
1366 | int | |
1367 | mips_linux_restart_reg_p (struct gdbarch *gdbarch) | |
1368 | { | |
1369 | /* If we do not have a target description with registers, then | |
1370 | MIPS_RESTART_REGNUM will not be included in the register set. */ | |
1371 | if (!tdesc_has_registers (gdbarch_target_desc (gdbarch))) | |
1372 | return 0; | |
1373 | ||
1374 | /* If we do, then MIPS_RESTART_REGNUM is safe to check; it will | |
1375 | either be GPR-sized or missing. */ | |
1376 | return register_size (gdbarch, MIPS_RESTART_REGNUM) > 0; | |
1377 | } | |
9f62d0e2 | 1378 | |
e38d4e1a DJ |
1379 | /* When FRAME is at a syscall instruction, return the PC of the next |
1380 | instruction to be executed. */ | |
1381 | ||
63807e1d | 1382 | static CORE_ADDR |
e38d4e1a DJ |
1383 | mips_linux_syscall_next_pc (struct frame_info *frame) |
1384 | { | |
1385 | CORE_ADDR pc = get_frame_pc (frame); | |
1386 | ULONGEST v0 = get_frame_register_unsigned (frame, MIPS_V0_REGNUM); | |
1387 | ||
1388 | /* If we are about to make a sigreturn syscall, use the unwinder to | |
1389 | decode the signal frame. */ | |
1390 | if (v0 == MIPS_NR_sigreturn | |
1391 | || v0 == MIPS_NR_rt_sigreturn | |
1392 | || v0 == MIPS_NR_N64_rt_sigreturn | |
1393 | || v0 == MIPS_NR_N32_rt_sigreturn) | |
c7ce8faa | 1394 | return frame_unwind_caller_pc (get_current_frame ()); |
e38d4e1a DJ |
1395 | |
1396 | return pc + 4; | |
1397 | } | |
1398 | ||
385203ed DD |
1399 | /* Return the current system call's number present in the |
1400 | v0 register. When the function fails, it returns -1. */ | |
1401 | ||
1402 | static LONGEST | |
1403 | mips_linux_get_syscall_number (struct gdbarch *gdbarch, | |
1404 | ptid_t ptid) | |
1405 | { | |
1406 | struct regcache *regcache = get_thread_regcache (ptid); | |
1407 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1408 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1409 | int regsize = register_size (gdbarch, MIPS_V0_REGNUM); | |
1410 | /* The content of a register */ | |
1411 | gdb_byte buf[8]; | |
1412 | /* The result */ | |
1413 | LONGEST ret; | |
1414 | ||
1415 | /* Make sure we're in a known ABI */ | |
1416 | gdb_assert (tdep->mips_abi == MIPS_ABI_O32 | |
1417 | || tdep->mips_abi == MIPS_ABI_N32 | |
1418 | || tdep->mips_abi == MIPS_ABI_N64); | |
1419 | ||
1420 | gdb_assert (regsize <= sizeof (buf)); | |
1421 | ||
1422 | /* Getting the system call number from the register. | |
1423 | syscall number is in v0 or $2. */ | |
1424 | regcache_cooked_read (regcache, MIPS_V0_REGNUM, buf); | |
1425 | ||
1426 | ret = extract_signed_integer (buf, regsize, byte_order); | |
1427 | ||
1428 | return ret; | |
1429 | } | |
1430 | ||
eb14d406 SDJ |
1431 | /* Implementation of `gdbarch_gdb_signal_to_target', as defined in |
1432 | gdbarch.h. */ | |
1433 | ||
1434 | static int | |
1435 | mips_gdb_signal_to_target (struct gdbarch *gdbarch, | |
1436 | enum gdb_signal signal) | |
1437 | { | |
1438 | switch (signal) | |
1439 | { | |
1440 | case GDB_SIGNAL_EMT: | |
1441 | return MIPS_LINUX_SIGEMT; | |
1442 | ||
1443 | case GDB_SIGNAL_BUS: | |
1444 | return MIPS_LINUX_SIGBUS; | |
1445 | ||
1446 | case GDB_SIGNAL_SYS: | |
1447 | return MIPS_LINUX_SIGSYS; | |
1448 | ||
1449 | case GDB_SIGNAL_USR1: | |
1450 | return MIPS_LINUX_SIGUSR1; | |
1451 | ||
1452 | case GDB_SIGNAL_USR2: | |
1453 | return MIPS_LINUX_SIGUSR2; | |
1454 | ||
1455 | case GDB_SIGNAL_CHLD: | |
1456 | return MIPS_LINUX_SIGCHLD; | |
1457 | ||
1458 | case GDB_SIGNAL_PWR: | |
1459 | return MIPS_LINUX_SIGPWR; | |
1460 | ||
1461 | case GDB_SIGNAL_WINCH: | |
1462 | return MIPS_LINUX_SIGWINCH; | |
1463 | ||
1464 | case GDB_SIGNAL_URG: | |
1465 | return MIPS_LINUX_SIGURG; | |
1466 | ||
1467 | case GDB_SIGNAL_IO: | |
1468 | return MIPS_LINUX_SIGIO; | |
1469 | ||
1470 | case GDB_SIGNAL_POLL: | |
1471 | return MIPS_LINUX_SIGPOLL; | |
1472 | ||
1473 | case GDB_SIGNAL_STOP: | |
1474 | return MIPS_LINUX_SIGSTOP; | |
1475 | ||
1476 | case GDB_SIGNAL_TSTP: | |
1477 | return MIPS_LINUX_SIGTSTP; | |
1478 | ||
1479 | case GDB_SIGNAL_CONT: | |
1480 | return MIPS_LINUX_SIGCONT; | |
1481 | ||
1482 | case GDB_SIGNAL_TTIN: | |
1483 | return MIPS_LINUX_SIGTTIN; | |
1484 | ||
1485 | case GDB_SIGNAL_TTOU: | |
1486 | return MIPS_LINUX_SIGTTOU; | |
1487 | ||
1488 | case GDB_SIGNAL_VTALRM: | |
1489 | return MIPS_LINUX_SIGVTALRM; | |
1490 | ||
1491 | case GDB_SIGNAL_PROF: | |
1492 | return MIPS_LINUX_SIGPROF; | |
1493 | ||
1494 | case GDB_SIGNAL_XCPU: | |
1495 | return MIPS_LINUX_SIGXCPU; | |
1496 | ||
1497 | case GDB_SIGNAL_XFSZ: | |
1498 | return MIPS_LINUX_SIGXFSZ; | |
1499 | ||
1500 | /* GDB_SIGNAL_REALTIME_32 is not continuous in <gdb/signals.def>, | |
1501 | therefore we have to handle it here. */ | |
1502 | case GDB_SIGNAL_REALTIME_32: | |
1503 | return MIPS_LINUX_SIGRTMIN; | |
1504 | } | |
1505 | ||
1506 | if (signal >= GDB_SIGNAL_REALTIME_33 | |
1507 | && signal <= GDB_SIGNAL_REALTIME_63) | |
1508 | { | |
1509 | int offset = signal - GDB_SIGNAL_REALTIME_33; | |
1510 | ||
1511 | return MIPS_LINUX_SIGRTMIN + 1 + offset; | |
1512 | } | |
1513 | else if (signal >= GDB_SIGNAL_REALTIME_64 | |
1514 | && signal <= GDB_SIGNAL_REALTIME_127) | |
1515 | { | |
1516 | int offset = signal - GDB_SIGNAL_REALTIME_64; | |
1517 | ||
1518 | return MIPS_LINUX_SIGRT64 + offset; | |
1519 | } | |
1520 | ||
1521 | return linux_gdb_signal_to_target (gdbarch, signal); | |
1522 | } | |
1523 | ||
7d266584 | 1524 | /* Translate signals based on MIPS signal values. |
232b8704 ME |
1525 | Adapted from gdb/common/signals.c. */ |
1526 | ||
1527 | static enum gdb_signal | |
eb14d406 | 1528 | mips_gdb_signal_from_target (struct gdbarch *gdbarch, int signal) |
232b8704 | 1529 | { |
eb14d406 | 1530 | switch (signal) |
232b8704 | 1531 | { |
eb14d406 | 1532 | case MIPS_LINUX_SIGEMT: |
232b8704 | 1533 | return GDB_SIGNAL_EMT; |
eb14d406 SDJ |
1534 | |
1535 | case MIPS_LINUX_SIGBUS: | |
232b8704 | 1536 | return GDB_SIGNAL_BUS; |
eb14d406 SDJ |
1537 | |
1538 | case MIPS_LINUX_SIGSYS: | |
232b8704 | 1539 | return GDB_SIGNAL_SYS; |
eb14d406 SDJ |
1540 | |
1541 | case MIPS_LINUX_SIGUSR1: | |
232b8704 | 1542 | return GDB_SIGNAL_USR1; |
eb14d406 SDJ |
1543 | |
1544 | case MIPS_LINUX_SIGUSR2: | |
232b8704 | 1545 | return GDB_SIGNAL_USR2; |
eb14d406 SDJ |
1546 | |
1547 | case MIPS_LINUX_SIGCHLD: | |
232b8704 | 1548 | return GDB_SIGNAL_CHLD; |
eb14d406 SDJ |
1549 | |
1550 | case MIPS_LINUX_SIGPWR: | |
232b8704 | 1551 | return GDB_SIGNAL_PWR; |
eb14d406 SDJ |
1552 | |
1553 | case MIPS_LINUX_SIGWINCH: | |
232b8704 | 1554 | return GDB_SIGNAL_WINCH; |
eb14d406 SDJ |
1555 | |
1556 | case MIPS_LINUX_SIGURG: | |
232b8704 | 1557 | return GDB_SIGNAL_URG; |
eb14d406 SDJ |
1558 | |
1559 | /* No way to differentiate between SIGIO and SIGPOLL. | |
1560 | Therefore, we just handle the first one. */ | |
1561 | case MIPS_LINUX_SIGIO: | |
1562 | return GDB_SIGNAL_IO; | |
1563 | ||
1564 | case MIPS_LINUX_SIGSTOP: | |
232b8704 | 1565 | return GDB_SIGNAL_STOP; |
eb14d406 SDJ |
1566 | |
1567 | case MIPS_LINUX_SIGTSTP: | |
232b8704 | 1568 | return GDB_SIGNAL_TSTP; |
eb14d406 SDJ |
1569 | |
1570 | case MIPS_LINUX_SIGCONT: | |
232b8704 | 1571 | return GDB_SIGNAL_CONT; |
eb14d406 SDJ |
1572 | |
1573 | case MIPS_LINUX_SIGTTIN: | |
232b8704 | 1574 | return GDB_SIGNAL_TTIN; |
eb14d406 SDJ |
1575 | |
1576 | case MIPS_LINUX_SIGTTOU: | |
232b8704 | 1577 | return GDB_SIGNAL_TTOU; |
eb14d406 SDJ |
1578 | |
1579 | case MIPS_LINUX_SIGVTALRM: | |
232b8704 | 1580 | return GDB_SIGNAL_VTALRM; |
eb14d406 SDJ |
1581 | |
1582 | case MIPS_LINUX_SIGPROF: | |
232b8704 | 1583 | return GDB_SIGNAL_PROF; |
eb14d406 SDJ |
1584 | |
1585 | case MIPS_LINUX_SIGXCPU: | |
232b8704 | 1586 | return GDB_SIGNAL_XCPU; |
eb14d406 SDJ |
1587 | |
1588 | case MIPS_LINUX_SIGXFSZ: | |
232b8704 | 1589 | return GDB_SIGNAL_XFSZ; |
eb14d406 | 1590 | } |
232b8704 | 1591 | |
eb14d406 | 1592 | if (signal >= MIPS_LINUX_SIGRTMIN && signal <= MIPS_LINUX_SIGRTMAX) |
232b8704 ME |
1593 | { |
1594 | /* GDB_SIGNAL_REALTIME values are not contiguous, map parts of | |
1595 | the MIPS block to the respective GDB_SIGNAL_REALTIME blocks. */ | |
eb14d406 SDJ |
1596 | int offset = signal - MIPS_LINUX_SIGRTMIN; |
1597 | ||
1598 | if (offset == 0) | |
232b8704 | 1599 | return GDB_SIGNAL_REALTIME_32; |
eb14d406 SDJ |
1600 | else if (offset < 32) |
1601 | return (enum gdb_signal) (offset - 1 | |
1602 | + (int) GDB_SIGNAL_REALTIME_33); | |
232b8704 | 1603 | else |
eb14d406 SDJ |
1604 | return (enum gdb_signal) (offset - 32 |
1605 | + (int) GDB_SIGNAL_REALTIME_64); | |
232b8704 ME |
1606 | } |
1607 | ||
eb14d406 | 1608 | return linux_gdb_signal_from_target (gdbarch, signal); |
232b8704 ME |
1609 | } |
1610 | ||
5792a79b DJ |
1611 | /* Initialize one of the GNU/Linux OS ABIs. */ |
1612 | ||
19ed69dd | 1613 | static void |
295093a4 MS |
1614 | mips_linux_init_abi (struct gdbarch_info info, |
1615 | struct gdbarch *gdbarch) | |
19ed69dd | 1616 | { |
96f026fc KB |
1617 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1618 | enum mips_abi abi = mips_abi (gdbarch); | |
0dba2a6c | 1619 | struct tdesc_arch_data *tdesc_data = info.tdesc_data; |
96f026fc | 1620 | |
a5ee0f0c PA |
1621 | linux_init_abi (info, gdbarch); |
1622 | ||
385203ed DD |
1623 | /* Get the syscall number from the arch's register. */ |
1624 | set_gdbarch_get_syscall_number (gdbarch, mips_linux_get_syscall_number); | |
1625 | ||
96f026fc KB |
1626 | switch (abi) |
1627 | { | |
1628 | case MIPS_ABI_O32: | |
1629 | set_gdbarch_get_longjmp_target (gdbarch, | |
7d266584 | 1630 | mips_linux_get_longjmp_target); |
96f026fc | 1631 | set_solib_svr4_fetch_link_map_offsets |
76a9d10f | 1632 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); |
858339f2 MR |
1633 | tramp_frame_prepend_unwinder (gdbarch, µmips_linux_o32_sigframe); |
1634 | tramp_frame_prepend_unwinder (gdbarch, | |
1635 | µmips_linux_o32_rt_sigframe); | |
fb2be677 AC |
1636 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_sigframe); |
1637 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_rt_sigframe); | |
458c8db8 | 1638 | set_xml_syscall_file_name (gdbarch, "syscalls/mips-o32-linux.xml"); |
96f026fc KB |
1639 | break; |
1640 | case MIPS_ABI_N32: | |
1641 | set_gdbarch_get_longjmp_target (gdbarch, | |
7d266584 | 1642 | mips_linux_get_longjmp_target); |
96f026fc | 1643 | set_solib_svr4_fetch_link_map_offsets |
76a9d10f | 1644 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); |
d05f6826 DJ |
1645 | set_gdbarch_long_double_bit (gdbarch, 128); |
1646 | /* These floatformats should probably be renamed. MIPS uses | |
1647 | the same 128-bit IEEE floating point format that IA-64 uses, | |
1648 | except that the quiet/signalling NaN bit is reversed (GDB | |
1649 | does not distinguish between quiet and signalling NaNs). */ | |
8da61cc4 | 1650 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); |
858339f2 MR |
1651 | tramp_frame_prepend_unwinder (gdbarch, |
1652 | µmips_linux_n32_rt_sigframe); | |
fb2be677 | 1653 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n32_rt_sigframe); |
458c8db8 | 1654 | set_xml_syscall_file_name (gdbarch, "syscalls/mips-n32-linux.xml"); |
96f026fc KB |
1655 | break; |
1656 | case MIPS_ABI_N64: | |
1657 | set_gdbarch_get_longjmp_target (gdbarch, | |
7d266584 | 1658 | mips64_linux_get_longjmp_target); |
96f026fc | 1659 | set_solib_svr4_fetch_link_map_offsets |
76a9d10f | 1660 | (gdbarch, svr4_lp64_fetch_link_map_offsets); |
d05f6826 DJ |
1661 | set_gdbarch_long_double_bit (gdbarch, 128); |
1662 | /* These floatformats should probably be renamed. MIPS uses | |
1663 | the same 128-bit IEEE floating point format that IA-64 uses, | |
1664 | except that the quiet/signalling NaN bit is reversed (GDB | |
1665 | does not distinguish between quiet and signalling NaNs). */ | |
8da61cc4 | 1666 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); |
858339f2 MR |
1667 | tramp_frame_prepend_unwinder (gdbarch, |
1668 | µmips_linux_n64_rt_sigframe); | |
fb2be677 | 1669 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n64_rt_sigframe); |
458c8db8 | 1670 | set_xml_syscall_file_name (gdbarch, "syscalls/mips-n64-linux.xml"); |
96f026fc KB |
1671 | break; |
1672 | default: | |
96f026fc KB |
1673 | break; |
1674 | } | |
6de918a6 DJ |
1675 | |
1676 | set_gdbarch_skip_solib_resolver (gdbarch, mips_linux_skip_resolver); | |
1677 | ||
0d0266c6 | 1678 | set_gdbarch_software_single_step (gdbarch, mips_software_single_step); |
b2756930 KB |
1679 | |
1680 | /* Enable TLS support. */ | |
1681 | set_gdbarch_fetch_tls_load_module_address (gdbarch, | |
7d266584 | 1682 | svr4_fetch_objfile_link_map); |
7d522c90 DJ |
1683 | |
1684 | /* Initialize this lazily, to avoid an initialization order | |
1685 | dependency on solib-svr4.c's _initialize routine. */ | |
1686 | if (mips_svr4_so_ops.in_dynsym_resolve_code == NULL) | |
1687 | { | |
1688 | mips_svr4_so_ops = svr4_so_ops; | |
1689 | mips_svr4_so_ops.in_dynsym_resolve_code | |
1690 | = mips_linux_in_dynsym_resolve_code; | |
1691 | } | |
1692 | set_solib_ops (gdbarch, &mips_svr4_so_ops); | |
822b6570 DJ |
1693 | |
1694 | set_gdbarch_write_pc (gdbarch, mips_linux_write_pc); | |
1695 | ||
4eb0ad19 DJ |
1696 | set_gdbarch_core_read_description (gdbarch, |
1697 | mips_linux_core_read_description); | |
1698 | ||
d4036235 AA |
1699 | set_gdbarch_iterate_over_regset_sections |
1700 | (gdbarch, mips_linux_iterate_over_regset_sections); | |
50e8a0d5 | 1701 | |
232b8704 ME |
1702 | set_gdbarch_gdb_signal_from_target (gdbarch, |
1703 | mips_gdb_signal_from_target); | |
1704 | ||
eb14d406 SDJ |
1705 | set_gdbarch_gdb_signal_to_target (gdbarch, |
1706 | mips_gdb_signal_to_target); | |
1707 | ||
e38d4e1a DJ |
1708 | tdep->syscall_next_pc = mips_linux_syscall_next_pc; |
1709 | ||
822b6570 DJ |
1710 | if (tdesc_data) |
1711 | { | |
1712 | const struct tdesc_feature *feature; | |
1713 | ||
1714 | /* If we have target-described registers, then we can safely | |
1715 | reserve a number for MIPS_RESTART_REGNUM (whether it is | |
1716 | described or not). */ | |
1717 | gdb_assert (gdbarch_num_regs (gdbarch) <= MIPS_RESTART_REGNUM); | |
1718 | set_gdbarch_num_regs (gdbarch, MIPS_RESTART_REGNUM + 1); | |
cf233303 | 1719 | set_gdbarch_num_pseudo_regs (gdbarch, MIPS_RESTART_REGNUM + 1); |
822b6570 DJ |
1720 | |
1721 | /* If it's present, then assign it to the reserved number. */ | |
1722 | feature = tdesc_find_feature (info.target_desc, | |
1723 | "org.gnu.gdb.mips.linux"); | |
1724 | if (feature != NULL) | |
1725 | tdesc_numbered_register (feature, tdesc_data, MIPS_RESTART_REGNUM, | |
1726 | "restart"); | |
1727 | } | |
19ed69dd KB |
1728 | } |
1729 | ||
2aa830e4 | 1730 | void |
d1bacddc | 1731 | _initialize_mips_linux_tdep (void) |
2aa830e4 | 1732 | { |
96f026fc KB |
1733 | const struct bfd_arch_info *arch_info; |
1734 | ||
96f026fc KB |
1735 | for (arch_info = bfd_lookup_arch (bfd_arch_mips, 0); |
1736 | arch_info != NULL; | |
1737 | arch_info = arch_info->next) | |
1738 | { | |
295093a4 MS |
1739 | gdbarch_register_osabi (bfd_arch_mips, arch_info->mach, |
1740 | GDB_OSABI_LINUX, | |
96f026fc KB |
1741 | mips_linux_init_abi); |
1742 | } | |
032bb6ea YQ |
1743 | |
1744 | /* Initialize the standard target descriptions. */ | |
1745 | initialize_tdesc_mips_linux (); | |
1746 | initialize_tdesc_mips_dsp_linux (); | |
1747 | initialize_tdesc_mips64_linux (); | |
1748 | initialize_tdesc_mips64_dsp_linux (); | |
2aa830e4 | 1749 | } |