Commit | Line | Data |
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75c9abc6 | 1 | /* Target-dependent code for GNU/Linux on MIPS processors. |
a094c6fb | 2 | |
6aba47ca | 3 | Copyright (C) 2001, 2002, 2004, 2005, 2006, 2007 |
76a9d10f | 4 | Free Software Foundation, Inc. |
2aa830e4 DJ |
5 | |
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
197e01b6 EZ |
20 | Foundation, Inc., 51 Franklin Street, Fifth Floor, |
21 | Boston, MA 02110-1301, USA. */ | |
2aa830e4 DJ |
22 | |
23 | #include "defs.h" | |
24 | #include "gdbcore.h" | |
25 | #include "target.h" | |
26 | #include "solib-svr4.h" | |
19ed69dd | 27 | #include "osabi.h" |
96f026fc | 28 | #include "mips-tdep.h" |
19ed69dd | 29 | #include "gdb_string.h" |
96f026fc | 30 | #include "gdb_assert.h" |
6de918a6 | 31 | #include "frame.h" |
2fdf551c | 32 | #include "regcache.h" |
5792a79b DJ |
33 | #include "trad-frame.h" |
34 | #include "tramp-frame.h" | |
e6bb342a | 35 | #include "gdbtypes.h" |
5ea03926 | 36 | #include "solib.h" |
7d522c90 DJ |
37 | #include "solib-svr4.h" |
38 | #include "solist.h" | |
982e9687 | 39 | #include "symtab.h" |
d37eb719 | 40 | #include "mips-linux-tdep.h" |
2aa830e4 | 41 | |
7d522c90 DJ |
42 | static struct target_so_ops mips_svr4_so_ops; |
43 | ||
2aa830e4 | 44 | /* Figure out where the longjmp will land. |
295093a4 MS |
45 | We expect the first arg to be a pointer to the jmp_buf structure |
46 | from which we extract the pc (MIPS_LINUX_JB_PC) that we will land | |
47 | at. The pc is copied into PC. This routine returns 1 on | |
48 | success. */ | |
2aa830e4 | 49 | |
19ed69dd KB |
50 | #define MIPS_LINUX_JB_ELEMENT_SIZE 4 |
51 | #define MIPS_LINUX_JB_PC 0 | |
52 | ||
53 | static int | |
2aa830e4 DJ |
54 | mips_linux_get_longjmp_target (CORE_ADDR *pc) |
55 | { | |
56 | CORE_ADDR jb_addr; | |
57 | char buf[TARGET_PTR_BIT / TARGET_CHAR_BIT]; | |
58 | ||
613e114f | 59 | jb_addr = read_register (MIPS_A0_REGNUM); |
2aa830e4 | 60 | |
bf072999 DJ |
61 | if (target_read_memory (jb_addr |
62 | + MIPS_LINUX_JB_PC * MIPS_LINUX_JB_ELEMENT_SIZE, | |
63 | buf, TARGET_PTR_BIT / TARGET_CHAR_BIT)) | |
2aa830e4 DJ |
64 | return 0; |
65 | ||
7c0b4a20 | 66 | *pc = extract_unsigned_integer (buf, TARGET_PTR_BIT / TARGET_CHAR_BIT); |
2aa830e4 DJ |
67 | |
68 | return 1; | |
69 | } | |
70 | ||
4246e332 | 71 | /* Transform the bits comprising a 32-bit register to the right size |
23a6d369 AC |
72 | for regcache_raw_supply(). This is needed when mips_isa_regsize() |
73 | is 8. */ | |
96f026fc KB |
74 | |
75 | static void | |
28f5035f | 76 | supply_32bit_reg (struct regcache *regcache, int regnum, const void *addr) |
96f026fc | 77 | { |
d37eb719 | 78 | gdb_byte buf[MAX_REGISTER_SIZE]; |
3acba339 | 79 | store_signed_integer (buf, register_size (current_gdbarch, regnum), |
96f026fc | 80 | extract_signed_integer (addr, 4)); |
28f5035f | 81 | regcache_raw_supply (regcache, regnum, buf); |
96f026fc KB |
82 | } |
83 | ||
2aa830e4 DJ |
84 | /* Unpack an elf_gregset_t into GDB's register cache. */ |
85 | ||
d37eb719 | 86 | void |
28f5035f UW |
87 | mips_supply_gregset (struct regcache *regcache, |
88 | const mips_elf_gregset_t *gregsetp) | |
2aa830e4 DJ |
89 | { |
90 | int regi; | |
28f5035f | 91 | const mips_elf_greg_t *regp = *gregsetp; |
d9d9c31f | 92 | char zerobuf[MAX_REGISTER_SIZE]; |
bf072999 | 93 | |
d9d9c31f | 94 | memset (zerobuf, 0, MAX_REGISTER_SIZE); |
2aa830e4 DJ |
95 | |
96 | for (regi = EF_REG0; regi <= EF_REG31; regi++) | |
28f5035f | 97 | supply_32bit_reg (regcache, regi - EF_REG0, regp + regi); |
2aa830e4 | 98 | |
28f5035f UW |
99 | supply_32bit_reg (regcache, mips_regnum (current_gdbarch)->lo, |
100 | regp + EF_LO); | |
101 | supply_32bit_reg (regcache, mips_regnum (current_gdbarch)->hi, | |
102 | regp + EF_HI); | |
56cea623 | 103 | |
28f5035f UW |
104 | supply_32bit_reg (regcache, mips_regnum (current_gdbarch)->pc, |
105 | regp + EF_CP0_EPC); | |
106 | supply_32bit_reg (regcache, mips_regnum (current_gdbarch)->badvaddr, | |
107 | regp + EF_CP0_BADVADDR); | |
108 | supply_32bit_reg (regcache, MIPS_PS_REGNUM, regp + EF_CP0_STATUS); | |
109 | supply_32bit_reg (regcache, mips_regnum (current_gdbarch)->cause, | |
110 | regp + EF_CP0_CAUSE); | |
2aa830e4 DJ |
111 | |
112 | /* Fill inaccessible registers with zero. */ | |
28f5035f | 113 | regcache_raw_supply (regcache, MIPS_UNUSED_REGNUM, zerobuf); |
295093a4 MS |
114 | for (regi = MIPS_FIRST_EMBED_REGNUM; |
115 | regi < MIPS_LAST_EMBED_REGNUM; | |
116 | regi++) | |
28f5035f | 117 | regcache_raw_supply (regcache, regi, zerobuf); |
2aa830e4 DJ |
118 | } |
119 | ||
120 | /* Pack our registers (or one register) into an elf_gregset_t. */ | |
121 | ||
d37eb719 | 122 | void |
28f5035f UW |
123 | mips_fill_gregset (const struct regcache *regcache, |
124 | mips_elf_gregset_t *gregsetp, int regno) | |
2aa830e4 DJ |
125 | { |
126 | int regaddr, regi; | |
d37eb719 | 127 | mips_elf_greg_t *regp = *gregsetp; |
96f026fc | 128 | void *dst; |
2aa830e4 DJ |
129 | |
130 | if (regno == -1) | |
131 | { | |
d37eb719 | 132 | memset (regp, 0, sizeof (mips_elf_gregset_t)); |
2aa830e4 | 133 | for (regi = 0; regi < 32; regi++) |
28f5035f UW |
134 | mips_fill_gregset (regcache, gregsetp, regi); |
135 | mips_fill_gregset (regcache, gregsetp, | |
136 | mips_regnum (current_gdbarch)->lo); | |
137 | mips_fill_gregset (regcache, gregsetp, | |
138 | mips_regnum (current_gdbarch)->hi); | |
139 | mips_fill_gregset (regcache, gregsetp, | |
140 | mips_regnum (current_gdbarch)->pc); | |
141 | mips_fill_gregset (regcache, gregsetp, | |
142 | mips_regnum (current_gdbarch)->badvaddr); | |
143 | mips_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM); | |
144 | mips_fill_gregset (regcache, gregsetp, | |
145 | mips_regnum (current_gdbarch)->cause); | |
2aa830e4 DJ |
146 | return; |
147 | } | |
148 | ||
149 | if (regno < 32) | |
150 | { | |
2aa830e4 | 151 | dst = regp + regno + EF_REG0; |
28f5035f | 152 | regcache_raw_collect (regcache, regno, dst); |
2aa830e4 DJ |
153 | return; |
154 | } | |
155 | ||
56cea623 AC |
156 | if (regno == mips_regnum (current_gdbarch)->lo) |
157 | regaddr = EF_LO; | |
158 | else if (regno == mips_regnum (current_gdbarch)->hi) | |
159 | regaddr = EF_HI; | |
160 | else if (regno == mips_regnum (current_gdbarch)->pc) | |
161 | regaddr = EF_CP0_EPC; | |
162 | else if (regno == mips_regnum (current_gdbarch)->badvaddr) | |
163 | regaddr = EF_CP0_BADVADDR; | |
24e05951 | 164 | else if (regno == MIPS_PS_REGNUM) |
56cea623 AC |
165 | regaddr = EF_CP0_STATUS; |
166 | else if (regno == mips_regnum (current_gdbarch)->cause) | |
167 | regaddr = EF_CP0_CAUSE; | |
168 | else | |
169 | regaddr = -1; | |
2aa830e4 DJ |
170 | |
171 | if (regaddr != -1) | |
172 | { | |
2aa830e4 | 173 | dst = regp + regaddr; |
28f5035f | 174 | regcache_raw_collect (regcache, regno, dst); |
2aa830e4 DJ |
175 | } |
176 | } | |
177 | ||
178 | /* Likewise, unpack an elf_fpregset_t. */ | |
179 | ||
d37eb719 | 180 | void |
28f5035f UW |
181 | mips_supply_fpregset (struct regcache *regcache, |
182 | const mips_elf_fpregset_t *fpregsetp) | |
2aa830e4 | 183 | { |
52f0bd74 | 184 | int regi; |
d9d9c31f | 185 | char zerobuf[MAX_REGISTER_SIZE]; |
bf072999 | 186 | |
d9d9c31f | 187 | memset (zerobuf, 0, MAX_REGISTER_SIZE); |
2aa830e4 DJ |
188 | |
189 | for (regi = 0; regi < 32; regi++) | |
28f5035f | 190 | regcache_raw_supply (regcache, FP0_REGNUM + regi, *fpregsetp + regi); |
2aa830e4 | 191 | |
28f5035f | 192 | regcache_raw_supply (regcache, |
23a6d369 | 193 | mips_regnum (current_gdbarch)->fp_control_status, |
28f5035f | 194 | *fpregsetp + 32); |
2aa830e4 | 195 | |
295093a4 | 196 | /* FIXME: how can we supply FCRIR? The ABI doesn't tell us. */ |
28f5035f | 197 | regcache_raw_supply (regcache, |
23a6d369 AC |
198 | mips_regnum (current_gdbarch)->fp_implementation_revision, |
199 | zerobuf); | |
2aa830e4 DJ |
200 | } |
201 | ||
202 | /* Likewise, pack one or all floating point registers into an | |
203 | elf_fpregset_t. */ | |
204 | ||
d37eb719 | 205 | void |
28f5035f UW |
206 | mips_fill_fpregset (const struct regcache *regcache, |
207 | mips_elf_fpregset_t *fpregsetp, int regno) | |
2aa830e4 DJ |
208 | { |
209 | char *from, *to; | |
210 | ||
211 | if ((regno >= FP0_REGNUM) && (regno < FP0_REGNUM + 32)) | |
212 | { | |
2aa830e4 | 213 | to = (char *) (*fpregsetp + regno - FP0_REGNUM); |
28f5035f | 214 | regcache_raw_collect (regcache, regno, to); |
2aa830e4 | 215 | } |
56cea623 | 216 | else if (regno == mips_regnum (current_gdbarch)->fp_control_status) |
2aa830e4 | 217 | { |
2aa830e4 | 218 | to = (char *) (*fpregsetp + 32); |
28f5035f | 219 | regcache_raw_collect (regcache, regno, to); |
2aa830e4 DJ |
220 | } |
221 | else if (regno == -1) | |
222 | { | |
223 | int regi; | |
224 | ||
225 | for (regi = 0; regi < 32; regi++) | |
28f5035f UW |
226 | mips_fill_fpregset (regcache, fpregsetp, FP0_REGNUM + regi); |
227 | mips_fill_fpregset (regcache, fpregsetp, | |
9f62d0e2 | 228 | mips_regnum (current_gdbarch)->fp_control_status); |
2aa830e4 DJ |
229 | } |
230 | } | |
231 | ||
96f026fc KB |
232 | /* Support for 64-bit ABIs. */ |
233 | ||
96f026fc | 234 | /* Figure out where the longjmp will land. |
295093a4 MS |
235 | We expect the first arg to be a pointer to the jmp_buf structure |
236 | from which we extract the pc (MIPS_LINUX_JB_PC) that we will land | |
237 | at. The pc is copied into PC. This routine returns 1 on | |
238 | success. */ | |
96f026fc KB |
239 | |
240 | /* Details about jmp_buf. */ | |
241 | ||
242 | #define MIPS64_LINUX_JB_PC 0 | |
243 | ||
244 | static int | |
245 | mips64_linux_get_longjmp_target (CORE_ADDR *pc) | |
246 | { | |
247 | CORE_ADDR jb_addr; | |
248 | void *buf = alloca (TARGET_PTR_BIT / TARGET_CHAR_BIT); | |
249 | int element_size = TARGET_PTR_BIT == 32 ? 4 : 8; | |
250 | ||
613e114f | 251 | jb_addr = read_register (MIPS_A0_REGNUM); |
96f026fc KB |
252 | |
253 | if (target_read_memory (jb_addr + MIPS64_LINUX_JB_PC * element_size, | |
254 | buf, TARGET_PTR_BIT / TARGET_CHAR_BIT)) | |
255 | return 0; | |
256 | ||
7c0b4a20 | 257 | *pc = extract_unsigned_integer (buf, TARGET_PTR_BIT / TARGET_CHAR_BIT); |
96f026fc KB |
258 | |
259 | return 1; | |
260 | } | |
261 | ||
d37eb719 DJ |
262 | /* Register set support functions. These operate on standard 64-bit |
263 | regsets, but work whether the target is 32-bit or 64-bit. A 32-bit | |
264 | target will still use the 64-bit format for PTRACE_GETREGS. */ | |
265 | ||
266 | /* Supply a 64-bit register. */ | |
96f026fc | 267 | |
d37eb719 | 268 | void |
28f5035f UW |
269 | supply_64bit_reg (struct regcache *regcache, int regnum, |
270 | const gdb_byte *buf) | |
d37eb719 DJ |
271 | { |
272 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG | |
273 | && register_size (current_gdbarch, regnum) == 4) | |
28f5035f | 274 | regcache_raw_supply (regcache, regnum, buf + 4); |
d37eb719 | 275 | else |
28f5035f | 276 | regcache_raw_supply (regcache, regnum, buf); |
d37eb719 DJ |
277 | } |
278 | ||
279 | /* Unpack a 64-bit elf_gregset_t into GDB's register cache. */ | |
280 | ||
281 | void | |
28f5035f UW |
282 | mips64_supply_gregset (struct regcache *regcache, |
283 | const mips64_elf_gregset_t *gregsetp) | |
96f026fc KB |
284 | { |
285 | int regi; | |
28f5035f | 286 | const mips64_elf_greg_t *regp = *gregsetp; |
d37eb719 | 287 | gdb_byte zerobuf[MAX_REGISTER_SIZE]; |
96f026fc | 288 | |
d9d9c31f | 289 | memset (zerobuf, 0, MAX_REGISTER_SIZE); |
96f026fc KB |
290 | |
291 | for (regi = MIPS64_EF_REG0; regi <= MIPS64_EF_REG31; regi++) | |
28f5035f UW |
292 | supply_64bit_reg (regcache, regi - MIPS64_EF_REG0, |
293 | (const gdb_byte *)(regp + regi)); | |
294 | ||
295 | supply_64bit_reg (regcache, mips_regnum (current_gdbarch)->lo, | |
296 | (const gdb_byte *) (regp + MIPS64_EF_LO)); | |
297 | supply_64bit_reg (regcache, mips_regnum (current_gdbarch)->hi, | |
298 | (const gdb_byte *) (regp + MIPS64_EF_HI)); | |
299 | ||
300 | supply_64bit_reg (regcache, mips_regnum (current_gdbarch)->pc, | |
301 | (const gdb_byte *) (regp + MIPS64_EF_CP0_EPC)); | |
302 | supply_64bit_reg (regcache, mips_regnum (current_gdbarch)->badvaddr, | |
303 | (const gdb_byte *) (regp + MIPS64_EF_CP0_BADVADDR)); | |
304 | supply_64bit_reg (regcache, MIPS_PS_REGNUM, | |
305 | (const gdb_byte *) (regp + MIPS64_EF_CP0_STATUS)); | |
306 | supply_64bit_reg (regcache, mips_regnum (current_gdbarch)->cause, | |
307 | (const gdb_byte *) (regp + MIPS64_EF_CP0_CAUSE)); | |
96f026fc KB |
308 | |
309 | /* Fill inaccessible registers with zero. */ | |
28f5035f | 310 | regcache_raw_supply (regcache, MIPS_UNUSED_REGNUM, zerobuf); |
295093a4 MS |
311 | for (regi = MIPS_FIRST_EMBED_REGNUM; |
312 | regi < MIPS_LAST_EMBED_REGNUM; | |
313 | regi++) | |
28f5035f | 314 | regcache_raw_supply (regcache, regi, zerobuf); |
96f026fc KB |
315 | } |
316 | ||
d37eb719 | 317 | /* Pack our registers (or one register) into a 64-bit elf_gregset_t. */ |
96f026fc | 318 | |
d37eb719 | 319 | void |
28f5035f UW |
320 | mips64_fill_gregset (const struct regcache *regcache, |
321 | mips64_elf_gregset_t *gregsetp, int regno) | |
96f026fc KB |
322 | { |
323 | int regaddr, regi; | |
324 | mips64_elf_greg_t *regp = *gregsetp; | |
325 | void *src, *dst; | |
326 | ||
327 | if (regno == -1) | |
328 | { | |
329 | memset (regp, 0, sizeof (mips64_elf_gregset_t)); | |
330 | for (regi = 0; regi < 32; regi++) | |
28f5035f UW |
331 | mips64_fill_gregset (regcache, gregsetp, regi); |
332 | mips64_fill_gregset (regcache, gregsetp, | |
333 | mips_regnum (current_gdbarch)->lo); | |
334 | mips64_fill_gregset (regcache, gregsetp, | |
335 | mips_regnum (current_gdbarch)->hi); | |
336 | mips64_fill_gregset (regcache, gregsetp, | |
337 | mips_regnum (current_gdbarch)->pc); | |
338 | mips64_fill_gregset (regcache, gregsetp, | |
295093a4 | 339 | mips_regnum (current_gdbarch)->badvaddr); |
28f5035f UW |
340 | mips64_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM); |
341 | mips64_fill_gregset (regcache, gregsetp, | |
295093a4 | 342 | mips_regnum (current_gdbarch)->cause); |
96f026fc KB |
343 | return; |
344 | } | |
345 | ||
346 | if (regno < 32) | |
d37eb719 DJ |
347 | regaddr = regno + MIPS64_EF_REG0; |
348 | else if (regno == mips_regnum (current_gdbarch)->lo) | |
56cea623 AC |
349 | regaddr = MIPS64_EF_LO; |
350 | else if (regno == mips_regnum (current_gdbarch)->hi) | |
351 | regaddr = MIPS64_EF_HI; | |
352 | else if (regno == mips_regnum (current_gdbarch)->pc) | |
353 | regaddr = MIPS64_EF_CP0_EPC; | |
354 | else if (regno == mips_regnum (current_gdbarch)->badvaddr) | |
355 | regaddr = MIPS64_EF_CP0_BADVADDR; | |
24e05951 | 356 | else if (regno == MIPS_PS_REGNUM) |
56cea623 AC |
357 | regaddr = MIPS64_EF_CP0_STATUS; |
358 | else if (regno == mips_regnum (current_gdbarch)->cause) | |
359 | regaddr = MIPS64_EF_CP0_CAUSE; | |
360 | else | |
361 | regaddr = -1; | |
96f026fc KB |
362 | |
363 | if (regaddr != -1) | |
364 | { | |
d37eb719 DJ |
365 | gdb_byte buf[MAX_REGISTER_SIZE]; |
366 | LONGEST val; | |
367 | ||
28f5035f | 368 | regcache_raw_collect (regcache, regno, buf); |
d37eb719 DJ |
369 | val = extract_signed_integer (buf, |
370 | register_size (current_gdbarch, regno)); | |
96f026fc | 371 | dst = regp + regaddr; |
d37eb719 | 372 | store_signed_integer (dst, 8, val); |
96f026fc KB |
373 | } |
374 | } | |
375 | ||
376 | /* Likewise, unpack an elf_fpregset_t. */ | |
377 | ||
d37eb719 | 378 | void |
28f5035f UW |
379 | mips64_supply_fpregset (struct regcache *regcache, |
380 | const mips64_elf_fpregset_t *fpregsetp) | |
96f026fc | 381 | { |
52f0bd74 | 382 | int regi; |
96f026fc | 383 | |
d37eb719 DJ |
384 | /* See mips_linux_o32_sigframe_init for a description of the |
385 | peculiar FP register layout. */ | |
386 | if (register_size (current_gdbarch, FP0_REGNUM) == 4) | |
387 | for (regi = 0; regi < 32; regi++) | |
388 | { | |
28f5035f | 389 | const gdb_byte *reg_ptr = (const gdb_byte *)(*fpregsetp + (regi & ~1)); |
d37eb719 DJ |
390 | if ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) != (regi & 1)) |
391 | reg_ptr += 4; | |
28f5035f | 392 | regcache_raw_supply (regcache, FP0_REGNUM + regi, reg_ptr); |
d37eb719 DJ |
393 | } |
394 | else | |
395 | for (regi = 0; regi < 32; regi++) | |
28f5035f UW |
396 | regcache_raw_supply (regcache, FP0_REGNUM + regi, |
397 | (const char *)(*fpregsetp + regi)); | |
d37eb719 | 398 | |
28f5035f UW |
399 | supply_32bit_reg (regcache, mips_regnum (current_gdbarch)->fp_control_status, |
400 | (const gdb_byte *)(*fpregsetp + 32)); | |
d37eb719 DJ |
401 | |
402 | /* The ABI doesn't tell us how to supply FCRIR, and core dumps don't | |
403 | include it - but the result of PTRACE_GETFPREGS does. The best we | |
404 | can do is to assume that its value is present. */ | |
28f5035f UW |
405 | supply_32bit_reg (regcache, |
406 | mips_regnum (current_gdbarch)->fp_implementation_revision, | |
407 | (const gdb_byte *)(*fpregsetp + 32) + 4); | |
96f026fc KB |
408 | } |
409 | ||
410 | /* Likewise, pack one or all floating point registers into an | |
411 | elf_fpregset_t. */ | |
412 | ||
d37eb719 | 413 | void |
28f5035f UW |
414 | mips64_fill_fpregset (const struct regcache *regcache, |
415 | mips64_elf_fpregset_t *fpregsetp, int regno) | |
96f026fc | 416 | { |
d37eb719 | 417 | gdb_byte *to; |
96f026fc KB |
418 | |
419 | if ((regno >= FP0_REGNUM) && (regno < FP0_REGNUM + 32)) | |
420 | { | |
d37eb719 DJ |
421 | /* See mips_linux_o32_sigframe_init for a description of the |
422 | peculiar FP register layout. */ | |
423 | if (register_size (current_gdbarch, regno) == 4) | |
424 | { | |
425 | int regi = regno - FP0_REGNUM; | |
426 | ||
427 | to = (gdb_byte *) (*fpregsetp + (regi & ~1)); | |
428 | if ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) != (regi & 1)) | |
429 | to += 4; | |
28f5035f | 430 | regcache_raw_collect (regcache, regno, to); |
d37eb719 DJ |
431 | } |
432 | else | |
433 | { | |
434 | to = (gdb_byte *) (*fpregsetp + regno - FP0_REGNUM); | |
28f5035f | 435 | regcache_raw_collect (regcache, regno, to); |
d37eb719 | 436 | } |
96f026fc | 437 | } |
56cea623 | 438 | else if (regno == mips_regnum (current_gdbarch)->fp_control_status) |
96f026fc | 439 | { |
d37eb719 DJ |
440 | gdb_byte buf[MAX_REGISTER_SIZE]; |
441 | LONGEST val; | |
442 | ||
28f5035f | 443 | regcache_raw_collect (regcache, regno, buf); |
d37eb719 DJ |
444 | val = extract_signed_integer (buf, |
445 | register_size (current_gdbarch, regno)); | |
446 | to = (gdb_byte *) (*fpregsetp + 32); | |
447 | store_signed_integer (to, 4, val); | |
448 | } | |
449 | else if (regno == mips_regnum (current_gdbarch)->fp_implementation_revision) | |
450 | { | |
451 | gdb_byte buf[MAX_REGISTER_SIZE]; | |
452 | LONGEST val; | |
453 | ||
28f5035f | 454 | regcache_raw_collect (regcache, regno, buf); |
d37eb719 DJ |
455 | val = extract_signed_integer (buf, |
456 | register_size (current_gdbarch, regno)); | |
457 | to = (gdb_byte *) (*fpregsetp + 32) + 4; | |
458 | store_signed_integer (to, 4, val); | |
96f026fc KB |
459 | } |
460 | else if (regno == -1) | |
461 | { | |
462 | int regi; | |
463 | ||
464 | for (regi = 0; regi < 32; regi++) | |
28f5035f UW |
465 | mips64_fill_fpregset (regcache, fpregsetp, FP0_REGNUM + regi); |
466 | mips64_fill_fpregset (regcache, fpregsetp, | |
d37eb719 | 467 | mips_regnum (current_gdbarch)->fp_control_status); |
28f5035f UW |
468 | mips64_fill_fpregset (regcache, fpregsetp, |
469 | (mips_regnum (current_gdbarch) | |
470 | ->fp_implementation_revision)); | |
96f026fc KB |
471 | } |
472 | } | |
473 | ||
474 | ||
2aa830e4 DJ |
475 | /* Use a local version of this function to get the correct types for |
476 | regsets, until multi-arch core support is ready. */ | |
477 | ||
478 | static void | |
9eefc95f UW |
479 | fetch_core_registers (struct regcache *regcache, |
480 | char *core_reg_sect, unsigned core_reg_size, | |
2aa830e4 DJ |
481 | int which, CORE_ADDR reg_addr) |
482 | { | |
d37eb719 DJ |
483 | mips_elf_gregset_t gregset; |
484 | mips_elf_fpregset_t fpregset; | |
96f026fc KB |
485 | mips64_elf_gregset_t gregset64; |
486 | mips64_elf_fpregset_t fpregset64; | |
2aa830e4 DJ |
487 | |
488 | if (which == 0) | |
489 | { | |
96f026fc | 490 | if (core_reg_size == sizeof (gregset)) |
2aa830e4 | 491 | { |
96f026fc | 492 | memcpy ((char *) &gregset, core_reg_sect, sizeof (gregset)); |
9eefc95f | 493 | mips_supply_gregset (regcache, |
28f5035f | 494 | (const mips_elf_gregset_t *) &gregset); |
96f026fc KB |
495 | } |
496 | else if (core_reg_size == sizeof (gregset64)) | |
497 | { | |
498 | memcpy ((char *) &gregset64, core_reg_sect, sizeof (gregset64)); | |
9eefc95f | 499 | mips64_supply_gregset (regcache, |
28f5035f | 500 | (const mips64_elf_gregset_t *) &gregset64); |
2aa830e4 DJ |
501 | } |
502 | else | |
503 | { | |
8a3fe4f8 | 504 | warning (_("wrong size gregset struct in core file")); |
2aa830e4 DJ |
505 | } |
506 | } | |
507 | else if (which == 2) | |
508 | { | |
96f026fc | 509 | if (core_reg_size == sizeof (fpregset)) |
2aa830e4 | 510 | { |
96f026fc | 511 | memcpy ((char *) &fpregset, core_reg_sect, sizeof (fpregset)); |
9eefc95f | 512 | mips_supply_fpregset (regcache, |
28f5035f | 513 | (const mips_elf_fpregset_t *) &fpregset); |
96f026fc KB |
514 | } |
515 | else if (core_reg_size == sizeof (fpregset64)) | |
516 | { | |
295093a4 MS |
517 | memcpy ((char *) &fpregset64, core_reg_sect, |
518 | sizeof (fpregset64)); | |
9eefc95f | 519 | mips64_supply_fpregset (regcache, |
28f5035f | 520 | (const mips64_elf_fpregset_t *) &fpregset64); |
2aa830e4 DJ |
521 | } |
522 | else | |
523 | { | |
8a3fe4f8 | 524 | warning (_("wrong size fpregset struct in core file")); |
2aa830e4 DJ |
525 | } |
526 | } | |
527 | } | |
528 | ||
529 | /* Register that we are able to handle ELF file formats using standard | |
530 | procfs "regset" structures. */ | |
531 | ||
532 | static struct core_fns regset_core_fns = | |
533 | { | |
534 | bfd_target_elf_flavour, /* core_flavour */ | |
535 | default_check_format, /* check_format */ | |
536 | default_core_sniffer, /* core_sniffer */ | |
537 | fetch_core_registers, /* core_read_registers */ | |
538 | NULL /* next */ | |
539 | }; | |
540 | ||
96f026fc | 541 | |
295093a4 MS |
542 | /* Check the code at PC for a dynamic linker lazy resolution stub. |
543 | Because they aren't in the .plt section, we pattern-match on the | |
544 | code generated by GNU ld. They look like this: | |
6de918a6 DJ |
545 | |
546 | lw t9,0x8010(gp) | |
547 | addu t7,ra | |
548 | jalr t9,ra | |
549 | addiu t8,zero,INDEX | |
550 | ||
295093a4 MS |
551 | (with the appropriate doubleword instructions for N64). Also |
552 | return the dynamic symbol index used in the last instruction. */ | |
6de918a6 DJ |
553 | |
554 | static int | |
555 | mips_linux_in_dynsym_stub (CORE_ADDR pc, char *name) | |
556 | { | |
557 | unsigned char buf[28], *p; | |
558 | ULONGEST insn, insn1; | |
559 | int n64 = (mips_abi (current_gdbarch) == MIPS_ABI_N64); | |
560 | ||
561 | read_memory (pc - 12, buf, 28); | |
562 | ||
563 | if (n64) | |
564 | { | |
565 | /* ld t9,0x8010(gp) */ | |
566 | insn1 = 0xdf998010; | |
567 | } | |
568 | else | |
569 | { | |
570 | /* lw t9,0x8010(gp) */ | |
571 | insn1 = 0x8f998010; | |
572 | } | |
573 | ||
574 | p = buf + 12; | |
575 | while (p >= buf) | |
576 | { | |
577 | insn = extract_unsigned_integer (p, 4); | |
578 | if (insn == insn1) | |
579 | break; | |
580 | p -= 4; | |
581 | } | |
582 | if (p < buf) | |
583 | return 0; | |
584 | ||
585 | insn = extract_unsigned_integer (p + 4, 4); | |
586 | if (n64) | |
587 | { | |
588 | /* daddu t7,ra */ | |
589 | if (insn != 0x03e0782d) | |
590 | return 0; | |
591 | } | |
592 | else | |
593 | { | |
594 | /* addu t7,ra */ | |
595 | if (insn != 0x03e07821) | |
596 | return 0; | |
597 | } | |
295093a4 | 598 | |
6de918a6 DJ |
599 | insn = extract_unsigned_integer (p + 8, 4); |
600 | /* jalr t9,ra */ | |
601 | if (insn != 0x0320f809) | |
602 | return 0; | |
603 | ||
604 | insn = extract_unsigned_integer (p + 12, 4); | |
605 | if (n64) | |
606 | { | |
607 | /* daddiu t8,zero,0 */ | |
608 | if ((insn & 0xffff0000) != 0x64180000) | |
609 | return 0; | |
610 | } | |
611 | else | |
612 | { | |
613 | /* addiu t8,zero,0 */ | |
614 | if ((insn & 0xffff0000) != 0x24180000) | |
615 | return 0; | |
616 | } | |
617 | ||
618 | return (insn & 0xffff); | |
619 | } | |
620 | ||
295093a4 MS |
621 | /* Return non-zero iff PC belongs to the dynamic linker resolution |
622 | code or to a stub. */ | |
6de918a6 | 623 | |
7d522c90 | 624 | static int |
6de918a6 DJ |
625 | mips_linux_in_dynsym_resolve_code (CORE_ADDR pc) |
626 | { | |
295093a4 MS |
627 | /* Check whether PC is in the dynamic linker. This also checks |
628 | whether it is in the .plt section, which MIPS does not use. */ | |
7d522c90 | 629 | if (svr4_in_dynsym_resolve_code (pc)) |
6de918a6 DJ |
630 | return 1; |
631 | ||
295093a4 MS |
632 | /* Pattern match for the stub. It would be nice if there were a |
633 | more efficient way to avoid this check. */ | |
6de918a6 DJ |
634 | if (mips_linux_in_dynsym_stub (pc, NULL)) |
635 | return 1; | |
636 | ||
637 | return 0; | |
638 | } | |
639 | ||
640 | /* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c, | |
641 | and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc | |
642 | implementation of this triggers at "fixup" from the same objfile as | |
c4c5b7ba AC |
643 | "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at |
644 | "__dl_runtime_resolve" directly. An unresolved PLT entry will | |
645 | point to _dl_runtime_resolve, which will first call | |
646 | __dl_runtime_resolve, and then pass control to the resolved | |
647 | function. */ | |
6de918a6 DJ |
648 | |
649 | static CORE_ADDR | |
650 | mips_linux_skip_resolver (struct gdbarch *gdbarch, CORE_ADDR pc) | |
651 | { | |
652 | struct minimal_symbol *resolver; | |
653 | ||
654 | resolver = lookup_minimal_symbol ("__dl_runtime_resolve", NULL, NULL); | |
655 | ||
656 | if (resolver && SYMBOL_VALUE_ADDRESS (resolver) == pc) | |
295093a4 | 657 | return frame_pc_unwind (get_current_frame ()); |
6de918a6 DJ |
658 | |
659 | return 0; | |
295093a4 | 660 | } |
6de918a6 | 661 | |
5792a79b DJ |
662 | /* Signal trampoline support. There are four supported layouts for a |
663 | signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and | |
664 | n64 rt_sigframe. We handle them all independently; not the most | |
665 | efficient way, but simplest. First, declare all the unwinders. */ | |
666 | ||
667 | static void mips_linux_o32_sigframe_init (const struct tramp_frame *self, | |
668 | struct frame_info *next_frame, | |
669 | struct trad_frame_cache *this_cache, | |
670 | CORE_ADDR func); | |
671 | ||
672 | static void mips_linux_n32n64_sigframe_init (const struct tramp_frame *self, | |
673 | struct frame_info *next_frame, | |
674 | struct trad_frame_cache *this_cache, | |
675 | CORE_ADDR func); | |
676 | ||
677 | #define MIPS_NR_LINUX 4000 | |
678 | #define MIPS_NR_N64_LINUX 5000 | |
679 | #define MIPS_NR_N32_LINUX 6000 | |
680 | ||
681 | #define MIPS_NR_sigreturn MIPS_NR_LINUX + 119 | |
682 | #define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193 | |
683 | #define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211 | |
684 | #define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211 | |
685 | ||
686 | #define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn | |
687 | #define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn | |
688 | #define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn | |
689 | #define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn | |
690 | #define MIPS_INST_SYSCALL 0x0000000c | |
691 | ||
2cd8546d AC |
692 | static const struct tramp_frame mips_linux_o32_sigframe = { |
693 | SIGTRAMP_FRAME, | |
5792a79b | 694 | 4, |
2cd8546d AC |
695 | { |
696 | { MIPS_INST_LI_V0_SIGRETURN, -1 }, | |
697 | { MIPS_INST_SYSCALL, -1 }, | |
698 | { TRAMP_SENTINEL_INSN, -1 } | |
699 | }, | |
5792a79b DJ |
700 | mips_linux_o32_sigframe_init |
701 | }; | |
702 | ||
2cd8546d AC |
703 | static const struct tramp_frame mips_linux_o32_rt_sigframe = { |
704 | SIGTRAMP_FRAME, | |
5792a79b | 705 | 4, |
2cd8546d AC |
706 | { |
707 | { MIPS_INST_LI_V0_RT_SIGRETURN, -1 }, | |
708 | { MIPS_INST_SYSCALL, -1 }, | |
709 | { TRAMP_SENTINEL_INSN, -1 } }, | |
5792a79b DJ |
710 | mips_linux_o32_sigframe_init |
711 | }; | |
712 | ||
2cd8546d AC |
713 | static const struct tramp_frame mips_linux_n32_rt_sigframe = { |
714 | SIGTRAMP_FRAME, | |
5792a79b | 715 | 4, |
2cd8546d AC |
716 | { |
717 | { MIPS_INST_LI_V0_N32_RT_SIGRETURN, -1 }, | |
718 | { MIPS_INST_SYSCALL, -1 }, | |
719 | { TRAMP_SENTINEL_INSN, -1 } | |
720 | }, | |
5792a79b DJ |
721 | mips_linux_n32n64_sigframe_init |
722 | }; | |
723 | ||
2cd8546d AC |
724 | static const struct tramp_frame mips_linux_n64_rt_sigframe = { |
725 | SIGTRAMP_FRAME, | |
5792a79b | 726 | 4, |
fcbd8a5c TS |
727 | { |
728 | { MIPS_INST_LI_V0_N64_RT_SIGRETURN, -1 }, | |
729 | { MIPS_INST_SYSCALL, -1 }, | |
730 | { TRAMP_SENTINEL_INSN, -1 } | |
731 | }, | |
5792a79b DJ |
732 | mips_linux_n32n64_sigframe_init |
733 | }; | |
734 | ||
735 | /* *INDENT-OFF* */ | |
736 | /* The unwinder for o32 signal frames. The legacy structures look | |
737 | like this: | |
738 | ||
739 | struct sigframe { | |
740 | u32 sf_ass[4]; [argument save space for o32] | |
741 | u32 sf_code[2]; [signal trampoline] | |
742 | struct sigcontext sf_sc; | |
743 | sigset_t sf_mask; | |
744 | }; | |
745 | ||
746 | struct sigcontext { | |
747 | unsigned int sc_regmask; [Unused] | |
748 | unsigned int sc_status; | |
749 | unsigned long long sc_pc; | |
750 | unsigned long long sc_regs[32]; | |
751 | unsigned long long sc_fpregs[32]; | |
752 | unsigned int sc_ownedfp; | |
753 | unsigned int sc_fpc_csr; | |
754 | unsigned int sc_fpc_eir; [Unused] | |
755 | unsigned int sc_used_math; | |
756 | unsigned int sc_ssflags; [Unused] | |
757 | [Alignment hole of four bytes] | |
758 | unsigned long long sc_mdhi; | |
759 | unsigned long long sc_mdlo; | |
760 | ||
761 | unsigned int sc_cause; [Unused] | |
762 | unsigned int sc_badvaddr; [Unused] | |
763 | ||
764 | unsigned long sc_sigset[4]; [kernel's sigset_t] | |
765 | }; | |
766 | ||
767 | The RT signal frames look like this: | |
768 | ||
769 | struct rt_sigframe { | |
770 | u32 rs_ass[4]; [argument save space for o32] | |
771 | u32 rs_code[2] [signal trampoline] | |
772 | struct siginfo rs_info; | |
773 | struct ucontext rs_uc; | |
774 | }; | |
775 | ||
776 | struct ucontext { | |
777 | unsigned long uc_flags; | |
778 | struct ucontext *uc_link; | |
779 | stack_t uc_stack; | |
780 | [Alignment hole of four bytes] | |
781 | struct sigcontext uc_mcontext; | |
782 | sigset_t uc_sigmask; | |
783 | }; */ | |
784 | /* *INDENT-ON* */ | |
785 | ||
786 | #define SIGFRAME_CODE_OFFSET (4 * 4) | |
787 | #define SIGFRAME_SIGCONTEXT_OFFSET (6 * 4) | |
788 | ||
789 | #define RTSIGFRAME_SIGINFO_SIZE 128 | |
790 | #define STACK_T_SIZE (3 * 4) | |
791 | #define UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + STACK_T_SIZE + 4) | |
792 | #define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ | |
793 | + RTSIGFRAME_SIGINFO_SIZE \ | |
794 | + UCONTEXT_SIGCONTEXT_OFFSET) | |
795 | ||
796 | #define SIGCONTEXT_PC (1 * 8) | |
797 | #define SIGCONTEXT_REGS (2 * 8) | |
798 | #define SIGCONTEXT_FPREGS (34 * 8) | |
799 | #define SIGCONTEXT_FPCSR (66 * 8 + 4) | |
800 | #define SIGCONTEXT_HI (69 * 8) | |
801 | #define SIGCONTEXT_LO (70 * 8) | |
802 | #define SIGCONTEXT_CAUSE (71 * 8 + 0) | |
803 | #define SIGCONTEXT_BADVADDR (71 * 8 + 4) | |
804 | ||
805 | #define SIGCONTEXT_REG_SIZE 8 | |
806 | ||
807 | static void | |
808 | mips_linux_o32_sigframe_init (const struct tramp_frame *self, | |
809 | struct frame_info *next_frame, | |
810 | struct trad_frame_cache *this_cache, | |
811 | CORE_ADDR func) | |
812 | { | |
813 | int ireg, reg_position; | |
814 | CORE_ADDR sigcontext_base = func - SIGFRAME_CODE_OFFSET; | |
815 | const struct mips_regnum *regs = mips_regnum (current_gdbarch); | |
37c4d197 | 816 | CORE_ADDR regs_base; |
5792a79b DJ |
817 | |
818 | if (self == &mips_linux_o32_sigframe) | |
819 | sigcontext_base += SIGFRAME_SIGCONTEXT_OFFSET; | |
820 | else | |
821 | sigcontext_base += RTSIGFRAME_SIGCONTEXT_OFFSET; | |
295093a4 MS |
822 | |
823 | /* I'm not proud of this hack. Eventually we will have the | |
824 | infrastructure to indicate the size of saved registers on a | |
825 | per-frame basis, but right now we don't; the kernel saves eight | |
37c4d197 DJ |
826 | bytes but we only want four. Use regs_base to access any |
827 | 64-bit fields. */ | |
5792a79b | 828 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
37c4d197 DJ |
829 | regs_base = sigcontext_base + 4; |
830 | else | |
831 | regs_base = sigcontext_base; | |
5792a79b DJ |
832 | |
833 | #if 0 | |
834 | trad_frame_set_reg_addr (this_cache, ORIG_ZERO_REGNUM + NUM_REGS, | |
37c4d197 | 835 | regs_base + SIGCONTEXT_REGS); |
5792a79b DJ |
836 | #endif |
837 | ||
838 | for (ireg = 1; ireg < 32; ireg++) | |
295093a4 MS |
839 | trad_frame_set_reg_addr (this_cache, |
840 | ireg + MIPS_ZERO_REGNUM + NUM_REGS, | |
37c4d197 | 841 | regs_base + SIGCONTEXT_REGS |
5792a79b DJ |
842 | + ireg * SIGCONTEXT_REG_SIZE); |
843 | ||
37c4d197 DJ |
844 | /* The way that floating point registers are saved, unfortunately, |
845 | depends on the architecture the kernel is built for. For the r3000 and | |
846 | tx39, four bytes of each register are at the beginning of each of the | |
847 | 32 eight byte slots. For everything else, the registers are saved | |
848 | using double precision; only the even-numbered slots are initialized, | |
849 | and the high bits are the odd-numbered register. Assume the latter | |
850 | layout, since we can't tell, and it's much more common. Which bits are | |
851 | the "high" bits depends on endianness. */ | |
5792a79b | 852 | for (ireg = 0; ireg < 32; ireg++) |
37c4d197 DJ |
853 | if ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) != (ireg & 1)) |
854 | trad_frame_set_reg_addr (this_cache, ireg + regs->fp0 + NUM_REGS, | |
855 | sigcontext_base + SIGCONTEXT_FPREGS + 4 | |
856 | + (ireg & ~1) * SIGCONTEXT_REG_SIZE); | |
857 | else | |
858 | trad_frame_set_reg_addr (this_cache, ireg + regs->fp0 + NUM_REGS, | |
859 | sigcontext_base + SIGCONTEXT_FPREGS | |
860 | + (ireg & ~1) * SIGCONTEXT_REG_SIZE); | |
5792a79b DJ |
861 | |
862 | trad_frame_set_reg_addr (this_cache, regs->pc + NUM_REGS, | |
37c4d197 | 863 | regs_base + SIGCONTEXT_PC); |
5792a79b | 864 | |
295093a4 MS |
865 | trad_frame_set_reg_addr (this_cache, |
866 | regs->fp_control_status + NUM_REGS, | |
5792a79b DJ |
867 | sigcontext_base + SIGCONTEXT_FPCSR); |
868 | trad_frame_set_reg_addr (this_cache, regs->hi + NUM_REGS, | |
37c4d197 | 869 | regs_base + SIGCONTEXT_HI); |
5792a79b | 870 | trad_frame_set_reg_addr (this_cache, regs->lo + NUM_REGS, |
37c4d197 | 871 | regs_base + SIGCONTEXT_LO); |
5792a79b DJ |
872 | trad_frame_set_reg_addr (this_cache, regs->cause + NUM_REGS, |
873 | sigcontext_base + SIGCONTEXT_CAUSE); | |
874 | trad_frame_set_reg_addr (this_cache, regs->badvaddr + NUM_REGS, | |
875 | sigcontext_base + SIGCONTEXT_BADVADDR); | |
876 | ||
877 | /* Choice of the bottom of the sigframe is somewhat arbitrary. */ | |
878 | trad_frame_set_id (this_cache, | |
295093a4 MS |
879 | frame_id_build (func - SIGFRAME_CODE_OFFSET, |
880 | func)); | |
5792a79b DJ |
881 | } |
882 | ||
883 | /* *INDENT-OFF* */ | |
884 | /* For N32/N64 things look different. There is no non-rt signal frame. | |
885 | ||
886 | struct rt_sigframe_n32 { | |
887 | u32 rs_ass[4]; [ argument save space for o32 ] | |
888 | u32 rs_code[2]; [ signal trampoline ] | |
889 | struct siginfo rs_info; | |
890 | struct ucontextn32 rs_uc; | |
891 | }; | |
892 | ||
893 | struct ucontextn32 { | |
894 | u32 uc_flags; | |
895 | s32 uc_link; | |
896 | stack32_t uc_stack; | |
897 | struct sigcontext uc_mcontext; | |
898 | sigset_t uc_sigmask; [ mask last for extensibility ] | |
899 | }; | |
295093a4 | 900 | |
5792a79b DJ |
901 | struct rt_sigframe_n32 { |
902 | u32 rs_ass[4]; [ argument save space for o32 ] | |
903 | u32 rs_code[2]; [ signal trampoline ] | |
904 | struct siginfo rs_info; | |
905 | struct ucontext rs_uc; | |
906 | }; | |
907 | ||
908 | struct ucontext { | |
909 | unsigned long uc_flags; | |
910 | struct ucontext *uc_link; | |
911 | stack_t uc_stack; | |
912 | struct sigcontext uc_mcontext; | |
913 | sigset_t uc_sigmask; [ mask last for extensibility ] | |
914 | }; | |
915 | ||
916 | And the sigcontext is different (this is for both n32 and n64): | |
917 | ||
918 | struct sigcontext { | |
919 | unsigned long long sc_regs[32]; | |
920 | unsigned long long sc_fpregs[32]; | |
921 | unsigned long long sc_mdhi; | |
922 | unsigned long long sc_mdlo; | |
923 | unsigned long long sc_pc; | |
924 | unsigned int sc_status; | |
925 | unsigned int sc_fpc_csr; | |
926 | unsigned int sc_fpc_eir; | |
927 | unsigned int sc_used_math; | |
928 | unsigned int sc_cause; | |
929 | unsigned int sc_badvaddr; | |
930 | }; */ | |
931 | /* *INDENT-ON* */ | |
932 | ||
933 | #define N32_STACK_T_SIZE STACK_T_SIZE | |
934 | #define N64_STACK_T_SIZE (2 * 8 + 4) | |
935 | #define N32_UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + N32_STACK_T_SIZE + 4) | |
936 | #define N64_UCONTEXT_SIGCONTEXT_OFFSET (2 * 8 + N64_STACK_T_SIZE + 4) | |
937 | #define N32_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ | |
938 | + RTSIGFRAME_SIGINFO_SIZE \ | |
939 | + N32_UCONTEXT_SIGCONTEXT_OFFSET) | |
940 | #define N64_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ | |
941 | + RTSIGFRAME_SIGINFO_SIZE \ | |
942 | + N64_UCONTEXT_SIGCONTEXT_OFFSET) | |
943 | ||
944 | #define N64_SIGCONTEXT_REGS (0 * 8) | |
945 | #define N64_SIGCONTEXT_FPREGS (32 * 8) | |
946 | #define N64_SIGCONTEXT_HI (64 * 8) | |
947 | #define N64_SIGCONTEXT_LO (65 * 8) | |
948 | #define N64_SIGCONTEXT_PC (66 * 8) | |
949 | #define N64_SIGCONTEXT_FPCSR (67 * 8 + 1 * 4) | |
950 | #define N64_SIGCONTEXT_FIR (67 * 8 + 2 * 4) | |
951 | #define N64_SIGCONTEXT_CAUSE (67 * 8 + 4 * 4) | |
952 | #define N64_SIGCONTEXT_BADVADDR (67 * 8 + 5 * 4) | |
953 | ||
954 | #define N64_SIGCONTEXT_REG_SIZE 8 | |
295093a4 | 955 | |
5792a79b DJ |
956 | static void |
957 | mips_linux_n32n64_sigframe_init (const struct tramp_frame *self, | |
958 | struct frame_info *next_frame, | |
959 | struct trad_frame_cache *this_cache, | |
960 | CORE_ADDR func) | |
961 | { | |
962 | int ireg, reg_position; | |
963 | CORE_ADDR sigcontext_base = func - SIGFRAME_CODE_OFFSET; | |
964 | const struct mips_regnum *regs = mips_regnum (current_gdbarch); | |
965 | ||
966 | if (self == &mips_linux_n32_rt_sigframe) | |
967 | sigcontext_base += N32_SIGFRAME_SIGCONTEXT_OFFSET; | |
968 | else | |
969 | sigcontext_base += N64_SIGFRAME_SIGCONTEXT_OFFSET; | |
295093a4 | 970 | |
5792a79b DJ |
971 | #if 0 |
972 | trad_frame_set_reg_addr (this_cache, ORIG_ZERO_REGNUM + NUM_REGS, | |
973 | sigcontext_base + N64_SIGCONTEXT_REGS); | |
974 | #endif | |
975 | ||
976 | for (ireg = 1; ireg < 32; ireg++) | |
295093a4 MS |
977 | trad_frame_set_reg_addr (this_cache, |
978 | ireg + MIPS_ZERO_REGNUM + NUM_REGS, | |
5792a79b DJ |
979 | sigcontext_base + N64_SIGCONTEXT_REGS |
980 | + ireg * N64_SIGCONTEXT_REG_SIZE); | |
981 | ||
982 | for (ireg = 0; ireg < 32; ireg++) | |
983 | trad_frame_set_reg_addr (this_cache, ireg + regs->fp0 + NUM_REGS, | |
984 | sigcontext_base + N64_SIGCONTEXT_FPREGS | |
985 | + ireg * N64_SIGCONTEXT_REG_SIZE); | |
986 | ||
987 | trad_frame_set_reg_addr (this_cache, regs->pc + NUM_REGS, | |
988 | sigcontext_base + N64_SIGCONTEXT_PC); | |
989 | ||
295093a4 MS |
990 | trad_frame_set_reg_addr (this_cache, |
991 | regs->fp_control_status + NUM_REGS, | |
5792a79b DJ |
992 | sigcontext_base + N64_SIGCONTEXT_FPCSR); |
993 | trad_frame_set_reg_addr (this_cache, regs->hi + NUM_REGS, | |
994 | sigcontext_base + N64_SIGCONTEXT_HI); | |
995 | trad_frame_set_reg_addr (this_cache, regs->lo + NUM_REGS, | |
996 | sigcontext_base + N64_SIGCONTEXT_LO); | |
997 | trad_frame_set_reg_addr (this_cache, regs->cause + NUM_REGS, | |
998 | sigcontext_base + N64_SIGCONTEXT_CAUSE); | |
999 | trad_frame_set_reg_addr (this_cache, regs->badvaddr + NUM_REGS, | |
1000 | sigcontext_base + N64_SIGCONTEXT_BADVADDR); | |
1001 | ||
1002 | /* Choice of the bottom of the sigframe is somewhat arbitrary. */ | |
1003 | trad_frame_set_id (this_cache, | |
295093a4 MS |
1004 | frame_id_build (func - SIGFRAME_CODE_OFFSET, |
1005 | func)); | |
5792a79b DJ |
1006 | } |
1007 | ||
9f62d0e2 | 1008 | |
5792a79b DJ |
1009 | /* Initialize one of the GNU/Linux OS ABIs. */ |
1010 | ||
19ed69dd | 1011 | static void |
295093a4 MS |
1012 | mips_linux_init_abi (struct gdbarch_info info, |
1013 | struct gdbarch *gdbarch) | |
19ed69dd | 1014 | { |
96f026fc KB |
1015 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1016 | enum mips_abi abi = mips_abi (gdbarch); | |
1017 | ||
1018 | switch (abi) | |
1019 | { | |
1020 | case MIPS_ABI_O32: | |
1021 | set_gdbarch_get_longjmp_target (gdbarch, | |
1022 | mips_linux_get_longjmp_target); | |
1023 | set_solib_svr4_fetch_link_map_offsets | |
76a9d10f | 1024 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); |
fb2be677 AC |
1025 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_sigframe); |
1026 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_rt_sigframe); | |
96f026fc KB |
1027 | break; |
1028 | case MIPS_ABI_N32: | |
1029 | set_gdbarch_get_longjmp_target (gdbarch, | |
1030 | mips_linux_get_longjmp_target); | |
1031 | set_solib_svr4_fetch_link_map_offsets | |
76a9d10f | 1032 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); |
d05f6826 DJ |
1033 | set_gdbarch_long_double_bit (gdbarch, 128); |
1034 | /* These floatformats should probably be renamed. MIPS uses | |
1035 | the same 128-bit IEEE floating point format that IA-64 uses, | |
1036 | except that the quiet/signalling NaN bit is reversed (GDB | |
1037 | does not distinguish between quiet and signalling NaNs). */ | |
8da61cc4 | 1038 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); |
fb2be677 | 1039 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n32_rt_sigframe); |
96f026fc KB |
1040 | break; |
1041 | case MIPS_ABI_N64: | |
1042 | set_gdbarch_get_longjmp_target (gdbarch, | |
1043 | mips64_linux_get_longjmp_target); | |
1044 | set_solib_svr4_fetch_link_map_offsets | |
76a9d10f | 1045 | (gdbarch, svr4_lp64_fetch_link_map_offsets); |
d05f6826 DJ |
1046 | set_gdbarch_long_double_bit (gdbarch, 128); |
1047 | /* These floatformats should probably be renamed. MIPS uses | |
1048 | the same 128-bit IEEE floating point format that IA-64 uses, | |
1049 | except that the quiet/signalling NaN bit is reversed (GDB | |
1050 | does not distinguish between quiet and signalling NaNs). */ | |
8da61cc4 | 1051 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); |
fb2be677 | 1052 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n64_rt_sigframe); |
96f026fc KB |
1053 | break; |
1054 | default: | |
e2e0b3e5 | 1055 | internal_error (__FILE__, __LINE__, _("can't handle ABI")); |
96f026fc KB |
1056 | break; |
1057 | } | |
6de918a6 | 1058 | |
982e9687 | 1059 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
6de918a6 DJ |
1060 | set_gdbarch_skip_solib_resolver (gdbarch, mips_linux_skip_resolver); |
1061 | ||
0d0266c6 | 1062 | set_gdbarch_software_single_step (gdbarch, mips_software_single_step); |
b2756930 KB |
1063 | |
1064 | /* Enable TLS support. */ | |
1065 | set_gdbarch_fetch_tls_load_module_address (gdbarch, | |
1066 | svr4_fetch_objfile_link_map); | |
7d522c90 DJ |
1067 | |
1068 | /* Initialize this lazily, to avoid an initialization order | |
1069 | dependency on solib-svr4.c's _initialize routine. */ | |
1070 | if (mips_svr4_so_ops.in_dynsym_resolve_code == NULL) | |
1071 | { | |
1072 | mips_svr4_so_ops = svr4_so_ops; | |
1073 | mips_svr4_so_ops.in_dynsym_resolve_code | |
1074 | = mips_linux_in_dynsym_resolve_code; | |
1075 | } | |
1076 | set_solib_ops (gdbarch, &mips_svr4_so_ops); | |
19ed69dd KB |
1077 | } |
1078 | ||
2aa830e4 | 1079 | void |
d1bacddc | 1080 | _initialize_mips_linux_tdep (void) |
2aa830e4 | 1081 | { |
96f026fc KB |
1082 | const struct bfd_arch_info *arch_info; |
1083 | ||
96f026fc KB |
1084 | for (arch_info = bfd_lookup_arch (bfd_arch_mips, 0); |
1085 | arch_info != NULL; | |
1086 | arch_info = arch_info->next) | |
1087 | { | |
295093a4 MS |
1088 | gdbarch_register_osabi (bfd_arch_mips, arch_info->mach, |
1089 | GDB_OSABI_LINUX, | |
96f026fc KB |
1090 | mips_linux_init_abi); |
1091 | } | |
1092 | ||
00e32a35 | 1093 | deprecated_add_core_fns (®set_core_fns); |
2aa830e4 | 1094 | } |