Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
0b302171 | 3 | Copyright (C) 1988-2012 Free Software Foundation, Inc. |
bf64bfd6 | 4 | |
c906108c SS |
5 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
6 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
7 | ||
c5aa993b | 8 | This file is part of GDB. |
c906108c | 9 | |
c5aa993b JM |
10 | This program is free software; you can redistribute it and/or modify |
11 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 12 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 13 | (at your option) any later version. |
c906108c | 14 | |
c5aa993b JM |
15 | This program is distributed in the hope that it will be useful, |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
c906108c | 19 | |
c5aa993b | 20 | You should have received a copy of the GNU General Public License |
a9762ec7 | 21 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
22 | |
23 | #include "defs.h" | |
24 | #include "gdb_string.h" | |
5e2e9765 | 25 | #include "gdb_assert.h" |
c906108c SS |
26 | #include "frame.h" |
27 | #include "inferior.h" | |
28 | #include "symtab.h" | |
29 | #include "value.h" | |
30 | #include "gdbcmd.h" | |
31 | #include "language.h" | |
32 | #include "gdbcore.h" | |
33 | #include "symfile.h" | |
34 | #include "objfiles.h" | |
35 | #include "gdbtypes.h" | |
36 | #include "target.h" | |
28d069e6 | 37 | #include "arch-utils.h" |
4e052eda | 38 | #include "regcache.h" |
70f80edf | 39 | #include "osabi.h" |
d1973055 | 40 | #include "mips-tdep.h" |
fe898f56 | 41 | #include "block.h" |
a4b8ebc8 | 42 | #include "reggroups.h" |
c906108c | 43 | #include "opcode/mips.h" |
c2d11a7d JM |
44 | #include "elf/mips.h" |
45 | #include "elf-bfd.h" | |
2475bac3 | 46 | #include "symcat.h" |
a4b8ebc8 | 47 | #include "sim-regno.h" |
a89aa300 | 48 | #include "dis-asm.h" |
edfae063 AC |
49 | #include "frame-unwind.h" |
50 | #include "frame-base.h" | |
51 | #include "trad-frame.h" | |
7d9b040b | 52 | #include "infcall.h" |
fed7ba43 | 53 | #include "floatformat.h" |
29709017 DJ |
54 | #include "remote.h" |
55 | #include "target-descriptions.h" | |
2bd0c3d7 | 56 | #include "dwarf2-frame.h" |
f8b73d13 | 57 | #include "user-regs.h" |
79a45b7d | 58 | #include "valprint.h" |
175ff332 | 59 | #include "ax.h" |
c906108c | 60 | |
8d5f9dcb DJ |
61 | static const struct objfile_data *mips_pdr_data; |
62 | ||
5bbcb741 | 63 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 64 | |
4cc0665f MR |
65 | static int mips32_instruction_has_delay_slot (struct gdbarch *, CORE_ADDR); |
66 | static int micromips_instruction_has_delay_slot (struct gdbarch *, CORE_ADDR, | |
67 | int); | |
68 | static int mips16_instruction_has_delay_slot (struct gdbarch *, CORE_ADDR, | |
69 | int); | |
70 | ||
24e05951 | 71 | /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ |
dd824b04 DJ |
72 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ |
73 | #define ST0_FR (1 << 26) | |
74 | ||
b0069a17 AC |
75 | /* The sizes of floating point registers. */ |
76 | ||
77 | enum | |
78 | { | |
79 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
80 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
81 | }; | |
82 | ||
1a69e1e4 DJ |
83 | enum |
84 | { | |
85 | MIPS32_REGSIZE = 4, | |
86 | MIPS64_REGSIZE = 8 | |
87 | }; | |
0dadbba0 | 88 | |
2e4ebe70 DJ |
89 | static const char *mips_abi_string; |
90 | ||
40478521 | 91 | static const char *const mips_abi_strings[] = { |
2e4ebe70 DJ |
92 | "auto", |
93 | "n32", | |
94 | "o32", | |
28d169de | 95 | "n64", |
2e4ebe70 DJ |
96 | "o64", |
97 | "eabi32", | |
98 | "eabi64", | |
99 | NULL | |
100 | }; | |
101 | ||
4cc0665f MR |
102 | /* For backwards compatibility we default to MIPS16. This flag is |
103 | overridden as soon as unambiguous ELF file flags tell us the | |
104 | compressed ISA encoding used. */ | |
105 | static const char mips_compression_mips16[] = "mips16"; | |
106 | static const char mips_compression_micromips[] = "micromips"; | |
107 | static const char *const mips_compression_strings[] = | |
108 | { | |
109 | mips_compression_mips16, | |
110 | mips_compression_micromips, | |
111 | NULL | |
112 | }; | |
113 | ||
114 | static const char *mips_compression_string = mips_compression_mips16; | |
115 | ||
f8b73d13 DJ |
116 | /* The standard register names, and all the valid aliases for them. */ |
117 | struct register_alias | |
118 | { | |
119 | const char *name; | |
120 | int regnum; | |
121 | }; | |
122 | ||
123 | /* Aliases for o32 and most other ABIs. */ | |
124 | const struct register_alias mips_o32_aliases[] = { | |
125 | { "ta0", 12 }, | |
126 | { "ta1", 13 }, | |
127 | { "ta2", 14 }, | |
128 | { "ta3", 15 } | |
129 | }; | |
130 | ||
131 | /* Aliases for n32 and n64. */ | |
132 | const struct register_alias mips_n32_n64_aliases[] = { | |
133 | { "ta0", 8 }, | |
134 | { "ta1", 9 }, | |
135 | { "ta2", 10 }, | |
136 | { "ta3", 11 } | |
137 | }; | |
138 | ||
139 | /* Aliases for ABI-independent registers. */ | |
140 | const struct register_alias mips_register_aliases[] = { | |
141 | /* The architecture manuals specify these ABI-independent names for | |
142 | the GPRs. */ | |
143 | #define R(n) { "r" #n, n } | |
144 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
145 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
146 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
147 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
148 | #undef R | |
149 | ||
150 | /* k0 and k1 are sometimes called these instead (for "kernel | |
151 | temp"). */ | |
152 | { "kt0", 26 }, | |
153 | { "kt1", 27 }, | |
154 | ||
155 | /* This is the traditional GDB name for the CP0 status register. */ | |
156 | { "sr", MIPS_PS_REGNUM }, | |
157 | ||
158 | /* This is the traditional GDB name for the CP0 BadVAddr register. */ | |
159 | { "bad", MIPS_EMBED_BADVADDR_REGNUM }, | |
160 | ||
161 | /* This is the traditional GDB name for the FCSR. */ | |
162 | { "fsr", MIPS_EMBED_FP0_REGNUM + 32 } | |
163 | }; | |
164 | ||
865093a3 AR |
165 | const struct register_alias mips_numeric_register_aliases[] = { |
166 | #define R(n) { #n, n } | |
167 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
168 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
169 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
170 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
171 | #undef R | |
172 | }; | |
173 | ||
c906108c SS |
174 | #ifndef MIPS_DEFAULT_FPU_TYPE |
175 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
176 | #endif | |
177 | static int mips_fpu_type_auto = 1; | |
178 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 179 | |
9ace0497 | 180 | static int mips_debug = 0; |
7a292a7a | 181 | |
29709017 DJ |
182 | /* Properties (for struct target_desc) describing the g/G packet |
183 | layout. */ | |
184 | #define PROPERTY_GP32 "internal: transfers-32bit-registers" | |
185 | #define PROPERTY_GP64 "internal: transfers-64bit-registers" | |
186 | ||
4eb0ad19 DJ |
187 | struct target_desc *mips_tdesc_gp32; |
188 | struct target_desc *mips_tdesc_gp64; | |
189 | ||
56cea623 AC |
190 | const struct mips_regnum * |
191 | mips_regnum (struct gdbarch *gdbarch) | |
192 | { | |
193 | return gdbarch_tdep (gdbarch)->regnum; | |
194 | } | |
195 | ||
196 | static int | |
197 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
198 | { | |
199 | return mips_regnum (gdbarch)->fp0 + 12; | |
200 | } | |
201 | ||
004159a2 MR |
202 | /* Return 1 if REGNUM refers to a floating-point general register, raw |
203 | or cooked. Otherwise return 0. */ | |
204 | ||
205 | static int | |
206 | mips_float_register_p (struct gdbarch *gdbarch, int regnum) | |
207 | { | |
208 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
209 | ||
210 | return (rawnum >= mips_regnum (gdbarch)->fp0 | |
211 | && rawnum < mips_regnum (gdbarch)->fp0 + 32); | |
212 | } | |
213 | ||
74ed0bb4 MD |
214 | #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \ |
215 | == MIPS_ABI_EABI32 \ | |
216 | || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64) | |
c2d11a7d | 217 | |
025bb325 MS |
218 | #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \ |
219 | (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum) | |
c2d11a7d | 220 | |
025bb325 MS |
221 | #define MIPS_LAST_ARG_REGNUM(gdbarch) \ |
222 | (gdbarch_tdep (gdbarch)->mips_last_arg_regnum) | |
c2d11a7d | 223 | |
74ed0bb4 | 224 | #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type) |
c2d11a7d | 225 | |
d1973055 KB |
226 | /* Return the MIPS ABI associated with GDBARCH. */ |
227 | enum mips_abi | |
228 | mips_abi (struct gdbarch *gdbarch) | |
229 | { | |
230 | return gdbarch_tdep (gdbarch)->mips_abi; | |
231 | } | |
232 | ||
4246e332 | 233 | int |
1b13c4f6 | 234 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 | 235 | { |
29709017 DJ |
236 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
237 | ||
238 | /* If we know how big the registers are, use that size. */ | |
239 | if (tdep->register_size_valid_p) | |
240 | return tdep->register_size; | |
241 | ||
242 | /* Fall back to the previous behavior. */ | |
4246e332 AC |
243 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word |
244 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
245 | } | |
246 | ||
025bb325 | 247 | /* Return the currently configured (or set) saved register size. */ |
480d3dd2 | 248 | |
e6bc2e8a | 249 | unsigned int |
13326b4e | 250 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 251 | { |
1a69e1e4 DJ |
252 | switch (mips_abi (gdbarch)) |
253 | { | |
254 | case MIPS_ABI_EABI32: | |
255 | case MIPS_ABI_O32: | |
256 | return 4; | |
257 | case MIPS_ABI_N32: | |
258 | case MIPS_ABI_N64: | |
259 | case MIPS_ABI_O64: | |
260 | case MIPS_ABI_EABI64: | |
261 | return 8; | |
262 | case MIPS_ABI_UNKNOWN: | |
263 | case MIPS_ABI_LAST: | |
264 | default: | |
265 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
266 | } | |
d929b26f AC |
267 | } |
268 | ||
4cc0665f MR |
269 | /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here |
270 | are some functions to handle addresses associated with compressed | |
271 | code including but not limited to testing, setting, or clearing | |
272 | bit 0 of such addresses. */ | |
742c84f6 | 273 | |
4cc0665f MR |
274 | /* Return one iff compressed code is the MIPS16 instruction set. */ |
275 | ||
276 | static int | |
277 | is_mips16_isa (struct gdbarch *gdbarch) | |
278 | { | |
279 | return gdbarch_tdep (gdbarch)->mips_isa == ISA_MIPS16; | |
280 | } | |
281 | ||
282 | /* Return one iff compressed code is the microMIPS instruction set. */ | |
283 | ||
284 | static int | |
285 | is_micromips_isa (struct gdbarch *gdbarch) | |
286 | { | |
287 | return gdbarch_tdep (gdbarch)->mips_isa == ISA_MICROMIPS; | |
288 | } | |
289 | ||
290 | /* Return one iff ADDR denotes compressed code. */ | |
291 | ||
292 | static int | |
293 | is_compact_addr (CORE_ADDR addr) | |
742c84f6 MR |
294 | { |
295 | return ((addr) & 1); | |
296 | } | |
297 | ||
4cc0665f MR |
298 | /* Return one iff ADDR denotes standard ISA code. */ |
299 | ||
300 | static int | |
301 | is_mips_addr (CORE_ADDR addr) | |
302 | { | |
303 | return !is_compact_addr (addr); | |
304 | } | |
305 | ||
306 | /* Return one iff ADDR denotes MIPS16 code. */ | |
307 | ||
308 | static int | |
309 | is_mips16_addr (struct gdbarch *gdbarch, CORE_ADDR addr) | |
310 | { | |
311 | return is_compact_addr (addr) && is_mips16_isa (gdbarch); | |
312 | } | |
313 | ||
314 | /* Return one iff ADDR denotes microMIPS code. */ | |
315 | ||
316 | static int | |
317 | is_micromips_addr (struct gdbarch *gdbarch, CORE_ADDR addr) | |
318 | { | |
319 | return is_compact_addr (addr) && is_micromips_isa (gdbarch); | |
320 | } | |
321 | ||
322 | /* Strip the ISA (compression) bit off from ADDR. */ | |
323 | ||
742c84f6 | 324 | static CORE_ADDR |
4cc0665f | 325 | unmake_compact_addr (CORE_ADDR addr) |
742c84f6 MR |
326 | { |
327 | return ((addr) & ~(CORE_ADDR) 1); | |
328 | } | |
329 | ||
4cc0665f MR |
330 | /* Add the ISA (compression) bit to ADDR. */ |
331 | ||
742c84f6 | 332 | static CORE_ADDR |
4cc0665f | 333 | make_compact_addr (CORE_ADDR addr) |
742c84f6 MR |
334 | { |
335 | return ((addr) | (CORE_ADDR) 1); | |
336 | } | |
337 | ||
71b8ef93 | 338 | /* Functions for setting and testing a bit in a minimal symbol that |
4cc0665f MR |
339 | marks it as MIPS16 or microMIPS function. The MSB of the minimal |
340 | symbol's "info" field is used for this purpose. | |
5a89d8aa | 341 | |
4cc0665f MR |
342 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is |
343 | "special", i.e. refers to a MIPS16 or microMIPS function, and sets | |
344 | one of the "special" bits in a minimal symbol to mark it accordingly. | |
345 | The test checks an ELF-private flag that is valid for true function | |
346 | symbols only; in particular synthetic symbols such as for PLT stubs | |
347 | have no ELF-private part at all. | |
5a89d8aa | 348 | |
4cc0665f MR |
349 | msymbol_is_mips16 and msymbol_is_micromips test the "special" bit |
350 | in a minimal symbol. */ | |
5a89d8aa | 351 | |
5a89d8aa | 352 | static void |
6d82d43b AC |
353 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
354 | { | |
4cc0665f MR |
355 | elf_symbol_type *elfsym = (elf_symbol_type *) sym; |
356 | ||
357 | if ((sym->flags & BSF_SYNTHETIC) != 0) | |
358 | return; | |
359 | ||
360 | if (ELF_ST_IS_MICROMIPS (elfsym->internal_elf_sym.st_other)) | |
361 | MSYMBOL_TARGET_FLAG_2 (msym) = 1; | |
362 | else if (ELF_ST_IS_MIPS16 (elfsym->internal_elf_sym.st_other)) | |
363 | MSYMBOL_TARGET_FLAG_1 (msym) = 1; | |
364 | } | |
365 | ||
366 | /* Return one iff MSYM refers to standard ISA code. */ | |
367 | ||
368 | static int | |
369 | msymbol_is_mips (struct minimal_symbol *msym) | |
370 | { | |
371 | return !(MSYMBOL_TARGET_FLAG_1 (msym) | MSYMBOL_TARGET_FLAG_2 (msym)); | |
5a89d8aa MS |
372 | } |
373 | ||
4cc0665f MR |
374 | /* Return one iff MSYM refers to MIPS16 code. */ |
375 | ||
71b8ef93 | 376 | static int |
4cc0665f | 377 | msymbol_is_mips16 (struct minimal_symbol *msym) |
71b8ef93 | 378 | { |
b887350f | 379 | return MSYMBOL_TARGET_FLAG_1 (msym); |
71b8ef93 MS |
380 | } |
381 | ||
4cc0665f MR |
382 | /* Return one iff MSYM refers to microMIPS code. */ |
383 | ||
384 | static int | |
385 | msymbol_is_micromips (struct minimal_symbol *msym) | |
386 | { | |
387 | return MSYMBOL_TARGET_FLAG_2 (msym); | |
388 | } | |
389 | ||
88658117 AC |
390 | /* XFER a value from the big/little/left end of the register. |
391 | Depending on the size of the value it might occupy the entire | |
392 | register or just part of it. Make an allowance for this, aligning | |
393 | things accordingly. */ | |
394 | ||
395 | static void | |
ba32f989 DJ |
396 | mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache, |
397 | int reg_num, int length, | |
870cd05e MK |
398 | enum bfd_endian endian, gdb_byte *in, |
399 | const gdb_byte *out, int buf_offset) | |
88658117 | 400 | { |
88658117 | 401 | int reg_offset = 0; |
72a155b4 UW |
402 | |
403 | gdb_assert (reg_num >= gdbarch_num_regs (gdbarch)); | |
cb1d2653 AC |
404 | /* Need to transfer the left or right part of the register, based on |
405 | the targets byte order. */ | |
88658117 AC |
406 | switch (endian) |
407 | { | |
408 | case BFD_ENDIAN_BIG: | |
72a155b4 | 409 | reg_offset = register_size (gdbarch, reg_num) - length; |
88658117 AC |
410 | break; |
411 | case BFD_ENDIAN_LITTLE: | |
412 | reg_offset = 0; | |
413 | break; | |
6d82d43b | 414 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
415 | reg_offset = 0; |
416 | break; | |
417 | default: | |
e2e0b3e5 | 418 | internal_error (__FILE__, __LINE__, _("bad switch")); |
88658117 AC |
419 | } |
420 | if (mips_debug) | |
cb1d2653 AC |
421 | fprintf_unfiltered (gdb_stderr, |
422 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
423 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
424 | if (mips_debug && out != NULL) |
425 | { | |
426 | int i; | |
cb1d2653 | 427 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 428 | for (i = 0; i < length; i++) |
cb1d2653 | 429 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
430 | } |
431 | if (in != NULL) | |
6d82d43b AC |
432 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
433 | in + buf_offset); | |
88658117 | 434 | if (out != NULL) |
6d82d43b AC |
435 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
436 | out + buf_offset); | |
88658117 AC |
437 | if (mips_debug && in != NULL) |
438 | { | |
439 | int i; | |
cb1d2653 | 440 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 441 | for (i = 0; i < length; i++) |
cb1d2653 | 442 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
443 | } |
444 | if (mips_debug) | |
445 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
446 | } | |
447 | ||
dd824b04 DJ |
448 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
449 | compatiblity mode. A return value of 1 means that we have | |
450 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
451 | ||
452 | static int | |
9c9acae0 | 453 | mips2_fp_compat (struct frame_info *frame) |
dd824b04 | 454 | { |
72a155b4 | 455 | struct gdbarch *gdbarch = get_frame_arch (frame); |
dd824b04 DJ |
456 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not |
457 | meaningful. */ | |
72a155b4 | 458 | if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4) |
dd824b04 DJ |
459 | return 0; |
460 | ||
461 | #if 0 | |
462 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
463 | in all the places we deal with FP registers. PR gdb/413. */ | |
464 | /* Otherwise check the FR bit in the status register - it controls | |
465 | the FP compatiblity mode. If it is clear we are in compatibility | |
466 | mode. */ | |
9c9acae0 | 467 | if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0) |
dd824b04 DJ |
468 | return 1; |
469 | #endif | |
361d1df0 | 470 | |
dd824b04 DJ |
471 | return 0; |
472 | } | |
473 | ||
7a292a7a | 474 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 475 | |
74ed0bb4 | 476 | static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR); |
c906108c | 477 | |
a14ed312 | 478 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 479 | |
025bb325 | 480 | /* The list of available "set mips " and "show mips " commands. */ |
acdb74a0 AC |
481 | |
482 | static struct cmd_list_element *setmipscmdlist = NULL; | |
483 | static struct cmd_list_element *showmipscmdlist = NULL; | |
484 | ||
5e2e9765 KB |
485 | /* Integer registers 0 thru 31 are handled explicitly by |
486 | mips_register_name(). Processor specific registers 32 and above | |
8a9fc081 | 487 | are listed in the following tables. */ |
691c0433 | 488 | |
6d82d43b AC |
489 | enum |
490 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
491 | |
492 | /* Generic MIPS. */ | |
493 | ||
494 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
495 | "sr", "lo", "hi", "bad", "cause", "pc", |
496 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
497 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
498 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
499 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
1faeff08 | 500 | "fsr", "fir", |
691c0433 AC |
501 | }; |
502 | ||
503 | /* Names of IDT R3041 registers. */ | |
504 | ||
505 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
506 | "sr", "lo", "hi", "bad", "cause", "pc", |
507 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
508 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
509 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
510 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
511 | "fsr", "fir", "", /*"fp" */ "", | |
512 | "", "", "bus", "ccfg", "", "", "", "", | |
513 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
514 | }; |
515 | ||
516 | /* Names of tx39 registers. */ | |
517 | ||
518 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
519 | "sr", "lo", "hi", "bad", "cause", "pc", |
520 | "", "", "", "", "", "", "", "", | |
521 | "", "", "", "", "", "", "", "", | |
522 | "", "", "", "", "", "", "", "", | |
523 | "", "", "", "", "", "", "", "", | |
524 | "", "", "", "", | |
525 | "", "", "", "", "", "", "", "", | |
1faeff08 | 526 | "", "", "config", "cache", "debug", "depc", "epc", |
691c0433 AC |
527 | }; |
528 | ||
529 | /* Names of IRIX registers. */ | |
530 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
531 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
532 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
533 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
534 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
535 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
536 | }; |
537 | ||
44099a67 | 538 | /* Names of registers with Linux kernels. */ |
1faeff08 MR |
539 | static const char *mips_linux_reg_names[NUM_MIPS_PROCESSOR_REGS] = { |
540 | "sr", "lo", "hi", "bad", "cause", "pc", | |
541 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
542 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
543 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
544 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
545 | "fsr", "fir" | |
546 | }; | |
547 | ||
cce74817 | 548 | |
5e2e9765 | 549 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 550 | static const char * |
d93859e2 | 551 | mips_register_name (struct gdbarch *gdbarch, int regno) |
cce74817 | 552 | { |
d93859e2 | 553 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
5e2e9765 KB |
554 | /* GPR names for all ABIs other than n32/n64. */ |
555 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
556 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
557 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
558 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
559 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
560 | }; |
561 | ||
562 | /* GPR names for n32 and n64 ABIs. */ | |
563 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
564 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
565 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
566 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
567 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
568 | }; |
569 | ||
d93859e2 | 570 | enum mips_abi abi = mips_abi (gdbarch); |
5e2e9765 | 571 | |
f57d151a | 572 | /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, |
6229fbea HZ |
573 | but then don't make the raw register names visible. This (upper) |
574 | range of user visible register numbers are the pseudo-registers. | |
575 | ||
576 | This approach was adopted accommodate the following scenario: | |
577 | It is possible to debug a 64-bit device using a 32-bit | |
578 | programming model. In such instances, the raw registers are | |
579 | configured to be 64-bits wide, while the pseudo registers are | |
580 | configured to be 32-bits wide. The registers that the user | |
581 | sees - the pseudo registers - match the users expectations | |
582 | given the programming model being used. */ | |
d93859e2 UW |
583 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
584 | if (regno < gdbarch_num_regs (gdbarch)) | |
a4b8ebc8 AC |
585 | return ""; |
586 | ||
5e2e9765 KB |
587 | /* The MIPS integer registers are always mapped from 0 to 31. The |
588 | names of the registers (which reflects the conventions regarding | |
589 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 590 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
591 | { |
592 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 593 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 594 | else |
a4b8ebc8 | 595 | return mips_gpr_names[rawnum]; |
5e2e9765 | 596 | } |
d93859e2 UW |
597 | else if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
598 | return tdesc_register_name (gdbarch, rawnum); | |
599 | else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch)) | |
691c0433 AC |
600 | { |
601 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
1faeff08 MR |
602 | if (tdep->mips_processor_reg_names[rawnum - 32]) |
603 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
604 | return ""; | |
691c0433 | 605 | } |
5e2e9765 KB |
606 | else |
607 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 608 | _("mips_register_name: bad register number %d"), rawnum); |
cce74817 | 609 | } |
5e2e9765 | 610 | |
a4b8ebc8 | 611 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 612 | |
a4b8ebc8 AC |
613 | static int |
614 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
615 | struct reggroup *reggroup) | |
616 | { | |
617 | int vector_p; | |
618 | int float_p; | |
619 | int raw_p; | |
72a155b4 UW |
620 | int rawnum = regnum % gdbarch_num_regs (gdbarch); |
621 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
a4b8ebc8 AC |
622 | if (reggroup == all_reggroup) |
623 | return pseudo; | |
624 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
625 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
626 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
627 | (gdbarch), as not all architectures are multi-arch. */ | |
72a155b4 UW |
628 | raw_p = rawnum < gdbarch_num_regs (gdbarch); |
629 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
630 | || gdbarch_register_name (gdbarch, regnum)[0] == '\0') | |
a4b8ebc8 AC |
631 | return 0; |
632 | if (reggroup == float_reggroup) | |
633 | return float_p && pseudo; | |
634 | if (reggroup == vector_reggroup) | |
635 | return vector_p && pseudo; | |
636 | if (reggroup == general_reggroup) | |
637 | return (!vector_p && !float_p) && pseudo; | |
638 | /* Save the pseudo registers. Need to make certain that any code | |
639 | extracting register values from a saved register cache also uses | |
640 | pseudo registers. */ | |
641 | if (reggroup == save_reggroup) | |
642 | return raw_p && pseudo; | |
643 | /* Restore the same pseudo register. */ | |
644 | if (reggroup == restore_reggroup) | |
645 | return raw_p && pseudo; | |
6d82d43b | 646 | return 0; |
a4b8ebc8 AC |
647 | } |
648 | ||
f8b73d13 DJ |
649 | /* Return the groups that a MIPS register can be categorised into. |
650 | This version is only used if we have a target description which | |
651 | describes real registers (and their groups). */ | |
652 | ||
653 | static int | |
654 | mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
655 | struct reggroup *reggroup) | |
656 | { | |
657 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
658 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
659 | int ret; | |
660 | ||
661 | /* Only save, restore, and display the pseudo registers. Need to | |
662 | make certain that any code extracting register values from a | |
663 | saved register cache also uses pseudo registers. | |
664 | ||
665 | Note: saving and restoring the pseudo registers is slightly | |
666 | strange; if we have 64 bits, we should save and restore all | |
667 | 64 bits. But this is hard and has little benefit. */ | |
668 | if (!pseudo) | |
669 | return 0; | |
670 | ||
671 | ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup); | |
672 | if (ret != -1) | |
673 | return ret; | |
674 | ||
675 | return mips_register_reggroup_p (gdbarch, regnum, reggroup); | |
676 | } | |
677 | ||
a4b8ebc8 | 678 | /* Map the symbol table registers which live in the range [1 * |
f57d151a | 679 | gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw |
47ebcfbe | 680 | registers. Take care of alignment and size problems. */ |
c5aa993b | 681 | |
05d1431c | 682 | static enum register_status |
a4b8ebc8 | 683 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
47a35522 | 684 | int cookednum, gdb_byte *buf) |
a4b8ebc8 | 685 | { |
72a155b4 UW |
686 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
687 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
688 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 689 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
05d1431c | 690 | return regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
691 | else if (register_size (gdbarch, rawnum) > |
692 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 693 | { |
8bdf35dc | 694 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
05d1431c | 695 | return regcache_raw_read_part (regcache, rawnum, 0, 4, buf); |
47ebcfbe | 696 | else |
8bdf35dc KB |
697 | { |
698 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
699 | LONGEST regval; | |
05d1431c PA |
700 | enum register_status status; |
701 | ||
702 | status = regcache_raw_read_signed (regcache, rawnum, ®val); | |
703 | if (status == REG_VALID) | |
704 | store_signed_integer (buf, 4, byte_order, regval); | |
705 | return status; | |
8bdf35dc | 706 | } |
47ebcfbe AC |
707 | } |
708 | else | |
e2e0b3e5 | 709 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 AC |
710 | } |
711 | ||
712 | static void | |
6d82d43b AC |
713 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
714 | struct regcache *regcache, int cookednum, | |
47a35522 | 715 | const gdb_byte *buf) |
a4b8ebc8 | 716 | { |
72a155b4 UW |
717 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
718 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
719 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 720 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 721 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
722 | else if (register_size (gdbarch, rawnum) > |
723 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 724 | { |
8bdf35dc | 725 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
47ebcfbe AC |
726 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); |
727 | else | |
8bdf35dc KB |
728 | { |
729 | /* Sign extend the shortened version of the register prior | |
730 | to placing it in the raw register. This is required for | |
731 | some mips64 parts in order to avoid unpredictable behavior. */ | |
732 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
733 | LONGEST regval = extract_signed_integer (buf, 4, byte_order); | |
734 | regcache_raw_write_signed (regcache, rawnum, regval); | |
735 | } | |
47ebcfbe AC |
736 | } |
737 | else | |
e2e0b3e5 | 738 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 | 739 | } |
c5aa993b | 740 | |
175ff332 HZ |
741 | static int |
742 | mips_ax_pseudo_register_collect (struct gdbarch *gdbarch, | |
743 | struct agent_expr *ax, int reg) | |
744 | { | |
745 | int rawnum = reg % gdbarch_num_regs (gdbarch); | |
746 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) | |
747 | && reg < 2 * gdbarch_num_regs (gdbarch)); | |
748 | ||
749 | ax_reg_mask (ax, rawnum); | |
750 | ||
751 | return 0; | |
752 | } | |
753 | ||
754 | static int | |
755 | mips_ax_pseudo_register_push_stack (struct gdbarch *gdbarch, | |
756 | struct agent_expr *ax, int reg) | |
757 | { | |
758 | int rawnum = reg % gdbarch_num_regs (gdbarch); | |
759 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) | |
760 | && reg < 2 * gdbarch_num_regs (gdbarch)); | |
761 | if (register_size (gdbarch, rawnum) >= register_size (gdbarch, reg)) | |
762 | { | |
763 | ax_reg (ax, rawnum); | |
764 | ||
765 | if (register_size (gdbarch, rawnum) > register_size (gdbarch, reg)) | |
766 | { | |
767 | if (!gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
768 | || gdbarch_byte_order (gdbarch) != BFD_ENDIAN_BIG) | |
769 | { | |
770 | ax_const_l (ax, 32); | |
771 | ax_simple (ax, aop_lsh); | |
772 | } | |
773 | ax_const_l (ax, 32); | |
774 | ax_simple (ax, aop_rsh_signed); | |
775 | } | |
776 | } | |
777 | else | |
778 | internal_error (__FILE__, __LINE__, _("bad register size")); | |
779 | ||
780 | return 0; | |
781 | } | |
782 | ||
4cc0665f | 783 | /* Table to translate 3-bit register field to actual register number. */ |
d467df4e | 784 | static const signed char mips_reg3_to_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
785 | |
786 | /* Heuristic_proc_start may hunt through the text section for a long | |
787 | time across a 2400 baud serial line. Allows the user to limit this | |
788 | search. */ | |
789 | ||
790 | static unsigned int heuristic_fence_post = 0; | |
791 | ||
46cd78fb | 792 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
793 | register N. NOTE: This defines the pseudo register type so need to |
794 | rebuild the architecture vector. */ | |
43e526b9 JM |
795 | |
796 | static int mips64_transfers_32bit_regs_p = 0; | |
797 | ||
719ec221 AC |
798 | static void |
799 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
800 | struct cmd_list_element *c) | |
43e526b9 | 801 | { |
719ec221 AC |
802 | struct gdbarch_info info; |
803 | gdbarch_info_init (&info); | |
804 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
805 | instead of relying on globals. Doing that would let generic code | |
806 | handle the search for this specific architecture. */ | |
807 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 808 | { |
719ec221 | 809 | mips64_transfers_32bit_regs_p = 0; |
8a3fe4f8 | 810 | error (_("32-bit compatibility mode not supported")); |
a4b8ebc8 | 811 | } |
a4b8ebc8 AC |
812 | } |
813 | ||
47ebcfbe | 814 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 815 | |
ee51a8c7 KB |
816 | /* This predicate tests for the case of an 8 byte floating point |
817 | value that is being transferred to or from a pair of floating point | |
818 | registers each of which are (or are considered to be) only 4 bytes | |
819 | wide. */ | |
ff2e87ac | 820 | static int |
ee51a8c7 KB |
821 | mips_convert_register_float_case_p (struct gdbarch *gdbarch, int regnum, |
822 | struct type *type) | |
ff2e87ac | 823 | { |
0abe36f5 MD |
824 | return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
825 | && register_size (gdbarch, regnum) == 4 | |
004159a2 | 826 | && mips_float_register_p (gdbarch, regnum) |
6d82d43b | 827 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
828 | } |
829 | ||
ee51a8c7 KB |
830 | /* This predicate tests for the case of a value of less than 8 |
831 | bytes in width that is being transfered to or from an 8 byte | |
832 | general purpose register. */ | |
833 | static int | |
834 | mips_convert_register_gpreg_case_p (struct gdbarch *gdbarch, int regnum, | |
835 | struct type *type) | |
836 | { | |
837 | int num_regs = gdbarch_num_regs (gdbarch); | |
838 | ||
839 | return (register_size (gdbarch, regnum) == 8 | |
840 | && regnum % num_regs > 0 && regnum % num_regs < 32 | |
841 | && TYPE_LENGTH (type) < 8); | |
842 | } | |
843 | ||
844 | static int | |
025bb325 MS |
845 | mips_convert_register_p (struct gdbarch *gdbarch, |
846 | int regnum, struct type *type) | |
ee51a8c7 | 847 | { |
eaa05d59 MR |
848 | return (mips_convert_register_float_case_p (gdbarch, regnum, type) |
849 | || mips_convert_register_gpreg_case_p (gdbarch, regnum, type)); | |
ee51a8c7 KB |
850 | } |
851 | ||
8dccd430 | 852 | static int |
ff2e87ac | 853 | mips_register_to_value (struct frame_info *frame, int regnum, |
8dccd430 PA |
854 | struct type *type, gdb_byte *to, |
855 | int *optimizedp, int *unavailablep) | |
102182a9 | 856 | { |
ee51a8c7 KB |
857 | struct gdbarch *gdbarch = get_frame_arch (frame); |
858 | ||
859 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
860 | { | |
861 | get_frame_register (frame, regnum + 0, to + 4); | |
862 | get_frame_register (frame, regnum + 1, to + 0); | |
8dccd430 PA |
863 | |
864 | if (!get_frame_register_bytes (frame, regnum + 0, 0, 4, to + 4, | |
865 | optimizedp, unavailablep)) | |
866 | return 0; | |
867 | ||
868 | if (!get_frame_register_bytes (frame, regnum + 1, 0, 4, to + 0, | |
869 | optimizedp, unavailablep)) | |
870 | return 0; | |
871 | *optimizedp = *unavailablep = 0; | |
872 | return 1; | |
ee51a8c7 KB |
873 | } |
874 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
875 | { | |
876 | int len = TYPE_LENGTH (type); | |
8dccd430 PA |
877 | CORE_ADDR offset; |
878 | ||
879 | offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 8 - len : 0; | |
880 | if (!get_frame_register_bytes (frame, regnum, offset, len, to, | |
881 | optimizedp, unavailablep)) | |
882 | return 0; | |
883 | ||
884 | *optimizedp = *unavailablep = 0; | |
885 | return 1; | |
ee51a8c7 KB |
886 | } |
887 | else | |
888 | { | |
889 | internal_error (__FILE__, __LINE__, | |
890 | _("mips_register_to_value: unrecognized case")); | |
891 | } | |
102182a9 MS |
892 | } |
893 | ||
42c466d7 | 894 | static void |
ff2e87ac | 895 | mips_value_to_register (struct frame_info *frame, int regnum, |
47a35522 | 896 | struct type *type, const gdb_byte *from) |
102182a9 | 897 | { |
ee51a8c7 KB |
898 | struct gdbarch *gdbarch = get_frame_arch (frame); |
899 | ||
900 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
901 | { | |
902 | put_frame_register (frame, regnum + 0, from + 4); | |
903 | put_frame_register (frame, regnum + 1, from + 0); | |
904 | } | |
905 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
906 | { | |
907 | gdb_byte fill[8]; | |
908 | int len = TYPE_LENGTH (type); | |
909 | ||
910 | /* Sign extend values, irrespective of type, that are stored to | |
911 | a 64-bit general purpose register. (32-bit unsigned values | |
912 | are stored as signed quantities within a 64-bit register. | |
913 | When performing an operation, in compiled code, that combines | |
914 | a 32-bit unsigned value with a signed 64-bit value, a type | |
915 | conversion is first performed that zeroes out the high 32 bits.) */ | |
916 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
917 | { | |
918 | if (from[0] & 0x80) | |
919 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, -1); | |
920 | else | |
921 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, 0); | |
922 | put_frame_register_bytes (frame, regnum, 0, 8 - len, fill); | |
923 | put_frame_register_bytes (frame, regnum, 8 - len, len, from); | |
924 | } | |
925 | else | |
926 | { | |
927 | if (from[len-1] & 0x80) | |
928 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, -1); | |
929 | else | |
930 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, 0); | |
931 | put_frame_register_bytes (frame, regnum, 0, len, from); | |
932 | put_frame_register_bytes (frame, regnum, len, 8 - len, fill); | |
933 | } | |
934 | } | |
935 | else | |
936 | { | |
937 | internal_error (__FILE__, __LINE__, | |
938 | _("mips_value_to_register: unrecognized case")); | |
939 | } | |
102182a9 MS |
940 | } |
941 | ||
a4b8ebc8 AC |
942 | /* Return the GDB type object for the "standard" data type of data in |
943 | register REG. */ | |
78fde5f8 KB |
944 | |
945 | static struct type * | |
a4b8ebc8 AC |
946 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
947 | { | |
72a155b4 | 948 | gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch)); |
004159a2 | 949 | if (mips_float_register_p (gdbarch, regnum)) |
a6425924 | 950 | { |
5ef80fb0 | 951 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 952 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
8da61cc4 | 953 | if (mips_isa_regsize (gdbarch) == 4) |
27067745 | 954 | return builtin_type (gdbarch)->builtin_float; |
8da61cc4 | 955 | else |
27067745 | 956 | return builtin_type (gdbarch)->builtin_double; |
a6425924 | 957 | } |
72a155b4 | 958 | else if (regnum < gdbarch_num_regs (gdbarch)) |
d5ac5a39 AC |
959 | { |
960 | /* The raw or ISA registers. These are all sized according to | |
961 | the ISA regsize. */ | |
962 | if (mips_isa_regsize (gdbarch) == 4) | |
df4df182 | 963 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 | 964 | else |
df4df182 | 965 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 966 | } |
78fde5f8 | 967 | else |
d5ac5a39 | 968 | { |
1faeff08 MR |
969 | int rawnum = regnum - gdbarch_num_regs (gdbarch); |
970 | ||
d5ac5a39 AC |
971 | /* The cooked or ABI registers. These are sized according to |
972 | the ABI (with a few complications). */ | |
1faeff08 MR |
973 | if (rawnum == mips_regnum (gdbarch)->fp_control_status |
974 | || rawnum == mips_regnum (gdbarch)->fp_implementation_revision) | |
975 | return builtin_type (gdbarch)->builtin_int32; | |
976 | else if (gdbarch_osabi (gdbarch) != GDB_OSABI_IRIX | |
977 | && gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX | |
978 | && rawnum >= MIPS_FIRST_EMBED_REGNUM | |
979 | && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
d5ac5a39 AC |
980 | /* The pseudo/cooked view of the embedded registers is always |
981 | 32-bit. The raw view is handled below. */ | |
df4df182 | 982 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
983 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
984 | /* The target, while possibly using a 64-bit register buffer, | |
985 | is only transfering 32-bits of each integer register. | |
986 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
df4df182 | 987 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
988 | else if (mips_abi_regsize (gdbarch) == 4) |
989 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
990 | 32- or 64-bit). */ | |
df4df182 | 991 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
992 | else |
993 | /* 64-bit ABI. */ | |
df4df182 | 994 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 995 | } |
78fde5f8 KB |
996 | } |
997 | ||
f8b73d13 DJ |
998 | /* Return the GDB type for the pseudo register REGNUM, which is the |
999 | ABI-level view. This function is only called if there is a target | |
1000 | description which includes registers, so we know precisely the | |
1001 | types of hardware registers. */ | |
1002 | ||
1003 | static struct type * | |
1004 | mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
1005 | { | |
1006 | const int num_regs = gdbarch_num_regs (gdbarch); | |
f8b73d13 DJ |
1007 | int rawnum = regnum % num_regs; |
1008 | struct type *rawtype; | |
1009 | ||
1010 | gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); | |
1011 | ||
1012 | /* Absent registers are still absent. */ | |
1013 | rawtype = gdbarch_register_type (gdbarch, rawnum); | |
1014 | if (TYPE_LENGTH (rawtype) == 0) | |
1015 | return rawtype; | |
1016 | ||
de13fcf2 | 1017 | if (mips_float_register_p (gdbarch, rawnum)) |
f8b73d13 DJ |
1018 | /* Present the floating point registers however the hardware did; |
1019 | do not try to convert between FPU layouts. */ | |
1020 | return rawtype; | |
1021 | ||
f8b73d13 DJ |
1022 | /* Use pointer types for registers if we can. For n32 we can not, |
1023 | since we do not have a 64-bit pointer type. */ | |
0dfff4cb UW |
1024 | if (mips_abi_regsize (gdbarch) |
1025 | == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr)) | |
f8b73d13 | 1026 | { |
1faeff08 MR |
1027 | if (rawnum == MIPS_SP_REGNUM |
1028 | || rawnum == mips_regnum (gdbarch)->badvaddr) | |
0dfff4cb | 1029 | return builtin_type (gdbarch)->builtin_data_ptr; |
1faeff08 | 1030 | else if (rawnum == mips_regnum (gdbarch)->pc) |
0dfff4cb | 1031 | return builtin_type (gdbarch)->builtin_func_ptr; |
f8b73d13 DJ |
1032 | } |
1033 | ||
1034 | if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8 | |
1faeff08 MR |
1035 | && ((rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_PS_REGNUM) |
1036 | || rawnum == mips_regnum (gdbarch)->lo | |
1037 | || rawnum == mips_regnum (gdbarch)->hi | |
1038 | || rawnum == mips_regnum (gdbarch)->badvaddr | |
1039 | || rawnum == mips_regnum (gdbarch)->cause | |
1040 | || rawnum == mips_regnum (gdbarch)->pc | |
1041 | || (mips_regnum (gdbarch)->dspacc != -1 | |
1042 | && rawnum >= mips_regnum (gdbarch)->dspacc | |
1043 | && rawnum < mips_regnum (gdbarch)->dspacc + 6))) | |
df4df182 | 1044 | return builtin_type (gdbarch)->builtin_int32; |
f8b73d13 | 1045 | |
1faeff08 MR |
1046 | if (gdbarch_osabi (gdbarch) != GDB_OSABI_IRIX |
1047 | && gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX | |
1048 | && rawnum >= MIPS_EMBED_FP0_REGNUM + 32 | |
1049 | && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
1050 | { | |
1051 | /* The pseudo/cooked view of embedded registers is always | |
1052 | 32-bit, even if the target transfers 64-bit values for them. | |
1053 | New targets relying on XML descriptions should only transfer | |
1054 | the necessary 32 bits, but older versions of GDB expected 64, | |
1055 | so allow the target to provide 64 bits without interfering | |
1056 | with the displayed type. */ | |
1057 | return builtin_type (gdbarch)->builtin_int32; | |
1058 | } | |
1059 | ||
f8b73d13 DJ |
1060 | /* For all other registers, pass through the hardware type. */ |
1061 | return rawtype; | |
1062 | } | |
bcb0cc15 | 1063 | |
025bb325 | 1064 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 1065 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
1066 | |
1067 | static int | |
480d3dd2 | 1068 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
1069 | { |
1070 | switch (mask_address_var) | |
1071 | { | |
7f19b9a2 | 1072 | case AUTO_BOOLEAN_TRUE: |
4014092b | 1073 | return 1; |
7f19b9a2 | 1074 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
1075 | return 0; |
1076 | break; | |
7f19b9a2 | 1077 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 1078 | return tdep->default_mask_address_p; |
4014092b | 1079 | default: |
025bb325 MS |
1080 | internal_error (__FILE__, __LINE__, |
1081 | _("mips_mask_address_p: bad switch")); | |
4014092b | 1082 | return -1; |
361d1df0 | 1083 | } |
4014092b AC |
1084 | } |
1085 | ||
1086 | static void | |
08546159 AC |
1087 | show_mask_address (struct ui_file *file, int from_tty, |
1088 | struct cmd_list_element *c, const char *value) | |
4014092b | 1089 | { |
1cf3db46 | 1090 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
08546159 AC |
1091 | |
1092 | deprecated_show_value_hack (file, from_tty, c, value); | |
4014092b AC |
1093 | switch (mask_address_var) |
1094 | { | |
7f19b9a2 | 1095 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
1096 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
1097 | break; | |
7f19b9a2 | 1098 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
1099 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
1100 | break; | |
7f19b9a2 | 1101 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
1102 | printf_filtered |
1103 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
1104 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
1105 | break; |
1106 | default: | |
e2e0b3e5 | 1107 | internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); |
4014092b | 1108 | break; |
361d1df0 | 1109 | } |
4014092b | 1110 | } |
c906108c | 1111 | |
4cc0665f MR |
1112 | /* Tell if the program counter value in MEMADDR is in a standard ISA |
1113 | function. */ | |
1114 | ||
1115 | int | |
1116 | mips_pc_is_mips (CORE_ADDR memaddr) | |
1117 | { | |
1118 | struct minimal_symbol *sym; | |
1119 | ||
1120 | /* Flags indicating that this is a MIPS16 or microMIPS function is | |
1121 | stored by elfread.c in the high bit of the info field. Use this | |
1122 | to decide if the function is standard MIPS. Otherwise if bit 0 | |
1123 | of the address is clear, then this is a standard MIPS function. */ | |
1124 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
1125 | if (sym) | |
1126 | return msymbol_is_mips (sym); | |
1127 | else | |
1128 | return is_mips_addr (memaddr); | |
1129 | } | |
1130 | ||
c906108c SS |
1131 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
1132 | ||
0fe7e7c8 | 1133 | int |
4cc0665f | 1134 | mips_pc_is_mips16 (struct gdbarch *gdbarch, CORE_ADDR memaddr) |
c906108c SS |
1135 | { |
1136 | struct minimal_symbol *sym; | |
1137 | ||
91912e4d MR |
1138 | /* A flag indicating that this is a MIPS16 function is stored by |
1139 | elfread.c in the high bit of the info field. Use this to decide | |
4cc0665f MR |
1140 | if the function is MIPS16. Otherwise if bit 0 of the address is |
1141 | set, then ELF file flags will tell if this is a MIPS16 function. */ | |
1142 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
1143 | if (sym) | |
1144 | return msymbol_is_mips16 (sym); | |
1145 | else | |
1146 | return is_mips16_addr (gdbarch, memaddr); | |
1147 | } | |
1148 | ||
1149 | /* Tell if the program counter value in MEMADDR is in a microMIPS function. */ | |
1150 | ||
1151 | int | |
1152 | mips_pc_is_micromips (struct gdbarch *gdbarch, CORE_ADDR memaddr) | |
1153 | { | |
1154 | struct minimal_symbol *sym; | |
1155 | ||
1156 | /* A flag indicating that this is a microMIPS function is stored by | |
1157 | elfread.c in the high bit of the info field. Use this to decide | |
1158 | if the function is microMIPS. Otherwise if bit 0 of the address | |
1159 | is set, then ELF file flags will tell if this is a microMIPS | |
1160 | function. */ | |
1161 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
1162 | if (sym) | |
1163 | return msymbol_is_micromips (sym); | |
1164 | else | |
1165 | return is_micromips_addr (gdbarch, memaddr); | |
1166 | } | |
1167 | ||
1168 | /* Tell the ISA type of the function the program counter value in MEMADDR | |
1169 | is in. */ | |
1170 | ||
1171 | static enum mips_isa | |
1172 | mips_pc_isa (struct gdbarch *gdbarch, CORE_ADDR memaddr) | |
1173 | { | |
1174 | struct minimal_symbol *sym; | |
1175 | ||
1176 | /* A flag indicating that this is a MIPS16 or a microMIPS function | |
1177 | is stored by elfread.c in the high bit of the info field. Use | |
1178 | this to decide if the function is MIPS16 or microMIPS or normal | |
1179 | MIPS. Otherwise if bit 0 of the address is set, then ELF file | |
1180 | flags will tell if this is a MIPS16 or a microMIPS function. */ | |
c906108c SS |
1181 | sym = lookup_minimal_symbol_by_pc (memaddr); |
1182 | if (sym) | |
4cc0665f MR |
1183 | { |
1184 | if (msymbol_is_micromips (sym)) | |
1185 | return ISA_MICROMIPS; | |
1186 | else if (msymbol_is_mips16 (sym)) | |
1187 | return ISA_MIPS16; | |
1188 | else | |
1189 | return ISA_MIPS; | |
1190 | } | |
c906108c | 1191 | else |
4cc0665f MR |
1192 | { |
1193 | if (is_mips_addr (memaddr)) | |
1194 | return ISA_MIPS; | |
1195 | else if (is_micromips_addr (gdbarch, memaddr)) | |
1196 | return ISA_MICROMIPS; | |
1197 | else | |
1198 | return ISA_MIPS16; | |
1199 | } | |
c906108c SS |
1200 | } |
1201 | ||
14132e89 MR |
1202 | /* Various MIPS16 thunk (aka stub or trampoline) names. */ |
1203 | ||
1204 | static const char mips_str_mips16_call_stub[] = "__mips16_call_stub_"; | |
1205 | static const char mips_str_mips16_ret_stub[] = "__mips16_ret_"; | |
1206 | static const char mips_str_call_fp_stub[] = "__call_stub_fp_"; | |
1207 | static const char mips_str_call_stub[] = "__call_stub_"; | |
1208 | static const char mips_str_fn_stub[] = "__fn_stub_"; | |
1209 | ||
1210 | /* This is used as a PIC thunk prefix. */ | |
1211 | ||
1212 | static const char mips_str_pic[] = ".pic."; | |
1213 | ||
1214 | /* Return non-zero if the PC is inside a call thunk (aka stub or | |
1215 | trampoline) that should be treated as a temporary frame. */ | |
1216 | ||
1217 | static int | |
1218 | mips_in_frame_stub (CORE_ADDR pc) | |
1219 | { | |
1220 | CORE_ADDR start_addr; | |
1221 | const char *name; | |
1222 | ||
1223 | /* Find the starting address of the function containing the PC. */ | |
1224 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
1225 | return 0; | |
1226 | ||
1227 | /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */ | |
1228 | if (strncmp (name, mips_str_mips16_call_stub, | |
1229 | strlen (mips_str_mips16_call_stub)) == 0) | |
1230 | return 1; | |
1231 | /* If the PC is in __call_stub_*, this is a call/return or a call stub. */ | |
1232 | if (strncmp (name, mips_str_call_stub, strlen (mips_str_call_stub)) == 0) | |
1233 | return 1; | |
1234 | /* If the PC is in __fn_stub_*, this is a call stub. */ | |
1235 | if (strncmp (name, mips_str_fn_stub, strlen (mips_str_fn_stub)) == 0) | |
1236 | return 1; | |
1237 | ||
1238 | return 0; /* Not a stub. */ | |
1239 | } | |
1240 | ||
b2fa5097 | 1241 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
025bb325 | 1242 | all registers should be sign extended for simplicity? */ |
6c997a34 AC |
1243 | |
1244 | static CORE_ADDR | |
61a1198a | 1245 | mips_read_pc (struct regcache *regcache) |
6c997a34 | 1246 | { |
8376de04 | 1247 | int regnum = gdbarch_pc_regnum (get_regcache_arch (regcache)); |
61a1198a | 1248 | ULONGEST pc; |
8376de04 | 1249 | |
61a1198a | 1250 | regcache_cooked_read_signed (regcache, regnum, &pc); |
4cc0665f MR |
1251 | if (is_compact_addr (pc)) |
1252 | pc = unmake_compact_addr (pc); | |
61a1198a | 1253 | return pc; |
b6cb9035 AC |
1254 | } |
1255 | ||
58dfe9ff AC |
1256 | static CORE_ADDR |
1257 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1258 | { | |
14132e89 | 1259 | CORE_ADDR pc; |
930bd0e0 | 1260 | |
8376de04 | 1261 | pc = frame_unwind_register_signed (next_frame, gdbarch_pc_regnum (gdbarch)); |
4cc0665f MR |
1262 | if (is_compact_addr (pc)) |
1263 | pc = unmake_compact_addr (pc); | |
14132e89 MR |
1264 | /* macro/2012-04-20: This hack skips over MIPS16 call thunks as |
1265 | intermediate frames. In this case we can get the caller's address | |
1266 | from $ra, or if $ra contains an address within a thunk as well, then | |
1267 | it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10} | |
1268 | and thus the caller's address is in $s2. */ | |
1269 | if (frame_relative_level (next_frame) >= 0 && mips_in_frame_stub (pc)) | |
1270 | { | |
1271 | pc = frame_unwind_register_signed | |
1272 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM); | |
4cc0665f MR |
1273 | if (is_compact_addr (pc)) |
1274 | pc = unmake_compact_addr (pc); | |
14132e89 MR |
1275 | if (mips_in_frame_stub (pc)) |
1276 | { | |
1277 | pc = frame_unwind_register_signed | |
1278 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); | |
4cc0665f MR |
1279 | if (is_compact_addr (pc)) |
1280 | pc = unmake_compact_addr (pc); | |
14132e89 MR |
1281 | } |
1282 | } | |
930bd0e0 | 1283 | return pc; |
edfae063 AC |
1284 | } |
1285 | ||
30244cd8 UW |
1286 | static CORE_ADDR |
1287 | mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1288 | { | |
72a155b4 UW |
1289 | return frame_unwind_register_signed |
1290 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM); | |
30244cd8 UW |
1291 | } |
1292 | ||
b8a22b94 | 1293 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that |
edfae063 AC |
1294 | dummy frame. The frame ID's base needs to match the TOS value |
1295 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
1296 | breakpoint. */ | |
1297 | ||
1298 | static struct frame_id | |
b8a22b94 | 1299 | mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
edfae063 | 1300 | { |
f57d151a | 1301 | return frame_id_build |
b8a22b94 DJ |
1302 | (get_frame_register_signed (this_frame, |
1303 | gdbarch_num_regs (gdbarch) | |
1304 | + MIPS_SP_REGNUM), | |
1305 | get_frame_pc (this_frame)); | |
58dfe9ff AC |
1306 | } |
1307 | ||
5a439849 MR |
1308 | /* Implement the "write_pc" gdbarch method. */ |
1309 | ||
1310 | void | |
61a1198a | 1311 | mips_write_pc (struct regcache *regcache, CORE_ADDR pc) |
b6cb9035 | 1312 | { |
8376de04 MR |
1313 | int regnum = gdbarch_pc_regnum (get_regcache_arch (regcache)); |
1314 | ||
4cc0665f | 1315 | if (mips_pc_is_mips (pc)) |
930bd0e0 | 1316 | regcache_cooked_write_unsigned (regcache, regnum, pc); |
4cc0665f MR |
1317 | else |
1318 | regcache_cooked_write_unsigned (regcache, regnum, make_compact_addr (pc)); | |
6c997a34 | 1319 | } |
c906108c | 1320 | |
4cc0665f MR |
1321 | /* Fetch and return instruction from the specified location. Handle |
1322 | MIPS16/microMIPS as appropriate. */ | |
c906108c | 1323 | |
d37cca3d | 1324 | static ULONGEST |
4cc0665f MR |
1325 | mips_fetch_instruction (struct gdbarch *gdbarch, |
1326 | enum mips_isa isa, CORE_ADDR addr, int *statusp) | |
c906108c | 1327 | { |
e17a4113 | 1328 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 1329 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
1330 | int instlen; |
1331 | int status; | |
1332 | ||
4cc0665f | 1333 | switch (isa) |
c906108c | 1334 | { |
4cc0665f MR |
1335 | case ISA_MICROMIPS: |
1336 | case ISA_MIPS16: | |
95ac2dcf | 1337 | instlen = MIPS_INSN16_SIZE; |
4cc0665f MR |
1338 | addr = unmake_compact_addr (addr); |
1339 | break; | |
1340 | case ISA_MIPS: | |
1341 | instlen = MIPS_INSN32_SIZE; | |
1342 | break; | |
1343 | default: | |
1344 | internal_error (__FILE__, __LINE__, _("invalid ISA")); | |
1345 | break; | |
c906108c | 1346 | } |
8defab1a | 1347 | status = target_read_memory (addr, buf, instlen); |
4cc0665f MR |
1348 | if (statusp != NULL) |
1349 | *statusp = status; | |
c906108c | 1350 | if (status) |
4cc0665f MR |
1351 | { |
1352 | if (statusp == NULL) | |
1353 | memory_error (status, addr); | |
1354 | return 0; | |
1355 | } | |
e17a4113 | 1356 | return extract_unsigned_integer (buf, instlen, byte_order); |
c906108c SS |
1357 | } |
1358 | ||
025bb325 | 1359 | /* These are the fields of 32 bit mips instructions. */ |
e135b889 DJ |
1360 | #define mips32_op(x) (x >> 26) |
1361 | #define itype_op(x) (x >> 26) | |
1362 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 1363 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 1364 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 1365 | |
e135b889 DJ |
1366 | #define jtype_op(x) (x >> 26) |
1367 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 1368 | |
e135b889 DJ |
1369 | #define rtype_op(x) (x >> 26) |
1370 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
1371 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
1372 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
1373 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
1374 | #define rtype_funct(x) (x & 0x3f) | |
c906108c | 1375 | |
4cc0665f MR |
1376 | /* MicroMIPS instruction fields. */ |
1377 | #define micromips_op(x) ((x) >> 10) | |
1378 | ||
1379 | /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest | |
1380 | bit and the size respectively of the field extracted. */ | |
1381 | #define b0s4_imm(x) ((x) & 0xf) | |
1382 | #define b0s5_imm(x) ((x) & 0x1f) | |
1383 | #define b0s5_reg(x) ((x) & 0x1f) | |
1384 | #define b0s7_imm(x) ((x) & 0x7f) | |
1385 | #define b0s10_imm(x) ((x) & 0x3ff) | |
1386 | #define b1s4_imm(x) (((x) >> 1) & 0xf) | |
1387 | #define b1s9_imm(x) (((x) >> 1) & 0x1ff) | |
1388 | #define b2s3_cc(x) (((x) >> 2) & 0x7) | |
1389 | #define b4s2_regl(x) (((x) >> 4) & 0x3) | |
1390 | #define b5s5_op(x) (((x) >> 5) & 0x1f) | |
1391 | #define b5s5_reg(x) (((x) >> 5) & 0x1f) | |
1392 | #define b6s4_op(x) (((x) >> 6) & 0xf) | |
1393 | #define b7s3_reg(x) (((x) >> 7) & 0x7) | |
1394 | ||
1395 | /* 32-bit instruction formats, B and S refer to the lowest bit and the size | |
1396 | respectively of the field extracted. */ | |
1397 | #define b0s6_op(x) ((x) & 0x3f) | |
1398 | #define b0s11_op(x) ((x) & 0x7ff) | |
1399 | #define b0s12_imm(x) ((x) & 0xfff) | |
1400 | #define b0s16_imm(x) ((x) & 0xffff) | |
1401 | #define b0s26_imm(x) ((x) & 0x3ffffff) | |
1402 | #define b6s10_ext(x) (((x) >> 6) & 0x3ff) | |
1403 | #define b11s5_reg(x) (((x) >> 11) & 0x1f) | |
1404 | #define b12s4_op(x) (((x) >> 12) & 0xf) | |
1405 | ||
1406 | /* Return the size in bytes of the instruction INSN encoded in the ISA | |
1407 | instruction set. */ | |
1408 | ||
1409 | static int | |
1410 | mips_insn_size (enum mips_isa isa, ULONGEST insn) | |
1411 | { | |
1412 | switch (isa) | |
1413 | { | |
1414 | case ISA_MICROMIPS: | |
1415 | if (micromips_op (insn) == 0x1f) | |
1416 | return 3 * MIPS_INSN16_SIZE; | |
1417 | else if (((micromips_op (insn) & 0x4) == 0x4) | |
1418 | || ((micromips_op (insn) & 0x7) == 0x0)) | |
1419 | return 2 * MIPS_INSN16_SIZE; | |
1420 | else | |
1421 | return MIPS_INSN16_SIZE; | |
1422 | case ISA_MIPS16: | |
1423 | if ((insn & 0xf800) == 0xf000) | |
1424 | return 2 * MIPS_INSN16_SIZE; | |
1425 | else | |
1426 | return MIPS_INSN16_SIZE; | |
1427 | case ISA_MIPS: | |
1428 | return MIPS_INSN32_SIZE; | |
1429 | } | |
1430 | internal_error (__FILE__, __LINE__, _("invalid ISA")); | |
1431 | } | |
1432 | ||
06987e64 MK |
1433 | static LONGEST |
1434 | mips32_relative_offset (ULONGEST inst) | |
c5aa993b | 1435 | { |
06987e64 | 1436 | return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; |
c906108c SS |
1437 | } |
1438 | ||
a385295e MR |
1439 | /* Determine the address of the next instruction executed after the INST |
1440 | floating condition branch instruction at PC. COUNT specifies the | |
1441 | number of the floating condition bits tested by the branch. */ | |
1442 | ||
1443 | static CORE_ADDR | |
1444 | mips32_bc1_pc (struct gdbarch *gdbarch, struct frame_info *frame, | |
1445 | ULONGEST inst, CORE_ADDR pc, int count) | |
1446 | { | |
1447 | int fcsr = mips_regnum (gdbarch)->fp_control_status; | |
1448 | int cnum = (itype_rt (inst) >> 2) & (count - 1); | |
1449 | int tf = itype_rt (inst) & 1; | |
1450 | int mask = (1 << count) - 1; | |
1451 | ULONGEST fcs; | |
1452 | int cond; | |
1453 | ||
1454 | if (fcsr == -1) | |
1455 | /* No way to handle; it'll most likely trap anyway. */ | |
1456 | return pc; | |
1457 | ||
1458 | fcs = get_frame_register_unsigned (frame, fcsr); | |
1459 | cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); | |
1460 | ||
1461 | if (((cond >> cnum) & mask) != mask * !tf) | |
1462 | pc += mips32_relative_offset (inst); | |
1463 | else | |
1464 | pc += 4; | |
1465 | ||
1466 | return pc; | |
1467 | } | |
1468 | ||
f49e4e6d MS |
1469 | /* Determine where to set a single step breakpoint while considering |
1470 | branch prediction. */ | |
5a89d8aa | 1471 | static CORE_ADDR |
0b1b3e42 | 1472 | mips32_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c5aa993b | 1473 | { |
e17a4113 | 1474 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c5aa993b JM |
1475 | unsigned long inst; |
1476 | int op; | |
4cc0665f | 1477 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
025bb325 MS |
1478 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch |
1479 | instruction. */ | |
c5aa993b | 1480 | { |
e135b889 | 1481 | if (itype_op (inst) >> 2 == 5) |
6d82d43b | 1482 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 1483 | { |
e135b889 | 1484 | op = (itype_op (inst) & 0x03); |
c906108c SS |
1485 | switch (op) |
1486 | { | |
e135b889 DJ |
1487 | case 0: /* BEQL */ |
1488 | goto equal_branch; | |
1489 | case 1: /* BNEL */ | |
1490 | goto neq_branch; | |
1491 | case 2: /* BLEZL */ | |
1492 | goto less_branch; | |
313628cc | 1493 | case 3: /* BGTZL */ |
e135b889 | 1494 | goto greater_branch; |
c5aa993b JM |
1495 | default: |
1496 | pc += 4; | |
c906108c SS |
1497 | } |
1498 | } | |
e135b889 | 1499 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
6d82d43b | 1500 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
a385295e MR |
1501 | pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 1); |
1502 | else if (itype_op (inst) == 17 && itype_rs (inst) == 9 | |
1503 | && (itype_rt (inst) & 2) == 0) | |
1504 | /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */ | |
1505 | pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 2); | |
1506 | else if (itype_op (inst) == 17 && itype_rs (inst) == 10 | |
1507 | && (itype_rt (inst) & 2) == 0) | |
1508 | /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */ | |
1509 | pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 4); | |
9e8da49c MR |
1510 | else if (itype_op (inst) == 29) |
1511 | /* JALX: 011101 */ | |
1512 | /* The new PC will be alternate mode. */ | |
1513 | { | |
1514 | unsigned long reg; | |
1515 | ||
1516 | reg = jtype_target (inst) << 2; | |
1517 | /* Add 1 to indicate 16-bit mode -- invert ISA mode. */ | |
1518 | pc = ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + reg + 1; | |
1519 | } | |
c5aa993b | 1520 | else |
025bb325 | 1521 | pc += 4; /* Not a branch, next instruction is easy. */ |
c906108c SS |
1522 | } |
1523 | else | |
025bb325 | 1524 | { /* This gets way messy. */ |
c5aa993b | 1525 | |
025bb325 MS |
1526 | /* Further subdivide into SPECIAL, REGIMM and other. */ |
1527 | switch (op = itype_op (inst) & 0x07) /* Extract bits 28,27,26. */ | |
c906108c | 1528 | { |
c5aa993b JM |
1529 | case 0: /* SPECIAL */ |
1530 | op = rtype_funct (inst); | |
1531 | switch (op) | |
1532 | { | |
1533 | case 8: /* JR */ | |
1534 | case 9: /* JALR */ | |
025bb325 | 1535 | /* Set PC to that address. */ |
0b1b3e42 | 1536 | pc = get_frame_register_signed (frame, rtype_rs (inst)); |
c5aa993b | 1537 | break; |
e38d4e1a DJ |
1538 | case 12: /* SYSCALL */ |
1539 | { | |
1540 | struct gdbarch_tdep *tdep; | |
1541 | ||
1542 | tdep = gdbarch_tdep (get_frame_arch (frame)); | |
1543 | if (tdep->syscall_next_pc != NULL) | |
1544 | pc = tdep->syscall_next_pc (frame); | |
1545 | else | |
1546 | pc += 4; | |
1547 | } | |
1548 | break; | |
c5aa993b JM |
1549 | default: |
1550 | pc += 4; | |
1551 | } | |
1552 | ||
6d82d43b | 1553 | break; /* end SPECIAL */ |
025bb325 | 1554 | case 1: /* REGIMM */ |
c906108c | 1555 | { |
e135b889 DJ |
1556 | op = itype_rt (inst); /* branch condition */ |
1557 | switch (op) | |
c906108c | 1558 | { |
c5aa993b | 1559 | case 0: /* BLTZ */ |
e135b889 DJ |
1560 | case 2: /* BLTZL */ |
1561 | case 16: /* BLTZAL */ | |
c5aa993b | 1562 | case 18: /* BLTZALL */ |
c906108c | 1563 | less_branch: |
0b1b3e42 | 1564 | if (get_frame_register_signed (frame, itype_rs (inst)) < 0) |
c5aa993b JM |
1565 | pc += mips32_relative_offset (inst) + 4; |
1566 | else | |
1567 | pc += 8; /* after the delay slot */ | |
1568 | break; | |
e135b889 | 1569 | case 1: /* BGEZ */ |
c5aa993b JM |
1570 | case 3: /* BGEZL */ |
1571 | case 17: /* BGEZAL */ | |
1572 | case 19: /* BGEZALL */ | |
0b1b3e42 | 1573 | if (get_frame_register_signed (frame, itype_rs (inst)) >= 0) |
c5aa993b JM |
1574 | pc += mips32_relative_offset (inst) + 4; |
1575 | else | |
1576 | pc += 8; /* after the delay slot */ | |
1577 | break; | |
a385295e MR |
1578 | case 0x1c: /* BPOSGE32 */ |
1579 | case 0x1e: /* BPOSGE64 */ | |
1580 | pc += 4; | |
1581 | if (itype_rs (inst) == 0) | |
1582 | { | |
1583 | unsigned int pos = (op & 2) ? 64 : 32; | |
1584 | int dspctl = mips_regnum (gdbarch)->dspctl; | |
1585 | ||
1586 | if (dspctl == -1) | |
1587 | /* No way to handle; it'll most likely trap anyway. */ | |
1588 | break; | |
1589 | ||
1590 | if ((get_frame_register_unsigned (frame, | |
1591 | dspctl) & 0x7f) >= pos) | |
1592 | pc += mips32_relative_offset (inst); | |
1593 | else | |
1594 | pc += 4; | |
1595 | } | |
1596 | break; | |
e135b889 | 1597 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1598 | default: |
1599 | pc += 4; | |
c906108c SS |
1600 | } |
1601 | } | |
6d82d43b | 1602 | break; /* end REGIMM */ |
c5aa993b JM |
1603 | case 2: /* J */ |
1604 | case 3: /* JAL */ | |
1605 | { | |
1606 | unsigned long reg; | |
1607 | reg = jtype_target (inst) << 2; | |
025bb325 | 1608 | /* Upper four bits get never changed... */ |
5b652102 | 1609 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
c906108c | 1610 | } |
c5aa993b | 1611 | break; |
e135b889 | 1612 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1613 | equal_branch: |
0b1b3e42 UW |
1614 | if (get_frame_register_signed (frame, itype_rs (inst)) == |
1615 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1616 | pc += mips32_relative_offset (inst) + 4; |
1617 | else | |
1618 | pc += 8; | |
1619 | break; | |
e135b889 | 1620 | case 5: /* BNE, BNEL */ |
c5aa993b | 1621 | neq_branch: |
0b1b3e42 UW |
1622 | if (get_frame_register_signed (frame, itype_rs (inst)) != |
1623 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1624 | pc += mips32_relative_offset (inst) + 4; |
1625 | else | |
1626 | pc += 8; | |
1627 | break; | |
e135b889 | 1628 | case 6: /* BLEZ, BLEZL */ |
0b1b3e42 | 1629 | if (get_frame_register_signed (frame, itype_rs (inst)) <= 0) |
c5aa993b JM |
1630 | pc += mips32_relative_offset (inst) + 4; |
1631 | else | |
1632 | pc += 8; | |
1633 | break; | |
1634 | case 7: | |
e135b889 DJ |
1635 | default: |
1636 | greater_branch: /* BGTZ, BGTZL */ | |
0b1b3e42 | 1637 | if (get_frame_register_signed (frame, itype_rs (inst)) > 0) |
c5aa993b JM |
1638 | pc += mips32_relative_offset (inst) + 4; |
1639 | else | |
1640 | pc += 8; | |
1641 | break; | |
c5aa993b JM |
1642 | } /* switch */ |
1643 | } /* else */ | |
1644 | return pc; | |
1645 | } /* mips32_next_pc */ | |
c906108c | 1646 | |
4cc0665f MR |
1647 | /* Extract the 7-bit signed immediate offset from the microMIPS instruction |
1648 | INSN. */ | |
1649 | ||
1650 | static LONGEST | |
1651 | micromips_relative_offset7 (ULONGEST insn) | |
1652 | { | |
1653 | return ((b0s7_imm (insn) ^ 0x40) - 0x40) << 1; | |
1654 | } | |
1655 | ||
1656 | /* Extract the 10-bit signed immediate offset from the microMIPS instruction | |
1657 | INSN. */ | |
1658 | ||
1659 | static LONGEST | |
1660 | micromips_relative_offset10 (ULONGEST insn) | |
1661 | { | |
1662 | return ((b0s10_imm (insn) ^ 0x200) - 0x200) << 1; | |
1663 | } | |
1664 | ||
1665 | /* Extract the 16-bit signed immediate offset from the microMIPS instruction | |
1666 | INSN. */ | |
1667 | ||
1668 | static LONGEST | |
1669 | micromips_relative_offset16 (ULONGEST insn) | |
1670 | { | |
1671 | return ((b0s16_imm (insn) ^ 0x8000) - 0x8000) << 1; | |
1672 | } | |
1673 | ||
1674 | /* Return the size in bytes of the microMIPS instruction at the address PC. */ | |
1675 | ||
1676 | static int | |
1677 | micromips_pc_insn_size (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1678 | { | |
1679 | ULONGEST insn; | |
1680 | ||
1681 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
1682 | return mips_insn_size (ISA_MICROMIPS, insn); | |
1683 | } | |
1684 | ||
1685 | /* Calculate the address of the next microMIPS instruction to execute | |
1686 | after the INSN coprocessor 1 conditional branch instruction at the | |
1687 | address PC. COUNT denotes the number of coprocessor condition bits | |
1688 | examined by the branch. */ | |
1689 | ||
1690 | static CORE_ADDR | |
1691 | micromips_bc1_pc (struct gdbarch *gdbarch, struct frame_info *frame, | |
1692 | ULONGEST insn, CORE_ADDR pc, int count) | |
1693 | { | |
1694 | int fcsr = mips_regnum (gdbarch)->fp_control_status; | |
1695 | int cnum = b2s3_cc (insn >> 16) & (count - 1); | |
1696 | int tf = b5s5_op (insn >> 16) & 1; | |
1697 | int mask = (1 << count) - 1; | |
1698 | ULONGEST fcs; | |
1699 | int cond; | |
1700 | ||
1701 | if (fcsr == -1) | |
1702 | /* No way to handle; it'll most likely trap anyway. */ | |
1703 | return pc; | |
1704 | ||
1705 | fcs = get_frame_register_unsigned (frame, fcsr); | |
1706 | cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); | |
1707 | ||
1708 | if (((cond >> cnum) & mask) != mask * !tf) | |
1709 | pc += micromips_relative_offset16 (insn); | |
1710 | else | |
1711 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1712 | ||
1713 | return pc; | |
1714 | } | |
1715 | ||
1716 | /* Calculate the address of the next microMIPS instruction to execute | |
1717 | after the instruction at the address PC. */ | |
1718 | ||
1719 | static CORE_ADDR | |
1720 | micromips_next_pc (struct frame_info *frame, CORE_ADDR pc) | |
1721 | { | |
1722 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
1723 | ULONGEST insn; | |
1724 | ||
1725 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
1726 | pc += MIPS_INSN16_SIZE; | |
1727 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
1728 | { | |
1729 | /* 48-bit instructions. */ | |
1730 | case 3 * MIPS_INSN16_SIZE: /* POOL48A: bits 011111 */ | |
1731 | /* No branch or jump instructions in this category. */ | |
1732 | pc += 2 * MIPS_INSN16_SIZE; | |
1733 | break; | |
1734 | ||
1735 | /* 32-bit instructions. */ | |
1736 | case 2 * MIPS_INSN16_SIZE: | |
1737 | insn <<= 16; | |
1738 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
1739 | pc += MIPS_INSN16_SIZE; | |
1740 | switch (micromips_op (insn >> 16)) | |
1741 | { | |
1742 | case 0x00: /* POOL32A: bits 000000 */ | |
1743 | if (b0s6_op (insn) == 0x3c | |
1744 | /* POOL32Axf: bits 000000 ... 111100 */ | |
1745 | && (b6s10_ext (insn) & 0x2bf) == 0x3c) | |
1746 | /* JALR, JALR.HB: 000000 000x111100 111100 */ | |
1747 | /* JALRS, JALRS.HB: 000000 010x111100 111100 */ | |
1748 | pc = get_frame_register_signed (frame, b0s5_reg (insn >> 16)); | |
1749 | break; | |
1750 | ||
1751 | case 0x10: /* POOL32I: bits 010000 */ | |
1752 | switch (b5s5_op (insn >> 16)) | |
1753 | { | |
1754 | case 0x00: /* BLTZ: bits 010000 00000 */ | |
1755 | case 0x01: /* BLTZAL: bits 010000 00001 */ | |
1756 | case 0x11: /* BLTZALS: bits 010000 10001 */ | |
1757 | if (get_frame_register_signed (frame, | |
1758 | b0s5_reg (insn >> 16)) < 0) | |
1759 | pc += micromips_relative_offset16 (insn); | |
1760 | else | |
1761 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1762 | break; | |
1763 | ||
1764 | case 0x02: /* BGEZ: bits 010000 00010 */ | |
1765 | case 0x03: /* BGEZAL: bits 010000 00011 */ | |
1766 | case 0x13: /* BGEZALS: bits 010000 10011 */ | |
1767 | if (get_frame_register_signed (frame, | |
1768 | b0s5_reg (insn >> 16)) >= 0) | |
1769 | pc += micromips_relative_offset16 (insn); | |
1770 | else | |
1771 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1772 | break; | |
1773 | ||
1774 | case 0x04: /* BLEZ: bits 010000 00100 */ | |
1775 | if (get_frame_register_signed (frame, | |
1776 | b0s5_reg (insn >> 16)) <= 0) | |
1777 | pc += micromips_relative_offset16 (insn); | |
1778 | else | |
1779 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1780 | break; | |
1781 | ||
1782 | case 0x05: /* BNEZC: bits 010000 00101 */ | |
1783 | if (get_frame_register_signed (frame, | |
1784 | b0s5_reg (insn >> 16)) != 0) | |
1785 | pc += micromips_relative_offset16 (insn); | |
1786 | break; | |
1787 | ||
1788 | case 0x06: /* BGTZ: bits 010000 00110 */ | |
1789 | if (get_frame_register_signed (frame, | |
1790 | b0s5_reg (insn >> 16)) > 0) | |
1791 | pc += micromips_relative_offset16 (insn); | |
1792 | else | |
1793 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1794 | break; | |
1795 | ||
1796 | case 0x07: /* BEQZC: bits 010000 00111 */ | |
1797 | if (get_frame_register_signed (frame, | |
1798 | b0s5_reg (insn >> 16)) == 0) | |
1799 | pc += micromips_relative_offset16 (insn); | |
1800 | break; | |
1801 | ||
1802 | case 0x14: /* BC2F: bits 010000 10100 xxx00 */ | |
1803 | case 0x15: /* BC2T: bits 010000 10101 xxx00 */ | |
1804 | if (((insn >> 16) & 0x3) == 0x0) | |
1805 | /* BC2F, BC2T: don't know how to handle these. */ | |
1806 | break; | |
1807 | break; | |
1808 | ||
1809 | case 0x1a: /* BPOSGE64: bits 010000 11010 */ | |
1810 | case 0x1b: /* BPOSGE32: bits 010000 11011 */ | |
1811 | { | |
1812 | unsigned int pos = (b5s5_op (insn >> 16) & 1) ? 32 : 64; | |
1813 | int dspctl = mips_regnum (gdbarch)->dspctl; | |
1814 | ||
1815 | if (dspctl == -1) | |
1816 | /* No way to handle; it'll most likely trap anyway. */ | |
1817 | break; | |
1818 | ||
1819 | if ((get_frame_register_unsigned (frame, | |
1820 | dspctl) & 0x7f) >= pos) | |
1821 | pc += micromips_relative_offset16 (insn); | |
1822 | else | |
1823 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1824 | } | |
1825 | break; | |
1826 | ||
1827 | case 0x1c: /* BC1F: bits 010000 11100 xxx00 */ | |
1828 | /* BC1ANY2F: bits 010000 11100 xxx01 */ | |
1829 | case 0x1d: /* BC1T: bits 010000 11101 xxx00 */ | |
1830 | /* BC1ANY2T: bits 010000 11101 xxx01 */ | |
1831 | if (((insn >> 16) & 0x2) == 0x0) | |
1832 | pc = micromips_bc1_pc (gdbarch, frame, insn, pc, | |
1833 | ((insn >> 16) & 0x1) + 1); | |
1834 | break; | |
1835 | ||
1836 | case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */ | |
1837 | case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */ | |
1838 | if (((insn >> 16) & 0x3) == 0x1) | |
1839 | pc = micromips_bc1_pc (gdbarch, frame, insn, pc, 4); | |
1840 | break; | |
1841 | } | |
1842 | break; | |
1843 | ||
1844 | case 0x1d: /* JALS: bits 011101 */ | |
1845 | case 0x35: /* J: bits 110101 */ | |
1846 | case 0x3d: /* JAL: bits 111101 */ | |
1847 | pc = ((pc | 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn) << 1); | |
1848 | break; | |
1849 | ||
1850 | case 0x25: /* BEQ: bits 100101 */ | |
1851 | if (get_frame_register_signed (frame, b0s5_reg (insn >> 16)) | |
1852 | == get_frame_register_signed (frame, b5s5_reg (insn >> 16))) | |
1853 | pc += micromips_relative_offset16 (insn); | |
1854 | else | |
1855 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1856 | break; | |
1857 | ||
1858 | case 0x2d: /* BNE: bits 101101 */ | |
1859 | if (get_frame_register_signed (frame, b0s5_reg (insn >> 16)) | |
1860 | != get_frame_register_signed (frame, b5s5_reg (insn >> 16))) | |
1861 | pc += micromips_relative_offset16 (insn); | |
1862 | else | |
1863 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1864 | break; | |
1865 | ||
1866 | case 0x3c: /* JALX: bits 111100 */ | |
1867 | pc = ((pc | 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn) << 2); | |
1868 | break; | |
1869 | } | |
1870 | break; | |
1871 | ||
1872 | /* 16-bit instructions. */ | |
1873 | case MIPS_INSN16_SIZE: | |
1874 | switch (micromips_op (insn)) | |
1875 | { | |
1876 | case 0x11: /* POOL16C: bits 010001 */ | |
1877 | if ((b5s5_op (insn) & 0x1c) == 0xc) | |
1878 | /* JR16, JRC, JALR16, JALRS16: 010001 011xx */ | |
1879 | pc = get_frame_register_signed (frame, b0s5_reg (insn)); | |
1880 | else if (b5s5_op (insn) == 0x18) | |
1881 | /* JRADDIUSP: bits 010001 11000 */ | |
1882 | pc = get_frame_register_signed (frame, MIPS_RA_REGNUM); | |
1883 | break; | |
1884 | ||
1885 | case 0x23: /* BEQZ16: bits 100011 */ | |
1886 | { | |
1887 | int rs = mips_reg3_to_reg[b7s3_reg (insn)]; | |
1888 | ||
1889 | if (get_frame_register_signed (frame, rs) == 0) | |
1890 | pc += micromips_relative_offset7 (insn); | |
1891 | else | |
1892 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1893 | } | |
1894 | break; | |
1895 | ||
1896 | case 0x2b: /* BNEZ16: bits 101011 */ | |
1897 | { | |
1898 | int rs = mips_reg3_to_reg[b7s3_reg (insn)]; | |
1899 | ||
1900 | if (get_frame_register_signed (frame, rs) != 0) | |
1901 | pc += micromips_relative_offset7 (insn); | |
1902 | else | |
1903 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1904 | } | |
1905 | break; | |
1906 | ||
1907 | case 0x33: /* B16: bits 110011 */ | |
1908 | pc += micromips_relative_offset10 (insn); | |
1909 | break; | |
1910 | } | |
1911 | break; | |
1912 | } | |
1913 | ||
1914 | return pc; | |
1915 | } | |
1916 | ||
c906108c | 1917 | /* Decoding the next place to set a breakpoint is irregular for the |
025bb325 MS |
1918 | mips 16 variant, but fortunately, there fewer instructions. We have |
1919 | to cope ith extensions for 16 bit instructions and a pair of actual | |
1920 | 32 bit instructions. We dont want to set a single step instruction | |
1921 | on the extend instruction either. */ | |
c906108c SS |
1922 | |
1923 | /* Lots of mips16 instruction formats */ | |
1924 | /* Predicting jumps requires itype,ritype,i8type | |
025bb325 | 1925 | and their extensions extItype,extritype,extI8type. */ |
c906108c SS |
1926 | enum mips16_inst_fmts |
1927 | { | |
c5aa993b JM |
1928 | itype, /* 0 immediate 5,10 */ |
1929 | ritype, /* 1 5,3,8 */ | |
1930 | rrtype, /* 2 5,3,3,5 */ | |
1931 | rritype, /* 3 5,3,3,5 */ | |
1932 | rrrtype, /* 4 5,3,3,3,2 */ | |
1933 | rriatype, /* 5 5,3,3,1,4 */ | |
1934 | shifttype, /* 6 5,3,3,3,2 */ | |
1935 | i8type, /* 7 5,3,8 */ | |
1936 | i8movtype, /* 8 5,3,3,5 */ | |
1937 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1938 | i64type, /* 10 5,3,8 */ | |
1939 | ri64type, /* 11 5,3,3,5 */ | |
1940 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1941 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1942 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1943 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1944 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1945 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1946 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1947 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1948 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1949 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1950 | }; | |
12f02c2a | 1951 | /* I am heaping all the fields of the formats into one structure and |
025bb325 | 1952 | then, only the fields which are involved in instruction extension. */ |
c906108c | 1953 | struct upk_mips16 |
6d82d43b AC |
1954 | { |
1955 | CORE_ADDR offset; | |
025bb325 | 1956 | unsigned int regx; /* Function in i8 type. */ |
6d82d43b AC |
1957 | unsigned int regy; |
1958 | }; | |
c906108c SS |
1959 | |
1960 | ||
12f02c2a | 1961 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
c68cf8ad | 1962 | for the bits which make up the immediate extension. */ |
c906108c | 1963 | |
12f02c2a AC |
1964 | static CORE_ADDR |
1965 | extended_offset (unsigned int extension) | |
c906108c | 1966 | { |
12f02c2a | 1967 | CORE_ADDR value; |
130854df | 1968 | |
4c2051c6 | 1969 | value = (extension >> 16) & 0x1f; /* Extract 15:11. */ |
c5aa993b | 1970 | value = value << 6; |
4c2051c6 | 1971 | value |= (extension >> 21) & 0x3f; /* Extract 10:5. */ |
c5aa993b | 1972 | value = value << 5; |
130854df MR |
1973 | value |= extension & 0x1f; /* Extract 4:0. */ |
1974 | ||
c5aa993b | 1975 | return value; |
c906108c SS |
1976 | } |
1977 | ||
1978 | /* Only call this function if you know that this is an extendable | |
bcf1ea1e MR |
1979 | instruction. It won't malfunction, but why make excess remote memory |
1980 | references? If the immediate operands get sign extended or something, | |
1981 | do it after the extension is performed. */ | |
c906108c | 1982 | /* FIXME: Every one of these cases needs to worry about sign extension |
bcf1ea1e | 1983 | when the offset is to be used in relative addressing. */ |
c906108c | 1984 | |
12f02c2a | 1985 | static unsigned int |
e17a4113 | 1986 | fetch_mips_16 (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 1987 | { |
e17a4113 | 1988 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 1989 | gdb_byte buf[8]; |
025bb325 | 1990 | pc &= 0xfffffffe; /* Clear the low order bit. */ |
c5aa993b | 1991 | target_read_memory (pc, buf, 2); |
e17a4113 | 1992 | return extract_unsigned_integer (buf, 2, byte_order); |
c906108c SS |
1993 | } |
1994 | ||
1995 | static void | |
e17a4113 | 1996 | unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc, |
12f02c2a AC |
1997 | unsigned int extension, |
1998 | unsigned int inst, | |
6d82d43b | 1999 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 2000 | { |
12f02c2a AC |
2001 | CORE_ADDR offset; |
2002 | int regx; | |
2003 | int regy; | |
2004 | switch (insn_format) | |
c906108c | 2005 | { |
c5aa993b | 2006 | case itype: |
c906108c | 2007 | { |
12f02c2a AC |
2008 | CORE_ADDR value; |
2009 | if (extension) | |
c5aa993b | 2010 | { |
4c2051c6 MR |
2011 | value = extended_offset ((extension << 16) | inst); |
2012 | value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ | |
c906108c SS |
2013 | } |
2014 | else | |
c5aa993b | 2015 | { |
12f02c2a | 2016 | value = inst & 0x7ff; |
4c2051c6 | 2017 | value = (value ^ 0x400) - 0x400; /* Sign-extend. */ |
c906108c | 2018 | } |
12f02c2a AC |
2019 | offset = value; |
2020 | regx = -1; | |
2021 | regy = -1; | |
c906108c | 2022 | } |
c5aa993b JM |
2023 | break; |
2024 | case ritype: | |
2025 | case i8type: | |
025bb325 | 2026 | { /* A register identifier and an offset. */ |
c906108c | 2027 | /* Most of the fields are the same as I type but the |
025bb325 | 2028 | immediate value is of a different length. */ |
12f02c2a AC |
2029 | CORE_ADDR value; |
2030 | if (extension) | |
c906108c | 2031 | { |
4c2051c6 MR |
2032 | value = extended_offset ((extension << 16) | inst); |
2033 | value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ | |
c906108c | 2034 | } |
c5aa993b JM |
2035 | else |
2036 | { | |
4c2051c6 MR |
2037 | value = inst & 0xff; /* 8 bits */ |
2038 | value = (value ^ 0x80) - 0x80; /* Sign-extend. */ | |
c5aa993b | 2039 | } |
12f02c2a | 2040 | offset = value; |
4c2051c6 | 2041 | regx = (inst >> 8) & 0x07; /* i8 funct */ |
12f02c2a | 2042 | regy = -1; |
c5aa993b | 2043 | break; |
c906108c | 2044 | } |
c5aa993b | 2045 | case jalxtype: |
c906108c | 2046 | { |
c5aa993b | 2047 | unsigned long value; |
12f02c2a AC |
2048 | unsigned int nexthalf; |
2049 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b | 2050 | value = value << 16; |
4cc0665f MR |
2051 | nexthalf = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc + 2, NULL); |
2052 | /* Low bit still set. */ | |
c5aa993b | 2053 | value |= nexthalf; |
12f02c2a AC |
2054 | offset = value; |
2055 | regx = -1; | |
2056 | regy = -1; | |
c5aa993b | 2057 | break; |
c906108c SS |
2058 | } |
2059 | default: | |
e2e0b3e5 | 2060 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c | 2061 | } |
12f02c2a AC |
2062 | upk->offset = offset; |
2063 | upk->regx = regx; | |
2064 | upk->regy = regy; | |
c906108c SS |
2065 | } |
2066 | ||
2067 | ||
c5aa993b JM |
2068 | static CORE_ADDR |
2069 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 2070 | { |
5b652102 | 2071 | return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff))); |
c906108c SS |
2072 | } |
2073 | ||
12f02c2a | 2074 | static CORE_ADDR |
0b1b3e42 | 2075 | extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc, |
6d82d43b | 2076 | unsigned int extension, unsigned int insn) |
c906108c | 2077 | { |
e17a4113 | 2078 | struct gdbarch *gdbarch = get_frame_arch (frame); |
12f02c2a AC |
2079 | int op = (insn >> 11); |
2080 | switch (op) | |
c906108c | 2081 | { |
6d82d43b | 2082 | case 2: /* Branch */ |
12f02c2a | 2083 | { |
12f02c2a | 2084 | struct upk_mips16 upk; |
e17a4113 | 2085 | unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk); |
4c2051c6 | 2086 | pc += (upk.offset << 1) + 2; |
12f02c2a AC |
2087 | break; |
2088 | } | |
025bb325 MS |
2089 | case 3: /* JAL , JALX - Watch out, these are 32 bit |
2090 | instructions. */ | |
12f02c2a AC |
2091 | { |
2092 | struct upk_mips16 upk; | |
e17a4113 | 2093 | unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk); |
12f02c2a AC |
2094 | pc = add_offset_16 (pc, upk.offset); |
2095 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
025bb325 | 2096 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode. */ |
12f02c2a AC |
2097 | else |
2098 | pc |= 0x01; | |
2099 | break; | |
2100 | } | |
6d82d43b | 2101 | case 4: /* beqz */ |
12f02c2a AC |
2102 | { |
2103 | struct upk_mips16 upk; | |
2104 | int reg; | |
e17a4113 | 2105 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
4cc0665f | 2106 | reg = get_frame_register_signed (frame, mips_reg3_to_reg[upk.regx]); |
12f02c2a AC |
2107 | if (reg == 0) |
2108 | pc += (upk.offset << 1) + 2; | |
2109 | else | |
2110 | pc += 2; | |
2111 | break; | |
2112 | } | |
6d82d43b | 2113 | case 5: /* bnez */ |
12f02c2a AC |
2114 | { |
2115 | struct upk_mips16 upk; | |
2116 | int reg; | |
e17a4113 | 2117 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
4cc0665f | 2118 | reg = get_frame_register_signed (frame, mips_reg3_to_reg[upk.regx]); |
12f02c2a AC |
2119 | if (reg != 0) |
2120 | pc += (upk.offset << 1) + 2; | |
2121 | else | |
2122 | pc += 2; | |
2123 | break; | |
2124 | } | |
6d82d43b | 2125 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
2126 | { |
2127 | struct upk_mips16 upk; | |
2128 | int reg; | |
e17a4113 | 2129 | unpack_mips16 (gdbarch, pc, extension, insn, i8type, &upk); |
12f02c2a | 2130 | /* upk.regx contains the opcode */ |
0b1b3e42 | 2131 | reg = get_frame_register_signed (frame, 24); /* Test register is 24 */ |
12f02c2a AC |
2132 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ |
2133 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
2134 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
2135 | pc += (upk.offset << 1) + 2; | |
2136 | else | |
2137 | pc += 2; | |
2138 | break; | |
2139 | } | |
6d82d43b | 2140 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
2141 | { |
2142 | struct upk_mips16 upk; | |
2143 | /* upk.fmt = rrtype; */ | |
2144 | op = insn & 0x1f; | |
2145 | if (op == 0) | |
c5aa993b | 2146 | { |
12f02c2a AC |
2147 | int reg; |
2148 | upk.regx = (insn >> 8) & 0x07; | |
2149 | upk.regy = (insn >> 5) & 0x07; | |
4c2051c6 | 2150 | if ((upk.regy & 1) == 0) |
4cc0665f | 2151 | reg = mips_reg3_to_reg[upk.regx]; |
4c2051c6 MR |
2152 | else |
2153 | reg = 31; /* Function return instruction. */ | |
0b1b3e42 | 2154 | pc = get_frame_register_signed (frame, reg); |
c906108c | 2155 | } |
12f02c2a | 2156 | else |
c5aa993b | 2157 | pc += 2; |
12f02c2a AC |
2158 | break; |
2159 | } | |
2160 | case 30: | |
2161 | /* This is an instruction extension. Fetch the real instruction | |
2162 | (which follows the extension) and decode things based on | |
025bb325 | 2163 | that. */ |
12f02c2a AC |
2164 | { |
2165 | pc += 2; | |
e17a4113 UW |
2166 | pc = extended_mips16_next_pc (frame, pc, insn, |
2167 | fetch_mips_16 (gdbarch, pc)); | |
12f02c2a AC |
2168 | break; |
2169 | } | |
2170 | default: | |
2171 | { | |
2172 | pc += 2; | |
2173 | break; | |
2174 | } | |
c906108c | 2175 | } |
c5aa993b | 2176 | return pc; |
12f02c2a | 2177 | } |
c906108c | 2178 | |
5a89d8aa | 2179 | static CORE_ADDR |
0b1b3e42 | 2180 | mips16_next_pc (struct frame_info *frame, CORE_ADDR pc) |
12f02c2a | 2181 | { |
e17a4113 UW |
2182 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2183 | unsigned int insn = fetch_mips_16 (gdbarch, pc); | |
0b1b3e42 | 2184 | return extended_mips16_next_pc (frame, pc, 0, insn); |
12f02c2a AC |
2185 | } |
2186 | ||
2187 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 2188 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a | 2189 | It works by decoding the current instruction and predicting where a |
025bb325 | 2190 | branch will go. This isnt hard because all the data is available. |
4cc0665f | 2191 | The MIPS32, MIPS16 and microMIPS variants are quite different. */ |
ad527d2e | 2192 | static CORE_ADDR |
0b1b3e42 | 2193 | mips_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 2194 | { |
4cc0665f MR |
2195 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2196 | ||
2197 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
0b1b3e42 | 2198 | return mips16_next_pc (frame, pc); |
4cc0665f MR |
2199 | else if (mips_pc_is_micromips (gdbarch, pc)) |
2200 | return micromips_next_pc (frame, pc); | |
c5aa993b | 2201 | else |
0b1b3e42 | 2202 | return mips32_next_pc (frame, pc); |
12f02c2a | 2203 | } |
c906108c | 2204 | |
edfae063 AC |
2205 | struct mips_frame_cache |
2206 | { | |
2207 | CORE_ADDR base; | |
2208 | struct trad_frame_saved_reg *saved_regs; | |
2209 | }; | |
2210 | ||
29639122 JB |
2211 | /* Set a register's saved stack address in temp_saved_regs. If an |
2212 | address has already been set for this register, do nothing; this | |
2213 | way we will only recognize the first save of a given register in a | |
2214 | function prologue. | |
eec63939 | 2215 | |
f57d151a UW |
2216 | For simplicity, save the address in both [0 .. gdbarch_num_regs) and |
2217 | [gdbarch_num_regs .. 2*gdbarch_num_regs). | |
2218 | Strictly speaking, only the second range is used as it is only second | |
2219 | range (the ABI instead of ISA registers) that comes into play when finding | |
2220 | saved registers in a frame. */ | |
eec63939 AC |
2221 | |
2222 | static void | |
74ed0bb4 MD |
2223 | set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache, |
2224 | int regnum, CORE_ADDR offset) | |
eec63939 | 2225 | { |
29639122 JB |
2226 | if (this_cache != NULL |
2227 | && this_cache->saved_regs[regnum].addr == -1) | |
2228 | { | |
74ed0bb4 MD |
2229 | this_cache->saved_regs[regnum + 0 * gdbarch_num_regs (gdbarch)].addr |
2230 | = offset; | |
2231 | this_cache->saved_regs[regnum + 1 * gdbarch_num_regs (gdbarch)].addr | |
2232 | = offset; | |
29639122 | 2233 | } |
eec63939 AC |
2234 | } |
2235 | ||
eec63939 | 2236 | |
29639122 JB |
2237 | /* Fetch the immediate value from a MIPS16 instruction. |
2238 | If the previous instruction was an EXTEND, use it to extend | |
2239 | the upper bits of the immediate value. This is a helper function | |
2240 | for mips16_scan_prologue. */ | |
eec63939 | 2241 | |
29639122 JB |
2242 | static int |
2243 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ | |
2244 | unsigned short inst, /* current instruction */ | |
2245 | int nbits, /* number of bits in imm field */ | |
2246 | int scale, /* scale factor to be applied to imm */ | |
025bb325 | 2247 | int is_signed) /* is the imm field signed? */ |
eec63939 | 2248 | { |
29639122 | 2249 | int offset; |
eec63939 | 2250 | |
29639122 JB |
2251 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
2252 | { | |
2253 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
2254 | if (offset & 0x8000) /* check for negative extend */ | |
2255 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
2256 | return offset | (inst & 0x1f); | |
2257 | } | |
eec63939 | 2258 | else |
29639122 JB |
2259 | { |
2260 | int max_imm = 1 << nbits; | |
2261 | int mask = max_imm - 1; | |
2262 | int sign_bit = max_imm >> 1; | |
45c9dd44 | 2263 | |
29639122 JB |
2264 | offset = inst & mask; |
2265 | if (is_signed && (offset & sign_bit)) | |
2266 | offset = 0 - (max_imm - offset); | |
2267 | return offset * scale; | |
2268 | } | |
2269 | } | |
eec63939 | 2270 | |
65596487 | 2271 | |
29639122 JB |
2272 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
2273 | the associated FRAME_CACHE if not null. | |
2274 | Return the address of the first instruction past the prologue. */ | |
eec63939 | 2275 | |
29639122 | 2276 | static CORE_ADDR |
e17a4113 UW |
2277 | mips16_scan_prologue (struct gdbarch *gdbarch, |
2278 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 2279 | struct frame_info *this_frame, |
29639122 JB |
2280 | struct mips_frame_cache *this_cache) |
2281 | { | |
2282 | CORE_ADDR cur_pc; | |
025bb325 | 2283 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer. */ |
29639122 JB |
2284 | CORE_ADDR sp; |
2285 | long frame_offset = 0; /* Size of stack frame. */ | |
2286 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
2287 | int frame_reg = MIPS_SP_REGNUM; | |
025bb325 | 2288 | unsigned short prev_inst = 0; /* saved copy of previous instruction. */ |
29639122 JB |
2289 | unsigned inst = 0; /* current instruction */ |
2290 | unsigned entry_inst = 0; /* the entry instruction */ | |
2207132d | 2291 | unsigned save_inst = 0; /* the save instruction */ |
29639122 | 2292 | int reg, offset; |
a343eb3c | 2293 | |
29639122 JB |
2294 | int extend_bytes = 0; |
2295 | int prev_extend_bytes; | |
2296 | CORE_ADDR end_prologue_addr = 0; | |
a343eb3c | 2297 | |
29639122 | 2298 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
2299 | THIS_FRAME. */ |
2300 | if (this_frame != NULL) | |
2301 | sp = get_frame_register_signed (this_frame, | |
2302 | gdbarch_num_regs (gdbarch) | |
2303 | + MIPS_SP_REGNUM); | |
29639122 JB |
2304 | else |
2305 | sp = 0; | |
eec63939 | 2306 | |
29639122 JB |
2307 | if (limit_pc > start_pc + 200) |
2308 | limit_pc = start_pc + 200; | |
eec63939 | 2309 | |
95ac2dcf | 2310 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) |
29639122 JB |
2311 | { |
2312 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
2313 | the immediate offset extension from it in mips16_get_imm. */ | |
2314 | prev_inst = inst; | |
eec63939 | 2315 | |
025bb325 | 2316 | /* Fetch and decode the instruction. */ |
4cc0665f MR |
2317 | inst = (unsigned short) mips_fetch_instruction (gdbarch, ISA_MIPS16, |
2318 | cur_pc, NULL); | |
eec63939 | 2319 | |
29639122 JB |
2320 | /* Normally we ignore extend instructions. However, if it is |
2321 | not followed by a valid prologue instruction, then this | |
2322 | instruction is not part of the prologue either. We must | |
2323 | remember in this case to adjust the end_prologue_addr back | |
2324 | over the extend. */ | |
2325 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
2326 | { | |
95ac2dcf | 2327 | extend_bytes = MIPS_INSN16_SIZE; |
29639122 JB |
2328 | continue; |
2329 | } | |
eec63939 | 2330 | |
29639122 JB |
2331 | prev_extend_bytes = extend_bytes; |
2332 | extend_bytes = 0; | |
eec63939 | 2333 | |
29639122 JB |
2334 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
2335 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2336 | { | |
2337 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
025bb325 | 2338 | if (offset < 0) /* Negative stack adjustment? */ |
29639122 JB |
2339 | frame_offset -= offset; |
2340 | else | |
2341 | /* Exit loop if a positive stack adjustment is found, which | |
2342 | usually means that the stack cleanup code in the function | |
2343 | epilogue is reached. */ | |
2344 | break; | |
2345 | } | |
2346 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
2347 | { | |
2348 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
4cc0665f | 2349 | reg = mips_reg3_to_reg[(inst & 0x700) >> 8]; |
74ed0bb4 | 2350 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
2351 | } |
2352 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
2353 | { | |
2354 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
4cc0665f | 2355 | reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
74ed0bb4 | 2356 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
2357 | } |
2358 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
2359 | { | |
2360 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
74ed0bb4 | 2361 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
2362 | } |
2363 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
2364 | { | |
2365 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
74ed0bb4 | 2366 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
2367 | } |
2368 | else if (inst == 0x673d) /* move $s1, $sp */ | |
2369 | { | |
2370 | frame_addr = sp; | |
2371 | frame_reg = 17; | |
2372 | } | |
2373 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
2374 | { | |
2375 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2376 | frame_addr = sp + offset; | |
2377 | frame_reg = 17; | |
2378 | frame_adjust = offset; | |
2379 | } | |
2380 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
2381 | { | |
2382 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
4cc0665f | 2383 | reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
74ed0bb4 | 2384 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
2385 | } |
2386 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
2387 | { | |
2388 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
4cc0665f | 2389 | reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
74ed0bb4 | 2390 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
2391 | } |
2392 | else if ((inst & 0xf81f) == 0xe809 | |
2393 | && (inst & 0x700) != 0x700) /* entry */ | |
025bb325 | 2394 | entry_inst = inst; /* Save for later processing. */ |
2207132d MR |
2395 | else if ((inst & 0xff80) == 0x6480) /* save */ |
2396 | { | |
025bb325 | 2397 | save_inst = inst; /* Save for later processing. */ |
2207132d MR |
2398 | if (prev_extend_bytes) /* extend */ |
2399 | save_inst |= prev_inst << 16; | |
2400 | } | |
29639122 | 2401 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
95ac2dcf | 2402 | cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ |
29639122 JB |
2403 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
2404 | { | |
2405 | /* This instruction is part of the prologue, but we don't | |
2406 | need to do anything special to handle it. */ | |
2407 | } | |
2408 | else | |
2409 | { | |
2410 | /* This instruction is not an instruction typically found | |
2411 | in a prologue, so we must have reached the end of the | |
2412 | prologue. */ | |
2413 | if (end_prologue_addr == 0) | |
2414 | end_prologue_addr = cur_pc - prev_extend_bytes; | |
2415 | } | |
2416 | } | |
eec63939 | 2417 | |
29639122 JB |
2418 | /* The entry instruction is typically the first instruction in a function, |
2419 | and it stores registers at offsets relative to the value of the old SP | |
2420 | (before the prologue). But the value of the sp parameter to this | |
2421 | function is the new SP (after the prologue has been executed). So we | |
2422 | can't calculate those offsets until we've seen the entire prologue, | |
025bb325 | 2423 | and can calculate what the old SP must have been. */ |
29639122 JB |
2424 | if (entry_inst != 0) |
2425 | { | |
2426 | int areg_count = (entry_inst >> 8) & 7; | |
2427 | int sreg_count = (entry_inst >> 6) & 3; | |
eec63939 | 2428 | |
29639122 JB |
2429 | /* The entry instruction always subtracts 32 from the SP. */ |
2430 | frame_offset += 32; | |
2431 | ||
2432 | /* Now we can calculate what the SP must have been at the | |
2433 | start of the function prologue. */ | |
2434 | sp += frame_offset; | |
2435 | ||
2436 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
2437 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
2438 | { | |
74ed0bb4 | 2439 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 2440 | offset += mips_abi_regsize (gdbarch); |
29639122 JB |
2441 | } |
2442 | ||
2443 | /* Check if the ra register was pushed on the stack. */ | |
2444 | offset = -4; | |
2445 | if (entry_inst & 0x20) | |
2446 | { | |
74ed0bb4 | 2447 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
72a155b4 | 2448 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
2449 | } |
2450 | ||
2451 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
2452 | for (reg = 16; reg < sreg_count + 16; reg++) | |
2453 | { | |
74ed0bb4 | 2454 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 2455 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
2456 | } |
2457 | } | |
2458 | ||
2207132d MR |
2459 | /* The SAVE instruction is similar to ENTRY, except that defined by the |
2460 | MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the | |
2461 | size of the frame is specified as an immediate field of instruction | |
2462 | and an extended variation exists which lets additional registers and | |
2463 | frame space to be specified. The instruction always treats registers | |
2464 | as 32-bit so its usefulness for 64-bit ABIs is questionable. */ | |
2465 | if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4) | |
2466 | { | |
2467 | static int args_table[16] = { | |
2468 | 0, 0, 0, 0, 1, 1, 1, 1, | |
2469 | 2, 2, 2, 0, 3, 3, 4, -1, | |
2470 | }; | |
2471 | static int astatic_table[16] = { | |
2472 | 0, 1, 2, 3, 0, 1, 2, 3, | |
2473 | 0, 1, 2, 4, 0, 1, 0, -1, | |
2474 | }; | |
2475 | int aregs = (save_inst >> 16) & 0xf; | |
2476 | int xsregs = (save_inst >> 24) & 0x7; | |
2477 | int args = args_table[aregs]; | |
2478 | int astatic = astatic_table[aregs]; | |
2479 | long frame_size; | |
2480 | ||
2481 | if (args < 0) | |
2482 | { | |
2483 | warning (_("Invalid number of argument registers encoded in SAVE.")); | |
2484 | args = 0; | |
2485 | } | |
2486 | if (astatic < 0) | |
2487 | { | |
2488 | warning (_("Invalid number of static registers encoded in SAVE.")); | |
2489 | astatic = 0; | |
2490 | } | |
2491 | ||
2492 | /* For standard SAVE the frame size of 0 means 128. */ | |
2493 | frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf); | |
2494 | if (frame_size == 0 && (save_inst >> 16) == 0) | |
2495 | frame_size = 16; | |
2496 | frame_size *= 8; | |
2497 | frame_offset += frame_size; | |
2498 | ||
2499 | /* Now we can calculate what the SP must have been at the | |
2500 | start of the function prologue. */ | |
2501 | sp += frame_offset; | |
2502 | ||
2503 | /* Check if A0-A3 were saved in the caller's argument save area. */ | |
2504 | for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++) | |
2505 | { | |
74ed0bb4 | 2506 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
2507 | offset += mips_abi_regsize (gdbarch); |
2508 | } | |
2509 | ||
2510 | offset = -4; | |
2511 | ||
2512 | /* Check if the RA register was pushed on the stack. */ | |
2513 | if (save_inst & 0x40) | |
2514 | { | |
74ed0bb4 | 2515 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
2207132d MR |
2516 | offset -= mips_abi_regsize (gdbarch); |
2517 | } | |
2518 | ||
2519 | /* Check if the S8 register was pushed on the stack. */ | |
2520 | if (xsregs > 6) | |
2521 | { | |
74ed0bb4 | 2522 | set_reg_offset (gdbarch, this_cache, 30, sp + offset); |
2207132d MR |
2523 | offset -= mips_abi_regsize (gdbarch); |
2524 | xsregs--; | |
2525 | } | |
2526 | /* Check if S2-S7 were pushed on the stack. */ | |
2527 | for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--) | |
2528 | { | |
74ed0bb4 | 2529 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
2530 | offset -= mips_abi_regsize (gdbarch); |
2531 | } | |
2532 | ||
2533 | /* Check if the S1 register was pushed on the stack. */ | |
2534 | if (save_inst & 0x10) | |
2535 | { | |
74ed0bb4 | 2536 | set_reg_offset (gdbarch, this_cache, 17, sp + offset); |
2207132d MR |
2537 | offset -= mips_abi_regsize (gdbarch); |
2538 | } | |
2539 | /* Check if the S0 register was pushed on the stack. */ | |
2540 | if (save_inst & 0x20) | |
2541 | { | |
74ed0bb4 | 2542 | set_reg_offset (gdbarch, this_cache, 16, sp + offset); |
2207132d MR |
2543 | offset -= mips_abi_regsize (gdbarch); |
2544 | } | |
2545 | ||
4cc0665f MR |
2546 | /* Check if A0-A3 were pushed on the stack. */ |
2547 | for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--) | |
2548 | { | |
2549 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); | |
2550 | offset -= mips_abi_regsize (gdbarch); | |
2551 | } | |
2552 | } | |
2553 | ||
2554 | if (this_cache != NULL) | |
2555 | { | |
2556 | this_cache->base = | |
2557 | (get_frame_register_signed (this_frame, | |
2558 | gdbarch_num_regs (gdbarch) + frame_reg) | |
2559 | + frame_offset - frame_adjust); | |
2560 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should | |
2561 | be able to get rid of the assignment below, evetually. But it's | |
2562 | still needed for now. */ | |
2563 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) | |
2564 | + mips_regnum (gdbarch)->pc] | |
2565 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; | |
2566 | } | |
2567 | ||
2568 | /* If we didn't reach the end of the prologue when scanning the function | |
2569 | instructions, then set end_prologue_addr to the address of the | |
2570 | instruction immediately after the last one we scanned. */ | |
2571 | if (end_prologue_addr == 0) | |
2572 | end_prologue_addr = cur_pc; | |
2573 | ||
2574 | return end_prologue_addr; | |
2575 | } | |
2576 | ||
2577 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). | |
2578 | Procedures that use the 32-bit instruction set are handled by the | |
2579 | mips_insn32 unwinder. */ | |
2580 | ||
2581 | static struct mips_frame_cache * | |
2582 | mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache) | |
2583 | { | |
2584 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2585 | struct mips_frame_cache *cache; | |
2586 | ||
2587 | if ((*this_cache) != NULL) | |
2588 | return (*this_cache); | |
2589 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); | |
2590 | (*this_cache) = cache; | |
2591 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
2592 | ||
2593 | /* Analyze the function prologue. */ | |
2594 | { | |
2595 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); | |
2596 | CORE_ADDR start_addr; | |
2597 | ||
2598 | find_pc_partial_function (pc, NULL, &start_addr, NULL); | |
2599 | if (start_addr == 0) | |
2600 | start_addr = heuristic_proc_start (gdbarch, pc); | |
2601 | /* We can't analyze the prologue if we couldn't find the begining | |
2602 | of the function. */ | |
2603 | if (start_addr == 0) | |
2604 | return cache; | |
2605 | ||
2606 | mips16_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); | |
2607 | } | |
2608 | ||
2609 | /* gdbarch_sp_regnum contains the value and not the address. */ | |
2610 | trad_frame_set_value (cache->saved_regs, | |
2611 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, | |
2612 | cache->base); | |
2613 | ||
2614 | return (*this_cache); | |
2615 | } | |
2616 | ||
2617 | static void | |
2618 | mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache, | |
2619 | struct frame_id *this_id) | |
2620 | { | |
2621 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, | |
2622 | this_cache); | |
2623 | /* This marks the outermost frame. */ | |
2624 | if (info->base == 0) | |
2625 | return; | |
2626 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); | |
2627 | } | |
2628 | ||
2629 | static struct value * | |
2630 | mips_insn16_frame_prev_register (struct frame_info *this_frame, | |
2631 | void **this_cache, int regnum) | |
2632 | { | |
2633 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, | |
2634 | this_cache); | |
2635 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); | |
2636 | } | |
2637 | ||
2638 | static int | |
2639 | mips_insn16_frame_sniffer (const struct frame_unwind *self, | |
2640 | struct frame_info *this_frame, void **this_cache) | |
2641 | { | |
2642 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2643 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2644 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
2645 | return 1; | |
2646 | return 0; | |
2647 | } | |
2648 | ||
2649 | static const struct frame_unwind mips_insn16_frame_unwind = | |
2650 | { | |
2651 | NORMAL_FRAME, | |
2652 | default_frame_unwind_stop_reason, | |
2653 | mips_insn16_frame_this_id, | |
2654 | mips_insn16_frame_prev_register, | |
2655 | NULL, | |
2656 | mips_insn16_frame_sniffer | |
2657 | }; | |
2658 | ||
2659 | static CORE_ADDR | |
2660 | mips_insn16_frame_base_address (struct frame_info *this_frame, | |
2661 | void **this_cache) | |
2662 | { | |
2663 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, | |
2664 | this_cache); | |
2665 | return info->base; | |
2666 | } | |
2667 | ||
2668 | static const struct frame_base mips_insn16_frame_base = | |
2669 | { | |
2670 | &mips_insn16_frame_unwind, | |
2671 | mips_insn16_frame_base_address, | |
2672 | mips_insn16_frame_base_address, | |
2673 | mips_insn16_frame_base_address | |
2674 | }; | |
2675 | ||
2676 | static const struct frame_base * | |
2677 | mips_insn16_frame_base_sniffer (struct frame_info *this_frame) | |
2678 | { | |
2679 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2680 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2681 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
2682 | return &mips_insn16_frame_base; | |
2683 | else | |
2684 | return NULL; | |
2685 | } | |
2686 | ||
2687 | /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped | |
2688 | to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are | |
2689 | interpreted directly, and then multiplied by 4. */ | |
2690 | ||
2691 | static int | |
2692 | micromips_decode_imm9 (int imm) | |
2693 | { | |
2694 | imm = (imm ^ 0x100) - 0x100; | |
2695 | if (imm > -3 && imm < 2) | |
2696 | imm ^= 0x100; | |
2697 | return imm << 2; | |
2698 | } | |
2699 | ||
2700 | /* Analyze the function prologue from START_PC to LIMIT_PC. Return | |
2701 | the address of the first instruction past the prologue. */ | |
2702 | ||
2703 | static CORE_ADDR | |
2704 | micromips_scan_prologue (struct gdbarch *gdbarch, | |
2705 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
2706 | struct frame_info *this_frame, | |
2707 | struct mips_frame_cache *this_cache) | |
2708 | { | |
2709 | CORE_ADDR end_prologue_addr = 0; | |
2710 | int prev_non_prologue_insn = 0; | |
2711 | int frame_reg = MIPS_SP_REGNUM; | |
2712 | int this_non_prologue_insn; | |
2713 | int non_prologue_insns = 0; | |
2714 | long frame_offset = 0; /* Size of stack frame. */ | |
2715 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
2716 | CORE_ADDR frame_addr = 0; /* Value of $30, used as frame pointer. */ | |
2717 | CORE_ADDR prev_pc; | |
2718 | CORE_ADDR cur_pc; | |
2719 | ULONGEST insn; /* current instruction */ | |
2720 | CORE_ADDR sp; | |
2721 | long offset; | |
2722 | long sp_adj; | |
2723 | long v1_off = 0; /* The assumption is LUI will replace it. */ | |
2724 | int reglist; | |
2725 | int breg; | |
2726 | int dreg; | |
2727 | int sreg; | |
2728 | int treg; | |
2729 | int loc; | |
2730 | int op; | |
2731 | int s; | |
2732 | int i; | |
2733 | ||
2734 | /* Can be called when there's no process, and hence when there's no | |
2735 | THIS_FRAME. */ | |
2736 | if (this_frame != NULL) | |
2737 | sp = get_frame_register_signed (this_frame, | |
2738 | gdbarch_num_regs (gdbarch) | |
2739 | + MIPS_SP_REGNUM); | |
2740 | else | |
2741 | sp = 0; | |
2742 | ||
2743 | if (limit_pc > start_pc + 200) | |
2744 | limit_pc = start_pc + 200; | |
2745 | prev_pc = start_pc; | |
2746 | ||
2747 | /* Permit at most one non-prologue non-control-transfer instruction | |
2748 | in the middle which may have been reordered by the compiler for | |
2749 | optimisation. */ | |
2750 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += loc) | |
2751 | { | |
2752 | this_non_prologue_insn = 0; | |
2753 | sp_adj = 0; | |
2754 | loc = 0; | |
2755 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, cur_pc, NULL); | |
2756 | loc += MIPS_INSN16_SIZE; | |
2757 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
2758 | { | |
2759 | /* 48-bit instructions. */ | |
2760 | case 3 * MIPS_INSN16_SIZE: | |
2761 | /* No prologue instructions in this category. */ | |
2762 | this_non_prologue_insn = 1; | |
2763 | loc += 2 * MIPS_INSN16_SIZE; | |
2764 | break; | |
2765 | ||
2766 | /* 32-bit instructions. */ | |
2767 | case 2 * MIPS_INSN16_SIZE: | |
2768 | insn <<= 16; | |
2769 | insn |= mips_fetch_instruction (gdbarch, | |
2770 | ISA_MICROMIPS, cur_pc + loc, NULL); | |
2771 | loc += MIPS_INSN16_SIZE; | |
2772 | switch (micromips_op (insn >> 16)) | |
2773 | { | |
2774 | /* Record $sp/$fp adjustment. */ | |
2775 | /* Discard (D)ADDU $gp,$jp used for PIC code. */ | |
2776 | case 0x0: /* POOL32A: bits 000000 */ | |
2777 | case 0x16: /* POOL32S: bits 010110 */ | |
2778 | op = b0s11_op (insn); | |
2779 | sreg = b0s5_reg (insn >> 16); | |
2780 | treg = b5s5_reg (insn >> 16); | |
2781 | dreg = b11s5_reg (insn); | |
2782 | if (op == 0x1d0 | |
2783 | /* SUBU: bits 000000 00111010000 */ | |
2784 | /* DSUBU: bits 010110 00111010000 */ | |
2785 | && dreg == MIPS_SP_REGNUM && sreg == MIPS_SP_REGNUM | |
2786 | && treg == 3) | |
2787 | /* (D)SUBU $sp, $v1 */ | |
2788 | sp_adj = v1_off; | |
2789 | else if (op != 0x150 | |
2790 | /* ADDU: bits 000000 00101010000 */ | |
2791 | /* DADDU: bits 010110 00101010000 */ | |
2792 | || dreg != 28 || sreg != 28 || treg != MIPS_T9_REGNUM) | |
2793 | this_non_prologue_insn = 1; | |
2794 | break; | |
2795 | ||
2796 | case 0x8: /* POOL32B: bits 001000 */ | |
2797 | op = b12s4_op (insn); | |
2798 | breg = b0s5_reg (insn >> 16); | |
2799 | reglist = sreg = b5s5_reg (insn >> 16); | |
2800 | offset = (b0s12_imm (insn) ^ 0x800) - 0x800; | |
2801 | if ((op == 0x9 || op == 0xc) | |
2802 | /* SWP: bits 001000 1001 */ | |
2803 | /* SDP: bits 001000 1100 */ | |
2804 | && breg == MIPS_SP_REGNUM && sreg < MIPS_RA_REGNUM) | |
2805 | /* S[DW]P reg,offset($sp) */ | |
2806 | { | |
2807 | s = 4 << ((b12s4_op (insn) & 0x4) == 0x4); | |
2808 | set_reg_offset (gdbarch, this_cache, | |
2809 | sreg, sp + offset); | |
2810 | set_reg_offset (gdbarch, this_cache, | |
2811 | sreg + 1, sp + offset + s); | |
2812 | } | |
2813 | else if ((op == 0xd || op == 0xf) | |
2814 | /* SWM: bits 001000 1101 */ | |
2815 | /* SDM: bits 001000 1111 */ | |
2816 | && breg == MIPS_SP_REGNUM | |
2817 | /* SWM reglist,offset($sp) */ | |
2818 | && ((reglist >= 1 && reglist <= 9) | |
2819 | || (reglist >= 16 && reglist <= 25))) | |
2820 | { | |
2821 | int sreglist = min(reglist & 0xf, 8); | |
2822 | ||
2823 | s = 4 << ((b12s4_op (insn) & 0x2) == 0x2); | |
2824 | for (i = 0; i < sreglist; i++) | |
2825 | set_reg_offset (gdbarch, this_cache, 16 + i, sp + s * i); | |
2826 | if ((reglist & 0xf) > 8) | |
2827 | set_reg_offset (gdbarch, this_cache, 30, sp + s * i++); | |
2828 | if ((reglist & 0x10) == 0x10) | |
2829 | set_reg_offset (gdbarch, this_cache, | |
2830 | MIPS_RA_REGNUM, sp + s * i++); | |
2831 | } | |
2832 | else | |
2833 | this_non_prologue_insn = 1; | |
2834 | break; | |
2835 | ||
2836 | /* Record $sp/$fp adjustment. */ | |
2837 | /* Discard (D)ADDIU $gp used for PIC code. */ | |
2838 | case 0xc: /* ADDIU: bits 001100 */ | |
2839 | case 0x17: /* DADDIU: bits 010111 */ | |
2840 | sreg = b0s5_reg (insn >> 16); | |
2841 | dreg = b5s5_reg (insn >> 16); | |
2842 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
2843 | if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM) | |
2844 | /* (D)ADDIU $sp, imm */ | |
2845 | sp_adj = offset; | |
2846 | else if (sreg == MIPS_SP_REGNUM && dreg == 30) | |
2847 | /* (D)ADDIU $fp, $sp, imm */ | |
2848 | { | |
2849 | frame_addr = sp + offset; | |
2850 | frame_adjust = offset; | |
2851 | frame_reg = 30; | |
2852 | } | |
2853 | else if (sreg != 28 || dreg != 28) | |
2854 | /* (D)ADDIU $gp, imm */ | |
2855 | this_non_prologue_insn = 1; | |
2856 | break; | |
2857 | ||
2858 | /* LUI $v1 is used for larger $sp adjustments. */ | |
2859 | /* Discard LUI $gp is used for PIC code. */ | |
2860 | case 0x10: /* POOL32I: bits 010000 */ | |
2861 | if (b5s5_op (insn >> 16) == 0xd | |
2862 | /* LUI: bits 010000 001101 */ | |
2863 | && b0s5_reg (insn >> 16) == 3) | |
2864 | /* LUI $v1, imm */ | |
2865 | v1_off = ((b0s16_imm (insn) << 16) ^ 0x80000000) - 0x80000000; | |
2866 | else if (b5s5_op (insn >> 16) != 0xd | |
2867 | /* LUI: bits 010000 001101 */ | |
2868 | || b0s5_reg (insn >> 16) != 28) | |
2869 | /* LUI $gp, imm */ | |
2870 | this_non_prologue_insn = 1; | |
2871 | break; | |
2872 | ||
2873 | /* ORI $v1 is used for larger $sp adjustments. */ | |
2874 | case 0x14: /* ORI: bits 010100 */ | |
2875 | sreg = b0s5_reg (insn >> 16); | |
2876 | dreg = b5s5_reg (insn >> 16); | |
2877 | if (sreg == 3 && dreg == 3) | |
2878 | /* ORI $v1, imm */ | |
2879 | v1_off |= b0s16_imm (insn); | |
2880 | else | |
2881 | this_non_prologue_insn = 1; | |
2882 | break; | |
2883 | ||
2884 | case 0x26: /* SWC1: bits 100110 */ | |
2885 | case 0x2e: /* SDC1: bits 101110 */ | |
2886 | breg = b0s5_reg (insn >> 16); | |
2887 | if (breg != MIPS_SP_REGNUM) | |
2888 | /* S[DW]C1 reg,offset($sp) */ | |
2889 | this_non_prologue_insn = 1; | |
2890 | break; | |
2891 | ||
2892 | case 0x36: /* SD: bits 110110 */ | |
2893 | case 0x3e: /* SW: bits 111110 */ | |
2894 | breg = b0s5_reg (insn >> 16); | |
2895 | sreg = b5s5_reg (insn >> 16); | |
2896 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
2897 | if (breg == MIPS_SP_REGNUM) | |
2898 | /* S[DW] reg,offset($sp) */ | |
2899 | set_reg_offset (gdbarch, this_cache, sreg, sp + offset); | |
2900 | else | |
2901 | this_non_prologue_insn = 1; | |
2902 | break; | |
2903 | ||
2904 | default: | |
2905 | this_non_prologue_insn = 1; | |
2906 | break; | |
2907 | } | |
2908 | break; | |
2909 | ||
2910 | /* 16-bit instructions. */ | |
2911 | case MIPS_INSN16_SIZE: | |
2912 | switch (micromips_op (insn)) | |
2913 | { | |
2914 | case 0x3: /* MOVE: bits 000011 */ | |
2915 | sreg = b0s5_reg (insn); | |
2916 | dreg = b5s5_reg (insn); | |
2917 | if (sreg == MIPS_SP_REGNUM && dreg == 30) | |
2918 | /* MOVE $fp, $sp */ | |
2919 | { | |
2920 | frame_addr = sp; | |
2921 | frame_reg = 30; | |
2922 | } | |
2923 | else if ((sreg & 0x1c) != 0x4) | |
2924 | /* MOVE reg, $a0-$a3 */ | |
2925 | this_non_prologue_insn = 1; | |
2926 | break; | |
2927 | ||
2928 | case 0x11: /* POOL16C: bits 010001 */ | |
2929 | if (b6s4_op (insn) == 0x5) | |
2930 | /* SWM: bits 010001 0101 */ | |
2931 | { | |
2932 | offset = ((b0s4_imm (insn) << 2) ^ 0x20) - 0x20; | |
2933 | reglist = b4s2_regl (insn); | |
2934 | for (i = 0; i <= reglist; i++) | |
2935 | set_reg_offset (gdbarch, this_cache, 16 + i, sp + 4 * i); | |
2936 | set_reg_offset (gdbarch, this_cache, | |
2937 | MIPS_RA_REGNUM, sp + 4 * i++); | |
2938 | } | |
2939 | else | |
2940 | this_non_prologue_insn = 1; | |
2941 | break; | |
2942 | ||
2943 | case 0x13: /* POOL16D: bits 010011 */ | |
2944 | if ((insn & 0x1) == 0x1) | |
2945 | /* ADDIUSP: bits 010011 1 */ | |
2946 | sp_adj = micromips_decode_imm9 (b1s9_imm (insn)); | |
2947 | else if (b5s5_reg (insn) == MIPS_SP_REGNUM) | |
2948 | /* ADDIUS5: bits 010011 0 */ | |
2949 | /* ADDIUS5 $sp, imm */ | |
2950 | sp_adj = (b1s4_imm (insn) ^ 8) - 8; | |
2951 | else | |
2952 | this_non_prologue_insn = 1; | |
2953 | break; | |
2954 | ||
2955 | case 0x32: /* SWSP: bits 110010 */ | |
2956 | offset = b0s5_imm (insn) << 2; | |
2957 | sreg = b5s5_reg (insn); | |
2958 | set_reg_offset (gdbarch, this_cache, sreg, sp + offset); | |
2959 | break; | |
2960 | ||
2961 | default: | |
2962 | this_non_prologue_insn = 1; | |
2963 | break; | |
2964 | } | |
2965 | break; | |
2966 | } | |
2967 | if (sp_adj < 0) | |
2968 | frame_offset -= sp_adj; | |
2969 | ||
2970 | non_prologue_insns += this_non_prologue_insn; | |
2971 | /* Enough non-prologue insns seen or positive stack adjustment? */ | |
2972 | if (end_prologue_addr == 0 && (non_prologue_insns > 1 || sp_adj > 0)) | |
2207132d | 2973 | { |
4cc0665f MR |
2974 | end_prologue_addr = prev_non_prologue_insn ? prev_pc : cur_pc; |
2975 | break; | |
2207132d | 2976 | } |
4cc0665f MR |
2977 | prev_non_prologue_insn = this_non_prologue_insn; |
2978 | prev_pc = cur_pc; | |
2207132d MR |
2979 | } |
2980 | ||
29639122 JB |
2981 | if (this_cache != NULL) |
2982 | { | |
2983 | this_cache->base = | |
4cc0665f | 2984 | (get_frame_register_signed (this_frame, |
b8a22b94 | 2985 | gdbarch_num_regs (gdbarch) + frame_reg) |
4cc0665f | 2986 | + frame_offset - frame_adjust); |
29639122 | 2987 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should |
4cc0665f MR |
2988 | be able to get rid of the assignment below, evetually. But it's |
2989 | still needed for now. */ | |
72a155b4 UW |
2990 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
2991 | + mips_regnum (gdbarch)->pc] | |
4cc0665f | 2992 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; |
29639122 JB |
2993 | } |
2994 | ||
2995 | /* If we didn't reach the end of the prologue when scanning the function | |
2996 | instructions, then set end_prologue_addr to the address of the | |
4cc0665f MR |
2997 | instruction immediately after the last one we scanned. Unless the |
2998 | last one looked like a non-prologue instruction (and we looked ahead), | |
2999 | in which case use its address instead. */ | |
29639122 | 3000 | if (end_prologue_addr == 0) |
4cc0665f | 3001 | end_prologue_addr = prev_non_prologue_insn ? prev_pc : cur_pc; |
29639122 JB |
3002 | |
3003 | return end_prologue_addr; | |
eec63939 AC |
3004 | } |
3005 | ||
4cc0665f | 3006 | /* Heuristic unwinder for procedures using microMIPS instructions. |
29639122 | 3007 | Procedures that use the 32-bit instruction set are handled by the |
4cc0665f | 3008 | mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */ |
29639122 JB |
3009 | |
3010 | static struct mips_frame_cache * | |
4cc0665f | 3011 | mips_micro_frame_cache (struct frame_info *this_frame, void **this_cache) |
eec63939 | 3012 | { |
e17a4113 | 3013 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 3014 | struct mips_frame_cache *cache; |
eec63939 AC |
3015 | |
3016 | if ((*this_cache) != NULL) | |
3017 | return (*this_cache); | |
4cc0665f | 3018 | |
29639122 JB |
3019 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
3020 | (*this_cache) = cache; | |
b8a22b94 | 3021 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
eec63939 | 3022 | |
29639122 JB |
3023 | /* Analyze the function prologue. */ |
3024 | { | |
b8a22b94 | 3025 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 3026 | CORE_ADDR start_addr; |
eec63939 | 3027 | |
29639122 JB |
3028 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
3029 | if (start_addr == 0) | |
4cc0665f | 3030 | start_addr = heuristic_proc_start (get_frame_arch (this_frame), pc); |
29639122 JB |
3031 | /* We can't analyze the prologue if we couldn't find the begining |
3032 | of the function. */ | |
3033 | if (start_addr == 0) | |
3034 | return cache; | |
eec63939 | 3035 | |
4cc0665f | 3036 | micromips_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); |
29639122 | 3037 | } |
4cc0665f | 3038 | |
3e8c568d | 3039 | /* gdbarch_sp_regnum contains the value and not the address. */ |
72a155b4 | 3040 | trad_frame_set_value (cache->saved_regs, |
e17a4113 | 3041 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
72a155b4 | 3042 | cache->base); |
eec63939 | 3043 | |
29639122 | 3044 | return (*this_cache); |
eec63939 AC |
3045 | } |
3046 | ||
3047 | static void | |
4cc0665f MR |
3048 | mips_micro_frame_this_id (struct frame_info *this_frame, void **this_cache, |
3049 | struct frame_id *this_id) | |
eec63939 | 3050 | { |
4cc0665f MR |
3051 | struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
3052 | this_cache); | |
21327321 DJ |
3053 | /* This marks the outermost frame. */ |
3054 | if (info->base == 0) | |
3055 | return; | |
b8a22b94 | 3056 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
eec63939 AC |
3057 | } |
3058 | ||
b8a22b94 | 3059 | static struct value * |
4cc0665f MR |
3060 | mips_micro_frame_prev_register (struct frame_info *this_frame, |
3061 | void **this_cache, int regnum) | |
eec63939 | 3062 | { |
4cc0665f MR |
3063 | struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
3064 | this_cache); | |
b8a22b94 DJ |
3065 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
3066 | } | |
3067 | ||
3068 | static int | |
4cc0665f MR |
3069 | mips_micro_frame_sniffer (const struct frame_unwind *self, |
3070 | struct frame_info *this_frame, void **this_cache) | |
b8a22b94 | 3071 | { |
4cc0665f | 3072 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
b8a22b94 | 3073 | CORE_ADDR pc = get_frame_pc (this_frame); |
4cc0665f MR |
3074 | |
3075 | if (mips_pc_is_micromips (gdbarch, pc)) | |
b8a22b94 DJ |
3076 | return 1; |
3077 | return 0; | |
eec63939 AC |
3078 | } |
3079 | ||
4cc0665f | 3080 | static const struct frame_unwind mips_micro_frame_unwind = |
eec63939 AC |
3081 | { |
3082 | NORMAL_FRAME, | |
8fbca658 | 3083 | default_frame_unwind_stop_reason, |
4cc0665f MR |
3084 | mips_micro_frame_this_id, |
3085 | mips_micro_frame_prev_register, | |
b8a22b94 | 3086 | NULL, |
4cc0665f | 3087 | mips_micro_frame_sniffer |
eec63939 AC |
3088 | }; |
3089 | ||
eec63939 | 3090 | static CORE_ADDR |
4cc0665f MR |
3091 | mips_micro_frame_base_address (struct frame_info *this_frame, |
3092 | void **this_cache) | |
eec63939 | 3093 | { |
4cc0665f MR |
3094 | struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
3095 | this_cache); | |
29639122 | 3096 | return info->base; |
eec63939 AC |
3097 | } |
3098 | ||
4cc0665f | 3099 | static const struct frame_base mips_micro_frame_base = |
eec63939 | 3100 | { |
4cc0665f MR |
3101 | &mips_micro_frame_unwind, |
3102 | mips_micro_frame_base_address, | |
3103 | mips_micro_frame_base_address, | |
3104 | mips_micro_frame_base_address | |
eec63939 AC |
3105 | }; |
3106 | ||
3107 | static const struct frame_base * | |
4cc0665f | 3108 | mips_micro_frame_base_sniffer (struct frame_info *this_frame) |
eec63939 | 3109 | { |
4cc0665f | 3110 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
b8a22b94 | 3111 | CORE_ADDR pc = get_frame_pc (this_frame); |
4cc0665f MR |
3112 | |
3113 | if (mips_pc_is_micromips (gdbarch, pc)) | |
3114 | return &mips_micro_frame_base; | |
eec63939 AC |
3115 | else |
3116 | return NULL; | |
edfae063 AC |
3117 | } |
3118 | ||
29639122 JB |
3119 | /* Mark all the registers as unset in the saved_regs array |
3120 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
3121 | ||
74ed0bb4 MD |
3122 | static void |
3123 | reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache) | |
c906108c | 3124 | { |
29639122 JB |
3125 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
3126 | return; | |
3127 | ||
3128 | { | |
74ed0bb4 | 3129 | const int num_regs = gdbarch_num_regs (gdbarch); |
29639122 | 3130 | int i; |
64159455 | 3131 | |
29639122 JB |
3132 | for (i = 0; i < num_regs; i++) |
3133 | { | |
3134 | this_cache->saved_regs[i].addr = -1; | |
3135 | } | |
3136 | } | |
c906108c SS |
3137 | } |
3138 | ||
025bb325 | 3139 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
29639122 JB |
3140 | the associated FRAME_CACHE if not null. |
3141 | Return the address of the first instruction past the prologue. */ | |
c906108c | 3142 | |
875e1767 | 3143 | static CORE_ADDR |
e17a4113 UW |
3144 | mips32_scan_prologue (struct gdbarch *gdbarch, |
3145 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 3146 | struct frame_info *this_frame, |
29639122 | 3147 | struct mips_frame_cache *this_cache) |
c906108c | 3148 | { |
29639122 | 3149 | CORE_ADDR cur_pc; |
025bb325 MS |
3150 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for |
3151 | frame-pointer. */ | |
29639122 JB |
3152 | CORE_ADDR sp; |
3153 | long frame_offset; | |
3154 | int frame_reg = MIPS_SP_REGNUM; | |
8fa9cfa1 | 3155 | |
29639122 JB |
3156 | CORE_ADDR end_prologue_addr = 0; |
3157 | int seen_sp_adjust = 0; | |
3158 | int load_immediate_bytes = 0; | |
db5f024e | 3159 | int in_delay_slot = 0; |
7d1e6fb8 | 3160 | int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8); |
8fa9cfa1 | 3161 | |
29639122 | 3162 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
3163 | THIS_FRAME. */ |
3164 | if (this_frame != NULL) | |
3165 | sp = get_frame_register_signed (this_frame, | |
3166 | gdbarch_num_regs (gdbarch) | |
3167 | + MIPS_SP_REGNUM); | |
8fa9cfa1 | 3168 | else |
29639122 | 3169 | sp = 0; |
9022177c | 3170 | |
29639122 JB |
3171 | if (limit_pc > start_pc + 200) |
3172 | limit_pc = start_pc + 200; | |
9022177c | 3173 | |
29639122 | 3174 | restart: |
9022177c | 3175 | |
29639122 | 3176 | frame_offset = 0; |
95ac2dcf | 3177 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) |
9022177c | 3178 | { |
29639122 JB |
3179 | unsigned long inst, high_word, low_word; |
3180 | int reg; | |
9022177c | 3181 | |
025bb325 | 3182 | /* Fetch the instruction. */ |
4cc0665f MR |
3183 | inst = (unsigned long) mips_fetch_instruction (gdbarch, ISA_MIPS, |
3184 | cur_pc, NULL); | |
9022177c | 3185 | |
29639122 JB |
3186 | /* Save some code by pre-extracting some useful fields. */ |
3187 | high_word = (inst >> 16) & 0xffff; | |
3188 | low_word = inst & 0xffff; | |
3189 | reg = high_word & 0x1f; | |
fe29b929 | 3190 | |
025bb325 | 3191 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
29639122 JB |
3192 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
3193 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
3194 | { | |
025bb325 | 3195 | if (low_word & 0x8000) /* Negative stack adjustment? */ |
29639122 JB |
3196 | frame_offset += 0x10000 - low_word; |
3197 | else | |
3198 | /* Exit loop if a positive stack adjustment is found, which | |
3199 | usually means that the stack cleanup code in the function | |
3200 | epilogue is reached. */ | |
3201 | break; | |
3202 | seen_sp_adjust = 1; | |
3203 | } | |
7d1e6fb8 KB |
3204 | else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ |
3205 | && !regsize_is_64_bits) | |
29639122 | 3206 | { |
74ed0bb4 | 3207 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
29639122 | 3208 | } |
7d1e6fb8 KB |
3209 | else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ |
3210 | && regsize_is_64_bits) | |
29639122 JB |
3211 | { |
3212 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ | |
74ed0bb4 | 3213 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
29639122 JB |
3214 | } |
3215 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
3216 | { | |
3217 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
3218 | if ((long) low_word != frame_offset) | |
3219 | frame_addr = sp + low_word; | |
b8a22b94 | 3220 | else if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
3221 | { |
3222 | unsigned alloca_adjust; | |
a4b8ebc8 | 3223 | |
29639122 | 3224 | frame_reg = 30; |
b8a22b94 DJ |
3225 | frame_addr = get_frame_register_signed |
3226 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 3227 | |
29639122 JB |
3228 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
3229 | if (alloca_adjust > 0) | |
3230 | { | |
025bb325 | 3231 | /* FP > SP + frame_size. This may be because of |
29639122 JB |
3232 | an alloca or somethings similar. Fix sp to |
3233 | "pre-alloca" value, and try again. */ | |
3234 | sp += alloca_adjust; | |
3235 | /* Need to reset the status of all registers. Otherwise, | |
3236 | we will hit a guard that prevents the new address | |
3237 | for each register to be recomputed during the second | |
3238 | pass. */ | |
74ed0bb4 | 3239 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
3240 | goto restart; |
3241 | } | |
3242 | } | |
3243 | } | |
3244 | /* move $30,$sp. With different versions of gas this will be either | |
3245 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
3246 | Accept any one of these. */ | |
3247 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
3248 | { | |
3249 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
b8a22b94 | 3250 | if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
3251 | { |
3252 | unsigned alloca_adjust; | |
c906108c | 3253 | |
29639122 | 3254 | frame_reg = 30; |
b8a22b94 DJ |
3255 | frame_addr = get_frame_register_signed |
3256 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 3257 | |
29639122 JB |
3258 | alloca_adjust = (unsigned) (frame_addr - sp); |
3259 | if (alloca_adjust > 0) | |
3260 | { | |
025bb325 | 3261 | /* FP > SP + frame_size. This may be because of |
29639122 JB |
3262 | an alloca or somethings similar. Fix sp to |
3263 | "pre-alloca" value, and try again. */ | |
3264 | sp = frame_addr; | |
3265 | /* Need to reset the status of all registers. Otherwise, | |
3266 | we will hit a guard that prevents the new address | |
3267 | for each register to be recomputed during the second | |
3268 | pass. */ | |
74ed0bb4 | 3269 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
3270 | goto restart; |
3271 | } | |
3272 | } | |
3273 | } | |
7d1e6fb8 KB |
3274 | else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */ |
3275 | && !regsize_is_64_bits) | |
29639122 | 3276 | { |
74ed0bb4 | 3277 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + low_word); |
29639122 JB |
3278 | } |
3279 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | |
3280 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ | |
3281 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | |
3282 | || high_word == 0x3c1c /* lui $gp,n */ | |
3283 | || high_word == 0x279c /* addiu $gp,$gp,n */ | |
3284 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
3285 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | |
3286 | ) | |
19080931 MR |
3287 | { |
3288 | /* These instructions are part of the prologue, but we don't | |
3289 | need to do anything special to handle them. */ | |
3290 | } | |
29639122 JB |
3291 | /* The instructions below load $at or $t0 with an immediate |
3292 | value in preparation for a stack adjustment via | |
025bb325 | 3293 | subu $sp,$sp,[$at,$t0]. These instructions could also |
29639122 JB |
3294 | initialize a local variable, so we accept them only before |
3295 | a stack adjustment instruction was seen. */ | |
3296 | else if (!seen_sp_adjust | |
19080931 MR |
3297 | && (high_word == 0x3c01 /* lui $at,n */ |
3298 | || high_word == 0x3c08 /* lui $t0,n */ | |
3299 | || high_word == 0x3421 /* ori $at,$at,n */ | |
3300 | || high_word == 0x3508 /* ori $t0,$t0,n */ | |
3301 | || high_word == 0x3401 /* ori $at,$zero,n */ | |
3302 | || high_word == 0x3408 /* ori $t0,$zero,n */ | |
3303 | )) | |
3304 | { | |
3305 | if (end_prologue_addr == 0) | |
3306 | load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ | |
3307 | } | |
29639122 | 3308 | else |
19080931 MR |
3309 | { |
3310 | /* This instruction is not an instruction typically found | |
3311 | in a prologue, so we must have reached the end of the | |
3312 | prologue. */ | |
3313 | /* FIXME: brobecker/2004-10-10: Can't we just break out of this | |
3314 | loop now? Why would we need to continue scanning the function | |
3315 | instructions? */ | |
3316 | if (end_prologue_addr == 0) | |
3317 | end_prologue_addr = cur_pc; | |
3318 | ||
3319 | /* Check for branches and jumps. For now, only jump to | |
3320 | register are caught (i.e. returns). */ | |
3321 | if ((itype_op (inst) & 0x07) == 0 && rtype_funct (inst) == 8) | |
3322 | in_delay_slot = 1; | |
3323 | } | |
db5f024e DJ |
3324 | |
3325 | /* If the previous instruction was a jump, we must have reached | |
3326 | the end of the prologue by now. Stop scanning so that we do | |
3327 | not go past the function return. */ | |
3328 | if (in_delay_slot) | |
3329 | break; | |
a4b8ebc8 | 3330 | } |
c906108c | 3331 | |
29639122 JB |
3332 | if (this_cache != NULL) |
3333 | { | |
3334 | this_cache->base = | |
b8a22b94 DJ |
3335 | (get_frame_register_signed (this_frame, |
3336 | gdbarch_num_regs (gdbarch) + frame_reg) | |
29639122 JB |
3337 | + frame_offset); |
3338 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of | |
3339 | this assignment below, eventually. But it's still needed | |
3340 | for now. */ | |
72a155b4 UW |
3341 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
3342 | + mips_regnum (gdbarch)->pc] | |
3343 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) | |
f57d151a | 3344 | + MIPS_RA_REGNUM]; |
29639122 | 3345 | } |
c906108c | 3346 | |
29639122 JB |
3347 | /* If we didn't reach the end of the prologue when scanning the function |
3348 | instructions, then set end_prologue_addr to the address of the | |
3349 | instruction immediately after the last one we scanned. */ | |
3350 | /* brobecker/2004-10-10: I don't think this would ever happen, but | |
3351 | we may as well be careful and do our best if we have a null | |
3352 | end_prologue_addr. */ | |
3353 | if (end_prologue_addr == 0) | |
3354 | end_prologue_addr = cur_pc; | |
3355 | ||
3356 | /* In a frameless function, we might have incorrectly | |
025bb325 | 3357 | skipped some load immediate instructions. Undo the skipping |
29639122 JB |
3358 | if the load immediate was not followed by a stack adjustment. */ |
3359 | if (load_immediate_bytes && !seen_sp_adjust) | |
3360 | end_prologue_addr -= load_immediate_bytes; | |
c906108c | 3361 | |
29639122 | 3362 | return end_prologue_addr; |
c906108c SS |
3363 | } |
3364 | ||
29639122 JB |
3365 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
3366 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
3367 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
4cc0665f | 3368 | unwinder. Likewise microMIPS and the mips_micro unwinder. */ |
c906108c | 3369 | |
29639122 | 3370 | static struct mips_frame_cache * |
b8a22b94 | 3371 | mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache) |
c906108c | 3372 | { |
e17a4113 | 3373 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 3374 | struct mips_frame_cache *cache; |
c906108c | 3375 | |
29639122 JB |
3376 | if ((*this_cache) != NULL) |
3377 | return (*this_cache); | |
c5aa993b | 3378 | |
29639122 JB |
3379 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
3380 | (*this_cache) = cache; | |
b8a22b94 | 3381 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
c5aa993b | 3382 | |
29639122 JB |
3383 | /* Analyze the function prologue. */ |
3384 | { | |
b8a22b94 | 3385 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 3386 | CORE_ADDR start_addr; |
c906108c | 3387 | |
29639122 JB |
3388 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
3389 | if (start_addr == 0) | |
e17a4113 | 3390 | start_addr = heuristic_proc_start (gdbarch, pc); |
29639122 JB |
3391 | /* We can't analyze the prologue if we couldn't find the begining |
3392 | of the function. */ | |
3393 | if (start_addr == 0) | |
3394 | return cache; | |
c5aa993b | 3395 | |
e17a4113 | 3396 | mips32_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); |
29639122 JB |
3397 | } |
3398 | ||
3e8c568d | 3399 | /* gdbarch_sp_regnum contains the value and not the address. */ |
f57d151a | 3400 | trad_frame_set_value (cache->saved_regs, |
e17a4113 | 3401 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
f57d151a | 3402 | cache->base); |
c5aa993b | 3403 | |
29639122 | 3404 | return (*this_cache); |
c906108c SS |
3405 | } |
3406 | ||
29639122 | 3407 | static void |
b8a22b94 | 3408 | mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 | 3409 | struct frame_id *this_id) |
c906108c | 3410 | { |
b8a22b94 | 3411 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 3412 | this_cache); |
21327321 DJ |
3413 | /* This marks the outermost frame. */ |
3414 | if (info->base == 0) | |
3415 | return; | |
b8a22b94 | 3416 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
29639122 | 3417 | } |
c906108c | 3418 | |
b8a22b94 DJ |
3419 | static struct value * |
3420 | mips_insn32_frame_prev_register (struct frame_info *this_frame, | |
3421 | void **this_cache, int regnum) | |
29639122 | 3422 | { |
b8a22b94 | 3423 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 3424 | this_cache); |
b8a22b94 DJ |
3425 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
3426 | } | |
3427 | ||
3428 | static int | |
3429 | mips_insn32_frame_sniffer (const struct frame_unwind *self, | |
3430 | struct frame_info *this_frame, void **this_cache) | |
3431 | { | |
3432 | CORE_ADDR pc = get_frame_pc (this_frame); | |
4cc0665f | 3433 | if (mips_pc_is_mips (pc)) |
b8a22b94 DJ |
3434 | return 1; |
3435 | return 0; | |
c906108c SS |
3436 | } |
3437 | ||
29639122 JB |
3438 | static const struct frame_unwind mips_insn32_frame_unwind = |
3439 | { | |
3440 | NORMAL_FRAME, | |
8fbca658 | 3441 | default_frame_unwind_stop_reason, |
29639122 | 3442 | mips_insn32_frame_this_id, |
b8a22b94 DJ |
3443 | mips_insn32_frame_prev_register, |
3444 | NULL, | |
3445 | mips_insn32_frame_sniffer | |
29639122 | 3446 | }; |
c906108c | 3447 | |
1c645fec | 3448 | static CORE_ADDR |
b8a22b94 | 3449 | mips_insn32_frame_base_address (struct frame_info *this_frame, |
29639122 | 3450 | void **this_cache) |
c906108c | 3451 | { |
b8a22b94 | 3452 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 JB |
3453 | this_cache); |
3454 | return info->base; | |
3455 | } | |
c906108c | 3456 | |
29639122 JB |
3457 | static const struct frame_base mips_insn32_frame_base = |
3458 | { | |
3459 | &mips_insn32_frame_unwind, | |
3460 | mips_insn32_frame_base_address, | |
3461 | mips_insn32_frame_base_address, | |
3462 | mips_insn32_frame_base_address | |
3463 | }; | |
1c645fec | 3464 | |
29639122 | 3465 | static const struct frame_base * |
b8a22b94 | 3466 | mips_insn32_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 3467 | { |
b8a22b94 | 3468 | CORE_ADDR pc = get_frame_pc (this_frame); |
4cc0665f | 3469 | if (mips_pc_is_mips (pc)) |
29639122 | 3470 | return &mips_insn32_frame_base; |
a65bbe44 | 3471 | else |
29639122 JB |
3472 | return NULL; |
3473 | } | |
a65bbe44 | 3474 | |
29639122 | 3475 | static struct trad_frame_cache * |
b8a22b94 | 3476 | mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache) |
29639122 JB |
3477 | { |
3478 | CORE_ADDR pc; | |
3479 | CORE_ADDR start_addr; | |
3480 | CORE_ADDR stack_addr; | |
3481 | struct trad_frame_cache *this_trad_cache; | |
b8a22b94 DJ |
3482 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
3483 | int num_regs = gdbarch_num_regs (gdbarch); | |
c906108c | 3484 | |
29639122 JB |
3485 | if ((*this_cache) != NULL) |
3486 | return (*this_cache); | |
b8a22b94 | 3487 | this_trad_cache = trad_frame_cache_zalloc (this_frame); |
29639122 | 3488 | (*this_cache) = this_trad_cache; |
1c645fec | 3489 | |
29639122 | 3490 | /* The return address is in the link register. */ |
3e8c568d | 3491 | trad_frame_set_reg_realreg (this_trad_cache, |
72a155b4 | 3492 | gdbarch_pc_regnum (gdbarch), |
b8a22b94 | 3493 | num_regs + MIPS_RA_REGNUM); |
1c645fec | 3494 | |
29639122 JB |
3495 | /* Frame ID, since it's a frameless / stackless function, no stack |
3496 | space is allocated and SP on entry is the current SP. */ | |
b8a22b94 | 3497 | pc = get_frame_pc (this_frame); |
29639122 | 3498 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
b8a22b94 DJ |
3499 | stack_addr = get_frame_register_signed (this_frame, |
3500 | num_regs + MIPS_SP_REGNUM); | |
aa6c981f | 3501 | trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr)); |
1c645fec | 3502 | |
29639122 JB |
3503 | /* Assume that the frame's base is the same as the |
3504 | stack-pointer. */ | |
3505 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
c906108c | 3506 | |
29639122 JB |
3507 | return this_trad_cache; |
3508 | } | |
c906108c | 3509 | |
29639122 | 3510 | static void |
b8a22b94 | 3511 | mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 JB |
3512 | struct frame_id *this_id) |
3513 | { | |
3514 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 3515 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
3516 | trad_frame_get_id (this_trad_cache, this_id); |
3517 | } | |
c906108c | 3518 | |
b8a22b94 DJ |
3519 | static struct value * |
3520 | mips_stub_frame_prev_register (struct frame_info *this_frame, | |
3521 | void **this_cache, int regnum) | |
29639122 JB |
3522 | { |
3523 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 DJ |
3524 | = mips_stub_frame_cache (this_frame, this_cache); |
3525 | return trad_frame_get_register (this_trad_cache, this_frame, regnum); | |
29639122 | 3526 | } |
c906108c | 3527 | |
b8a22b94 DJ |
3528 | static int |
3529 | mips_stub_frame_sniffer (const struct frame_unwind *self, | |
3530 | struct frame_info *this_frame, void **this_cache) | |
29639122 | 3531 | { |
aa6c981f | 3532 | gdb_byte dummy[4]; |
979b38e0 | 3533 | struct obj_section *s; |
b8a22b94 | 3534 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
db5f024e | 3535 | struct minimal_symbol *msym; |
979b38e0 | 3536 | |
aa6c981f | 3537 | /* Use the stub unwinder for unreadable code. */ |
b8a22b94 DJ |
3538 | if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) |
3539 | return 1; | |
aa6c981f | 3540 | |
29639122 | 3541 | if (in_plt_section (pc, NULL)) |
b8a22b94 | 3542 | return 1; |
979b38e0 DJ |
3543 | |
3544 | /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */ | |
3545 | s = find_pc_section (pc); | |
3546 | ||
3547 | if (s != NULL | |
3548 | && strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section), | |
3549 | ".MIPS.stubs") == 0) | |
b8a22b94 | 3550 | return 1; |
979b38e0 | 3551 | |
db5f024e DJ |
3552 | /* Calling a PIC function from a non-PIC function passes through a |
3553 | stub. The stub for foo is named ".pic.foo". */ | |
3554 | msym = lookup_minimal_symbol_by_pc (pc); | |
3555 | if (msym != NULL | |
3556 | && SYMBOL_LINKAGE_NAME (msym) != NULL | |
3557 | && strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) == 0) | |
3558 | return 1; | |
3559 | ||
b8a22b94 | 3560 | return 0; |
29639122 | 3561 | } |
c906108c | 3562 | |
b8a22b94 DJ |
3563 | static const struct frame_unwind mips_stub_frame_unwind = |
3564 | { | |
3565 | NORMAL_FRAME, | |
8fbca658 | 3566 | default_frame_unwind_stop_reason, |
b8a22b94 DJ |
3567 | mips_stub_frame_this_id, |
3568 | mips_stub_frame_prev_register, | |
3569 | NULL, | |
3570 | mips_stub_frame_sniffer | |
3571 | }; | |
3572 | ||
29639122 | 3573 | static CORE_ADDR |
b8a22b94 | 3574 | mips_stub_frame_base_address (struct frame_info *this_frame, |
29639122 JB |
3575 | void **this_cache) |
3576 | { | |
3577 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 3578 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
3579 | return trad_frame_get_this_base (this_trad_cache); |
3580 | } | |
0fce0821 | 3581 | |
29639122 JB |
3582 | static const struct frame_base mips_stub_frame_base = |
3583 | { | |
3584 | &mips_stub_frame_unwind, | |
3585 | mips_stub_frame_base_address, | |
3586 | mips_stub_frame_base_address, | |
3587 | mips_stub_frame_base_address | |
3588 | }; | |
3589 | ||
3590 | static const struct frame_base * | |
b8a22b94 | 3591 | mips_stub_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 3592 | { |
b8a22b94 | 3593 | if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL)) |
29639122 JB |
3594 | return &mips_stub_frame_base; |
3595 | else | |
3596 | return NULL; | |
3597 | } | |
3598 | ||
29639122 | 3599 | /* mips_addr_bits_remove - remove useless address bits */ |
65596487 | 3600 | |
29639122 | 3601 | static CORE_ADDR |
24568a2c | 3602 | mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) |
65596487 | 3603 | { |
24568a2c | 3604 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
930bd0e0 | 3605 | |
4cc0665f MR |
3606 | if (is_compact_addr (addr)) |
3607 | addr = unmake_compact_addr (addr); | |
930bd0e0 | 3608 | |
29639122 JB |
3609 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) |
3610 | /* This hack is a work-around for existing boards using PMON, the | |
3611 | simulator, and any other 64-bit targets that doesn't have true | |
3612 | 64-bit addressing. On these targets, the upper 32 bits of | |
3613 | addresses are ignored by the hardware. Thus, the PC or SP are | |
3614 | likely to have been sign extended to all 1s by instruction | |
3615 | sequences that load 32-bit addresses. For example, a typical | |
3616 | piece of code that loads an address is this: | |
65596487 | 3617 | |
29639122 JB |
3618 | lui $r2, <upper 16 bits> |
3619 | ori $r2, <lower 16 bits> | |
65596487 | 3620 | |
29639122 JB |
3621 | But the lui sign-extends the value such that the upper 32 bits |
3622 | may be all 1s. The workaround is simply to mask off these | |
3623 | bits. In the future, gcc may be changed to support true 64-bit | |
3624 | addressing, and this masking will have to be disabled. */ | |
3625 | return addr &= 0xffffffffUL; | |
3626 | else | |
3627 | return addr; | |
65596487 JB |
3628 | } |
3629 | ||
3d5f6d12 DJ |
3630 | |
3631 | /* Checks for an atomic sequence of instructions beginning with a LL/LLD | |
3632 | instruction and ending with a SC/SCD instruction. If such a sequence | |
3633 | is found, attempt to step through it. A breakpoint is placed at the end of | |
3634 | the sequence. */ | |
3635 | ||
4cc0665f MR |
3636 | /* Instructions used during single-stepping of atomic sequences, standard |
3637 | ISA version. */ | |
3638 | #define LL_OPCODE 0x30 | |
3639 | #define LLD_OPCODE 0x34 | |
3640 | #define SC_OPCODE 0x38 | |
3641 | #define SCD_OPCODE 0x3c | |
3642 | ||
3d5f6d12 | 3643 | static int |
4cc0665f MR |
3644 | mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, |
3645 | struct address_space *aspace, CORE_ADDR pc) | |
3d5f6d12 DJ |
3646 | { |
3647 | CORE_ADDR breaks[2] = {-1, -1}; | |
3648 | CORE_ADDR loc = pc; | |
3649 | CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ | |
4cc0665f | 3650 | ULONGEST insn; |
3d5f6d12 DJ |
3651 | int insn_count; |
3652 | int index; | |
3653 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
3654 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
3655 | ||
4cc0665f | 3656 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); |
3d5f6d12 DJ |
3657 | /* Assume all atomic sequences start with a ll/lld instruction. */ |
3658 | if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE) | |
3659 | return 0; | |
3660 | ||
3661 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" | |
3662 | instructions. */ | |
3663 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
3664 | { | |
3665 | int is_branch = 0; | |
3666 | loc += MIPS_INSN32_SIZE; | |
4cc0665f | 3667 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); |
3d5f6d12 DJ |
3668 | |
3669 | /* Assume that there is at most one branch in the atomic | |
3670 | sequence. If a branch is found, put a breakpoint in its | |
3671 | destination address. */ | |
3672 | switch (itype_op (insn)) | |
3673 | { | |
3674 | case 0: /* SPECIAL */ | |
3675 | if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */ | |
025bb325 | 3676 | return 0; /* fallback to the standard single-step code. */ |
3d5f6d12 DJ |
3677 | break; |
3678 | case 1: /* REGIMM */ | |
a385295e MR |
3679 | is_branch = ((itype_rt (insn) & 0xc) == 0 /* B{LT,GE}Z* */ |
3680 | || ((itype_rt (insn) & 0x1e) == 0 | |
3681 | && itype_rs (insn) == 0)); /* BPOSGE* */ | |
3d5f6d12 DJ |
3682 | break; |
3683 | case 2: /* J */ | |
3684 | case 3: /* JAL */ | |
025bb325 | 3685 | return 0; /* fallback to the standard single-step code. */ |
3d5f6d12 DJ |
3686 | case 4: /* BEQ */ |
3687 | case 5: /* BNE */ | |
3688 | case 6: /* BLEZ */ | |
3689 | case 7: /* BGTZ */ | |
3690 | case 20: /* BEQL */ | |
3691 | case 21: /* BNEL */ | |
3692 | case 22: /* BLEZL */ | |
3693 | case 23: /* BGTTL */ | |
3694 | is_branch = 1; | |
3695 | break; | |
3696 | case 17: /* COP1 */ | |
a385295e MR |
3697 | is_branch = ((itype_rs (insn) == 9 || itype_rs (insn) == 10) |
3698 | && (itype_rt (insn) & 0x2) == 0); | |
3699 | if (is_branch) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */ | |
3700 | break; | |
3701 | /* Fall through. */ | |
3d5f6d12 DJ |
3702 | case 18: /* COP2 */ |
3703 | case 19: /* COP3 */ | |
3704 | is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */ | |
3705 | break; | |
3706 | } | |
3707 | if (is_branch) | |
3708 | { | |
3709 | branch_bp = loc + mips32_relative_offset (insn) + 4; | |
3710 | if (last_breakpoint >= 1) | |
3711 | return 0; /* More than one branch found, fallback to the | |
3712 | standard single-step code. */ | |
3713 | breaks[1] = branch_bp; | |
3714 | last_breakpoint++; | |
3715 | } | |
3716 | ||
3717 | if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE) | |
3718 | break; | |
3719 | } | |
3720 | ||
3721 | /* Assume that the atomic sequence ends with a sc/scd instruction. */ | |
3722 | if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE) | |
3723 | return 0; | |
3724 | ||
3725 | loc += MIPS_INSN32_SIZE; | |
3726 | ||
3727 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
3728 | breaks[0] = loc; | |
3729 | ||
3730 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
025bb325 | 3731 | placed (branch instruction's destination) in the atomic sequence. */ |
3d5f6d12 DJ |
3732 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) |
3733 | last_breakpoint = 0; | |
3734 | ||
3735 | /* Effectively inserts the breakpoints. */ | |
3736 | for (index = 0; index <= last_breakpoint; index++) | |
6c95b8df | 3737 | insert_single_step_breakpoint (gdbarch, aspace, breaks[index]); |
3d5f6d12 DJ |
3738 | |
3739 | return 1; | |
3740 | } | |
3741 | ||
4cc0665f MR |
3742 | static int |
3743 | micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch, | |
3744 | struct address_space *aspace, | |
3745 | CORE_ADDR pc) | |
3746 | { | |
3747 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
3748 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
3749 | CORE_ADDR breaks[2] = {-1, -1}; | |
3750 | CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ | |
3751 | CORE_ADDR loc = pc; | |
3752 | int sc_found = 0; | |
3753 | ULONGEST insn; | |
3754 | int insn_count; | |
3755 | int index; | |
3756 | ||
3757 | /* Assume all atomic sequences start with a ll/lld instruction. */ | |
3758 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); | |
3759 | if (micromips_op (insn) != 0x18) /* POOL32C: bits 011000 */ | |
3760 | return 0; | |
3761 | loc += MIPS_INSN16_SIZE; | |
3762 | insn <<= 16; | |
3763 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); | |
3764 | if ((b12s4_op (insn) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */ | |
3765 | return 0; | |
3766 | loc += MIPS_INSN16_SIZE; | |
3767 | ||
3768 | /* Assume all atomic sequences end with an sc/scd instruction. Assume | |
3769 | that no atomic sequence is longer than "atomic_sequence_length" | |
3770 | instructions. */ | |
3771 | for (insn_count = 0; | |
3772 | !sc_found && insn_count < atomic_sequence_length; | |
3773 | ++insn_count) | |
3774 | { | |
3775 | int is_branch = 0; | |
3776 | ||
3777 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); | |
3778 | loc += MIPS_INSN16_SIZE; | |
3779 | ||
3780 | /* Assume that there is at most one conditional branch in the | |
3781 | atomic sequence. If a branch is found, put a breakpoint in | |
3782 | its destination address. */ | |
3783 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
3784 | { | |
3785 | /* 48-bit instructions. */ | |
3786 | case 3 * MIPS_INSN16_SIZE: /* POOL48A: bits 011111 */ | |
3787 | loc += 2 * MIPS_INSN16_SIZE; | |
3788 | break; | |
3789 | ||
3790 | /* 32-bit instructions. */ | |
3791 | case 2 * MIPS_INSN16_SIZE: | |
3792 | switch (micromips_op (insn)) | |
3793 | { | |
3794 | case 0x10: /* POOL32I: bits 010000 */ | |
3795 | if ((b5s5_op (insn) & 0x18) != 0x0 | |
3796 | /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */ | |
3797 | /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */ | |
3798 | && (b5s5_op (insn) & 0x1d) != 0x11 | |
3799 | /* BLTZALS, BGEZALS: bits 010000 100x1 */ | |
3800 | && ((b5s5_op (insn) & 0x1e) != 0x14 | |
3801 | || (insn & 0x3) != 0x0) | |
3802 | /* BC2F, BC2T: bits 010000 1010x xxx00 */ | |
3803 | && (b5s5_op (insn) & 0x1e) != 0x1a | |
3804 | /* BPOSGE64, BPOSGE32: bits 010000 1101x */ | |
3805 | && ((b5s5_op (insn) & 0x1e) != 0x1c | |
3806 | || (insn & 0x3) != 0x0) | |
3807 | /* BC1F, BC1T: bits 010000 1110x xxx00 */ | |
3808 | && ((b5s5_op (insn) & 0x1c) != 0x1c | |
3809 | || (insn & 0x3) != 0x1)) | |
3810 | /* BC1ANY*: bits 010000 111xx xxx01 */ | |
3811 | break; | |
3812 | /* Fall through. */ | |
3813 | ||
3814 | case 0x25: /* BEQ: bits 100101 */ | |
3815 | case 0x2d: /* BNE: bits 101101 */ | |
3816 | insn <<= 16; | |
3817 | insn |= mips_fetch_instruction (gdbarch, | |
3818 | ISA_MICROMIPS, loc, NULL); | |
3819 | branch_bp = (loc + MIPS_INSN16_SIZE | |
3820 | + micromips_relative_offset16 (insn)); | |
3821 | is_branch = 1; | |
3822 | break; | |
3823 | ||
3824 | case 0x00: /* POOL32A: bits 000000 */ | |
3825 | insn <<= 16; | |
3826 | insn |= mips_fetch_instruction (gdbarch, | |
3827 | ISA_MICROMIPS, loc, NULL); | |
3828 | if (b0s6_op (insn) != 0x3c | |
3829 | /* POOL32Axf: bits 000000 ... 111100 */ | |
3830 | || (b6s10_ext (insn) & 0x2bf) != 0x3c) | |
3831 | /* JALR, JALR.HB: 000000 000x111100 111100 */ | |
3832 | /* JALRS, JALRS.HB: 000000 010x111100 111100 */ | |
3833 | break; | |
3834 | /* Fall through. */ | |
3835 | ||
3836 | case 0x1d: /* JALS: bits 011101 */ | |
3837 | case 0x35: /* J: bits 110101 */ | |
3838 | case 0x3d: /* JAL: bits 111101 */ | |
3839 | case 0x3c: /* JALX: bits 111100 */ | |
3840 | return 0; /* Fall back to the standard single-step code. */ | |
3841 | ||
3842 | case 0x18: /* POOL32C: bits 011000 */ | |
3843 | if ((b12s4_op (insn) & 0xb) == 0xb) | |
3844 | /* SC, SCD: bits 011000 1x11 */ | |
3845 | sc_found = 1; | |
3846 | break; | |
3847 | } | |
3848 | loc += MIPS_INSN16_SIZE; | |
3849 | break; | |
3850 | ||
3851 | /* 16-bit instructions. */ | |
3852 | case MIPS_INSN16_SIZE: | |
3853 | switch (micromips_op (insn)) | |
3854 | { | |
3855 | case 0x23: /* BEQZ16: bits 100011 */ | |
3856 | case 0x2b: /* BNEZ16: bits 101011 */ | |
3857 | branch_bp = loc + micromips_relative_offset7 (insn); | |
3858 | is_branch = 1; | |
3859 | break; | |
3860 | ||
3861 | case 0x11: /* POOL16C: bits 010001 */ | |
3862 | if ((b5s5_op (insn) & 0x1c) != 0xc | |
3863 | /* JR16, JRC, JALR16, JALRS16: 010001 011xx */ | |
3864 | && b5s5_op (insn) != 0x18) | |
3865 | /* JRADDIUSP: bits 010001 11000 */ | |
3866 | break; | |
3867 | return 0; /* Fall back to the standard single-step code. */ | |
3868 | ||
3869 | case 0x33: /* B16: bits 110011 */ | |
3870 | return 0; /* Fall back to the standard single-step code. */ | |
3871 | } | |
3872 | break; | |
3873 | } | |
3874 | if (is_branch) | |
3875 | { | |
3876 | if (last_breakpoint >= 1) | |
3877 | return 0; /* More than one branch found, fallback to the | |
3878 | standard single-step code. */ | |
3879 | breaks[1] = branch_bp; | |
3880 | last_breakpoint++; | |
3881 | } | |
3882 | } | |
3883 | if (!sc_found) | |
3884 | return 0; | |
3885 | ||
3886 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
3887 | breaks[0] = loc; | |
3888 | ||
3889 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
3890 | placed (branch instruction's destination) in the atomic sequence */ | |
3891 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) | |
3892 | last_breakpoint = 0; | |
3893 | ||
3894 | /* Effectively inserts the breakpoints. */ | |
3895 | for (index = 0; index <= last_breakpoint; index++) | |
3896 | insert_single_step_breakpoint (gdbarch, aspace, breaks[index]); | |
3897 | ||
3898 | return 1; | |
3899 | } | |
3900 | ||
3901 | static int | |
3902 | deal_with_atomic_sequence (struct gdbarch *gdbarch, | |
3903 | struct address_space *aspace, CORE_ADDR pc) | |
3904 | { | |
3905 | if (mips_pc_is_mips (pc)) | |
3906 | return mips_deal_with_atomic_sequence (gdbarch, aspace, pc); | |
3907 | else if (mips_pc_is_micromips (gdbarch, pc)) | |
3908 | return micromips_deal_with_atomic_sequence (gdbarch, aspace, pc); | |
3909 | else | |
3910 | return 0; | |
3911 | } | |
3912 | ||
29639122 JB |
3913 | /* mips_software_single_step() is called just before we want to resume |
3914 | the inferior, if we want to single-step it but there is no hardware | |
3915 | or kernel single-step support (MIPS on GNU/Linux for example). We find | |
e0cd558a | 3916 | the target of the coming instruction and breakpoint it. */ |
29639122 | 3917 | |
e6590a1b | 3918 | int |
0b1b3e42 | 3919 | mips_software_single_step (struct frame_info *frame) |
c906108c | 3920 | { |
a6d9a66e | 3921 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6c95b8df | 3922 | struct address_space *aspace = get_frame_address_space (frame); |
8181d85f | 3923 | CORE_ADDR pc, next_pc; |
65596487 | 3924 | |
0b1b3e42 | 3925 | pc = get_frame_pc (frame); |
6c95b8df | 3926 | if (deal_with_atomic_sequence (gdbarch, aspace, pc)) |
3d5f6d12 DJ |
3927 | return 1; |
3928 | ||
0b1b3e42 | 3929 | next_pc = mips_next_pc (frame, pc); |
e6590a1b | 3930 | |
6c95b8df | 3931 | insert_single_step_breakpoint (gdbarch, aspace, next_pc); |
e6590a1b | 3932 | return 1; |
29639122 | 3933 | } |
a65bbe44 | 3934 | |
29639122 | 3935 | /* Test whether the PC points to the return instruction at the |
025bb325 | 3936 | end of a function. */ |
65596487 | 3937 | |
29639122 | 3938 | static int |
e17a4113 | 3939 | mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 | 3940 | { |
6321c22a MR |
3941 | ULONGEST insn; |
3942 | ULONGEST hint; | |
3943 | ||
3944 | /* This used to check for MIPS16, but this piece of code is never | |
4cc0665f MR |
3945 | called for MIPS16 functions. And likewise microMIPS ones. */ |
3946 | gdb_assert (mips_pc_is_mips (pc)); | |
6321c22a | 3947 | |
4cc0665f | 3948 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
6321c22a MR |
3949 | hint = 0x7c0; |
3950 | return (insn & ~hint) == 0x3e00008; /* jr(.hb) $ra */ | |
29639122 | 3951 | } |
c906108c | 3952 | |
c906108c | 3953 | |
29639122 JB |
3954 | /* This fencepost looks highly suspicious to me. Removing it also |
3955 | seems suspicious as it could affect remote debugging across serial | |
3956 | lines. */ | |
c906108c | 3957 | |
29639122 | 3958 | static CORE_ADDR |
74ed0bb4 | 3959 | heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 JB |
3960 | { |
3961 | CORE_ADDR start_pc; | |
3962 | CORE_ADDR fence; | |
3963 | int instlen; | |
3964 | int seen_adjsp = 0; | |
d6b48e9c | 3965 | struct inferior *inf; |
65596487 | 3966 | |
74ed0bb4 | 3967 | pc = gdbarch_addr_bits_remove (gdbarch, pc); |
29639122 JB |
3968 | start_pc = pc; |
3969 | fence = start_pc - heuristic_fence_post; | |
3970 | if (start_pc == 0) | |
3971 | return 0; | |
65596487 | 3972 | |
29639122 JB |
3973 | if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
3974 | fence = VM_MIN_ADDRESS; | |
65596487 | 3975 | |
4cc0665f | 3976 | instlen = mips_pc_is_mips (pc) ? MIPS_INSN32_SIZE : MIPS_INSN16_SIZE; |
98b4dd94 | 3977 | |
d6b48e9c PA |
3978 | inf = current_inferior (); |
3979 | ||
025bb325 | 3980 | /* Search back for previous return. */ |
29639122 JB |
3981 | for (start_pc -= instlen;; start_pc -= instlen) |
3982 | if (start_pc < fence) | |
3983 | { | |
3984 | /* It's not clear to me why we reach this point when | |
3985 | stop_soon, but with this test, at least we | |
3986 | don't print out warnings for every child forked (eg, on | |
3987 | decstation). 22apr93 rich@cygnus.com. */ | |
16c381f0 | 3988 | if (inf->control.stop_soon == NO_STOP_QUIETLY) |
29639122 JB |
3989 | { |
3990 | static int blurb_printed = 0; | |
98b4dd94 | 3991 | |
5af949e3 UW |
3992 | warning (_("GDB can't find the start of the function at %s."), |
3993 | paddress (gdbarch, pc)); | |
29639122 JB |
3994 | |
3995 | if (!blurb_printed) | |
3996 | { | |
3997 | /* This actually happens frequently in embedded | |
3998 | development, when you first connect to a board | |
3999 | and your stack pointer and pc are nowhere in | |
4000 | particular. This message needs to give people | |
4001 | in that situation enough information to | |
4002 | determine that it's no big deal. */ | |
4003 | printf_filtered ("\n\ | |
5af949e3 | 4004 | GDB is unable to find the start of the function at %s\n\ |
29639122 JB |
4005 | and thus can't determine the size of that function's stack frame.\n\ |
4006 | This means that GDB may be unable to access that stack frame, or\n\ | |
4007 | the frames below it.\n\ | |
4008 | This problem is most likely caused by an invalid program counter or\n\ | |
4009 | stack pointer.\n\ | |
4010 | However, if you think GDB should simply search farther back\n\ | |
5af949e3 | 4011 | from %s for code which looks like the beginning of a\n\ |
29639122 | 4012 | function, you can increase the range of the search using the `set\n\ |
5af949e3 UW |
4013 | heuristic-fence-post' command.\n", |
4014 | paddress (gdbarch, pc), paddress (gdbarch, pc)); | |
29639122 JB |
4015 | blurb_printed = 1; |
4016 | } | |
4017 | } | |
4018 | ||
4019 | return 0; | |
4020 | } | |
4cc0665f | 4021 | else if (mips_pc_is_mips16 (gdbarch, start_pc)) |
29639122 JB |
4022 | { |
4023 | unsigned short inst; | |
4024 | ||
4025 | /* On MIPS16, any one of the following is likely to be the | |
4026 | start of a function: | |
193774b3 MR |
4027 | extend save |
4028 | save | |
29639122 JB |
4029 | entry |
4030 | addiu sp,-n | |
4031 | daddiu sp,-n | |
025bb325 | 4032 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */ |
4cc0665f | 4033 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, start_pc, NULL); |
193774b3 MR |
4034 | if ((inst & 0xff80) == 0x6480) /* save */ |
4035 | { | |
4036 | if (start_pc - instlen >= fence) | |
4037 | { | |
4cc0665f MR |
4038 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, |
4039 | start_pc - instlen, NULL); | |
193774b3 MR |
4040 | if ((inst & 0xf800) == 0xf000) /* extend */ |
4041 | start_pc -= instlen; | |
4042 | } | |
4043 | break; | |
4044 | } | |
4045 | else if (((inst & 0xf81f) == 0xe809 | |
4046 | && (inst & 0x700) != 0x700) /* entry */ | |
4047 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
4048 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
4049 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
29639122 JB |
4050 | break; |
4051 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
4052 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
4053 | seen_adjsp = 1; | |
4054 | else | |
4055 | seen_adjsp = 0; | |
4056 | } | |
4cc0665f MR |
4057 | else if (mips_pc_is_micromips (gdbarch, start_pc)) |
4058 | { | |
4059 | ULONGEST insn; | |
4060 | int stop = 0; | |
4061 | long offset; | |
4062 | int dreg; | |
4063 | int sreg; | |
4064 | ||
4065 | /* On microMIPS, any one of the following is likely to be the | |
4066 | start of a function: | |
4067 | ADDIUSP -imm | |
4068 | (D)ADDIU $sp, -imm | |
4069 | LUI $gp, imm */ | |
4070 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
4071 | switch (micromips_op (insn)) | |
4072 | { | |
4073 | case 0xc: /* ADDIU: bits 001100 */ | |
4074 | case 0x17: /* DADDIU: bits 010111 */ | |
4075 | sreg = b0s5_reg (insn); | |
4076 | dreg = b5s5_reg (insn); | |
4077 | insn <<= 16; | |
4078 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, | |
4079 | pc + MIPS_INSN16_SIZE, NULL); | |
4080 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
4081 | if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM | |
4082 | /* (D)ADDIU $sp, imm */ | |
4083 | && offset < 0) | |
4084 | stop = 1; | |
4085 | break; | |
4086 | ||
4087 | case 0x10: /* POOL32I: bits 010000 */ | |
4088 | if (b5s5_op (insn) == 0xd | |
4089 | /* LUI: bits 010000 001101 */ | |
4090 | && b0s5_reg (insn >> 16) == 28) | |
4091 | /* LUI $gp, imm */ | |
4092 | stop = 1; | |
4093 | break; | |
4094 | ||
4095 | case 0x13: /* POOL16D: bits 010011 */ | |
4096 | if ((insn & 0x1) == 0x1) | |
4097 | /* ADDIUSP: bits 010011 1 */ | |
4098 | { | |
4099 | offset = micromips_decode_imm9 (b1s9_imm (insn)); | |
4100 | if (offset < 0) | |
4101 | /* ADDIUSP -imm */ | |
4102 | stop = 1; | |
4103 | } | |
4104 | else | |
4105 | /* ADDIUS5: bits 010011 0 */ | |
4106 | { | |
4107 | dreg = b5s5_reg (insn); | |
4108 | offset = (b1s4_imm (insn) ^ 8) - 8; | |
4109 | if (dreg == MIPS_SP_REGNUM && offset < 0) | |
4110 | /* ADDIUS5 $sp, -imm */ | |
4111 | stop = 1; | |
4112 | } | |
4113 | break; | |
4114 | } | |
4115 | if (stop) | |
4116 | break; | |
4117 | } | |
e17a4113 | 4118 | else if (mips_about_to_return (gdbarch, start_pc)) |
29639122 | 4119 | { |
4c7d22cb | 4120 | /* Skip return and its delay slot. */ |
95ac2dcf | 4121 | start_pc += 2 * MIPS_INSN32_SIZE; |
29639122 JB |
4122 | break; |
4123 | } | |
4124 | ||
4125 | return start_pc; | |
c906108c SS |
4126 | } |
4127 | ||
6c0d6680 DJ |
4128 | struct mips_objfile_private |
4129 | { | |
4130 | bfd_size_type size; | |
4131 | char *contents; | |
4132 | }; | |
4133 | ||
f09ded24 AC |
4134 | /* According to the current ABI, should the type be passed in a |
4135 | floating-point register (assuming that there is space)? When there | |
a1f5b845 | 4136 | is no FPU, FP are not even considered as possible candidates for |
f09ded24 | 4137 | FP registers and, consequently this returns false - forces FP |
025bb325 | 4138 | arguments into integer registers. */ |
f09ded24 AC |
4139 | |
4140 | static int | |
74ed0bb4 MD |
4141 | fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode, |
4142 | struct type *arg_type) | |
f09ded24 AC |
4143 | { |
4144 | return ((typecode == TYPE_CODE_FLT | |
74ed0bb4 | 4145 | || (MIPS_EABI (gdbarch) |
6d82d43b AC |
4146 | && (typecode == TYPE_CODE_STRUCT |
4147 | || typecode == TYPE_CODE_UNION) | |
f09ded24 | 4148 | && TYPE_NFIELDS (arg_type) == 1 |
b2d6f210 MS |
4149 | && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0))) |
4150 | == TYPE_CODE_FLT)) | |
74ed0bb4 | 4151 | && MIPS_FPU_TYPE(gdbarch) != MIPS_FPU_NONE); |
f09ded24 AC |
4152 | } |
4153 | ||
49e790b0 | 4154 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
025bb325 | 4155 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ |
49e790b0 DJ |
4156 | |
4157 | static int | |
4158 | mips_type_needs_double_align (struct type *type) | |
4159 | { | |
4160 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 4161 | |
49e790b0 DJ |
4162 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
4163 | return 1; | |
4164 | else if (typecode == TYPE_CODE_STRUCT) | |
4165 | { | |
4166 | if (TYPE_NFIELDS (type) < 1) | |
4167 | return 0; | |
4168 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
4169 | } | |
4170 | else if (typecode == TYPE_CODE_UNION) | |
4171 | { | |
361d1df0 | 4172 | int i, n; |
49e790b0 DJ |
4173 | |
4174 | n = TYPE_NFIELDS (type); | |
4175 | for (i = 0; i < n; i++) | |
4176 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
4177 | return 1; | |
4178 | return 0; | |
4179 | } | |
4180 | return 0; | |
4181 | } | |
4182 | ||
dc604539 AC |
4183 | /* Adjust the address downward (direction of stack growth) so that it |
4184 | is correctly aligned for a new stack frame. */ | |
4185 | static CORE_ADDR | |
4186 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
4187 | { | |
5b03f266 | 4188 | return align_down (addr, 16); |
dc604539 AC |
4189 | } |
4190 | ||
8ae38c14 | 4191 | /* Implement the "push_dummy_code" gdbarch method. */ |
2c76a0c7 JB |
4192 | |
4193 | static CORE_ADDR | |
4194 | mips_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
4195 | CORE_ADDR funaddr, struct value **args, | |
4196 | int nargs, struct type *value_type, | |
4197 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, | |
4198 | struct regcache *regcache) | |
4199 | { | |
2c76a0c7 | 4200 | static gdb_byte nop_insn[] = { 0, 0, 0, 0 }; |
2e81047f MR |
4201 | CORE_ADDR nop_addr; |
4202 | CORE_ADDR bp_slot; | |
2c76a0c7 JB |
4203 | |
4204 | /* Reserve enough room on the stack for our breakpoint instruction. */ | |
2e81047f MR |
4205 | bp_slot = sp - sizeof (nop_insn); |
4206 | ||
4207 | /* Return to microMIPS mode if calling microMIPS code to avoid | |
4208 | triggering an address error exception on processors that only | |
4209 | support microMIPS execution. */ | |
4210 | *bp_addr = (mips_pc_is_micromips (gdbarch, funaddr) | |
4211 | ? make_compact_addr (bp_slot) : bp_slot); | |
2c76a0c7 JB |
4212 | |
4213 | /* The breakpoint layer automatically adjusts the address of | |
4214 | breakpoints inserted in a branch delay slot. With enough | |
4215 | bad luck, the 4 bytes located just before our breakpoint | |
4216 | instruction could look like a branch instruction, and thus | |
4217 | trigger the adjustement, and break the function call entirely. | |
4218 | So, we reserve those 4 bytes and write a nop instruction | |
4219 | to prevent that from happening. */ | |
2e81047f | 4220 | nop_addr = bp_slot - sizeof (nop_insn); |
2c76a0c7 JB |
4221 | write_memory (nop_addr, nop_insn, sizeof (nop_insn)); |
4222 | sp = mips_frame_align (gdbarch, nop_addr); | |
4223 | ||
4224 | /* Inferior resumes at the function entry point. */ | |
4225 | *real_pc = funaddr; | |
4226 | ||
4227 | return sp; | |
4228 | } | |
4229 | ||
f7ab6ec6 | 4230 | static CORE_ADDR |
7d9b040b | 4231 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4232 | struct regcache *regcache, CORE_ADDR bp_addr, |
4233 | int nargs, struct value **args, CORE_ADDR sp, | |
4234 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
4235 | { |
4236 | int argreg; | |
4237 | int float_argreg; | |
4238 | int argnum; | |
4239 | int len = 0; | |
4240 | int stack_offset = 0; | |
e17a4113 | 4241 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 4242 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
1a69e1e4 | 4243 | int regsize = mips_abi_regsize (gdbarch); |
c906108c | 4244 | |
25ab4790 AC |
4245 | /* For shared libraries, "t9" needs to point at the function |
4246 | address. */ | |
4c7d22cb | 4247 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
4248 | |
4249 | /* Set the return address register to point to the entry point of | |
4250 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 4251 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 4252 | |
c906108c | 4253 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
4254 | are properly aligned. The stack has to be at least 64-bit |
4255 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4256 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4257 | aligned, so we round to this widest known alignment. */ | |
4258 | ||
5b03f266 AC |
4259 | sp = align_down (sp, 16); |
4260 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 4261 | |
46e0f506 | 4262 | /* Now make space on the stack for the args. We allocate more |
c906108c | 4263 | than necessary for EABI, because the first few arguments are |
46e0f506 | 4264 | passed in registers, but that's OK. */ |
c906108c | 4265 | for (argnum = 0; argnum < nargs; argnum++) |
1a69e1e4 | 4266 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize); |
5b03f266 | 4267 | sp -= align_up (len, 16); |
c906108c | 4268 | |
9ace0497 | 4269 | if (mips_debug) |
6d82d43b | 4270 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
4271 | "mips_eabi_push_dummy_call: sp=%s allocated %ld\n", |
4272 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
9ace0497 | 4273 | |
c906108c | 4274 | /* Initialize the integer and float register pointers. */ |
4c7d22cb | 4275 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 4276 | float_argreg = mips_fpa0_regnum (gdbarch); |
c906108c | 4277 | |
46e0f506 | 4278 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 4279 | if (struct_return) |
9ace0497 AC |
4280 | { |
4281 | if (mips_debug) | |
4282 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
4283 | "mips_eabi_push_dummy_call: " |
4284 | "struct_return reg=%d %s\n", | |
5af949e3 | 4285 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 4286 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
9ace0497 | 4287 | } |
c906108c SS |
4288 | |
4289 | /* Now load as many as possible of the first arguments into | |
4290 | registers, and push the rest onto the stack. Loop thru args | |
4291 | from first to last. */ | |
4292 | for (argnum = 0; argnum < nargs; argnum++) | |
4293 | { | |
47a35522 MK |
4294 | const gdb_byte *val; |
4295 | gdb_byte valbuf[MAX_REGISTER_SIZE]; | |
ea7c478f | 4296 | struct value *arg = args[argnum]; |
4991999e | 4297 | struct type *arg_type = check_typedef (value_type (arg)); |
c906108c SS |
4298 | int len = TYPE_LENGTH (arg_type); |
4299 | enum type_code typecode = TYPE_CODE (arg_type); | |
4300 | ||
9ace0497 AC |
4301 | if (mips_debug) |
4302 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4303 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 4304 | argnum + 1, len, (int) typecode); |
9ace0497 | 4305 | |
930bd0e0 KB |
4306 | /* Function pointer arguments to mips16 code need to be made into |
4307 | mips16 pointers. */ | |
4308 | if (typecode == TYPE_CODE_PTR | |
4309 | && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC) | |
4310 | { | |
4311 | CORE_ADDR addr = extract_signed_integer (value_contents (arg), | |
4312 | len, byte_order); | |
4cc0665f MR |
4313 | if (mips_pc_is_mips (addr)) |
4314 | val = value_contents (arg); | |
4315 | else | |
930bd0e0 KB |
4316 | { |
4317 | store_signed_integer (valbuf, len, byte_order, | |
4cc0665f | 4318 | make_compact_addr (addr)); |
930bd0e0 KB |
4319 | val = valbuf; |
4320 | } | |
930bd0e0 | 4321 | } |
c906108c | 4322 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 4323 | reference. */ |
930bd0e0 | 4324 | else if (len > regsize |
9ace0497 | 4325 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 4326 | { |
e17a4113 UW |
4327 | store_unsigned_integer (valbuf, regsize, byte_order, |
4328 | value_address (arg)); | |
c906108c | 4329 | typecode = TYPE_CODE_PTR; |
1a69e1e4 | 4330 | len = regsize; |
c906108c | 4331 | val = valbuf; |
9ace0497 AC |
4332 | if (mips_debug) |
4333 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
4334 | } |
4335 | else | |
47a35522 | 4336 | val = value_contents (arg); |
c906108c SS |
4337 | |
4338 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
4339 | even-numbered floating point register. Round the FP register |
4340 | up before the check to see if there are any FP registers | |
46e0f506 MS |
4341 | left. Non MIPS_EABI targets also pass the FP in the integer |
4342 | registers so also round up normal registers. */ | |
74ed0bb4 | 4343 | if (regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type)) |
acdb74a0 AC |
4344 | { |
4345 | if ((float_argreg & 1)) | |
4346 | float_argreg++; | |
4347 | } | |
c906108c SS |
4348 | |
4349 | /* Floating point arguments passed in registers have to be | |
4350 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
4351 | are passed in register pairs; the even register gets |
4352 | the low word, and the odd register gets the high word. | |
4353 | On non-EABI processors, the first two floating point arguments are | |
4354 | also copied to general registers, because MIPS16 functions | |
4355 | don't use float registers for arguments. This duplication of | |
4356 | arguments in general registers can't hurt non-MIPS16 functions | |
4357 | because those registers are normally skipped. */ | |
1012bd0e EZ |
4358 | /* MIPS_EABI squeezes a struct that contains a single floating |
4359 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 4360 | stack. */ |
74ed0bb4 MD |
4361 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
4362 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
c906108c | 4363 | { |
6da397e0 KB |
4364 | /* EABI32 will pass doubles in consecutive registers, even on |
4365 | 64-bit cores. At one time, we used to check the size of | |
4366 | `float_argreg' to determine whether or not to pass doubles | |
4367 | in consecutive registers, but this is not sufficient for | |
4368 | making the ABI determination. */ | |
4369 | if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) | |
c906108c | 4370 | { |
72a155b4 | 4371 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 4372 | == BFD_ENDIAN_BIG ? 4 : 0; |
a8852dc5 | 4373 | long regval; |
c906108c SS |
4374 | |
4375 | /* Write the low word of the double to the even register(s). */ | |
a8852dc5 KB |
4376 | regval = extract_signed_integer (val + low_offset, |
4377 | 4, byte_order); | |
9ace0497 | 4378 | if (mips_debug) |
acdb74a0 | 4379 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 4380 | float_argreg, phex (regval, 4)); |
a8852dc5 | 4381 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
4382 | |
4383 | /* Write the high word of the double to the odd register(s). */ | |
a8852dc5 KB |
4384 | regval = extract_signed_integer (val + 4 - low_offset, |
4385 | 4, byte_order); | |
9ace0497 | 4386 | if (mips_debug) |
acdb74a0 | 4387 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 4388 | float_argreg, phex (regval, 4)); |
a8852dc5 | 4389 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
4390 | } |
4391 | else | |
4392 | { | |
4393 | /* This is a floating point value that fits entirely | |
4394 | in a single register. */ | |
53a5351d | 4395 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 4396 | above to ensure that it is even register aligned. */ |
a8852dc5 | 4397 | LONGEST regval = extract_signed_integer (val, len, byte_order); |
9ace0497 | 4398 | if (mips_debug) |
acdb74a0 | 4399 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 4400 | float_argreg, phex (regval, len)); |
a8852dc5 | 4401 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
4402 | } |
4403 | } | |
4404 | else | |
4405 | { | |
4406 | /* Copy the argument to general registers or the stack in | |
4407 | register-sized pieces. Large arguments are split between | |
4408 | registers and stack. */ | |
1a69e1e4 DJ |
4409 | /* Note: structs whose size is not a multiple of regsize |
4410 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
4411 | them in registers where gcc sometimes puts them on the |
4412 | stack. For maximum compatibility, we will put them in | |
4413 | both places. */ | |
1a69e1e4 | 4414 | int odd_sized_struct = (len > regsize && len % regsize != 0); |
46e0f506 | 4415 | |
f09ded24 | 4416 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 4417 | register are only written to memory. */ |
c906108c SS |
4418 | while (len > 0) |
4419 | { | |
ebafbe83 | 4420 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 4421 | int stack_used_p = 0; |
1a69e1e4 | 4422 | int partial_len = (len < regsize ? len : regsize); |
c906108c | 4423 | |
acdb74a0 AC |
4424 | if (mips_debug) |
4425 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4426 | partial_len); | |
4427 | ||
566f0f7a | 4428 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 4429 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
f09ded24 | 4430 | || odd_sized_struct |
74ed0bb4 | 4431 | || fp_register_arg_p (gdbarch, typecode, arg_type)) |
c906108c | 4432 | { |
c906108c | 4433 | /* Should shorter than int integer values be |
025bb325 | 4434 | promoted to int before being stored? */ |
c906108c | 4435 | int longword_offset = 0; |
9ace0497 | 4436 | CORE_ADDR addr; |
566f0f7a | 4437 | stack_used_p = 1; |
72a155b4 | 4438 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
7a292a7a | 4439 | { |
1a69e1e4 | 4440 | if (regsize == 8 |
480d3dd2 AC |
4441 | && (typecode == TYPE_CODE_INT |
4442 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 4443 | || typecode == TYPE_CODE_FLT) && len <= 4) |
1a69e1e4 | 4444 | longword_offset = regsize - len; |
480d3dd2 AC |
4445 | else if ((typecode == TYPE_CODE_STRUCT |
4446 | || typecode == TYPE_CODE_UNION) | |
1a69e1e4 DJ |
4447 | && TYPE_LENGTH (arg_type) < regsize) |
4448 | longword_offset = regsize - len; | |
7a292a7a | 4449 | } |
c5aa993b | 4450 | |
9ace0497 AC |
4451 | if (mips_debug) |
4452 | { | |
5af949e3 UW |
4453 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
4454 | paddress (gdbarch, stack_offset)); | |
4455 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
4456 | paddress (gdbarch, longword_offset)); | |
9ace0497 | 4457 | } |
361d1df0 | 4458 | |
9ace0497 AC |
4459 | addr = sp + stack_offset + longword_offset; |
4460 | ||
4461 | if (mips_debug) | |
4462 | { | |
4463 | int i; | |
5af949e3 UW |
4464 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
4465 | paddress (gdbarch, addr)); | |
9ace0497 AC |
4466 | for (i = 0; i < partial_len; i++) |
4467 | { | |
6d82d43b | 4468 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 4469 | val[i] & 0xff); |
9ace0497 AC |
4470 | } |
4471 | } | |
4472 | write_memory (addr, val, partial_len); | |
c906108c SS |
4473 | } |
4474 | ||
f09ded24 AC |
4475 | /* Note!!! This is NOT an else clause. Odd sized |
4476 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 4477 | arguments will not. */ |
566f0f7a | 4478 | /* Write this portion of the argument to a general |
6d82d43b | 4479 | purpose register. */ |
74ed0bb4 MD |
4480 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch) |
4481 | && !fp_register_arg_p (gdbarch, typecode, arg_type)) | |
c906108c | 4482 | { |
6d82d43b | 4483 | LONGEST regval = |
a8852dc5 | 4484 | extract_signed_integer (val, partial_len, byte_order); |
c906108c | 4485 | |
9ace0497 | 4486 | if (mips_debug) |
acdb74a0 | 4487 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 4488 | argreg, |
1a69e1e4 | 4489 | phex (regval, regsize)); |
a8852dc5 | 4490 | regcache_cooked_write_signed (regcache, argreg, regval); |
c906108c | 4491 | argreg++; |
c906108c | 4492 | } |
c5aa993b | 4493 | |
c906108c SS |
4494 | len -= partial_len; |
4495 | val += partial_len; | |
4496 | ||
b021a221 MS |
4497 | /* Compute the offset into the stack at which we will |
4498 | copy the next parameter. | |
566f0f7a | 4499 | |
566f0f7a | 4500 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 4501 | only needs to be adjusted when it has been used. */ |
c906108c | 4502 | |
46e0f506 | 4503 | if (stack_used_p) |
1a69e1e4 | 4504 | stack_offset += align_up (partial_len, regsize); |
c906108c SS |
4505 | } |
4506 | } | |
9ace0497 AC |
4507 | if (mips_debug) |
4508 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
4509 | } |
4510 | ||
f10683bb | 4511 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4512 | |
0f71a2f6 JM |
4513 | /* Return adjusted stack pointer. */ |
4514 | return sp; | |
4515 | } | |
4516 | ||
a1f5b845 | 4517 | /* Determine the return value convention being used. */ |
6d82d43b | 4518 | |
9c8fdbfa | 4519 | static enum return_value_convention |
6a3a010b | 4520 | mips_eabi_return_value (struct gdbarch *gdbarch, struct value *function, |
9c8fdbfa | 4521 | struct type *type, struct regcache *regcache, |
47a35522 | 4522 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 4523 | { |
609ba780 JM |
4524 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4525 | int fp_return_type = 0; | |
4526 | int offset, regnum, xfer; | |
4527 | ||
9c8fdbfa AC |
4528 | if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
4529 | return RETURN_VALUE_STRUCT_CONVENTION; | |
609ba780 JM |
4530 | |
4531 | /* Floating point type? */ | |
4532 | if (tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4533 | { | |
4534 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
4535 | fp_return_type = 1; | |
4536 | /* Structs with a single field of float type | |
4537 | are returned in a floating point register. */ | |
4538 | if ((TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4539 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4540 | && TYPE_NFIELDS (type) == 1) | |
4541 | { | |
4542 | struct type *fieldtype = TYPE_FIELD_TYPE (type, 0); | |
4543 | ||
4544 | if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT) | |
4545 | fp_return_type = 1; | |
4546 | } | |
4547 | } | |
4548 | ||
4549 | if (fp_return_type) | |
4550 | { | |
4551 | /* A floating-point value belongs in the least significant part | |
4552 | of FP0/FP1. */ | |
4553 | if (mips_debug) | |
4554 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
4555 | regnum = mips_regnum (gdbarch)->fp0; | |
4556 | } | |
4557 | else | |
4558 | { | |
4559 | /* An integer value goes in V0/V1. */ | |
4560 | if (mips_debug) | |
4561 | fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n"); | |
4562 | regnum = MIPS_V0_REGNUM; | |
4563 | } | |
4564 | for (offset = 0; | |
4565 | offset < TYPE_LENGTH (type); | |
4566 | offset += mips_abi_regsize (gdbarch), regnum++) | |
4567 | { | |
4568 | xfer = mips_abi_regsize (gdbarch); | |
4569 | if (offset + xfer > TYPE_LENGTH (type)) | |
4570 | xfer = TYPE_LENGTH (type) - offset; | |
4571 | mips_xfer_register (gdbarch, regcache, | |
4572 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
4573 | gdbarch_byte_order (gdbarch), readbuf, writebuf, | |
4574 | offset); | |
4575 | } | |
4576 | ||
9c8fdbfa | 4577 | return RETURN_VALUE_REGISTER_CONVENTION; |
6d82d43b AC |
4578 | } |
4579 | ||
6d82d43b AC |
4580 | |
4581 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 4582 | |
8d26208a DJ |
4583 | /* Search for a naturally aligned double at OFFSET inside a struct |
4584 | ARG_TYPE. The N32 / N64 ABIs pass these in floating point | |
4585 | registers. */ | |
4586 | ||
4587 | static int | |
74ed0bb4 MD |
4588 | mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type, |
4589 | int offset) | |
8d26208a DJ |
4590 | { |
4591 | int i; | |
4592 | ||
4593 | if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT) | |
4594 | return 0; | |
4595 | ||
74ed0bb4 | 4596 | if (MIPS_FPU_TYPE (gdbarch) != MIPS_FPU_DOUBLE) |
8d26208a DJ |
4597 | return 0; |
4598 | ||
4599 | if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE) | |
4600 | return 0; | |
4601 | ||
4602 | for (i = 0; i < TYPE_NFIELDS (arg_type); i++) | |
4603 | { | |
4604 | int pos; | |
4605 | struct type *field_type; | |
4606 | ||
4607 | /* We're only looking at normal fields. */ | |
5bc60cfb | 4608 | if (field_is_static (&TYPE_FIELD (arg_type, i)) |
8d26208a DJ |
4609 | || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0) |
4610 | continue; | |
4611 | ||
4612 | /* If we have gone past the offset, there is no double to pass. */ | |
4613 | pos = TYPE_FIELD_BITPOS (arg_type, i) / 8; | |
4614 | if (pos > offset) | |
4615 | return 0; | |
4616 | ||
4617 | field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i)); | |
4618 | ||
4619 | /* If this field is entirely before the requested offset, go | |
4620 | on to the next one. */ | |
4621 | if (pos + TYPE_LENGTH (field_type) <= offset) | |
4622 | continue; | |
4623 | ||
4624 | /* If this is our special aligned double, we can stop. */ | |
4625 | if (TYPE_CODE (field_type) == TYPE_CODE_FLT | |
4626 | && TYPE_LENGTH (field_type) == MIPS64_REGSIZE) | |
4627 | return 1; | |
4628 | ||
4629 | /* This field starts at or before the requested offset, and | |
4630 | overlaps it. If it is a structure, recurse inwards. */ | |
74ed0bb4 | 4631 | return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos); |
8d26208a DJ |
4632 | } |
4633 | ||
4634 | return 0; | |
4635 | } | |
4636 | ||
f7ab6ec6 | 4637 | static CORE_ADDR |
7d9b040b | 4638 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4639 | struct regcache *regcache, CORE_ADDR bp_addr, |
4640 | int nargs, struct value **args, CORE_ADDR sp, | |
4641 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
4642 | { |
4643 | int argreg; | |
4644 | int float_argreg; | |
4645 | int argnum; | |
4646 | int len = 0; | |
4647 | int stack_offset = 0; | |
e17a4113 | 4648 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 4649 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 4650 | |
25ab4790 AC |
4651 | /* For shared libraries, "t9" needs to point at the function |
4652 | address. */ | |
4c7d22cb | 4653 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
4654 | |
4655 | /* Set the return address register to point to the entry point of | |
4656 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 4657 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 4658 | |
cb3d25d1 MS |
4659 | /* First ensure that the stack and structure return address (if any) |
4660 | are properly aligned. The stack has to be at least 64-bit | |
4661 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4662 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4663 | aligned, so we round to this widest known alignment. */ | |
4664 | ||
5b03f266 AC |
4665 | sp = align_down (sp, 16); |
4666 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
4667 | |
4668 | /* Now make space on the stack for the args. */ | |
4669 | for (argnum = 0; argnum < nargs; argnum++) | |
1a69e1e4 | 4670 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE); |
5b03f266 | 4671 | sp -= align_up (len, 16); |
cb3d25d1 MS |
4672 | |
4673 | if (mips_debug) | |
6d82d43b | 4674 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
4675 | "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n", |
4676 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
4677 | |
4678 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 4679 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 4680 | float_argreg = mips_fpa0_regnum (gdbarch); |
cb3d25d1 | 4681 | |
46e0f506 | 4682 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
4683 | if (struct_return) |
4684 | { | |
4685 | if (mips_debug) | |
4686 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
4687 | "mips_n32n64_push_dummy_call: " |
4688 | "struct_return reg=%d %s\n", | |
5af949e3 | 4689 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 4690 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
cb3d25d1 MS |
4691 | } |
4692 | ||
4693 | /* Now load as many as possible of the first arguments into | |
4694 | registers, and push the rest onto the stack. Loop thru args | |
4695 | from first to last. */ | |
4696 | for (argnum = 0; argnum < nargs; argnum++) | |
4697 | { | |
47a35522 | 4698 | const gdb_byte *val; |
cb3d25d1 | 4699 | struct value *arg = args[argnum]; |
4991999e | 4700 | struct type *arg_type = check_typedef (value_type (arg)); |
cb3d25d1 MS |
4701 | int len = TYPE_LENGTH (arg_type); |
4702 | enum type_code typecode = TYPE_CODE (arg_type); | |
4703 | ||
4704 | if (mips_debug) | |
4705 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4706 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
4707 | argnum + 1, len, (int) typecode); |
4708 | ||
47a35522 | 4709 | val = value_contents (arg); |
cb3d25d1 | 4710 | |
5b68030f JM |
4711 | /* A 128-bit long double value requires an even-odd pair of |
4712 | floating-point registers. */ | |
4713 | if (len == 16 | |
4714 | && fp_register_arg_p (gdbarch, typecode, arg_type) | |
4715 | && (float_argreg & 1)) | |
4716 | { | |
4717 | float_argreg++; | |
4718 | argreg++; | |
4719 | } | |
4720 | ||
74ed0bb4 MD |
4721 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
4722 | && argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) | |
cb3d25d1 MS |
4723 | { |
4724 | /* This is a floating point value that fits entirely | |
5b68030f JM |
4725 | in a single register or a pair of registers. */ |
4726 | int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE); | |
e17a4113 | 4727 | LONGEST regval = extract_unsigned_integer (val, reglen, byte_order); |
cb3d25d1 MS |
4728 | if (mips_debug) |
4729 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5b68030f | 4730 | float_argreg, phex (regval, reglen)); |
8d26208a | 4731 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); |
cb3d25d1 MS |
4732 | |
4733 | if (mips_debug) | |
4734 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5b68030f | 4735 | argreg, phex (regval, reglen)); |
9c9acae0 | 4736 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a DJ |
4737 | float_argreg++; |
4738 | argreg++; | |
5b68030f JM |
4739 | if (len == 16) |
4740 | { | |
e17a4113 UW |
4741 | regval = extract_unsigned_integer (val + reglen, |
4742 | reglen, byte_order); | |
5b68030f JM |
4743 | if (mips_debug) |
4744 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4745 | float_argreg, phex (regval, reglen)); | |
4746 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); | |
4747 | ||
4748 | if (mips_debug) | |
4749 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4750 | argreg, phex (regval, reglen)); | |
4751 | regcache_cooked_write_unsigned (regcache, argreg, regval); | |
4752 | float_argreg++; | |
4753 | argreg++; | |
4754 | } | |
cb3d25d1 MS |
4755 | } |
4756 | else | |
4757 | { | |
4758 | /* Copy the argument to general registers or the stack in | |
4759 | register-sized pieces. Large arguments are split between | |
4760 | registers and stack. */ | |
ab2e1992 MR |
4761 | /* For N32/N64, structs, unions, or other composite types are |
4762 | treated as a sequence of doublewords, and are passed in integer | |
4763 | or floating point registers as though they were simple scalar | |
4764 | parameters to the extent that they fit, with any excess on the | |
4765 | stack packed according to the normal memory layout of the | |
4766 | object. | |
4767 | The caller does not reserve space for the register arguments; | |
4768 | the callee is responsible for reserving it if required. */ | |
cb3d25d1 | 4769 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 4770 | register are only written to memory. */ |
cb3d25d1 MS |
4771 | while (len > 0) |
4772 | { | |
ad018eee | 4773 | /* Remember if the argument was written to the stack. */ |
cb3d25d1 | 4774 | int stack_used_p = 0; |
1a69e1e4 | 4775 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
cb3d25d1 MS |
4776 | |
4777 | if (mips_debug) | |
4778 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4779 | partial_len); | |
4780 | ||
74ed0bb4 MD |
4781 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
4782 | gdb_assert (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)); | |
8d26208a | 4783 | |
cb3d25d1 | 4784 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 4785 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 MS |
4786 | { |
4787 | /* Should shorter than int integer values be | |
025bb325 | 4788 | promoted to int before being stored? */ |
cb3d25d1 MS |
4789 | int longword_offset = 0; |
4790 | CORE_ADDR addr; | |
4791 | stack_used_p = 1; | |
72a155b4 | 4792 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
cb3d25d1 | 4793 | { |
1a69e1e4 | 4794 | if ((typecode == TYPE_CODE_INT |
5b68030f | 4795 | || typecode == TYPE_CODE_PTR) |
1a69e1e4 DJ |
4796 | && len <= 4) |
4797 | longword_offset = MIPS64_REGSIZE - len; | |
cb3d25d1 MS |
4798 | } |
4799 | ||
4800 | if (mips_debug) | |
4801 | { | |
5af949e3 UW |
4802 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
4803 | paddress (gdbarch, stack_offset)); | |
4804 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
4805 | paddress (gdbarch, longword_offset)); | |
cb3d25d1 MS |
4806 | } |
4807 | ||
4808 | addr = sp + stack_offset + longword_offset; | |
4809 | ||
4810 | if (mips_debug) | |
4811 | { | |
4812 | int i; | |
5af949e3 UW |
4813 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
4814 | paddress (gdbarch, addr)); | |
cb3d25d1 MS |
4815 | for (i = 0; i < partial_len; i++) |
4816 | { | |
6d82d43b | 4817 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
4818 | val[i] & 0xff); |
4819 | } | |
4820 | } | |
4821 | write_memory (addr, val, partial_len); | |
4822 | } | |
4823 | ||
4824 | /* Note!!! This is NOT an else clause. Odd sized | |
8d26208a | 4825 | structs may go thru BOTH paths. */ |
cb3d25d1 | 4826 | /* Write this portion of the argument to a general |
6d82d43b | 4827 | purpose register. */ |
74ed0bb4 | 4828 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 | 4829 | { |
5863b5d5 MR |
4830 | LONGEST regval; |
4831 | ||
4832 | /* Sign extend pointers, 32-bit integers and signed | |
4833 | 16-bit and 8-bit integers; everything else is taken | |
4834 | as is. */ | |
4835 | ||
4836 | if ((partial_len == 4 | |
4837 | && (typecode == TYPE_CODE_PTR | |
4838 | || typecode == TYPE_CODE_INT)) | |
4839 | || (partial_len < 4 | |
4840 | && typecode == TYPE_CODE_INT | |
4841 | && !TYPE_UNSIGNED (arg_type))) | |
e17a4113 UW |
4842 | regval = extract_signed_integer (val, partial_len, |
4843 | byte_order); | |
5863b5d5 | 4844 | else |
e17a4113 UW |
4845 | regval = extract_unsigned_integer (val, partial_len, |
4846 | byte_order); | |
cb3d25d1 MS |
4847 | |
4848 | /* A non-floating-point argument being passed in a | |
4849 | general register. If a struct or union, and if | |
4850 | the remaining length is smaller than the register | |
4851 | size, we have to adjust the register value on | |
4852 | big endian targets. | |
4853 | ||
4854 | It does not seem to be necessary to do the | |
1a69e1e4 | 4855 | same for integral types. */ |
cb3d25d1 | 4856 | |
72a155b4 | 4857 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 4858 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
4859 | && (typecode == TYPE_CODE_STRUCT |
4860 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 4861 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 4862 | * TARGET_CHAR_BIT); |
cb3d25d1 MS |
4863 | |
4864 | if (mips_debug) | |
4865 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
4866 | argreg, | |
1a69e1e4 | 4867 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 4868 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a | 4869 | |
74ed0bb4 | 4870 | if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type, |
8d26208a DJ |
4871 | TYPE_LENGTH (arg_type) - len)) |
4872 | { | |
4873 | if (mips_debug) | |
4874 | fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s", | |
4875 | float_argreg, | |
4876 | phex (regval, MIPS64_REGSIZE)); | |
4877 | regcache_cooked_write_unsigned (regcache, float_argreg, | |
4878 | regval); | |
4879 | } | |
4880 | ||
4881 | float_argreg++; | |
cb3d25d1 MS |
4882 | argreg++; |
4883 | } | |
4884 | ||
4885 | len -= partial_len; | |
4886 | val += partial_len; | |
4887 | ||
b021a221 MS |
4888 | /* Compute the offset into the stack at which we will |
4889 | copy the next parameter. | |
cb3d25d1 MS |
4890 | |
4891 | In N32 (N64?), the stack_offset only needs to be | |
4892 | adjusted when it has been used. */ | |
4893 | ||
4894 | if (stack_used_p) | |
1a69e1e4 | 4895 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
cb3d25d1 MS |
4896 | } |
4897 | } | |
4898 | if (mips_debug) | |
4899 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
4900 | } | |
4901 | ||
f10683bb | 4902 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4903 | |
cb3d25d1 MS |
4904 | /* Return adjusted stack pointer. */ |
4905 | return sp; | |
4906 | } | |
4907 | ||
6d82d43b | 4908 | static enum return_value_convention |
6a3a010b | 4909 | mips_n32n64_return_value (struct gdbarch *gdbarch, struct value *function, |
6d82d43b | 4910 | struct type *type, struct regcache *regcache, |
47a35522 | 4911 | gdb_byte *readbuf, const gdb_byte *writebuf) |
ebafbe83 | 4912 | { |
72a155b4 | 4913 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
b18bb924 MR |
4914 | |
4915 | /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004 | |
4916 | ||
4917 | Function results are returned in $2 (and $3 if needed), or $f0 (and $f2 | |
4918 | if needed), as appropriate for the type. Composite results (struct, | |
4919 | union, or array) are returned in $2/$f0 and $3/$f2 according to the | |
4920 | following rules: | |
4921 | ||
4922 | * A struct with only one or two floating point fields is returned in $f0 | |
4923 | (and $f2 if necessary). This is a generalization of the Fortran COMPLEX | |
4924 | case. | |
4925 | ||
f08877ba | 4926 | * Any other composite results of at most 128 bits are returned in |
b18bb924 MR |
4927 | $2 (first 64 bits) and $3 (remainder, if necessary). |
4928 | ||
4929 | * Larger composite results are handled by converting the function to a | |
4930 | procedure with an implicit first parameter, which is a pointer to an area | |
4931 | reserved by the caller to receive the result. [The o32-bit ABI requires | |
4932 | that all composite results be handled by conversion to implicit first | |
4933 | parameters. The MIPS/SGI Fortran implementation has always made a | |
4934 | specific exception to return COMPLEX results in the floating point | |
4935 | registers.] */ | |
4936 | ||
f08877ba | 4937 | if (TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE) |
6d82d43b | 4938 | return RETURN_VALUE_STRUCT_CONVENTION; |
d05f6826 DJ |
4939 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
4940 | && TYPE_LENGTH (type) == 16 | |
4941 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4942 | { | |
4943 | /* A 128-bit floating-point value fills both $f0 and $f2. The | |
4944 | two registers are used in the same as memory order, so the | |
4945 | eight bytes with the lower memory address are in $f0. */ | |
4946 | if (mips_debug) | |
4947 | fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n"); | |
ba32f989 | 4948 | mips_xfer_register (gdbarch, regcache, |
dca9aa3a MR |
4949 | (gdbarch_num_regs (gdbarch) |
4950 | + mips_regnum (gdbarch)->fp0), | |
72a155b4 | 4951 | 8, gdbarch_byte_order (gdbarch), |
4c6b5505 | 4952 | readbuf, writebuf, 0); |
ba32f989 | 4953 | mips_xfer_register (gdbarch, regcache, |
dca9aa3a MR |
4954 | (gdbarch_num_regs (gdbarch) |
4955 | + mips_regnum (gdbarch)->fp0 + 2), | |
72a155b4 | 4956 | 8, gdbarch_byte_order (gdbarch), |
4c6b5505 | 4957 | readbuf ? readbuf + 8 : readbuf, |
d05f6826 DJ |
4958 | writebuf ? writebuf + 8 : writebuf, 0); |
4959 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4960 | } | |
6d82d43b AC |
4961 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
4962 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4963 | { | |
59aa1faa | 4964 | /* A single or double floating-point value that fits in FP0. */ |
6d82d43b AC |
4965 | if (mips_debug) |
4966 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 4967 | mips_xfer_register (gdbarch, regcache, |
dca9aa3a MR |
4968 | (gdbarch_num_regs (gdbarch) |
4969 | + mips_regnum (gdbarch)->fp0), | |
6d82d43b | 4970 | TYPE_LENGTH (type), |
72a155b4 | 4971 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4972 | readbuf, writebuf, 0); |
6d82d43b AC |
4973 | return RETURN_VALUE_REGISTER_CONVENTION; |
4974 | } | |
4975 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4976 | && TYPE_NFIELDS (type) <= 2 | |
4977 | && TYPE_NFIELDS (type) >= 1 | |
4978 | && ((TYPE_NFIELDS (type) == 1 | |
b18bb924 | 4979 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b AC |
4980 | == TYPE_CODE_FLT)) |
4981 | || (TYPE_NFIELDS (type) == 2 | |
b18bb924 | 4982 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b | 4983 | == TYPE_CODE_FLT) |
b18bb924 | 4984 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1))) |
5b68030f | 4985 | == TYPE_CODE_FLT)))) |
6d82d43b AC |
4986 | { |
4987 | /* A struct that contains one or two floats. Each value is part | |
4988 | in the least significant part of their floating point | |
5b68030f | 4989 | register (or GPR, for soft float). */ |
6d82d43b AC |
4990 | int regnum; |
4991 | int field; | |
5b68030f JM |
4992 | for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE |
4993 | ? mips_regnum (gdbarch)->fp0 | |
4994 | : MIPS_V0_REGNUM); | |
6d82d43b AC |
4995 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
4996 | { | |
4997 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
4998 | / TARGET_CHAR_BIT); | |
4999 | if (mips_debug) | |
5000 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
5001 | offset); | |
5b68030f JM |
5002 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)) == 16) |
5003 | { | |
5004 | /* A 16-byte long double field goes in two consecutive | |
5005 | registers. */ | |
5006 | mips_xfer_register (gdbarch, regcache, | |
5007 | gdbarch_num_regs (gdbarch) + regnum, | |
5008 | 8, | |
5009 | gdbarch_byte_order (gdbarch), | |
5010 | readbuf, writebuf, offset); | |
5011 | mips_xfer_register (gdbarch, regcache, | |
5012 | gdbarch_num_regs (gdbarch) + regnum + 1, | |
5013 | 8, | |
5014 | gdbarch_byte_order (gdbarch), | |
5015 | readbuf, writebuf, offset + 8); | |
5016 | } | |
5017 | else | |
5018 | mips_xfer_register (gdbarch, regcache, | |
5019 | gdbarch_num_regs (gdbarch) + regnum, | |
5020 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
5021 | gdbarch_byte_order (gdbarch), | |
5022 | readbuf, writebuf, offset); | |
6d82d43b AC |
5023 | } |
5024 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5025 | } | |
5026 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
f08877ba JB |
5027 | || TYPE_CODE (type) == TYPE_CODE_UNION |
5028 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
6d82d43b | 5029 | { |
f08877ba | 5030 | /* A composite type. Extract the left justified value, |
6d82d43b AC |
5031 | regardless of the byte order. I.e. DO NOT USE |
5032 | mips_xfer_lower. */ | |
5033 | int offset; | |
5034 | int regnum; | |
4c7d22cb | 5035 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 5036 | offset < TYPE_LENGTH (type); |
72a155b4 | 5037 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 5038 | { |
72a155b4 | 5039 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
5040 | if (offset + xfer > TYPE_LENGTH (type)) |
5041 | xfer = TYPE_LENGTH (type) - offset; | |
5042 | if (mips_debug) | |
5043 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
5044 | offset, xfer, regnum); | |
ba32f989 DJ |
5045 | mips_xfer_register (gdbarch, regcache, |
5046 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 UW |
5047 | xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf, |
5048 | offset); | |
6d82d43b AC |
5049 | } |
5050 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5051 | } | |
5052 | else | |
5053 | { | |
5054 | /* A scalar extract each part but least-significant-byte | |
5055 | justified. */ | |
5056 | int offset; | |
5057 | int regnum; | |
4c7d22cb | 5058 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 5059 | offset < TYPE_LENGTH (type); |
72a155b4 | 5060 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 5061 | { |
72a155b4 | 5062 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
5063 | if (offset + xfer > TYPE_LENGTH (type)) |
5064 | xfer = TYPE_LENGTH (type) - offset; | |
5065 | if (mips_debug) | |
5066 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
5067 | offset, xfer, regnum); | |
ba32f989 DJ |
5068 | mips_xfer_register (gdbarch, regcache, |
5069 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 5070 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5071 | readbuf, writebuf, offset); |
6d82d43b AC |
5072 | } |
5073 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5074 | } | |
5075 | } | |
5076 | ||
6a3a010b MR |
5077 | /* Which registers to use for passing floating-point values between |
5078 | function calls, one of floating-point, general and both kinds of | |
5079 | registers. O32 and O64 use different register kinds for standard | |
5080 | MIPS and MIPS16 code; to make the handling of cases where we may | |
5081 | not know what kind of code is being used (e.g. no debug information) | |
5082 | easier we sometimes use both kinds. */ | |
5083 | ||
5084 | enum mips_fval_reg | |
5085 | { | |
5086 | mips_fval_fpr, | |
5087 | mips_fval_gpr, | |
5088 | mips_fval_both | |
5089 | }; | |
5090 | ||
6d82d43b AC |
5091 | /* O32 ABI stuff. */ |
5092 | ||
5093 | static CORE_ADDR | |
7d9b040b | 5094 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
5095 | struct regcache *regcache, CORE_ADDR bp_addr, |
5096 | int nargs, struct value **args, CORE_ADDR sp, | |
5097 | int struct_return, CORE_ADDR struct_addr) | |
5098 | { | |
5099 | int argreg; | |
5100 | int float_argreg; | |
5101 | int argnum; | |
5102 | int len = 0; | |
5103 | int stack_offset = 0; | |
e17a4113 | 5104 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 5105 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
5106 | |
5107 | /* For shared libraries, "t9" needs to point at the function | |
5108 | address. */ | |
4c7d22cb | 5109 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
6d82d43b AC |
5110 | |
5111 | /* Set the return address register to point to the entry point of | |
5112 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 5113 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
6d82d43b AC |
5114 | |
5115 | /* First ensure that the stack and structure return address (if any) | |
5116 | are properly aligned. The stack has to be at least 64-bit | |
5117 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
5118 | aligned. For n32 and n64, stack frames need to be 128-bit |
5119 | aligned, so we round to this widest known alignment. */ | |
5120 | ||
5b03f266 AC |
5121 | sp = align_down (sp, 16); |
5122 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
5123 | |
5124 | /* Now make space on the stack for the args. */ | |
5125 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
5126 | { |
5127 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
5128 | int arglen = TYPE_LENGTH (arg_type); | |
5129 | ||
5130 | /* Align to double-word if necessary. */ | |
2afd3f0a | 5131 | if (mips_type_needs_double_align (arg_type)) |
1a69e1e4 | 5132 | len = align_up (len, MIPS32_REGSIZE * 2); |
968b5391 | 5133 | /* Allocate space on the stack. */ |
1a69e1e4 | 5134 | len += align_up (arglen, MIPS32_REGSIZE); |
968b5391 | 5135 | } |
5b03f266 | 5136 | sp -= align_up (len, 16); |
ebafbe83 MS |
5137 | |
5138 | if (mips_debug) | |
6d82d43b | 5139 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
5140 | "mips_o32_push_dummy_call: sp=%s allocated %ld\n", |
5141 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
5142 | |
5143 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 5144 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 5145 | float_argreg = mips_fpa0_regnum (gdbarch); |
ebafbe83 | 5146 | |
bcb0cc15 | 5147 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
5148 | if (struct_return) |
5149 | { | |
5150 | if (mips_debug) | |
5151 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
5152 | "mips_o32_push_dummy_call: " |
5153 | "struct_return reg=%d %s\n", | |
5af949e3 | 5154 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 5155 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 5156 | stack_offset += MIPS32_REGSIZE; |
ebafbe83 MS |
5157 | } |
5158 | ||
5159 | /* Now load as many as possible of the first arguments into | |
5160 | registers, and push the rest onto the stack. Loop thru args | |
5161 | from first to last. */ | |
5162 | for (argnum = 0; argnum < nargs; argnum++) | |
5163 | { | |
47a35522 | 5164 | const gdb_byte *val; |
ebafbe83 | 5165 | struct value *arg = args[argnum]; |
4991999e | 5166 | struct type *arg_type = check_typedef (value_type (arg)); |
ebafbe83 MS |
5167 | int len = TYPE_LENGTH (arg_type); |
5168 | enum type_code typecode = TYPE_CODE (arg_type); | |
5169 | ||
5170 | if (mips_debug) | |
5171 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 5172 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
5173 | argnum + 1, len, (int) typecode); |
5174 | ||
47a35522 | 5175 | val = value_contents (arg); |
46cac009 AC |
5176 | |
5177 | /* 32-bit ABIs always start floating point arguments in an | |
5178 | even-numbered floating point register. Round the FP register | |
5179 | up before the check to see if there are any FP registers | |
6a3a010b MR |
5180 | left. O32 targets also pass the FP in the integer registers |
5181 | so also round up normal registers. */ | |
74ed0bb4 | 5182 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
46cac009 AC |
5183 | { |
5184 | if ((float_argreg & 1)) | |
5185 | float_argreg++; | |
5186 | } | |
5187 | ||
5188 | /* Floating point arguments passed in registers have to be | |
6a3a010b MR |
5189 | treated specially. On 32-bit architectures, doubles are |
5190 | passed in register pairs; the even FP register gets the | |
5191 | low word, and the odd FP register gets the high word. | |
5192 | On O32, the first two floating point arguments are also | |
5193 | copied to general registers, following their memory order, | |
5194 | because MIPS16 functions don't use float registers for | |
5195 | arguments. This duplication of arguments in general | |
5196 | registers can't hurt non-MIPS16 functions, because those | |
5197 | registers are normally skipped. */ | |
46cac009 | 5198 | |
74ed0bb4 MD |
5199 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
5200 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
46cac009 | 5201 | { |
8b07f6d8 | 5202 | if (register_size (gdbarch, float_argreg) < 8 && len == 8) |
46cac009 | 5203 | { |
6a3a010b MR |
5204 | int freg_offset = gdbarch_byte_order (gdbarch) |
5205 | == BFD_ENDIAN_BIG ? 1 : 0; | |
46cac009 AC |
5206 | unsigned long regval; |
5207 | ||
6a3a010b MR |
5208 | /* First word. */ |
5209 | regval = extract_unsigned_integer (val, 4, byte_order); | |
46cac009 AC |
5210 | if (mips_debug) |
5211 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
6a3a010b MR |
5212 | float_argreg + freg_offset, |
5213 | phex (regval, 4)); | |
025bb325 | 5214 | regcache_cooked_write_unsigned (regcache, |
6a3a010b MR |
5215 | float_argreg++ + freg_offset, |
5216 | regval); | |
46cac009 AC |
5217 | if (mips_debug) |
5218 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5219 | argreg, phex (regval, 4)); | |
9c9acae0 | 5220 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 | 5221 | |
6a3a010b MR |
5222 | /* Second word. */ |
5223 | regval = extract_unsigned_integer (val + 4, 4, byte_order); | |
46cac009 AC |
5224 | if (mips_debug) |
5225 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
6a3a010b MR |
5226 | float_argreg - freg_offset, |
5227 | phex (regval, 4)); | |
025bb325 | 5228 | regcache_cooked_write_unsigned (regcache, |
6a3a010b MR |
5229 | float_argreg++ - freg_offset, |
5230 | regval); | |
46cac009 AC |
5231 | if (mips_debug) |
5232 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5233 | argreg, phex (regval, 4)); | |
9c9acae0 | 5234 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
5235 | } |
5236 | else | |
5237 | { | |
5238 | /* This is a floating point value that fits entirely | |
5239 | in a single register. */ | |
5240 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 5241 | above to ensure that it is even register aligned. */ |
e17a4113 | 5242 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
46cac009 AC |
5243 | if (mips_debug) |
5244 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5245 | float_argreg, phex (regval, len)); | |
025bb325 MS |
5246 | regcache_cooked_write_unsigned (regcache, |
5247 | float_argreg++, regval); | |
5b68030f JM |
5248 | /* Although two FP registers are reserved for each |
5249 | argument, only one corresponding integer register is | |
5250 | reserved. */ | |
46cac009 AC |
5251 | if (mips_debug) |
5252 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5253 | argreg, phex (regval, len)); | |
5b68030f | 5254 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
5255 | } |
5256 | /* Reserve space for the FP register. */ | |
1a69e1e4 | 5257 | stack_offset += align_up (len, MIPS32_REGSIZE); |
46cac009 AC |
5258 | } |
5259 | else | |
5260 | { | |
5261 | /* Copy the argument to general registers or the stack in | |
5262 | register-sized pieces. Large arguments are split between | |
5263 | registers and stack. */ | |
1a69e1e4 DJ |
5264 | /* Note: structs whose size is not a multiple of MIPS32_REGSIZE |
5265 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
5266 | them in registers where gcc sometimes puts them on the |
5267 | stack. For maximum compatibility, we will put them in | |
5268 | both places. */ | |
1a69e1e4 DJ |
5269 | int odd_sized_struct = (len > MIPS32_REGSIZE |
5270 | && len % MIPS32_REGSIZE != 0); | |
46cac009 AC |
5271 | /* Structures should be aligned to eight bytes (even arg registers) |
5272 | on MIPS_ABI_O32, if their first member has double precision. */ | |
2afd3f0a | 5273 | if (mips_type_needs_double_align (arg_type)) |
46cac009 AC |
5274 | { |
5275 | if ((argreg & 1)) | |
968b5391 MR |
5276 | { |
5277 | argreg++; | |
1a69e1e4 | 5278 | stack_offset += MIPS32_REGSIZE; |
968b5391 | 5279 | } |
46cac009 | 5280 | } |
46cac009 AC |
5281 | while (len > 0) |
5282 | { | |
5283 | /* Remember if the argument was written to the stack. */ | |
5284 | int stack_used_p = 0; | |
1a69e1e4 | 5285 | int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); |
46cac009 AC |
5286 | |
5287 | if (mips_debug) | |
5288 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
5289 | partial_len); | |
5290 | ||
5291 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 5292 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 5293 | || odd_sized_struct) |
46cac009 AC |
5294 | { |
5295 | /* Should shorter than int integer values be | |
025bb325 | 5296 | promoted to int before being stored? */ |
46cac009 AC |
5297 | int longword_offset = 0; |
5298 | CORE_ADDR addr; | |
5299 | stack_used_p = 1; | |
46cac009 AC |
5300 | |
5301 | if (mips_debug) | |
5302 | { | |
5af949e3 UW |
5303 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
5304 | paddress (gdbarch, stack_offset)); | |
5305 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
5306 | paddress (gdbarch, longword_offset)); | |
46cac009 AC |
5307 | } |
5308 | ||
5309 | addr = sp + stack_offset + longword_offset; | |
5310 | ||
5311 | if (mips_debug) | |
5312 | { | |
5313 | int i; | |
5af949e3 UW |
5314 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
5315 | paddress (gdbarch, addr)); | |
46cac009 AC |
5316 | for (i = 0; i < partial_len; i++) |
5317 | { | |
6d82d43b | 5318 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
5319 | val[i] & 0xff); |
5320 | } | |
5321 | } | |
5322 | write_memory (addr, val, partial_len); | |
5323 | } | |
5324 | ||
5325 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 5326 | structs may go thru BOTH paths. */ |
46cac009 | 5327 | /* Write this portion of the argument to a general |
6d82d43b | 5328 | purpose register. */ |
74ed0bb4 | 5329 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
46cac009 | 5330 | { |
e17a4113 UW |
5331 | LONGEST regval = extract_signed_integer (val, partial_len, |
5332 | byte_order); | |
4246e332 | 5333 | /* Value may need to be sign extended, because |
1b13c4f6 | 5334 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
5335 | |
5336 | /* A non-floating-point argument being passed in a | |
5337 | general register. If a struct or union, and if | |
5338 | the remaining length is smaller than the register | |
5339 | size, we have to adjust the register value on | |
5340 | big endian targets. | |
5341 | ||
5342 | It does not seem to be necessary to do the | |
5343 | same for integral types. | |
5344 | ||
5345 | Also don't do this adjustment on O64 binaries. | |
5346 | ||
5347 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
5348 | outputting LE O32 with sizeof (struct) < | |
e914cb17 MR |
5349 | mips_abi_regsize(), generates a left shift |
5350 | as part of storing the argument in a register | |
5351 | (the left shift isn't generated when | |
1b13c4f6 | 5352 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
5353 | it is quite possible that this is GCC |
5354 | contradicting the LE/O32 ABI, GDB has not been | |
5355 | adjusted to accommodate this. Either someone | |
5356 | needs to demonstrate that the LE/O32 ABI | |
5357 | specifies such a left shift OR this new ABI gets | |
5358 | identified as such and GDB gets tweaked | |
5359 | accordingly. */ | |
5360 | ||
72a155b4 | 5361 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 5362 | && partial_len < MIPS32_REGSIZE |
06f9a1af MR |
5363 | && (typecode == TYPE_CODE_STRUCT |
5364 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 5365 | regval <<= ((MIPS32_REGSIZE - partial_len) |
9ecf7166 | 5366 | * TARGET_CHAR_BIT); |
46cac009 AC |
5367 | |
5368 | if (mips_debug) | |
5369 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
5370 | argreg, | |
1a69e1e4 | 5371 | phex (regval, MIPS32_REGSIZE)); |
9c9acae0 | 5372 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
46cac009 AC |
5373 | argreg++; |
5374 | ||
5375 | /* Prevent subsequent floating point arguments from | |
5376 | being passed in floating point registers. */ | |
74ed0bb4 | 5377 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
46cac009 AC |
5378 | } |
5379 | ||
5380 | len -= partial_len; | |
5381 | val += partial_len; | |
5382 | ||
b021a221 MS |
5383 | /* Compute the offset into the stack at which we will |
5384 | copy the next parameter. | |
46cac009 | 5385 | |
6d82d43b AC |
5386 | In older ABIs, the caller reserved space for |
5387 | registers that contained arguments. This was loosely | |
5388 | refered to as their "home". Consequently, space is | |
5389 | always allocated. */ | |
46cac009 | 5390 | |
1a69e1e4 | 5391 | stack_offset += align_up (partial_len, MIPS32_REGSIZE); |
46cac009 AC |
5392 | } |
5393 | } | |
5394 | if (mips_debug) | |
5395 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
5396 | } | |
5397 | ||
f10683bb | 5398 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 5399 | |
46cac009 AC |
5400 | /* Return adjusted stack pointer. */ |
5401 | return sp; | |
5402 | } | |
5403 | ||
6d82d43b | 5404 | static enum return_value_convention |
6a3a010b | 5405 | mips_o32_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 | 5406 | struct type *type, struct regcache *regcache, |
47a35522 | 5407 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 5408 | { |
6a3a010b | 5409 | CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0; |
4cc0665f | 5410 | int mips16 = mips_pc_is_mips16 (gdbarch, func_addr); |
72a155b4 | 5411 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
6a3a010b | 5412 | enum mips_fval_reg fval_reg; |
6d82d43b | 5413 | |
6a3a010b | 5414 | fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both; |
6d82d43b AC |
5415 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
5416 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
5417 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
5418 | return RETURN_VALUE_STRUCT_CONVENTION; | |
5419 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
5420 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5421 | { | |
6a3a010b MR |
5422 | /* A single-precision floating-point value. If reading in or copying, |
5423 | then we get it from/put it to FP0 for standard MIPS code or GPR2 | |
5424 | for MIPS16 code. If writing out only, then we put it to both FP0 | |
5425 | and GPR2. We do not support reading in with no function known, if | |
5426 | this safety check ever triggers, then we'll have to try harder. */ | |
5427 | gdb_assert (function || !readbuf); | |
6d82d43b | 5428 | if (mips_debug) |
6a3a010b MR |
5429 | switch (fval_reg) |
5430 | { | |
5431 | case mips_fval_fpr: | |
5432 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
5433 | break; | |
5434 | case mips_fval_gpr: | |
5435 | fprintf_unfiltered (gdb_stderr, "Return float in $2\n"); | |
5436 | break; | |
5437 | case mips_fval_both: | |
5438 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n"); | |
5439 | break; | |
5440 | } | |
5441 | if (fval_reg != mips_fval_gpr) | |
5442 | mips_xfer_register (gdbarch, regcache, | |
5443 | (gdbarch_num_regs (gdbarch) | |
5444 | + mips_regnum (gdbarch)->fp0), | |
5445 | TYPE_LENGTH (type), | |
5446 | gdbarch_byte_order (gdbarch), | |
5447 | readbuf, writebuf, 0); | |
5448 | if (fval_reg != mips_fval_fpr) | |
5449 | mips_xfer_register (gdbarch, regcache, | |
5450 | gdbarch_num_regs (gdbarch) + 2, | |
5451 | TYPE_LENGTH (type), | |
5452 | gdbarch_byte_order (gdbarch), | |
5453 | readbuf, writebuf, 0); | |
6d82d43b AC |
5454 | return RETURN_VALUE_REGISTER_CONVENTION; |
5455 | } | |
5456 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
5457 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5458 | { | |
6a3a010b MR |
5459 | /* A double-precision floating-point value. If reading in or copying, |
5460 | then we get it from/put it to FP1 and FP0 for standard MIPS code or | |
5461 | GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it | |
5462 | to both FP1/FP0 and GPR2/GPR3. We do not support reading in with | |
5463 | no function known, if this safety check ever triggers, then we'll | |
5464 | have to try harder. */ | |
5465 | gdb_assert (function || !readbuf); | |
6d82d43b | 5466 | if (mips_debug) |
6a3a010b MR |
5467 | switch (fval_reg) |
5468 | { | |
5469 | case mips_fval_fpr: | |
5470 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
5471 | break; | |
5472 | case mips_fval_gpr: | |
5473 | fprintf_unfiltered (gdb_stderr, "Return float in $2/$3\n"); | |
5474 | break; | |
5475 | case mips_fval_both: | |
5476 | fprintf_unfiltered (gdb_stderr, | |
5477 | "Return float in $fp1/$fp0 and $2/$3\n"); | |
5478 | break; | |
5479 | } | |
5480 | if (fval_reg != mips_fval_gpr) | |
6d82d43b | 5481 | { |
6a3a010b MR |
5482 | /* The most significant part goes in FP1, and the least significant |
5483 | in FP0. */ | |
5484 | switch (gdbarch_byte_order (gdbarch)) | |
5485 | { | |
5486 | case BFD_ENDIAN_LITTLE: | |
5487 | mips_xfer_register (gdbarch, regcache, | |
5488 | (gdbarch_num_regs (gdbarch) | |
5489 | + mips_regnum (gdbarch)->fp0 + 0), | |
5490 | 4, gdbarch_byte_order (gdbarch), | |
5491 | readbuf, writebuf, 0); | |
5492 | mips_xfer_register (gdbarch, regcache, | |
5493 | (gdbarch_num_regs (gdbarch) | |
5494 | + mips_regnum (gdbarch)->fp0 + 1), | |
5495 | 4, gdbarch_byte_order (gdbarch), | |
5496 | readbuf, writebuf, 4); | |
5497 | break; | |
5498 | case BFD_ENDIAN_BIG: | |
5499 | mips_xfer_register (gdbarch, regcache, | |
5500 | (gdbarch_num_regs (gdbarch) | |
5501 | + mips_regnum (gdbarch)->fp0 + 1), | |
5502 | 4, gdbarch_byte_order (gdbarch), | |
5503 | readbuf, writebuf, 0); | |
5504 | mips_xfer_register (gdbarch, regcache, | |
5505 | (gdbarch_num_regs (gdbarch) | |
5506 | + mips_regnum (gdbarch)->fp0 + 0), | |
5507 | 4, gdbarch_byte_order (gdbarch), | |
5508 | readbuf, writebuf, 4); | |
5509 | break; | |
5510 | default: | |
5511 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
5512 | } | |
5513 | } | |
5514 | if (fval_reg != mips_fval_fpr) | |
5515 | { | |
5516 | /* The two 32-bit parts are always placed in GPR2 and GPR3 | |
5517 | following these registers' memory order. */ | |
ba32f989 | 5518 | mips_xfer_register (gdbarch, regcache, |
6a3a010b | 5519 | gdbarch_num_regs (gdbarch) + 2, |
72a155b4 | 5520 | 4, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5521 | readbuf, writebuf, 0); |
ba32f989 | 5522 | mips_xfer_register (gdbarch, regcache, |
6a3a010b | 5523 | gdbarch_num_regs (gdbarch) + 3, |
72a155b4 | 5524 | 4, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5525 | readbuf, writebuf, 4); |
6d82d43b AC |
5526 | } |
5527 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5528 | } | |
5529 | #if 0 | |
5530 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
5531 | && TYPE_NFIELDS (type) <= 2 | |
5532 | && TYPE_NFIELDS (type) >= 1 | |
5533 | && ((TYPE_NFIELDS (type) == 1 | |
5534 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
5535 | == TYPE_CODE_FLT)) | |
5536 | || (TYPE_NFIELDS (type) == 2 | |
5537 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
5538 | == TYPE_CODE_FLT) | |
5539 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
5540 | == TYPE_CODE_FLT))) | |
5541 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5542 | { | |
5543 | /* A struct that contains one or two floats. Each value is part | |
5544 | in the least significant part of their floating point | |
5545 | register.. */ | |
870cd05e | 5546 | gdb_byte reg[MAX_REGISTER_SIZE]; |
6d82d43b AC |
5547 | int regnum; |
5548 | int field; | |
72a155b4 | 5549 | for (field = 0, regnum = mips_regnum (gdbarch)->fp0; |
6d82d43b AC |
5550 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
5551 | { | |
5552 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
5553 | / TARGET_CHAR_BIT); | |
5554 | if (mips_debug) | |
5555 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
5556 | offset); | |
ba32f989 DJ |
5557 | mips_xfer_register (gdbarch, regcache, |
5558 | gdbarch_num_regs (gdbarch) + regnum, | |
6d82d43b | 5559 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
72a155b4 | 5560 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 5561 | readbuf, writebuf, offset); |
6d82d43b AC |
5562 | } |
5563 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5564 | } | |
5565 | #endif | |
5566 | #if 0 | |
5567 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
5568 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
5569 | { | |
5570 | /* A structure or union. Extract the left justified value, | |
5571 | regardless of the byte order. I.e. DO NOT USE | |
5572 | mips_xfer_lower. */ | |
5573 | int offset; | |
5574 | int regnum; | |
4c7d22cb | 5575 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 5576 | offset < TYPE_LENGTH (type); |
72a155b4 | 5577 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 5578 | { |
72a155b4 | 5579 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
5580 | if (offset + xfer > TYPE_LENGTH (type)) |
5581 | xfer = TYPE_LENGTH (type) - offset; | |
5582 | if (mips_debug) | |
5583 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
5584 | offset, xfer, regnum); | |
ba32f989 DJ |
5585 | mips_xfer_register (gdbarch, regcache, |
5586 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
6d82d43b AC |
5587 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
5588 | } | |
5589 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5590 | } | |
5591 | #endif | |
5592 | else | |
5593 | { | |
5594 | /* A scalar extract each part but least-significant-byte | |
5595 | justified. o32 thinks registers are 4 byte, regardless of | |
1a69e1e4 | 5596 | the ISA. */ |
6d82d43b AC |
5597 | int offset; |
5598 | int regnum; | |
4c7d22cb | 5599 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 5600 | offset < TYPE_LENGTH (type); |
1a69e1e4 | 5601 | offset += MIPS32_REGSIZE, regnum++) |
6d82d43b | 5602 | { |
1a69e1e4 | 5603 | int xfer = MIPS32_REGSIZE; |
6d82d43b AC |
5604 | if (offset + xfer > TYPE_LENGTH (type)) |
5605 | xfer = TYPE_LENGTH (type) - offset; | |
5606 | if (mips_debug) | |
5607 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
5608 | offset, xfer, regnum); | |
ba32f989 DJ |
5609 | mips_xfer_register (gdbarch, regcache, |
5610 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
72a155b4 | 5611 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 5612 | readbuf, writebuf, offset); |
6d82d43b AC |
5613 | } |
5614 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5615 | } | |
5616 | } | |
5617 | ||
5618 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
5619 | ABI. */ | |
46cac009 AC |
5620 | |
5621 | static CORE_ADDR | |
7d9b040b | 5622 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
5623 | struct regcache *regcache, CORE_ADDR bp_addr, |
5624 | int nargs, | |
5625 | struct value **args, CORE_ADDR sp, | |
5626 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
5627 | { |
5628 | int argreg; | |
5629 | int float_argreg; | |
5630 | int argnum; | |
5631 | int len = 0; | |
5632 | int stack_offset = 0; | |
e17a4113 | 5633 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 5634 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 5635 | |
25ab4790 AC |
5636 | /* For shared libraries, "t9" needs to point at the function |
5637 | address. */ | |
4c7d22cb | 5638 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
5639 | |
5640 | /* Set the return address register to point to the entry point of | |
5641 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 5642 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 5643 | |
46cac009 AC |
5644 | /* First ensure that the stack and structure return address (if any) |
5645 | are properly aligned. The stack has to be at least 64-bit | |
5646 | aligned even on 32-bit machines, because doubles must be 64-bit | |
5647 | aligned. For n32 and n64, stack frames need to be 128-bit | |
5648 | aligned, so we round to this widest known alignment. */ | |
5649 | ||
5b03f266 AC |
5650 | sp = align_down (sp, 16); |
5651 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
5652 | |
5653 | /* Now make space on the stack for the args. */ | |
5654 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
5655 | { |
5656 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
5657 | int arglen = TYPE_LENGTH (arg_type); | |
5658 | ||
968b5391 | 5659 | /* Allocate space on the stack. */ |
1a69e1e4 | 5660 | len += align_up (arglen, MIPS64_REGSIZE); |
968b5391 | 5661 | } |
5b03f266 | 5662 | sp -= align_up (len, 16); |
46cac009 AC |
5663 | |
5664 | if (mips_debug) | |
6d82d43b | 5665 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
5666 | "mips_o64_push_dummy_call: sp=%s allocated %ld\n", |
5667 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
46cac009 AC |
5668 | |
5669 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 5670 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 5671 | float_argreg = mips_fpa0_regnum (gdbarch); |
46cac009 AC |
5672 | |
5673 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
5674 | if (struct_return) | |
5675 | { | |
5676 | if (mips_debug) | |
5677 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
5678 | "mips_o64_push_dummy_call: " |
5679 | "struct_return reg=%d %s\n", | |
5af949e3 | 5680 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 5681 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 5682 | stack_offset += MIPS64_REGSIZE; |
46cac009 AC |
5683 | } |
5684 | ||
5685 | /* Now load as many as possible of the first arguments into | |
5686 | registers, and push the rest onto the stack. Loop thru args | |
5687 | from first to last. */ | |
5688 | for (argnum = 0; argnum < nargs; argnum++) | |
5689 | { | |
47a35522 | 5690 | const gdb_byte *val; |
930bd0e0 | 5691 | gdb_byte valbuf[MAX_REGISTER_SIZE]; |
46cac009 | 5692 | struct value *arg = args[argnum]; |
4991999e | 5693 | struct type *arg_type = check_typedef (value_type (arg)); |
46cac009 AC |
5694 | int len = TYPE_LENGTH (arg_type); |
5695 | enum type_code typecode = TYPE_CODE (arg_type); | |
5696 | ||
5697 | if (mips_debug) | |
5698 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 5699 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
5700 | argnum + 1, len, (int) typecode); |
5701 | ||
47a35522 | 5702 | val = value_contents (arg); |
ebafbe83 | 5703 | |
930bd0e0 KB |
5704 | /* Function pointer arguments to mips16 code need to be made into |
5705 | mips16 pointers. */ | |
5706 | if (typecode == TYPE_CODE_PTR | |
5707 | && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC) | |
5708 | { | |
5709 | CORE_ADDR addr = extract_signed_integer (value_contents (arg), | |
5710 | len, byte_order); | |
4cc0665f | 5711 | if (!mips_pc_is_mips (addr)) |
930bd0e0 KB |
5712 | { |
5713 | store_signed_integer (valbuf, len, byte_order, | |
4cc0665f | 5714 | make_compact_addr (addr)); |
930bd0e0 KB |
5715 | val = valbuf; |
5716 | } | |
5717 | } | |
5718 | ||
ebafbe83 | 5719 | /* Floating point arguments passed in registers have to be |
6a3a010b MR |
5720 | treated specially. On 32-bit architectures, doubles are |
5721 | passed in register pairs; the even FP register gets the | |
5722 | low word, and the odd FP register gets the high word. | |
5723 | On O64, the first two floating point arguments are also | |
5724 | copied to general registers, because MIPS16 functions | |
5725 | don't use float registers for arguments. This duplication | |
5726 | of arguments in general registers can't hurt non-MIPS16 | |
5727 | functions because those registers are normally skipped. */ | |
ebafbe83 | 5728 | |
74ed0bb4 MD |
5729 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
5730 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
ebafbe83 | 5731 | { |
e17a4113 | 5732 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
2afd3f0a MR |
5733 | if (mips_debug) |
5734 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5735 | float_argreg, phex (regval, len)); | |
9c9acae0 | 5736 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
2afd3f0a MR |
5737 | if (mips_debug) |
5738 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5739 | argreg, phex (regval, len)); | |
9c9acae0 | 5740 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
2afd3f0a | 5741 | argreg++; |
ebafbe83 | 5742 | /* Reserve space for the FP register. */ |
1a69e1e4 | 5743 | stack_offset += align_up (len, MIPS64_REGSIZE); |
ebafbe83 MS |
5744 | } |
5745 | else | |
5746 | { | |
5747 | /* Copy the argument to general registers or the stack in | |
5748 | register-sized pieces. Large arguments are split between | |
5749 | registers and stack. */ | |
1a69e1e4 | 5750 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
5751 | are treated specially: Irix cc passes them in registers |
5752 | where gcc sometimes puts them on the stack. For maximum | |
5753 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
5754 | int odd_sized_struct = (len > MIPS64_REGSIZE |
5755 | && len % MIPS64_REGSIZE != 0); | |
ebafbe83 MS |
5756 | while (len > 0) |
5757 | { | |
5758 | /* Remember if the argument was written to the stack. */ | |
5759 | int stack_used_p = 0; | |
1a69e1e4 | 5760 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
ebafbe83 MS |
5761 | |
5762 | if (mips_debug) | |
5763 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
5764 | partial_len); | |
5765 | ||
5766 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 5767 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 5768 | || odd_sized_struct) |
ebafbe83 MS |
5769 | { |
5770 | /* Should shorter than int integer values be | |
025bb325 | 5771 | promoted to int before being stored? */ |
ebafbe83 MS |
5772 | int longword_offset = 0; |
5773 | CORE_ADDR addr; | |
5774 | stack_used_p = 1; | |
72a155b4 | 5775 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ebafbe83 | 5776 | { |
1a69e1e4 DJ |
5777 | if ((typecode == TYPE_CODE_INT |
5778 | || typecode == TYPE_CODE_PTR | |
5779 | || typecode == TYPE_CODE_FLT) | |
5780 | && len <= 4) | |
5781 | longword_offset = MIPS64_REGSIZE - len; | |
ebafbe83 MS |
5782 | } |
5783 | ||
5784 | if (mips_debug) | |
5785 | { | |
5af949e3 UW |
5786 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
5787 | paddress (gdbarch, stack_offset)); | |
5788 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
5789 | paddress (gdbarch, longword_offset)); | |
ebafbe83 MS |
5790 | } |
5791 | ||
5792 | addr = sp + stack_offset + longword_offset; | |
5793 | ||
5794 | if (mips_debug) | |
5795 | { | |
5796 | int i; | |
5af949e3 UW |
5797 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
5798 | paddress (gdbarch, addr)); | |
ebafbe83 MS |
5799 | for (i = 0; i < partial_len; i++) |
5800 | { | |
6d82d43b | 5801 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
5802 | val[i] & 0xff); |
5803 | } | |
5804 | } | |
5805 | write_memory (addr, val, partial_len); | |
5806 | } | |
5807 | ||
5808 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 5809 | structs may go thru BOTH paths. */ |
ebafbe83 | 5810 | /* Write this portion of the argument to a general |
6d82d43b | 5811 | purpose register. */ |
74ed0bb4 | 5812 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
ebafbe83 | 5813 | { |
e17a4113 UW |
5814 | LONGEST regval = extract_signed_integer (val, partial_len, |
5815 | byte_order); | |
4246e332 | 5816 | /* Value may need to be sign extended, because |
1b13c4f6 | 5817 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
5818 | |
5819 | /* A non-floating-point argument being passed in a | |
5820 | general register. If a struct or union, and if | |
5821 | the remaining length is smaller than the register | |
5822 | size, we have to adjust the register value on | |
5823 | big endian targets. | |
5824 | ||
5825 | It does not seem to be necessary to do the | |
025bb325 | 5826 | same for integral types. */ |
480d3dd2 | 5827 | |
72a155b4 | 5828 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 5829 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
5830 | && (typecode == TYPE_CODE_STRUCT |
5831 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 5832 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 5833 | * TARGET_CHAR_BIT); |
ebafbe83 MS |
5834 | |
5835 | if (mips_debug) | |
5836 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
5837 | argreg, | |
1a69e1e4 | 5838 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 5839 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
ebafbe83 MS |
5840 | argreg++; |
5841 | ||
5842 | /* Prevent subsequent floating point arguments from | |
5843 | being passed in floating point registers. */ | |
74ed0bb4 | 5844 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
ebafbe83 MS |
5845 | } |
5846 | ||
5847 | len -= partial_len; | |
5848 | val += partial_len; | |
5849 | ||
b021a221 MS |
5850 | /* Compute the offset into the stack at which we will |
5851 | copy the next parameter. | |
ebafbe83 | 5852 | |
6d82d43b AC |
5853 | In older ABIs, the caller reserved space for |
5854 | registers that contained arguments. This was loosely | |
5855 | refered to as their "home". Consequently, space is | |
5856 | always allocated. */ | |
ebafbe83 | 5857 | |
1a69e1e4 | 5858 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
ebafbe83 MS |
5859 | } |
5860 | } | |
5861 | if (mips_debug) | |
5862 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
5863 | } | |
5864 | ||
f10683bb | 5865 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 5866 | |
ebafbe83 MS |
5867 | /* Return adjusted stack pointer. */ |
5868 | return sp; | |
5869 | } | |
5870 | ||
9c8fdbfa | 5871 | static enum return_value_convention |
6a3a010b | 5872 | mips_o64_return_value (struct gdbarch *gdbarch, struct value *function, |
9c8fdbfa | 5873 | struct type *type, struct regcache *regcache, |
47a35522 | 5874 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 5875 | { |
6a3a010b | 5876 | CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0; |
4cc0665f | 5877 | int mips16 = mips_pc_is_mips16 (gdbarch, func_addr); |
72a155b4 | 5878 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
6a3a010b | 5879 | enum mips_fval_reg fval_reg; |
7a076fd2 | 5880 | |
6a3a010b | 5881 | fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both; |
7a076fd2 FF |
5882 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
5883 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
5884 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
5885 | return RETURN_VALUE_STRUCT_CONVENTION; | |
74ed0bb4 | 5886 | else if (fp_register_arg_p (gdbarch, TYPE_CODE (type), type)) |
7a076fd2 | 5887 | { |
6a3a010b MR |
5888 | /* A floating-point value. If reading in or copying, then we get it |
5889 | from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code. | |
5890 | If writing out only, then we put it to both FP0 and GPR2. We do | |
5891 | not support reading in with no function known, if this safety | |
5892 | check ever triggers, then we'll have to try harder. */ | |
5893 | gdb_assert (function || !readbuf); | |
7a076fd2 | 5894 | if (mips_debug) |
6a3a010b MR |
5895 | switch (fval_reg) |
5896 | { | |
5897 | case mips_fval_fpr: | |
5898 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
5899 | break; | |
5900 | case mips_fval_gpr: | |
5901 | fprintf_unfiltered (gdb_stderr, "Return float in $2\n"); | |
5902 | break; | |
5903 | case mips_fval_both: | |
5904 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n"); | |
5905 | break; | |
5906 | } | |
5907 | if (fval_reg != mips_fval_gpr) | |
5908 | mips_xfer_register (gdbarch, regcache, | |
5909 | (gdbarch_num_regs (gdbarch) | |
5910 | + mips_regnum (gdbarch)->fp0), | |
5911 | TYPE_LENGTH (type), | |
5912 | gdbarch_byte_order (gdbarch), | |
5913 | readbuf, writebuf, 0); | |
5914 | if (fval_reg != mips_fval_fpr) | |
5915 | mips_xfer_register (gdbarch, regcache, | |
5916 | gdbarch_num_regs (gdbarch) + 2, | |
5917 | TYPE_LENGTH (type), | |
5918 | gdbarch_byte_order (gdbarch), | |
5919 | readbuf, writebuf, 0); | |
7a076fd2 FF |
5920 | return RETURN_VALUE_REGISTER_CONVENTION; |
5921 | } | |
5922 | else | |
5923 | { | |
5924 | /* A scalar extract each part but least-significant-byte | |
025bb325 | 5925 | justified. */ |
7a076fd2 FF |
5926 | int offset; |
5927 | int regnum; | |
5928 | for (offset = 0, regnum = MIPS_V0_REGNUM; | |
5929 | offset < TYPE_LENGTH (type); | |
1a69e1e4 | 5930 | offset += MIPS64_REGSIZE, regnum++) |
7a076fd2 | 5931 | { |
1a69e1e4 | 5932 | int xfer = MIPS64_REGSIZE; |
7a076fd2 FF |
5933 | if (offset + xfer > TYPE_LENGTH (type)) |
5934 | xfer = TYPE_LENGTH (type) - offset; | |
5935 | if (mips_debug) | |
5936 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
5937 | offset, xfer, regnum); | |
ba32f989 DJ |
5938 | mips_xfer_register (gdbarch, regcache, |
5939 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 5940 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5941 | readbuf, writebuf, offset); |
7a076fd2 FF |
5942 | } |
5943 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5944 | } | |
6d82d43b AC |
5945 | } |
5946 | ||
dd824b04 DJ |
5947 | /* Floating point register management. |
5948 | ||
5949 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
5950 | 64bit operations, these early MIPS cpus treat fp register pairs | |
5951 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
5952 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
5953 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
5954 | double precision floats into two 32-bit chunks and store them in | |
5955 | consecutive fp regs. To display 64-bit floats stored in this | |
5956 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
5957 | Throw in user-configurable endianness and you have a real mess. | |
5958 | ||
5959 | The way this works is: | |
5960 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
5961 | double-precision value will be split across two logical registers. | |
5962 | The lower-numbered logical register will hold the low-order bits, | |
5963 | regardless of the processor's endianness. | |
5964 | - If we are on a 64-bit processor, and we are looking for a | |
5965 | single-precision value, it will be in the low ordered bits | |
5966 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
5967 | save slot in memory. | |
5968 | - If we are in 64-bit mode, everything is straightforward. | |
5969 | ||
5970 | Note that this code only deals with "live" registers at the top of the | |
5971 | stack. We will attempt to deal with saved registers later, when | |
025bb325 | 5972 | the raw/cooked register interface is in place. (We need a general |
dd824b04 DJ |
5973 | interface that can deal with dynamic saved register sizes -- fp |
5974 | regs could be 32 bits wide in one frame and 64 on the frame above | |
5975 | and below). */ | |
5976 | ||
5977 | /* Copy a 32-bit single-precision value from the current frame | |
5978 | into rare_buffer. */ | |
5979 | ||
5980 | static void | |
e11c53d2 | 5981 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
47a35522 | 5982 | gdb_byte *rare_buffer) |
dd824b04 | 5983 | { |
72a155b4 UW |
5984 | struct gdbarch *gdbarch = get_frame_arch (frame); |
5985 | int raw_size = register_size (gdbarch, regno); | |
47a35522 | 5986 | gdb_byte *raw_buffer = alloca (raw_size); |
dd824b04 | 5987 | |
e11c53d2 | 5988 | if (!frame_register_read (frame, regno, raw_buffer)) |
c9f4d572 | 5989 | error (_("can't read register %d (%s)"), |
72a155b4 | 5990 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
5991 | if (raw_size == 8) |
5992 | { | |
5993 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 5994 | 32 bits. */ |
dd824b04 DJ |
5995 | int offset; |
5996 | ||
72a155b4 | 5997 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 DJ |
5998 | offset = 4; |
5999 | else | |
6000 | offset = 0; | |
6001 | ||
6002 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
6003 | } | |
6004 | else | |
6005 | { | |
6006 | memcpy (rare_buffer, raw_buffer, 4); | |
6007 | } | |
6008 | } | |
6009 | ||
6010 | /* Copy a 64-bit double-precision value from the current frame into | |
6011 | rare_buffer. This may include getting half of it from the next | |
6012 | register. */ | |
6013 | ||
6014 | static void | |
e11c53d2 | 6015 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
47a35522 | 6016 | gdb_byte *rare_buffer) |
dd824b04 | 6017 | { |
72a155b4 UW |
6018 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6019 | int raw_size = register_size (gdbarch, regno); | |
dd824b04 | 6020 | |
9c9acae0 | 6021 | if (raw_size == 8 && !mips2_fp_compat (frame)) |
dd824b04 DJ |
6022 | { |
6023 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 6024 | all 64 bits. */ |
e11c53d2 | 6025 | if (!frame_register_read (frame, regno, rare_buffer)) |
c9f4d572 | 6026 | error (_("can't read register %d (%s)"), |
72a155b4 | 6027 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
6028 | } |
6029 | else | |
6030 | { | |
72a155b4 | 6031 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
82e91389 | 6032 | |
72a155b4 | 6033 | if ((rawnum - mips_regnum (gdbarch)->fp0) & 1) |
dd824b04 | 6034 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
6035 | _("mips_read_fp_register_double: bad access to " |
6036 | "odd-numbered FP register")); | |
dd824b04 DJ |
6037 | |
6038 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 6039 | each register. */ |
72a155b4 | 6040 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 | 6041 | { |
e11c53d2 AC |
6042 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
6043 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 6044 | } |
361d1df0 | 6045 | else |
dd824b04 | 6046 | { |
e11c53d2 AC |
6047 | mips_read_fp_register_single (frame, regno, rare_buffer); |
6048 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
6049 | } |
6050 | } | |
6051 | } | |
6052 | ||
c906108c | 6053 | static void |
e11c53d2 AC |
6054 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
6055 | int regnum) | |
025bb325 | 6056 | { /* Do values for FP (float) regs. */ |
72a155b4 | 6057 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 6058 | gdb_byte *raw_buffer; |
025bb325 | 6059 | double doub, flt1; /* Doubles extracted from raw hex data. */ |
3903d437 | 6060 | int inv1, inv2; |
c5aa993b | 6061 | |
025bb325 MS |
6062 | raw_buffer = alloca (2 * register_size (gdbarch, |
6063 | mips_regnum (gdbarch)->fp0)); | |
c906108c | 6064 | |
72a155b4 | 6065 | fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum)); |
c9f4d572 | 6066 | fprintf_filtered (file, "%*s", |
72a155b4 | 6067 | 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)), |
e11c53d2 | 6068 | ""); |
f0ef6b29 | 6069 | |
72a155b4 | 6070 | if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame)) |
c906108c | 6071 | { |
79a45b7d TT |
6072 | struct value_print_options opts; |
6073 | ||
f0ef6b29 KB |
6074 | /* 4-byte registers: Print hex and floating. Also print even |
6075 | numbered registers as doubles. */ | |
e11c53d2 | 6076 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
025bb325 MS |
6077 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, |
6078 | raw_buffer, &inv1); | |
c5aa993b | 6079 | |
79a45b7d | 6080 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
6081 | print_scalar_formatted (raw_buffer, |
6082 | builtin_type (gdbarch)->builtin_uint32, | |
6083 | &opts, 'w', file); | |
dd824b04 | 6084 | |
e11c53d2 | 6085 | fprintf_filtered (file, " flt: "); |
1adad886 | 6086 | if (inv1) |
e11c53d2 | 6087 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 6088 | else |
e11c53d2 | 6089 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 6090 | |
72a155b4 | 6091 | if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0) |
f0ef6b29 | 6092 | { |
e11c53d2 | 6093 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
27067745 UW |
6094 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
6095 | raw_buffer, &inv2); | |
1adad886 | 6096 | |
e11c53d2 | 6097 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 6098 | if (inv2) |
e11c53d2 | 6099 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 6100 | else |
e11c53d2 | 6101 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 6102 | } |
c906108c SS |
6103 | } |
6104 | else | |
dd824b04 | 6105 | { |
79a45b7d TT |
6106 | struct value_print_options opts; |
6107 | ||
f0ef6b29 | 6108 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 6109 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
27067745 UW |
6110 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, |
6111 | raw_buffer, &inv1); | |
c906108c | 6112 | |
e11c53d2 | 6113 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
27067745 UW |
6114 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
6115 | raw_buffer, &inv2); | |
f0ef6b29 | 6116 | |
79a45b7d | 6117 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
6118 | print_scalar_formatted (raw_buffer, |
6119 | builtin_type (gdbarch)->builtin_uint64, | |
6120 | &opts, 'g', file); | |
f0ef6b29 | 6121 | |
e11c53d2 | 6122 | fprintf_filtered (file, " flt: "); |
1adad886 | 6123 | if (inv1) |
e11c53d2 | 6124 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 6125 | else |
e11c53d2 | 6126 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 6127 | |
e11c53d2 | 6128 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 6129 | if (inv2) |
e11c53d2 | 6130 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 6131 | else |
e11c53d2 | 6132 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
6133 | } |
6134 | } | |
6135 | ||
6136 | static void | |
e11c53d2 | 6137 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
0cc93a06 | 6138 | int regnum) |
f0ef6b29 | 6139 | { |
a4b8ebc8 | 6140 | struct gdbarch *gdbarch = get_frame_arch (frame); |
79a45b7d | 6141 | struct value_print_options opts; |
de15c4ab | 6142 | struct value *val; |
1adad886 | 6143 | |
004159a2 | 6144 | if (mips_float_register_p (gdbarch, regnum)) |
f0ef6b29 | 6145 | { |
e11c53d2 | 6146 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
6147 | return; |
6148 | } | |
6149 | ||
de15c4ab PA |
6150 | val = get_frame_register_value (frame, regnum); |
6151 | if (value_optimized_out (val)) | |
f0ef6b29 | 6152 | { |
c9f4d572 | 6153 | fprintf_filtered (file, "%s: [Invalid]", |
72a155b4 | 6154 | gdbarch_register_name (gdbarch, regnum)); |
f0ef6b29 | 6155 | return; |
c906108c | 6156 | } |
f0ef6b29 | 6157 | |
72a155b4 | 6158 | fputs_filtered (gdbarch_register_name (gdbarch, regnum), file); |
f0ef6b29 KB |
6159 | |
6160 | /* The problem with printing numeric register names (r26, etc.) is that | |
6161 | the user can't use them on input. Probably the best solution is to | |
6162 | fix it so that either the numeric or the funky (a2, etc.) names | |
6163 | are accepted on input. */ | |
6164 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 6165 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 6166 | else |
e11c53d2 | 6167 | fprintf_filtered (file, ": "); |
f0ef6b29 | 6168 | |
79a45b7d | 6169 | get_formatted_print_options (&opts, 'x'); |
de15c4ab PA |
6170 | val_print_scalar_formatted (value_type (val), |
6171 | value_contents_for_printing (val), | |
6172 | value_embedded_offset (val), | |
6173 | val, | |
6174 | &opts, 0, file); | |
c906108c SS |
6175 | } |
6176 | ||
f0ef6b29 KB |
6177 | /* Replacement for generic do_registers_info. |
6178 | Print regs in pretty columns. */ | |
6179 | ||
6180 | static int | |
e11c53d2 AC |
6181 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
6182 | int regnum) | |
f0ef6b29 | 6183 | { |
e11c53d2 AC |
6184 | fprintf_filtered (file, " "); |
6185 | mips_print_fp_register (file, frame, regnum); | |
6186 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
6187 | return regnum + 1; |
6188 | } | |
6189 | ||
6190 | ||
025bb325 | 6191 | /* Print a row's worth of GP (int) registers, with name labels above. */ |
c906108c SS |
6192 | |
6193 | static int | |
e11c53d2 | 6194 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 6195 | int start_regnum) |
c906108c | 6196 | { |
a4b8ebc8 | 6197 | struct gdbarch *gdbarch = get_frame_arch (frame); |
025bb325 | 6198 | /* Do values for GP (int) regs. */ |
47a35522 | 6199 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
025bb325 MS |
6200 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols |
6201 | per row. */ | |
c906108c | 6202 | int col, byte; |
a4b8ebc8 | 6203 | int regnum; |
c906108c | 6204 | |
025bb325 | 6205 | /* For GP registers, we print a separate row of names above the vals. */ |
a4b8ebc8 | 6206 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
6207 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
6208 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 6209 | regnum++) |
c906108c | 6210 | { |
72a155b4 | 6211 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 6212 | continue; /* unused register */ |
004159a2 | 6213 | if (mips_float_register_p (gdbarch, regnum)) |
025bb325 | 6214 | break; /* End the row: reached FP register. */ |
0cc93a06 | 6215 | /* Large registers are handled separately. */ |
72a155b4 | 6216 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
6217 | { |
6218 | if (col > 0) | |
6219 | break; /* End the row before this register. */ | |
6220 | ||
6221 | /* Print this register on a row by itself. */ | |
6222 | mips_print_register (file, frame, regnum); | |
6223 | fprintf_filtered (file, "\n"); | |
6224 | return regnum + 1; | |
6225 | } | |
d05f6826 DJ |
6226 | if (col == 0) |
6227 | fprintf_filtered (file, " "); | |
6d82d43b | 6228 | fprintf_filtered (file, |
72a155b4 UW |
6229 | mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s", |
6230 | gdbarch_register_name (gdbarch, regnum)); | |
c906108c SS |
6231 | col++; |
6232 | } | |
d05f6826 DJ |
6233 | |
6234 | if (col == 0) | |
6235 | return regnum; | |
6236 | ||
025bb325 | 6237 | /* Print the R0 to R31 names. */ |
72a155b4 | 6238 | if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS) |
f57d151a | 6239 | fprintf_filtered (file, "\n R%-4d", |
72a155b4 | 6240 | start_regnum % gdbarch_num_regs (gdbarch)); |
20e6603c AC |
6241 | else |
6242 | fprintf_filtered (file, "\n "); | |
c906108c | 6243 | |
025bb325 | 6244 | /* Now print the values in hex, 4 or 8 to the row. */ |
a4b8ebc8 | 6245 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
6246 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
6247 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 6248 | regnum++) |
c906108c | 6249 | { |
72a155b4 | 6250 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 6251 | continue; /* unused register */ |
004159a2 | 6252 | if (mips_float_register_p (gdbarch, regnum)) |
025bb325 | 6253 | break; /* End row: reached FP register. */ |
72a155b4 | 6254 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
6255 | break; /* End row: large register. */ |
6256 | ||
c906108c | 6257 | /* OK: get the data in raw format. */ |
e11c53d2 | 6258 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c9f4d572 | 6259 | error (_("can't read register %d (%s)"), |
72a155b4 | 6260 | regnum, gdbarch_register_name (gdbarch, regnum)); |
c906108c | 6261 | /* pad small registers */ |
4246e332 | 6262 | for (byte = 0; |
72a155b4 UW |
6263 | byte < (mips_abi_regsize (gdbarch) |
6264 | - register_size (gdbarch, regnum)); byte++) | |
c906108c | 6265 | printf_filtered (" "); |
025bb325 | 6266 | /* Now print the register value in hex, endian order. */ |
72a155b4 | 6267 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b | 6268 | for (byte = |
72a155b4 UW |
6269 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
6270 | byte < register_size (gdbarch, regnum); byte++) | |
47a35522 | 6271 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
c906108c | 6272 | else |
72a155b4 | 6273 | for (byte = register_size (gdbarch, regnum) - 1; |
6d82d43b | 6274 | byte >= 0; byte--) |
47a35522 | 6275 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
e11c53d2 | 6276 | fprintf_filtered (file, " "); |
c906108c SS |
6277 | col++; |
6278 | } | |
025bb325 | 6279 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 6280 | fprintf_filtered (file, "\n"); |
c906108c SS |
6281 | |
6282 | return regnum; | |
6283 | } | |
6284 | ||
025bb325 | 6285 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */ |
c906108c | 6286 | |
bf1f5b4c | 6287 | static void |
e11c53d2 AC |
6288 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
6289 | struct frame_info *frame, int regnum, int all) | |
c906108c | 6290 | { |
025bb325 | 6291 | if (regnum != -1) /* Do one specified register. */ |
c906108c | 6292 | { |
72a155b4 UW |
6293 | gdb_assert (regnum >= gdbarch_num_regs (gdbarch)); |
6294 | if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
8a3fe4f8 | 6295 | error (_("Not a valid register for the current processor type")); |
c906108c | 6296 | |
0cc93a06 | 6297 | mips_print_register (file, frame, regnum); |
e11c53d2 | 6298 | fprintf_filtered (file, "\n"); |
c906108c | 6299 | } |
c5aa993b | 6300 | else |
025bb325 | 6301 | /* Do all (or most) registers. */ |
c906108c | 6302 | { |
72a155b4 UW |
6303 | regnum = gdbarch_num_regs (gdbarch); |
6304 | while (regnum < gdbarch_num_regs (gdbarch) | |
6305 | + gdbarch_num_pseudo_regs (gdbarch)) | |
c906108c | 6306 | { |
004159a2 | 6307 | if (mips_float_register_p (gdbarch, regnum)) |
e11c53d2 | 6308 | { |
025bb325 | 6309 | if (all) /* True for "INFO ALL-REGISTERS" command. */ |
e11c53d2 AC |
6310 | regnum = print_fp_register_row (file, frame, regnum); |
6311 | else | |
025bb325 | 6312 | regnum += MIPS_NUMREGS; /* Skip floating point regs. */ |
e11c53d2 | 6313 | } |
c906108c | 6314 | else |
e11c53d2 | 6315 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
6316 | } |
6317 | } | |
6318 | } | |
6319 | ||
63807e1d | 6320 | static int |
3352ef37 AC |
6321 | mips_single_step_through_delay (struct gdbarch *gdbarch, |
6322 | struct frame_info *frame) | |
c906108c | 6323 | { |
e17a4113 | 6324 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
3352ef37 | 6325 | CORE_ADDR pc = get_frame_pc (frame); |
4cc0665f MR |
6326 | struct address_space *aspace; |
6327 | enum mips_isa isa; | |
6328 | ULONGEST insn; | |
6329 | int status; | |
6330 | int size; | |
6331 | ||
6332 | if ((mips_pc_is_mips (pc) | |
6333 | && !mips32_instruction_has_delay_slot (gdbarch, pc)) | |
6334 | || (mips_pc_is_micromips (gdbarch, pc) | |
6335 | && !micromips_instruction_has_delay_slot (gdbarch, pc, 0)) | |
6336 | || (mips_pc_is_mips16 (gdbarch, pc) | |
6337 | && !mips16_instruction_has_delay_slot (gdbarch, pc, 0))) | |
06648491 MK |
6338 | return 0; |
6339 | ||
4cc0665f MR |
6340 | isa = mips_pc_isa (gdbarch, pc); |
6341 | /* _has_delay_slot above will have validated the read. */ | |
6342 | insn = mips_fetch_instruction (gdbarch, isa, pc, NULL); | |
6343 | size = mips_insn_size (isa, insn); | |
6344 | aspace = get_frame_address_space (frame); | |
6345 | return breakpoint_here_p (aspace, pc + size) != no_breakpoint_here; | |
c906108c SS |
6346 | } |
6347 | ||
6d82d43b AC |
6348 | /* To skip prologues, I use this predicate. Returns either PC itself |
6349 | if the code at PC does not look like a function prologue; otherwise | |
6350 | returns an address that (if we're lucky) follows the prologue. If | |
6351 | LENIENT, then we must skip everything which is involved in setting | |
6352 | up the frame (it's OK to skip more, just so long as we don't skip | |
6353 | anything which might clobber the registers which are being saved. | |
6354 | We must skip more in the case where part of the prologue is in the | |
6355 | delay slot of a non-prologue instruction). */ | |
6356 | ||
6357 | static CORE_ADDR | |
6093d2eb | 6358 | mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
6d82d43b | 6359 | { |
8b622e6a AC |
6360 | CORE_ADDR limit_pc; |
6361 | CORE_ADDR func_addr; | |
6362 | ||
6d82d43b AC |
6363 | /* See if we can determine the end of the prologue via the symbol table. |
6364 | If so, then return either PC, or the PC after the prologue, whichever | |
6365 | is greater. */ | |
8b622e6a AC |
6366 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
6367 | { | |
d80b854b UW |
6368 | CORE_ADDR post_prologue_pc |
6369 | = skip_prologue_using_sal (gdbarch, func_addr); | |
8b622e6a AC |
6370 | if (post_prologue_pc != 0) |
6371 | return max (pc, post_prologue_pc); | |
6372 | } | |
6d82d43b AC |
6373 | |
6374 | /* Can't determine prologue from the symbol table, need to examine | |
6375 | instructions. */ | |
6376 | ||
98b4dd94 JB |
6377 | /* Find an upper limit on the function prologue using the debug |
6378 | information. If the debug information could not be used to provide | |
6379 | that bound, then use an arbitrary large number as the upper bound. */ | |
d80b854b | 6380 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
98b4dd94 JB |
6381 | if (limit_pc == 0) |
6382 | limit_pc = pc + 100; /* Magic. */ | |
6383 | ||
4cc0665f | 6384 | if (mips_pc_is_mips16 (gdbarch, pc)) |
e17a4113 | 6385 | return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
4cc0665f MR |
6386 | else if (mips_pc_is_micromips (gdbarch, pc)) |
6387 | return micromips_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); | |
6d82d43b | 6388 | else |
e17a4113 | 6389 | return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
88658117 AC |
6390 | } |
6391 | ||
97ab0fdd MR |
6392 | /* Check whether the PC is in a function epilogue (32-bit version). |
6393 | This is a helper function for mips_in_function_epilogue_p. */ | |
6394 | static int | |
e17a4113 | 6395 | mips32_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
6396 | { |
6397 | CORE_ADDR func_addr = 0, func_end = 0; | |
6398 | ||
6399 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
6400 | { | |
6401 | /* The MIPS epilogue is max. 12 bytes long. */ | |
6402 | CORE_ADDR addr = func_end - 12; | |
6403 | ||
6404 | if (addr < func_addr + 4) | |
6405 | addr = func_addr + 4; | |
6406 | if (pc < addr) | |
6407 | return 0; | |
6408 | ||
6409 | for (; pc < func_end; pc += MIPS_INSN32_SIZE) | |
6410 | { | |
6411 | unsigned long high_word; | |
6412 | unsigned long inst; | |
6413 | ||
4cc0665f | 6414 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
97ab0fdd MR |
6415 | high_word = (inst >> 16) & 0xffff; |
6416 | ||
6417 | if (high_word != 0x27bd /* addiu $sp,$sp,offset */ | |
6418 | && high_word != 0x67bd /* daddiu $sp,$sp,offset */ | |
6419 | && inst != 0x03e00008 /* jr $ra */ | |
6420 | && inst != 0x00000000) /* nop */ | |
6421 | return 0; | |
6422 | } | |
6423 | ||
6424 | return 1; | |
6425 | } | |
6426 | ||
6427 | return 0; | |
6428 | } | |
6429 | ||
4cc0665f MR |
6430 | /* Check whether the PC is in a function epilogue (microMIPS version). |
6431 | This is a helper function for mips_in_function_epilogue_p. */ | |
6432 | ||
6433 | static int | |
6434 | micromips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
6435 | { | |
6436 | CORE_ADDR func_addr = 0; | |
6437 | CORE_ADDR func_end = 0; | |
6438 | CORE_ADDR addr; | |
6439 | ULONGEST insn; | |
6440 | long offset; | |
6441 | int dreg; | |
6442 | int sreg; | |
6443 | int loc; | |
6444 | ||
6445 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
6446 | return 0; | |
6447 | ||
6448 | /* The microMIPS epilogue is max. 12 bytes long. */ | |
6449 | addr = func_end - 12; | |
6450 | ||
6451 | if (addr < func_addr + 2) | |
6452 | addr = func_addr + 2; | |
6453 | if (pc < addr) | |
6454 | return 0; | |
6455 | ||
6456 | for (; pc < func_end; pc += loc) | |
6457 | { | |
6458 | loc = 0; | |
6459 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
6460 | loc += MIPS_INSN16_SIZE; | |
6461 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
6462 | { | |
6463 | /* 48-bit instructions. */ | |
6464 | case 3 * MIPS_INSN16_SIZE: | |
6465 | /* No epilogue instructions in this category. */ | |
6466 | return 0; | |
6467 | ||
6468 | /* 32-bit instructions. */ | |
6469 | case 2 * MIPS_INSN16_SIZE: | |
6470 | insn <<= 16; | |
6471 | insn |= mips_fetch_instruction (gdbarch, | |
6472 | ISA_MICROMIPS, pc + loc, NULL); | |
6473 | loc += MIPS_INSN16_SIZE; | |
6474 | switch (micromips_op (insn >> 16)) | |
6475 | { | |
6476 | case 0xc: /* ADDIU: bits 001100 */ | |
6477 | case 0x17: /* DADDIU: bits 010111 */ | |
6478 | sreg = b0s5_reg (insn >> 16); | |
6479 | dreg = b5s5_reg (insn >> 16); | |
6480 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
6481 | if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM | |
6482 | /* (D)ADDIU $sp, imm */ | |
6483 | && offset >= 0) | |
6484 | break; | |
6485 | return 0; | |
6486 | ||
6487 | default: | |
6488 | return 0; | |
6489 | } | |
6490 | break; | |
6491 | ||
6492 | /* 16-bit instructions. */ | |
6493 | case MIPS_INSN16_SIZE: | |
6494 | switch (micromips_op (insn)) | |
6495 | { | |
6496 | case 0x3: /* MOVE: bits 000011 */ | |
6497 | sreg = b0s5_reg (insn); | |
6498 | dreg = b5s5_reg (insn); | |
6499 | if (sreg == 0 && dreg == 0) | |
6500 | /* MOVE $zero, $zero aka NOP */ | |
6501 | break; | |
6502 | return 0; | |
6503 | ||
6504 | case 0x11: /* POOL16C: bits 010001 */ | |
6505 | if (b5s5_op (insn) == 0x18 | |
6506 | /* JRADDIUSP: bits 010011 11000 */ | |
6507 | || (b5s5_op (insn) == 0xd | |
6508 | /* JRC: bits 010011 01101 */ | |
6509 | && b0s5_reg (insn) == MIPS_RA_REGNUM)) | |
6510 | /* JRC $ra */ | |
6511 | break; | |
6512 | return 0; | |
6513 | ||
6514 | case 0x13: /* POOL16D: bits 010011 */ | |
6515 | offset = micromips_decode_imm9 (b1s9_imm (insn)); | |
6516 | if ((insn & 0x1) == 0x1 | |
6517 | /* ADDIUSP: bits 010011 1 */ | |
6518 | && offset > 0) | |
6519 | break; | |
6520 | return 0; | |
6521 | ||
6522 | default: | |
6523 | return 0; | |
6524 | } | |
6525 | } | |
6526 | } | |
6527 | ||
6528 | return 1; | |
6529 | } | |
6530 | ||
97ab0fdd MR |
6531 | /* Check whether the PC is in a function epilogue (16-bit version). |
6532 | This is a helper function for mips_in_function_epilogue_p. */ | |
6533 | static int | |
e17a4113 | 6534 | mips16_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
6535 | { |
6536 | CORE_ADDR func_addr = 0, func_end = 0; | |
6537 | ||
6538 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
6539 | { | |
6540 | /* The MIPS epilogue is max. 12 bytes long. */ | |
6541 | CORE_ADDR addr = func_end - 12; | |
6542 | ||
6543 | if (addr < func_addr + 4) | |
6544 | addr = func_addr + 4; | |
6545 | if (pc < addr) | |
6546 | return 0; | |
6547 | ||
6548 | for (; pc < func_end; pc += MIPS_INSN16_SIZE) | |
6549 | { | |
6550 | unsigned short inst; | |
6551 | ||
4cc0665f | 6552 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc, NULL); |
97ab0fdd MR |
6553 | |
6554 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
6555 | continue; | |
6556 | ||
6557 | if (inst != 0x6300 /* addiu $sp,offset */ | |
6558 | && inst != 0xfb00 /* daddiu $sp,$sp,offset */ | |
6559 | && inst != 0xe820 /* jr $ra */ | |
6560 | && inst != 0xe8a0 /* jrc $ra */ | |
6561 | && inst != 0x6500) /* nop */ | |
6562 | return 0; | |
6563 | } | |
6564 | ||
6565 | return 1; | |
6566 | } | |
6567 | ||
6568 | return 0; | |
6569 | } | |
6570 | ||
6571 | /* The epilogue is defined here as the area at the end of a function, | |
6572 | after an instruction which destroys the function's stack frame. */ | |
6573 | static int | |
6574 | mips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
6575 | { | |
4cc0665f | 6576 | if (mips_pc_is_mips16 (gdbarch, pc)) |
e17a4113 | 6577 | return mips16_in_function_epilogue_p (gdbarch, pc); |
4cc0665f MR |
6578 | else if (mips_pc_is_micromips (gdbarch, pc)) |
6579 | return micromips_in_function_epilogue_p (gdbarch, pc); | |
97ab0fdd | 6580 | else |
e17a4113 | 6581 | return mips32_in_function_epilogue_p (gdbarch, pc); |
97ab0fdd MR |
6582 | } |
6583 | ||
025bb325 | 6584 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
a5ea2558 AC |
6585 | used for all MIPS-specific commands. */ |
6586 | ||
a5ea2558 | 6587 | static void |
acdb74a0 | 6588 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
6589 | { |
6590 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
6591 | } | |
6592 | ||
a5ea2558 | 6593 | static void |
acdb74a0 | 6594 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 6595 | { |
6d82d43b AC |
6596 | printf_unfiltered |
6597 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
6598 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
6599 | } | |
6600 | ||
c906108c SS |
6601 | /* Commands to show/set the MIPS FPU type. */ |
6602 | ||
c906108c | 6603 | static void |
acdb74a0 | 6604 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 6605 | { |
c906108c | 6606 | char *fpu; |
6ca0852e | 6607 | |
1cf3db46 | 6608 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips) |
6ca0852e UW |
6609 | { |
6610 | printf_unfiltered | |
6611 | ("The MIPS floating-point coprocessor is unknown " | |
6612 | "because the current architecture is not MIPS.\n"); | |
6613 | return; | |
6614 | } | |
6615 | ||
1cf3db46 | 6616 | switch (MIPS_FPU_TYPE (target_gdbarch)) |
c906108c SS |
6617 | { |
6618 | case MIPS_FPU_SINGLE: | |
6619 | fpu = "single-precision"; | |
6620 | break; | |
6621 | case MIPS_FPU_DOUBLE: | |
6622 | fpu = "double-precision"; | |
6623 | break; | |
6624 | case MIPS_FPU_NONE: | |
6625 | fpu = "absent (none)"; | |
6626 | break; | |
93d56215 | 6627 | default: |
e2e0b3e5 | 6628 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c SS |
6629 | } |
6630 | if (mips_fpu_type_auto) | |
025bb325 MS |
6631 | printf_unfiltered ("The MIPS floating-point coprocessor " |
6632 | "is set automatically (currently %s)\n", | |
6633 | fpu); | |
c906108c | 6634 | else |
6d82d43b AC |
6635 | printf_unfiltered |
6636 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
6637 | } |
6638 | ||
6639 | ||
c906108c | 6640 | static void |
acdb74a0 | 6641 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 6642 | { |
025bb325 MS |
6643 | printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", " |
6644 | "\"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
6645 | show_mipsfpu_command (args, from_tty); |
6646 | } | |
6647 | ||
c906108c | 6648 | static void |
acdb74a0 | 6649 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 6650 | { |
8d5838b5 AC |
6651 | struct gdbarch_info info; |
6652 | gdbarch_info_init (&info); | |
c906108c SS |
6653 | mips_fpu_type = MIPS_FPU_SINGLE; |
6654 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
6655 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
6656 | instead of relying on globals. Doing that would let generic code | |
6657 | handle the search for this specific architecture. */ | |
6658 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 6659 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
6660 | } |
6661 | ||
c906108c | 6662 | static void |
acdb74a0 | 6663 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 6664 | { |
8d5838b5 AC |
6665 | struct gdbarch_info info; |
6666 | gdbarch_info_init (&info); | |
c906108c SS |
6667 | mips_fpu_type = MIPS_FPU_DOUBLE; |
6668 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
6669 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
6670 | instead of relying on globals. Doing that would let generic code | |
6671 | handle the search for this specific architecture. */ | |
6672 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 6673 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
6674 | } |
6675 | ||
c906108c | 6676 | static void |
acdb74a0 | 6677 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 6678 | { |
8d5838b5 AC |
6679 | struct gdbarch_info info; |
6680 | gdbarch_info_init (&info); | |
c906108c SS |
6681 | mips_fpu_type = MIPS_FPU_NONE; |
6682 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
6683 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
6684 | instead of relying on globals. Doing that would let generic code | |
6685 | handle the search for this specific architecture. */ | |
6686 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 6687 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
6688 | } |
6689 | ||
c906108c | 6690 | static void |
acdb74a0 | 6691 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
6692 | { |
6693 | mips_fpu_type_auto = 1; | |
6694 | } | |
6695 | ||
c906108c | 6696 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
6697 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
6698 | the relevant processor still exists (it dates back to '94) and | |
6699 | secondly this is not the way to do this. The processor type should | |
6700 | be set by forcing an architecture change. */ | |
c906108c | 6701 | |
691c0433 AC |
6702 | void |
6703 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 6704 | { |
bb486190 UW |
6705 | struct regcache *regcache = get_current_regcache (); |
6706 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
6707 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
a9614958 | 6708 | ULONGEST prid; |
c906108c | 6709 | |
bb486190 | 6710 | regcache_cooked_read_unsigned (regcache, MIPS_PRID_REGNUM, &prid); |
c906108c | 6711 | if ((prid & ~0xf) == 0x700) |
691c0433 | 6712 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
6713 | } |
6714 | ||
6715 | /* Just like reinit_frame_cache, but with the right arguments to be | |
6716 | callable as an sfunc. */ | |
6717 | ||
6718 | static void | |
acdb74a0 AC |
6719 | reinit_frame_cache_sfunc (char *args, int from_tty, |
6720 | struct cmd_list_element *c) | |
c906108c SS |
6721 | { |
6722 | reinit_frame_cache (); | |
6723 | } | |
6724 | ||
a89aa300 AC |
6725 | static int |
6726 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 6727 | { |
4cc0665f MR |
6728 | struct gdbarch *gdbarch = info->application_data; |
6729 | ||
d31431ed AC |
6730 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
6731 | disassembler needs to be able to locally determine the ISA, and | |
6732 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
6733 | work. */ | |
4cc0665f | 6734 | if (mips_pc_is_mips16 (gdbarch, memaddr)) |
ec4045ea | 6735 | info->mach = bfd_mach_mips16; |
4cc0665f MR |
6736 | else if (mips_pc_is_micromips (gdbarch, memaddr)) |
6737 | info->mach = bfd_mach_mips_micromips; | |
c906108c SS |
6738 | |
6739 | /* Round down the instruction address to the appropriate boundary. */ | |
4cc0665f MR |
6740 | memaddr &= (info->mach == bfd_mach_mips16 |
6741 | || info->mach == bfd_mach_mips_micromips) ? ~1 : ~3; | |
c5aa993b | 6742 | |
e5ab0dce | 6743 | /* Set the disassembler options. */ |
9dae60cc | 6744 | if (!info->disassembler_options) |
e5ab0dce AC |
6745 | /* This string is not recognized explicitly by the disassembler, |
6746 | but it tells the disassembler to not try to guess the ABI from | |
6747 | the bfd elf headers, such that, if the user overrides the ABI | |
6748 | of a program linked as NewABI, the disassembly will follow the | |
6749 | register naming conventions specified by the user. */ | |
6750 | info->disassembler_options = "gpr-names=32"; | |
6751 | ||
c906108c | 6752 | /* Call the appropriate disassembler based on the target endian-ness. */ |
40887e1a | 6753 | if (info->endian == BFD_ENDIAN_BIG) |
c906108c SS |
6754 | return print_insn_big_mips (memaddr, info); |
6755 | else | |
6756 | return print_insn_little_mips (memaddr, info); | |
6757 | } | |
6758 | ||
9dae60cc UW |
6759 | static int |
6760 | gdb_print_insn_mips_n32 (bfd_vma memaddr, struct disassemble_info *info) | |
6761 | { | |
6762 | /* Set up the disassembler info, so that we get the right | |
6763 | register names from libopcodes. */ | |
6764 | info->disassembler_options = "gpr-names=n32"; | |
6765 | info->flavour = bfd_target_elf_flavour; | |
6766 | ||
6767 | return gdb_print_insn_mips (memaddr, info); | |
6768 | } | |
6769 | ||
6770 | static int | |
6771 | gdb_print_insn_mips_n64 (bfd_vma memaddr, struct disassemble_info *info) | |
6772 | { | |
6773 | /* Set up the disassembler info, so that we get the right | |
6774 | register names from libopcodes. */ | |
6775 | info->disassembler_options = "gpr-names=64"; | |
6776 | info->flavour = bfd_target_elf_flavour; | |
6777 | ||
6778 | return gdb_print_insn_mips (memaddr, info); | |
6779 | } | |
6780 | ||
025bb325 MS |
6781 | /* This function implements gdbarch_breakpoint_from_pc. It uses the |
6782 | program counter value to determine whether a 16- or 32-bit breakpoint | |
6783 | should be used. It returns a pointer to a string of bytes that encode a | |
6784 | breakpoint instruction, stores the length of the string to *lenptr, and | |
6785 | adjusts pc (if necessary) to point to the actual memory location where | |
6786 | the breakpoint should be inserted. */ | |
c906108c | 6787 | |
47a35522 | 6788 | static const gdb_byte * |
025bb325 MS |
6789 | mips_breakpoint_from_pc (struct gdbarch *gdbarch, |
6790 | CORE_ADDR *pcptr, int *lenptr) | |
c906108c | 6791 | { |
4cc0665f MR |
6792 | CORE_ADDR pc = *pcptr; |
6793 | ||
67d57894 | 6794 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
c906108c | 6795 | { |
4cc0665f | 6796 | if (mips_pc_is_mips16 (gdbarch, pc)) |
c906108c | 6797 | { |
47a35522 | 6798 | static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
4cc0665f | 6799 | *pcptr = unmake_compact_addr (pc); |
c5aa993b | 6800 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
6801 | return mips16_big_breakpoint; |
6802 | } | |
4cc0665f MR |
6803 | else if (mips_pc_is_micromips (gdbarch, pc)) |
6804 | { | |
6805 | static gdb_byte micromips16_big_breakpoint[] = { 0x46, 0x85 }; | |
6806 | static gdb_byte micromips32_big_breakpoint[] = { 0, 0x5, 0, 0x7 }; | |
6807 | ULONGEST insn; | |
6808 | int status; | |
6809 | int size; | |
6810 | ||
6811 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status); | |
6812 | size = status ? 2 | |
6813 | : mips_insn_size (ISA_MICROMIPS, insn) == 2 ? 2 : 4; | |
6814 | *pcptr = unmake_compact_addr (pc); | |
6815 | *lenptr = size; | |
6816 | return (size == 2) ? micromips16_big_breakpoint | |
6817 | : micromips32_big_breakpoint; | |
6818 | } | |
c906108c SS |
6819 | else |
6820 | { | |
aaab4dba AC |
6821 | /* The IDT board uses an unusual breakpoint value, and |
6822 | sometimes gets confused when it sees the usual MIPS | |
6823 | breakpoint instruction. */ | |
47a35522 MK |
6824 | static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
6825 | static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
6826 | static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
f2ec0ecf | 6827 | /* Likewise, IRIX appears to expect a different breakpoint, |
025bb325 | 6828 | although this is not apparent until you try to use pthreads. */ |
f2ec0ecf | 6829 | static gdb_byte irix_big_breakpoint[] = { 0, 0, 0, 0xd }; |
c906108c | 6830 | |
c5aa993b | 6831 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
6832 | |
6833 | if (strcmp (target_shortname, "mips") == 0) | |
6834 | return idt_big_breakpoint; | |
6835 | else if (strcmp (target_shortname, "ddb") == 0 | |
6836 | || strcmp (target_shortname, "pmon") == 0 | |
6837 | || strcmp (target_shortname, "lsi") == 0) | |
6838 | return pmon_big_breakpoint; | |
f2ec0ecf JB |
6839 | else if (gdbarch_osabi (gdbarch) == GDB_OSABI_IRIX) |
6840 | return irix_big_breakpoint; | |
c906108c SS |
6841 | else |
6842 | return big_breakpoint; | |
6843 | } | |
6844 | } | |
6845 | else | |
6846 | { | |
4cc0665f | 6847 | if (mips_pc_is_mips16 (gdbarch, pc)) |
c906108c | 6848 | { |
47a35522 | 6849 | static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
4cc0665f | 6850 | *pcptr = unmake_compact_addr (pc); |
c5aa993b | 6851 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
6852 | return mips16_little_breakpoint; |
6853 | } | |
4cc0665f MR |
6854 | else if (mips_pc_is_micromips (gdbarch, pc)) |
6855 | { | |
6856 | static gdb_byte micromips16_little_breakpoint[] = { 0x85, 0x46 }; | |
6857 | static gdb_byte micromips32_little_breakpoint[] = { 0x5, 0, 0x7, 0 }; | |
6858 | ULONGEST insn; | |
6859 | int status; | |
6860 | int size; | |
6861 | ||
6862 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status); | |
6863 | size = status ? 2 | |
6864 | : mips_insn_size (ISA_MICROMIPS, insn) == 2 ? 2 : 4; | |
6865 | *pcptr = unmake_compact_addr (pc); | |
6866 | *lenptr = size; | |
6867 | return (size == 2) ? micromips16_little_breakpoint | |
6868 | : micromips32_little_breakpoint; | |
6869 | } | |
c906108c SS |
6870 | else |
6871 | { | |
47a35522 MK |
6872 | static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
6873 | static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
6874 | static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 6875 | |
c5aa993b | 6876 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
6877 | |
6878 | if (strcmp (target_shortname, "mips") == 0) | |
6879 | return idt_little_breakpoint; | |
6880 | else if (strcmp (target_shortname, "ddb") == 0 | |
6881 | || strcmp (target_shortname, "pmon") == 0 | |
6882 | || strcmp (target_shortname, "lsi") == 0) | |
6883 | return pmon_little_breakpoint; | |
6884 | else | |
6885 | return little_breakpoint; | |
6886 | } | |
6887 | } | |
6888 | } | |
6889 | ||
4cc0665f MR |
6890 | /* Determine the remote breakpoint kind suitable for the PC. The following |
6891 | kinds are used: | |
6892 | ||
6893 | * 2 -- 16-bit MIPS16 mode breakpoint, | |
6894 | ||
6895 | * 3 -- 16-bit microMIPS mode breakpoint, | |
6896 | ||
6897 | * 4 -- 32-bit standard MIPS mode breakpoint, | |
6898 | ||
6899 | * 5 -- 32-bit microMIPS mode breakpoint. */ | |
6900 | ||
6901 | static void | |
6902 | mips_remote_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, | |
6903 | int *kindptr) | |
6904 | { | |
6905 | CORE_ADDR pc = *pcptr; | |
6906 | ||
6907 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
6908 | { | |
6909 | *pcptr = unmake_compact_addr (pc); | |
6910 | *kindptr = 2; | |
6911 | } | |
6912 | else if (mips_pc_is_micromips (gdbarch, pc)) | |
6913 | { | |
6914 | ULONGEST insn; | |
6915 | int status; | |
6916 | int size; | |
6917 | ||
6918 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status); | |
6919 | size = status ? 2 : mips_insn_size (ISA_MICROMIPS, insn) == 2 ? 2 : 4; | |
6920 | *pcptr = unmake_compact_addr (pc); | |
6921 | *kindptr = size | 1; | |
6922 | } | |
6923 | else | |
6924 | *kindptr = 4; | |
6925 | } | |
6926 | ||
c8cef75f MR |
6927 | /* Return non-zero if the ADDR instruction has a branch delay slot |
6928 | (i.e. it is a jump or branch instruction). This function is based | |
6929 | on mips32_next_pc. */ | |
6930 | ||
6931 | static int | |
6932 | mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr) | |
6933 | { | |
c8cef75f MR |
6934 | unsigned long inst; |
6935 | int status; | |
6936 | int op; | |
a385295e MR |
6937 | int rs; |
6938 | int rt; | |
c8cef75f | 6939 | |
4cc0665f | 6940 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS, addr, &status); |
c8cef75f MR |
6941 | if (status) |
6942 | return 0; | |
6943 | ||
c8cef75f MR |
6944 | op = itype_op (inst); |
6945 | if ((inst & 0xe0000000) != 0) | |
a385295e MR |
6946 | { |
6947 | rs = itype_rs (inst); | |
6948 | rt = itype_rt (inst); | |
6949 | return (op >> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ | |
6950 | || op == 29 /* JALX: bits 011101 */ | |
6951 | || (op == 17 | |
6952 | && (rs == 8 | |
c8cef75f | 6953 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
a385295e MR |
6954 | || (rs == 9 && (rt & 0x2) == 0) |
6955 | /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */ | |
6956 | || (rs == 10 && (rt & 0x2) == 0)))); | |
6957 | /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */ | |
6958 | } | |
c8cef75f MR |
6959 | else |
6960 | switch (op & 0x07) /* extract bits 28,27,26 */ | |
6961 | { | |
6962 | case 0: /* SPECIAL */ | |
6963 | op = rtype_funct (inst); | |
6964 | return (op == 8 /* JR */ | |
6965 | || op == 9); /* JALR */ | |
6966 | break; /* end SPECIAL */ | |
6967 | case 1: /* REGIMM */ | |
a385295e MR |
6968 | rs = itype_rs (inst); |
6969 | rt = itype_rt (inst); /* branch condition */ | |
6970 | return ((rt & 0xc) == 0 | |
c8cef75f MR |
6971 | /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */ |
6972 | /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */ | |
a385295e MR |
6973 | || ((rt & 0x1e) == 0x1c && rs == 0)); |
6974 | /* BPOSGE32, BPOSGE64: bits 1110x */ | |
c8cef75f MR |
6975 | break; /* end REGIMM */ |
6976 | default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */ | |
6977 | return 1; | |
6978 | break; | |
6979 | } | |
6980 | } | |
6981 | ||
6982 | /* Return non-zero if the ADDR instruction, which must be a 32-bit | |
6983 | instruction if MUSTBE32 is set or can be any instruction otherwise, | |
6984 | has a branch delay slot (i.e. it is a non-compact jump instruction). */ | |
6985 | ||
4cc0665f MR |
6986 | static int |
6987 | micromips_instruction_has_delay_slot (struct gdbarch *gdbarch, | |
6988 | CORE_ADDR addr, int mustbe32) | |
6989 | { | |
6990 | ULONGEST insn; | |
6991 | int status; | |
6992 | ||
6993 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status); | |
6994 | if (status) | |
6995 | return 0; | |
6996 | ||
6997 | if (!mustbe32) /* 16-bit instructions. */ | |
6998 | return (micromips_op (insn) == 0x11 | |
6999 | /* POOL16C: bits 010001 */ | |
7000 | && (b5s5_op (insn) == 0xc | |
7001 | /* JR16: bits 010001 01100 */ | |
7002 | || (b5s5_op (insn) & 0x1e) == 0xe)) | |
7003 | /* JALR16, JALRS16: bits 010001 0111x */ | |
7004 | || (micromips_op (insn) & 0x37) == 0x23 | |
7005 | /* BEQZ16, BNEZ16: bits 10x011 */ | |
7006 | || micromips_op (insn) == 0x33; | |
7007 | /* B16: bits 110011 */ | |
7008 | ||
7009 | /* 32-bit instructions. */ | |
7010 | if (micromips_op (insn) == 0x0) | |
7011 | /* POOL32A: bits 000000 */ | |
7012 | { | |
7013 | insn <<= 16; | |
7014 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status); | |
7015 | if (status) | |
7016 | return 0; | |
7017 | return b0s6_op (insn) == 0x3c | |
7018 | /* POOL32Axf: bits 000000 ... 111100 */ | |
7019 | && (b6s10_ext (insn) & 0x2bf) == 0x3c; | |
7020 | /* JALR, JALR.HB: 000000 000x111100 111100 */ | |
7021 | /* JALRS, JALRS.HB: 000000 010x111100 111100 */ | |
7022 | } | |
7023 | ||
7024 | return (micromips_op (insn) == 0x10 | |
7025 | /* POOL32I: bits 010000 */ | |
7026 | && ((b5s5_op (insn) & 0x1c) == 0x0 | |
7027 | /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */ | |
7028 | || (b5s5_op (insn) & 0x1d) == 0x4 | |
7029 | /* BLEZ, BGTZ: bits 010000 001x0 */ | |
7030 | || (b5s5_op (insn) & 0x1d) == 0x11 | |
7031 | /* BLTZALS, BGEZALS: bits 010000 100x1 */ | |
7032 | || ((b5s5_op (insn) & 0x1e) == 0x14 | |
7033 | && (insn & 0x3) == 0x0) | |
7034 | /* BC2F, BC2T: bits 010000 1010x xxx00 */ | |
7035 | || (b5s5_op (insn) & 0x1e) == 0x1a | |
7036 | /* BPOSGE64, BPOSGE32: bits 010000 1101x */ | |
7037 | || ((b5s5_op (insn) & 0x1e) == 0x1c | |
7038 | && (insn & 0x3) == 0x0) | |
7039 | /* BC1F, BC1T: bits 010000 1110x xxx00 */ | |
7040 | || ((b5s5_op (insn) & 0x1c) == 0x1c | |
7041 | && (insn & 0x3) == 0x1))) | |
7042 | /* BC1ANY*: bits 010000 111xx xxx01 */ | |
7043 | || (micromips_op (insn) & 0x1f) == 0x1d | |
7044 | /* JALS, JAL: bits x11101 */ | |
7045 | || (micromips_op (insn) & 0x37) == 0x25 | |
7046 | /* BEQ, BNE: bits 10x101 */ | |
7047 | || micromips_op (insn) == 0x35 | |
7048 | /* J: bits 110101 */ | |
7049 | || micromips_op (insn) == 0x3c; | |
7050 | /* JALX: bits 111100 */ | |
7051 | } | |
7052 | ||
c8cef75f MR |
7053 | static int |
7054 | mips16_instruction_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr, | |
7055 | int mustbe32) | |
7056 | { | |
c8cef75f MR |
7057 | unsigned short inst; |
7058 | int status; | |
7059 | ||
4cc0665f | 7060 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, addr, &status); |
c8cef75f MR |
7061 | if (status) |
7062 | return 0; | |
7063 | ||
c8cef75f MR |
7064 | if (!mustbe32) |
7065 | return (inst & 0xf89f) == 0xe800; /* JR/JALR (16-bit instruction) */ | |
7066 | return (inst & 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */ | |
7067 | } | |
7068 | ||
7069 | /* Calculate the starting address of the MIPS memory segment BPADDR is in. | |
7070 | This assumes KSSEG exists. */ | |
7071 | ||
7072 | static CORE_ADDR | |
7073 | mips_segment_boundary (CORE_ADDR bpaddr) | |
7074 | { | |
7075 | CORE_ADDR mask = CORE_ADDR_MAX; | |
7076 | int segsize; | |
7077 | ||
7078 | if (sizeof (CORE_ADDR) == 8) | |
7079 | /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid | |
7080 | a compiler warning produced where CORE_ADDR is a 32-bit type even | |
7081 | though in that case this is dead code). */ | |
7082 | switch (bpaddr >> ((sizeof (CORE_ADDR) << 3) - 2) & 3) | |
7083 | { | |
7084 | case 3: | |
7085 | if (bpaddr == (bfd_signed_vma) (int32_t) bpaddr) | |
7086 | segsize = 29; /* 32-bit compatibility segment */ | |
7087 | else | |
7088 | segsize = 62; /* xkseg */ | |
7089 | break; | |
7090 | case 2: /* xkphys */ | |
7091 | segsize = 59; | |
7092 | break; | |
7093 | default: /* xksseg (1), xkuseg/kuseg (0) */ | |
7094 | segsize = 62; | |
7095 | break; | |
7096 | } | |
7097 | else if (bpaddr & 0x80000000) /* kernel segment */ | |
7098 | segsize = 29; | |
7099 | else | |
7100 | segsize = 31; /* user segment */ | |
7101 | mask <<= segsize; | |
7102 | return bpaddr & mask; | |
7103 | } | |
7104 | ||
7105 | /* Move the breakpoint at BPADDR out of any branch delay slot by shifting | |
7106 | it backwards if necessary. Return the address of the new location. */ | |
7107 | ||
7108 | static CORE_ADDR | |
7109 | mips_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) | |
7110 | { | |
22e048c9 | 7111 | CORE_ADDR prev_addr; |
c8cef75f MR |
7112 | CORE_ADDR boundary; |
7113 | CORE_ADDR func_addr; | |
7114 | ||
7115 | /* If a breakpoint is set on the instruction in a branch delay slot, | |
7116 | GDB gets confused. When the breakpoint is hit, the PC isn't on | |
7117 | the instruction in the branch delay slot, the PC will point to | |
7118 | the branch instruction. Since the PC doesn't match any known | |
7119 | breakpoints, GDB reports a trap exception. | |
7120 | ||
7121 | There are two possible fixes for this problem. | |
7122 | ||
7123 | 1) When the breakpoint gets hit, see if the BD bit is set in the | |
7124 | Cause register (which indicates the last exception occurred in a | |
7125 | branch delay slot). If the BD bit is set, fix the PC to point to | |
7126 | the instruction in the branch delay slot. | |
7127 | ||
7128 | 2) When the user sets the breakpoint, don't allow him to set the | |
7129 | breakpoint on the instruction in the branch delay slot. Instead | |
7130 | move the breakpoint to the branch instruction (which will have | |
7131 | the same result). | |
7132 | ||
7133 | The problem with the first solution is that if the user then | |
7134 | single-steps the processor, the branch instruction will get | |
7135 | skipped (since GDB thinks the PC is on the instruction in the | |
7136 | branch delay slot). | |
7137 | ||
7138 | So, we'll use the second solution. To do this we need to know if | |
7139 | the instruction we're trying to set the breakpoint on is in the | |
7140 | branch delay slot. */ | |
7141 | ||
7142 | boundary = mips_segment_boundary (bpaddr); | |
7143 | ||
7144 | /* Make sure we don't scan back before the beginning of the current | |
7145 | function, since we may fetch constant data or insns that look like | |
7146 | a jump. Of course we might do that anyway if the compiler has | |
7147 | moved constants inline. :-( */ | |
7148 | if (find_pc_partial_function (bpaddr, NULL, &func_addr, NULL) | |
7149 | && func_addr > boundary && func_addr <= bpaddr) | |
7150 | boundary = func_addr; | |
7151 | ||
4cc0665f | 7152 | if (mips_pc_is_mips (bpaddr)) |
c8cef75f MR |
7153 | { |
7154 | if (bpaddr == boundary) | |
7155 | return bpaddr; | |
7156 | ||
7157 | /* If the previous instruction has a branch delay slot, we have | |
7158 | to move the breakpoint to the branch instruction. */ | |
7159 | prev_addr = bpaddr - 4; | |
7160 | if (mips32_instruction_has_delay_slot (gdbarch, prev_addr)) | |
7161 | bpaddr = prev_addr; | |
7162 | } | |
7163 | else | |
7164 | { | |
4cc0665f | 7165 | int (*instruction_has_delay_slot) (struct gdbarch *, CORE_ADDR, int); |
c8cef75f MR |
7166 | CORE_ADDR addr, jmpaddr; |
7167 | int i; | |
7168 | ||
4cc0665f | 7169 | boundary = unmake_compact_addr (boundary); |
c8cef75f MR |
7170 | |
7171 | /* The only MIPS16 instructions with delay slots are JAL, JALX, | |
7172 | JALR and JR. An absolute JAL/JALX is always 4 bytes long, | |
7173 | so try for that first, then try the 2 byte JALR/JR. | |
4cc0665f MR |
7174 | The microMIPS ASE has a whole range of jumps and branches |
7175 | with delay slots, some of which take 4 bytes and some take | |
7176 | 2 bytes, so the idea is the same. | |
c8cef75f MR |
7177 | FIXME: We have to assume that bpaddr is not the second half |
7178 | of an extended instruction. */ | |
4cc0665f MR |
7179 | instruction_has_delay_slot = (mips_pc_is_micromips (gdbarch, bpaddr) |
7180 | ? micromips_instruction_has_delay_slot | |
7181 | : mips16_instruction_has_delay_slot); | |
c8cef75f MR |
7182 | |
7183 | jmpaddr = 0; | |
7184 | addr = bpaddr; | |
7185 | for (i = 1; i < 4; i++) | |
7186 | { | |
4cc0665f | 7187 | if (unmake_compact_addr (addr) == boundary) |
c8cef75f | 7188 | break; |
4cc0665f MR |
7189 | addr -= MIPS_INSN16_SIZE; |
7190 | if (i == 1 && instruction_has_delay_slot (gdbarch, addr, 0)) | |
c8cef75f MR |
7191 | /* Looks like a JR/JALR at [target-1], but it could be |
7192 | the second word of a previous JAL/JALX, so record it | |
7193 | and check back one more. */ | |
7194 | jmpaddr = addr; | |
4cc0665f | 7195 | else if (i > 1 && instruction_has_delay_slot (gdbarch, addr, 1)) |
c8cef75f MR |
7196 | { |
7197 | if (i == 2) | |
7198 | /* Looks like a JAL/JALX at [target-2], but it could also | |
7199 | be the second word of a previous JAL/JALX, record it, | |
7200 | and check back one more. */ | |
7201 | jmpaddr = addr; | |
7202 | else | |
7203 | /* Looks like a JAL/JALX at [target-3], so any previously | |
7204 | recorded JAL/JALX or JR/JALR must be wrong, because: | |
7205 | ||
7206 | >-3: JAL | |
7207 | -2: JAL-ext (can't be JAL/JALX) | |
7208 | -1: bdslot (can't be JR/JALR) | |
7209 | 0: target insn | |
7210 | ||
7211 | Of course it could be another JAL-ext which looks | |
7212 | like a JAL, but in that case we'd have broken out | |
7213 | of this loop at [target-2]: | |
7214 | ||
7215 | -4: JAL | |
7216 | >-3: JAL-ext | |
7217 | -2: bdslot (can't be jmp) | |
7218 | -1: JR/JALR | |
7219 | 0: target insn */ | |
7220 | jmpaddr = 0; | |
7221 | } | |
7222 | else | |
7223 | { | |
7224 | /* Not a jump instruction: if we're at [target-1] this | |
7225 | could be the second word of a JAL/JALX, so continue; | |
7226 | otherwise we're done. */ | |
7227 | if (i > 1) | |
7228 | break; | |
7229 | } | |
7230 | } | |
7231 | ||
7232 | if (jmpaddr) | |
7233 | bpaddr = jmpaddr; | |
7234 | } | |
7235 | ||
7236 | return bpaddr; | |
7237 | } | |
7238 | ||
14132e89 MR |
7239 | /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16 |
7240 | call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */ | |
7241 | ||
7242 | static int | |
7243 | mips_is_stub_suffix (const char *suffix, int zero) | |
7244 | { | |
7245 | switch (suffix[0]) | |
7246 | { | |
7247 | case '0': | |
7248 | return zero && suffix[1] == '\0'; | |
7249 | case '1': | |
7250 | return suffix[1] == '\0' || (suffix[1] == '0' && suffix[2] == '\0'); | |
7251 | case '2': | |
7252 | case '5': | |
7253 | case '6': | |
7254 | case '9': | |
7255 | return suffix[1] == '\0'; | |
7256 | default: | |
7257 | return 0; | |
7258 | } | |
7259 | } | |
7260 | ||
7261 | /* Return non-zero if MODE is one of the mode infixes used for MIPS16 | |
7262 | call stubs, one of sf, df, sc, or dc. */ | |
7263 | ||
7264 | static int | |
7265 | mips_is_stub_mode (const char *mode) | |
7266 | { | |
7267 | return ((mode[0] == 's' || mode[0] == 'd') | |
7268 | && (mode[1] == 'f' || mode[1] == 'c')); | |
7269 | } | |
7270 | ||
7271 | /* Code at PC is a compiler-generated stub. Such a stub for a function | |
7272 | bar might have a name like __fn_stub_bar, and might look like this: | |
7273 | ||
7274 | mfc1 $4, $f13 | |
7275 | mfc1 $5, $f12 | |
7276 | mfc1 $6, $f15 | |
7277 | mfc1 $7, $f14 | |
7278 | ||
7279 | followed by (or interspersed with): | |
7280 | ||
7281 | j bar | |
7282 | ||
7283 | or: | |
7284 | ||
7285 | lui $25, %hi(bar) | |
7286 | addiu $25, $25, %lo(bar) | |
7287 | jr $25 | |
7288 | ||
7289 | ($1 may be used in old code; for robustness we accept any register) | |
7290 | or, in PIC code: | |
7291 | ||
7292 | lui $28, %hi(_gp_disp) | |
7293 | addiu $28, $28, %lo(_gp_disp) | |
7294 | addu $28, $28, $25 | |
7295 | lw $25, %got(bar) | |
7296 | addiu $25, $25, %lo(bar) | |
7297 | jr $25 | |
7298 | ||
7299 | In the case of a __call_stub_bar stub, the sequence to set up | |
7300 | arguments might look like this: | |
7301 | ||
7302 | mtc1 $4, $f13 | |
7303 | mtc1 $5, $f12 | |
7304 | mtc1 $6, $f15 | |
7305 | mtc1 $7, $f14 | |
7306 | ||
7307 | followed by (or interspersed with) one of the jump sequences above. | |
7308 | ||
7309 | In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead | |
7310 | of J or JR, respectively, followed by: | |
7311 | ||
7312 | mfc1 $2, $f0 | |
7313 | mfc1 $3, $f1 | |
7314 | jr $18 | |
7315 | ||
7316 | We are at the beginning of the stub here, and scan down and extract | |
7317 | the target address from the jump immediate instruction or, if a jump | |
7318 | register instruction is used, from the register referred. Return | |
7319 | the value of PC calculated or 0 if inconclusive. | |
7320 | ||
7321 | The limit on the search is arbitrarily set to 20 instructions. FIXME. */ | |
7322 | ||
7323 | static CORE_ADDR | |
7324 | mips_get_mips16_fn_stub_pc (struct frame_info *frame, CORE_ADDR pc) | |
7325 | { | |
7326 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
7327 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
7328 | int addrreg = MIPS_ZERO_REGNUM; | |
7329 | CORE_ADDR start_pc = pc; | |
7330 | CORE_ADDR target_pc = 0; | |
7331 | CORE_ADDR addr = 0; | |
7332 | CORE_ADDR gp = 0; | |
7333 | int status = 0; | |
7334 | int i; | |
7335 | ||
7336 | for (i = 0; | |
7337 | status == 0 && target_pc == 0 && i < 20; | |
7338 | i++, pc += MIPS_INSN32_SIZE) | |
7339 | { | |
4cc0665f | 7340 | ULONGEST inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
14132e89 MR |
7341 | CORE_ADDR imm; |
7342 | int rt; | |
7343 | int rs; | |
7344 | int rd; | |
7345 | ||
7346 | switch (itype_op (inst)) | |
7347 | { | |
7348 | case 0: /* SPECIAL */ | |
7349 | switch (rtype_funct (inst)) | |
7350 | { | |
7351 | case 8: /* JR */ | |
7352 | case 9: /* JALR */ | |
7353 | rs = rtype_rs (inst); | |
7354 | if (rs == MIPS_GP_REGNUM) | |
7355 | target_pc = gp; /* Hmm... */ | |
7356 | else if (rs == addrreg) | |
7357 | target_pc = addr; | |
7358 | break; | |
7359 | ||
7360 | case 0x21: /* ADDU */ | |
7361 | rt = rtype_rt (inst); | |
7362 | rs = rtype_rs (inst); | |
7363 | rd = rtype_rd (inst); | |
7364 | if (rd == MIPS_GP_REGNUM | |
7365 | && ((rs == MIPS_GP_REGNUM && rt == MIPS_T9_REGNUM) | |
7366 | || (rs == MIPS_T9_REGNUM && rt == MIPS_GP_REGNUM))) | |
7367 | gp += start_pc; | |
7368 | break; | |
7369 | } | |
7370 | break; | |
7371 | ||
7372 | case 2: /* J */ | |
7373 | case 3: /* JAL */ | |
7374 | target_pc = jtype_target (inst) << 2; | |
7375 | target_pc += ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); | |
7376 | break; | |
7377 | ||
7378 | case 9: /* ADDIU */ | |
7379 | rt = itype_rt (inst); | |
7380 | rs = itype_rs (inst); | |
7381 | if (rt == rs) | |
7382 | { | |
7383 | imm = (itype_immediate (inst) ^ 0x8000) - 0x8000; | |
7384 | if (rt == MIPS_GP_REGNUM) | |
7385 | gp += imm; | |
7386 | else if (rt == addrreg) | |
7387 | addr += imm; | |
7388 | } | |
7389 | break; | |
7390 | ||
7391 | case 0xf: /* LUI */ | |
7392 | rt = itype_rt (inst); | |
7393 | imm = ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 16; | |
7394 | if (rt == MIPS_GP_REGNUM) | |
7395 | gp = imm; | |
7396 | else if (rt != MIPS_ZERO_REGNUM) | |
7397 | { | |
7398 | addrreg = rt; | |
7399 | addr = imm; | |
7400 | } | |
7401 | break; | |
7402 | ||
7403 | case 0x23: /* LW */ | |
7404 | rt = itype_rt (inst); | |
7405 | rs = itype_rs (inst); | |
7406 | imm = (itype_immediate (inst) ^ 0x8000) - 0x8000; | |
7407 | if (gp != 0 && rs == MIPS_GP_REGNUM) | |
7408 | { | |
7409 | gdb_byte buf[4]; | |
7410 | ||
7411 | memset (buf, 0, sizeof (buf)); | |
7412 | status = target_read_memory (gp + imm, buf, sizeof (buf)); | |
7413 | addrreg = rt; | |
7414 | addr = extract_signed_integer (buf, sizeof (buf), byte_order); | |
7415 | } | |
7416 | break; | |
7417 | } | |
7418 | } | |
7419 | ||
7420 | return target_pc; | |
7421 | } | |
7422 | ||
7423 | /* If PC is in a MIPS16 call or return stub, return the address of the | |
7424 | target PC, which is either the callee or the caller. There are several | |
c906108c SS |
7425 | cases which must be handled: |
7426 | ||
14132e89 MR |
7427 | * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub |
7428 | and the target PC is in $31 ($ra). | |
c906108c | 7429 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
14132e89 MR |
7430 | and the target PC is in $2. |
7431 | * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10}, | |
7432 | i.e. before the JALR instruction, this is effectively a call stub | |
7433 | and the target PC is in $2. Otherwise this is effectively | |
7434 | a return stub and the target PC is in $18. | |
7435 | * If the PC is at the start of __call_stub_fp_*, i.e. before the | |
7436 | JAL or JALR instruction, this is effectively a call stub and the | |
7437 | target PC is buried in the instruction stream. Otherwise this | |
7438 | is effectively a return stub and the target PC is in $18. | |
7439 | * If the PC is in __call_stub_* or in __fn_stub_*, this is a call | |
7440 | stub and the target PC is buried in the instruction stream. | |
7441 | ||
7442 | See the source code for the stubs in gcc/config/mips/mips16.S, or the | |
7443 | stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the | |
e7d6a6d2 | 7444 | gory details. */ |
c906108c | 7445 | |
757a7cc6 | 7446 | static CORE_ADDR |
db5f024e | 7447 | mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 7448 | { |
e17a4113 | 7449 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 7450 | CORE_ADDR start_addr; |
14132e89 MR |
7451 | const char *name; |
7452 | size_t prefixlen; | |
c906108c SS |
7453 | |
7454 | /* Find the starting address and name of the function containing the PC. */ | |
7455 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
7456 | return 0; | |
7457 | ||
14132e89 MR |
7458 | /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub |
7459 | and the target PC is in $31 ($ra). */ | |
7460 | prefixlen = strlen (mips_str_mips16_ret_stub); | |
7461 | if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0 | |
7462 | && mips_is_stub_mode (name + prefixlen) | |
7463 | && name[prefixlen + 2] == '\0') | |
7464 | return get_frame_register_signed | |
7465 | (frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM); | |
7466 | ||
7467 | /* If the PC is in __mips16_call_stub_*, this is one of the call | |
7468 | call/return stubs. */ | |
7469 | prefixlen = strlen (mips_str_mips16_call_stub); | |
7470 | if (strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0) | |
c906108c SS |
7471 | { |
7472 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
7473 | and the target PC is in $2. */ | |
14132e89 MR |
7474 | if (mips_is_stub_suffix (name + prefixlen, 0)) |
7475 | return get_frame_register_signed | |
7476 | (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); | |
c906108c | 7477 | |
14132e89 MR |
7478 | /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10}, |
7479 | i.e. before the JALR instruction, this is effectively a call stub | |
b021a221 | 7480 | and the target PC is in $2. Otherwise this is effectively |
c5aa993b | 7481 | a return stub and the target PC is in $18. */ |
14132e89 MR |
7482 | else if (mips_is_stub_mode (name + prefixlen) |
7483 | && name[prefixlen + 2] == '_' | |
7484 | && mips_is_stub_suffix (name + prefixlen + 3, 0)) | |
c906108c SS |
7485 | { |
7486 | if (pc == start_addr) | |
14132e89 MR |
7487 | /* This is the 'call' part of a call stub. The return |
7488 | address is in $2. */ | |
7489 | return get_frame_register_signed | |
7490 | (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); | |
c906108c SS |
7491 | else |
7492 | /* This is the 'return' part of a call stub. The return | |
14132e89 MR |
7493 | address is in $18. */ |
7494 | return get_frame_register_signed | |
7495 | (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); | |
c906108c | 7496 | } |
14132e89 MR |
7497 | else |
7498 | return 0; /* Not a stub. */ | |
7499 | } | |
7500 | ||
7501 | /* If the PC is in __call_stub_* or __fn_stub*, this is one of the | |
7502 | compiler-generated call or call/return stubs. */ | |
7503 | if (strncmp (name, mips_str_fn_stub, strlen (mips_str_fn_stub)) == 0 | |
7504 | || strncmp (name, mips_str_call_stub, strlen (mips_str_call_stub)) == 0) | |
7505 | { | |
7506 | if (pc == start_addr) | |
7507 | /* This is the 'call' part of a call stub. Call this helper | |
7508 | to scan through this code for interesting instructions | |
7509 | and determine the final PC. */ | |
7510 | return mips_get_mips16_fn_stub_pc (frame, pc); | |
7511 | else | |
7512 | /* This is the 'return' part of a call stub. The return address | |
7513 | is in $18. */ | |
7514 | return get_frame_register_signed | |
7515 | (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); | |
c906108c | 7516 | } |
14132e89 MR |
7517 | |
7518 | return 0; /* Not a stub. */ | |
7519 | } | |
7520 | ||
7521 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
7522 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
7523 | ||
7524 | static int | |
7525 | mips_in_return_stub (struct gdbarch *gdbarch, CORE_ADDR pc, const char *name) | |
7526 | { | |
7527 | CORE_ADDR start_addr; | |
7528 | size_t prefixlen; | |
7529 | ||
7530 | /* Find the starting address of the function containing the PC. */ | |
7531 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
7532 | return 0; | |
7533 | ||
7534 | /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at | |
7535 | the start, i.e. after the JALR instruction, this is effectively | |
7536 | a return stub. */ | |
7537 | prefixlen = strlen (mips_str_mips16_call_stub); | |
7538 | if (pc != start_addr | |
7539 | && strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0 | |
7540 | && mips_is_stub_mode (name + prefixlen) | |
7541 | && name[prefixlen + 2] == '_' | |
7542 | && mips_is_stub_suffix (name + prefixlen + 3, 1)) | |
7543 | return 1; | |
7544 | ||
7545 | /* If the PC is in __call_stub_fp_* but not at the start, i.e. after | |
7546 | the JAL or JALR instruction, this is effectively a return stub. */ | |
7547 | prefixlen = strlen (mips_str_call_fp_stub); | |
7548 | if (pc != start_addr | |
7549 | && strncmp (name, mips_str_call_fp_stub, prefixlen) == 0) | |
7550 | return 1; | |
7551 | ||
7552 | /* Consume the .pic. prefix of any PIC stub, this function must return | |
7553 | true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub | |
7554 | or the call stub path will trigger in handle_inferior_event causing | |
7555 | it to go astray. */ | |
7556 | prefixlen = strlen (mips_str_pic); | |
7557 | if (strncmp (name, mips_str_pic, prefixlen) == 0) | |
7558 | name += prefixlen; | |
7559 | ||
7560 | /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */ | |
7561 | prefixlen = strlen (mips_str_mips16_ret_stub); | |
7562 | if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0 | |
7563 | && mips_is_stub_mode (name + prefixlen) | |
7564 | && name[prefixlen + 2] == '\0') | |
7565 | return 1; | |
7566 | ||
7567 | return 0; /* Not a stub. */ | |
c906108c SS |
7568 | } |
7569 | ||
db5f024e DJ |
7570 | /* If the current PC is the start of a non-PIC-to-PIC stub, return the |
7571 | PC of the stub target. The stub just loads $t9 and jumps to it, | |
7572 | so that $t9 has the correct value at function entry. */ | |
7573 | ||
7574 | static CORE_ADDR | |
7575 | mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
7576 | { | |
e17a4113 UW |
7577 | struct gdbarch *gdbarch = get_frame_arch (frame); |
7578 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
db5f024e DJ |
7579 | struct minimal_symbol *msym; |
7580 | int i; | |
7581 | gdb_byte stub_code[16]; | |
7582 | int32_t stub_words[4]; | |
7583 | ||
7584 | /* The stub for foo is named ".pic.foo", and is either two | |
7585 | instructions inserted before foo or a three instruction sequence | |
7586 | which jumps to foo. */ | |
7587 | msym = lookup_minimal_symbol_by_pc (pc); | |
7588 | if (msym == NULL | |
7589 | || SYMBOL_VALUE_ADDRESS (msym) != pc | |
7590 | || SYMBOL_LINKAGE_NAME (msym) == NULL | |
7591 | || strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) != 0) | |
7592 | return 0; | |
7593 | ||
7594 | /* A two-instruction header. */ | |
7595 | if (MSYMBOL_SIZE (msym) == 8) | |
7596 | return pc + 8; | |
7597 | ||
7598 | /* A three-instruction (plus delay slot) trampoline. */ | |
7599 | if (MSYMBOL_SIZE (msym) == 16) | |
7600 | { | |
7601 | if (target_read_memory (pc, stub_code, 16) != 0) | |
7602 | return 0; | |
7603 | for (i = 0; i < 4; i++) | |
e17a4113 UW |
7604 | stub_words[i] = extract_unsigned_integer (stub_code + i * 4, |
7605 | 4, byte_order); | |
db5f024e DJ |
7606 | |
7607 | /* A stub contains these instructions: | |
7608 | lui t9, %hi(target) | |
7609 | j target | |
7610 | addiu t9, t9, %lo(target) | |
7611 | nop | |
7612 | ||
7613 | This works even for N64, since stubs are only generated with | |
7614 | -msym32. */ | |
7615 | if ((stub_words[0] & 0xffff0000U) == 0x3c190000 | |
7616 | && (stub_words[1] & 0xfc000000U) == 0x08000000 | |
7617 | && (stub_words[2] & 0xffff0000U) == 0x27390000 | |
7618 | && stub_words[3] == 0x00000000) | |
34b192ce MR |
7619 | return ((((stub_words[0] & 0x0000ffff) << 16) |
7620 | + (stub_words[2] & 0x0000ffff)) ^ 0x8000) - 0x8000; | |
db5f024e DJ |
7621 | } |
7622 | ||
7623 | /* Not a recognized stub. */ | |
7624 | return 0; | |
7625 | } | |
7626 | ||
7627 | static CORE_ADDR | |
7628 | mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
7629 | { | |
14132e89 | 7630 | CORE_ADDR requested_pc = pc; |
db5f024e | 7631 | CORE_ADDR target_pc; |
14132e89 MR |
7632 | CORE_ADDR new_pc; |
7633 | ||
7634 | do | |
7635 | { | |
7636 | target_pc = pc; | |
db5f024e | 7637 | |
14132e89 MR |
7638 | new_pc = mips_skip_mips16_trampoline_code (frame, pc); |
7639 | if (new_pc) | |
7640 | { | |
7641 | pc = new_pc; | |
4cc0665f MR |
7642 | if (is_compact_addr (pc)) |
7643 | pc = unmake_compact_addr (pc); | |
14132e89 | 7644 | } |
db5f024e | 7645 | |
14132e89 MR |
7646 | new_pc = find_solib_trampoline_target (frame, pc); |
7647 | if (new_pc) | |
7648 | { | |
7649 | pc = new_pc; | |
4cc0665f MR |
7650 | if (is_compact_addr (pc)) |
7651 | pc = unmake_compact_addr (pc); | |
14132e89 | 7652 | } |
db5f024e | 7653 | |
14132e89 MR |
7654 | new_pc = mips_skip_pic_trampoline_code (frame, pc); |
7655 | if (new_pc) | |
7656 | { | |
7657 | pc = new_pc; | |
4cc0665f MR |
7658 | if (is_compact_addr (pc)) |
7659 | pc = unmake_compact_addr (pc); | |
14132e89 MR |
7660 | } |
7661 | } | |
7662 | while (pc != target_pc); | |
db5f024e | 7663 | |
14132e89 | 7664 | return pc != requested_pc ? pc : 0; |
db5f024e DJ |
7665 | } |
7666 | ||
a4b8ebc8 | 7667 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
f57d151a | 7668 | [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
7669 | |
7670 | static int | |
d3f73121 | 7671 | mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 7672 | { |
a4b8ebc8 | 7673 | int regnum; |
2f38ef89 | 7674 | if (num >= 0 && num < 32) |
a4b8ebc8 | 7675 | regnum = num; |
2f38ef89 | 7676 | else if (num >= 38 && num < 70) |
d3f73121 | 7677 | regnum = num + mips_regnum (gdbarch)->fp0 - 38; |
040b99fd | 7678 | else if (num == 70) |
d3f73121 | 7679 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 7680 | else if (num == 71) |
d3f73121 | 7681 | regnum = mips_regnum (gdbarch)->lo; |
1faeff08 MR |
7682 | else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 72 && num < 78) |
7683 | regnum = num + mips_regnum (gdbarch)->dspacc - 72; | |
2f38ef89 | 7684 | else |
a4b8ebc8 AC |
7685 | /* This will hopefully (eventually) provoke a warning. Should |
7686 | we be calling complaint() here? */ | |
d3f73121 MD |
7687 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
7688 | return gdbarch_num_regs (gdbarch) + regnum; | |
88c72b7d AC |
7689 | } |
7690 | ||
2f38ef89 | 7691 | |
a4b8ebc8 | 7692 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
f57d151a | 7693 | gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
7694 | |
7695 | static int | |
d3f73121 | 7696 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 7697 | { |
a4b8ebc8 | 7698 | int regnum; |
2f38ef89 | 7699 | if (num >= 0 && num < 32) |
a4b8ebc8 | 7700 | regnum = num; |
2f38ef89 | 7701 | else if (num >= 32 && num < 64) |
d3f73121 | 7702 | regnum = num + mips_regnum (gdbarch)->fp0 - 32; |
040b99fd | 7703 | else if (num == 64) |
d3f73121 | 7704 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 7705 | else if (num == 65) |
d3f73121 | 7706 | regnum = mips_regnum (gdbarch)->lo; |
1faeff08 MR |
7707 | else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 66 && num < 72) |
7708 | regnum = num + mips_regnum (gdbarch)->dspacc - 66; | |
2f38ef89 | 7709 | else |
a4b8ebc8 AC |
7710 | /* This will hopefully (eventually) provoke a warning. Should we |
7711 | be calling complaint() here? */ | |
d3f73121 MD |
7712 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
7713 | return gdbarch_num_regs (gdbarch) + regnum; | |
a4b8ebc8 AC |
7714 | } |
7715 | ||
7716 | static int | |
e7faf938 | 7717 | mips_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
a4b8ebc8 AC |
7718 | { |
7719 | /* Only makes sense to supply raw registers. */ | |
e7faf938 | 7720 | gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)); |
a4b8ebc8 AC |
7721 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to |
7722 | decide if it is valid. Should instead define a standard sim/gdb | |
7723 | register numbering scheme. */ | |
e7faf938 MD |
7724 | if (gdbarch_register_name (gdbarch, |
7725 | gdbarch_num_regs (gdbarch) + regnum) != NULL | |
7726 | && gdbarch_register_name (gdbarch, | |
025bb325 MS |
7727 | gdbarch_num_regs (gdbarch) |
7728 | + regnum)[0] != '\0') | |
a4b8ebc8 AC |
7729 | return regnum; |
7730 | else | |
6d82d43b | 7731 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
7732 | } |
7733 | ||
2f38ef89 | 7734 | |
4844f454 CV |
7735 | /* Convert an integer into an address. Extracting the value signed |
7736 | guarantees a correctly sign extended address. */ | |
fc0c74b1 AC |
7737 | |
7738 | static CORE_ADDR | |
79dd2d24 | 7739 | mips_integer_to_address (struct gdbarch *gdbarch, |
870cd05e | 7740 | struct type *type, const gdb_byte *buf) |
fc0c74b1 | 7741 | { |
e17a4113 UW |
7742 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7743 | return extract_signed_integer (buf, TYPE_LENGTH (type), byte_order); | |
fc0c74b1 AC |
7744 | } |
7745 | ||
82e91389 DJ |
7746 | /* Dummy virtual frame pointer method. This is no more or less accurate |
7747 | than most other architectures; we just need to be explicit about it, | |
7748 | because the pseudo-register gdbarch_sp_regnum will otherwise lead to | |
7749 | an assertion failure. */ | |
7750 | ||
7751 | static void | |
a54fba4c MD |
7752 | mips_virtual_frame_pointer (struct gdbarch *gdbarch, |
7753 | CORE_ADDR pc, int *reg, LONGEST *offset) | |
82e91389 DJ |
7754 | { |
7755 | *reg = MIPS_SP_REGNUM; | |
7756 | *offset = 0; | |
7757 | } | |
7758 | ||
caaa3122 DJ |
7759 | static void |
7760 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
7761 | { | |
7762 | enum mips_abi *abip = (enum mips_abi *) obj; | |
7763 | const char *name = bfd_get_section_name (abfd, sect); | |
7764 | ||
7765 | if (*abip != MIPS_ABI_UNKNOWN) | |
7766 | return; | |
7767 | ||
7768 | if (strncmp (name, ".mdebug.", 8) != 0) | |
7769 | return; | |
7770 | ||
7771 | if (strcmp (name, ".mdebug.abi32") == 0) | |
7772 | *abip = MIPS_ABI_O32; | |
7773 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
7774 | *abip = MIPS_ABI_N32; | |
62a49b2c | 7775 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 7776 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
7777 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
7778 | *abip = MIPS_ABI_O64; | |
7779 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
7780 | *abip = MIPS_ABI_EABI32; | |
7781 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
7782 | *abip = MIPS_ABI_EABI64; | |
7783 | else | |
8a3fe4f8 | 7784 | warning (_("unsupported ABI %s."), name + 8); |
caaa3122 DJ |
7785 | } |
7786 | ||
22e47e37 FF |
7787 | static void |
7788 | mips_find_long_section (bfd *abfd, asection *sect, void *obj) | |
7789 | { | |
7790 | int *lbp = (int *) obj; | |
7791 | const char *name = bfd_get_section_name (abfd, sect); | |
7792 | ||
7793 | if (strncmp (name, ".gcc_compiled_long32", 20) == 0) | |
7794 | *lbp = 32; | |
7795 | else if (strncmp (name, ".gcc_compiled_long64", 20) == 0) | |
7796 | *lbp = 64; | |
7797 | else if (strncmp (name, ".gcc_compiled_long", 18) == 0) | |
7798 | warning (_("unrecognized .gcc_compiled_longXX")); | |
7799 | } | |
7800 | ||
2e4ebe70 DJ |
7801 | static enum mips_abi |
7802 | global_mips_abi (void) | |
7803 | { | |
7804 | int i; | |
7805 | ||
7806 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
7807 | if (mips_abi_strings[i] == mips_abi_string) | |
7808 | return (enum mips_abi) i; | |
7809 | ||
e2e0b3e5 | 7810 | internal_error (__FILE__, __LINE__, _("unknown ABI string")); |
2e4ebe70 DJ |
7811 | } |
7812 | ||
4cc0665f MR |
7813 | /* Return the default compressed instruction set, either of MIPS16 |
7814 | or microMIPS, selected when none could have been determined from | |
7815 | the ELF header of the binary being executed (or no binary has been | |
7816 | selected. */ | |
7817 | ||
7818 | static enum mips_isa | |
7819 | global_mips_compression (void) | |
7820 | { | |
7821 | int i; | |
7822 | ||
7823 | for (i = 0; mips_compression_strings[i] != NULL; i++) | |
7824 | if (mips_compression_strings[i] == mips_compression_string) | |
7825 | return (enum mips_isa) i; | |
7826 | ||
7827 | internal_error (__FILE__, __LINE__, _("unknown compressed ISA string")); | |
7828 | } | |
7829 | ||
29709017 DJ |
7830 | static void |
7831 | mips_register_g_packet_guesses (struct gdbarch *gdbarch) | |
7832 | { | |
29709017 DJ |
7833 | /* If the size matches the set of 32-bit or 64-bit integer registers, |
7834 | assume that's what we've got. */ | |
4eb0ad19 DJ |
7835 | register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32); |
7836 | register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64); | |
29709017 DJ |
7837 | |
7838 | /* If the size matches the full set of registers GDB traditionally | |
7839 | knows about, including floating point, for either 32-bit or | |
7840 | 64-bit, assume that's what we've got. */ | |
4eb0ad19 DJ |
7841 | register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32); |
7842 | register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64); | |
29709017 DJ |
7843 | |
7844 | /* Otherwise we don't have a useful guess. */ | |
7845 | } | |
7846 | ||
f8b73d13 DJ |
7847 | static struct value * |
7848 | value_of_mips_user_reg (struct frame_info *frame, const void *baton) | |
7849 | { | |
7850 | const int *reg_p = baton; | |
7851 | return value_of_register (*reg_p, frame); | |
7852 | } | |
7853 | ||
c2d11a7d | 7854 | static struct gdbarch * |
6d82d43b | 7855 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 7856 | { |
c2d11a7d JM |
7857 | struct gdbarch *gdbarch; |
7858 | struct gdbarch_tdep *tdep; | |
7859 | int elf_flags; | |
2e4ebe70 | 7860 | enum mips_abi mips_abi, found_abi, wanted_abi; |
f8b73d13 | 7861 | int i, num_regs; |
8d5838b5 | 7862 | enum mips_fpu_type fpu_type; |
f8b73d13 | 7863 | struct tdesc_arch_data *tdesc_data = NULL; |
609ca2b9 | 7864 | int elf_fpu_type = 0; |
1faeff08 MR |
7865 | const char **reg_names; |
7866 | struct mips_regnum mips_regnum, *regnum; | |
4cc0665f | 7867 | enum mips_isa mips_isa; |
1faeff08 MR |
7868 | int dspacc; |
7869 | int dspctl; | |
7870 | ||
7871 | /* Fill in the OS dependent register numbers and names. */ | |
7872 | if (info.osabi == GDB_OSABI_IRIX) | |
7873 | { | |
7874 | mips_regnum.fp0 = 32; | |
7875 | mips_regnum.pc = 64; | |
7876 | mips_regnum.cause = 65; | |
7877 | mips_regnum.badvaddr = 66; | |
7878 | mips_regnum.hi = 67; | |
7879 | mips_regnum.lo = 68; | |
7880 | mips_regnum.fp_control_status = 69; | |
7881 | mips_regnum.fp_implementation_revision = 70; | |
7882 | mips_regnum.dspacc = dspacc = -1; | |
7883 | mips_regnum.dspctl = dspctl = -1; | |
7884 | num_regs = 71; | |
7885 | reg_names = mips_irix_reg_names; | |
7886 | } | |
7887 | else if (info.osabi == GDB_OSABI_LINUX) | |
7888 | { | |
7889 | mips_regnum.fp0 = 38; | |
7890 | mips_regnum.pc = 37; | |
7891 | mips_regnum.cause = 36; | |
7892 | mips_regnum.badvaddr = 35; | |
7893 | mips_regnum.hi = 34; | |
7894 | mips_regnum.lo = 33; | |
7895 | mips_regnum.fp_control_status = 70; | |
7896 | mips_regnum.fp_implementation_revision = 71; | |
7897 | mips_regnum.dspacc = -1; | |
7898 | mips_regnum.dspctl = -1; | |
7899 | dspacc = 72; | |
7900 | dspctl = 78; | |
7901 | num_regs = 79; | |
7902 | reg_names = mips_linux_reg_names; | |
7903 | } | |
7904 | else | |
7905 | { | |
7906 | mips_regnum.lo = MIPS_EMBED_LO_REGNUM; | |
7907 | mips_regnum.hi = MIPS_EMBED_HI_REGNUM; | |
7908 | mips_regnum.badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
7909 | mips_regnum.cause = MIPS_EMBED_CAUSE_REGNUM; | |
7910 | mips_regnum.pc = MIPS_EMBED_PC_REGNUM; | |
7911 | mips_regnum.fp0 = MIPS_EMBED_FP0_REGNUM; | |
7912 | mips_regnum.fp_control_status = 70; | |
7913 | mips_regnum.fp_implementation_revision = 71; | |
7914 | mips_regnum.dspacc = dspacc = -1; | |
7915 | mips_regnum.dspctl = dspctl = -1; | |
7916 | num_regs = MIPS_LAST_EMBED_REGNUM + 1; | |
7917 | if (info.bfd_arch_info != NULL | |
7918 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
7919 | reg_names = mips_tx39_reg_names; | |
7920 | else | |
7921 | reg_names = mips_generic_reg_names; | |
7922 | } | |
f8b73d13 DJ |
7923 | |
7924 | /* Check any target description for validity. */ | |
7925 | if (tdesc_has_registers (info.target_desc)) | |
7926 | { | |
7927 | static const char *const mips_gprs[] = { | |
7928 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
7929 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
7930 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
7931 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
7932 | }; | |
7933 | static const char *const mips_fprs[] = { | |
7934 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
7935 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
7936 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
7937 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
7938 | }; | |
7939 | ||
7940 | const struct tdesc_feature *feature; | |
7941 | int valid_p; | |
7942 | ||
7943 | feature = tdesc_find_feature (info.target_desc, | |
7944 | "org.gnu.gdb.mips.cpu"); | |
7945 | if (feature == NULL) | |
7946 | return NULL; | |
7947 | ||
7948 | tdesc_data = tdesc_data_alloc (); | |
7949 | ||
7950 | valid_p = 1; | |
7951 | for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) | |
7952 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
7953 | mips_gprs[i]); | |
7954 | ||
7955 | ||
7956 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 7957 | mips_regnum.lo, "lo"); |
f8b73d13 | 7958 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
1faeff08 | 7959 | mips_regnum.hi, "hi"); |
f8b73d13 | 7960 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
1faeff08 | 7961 | mips_regnum.pc, "pc"); |
f8b73d13 DJ |
7962 | |
7963 | if (!valid_p) | |
7964 | { | |
7965 | tdesc_data_cleanup (tdesc_data); | |
7966 | return NULL; | |
7967 | } | |
7968 | ||
7969 | feature = tdesc_find_feature (info.target_desc, | |
7970 | "org.gnu.gdb.mips.cp0"); | |
7971 | if (feature == NULL) | |
7972 | { | |
7973 | tdesc_data_cleanup (tdesc_data); | |
7974 | return NULL; | |
7975 | } | |
7976 | ||
7977 | valid_p = 1; | |
7978 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 7979 | mips_regnum.badvaddr, "badvaddr"); |
f8b73d13 DJ |
7980 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
7981 | MIPS_PS_REGNUM, "status"); | |
7982 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 7983 | mips_regnum.cause, "cause"); |
f8b73d13 DJ |
7984 | |
7985 | if (!valid_p) | |
7986 | { | |
7987 | tdesc_data_cleanup (tdesc_data); | |
7988 | return NULL; | |
7989 | } | |
7990 | ||
7991 | /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS | |
7992 | backend is not prepared for that, though. */ | |
7993 | feature = tdesc_find_feature (info.target_desc, | |
7994 | "org.gnu.gdb.mips.fpu"); | |
7995 | if (feature == NULL) | |
7996 | { | |
7997 | tdesc_data_cleanup (tdesc_data); | |
7998 | return NULL; | |
7999 | } | |
8000 | ||
8001 | valid_p = 1; | |
8002 | for (i = 0; i < 32; i++) | |
8003 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 8004 | i + mips_regnum.fp0, mips_fprs[i]); |
f8b73d13 DJ |
8005 | |
8006 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 MR |
8007 | mips_regnum.fp_control_status, |
8008 | "fcsr"); | |
8009 | valid_p | |
8010 | &= tdesc_numbered_register (feature, tdesc_data, | |
8011 | mips_regnum.fp_implementation_revision, | |
8012 | "fir"); | |
f8b73d13 DJ |
8013 | |
8014 | if (!valid_p) | |
8015 | { | |
8016 | tdesc_data_cleanup (tdesc_data); | |
8017 | return NULL; | |
8018 | } | |
8019 | ||
1faeff08 MR |
8020 | if (dspacc >= 0) |
8021 | { | |
8022 | feature = tdesc_find_feature (info.target_desc, | |
8023 | "org.gnu.gdb.mips.dsp"); | |
8024 | /* The DSP registers are optional; it's OK if they are absent. */ | |
8025 | if (feature != NULL) | |
8026 | { | |
8027 | i = 0; | |
8028 | valid_p = 1; | |
8029 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8030 | dspacc + i++, "hi1"); | |
8031 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8032 | dspacc + i++, "lo1"); | |
8033 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8034 | dspacc + i++, "hi2"); | |
8035 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8036 | dspacc + i++, "lo2"); | |
8037 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8038 | dspacc + i++, "hi3"); | |
8039 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8040 | dspacc + i++, "lo3"); | |
8041 | ||
8042 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8043 | dspctl, "dspctl"); | |
8044 | ||
8045 | if (!valid_p) | |
8046 | { | |
8047 | tdesc_data_cleanup (tdesc_data); | |
8048 | return NULL; | |
8049 | } | |
8050 | ||
8051 | mips_regnum.dspacc = dspacc; | |
8052 | mips_regnum.dspctl = dspctl; | |
8053 | } | |
8054 | } | |
8055 | ||
f8b73d13 DJ |
8056 | /* It would be nice to detect an attempt to use a 64-bit ABI |
8057 | when only 32-bit registers are provided. */ | |
1faeff08 | 8058 | reg_names = NULL; |
f8b73d13 | 8059 | } |
c2d11a7d | 8060 | |
ec03c1ac AC |
8061 | /* First of all, extract the elf_flags, if available. */ |
8062 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
8063 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
8064 | else if (arches != NULL) |
8065 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
8066 | else |
8067 | elf_flags = 0; | |
8068 | if (gdbarch_debug) | |
8069 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 8070 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 8071 | |
102182a9 | 8072 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
8073 | switch ((elf_flags & EF_MIPS_ABI)) |
8074 | { | |
8075 | case E_MIPS_ABI_O32: | |
ec03c1ac | 8076 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
8077 | break; |
8078 | case E_MIPS_ABI_O64: | |
ec03c1ac | 8079 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
8080 | break; |
8081 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 8082 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
8083 | break; |
8084 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 8085 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
8086 | break; |
8087 | default: | |
acdb74a0 | 8088 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 8089 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 8090 | else |
ec03c1ac | 8091 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
8092 | break; |
8093 | } | |
acdb74a0 | 8094 | |
caaa3122 | 8095 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
8096 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
8097 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 8098 | |
dc305454 | 8099 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
8100 | MIPS architecture (if there is one). */ |
8101 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
8102 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 8103 | |
32a6503c | 8104 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 8105 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
8106 | && info.bfd_arch_info != NULL |
8107 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
8108 | { | |
8109 | switch (info.bfd_arch_info->mach) | |
8110 | { | |
8111 | case bfd_mach_mips3900: | |
ec03c1ac | 8112 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
8113 | break; |
8114 | case bfd_mach_mips4100: | |
8115 | case bfd_mach_mips5000: | |
ec03c1ac | 8116 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 8117 | break; |
1d06468c EZ |
8118 | case bfd_mach_mips8000: |
8119 | case bfd_mach_mips10000: | |
32a6503c KB |
8120 | /* On Irix, ELF64 executables use the N64 ABI. The |
8121 | pseudo-sections which describe the ABI aren't present | |
8122 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
8123 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
8124 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 8125 | found_abi = MIPS_ABI_N64; |
28d169de | 8126 | else |
ec03c1ac | 8127 | found_abi = MIPS_ABI_N32; |
1d06468c | 8128 | break; |
bf64bfd6 AC |
8129 | } |
8130 | } | |
2e4ebe70 | 8131 | |
26c53e50 DJ |
8132 | /* Default 64-bit objects to N64 instead of O32. */ |
8133 | if (found_abi == MIPS_ABI_UNKNOWN | |
8134 | && info.abfd != NULL | |
8135 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
8136 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
8137 | found_abi = MIPS_ABI_N64; | |
8138 | ||
ec03c1ac AC |
8139 | if (gdbarch_debug) |
8140 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
8141 | found_abi); | |
8142 | ||
8143 | /* What has the user specified from the command line? */ | |
8144 | wanted_abi = global_mips_abi (); | |
8145 | if (gdbarch_debug) | |
8146 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
8147 | wanted_abi); | |
2e4ebe70 DJ |
8148 | |
8149 | /* Now that we have found what the ABI for this binary would be, | |
8150 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
8151 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
8152 | mips_abi = wanted_abi; | |
ec03c1ac AC |
8153 | else if (found_abi != MIPS_ABI_UNKNOWN) |
8154 | mips_abi = found_abi; | |
8155 | else | |
8156 | mips_abi = MIPS_ABI_O32; | |
8157 | if (gdbarch_debug) | |
8158 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
8159 | mips_abi); | |
2e4ebe70 | 8160 | |
4cc0665f MR |
8161 | /* Determine the default compressed ISA. */ |
8162 | if ((elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0 | |
8163 | && (elf_flags & EF_MIPS_ARCH_ASE_M16) == 0) | |
8164 | mips_isa = ISA_MICROMIPS; | |
8165 | else if ((elf_flags & EF_MIPS_ARCH_ASE_M16) != 0 | |
8166 | && (elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) == 0) | |
8167 | mips_isa = ISA_MIPS16; | |
8168 | else | |
8169 | mips_isa = global_mips_compression (); | |
8170 | mips_compression_string = mips_compression_strings[mips_isa]; | |
8171 | ||
ec03c1ac | 8172 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 8173 | if (gdbarch_debug) |
ec03c1ac | 8174 | fprintf_unfiltered (gdb_stdlog, |
025bb325 MS |
8175 | "mips_gdbarch_init: " |
8176 | "mips64_transfers_32bit_regs_p = %d\n", | |
ec03c1ac | 8177 | mips64_transfers_32bit_regs_p); |
0dadbba0 | 8178 | |
8d5838b5 | 8179 | /* Determine the MIPS FPU type. */ |
609ca2b9 DJ |
8180 | #ifdef HAVE_ELF |
8181 | if (info.abfd | |
8182 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
8183 | elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
8184 | Tag_GNU_MIPS_ABI_FP); | |
8185 | #endif /* HAVE_ELF */ | |
8186 | ||
8d5838b5 AC |
8187 | if (!mips_fpu_type_auto) |
8188 | fpu_type = mips_fpu_type; | |
609ca2b9 DJ |
8189 | else if (elf_fpu_type != 0) |
8190 | { | |
8191 | switch (elf_fpu_type) | |
8192 | { | |
8193 | case 1: | |
8194 | fpu_type = MIPS_FPU_DOUBLE; | |
8195 | break; | |
8196 | case 2: | |
8197 | fpu_type = MIPS_FPU_SINGLE; | |
8198 | break; | |
8199 | case 3: | |
8200 | default: | |
8201 | /* Soft float or unknown. */ | |
8202 | fpu_type = MIPS_FPU_NONE; | |
8203 | break; | |
8204 | } | |
8205 | } | |
8d5838b5 AC |
8206 | else if (info.bfd_arch_info != NULL |
8207 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
8208 | switch (info.bfd_arch_info->mach) | |
8209 | { | |
8210 | case bfd_mach_mips3900: | |
8211 | case bfd_mach_mips4100: | |
8212 | case bfd_mach_mips4111: | |
a9d61c86 | 8213 | case bfd_mach_mips4120: |
8d5838b5 AC |
8214 | fpu_type = MIPS_FPU_NONE; |
8215 | break; | |
8216 | case bfd_mach_mips4650: | |
8217 | fpu_type = MIPS_FPU_SINGLE; | |
8218 | break; | |
8219 | default: | |
8220 | fpu_type = MIPS_FPU_DOUBLE; | |
8221 | break; | |
8222 | } | |
8223 | else if (arches != NULL) | |
8224 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
8225 | else | |
8226 | fpu_type = MIPS_FPU_DOUBLE; | |
8227 | if (gdbarch_debug) | |
8228 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 8229 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 8230 | |
29709017 DJ |
8231 | /* Check for blatant incompatibilities. */ |
8232 | ||
8233 | /* If we have only 32-bit registers, then we can't debug a 64-bit | |
8234 | ABI. */ | |
8235 | if (info.target_desc | |
8236 | && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL | |
8237 | && mips_abi != MIPS_ABI_EABI32 | |
8238 | && mips_abi != MIPS_ABI_O32) | |
f8b73d13 DJ |
8239 | { |
8240 | if (tdesc_data != NULL) | |
8241 | tdesc_data_cleanup (tdesc_data); | |
8242 | return NULL; | |
8243 | } | |
29709017 | 8244 | |
025bb325 | 8245 | /* Try to find a pre-existing architecture. */ |
c2d11a7d JM |
8246 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
8247 | arches != NULL; | |
8248 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
8249 | { | |
8250 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 8251 | using. */ |
9103eae0 | 8252 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 8253 | continue; |
9103eae0 | 8254 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 8255 | continue; |
719ec221 AC |
8256 | /* Need to be pedantic about which register virtual size is |
8257 | used. */ | |
8258 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
8259 | != mips64_transfers_32bit_regs_p) | |
8260 | continue; | |
8d5838b5 AC |
8261 | /* Be pedantic about which FPU is selected. */ |
8262 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
8263 | continue; | |
f8b73d13 DJ |
8264 | |
8265 | if (tdesc_data != NULL) | |
8266 | tdesc_data_cleanup (tdesc_data); | |
4be87837 | 8267 | return arches->gdbarch; |
c2d11a7d JM |
8268 | } |
8269 | ||
102182a9 | 8270 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
8271 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
8272 | gdbarch = gdbarch_alloc (&info, tdep); | |
8273 | tdep->elf_flags = elf_flags; | |
719ec221 | 8274 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
8275 | tdep->found_abi = found_abi; |
8276 | tdep->mips_abi = mips_abi; | |
4cc0665f | 8277 | tdep->mips_isa = mips_isa; |
8d5838b5 | 8278 | tdep->mips_fpu_type = fpu_type; |
29709017 DJ |
8279 | tdep->register_size_valid_p = 0; |
8280 | tdep->register_size = 0; | |
50e8a0d5 HZ |
8281 | tdep->gregset = NULL; |
8282 | tdep->gregset64 = NULL; | |
8283 | tdep->fpregset = NULL; | |
8284 | tdep->fpregset64 = NULL; | |
29709017 DJ |
8285 | |
8286 | if (info.target_desc) | |
8287 | { | |
8288 | /* Some useful properties can be inferred from the target. */ | |
8289 | if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) | |
8290 | { | |
8291 | tdep->register_size_valid_p = 1; | |
8292 | tdep->register_size = 4; | |
8293 | } | |
8294 | else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) | |
8295 | { | |
8296 | tdep->register_size_valid_p = 1; | |
8297 | tdep->register_size = 8; | |
8298 | } | |
8299 | } | |
c2d11a7d | 8300 | |
102182a9 | 8301 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
8302 | set_gdbarch_short_bit (gdbarch, 16); |
8303 | set_gdbarch_int_bit (gdbarch, 32); | |
8304 | set_gdbarch_float_bit (gdbarch, 32); | |
8305 | set_gdbarch_double_bit (gdbarch, 64); | |
8306 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
8307 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
8308 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
8309 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 8310 | |
175ff332 HZ |
8311 | set_gdbarch_ax_pseudo_register_collect (gdbarch, |
8312 | mips_ax_pseudo_register_collect); | |
8313 | set_gdbarch_ax_pseudo_register_push_stack | |
8314 | (gdbarch, mips_ax_pseudo_register_push_stack); | |
8315 | ||
6d82d43b | 8316 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
8317 | mips_elf_make_msymbol_special); |
8318 | ||
1faeff08 MR |
8319 | regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, struct mips_regnum); |
8320 | *regnum = mips_regnum; | |
1faeff08 MR |
8321 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
8322 | set_gdbarch_num_regs (gdbarch, num_regs); | |
8323 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
8324 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
8325 | set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer); | |
8326 | tdep->mips_processor_reg_names = reg_names; | |
8327 | tdep->regnum = regnum; | |
fe29b929 | 8328 | |
0dadbba0 | 8329 | switch (mips_abi) |
c2d11a7d | 8330 | { |
0dadbba0 | 8331 | case MIPS_ABI_O32: |
25ab4790 | 8332 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 8333 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
4c7d22cb | 8334 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 8335 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 8336 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8337 | set_gdbarch_long_bit (gdbarch, 32); |
8338 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8339 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8340 | break; | |
0dadbba0 | 8341 | case MIPS_ABI_O64: |
25ab4790 | 8342 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
9c8fdbfa | 8343 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
4c7d22cb | 8344 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 8345 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 8346 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8347 | set_gdbarch_long_bit (gdbarch, 32); |
8348 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8349 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8350 | break; | |
0dadbba0 | 8351 | case MIPS_ABI_EABI32: |
25ab4790 | 8352 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 8353 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 8354 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8355 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 8356 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8357 | set_gdbarch_long_bit (gdbarch, 32); |
8358 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8359 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8360 | break; | |
0dadbba0 | 8361 | case MIPS_ABI_EABI64: |
25ab4790 | 8362 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 8363 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 8364 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8365 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 8366 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8367 | set_gdbarch_long_bit (gdbarch, 64); |
8368 | set_gdbarch_ptr_bit (gdbarch, 64); | |
8369 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8370 | break; | |
0dadbba0 | 8371 | case MIPS_ABI_N32: |
25ab4790 | 8372 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 8373 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 8374 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8375 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 8376 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
8377 | set_gdbarch_long_bit (gdbarch, 32); |
8378 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8379 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 8380 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 8381 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
28d169de KB |
8382 | break; |
8383 | case MIPS_ABI_N64: | |
25ab4790 | 8384 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 8385 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 8386 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8387 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
8388 | tdep->default_mask_address_p = 0; |
8389 | set_gdbarch_long_bit (gdbarch, 64); | |
8390 | set_gdbarch_ptr_bit (gdbarch, 64); | |
8391 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 8392 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 8393 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
0dadbba0 | 8394 | break; |
c2d11a7d | 8395 | default: |
e2e0b3e5 | 8396 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); |
c2d11a7d JM |
8397 | } |
8398 | ||
22e47e37 FF |
8399 | /* GCC creates a pseudo-section whose name specifies the size of |
8400 | longs, since -mlong32 or -mlong64 may be used independent of | |
8401 | other options. How those options affect pointer sizes is ABI and | |
8402 | architecture dependent, so use them to override the default sizes | |
8403 | set by the ABI. This table shows the relationship between ABI, | |
8404 | -mlongXX, and size of pointers: | |
8405 | ||
8406 | ABI -mlongXX ptr bits | |
8407 | --- -------- -------- | |
8408 | o32 32 32 | |
8409 | o32 64 32 | |
8410 | n32 32 32 | |
8411 | n32 64 64 | |
8412 | o64 32 32 | |
8413 | o64 64 64 | |
8414 | n64 32 32 | |
8415 | n64 64 64 | |
8416 | eabi32 32 32 | |
8417 | eabi32 64 32 | |
8418 | eabi64 32 32 | |
8419 | eabi64 64 64 | |
8420 | ||
8421 | Note that for o32 and eabi32, pointers are always 32 bits | |
8422 | regardless of any -mlongXX option. For all others, pointers and | |
025bb325 | 8423 | longs are the same, as set by -mlongXX or set by defaults. */ |
22e47e37 FF |
8424 | |
8425 | if (info.abfd != NULL) | |
8426 | { | |
8427 | int long_bit = 0; | |
8428 | ||
8429 | bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); | |
8430 | if (long_bit) | |
8431 | { | |
8432 | set_gdbarch_long_bit (gdbarch, long_bit); | |
8433 | switch (mips_abi) | |
8434 | { | |
8435 | case MIPS_ABI_O32: | |
8436 | case MIPS_ABI_EABI32: | |
8437 | break; | |
8438 | case MIPS_ABI_N32: | |
8439 | case MIPS_ABI_O64: | |
8440 | case MIPS_ABI_N64: | |
8441 | case MIPS_ABI_EABI64: | |
8442 | set_gdbarch_ptr_bit (gdbarch, long_bit); | |
8443 | break; | |
8444 | default: | |
8445 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); | |
8446 | } | |
8447 | } | |
8448 | } | |
8449 | ||
a5ea2558 AC |
8450 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
8451 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
8452 | comment: | |
8453 | ||
8454 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
8455 | flag in object files because to do so would make it impossible to | |
102182a9 | 8456 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 8457 | unnecessarily restrictive. |
361d1df0 | 8458 | |
a5ea2558 AC |
8459 | We could solve this problem by adding "-gp32" multilibs to gcc, |
8460 | but to set this flag before gcc is built with such multilibs will | |
8461 | break too many systems.'' | |
8462 | ||
8463 | But even more unhelpfully, the default linker output target for | |
8464 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
8465 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 8466 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
8467 | this flag to detect 32-bit mode would do the wrong thing given |
8468 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 8469 | as 32-bit programs by default. */ |
a5ea2558 | 8470 | |
6c997a34 | 8471 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 8472 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
c2d11a7d | 8473 | |
102182a9 MS |
8474 | /* Add/remove bits from an address. The MIPS needs be careful to |
8475 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
8476 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
8477 | ||
58dfe9ff AC |
8478 | /* Unwind the frame. */ |
8479 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
30244cd8 | 8480 | set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); |
b8a22b94 | 8481 | set_gdbarch_dummy_id (gdbarch, mips_dummy_id); |
10312cc4 | 8482 | |
102182a9 | 8483 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 8484 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
8485 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
8486 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
6d82d43b AC |
8487 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, |
8488 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 8489 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 8490 | |
025bb325 | 8491 | /* MIPS version of CALL_DUMMY. */ |
c2d11a7d | 8492 | |
2c76a0c7 JB |
8493 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
8494 | set_gdbarch_push_dummy_code (gdbarch, mips_push_dummy_code); | |
dc604539 | 8495 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 8496 | |
87783b8b AC |
8497 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
8498 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
8499 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
8500 | ||
f7b9e9fc AC |
8501 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
8502 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
4cc0665f MR |
8503 | set_gdbarch_remote_breakpoint_from_pc (gdbarch, |
8504 | mips_remote_breakpoint_from_pc); | |
c8cef75f MR |
8505 | set_gdbarch_adjust_breakpoint_address (gdbarch, |
8506 | mips_adjust_breakpoint_address); | |
f7b9e9fc AC |
8507 | |
8508 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 8509 | |
97ab0fdd MR |
8510 | set_gdbarch_in_function_epilogue_p (gdbarch, mips_in_function_epilogue_p); |
8511 | ||
fc0c74b1 AC |
8512 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
8513 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
8514 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 8515 | |
a4b8ebc8 | 8516 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 8517 | |
e11c53d2 | 8518 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 8519 | |
9dae60cc UW |
8520 | if (mips_abi == MIPS_ABI_N32) |
8521 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n32); | |
8522 | else if (mips_abi == MIPS_ABI_N64) | |
8523 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n64); | |
8524 | else | |
8525 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); | |
e5ab0dce | 8526 | |
d92524f1 PM |
8527 | /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint, |
8528 | HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint | |
3a3bc038 | 8529 | need to all be folded into the target vector. Since they are |
d92524f1 PM |
8530 | being used as guards for target_stopped_by_watchpoint, why not have |
8531 | target_stopped_by_watchpoint return the type of watchpoint that the code | |
3a3bc038 AC |
8532 | is sitting on? */ |
8533 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
8534 | ||
e7d6a6d2 | 8535 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
757a7cc6 | 8536 | |
14132e89 MR |
8537 | /* NOTE drow/2012-04-25: We overload the core solib trampoline code |
8538 | to support MIPS16. This is a bad thing. Make sure not to do it | |
8539 | if we have an OS ABI that actually supports shared libraries, since | |
8540 | shared library support is more important. If we have an OS someday | |
8541 | that supports both shared libraries and MIPS16, we'll have to find | |
8542 | a better place for these. | |
8543 | macro/2012-04-25: But that applies to return trampolines only and | |
8544 | currently no MIPS OS ABI uses shared libraries that have them. */ | |
8545 | set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); | |
8546 | ||
025bb325 MS |
8547 | set_gdbarch_single_step_through_delay (gdbarch, |
8548 | mips_single_step_through_delay); | |
3352ef37 | 8549 | |
0d5de010 DJ |
8550 | /* Virtual tables. */ |
8551 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
8552 | ||
29709017 DJ |
8553 | mips_register_g_packet_guesses (gdbarch); |
8554 | ||
6de918a6 | 8555 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
822b6570 | 8556 | info.tdep_info = (void *) tdesc_data; |
6de918a6 | 8557 | gdbarch_init_osabi (info, gdbarch); |
757a7cc6 | 8558 | |
9aac7884 MR |
8559 | /* The hook may have adjusted num_regs, fetch the final value and |
8560 | set pc_regnum and sp_regnum now that it has been fixed. */ | |
9aac7884 MR |
8561 | num_regs = gdbarch_num_regs (gdbarch); |
8562 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); | |
8563 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
8564 | ||
5792a79b | 8565 | /* Unwind the frame. */ |
b8a22b94 DJ |
8566 | dwarf2_append_unwinders (gdbarch); |
8567 | frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind); | |
8568 | frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind); | |
4cc0665f | 8569 | frame_unwind_append_unwinder (gdbarch, &mips_micro_frame_unwind); |
b8a22b94 | 8570 | frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind); |
2bd0c3d7 | 8571 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
eec63939 | 8572 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
45c9dd44 | 8573 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
4cc0665f | 8574 | frame_base_append_sniffer (gdbarch, mips_micro_frame_base_sniffer); |
45c9dd44 | 8575 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); |
5792a79b | 8576 | |
f8b73d13 DJ |
8577 | if (tdesc_data) |
8578 | { | |
8579 | set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); | |
7cc46491 | 8580 | tdesc_use_registers (gdbarch, info.target_desc, tdesc_data); |
f8b73d13 DJ |
8581 | |
8582 | /* Override the normal target description methods to handle our | |
8583 | dual real and pseudo registers. */ | |
8584 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
025bb325 MS |
8585 | set_gdbarch_register_reggroup_p (gdbarch, |
8586 | mips_tdesc_register_reggroup_p); | |
f8b73d13 DJ |
8587 | |
8588 | num_regs = gdbarch_num_regs (gdbarch); | |
8589 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
8590 | set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs); | |
8591 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
8592 | } | |
8593 | ||
8594 | /* Add ABI-specific aliases for the registers. */ | |
8595 | if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) | |
8596 | for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++) | |
8597 | user_reg_add (gdbarch, mips_n32_n64_aliases[i].name, | |
8598 | value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); | |
8599 | else | |
8600 | for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) | |
8601 | user_reg_add (gdbarch, mips_o32_aliases[i].name, | |
8602 | value_of_mips_user_reg, &mips_o32_aliases[i].regnum); | |
8603 | ||
8604 | /* Add some other standard aliases. */ | |
8605 | for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) | |
8606 | user_reg_add (gdbarch, mips_register_aliases[i].name, | |
8607 | value_of_mips_user_reg, &mips_register_aliases[i].regnum); | |
8608 | ||
865093a3 AR |
8609 | for (i = 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++) |
8610 | user_reg_add (gdbarch, mips_numeric_register_aliases[i].name, | |
8611 | value_of_mips_user_reg, | |
8612 | &mips_numeric_register_aliases[i].regnum); | |
8613 | ||
4b9b3959 AC |
8614 | return gdbarch; |
8615 | } | |
8616 | ||
2e4ebe70 | 8617 | static void |
6d82d43b | 8618 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
8619 | { |
8620 | struct gdbarch_info info; | |
8621 | ||
8622 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
8623 | mips_gdbarch_init will take care of the rest. */ | |
8624 | gdbarch_info_init (&info); | |
8625 | gdbarch_update_p (info); | |
8626 | } | |
8627 | ||
ad188201 KB |
8628 | /* Print out which MIPS ABI is in use. */ |
8629 | ||
8630 | static void | |
1f8ca57c JB |
8631 | show_mips_abi (struct ui_file *file, |
8632 | int from_tty, | |
8633 | struct cmd_list_element *ignored_cmd, | |
8634 | const char *ignored_value) | |
ad188201 | 8635 | { |
1cf3db46 | 8636 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips) |
1f8ca57c JB |
8637 | fprintf_filtered |
8638 | (file, | |
8639 | "The MIPS ABI is unknown because the current architecture " | |
8640 | "is not MIPS.\n"); | |
ad188201 KB |
8641 | else |
8642 | { | |
8643 | enum mips_abi global_abi = global_mips_abi (); | |
1cf3db46 | 8644 | enum mips_abi actual_abi = mips_abi (target_gdbarch); |
ad188201 KB |
8645 | const char *actual_abi_str = mips_abi_strings[actual_abi]; |
8646 | ||
8647 | if (global_abi == MIPS_ABI_UNKNOWN) | |
1f8ca57c JB |
8648 | fprintf_filtered |
8649 | (file, | |
8650 | "The MIPS ABI is set automatically (currently \"%s\").\n", | |
6d82d43b | 8651 | actual_abi_str); |
ad188201 | 8652 | else if (global_abi == actual_abi) |
1f8ca57c JB |
8653 | fprintf_filtered |
8654 | (file, | |
8655 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6d82d43b | 8656 | actual_abi_str); |
ad188201 KB |
8657 | else |
8658 | { | |
8659 | /* Probably shouldn't happen... */ | |
025bb325 MS |
8660 | fprintf_filtered (file, |
8661 | "The (auto detected) MIPS ABI \"%s\" is in use " | |
8662 | "even though the user setting was \"%s\".\n", | |
6d82d43b | 8663 | actual_abi_str, mips_abi_strings[global_abi]); |
ad188201 KB |
8664 | } |
8665 | } | |
8666 | } | |
8667 | ||
4cc0665f MR |
8668 | /* Print out which MIPS compressed ISA encoding is used. */ |
8669 | ||
8670 | static void | |
8671 | show_mips_compression (struct ui_file *file, int from_tty, | |
8672 | struct cmd_list_element *c, const char *value) | |
8673 | { | |
8674 | fprintf_filtered (file, _("The compressed ISA encoding used is %s.\n"), | |
8675 | value); | |
8676 | } | |
8677 | ||
4b9b3959 | 8678 | static void |
72a155b4 | 8679 | mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
4b9b3959 | 8680 | { |
72a155b4 | 8681 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4b9b3959 | 8682 | if (tdep != NULL) |
c2d11a7d | 8683 | { |
acdb74a0 AC |
8684 | int ef_mips_arch; |
8685 | int ef_mips_32bitmode; | |
f49e4e6d | 8686 | /* Determine the ISA. */ |
acdb74a0 AC |
8687 | switch (tdep->elf_flags & EF_MIPS_ARCH) |
8688 | { | |
8689 | case E_MIPS_ARCH_1: | |
8690 | ef_mips_arch = 1; | |
8691 | break; | |
8692 | case E_MIPS_ARCH_2: | |
8693 | ef_mips_arch = 2; | |
8694 | break; | |
8695 | case E_MIPS_ARCH_3: | |
8696 | ef_mips_arch = 3; | |
8697 | break; | |
8698 | case E_MIPS_ARCH_4: | |
93d56215 | 8699 | ef_mips_arch = 4; |
acdb74a0 AC |
8700 | break; |
8701 | default: | |
93d56215 | 8702 | ef_mips_arch = 0; |
acdb74a0 AC |
8703 | break; |
8704 | } | |
f49e4e6d | 8705 | /* Determine the size of a pointer. */ |
acdb74a0 | 8706 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); |
4b9b3959 AC |
8707 | fprintf_unfiltered (file, |
8708 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 8709 | tdep->elf_flags); |
4b9b3959 | 8710 | fprintf_unfiltered (file, |
acdb74a0 AC |
8711 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
8712 | ef_mips_32bitmode); | |
8713 | fprintf_unfiltered (file, | |
8714 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
8715 | ef_mips_arch); | |
8716 | fprintf_unfiltered (file, | |
8717 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 8718 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b | 8719 | fprintf_unfiltered (file, |
025bb325 MS |
8720 | "mips_dump_tdep: " |
8721 | "mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 8722 | mips_mask_address_p (tdep), |
4014092b | 8723 | tdep->default_mask_address_p); |
c2d11a7d | 8724 | } |
4b9b3959 AC |
8725 | fprintf_unfiltered (file, |
8726 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
8727 | MIPS_DEFAULT_FPU_TYPE, | |
8728 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
8729 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
8730 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
8731 | : "???")); | |
74ed0bb4 MD |
8732 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", |
8733 | MIPS_EABI (gdbarch)); | |
4b9b3959 AC |
8734 | fprintf_unfiltered (file, |
8735 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
74ed0bb4 MD |
8736 | MIPS_FPU_TYPE (gdbarch), |
8737 | (MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_NONE ? "none" | |
8738 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_SINGLE ? "single" | |
8739 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_DOUBLE ? "double" | |
4b9b3959 | 8740 | : "???")); |
c2d11a7d JM |
8741 | } |
8742 | ||
025bb325 | 8743 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 8744 | |
c906108c | 8745 | void |
acdb74a0 | 8746 | _initialize_mips_tdep (void) |
c906108c SS |
8747 | { |
8748 | static struct cmd_list_element *mipsfpulist = NULL; | |
8749 | struct cmd_list_element *c; | |
8750 | ||
6d82d43b | 8751 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
8752 | if (MIPS_ABI_LAST + 1 |
8753 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
e2e0b3e5 | 8754 | internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync")); |
2e4ebe70 | 8755 | |
4b9b3959 | 8756 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 8757 | |
8d5f9dcb DJ |
8758 | mips_pdr_data = register_objfile_data (); |
8759 | ||
4eb0ad19 DJ |
8760 | /* Create feature sets with the appropriate properties. The values |
8761 | are not important. */ | |
8762 | mips_tdesc_gp32 = allocate_target_description (); | |
8763 | set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, ""); | |
8764 | ||
8765 | mips_tdesc_gp64 = allocate_target_description (); | |
8766 | set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, ""); | |
8767 | ||
025bb325 | 8768 | /* Add root prefix command for all "set mips"/"show mips" commands. */ |
a5ea2558 | 8769 | add_prefix_cmd ("mips", no_class, set_mips_command, |
1bedd215 | 8770 | _("Various MIPS specific commands."), |
a5ea2558 AC |
8771 | &setmipscmdlist, "set mips ", 0, &setlist); |
8772 | ||
8773 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
1bedd215 | 8774 | _("Various MIPS specific commands."), |
a5ea2558 AC |
8775 | &showmipscmdlist, "show mips ", 0, &showlist); |
8776 | ||
025bb325 | 8777 | /* Allow the user to override the ABI. */ |
7ab04401 AC |
8778 | add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, |
8779 | &mips_abi_string, _("\ | |
8780 | Set the MIPS ABI used by this program."), _("\ | |
8781 | Show the MIPS ABI used by this program."), _("\ | |
8782 | This option can be set to one of:\n\ | |
8783 | auto - the default ABI associated with the current binary\n\ | |
8784 | o32\n\ | |
8785 | o64\n\ | |
8786 | n32\n\ | |
8787 | n64\n\ | |
8788 | eabi32\n\ | |
8789 | eabi64"), | |
8790 | mips_abi_update, | |
8791 | show_mips_abi, | |
8792 | &setmipscmdlist, &showmipscmdlist); | |
2e4ebe70 | 8793 | |
4cc0665f MR |
8794 | /* Allow the user to set the ISA to assume for compressed code if ELF |
8795 | file flags don't tell or there is no program file selected. This | |
8796 | setting is updated whenever unambiguous ELF file flags are interpreted, | |
8797 | and carried over to subsequent sessions. */ | |
8798 | add_setshow_enum_cmd ("compression", class_obscure, mips_compression_strings, | |
8799 | &mips_compression_string, _("\ | |
8800 | Set the compressed ISA encoding used by MIPS code."), _("\ | |
8801 | Show the compressed ISA encoding used by MIPS code."), _("\ | |
8802 | Select the compressed ISA encoding used in functions that have no symbol\n\ | |
8803 | information available. The encoding can be set to either of:\n\ | |
8804 | mips16\n\ | |
8805 | micromips\n\ | |
8806 | and is updated automatically from ELF file flags if available."), | |
8807 | mips_abi_update, | |
8808 | show_mips_compression, | |
8809 | &setmipscmdlist, &showmipscmdlist); | |
8810 | ||
c906108c SS |
8811 | /* Let the user turn off floating point and set the fence post for |
8812 | heuristic_proc_start. */ | |
8813 | ||
8814 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
1bedd215 | 8815 | _("Set use of MIPS floating-point coprocessor."), |
c906108c SS |
8816 | &mipsfpulist, "set mipsfpu ", 0, &setlist); |
8817 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
1a966eab | 8818 | _("Select single-precision MIPS floating-point coprocessor."), |
c906108c SS |
8819 | &mipsfpulist); |
8820 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
1a966eab | 8821 | _("Select double-precision MIPS floating-point coprocessor."), |
c906108c SS |
8822 | &mipsfpulist); |
8823 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
8824 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
8825 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
8826 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
1a966eab | 8827 | _("Select no MIPS floating-point coprocessor."), &mipsfpulist); |
c906108c SS |
8828 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
8829 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
8830 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
8831 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
1a966eab | 8832 | _("Select MIPS floating-point coprocessor automatically."), |
c906108c SS |
8833 | &mipsfpulist); |
8834 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
1a966eab | 8835 | _("Show current use of MIPS floating-point coprocessor target."), |
c906108c SS |
8836 | &showlist); |
8837 | ||
c906108c SS |
8838 | /* We really would like to have both "0" and "unlimited" work, but |
8839 | command.c doesn't deal with that. So make it a var_zinteger | |
8840 | because the user can always use "999999" or some such for unlimited. */ | |
6bcadd06 | 8841 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
7915a72c AC |
8842 | &heuristic_fence_post, _("\ |
8843 | Set the distance searched for the start of a function."), _("\ | |
8844 | Show the distance searched for the start of a function."), _("\ | |
c906108c SS |
8845 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
8846 | program for the start of a function. This command sets the distance of the\n\ | |
7915a72c | 8847 | search. The only need to set it is when debugging a stripped executable."), |
2c5b56ce | 8848 | reinit_frame_cache_sfunc, |
025bb325 MS |
8849 | NULL, /* FIXME: i18n: The distance searched for |
8850 | the start of a function is %s. */ | |
6bcadd06 | 8851 | &setlist, &showlist); |
c906108c SS |
8852 | |
8853 | /* Allow the user to control whether the upper bits of 64-bit | |
8854 | addresses should be zeroed. */ | |
7915a72c AC |
8855 | add_setshow_auto_boolean_cmd ("mask-address", no_class, |
8856 | &mask_address_var, _("\ | |
8857 | Set zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
8858 | Show zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
cce7e648 | 8859 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\ |
7915a72c | 8860 | allow GDB to determine the correct value."), |
08546159 AC |
8861 | NULL, show_mask_address, |
8862 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
8863 | |
8864 | /* Allow the user to control the size of 32 bit registers within the | |
8865 | raw remote packet. */ | |
b3f42336 | 8866 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
7915a72c AC |
8867 | &mips64_transfers_32bit_regs_p, _("\ |
8868 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
8869 | _("\ | |
8870 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
8871 | _("\ | |
719ec221 AC |
8872 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
8873 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
7915a72c | 8874 | 64 bits for others. Use \"off\" to disable compatibility mode"), |
2c5b56ce | 8875 | set_mips64_transfers_32bit_regs, |
025bb325 MS |
8876 | NULL, /* FIXME: i18n: Compatibility with 64-bit |
8877 | MIPS target that transfers 32-bit | |
8878 | quantities is %s. */ | |
7915a72c | 8879 | &setlist, &showlist); |
9ace0497 | 8880 | |
025bb325 | 8881 | /* Debug this files internals. */ |
6bcadd06 | 8882 | add_setshow_zinteger_cmd ("mips", class_maintenance, |
7915a72c AC |
8883 | &mips_debug, _("\ |
8884 | Set mips debugging."), _("\ | |
8885 | Show mips debugging."), _("\ | |
8886 | When non-zero, mips specific debugging is enabled."), | |
2c5b56ce | 8887 | NULL, |
025bb325 MS |
8888 | NULL, /* FIXME: i18n: Mips debugging is |
8889 | currently %s. */ | |
6bcadd06 | 8890 | &setdebuglist, &showdebuglist); |
c906108c | 8891 | } |