Commit | Line | Data |
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7d9884b9 | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
a00dfa36 | 2 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998 |
0434c1a0 | 3 | Free Software Foundation, Inc. |
bd5635a1 RP |
4 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
5 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
6 | ||
7 | This file is part of GDB. | |
8 | ||
361bf6ee | 9 | This program is free software; you can redistribute it and/or modify |
bd5635a1 | 10 | it under the terms of the GNU General Public License as published by |
361bf6ee JG |
11 | the Free Software Foundation; either version 2 of the License, or |
12 | (at your option) any later version. | |
bd5635a1 | 13 | |
361bf6ee | 14 | This program is distributed in the hope that it will be useful, |
bd5635a1 RP |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
361bf6ee | 20 | along with this program; if not, write to the Free Software |
09af5868 | 21 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ |
bd5635a1 | 22 | |
bd5635a1 | 23 | #include "defs.h" |
09af5868 | 24 | #include "gdb_string.h" |
bd5635a1 RP |
25 | #include "frame.h" |
26 | #include "inferior.h" | |
27 | #include "symtab.h" | |
28 | #include "value.h" | |
29 | #include "gdbcmd.h" | |
ef08856f | 30 | #include "language.h" |
bd5635a1 | 31 | #include "gdbcore.h" |
62a469e1 SG |
32 | #include "symfile.h" |
33 | #include "objfiles.h" | |
3fed1c4a | 34 | #include "gdbtypes.h" |
28444bf3 | 35 | #include "target.h" |
bd5635a1 | 36 | |
ee5fb959 | 37 | #include "opcode/mips.h" |
ff6f2f57 AC |
38 | /* start-sanitize-carp start-sanitize-vr4xxx */ |
39 | #include "elf/mips.h" | |
40 | #include "elf-bfd.h" | |
41 | ||
1fe2e66a AC |
42 | /* end-sanitize-carp end-sanitize-vr4xxx */ |
43 | ||
44 | /* Some MIPS boards don't support floating point, so we permit the | |
45 | user to turn it off. */ | |
46 | ||
47 | enum mips_fpu_type | |
48 | { | |
49 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
50 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
51 | MIPS_FPU_NONE /* No floating point. */ | |
52 | }; | |
53 | ||
4ef1f467 DT |
54 | #ifndef MIPS_DEFAULT_FPU_TYPE |
55 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
56 | #endif | |
1fe2e66a | 57 | static int mips_fpu_type_auto = 1; |
1fe2e66a | 58 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; |
1fe2e66a AC |
59 | #define MIPS_FPU_TYPE mips_fpu_type |
60 | ||
61 | /* start-sanitize-carp start-sanitize-vr4xxx */ | |
62 | ||
ff6f2f57 AC |
63 | /* MIPS specific per-architecture information */ |
64 | struct gdbarch_tdep | |
65 | { | |
66 | int elf_abi; | |
67 | /* mips options */ | |
68 | int mips_eabi; | |
1fe2e66a | 69 | enum mips_fpu_type mips_fpu_type; |
ff6f2f57 AC |
70 | int mips_last_arg_regnum; |
71 | int mips_last_fp_arg_regnum; | |
72 | }; | |
73 | ||
74 | #if GDB_MULTI_ARCH | |
75 | #undef MIPS_EABI | |
76 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_eabi) | |
77 | #endif | |
78 | ||
79 | #if GDB_MULTI_ARCH | |
80 | #undef MIPS_LAST_FP_ARG_REGNUM | |
81 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) | |
82 | #endif | |
83 | ||
84 | #if GDB_MULTI_ARCH | |
85 | #undef MIPS_LAST_ARG_REGNUM | |
86 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) | |
87 | #endif | |
88 | ||
1fe2e66a AC |
89 | #if GDB_MULTI_ARCH |
90 | #undef MIPS_FPU_TYPE | |
91 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) | |
92 | #endif | |
93 | ||
2e64ee9a | 94 | /* end-sanitize-carp end-sanitize-vr4xxx */ |
ee5fb959 | 95 | |
28444bf3 | 96 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
70126bf9 | 97 | |
a00dfa36 MS |
98 | /* Do not use "TARGET_IS_MIPS64" to test the size of floating point registers */ |
99 | #define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8) | |
100 | ||
002a422b | 101 | #if 0 |
ee5fb959 | 102 | static int mips_in_lenient_prologue PARAMS ((CORE_ADDR, CORE_ADDR)); |
002a422b | 103 | #endif |
ee5fb959 | 104 | |
912e805f | 105 | int gdb_print_insn_mips PARAMS ((bfd_vma, disassemble_info *)); |
28444bf3 | 106 | |
f2bf454e FF |
107 | static void mips_print_register PARAMS ((int, int)); |
108 | ||
109 | static mips_extra_func_info_t | |
110 | heuristic_proc_desc PARAMS ((CORE_ADDR, CORE_ADDR, struct frame_info *)); | |
111 | ||
112 | static CORE_ADDR heuristic_proc_start PARAMS ((CORE_ADDR)); | |
113 | ||
28444bf3 | 114 | static CORE_ADDR read_next_frame_reg PARAMS ((struct frame_info *, int)); |
f2bf454e | 115 | |
9f9f94aa SS |
116 | void mips_set_processor_type_command PARAMS ((char *, int)); |
117 | ||
1d9489c1 JK |
118 | int mips_set_processor_type PARAMS ((char *)); |
119 | ||
120 | static void mips_show_processor_type_command PARAMS ((char *, int)); | |
121 | ||
9f9f94aa SS |
122 | static void reinit_frame_cache_sfunc PARAMS ((char *, int, |
123 | struct cmd_list_element *)); | |
124 | ||
f2bf454e FF |
125 | static mips_extra_func_info_t |
126 | find_proc_desc PARAMS ((CORE_ADDR pc, struct frame_info *next_frame)); | |
127 | ||
128 | static CORE_ADDR after_prologue PARAMS ((CORE_ADDR pc, | |
129 | mips_extra_func_info_t proc_desc)); | |
130 | ||
9f9f94aa SS |
131 | /* This value is the model of MIPS in use. It is derived from the value |
132 | of the PrID register. */ | |
133 | ||
134 | char *mips_processor_type; | |
135 | ||
136 | char *tmp_mips_processor_type; | |
137 | ||
9f9f94aa SS |
138 | /* A set of original names, to be used when restoring back to generic |
139 | registers from a specific set. */ | |
140 | ||
141 | char *mips_generic_reg_names[] = REGISTER_NAMES; | |
142 | ||
143 | /* Names of IDT R3041 registers. */ | |
144 | ||
145 | char *mips_r3041_reg_names[] = { | |
146 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
147 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
148 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
149 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
150 | "sr", "lo", "hi", "bad", "cause","pc", | |
151 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
152 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
153 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
154 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
155 | "fsr", "fir", "fp", "", | |
156 | "", "", "bus", "ccfg", "", "", "", "", | |
157 | "", "", "port", "cmp", "", "", "epc", "prid", | |
158 | }; | |
159 | ||
160 | /* Names of IDT R3051 registers. */ | |
161 | ||
162 | char *mips_r3051_reg_names[] = { | |
163 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
164 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
165 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
166 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
167 | "sr", "lo", "hi", "bad", "cause","pc", | |
168 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
169 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
170 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
171 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
172 | "fsr", "fir", "fp", "", | |
173 | "inx", "rand", "elo", "", "ctxt", "", "", "", | |
174 | "", "", "ehi", "", "", "", "epc", "prid", | |
175 | }; | |
176 | ||
177 | /* Names of IDT R3081 registers. */ | |
178 | ||
179 | char *mips_r3081_reg_names[] = { | |
180 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
181 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
182 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
183 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
184 | "sr", "lo", "hi", "bad", "cause","pc", | |
185 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
186 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
187 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
188 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
189 | "fsr", "fir", "fp", "", | |
190 | "inx", "rand", "elo", "cfg", "ctxt", "", "", "", | |
191 | "", "", "ehi", "", "", "", "epc", "prid", | |
192 | }; | |
193 | ||
e4dbd248 PS |
194 | /* Names of LSI 33k registers. */ |
195 | ||
196 | char *mips_lsi33k_reg_names[] = { | |
197 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
198 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
199 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
200 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
201 | "epc", "hi", "lo", "sr", "cause","badvaddr", | |
202 | "dcic", "bpc", "bda", "", "", "", "", "", | |
203 | "", "", "", "", "", "", "", "", | |
204 | "", "", "", "", "", "", "", "", | |
205 | "", "", "", "", "", "", "", "", | |
206 | "", "", "", "", | |
207 | "", "", "", "", "", "", "", "", | |
208 | "", "", "", "", "", "", "", "", | |
209 | }; | |
210 | ||
9f9f94aa SS |
211 | struct { |
212 | char *name; | |
213 | char **regnames; | |
214 | } mips_processor_type_table[] = { | |
215 | { "generic", mips_generic_reg_names }, | |
216 | { "r3041", mips_r3041_reg_names }, | |
217 | { "r3051", mips_r3051_reg_names }, | |
218 | { "r3071", mips_r3081_reg_names }, | |
219 | { "r3081", mips_r3081_reg_names }, | |
e4dbd248 | 220 | { "lsi33k", mips_lsi33k_reg_names }, |
9f9f94aa SS |
221 | { NULL, NULL } |
222 | }; | |
223 | ||
f9f8c14b MA |
224 | /* Table to translate MIPS16 register field to actual register number. */ |
225 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; | |
226 | ||
3127785a RP |
227 | /* Heuristic_proc_start may hunt through the text section for a long |
228 | time across a 2400 baud serial line. Allows the user to limit this | |
229 | search. */ | |
9f9f94aa | 230 | |
3127785a RP |
231 | static unsigned int heuristic_fence_post = 0; |
232 | ||
0f552c5f | 233 | #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ |
28444bf3 | 234 | #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */ |
0f552c5f JG |
235 | #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) |
236 | #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) | |
af774411 | 237 | #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust) |
0f552c5f JG |
238 | #define PROC_REG_MASK(proc) ((proc)->pdr.regmask) |
239 | #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) | |
240 | #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) | |
241 | #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) | |
242 | #define PROC_PC_REG(proc) ((proc)->pdr.pcreg) | |
243 | #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) | |
bd5635a1 | 244 | #define _PROC_MAGIC_ 0x0F0F0F0F |
0f552c5f JG |
245 | #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_) |
246 | #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_) | |
bd5635a1 RP |
247 | |
248 | struct linked_proc_info | |
249 | { | |
250 | struct mips_extra_func_info info; | |
251 | struct linked_proc_info *next; | |
dac4929a | 252 | } *linked_proc_desc_table = NULL; |
bd5635a1 | 253 | |
f2bf454e | 254 | |
98760eab AC |
255 | /* Should the upper word of 64-bit addresses be zeroed? */ |
256 | static int mask_address_p = 1; | |
257 | ||
258 | /* Should call_function allocate stack space for a struct return? */ | |
259 | int | |
260 | mips_use_struct_convention (gcc_p, type) | |
261 | int gcc_p; | |
262 | struct type *type; | |
263 | { | |
264 | if (MIPS_EABI) | |
265 | return (TYPE_LENGTH (type) > 2 * MIPS_REGSIZE); | |
266 | else | |
267 | return 1; /* Structures are returned by ref in extra arg0 */ | |
268 | } | |
269 | ||
899c4021 MA |
270 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
271 | ||
272 | static int | |
273 | pc_is_mips16 (bfd_vma memaddr) | |
274 | { | |
275 | struct minimal_symbol *sym; | |
276 | ||
277 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
278 | if (IS_MIPS16_ADDR (memaddr)) | |
279 | return 1; | |
280 | ||
281 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
282 | the high bit of the info field. Use this to decide if the function is | |
283 | MIPS16 or normal MIPS. */ | |
284 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
285 | if (sym) | |
286 | return MSYMBOL_IS_SPECIAL (sym); | |
287 | else | |
288 | return 0; | |
289 | } | |
290 | ||
291 | ||
f2bf454e FF |
292 | /* This returns the PC of the first inst after the prologue. If we can't |
293 | find the prologue, then return 0. */ | |
294 | ||
295 | static CORE_ADDR | |
296 | after_prologue (pc, proc_desc) | |
297 | CORE_ADDR pc; | |
298 | mips_extra_func_info_t proc_desc; | |
299 | { | |
300 | struct symtab_and_line sal; | |
301 | CORE_ADDR func_addr, func_end; | |
302 | ||
303 | if (!proc_desc) | |
304 | proc_desc = find_proc_desc (pc, NULL); | |
305 | ||
306 | if (proc_desc) | |
307 | { | |
308 | /* If function is frameless, then we need to do it the hard way. I | |
309 | strongly suspect that frameless always means prologueless... */ | |
310 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM | |
311 | && PROC_FRAME_OFFSET (proc_desc) == 0) | |
312 | return 0; | |
313 | } | |
314 | ||
315 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
316 | return 0; /* Unknown */ | |
317 | ||
318 | sal = find_pc_line (func_addr, 0); | |
319 | ||
320 | if (sal.end < func_end) | |
321 | return sal.end; | |
322 | ||
323 | /* The line after the prologue is after the end of the function. In this | |
324 | case, tell the caller to find the prologue the hard way. */ | |
325 | ||
326 | return 0; | |
327 | } | |
328 | ||
f9f8c14b MA |
329 | /* Decode a MIPS32 instruction that saves a register in the stack, and |
330 | set the appropriate bit in the general register mask or float register mask | |
331 | to indicate which register is saved. This is a helper function | |
332 | for mips_find_saved_regs. */ | |
333 | ||
334 | static void | |
335 | mips32_decode_reg_save (inst, gen_mask, float_mask) | |
336 | t_inst inst; | |
337 | unsigned long *gen_mask; | |
338 | unsigned long *float_mask; | |
339 | { | |
340 | int reg; | |
341 | ||
342 | if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */ | |
343 | || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */ | |
a00dfa36 MS |
344 | /* start-sanitize-r5900 */ |
345 | || (inst & 0xffe00000) == 0x7fa00000 /* sq reg,n($sp) */ | |
346 | /* end-sanitize-r5900 */ | |
f9f8c14b MA |
347 | || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */ |
348 | { | |
349 | /* It might be possible to use the instruction to | |
350 | find the offset, rather than the code below which | |
351 | is based on things being in a certain order in the | |
352 | frame, but figuring out what the instruction's offset | |
353 | is relative to might be a little tricky. */ | |
354 | reg = (inst & 0x001f0000) >> 16; | |
355 | *gen_mask |= (1 << reg); | |
356 | } | |
357 | else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */ | |
358 | || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */ | |
359 | || (inst & 0xffe00000) == 0xf7a00000)/* sdc1 freg,n($sp) */ | |
360 | ||
361 | { | |
362 | reg = ((inst & 0x001f0000) >> 16); | |
363 | *float_mask |= (1 << reg); | |
364 | } | |
365 | } | |
366 | ||
367 | /* Decode a MIPS16 instruction that saves a register in the stack, and | |
368 | set the appropriate bit in the general register or float register mask | |
369 | to indicate which register is saved. This is a helper function | |
370 | for mips_find_saved_regs. */ | |
371 | ||
372 | static void | |
373 | mips16_decode_reg_save (inst, gen_mask) | |
374 | t_inst inst; | |
375 | unsigned long *gen_mask; | |
376 | { | |
b348b9fd | 377 | if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ |
f9f8c14b | 378 | { |
b348b9fd MA |
379 | int reg = mips16_to_32_reg[(inst & 0x700) >> 8]; |
380 | *gen_mask |= (1 << reg); | |
381 | } | |
382 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
383 | { | |
384 | int reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
f9f8c14b MA |
385 | *gen_mask |= (1 << reg); |
386 | } | |
387 | else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */ | |
388 | || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
af774411 | 389 | *gen_mask |= (1 << RA_REGNUM); |
f9f8c14b MA |
390 | } |
391 | ||
c81a76b3 MA |
392 | |
393 | /* Fetch and return instruction from the specified location. If the PC | |
394 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
395 | ||
396 | static t_inst | |
397 | mips_fetch_instruction (addr) | |
398 | CORE_ADDR addr; | |
399 | { | |
400 | char buf[MIPS_INSTLEN]; | |
401 | int instlen; | |
402 | int status; | |
403 | ||
899c4021 | 404 | if (pc_is_mips16 (addr)) |
c81a76b3 MA |
405 | { |
406 | instlen = MIPS16_INSTLEN; | |
407 | addr = UNMAKE_MIPS16_ADDR (addr); | |
408 | } | |
409 | else | |
410 | instlen = MIPS_INSTLEN; | |
411 | status = read_memory_nobpt (addr, buf, instlen); | |
412 | if (status) | |
413 | memory_error (status, addr); | |
414 | return extract_unsigned_integer (buf, instlen); | |
415 | } | |
416 | ||
417 | ||
88ff9e06 FCE |
418 | /* These the fields of 32 bit mips instructions */ |
419 | #define mips32_op(x) (x >> 25) | |
420 | #define itype_op(x) (x >> 25) | |
421 | #define itype_rs(x) ((x >> 21)& 0x1f) | |
422 | #define itype_rt(x) ((x >> 16) & 0x1f) | |
423 | #define itype_immediate(x) ( x & 0xffff) | |
424 | ||
425 | #define jtype_op(x) (x >> 25) | |
426 | #define jtype_target(x) ( x & 0x03fffff) | |
427 | ||
428 | #define rtype_op(x) (x >>25) | |
429 | #define rtype_rs(x) ((x>>21) & 0x1f) | |
430 | #define rtype_rt(x) ((x>>16) & 0x1f) | |
431 | #define rtype_rd(x) ((x>>11) & 0x1f) | |
432 | #define rtype_shamt(x) ((x>>6) & 0x1f) | |
433 | #define rtype_funct(x) (x & 0x3f ) | |
434 | ||
435 | static CORE_ADDR | |
436 | mips32_relative_offset(unsigned long inst) | |
437 | { long x ; | |
438 | x = itype_immediate(inst) ; | |
439 | if (x & 0x8000) /* sign bit set */ | |
440 | { | |
441 | x |= 0xffff0000 ; /* sign extension */ | |
442 | } | |
443 | x = x << 2 ; | |
444 | return x ; | |
445 | } | |
446 | ||
447 | /* Determine whate to set a single step breakpoint while considering | |
448 | branch prediction */ | |
449 | CORE_ADDR | |
450 | mips32_next_pc(CORE_ADDR pc) | |
451 | { | |
452 | unsigned long inst ; | |
453 | int op ; | |
454 | inst = mips_fetch_instruction(pc) ; | |
455 | if ((inst & 0xe0000000) != 0) /* Not a special, junp or branch instruction */ | |
456 | { if ((inst >> 27) == 5) /* BEQL BNEZ BLEZL BGTZE , bits 0101xx */ | |
457 | { op = ((inst >> 25) & 0x03) ; | |
458 | switch (op) | |
459 | { | |
460 | case 0 : goto equal_branch ; /* BEQL */ | |
461 | case 1 : goto neq_branch ; /* BNEZ */ | |
462 | case 2 : goto less_branch ; /* BLEZ */ | |
463 | case 3 : goto greater_branch ; /* BGTZ */ | |
464 | default : pc += 4 ; | |
465 | } | |
466 | } | |
467 | else pc += 4 ; /* Not a branch, next instruction is easy */ | |
468 | } | |
469 | else | |
470 | { /* This gets way messy */ | |
471 | ||
472 | /* Further subdivide into SPECIAL, REGIMM and other */ | |
473 | switch (op = ((inst >> 26) & 0x07)) /* extract bits 28,27,26 */ | |
474 | { | |
475 | case 0 : /* SPECIAL */ | |
476 | op = rtype_funct(inst) ; | |
477 | switch (op) | |
478 | { | |
479 | case 8 : /* JR */ | |
480 | case 9 : /* JALR */ | |
481 | pc = read_register(rtype_rs(inst)) ; /* Set PC to that address */ | |
482 | break ; | |
483 | default: pc += 4 ; | |
484 | } | |
485 | ||
486 | break ; /* end special */ | |
487 | case 1 : /* REGIMM */ | |
488 | { | |
489 | op = jtype_op(inst) ; /* branch condition */ | |
490 | switch (jtype_op(inst)) | |
491 | { | |
492 | case 0 : /* BLTZ */ | |
493 | case 2 : /* BLTXL */ | |
494 | case 16 : /* BLTZALL */ | |
495 | case 18 : /* BLTZALL */ | |
496 | less_branch: | |
497 | if (read_register(itype_rs(inst)) < 0) | |
498 | pc += mips32_relative_offset(inst) + 4 ; | |
499 | else pc += 8 ; /* after the delay slot */ | |
500 | break ; | |
501 | case 1 : /* GEZ */ | |
502 | case 3 : /* BGEZL */ | |
503 | case 17 : /* BGEZAL */ | |
504 | case 19 : /* BGEZALL */ | |
505 | greater_equal_branch: | |
506 | if (read_register(itype_rs(inst)) >= 0) | |
507 | pc += mips32_relative_offset(inst) + 4 ; | |
508 | else pc += 8 ; /* after the delay slot */ | |
509 | break ; | |
510 | /* All of the other intructions in the REGIMM catagory */ | |
511 | default: pc += 4 ; | |
512 | } | |
513 | } | |
514 | break ; /* end REGIMM */ | |
515 | case 2 : /* J */ | |
516 | case 3 : /* JAL */ | |
517 | { unsigned long reg ; | |
518 | reg = jtype_target(inst) << 2 ; | |
519 | pc = reg + ((pc+4) & 0xf0000000) ; | |
520 | /* Whats this mysterious 0xf000000 adjustment ??? */ | |
521 | } | |
522 | break ; | |
523 | /* FIXME case JALX :*/ | |
524 | { unsigned long reg ; | |
525 | reg = jtype_target(inst) << 2 ; | |
526 | pc = reg + ((pc+4) & 0xf0000000) + 1 ; /* yes, +1 */ | |
527 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ | |
528 | } | |
529 | break ; /* The new PC will be alternate mode */ | |
530 | case 4 : /* BEQ , BEQL */ | |
531 | equal_branch : | |
532 | if (read_register(itype_rs(inst)) == | |
533 | read_register(itype_rt(inst))) | |
534 | pc += mips32_relative_offset(inst) + 4 ; | |
535 | else pc += 8 ; | |
536 | break ; | |
537 | case 5 : /* BNE , BNEL */ | |
538 | neq_branch : | |
539 | if (read_register(itype_rs(inst)) != | |
540 | read_register(itype_rs(inst))) | |
541 | pc += mips32_relative_offset(inst) + 4 ; | |
542 | else pc += 8 ; | |
543 | break ; | |
544 | case 6 : /* BLEZ , BLEZL */ | |
545 | less_zero_branch: | |
546 | if (read_register(itype_rs(inst) <= 0)) | |
547 | pc += mips32_relative_offset(inst) + 4 ; | |
548 | else pc += 8 ; | |
549 | break ; | |
550 | case 7 : | |
551 | greater_branch : /* BGTZ BGTZL */ | |
552 | if (read_register(itype_rs(inst) > 0)) | |
553 | pc += mips32_relative_offset(inst) + 4 ; | |
554 | else pc += 8 ; | |
555 | break ; | |
556 | default : pc += 8 ; | |
557 | } /* switch */ | |
558 | } /* else */ | |
559 | return pc ; | |
560 | } /* mips32_next_pc */ | |
561 | ||
562 | /* Decoding the next place to set a breakpoint is irregular for the | |
563 | mips 16 variant, but fortunatly, there fewer instructions. We have to cope | |
564 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. | |
565 | We dont want to set a single step instruction on the extend instruction | |
566 | either. | |
567 | */ | |
568 | ||
569 | /* Lots of mips16 instruction formats */ | |
570 | /* Predicting jumps requires itype,ritype,i8type | |
571 | and their extensions extItype,extritype,extI8type | |
572 | */ | |
573 | enum mips16_inst_fmts | |
574 | { | |
575 | itype, /* 0 immediate 5,10 */ | |
576 | ritype, /* 1 5,3,8 */ | |
577 | rrtype, /* 2 5,3,3,5 */ | |
578 | rritype, /* 3 5,3,3,5 */ | |
579 | rrrtype, /* 4 5,3,3,3,2 */ | |
580 | rriatype, /* 5 5,3,3,1,4 */ | |
581 | shifttype, /* 6 5,3,3,3,2 */ | |
582 | i8type, /* 7 5,3,8 */ | |
583 | i8movtype, /* 8 5,3,3,5 */ | |
584 | i8mov32rtype, /* 9 5,3,5,3 */ | |
585 | i64type, /* 10 5,3,8 */ | |
586 | ri64type, /* 11 5,3,3,5 */ | |
587 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
588 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
589 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
590 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
591 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
592 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
593 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
594 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
595 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
596 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
597 | } ; | |
598 | /* I am heaping all the fields of the formats into one structure and then, | |
599 | only the fields which are involved in instruction extension */ | |
600 | struct upk_mips16 | |
601 | { | |
602 | unsigned short inst ; | |
603 | enum mips16_inst_fmts fmt ; | |
604 | unsigned long offset ; | |
605 | unsigned int regx ; /* Function in i8 type */ | |
606 | unsigned int regy ; | |
607 | } ; | |
608 | ||
609 | ||
610 | ||
611 | static void print_unpack(char * comment, | |
612 | struct upk_mips16 * u) | |
613 | { | |
614 | printf("%s %04x ,f(%d) off(%08x) (x(%x) y(%x)\n", | |
615 | comment,u->inst,u->fmt,u->offset,u->regx,u->regy) ; | |
616 | } | |
617 | ||
618 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same | |
619 | format for the bits which make up the immediatate extension. | |
620 | */ | |
621 | static unsigned long | |
622 | extended_offset(unsigned long extension) | |
623 | { | |
624 | unsigned long value ; | |
625 | value = (extension >> 21) & 0x3f ; /* * extract 15:11 */ | |
626 | value = value << 6 ; | |
627 | value |= (extension >> 16) & 0x1f ; /* extrace 10:5 */ | |
628 | value = value << 5 ; | |
629 | value |= extension & 0x01f ; /* extract 4:0 */ | |
630 | return value ; | |
631 | } | |
632 | ||
633 | /* Only call this function if you know that this is an extendable | |
634 | instruction, It wont malfunction, but why make excess remote memory references? | |
635 | If the immediate operands get sign extended or somthing, do it after | |
636 | the extension is performed. | |
637 | */ | |
638 | /* FIXME: Every one of these cases needs to worry about sign extension | |
639 | when the offset is to be used in relative addressing */ | |
640 | ||
641 | ||
642 | static unsigned short fetch_mips_16(CORE_ADDR pc) | |
643 | { | |
644 | char buf[8] ; | |
645 | pc &= 0xfffffffe ; /* clear the low order bit */ | |
646 | target_read_memory(pc,buf,2) ; | |
647 | return extract_unsigned_integer(buf,2) ; | |
648 | } | |
649 | ||
650 | static void | |
651 | unpack_mips16(CORE_ADDR pc, | |
652 | struct upk_mips16 * upk) | |
653 | { | |
654 | CORE_ADDR extpc ; | |
655 | unsigned long extension ; | |
656 | int extended ; | |
657 | extpc = (pc - 4) & ~0x01 ; /* Extensions are 32 bit instructions */ | |
658 | /* Decrement to previous address and loose the 16bit mode flag */ | |
659 | /* return if the instruction was extendable, but not actually extended */ | |
660 | extended = ((mips32_op(extension) == 30) ? 1 : 0) ; | |
661 | if (extended) { extension = mips_fetch_instruction(extpc) ;} | |
662 | switch (upk->fmt) | |
663 | { | |
664 | case itype : | |
665 | { | |
666 | unsigned long value ; | |
667 | if (extended) | |
668 | { value = extended_offset(extension) ; | |
669 | value = value << 11 ; /* rom for the original value */ | |
670 | value |= upk->inst & 0x7ff ; /* eleven bits from instruction */ | |
671 | } | |
672 | else | |
673 | { value = upk->inst & 0x7ff ; | |
674 | /* FIXME : Consider sign extension */ | |
675 | } | |
676 | upk->offset = value ; | |
677 | } | |
678 | break ; | |
679 | case ritype : | |
680 | case i8type : | |
681 | { /* A register identifier and an offset */ | |
682 | /* Most of the fields are the same as I type but the | |
683 | immediate value is of a different length */ | |
684 | unsigned long value ; | |
685 | if (extended) | |
686 | { | |
687 | value = extended_offset(extension) ; | |
688 | value = value << 8 ; /* from the original instruction */ | |
689 | value |= upk->inst & 0xff ; /* eleven bits from instruction */ | |
690 | upk->regx = (extension >> 8) & 0x07 ; /* or i8 funct */ | |
691 | if (value & 0x4000) /* test the sign bit , bit 26 */ | |
692 | { value &= ~ 0x3fff ; /* remove the sign bit */ | |
693 | value = -value ; | |
694 | } | |
695 | } | |
696 | else { | |
697 | value = upk->inst & 0xff ; /* 8 bits */ | |
698 | upk->regx = (upk->inst >> 8) & 0x07 ; /* or i8 funct */ | |
699 | /* FIXME: Do sign extension , this format needs it */ | |
700 | if (value & 0x80) /* THIS CONFUSES ME */ | |
701 | { value &= 0xef ; /* remove the sign bit */ | |
702 | value = -value ; | |
703 | } | |
704 | ||
705 | } | |
706 | upk->offset = value ; | |
707 | break ; | |
708 | } | |
709 | case jalxtype : | |
710 | { | |
711 | unsigned long value ; | |
712 | unsigned short nexthalf ; | |
713 | value = ((upk->inst & 0x1f) << 5) | ((upk->inst >> 5) & 0x1f) ; | |
714 | value = value << 16 ; | |
715 | nexthalf = mips_fetch_instruction(pc+2) ; /* low bit still set */ | |
716 | value |= nexthalf ; | |
717 | upk->offset = value ; | |
718 | break ; | |
719 | } | |
720 | default: | |
721 | printf_filtered("Decoding unimplemented instruction format type\n") ; | |
722 | break ; | |
723 | } | |
724 | /* print_unpack("UPK",upk) ; */ | |
725 | } | |
726 | ||
727 | ||
728 | #define mips16_op(x) (x >> 11) | |
729 | ||
730 | /* This is a map of the opcodes which ae known to perform branches */ | |
731 | static unsigned char map16[32] = | |
732 | { 0,0,1,1,1,1,0,0, | |
733 | 0,0,0,0,1,0,0,0, | |
734 | 0,0,0,0,0,0,0,0, | |
735 | 0,0,0,0,0,1,1,0 | |
736 | } ; | |
737 | ||
738 | static CORE_ADDR add_offset_16(CORE_ADDR pc, int offset) | |
739 | { | |
740 | return ((offset << 2) | ((pc + 2) & (0xf0000000))) ; | |
741 | ||
742 | } | |
743 | ||
744 | ||
745 | ||
746 | static struct upk_mips16 upk ; | |
747 | ||
748 | CORE_ADDR mips16_next_pc(CORE_ADDR pc) | |
749 | { | |
750 | int op ; | |
751 | t_inst inst ; | |
752 | /* inst = mips_fetch_instruction(pc) ; - This doesnt always work */ | |
753 | inst = fetch_mips_16(pc) ; | |
754 | upk.inst = inst ; | |
755 | op = mips16_op(upk.inst) ; | |
756 | if (map16[op]) | |
757 | { | |
758 | int reg ; | |
759 | switch (op) | |
760 | { | |
761 | case 2 : /* Branch */ | |
762 | upk.fmt = itype ; | |
763 | unpack_mips16(pc,&upk) ; | |
764 | { long offset ; | |
765 | offset = upk.offset ; | |
766 | if (offset & 0x800) | |
767 | { offset &= 0xeff ; | |
768 | offset = - offset ; | |
769 | } | |
770 | pc += (offset << 1) + 2 ; | |
771 | } | |
772 | break ; | |
773 | case 3 : /* JAL , JALX - Watch out, these are 32 bit instruction*/ | |
774 | upk.fmt = jalxtype ; | |
775 | unpack_mips16(pc,&upk) ; | |
776 | pc = add_offset_16(pc,upk.offset) ; | |
777 | if ((upk.inst >> 10) & 0x01) /* Exchange mode */ | |
778 | pc = pc & ~ 0x01 ; /* Clear low bit, indicate 32 bit mode */ | |
779 | else pc |= 0x01 ; | |
780 | break ; | |
781 | case 4 : /* beqz */ | |
782 | upk.fmt = ritype ; | |
783 | unpack_mips16(pc,&upk) ; | |
784 | reg = read_register(upk.regx) ; | |
785 | if (reg == 0) | |
786 | pc += (upk.offset << 1) + 2 ; | |
787 | else pc += 2 ; | |
788 | break ; | |
789 | case 5 : /* bnez */ | |
790 | upk.fmt = ritype ; | |
791 | unpack_mips16(pc,&upk) ; | |
792 | reg = read_register(upk.regx) ; | |
793 | if (reg != 0) | |
794 | pc += (upk.offset << 1) + 2 ; | |
795 | else pc += 2 ; | |
796 | break ; | |
797 | case 12 : /* I8 Formats btez btnez */ | |
798 | upk.fmt = i8type ; | |
799 | unpack_mips16(pc,&upk) ; | |
800 | /* upk.regx contains the opcode */ | |
801 | reg = read_register(24) ; /* Test register is 24 */ | |
802 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ | |
803 | || ((upk.regx == 1 ) && (reg != 0))) /* BTNEZ */ | |
804 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
805 | pc += (upk.offset << 1) + 2 ; | |
806 | else pc += 2 ; | |
807 | break ; | |
808 | case 29 : /* RR Formats JR, JALR, JALR-RA */ | |
809 | upk.fmt = rrtype ; | |
810 | op = upk.inst & 0x1f ; | |
811 | if (op == 0) | |
812 | { | |
813 | upk.regx = (upk.inst >> 8) & 0x07 ; | |
814 | upk.regy = (upk.inst >> 5) & 0x07 ; | |
815 | switch (upk.regy) | |
816 | { | |
817 | case 0 : reg = upk.regx ; break ; | |
818 | case 1 : reg = 31 ; break ; /* Function return instruction*/ | |
819 | case 2 : reg = upk.regx ; break ; | |
820 | default: reg = 31 ; break ; /* BOGUS Guess */ | |
821 | } | |
822 | pc = read_register(reg) ; | |
823 | } | |
824 | else pc += 2 ; | |
825 | break ; | |
826 | case 30 : /* This is an extend instruction */ | |
827 | pc += 4 ; /* Dont be setting breakpints on the second half */ | |
828 | break ; | |
829 | default : | |
830 | printf("Filtered - next PC probably incorrrect due to jump inst\n"); | |
831 | pc += 2 ; | |
832 | break ; | |
833 | } | |
834 | } | |
835 | else pc+= 2 ; /* just a good old instruction */ | |
836 | /* See if we CAN actually break on the next instruction */ | |
837 | /* printf("NXTm16PC %08x\n",(unsigned long)pc) ; */ | |
838 | return pc ; | |
839 | } /* mips16_next_pc */ | |
840 | ||
841 | /* The mips_next_pc function supports single_tep when the remote target monitor or | |
842 | stub is not developed enough to so a single_step. | |
843 | It works by decoding the current instruction and predicting where a branch | |
844 | will go. This isnt hard because all the data is available. | |
845 | The MIPS32 and MIPS16 variants are quite different | |
846 | */ | |
847 | CORE_ADDR mips_next_pc(CORE_ADDR pc) | |
848 | { | |
849 | t_inst inst ; | |
850 | /* inst = mips_fetch_instruction(pc) ; */ | |
851 | /* if (pc_is_mips16) <----- This is failing */ | |
852 | if (pc & 0x01) | |
853 | return mips16_next_pc(pc) ; | |
854 | else return mips32_next_pc(pc) ; | |
855 | } /* mips_next_pc */ | |
856 | ||
70126bf9 KH |
857 | /* Guaranteed to set fci->saved_regs to some values (it never leaves it |
858 | NULL). */ | |
859 | ||
860 | void | |
861 | mips_find_saved_regs (fci) | |
9f9f94aa | 862 | struct frame_info *fci; |
70126bf9 KH |
863 | { |
864 | int ireg; | |
865 | CORE_ADDR reg_position; | |
866 | /* r0 bit means kernel trap */ | |
867 | int kernel_trap; | |
868 | /* What registers have been saved? Bitmasks. */ | |
869 | unsigned long gen_mask, float_mask; | |
870 | mips_extra_func_info_t proc_desc; | |
c81a76b3 | 871 | t_inst inst; |
70126bf9 | 872 | |
86a51f41 | 873 | frame_saved_regs_zalloc (fci); |
70126bf9 | 874 | |
e4dbd248 PS |
875 | /* If it is the frame for sigtramp, the saved registers are located |
876 | in a sigcontext structure somewhere on the stack. | |
877 | If the stack layout for sigtramp changes we might have to change these | |
878 | constants and the companion fixup_sigtramp in mdebugread.c */ | |
879 | #ifndef SIGFRAME_BASE | |
880 | /* To satisfy alignment restrictions, sigcontext is located 4 bytes | |
881 | above the sigtramp frame. */ | |
28444bf3 DP |
882 | #define SIGFRAME_BASE MIPS_REGSIZE |
883 | /* FIXME! Are these correct?? */ | |
884 | #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE) | |
885 | #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE) | |
886 | #define SIGFRAME_FPREGSAVE_OFF \ | |
887 | (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE) | |
e4dbd248 PS |
888 | #endif |
889 | #ifndef SIGFRAME_REG_SIZE | |
28444bf3 DP |
890 | /* FIXME! Is this correct?? */ |
891 | #define SIGFRAME_REG_SIZE MIPS_REGSIZE | |
e4dbd248 PS |
892 | #endif |
893 | if (fci->signal_handler_caller) | |
894 | { | |
28444bf3 | 895 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) |
e4dbd248 PS |
896 | { |
897 | reg_position = fci->frame + SIGFRAME_REGSAVE_OFF | |
898 | + ireg * SIGFRAME_REG_SIZE; | |
86a51f41 | 899 | fci->saved_regs[ireg] = reg_position; |
e4dbd248 | 900 | } |
28444bf3 | 901 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) |
e4dbd248 PS |
902 | { |
903 | reg_position = fci->frame + SIGFRAME_FPREGSAVE_OFF | |
904 | + ireg * SIGFRAME_REG_SIZE; | |
86a51f41 | 905 | fci->saved_regs[FP0_REGNUM + ireg] = reg_position; |
e4dbd248 | 906 | } |
86a51f41 | 907 | fci->saved_regs[PC_REGNUM] = fci->frame + SIGFRAME_PC_OFF; |
e4dbd248 PS |
908 | return; |
909 | } | |
910 | ||
70126bf9 KH |
911 | proc_desc = fci->proc_desc; |
912 | if (proc_desc == NULL) | |
913 | /* I'm not sure how/whether this can happen. Normally when we can't | |
914 | find a proc_desc, we "synthesize" one using heuristic_proc_desc | |
915 | and set the saved_regs right away. */ | |
916 | return; | |
917 | ||
918 | kernel_trap = PROC_REG_MASK(proc_desc) & 1; | |
919 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK(proc_desc); | |
920 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK(proc_desc); | |
921 | ||
f9f8c14b MA |
922 | if (/* In any frame other than the innermost or a frame interrupted by |
923 | a signal, we assume that all registers have been saved. | |
924 | This assumes that all register saves in a function happen before | |
925 | the first function call. */ | |
926 | (fci->next == NULL || fci->next->signal_handler_caller) | |
70126bf9 KH |
927 | |
928 | /* In a dummy frame we know exactly where things are saved. */ | |
929 | && !PROC_DESC_IS_DUMMY (proc_desc) | |
930 | ||
f2bf454e FF |
931 | /* Don't bother unless we are inside a function prologue. Outside the |
932 | prologue, we know where everything is. */ | |
933 | ||
934 | && in_prologue (fci->pc, PROC_LOW_ADDR (proc_desc)) | |
935 | ||
70126bf9 KH |
936 | /* Not sure exactly what kernel_trap means, but if it means |
937 | the kernel saves the registers without a prologue doing it, | |
938 | we better not examine the prologue to see whether registers | |
939 | have been saved yet. */ | |
940 | && !kernel_trap) | |
941 | { | |
942 | /* We need to figure out whether the registers that the proc_desc | |
943 | claims are saved have been saved yet. */ | |
944 | ||
945 | CORE_ADDR addr; | |
70126bf9 KH |
946 | |
947 | /* Bitmasks; set if we have found a save for the register. */ | |
948 | unsigned long gen_save_found = 0; | |
949 | unsigned long float_save_found = 0; | |
c81a76b3 | 950 | int instlen; |
70126bf9 | 951 | |
c1fc0935 MA |
952 | /* If the address is odd, assume this is MIPS16 code. */ |
953 | addr = PROC_LOW_ADDR (proc_desc); | |
899c4021 | 954 | instlen = pc_is_mips16 (addr) ? MIPS16_INSTLEN : MIPS_INSTLEN; |
f9f8c14b | 955 | |
20fa0902 MA |
956 | /* Scan through this function's instructions preceding the current |
957 | PC, and look for those that save registers. */ | |
f9f8c14b MA |
958 | while (addr < fci->pc) |
959 | { | |
c81a76b3 | 960 | inst = mips_fetch_instruction (addr); |
899c4021 | 961 | if (pc_is_mips16 (addr)) |
f9f8c14b MA |
962 | mips16_decode_reg_save (inst, &gen_save_found); |
963 | else | |
964 | mips32_decode_reg_save (inst, &gen_save_found, &float_save_found); | |
965 | addr += instlen; | |
70126bf9 KH |
966 | } |
967 | gen_mask = gen_save_found; | |
968 | float_mask = float_save_found; | |
969 | } | |
970 | ||
971 | /* Fill in the offsets for the registers which gen_mask says | |
972 | were saved. */ | |
973 | reg_position = fci->frame + PROC_REG_OFFSET (proc_desc); | |
28444bf3 | 974 | for (ireg= MIPS_NUMREGS-1; gen_mask; --ireg, gen_mask <<= 1) |
70126bf9 KH |
975 | if (gen_mask & 0x80000000) |
976 | { | |
86a51f41 | 977 | fci->saved_regs[ireg] = reg_position; |
70126bf9 | 978 | reg_position -= MIPS_REGSIZE; |
a00dfa36 MS |
979 | /* start-sanitize-r5900 */ |
980 | #ifdef R5900_128BIT_GPR_HACK | |
981 | /* Gross. The r5900 has 128bit wide registers, but MIPS_REGSIZE is | |
982 | still 64bits. See the comments in tm.h for a discussion of the | |
983 | various problems this causes. */ | |
984 | if (ireg <= RA_REGNUM) | |
985 | reg_position -= MIPS_REGSIZE; | |
986 | #endif | |
987 | /* end-sanitize-r5900 */ | |
70126bf9 | 988 | } |
c81a76b3 MA |
989 | |
990 | /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order | |
991 | of that normally used by gcc. Therefore, we have to fetch the first | |
992 | instruction of the function, and if it's an entry instruction that | |
993 | saves $s0 or $s1, correct their saved addresses. */ | |
899c4021 | 994 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) |
c81a76b3 MA |
995 | { |
996 | inst = mips_fetch_instruction (PROC_LOW_ADDR (proc_desc)); | |
997 | if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
998 | { | |
999 | int reg; | |
1000 | int sreg_count = (inst >> 6) & 3; | |
1001 | ||
1002 | /* Check if the ra register was pushed on the stack. */ | |
1003 | reg_position = fci->frame + PROC_REG_OFFSET (proc_desc); | |
1004 | if (inst & 0x20) | |
1005 | reg_position -= MIPS_REGSIZE; | |
1006 | ||
1007 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
1008 | for (reg = 16; reg < sreg_count+16; reg++) | |
1009 | { | |
86a51f41 | 1010 | fci->saved_regs[reg] = reg_position; |
c81a76b3 MA |
1011 | reg_position -= MIPS_REGSIZE; |
1012 | } | |
1013 | } | |
1014 | } | |
1015 | ||
70126bf9 KH |
1016 | /* Fill in the offsets for the registers which float_mask says |
1017 | were saved. */ | |
1018 | reg_position = fci->frame + PROC_FREG_OFFSET (proc_desc); | |
1019 | ||
1020 | /* The freg_offset points to where the first *double* register | |
1021 | is saved. So skip to the high-order word. */ | |
28444bf3 | 1022 | if (! GDB_TARGET_IS_MIPS64) |
c81a76b3 | 1023 | reg_position += MIPS_REGSIZE; |
28444bf3 | 1024 | |
20fa0902 MA |
1025 | /* Fill in the offsets for the float registers which float_mask says |
1026 | were saved. */ | |
28444bf3 | 1027 | for (ireg = MIPS_NUMREGS-1; float_mask; --ireg, float_mask <<= 1) |
70126bf9 KH |
1028 | if (float_mask & 0x80000000) |
1029 | { | |
86a51f41 | 1030 | fci->saved_regs[FP0_REGNUM+ireg] = reg_position; |
70126bf9 KH |
1031 | reg_position -= MIPS_REGSIZE; |
1032 | } | |
1033 | ||
86a51f41 | 1034 | fci->saved_regs[PC_REGNUM] = fci->saved_regs[RA_REGNUM]; |
70126bf9 | 1035 | } |
bd5635a1 | 1036 | |
28444bf3 | 1037 | static CORE_ADDR |
bd5635a1 | 1038 | read_next_frame_reg(fi, regno) |
9f9f94aa | 1039 | struct frame_info *fi; |
bd5635a1 RP |
1040 | int regno; |
1041 | { | |
bd5635a1 | 1042 | for (; fi; fi = fi->next) |
70126bf9 | 1043 | { |
e4dbd248 PS |
1044 | /* We have to get the saved sp from the sigcontext |
1045 | if it is a signal handler frame. */ | |
1046 | if (regno == SP_REGNUM && !fi->signal_handler_caller) | |
1047 | return fi->frame; | |
70126bf9 KH |
1048 | else |
1049 | { | |
1050 | if (fi->saved_regs == NULL) | |
1051 | mips_find_saved_regs (fi); | |
86a51f41 AC |
1052 | if (fi->saved_regs[regno]) |
1053 | return read_memory_integer(fi->saved_regs[regno], MIPS_REGSIZE); | |
70126bf9 KH |
1054 | } |
1055 | } | |
1056 | return read_register (regno); | |
bd5635a1 RP |
1057 | } |
1058 | ||
96431497 MA |
1059 | /* mips_addr_bits_remove - remove useless address bits */ |
1060 | ||
1061 | CORE_ADDR | |
1062 | mips_addr_bits_remove (addr) | |
1063 | CORE_ADDR addr; | |
1064 | { | |
97e091b2 | 1065 | #if GDB_TARGET_IS_MIPS64 |
98760eab | 1066 | if (mask_address_p && (addr >> 32 == (CORE_ADDR)0xffffffff)) |
96431497 MA |
1067 | { |
1068 | /* This hack is a work-around for existing boards using PMON, | |
1069 | the simulator, and any other 64-bit targets that doesn't have | |
1070 | true 64-bit addressing. On these targets, the upper 32 bits | |
1071 | of addresses are ignored by the hardware. Thus, the PC or SP | |
1072 | are likely to have been sign extended to all 1s by instruction | |
1073 | sequences that load 32-bit addresses. For example, a typical | |
1074 | piece of code that loads an address is this: | |
1075 | lui $r2, <upper 16 bits> | |
1076 | ori $r2, <lower 16 bits> | |
1077 | But the lui sign-extends the value such that the upper 32 bits | |
1078 | may be all 1s. The workaround is simply to mask off these bits. | |
1079 | In the future, gcc may be changed to support true 64-bit | |
1080 | addressing, and this masking will have to be disabled. */ | |
1081 | addr &= (CORE_ADDR)0xffffffff; | |
1082 | } | |
f9f8c14b MA |
1083 | #else |
1084 | /* Even when GDB is configured for some 32-bit targets (e.g. mips-elf), | |
1085 | BFD is configured to handle 64-bit targets, so CORE_ADDR is 64 bits. | |
1086 | So we still have to mask off useless bits from addresses. */ | |
1087 | addr &= (CORE_ADDR)0xffffffff; | |
97e091b2 | 1088 | #endif |
96431497 MA |
1089 | |
1090 | return addr; | |
1091 | } | |
1092 | ||
f781fe93 MA |
1093 | void |
1094 | mips_init_frame_pc_first (fromleaf, prev) | |
1095 | int fromleaf; | |
1096 | struct frame_info *prev; | |
1097 | { | |
1098 | CORE_ADDR pc, tmp; | |
1099 | ||
1100 | pc = ((fromleaf) ? SAVED_PC_AFTER_CALL (prev->next) : | |
1101 | prev->next ? FRAME_SAVED_PC (prev->next) : read_pc ()); | |
1102 | tmp = mips_skip_stub (pc); | |
1103 | prev->pc = tmp ? tmp : pc; | |
1104 | } | |
1105 | ||
1106 | ||
28444bf3 | 1107 | CORE_ADDR |
bd5635a1 | 1108 | mips_frame_saved_pc(frame) |
9f9f94aa | 1109 | struct frame_info *frame; |
bd5635a1 | 1110 | { |
28444bf3 | 1111 | CORE_ADDR saved_pc; |
0f552c5f | 1112 | mips_extra_func_info_t proc_desc = frame->proc_desc; |
0434c1a0 PS |
1113 | /* We have to get the saved pc from the sigcontext |
1114 | if it is a signal handler frame. */ | |
1115 | int pcreg = frame->signal_handler_caller ? PC_REGNUM | |
1116 | : (proc_desc ? PROC_PC_REG(proc_desc) : RA_REGNUM); | |
0f552c5f | 1117 | |
bd5635a1 | 1118 | if (proc_desc && PROC_DESC_IS_DUMMY(proc_desc)) |
28444bf3 DP |
1119 | saved_pc = read_memory_integer(frame->frame - MIPS_REGSIZE, MIPS_REGSIZE); |
1120 | else | |
1121 | saved_pc = read_next_frame_reg(frame, pcreg); | |
0f552c5f | 1122 | |
96431497 | 1123 | return ADDR_BITS_REMOVE (saved_pc); |
bd5635a1 RP |
1124 | } |
1125 | ||
1126 | static struct mips_extra_func_info temp_proc_desc; | |
1127 | static struct frame_saved_regs temp_saved_regs; | |
1128 | ||
639c8612 MA |
1129 | /* Set a register's saved stack address in temp_saved_regs. If an address |
1130 | has already been set for this register, do nothing; this way we will | |
1131 | only recognize the first save of a given register in a function prologue. | |
1132 | This is a helper function for mips{16,32}_heuristic_proc_desc. */ | |
1133 | ||
1134 | static void | |
1135 | set_reg_offset (regno, offset) | |
1136 | int regno; | |
1137 | CORE_ADDR offset; | |
1138 | { | |
1139 | if (temp_saved_regs.regs[regno] == 0) | |
1140 | temp_saved_regs.regs[regno] = offset; | |
1141 | } | |
1142 | ||
1143 | ||
9ddf9aa9 AC |
1144 | /* Test whether the PC points to the return instruction at the |
1145 | end of a function. */ | |
1146 | ||
1147 | static int | |
1148 | mips_about_to_return (pc) | |
1149 | CORE_ADDR pc; | |
1150 | { | |
1151 | if (pc_is_mips16 (pc)) | |
1152 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler | |
1153 | generates a "jr $ra"; other times it generates code to load | |
1154 | the return address from the stack to an accessible register (such | |
1155 | as $a3), then a "jr" using that register. This second case | |
1156 | is almost impossible to distinguish from an indirect jump | |
1157 | used for switch statements, so we don't even try. */ | |
1158 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
1159 | else | |
1160 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
1161 | } | |
1162 | ||
1163 | ||
a8172eea RP |
1164 | /* This fencepost looks highly suspicious to me. Removing it also |
1165 | seems suspicious as it could affect remote debugging across serial | |
3127785a | 1166 | lines. */ |
a8172eea | 1167 | |
0f552c5f | 1168 | static CORE_ADDR |
9ddf9aa9 | 1169 | heuristic_proc_start (pc) |
bd5635a1 RP |
1170 | CORE_ADDR pc; |
1171 | { | |
32dab603 MA |
1172 | CORE_ADDR start_pc; |
1173 | CORE_ADDR fence; | |
20fa0902 | 1174 | int instlen; |
b348b9fd | 1175 | int seen_adjsp = 0; |
0f552c5f | 1176 | |
32dab603 MA |
1177 | pc = ADDR_BITS_REMOVE (pc); |
1178 | start_pc = pc; | |
1179 | fence = start_pc - heuristic_fence_post; | |
0f552c5f | 1180 | if (start_pc == 0) return 0; |
3127785a RP |
1181 | |
1182 | if (heuristic_fence_post == UINT_MAX | |
1183 | || fence < VM_MIN_ADDRESS) | |
1184 | fence = VM_MIN_ADDRESS; | |
0f552c5f | 1185 | |
899c4021 | 1186 | instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN; |
20fa0902 | 1187 | |
bd5635a1 | 1188 | /* search back for previous return */ |
20fa0902 | 1189 | for (start_pc -= instlen; ; start_pc -= instlen) |
a8172eea RP |
1190 | if (start_pc < fence) |
1191 | { | |
3127785a RP |
1192 | /* It's not clear to me why we reach this point when |
1193 | stop_soon_quietly, but with this test, at least we | |
1194 | don't print out warnings for every child forked (eg, on | |
1195 | decstation). 22apr93 rich@cygnus.com. */ | |
1196 | if (!stop_soon_quietly) | |
1197 | { | |
23d35572 JK |
1198 | static int blurb_printed = 0; |
1199 | ||
3127785a RP |
1200 | if (fence == VM_MIN_ADDRESS) |
1201 | warning("Hit beginning of text section without finding"); | |
1202 | else | |
1203 | warning("Hit heuristic-fence-post without finding"); | |
1204 | ||
f781fe93 | 1205 | warning("enclosing function for address 0x%s", paddr_nz (pc)); |
23d35572 JK |
1206 | if (!blurb_printed) |
1207 | { | |
1208 | printf_filtered ("\ | |
1209 | This warning occurs if you are debugging a function without any symbols\n\ | |
1210 | (for example, in a stripped executable). In that case, you may wish to\n\ | |
1211 | increase the size of the search with the `set heuristic-fence-post' command.\n\ | |
1212 | \n\ | |
1213 | Otherwise, you told GDB there was a function where there isn't one, or\n\ | |
1214 | (more likely) you have encountered a bug in GDB.\n"); | |
1215 | blurb_printed = 1; | |
1216 | } | |
3127785a RP |
1217 | } |
1218 | ||
a8172eea RP |
1219 | return 0; |
1220 | } | |
899c4021 | 1221 | else if (pc_is_mips16 (start_pc)) |
20fa0902 | 1222 | { |
c1fc0935 MA |
1223 | unsigned short inst; |
1224 | ||
b348b9fd MA |
1225 | /* On MIPS16, any one of the following is likely to be the |
1226 | start of a function: | |
1227 | entry | |
1228 | addiu sp,-n | |
1229 | daddiu sp,-n | |
1230 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
c81a76b3 | 1231 | inst = mips_fetch_instruction (start_pc); |
b348b9fd MA |
1232 | if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
1233 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
1234 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
1235 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
1236 | break; | |
1237 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
1238 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1239 | seen_adjsp = 1; | |
1240 | else | |
1241 | seen_adjsp = 0; | |
20fa0902 | 1242 | } |
9ddf9aa9 | 1243 | else if (mips_about_to_return (start_pc)) |
20fa0902 MA |
1244 | { |
1245 | start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */ | |
bd5635a1 | 1246 | break; |
20fa0902 | 1247 | } |
bd5635a1 | 1248 | |
bd5635a1 RP |
1249 | #if 0 |
1250 | /* skip nops (usually 1) 0 - is this */ | |
28444bf3 DP |
1251 | while (start_pc < pc && read_memory_integer (start_pc, MIPS_INSTLEN) == 0) |
1252 | start_pc += MIPS_INSTLEN; | |
bd5635a1 RP |
1253 | #endif |
1254 | return start_pc; | |
1255 | } | |
1256 | ||
c81a76b3 | 1257 | /* Fetch the immediate value from a MIPS16 instruction. |
b348b9fd MA |
1258 | If the previous instruction was an EXTEND, use it to extend |
1259 | the upper bits of the immediate value. This is a helper function | |
1260 | for mips16_heuristic_proc_desc. */ | |
1261 | ||
1262 | static int | |
1263 | mips16_get_imm (prev_inst, inst, nbits, scale, is_signed) | |
1264 | unsigned short prev_inst; /* previous instruction */ | |
af774411 | 1265 | unsigned short inst; /* current instruction */ |
b348b9fd MA |
1266 | int nbits; /* number of bits in imm field */ |
1267 | int scale; /* scale factor to be applied to imm */ | |
1268 | int is_signed; /* is the imm field signed? */ | |
1269 | { | |
1270 | int offset; | |
1271 | ||
1272 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ | |
1273 | { | |
7d9e8fac | 1274 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); |
b348b9fd MA |
1275 | if (offset & 0x8000) /* check for negative extend */ |
1276 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
1277 | return offset | (inst & 0x1f); | |
1278 | } | |
1279 | else | |
1280 | { | |
1281 | int max_imm = 1 << nbits; | |
1282 | int mask = max_imm - 1; | |
1283 | int sign_bit = max_imm >> 1; | |
1284 | ||
1285 | offset = inst & mask; | |
1286 | if (is_signed && (offset & sign_bit)) | |
1287 | offset = 0 - (max_imm - offset); | |
1288 | return offset * scale; | |
1289 | } | |
1290 | } | |
1291 | ||
1292 | ||
1293 | /* Fill in values in temp_proc_desc based on the MIPS16 instruction | |
1294 | stream from start_pc to limit_pc. */ | |
1295 | ||
1296 | static void | |
1297 | mips16_heuristic_proc_desc(start_pc, limit_pc, next_frame, sp) | |
bd5635a1 | 1298 | CORE_ADDR start_pc, limit_pc; |
9f9f94aa | 1299 | struct frame_info *next_frame; |
b348b9fd | 1300 | CORE_ADDR sp; |
bd5635a1 | 1301 | { |
b348b9fd MA |
1302 | CORE_ADDR cur_pc; |
1303 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
1304 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
1305 | unsigned inst = 0; /* current instruction */ | |
639c8612 MA |
1306 | unsigned entry_inst = 0; /* the entry instruction */ |
1307 | int reg, offset; | |
bd5635a1 | 1308 | |
af774411 MA |
1309 | PROC_FRAME_OFFSET(&temp_proc_desc) = 0; /* size of stack frame */ |
1310 | PROC_FRAME_ADJUST(&temp_proc_desc) = 0; /* offset of FP from SP */ | |
34df79fc | 1311 | |
b348b9fd MA |
1312 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN) |
1313 | { | |
b348b9fd MA |
1314 | /* Save the previous instruction. If it's an EXTEND, we'll extract |
1315 | the immediate offset extension from it in mips16_get_imm. */ | |
1316 | prev_inst = inst; | |
1317 | ||
c81a76b3 MA |
1318 | /* Fetch and decode the instruction. */ |
1319 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
b348b9fd MA |
1320 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
1321 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1322 | { | |
1323 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
1324 | if (offset < 0) /* negative stack adjustment? */ | |
1325 | PROC_FRAME_OFFSET(&temp_proc_desc) -= offset; | |
1326 | else | |
1327 | /* Exit loop if a positive stack adjustment is found, which | |
1328 | usually means that the stack cleanup code in the function | |
1329 | epilogue is reached. */ | |
1330 | break; | |
1331 | } | |
1332 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
1333 | { | |
1334 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1335 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
1336 | PROC_REG_MASK(&temp_proc_desc) |= (1 << reg); | |
639c8612 | 1337 | set_reg_offset (reg, sp + offset); |
b348b9fd MA |
1338 | } |
1339 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
1340 | { | |
1341 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1342 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1343 | PROC_REG_MASK(&temp_proc_desc) |= (1 << reg); | |
639c8612 | 1344 | set_reg_offset (reg, sp + offset); |
b348b9fd MA |
1345 | } |
1346 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
1347 | { | |
1348 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
af774411 | 1349 | PROC_REG_MASK(&temp_proc_desc) |= (1 << RA_REGNUM); |
639c8612 | 1350 | set_reg_offset (RA_REGNUM, sp + offset); |
97e091b2 | 1351 | } |
b348b9fd MA |
1352 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ |
1353 | { | |
1354 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
af774411 | 1355 | PROC_REG_MASK(&temp_proc_desc) |= (1 << RA_REGNUM); |
639c8612 | 1356 | set_reg_offset (RA_REGNUM, sp + offset); |
bd5635a1 | 1357 | } |
b348b9fd MA |
1358 | else if (inst == 0x673d) /* move $s1, $sp */ |
1359 | { | |
639c8612 | 1360 | frame_addr = sp; |
b348b9fd | 1361 | PROC_FRAME_REG (&temp_proc_desc) = 17; |
97e091b2 | 1362 | } |
32dab603 MA |
1363 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ |
1364 | { | |
1365 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1366 | frame_addr = sp + offset; | |
1367 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
af774411 | 1368 | PROC_FRAME_ADJUST (&temp_proc_desc) = offset; |
32dab603 | 1369 | } |
b348b9fd MA |
1370 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ |
1371 | { | |
1372 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
1373 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1374 | PROC_REG_MASK(&temp_proc_desc) |= 1 << reg; | |
639c8612 | 1375 | set_reg_offset (reg, frame_addr + offset); |
b348b9fd MA |
1376 | } |
1377 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
1378 | { | |
1379 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1380 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1381 | PROC_REG_MASK(&temp_proc_desc) |= 1 << reg; | |
639c8612 | 1382 | set_reg_offset (reg, frame_addr + offset); |
b348b9fd MA |
1383 | } |
1384 | else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
639c8612 MA |
1385 | entry_inst = inst; /* save for later processing */ |
1386 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ | |
1387 | cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */ | |
1388 | } | |
b348b9fd | 1389 | |
639c8612 MA |
1390 | /* The entry instruction is typically the first instruction in a function, |
1391 | and it stores registers at offsets relative to the value of the old SP | |
1392 | (before the prologue). But the value of the sp parameter to this | |
1393 | function is the new SP (after the prologue has been executed). So we | |
1394 | can't calculate those offsets until we've seen the entire prologue, | |
1395 | and can calculate what the old SP must have been. */ | |
1396 | if (entry_inst != 0) | |
1397 | { | |
1398 | int areg_count = (entry_inst >> 8) & 7; | |
1399 | int sreg_count = (entry_inst >> 6) & 3; | |
b348b9fd | 1400 | |
639c8612 MA |
1401 | /* The entry instruction always subtracts 32 from the SP. */ |
1402 | PROC_FRAME_OFFSET(&temp_proc_desc) += 32; | |
b348b9fd | 1403 | |
639c8612 MA |
1404 | /* Now we can calculate what the SP must have been at the |
1405 | start of the function prologue. */ | |
1406 | sp += PROC_FRAME_OFFSET(&temp_proc_desc); | |
b348b9fd | 1407 | |
639c8612 MA |
1408 | /* Check if a0-a3 were saved in the caller's argument save area. */ |
1409 | for (reg = 4, offset = 0; reg < areg_count+4; reg++) | |
1410 | { | |
1411 | PROC_REG_MASK(&temp_proc_desc) |= 1 << reg; | |
1412 | set_reg_offset (reg, sp + offset); | |
1413 | offset += MIPS_REGSIZE; | |
1414 | } | |
1415 | ||
1416 | /* Check if the ra register was pushed on the stack. */ | |
1417 | offset = -4; | |
1418 | if (entry_inst & 0x20) | |
1419 | { | |
1420 | PROC_REG_MASK(&temp_proc_desc) |= 1 << RA_REGNUM; | |
1421 | set_reg_offset (RA_REGNUM, sp + offset); | |
1422 | offset -= MIPS_REGSIZE; | |
1423 | } | |
1424 | ||
1425 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
1426 | for (reg = 16; reg < sreg_count+16; reg++) | |
1427 | { | |
1428 | PROC_REG_MASK(&temp_proc_desc) |= 1 << reg; | |
1429 | set_reg_offset (reg, sp + offset); | |
1430 | offset -= MIPS_REGSIZE; | |
1431 | } | |
1432 | } | |
b348b9fd MA |
1433 | } |
1434 | ||
1435 | static void | |
1436 | mips32_heuristic_proc_desc(start_pc, limit_pc, next_frame, sp) | |
1437 | CORE_ADDR start_pc, limit_pc; | |
1438 | struct frame_info *next_frame; | |
1439 | CORE_ADDR sp; | |
1440 | { | |
1441 | CORE_ADDR cur_pc; | |
1442 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ | |
1443 | restart: | |
0e52a532 | 1444 | memset (&temp_saved_regs, '\0', sizeof(struct frame_saved_regs)); |
b348b9fd | 1445 | PROC_FRAME_OFFSET(&temp_proc_desc) = 0; |
639c8612 | 1446 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ |
b348b9fd MA |
1447 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN) |
1448 | { | |
b348b9fd | 1449 | unsigned long inst, high_word, low_word; |
c81a76b3 | 1450 | int reg; |
b348b9fd MA |
1451 | |
1452 | /* Fetch the instruction. */ | |
c81a76b3 | 1453 | inst = (unsigned long) mips_fetch_instruction (cur_pc); |
b348b9fd MA |
1454 | |
1455 | /* Save some code by pre-extracting some useful fields. */ | |
1456 | high_word = (inst >> 16) & 0xffff; | |
1457 | low_word = inst & 0xffff; | |
1458 | reg = high_word & 0x1f; | |
1459 | ||
1460 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ | |
1461 | || high_word == 0x23bd /* addi $sp,$sp,-i */ | |
1462 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
1463 | { | |
1464 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
1465 | PROC_FRAME_OFFSET(&temp_proc_desc) += 0x10000 - low_word; | |
1466 | else | |
1467 | /* Exit loop if a positive stack adjustment is found, which | |
1468 | usually means that the stack cleanup code in the function | |
1469 | epilogue is reached. */ | |
1470 | break; | |
1471 | } | |
1472 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
1473 | { | |
1474 | PROC_REG_MASK(&temp_proc_desc) |= 1 << reg; | |
639c8612 | 1475 | set_reg_offset (reg, sp + low_word); |
b348b9fd MA |
1476 | } |
1477 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
1478 | { | |
1479 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra, | |
1480 | but the register size used is only 32 bits. Make the address | |
1481 | for the saved register point to the lower 32 bits. */ | |
1482 | PROC_REG_MASK(&temp_proc_desc) |= 1 << reg; | |
639c8612 | 1483 | set_reg_offset (reg, sp + low_word + 8 - MIPS_REGSIZE); |
b348b9fd | 1484 | } |
a00dfa36 MS |
1485 | /* start-sanitize-r5900 */ |
1486 | else if ((high_word & 0xFFE0) == 0x7fa0) /* sq reg,offset($sp) */ | |
1487 | { | |
1488 | /* I don't think we have to worry about the Irix 6.2 N32 ABI | |
1489 | issue noted int he sd reg, offset($sp) case above. */ | |
1490 | PROC_REG_MASK(&temp_proc_desc) |= 1 << reg; | |
1491 | set_reg_offset (reg, sp + low_word); | |
1492 | } | |
1493 | /* end-sanitize-r5900 */ | |
b348b9fd MA |
1494 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ |
1495 | { | |
1496 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
32dab603 | 1497 | if ((long)low_word != PROC_FRAME_OFFSET(&temp_proc_desc)) |
b348b9fd MA |
1498 | frame_addr = sp + low_word; |
1499 | else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) | |
1500 | { | |
1501 | unsigned alloca_adjust; | |
1502 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
1503 | frame_addr = read_next_frame_reg(next_frame, 30); | |
1504 | alloca_adjust = (unsigned)(frame_addr - (sp + low_word)); | |
1505 | if (alloca_adjust > 0) | |
1506 | { | |
1507 | /* FP > SP + frame_size. This may be because | |
1508 | * of an alloca or somethings similar. | |
1509 | * Fix sp to "pre-alloca" value, and try again. | |
1510 | */ | |
1511 | sp += alloca_adjust; | |
1512 | goto restart; | |
bd5635a1 RP |
1513 | } |
1514 | } | |
1515 | } | |
b348b9fd MA |
1516 | /* move $30,$sp. With different versions of gas this will be either |
1517 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
1518 | Accept any one of these. */ | |
1519 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
1520 | { | |
1521 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
1522 | if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) | |
1523 | { | |
1524 | unsigned alloca_adjust; | |
1525 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
1526 | frame_addr = read_next_frame_reg(next_frame, 30); | |
1527 | alloca_adjust = (unsigned)(frame_addr - sp); | |
1528 | if (alloca_adjust > 0) | |
1529 | { | |
1530 | /* FP > SP + frame_size. This may be because | |
1531 | * of an alloca or somethings similar. | |
1532 | * Fix sp to "pre-alloca" value, and try again. | |
1533 | */ | |
1534 | sp += alloca_adjust; | |
1535 | goto restart; | |
97e091b2 MA |
1536 | } |
1537 | } | |
1538 | } | |
b348b9fd MA |
1539 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ |
1540 | { | |
1541 | PROC_REG_MASK(&temp_proc_desc) |= 1 << reg; | |
639c8612 | 1542 | set_reg_offset (reg, frame_addr + low_word); |
bd5635a1 RP |
1543 | } |
1544 | } | |
b348b9fd MA |
1545 | } |
1546 | ||
1547 | static mips_extra_func_info_t | |
1548 | heuristic_proc_desc(start_pc, limit_pc, next_frame) | |
1549 | CORE_ADDR start_pc, limit_pc; | |
1550 | struct frame_info *next_frame; | |
1551 | { | |
1552 | CORE_ADDR sp = read_next_frame_reg (next_frame, SP_REGNUM); | |
1553 | ||
1554 | if (start_pc == 0) return NULL; | |
1555 | memset (&temp_proc_desc, '\0', sizeof(temp_proc_desc)); | |
1556 | memset (&temp_saved_regs, '\0', sizeof(struct frame_saved_regs)); | |
1557 | PROC_LOW_ADDR (&temp_proc_desc) = start_pc; | |
1558 | PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM; | |
1559 | PROC_PC_REG (&temp_proc_desc) = RA_REGNUM; | |
1560 | ||
1561 | if (start_pc + 200 < limit_pc) | |
1562 | limit_pc = start_pc + 200; | |
899c4021 | 1563 | if (pc_is_mips16 (start_pc)) |
b348b9fd MA |
1564 | mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); |
1565 | else | |
1566 | mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
1567 | return &temp_proc_desc; | |
bd5635a1 RP |
1568 | } |
1569 | ||
0f552c5f | 1570 | static mips_extra_func_info_t |
c1fc0935 | 1571 | non_heuristic_proc_desc (pc, addrptr) |
9f9f94aa | 1572 | CORE_ADDR pc; |
c1fc0935 | 1573 | CORE_ADDR *addrptr; |
bd5635a1 | 1574 | { |
c1fc0935 | 1575 | CORE_ADDR startaddr; |
bd5635a1 | 1576 | mips_extra_func_info_t proc_desc; |
0f552c5f | 1577 | struct block *b = block_for_pc(pc); |
48be4c35 | 1578 | struct symbol *sym; |
48be4c35 JK |
1579 | |
1580 | find_pc_partial_function (pc, NULL, &startaddr, NULL); | |
c1fc0935 MA |
1581 | if (addrptr) |
1582 | *addrptr = startaddr; | |
97e091b2 | 1583 | if (b == NULL || PC_IN_CALL_DUMMY (pc, 0, 0)) |
48be4c35 JK |
1584 | sym = NULL; |
1585 | else | |
1586 | { | |
1587 | if (startaddr > BLOCK_START (b)) | |
1588 | /* This is the "pathological" case referred to in a comment in | |
1589 | print_frame_info. It might be better to move this check into | |
1590 | symbol reading. */ | |
1591 | sym = NULL; | |
1592 | else | |
c1fc0935 | 1593 | sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_NAMESPACE, 0, NULL); |
48be4c35 | 1594 | } |
0f552c5f | 1595 | |
e4dbd248 PS |
1596 | /* If we never found a PDR for this function in symbol reading, then |
1597 | examine prologues to find the information. */ | |
0f552c5f | 1598 | if (sym) |
bd5635a1 | 1599 | { |
c1fc0935 MA |
1600 | proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); |
1601 | if (PROC_FRAME_REG (proc_desc) == -1) | |
1602 | return NULL; | |
1603 | else | |
1604 | return proc_desc; | |
1605 | } | |
1606 | else | |
1607 | return NULL; | |
1608 | } | |
1609 | ||
1610 | ||
1611 | static mips_extra_func_info_t | |
1612 | find_proc_desc (pc, next_frame) | |
1613 | CORE_ADDR pc; | |
1614 | struct frame_info *next_frame; | |
1615 | { | |
1616 | mips_extra_func_info_t proc_desc; | |
1617 | CORE_ADDR startaddr; | |
1618 | ||
1619 | proc_desc = non_heuristic_proc_desc (pc, &startaddr); | |
1620 | ||
1621 | if (proc_desc) | |
1622 | { | |
1623 | /* IF this is the topmost frame AND | |
1624 | * (this proc does not have debugging information OR | |
1625 | * the PC is in the procedure prologue) | |
1626 | * THEN create a "heuristic" proc_desc (by analyzing | |
1627 | * the actual code) to replace the "official" proc_desc. | |
1628 | */ | |
1629 | if (next_frame == NULL) | |
1630 | { | |
1631 | struct symtab_and_line val; | |
1632 | struct symbol *proc_symbol = | |
1633 | PROC_DESC_IS_DUMMY(proc_desc) ? 0 : PROC_SYMBOL(proc_desc); | |
1634 | ||
1635 | if (proc_symbol) | |
1636 | { | |
1637 | val = find_pc_line (BLOCK_START | |
1638 | (SYMBOL_BLOCK_VALUE(proc_symbol)), | |
1639 | 0); | |
1640 | val.pc = val.end ? val.end : pc; | |
bd5635a1 | 1641 | } |
c1fc0935 MA |
1642 | if (!proc_symbol || pc < val.pc) |
1643 | { | |
1644 | mips_extra_func_info_t found_heuristic = | |
1645 | heuristic_proc_desc (PROC_LOW_ADDR (proc_desc), | |
1646 | pc, next_frame); | |
1647 | if (found_heuristic) | |
1648 | proc_desc = found_heuristic; | |
bd5635a1 RP |
1649 | } |
1650 | } | |
1651 | } | |
1652 | else | |
1653 | { | |
0f552c5f JG |
1654 | /* Is linked_proc_desc_table really necessary? It only seems to be used |
1655 | by procedure call dummys. However, the procedures being called ought | |
1656 | to have their own proc_descs, and even if they don't, | |
1657 | heuristic_proc_desc knows how to create them! */ | |
1658 | ||
bd5635a1 | 1659 | register struct linked_proc_info *link; |
9f9f94aa | 1660 | |
bd5635a1 | 1661 | for (link = linked_proc_desc_table; link; link = link->next) |
9f9f94aa SS |
1662 | if (PROC_LOW_ADDR(&link->info) <= pc |
1663 | && PROC_HIGH_ADDR(&link->info) > pc) | |
1664 | return &link->info; | |
23d35572 | 1665 | |
48be4c35 JK |
1666 | if (startaddr == 0) |
1667 | startaddr = heuristic_proc_start (pc); | |
1668 | ||
bd5635a1 | 1669 | proc_desc = |
48be4c35 | 1670 | heuristic_proc_desc (startaddr, pc, next_frame); |
bd5635a1 RP |
1671 | } |
1672 | return proc_desc; | |
1673 | } | |
1674 | ||
96431497 MA |
1675 | static CORE_ADDR |
1676 | get_frame_pointer(frame, proc_desc) | |
1677 | struct frame_info *frame; | |
1678 | mips_extra_func_info_t proc_desc; | |
1679 | { | |
af774411 MA |
1680 | return ADDR_BITS_REMOVE ( |
1681 | read_next_frame_reg (frame, PROC_FRAME_REG (proc_desc)) + | |
1682 | PROC_FRAME_OFFSET (proc_desc) - PROC_FRAME_ADJUST (proc_desc)); | |
96431497 MA |
1683 | } |
1684 | ||
bd5635a1 RP |
1685 | mips_extra_func_info_t cached_proc_desc; |
1686 | ||
9f9f94aa | 1687 | CORE_ADDR |
0f552c5f | 1688 | mips_frame_chain(frame) |
9f9f94aa | 1689 | struct frame_info *frame; |
bd5635a1 | 1690 | { |
f781fe93 MA |
1691 | mips_extra_func_info_t proc_desc; |
1692 | CORE_ADDR tmp; | |
1693 | CORE_ADDR saved_pc = FRAME_SAVED_PC(frame); | |
1694 | ||
1695 | if (saved_pc == 0 || inside_entry_file (saved_pc)) | |
1696 | return 0; | |
1697 | ||
1698 | /* Check if the PC is inside a call stub. If it is, fetch the | |
1699 | PC of the caller of that stub. */ | |
1700 | if ((tmp = mips_skip_stub (saved_pc)) != 0) | |
1701 | saved_pc = tmp; | |
1702 | ||
1703 | /* Look up the procedure descriptor for this PC. */ | |
1704 | proc_desc = find_proc_desc(saved_pc, frame); | |
1705 | if (!proc_desc) | |
1706 | return 0; | |
1707 | ||
1708 | cached_proc_desc = proc_desc; | |
1709 | ||
1710 | /* If no frame pointer and frame size is zero, we must be at end | |
1711 | of stack (or otherwise hosed). If we don't check frame size, | |
1712 | we loop forever if we see a zero size frame. */ | |
1713 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM | |
1714 | && PROC_FRAME_OFFSET (proc_desc) == 0 | |
1715 | /* The previous frame from a sigtramp frame might be frameless | |
1716 | and have frame size zero. */ | |
1717 | && !frame->signal_handler_caller) | |
1718 | return 0; | |
1719 | else | |
1720 | return get_frame_pointer (frame, proc_desc); | |
bd5635a1 RP |
1721 | } |
1722 | ||
1723 | void | |
1724 | init_extra_frame_info(fci) | |
1725 | struct frame_info *fci; | |
1726 | { | |
96431497 MA |
1727 | int regnum; |
1728 | ||
bd5635a1 | 1729 | /* Use proc_desc calculated in frame_chain */ |
ee5fb959 JK |
1730 | mips_extra_func_info_t proc_desc = |
1731 | fci->next ? cached_proc_desc : find_proc_desc(fci->pc, fci->next); | |
0f552c5f | 1732 | |
70126bf9 | 1733 | fci->saved_regs = NULL; |
bd5635a1 | 1734 | fci->proc_desc = |
ee5fb959 | 1735 | proc_desc == &temp_proc_desc ? 0 : proc_desc; |
bd5635a1 RP |
1736 | if (proc_desc) |
1737 | { | |
c2a0f1cb | 1738 | /* Fixup frame-pointer - only needed for top frame */ |
5efd597b PS |
1739 | /* This may not be quite right, if proc has a real frame register. |
1740 | Get the value of the frame relative sp, procedure might have been | |
1741 | interrupted by a signal at it's very start. */ | |
70126bf9 KH |
1742 | if (fci->pc == PROC_LOW_ADDR (proc_desc) |
1743 | && !PROC_DESC_IS_DUMMY (proc_desc)) | |
1744 | fci->frame = read_next_frame_reg (fci->next, SP_REGNUM); | |
c2a0f1cb | 1745 | else |
96431497 | 1746 | fci->frame = get_frame_pointer (fci->next, proc_desc); |
bd5635a1 | 1747 | |
48be4c35 | 1748 | if (proc_desc == &temp_proc_desc) |
ee5fb959 | 1749 | { |
09af5868 PS |
1750 | char *name; |
1751 | ||
1752 | /* Do not set the saved registers for a sigtramp frame, | |
1753 | mips_find_saved_registers will do that for us. | |
1754 | We can't use fci->signal_handler_caller, it is not yet set. */ | |
1755 | find_pc_partial_function (fci->pc, &name, | |
1756 | (CORE_ADDR *)NULL,(CORE_ADDR *)NULL); | |
1757 | if (!IN_SIGTRAMP (fci->pc, name)) | |
1758 | { | |
86a51f41 AC |
1759 | fci->saved_regs = (CORE_ADDR*) |
1760 | frame_obstack_alloc (SIZEOF_FRAME_SAVED_REGS); | |
1761 | memcpy (fci->saved_regs, temp_saved_regs.regs, SIZEOF_FRAME_SAVED_REGS); | |
1762 | fci->saved_regs[PC_REGNUM] | |
1763 | = fci->saved_regs[RA_REGNUM]; | |
09af5868 | 1764 | } |
ee5fb959 | 1765 | } |
bd5635a1 RP |
1766 | |
1767 | /* hack: if argument regs are saved, guess these contain args */ | |
96431497 MA |
1768 | fci->num_args = -1; /* assume we can't tell how many args for now */ |
1769 | for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--) | |
1770 | { | |
1771 | if (PROC_REG_MASK(proc_desc) & (1 << regnum)) | |
1772 | { | |
1773 | fci->num_args = regnum - A0_REGNUM + 1; | |
1774 | break; | |
1775 | } | |
1776 | } | |
bd5635a1 | 1777 | } |
bd5635a1 RP |
1778 | } |
1779 | ||
a70dc898 RP |
1780 | /* MIPS stack frames are almost impenetrable. When execution stops, |
1781 | we basically have to look at symbol information for the function | |
1782 | that we stopped in, which tells us *which* register (if any) is | |
1783 | the base of the frame pointer, and what offset from that register | |
1784 | the frame itself is at. | |
1785 | ||
1786 | This presents a problem when trying to examine a stack in memory | |
1787 | (that isn't executing at the moment), using the "frame" command. We | |
1788 | don't have a PC, nor do we have any registers except SP. | |
1789 | ||
1790 | This routine takes two arguments, SP and PC, and tries to make the | |
1791 | cached frames look as if these two arguments defined a frame on the | |
1792 | cache. This allows the rest of info frame to extract the important | |
1793 | arguments without difficulty. */ | |
1794 | ||
9f9f94aa | 1795 | struct frame_info * |
c2a0f1cb ILT |
1796 | setup_arbitrary_frame (argc, argv) |
1797 | int argc; | |
9f9f94aa | 1798 | CORE_ADDR *argv; |
a70dc898 | 1799 | { |
c2a0f1cb ILT |
1800 | if (argc != 2) |
1801 | error ("MIPS frame specifications require two arguments: sp and pc"); | |
1802 | ||
1803 | return create_new_frame (argv[0], argv[1]); | |
a70dc898 RP |
1804 | } |
1805 | ||
a00dfa36 MS |
1806 | /* |
1807 | * STACK_ARGSIZE -- how many bytes does a pushed function arg take up on the stack? | |
1808 | * | |
1809 | * For n32 ABI, eight. | |
1810 | * For all others, he same as the size of a general register. | |
1811 | */ | |
1812 | #if defined (_MIPS_SIM_NABI32) && _MIPS_SIM == _MIPS_SIM_NABI32 | |
1813 | #define MIPS_NABI32 1 | |
1814 | #define STACK_ARGSIZE 8 | |
1815 | #else | |
1816 | #define MIPS_NABI32 0 | |
1817 | #define STACK_ARGSIZE MIPS_REGSIZE | |
1818 | #endif | |
1819 | ||
0f552c5f JG |
1820 | CORE_ADDR |
1821 | mips_push_arguments(nargs, args, sp, struct_return, struct_addr) | |
97e091b2 MA |
1822 | int nargs; |
1823 | value_ptr *args; | |
1824 | CORE_ADDR sp; | |
1825 | int struct_return; | |
1826 | CORE_ADDR struct_addr; | |
bd5635a1 | 1827 | { |
97e091b2 MA |
1828 | int argreg; |
1829 | int float_argreg; | |
1830 | int argnum; | |
1831 | int len = 0; | |
781a59b2 | 1832 | int stack_offset = 0; |
97e091b2 MA |
1833 | |
1834 | /* Macros to round N up or down to the next A boundary; A must be | |
1835 | a power of two. */ | |
1836 | #define ROUND_DOWN(n,a) ((n) & ~((a)-1)) | |
1837 | #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1)) | |
28444bf3 DP |
1838 | |
1839 | /* First ensure that the stack and structure return address (if any) | |
98760eab AC |
1840 | are properly aligned. The stack has to be at least 64-bit aligned |
1841 | even on 32-bit machines, because doubles must be 64-bit aligned. | |
1842 | On at least one MIPS variant, stack frames need to be 128-bit | |
1843 | aligned, so we round to this widest known alignment. */ | |
1844 | sp = ROUND_DOWN (sp, 16); | |
97e091b2 | 1845 | struct_addr = ROUND_DOWN (struct_addr, MIPS_REGSIZE); |
28444bf3 | 1846 | |
97e091b2 MA |
1847 | /* Now make space on the stack for the args. We allocate more |
1848 | than necessary for EABI, because the first few arguments are | |
1849 | passed in registers, but that's OK. */ | |
1850 | for (argnum = 0; argnum < nargs; argnum++) | |
1851 | len += ROUND_UP (TYPE_LENGTH(VALUE_TYPE(args[argnum])), MIPS_REGSIZE); | |
98760eab | 1852 | sp -= ROUND_UP (len, 16); |
97e091b2 MA |
1853 | |
1854 | /* Initialize the integer and float register pointers. */ | |
1855 | argreg = A0_REGNUM; | |
1856 | float_argreg = FPA0_REGNUM; | |
1857 | ||
1858 | /* the struct_return pointer occupies the first parameter-passing reg */ | |
5efd597b | 1859 | if (struct_return) |
97e091b2 MA |
1860 | write_register (argreg++, struct_addr); |
1861 | ||
97e091b2 MA |
1862 | /* Now load as many as possible of the first arguments into |
1863 | registers, and push the rest onto the stack. Loop thru args | |
1864 | from first to last. */ | |
1865 | for (argnum = 0; argnum < nargs; argnum++) | |
5efd597b | 1866 | { |
97e091b2 | 1867 | char *val; |
912e805f | 1868 | char valbuf[MAX_REGISTER_RAW_SIZE]; |
97e091b2 MA |
1869 | value_ptr arg = args[argnum]; |
1870 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
1871 | int len = TYPE_LENGTH (arg_type); | |
1872 | enum type_code typecode = TYPE_CODE (arg_type); | |
1873 | ||
61d2d19a PS |
1874 | /* The EABI passes structures that do not fit in a register by |
1875 | reference. In all other cases, pass the structure by value. */ | |
781a59b2 MS |
1876 | if (MIPS_EABI && len > MIPS_REGSIZE && |
1877 | (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) | |
97e091b2 MA |
1878 | { |
1879 | store_address (valbuf, MIPS_REGSIZE, VALUE_ADDRESS (arg)); | |
08d8f995 | 1880 | typecode = TYPE_CODE_PTR; |
97e091b2 MA |
1881 | len = MIPS_REGSIZE; |
1882 | val = valbuf; | |
1883 | } | |
1884 | else | |
1885 | val = (char *)VALUE_CONTENTS (arg); | |
1886 | ||
1887 | /* 32-bit ABIs always start floating point arguments in an | |
1888 | even-numbered floating point register. */ | |
a00dfa36 | 1889 | if (!FP_REGISTER_DOUBLE && typecode == TYPE_CODE_FLT |
97e091b2 MA |
1890 | && (float_argreg & 1)) |
1891 | float_argreg++; | |
1892 | ||
1893 | /* Floating point arguments passed in registers have to be | |
1894 | treated specially. On 32-bit architectures, doubles | |
1895 | are passed in register pairs; the even register gets | |
c81a76b3 MA |
1896 | the low word, and the odd register gets the high word. |
1897 | On non-EABI processors, the first two floating point arguments are | |
1898 | also copied to general registers, because MIPS16 functions | |
1899 | don't use float registers for arguments. This duplication of | |
1900 | arguments in general registers can't hurt non-MIPS16 functions | |
1901 | because those registers are normally skipped. */ | |
97e091b2 MA |
1902 | if (typecode == TYPE_CODE_FLT |
1903 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM | |
1fe2e66a | 1904 | && MIPS_FPU_TYPE != MIPS_FPU_NONE) |
97e091b2 | 1905 | { |
a00dfa36 | 1906 | if (!FP_REGISTER_DOUBLE && len == 8) |
97e091b2 MA |
1907 | { |
1908 | int low_offset = TARGET_BYTE_ORDER == BIG_ENDIAN ? 4 : 0; | |
1909 | unsigned long regval; | |
1910 | ||
c81a76b3 | 1911 | /* Write the low word of the double to the even register(s). */ |
97e091b2 | 1912 | regval = extract_unsigned_integer (val+low_offset, 4); |
c81a76b3 MA |
1913 | write_register (float_argreg++, regval); |
1914 | if (!MIPS_EABI) | |
1915 | write_register (argreg+1, regval); | |
1916 | ||
1917 | /* Write the high word of the double to the odd register(s). */ | |
97e091b2 | 1918 | regval = extract_unsigned_integer (val+4-low_offset, 4); |
c81a76b3 MA |
1919 | write_register (float_argreg++, regval); |
1920 | if (!MIPS_EABI) | |
1921 | { | |
1922 | write_register (argreg, regval); | |
1923 | argreg += 2; | |
1924 | } | |
97e091b2 MA |
1925 | |
1926 | } | |
1927 | else | |
1928 | { | |
c81a76b3 MA |
1929 | /* This is a floating point value that fits entirely |
1930 | in a single register. */ | |
97e091b2 MA |
1931 | CORE_ADDR regval = extract_address (val, len); |
1932 | write_register (float_argreg++, regval); | |
c81a76b3 MA |
1933 | if (!MIPS_EABI) |
1934 | { | |
1935 | write_register (argreg, regval); | |
a00dfa36 | 1936 | argreg += FP_REGISTER_DOUBLE ? 1 : 2; |
c81a76b3 | 1937 | } |
97e091b2 | 1938 | } |
97e091b2 MA |
1939 | } |
1940 | else | |
1941 | { | |
1942 | /* Copy the argument to general registers or the stack in | |
1943 | register-sized pieces. Large arguments are split between | |
1944 | registers and stack. */ | |
781a59b2 MS |
1945 | /* Note: structs whose size is not a multiple of MIPS_REGSIZE |
1946 | are treated specially: Irix cc passes them in registers | |
1947 | where gcc sometimes puts them on the stack. For maximum | |
1948 | compatibility, we will put them in both places. */ | |
1949 | ||
1950 | int odd_sized_struct = ((len > MIPS_REGSIZE) && | |
1951 | (len % MIPS_REGSIZE != 0)); | |
97e091b2 MA |
1952 | while (len > 0) |
1953 | { | |
1954 | int partial_len = len < MIPS_REGSIZE ? len : MIPS_REGSIZE; | |
61d2d19a | 1955 | |
781a59b2 MS |
1956 | if (argreg > MIPS_LAST_ARG_REGNUM || odd_sized_struct) |
1957 | { | |
1958 | /* Write this portion of the argument to the stack. */ | |
912e805f AC |
1959 | /* Should shorter than int integer values be |
1960 | promoted to int before being stored? */ | |
781a59b2 | 1961 | |
912e805f | 1962 | int longword_offset = 0; |
781a59b2 | 1963 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
a00dfa36 | 1964 | if (STACK_ARGSIZE == 8 && |
781a59b2 MS |
1965 | (typecode == TYPE_CODE_INT || |
1966 | typecode == TYPE_CODE_PTR || | |
1967 | typecode == TYPE_CODE_FLT) && len <= 4) | |
a00dfa36 | 1968 | longword_offset = STACK_ARGSIZE - len; |
781a59b2 MS |
1969 | else if ((typecode == TYPE_CODE_STRUCT || |
1970 | typecode == TYPE_CODE_UNION) && | |
a00dfa36 MS |
1971 | TYPE_LENGTH (arg_type) < STACK_ARGSIZE) |
1972 | longword_offset = STACK_ARGSIZE - len; | |
781a59b2 MS |
1973 | |
1974 | write_memory (sp + stack_offset + longword_offset, | |
1975 | val, partial_len); | |
1976 | } | |
1977 | ||
1978 | /* Note!!! This is NOT an else clause. | |
1979 | Odd sized structs may go thru BOTH paths. */ | |
97e091b2 MA |
1980 | if (argreg <= MIPS_LAST_ARG_REGNUM) |
1981 | { | |
61d2d19a PS |
1982 | CORE_ADDR regval = extract_address (val, partial_len); |
1983 | ||
c430260c MS |
1984 | /* A non-floating-point argument being passed in a |
1985 | general register. If a struct or union, and if | |
91ee2779 JL |
1986 | the remaining length is smaller than the register |
1987 | size, we have to adjust the register value on | |
1988 | big endian targets. | |
158bda58 | 1989 | |
c430260c MS |
1990 | It does not seem to be necessary to do the |
1991 | same for integral types. | |
158bda58 | 1992 | |
0e52a532 SG |
1993 | Also don't do this adjustment on EABI and O64 |
1994 | binaries. */ | |
158bda58 | 1995 | |
0e52a532 SG |
1996 | if (!MIPS_EABI |
1997 | && (MIPS_REGSIZE < 8) | |
1998 | && TARGET_BYTE_ORDER == BIG_ENDIAN | |
1999 | && (partial_len < MIPS_REGSIZE) | |
2000 | && (typecode == TYPE_CODE_STRUCT || | |
2001 | typecode == TYPE_CODE_UNION)) | |
158bda58 MS |
2002 | regval <<= ((MIPS_REGSIZE - partial_len) * |
2003 | TARGET_CHAR_BIT); | |
2004 | ||
97e091b2 MA |
2005 | write_register (argreg, regval); |
2006 | argreg++; | |
2007 | ||
2008 | /* If this is the old ABI, prevent subsequent floating | |
2009 | point arguments from being passed in floating point | |
2010 | registers. */ | |
2011 | if (!MIPS_EABI) | |
2012 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
2013 | } | |
97e091b2 MA |
2014 | |
2015 | len -= partial_len; | |
2016 | val += partial_len; | |
781a59b2 MS |
2017 | |
2018 | /* The offset onto the stack at which we will start | |
2019 | copying parameters (after the registers are used up) | |
2020 | begins at (4 * MIPS_REGSIZE) in the old ABI. This | |
2021 | leaves room for the "home" area for register parameters. | |
2022 | ||
a00dfa36 MS |
2023 | In the new EABI (and the NABI32), the 8 register parameters |
2024 | do not have "home" stack space reserved for them, so the | |
781a59b2 MS |
2025 | stack offset does not get incremented until after |
2026 | we have used up the 8 parameter registers. */ | |
a00dfa36 MS |
2027 | |
2028 | if (!(MIPS_EABI || MIPS_NABI32) || | |
2029 | argnum >= 8) | |
2030 | stack_offset += ROUND_UP (partial_len, STACK_ARGSIZE); | |
97e091b2 MA |
2031 | } |
2032 | } | |
5efd597b | 2033 | } |
97e091b2 MA |
2034 | |
2035 | /* Set the return address register to point to the entry | |
2036 | point of the program, where a breakpoint lies in wait. */ | |
2037 | write_register (RA_REGNUM, CALL_DUMMY_ADDRESS()); | |
2038 | ||
2039 | /* Return adjusted stack pointer. */ | |
bd5635a1 RP |
2040 | return sp; |
2041 | } | |
2042 | ||
c81a76b3 | 2043 | static void |
28444bf3 DP |
2044 | mips_push_register(CORE_ADDR *sp, int regno) |
2045 | { | |
2046 | char buffer[MAX_REGISTER_RAW_SIZE]; | |
2047 | int regsize = REGISTER_RAW_SIZE (regno); | |
2048 | ||
2049 | *sp -= regsize; | |
2050 | read_register_gen (regno, buffer); | |
2051 | write_memory (*sp, buffer, regsize); | |
2052 | } | |
2053 | ||
2054 | /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */ | |
e03c0cc6 | 2055 | #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1)) |
bd5635a1 RP |
2056 | |
2057 | void | |
2058 | mips_push_dummy_frame() | |
2059 | { | |
2060 | int ireg; | |
2061 | struct linked_proc_info *link = (struct linked_proc_info*) | |
2062 | xmalloc(sizeof(struct linked_proc_info)); | |
2063 | mips_extra_func_info_t proc_desc = &link->info; | |
96431497 | 2064 | CORE_ADDR sp = ADDR_BITS_REMOVE (read_register (SP_REGNUM)); |
28444bf3 | 2065 | CORE_ADDR old_sp = sp; |
bd5635a1 RP |
2066 | link->next = linked_proc_desc_table; |
2067 | linked_proc_desc_table = link; | |
28444bf3 DP |
2068 | |
2069 | /* FIXME! are these correct ? */ | |
bd5635a1 | 2070 | #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */ |
28444bf3 | 2071 | #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1)) |
bd5635a1 | 2072 | #define FLOAT_REG_SAVE_MASK MASK(0,19) |
e4dbd248 PS |
2073 | #define FLOAT_SINGLE_REG_SAVE_MASK \ |
2074 | ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0)) | |
bd5635a1 RP |
2075 | /* |
2076 | * The registers we must save are all those not preserved across | |
2077 | * procedure calls. Dest_Reg (see tm-mips.h) must also be saved. | |
28444bf3 DP |
2078 | * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI |
2079 | * and FP Control/Status registers. | |
2080 | * | |
bd5635a1 RP |
2081 | * |
2082 | * Dummy frame layout: | |
2083 | * (high memory) | |
2084 | * Saved PC | |
2085 | * Saved MMHI, MMLO, FPC_CSR | |
2086 | * Saved R31 | |
2087 | * Saved R28 | |
2088 | * ... | |
2089 | * Saved R1 | |
2090 | * Saved D18 (i.e. F19, F18) | |
2091 | * ... | |
2092 | * Saved D0 (i.e. F1, F0) | |
f9f8c14b | 2093 | * Argument build area and stack arguments written via mips_push_arguments |
bd5635a1 RP |
2094 | * (low memory) |
2095 | */ | |
28444bf3 DP |
2096 | |
2097 | /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */ | |
28444bf3 DP |
2098 | PROC_FRAME_REG(proc_desc) = PUSH_FP_REGNUM; |
2099 | PROC_FRAME_OFFSET(proc_desc) = 0; | |
639c8612 | 2100 | PROC_FRAME_ADJUST(proc_desc) = 0; |
28444bf3 DP |
2101 | mips_push_register (&sp, PC_REGNUM); |
2102 | mips_push_register (&sp, HI_REGNUM); | |
2103 | mips_push_register (&sp, LO_REGNUM); | |
1fe2e66a | 2104 | mips_push_register (&sp, MIPS_FPU_TYPE == MIPS_FPU_NONE ? 0 : FCRCS_REGNUM); |
28444bf3 DP |
2105 | |
2106 | /* Save general CPU registers */ | |
bd5635a1 | 2107 | PROC_REG_MASK(proc_desc) = GEN_REG_SAVE_MASK; |
a00dfa36 MS |
2108 | /* PROC_REG_OFFSET is the offset of the first saved register from FP. */ |
2109 | PROC_REG_OFFSET(proc_desc) = sp - old_sp - MIPS_REGSIZE; | |
bd5635a1 RP |
2110 | for (ireg = 32; --ireg >= 0; ) |
2111 | if (PROC_REG_MASK(proc_desc) & (1 << ireg)) | |
28444bf3 | 2112 | mips_push_register (&sp, ireg); |
3fed1c4a | 2113 | |
28444bf3 DP |
2114 | /* Save floating point registers starting with high order word */ |
2115 | PROC_FREG_MASK(proc_desc) = | |
1fe2e66a AC |
2116 | MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? FLOAT_REG_SAVE_MASK |
2117 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? FLOAT_SINGLE_REG_SAVE_MASK : 0; | |
a00dfa36 MS |
2118 | /* PROC_FREG_OFFSET is the offset of the first saved *double* register |
2119 | from FP. */ | |
2120 | PROC_FREG_OFFSET(proc_desc) = sp - old_sp - 8; | |
bd5635a1 RP |
2121 | for (ireg = 32; --ireg >= 0; ) |
2122 | if (PROC_FREG_MASK(proc_desc) & (1 << ireg)) | |
28444bf3 | 2123 | mips_push_register (&sp, ireg + FP0_REGNUM); |
3fed1c4a | 2124 | |
f9f8c14b MA |
2125 | /* Update the frame pointer for the call dummy and the stack pointer. |
2126 | Set the procedure's starting and ending addresses to point to the | |
2127 | call dummy address at the entry point. */ | |
2128 | write_register (PUSH_FP_REGNUM, old_sp); | |
bd5635a1 | 2129 | write_register (SP_REGNUM, sp); |
97e091b2 MA |
2130 | PROC_LOW_ADDR(proc_desc) = CALL_DUMMY_ADDRESS(); |
2131 | PROC_HIGH_ADDR(proc_desc) = CALL_DUMMY_ADDRESS() + 4; | |
bd5635a1 RP |
2132 | SET_PROC_DESC_IS_DUMMY(proc_desc); |
2133 | PROC_PC_REG(proc_desc) = RA_REGNUM; | |
2134 | } | |
2135 | ||
2136 | void | |
2137 | mips_pop_frame() | |
dac4929a SG |
2138 | { |
2139 | register int regnum; | |
9f9f94aa SS |
2140 | struct frame_info *frame = get_current_frame (); |
2141 | CORE_ADDR new_sp = FRAME_FP (frame); | |
dac4929a | 2142 | |
a70dc898 | 2143 | mips_extra_func_info_t proc_desc = frame->proc_desc; |
dac4929a SG |
2144 | |
2145 | write_register (PC_REGNUM, FRAME_SAVED_PC(frame)); | |
70126bf9 KH |
2146 | if (frame->saved_regs == NULL) |
2147 | mips_find_saved_regs (frame); | |
61d2d19a | 2148 | for (regnum = 0; regnum < NUM_REGS; regnum++) |
dac4929a | 2149 | { |
61d2d19a | 2150 | if (regnum != SP_REGNUM && regnum != PC_REGNUM |
86a51f41 | 2151 | && frame->saved_regs[regnum]) |
61d2d19a | 2152 | write_register (regnum, |
86a51f41 | 2153 | read_memory_integer (frame->saved_regs[regnum], |
61d2d19a | 2154 | MIPS_REGSIZE)); |
dac4929a SG |
2155 | } |
2156 | write_register (SP_REGNUM, new_sp); | |
2157 | flush_cached_frames (); | |
dac4929a | 2158 | |
199b2450 | 2159 | if (proc_desc && PROC_DESC_IS_DUMMY(proc_desc)) |
bd5635a1 | 2160 | { |
dac4929a SG |
2161 | struct linked_proc_info *pi_ptr, *prev_ptr; |
2162 | ||
2163 | for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL; | |
2164 | pi_ptr != NULL; | |
2165 | prev_ptr = pi_ptr, pi_ptr = pi_ptr->next) | |
2166 | { | |
2167 | if (&pi_ptr->info == proc_desc) | |
2168 | break; | |
2169 | } | |
2170 | ||
2171 | if (pi_ptr == NULL) | |
2172 | error ("Can't locate dummy extra frame info\n"); | |
2173 | ||
2174 | if (prev_ptr != NULL) | |
2175 | prev_ptr->next = pi_ptr->next; | |
2176 | else | |
2177 | linked_proc_desc_table = pi_ptr->next; | |
2178 | ||
2179 | free (pi_ptr); | |
2180 | ||
28444bf3 DP |
2181 | write_register (HI_REGNUM, |
2182 | read_memory_integer (new_sp - 2*MIPS_REGSIZE, MIPS_REGSIZE)); | |
2183 | write_register (LO_REGNUM, | |
2184 | read_memory_integer (new_sp - 3*MIPS_REGSIZE, MIPS_REGSIZE)); | |
1fe2e66a | 2185 | if (MIPS_FPU_TYPE != MIPS_FPU_NONE) |
28444bf3 DP |
2186 | write_register (FCRCS_REGNUM, |
2187 | read_memory_integer (new_sp - 4*MIPS_REGSIZE, MIPS_REGSIZE)); | |
bd5635a1 | 2188 | } |
bd5635a1 RP |
2189 | } |
2190 | ||
0f552c5f | 2191 | static void |
a70dc898 | 2192 | mips_print_register (regnum, all) |
bd5635a1 RP |
2193 | int regnum, all; |
2194 | { | |
e4dbd248 | 2195 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; |
bd5635a1 | 2196 | |
48be4c35 JK |
2197 | /* Get the data in raw format. */ |
2198 | if (read_relative_register_raw_bytes (regnum, raw_buffer)) | |
2199 | { | |
9ddf9aa9 | 2200 | printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum)); |
48be4c35 JK |
2201 | return; |
2202 | } | |
2203 | ||
781a59b2 | 2204 | /* If an even floating point register, also print as double. */ |
899c4021 | 2205 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT |
e4dbd248 | 2206 | && !((regnum-FP0_REGNUM) & 1)) |
a00dfa36 | 2207 | if (REGISTER_RAW_SIZE(regnum) == 4) /* this would be silly on MIPS64 or N32 (Irix 6) */ |
899c4021 MA |
2208 | { |
2209 | char dbuffer[2 * MAX_REGISTER_RAW_SIZE]; | |
48be4c35 | 2210 | |
899c4021 MA |
2211 | read_relative_register_raw_bytes (regnum, dbuffer); |
2212 | read_relative_register_raw_bytes (regnum+1, dbuffer+MIPS_REGSIZE); | |
2213 | REGISTER_CONVERT_TO_TYPE (regnum, builtin_type_double, dbuffer); | |
c81a76b3 | 2214 | |
899c4021 | 2215 | printf_filtered ("(d%d: ", regnum-FP0_REGNUM); |
4ef1f467 | 2216 | val_print (builtin_type_double, dbuffer, 0, 0, |
899c4021 MA |
2217 | gdb_stdout, 0, 1, 0, Val_pretty_default); |
2218 | printf_filtered ("); "); | |
2219 | } | |
9ddf9aa9 | 2220 | fputs_filtered (REGISTER_NAME (regnum), gdb_stdout); |
48be4c35 JK |
2221 | |
2222 | /* The problem with printing numeric register names (r26, etc.) is that | |
2223 | the user can't use them on input. Probably the best solution is to | |
2224 | fix it so that either the numeric or the funky (a2, etc.) names | |
2225 | are accepted on input. */ | |
28444bf3 | 2226 | if (regnum < MIPS_NUMREGS) |
48be4c35 JK |
2227 | printf_filtered ("(r%d): ", regnum); |
2228 | else | |
2229 | printf_filtered (": "); | |
bd5635a1 | 2230 | |
48be4c35 | 2231 | /* If virtual format is floating, print it that way. */ |
ac57e5ad | 2232 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
a00dfa36 | 2233 | if (FP_REGISTER_DOUBLE) |
899c4021 MA |
2234 | { /* show 8-byte floats as float AND double: */ |
2235 | int offset = 4 * (TARGET_BYTE_ORDER == BIG_ENDIAN); | |
2236 | ||
2237 | printf_filtered (" (float) "); | |
4ef1f467 | 2238 | val_print (builtin_type_float, raw_buffer + offset, 0, 0, |
899c4021 MA |
2239 | gdb_stdout, 0, 1, 0, Val_pretty_default); |
2240 | printf_filtered (", (double) "); | |
4ef1f467 | 2241 | val_print (builtin_type_double, raw_buffer, 0, 0, |
899c4021 MA |
2242 | gdb_stdout, 0, 1, 0, Val_pretty_default); |
2243 | } | |
2244 | else | |
4ef1f467 | 2245 | val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0, |
899c4021 | 2246 | gdb_stdout, 0, 1, 0, Val_pretty_default); |
48be4c35 JK |
2247 | /* Else print as integer in hex. */ |
2248 | else | |
ac57e5ad SS |
2249 | print_scalar_formatted (raw_buffer, REGISTER_VIRTUAL_TYPE (regnum), |
2250 | 'x', 0, gdb_stdout); | |
bd5635a1 RP |
2251 | } |
2252 | ||
899c4021 MA |
2253 | /* Replacement for generic do_registers_info. |
2254 | Print regs in pretty columns. */ | |
2255 | ||
2256 | static int | |
2257 | do_fp_register_row (regnum) | |
2258 | int regnum; | |
2259 | { /* do values for FP (float) regs */ | |
cf93a3aa ILT |
2260 | char *raw_buffer[2]; |
2261 | char *dbl_buffer; | |
899c4021 MA |
2262 | /* use HI and LO to control the order of combining two flt regs */ |
2263 | int HI = (TARGET_BYTE_ORDER == BIG_ENDIAN); | |
2264 | int LO = (TARGET_BYTE_ORDER != BIG_ENDIAN); | |
2265 | double doub, flt1, flt2; /* doubles extracted from raw hex data */ | |
2266 | int inv1, inv2, inv3; | |
2267 | ||
cf93a3aa ILT |
2268 | raw_buffer[0] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM)); |
2269 | raw_buffer[1] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM)); | |
2270 | dbl_buffer = (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM)); | |
2271 | ||
899c4021 MA |
2272 | /* Get the data in raw format. */ |
2273 | if (read_relative_register_raw_bytes (regnum, raw_buffer[HI])) | |
9ddf9aa9 | 2274 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); |
899c4021 MA |
2275 | if (REGISTER_RAW_SIZE(regnum) == 4) |
2276 | { | |
2277 | /* 4-byte registers: we can fit two registers per row. */ | |
2278 | /* Also print every pair of 4-byte regs as an 8-byte double. */ | |
2279 | if (read_relative_register_raw_bytes (regnum + 1, raw_buffer[LO])) | |
2280 | error ("can't read register %d (%s)", | |
9ddf9aa9 | 2281 | regnum + 1, REGISTER_NAME (regnum + 1)); |
899c4021 MA |
2282 | |
2283 | /* copy the two floats into one double, and unpack both */ | |
2284 | memcpy (dbl_buffer, raw_buffer, sizeof(dbl_buffer)); | |
2285 | flt1 = unpack_double (builtin_type_float, raw_buffer[HI], &inv1); | |
2286 | flt2 = unpack_double (builtin_type_float, raw_buffer[LO], &inv2); | |
2287 | doub = unpack_double (builtin_type_double, dbl_buffer, &inv3); | |
2288 | ||
2289 | printf_filtered (inv1 ? " %-5s: <invalid float>" : | |
9ddf9aa9 | 2290 | " %-5s%-17.9g", REGISTER_NAME (regnum), flt1); |
899c4021 | 2291 | printf_filtered (inv2 ? " %-5s: <invalid float>" : |
9ddf9aa9 | 2292 | " %-5s%-17.9g", REGISTER_NAME (regnum + 1), flt2); |
899c4021 MA |
2293 | printf_filtered (inv3 ? " dbl: <invalid double>\n" : |
2294 | " dbl: %-24.17g\n", doub); | |
2295 | /* may want to do hex display here (future enhancement) */ | |
2296 | regnum +=2; | |
2297 | } | |
2298 | else | |
2299 | { /* eight byte registers: print each one as float AND as double. */ | |
2300 | int offset = 4 * (TARGET_BYTE_ORDER == BIG_ENDIAN); | |
2301 | ||
2302 | memcpy (dbl_buffer, raw_buffer[HI], sizeof(dbl_buffer)); | |
2303 | flt1 = unpack_double (builtin_type_float, | |
2304 | &raw_buffer[HI][offset], &inv1); | |
2305 | doub = unpack_double (builtin_type_double, dbl_buffer, &inv3); | |
2306 | ||
2307 | printf_filtered (inv1 ? " %-5s: <invalid float>" : | |
9ddf9aa9 | 2308 | " %-5s flt: %-17.9g", REGISTER_NAME (regnum), flt1); |
899c4021 MA |
2309 | printf_filtered (inv3 ? " dbl: <invalid double>\n" : |
2310 | " dbl: %-24.17g\n", doub); | |
2311 | /* may want to do hex display here (future enhancement) */ | |
2312 | regnum++; | |
2313 | } | |
2314 | return regnum; | |
2315 | } | |
2316 | ||
2317 | /* Print a row's worth of GP (int) registers, with name labels above */ | |
2318 | ||
2319 | static int | |
2320 | do_gp_register_row (regnum) | |
2321 | int regnum; | |
912e805f AC |
2322 | { |
2323 | /* do values for GP (int) regs */ | |
2324 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; | |
2325 | int ncols = (MIPS_REGSIZE == 8 ? 4 : 8); /* display cols per row */ | |
2326 | int col, byte; | |
2327 | int start_regnum = regnum; | |
2328 | int numregs = NUM_REGS; | |
2329 | ||
2330 | /* start-sanitize-sky */ | |
98760eab AC |
2331 | #ifdef NUM_CORE_REGS |
2332 | numregs = NUM_CORE_REGS; | |
912e805f AC |
2333 | #endif |
2334 | /* end-sanitize-sky */ | |
899c4021 MA |
2335 | |
2336 | /* For GP registers, we print a separate row of names above the vals */ | |
2337 | printf_filtered (" "); | |
912e805f | 2338 | for (col = 0; col < ncols && regnum < numregs; regnum++) |
899c4021 | 2339 | { |
9ddf9aa9 | 2340 | if (*REGISTER_NAME (regnum) == '\0') |
899c4021 MA |
2341 | continue; /* unused register */ |
2342 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) | |
2343 | break; /* end the row: reached FP register */ | |
2344 | printf_filtered (MIPS_REGSIZE == 8 ? "%17s" : "%9s", | |
9ddf9aa9 | 2345 | REGISTER_NAME (regnum)); |
899c4021 MA |
2346 | col++; |
2347 | } | |
2348 | printf_filtered (start_regnum < MIPS_NUMREGS ? "\n R%-4d" : "\n ", | |
2349 | start_regnum); /* print the R0 to R31 names */ | |
2350 | ||
2351 | regnum = start_regnum; /* go back to start of row */ | |
2352 | /* now print the values in hex, 4 or 8 to the row */ | |
912e805f | 2353 | for (col = 0; col < ncols && regnum < numregs; regnum++) |
899c4021 | 2354 | { |
9ddf9aa9 | 2355 | if (*REGISTER_NAME (regnum) == '\0') |
899c4021 MA |
2356 | continue; /* unused register */ |
2357 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) | |
2358 | break; /* end row: reached FP register */ | |
2359 | /* OK: get the data in raw format. */ | |
2360 | if (read_relative_register_raw_bytes (regnum, raw_buffer)) | |
9ddf9aa9 | 2361 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); |
912e805f AC |
2362 | /* pad small registers */ |
2363 | for (byte = 0; byte < (MIPS_REGSIZE - REGISTER_RAW_SIZE (regnum)); byte++) | |
2364 | printf_filtered (" "); | |
899c4021 MA |
2365 | /* Now print the register value in hex, endian order. */ |
2366 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
2367 | for (byte = 0; byte < REGISTER_RAW_SIZE (regnum); byte++) | |
2368 | printf_filtered ("%02x", (unsigned char) raw_buffer[byte]); | |
2369 | else | |
2370 | for (byte = REGISTER_RAW_SIZE (regnum) - 1; byte >= 0; byte--) | |
2371 | printf_filtered ("%02x", (unsigned char) raw_buffer[byte]); | |
2372 | printf_filtered (" "); | |
2373 | col++; | |
2374 | } | |
2375 | if (col > 0) /* ie. if we actually printed anything... */ | |
2376 | printf_filtered ("\n"); | |
2377 | ||
2378 | return regnum; | |
2379 | } | |
2380 | ||
2381 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
9f9f94aa | 2382 | |
0f552c5f | 2383 | void |
361bf6ee | 2384 | mips_do_registers_info (regnum, fpregs) |
bd5635a1 | 2385 | int regnum; |
361bf6ee | 2386 | int fpregs; |
bd5635a1 | 2387 | { |
899c4021 | 2388 | if (regnum != -1) /* do one specified register */ |
9f9f94aa | 2389 | { |
9ddf9aa9 | 2390 | if (*(REGISTER_NAME (regnum)) == '\0') |
9f9f94aa SS |
2391 | error ("Not a valid register for the current processor type"); |
2392 | ||
bd5635a1 RP |
2393 | mips_print_register (regnum, 0); |
2394 | printf_filtered ("\n"); | |
9f9f94aa | 2395 | } |
899c4021 | 2396 | else /* do all (or most) registers */ |
9f9f94aa | 2397 | { |
899c4021 MA |
2398 | regnum = 0; |
2399 | while (regnum < NUM_REGS) | |
912e805f AC |
2400 | { |
2401 | if (TYPE_CODE(REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) | |
2402 | if (fpregs) /* true for "INFO ALL-REGISTERS" command */ | |
2403 | regnum = do_fp_register_row (regnum); /* FP regs */ | |
2404 | else | |
2405 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
899c4021 | 2406 | else |
912e805f AC |
2407 | regnum = do_gp_register_row (regnum); /* GP (int) regs */ |
2408 | /* start-sanitize-sky */ | |
98760eab | 2409 | #ifdef NUM_CORE_REGS |
912e805f AC |
2410 | /* For the sky project, NUM_REGS includes the vector slaves, |
2411 | which are handled elsewhere */ | |
98760eab | 2412 | if (regnum >= NUM_CORE_REGS) |
912e805f AC |
2413 | break; |
2414 | #endif | |
2415 | /* end-sanitize-sky */ | |
2416 | } | |
9f9f94aa | 2417 | } |
bd5635a1 | 2418 | } |
9f9f94aa | 2419 | |
bd5635a1 RP |
2420 | /* Return number of args passed to a frame. described by FIP. |
2421 | Can return -1, meaning no way to tell. */ | |
2422 | ||
0f552c5f | 2423 | int |
9f9f94aa SS |
2424 | mips_frame_num_args (frame) |
2425 | struct frame_info *frame; | |
bd5635a1 | 2426 | { |
9f9f94aa SS |
2427 | #if 0 /* FIXME Use or lose this! */ |
2428 | struct chain_info_t *p; | |
bd5635a1 | 2429 | |
9f9f94aa SS |
2430 | p = mips_find_cached_frame (FRAME_FP (frame)); |
2431 | if (p->valid) | |
2432 | return p->the_info.numargs; | |
bd5635a1 | 2433 | #endif |
9f9f94aa | 2434 | return -1; |
bd5635a1 | 2435 | } |
96431497 | 2436 | |
427fec5d | 2437 | /* Is this a branch with a delay slot? */ |
9f9f94aa | 2438 | |
b5aff268 JK |
2439 | static int is_delayed PARAMS ((unsigned long)); |
2440 | ||
ee5fb959 JK |
2441 | static int |
2442 | is_delayed (insn) | |
2443 | unsigned long insn; | |
2444 | { | |
2445 | int i; | |
2446 | for (i = 0; i < NUMOPCODES; ++i) | |
2447 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
2448 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
2449 | break; | |
427fec5d JK |
2450 | return (i < NUMOPCODES |
2451 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
2452 | | INSN_COND_BRANCH_DELAY | |
2453 | | INSN_COND_BRANCH_LIKELY))); | |
ee5fb959 | 2454 | } |
b5aff268 JK |
2455 | |
2456 | int | |
2457 | mips_step_skips_delay (pc) | |
2458 | CORE_ADDR pc; | |
2459 | { | |
96431497 | 2460 | char buf[MIPS_INSTLEN]; |
b5aff268 | 2461 | |
f9f8c14b | 2462 | /* There is no branch delay slot on MIPS16. */ |
899c4021 | 2463 | if (pc_is_mips16 (pc)) |
f9f8c14b MA |
2464 | return 0; |
2465 | ||
96431497 | 2466 | if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0) |
b5aff268 JK |
2467 | /* If error reading memory, guess that it is not a delayed branch. */ |
2468 | return 0; | |
96431497 | 2469 | return is_delayed ((unsigned long)extract_unsigned_integer (buf, MIPS_INSTLEN)); |
b5aff268 | 2470 | } |
ee5fb959 | 2471 | |
bd5635a1 | 2472 | |
20fa0902 MA |
2473 | /* Skip the PC past function prologue instructions (32-bit version). |
2474 | This is a helper function for mips_skip_prologue. */ | |
2475 | ||
2476 | static CORE_ADDR | |
2477 | mips32_skip_prologue (pc, lenient) | |
2478 | CORE_ADDR pc; /* starting PC to search from */ | |
ee5fb959 | 2479 | int lenient; |
bd5635a1 | 2480 | { |
28444bf3 | 2481 | t_inst inst; |
20fa0902 | 2482 | CORE_ADDR end_pc; |
0b0d6c3f | 2483 | int seen_sp_adjust = 0; |
ac57e5ad | 2484 | int load_immediate_bytes = 0; |
bd5635a1 | 2485 | |
e157305c PS |
2486 | /* Skip the typical prologue instructions. These are the stack adjustment |
2487 | instruction and the instructions that save registers on the stack | |
2488 | or in the gcc frame. */ | |
20fa0902 | 2489 | for (end_pc = pc + 100; pc < end_pc; pc += MIPS_INSTLEN) |
ee5fb959 | 2490 | { |
b348b9fd | 2491 | unsigned long high_word; |
ee5fb959 | 2492 | |
c81a76b3 | 2493 | inst = mips_fetch_instruction (pc); |
b348b9fd | 2494 | high_word = (inst >> 16) & 0xffff; |
ee5fb959 | 2495 | |
002a422b | 2496 | #if 0 |
ee5fb959 JK |
2497 | if (lenient && is_delayed (inst)) |
2498 | continue; | |
002a422b | 2499 | #endif |
ee5fb959 | 2500 | |
b348b9fd MA |
2501 | if (high_word == 0x27bd /* addiu $sp,$sp,offset */ |
2502 | || high_word == 0x67bd) /* daddiu $sp,$sp,offset */ | |
0b0d6c3f | 2503 | seen_sp_adjust = 1; |
ac57e5ad SS |
2504 | else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */ |
2505 | inst == 0x03a8e823) /* subu $sp,$sp,$t0 */ | |
2506 | seen_sp_adjust = 1; | |
97e091b2 | 2507 | else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */ |
a00dfa36 MS |
2508 | /* start-sanitize-r5900 */ |
2509 | || (inst & 0xFFE00000) == 0x7FA00000 /* sq reg,n($sp) */ | |
2510 | /* end-sanitize-r5900 */ | |
97e091b2 MA |
2511 | || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */ |
2512 | && (inst & 0x001F0000)) /* reg != $zero */ | |
2513 | continue; | |
2514 | ||
e157305c PS |
2515 | else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */ |
2516 | continue; | |
2517 | else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000)) | |
2518 | /* sx reg,n($s8) */ | |
2519 | continue; /* reg != $zero */ | |
1d9489c1 JK |
2520 | |
2521 | /* move $s8,$sp. With different versions of gas this will be either | |
20fa0902 MA |
2522 | `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'. |
2523 | Accept any one of these. */ | |
2524 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
0b0d6c3f | 2525 | continue; |
1d9489c1 | 2526 | |
1b71de8e PS |
2527 | else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */ |
2528 | continue; | |
b348b9fd | 2529 | else if (high_word == 0x3c1c) /* lui $gp,n */ |
e03c0cc6 | 2530 | continue; |
b348b9fd | 2531 | else if (high_word == 0x279c) /* addiu $gp,$gp,n */ |
e03c0cc6 ILT |
2532 | continue; |
2533 | else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
2534 | || inst == 0x033ce021) /* addu $gp,$t9,$gp */ | |
2535 | continue; | |
ac57e5ad SS |
2536 | /* The following instructions load $at or $t0 with an immediate |
2537 | value in preparation for a stack adjustment via | |
2538 | subu $sp,$sp,[$at,$t0]. These instructions could also initialize | |
2539 | a local variable, so we accept them only before a stack adjustment | |
2540 | instruction was seen. */ | |
2541 | else if (!seen_sp_adjust) | |
2542 | { | |
b348b9fd MA |
2543 | if (high_word == 0x3c01 || /* lui $at,n */ |
2544 | high_word == 0x3c08) /* lui $t0,n */ | |
ac57e5ad | 2545 | { |
28444bf3 | 2546 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ |
ac57e5ad SS |
2547 | continue; |
2548 | } | |
b348b9fd MA |
2549 | else if (high_word == 0x3421 || /* ori $at,$at,n */ |
2550 | high_word == 0x3508 || /* ori $t0,$t0,n */ | |
2551 | high_word == 0x3401 || /* ori $at,$zero,n */ | |
2552 | high_word == 0x3408) /* ori $t0,$zero,n */ | |
ac57e5ad | 2553 | { |
28444bf3 | 2554 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ |
ac57e5ad SS |
2555 | continue; |
2556 | } | |
2557 | else | |
2558 | break; | |
2559 | } | |
0b0d6c3f | 2560 | else |
ac57e5ad | 2561 | break; |
d747e0af | 2562 | } |
e157305c | 2563 | |
ac57e5ad SS |
2564 | /* In a frameless function, we might have incorrectly |
2565 | skipped some load immediate instructions. Undo the skipping | |
2566 | if the load immediate was not followed by a stack adjustment. */ | |
2567 | if (load_immediate_bytes && !seen_sp_adjust) | |
20fa0902 MA |
2568 | pc -= load_immediate_bytes; |
2569 | return pc; | |
2570 | } | |
2571 | ||
2572 | /* Skip the PC past function prologue instructions (16-bit version). | |
2573 | This is a helper function for mips_skip_prologue. */ | |
2574 | ||
2575 | static CORE_ADDR | |
2576 | mips16_skip_prologue (pc, lenient) | |
2577 | CORE_ADDR pc; /* starting PC to search from */ | |
2578 | int lenient; | |
2579 | { | |
2580 | CORE_ADDR end_pc; | |
c81a76b3 MA |
2581 | int extend_bytes = 0; |
2582 | int prev_extend_bytes; | |
20fa0902 MA |
2583 | |
2584 | /* Table of instructions likely to be found in a function prologue. */ | |
2585 | static struct | |
2586 | { | |
2587 | unsigned short inst; | |
2588 | unsigned short mask; | |
2589 | } table[] = | |
2590 | { | |
2591 | { 0x6300, 0xff00 }, /* addiu $sp,offset */ | |
2592 | { 0xfb00, 0xff00 }, /* daddiu $sp,offset */ | |
2593 | { 0xd000, 0xf800 }, /* sw reg,n($sp) */ | |
2594 | { 0xf900, 0xff00 }, /* sd reg,n($sp) */ | |
2595 | { 0x6200, 0xff00 }, /* sw $ra,n($sp) */ | |
2596 | { 0xfa00, 0xff00 }, /* sd $ra,n($sp) */ | |
2597 | { 0x673d, 0xffff }, /* move $s1,sp */ | |
2598 | { 0xd980, 0xff80 }, /* sw $a0-$a3,n($s1) */ | |
2599 | { 0x6704, 0xff1c }, /* move reg,$a0-$a3 */ | |
2600 | { 0xe809, 0xf81f }, /* entry pseudo-op */ | |
32dab603 | 2601 | { 0x0100, 0xff00 }, /* addiu $s1,$sp,n */ |
20fa0902 MA |
2602 | { 0, 0 } /* end of table marker */ |
2603 | }; | |
2604 | ||
2605 | /* Skip the typical prologue instructions. These are the stack adjustment | |
2606 | instruction and the instructions that save registers on the stack | |
2607 | or in the gcc frame. */ | |
2608 | for (end_pc = pc + 100; pc < end_pc; pc += MIPS16_INSTLEN) | |
2609 | { | |
20fa0902 | 2610 | unsigned short inst; |
20fa0902 MA |
2611 | int i; |
2612 | ||
c81a76b3 | 2613 | inst = mips_fetch_instruction (pc); |
20fa0902 MA |
2614 | |
2615 | /* Normally we ignore an extend instruction. However, if it is | |
2616 | not followed by a valid prologue instruction, we must adjust | |
2617 | the pc back over the extend so that it won't be considered | |
2618 | part of the prologue. */ | |
2619 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
2620 | { | |
2621 | extend_bytes = MIPS16_INSTLEN; | |
2622 | continue; | |
2623 | } | |
2624 | prev_extend_bytes = extend_bytes; | |
2625 | extend_bytes = 0; | |
2626 | ||
2627 | /* Check for other valid prologue instructions besides extend. */ | |
2628 | for (i = 0; table[i].mask != 0; i++) | |
2629 | if ((inst & table[i].mask) == table[i].inst) /* found, get out */ | |
2630 | break; | |
2631 | if (table[i].mask != 0) /* it was in table? */ | |
32dab603 | 2632 | continue; /* ignore it */ |
20fa0902 MA |
2633 | else /* non-prologue */ |
2634 | { | |
2635 | /* Return the current pc, adjusted backwards by 2 if | |
2636 | the previous instruction was an extend. */ | |
2637 | return pc - prev_extend_bytes; | |
2638 | } | |
2639 | } | |
32dab603 | 2640 | return pc; |
20fa0902 MA |
2641 | } |
2642 | ||
2643 | /* To skip prologues, I use this predicate. Returns either PC itself | |
2644 | if the code at PC does not look like a function prologue; otherwise | |
2645 | returns an address that (if we're lucky) follows the prologue. If | |
2646 | LENIENT, then we must skip everything which is involved in setting | |
2647 | up the frame (it's OK to skip more, just so long as we don't skip | |
2648 | anything which might clobber the registers which are being saved. | |
2649 | We must skip more in the case where part of the prologue is in the | |
2650 | delay slot of a non-prologue instruction). */ | |
2651 | ||
2652 | CORE_ADDR | |
2653 | mips_skip_prologue (pc, lenient) | |
2654 | CORE_ADDR pc; | |
2655 | int lenient; | |
2656 | { | |
2657 | /* See if we can determine the end of the prologue via the symbol table. | |
2658 | If so, then return either PC, or the PC after the prologue, whichever | |
2659 | is greater. */ | |
2660 | ||
2661 | CORE_ADDR post_prologue_pc = after_prologue (pc, NULL); | |
2662 | ||
2663 | if (post_prologue_pc != 0) | |
2664 | return max (pc, post_prologue_pc); | |
2665 | ||
2666 | /* Can't determine prologue from the symbol table, need to examine | |
2667 | instructions. */ | |
2668 | ||
899c4021 | 2669 | if (pc_is_mips16 (pc)) |
20fa0902 MA |
2670 | return mips16_skip_prologue (pc, lenient); |
2671 | else | |
2672 | return mips32_skip_prologue (pc, lenient); | |
bd5635a1 | 2673 | } |
c2a0f1cb | 2674 | |
002a422b | 2675 | #if 0 |
20fa0902 | 2676 | /* The lenient prologue stuff should be superseded by the code in |
002a422b JK |
2677 | init_extra_frame_info which looks to see whether the stores mentioned |
2678 | in the proc_desc have actually taken place. */ | |
2679 | ||
ee5fb959 JK |
2680 | /* Is address PC in the prologue (loosely defined) for function at |
2681 | STARTADDR? */ | |
2682 | ||
2683 | static int | |
2684 | mips_in_lenient_prologue (startaddr, pc) | |
2685 | CORE_ADDR startaddr; | |
2686 | CORE_ADDR pc; | |
2687 | { | |
2688 | CORE_ADDR end_prologue = mips_skip_prologue (startaddr, 1); | |
2689 | return pc >= startaddr && pc < end_prologue; | |
2690 | } | |
002a422b | 2691 | #endif |
ee5fb959 | 2692 | |
ac8cf67d PS |
2693 | /* Given a return value in `regbuf' with a type `valtype', |
2694 | extract and copy its value into `valbuf'. */ | |
2695 | void | |
2696 | mips_extract_return_value (valtype, regbuf, valbuf) | |
2697 | struct type *valtype; | |
2698 | char regbuf[REGISTER_BYTES]; | |
2699 | char *valbuf; | |
2700 | { | |
2701 | int regnum; | |
92a6d600 | 2702 | int offset = 0; |
c81a76b3 | 2703 | int len = TYPE_LENGTH (valtype); |
ac8cf67d | 2704 | |
e4dbd248 PS |
2705 | regnum = 2; |
2706 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT | |
1fe2e66a AC |
2707 | && (MIPS_FPU_TYPE == MIPS_FPU_DOUBLE |
2708 | || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE | |
2709 | && len <= MIPS_FPU_SINGLE_REGSIZE))) | |
f781fe93 | 2710 | regnum = FP0_REGNUM; |
ac8cf67d | 2711 | |
0af60e03 MS |
2712 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
2713 | { /* "un-left-justify" the value from the register */ | |
87910097 | 2714 | if (len < REGISTER_RAW_SIZE (regnum)) |
0af60e03 MS |
2715 | offset = REGISTER_RAW_SIZE (regnum) - len; |
2716 | if (len > REGISTER_RAW_SIZE (regnum) && /* odd-size structs */ | |
2717 | len < REGISTER_RAW_SIZE (regnum) * 2 && | |
2718 | (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || | |
2719 | TYPE_CODE (valtype) == TYPE_CODE_UNION)) | |
2720 | offset = 2 * REGISTER_RAW_SIZE (regnum) - len; | |
2721 | } | |
c81a76b3 | 2722 | memcpy (valbuf, regbuf + REGISTER_BYTE (regnum) + offset, len); |
f781fe93 | 2723 | REGISTER_CONVERT_TO_TYPE (regnum, valtype, valbuf); |
ac8cf67d PS |
2724 | } |
2725 | ||
2726 | /* Given a return value in `regbuf' with a type `valtype', | |
2727 | write it's value into the appropriate register. */ | |
2728 | void | |
2729 | mips_store_return_value (valtype, valbuf) | |
2730 | struct type *valtype; | |
2731 | char *valbuf; | |
2732 | { | |
2733 | int regnum; | |
0af60e03 MS |
2734 | int offset = 0; |
2735 | int len = TYPE_LENGTH (valtype); | |
ac8cf67d PS |
2736 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; |
2737 | ||
e4dbd248 PS |
2738 | regnum = 2; |
2739 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT | |
1fe2e66a AC |
2740 | && (MIPS_FPU_TYPE == MIPS_FPU_DOUBLE |
2741 | || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE | |
2742 | && len <= MIPS_REGSIZE))) | |
e4dbd248 PS |
2743 | regnum = FP0_REGNUM; |
2744 | ||
0af60e03 MS |
2745 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
2746 | { /* "left-justify" the value in the register */ | |
2747 | if (len < REGISTER_RAW_SIZE (regnum)) | |
2748 | offset = REGISTER_RAW_SIZE (regnum) - len; | |
2749 | if (len > REGISTER_RAW_SIZE (regnum) && /* odd-size structs */ | |
2750 | len < REGISTER_RAW_SIZE (regnum) * 2 && | |
2751 | (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || | |
2752 | TYPE_CODE (valtype) == TYPE_CODE_UNION)) | |
2753 | offset = 2 * REGISTER_RAW_SIZE (regnum) - len; | |
2754 | } | |
2755 | memcpy(raw_buffer + offset, valbuf, len); | |
ac8cf67d | 2756 | REGISTER_CONVERT_FROM_TYPE(regnum, valtype, raw_buffer); |
0af60e03 MS |
2757 | write_register_bytes(REGISTER_BYTE (regnum), raw_buffer, |
2758 | len > REGISTER_RAW_SIZE (regnum) ? | |
2759 | len : REGISTER_RAW_SIZE (regnum)); | |
ac8cf67d PS |
2760 | } |
2761 | ||
e03c0cc6 ILT |
2762 | /* Exported procedure: Is PC in the signal trampoline code */ |
2763 | ||
2764 | int | |
2765 | in_sigtramp (pc, ignore) | |
2766 | CORE_ADDR pc; | |
2767 | char *ignore; /* function name */ | |
2768 | { | |
2769 | if (sigtramp_address == 0) | |
2770 | fixup_sigtramp (); | |
2771 | return (pc >= sigtramp_address && pc < sigtramp_end); | |
2772 | } | |
2773 | ||
1fe2e66a | 2774 | /* Commands to show/set the MIPS FPU type. */ |
e4dbd248 | 2775 | |
1fe2e66a | 2776 | static void show_mipsfpu_command PARAMS ((char *, int)); |
e4dbd248 | 2777 | static void |
1fe2e66a | 2778 | show_mipsfpu_command (args, from_tty) |
e4dbd248 PS |
2779 | char *args; |
2780 | int from_tty; | |
e4dbd248 | 2781 | { |
1fe2e66a AC |
2782 | char *msg; |
2783 | char *fpu; | |
2784 | switch (MIPS_FPU_TYPE) | |
e4dbd248 | 2785 | { |
e4dbd248 | 2786 | case MIPS_FPU_SINGLE: |
1fe2e66a AC |
2787 | fpu = "single-precision"; |
2788 | break; | |
2789 | case MIPS_FPU_DOUBLE: | |
2790 | fpu = "double-precision"; | |
e4dbd248 PS |
2791 | break; |
2792 | case MIPS_FPU_NONE: | |
1fe2e66a | 2793 | fpu = "absent (none)"; |
e4dbd248 PS |
2794 | break; |
2795 | } | |
1fe2e66a AC |
2796 | if (mips_fpu_type_auto) |
2797 | printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
2798 | fpu); | |
2799 | else | |
2800 | printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n", | |
2801 | fpu); | |
2802 | } | |
e4dbd248 | 2803 | |
1fe2e66a AC |
2804 | |
2805 | static void set_mipsfpu_command PARAMS ((char *, int)); | |
2806 | static void | |
2807 | set_mipsfpu_command (args, from_tty) | |
2808 | char *args; | |
2809 | int from_tty; | |
2810 | { | |
2811 | printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
2812 | show_mipsfpu_command (args, from_tty); | |
2813 | } | |
2814 | ||
2815 | static void set_mipsfpu_single_command PARAMS ((char *, int)); | |
2816 | static void | |
2817 | set_mipsfpu_single_command (args, from_tty) | |
2818 | char *args; | |
2819 | int from_tty; | |
2820 | { | |
2821 | mips_fpu_type = MIPS_FPU_SINGLE; | |
2822 | mips_fpu_type_auto = 0; | |
2823 | /* start-sanitize-carp start-sanitize-vr4xxx */ | |
2824 | if (GDB_MULTI_ARCH) | |
e4dbd248 | 2825 | { |
1fe2e66a | 2826 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_SINGLE; |
e4dbd248 | 2827 | } |
1fe2e66a | 2828 | /* end-sanitize-carp end-sanitize-vr4xxx */ |
e4dbd248 PS |
2829 | } |
2830 | ||
1fe2e66a | 2831 | static void set_mipsfpu_double_command PARAMS ((char *, int)); |
e4dbd248 | 2832 | static void |
1fe2e66a AC |
2833 | set_mipsfpu_double_command (args, from_tty) |
2834 | char *args; | |
2835 | int from_tty; | |
2836 | { | |
2837 | mips_fpu_type = MIPS_FPU_DOUBLE; | |
2838 | mips_fpu_type_auto = 0; | |
2839 | /* start-sanitize-carp start-sanitize-vr4xxx */ | |
2840 | if (GDB_MULTI_ARCH) | |
2841 | { | |
2842 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_DOUBLE; | |
2843 | } | |
2844 | /* end-sanitize-carp end-sanitize-vr4xxx */ | |
2845 | } | |
2846 | ||
2847 | static void set_mipsfpu_none_command PARAMS ((char *, int)); | |
2848 | static void | |
2849 | set_mipsfpu_none_command (args, from_tty) | |
2850 | char *args; | |
2851 | int from_tty; | |
2852 | { | |
2853 | mips_fpu_type = MIPS_FPU_NONE; | |
2854 | mips_fpu_type_auto = 0; | |
2855 | /* start-sanitize-carp start-sanitize-vr4xxx */ | |
2856 | if (GDB_MULTI_ARCH) | |
2857 | { | |
2858 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_NONE; | |
2859 | } | |
2860 | /* end-sanitize-carp end-sanitize-vr4xxx */ | |
2861 | } | |
2862 | ||
2863 | static void set_mipsfpu_auto_command PARAMS ((char *, int)); | |
2864 | static void | |
2865 | set_mipsfpu_auto_command (args, from_tty) | |
e4dbd248 PS |
2866 | char *args; |
2867 | int from_tty; | |
e4dbd248 | 2868 | { |
1fe2e66a | 2869 | mips_fpu_type_auto = 1; |
e4dbd248 PS |
2870 | } |
2871 | ||
9f9f94aa SS |
2872 | /* Command to set the processor type. */ |
2873 | ||
2874 | void | |
2875 | mips_set_processor_type_command (args, from_tty) | |
2876 | char *args; | |
2877 | int from_tty; | |
2878 | { | |
2879 | int i; | |
2880 | ||
2881 | if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0') | |
2882 | { | |
2883 | printf_unfiltered ("The known MIPS processor types are as follows:\n\n"); | |
2884 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
2885 | printf_unfiltered ("%s\n", mips_processor_type_table[i].name); | |
2886 | ||
2887 | /* Restore the value. */ | |
2888 | tmp_mips_processor_type = strsave (mips_processor_type); | |
2889 | ||
2890 | return; | |
2891 | } | |
2892 | ||
2893 | if (!mips_set_processor_type (tmp_mips_processor_type)) | |
2894 | { | |
2895 | error ("Unknown processor type `%s'.", tmp_mips_processor_type); | |
2896 | /* Restore its value. */ | |
2897 | tmp_mips_processor_type = strsave (mips_processor_type); | |
2898 | } | |
2899 | } | |
2900 | ||
2901 | static void | |
2902 | mips_show_processor_type_command (args, from_tty) | |
2903 | char *args; | |
2904 | int from_tty; | |
2905 | { | |
2906 | } | |
2907 | ||
2908 | /* Modify the actual processor type. */ | |
2909 | ||
2910 | int | |
2911 | mips_set_processor_type (str) | |
2912 | char *str; | |
2913 | { | |
2914 | int i, j; | |
2915 | ||
2916 | if (str == NULL) | |
1d9489c1 | 2917 | return 0; |
9f9f94aa SS |
2918 | |
2919 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
2920 | { | |
2921 | if (strcasecmp (str, mips_processor_type_table[i].name) == 0) | |
2922 | { | |
2923 | mips_processor_type = str; | |
2924 | ||
2925 | for (j = 0; j < NUM_REGS; ++j) | |
9ddf9aa9 AC |
2926 | /* FIXME - MIPS should be defining REGISTER_NAME() instead */ |
2927 | gdb_register_names[j] = mips_processor_type_table[i].regnames[j]; | |
9f9f94aa SS |
2928 | |
2929 | return 1; | |
2930 | ||
2931 | /* FIXME tweak fpu flag too */ | |
2932 | } | |
2933 | } | |
2934 | ||
2935 | return 0; | |
2936 | } | |
2937 | ||
2938 | /* Attempt to identify the particular processor model by reading the | |
2939 | processor id. */ | |
2940 | ||
2941 | char * | |
2942 | mips_read_processor_type () | |
2943 | { | |
28444bf3 | 2944 | CORE_ADDR prid; |
9f9f94aa SS |
2945 | |
2946 | prid = read_register (PRID_REGNUM); | |
2947 | ||
80e0e92a | 2948 | if ((prid & ~0xf) == 0x700) |
9f9f94aa SS |
2949 | return savestring ("r3041", strlen("r3041")); |
2950 | ||
2951 | return NULL; | |
2952 | } | |
427fec5d JK |
2953 | |
2954 | /* Just like reinit_frame_cache, but with the right arguments to be | |
2955 | callable as an sfunc. */ | |
9f9f94aa | 2956 | |
427fec5d JK |
2957 | static void |
2958 | reinit_frame_cache_sfunc (args, from_tty, c) | |
2959 | char *args; | |
2960 | int from_tty; | |
2961 | struct cmd_list_element *c; | |
2962 | { | |
2963 | reinit_frame_cache (); | |
2964 | } | |
c2a0f1cb | 2965 | |
912e805f | 2966 | int |
18b46e7c SS |
2967 | gdb_print_insn_mips (memaddr, info) |
2968 | bfd_vma memaddr; | |
2969 | disassemble_info *info; | |
2970 | { | |
f9f8c14b MA |
2971 | mips_extra_func_info_t proc_desc; |
2972 | ||
2973 | /* Search for the function containing this address. Set the low bit | |
2974 | of the address when searching, in case we were given an even address | |
2975 | that is the start of a 16-bit function. If we didn't do this, | |
2976 | the search would fail because the symbol table says the function | |
2977 | starts at an odd address, i.e. 1 byte past the given address. */ | |
c1fc0935 MA |
2978 | memaddr = ADDR_BITS_REMOVE (memaddr); |
2979 | proc_desc = non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr), NULL); | |
f9f8c14b MA |
2980 | |
2981 | /* Make an attempt to determine if this is a 16-bit function. If | |
2982 | the procedure descriptor exists and the address therein is odd, | |
2983 | it's definitely a 16-bit function. Otherwise, we have to just | |
2984 | guess that if the address passed in is odd, it's 16-bits. */ | |
2985 | if (proc_desc) | |
88ff9e06 | 2986 | info->mach = pc_is_mips16 (PROC_LOW_ADDR (proc_desc)) ? 16 : TM_PRINT_INSN_MACH; |
f9f8c14b | 2987 | else |
88ff9e06 | 2988 | info->mach = pc_is_mips16 (memaddr) ? 16 : TM_PRINT_INSN_MACH; |
f9f8c14b | 2989 | |
c1fc0935 | 2990 | /* Round down the instruction address to the appropriate boundary. */ |
f9f8c14b MA |
2991 | memaddr &= (info->mach == 16 ? ~1 : ~3); |
2992 | ||
2993 | /* Call the appropriate disassembler based on the target endian-ness. */ | |
18b46e7c SS |
2994 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
2995 | return print_insn_big_mips (memaddr, info); | |
2996 | else | |
2997 | return print_insn_little_mips (memaddr, info); | |
2998 | } | |
2999 | ||
9ddf9aa9 AC |
3000 | /* Old-style breakpoint macros. |
3001 | The IDT board uses an unusual breakpoint value, and sometimes gets | |
3002 | confused when it sees the usual MIPS breakpoint instruction. */ | |
3003 | ||
3004 | #define BIG_BREAKPOINT {0, 0x5, 0, 0xd} | |
3005 | #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0} | |
3006 | #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd} | |
3007 | #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0} | |
3008 | #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd} | |
3009 | #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0} | |
3010 | #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5} | |
3011 | #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8} | |
3012 | ||
f9f8c14b MA |
3013 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program |
3014 | counter value to determine whether a 16- or 32-bit breakpoint should be | |
3015 | used. It returns a pointer to a string of bytes that encode a breakpoint | |
3016 | instruction, stores the length of the string to *lenptr, and adjusts pc | |
3017 | (if necessary) to point to the actual memory location where the | |
3018 | breakpoint should be inserted. */ | |
3019 | ||
3020 | unsigned char *mips_breakpoint_from_pc (pcptr, lenptr) | |
3021 | CORE_ADDR *pcptr; | |
3022 | int *lenptr; | |
3023 | { | |
3024 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
3025 | { | |
899c4021 | 3026 | if (pc_is_mips16 (*pcptr)) |
f9f8c14b MA |
3027 | { |
3028 | static char mips16_big_breakpoint[] = MIPS16_BIG_BREAKPOINT; | |
c1fc0935 | 3029 | *pcptr = UNMAKE_MIPS16_ADDR (*pcptr); |
f9f8c14b MA |
3030 | *lenptr = sizeof(mips16_big_breakpoint); |
3031 | return mips16_big_breakpoint; | |
3032 | } | |
3033 | else | |
3034 | { | |
3035 | static char big_breakpoint[] = BIG_BREAKPOINT; | |
f781fe93 MA |
3036 | static char pmon_big_breakpoint[] = PMON_BIG_BREAKPOINT; |
3037 | static char idt_big_breakpoint[] = IDT_BIG_BREAKPOINT; | |
3038 | ||
f9f8c14b | 3039 | *lenptr = sizeof(big_breakpoint); |
f781fe93 MA |
3040 | |
3041 | if (strcmp (target_shortname, "mips") == 0) | |
3042 | return idt_big_breakpoint; | |
3043 | else if (strcmp (target_shortname, "ddb") == 0 | |
3044 | || strcmp (target_shortname, "pmon") == 0 | |
3045 | || strcmp (target_shortname, "lsi") == 0) | |
3046 | return pmon_big_breakpoint; | |
3047 | else | |
3048 | return big_breakpoint; | |
f9f8c14b MA |
3049 | } |
3050 | } | |
3051 | else | |
3052 | { | |
899c4021 | 3053 | if (pc_is_mips16 (*pcptr)) |
f9f8c14b MA |
3054 | { |
3055 | static char mips16_little_breakpoint[] = MIPS16_LITTLE_BREAKPOINT; | |
c1fc0935 | 3056 | *pcptr = UNMAKE_MIPS16_ADDR (*pcptr); |
f9f8c14b MA |
3057 | *lenptr = sizeof(mips16_little_breakpoint); |
3058 | return mips16_little_breakpoint; | |
3059 | } | |
3060 | else | |
3061 | { | |
3062 | static char little_breakpoint[] = LITTLE_BREAKPOINT; | |
f781fe93 MA |
3063 | static char pmon_little_breakpoint[] = PMON_LITTLE_BREAKPOINT; |
3064 | static char idt_little_breakpoint[] = IDT_LITTLE_BREAKPOINT; | |
3065 | ||
f9f8c14b | 3066 | *lenptr = sizeof(little_breakpoint); |
f781fe93 MA |
3067 | |
3068 | if (strcmp (target_shortname, "mips") == 0) | |
3069 | return idt_little_breakpoint; | |
3070 | else if (strcmp (target_shortname, "ddb") == 0 | |
3071 | || strcmp (target_shortname, "pmon") == 0 | |
3072 | || strcmp (target_shortname, "lsi") == 0) | |
3073 | return pmon_little_breakpoint; | |
3074 | else | |
3075 | return little_breakpoint; | |
f9f8c14b MA |
3076 | } |
3077 | } | |
3078 | } | |
3079 | ||
f781fe93 MA |
3080 | /* If PC is in a mips16 call or return stub, return the address of the target |
3081 | PC, which is either the callee or the caller. There are several | |
3082 | cases which must be handled: | |
3083 | ||
3084 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
3085 | target PC is in $31 ($ra). | |
3086 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
3087 | and the target PC is in $2. | |
3088 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
3089 | before the jal instruction, this is effectively a call stub | |
3090 | and the the target PC is in $2. Otherwise this is effectively | |
3091 | a return stub and the target PC is in $18. | |
3092 | ||
3093 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
3094 | gory details. | |
3095 | ||
3096 | This function implements the SKIP_TRAMPOLINE_CODE macro. | |
3097 | */ | |
3098 | ||
3099 | CORE_ADDR | |
3100 | mips_skip_stub (pc) | |
3101 | CORE_ADDR pc; | |
3102 | { | |
3103 | char *name; | |
3104 | CORE_ADDR start_addr; | |
3105 | ||
3106 | /* Find the starting address and name of the function containing the PC. */ | |
3107 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
3108 | return 0; | |
3109 | ||
3110 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
3111 | target PC is in $31 ($ra). */ | |
3112 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
3113 | || strcmp (name, "__mips16_ret_df") == 0) | |
3114 | return read_register (RA_REGNUM); | |
3115 | ||
3116 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
3117 | { | |
3118 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
3119 | and the target PC is in $2. */ | |
3120 | if (name[19] >= '0' && name[19] <= '9') | |
3121 | return read_register (2); | |
3122 | ||
3123 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
3124 | before the jal instruction, this is effectively a call stub | |
3125 | and the the target PC is in $2. Otherwise this is effectively | |
3126 | a return stub and the target PC is in $18. */ | |
3127 | else if (name[19] == 's' || name[19] == 'd') | |
3128 | { | |
3129 | if (pc == start_addr) | |
3130 | { | |
3131 | /* Check if the target of the stub is a compiler-generated | |
3132 | stub. Such a stub for a function bar might have a name | |
3133 | like __fn_stub_bar, and might look like this: | |
3134 | mfc1 $4,$f13 | |
3135 | mfc1 $5,$f12 | |
3136 | mfc1 $6,$f15 | |
3137 | mfc1 $7,$f14 | |
3138 | la $1,bar (becomes a lui/addiu pair) | |
3139 | jr $1 | |
3140 | So scan down to the lui/addi and extract the target | |
3141 | address from those two instructions. */ | |
3142 | ||
3143 | CORE_ADDR target_pc = read_register (2); | |
3144 | t_inst inst; | |
3145 | int i; | |
3146 | ||
3147 | /* See if the name of the target function is __fn_stub_*. */ | |
3148 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == 0) | |
3149 | return target_pc; | |
3150 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
3151 | && strcmp (name, "etext") != 0 | |
3152 | && strcmp (name, "_etext") != 0) | |
3153 | return target_pc; | |
3154 | ||
3155 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
3156 | The limit on the search is arbitrarily set to 20 | |
3157 | instructions. FIXME. */ | |
3158 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN) | |
3159 | { | |
3160 | inst = mips_fetch_instruction (target_pc); | |
3161 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
3162 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
3163 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
3164 | return pc | (inst & 0xffff); /* low word */ | |
3165 | } | |
3166 | ||
3167 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
3168 | return target_pc; | |
3169 | } | |
3170 | else | |
3171 | /* This is the 'return' part of a call stub. The return | |
3172 | address is in $r18. */ | |
3173 | return read_register (18); | |
3174 | } | |
3175 | } | |
3176 | return 0; /* not a stub */ | |
3177 | } | |
3178 | ||
3179 | ||
3180 | /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline). | |
3181 | This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */ | |
3182 | ||
3183 | int | |
3184 | mips_in_call_stub (pc, name) | |
3185 | CORE_ADDR pc; | |
3186 | char *name; | |
3187 | { | |
3188 | CORE_ADDR start_addr; | |
3189 | ||
3190 | /* Find the starting address of the function containing the PC. If the | |
3191 | caller didn't give us a name, look it up at the same time. */ | |
3192 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0) | |
3193 | return 0; | |
3194 | ||
3195 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
3196 | { | |
3197 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */ | |
3198 | if (name[19] >= '0' && name[19] <= '9') | |
3199 | return 1; | |
3200 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
3201 | before the jal instruction, this is effectively a call stub. */ | |
3202 | else if (name[19] == 's' || name[19] == 'd') | |
3203 | return pc == start_addr; | |
3204 | } | |
3205 | ||
3206 | return 0; /* not a stub */ | |
3207 | } | |
3208 | ||
3209 | ||
3210 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
3211 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
3212 | ||
3213 | int | |
3214 | mips_in_return_stub (pc, name) | |
3215 | CORE_ADDR pc; | |
3216 | char *name; | |
3217 | { | |
3218 | CORE_ADDR start_addr; | |
3219 | ||
3220 | /* Find the starting address of the function containing the PC. */ | |
3221 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
3222 | return 0; | |
3223 | ||
3224 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */ | |
3225 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
3226 | || strcmp (name, "__mips16_ret_df") == 0) | |
3227 | return 1; | |
3228 | ||
3229 | /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start, | |
3230 | i.e. after the jal instruction, this is effectively a return stub. */ | |
3231 | if (strncmp (name, "__mips16_call_stub_", 19) == 0 | |
3232 | && (name[19] == 's' || name[19] == 'd') | |
3233 | && pc != start_addr) | |
3234 | return 1; | |
3235 | ||
3236 | return 0; /* not a stub */ | |
3237 | } | |
3238 | ||
3239 | ||
3240 | /* Return non-zero if the PC is in a library helper function that should | |
3241 | be ignored. This implements the IGNORE_HELPER_CALL macro. */ | |
3242 | ||
3243 | int | |
3244 | mips_ignore_helper (pc) | |
3245 | CORE_ADDR pc; | |
3246 | { | |
3247 | char *name; | |
3248 | ||
3249 | /* Find the starting address and name of the function containing the PC. */ | |
3250 | if (find_pc_partial_function (pc, &name, NULL, NULL) == 0) | |
3251 | return 0; | |
3252 | ||
3253 | /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function | |
3254 | that we want to ignore. */ | |
3255 | return (strcmp (name, "__mips16_ret_sf") == 0 | |
3256 | || strcmp (name, "__mips16_ret_df") == 0); | |
3257 | } | |
3258 | ||
3259 | ||
98760eab AC |
3260 | /* Return a location where we can set a breakpoint that will be hit |
3261 | when an inferior function call returns. This is normally the | |
3262 | program's entry point. Executables that don't have an entry | |
3263 | point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS | |
3264 | whose address is the location where the breakpoint should be placed. */ | |
3265 | ||
3266 | CORE_ADDR | |
3267 | mips_call_dummy_address () | |
3268 | { | |
3269 | struct minimal_symbol *sym; | |
3270 | ||
3271 | sym = lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL, NULL); | |
3272 | if (sym) | |
3273 | return SYMBOL_VALUE_ADDRESS (sym); | |
3274 | else | |
3275 | return entry_point_address (); | |
3276 | } | |
3277 | ||
ff6f2f57 AC |
3278 | /* start-sanitize-carp start-sanitize-vr4xxx */ |
3279 | ||
3280 | static gdbarch_init_ftype mips_gdbarch_init; | |
3281 | static struct gdbarch * | |
3282 | mips_gdbarch_init (info, arches) | |
2e64ee9a | 3283 | struct gdbarch_info info; |
ff6f2f57 AC |
3284 | struct gdbarch_list *arches; |
3285 | { | |
3286 | struct gdbarch *gdbarch; | |
3287 | struct gdbarch_tdep *tdep; | |
3288 | int elf_abi; | |
2e64ee9a AC |
3289 | char *abi_name; |
3290 | ||
3291 | /* find a default for ELF_ABI */ | |
3292 | if (info.abfd != NULL) | |
3293 | elf_abi = elf_elfheader (info.abfd)->e_flags & EF_MIPS_ABI; | |
ff6f2f57 AC |
3294 | else if (gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_mips) |
3295 | elf_abi = gdbarch_tdep (current_gdbarch)->elf_abi; | |
3296 | else | |
3297 | elf_abi = 0; | |
3298 | ||
3299 | /* try to find a pre-existing architecture */ | |
2e64ee9a | 3300 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
ff6f2f57 | 3301 | arches != NULL; |
2e64ee9a | 3302 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) |
ff6f2f57 AC |
3303 | { |
3304 | /* MIPS needs to be pedantic about which ABI the object is | |
3305 | using. */ | |
3306 | if (gdbarch_tdep (current_gdbarch)->elf_abi != elf_abi) | |
3307 | continue; | |
3308 | return arches->gdbarch; | |
3309 | } | |
3310 | ||
3311 | /* Need a new architecture. Fill in a target specific vector. */ | |
3312 | tdep = (struct gdbarch_tdep*) xmalloc (sizeof (struct gdbarch_tdep)); | |
2e64ee9a | 3313 | gdbarch = gdbarch_alloc (&info, tdep); |
ff6f2f57 AC |
3314 | tdep->elf_abi = elf_abi; |
3315 | switch (elf_abi) | |
3316 | { | |
3317 | case E_MIPS_ABI_O32: | |
2e64ee9a | 3318 | abi_name = "o32"; |
ff6f2f57 AC |
3319 | tdep->mips_eabi = 0; |
3320 | set_gdbarch_long_bit (gdbarch, 32); | |
3321 | set_gdbarch_ptr_bit (gdbarch, 32); | |
3322 | break; | |
3323 | case E_MIPS_ABI_O64: | |
2e64ee9a | 3324 | abi_name = "o64"; |
ff6f2f57 AC |
3325 | tdep->mips_eabi = 0; |
3326 | set_gdbarch_long_bit (gdbarch, 32); | |
3327 | set_gdbarch_ptr_bit (gdbarch, 32); | |
3328 | break; | |
3329 | case E_MIPS_ABI_EABI32: | |
2e64ee9a | 3330 | abi_name = "eabi32"; |
ff6f2f57 AC |
3331 | tdep->mips_eabi = 1; |
3332 | set_gdbarch_long_bit (gdbarch, 32); | |
3333 | set_gdbarch_ptr_bit (gdbarch, 32); | |
3334 | break; | |
3335 | case E_MIPS_ABI_EABI64: | |
2e64ee9a | 3336 | abi_name = "eabi64"; |
ff6f2f57 AC |
3337 | tdep->mips_eabi = 1; |
3338 | set_gdbarch_long_bit (gdbarch, 64); | |
3339 | set_gdbarch_ptr_bit (gdbarch, 64); | |
3340 | break; | |
3341 | default: | |
2e64ee9a | 3342 | abi_name = "default"; |
ff6f2f57 AC |
3343 | tdep->mips_eabi = 0; |
3344 | set_gdbarch_long_bit (gdbarch, 32); | |
3345 | set_gdbarch_ptr_bit (gdbarch, 32); | |
3346 | break; | |
3347 | } | |
3348 | if (tdep->mips_eabi) | |
3349 | { | |
3350 | /* EABI uses R4 through R11 for args */ | |
3351 | tdep->mips_last_arg_regnum = 11; | |
3352 | /* EABI uses F12 through F19 for args */ | |
3353 | tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 19; | |
3354 | } | |
3355 | else | |
3356 | { | |
3357 | /* old ABI uses R4 through R7 for args */ | |
3358 | tdep->mips_last_arg_regnum = 7; | |
3359 | /* old ABI uses F12 through F15 for args */ | |
3360 | tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 15; | |
3361 | } | |
3362 | set_gdbarch_long_long_bit (gdbarch, 64); | |
3363 | ||
1fe2e66a AC |
3364 | /* enable/disable the MIPS FPU */ |
3365 | if (!mips_fpu_type_auto) | |
3366 | tdep->mips_fpu_type = mips_fpu_type; | |
3367 | else if (info.bfd_arch_info != NULL | |
3368 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
3369 | switch (info.bfd_arch_info->mach) | |
3370 | { | |
cb2f9c9c | 3371 | case bfd_mach_mips4100: |
1fe2e66a AC |
3372 | case bfd_mach_mips4111: |
3373 | case bfd_mach_mips4121: | |
3374 | tdep->mips_fpu_type = MIPS_FPU_NONE; | |
3375 | break; | |
3376 | default: | |
3377 | tdep->mips_fpu_type = MIPS_FPU_DOUBLE; | |
3378 | break; | |
3379 | } | |
3380 | else | |
3381 | tdep->mips_fpu_type = MIPS_FPU_DOUBLE; | |
3382 | ||
ff6f2f57 AC |
3383 | if (gdbarch_debug) |
3384 | { | |
2e64ee9a AC |
3385 | fprintf_unfiltered (stderr, |
3386 | "mips_gdbarch_init: (info)elf_abi 0x%x (%s)\n", | |
3387 | elf_abi, abi_name); | |
3388 | fprintf_unfiltered (stderr, | |
3389 | "mips_gdbarch_init: MIPS_EABI = %d\n", | |
3390 | tdep->mips_eabi); | |
3391 | fprintf_unfiltered (stderr, | |
3392 | "mips_gdbarch_init: MIPS_LAST_ARG_REGNUM = %d\n", | |
3393 | tdep->mips_last_arg_regnum); | |
3394 | fprintf_unfiltered (stderr, | |
3395 | "mips_gdbarch_init: MIPS_LAST_FP_ARG_REGNUM = %d (%d)\n", | |
3396 | tdep->mips_last_fp_arg_regnum, | |
3397 | tdep->mips_last_fp_arg_regnum - FP0_REGNUM); | |
1fe2e66a AC |
3398 | fprintf_unfiltered (stderr, |
3399 | "mips_gdbarch_init: tdep->mips_fpu_type = %d (%s)\n", | |
3400 | tdep->mips_fpu_type, | |
3401 | (tdep->mips_fpu_type == MIPS_FPU_NONE ? "none" | |
3402 | : tdep->mips_fpu_type == MIPS_FPU_SINGLE ? "single" | |
3403 | : tdep->mips_fpu_type == MIPS_FPU_DOUBLE ? "double" | |
3404 | : "???")); | |
ff6f2f57 AC |
3405 | } |
3406 | ||
3407 | return gdbarch; | |
3408 | } | |
3409 | ||
2e64ee9a | 3410 | /* end-sanitize-carp end-sanitize-vr4xxx */ |
ff6f2f57 | 3411 | |
c2a0f1cb ILT |
3412 | void |
3413 | _initialize_mips_tdep () | |
3414 | { | |
1fe2e66a | 3415 | static struct cmd_list_element *mipsfpulist = NULL; |
427fec5d JK |
3416 | struct cmd_list_element *c; |
3417 | ||
ff6f2f57 AC |
3418 | /* start-sanitize-carp start-sanitize-vr4xxx */ |
3419 | if (GDB_MULTI_ARCH) | |
3420 | register_gdbarch_init (bfd_arch_mips, mips_gdbarch_init); | |
2e64ee9a | 3421 | /* end-sanitize-carp end-sanitize-vr4xxx */ |
912e805f AC |
3422 | if (!tm_print_insn) /* Someone may have already set it */ |
3423 | tm_print_insn = gdb_print_insn_mips; | |
18b46e7c | 3424 | |
427fec5d JK |
3425 | /* Let the user turn off floating point and set the fence post for |
3426 | heuristic_proc_start. */ | |
3427 | ||
1fe2e66a AC |
3428 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, |
3429 | "Set use of MIPS floating-point coprocessor.", | |
3430 | &mipsfpulist, "set mipsfpu ", 0, &setlist); | |
3431 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
3432 | "Select single-precision MIPS floating-point coprocessor.", | |
3433 | &mipsfpulist); | |
3434 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
3435 | "Select double-precision MIPS floating-point coprocessor .", | |
3436 | &mipsfpulist); | |
3437 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
3438 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
3439 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
3440 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
3441 | "Select no MIPS floating-point coprocessor.", | |
3442 | &mipsfpulist); | |
3443 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); | |
3444 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
3445 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
3446 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
3447 | "Select MIPS floating-point coprocessor automatically.", | |
3448 | &mipsfpulist); | |
3449 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
3450 | "Show current use of MIPS floating-point coprocessor target.", | |
3451 | &showlist); | |
3127785a | 3452 | |
1fe2e66a AC |
3453 | /* start-sanitize-carp start-sanitize-vr4xxx */ |
3454 | #if !GDB_MULTI_ARCH | |
3455 | /* end-sanitize-carp end-sanitize-vr4xxx */ | |
9f9f94aa SS |
3456 | c = add_set_cmd ("processor", class_support, var_string_noescape, |
3457 | (char *) &tmp_mips_processor_type, | |
3458 | "Set the type of MIPS processor in use.\n\ | |
3459 | Set this to be able to access processor-type-specific registers.\n\ | |
3460 | ", | |
3461 | &setlist); | |
3462 | c->function.cfunc = mips_set_processor_type_command; | |
3463 | c = add_show_from_set (c, &showlist); | |
3464 | c->function.cfunc = mips_show_processor_type_command; | |
3465 | ||
3466 | tmp_mips_processor_type = strsave (DEFAULT_MIPS_TYPE); | |
3467 | mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE), 0); | |
1fe2e66a AC |
3468 | /* start-sanitize-carp start-sanitize-vr4xxx */ |
3469 | #endif | |
3470 | /* end-sanitize-carp end-sanitize-vr4xxx */ | |
9f9f94aa | 3471 | |
bdef72d2 JK |
3472 | /* We really would like to have both "0" and "unlimited" work, but |
3473 | command.c doesn't deal with that. So make it a var_zinteger | |
3474 | because the user can always use "999999" or some such for unlimited. */ | |
3475 | c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger, | |
427fec5d JK |
3476 | (char *) &heuristic_fence_post, |
3477 | "\ | |
23d35572 JK |
3478 | Set the distance searched for the start of a function.\n\ |
3479 | If you are debugging a stripped executable, GDB needs to search through the\n\ | |
3480 | program for the start of a function. This command sets the distance of the\n\ | |
3481 | search. The only need to set it is when debugging a stripped executable.", | |
427fec5d JK |
3482 | &setlist); |
3483 | /* We need to throw away the frame cache when we set this, since it | |
3484 | might change our ability to get backtraces. */ | |
3485 | c->function.sfunc = reinit_frame_cache_sfunc; | |
3486 | add_show_from_set (c, &showlist); | |
98760eab AC |
3487 | |
3488 | /* Allow the user to control whether the upper bits of 64-bit | |
3489 | addresses should be zeroed. */ | |
3490 | add_show_from_set | |
3491 | (add_set_cmd ("mask-address", no_class, var_boolean, (char *)&mask_address_p, | |
3492 | "Set zeroing of upper 32 bits of 64-bit addresses.\n\ | |
3493 | Use \"on\" to enable the masking, and \"off\" to disable it.\n\ | |
3494 | Without an argument, zeroing of upper address bits is enabled.", &setlist), | |
3495 | &showlist); | |
c2a0f1cb | 3496 | } |