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7d9884b9 | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
97e091b2 | 2 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996 |
0434c1a0 | 3 | Free Software Foundation, Inc. |
bd5635a1 RP |
4 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
5 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
6 | ||
7 | This file is part of GDB. | |
8 | ||
361bf6ee | 9 | This program is free software; you can redistribute it and/or modify |
bd5635a1 | 10 | it under the terms of the GNU General Public License as published by |
361bf6ee JG |
11 | the Free Software Foundation; either version 2 of the License, or |
12 | (at your option) any later version. | |
bd5635a1 | 13 | |
361bf6ee | 14 | This program is distributed in the hope that it will be useful, |
bd5635a1 RP |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
361bf6ee | 20 | along with this program; if not, write to the Free Software |
09af5868 | 21 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ |
bd5635a1 | 22 | |
bd5635a1 | 23 | #include "defs.h" |
09af5868 | 24 | #include "gdb_string.h" |
bd5635a1 RP |
25 | #include "frame.h" |
26 | #include "inferior.h" | |
27 | #include "symtab.h" | |
28 | #include "value.h" | |
29 | #include "gdbcmd.h" | |
ef08856f | 30 | #include "language.h" |
bd5635a1 | 31 | #include "gdbcore.h" |
62a469e1 SG |
32 | #include "symfile.h" |
33 | #include "objfiles.h" | |
3fed1c4a | 34 | #include "gdbtypes.h" |
28444bf3 | 35 | #include "target.h" |
bd5635a1 | 36 | |
ee5fb959 JK |
37 | #include "opcode/mips.h" |
38 | ||
28444bf3 | 39 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
70126bf9 KH |
40 | |
41 | /* FIXME: Put this declaration in frame.h. */ | |
42 | extern struct obstack frame_cache_obstack; | |
28444bf3 DP |
43 | |
44 | /* FIXME! this code assumes 4-byte instructions. */ | |
96431497 | 45 | #define MIPS_INSTLEN 4 /* Length of an instruction */ |
20fa0902 | 46 | #define MIPS16_INSTLEN 2 /* Length of an instruction on MIPS16*/ |
96431497 MA |
47 | #define MIPS_NUMREGS 32 /* Number of integer or float registers */ |
48 | typedef unsigned long t_inst; /* Integer big enough to hold an instruction */ | |
28444bf3 | 49 | |
c1fc0935 MA |
50 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
51 | macros to test, set, or clear bit 0 of addresses. */ | |
52 | #define IS_MIPS16_ADDR(addr) ((addr) & 1) | |
53 | #define MAKE_MIPS16_ADDR(addr) ((addr) | 1) | |
54 | #define UNMAKE_MIPS16_ADDR(addr) ((addr) & ~1) | |
55 | ||
002a422b | 56 | #if 0 |
ee5fb959 | 57 | static int mips_in_lenient_prologue PARAMS ((CORE_ADDR, CORE_ADDR)); |
002a422b | 58 | #endif |
ee5fb959 | 59 | |
28444bf3 DP |
60 | static int gdb_print_insn_mips PARAMS ((bfd_vma, disassemble_info *)); |
61 | ||
f2bf454e FF |
62 | static void mips_print_register PARAMS ((int, int)); |
63 | ||
64 | static mips_extra_func_info_t | |
65 | heuristic_proc_desc PARAMS ((CORE_ADDR, CORE_ADDR, struct frame_info *)); | |
66 | ||
67 | static CORE_ADDR heuristic_proc_start PARAMS ((CORE_ADDR)); | |
68 | ||
28444bf3 | 69 | static CORE_ADDR read_next_frame_reg PARAMS ((struct frame_info *, int)); |
f2bf454e | 70 | |
e4dbd248 PS |
71 | static void mips_set_fpu_command PARAMS ((char *, int, |
72 | struct cmd_list_element *)); | |
73 | ||
74 | static void mips_show_fpu_command PARAMS ((char *, int, | |
75 | struct cmd_list_element *)); | |
76 | ||
9f9f94aa SS |
77 | void mips_set_processor_type_command PARAMS ((char *, int)); |
78 | ||
1d9489c1 JK |
79 | int mips_set_processor_type PARAMS ((char *)); |
80 | ||
81 | static void mips_show_processor_type_command PARAMS ((char *, int)); | |
82 | ||
9f9f94aa SS |
83 | static void reinit_frame_cache_sfunc PARAMS ((char *, int, |
84 | struct cmd_list_element *)); | |
85 | ||
f2bf454e FF |
86 | static mips_extra_func_info_t |
87 | find_proc_desc PARAMS ((CORE_ADDR pc, struct frame_info *next_frame)); | |
88 | ||
89 | static CORE_ADDR after_prologue PARAMS ((CORE_ADDR pc, | |
90 | mips_extra_func_info_t proc_desc)); | |
91 | ||
9f9f94aa SS |
92 | /* This value is the model of MIPS in use. It is derived from the value |
93 | of the PrID register. */ | |
94 | ||
95 | char *mips_processor_type; | |
96 | ||
97 | char *tmp_mips_processor_type; | |
98 | ||
c2a0f1cb ILT |
99 | /* Some MIPS boards don't support floating point, so we permit the |
100 | user to turn it off. */ | |
9f9f94aa | 101 | |
e4dbd248 PS |
102 | enum mips_fpu_type mips_fpu; |
103 | ||
104 | static char *mips_fpu_string; | |
c2a0f1cb | 105 | |
9f9f94aa SS |
106 | /* A set of original names, to be used when restoring back to generic |
107 | registers from a specific set. */ | |
108 | ||
109 | char *mips_generic_reg_names[] = REGISTER_NAMES; | |
110 | ||
111 | /* Names of IDT R3041 registers. */ | |
112 | ||
113 | char *mips_r3041_reg_names[] = { | |
114 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
115 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
116 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
117 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
118 | "sr", "lo", "hi", "bad", "cause","pc", | |
119 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
120 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
121 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
122 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
123 | "fsr", "fir", "fp", "", | |
124 | "", "", "bus", "ccfg", "", "", "", "", | |
125 | "", "", "port", "cmp", "", "", "epc", "prid", | |
126 | }; | |
127 | ||
128 | /* Names of IDT R3051 registers. */ | |
129 | ||
130 | char *mips_r3051_reg_names[] = { | |
131 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
132 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
133 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
134 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
135 | "sr", "lo", "hi", "bad", "cause","pc", | |
136 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
137 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
138 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
139 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
140 | "fsr", "fir", "fp", "", | |
141 | "inx", "rand", "elo", "", "ctxt", "", "", "", | |
142 | "", "", "ehi", "", "", "", "epc", "prid", | |
143 | }; | |
144 | ||
145 | /* Names of IDT R3081 registers. */ | |
146 | ||
147 | char *mips_r3081_reg_names[] = { | |
148 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
149 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
150 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
151 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
152 | "sr", "lo", "hi", "bad", "cause","pc", | |
153 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
154 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
155 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
156 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
157 | "fsr", "fir", "fp", "", | |
158 | "inx", "rand", "elo", "cfg", "ctxt", "", "", "", | |
159 | "", "", "ehi", "", "", "", "epc", "prid", | |
160 | }; | |
161 | ||
e4dbd248 PS |
162 | /* Names of LSI 33k registers. */ |
163 | ||
164 | char *mips_lsi33k_reg_names[] = { | |
165 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
166 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
167 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
168 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
169 | "epc", "hi", "lo", "sr", "cause","badvaddr", | |
170 | "dcic", "bpc", "bda", "", "", "", "", "", | |
171 | "", "", "", "", "", "", "", "", | |
172 | "", "", "", "", "", "", "", "", | |
173 | "", "", "", "", "", "", "", "", | |
174 | "", "", "", "", | |
175 | "", "", "", "", "", "", "", "", | |
176 | "", "", "", "", "", "", "", "", | |
177 | }; | |
178 | ||
9f9f94aa SS |
179 | struct { |
180 | char *name; | |
181 | char **regnames; | |
182 | } mips_processor_type_table[] = { | |
183 | { "generic", mips_generic_reg_names }, | |
184 | { "r3041", mips_r3041_reg_names }, | |
185 | { "r3051", mips_r3051_reg_names }, | |
186 | { "r3071", mips_r3081_reg_names }, | |
187 | { "r3081", mips_r3081_reg_names }, | |
e4dbd248 | 188 | { "lsi33k", mips_lsi33k_reg_names }, |
9f9f94aa SS |
189 | { NULL, NULL } |
190 | }; | |
191 | ||
f9f8c14b MA |
192 | /* Table to translate MIPS16 register field to actual register number. */ |
193 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; | |
194 | ||
3127785a RP |
195 | /* Heuristic_proc_start may hunt through the text section for a long |
196 | time across a 2400 baud serial line. Allows the user to limit this | |
197 | search. */ | |
9f9f94aa | 198 | |
3127785a RP |
199 | static unsigned int heuristic_fence_post = 0; |
200 | ||
0f552c5f | 201 | #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ |
28444bf3 | 202 | #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */ |
0f552c5f JG |
203 | #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) |
204 | #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) | |
205 | #define PROC_REG_MASK(proc) ((proc)->pdr.regmask) | |
206 | #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) | |
207 | #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) | |
208 | #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) | |
209 | #define PROC_PC_REG(proc) ((proc)->pdr.pcreg) | |
210 | #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) | |
bd5635a1 | 211 | #define _PROC_MAGIC_ 0x0F0F0F0F |
0f552c5f JG |
212 | #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_) |
213 | #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_) | |
bd5635a1 RP |
214 | |
215 | struct linked_proc_info | |
216 | { | |
217 | struct mips_extra_func_info info; | |
218 | struct linked_proc_info *next; | |
dac4929a | 219 | } *linked_proc_desc_table = NULL; |
bd5635a1 | 220 | |
f2bf454e FF |
221 | |
222 | /* This returns the PC of the first inst after the prologue. If we can't | |
223 | find the prologue, then return 0. */ | |
224 | ||
225 | static CORE_ADDR | |
226 | after_prologue (pc, proc_desc) | |
227 | CORE_ADDR pc; | |
228 | mips_extra_func_info_t proc_desc; | |
229 | { | |
230 | struct symtab_and_line sal; | |
231 | CORE_ADDR func_addr, func_end; | |
232 | ||
233 | if (!proc_desc) | |
234 | proc_desc = find_proc_desc (pc, NULL); | |
235 | ||
236 | if (proc_desc) | |
237 | { | |
238 | /* If function is frameless, then we need to do it the hard way. I | |
239 | strongly suspect that frameless always means prologueless... */ | |
240 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM | |
241 | && PROC_FRAME_OFFSET (proc_desc) == 0) | |
242 | return 0; | |
243 | } | |
244 | ||
245 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
246 | return 0; /* Unknown */ | |
247 | ||
248 | sal = find_pc_line (func_addr, 0); | |
249 | ||
250 | if (sal.end < func_end) | |
251 | return sal.end; | |
252 | ||
253 | /* The line after the prologue is after the end of the function. In this | |
254 | case, tell the caller to find the prologue the hard way. */ | |
255 | ||
256 | return 0; | |
257 | } | |
258 | ||
f9f8c14b MA |
259 | /* Decode a MIPS32 instruction that saves a register in the stack, and |
260 | set the appropriate bit in the general register mask or float register mask | |
261 | to indicate which register is saved. This is a helper function | |
262 | for mips_find_saved_regs. */ | |
263 | ||
264 | static void | |
265 | mips32_decode_reg_save (inst, gen_mask, float_mask) | |
266 | t_inst inst; | |
267 | unsigned long *gen_mask; | |
268 | unsigned long *float_mask; | |
269 | { | |
270 | int reg; | |
271 | ||
272 | if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */ | |
273 | || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */ | |
274 | || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */ | |
275 | { | |
276 | /* It might be possible to use the instruction to | |
277 | find the offset, rather than the code below which | |
278 | is based on things being in a certain order in the | |
279 | frame, but figuring out what the instruction's offset | |
280 | is relative to might be a little tricky. */ | |
281 | reg = (inst & 0x001f0000) >> 16; | |
282 | *gen_mask |= (1 << reg); | |
283 | } | |
284 | else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */ | |
285 | || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */ | |
286 | || (inst & 0xffe00000) == 0xf7a00000)/* sdc1 freg,n($sp) */ | |
287 | ||
288 | { | |
289 | reg = ((inst & 0x001f0000) >> 16); | |
290 | *float_mask |= (1 << reg); | |
291 | } | |
292 | } | |
293 | ||
294 | /* Decode a MIPS16 instruction that saves a register in the stack, and | |
295 | set the appropriate bit in the general register or float register mask | |
296 | to indicate which register is saved. This is a helper function | |
297 | for mips_find_saved_regs. */ | |
298 | ||
299 | static void | |
300 | mips16_decode_reg_save (inst, gen_mask) | |
301 | t_inst inst; | |
302 | unsigned long *gen_mask; | |
303 | { | |
b348b9fd | 304 | if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ |
f9f8c14b | 305 | { |
b348b9fd MA |
306 | int reg = mips16_to_32_reg[(inst & 0x700) >> 8]; |
307 | *gen_mask |= (1 << reg); | |
308 | } | |
309 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
310 | { | |
311 | int reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
f9f8c14b MA |
312 | *gen_mask |= (1 << reg); |
313 | } | |
314 | else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */ | |
315 | || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
316 | *gen_mask |= (1 << 31); | |
317 | } | |
318 | ||
c81a76b3 MA |
319 | |
320 | /* Fetch and return instruction from the specified location. If the PC | |
321 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
322 | ||
323 | static t_inst | |
324 | mips_fetch_instruction (addr) | |
325 | CORE_ADDR addr; | |
326 | { | |
327 | char buf[MIPS_INSTLEN]; | |
328 | int instlen; | |
329 | int status; | |
330 | ||
331 | if (IS_MIPS16_ADDR (addr)) | |
332 | { | |
333 | instlen = MIPS16_INSTLEN; | |
334 | addr = UNMAKE_MIPS16_ADDR (addr); | |
335 | } | |
336 | else | |
337 | instlen = MIPS_INSTLEN; | |
338 | status = read_memory_nobpt (addr, buf, instlen); | |
339 | if (status) | |
340 | memory_error (status, addr); | |
341 | return extract_unsigned_integer (buf, instlen); | |
342 | } | |
343 | ||
344 | ||
70126bf9 KH |
345 | /* Guaranteed to set fci->saved_regs to some values (it never leaves it |
346 | NULL). */ | |
347 | ||
348 | void | |
349 | mips_find_saved_regs (fci) | |
9f9f94aa | 350 | struct frame_info *fci; |
70126bf9 KH |
351 | { |
352 | int ireg; | |
353 | CORE_ADDR reg_position; | |
354 | /* r0 bit means kernel trap */ | |
355 | int kernel_trap; | |
356 | /* What registers have been saved? Bitmasks. */ | |
357 | unsigned long gen_mask, float_mask; | |
358 | mips_extra_func_info_t proc_desc; | |
c81a76b3 | 359 | t_inst inst; |
70126bf9 KH |
360 | |
361 | fci->saved_regs = (struct frame_saved_regs *) | |
362 | obstack_alloc (&frame_cache_obstack, sizeof(struct frame_saved_regs)); | |
363 | memset (fci->saved_regs, 0, sizeof (struct frame_saved_regs)); | |
364 | ||
e4dbd248 PS |
365 | /* If it is the frame for sigtramp, the saved registers are located |
366 | in a sigcontext structure somewhere on the stack. | |
367 | If the stack layout for sigtramp changes we might have to change these | |
368 | constants and the companion fixup_sigtramp in mdebugread.c */ | |
369 | #ifndef SIGFRAME_BASE | |
370 | /* To satisfy alignment restrictions, sigcontext is located 4 bytes | |
371 | above the sigtramp frame. */ | |
28444bf3 DP |
372 | #define SIGFRAME_BASE MIPS_REGSIZE |
373 | /* FIXME! Are these correct?? */ | |
374 | #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE) | |
375 | #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE) | |
376 | #define SIGFRAME_FPREGSAVE_OFF \ | |
377 | (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE) | |
e4dbd248 PS |
378 | #endif |
379 | #ifndef SIGFRAME_REG_SIZE | |
28444bf3 DP |
380 | /* FIXME! Is this correct?? */ |
381 | #define SIGFRAME_REG_SIZE MIPS_REGSIZE | |
e4dbd248 PS |
382 | #endif |
383 | if (fci->signal_handler_caller) | |
384 | { | |
28444bf3 | 385 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) |
e4dbd248 PS |
386 | { |
387 | reg_position = fci->frame + SIGFRAME_REGSAVE_OFF | |
388 | + ireg * SIGFRAME_REG_SIZE; | |
389 | fci->saved_regs->regs[ireg] = reg_position; | |
390 | } | |
28444bf3 | 391 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) |
e4dbd248 PS |
392 | { |
393 | reg_position = fci->frame + SIGFRAME_FPREGSAVE_OFF | |
394 | + ireg * SIGFRAME_REG_SIZE; | |
395 | fci->saved_regs->regs[FP0_REGNUM + ireg] = reg_position; | |
396 | } | |
397 | fci->saved_regs->regs[PC_REGNUM] = fci->frame + SIGFRAME_PC_OFF; | |
398 | return; | |
399 | } | |
400 | ||
70126bf9 KH |
401 | proc_desc = fci->proc_desc; |
402 | if (proc_desc == NULL) | |
403 | /* I'm not sure how/whether this can happen. Normally when we can't | |
404 | find a proc_desc, we "synthesize" one using heuristic_proc_desc | |
405 | and set the saved_regs right away. */ | |
406 | return; | |
407 | ||
408 | kernel_trap = PROC_REG_MASK(proc_desc) & 1; | |
409 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK(proc_desc); | |
410 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK(proc_desc); | |
411 | ||
f9f8c14b MA |
412 | if (/* In any frame other than the innermost or a frame interrupted by |
413 | a signal, we assume that all registers have been saved. | |
414 | This assumes that all register saves in a function happen before | |
415 | the first function call. */ | |
416 | (fci->next == NULL || fci->next->signal_handler_caller) | |
70126bf9 KH |
417 | |
418 | /* In a dummy frame we know exactly where things are saved. */ | |
419 | && !PROC_DESC_IS_DUMMY (proc_desc) | |
420 | ||
f2bf454e FF |
421 | /* Don't bother unless we are inside a function prologue. Outside the |
422 | prologue, we know where everything is. */ | |
423 | ||
424 | && in_prologue (fci->pc, PROC_LOW_ADDR (proc_desc)) | |
425 | ||
70126bf9 KH |
426 | /* Not sure exactly what kernel_trap means, but if it means |
427 | the kernel saves the registers without a prologue doing it, | |
428 | we better not examine the prologue to see whether registers | |
429 | have been saved yet. */ | |
430 | && !kernel_trap) | |
431 | { | |
432 | /* We need to figure out whether the registers that the proc_desc | |
433 | claims are saved have been saved yet. */ | |
434 | ||
435 | CORE_ADDR addr; | |
70126bf9 KH |
436 | |
437 | /* Bitmasks; set if we have found a save for the register. */ | |
438 | unsigned long gen_save_found = 0; | |
439 | unsigned long float_save_found = 0; | |
c81a76b3 | 440 | int instlen; |
70126bf9 | 441 | |
c1fc0935 MA |
442 | /* If the address is odd, assume this is MIPS16 code. */ |
443 | addr = PROC_LOW_ADDR (proc_desc); | |
c81a76b3 | 444 | instlen = IS_MIPS16_ADDR (addr) ? MIPS16_INSTLEN : MIPS_INSTLEN; |
f9f8c14b | 445 | |
20fa0902 MA |
446 | /* Scan through this function's instructions preceding the current |
447 | PC, and look for those that save registers. */ | |
f9f8c14b MA |
448 | while (addr < fci->pc) |
449 | { | |
c81a76b3 MA |
450 | inst = mips_fetch_instruction (addr); |
451 | if (IS_MIPS16_ADDR (addr)) | |
f9f8c14b MA |
452 | mips16_decode_reg_save (inst, &gen_save_found); |
453 | else | |
454 | mips32_decode_reg_save (inst, &gen_save_found, &float_save_found); | |
455 | addr += instlen; | |
70126bf9 KH |
456 | } |
457 | gen_mask = gen_save_found; | |
458 | float_mask = float_save_found; | |
459 | } | |
460 | ||
461 | /* Fill in the offsets for the registers which gen_mask says | |
462 | were saved. */ | |
463 | reg_position = fci->frame + PROC_REG_OFFSET (proc_desc); | |
28444bf3 | 464 | for (ireg= MIPS_NUMREGS-1; gen_mask; --ireg, gen_mask <<= 1) |
70126bf9 KH |
465 | if (gen_mask & 0x80000000) |
466 | { | |
467 | fci->saved_regs->regs[ireg] = reg_position; | |
468 | reg_position -= MIPS_REGSIZE; | |
469 | } | |
c81a76b3 MA |
470 | |
471 | /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order | |
472 | of that normally used by gcc. Therefore, we have to fetch the first | |
473 | instruction of the function, and if it's an entry instruction that | |
474 | saves $s0 or $s1, correct their saved addresses. */ | |
475 | if (IS_MIPS16_ADDR (PROC_LOW_ADDR (proc_desc))) | |
476 | { | |
477 | inst = mips_fetch_instruction (PROC_LOW_ADDR (proc_desc)); | |
478 | if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
479 | { | |
480 | int reg; | |
481 | int sreg_count = (inst >> 6) & 3; | |
482 | ||
483 | /* Check if the ra register was pushed on the stack. */ | |
484 | reg_position = fci->frame + PROC_REG_OFFSET (proc_desc); | |
485 | if (inst & 0x20) | |
486 | reg_position -= MIPS_REGSIZE; | |
487 | ||
488 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
489 | for (reg = 16; reg < sreg_count+16; reg++) | |
490 | { | |
491 | fci->saved_regs->regs[reg] = reg_position; | |
492 | reg_position -= MIPS_REGSIZE; | |
493 | } | |
494 | } | |
495 | } | |
496 | ||
70126bf9 KH |
497 | /* Fill in the offsets for the registers which float_mask says |
498 | were saved. */ | |
499 | reg_position = fci->frame + PROC_FREG_OFFSET (proc_desc); | |
500 | ||
501 | /* The freg_offset points to where the first *double* register | |
502 | is saved. So skip to the high-order word. */ | |
28444bf3 | 503 | if (! GDB_TARGET_IS_MIPS64) |
c81a76b3 | 504 | reg_position += MIPS_REGSIZE; |
28444bf3 | 505 | |
20fa0902 MA |
506 | /* Fill in the offsets for the float registers which float_mask says |
507 | were saved. */ | |
28444bf3 | 508 | for (ireg = MIPS_NUMREGS-1; float_mask; --ireg, float_mask <<= 1) |
70126bf9 KH |
509 | if (float_mask & 0x80000000) |
510 | { | |
511 | fci->saved_regs->regs[FP0_REGNUM+ireg] = reg_position; | |
512 | reg_position -= MIPS_REGSIZE; | |
513 | } | |
514 | ||
515 | fci->saved_regs->regs[PC_REGNUM] = fci->saved_regs->regs[RA_REGNUM]; | |
516 | } | |
bd5635a1 | 517 | |
28444bf3 | 518 | static CORE_ADDR |
bd5635a1 | 519 | read_next_frame_reg(fi, regno) |
9f9f94aa | 520 | struct frame_info *fi; |
bd5635a1 RP |
521 | int regno; |
522 | { | |
bd5635a1 | 523 | for (; fi; fi = fi->next) |
70126bf9 | 524 | { |
e4dbd248 PS |
525 | /* We have to get the saved sp from the sigcontext |
526 | if it is a signal handler frame. */ | |
527 | if (regno == SP_REGNUM && !fi->signal_handler_caller) | |
528 | return fi->frame; | |
70126bf9 KH |
529 | else |
530 | { | |
531 | if (fi->saved_regs == NULL) | |
532 | mips_find_saved_regs (fi); | |
533 | if (fi->saved_regs->regs[regno]) | |
534 | return read_memory_integer(fi->saved_regs->regs[regno], MIPS_REGSIZE); | |
535 | } | |
536 | } | |
537 | return read_register (regno); | |
bd5635a1 RP |
538 | } |
539 | ||
96431497 MA |
540 | /* mips_addr_bits_remove - remove useless address bits */ |
541 | ||
542 | CORE_ADDR | |
543 | mips_addr_bits_remove (addr) | |
544 | CORE_ADDR addr; | |
545 | { | |
97e091b2 MA |
546 | #if GDB_TARGET_IS_MIPS64 |
547 | if ((addr >> 32 == (CORE_ADDR)0xffffffff) | |
96431497 MA |
548 | && (strcmp(target_shortname,"pmon")==0 |
549 | || strcmp(target_shortname,"ddb")==0 | |
550 | || strcmp(target_shortname,"sim")==0)) | |
551 | { | |
552 | /* This hack is a work-around for existing boards using PMON, | |
553 | the simulator, and any other 64-bit targets that doesn't have | |
554 | true 64-bit addressing. On these targets, the upper 32 bits | |
555 | of addresses are ignored by the hardware. Thus, the PC or SP | |
556 | are likely to have been sign extended to all 1s by instruction | |
557 | sequences that load 32-bit addresses. For example, a typical | |
558 | piece of code that loads an address is this: | |
559 | lui $r2, <upper 16 bits> | |
560 | ori $r2, <lower 16 bits> | |
561 | But the lui sign-extends the value such that the upper 32 bits | |
562 | may be all 1s. The workaround is simply to mask off these bits. | |
563 | In the future, gcc may be changed to support true 64-bit | |
564 | addressing, and this masking will have to be disabled. */ | |
565 | addr &= (CORE_ADDR)0xffffffff; | |
566 | } | |
f9f8c14b MA |
567 | #else |
568 | /* Even when GDB is configured for some 32-bit targets (e.g. mips-elf), | |
569 | BFD is configured to handle 64-bit targets, so CORE_ADDR is 64 bits. | |
570 | So we still have to mask off useless bits from addresses. */ | |
571 | addr &= (CORE_ADDR)0xffffffff; | |
97e091b2 | 572 | #endif |
96431497 MA |
573 | |
574 | return addr; | |
575 | } | |
576 | ||
28444bf3 | 577 | CORE_ADDR |
bd5635a1 | 578 | mips_frame_saved_pc(frame) |
9f9f94aa | 579 | struct frame_info *frame; |
bd5635a1 | 580 | { |
28444bf3 | 581 | CORE_ADDR saved_pc; |
0f552c5f | 582 | mips_extra_func_info_t proc_desc = frame->proc_desc; |
0434c1a0 PS |
583 | /* We have to get the saved pc from the sigcontext |
584 | if it is a signal handler frame. */ | |
585 | int pcreg = frame->signal_handler_caller ? PC_REGNUM | |
586 | : (proc_desc ? PROC_PC_REG(proc_desc) : RA_REGNUM); | |
0f552c5f | 587 | |
bd5635a1 | 588 | if (proc_desc && PROC_DESC_IS_DUMMY(proc_desc)) |
28444bf3 DP |
589 | saved_pc = read_memory_integer(frame->frame - MIPS_REGSIZE, MIPS_REGSIZE); |
590 | else | |
591 | saved_pc = read_next_frame_reg(frame, pcreg); | |
0f552c5f | 592 | |
96431497 | 593 | return ADDR_BITS_REMOVE (saved_pc); |
bd5635a1 RP |
594 | } |
595 | ||
596 | static struct mips_extra_func_info temp_proc_desc; | |
597 | static struct frame_saved_regs temp_saved_regs; | |
598 | ||
a8172eea RP |
599 | /* This fencepost looks highly suspicious to me. Removing it also |
600 | seems suspicious as it could affect remote debugging across serial | |
3127785a | 601 | lines. */ |
a8172eea | 602 | |
0f552c5f JG |
603 | static CORE_ADDR |
604 | heuristic_proc_start(pc) | |
bd5635a1 RP |
605 | CORE_ADDR pc; |
606 | { | |
32dab603 MA |
607 | CORE_ADDR start_pc; |
608 | CORE_ADDR fence; | |
20fa0902 | 609 | int instlen; |
b348b9fd | 610 | int seen_adjsp = 0; |
0f552c5f | 611 | |
32dab603 MA |
612 | pc = ADDR_BITS_REMOVE (pc); |
613 | start_pc = pc; | |
614 | fence = start_pc - heuristic_fence_post; | |
0f552c5f | 615 | if (start_pc == 0) return 0; |
3127785a RP |
616 | |
617 | if (heuristic_fence_post == UINT_MAX | |
618 | || fence < VM_MIN_ADDRESS) | |
619 | fence = VM_MIN_ADDRESS; | |
0f552c5f | 620 | |
c1fc0935 | 621 | instlen = IS_MIPS16_ADDR (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN; |
20fa0902 | 622 | |
bd5635a1 | 623 | /* search back for previous return */ |
20fa0902 | 624 | for (start_pc -= instlen; ; start_pc -= instlen) |
a8172eea RP |
625 | if (start_pc < fence) |
626 | { | |
3127785a RP |
627 | /* It's not clear to me why we reach this point when |
628 | stop_soon_quietly, but with this test, at least we | |
629 | don't print out warnings for every child forked (eg, on | |
630 | decstation). 22apr93 rich@cygnus.com. */ | |
631 | if (!stop_soon_quietly) | |
632 | { | |
23d35572 JK |
633 | static int blurb_printed = 0; |
634 | ||
3127785a RP |
635 | if (fence == VM_MIN_ADDRESS) |
636 | warning("Hit beginning of text section without finding"); | |
637 | else | |
638 | warning("Hit heuristic-fence-post without finding"); | |
639 | ||
96431497 | 640 | warning("enclosing function for address 0x%s", paddr (pc)); |
23d35572 JK |
641 | if (!blurb_printed) |
642 | { | |
643 | printf_filtered ("\ | |
644 | This warning occurs if you are debugging a function without any symbols\n\ | |
645 | (for example, in a stripped executable). In that case, you may wish to\n\ | |
646 | increase the size of the search with the `set heuristic-fence-post' command.\n\ | |
647 | \n\ | |
648 | Otherwise, you told GDB there was a function where there isn't one, or\n\ | |
649 | (more likely) you have encountered a bug in GDB.\n"); | |
650 | blurb_printed = 1; | |
651 | } | |
3127785a RP |
652 | } |
653 | ||
a8172eea RP |
654 | return 0; |
655 | } | |
c1fc0935 | 656 | else if (IS_MIPS16_ADDR (start_pc)) |
20fa0902 | 657 | { |
c1fc0935 MA |
658 | unsigned short inst; |
659 | ||
b348b9fd MA |
660 | /* On MIPS16, any one of the following is likely to be the |
661 | start of a function: | |
662 | entry | |
663 | addiu sp,-n | |
664 | daddiu sp,-n | |
665 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
c81a76b3 | 666 | inst = mips_fetch_instruction (start_pc); |
b348b9fd MA |
667 | if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
668 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
669 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
670 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
671 | break; | |
672 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
673 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
674 | seen_adjsp = 1; | |
675 | else | |
676 | seen_adjsp = 0; | |
20fa0902 | 677 | } |
bd5635a1 | 678 | else if (ABOUT_TO_RETURN(start_pc)) |
20fa0902 MA |
679 | { |
680 | start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */ | |
bd5635a1 | 681 | break; |
20fa0902 | 682 | } |
bd5635a1 | 683 | |
bd5635a1 RP |
684 | #if 0 |
685 | /* skip nops (usually 1) 0 - is this */ | |
28444bf3 DP |
686 | while (start_pc < pc && read_memory_integer (start_pc, MIPS_INSTLEN) == 0) |
687 | start_pc += MIPS_INSTLEN; | |
bd5635a1 RP |
688 | #endif |
689 | return start_pc; | |
690 | } | |
691 | ||
c81a76b3 | 692 | /* Fetch the immediate value from a MIPS16 instruction. |
b348b9fd MA |
693 | If the previous instruction was an EXTEND, use it to extend |
694 | the upper bits of the immediate value. This is a helper function | |
695 | for mips16_heuristic_proc_desc. */ | |
696 | ||
697 | static int | |
698 | mips16_get_imm (prev_inst, inst, nbits, scale, is_signed) | |
699 | unsigned short prev_inst; /* previous instruction */ | |
700 | unsigned short inst; /* current current instruction */ | |
701 | int nbits; /* number of bits in imm field */ | |
702 | int scale; /* scale factor to be applied to imm */ | |
703 | int is_signed; /* is the imm field signed? */ | |
704 | { | |
705 | int offset; | |
706 | ||
707 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ | |
708 | { | |
7d9e8fac | 709 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); |
b348b9fd MA |
710 | if (offset & 0x8000) /* check for negative extend */ |
711 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
712 | return offset | (inst & 0x1f); | |
713 | } | |
714 | else | |
715 | { | |
716 | int max_imm = 1 << nbits; | |
717 | int mask = max_imm - 1; | |
718 | int sign_bit = max_imm >> 1; | |
719 | ||
720 | offset = inst & mask; | |
721 | if (is_signed && (offset & sign_bit)) | |
722 | offset = 0 - (max_imm - offset); | |
723 | return offset * scale; | |
724 | } | |
725 | } | |
726 | ||
727 | ||
728 | /* Fill in values in temp_proc_desc based on the MIPS16 instruction | |
729 | stream from start_pc to limit_pc. */ | |
730 | ||
731 | static void | |
732 | mips16_heuristic_proc_desc(start_pc, limit_pc, next_frame, sp) | |
bd5635a1 | 733 | CORE_ADDR start_pc, limit_pc; |
9f9f94aa | 734 | struct frame_info *next_frame; |
b348b9fd | 735 | CORE_ADDR sp; |
bd5635a1 | 736 | { |
b348b9fd MA |
737 | CORE_ADDR cur_pc; |
738 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
739 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
740 | unsigned inst = 0; /* current instruction */ | |
bd5635a1 | 741 | |
b348b9fd | 742 | PROC_FRAME_OFFSET(&temp_proc_desc) = 0; |
34df79fc | 743 | |
b348b9fd MA |
744 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN) |
745 | { | |
c81a76b3 | 746 | int reg, offset; |
b348b9fd MA |
747 | |
748 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
749 | the immediate offset extension from it in mips16_get_imm. */ | |
750 | prev_inst = inst; | |
751 | ||
c81a76b3 MA |
752 | /* Fetch and decode the instruction. */ |
753 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
b348b9fd MA |
754 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
755 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
756 | { | |
757 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
758 | if (offset < 0) /* negative stack adjustment? */ | |
759 | PROC_FRAME_OFFSET(&temp_proc_desc) -= offset; | |
760 | else | |
761 | /* Exit loop if a positive stack adjustment is found, which | |
762 | usually means that the stack cleanup code in the function | |
763 | epilogue is reached. */ | |
764 | break; | |
765 | } | |
766 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
767 | { | |
768 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
769 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
770 | PROC_REG_MASK(&temp_proc_desc) |= (1 << reg); | |
771 | temp_saved_regs.regs[reg] = sp + offset; | |
772 | } | |
773 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
774 | { | |
775 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
776 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
777 | PROC_REG_MASK(&temp_proc_desc) |= (1 << reg); | |
778 | temp_saved_regs.regs[reg] = sp + offset; | |
779 | } | |
780 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
781 | { | |
782 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
783 | PROC_REG_MASK(&temp_proc_desc) |= (1 << 31); | |
784 | temp_saved_regs.regs[31] = sp + offset; | |
97e091b2 | 785 | } |
b348b9fd MA |
786 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ |
787 | { | |
788 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
789 | PROC_REG_MASK(&temp_proc_desc) |= (1 << 31); | |
790 | temp_saved_regs.regs[31] = sp + offset; | |
bd5635a1 | 791 | } |
b348b9fd MA |
792 | else if (inst == 0x673d) /* move $s1, $sp */ |
793 | { | |
794 | frame_addr = read_next_frame_reg(next_frame, 30); | |
795 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
97e091b2 | 796 | } |
32dab603 MA |
797 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ |
798 | { | |
799 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
800 | frame_addr = sp + offset; | |
801 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
802 | } | |
b348b9fd MA |
803 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ |
804 | { | |
805 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
806 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
807 | PROC_REG_MASK(&temp_proc_desc) |= 1 << reg; | |
808 | temp_saved_regs.regs[reg] = frame_addr + offset; | |
809 | } | |
810 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
811 | { | |
812 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
813 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
814 | PROC_REG_MASK(&temp_proc_desc) |= 1 << reg; | |
815 | temp_saved_regs.regs[reg] = frame_addr + offset; | |
816 | } | |
817 | else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
818 | { | |
819 | int areg_count = (inst >> 8) & 7; | |
820 | int sreg_count = (inst >> 6) & 3; | |
821 | ||
822 | /* The entry instruction always subtracts 32 from the SP. */ | |
823 | PROC_FRAME_OFFSET(&temp_proc_desc) += 32; | |
824 | ||
825 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
c81a76b3 | 826 | for (reg = 4, offset = 32; reg < areg_count+4; reg++) |
b348b9fd MA |
827 | { |
828 | PROC_REG_MASK(&temp_proc_desc) |= 1 << reg; | |
829 | temp_saved_regs.regs[reg] = sp + offset; | |
c81a76b3 | 830 | offset -= MIPS_REGSIZE; |
b348b9fd MA |
831 | } |
832 | ||
833 | /* Check if the ra register was pushed on the stack. */ | |
834 | offset = 28; | |
835 | if (inst & 0x20) | |
836 | { | |
837 | PROC_REG_MASK(&temp_proc_desc) |= 1 << 31; | |
838 | temp_saved_regs.regs[31] = sp + offset; | |
c81a76b3 | 839 | offset -= MIPS_REGSIZE; |
b348b9fd MA |
840 | } |
841 | ||
842 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
c81a76b3 | 843 | for (reg = 16; reg < sreg_count+16; reg++) |
b348b9fd MA |
844 | { |
845 | PROC_REG_MASK(&temp_proc_desc) |= 1 << reg; | |
846 | temp_saved_regs.regs[reg] = sp + offset; | |
c81a76b3 | 847 | offset -= MIPS_REGSIZE; |
b348b9fd MA |
848 | } |
849 | } | |
7d9e8fac MA |
850 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
851 | cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */ | |
b348b9fd MA |
852 | } |
853 | } | |
854 | ||
855 | static void | |
856 | mips32_heuristic_proc_desc(start_pc, limit_pc, next_frame, sp) | |
857 | CORE_ADDR start_pc, limit_pc; | |
858 | struct frame_info *next_frame; | |
859 | CORE_ADDR sp; | |
860 | { | |
861 | CORE_ADDR cur_pc; | |
862 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ | |
863 | restart: | |
864 | PROC_FRAME_OFFSET(&temp_proc_desc) = 0; | |
865 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN) | |
866 | { | |
b348b9fd | 867 | unsigned long inst, high_word, low_word; |
c81a76b3 | 868 | int reg; |
b348b9fd MA |
869 | |
870 | /* Fetch the instruction. */ | |
c81a76b3 | 871 | inst = (unsigned long) mips_fetch_instruction (cur_pc); |
b348b9fd MA |
872 | |
873 | /* Save some code by pre-extracting some useful fields. */ | |
874 | high_word = (inst >> 16) & 0xffff; | |
875 | low_word = inst & 0xffff; | |
876 | reg = high_word & 0x1f; | |
877 | ||
878 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ | |
879 | || high_word == 0x23bd /* addi $sp,$sp,-i */ | |
880 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
881 | { | |
882 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
883 | PROC_FRAME_OFFSET(&temp_proc_desc) += 0x10000 - low_word; | |
884 | else | |
885 | /* Exit loop if a positive stack adjustment is found, which | |
886 | usually means that the stack cleanup code in the function | |
887 | epilogue is reached. */ | |
888 | break; | |
889 | } | |
890 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
891 | { | |
892 | PROC_REG_MASK(&temp_proc_desc) |= 1 << reg; | |
893 | temp_saved_regs.regs[reg] = sp + low_word; | |
894 | } | |
895 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
896 | { | |
897 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra, | |
898 | but the register size used is only 32 bits. Make the address | |
899 | for the saved register point to the lower 32 bits. */ | |
900 | PROC_REG_MASK(&temp_proc_desc) |= 1 << reg; | |
901 | temp_saved_regs.regs[reg] = sp + low_word + 8 - MIPS_REGSIZE; | |
902 | } | |
903 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
904 | { | |
905 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
32dab603 | 906 | if ((long)low_word != PROC_FRAME_OFFSET(&temp_proc_desc)) |
b348b9fd MA |
907 | frame_addr = sp + low_word; |
908 | else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) | |
909 | { | |
910 | unsigned alloca_adjust; | |
911 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
912 | frame_addr = read_next_frame_reg(next_frame, 30); | |
913 | alloca_adjust = (unsigned)(frame_addr - (sp + low_word)); | |
914 | if (alloca_adjust > 0) | |
915 | { | |
916 | /* FP > SP + frame_size. This may be because | |
917 | * of an alloca or somethings similar. | |
918 | * Fix sp to "pre-alloca" value, and try again. | |
919 | */ | |
920 | sp += alloca_adjust; | |
921 | goto restart; | |
bd5635a1 RP |
922 | } |
923 | } | |
924 | } | |
b348b9fd MA |
925 | /* move $30,$sp. With different versions of gas this will be either |
926 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
927 | Accept any one of these. */ | |
928 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
929 | { | |
930 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
931 | if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) | |
932 | { | |
933 | unsigned alloca_adjust; | |
934 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
935 | frame_addr = read_next_frame_reg(next_frame, 30); | |
936 | alloca_adjust = (unsigned)(frame_addr - sp); | |
937 | if (alloca_adjust > 0) | |
938 | { | |
939 | /* FP > SP + frame_size. This may be because | |
940 | * of an alloca or somethings similar. | |
941 | * Fix sp to "pre-alloca" value, and try again. | |
942 | */ | |
943 | sp += alloca_adjust; | |
944 | goto restart; | |
97e091b2 MA |
945 | } |
946 | } | |
947 | } | |
b348b9fd MA |
948 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ |
949 | { | |
950 | PROC_REG_MASK(&temp_proc_desc) |= 1 << reg; | |
951 | temp_saved_regs.regs[reg] = frame_addr + low_word; | |
bd5635a1 RP |
952 | } |
953 | } | |
b348b9fd MA |
954 | } |
955 | ||
956 | static mips_extra_func_info_t | |
957 | heuristic_proc_desc(start_pc, limit_pc, next_frame) | |
958 | CORE_ADDR start_pc, limit_pc; | |
959 | struct frame_info *next_frame; | |
960 | { | |
961 | CORE_ADDR sp = read_next_frame_reg (next_frame, SP_REGNUM); | |
962 | ||
963 | if (start_pc == 0) return NULL; | |
964 | memset (&temp_proc_desc, '\0', sizeof(temp_proc_desc)); | |
965 | memset (&temp_saved_regs, '\0', sizeof(struct frame_saved_regs)); | |
966 | PROC_LOW_ADDR (&temp_proc_desc) = start_pc; | |
967 | PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM; | |
968 | PROC_PC_REG (&temp_proc_desc) = RA_REGNUM; | |
969 | ||
970 | if (start_pc + 200 < limit_pc) | |
971 | limit_pc = start_pc + 200; | |
c1fc0935 | 972 | if (IS_MIPS16_ADDR (start_pc)) |
b348b9fd MA |
973 | mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); |
974 | else | |
975 | mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
976 | return &temp_proc_desc; | |
bd5635a1 RP |
977 | } |
978 | ||
0f552c5f | 979 | static mips_extra_func_info_t |
c1fc0935 | 980 | non_heuristic_proc_desc (pc, addrptr) |
9f9f94aa | 981 | CORE_ADDR pc; |
c1fc0935 | 982 | CORE_ADDR *addrptr; |
bd5635a1 | 983 | { |
c1fc0935 | 984 | CORE_ADDR startaddr; |
bd5635a1 | 985 | mips_extra_func_info_t proc_desc; |
0f552c5f | 986 | struct block *b = block_for_pc(pc); |
48be4c35 | 987 | struct symbol *sym; |
48be4c35 JK |
988 | |
989 | find_pc_partial_function (pc, NULL, &startaddr, NULL); | |
c1fc0935 MA |
990 | if (addrptr) |
991 | *addrptr = startaddr; | |
97e091b2 | 992 | if (b == NULL || PC_IN_CALL_DUMMY (pc, 0, 0)) |
48be4c35 JK |
993 | sym = NULL; |
994 | else | |
995 | { | |
996 | if (startaddr > BLOCK_START (b)) | |
997 | /* This is the "pathological" case referred to in a comment in | |
998 | print_frame_info. It might be better to move this check into | |
999 | symbol reading. */ | |
1000 | sym = NULL; | |
1001 | else | |
c1fc0935 | 1002 | sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_NAMESPACE, 0, NULL); |
48be4c35 | 1003 | } |
0f552c5f | 1004 | |
e4dbd248 PS |
1005 | /* If we never found a PDR for this function in symbol reading, then |
1006 | examine prologues to find the information. */ | |
0f552c5f | 1007 | if (sym) |
bd5635a1 | 1008 | { |
c1fc0935 MA |
1009 | proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); |
1010 | if (PROC_FRAME_REG (proc_desc) == -1) | |
1011 | return NULL; | |
1012 | else | |
1013 | return proc_desc; | |
1014 | } | |
1015 | else | |
1016 | return NULL; | |
1017 | } | |
1018 | ||
1019 | ||
1020 | static mips_extra_func_info_t | |
1021 | find_proc_desc (pc, next_frame) | |
1022 | CORE_ADDR pc; | |
1023 | struct frame_info *next_frame; | |
1024 | { | |
1025 | mips_extra_func_info_t proc_desc; | |
1026 | CORE_ADDR startaddr; | |
1027 | ||
1028 | proc_desc = non_heuristic_proc_desc (pc, &startaddr); | |
1029 | ||
1030 | if (proc_desc) | |
1031 | { | |
1032 | /* IF this is the topmost frame AND | |
1033 | * (this proc does not have debugging information OR | |
1034 | * the PC is in the procedure prologue) | |
1035 | * THEN create a "heuristic" proc_desc (by analyzing | |
1036 | * the actual code) to replace the "official" proc_desc. | |
1037 | */ | |
1038 | if (next_frame == NULL) | |
1039 | { | |
1040 | struct symtab_and_line val; | |
1041 | struct symbol *proc_symbol = | |
1042 | PROC_DESC_IS_DUMMY(proc_desc) ? 0 : PROC_SYMBOL(proc_desc); | |
1043 | ||
1044 | if (proc_symbol) | |
1045 | { | |
1046 | val = find_pc_line (BLOCK_START | |
1047 | (SYMBOL_BLOCK_VALUE(proc_symbol)), | |
1048 | 0); | |
1049 | val.pc = val.end ? val.end : pc; | |
bd5635a1 | 1050 | } |
c1fc0935 MA |
1051 | if (!proc_symbol || pc < val.pc) |
1052 | { | |
1053 | mips_extra_func_info_t found_heuristic = | |
1054 | heuristic_proc_desc (PROC_LOW_ADDR (proc_desc), | |
1055 | pc, next_frame); | |
1056 | if (found_heuristic) | |
1057 | proc_desc = found_heuristic; | |
bd5635a1 RP |
1058 | } |
1059 | } | |
1060 | } | |
1061 | else | |
1062 | { | |
0f552c5f JG |
1063 | /* Is linked_proc_desc_table really necessary? It only seems to be used |
1064 | by procedure call dummys. However, the procedures being called ought | |
1065 | to have their own proc_descs, and even if they don't, | |
1066 | heuristic_proc_desc knows how to create them! */ | |
1067 | ||
bd5635a1 | 1068 | register struct linked_proc_info *link; |
9f9f94aa | 1069 | |
bd5635a1 | 1070 | for (link = linked_proc_desc_table; link; link = link->next) |
9f9f94aa SS |
1071 | if (PROC_LOW_ADDR(&link->info) <= pc |
1072 | && PROC_HIGH_ADDR(&link->info) > pc) | |
1073 | return &link->info; | |
23d35572 | 1074 | |
48be4c35 JK |
1075 | if (startaddr == 0) |
1076 | startaddr = heuristic_proc_start (pc); | |
1077 | ||
bd5635a1 | 1078 | proc_desc = |
48be4c35 | 1079 | heuristic_proc_desc (startaddr, pc, next_frame); |
bd5635a1 RP |
1080 | } |
1081 | return proc_desc; | |
1082 | } | |
1083 | ||
96431497 MA |
1084 | static CORE_ADDR |
1085 | get_frame_pointer(frame, proc_desc) | |
1086 | struct frame_info *frame; | |
1087 | mips_extra_func_info_t proc_desc; | |
1088 | { | |
1089 | return ADDR_BITS_REMOVE (read_next_frame_reg (frame, | |
1090 | PROC_FRAME_REG(proc_desc)) + PROC_FRAME_OFFSET(proc_desc)); | |
1091 | } | |
1092 | ||
bd5635a1 RP |
1093 | mips_extra_func_info_t cached_proc_desc; |
1094 | ||
9f9f94aa | 1095 | CORE_ADDR |
0f552c5f | 1096 | mips_frame_chain(frame) |
9f9f94aa | 1097 | struct frame_info *frame; |
bd5635a1 | 1098 | { |
bd5635a1 RP |
1099 | mips_extra_func_info_t proc_desc; |
1100 | CORE_ADDR saved_pc = FRAME_SAVED_PC(frame); | |
be772100 | 1101 | |
0f552c5f JG |
1102 | if (saved_pc == 0 || inside_entry_file (saved_pc)) |
1103 | return 0; | |
1104 | ||
bd5635a1 | 1105 | proc_desc = find_proc_desc(saved_pc, frame); |
0f552c5f JG |
1106 | if (!proc_desc) |
1107 | return 0; | |
1108 | ||
bd5635a1 | 1109 | cached_proc_desc = proc_desc; |
e797b4bc JK |
1110 | |
1111 | /* If no frame pointer and frame size is zero, we must be at end | |
1112 | of stack (or otherwise hosed). If we don't check frame size, | |
1113 | we loop forever if we see a zero size frame. */ | |
1114 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM | |
3f528883 | 1115 | && PROC_FRAME_OFFSET (proc_desc) == 0 |
199b2450 TL |
1116 | /* The previous frame from a sigtramp frame might be frameless |
1117 | and have frame size zero. */ | |
1118 | && !frame->signal_handler_caller) | |
bdef72d2 JK |
1119 | return 0; |
1120 | else | |
96431497 | 1121 | return get_frame_pointer (frame, proc_desc); |
bd5635a1 RP |
1122 | } |
1123 | ||
1124 | void | |
1125 | init_extra_frame_info(fci) | |
1126 | struct frame_info *fci; | |
1127 | { | |
96431497 MA |
1128 | int regnum; |
1129 | ||
bd5635a1 | 1130 | /* Use proc_desc calculated in frame_chain */ |
ee5fb959 JK |
1131 | mips_extra_func_info_t proc_desc = |
1132 | fci->next ? cached_proc_desc : find_proc_desc(fci->pc, fci->next); | |
0f552c5f | 1133 | |
70126bf9 | 1134 | fci->saved_regs = NULL; |
bd5635a1 | 1135 | fci->proc_desc = |
ee5fb959 | 1136 | proc_desc == &temp_proc_desc ? 0 : proc_desc; |
bd5635a1 RP |
1137 | if (proc_desc) |
1138 | { | |
c2a0f1cb | 1139 | /* Fixup frame-pointer - only needed for top frame */ |
5efd597b PS |
1140 | /* This may not be quite right, if proc has a real frame register. |
1141 | Get the value of the frame relative sp, procedure might have been | |
1142 | interrupted by a signal at it's very start. */ | |
70126bf9 KH |
1143 | if (fci->pc == PROC_LOW_ADDR (proc_desc) |
1144 | && !PROC_DESC_IS_DUMMY (proc_desc)) | |
1145 | fci->frame = read_next_frame_reg (fci->next, SP_REGNUM); | |
c2a0f1cb | 1146 | else |
96431497 | 1147 | fci->frame = get_frame_pointer (fci->next, proc_desc); |
bd5635a1 | 1148 | |
48be4c35 | 1149 | if (proc_desc == &temp_proc_desc) |
ee5fb959 | 1150 | { |
09af5868 PS |
1151 | char *name; |
1152 | ||
1153 | /* Do not set the saved registers for a sigtramp frame, | |
1154 | mips_find_saved_registers will do that for us. | |
1155 | We can't use fci->signal_handler_caller, it is not yet set. */ | |
1156 | find_pc_partial_function (fci->pc, &name, | |
1157 | (CORE_ADDR *)NULL,(CORE_ADDR *)NULL); | |
1158 | if (!IN_SIGTRAMP (fci->pc, name)) | |
1159 | { | |
1160 | fci->saved_regs = (struct frame_saved_regs*) | |
1161 | obstack_alloc (&frame_cache_obstack, | |
1162 | sizeof (struct frame_saved_regs)); | |
1163 | *fci->saved_regs = temp_saved_regs; | |
1164 | fci->saved_regs->regs[PC_REGNUM] | |
1165 | = fci->saved_regs->regs[RA_REGNUM]; | |
1166 | } | |
ee5fb959 | 1167 | } |
bd5635a1 RP |
1168 | |
1169 | /* hack: if argument regs are saved, guess these contain args */ | |
96431497 MA |
1170 | fci->num_args = -1; /* assume we can't tell how many args for now */ |
1171 | for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--) | |
1172 | { | |
1173 | if (PROC_REG_MASK(proc_desc) & (1 << regnum)) | |
1174 | { | |
1175 | fci->num_args = regnum - A0_REGNUM + 1; | |
1176 | break; | |
1177 | } | |
1178 | } | |
bd5635a1 | 1179 | } |
bd5635a1 RP |
1180 | } |
1181 | ||
a70dc898 RP |
1182 | /* MIPS stack frames are almost impenetrable. When execution stops, |
1183 | we basically have to look at symbol information for the function | |
1184 | that we stopped in, which tells us *which* register (if any) is | |
1185 | the base of the frame pointer, and what offset from that register | |
1186 | the frame itself is at. | |
1187 | ||
1188 | This presents a problem when trying to examine a stack in memory | |
1189 | (that isn't executing at the moment), using the "frame" command. We | |
1190 | don't have a PC, nor do we have any registers except SP. | |
1191 | ||
1192 | This routine takes two arguments, SP and PC, and tries to make the | |
1193 | cached frames look as if these two arguments defined a frame on the | |
1194 | cache. This allows the rest of info frame to extract the important | |
1195 | arguments without difficulty. */ | |
1196 | ||
9f9f94aa | 1197 | struct frame_info * |
c2a0f1cb ILT |
1198 | setup_arbitrary_frame (argc, argv) |
1199 | int argc; | |
9f9f94aa | 1200 | CORE_ADDR *argv; |
a70dc898 | 1201 | { |
c2a0f1cb ILT |
1202 | if (argc != 2) |
1203 | error ("MIPS frame specifications require two arguments: sp and pc"); | |
1204 | ||
1205 | return create_new_frame (argv[0], argv[1]); | |
a70dc898 RP |
1206 | } |
1207 | ||
0f552c5f JG |
1208 | CORE_ADDR |
1209 | mips_push_arguments(nargs, args, sp, struct_return, struct_addr) | |
97e091b2 MA |
1210 | int nargs; |
1211 | value_ptr *args; | |
1212 | CORE_ADDR sp; | |
1213 | int struct_return; | |
1214 | CORE_ADDR struct_addr; | |
bd5635a1 | 1215 | { |
97e091b2 MA |
1216 | int argreg; |
1217 | int float_argreg; | |
1218 | int argnum; | |
1219 | int len = 0; | |
1220 | int stack_offset; | |
1221 | ||
1222 | /* Macros to round N up or down to the next A boundary; A must be | |
1223 | a power of two. */ | |
1224 | #define ROUND_DOWN(n,a) ((n) & ~((a)-1)) | |
1225 | #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1)) | |
28444bf3 DP |
1226 | |
1227 | /* First ensure that the stack and structure return address (if any) | |
97e091b2 MA |
1228 | are properly aligned. The stack has to be 64-bit aligned even |
1229 | on 32-bit machines, because doubles must be 64-bit aligned. */ | |
1230 | sp = ROUND_DOWN (sp, 8); | |
1231 | struct_addr = ROUND_DOWN (struct_addr, MIPS_REGSIZE); | |
28444bf3 | 1232 | |
97e091b2 MA |
1233 | /* Now make space on the stack for the args. We allocate more |
1234 | than necessary for EABI, because the first few arguments are | |
1235 | passed in registers, but that's OK. */ | |
1236 | for (argnum = 0; argnum < nargs; argnum++) | |
1237 | len += ROUND_UP (TYPE_LENGTH(VALUE_TYPE(args[argnum])), MIPS_REGSIZE); | |
61d2d19a | 1238 | sp -= ROUND_UP (len, 8); |
97e091b2 MA |
1239 | |
1240 | /* Initialize the integer and float register pointers. */ | |
1241 | argreg = A0_REGNUM; | |
1242 | float_argreg = FPA0_REGNUM; | |
1243 | ||
1244 | /* the struct_return pointer occupies the first parameter-passing reg */ | |
5efd597b | 1245 | if (struct_return) |
97e091b2 MA |
1246 | write_register (argreg++, struct_addr); |
1247 | ||
1248 | /* The offset onto the stack at which we will start copying parameters | |
1249 | (after the registers are used up) begins at 16 in the old ABI. | |
1250 | This leaves room for the "home" area for register parameters. */ | |
1251 | stack_offset = MIPS_EABI ? 0 : MIPS_REGSIZE * 4; | |
1252 | ||
1253 | /* Now load as many as possible of the first arguments into | |
1254 | registers, and push the rest onto the stack. Loop thru args | |
1255 | from first to last. */ | |
1256 | for (argnum = 0; argnum < nargs; argnum++) | |
5efd597b | 1257 | { |
97e091b2 MA |
1258 | char *val; |
1259 | char valbuf[REGISTER_RAW_SIZE(A0_REGNUM)]; | |
1260 | value_ptr arg = args[argnum]; | |
1261 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
1262 | int len = TYPE_LENGTH (arg_type); | |
1263 | enum type_code typecode = TYPE_CODE (arg_type); | |
1264 | ||
61d2d19a PS |
1265 | /* The EABI passes structures that do not fit in a register by |
1266 | reference. In all other cases, pass the structure by value. */ | |
1267 | if (typecode == TYPE_CODE_STRUCT && MIPS_EABI && len > MIPS_REGSIZE) | |
97e091b2 MA |
1268 | { |
1269 | store_address (valbuf, MIPS_REGSIZE, VALUE_ADDRESS (arg)); | |
1270 | len = MIPS_REGSIZE; | |
1271 | val = valbuf; | |
1272 | } | |
1273 | else | |
1274 | val = (char *)VALUE_CONTENTS (arg); | |
1275 | ||
1276 | /* 32-bit ABIs always start floating point arguments in an | |
1277 | even-numbered floating point register. */ | |
1278 | if (!GDB_TARGET_IS_MIPS64 && typecode == TYPE_CODE_FLT | |
1279 | && (float_argreg & 1)) | |
1280 | float_argreg++; | |
1281 | ||
1282 | /* Floating point arguments passed in registers have to be | |
1283 | treated specially. On 32-bit architectures, doubles | |
1284 | are passed in register pairs; the even register gets | |
c81a76b3 MA |
1285 | the low word, and the odd register gets the high word. |
1286 | On non-EABI processors, the first two floating point arguments are | |
1287 | also copied to general registers, because MIPS16 functions | |
1288 | don't use float registers for arguments. This duplication of | |
1289 | arguments in general registers can't hurt non-MIPS16 functions | |
1290 | because those registers are normally skipped. */ | |
97e091b2 MA |
1291 | if (typecode == TYPE_CODE_FLT |
1292 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM | |
1293 | && mips_fpu != MIPS_FPU_NONE) | |
1294 | { | |
1295 | if (!GDB_TARGET_IS_MIPS64 && len == 8) | |
1296 | { | |
1297 | int low_offset = TARGET_BYTE_ORDER == BIG_ENDIAN ? 4 : 0; | |
1298 | unsigned long regval; | |
1299 | ||
c81a76b3 | 1300 | /* Write the low word of the double to the even register(s). */ |
97e091b2 | 1301 | regval = extract_unsigned_integer (val+low_offset, 4); |
c81a76b3 MA |
1302 | write_register (float_argreg++, regval); |
1303 | if (!MIPS_EABI) | |
1304 | write_register (argreg+1, regval); | |
1305 | ||
1306 | /* Write the high word of the double to the odd register(s). */ | |
97e091b2 | 1307 | regval = extract_unsigned_integer (val+4-low_offset, 4); |
c81a76b3 MA |
1308 | write_register (float_argreg++, regval); |
1309 | if (!MIPS_EABI) | |
1310 | { | |
1311 | write_register (argreg, regval); | |
1312 | argreg += 2; | |
1313 | } | |
97e091b2 MA |
1314 | |
1315 | } | |
1316 | else | |
1317 | { | |
c81a76b3 MA |
1318 | /* This is a floating point value that fits entirely |
1319 | in a single register. */ | |
97e091b2 MA |
1320 | CORE_ADDR regval = extract_address (val, len); |
1321 | write_register (float_argreg++, regval); | |
c81a76b3 MA |
1322 | if (!MIPS_EABI) |
1323 | { | |
1324 | write_register (argreg, regval); | |
1325 | argreg += GDB_TARGET_IS_MIPS64 ? 1 : 2; | |
1326 | } | |
97e091b2 | 1327 | } |
97e091b2 MA |
1328 | } |
1329 | else | |
1330 | { | |
1331 | /* Copy the argument to general registers or the stack in | |
1332 | register-sized pieces. Large arguments are split between | |
1333 | registers and stack. */ | |
1334 | while (len > 0) | |
1335 | { | |
1336 | int partial_len = len < MIPS_REGSIZE ? len : MIPS_REGSIZE; | |
61d2d19a | 1337 | |
97e091b2 MA |
1338 | if (argreg <= MIPS_LAST_ARG_REGNUM) |
1339 | { | |
61d2d19a PS |
1340 | CORE_ADDR regval = extract_address (val, partial_len); |
1341 | ||
1342 | /* It's a simple argument being passed in a general | |
1343 | register. | |
1344 | If the argument length is smaller than the register size, | |
b348b9fd MA |
1345 | we have to adjust the argument on big endian targets. |
1346 | But don't do this adjustment on EABI targets. */ | |
61d2d19a | 1347 | if (TARGET_BYTE_ORDER == BIG_ENDIAN |
b348b9fd MA |
1348 | && partial_len < MIPS_REGSIZE |
1349 | && !MIPS_EABI) | |
61d2d19a | 1350 | regval <<= ((MIPS_REGSIZE - partial_len) * TARGET_CHAR_BIT); |
97e091b2 MA |
1351 | write_register (argreg, regval); |
1352 | argreg++; | |
1353 | ||
1354 | /* If this is the old ABI, prevent subsequent floating | |
1355 | point arguments from being passed in floating point | |
1356 | registers. */ | |
1357 | if (!MIPS_EABI) | |
1358 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
1359 | } | |
1360 | else | |
1361 | { | |
61d2d19a PS |
1362 | /* Write this portion of the argument to the stack. */ |
1363 | partial_len = len; | |
1364 | write_memory (sp + stack_offset, val, partial_len); | |
1365 | stack_offset += ROUND_UP (partial_len, MIPS_REGSIZE); | |
97e091b2 MA |
1366 | } |
1367 | ||
1368 | len -= partial_len; | |
1369 | val += partial_len; | |
1370 | } | |
1371 | } | |
5efd597b | 1372 | } |
97e091b2 MA |
1373 | |
1374 | /* Set the return address register to point to the entry | |
1375 | point of the program, where a breakpoint lies in wait. */ | |
1376 | write_register (RA_REGNUM, CALL_DUMMY_ADDRESS()); | |
1377 | ||
1378 | /* Return adjusted stack pointer. */ | |
bd5635a1 RP |
1379 | return sp; |
1380 | } | |
1381 | ||
c81a76b3 | 1382 | static void |
28444bf3 DP |
1383 | mips_push_register(CORE_ADDR *sp, int regno) |
1384 | { | |
1385 | char buffer[MAX_REGISTER_RAW_SIZE]; | |
1386 | int regsize = REGISTER_RAW_SIZE (regno); | |
1387 | ||
1388 | *sp -= regsize; | |
1389 | read_register_gen (regno, buffer); | |
1390 | write_memory (*sp, buffer, regsize); | |
1391 | } | |
1392 | ||
1393 | /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */ | |
e03c0cc6 | 1394 | #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1)) |
bd5635a1 RP |
1395 | |
1396 | void | |
1397 | mips_push_dummy_frame() | |
1398 | { | |
1399 | int ireg; | |
1400 | struct linked_proc_info *link = (struct linked_proc_info*) | |
1401 | xmalloc(sizeof(struct linked_proc_info)); | |
1402 | mips_extra_func_info_t proc_desc = &link->info; | |
96431497 | 1403 | CORE_ADDR sp = ADDR_BITS_REMOVE (read_register (SP_REGNUM)); |
28444bf3 | 1404 | CORE_ADDR old_sp = sp; |
bd5635a1 RP |
1405 | link->next = linked_proc_desc_table; |
1406 | linked_proc_desc_table = link; | |
28444bf3 DP |
1407 | |
1408 | /* FIXME! are these correct ? */ | |
bd5635a1 | 1409 | #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */ |
28444bf3 | 1410 | #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1)) |
bd5635a1 | 1411 | #define FLOAT_REG_SAVE_MASK MASK(0,19) |
e4dbd248 PS |
1412 | #define FLOAT_SINGLE_REG_SAVE_MASK \ |
1413 | ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0)) | |
bd5635a1 RP |
1414 | /* |
1415 | * The registers we must save are all those not preserved across | |
1416 | * procedure calls. Dest_Reg (see tm-mips.h) must also be saved. | |
28444bf3 DP |
1417 | * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI |
1418 | * and FP Control/Status registers. | |
1419 | * | |
bd5635a1 RP |
1420 | * |
1421 | * Dummy frame layout: | |
1422 | * (high memory) | |
1423 | * Saved PC | |
1424 | * Saved MMHI, MMLO, FPC_CSR | |
1425 | * Saved R31 | |
1426 | * Saved R28 | |
1427 | * ... | |
1428 | * Saved R1 | |
1429 | * Saved D18 (i.e. F19, F18) | |
1430 | * ... | |
1431 | * Saved D0 (i.e. F1, F0) | |
f9f8c14b | 1432 | * Argument build area and stack arguments written via mips_push_arguments |
bd5635a1 RP |
1433 | * (low memory) |
1434 | */ | |
28444bf3 DP |
1435 | |
1436 | /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */ | |
28444bf3 DP |
1437 | PROC_FRAME_REG(proc_desc) = PUSH_FP_REGNUM; |
1438 | PROC_FRAME_OFFSET(proc_desc) = 0; | |
1439 | mips_push_register (&sp, PC_REGNUM); | |
1440 | mips_push_register (&sp, HI_REGNUM); | |
1441 | mips_push_register (&sp, LO_REGNUM); | |
1442 | mips_push_register (&sp, mips_fpu == MIPS_FPU_NONE ? 0 : FCRCS_REGNUM); | |
1443 | ||
1444 | /* Save general CPU registers */ | |
bd5635a1 | 1445 | PROC_REG_MASK(proc_desc) = GEN_REG_SAVE_MASK; |
28444bf3 | 1446 | PROC_REG_OFFSET(proc_desc) = sp - old_sp; /* offset of (Saved R31) from FP */ |
bd5635a1 RP |
1447 | for (ireg = 32; --ireg >= 0; ) |
1448 | if (PROC_REG_MASK(proc_desc) & (1 << ireg)) | |
28444bf3 | 1449 | mips_push_register (&sp, ireg); |
3fed1c4a | 1450 | |
28444bf3 DP |
1451 | /* Save floating point registers starting with high order word */ |
1452 | PROC_FREG_MASK(proc_desc) = | |
1453 | mips_fpu == MIPS_FPU_DOUBLE ? FLOAT_REG_SAVE_MASK | |
1454 | : mips_fpu == MIPS_FPU_SINGLE ? FLOAT_SINGLE_REG_SAVE_MASK : 0; | |
1455 | PROC_FREG_OFFSET(proc_desc) = sp - old_sp; /* offset of (Saved D18) from FP */ | |
bd5635a1 RP |
1456 | for (ireg = 32; --ireg >= 0; ) |
1457 | if (PROC_FREG_MASK(proc_desc) & (1 << ireg)) | |
28444bf3 | 1458 | mips_push_register (&sp, ireg + FP0_REGNUM); |
3fed1c4a | 1459 | |
f9f8c14b MA |
1460 | /* Update the frame pointer for the call dummy and the stack pointer. |
1461 | Set the procedure's starting and ending addresses to point to the | |
1462 | call dummy address at the entry point. */ | |
1463 | write_register (PUSH_FP_REGNUM, old_sp); | |
bd5635a1 | 1464 | write_register (SP_REGNUM, sp); |
97e091b2 MA |
1465 | PROC_LOW_ADDR(proc_desc) = CALL_DUMMY_ADDRESS(); |
1466 | PROC_HIGH_ADDR(proc_desc) = CALL_DUMMY_ADDRESS() + 4; | |
bd5635a1 RP |
1467 | SET_PROC_DESC_IS_DUMMY(proc_desc); |
1468 | PROC_PC_REG(proc_desc) = RA_REGNUM; | |
1469 | } | |
1470 | ||
1471 | void | |
1472 | mips_pop_frame() | |
dac4929a SG |
1473 | { |
1474 | register int regnum; | |
9f9f94aa SS |
1475 | struct frame_info *frame = get_current_frame (); |
1476 | CORE_ADDR new_sp = FRAME_FP (frame); | |
dac4929a | 1477 | |
a70dc898 | 1478 | mips_extra_func_info_t proc_desc = frame->proc_desc; |
dac4929a SG |
1479 | |
1480 | write_register (PC_REGNUM, FRAME_SAVED_PC(frame)); | |
70126bf9 KH |
1481 | if (frame->saved_regs == NULL) |
1482 | mips_find_saved_regs (frame); | |
61d2d19a | 1483 | for (regnum = 0; regnum < NUM_REGS; regnum++) |
dac4929a | 1484 | { |
61d2d19a PS |
1485 | if (regnum != SP_REGNUM && regnum != PC_REGNUM |
1486 | && frame->saved_regs->regs[regnum]) | |
1487 | write_register (regnum, | |
1488 | read_memory_integer (frame->saved_regs->regs[regnum], | |
1489 | MIPS_REGSIZE)); | |
dac4929a SG |
1490 | } |
1491 | write_register (SP_REGNUM, new_sp); | |
1492 | flush_cached_frames (); | |
dac4929a | 1493 | |
199b2450 | 1494 | if (proc_desc && PROC_DESC_IS_DUMMY(proc_desc)) |
bd5635a1 | 1495 | { |
dac4929a SG |
1496 | struct linked_proc_info *pi_ptr, *prev_ptr; |
1497 | ||
1498 | for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL; | |
1499 | pi_ptr != NULL; | |
1500 | prev_ptr = pi_ptr, pi_ptr = pi_ptr->next) | |
1501 | { | |
1502 | if (&pi_ptr->info == proc_desc) | |
1503 | break; | |
1504 | } | |
1505 | ||
1506 | if (pi_ptr == NULL) | |
1507 | error ("Can't locate dummy extra frame info\n"); | |
1508 | ||
1509 | if (prev_ptr != NULL) | |
1510 | prev_ptr->next = pi_ptr->next; | |
1511 | else | |
1512 | linked_proc_desc_table = pi_ptr->next; | |
1513 | ||
1514 | free (pi_ptr); | |
1515 | ||
28444bf3 DP |
1516 | write_register (HI_REGNUM, |
1517 | read_memory_integer (new_sp - 2*MIPS_REGSIZE, MIPS_REGSIZE)); | |
1518 | write_register (LO_REGNUM, | |
1519 | read_memory_integer (new_sp - 3*MIPS_REGSIZE, MIPS_REGSIZE)); | |
e4dbd248 | 1520 | if (mips_fpu != MIPS_FPU_NONE) |
28444bf3 DP |
1521 | write_register (FCRCS_REGNUM, |
1522 | read_memory_integer (new_sp - 4*MIPS_REGSIZE, MIPS_REGSIZE)); | |
bd5635a1 | 1523 | } |
bd5635a1 RP |
1524 | } |
1525 | ||
0f552c5f | 1526 | static void |
a70dc898 | 1527 | mips_print_register (regnum, all) |
bd5635a1 RP |
1528 | int regnum, all; |
1529 | { | |
e4dbd248 | 1530 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; |
bd5635a1 | 1531 | |
48be4c35 JK |
1532 | /* Get the data in raw format. */ |
1533 | if (read_relative_register_raw_bytes (regnum, raw_buffer)) | |
1534 | { | |
1535 | printf_filtered ("%s: [Invalid]", reg_names[regnum]); | |
1536 | return; | |
1537 | } | |
1538 | ||
1539 | /* If an even floating pointer register, also print as double. */ | |
28444bf3 | 1540 | if (regnum >= FP0_REGNUM && regnum < FP0_REGNUM+MIPS_NUMREGS |
e4dbd248 PS |
1541 | && !((regnum-FP0_REGNUM) & 1)) |
1542 | { | |
1543 | char dbuffer[MAX_REGISTER_RAW_SIZE]; | |
48be4c35 | 1544 | |
c81a76b3 MA |
1545 | /* MIPS doubles are stored in a register pair with the least |
1546 | signficant register in the lower-numbered register. */ | |
1547 | read_relative_register_raw_bytes (regnum+1, dbuffer); | |
1548 | read_relative_register_raw_bytes (regnum, dbuffer+MIPS_REGSIZE); | |
1549 | ||
e4dbd248 PS |
1550 | printf_filtered ("(d%d: ", regnum-FP0_REGNUM); |
1551 | val_print (builtin_type_double, dbuffer, 0, | |
1552 | gdb_stdout, 0, 1, 0, Val_pretty_default); | |
1553 | printf_filtered ("); "); | |
1554 | } | |
199b2450 | 1555 | fputs_filtered (reg_names[regnum], gdb_stdout); |
48be4c35 JK |
1556 | |
1557 | /* The problem with printing numeric register names (r26, etc.) is that | |
1558 | the user can't use them on input. Probably the best solution is to | |
1559 | fix it so that either the numeric or the funky (a2, etc.) names | |
1560 | are accepted on input. */ | |
28444bf3 | 1561 | if (regnum < MIPS_NUMREGS) |
48be4c35 JK |
1562 | printf_filtered ("(r%d): ", regnum); |
1563 | else | |
1564 | printf_filtered (": "); | |
bd5635a1 | 1565 | |
48be4c35 | 1566 | /* If virtual format is floating, print it that way. */ |
ac57e5ad | 1567 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
48be4c35 | 1568 | val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, |
199b2450 | 1569 | gdb_stdout, 0, 1, 0, Val_pretty_default); |
48be4c35 JK |
1570 | /* Else print as integer in hex. */ |
1571 | else | |
ac57e5ad SS |
1572 | print_scalar_formatted (raw_buffer, REGISTER_VIRTUAL_TYPE (regnum), |
1573 | 'x', 0, gdb_stdout); | |
bd5635a1 RP |
1574 | } |
1575 | ||
d8b3b00e | 1576 | /* Replacement for generic do_registers_info. */ |
9f9f94aa | 1577 | |
0f552c5f | 1578 | void |
361bf6ee | 1579 | mips_do_registers_info (regnum, fpregs) |
bd5635a1 | 1580 | int regnum; |
361bf6ee | 1581 | int fpregs; |
bd5635a1 | 1582 | { |
9f9f94aa SS |
1583 | if (regnum != -1) |
1584 | { | |
1585 | if (*(reg_names[regnum]) == '\0') | |
1586 | error ("Not a valid register for the current processor type"); | |
1587 | ||
bd5635a1 RP |
1588 | mips_print_register (regnum, 0); |
1589 | printf_filtered ("\n"); | |
9f9f94aa SS |
1590 | } |
1591 | else | |
1592 | { | |
09af5868 | 1593 | int did_newline = 0; |
9f9f94aa SS |
1594 | |
1595 | for (regnum = 0; regnum < NUM_REGS; ) | |
1596 | { | |
1597 | if (((!fpregs) && regnum >= FP0_REGNUM && regnum <= FCRIR_REGNUM) | |
1598 | || *(reg_names[regnum]) == '\0') | |
1599 | { | |
1600 | regnum++; | |
1601 | continue; | |
1602 | } | |
bd5635a1 RP |
1603 | mips_print_register (regnum, 1); |
1604 | regnum++; | |
9f9f94aa SS |
1605 | printf_filtered ("; "); |
1606 | did_newline = 0; | |
1607 | if ((regnum & 3) == 0) | |
1608 | { | |
1609 | printf_filtered ("\n"); | |
1610 | did_newline = 1; | |
1611 | } | |
1612 | } | |
1613 | if (!did_newline) | |
1614 | printf_filtered ("\n"); | |
1615 | } | |
bd5635a1 | 1616 | } |
9f9f94aa | 1617 | |
bd5635a1 RP |
1618 | /* Return number of args passed to a frame. described by FIP. |
1619 | Can return -1, meaning no way to tell. */ | |
1620 | ||
0f552c5f | 1621 | int |
9f9f94aa SS |
1622 | mips_frame_num_args (frame) |
1623 | struct frame_info *frame; | |
bd5635a1 | 1624 | { |
9f9f94aa SS |
1625 | #if 0 /* FIXME Use or lose this! */ |
1626 | struct chain_info_t *p; | |
bd5635a1 | 1627 | |
9f9f94aa SS |
1628 | p = mips_find_cached_frame (FRAME_FP (frame)); |
1629 | if (p->valid) | |
1630 | return p->the_info.numargs; | |
bd5635a1 | 1631 | #endif |
9f9f94aa | 1632 | return -1; |
bd5635a1 | 1633 | } |
96431497 | 1634 | |
427fec5d | 1635 | /* Is this a branch with a delay slot? */ |
9f9f94aa | 1636 | |
b5aff268 JK |
1637 | static int is_delayed PARAMS ((unsigned long)); |
1638 | ||
ee5fb959 JK |
1639 | static int |
1640 | is_delayed (insn) | |
1641 | unsigned long insn; | |
1642 | { | |
1643 | int i; | |
1644 | for (i = 0; i < NUMOPCODES; ++i) | |
1645 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
1646 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
1647 | break; | |
427fec5d JK |
1648 | return (i < NUMOPCODES |
1649 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
1650 | | INSN_COND_BRANCH_DELAY | |
1651 | | INSN_COND_BRANCH_LIKELY))); | |
ee5fb959 | 1652 | } |
b5aff268 JK |
1653 | |
1654 | int | |
1655 | mips_step_skips_delay (pc) | |
1656 | CORE_ADDR pc; | |
1657 | { | |
96431497 | 1658 | char buf[MIPS_INSTLEN]; |
b5aff268 | 1659 | |
f9f8c14b | 1660 | /* There is no branch delay slot on MIPS16. */ |
c1fc0935 | 1661 | if (IS_MIPS16_ADDR (pc)) |
f9f8c14b MA |
1662 | return 0; |
1663 | ||
96431497 | 1664 | if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0) |
b5aff268 JK |
1665 | /* If error reading memory, guess that it is not a delayed branch. */ |
1666 | return 0; | |
96431497 | 1667 | return is_delayed ((unsigned long)extract_unsigned_integer (buf, MIPS_INSTLEN)); |
b5aff268 | 1668 | } |
ee5fb959 | 1669 | |
bd5635a1 | 1670 | |
20fa0902 MA |
1671 | /* Skip the PC past function prologue instructions (32-bit version). |
1672 | This is a helper function for mips_skip_prologue. */ | |
1673 | ||
1674 | static CORE_ADDR | |
1675 | mips32_skip_prologue (pc, lenient) | |
1676 | CORE_ADDR pc; /* starting PC to search from */ | |
ee5fb959 | 1677 | int lenient; |
bd5635a1 | 1678 | { |
28444bf3 | 1679 | t_inst inst; |
20fa0902 | 1680 | CORE_ADDR end_pc; |
0b0d6c3f | 1681 | int seen_sp_adjust = 0; |
ac57e5ad | 1682 | int load_immediate_bytes = 0; |
bd5635a1 | 1683 | |
e157305c PS |
1684 | /* Skip the typical prologue instructions. These are the stack adjustment |
1685 | instruction and the instructions that save registers on the stack | |
1686 | or in the gcc frame. */ | |
20fa0902 | 1687 | for (end_pc = pc + 100; pc < end_pc; pc += MIPS_INSTLEN) |
ee5fb959 | 1688 | { |
b348b9fd | 1689 | unsigned long high_word; |
ee5fb959 | 1690 | |
c81a76b3 | 1691 | inst = mips_fetch_instruction (pc); |
b348b9fd | 1692 | high_word = (inst >> 16) & 0xffff; |
ee5fb959 | 1693 | |
002a422b | 1694 | #if 0 |
ee5fb959 JK |
1695 | if (lenient && is_delayed (inst)) |
1696 | continue; | |
002a422b | 1697 | #endif |
ee5fb959 | 1698 | |
b348b9fd MA |
1699 | if (high_word == 0x27bd /* addiu $sp,$sp,offset */ |
1700 | || high_word == 0x67bd) /* daddiu $sp,$sp,offset */ | |
0b0d6c3f | 1701 | seen_sp_adjust = 1; |
ac57e5ad SS |
1702 | else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */ |
1703 | inst == 0x03a8e823) /* subu $sp,$sp,$t0 */ | |
1704 | seen_sp_adjust = 1; | |
97e091b2 MA |
1705 | else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */ |
1706 | || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */ | |
1707 | && (inst & 0x001F0000)) /* reg != $zero */ | |
1708 | continue; | |
1709 | ||
e157305c PS |
1710 | else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */ |
1711 | continue; | |
1712 | else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000)) | |
1713 | /* sx reg,n($s8) */ | |
1714 | continue; /* reg != $zero */ | |
1d9489c1 JK |
1715 | |
1716 | /* move $s8,$sp. With different versions of gas this will be either | |
20fa0902 MA |
1717 | `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'. |
1718 | Accept any one of these. */ | |
1719 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
0b0d6c3f | 1720 | continue; |
1d9489c1 | 1721 | |
1b71de8e PS |
1722 | else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */ |
1723 | continue; | |
b348b9fd | 1724 | else if (high_word == 0x3c1c) /* lui $gp,n */ |
e03c0cc6 | 1725 | continue; |
b348b9fd | 1726 | else if (high_word == 0x279c) /* addiu $gp,$gp,n */ |
e03c0cc6 ILT |
1727 | continue; |
1728 | else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
1729 | || inst == 0x033ce021) /* addu $gp,$t9,$gp */ | |
1730 | continue; | |
ac57e5ad SS |
1731 | /* The following instructions load $at or $t0 with an immediate |
1732 | value in preparation for a stack adjustment via | |
1733 | subu $sp,$sp,[$at,$t0]. These instructions could also initialize | |
1734 | a local variable, so we accept them only before a stack adjustment | |
1735 | instruction was seen. */ | |
1736 | else if (!seen_sp_adjust) | |
1737 | { | |
b348b9fd MA |
1738 | if (high_word == 0x3c01 || /* lui $at,n */ |
1739 | high_word == 0x3c08) /* lui $t0,n */ | |
ac57e5ad | 1740 | { |
28444bf3 | 1741 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ |
ac57e5ad SS |
1742 | continue; |
1743 | } | |
b348b9fd MA |
1744 | else if (high_word == 0x3421 || /* ori $at,$at,n */ |
1745 | high_word == 0x3508 || /* ori $t0,$t0,n */ | |
1746 | high_word == 0x3401 || /* ori $at,$zero,n */ | |
1747 | high_word == 0x3408) /* ori $t0,$zero,n */ | |
ac57e5ad | 1748 | { |
28444bf3 | 1749 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ |
ac57e5ad SS |
1750 | continue; |
1751 | } | |
1752 | else | |
1753 | break; | |
1754 | } | |
0b0d6c3f | 1755 | else |
ac57e5ad | 1756 | break; |
d747e0af | 1757 | } |
e157305c | 1758 | |
ac57e5ad SS |
1759 | /* In a frameless function, we might have incorrectly |
1760 | skipped some load immediate instructions. Undo the skipping | |
1761 | if the load immediate was not followed by a stack adjustment. */ | |
1762 | if (load_immediate_bytes && !seen_sp_adjust) | |
20fa0902 MA |
1763 | pc -= load_immediate_bytes; |
1764 | return pc; | |
1765 | } | |
1766 | ||
1767 | /* Skip the PC past function prologue instructions (16-bit version). | |
1768 | This is a helper function for mips_skip_prologue. */ | |
1769 | ||
1770 | static CORE_ADDR | |
1771 | mips16_skip_prologue (pc, lenient) | |
1772 | CORE_ADDR pc; /* starting PC to search from */ | |
1773 | int lenient; | |
1774 | { | |
1775 | CORE_ADDR end_pc; | |
c81a76b3 MA |
1776 | int extend_bytes = 0; |
1777 | int prev_extend_bytes; | |
20fa0902 MA |
1778 | |
1779 | /* Table of instructions likely to be found in a function prologue. */ | |
1780 | static struct | |
1781 | { | |
1782 | unsigned short inst; | |
1783 | unsigned short mask; | |
1784 | } table[] = | |
1785 | { | |
1786 | { 0x6300, 0xff00 }, /* addiu $sp,offset */ | |
1787 | { 0xfb00, 0xff00 }, /* daddiu $sp,offset */ | |
1788 | { 0xd000, 0xf800 }, /* sw reg,n($sp) */ | |
1789 | { 0xf900, 0xff00 }, /* sd reg,n($sp) */ | |
1790 | { 0x6200, 0xff00 }, /* sw $ra,n($sp) */ | |
1791 | { 0xfa00, 0xff00 }, /* sd $ra,n($sp) */ | |
1792 | { 0x673d, 0xffff }, /* move $s1,sp */ | |
1793 | { 0xd980, 0xff80 }, /* sw $a0-$a3,n($s1) */ | |
1794 | { 0x6704, 0xff1c }, /* move reg,$a0-$a3 */ | |
1795 | { 0xe809, 0xf81f }, /* entry pseudo-op */ | |
32dab603 | 1796 | { 0x0100, 0xff00 }, /* addiu $s1,$sp,n */ |
20fa0902 MA |
1797 | { 0, 0 } /* end of table marker */ |
1798 | }; | |
1799 | ||
1800 | /* Skip the typical prologue instructions. These are the stack adjustment | |
1801 | instruction and the instructions that save registers on the stack | |
1802 | or in the gcc frame. */ | |
1803 | for (end_pc = pc + 100; pc < end_pc; pc += MIPS16_INSTLEN) | |
1804 | { | |
20fa0902 | 1805 | unsigned short inst; |
20fa0902 MA |
1806 | int i; |
1807 | ||
c81a76b3 | 1808 | inst = mips_fetch_instruction (pc); |
20fa0902 MA |
1809 | |
1810 | /* Normally we ignore an extend instruction. However, if it is | |
1811 | not followed by a valid prologue instruction, we must adjust | |
1812 | the pc back over the extend so that it won't be considered | |
1813 | part of the prologue. */ | |
1814 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
1815 | { | |
1816 | extend_bytes = MIPS16_INSTLEN; | |
1817 | continue; | |
1818 | } | |
1819 | prev_extend_bytes = extend_bytes; | |
1820 | extend_bytes = 0; | |
1821 | ||
1822 | /* Check for other valid prologue instructions besides extend. */ | |
1823 | for (i = 0; table[i].mask != 0; i++) | |
1824 | if ((inst & table[i].mask) == table[i].inst) /* found, get out */ | |
1825 | break; | |
1826 | if (table[i].mask != 0) /* it was in table? */ | |
32dab603 | 1827 | continue; /* ignore it */ |
20fa0902 MA |
1828 | else /* non-prologue */ |
1829 | { | |
1830 | /* Return the current pc, adjusted backwards by 2 if | |
1831 | the previous instruction was an extend. */ | |
1832 | return pc - prev_extend_bytes; | |
1833 | } | |
1834 | } | |
32dab603 | 1835 | return pc; |
20fa0902 MA |
1836 | } |
1837 | ||
1838 | /* To skip prologues, I use this predicate. Returns either PC itself | |
1839 | if the code at PC does not look like a function prologue; otherwise | |
1840 | returns an address that (if we're lucky) follows the prologue. If | |
1841 | LENIENT, then we must skip everything which is involved in setting | |
1842 | up the frame (it's OK to skip more, just so long as we don't skip | |
1843 | anything which might clobber the registers which are being saved. | |
1844 | We must skip more in the case where part of the prologue is in the | |
1845 | delay slot of a non-prologue instruction). */ | |
1846 | ||
1847 | CORE_ADDR | |
1848 | mips_skip_prologue (pc, lenient) | |
1849 | CORE_ADDR pc; | |
1850 | int lenient; | |
1851 | { | |
1852 | /* See if we can determine the end of the prologue via the symbol table. | |
1853 | If so, then return either PC, or the PC after the prologue, whichever | |
1854 | is greater. */ | |
1855 | ||
1856 | CORE_ADDR post_prologue_pc = after_prologue (pc, NULL); | |
1857 | ||
1858 | if (post_prologue_pc != 0) | |
1859 | return max (pc, post_prologue_pc); | |
1860 | ||
1861 | /* Can't determine prologue from the symbol table, need to examine | |
1862 | instructions. */ | |
1863 | ||
c1fc0935 | 1864 | if (IS_MIPS16_ADDR (pc)) |
20fa0902 MA |
1865 | return mips16_skip_prologue (pc, lenient); |
1866 | else | |
1867 | return mips32_skip_prologue (pc, lenient); | |
bd5635a1 | 1868 | } |
c2a0f1cb | 1869 | |
002a422b | 1870 | #if 0 |
20fa0902 | 1871 | /* The lenient prologue stuff should be superseded by the code in |
002a422b JK |
1872 | init_extra_frame_info which looks to see whether the stores mentioned |
1873 | in the proc_desc have actually taken place. */ | |
1874 | ||
ee5fb959 JK |
1875 | /* Is address PC in the prologue (loosely defined) for function at |
1876 | STARTADDR? */ | |
1877 | ||
1878 | static int | |
1879 | mips_in_lenient_prologue (startaddr, pc) | |
1880 | CORE_ADDR startaddr; | |
1881 | CORE_ADDR pc; | |
1882 | { | |
1883 | CORE_ADDR end_prologue = mips_skip_prologue (startaddr, 1); | |
1884 | return pc >= startaddr && pc < end_prologue; | |
1885 | } | |
002a422b | 1886 | #endif |
ee5fb959 | 1887 | |
ac8cf67d PS |
1888 | /* Given a return value in `regbuf' with a type `valtype', |
1889 | extract and copy its value into `valbuf'. */ | |
1890 | void | |
1891 | mips_extract_return_value (valtype, regbuf, valbuf) | |
1892 | struct type *valtype; | |
1893 | char regbuf[REGISTER_BYTES]; | |
1894 | char *valbuf; | |
1895 | { | |
1896 | int regnum; | |
92a6d600 | 1897 | int offset = 0; |
c81a76b3 | 1898 | int len = TYPE_LENGTH (valtype); |
ac8cf67d | 1899 | |
e4dbd248 PS |
1900 | regnum = 2; |
1901 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT | |
1902 | && (mips_fpu == MIPS_FPU_DOUBLE | |
c81a76b3 MA |
1903 | || (mips_fpu == MIPS_FPU_SINGLE && len <= MIPS_REGSIZE))) |
1904 | { | |
1905 | regnum = FP0_REGNUM; | |
1906 | ||
1907 | /* If this is a double, the odd-numbered register (FP1) contains the | |
1908 | high word of the result. Copy that to the buffer before | |
1909 | copying the low word in FP0. */ | |
1910 | if (len > MIPS_REGSIZE) | |
1911 | { | |
1912 | memcpy (valbuf, regbuf + REGISTER_BYTE (regnum+1), MIPS_REGSIZE); | |
1913 | len -= MIPS_REGSIZE; | |
1914 | valbuf += MIPS_REGSIZE; | |
1915 | } | |
1916 | } | |
ac8cf67d | 1917 | |
92a6d600 PS |
1918 | if (TARGET_BYTE_ORDER == BIG_ENDIAN |
1919 | && TYPE_CODE (valtype) != TYPE_CODE_FLT | |
c81a76b3 MA |
1920 | && len < REGISTER_RAW_SIZE (regnum)) |
1921 | offset = REGISTER_RAW_SIZE (regnum) - len; | |
1922 | ||
1923 | memcpy (valbuf, regbuf + REGISTER_BYTE (regnum) + offset, len); | |
ac8cf67d PS |
1924 | } |
1925 | ||
1926 | /* Given a return value in `regbuf' with a type `valtype', | |
1927 | write it's value into the appropriate register. */ | |
1928 | void | |
1929 | mips_store_return_value (valtype, valbuf) | |
1930 | struct type *valtype; | |
1931 | char *valbuf; | |
1932 | { | |
1933 | int regnum; | |
1934 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; | |
1935 | ||
e4dbd248 PS |
1936 | regnum = 2; |
1937 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT | |
1938 | && (mips_fpu == MIPS_FPU_DOUBLE | |
28444bf3 | 1939 | || (mips_fpu == MIPS_FPU_SINGLE && TYPE_LENGTH (valtype) <= 4))) /* FIXME!! */ |
e4dbd248 PS |
1940 | regnum = FP0_REGNUM; |
1941 | ||
ac8cf67d PS |
1942 | memcpy(raw_buffer, valbuf, TYPE_LENGTH (valtype)); |
1943 | ||
1944 | #ifdef REGISTER_CONVERT_FROM_TYPE | |
1945 | REGISTER_CONVERT_FROM_TYPE(regnum, valtype, raw_buffer); | |
1946 | #endif | |
1947 | ||
1948 | write_register_bytes(REGISTER_BYTE (regnum), raw_buffer, TYPE_LENGTH (valtype)); | |
1949 | } | |
1950 | ||
e03c0cc6 ILT |
1951 | /* Exported procedure: Is PC in the signal trampoline code */ |
1952 | ||
1953 | int | |
1954 | in_sigtramp (pc, ignore) | |
1955 | CORE_ADDR pc; | |
1956 | char *ignore; /* function name */ | |
1957 | { | |
1958 | if (sigtramp_address == 0) | |
1959 | fixup_sigtramp (); | |
1960 | return (pc >= sigtramp_address && pc < sigtramp_end); | |
1961 | } | |
1962 | ||
e4dbd248 PS |
1963 | /* Command to set FPU type. mips_fpu_string will have been set to the |
1964 | user's argument. Set mips_fpu based on mips_fpu_string, and then | |
1965 | canonicalize mips_fpu_string. */ | |
1966 | ||
1967 | /*ARGSUSED*/ | |
1968 | static void | |
1969 | mips_set_fpu_command (args, from_tty, c) | |
1970 | char *args; | |
1971 | int from_tty; | |
1972 | struct cmd_list_element *c; | |
1973 | { | |
1974 | char *err = NULL; | |
1975 | ||
1976 | if (mips_fpu_string == NULL || *mips_fpu_string == '\0') | |
1977 | mips_fpu = MIPS_FPU_DOUBLE; | |
1978 | else if (strcasecmp (mips_fpu_string, "double") == 0 | |
1979 | || strcasecmp (mips_fpu_string, "on") == 0 | |
1980 | || strcasecmp (mips_fpu_string, "1") == 0 | |
1981 | || strcasecmp (mips_fpu_string, "yes") == 0) | |
1982 | mips_fpu = MIPS_FPU_DOUBLE; | |
1983 | else if (strcasecmp (mips_fpu_string, "none") == 0 | |
1984 | || strcasecmp (mips_fpu_string, "off") == 0 | |
1985 | || strcasecmp (mips_fpu_string, "0") == 0 | |
1986 | || strcasecmp (mips_fpu_string, "no") == 0) | |
1987 | mips_fpu = MIPS_FPU_NONE; | |
1988 | else if (strcasecmp (mips_fpu_string, "single") == 0) | |
1989 | mips_fpu = MIPS_FPU_SINGLE; | |
1990 | else | |
1991 | err = strsave (mips_fpu_string); | |
1992 | ||
1993 | if (mips_fpu_string != NULL) | |
1994 | free (mips_fpu_string); | |
1995 | ||
1996 | switch (mips_fpu) | |
1997 | { | |
1998 | case MIPS_FPU_DOUBLE: | |
1999 | mips_fpu_string = strsave ("double"); | |
2000 | break; | |
2001 | case MIPS_FPU_SINGLE: | |
2002 | mips_fpu_string = strsave ("single"); | |
2003 | break; | |
2004 | case MIPS_FPU_NONE: | |
2005 | mips_fpu_string = strsave ("none"); | |
2006 | break; | |
2007 | } | |
2008 | ||
2009 | if (err != NULL) | |
2010 | { | |
2011 | struct cleanup *cleanups = make_cleanup (free, err); | |
2012 | error ("Unknown FPU type `%s'. Use `double', `none', or `single'.", | |
2013 | err); | |
2014 | do_cleanups (cleanups); | |
2015 | } | |
2016 | } | |
2017 | ||
2018 | static void | |
2019 | mips_show_fpu_command (args, from_tty, c) | |
2020 | char *args; | |
2021 | int from_tty; | |
2022 | struct cmd_list_element *c; | |
2023 | { | |
2024 | } | |
2025 | ||
9f9f94aa SS |
2026 | /* Command to set the processor type. */ |
2027 | ||
2028 | void | |
2029 | mips_set_processor_type_command (args, from_tty) | |
2030 | char *args; | |
2031 | int from_tty; | |
2032 | { | |
2033 | int i; | |
2034 | ||
2035 | if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0') | |
2036 | { | |
2037 | printf_unfiltered ("The known MIPS processor types are as follows:\n\n"); | |
2038 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
2039 | printf_unfiltered ("%s\n", mips_processor_type_table[i].name); | |
2040 | ||
2041 | /* Restore the value. */ | |
2042 | tmp_mips_processor_type = strsave (mips_processor_type); | |
2043 | ||
2044 | return; | |
2045 | } | |
2046 | ||
2047 | if (!mips_set_processor_type (tmp_mips_processor_type)) | |
2048 | { | |
2049 | error ("Unknown processor type `%s'.", tmp_mips_processor_type); | |
2050 | /* Restore its value. */ | |
2051 | tmp_mips_processor_type = strsave (mips_processor_type); | |
2052 | } | |
2053 | } | |
2054 | ||
2055 | static void | |
2056 | mips_show_processor_type_command (args, from_tty) | |
2057 | char *args; | |
2058 | int from_tty; | |
2059 | { | |
2060 | } | |
2061 | ||
2062 | /* Modify the actual processor type. */ | |
2063 | ||
2064 | int | |
2065 | mips_set_processor_type (str) | |
2066 | char *str; | |
2067 | { | |
2068 | int i, j; | |
2069 | ||
2070 | if (str == NULL) | |
1d9489c1 | 2071 | return 0; |
9f9f94aa SS |
2072 | |
2073 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
2074 | { | |
2075 | if (strcasecmp (str, mips_processor_type_table[i].name) == 0) | |
2076 | { | |
2077 | mips_processor_type = str; | |
2078 | ||
2079 | for (j = 0; j < NUM_REGS; ++j) | |
2080 | reg_names[j] = mips_processor_type_table[i].regnames[j]; | |
2081 | ||
2082 | return 1; | |
2083 | ||
2084 | /* FIXME tweak fpu flag too */ | |
2085 | } | |
2086 | } | |
2087 | ||
2088 | return 0; | |
2089 | } | |
2090 | ||
2091 | /* Attempt to identify the particular processor model by reading the | |
2092 | processor id. */ | |
2093 | ||
2094 | char * | |
2095 | mips_read_processor_type () | |
2096 | { | |
28444bf3 | 2097 | CORE_ADDR prid; |
9f9f94aa SS |
2098 | |
2099 | prid = read_register (PRID_REGNUM); | |
2100 | ||
80e0e92a | 2101 | if ((prid & ~0xf) == 0x700) |
9f9f94aa SS |
2102 | return savestring ("r3041", strlen("r3041")); |
2103 | ||
2104 | return NULL; | |
2105 | } | |
427fec5d JK |
2106 | |
2107 | /* Just like reinit_frame_cache, but with the right arguments to be | |
2108 | callable as an sfunc. */ | |
9f9f94aa | 2109 | |
427fec5d JK |
2110 | static void |
2111 | reinit_frame_cache_sfunc (args, from_tty, c) | |
2112 | char *args; | |
2113 | int from_tty; | |
2114 | struct cmd_list_element *c; | |
2115 | { | |
2116 | reinit_frame_cache (); | |
2117 | } | |
c2a0f1cb | 2118 | |
28444bf3 | 2119 | static int |
18b46e7c SS |
2120 | gdb_print_insn_mips (memaddr, info) |
2121 | bfd_vma memaddr; | |
2122 | disassemble_info *info; | |
2123 | { | |
f9f8c14b MA |
2124 | mips_extra_func_info_t proc_desc; |
2125 | ||
2126 | /* Search for the function containing this address. Set the low bit | |
2127 | of the address when searching, in case we were given an even address | |
2128 | that is the start of a 16-bit function. If we didn't do this, | |
2129 | the search would fail because the symbol table says the function | |
2130 | starts at an odd address, i.e. 1 byte past the given address. */ | |
c1fc0935 MA |
2131 | memaddr = ADDR_BITS_REMOVE (memaddr); |
2132 | proc_desc = non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr), NULL); | |
f9f8c14b MA |
2133 | |
2134 | /* Make an attempt to determine if this is a 16-bit function. If | |
2135 | the procedure descriptor exists and the address therein is odd, | |
2136 | it's definitely a 16-bit function. Otherwise, we have to just | |
2137 | guess that if the address passed in is odd, it's 16-bits. */ | |
2138 | if (proc_desc) | |
c1fc0935 | 2139 | info->mach = IS_MIPS16_ADDR (PROC_LOW_ADDR (proc_desc)) ? 16 : 0; |
f9f8c14b | 2140 | else |
c1fc0935 | 2141 | info->mach = IS_MIPS16_ADDR (memaddr) ? 16 : 0; |
f9f8c14b | 2142 | |
c1fc0935 | 2143 | /* Round down the instruction address to the appropriate boundary. */ |
f9f8c14b MA |
2144 | memaddr &= (info->mach == 16 ? ~1 : ~3); |
2145 | ||
2146 | /* Call the appropriate disassembler based on the target endian-ness. */ | |
18b46e7c SS |
2147 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
2148 | return print_insn_big_mips (memaddr, info); | |
2149 | else | |
2150 | return print_insn_little_mips (memaddr, info); | |
2151 | } | |
2152 | ||
f9f8c14b MA |
2153 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program |
2154 | counter value to determine whether a 16- or 32-bit breakpoint should be | |
2155 | used. It returns a pointer to a string of bytes that encode a breakpoint | |
2156 | instruction, stores the length of the string to *lenptr, and adjusts pc | |
2157 | (if necessary) to point to the actual memory location where the | |
2158 | breakpoint should be inserted. */ | |
2159 | ||
2160 | unsigned char *mips_breakpoint_from_pc (pcptr, lenptr) | |
2161 | CORE_ADDR *pcptr; | |
2162 | int *lenptr; | |
2163 | { | |
2164 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
2165 | { | |
c1fc0935 | 2166 | if (IS_MIPS16_ADDR (*pcptr)) |
f9f8c14b MA |
2167 | { |
2168 | static char mips16_big_breakpoint[] = MIPS16_BIG_BREAKPOINT; | |
c1fc0935 | 2169 | *pcptr = UNMAKE_MIPS16_ADDR (*pcptr); |
f9f8c14b MA |
2170 | *lenptr = sizeof(mips16_big_breakpoint); |
2171 | return mips16_big_breakpoint; | |
2172 | } | |
2173 | else | |
2174 | { | |
2175 | static char big_breakpoint[] = BIG_BREAKPOINT; | |
2176 | *lenptr = sizeof(big_breakpoint); | |
2177 | return big_breakpoint; | |
2178 | } | |
2179 | } | |
2180 | else | |
2181 | { | |
c1fc0935 | 2182 | if (IS_MIPS16_ADDR (*pcptr)) |
f9f8c14b MA |
2183 | { |
2184 | static char mips16_little_breakpoint[] = MIPS16_LITTLE_BREAKPOINT; | |
c1fc0935 | 2185 | *pcptr = UNMAKE_MIPS16_ADDR (*pcptr); |
f9f8c14b MA |
2186 | *lenptr = sizeof(mips16_little_breakpoint); |
2187 | return mips16_little_breakpoint; | |
2188 | } | |
2189 | else | |
2190 | { | |
2191 | static char little_breakpoint[] = LITTLE_BREAKPOINT; | |
2192 | *lenptr = sizeof(little_breakpoint); | |
2193 | return little_breakpoint; | |
2194 | } | |
2195 | } | |
2196 | } | |
2197 | ||
2198 | /* Test whether the PC points to the return instruction at the | |
2199 | end of a function. This implements the ABOUT_TO_RETURN macro. */ | |
2200 | ||
2201 | int | |
2202 | mips_about_to_return (pc) | |
2203 | CORE_ADDR pc; | |
2204 | { | |
c1fc0935 | 2205 | if (IS_MIPS16_ADDR (pc)) |
f9f8c14b MA |
2206 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler |
2207 | generates a "jr $ra"; other times it generates code to load | |
2208 | the return address from the stack to an accessible register (such | |
2209 | as $a3), then a "jr" using that register. This second case | |
2210 | is almost impossible to distinguish from an indirect jump | |
2211 | used for switch statements, so we don't even try. */ | |
c81a76b3 | 2212 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ |
f9f8c14b | 2213 | else |
c81a76b3 | 2214 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ |
f9f8c14b MA |
2215 | } |
2216 | ||
2217 | ||
c2a0f1cb ILT |
2218 | void |
2219 | _initialize_mips_tdep () | |
2220 | { | |
427fec5d JK |
2221 | struct cmd_list_element *c; |
2222 | ||
18b46e7c SS |
2223 | tm_print_insn = gdb_print_insn_mips; |
2224 | ||
427fec5d JK |
2225 | /* Let the user turn off floating point and set the fence post for |
2226 | heuristic_proc_start. */ | |
2227 | ||
e4dbd248 PS |
2228 | c = add_set_cmd ("mipsfpu", class_support, var_string_noescape, |
2229 | (char *) &mips_fpu_string, | |
2230 | "Set use of floating point coprocessor.\n\ | |
2231 | Set to `none' to avoid using floating point instructions when calling\n\ | |
2232 | functions or dealing with return values. Set to `single' to use only\n\ | |
2233 | single precision floating point as on the R4650. Set to `double' for\n\ | |
2234 | normal floating point support.", | |
2235 | &setlist); | |
2236 | c->function.sfunc = mips_set_fpu_command; | |
2237 | c = add_show_from_set (c, &showlist); | |
2238 | c->function.sfunc = mips_show_fpu_command; | |
2239 | ||
2240 | mips_fpu = MIPS_FPU_DOUBLE; | |
2241 | mips_fpu_string = strsave ("double"); | |
3127785a | 2242 | |
9f9f94aa SS |
2243 | c = add_set_cmd ("processor", class_support, var_string_noescape, |
2244 | (char *) &tmp_mips_processor_type, | |
2245 | "Set the type of MIPS processor in use.\n\ | |
2246 | Set this to be able to access processor-type-specific registers.\n\ | |
2247 | ", | |
2248 | &setlist); | |
2249 | c->function.cfunc = mips_set_processor_type_command; | |
2250 | c = add_show_from_set (c, &showlist); | |
2251 | c->function.cfunc = mips_show_processor_type_command; | |
2252 | ||
2253 | tmp_mips_processor_type = strsave (DEFAULT_MIPS_TYPE); | |
2254 | mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE), 0); | |
2255 | ||
bdef72d2 JK |
2256 | /* We really would like to have both "0" and "unlimited" work, but |
2257 | command.c doesn't deal with that. So make it a var_zinteger | |
2258 | because the user can always use "999999" or some such for unlimited. */ | |
2259 | c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger, | |
427fec5d JK |
2260 | (char *) &heuristic_fence_post, |
2261 | "\ | |
23d35572 JK |
2262 | Set the distance searched for the start of a function.\n\ |
2263 | If you are debugging a stripped executable, GDB needs to search through the\n\ | |
2264 | program for the start of a function. This command sets the distance of the\n\ | |
2265 | search. The only need to set it is when debugging a stripped executable.", | |
427fec5d JK |
2266 | &setlist); |
2267 | /* We need to throw away the frame cache when we set this, since it | |
2268 | might change our ability to get backtraces. */ | |
2269 | c->function.sfunc = reinit_frame_cache_sfunc; | |
2270 | add_show_from_set (c, &showlist); | |
c2a0f1cb | 2271 | } |