Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
6aba47ca | 3 | Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
9b254dd1 | 4 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 |
47a35522 | 5 | Free Software Foundation, Inc. |
bf64bfd6 | 6 | |
c906108c SS |
7 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
8 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
9 | ||
c5aa993b | 10 | This file is part of GDB. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is free software; you can redistribute it and/or modify |
13 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 14 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 15 | (at your option) any later version. |
c906108c | 16 | |
c5aa993b JM |
17 | This program is distributed in the hope that it will be useful, |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
c906108c | 21 | |
c5aa993b | 22 | You should have received a copy of the GNU General Public License |
a9762ec7 | 23 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
24 | |
25 | #include "defs.h" | |
26 | #include "gdb_string.h" | |
5e2e9765 | 27 | #include "gdb_assert.h" |
c906108c SS |
28 | #include "frame.h" |
29 | #include "inferior.h" | |
30 | #include "symtab.h" | |
31 | #include "value.h" | |
32 | #include "gdbcmd.h" | |
33 | #include "language.h" | |
34 | #include "gdbcore.h" | |
35 | #include "symfile.h" | |
36 | #include "objfiles.h" | |
37 | #include "gdbtypes.h" | |
38 | #include "target.h" | |
28d069e6 | 39 | #include "arch-utils.h" |
4e052eda | 40 | #include "regcache.h" |
70f80edf | 41 | #include "osabi.h" |
d1973055 | 42 | #include "mips-tdep.h" |
fe898f56 | 43 | #include "block.h" |
a4b8ebc8 | 44 | #include "reggroups.h" |
c906108c | 45 | #include "opcode/mips.h" |
c2d11a7d JM |
46 | #include "elf/mips.h" |
47 | #include "elf-bfd.h" | |
2475bac3 | 48 | #include "symcat.h" |
a4b8ebc8 | 49 | #include "sim-regno.h" |
a89aa300 | 50 | #include "dis-asm.h" |
edfae063 AC |
51 | #include "frame-unwind.h" |
52 | #include "frame-base.h" | |
53 | #include "trad-frame.h" | |
7d9b040b | 54 | #include "infcall.h" |
fed7ba43 | 55 | #include "floatformat.h" |
29709017 DJ |
56 | #include "remote.h" |
57 | #include "target-descriptions.h" | |
2bd0c3d7 | 58 | #include "dwarf2-frame.h" |
f8b73d13 | 59 | #include "user-regs.h" |
c906108c | 60 | |
8d5f9dcb DJ |
61 | static const struct objfile_data *mips_pdr_data; |
62 | ||
5bbcb741 | 63 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 64 | |
24e05951 | 65 | /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ |
dd824b04 DJ |
66 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ |
67 | #define ST0_FR (1 << 26) | |
68 | ||
b0069a17 AC |
69 | /* The sizes of floating point registers. */ |
70 | ||
71 | enum | |
72 | { | |
73 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
74 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
75 | }; | |
76 | ||
1a69e1e4 DJ |
77 | enum |
78 | { | |
79 | MIPS32_REGSIZE = 4, | |
80 | MIPS64_REGSIZE = 8 | |
81 | }; | |
0dadbba0 | 82 | |
2e4ebe70 DJ |
83 | static const char *mips_abi_string; |
84 | ||
85 | static const char *mips_abi_strings[] = { | |
86 | "auto", | |
87 | "n32", | |
88 | "o32", | |
28d169de | 89 | "n64", |
2e4ebe70 DJ |
90 | "o64", |
91 | "eabi32", | |
92 | "eabi64", | |
93 | NULL | |
94 | }; | |
95 | ||
f8b73d13 DJ |
96 | /* The standard register names, and all the valid aliases for them. */ |
97 | struct register_alias | |
98 | { | |
99 | const char *name; | |
100 | int regnum; | |
101 | }; | |
102 | ||
103 | /* Aliases for o32 and most other ABIs. */ | |
104 | const struct register_alias mips_o32_aliases[] = { | |
105 | { "ta0", 12 }, | |
106 | { "ta1", 13 }, | |
107 | { "ta2", 14 }, | |
108 | { "ta3", 15 } | |
109 | }; | |
110 | ||
111 | /* Aliases for n32 and n64. */ | |
112 | const struct register_alias mips_n32_n64_aliases[] = { | |
113 | { "ta0", 8 }, | |
114 | { "ta1", 9 }, | |
115 | { "ta2", 10 }, | |
116 | { "ta3", 11 } | |
117 | }; | |
118 | ||
119 | /* Aliases for ABI-independent registers. */ | |
120 | const struct register_alias mips_register_aliases[] = { | |
121 | /* The architecture manuals specify these ABI-independent names for | |
122 | the GPRs. */ | |
123 | #define R(n) { "r" #n, n } | |
124 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
125 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
126 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
127 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
128 | #undef R | |
129 | ||
130 | /* k0 and k1 are sometimes called these instead (for "kernel | |
131 | temp"). */ | |
132 | { "kt0", 26 }, | |
133 | { "kt1", 27 }, | |
134 | ||
135 | /* This is the traditional GDB name for the CP0 status register. */ | |
136 | { "sr", MIPS_PS_REGNUM }, | |
137 | ||
138 | /* This is the traditional GDB name for the CP0 BadVAddr register. */ | |
139 | { "bad", MIPS_EMBED_BADVADDR_REGNUM }, | |
140 | ||
141 | /* This is the traditional GDB name for the FCSR. */ | |
142 | { "fsr", MIPS_EMBED_FP0_REGNUM + 32 } | |
143 | }; | |
144 | ||
c906108c SS |
145 | #ifndef MIPS_DEFAULT_FPU_TYPE |
146 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
147 | #endif | |
148 | static int mips_fpu_type_auto = 1; | |
149 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 150 | |
9ace0497 | 151 | static int mips_debug = 0; |
7a292a7a | 152 | |
29709017 DJ |
153 | /* Properties (for struct target_desc) describing the g/G packet |
154 | layout. */ | |
155 | #define PROPERTY_GP32 "internal: transfers-32bit-registers" | |
156 | #define PROPERTY_GP64 "internal: transfers-64bit-registers" | |
157 | ||
4eb0ad19 DJ |
158 | struct target_desc *mips_tdesc_gp32; |
159 | struct target_desc *mips_tdesc_gp64; | |
160 | ||
56cea623 AC |
161 | const struct mips_regnum * |
162 | mips_regnum (struct gdbarch *gdbarch) | |
163 | { | |
164 | return gdbarch_tdep (gdbarch)->regnum; | |
165 | } | |
166 | ||
167 | static int | |
168 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
169 | { | |
170 | return mips_regnum (gdbarch)->fp0 + 12; | |
171 | } | |
172 | ||
74ed0bb4 MD |
173 | #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \ |
174 | == MIPS_ABI_EABI32 \ | |
175 | || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64) | |
c2d11a7d | 176 | |
74ed0bb4 | 177 | #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 178 | |
74ed0bb4 | 179 | #define MIPS_LAST_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 180 | |
74ed0bb4 | 181 | #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type) |
c2d11a7d | 182 | |
95404a3e AC |
183 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
184 | functions to test, set, or clear bit 0 of addresses. */ | |
185 | ||
186 | static CORE_ADDR | |
187 | is_mips16_addr (CORE_ADDR addr) | |
188 | { | |
189 | return ((addr) & 1); | |
190 | } | |
191 | ||
95404a3e AC |
192 | static CORE_ADDR |
193 | unmake_mips16_addr (CORE_ADDR addr) | |
194 | { | |
5b652102 | 195 | return ((addr) & ~(CORE_ADDR) 1); |
95404a3e AC |
196 | } |
197 | ||
d1973055 KB |
198 | /* Return the MIPS ABI associated with GDBARCH. */ |
199 | enum mips_abi | |
200 | mips_abi (struct gdbarch *gdbarch) | |
201 | { | |
202 | return gdbarch_tdep (gdbarch)->mips_abi; | |
203 | } | |
204 | ||
4246e332 | 205 | int |
1b13c4f6 | 206 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 | 207 | { |
29709017 DJ |
208 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
209 | ||
210 | /* If we know how big the registers are, use that size. */ | |
211 | if (tdep->register_size_valid_p) | |
212 | return tdep->register_size; | |
213 | ||
214 | /* Fall back to the previous behavior. */ | |
4246e332 AC |
215 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word |
216 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
217 | } | |
218 | ||
480d3dd2 AC |
219 | /* Return the currently configured (or set) saved register size. */ |
220 | ||
e6bc2e8a | 221 | unsigned int |
13326b4e | 222 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 223 | { |
1a69e1e4 DJ |
224 | switch (mips_abi (gdbarch)) |
225 | { | |
226 | case MIPS_ABI_EABI32: | |
227 | case MIPS_ABI_O32: | |
228 | return 4; | |
229 | case MIPS_ABI_N32: | |
230 | case MIPS_ABI_N64: | |
231 | case MIPS_ABI_O64: | |
232 | case MIPS_ABI_EABI64: | |
233 | return 8; | |
234 | case MIPS_ABI_UNKNOWN: | |
235 | case MIPS_ABI_LAST: | |
236 | default: | |
237 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
238 | } | |
d929b26f AC |
239 | } |
240 | ||
71b8ef93 | 241 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 242 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 243 | "info" field is used for this purpose. |
5a89d8aa | 244 | |
95f1da47 | 245 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special", |
5a89d8aa MS |
246 | i.e. refers to a 16-bit function, and sets a "special" bit in a |
247 | minimal symbol to mark it as a 16-bit function | |
248 | ||
f594e5e9 | 249 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 250 | |
5a89d8aa | 251 | static void |
6d82d43b AC |
252 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
253 | { | |
254 | if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16) | |
255 | { | |
256 | MSYMBOL_INFO (msym) = (char *) | |
257 | (((long) MSYMBOL_INFO (msym)) | 0x80000000); | |
258 | SYMBOL_VALUE_ADDRESS (msym) |= 1; | |
259 | } | |
5a89d8aa MS |
260 | } |
261 | ||
71b8ef93 MS |
262 | static int |
263 | msymbol_is_special (struct minimal_symbol *msym) | |
264 | { | |
265 | return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0); | |
266 | } | |
267 | ||
88658117 AC |
268 | /* XFER a value from the big/little/left end of the register. |
269 | Depending on the size of the value it might occupy the entire | |
270 | register or just part of it. Make an allowance for this, aligning | |
271 | things accordingly. */ | |
272 | ||
273 | static void | |
ba32f989 DJ |
274 | mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache, |
275 | int reg_num, int length, | |
870cd05e MK |
276 | enum bfd_endian endian, gdb_byte *in, |
277 | const gdb_byte *out, int buf_offset) | |
88658117 | 278 | { |
88658117 | 279 | int reg_offset = 0; |
72a155b4 UW |
280 | |
281 | gdb_assert (reg_num >= gdbarch_num_regs (gdbarch)); | |
cb1d2653 AC |
282 | /* Need to transfer the left or right part of the register, based on |
283 | the targets byte order. */ | |
88658117 AC |
284 | switch (endian) |
285 | { | |
286 | case BFD_ENDIAN_BIG: | |
72a155b4 | 287 | reg_offset = register_size (gdbarch, reg_num) - length; |
88658117 AC |
288 | break; |
289 | case BFD_ENDIAN_LITTLE: | |
290 | reg_offset = 0; | |
291 | break; | |
6d82d43b | 292 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
293 | reg_offset = 0; |
294 | break; | |
295 | default: | |
e2e0b3e5 | 296 | internal_error (__FILE__, __LINE__, _("bad switch")); |
88658117 AC |
297 | } |
298 | if (mips_debug) | |
cb1d2653 AC |
299 | fprintf_unfiltered (gdb_stderr, |
300 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
301 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
302 | if (mips_debug && out != NULL) |
303 | { | |
304 | int i; | |
cb1d2653 | 305 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 306 | for (i = 0; i < length; i++) |
cb1d2653 | 307 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
308 | } |
309 | if (in != NULL) | |
6d82d43b AC |
310 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
311 | in + buf_offset); | |
88658117 | 312 | if (out != NULL) |
6d82d43b AC |
313 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
314 | out + buf_offset); | |
88658117 AC |
315 | if (mips_debug && in != NULL) |
316 | { | |
317 | int i; | |
cb1d2653 | 318 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 319 | for (i = 0; i < length; i++) |
cb1d2653 | 320 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
321 | } |
322 | if (mips_debug) | |
323 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
324 | } | |
325 | ||
dd824b04 DJ |
326 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
327 | compatiblity mode. A return value of 1 means that we have | |
328 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
329 | ||
330 | static int | |
9c9acae0 | 331 | mips2_fp_compat (struct frame_info *frame) |
dd824b04 | 332 | { |
72a155b4 | 333 | struct gdbarch *gdbarch = get_frame_arch (frame); |
dd824b04 DJ |
334 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not |
335 | meaningful. */ | |
72a155b4 | 336 | if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4) |
dd824b04 DJ |
337 | return 0; |
338 | ||
339 | #if 0 | |
340 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
341 | in all the places we deal with FP registers. PR gdb/413. */ | |
342 | /* Otherwise check the FR bit in the status register - it controls | |
343 | the FP compatiblity mode. If it is clear we are in compatibility | |
344 | mode. */ | |
9c9acae0 | 345 | if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0) |
dd824b04 DJ |
346 | return 1; |
347 | #endif | |
361d1df0 | 348 | |
dd824b04 DJ |
349 | return 0; |
350 | } | |
351 | ||
7a292a7a | 352 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 353 | |
74ed0bb4 | 354 | static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR); |
c906108c | 355 | |
a14ed312 | 356 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 357 | |
67b2c998 DJ |
358 | static struct type *mips_float_register_type (void); |
359 | static struct type *mips_double_register_type (void); | |
360 | ||
acdb74a0 AC |
361 | /* The list of available "set mips " and "show mips " commands */ |
362 | ||
363 | static struct cmd_list_element *setmipscmdlist = NULL; | |
364 | static struct cmd_list_element *showmipscmdlist = NULL; | |
365 | ||
5e2e9765 KB |
366 | /* Integer registers 0 thru 31 are handled explicitly by |
367 | mips_register_name(). Processor specific registers 32 and above | |
8a9fc081 | 368 | are listed in the following tables. */ |
691c0433 | 369 | |
6d82d43b AC |
370 | enum |
371 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
372 | |
373 | /* Generic MIPS. */ | |
374 | ||
375 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
376 | "sr", "lo", "hi", "bad", "cause", "pc", |
377 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
378 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
379 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
380 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
381 | "fsr", "fir", "" /*"fp" */ , "", | |
382 | "", "", "", "", "", "", "", "", | |
383 | "", "", "", "", "", "", "", "", | |
691c0433 AC |
384 | }; |
385 | ||
386 | /* Names of IDT R3041 registers. */ | |
387 | ||
388 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
389 | "sr", "lo", "hi", "bad", "cause", "pc", |
390 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
391 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
392 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
393 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
394 | "fsr", "fir", "", /*"fp" */ "", | |
395 | "", "", "bus", "ccfg", "", "", "", "", | |
396 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
397 | }; |
398 | ||
399 | /* Names of tx39 registers. */ | |
400 | ||
401 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
402 | "sr", "lo", "hi", "bad", "cause", "pc", |
403 | "", "", "", "", "", "", "", "", | |
404 | "", "", "", "", "", "", "", "", | |
405 | "", "", "", "", "", "", "", "", | |
406 | "", "", "", "", "", "", "", "", | |
407 | "", "", "", "", | |
408 | "", "", "", "", "", "", "", "", | |
409 | "", "", "config", "cache", "debug", "depc", "epc", "" | |
691c0433 AC |
410 | }; |
411 | ||
412 | /* Names of IRIX registers. */ | |
413 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
414 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
415 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
416 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
417 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
418 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
419 | }; |
420 | ||
cce74817 | 421 | |
5e2e9765 | 422 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 423 | static const char * |
d93859e2 | 424 | mips_register_name (struct gdbarch *gdbarch, int regno) |
cce74817 | 425 | { |
d93859e2 | 426 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
5e2e9765 KB |
427 | /* GPR names for all ABIs other than n32/n64. */ |
428 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
429 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
430 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
431 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
432 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
433 | }; |
434 | ||
435 | /* GPR names for n32 and n64 ABIs. */ | |
436 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
437 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
438 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
439 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
440 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
441 | }; |
442 | ||
d93859e2 | 443 | enum mips_abi abi = mips_abi (gdbarch); |
5e2e9765 | 444 | |
f57d151a UW |
445 | /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, |
446 | but then don't make the raw register names visible. */ | |
d93859e2 UW |
447 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
448 | if (regno < gdbarch_num_regs (gdbarch)) | |
a4b8ebc8 AC |
449 | return ""; |
450 | ||
5e2e9765 KB |
451 | /* The MIPS integer registers are always mapped from 0 to 31. The |
452 | names of the registers (which reflects the conventions regarding | |
453 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 454 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
455 | { |
456 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 457 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 458 | else |
a4b8ebc8 | 459 | return mips_gpr_names[rawnum]; |
5e2e9765 | 460 | } |
d93859e2 UW |
461 | else if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
462 | return tdesc_register_name (gdbarch, rawnum); | |
463 | else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch)) | |
691c0433 AC |
464 | { |
465 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
466 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
467 | } | |
5e2e9765 KB |
468 | else |
469 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 470 | _("mips_register_name: bad register number %d"), rawnum); |
cce74817 | 471 | } |
5e2e9765 | 472 | |
a4b8ebc8 | 473 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 474 | |
a4b8ebc8 AC |
475 | static int |
476 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
477 | struct reggroup *reggroup) | |
478 | { | |
479 | int vector_p; | |
480 | int float_p; | |
481 | int raw_p; | |
72a155b4 UW |
482 | int rawnum = regnum % gdbarch_num_regs (gdbarch); |
483 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
a4b8ebc8 AC |
484 | if (reggroup == all_reggroup) |
485 | return pseudo; | |
486 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
487 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
488 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
489 | (gdbarch), as not all architectures are multi-arch. */ | |
72a155b4 UW |
490 | raw_p = rawnum < gdbarch_num_regs (gdbarch); |
491 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
492 | || gdbarch_register_name (gdbarch, regnum)[0] == '\0') | |
a4b8ebc8 AC |
493 | return 0; |
494 | if (reggroup == float_reggroup) | |
495 | return float_p && pseudo; | |
496 | if (reggroup == vector_reggroup) | |
497 | return vector_p && pseudo; | |
498 | if (reggroup == general_reggroup) | |
499 | return (!vector_p && !float_p) && pseudo; | |
500 | /* Save the pseudo registers. Need to make certain that any code | |
501 | extracting register values from a saved register cache also uses | |
502 | pseudo registers. */ | |
503 | if (reggroup == save_reggroup) | |
504 | return raw_p && pseudo; | |
505 | /* Restore the same pseudo register. */ | |
506 | if (reggroup == restore_reggroup) | |
507 | return raw_p && pseudo; | |
6d82d43b | 508 | return 0; |
a4b8ebc8 AC |
509 | } |
510 | ||
f8b73d13 DJ |
511 | /* Return the groups that a MIPS register can be categorised into. |
512 | This version is only used if we have a target description which | |
513 | describes real registers (and their groups). */ | |
514 | ||
515 | static int | |
516 | mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
517 | struct reggroup *reggroup) | |
518 | { | |
519 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
520 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
521 | int ret; | |
522 | ||
523 | /* Only save, restore, and display the pseudo registers. Need to | |
524 | make certain that any code extracting register values from a | |
525 | saved register cache also uses pseudo registers. | |
526 | ||
527 | Note: saving and restoring the pseudo registers is slightly | |
528 | strange; if we have 64 bits, we should save and restore all | |
529 | 64 bits. But this is hard and has little benefit. */ | |
530 | if (!pseudo) | |
531 | return 0; | |
532 | ||
533 | ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup); | |
534 | if (ret != -1) | |
535 | return ret; | |
536 | ||
537 | return mips_register_reggroup_p (gdbarch, regnum, reggroup); | |
538 | } | |
539 | ||
a4b8ebc8 | 540 | /* Map the symbol table registers which live in the range [1 * |
f57d151a | 541 | gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw |
47ebcfbe | 542 | registers. Take care of alignment and size problems. */ |
c5aa993b | 543 | |
a4b8ebc8 AC |
544 | static void |
545 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
47a35522 | 546 | int cookednum, gdb_byte *buf) |
a4b8ebc8 | 547 | { |
72a155b4 UW |
548 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
549 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
550 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 551 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 552 | regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
553 | else if (register_size (gdbarch, rawnum) > |
554 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
555 | { |
556 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
72a155b4 | 557 | || gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
47ebcfbe AC |
558 | regcache_raw_read_part (regcache, rawnum, 0, 4, buf); |
559 | else | |
560 | regcache_raw_read_part (regcache, rawnum, 4, 4, buf); | |
561 | } | |
562 | else | |
e2e0b3e5 | 563 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 AC |
564 | } |
565 | ||
566 | static void | |
6d82d43b AC |
567 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
568 | struct regcache *regcache, int cookednum, | |
47a35522 | 569 | const gdb_byte *buf) |
a4b8ebc8 | 570 | { |
72a155b4 UW |
571 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
572 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
573 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 574 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 575 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
576 | else if (register_size (gdbarch, rawnum) > |
577 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
578 | { |
579 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
72a155b4 | 580 | || gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
47ebcfbe AC |
581 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); |
582 | else | |
583 | regcache_raw_write_part (regcache, rawnum, 4, 4, buf); | |
584 | } | |
585 | else | |
e2e0b3e5 | 586 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 | 587 | } |
c5aa993b | 588 | |
c906108c | 589 | /* Table to translate MIPS16 register field to actual register number. */ |
6d82d43b | 590 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
591 | |
592 | /* Heuristic_proc_start may hunt through the text section for a long | |
593 | time across a 2400 baud serial line. Allows the user to limit this | |
594 | search. */ | |
595 | ||
596 | static unsigned int heuristic_fence_post = 0; | |
597 | ||
46cd78fb | 598 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
599 | register N. NOTE: This defines the pseudo register type so need to |
600 | rebuild the architecture vector. */ | |
43e526b9 JM |
601 | |
602 | static int mips64_transfers_32bit_regs_p = 0; | |
603 | ||
719ec221 AC |
604 | static void |
605 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
606 | struct cmd_list_element *c) | |
43e526b9 | 607 | { |
719ec221 AC |
608 | struct gdbarch_info info; |
609 | gdbarch_info_init (&info); | |
610 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
611 | instead of relying on globals. Doing that would let generic code | |
612 | handle the search for this specific architecture. */ | |
613 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 614 | { |
719ec221 | 615 | mips64_transfers_32bit_regs_p = 0; |
8a3fe4f8 | 616 | error (_("32-bit compatibility mode not supported")); |
a4b8ebc8 | 617 | } |
a4b8ebc8 AC |
618 | } |
619 | ||
47ebcfbe | 620 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 621 | |
ff2e87ac | 622 | static int |
0abe36f5 | 623 | mips_convert_register_p (struct gdbarch *gdbarch, int regnum, struct type *type) |
ff2e87ac | 624 | { |
0abe36f5 MD |
625 | return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
626 | && register_size (gdbarch, regnum) == 4 | |
627 | && (regnum % gdbarch_num_regs (gdbarch)) | |
628 | >= mips_regnum (gdbarch)->fp0 | |
629 | && (regnum % gdbarch_num_regs (gdbarch)) | |
630 | < mips_regnum (gdbarch)->fp0 + 32 | |
6d82d43b | 631 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
632 | } |
633 | ||
42c466d7 | 634 | static void |
ff2e87ac | 635 | mips_register_to_value (struct frame_info *frame, int regnum, |
47a35522 | 636 | struct type *type, gdb_byte *to) |
102182a9 | 637 | { |
47a35522 MK |
638 | get_frame_register (frame, regnum + 0, to + 4); |
639 | get_frame_register (frame, regnum + 1, to + 0); | |
102182a9 MS |
640 | } |
641 | ||
42c466d7 | 642 | static void |
ff2e87ac | 643 | mips_value_to_register (struct frame_info *frame, int regnum, |
47a35522 | 644 | struct type *type, const gdb_byte *from) |
102182a9 | 645 | { |
47a35522 MK |
646 | put_frame_register (frame, regnum + 0, from + 4); |
647 | put_frame_register (frame, regnum + 1, from + 0); | |
102182a9 MS |
648 | } |
649 | ||
a4b8ebc8 AC |
650 | /* Return the GDB type object for the "standard" data type of data in |
651 | register REG. */ | |
78fde5f8 KB |
652 | |
653 | static struct type * | |
a4b8ebc8 AC |
654 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
655 | { | |
72a155b4 UW |
656 | gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch)); |
657 | if ((regnum % gdbarch_num_regs (gdbarch)) >= mips_regnum (gdbarch)->fp0 | |
658 | && (regnum % gdbarch_num_regs (gdbarch)) | |
659 | < mips_regnum (gdbarch)->fp0 + 32) | |
a6425924 | 660 | { |
5ef80fb0 | 661 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 662 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
8da61cc4 DJ |
663 | if (mips_isa_regsize (gdbarch) == 4) |
664 | return builtin_type_ieee_single; | |
665 | else | |
666 | return builtin_type_ieee_double; | |
a6425924 | 667 | } |
72a155b4 | 668 | else if (regnum < gdbarch_num_regs (gdbarch)) |
d5ac5a39 AC |
669 | { |
670 | /* The raw or ISA registers. These are all sized according to | |
671 | the ISA regsize. */ | |
672 | if (mips_isa_regsize (gdbarch) == 4) | |
673 | return builtin_type_int32; | |
674 | else | |
675 | return builtin_type_int64; | |
676 | } | |
78fde5f8 | 677 | else |
d5ac5a39 AC |
678 | { |
679 | /* The cooked or ABI registers. These are sized according to | |
680 | the ABI (with a few complications). */ | |
72a155b4 UW |
681 | if (regnum >= (gdbarch_num_regs (gdbarch) |
682 | + mips_regnum (gdbarch)->fp_control_status) | |
683 | && regnum <= gdbarch_num_regs (gdbarch) + MIPS_LAST_EMBED_REGNUM) | |
d5ac5a39 AC |
684 | /* The pseudo/cooked view of the embedded registers is always |
685 | 32-bit. The raw view is handled below. */ | |
686 | return builtin_type_int32; | |
687 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) | |
688 | /* The target, while possibly using a 64-bit register buffer, | |
689 | is only transfering 32-bits of each integer register. | |
690 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
691 | return builtin_type_int32; | |
692 | else if (mips_abi_regsize (gdbarch) == 4) | |
693 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
694 | 32- or 64-bit). */ | |
695 | return builtin_type_int32; | |
696 | else | |
697 | /* 64-bit ABI. */ | |
698 | return builtin_type_int64; | |
699 | } | |
78fde5f8 KB |
700 | } |
701 | ||
f8b73d13 DJ |
702 | /* Return the GDB type for the pseudo register REGNUM, which is the |
703 | ABI-level view. This function is only called if there is a target | |
704 | description which includes registers, so we know precisely the | |
705 | types of hardware registers. */ | |
706 | ||
707 | static struct type * | |
708 | mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
709 | { | |
710 | const int num_regs = gdbarch_num_regs (gdbarch); | |
711 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
712 | int rawnum = regnum % num_regs; | |
713 | struct type *rawtype; | |
714 | ||
715 | gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); | |
716 | ||
717 | /* Absent registers are still absent. */ | |
718 | rawtype = gdbarch_register_type (gdbarch, rawnum); | |
719 | if (TYPE_LENGTH (rawtype) == 0) | |
720 | return rawtype; | |
721 | ||
722 | if (rawnum >= MIPS_EMBED_FP0_REGNUM && rawnum < MIPS_EMBED_FP0_REGNUM + 32) | |
723 | /* Present the floating point registers however the hardware did; | |
724 | do not try to convert between FPU layouts. */ | |
725 | return rawtype; | |
726 | ||
727 | if (rawnum >= MIPS_EMBED_FP0_REGNUM + 32 && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
728 | { | |
729 | /* The pseudo/cooked view of embedded registers is always | |
730 | 32-bit, even if the target transfers 64-bit values for them. | |
731 | New targets relying on XML descriptions should only transfer | |
732 | the necessary 32 bits, but older versions of GDB expected 64, | |
733 | so allow the target to provide 64 bits without interfering | |
734 | with the displayed type. */ | |
735 | return builtin_type_int32; | |
736 | } | |
737 | ||
738 | /* Use pointer types for registers if we can. For n32 we can not, | |
739 | since we do not have a 64-bit pointer type. */ | |
0dfff4cb UW |
740 | if (mips_abi_regsize (gdbarch) |
741 | == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr)) | |
f8b73d13 DJ |
742 | { |
743 | if (rawnum == MIPS_SP_REGNUM || rawnum == MIPS_EMBED_BADVADDR_REGNUM) | |
0dfff4cb | 744 | return builtin_type (gdbarch)->builtin_data_ptr; |
f8b73d13 | 745 | else if (rawnum == MIPS_EMBED_PC_REGNUM) |
0dfff4cb | 746 | return builtin_type (gdbarch)->builtin_func_ptr; |
f8b73d13 DJ |
747 | } |
748 | ||
749 | if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8 | |
750 | && rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_EMBED_PC_REGNUM) | |
751 | return builtin_type_int32; | |
752 | ||
753 | /* For all other registers, pass through the hardware type. */ | |
754 | return rawtype; | |
755 | } | |
bcb0cc15 | 756 | |
c906108c | 757 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 758 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
759 | |
760 | static int | |
480d3dd2 | 761 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
762 | { |
763 | switch (mask_address_var) | |
764 | { | |
7f19b9a2 | 765 | case AUTO_BOOLEAN_TRUE: |
4014092b | 766 | return 1; |
7f19b9a2 | 767 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
768 | return 0; |
769 | break; | |
7f19b9a2 | 770 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 771 | return tdep->default_mask_address_p; |
4014092b | 772 | default: |
e2e0b3e5 | 773 | internal_error (__FILE__, __LINE__, _("mips_mask_address_p: bad switch")); |
4014092b | 774 | return -1; |
361d1df0 | 775 | } |
4014092b AC |
776 | } |
777 | ||
778 | static void | |
08546159 AC |
779 | show_mask_address (struct ui_file *file, int from_tty, |
780 | struct cmd_list_element *c, const char *value) | |
4014092b | 781 | { |
1cf3db46 | 782 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
08546159 AC |
783 | |
784 | deprecated_show_value_hack (file, from_tty, c, value); | |
4014092b AC |
785 | switch (mask_address_var) |
786 | { | |
7f19b9a2 | 787 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
788 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
789 | break; | |
7f19b9a2 | 790 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
791 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
792 | break; | |
7f19b9a2 | 793 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
794 | printf_filtered |
795 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
796 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
797 | break; |
798 | default: | |
e2e0b3e5 | 799 | internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); |
4014092b | 800 | break; |
361d1df0 | 801 | } |
4014092b | 802 | } |
c906108c | 803 | |
c906108c SS |
804 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
805 | ||
0fe7e7c8 AC |
806 | int |
807 | mips_pc_is_mips16 (CORE_ADDR memaddr) | |
c906108c SS |
808 | { |
809 | struct minimal_symbol *sym; | |
810 | ||
811 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
95404a3e | 812 | if (is_mips16_addr (memaddr)) |
c906108c SS |
813 | return 1; |
814 | ||
815 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
816 | the high bit of the info field. Use this to decide if the function is | |
817 | MIPS16 or normal MIPS. */ | |
818 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
819 | if (sym) | |
71b8ef93 | 820 | return msymbol_is_special (sym); |
c906108c SS |
821 | else |
822 | return 0; | |
823 | } | |
824 | ||
b2fa5097 | 825 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
6c997a34 AC |
826 | all registers should be sign extended for simplicity? */ |
827 | ||
828 | static CORE_ADDR | |
61a1198a | 829 | mips_read_pc (struct regcache *regcache) |
6c997a34 | 830 | { |
61a1198a UW |
831 | ULONGEST pc; |
832 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; | |
833 | regcache_cooked_read_signed (regcache, regnum, &pc); | |
834 | return pc; | |
b6cb9035 AC |
835 | } |
836 | ||
58dfe9ff AC |
837 | static CORE_ADDR |
838 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
839 | { | |
72a155b4 UW |
840 | return frame_unwind_register_signed |
841 | (next_frame, gdbarch_num_regs (gdbarch) + mips_regnum (gdbarch)->pc); | |
edfae063 AC |
842 | } |
843 | ||
30244cd8 UW |
844 | static CORE_ADDR |
845 | mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
846 | { | |
72a155b4 UW |
847 | return frame_unwind_register_signed |
848 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM); | |
30244cd8 UW |
849 | } |
850 | ||
b8a22b94 | 851 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that |
edfae063 AC |
852 | dummy frame. The frame ID's base needs to match the TOS value |
853 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
854 | breakpoint. */ | |
855 | ||
856 | static struct frame_id | |
b8a22b94 | 857 | mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
edfae063 | 858 | { |
f57d151a | 859 | return frame_id_build |
b8a22b94 DJ |
860 | (get_frame_register_signed (this_frame, |
861 | gdbarch_num_regs (gdbarch) | |
862 | + MIPS_SP_REGNUM), | |
863 | get_frame_pc (this_frame)); | |
58dfe9ff AC |
864 | } |
865 | ||
b6cb9035 | 866 | static void |
61a1198a | 867 | mips_write_pc (struct regcache *regcache, CORE_ADDR pc) |
b6cb9035 | 868 | { |
61a1198a UW |
869 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; |
870 | regcache_cooked_write_unsigned (regcache, regnum, pc); | |
6c997a34 | 871 | } |
c906108c | 872 | |
c906108c SS |
873 | /* Fetch and return instruction from the specified location. If the PC |
874 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
875 | ||
d37cca3d | 876 | static ULONGEST |
acdb74a0 | 877 | mips_fetch_instruction (CORE_ADDR addr) |
c906108c | 878 | { |
47a35522 | 879 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
880 | int instlen; |
881 | int status; | |
882 | ||
0fe7e7c8 | 883 | if (mips_pc_is_mips16 (addr)) |
c906108c | 884 | { |
95ac2dcf | 885 | instlen = MIPS_INSN16_SIZE; |
95404a3e | 886 | addr = unmake_mips16_addr (addr); |
c906108c SS |
887 | } |
888 | else | |
95ac2dcf | 889 | instlen = MIPS_INSN32_SIZE; |
8defab1a | 890 | status = target_read_memory (addr, buf, instlen); |
c906108c SS |
891 | if (status) |
892 | memory_error (status, addr); | |
893 | return extract_unsigned_integer (buf, instlen); | |
894 | } | |
895 | ||
c906108c | 896 | /* These the fields of 32 bit mips instructions */ |
e135b889 DJ |
897 | #define mips32_op(x) (x >> 26) |
898 | #define itype_op(x) (x >> 26) | |
899 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 900 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 901 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 902 | |
e135b889 DJ |
903 | #define jtype_op(x) (x >> 26) |
904 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 905 | |
e135b889 DJ |
906 | #define rtype_op(x) (x >> 26) |
907 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
908 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
909 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
910 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
911 | #define rtype_funct(x) (x & 0x3f) | |
c906108c | 912 | |
06987e64 MK |
913 | static LONGEST |
914 | mips32_relative_offset (ULONGEST inst) | |
c5aa993b | 915 | { |
06987e64 | 916 | return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; |
c906108c SS |
917 | } |
918 | ||
f49e4e6d MS |
919 | /* Determine where to set a single step breakpoint while considering |
920 | branch prediction. */ | |
5a89d8aa | 921 | static CORE_ADDR |
0b1b3e42 | 922 | mips32_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c5aa993b JM |
923 | { |
924 | unsigned long inst; | |
925 | int op; | |
926 | inst = mips_fetch_instruction (pc); | |
e135b889 | 927 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 928 | { |
e135b889 | 929 | if (itype_op (inst) >> 2 == 5) |
6d82d43b | 930 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 931 | { |
e135b889 | 932 | op = (itype_op (inst) & 0x03); |
c906108c SS |
933 | switch (op) |
934 | { | |
e135b889 DJ |
935 | case 0: /* BEQL */ |
936 | goto equal_branch; | |
937 | case 1: /* BNEL */ | |
938 | goto neq_branch; | |
939 | case 2: /* BLEZL */ | |
940 | goto less_branch; | |
313628cc | 941 | case 3: /* BGTZL */ |
e135b889 | 942 | goto greater_branch; |
c5aa993b JM |
943 | default: |
944 | pc += 4; | |
c906108c SS |
945 | } |
946 | } | |
e135b889 | 947 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
6d82d43b | 948 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
e135b889 DJ |
949 | { |
950 | int tf = itype_rt (inst) & 0x01; | |
951 | int cnum = itype_rt (inst) >> 2; | |
6d82d43b | 952 | int fcrcs = |
72a155b4 UW |
953 | get_frame_register_signed (frame, |
954 | mips_regnum (get_frame_arch (frame))-> | |
0b1b3e42 | 955 | fp_control_status); |
e135b889 DJ |
956 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); |
957 | ||
958 | if (((cond >> cnum) & 0x01) == tf) | |
959 | pc += mips32_relative_offset (inst) + 4; | |
960 | else | |
961 | pc += 8; | |
962 | } | |
c5aa993b JM |
963 | else |
964 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
965 | } |
966 | else | |
c5aa993b JM |
967 | { /* This gets way messy */ |
968 | ||
c906108c | 969 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 970 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 971 | { |
c5aa993b JM |
972 | case 0: /* SPECIAL */ |
973 | op = rtype_funct (inst); | |
974 | switch (op) | |
975 | { | |
976 | case 8: /* JR */ | |
977 | case 9: /* JALR */ | |
6c997a34 | 978 | /* Set PC to that address */ |
0b1b3e42 | 979 | pc = get_frame_register_signed (frame, rtype_rs (inst)); |
c5aa993b | 980 | break; |
e38d4e1a DJ |
981 | case 12: /* SYSCALL */ |
982 | { | |
983 | struct gdbarch_tdep *tdep; | |
984 | ||
985 | tdep = gdbarch_tdep (get_frame_arch (frame)); | |
986 | if (tdep->syscall_next_pc != NULL) | |
987 | pc = tdep->syscall_next_pc (frame); | |
988 | else | |
989 | pc += 4; | |
990 | } | |
991 | break; | |
c5aa993b JM |
992 | default: |
993 | pc += 4; | |
994 | } | |
995 | ||
6d82d43b | 996 | break; /* end SPECIAL */ |
c5aa993b | 997 | case 1: /* REGIMM */ |
c906108c | 998 | { |
e135b889 DJ |
999 | op = itype_rt (inst); /* branch condition */ |
1000 | switch (op) | |
c906108c | 1001 | { |
c5aa993b | 1002 | case 0: /* BLTZ */ |
e135b889 DJ |
1003 | case 2: /* BLTZL */ |
1004 | case 16: /* BLTZAL */ | |
c5aa993b | 1005 | case 18: /* BLTZALL */ |
c906108c | 1006 | less_branch: |
0b1b3e42 | 1007 | if (get_frame_register_signed (frame, itype_rs (inst)) < 0) |
c5aa993b JM |
1008 | pc += mips32_relative_offset (inst) + 4; |
1009 | else | |
1010 | pc += 8; /* after the delay slot */ | |
1011 | break; | |
e135b889 | 1012 | case 1: /* BGEZ */ |
c5aa993b JM |
1013 | case 3: /* BGEZL */ |
1014 | case 17: /* BGEZAL */ | |
1015 | case 19: /* BGEZALL */ | |
0b1b3e42 | 1016 | if (get_frame_register_signed (frame, itype_rs (inst)) >= 0) |
c5aa993b JM |
1017 | pc += mips32_relative_offset (inst) + 4; |
1018 | else | |
1019 | pc += 8; /* after the delay slot */ | |
1020 | break; | |
e135b889 | 1021 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1022 | default: |
1023 | pc += 4; | |
c906108c SS |
1024 | } |
1025 | } | |
6d82d43b | 1026 | break; /* end REGIMM */ |
c5aa993b JM |
1027 | case 2: /* J */ |
1028 | case 3: /* JAL */ | |
1029 | { | |
1030 | unsigned long reg; | |
1031 | reg = jtype_target (inst) << 2; | |
e135b889 | 1032 | /* Upper four bits get never changed... */ |
5b652102 | 1033 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
c906108c | 1034 | } |
c5aa993b JM |
1035 | break; |
1036 | /* FIXME case JALX : */ | |
1037 | { | |
1038 | unsigned long reg; | |
1039 | reg = jtype_target (inst) << 2; | |
5b652102 | 1040 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + 1; /* yes, +1 */ |
c906108c SS |
1041 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1042 | } | |
c5aa993b | 1043 | break; /* The new PC will be alternate mode */ |
e135b889 | 1044 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1045 | equal_branch: |
0b1b3e42 UW |
1046 | if (get_frame_register_signed (frame, itype_rs (inst)) == |
1047 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1048 | pc += mips32_relative_offset (inst) + 4; |
1049 | else | |
1050 | pc += 8; | |
1051 | break; | |
e135b889 | 1052 | case 5: /* BNE, BNEL */ |
c5aa993b | 1053 | neq_branch: |
0b1b3e42 UW |
1054 | if (get_frame_register_signed (frame, itype_rs (inst)) != |
1055 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1056 | pc += mips32_relative_offset (inst) + 4; |
1057 | else | |
1058 | pc += 8; | |
1059 | break; | |
e135b889 | 1060 | case 6: /* BLEZ, BLEZL */ |
0b1b3e42 | 1061 | if (get_frame_register_signed (frame, itype_rs (inst)) <= 0) |
c5aa993b JM |
1062 | pc += mips32_relative_offset (inst) + 4; |
1063 | else | |
1064 | pc += 8; | |
1065 | break; | |
1066 | case 7: | |
e135b889 DJ |
1067 | default: |
1068 | greater_branch: /* BGTZ, BGTZL */ | |
0b1b3e42 | 1069 | if (get_frame_register_signed (frame, itype_rs (inst)) > 0) |
c5aa993b JM |
1070 | pc += mips32_relative_offset (inst) + 4; |
1071 | else | |
1072 | pc += 8; | |
1073 | break; | |
c5aa993b JM |
1074 | } /* switch */ |
1075 | } /* else */ | |
1076 | return pc; | |
1077 | } /* mips32_next_pc */ | |
c906108c SS |
1078 | |
1079 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 1080 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
1081 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
1082 | We dont want to set a single step instruction on the extend instruction | |
1083 | either. | |
c5aa993b | 1084 | */ |
c906108c SS |
1085 | |
1086 | /* Lots of mips16 instruction formats */ | |
1087 | /* Predicting jumps requires itype,ritype,i8type | |
1088 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 1089 | */ |
c906108c SS |
1090 | enum mips16_inst_fmts |
1091 | { | |
c5aa993b JM |
1092 | itype, /* 0 immediate 5,10 */ |
1093 | ritype, /* 1 5,3,8 */ | |
1094 | rrtype, /* 2 5,3,3,5 */ | |
1095 | rritype, /* 3 5,3,3,5 */ | |
1096 | rrrtype, /* 4 5,3,3,3,2 */ | |
1097 | rriatype, /* 5 5,3,3,1,4 */ | |
1098 | shifttype, /* 6 5,3,3,3,2 */ | |
1099 | i8type, /* 7 5,3,8 */ | |
1100 | i8movtype, /* 8 5,3,3,5 */ | |
1101 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1102 | i64type, /* 10 5,3,8 */ | |
1103 | ri64type, /* 11 5,3,3,5 */ | |
1104 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1105 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1106 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1107 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1108 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1109 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1110 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1111 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1112 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1113 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1114 | }; | |
12f02c2a AC |
1115 | /* I am heaping all the fields of the formats into one structure and |
1116 | then, only the fields which are involved in instruction extension */ | |
c906108c | 1117 | struct upk_mips16 |
6d82d43b AC |
1118 | { |
1119 | CORE_ADDR offset; | |
1120 | unsigned int regx; /* Function in i8 type */ | |
1121 | unsigned int regy; | |
1122 | }; | |
c906108c SS |
1123 | |
1124 | ||
12f02c2a | 1125 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
c68cf8ad | 1126 | for the bits which make up the immediate extension. */ |
c906108c | 1127 | |
12f02c2a AC |
1128 | static CORE_ADDR |
1129 | extended_offset (unsigned int extension) | |
c906108c | 1130 | { |
12f02c2a | 1131 | CORE_ADDR value; |
c5aa993b JM |
1132 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1133 | value = value << 6; | |
1134 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
1135 | value = value << 5; | |
1136 | value |= extension & 0x01f; /* extract 4:0 */ | |
1137 | return value; | |
c906108c SS |
1138 | } |
1139 | ||
1140 | /* Only call this function if you know that this is an extendable | |
bcf1ea1e MR |
1141 | instruction. It won't malfunction, but why make excess remote memory |
1142 | references? If the immediate operands get sign extended or something, | |
1143 | do it after the extension is performed. */ | |
c906108c | 1144 | /* FIXME: Every one of these cases needs to worry about sign extension |
bcf1ea1e | 1145 | when the offset is to be used in relative addressing. */ |
c906108c | 1146 | |
12f02c2a | 1147 | static unsigned int |
c5aa993b | 1148 | fetch_mips_16 (CORE_ADDR pc) |
c906108c | 1149 | { |
47a35522 | 1150 | gdb_byte buf[8]; |
c5aa993b JM |
1151 | pc &= 0xfffffffe; /* clear the low order bit */ |
1152 | target_read_memory (pc, buf, 2); | |
1153 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
1154 | } |
1155 | ||
1156 | static void | |
c5aa993b | 1157 | unpack_mips16 (CORE_ADDR pc, |
12f02c2a AC |
1158 | unsigned int extension, |
1159 | unsigned int inst, | |
6d82d43b | 1160 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 1161 | { |
12f02c2a AC |
1162 | CORE_ADDR offset; |
1163 | int regx; | |
1164 | int regy; | |
1165 | switch (insn_format) | |
c906108c | 1166 | { |
c5aa993b | 1167 | case itype: |
c906108c | 1168 | { |
12f02c2a AC |
1169 | CORE_ADDR value; |
1170 | if (extension) | |
c5aa993b JM |
1171 | { |
1172 | value = extended_offset (extension); | |
1173 | value = value << 11; /* rom for the original value */ | |
6d82d43b | 1174 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1175 | } |
1176 | else | |
c5aa993b | 1177 | { |
12f02c2a | 1178 | value = inst & 0x7ff; |
c5aa993b | 1179 | /* FIXME : Consider sign extension */ |
c906108c | 1180 | } |
12f02c2a AC |
1181 | offset = value; |
1182 | regx = -1; | |
1183 | regy = -1; | |
c906108c | 1184 | } |
c5aa993b JM |
1185 | break; |
1186 | case ritype: | |
1187 | case i8type: | |
1188 | { /* A register identifier and an offset */ | |
c906108c SS |
1189 | /* Most of the fields are the same as I type but the |
1190 | immediate value is of a different length */ | |
12f02c2a AC |
1191 | CORE_ADDR value; |
1192 | if (extension) | |
c906108c | 1193 | { |
c5aa993b JM |
1194 | value = extended_offset (extension); |
1195 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1196 | value |= inst & 0xff; /* eleven bits from instruction */ |
1197 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1198 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1199 | { | |
1200 | value &= ~0x3fff; /* remove the sign bit */ | |
1201 | value = -value; | |
c906108c SS |
1202 | } |
1203 | } | |
c5aa993b JM |
1204 | else |
1205 | { | |
12f02c2a AC |
1206 | value = inst & 0xff; /* 8 bits */ |
1207 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1208 | /* FIXME: Do sign extension , this format needs it */ |
1209 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1210 | { | |
1211 | value &= 0xef; /* remove the sign bit */ | |
1212 | value = -value; | |
1213 | } | |
c5aa993b | 1214 | } |
12f02c2a AC |
1215 | offset = value; |
1216 | regy = -1; | |
c5aa993b | 1217 | break; |
c906108c | 1218 | } |
c5aa993b | 1219 | case jalxtype: |
c906108c | 1220 | { |
c5aa993b | 1221 | unsigned long value; |
12f02c2a AC |
1222 | unsigned int nexthalf; |
1223 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b JM |
1224 | value = value << 16; |
1225 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
1226 | value |= nexthalf; | |
12f02c2a AC |
1227 | offset = value; |
1228 | regx = -1; | |
1229 | regy = -1; | |
c5aa993b | 1230 | break; |
c906108c SS |
1231 | } |
1232 | default: | |
e2e0b3e5 | 1233 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c | 1234 | } |
12f02c2a AC |
1235 | upk->offset = offset; |
1236 | upk->regx = regx; | |
1237 | upk->regy = regy; | |
c906108c SS |
1238 | } |
1239 | ||
1240 | ||
c5aa993b JM |
1241 | static CORE_ADDR |
1242 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1243 | { |
5b652102 | 1244 | return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff))); |
c906108c SS |
1245 | } |
1246 | ||
12f02c2a | 1247 | static CORE_ADDR |
0b1b3e42 | 1248 | extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc, |
6d82d43b | 1249 | unsigned int extension, unsigned int insn) |
c906108c | 1250 | { |
12f02c2a AC |
1251 | int op = (insn >> 11); |
1252 | switch (op) | |
c906108c | 1253 | { |
6d82d43b | 1254 | case 2: /* Branch */ |
12f02c2a AC |
1255 | { |
1256 | CORE_ADDR offset; | |
1257 | struct upk_mips16 upk; | |
1258 | unpack_mips16 (pc, extension, insn, itype, &upk); | |
1259 | offset = upk.offset; | |
1260 | if (offset & 0x800) | |
1261 | { | |
1262 | offset &= 0xeff; | |
1263 | offset = -offset; | |
1264 | } | |
1265 | pc += (offset << 1) + 2; | |
1266 | break; | |
1267 | } | |
6d82d43b | 1268 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ |
12f02c2a AC |
1269 | { |
1270 | struct upk_mips16 upk; | |
1271 | unpack_mips16 (pc, extension, insn, jalxtype, &upk); | |
1272 | pc = add_offset_16 (pc, upk.offset); | |
1273 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1274 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1275 | else | |
1276 | pc |= 0x01; | |
1277 | break; | |
1278 | } | |
6d82d43b | 1279 | case 4: /* beqz */ |
12f02c2a AC |
1280 | { |
1281 | struct upk_mips16 upk; | |
1282 | int reg; | |
1283 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
0b1b3e42 | 1284 | reg = get_frame_register_signed (frame, upk.regx); |
12f02c2a AC |
1285 | if (reg == 0) |
1286 | pc += (upk.offset << 1) + 2; | |
1287 | else | |
1288 | pc += 2; | |
1289 | break; | |
1290 | } | |
6d82d43b | 1291 | case 5: /* bnez */ |
12f02c2a AC |
1292 | { |
1293 | struct upk_mips16 upk; | |
1294 | int reg; | |
1295 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
0b1b3e42 | 1296 | reg = get_frame_register_signed (frame, upk.regx); |
12f02c2a AC |
1297 | if (reg != 0) |
1298 | pc += (upk.offset << 1) + 2; | |
1299 | else | |
1300 | pc += 2; | |
1301 | break; | |
1302 | } | |
6d82d43b | 1303 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
1304 | { |
1305 | struct upk_mips16 upk; | |
1306 | int reg; | |
1307 | unpack_mips16 (pc, extension, insn, i8type, &upk); | |
1308 | /* upk.regx contains the opcode */ | |
0b1b3e42 | 1309 | reg = get_frame_register_signed (frame, 24); /* Test register is 24 */ |
12f02c2a AC |
1310 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ |
1311 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1312 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1313 | pc += (upk.offset << 1) + 2; | |
1314 | else | |
1315 | pc += 2; | |
1316 | break; | |
1317 | } | |
6d82d43b | 1318 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
1319 | { |
1320 | struct upk_mips16 upk; | |
1321 | /* upk.fmt = rrtype; */ | |
1322 | op = insn & 0x1f; | |
1323 | if (op == 0) | |
c5aa993b | 1324 | { |
12f02c2a AC |
1325 | int reg; |
1326 | upk.regx = (insn >> 8) & 0x07; | |
1327 | upk.regy = (insn >> 5) & 0x07; | |
1328 | switch (upk.regy) | |
c5aa993b | 1329 | { |
12f02c2a AC |
1330 | case 0: |
1331 | reg = upk.regx; | |
1332 | break; | |
1333 | case 1: | |
1334 | reg = 31; | |
6d82d43b | 1335 | break; /* Function return instruction */ |
12f02c2a AC |
1336 | case 2: |
1337 | reg = upk.regx; | |
1338 | break; | |
1339 | default: | |
1340 | reg = 31; | |
6d82d43b | 1341 | break; /* BOGUS Guess */ |
c906108c | 1342 | } |
0b1b3e42 | 1343 | pc = get_frame_register_signed (frame, reg); |
c906108c | 1344 | } |
12f02c2a | 1345 | else |
c5aa993b | 1346 | pc += 2; |
12f02c2a AC |
1347 | break; |
1348 | } | |
1349 | case 30: | |
1350 | /* This is an instruction extension. Fetch the real instruction | |
1351 | (which follows the extension) and decode things based on | |
1352 | that. */ | |
1353 | { | |
1354 | pc += 2; | |
0b1b3e42 | 1355 | pc = extended_mips16_next_pc (frame, pc, insn, fetch_mips_16 (pc)); |
12f02c2a AC |
1356 | break; |
1357 | } | |
1358 | default: | |
1359 | { | |
1360 | pc += 2; | |
1361 | break; | |
1362 | } | |
c906108c | 1363 | } |
c5aa993b | 1364 | return pc; |
12f02c2a | 1365 | } |
c906108c | 1366 | |
5a89d8aa | 1367 | static CORE_ADDR |
0b1b3e42 | 1368 | mips16_next_pc (struct frame_info *frame, CORE_ADDR pc) |
12f02c2a AC |
1369 | { |
1370 | unsigned int insn = fetch_mips_16 (pc); | |
0b1b3e42 | 1371 | return extended_mips16_next_pc (frame, pc, 0, insn); |
12f02c2a AC |
1372 | } |
1373 | ||
1374 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1375 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1376 | It works by decoding the current instruction and predicting where a |
1377 | branch will go. This isnt hard because all the data is available. | |
ce1f96de | 1378 | The MIPS32 and MIPS16 variants are quite different. */ |
ad527d2e | 1379 | static CORE_ADDR |
0b1b3e42 | 1380 | mips_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 1381 | { |
ce1f96de | 1382 | if (is_mips16_addr (pc)) |
0b1b3e42 | 1383 | return mips16_next_pc (frame, pc); |
c5aa993b | 1384 | else |
0b1b3e42 | 1385 | return mips32_next_pc (frame, pc); |
12f02c2a | 1386 | } |
c906108c | 1387 | |
edfae063 AC |
1388 | struct mips_frame_cache |
1389 | { | |
1390 | CORE_ADDR base; | |
1391 | struct trad_frame_saved_reg *saved_regs; | |
1392 | }; | |
1393 | ||
29639122 JB |
1394 | /* Set a register's saved stack address in temp_saved_regs. If an |
1395 | address has already been set for this register, do nothing; this | |
1396 | way we will only recognize the first save of a given register in a | |
1397 | function prologue. | |
eec63939 | 1398 | |
f57d151a UW |
1399 | For simplicity, save the address in both [0 .. gdbarch_num_regs) and |
1400 | [gdbarch_num_regs .. 2*gdbarch_num_regs). | |
1401 | Strictly speaking, only the second range is used as it is only second | |
1402 | range (the ABI instead of ISA registers) that comes into play when finding | |
1403 | saved registers in a frame. */ | |
eec63939 AC |
1404 | |
1405 | static void | |
74ed0bb4 MD |
1406 | set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache, |
1407 | int regnum, CORE_ADDR offset) | |
eec63939 | 1408 | { |
29639122 JB |
1409 | if (this_cache != NULL |
1410 | && this_cache->saved_regs[regnum].addr == -1) | |
1411 | { | |
74ed0bb4 MD |
1412 | this_cache->saved_regs[regnum + 0 * gdbarch_num_regs (gdbarch)].addr |
1413 | = offset; | |
1414 | this_cache->saved_regs[regnum + 1 * gdbarch_num_regs (gdbarch)].addr | |
1415 | = offset; | |
29639122 | 1416 | } |
eec63939 AC |
1417 | } |
1418 | ||
eec63939 | 1419 | |
29639122 JB |
1420 | /* Fetch the immediate value from a MIPS16 instruction. |
1421 | If the previous instruction was an EXTEND, use it to extend | |
1422 | the upper bits of the immediate value. This is a helper function | |
1423 | for mips16_scan_prologue. */ | |
eec63939 | 1424 | |
29639122 JB |
1425 | static int |
1426 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ | |
1427 | unsigned short inst, /* current instruction */ | |
1428 | int nbits, /* number of bits in imm field */ | |
1429 | int scale, /* scale factor to be applied to imm */ | |
1430 | int is_signed) /* is the imm field signed? */ | |
eec63939 | 1431 | { |
29639122 | 1432 | int offset; |
eec63939 | 1433 | |
29639122 JB |
1434 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
1435 | { | |
1436 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
1437 | if (offset & 0x8000) /* check for negative extend */ | |
1438 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
1439 | return offset | (inst & 0x1f); | |
1440 | } | |
eec63939 | 1441 | else |
29639122 JB |
1442 | { |
1443 | int max_imm = 1 << nbits; | |
1444 | int mask = max_imm - 1; | |
1445 | int sign_bit = max_imm >> 1; | |
45c9dd44 | 1446 | |
29639122 JB |
1447 | offset = inst & mask; |
1448 | if (is_signed && (offset & sign_bit)) | |
1449 | offset = 0 - (max_imm - offset); | |
1450 | return offset * scale; | |
1451 | } | |
1452 | } | |
eec63939 | 1453 | |
65596487 | 1454 | |
29639122 JB |
1455 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1456 | the associated FRAME_CACHE if not null. | |
1457 | Return the address of the first instruction past the prologue. */ | |
eec63939 | 1458 | |
29639122 JB |
1459 | static CORE_ADDR |
1460 | mips16_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 1461 | struct frame_info *this_frame, |
29639122 JB |
1462 | struct mips_frame_cache *this_cache) |
1463 | { | |
1464 | CORE_ADDR cur_pc; | |
1465 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
1466 | CORE_ADDR sp; | |
1467 | long frame_offset = 0; /* Size of stack frame. */ | |
1468 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
1469 | int frame_reg = MIPS_SP_REGNUM; | |
1470 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
1471 | unsigned inst = 0; /* current instruction */ | |
1472 | unsigned entry_inst = 0; /* the entry instruction */ | |
2207132d | 1473 | unsigned save_inst = 0; /* the save instruction */ |
29639122 | 1474 | int reg, offset; |
a343eb3c | 1475 | |
29639122 JB |
1476 | int extend_bytes = 0; |
1477 | int prev_extend_bytes; | |
1478 | CORE_ADDR end_prologue_addr = 0; | |
b8a22b94 | 1479 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
a343eb3c | 1480 | |
29639122 | 1481 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
1482 | THIS_FRAME. */ |
1483 | if (this_frame != NULL) | |
1484 | sp = get_frame_register_signed (this_frame, | |
1485 | gdbarch_num_regs (gdbarch) | |
1486 | + MIPS_SP_REGNUM); | |
29639122 JB |
1487 | else |
1488 | sp = 0; | |
eec63939 | 1489 | |
29639122 JB |
1490 | if (limit_pc > start_pc + 200) |
1491 | limit_pc = start_pc + 200; | |
eec63939 | 1492 | |
95ac2dcf | 1493 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) |
29639122 JB |
1494 | { |
1495 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1496 | the immediate offset extension from it in mips16_get_imm. */ | |
1497 | prev_inst = inst; | |
eec63939 | 1498 | |
29639122 JB |
1499 | /* Fetch and decode the instruction. */ |
1500 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
eec63939 | 1501 | |
29639122 JB |
1502 | /* Normally we ignore extend instructions. However, if it is |
1503 | not followed by a valid prologue instruction, then this | |
1504 | instruction is not part of the prologue either. We must | |
1505 | remember in this case to adjust the end_prologue_addr back | |
1506 | over the extend. */ | |
1507 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
1508 | { | |
95ac2dcf | 1509 | extend_bytes = MIPS_INSN16_SIZE; |
29639122 JB |
1510 | continue; |
1511 | } | |
eec63939 | 1512 | |
29639122 JB |
1513 | prev_extend_bytes = extend_bytes; |
1514 | extend_bytes = 0; | |
eec63939 | 1515 | |
29639122 JB |
1516 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
1517 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1518 | { | |
1519 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
1520 | if (offset < 0) /* negative stack adjustment? */ | |
1521 | frame_offset -= offset; | |
1522 | else | |
1523 | /* Exit loop if a positive stack adjustment is found, which | |
1524 | usually means that the stack cleanup code in the function | |
1525 | epilogue is reached. */ | |
1526 | break; | |
1527 | } | |
1528 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
1529 | { | |
1530 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1531 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
74ed0bb4 | 1532 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
1533 | } |
1534 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
1535 | { | |
1536 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1537 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1538 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
1539 | } |
1540 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
1541 | { | |
1542 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
74ed0bb4 | 1543 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1544 | } |
1545 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
1546 | { | |
1547 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
74ed0bb4 | 1548 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1549 | } |
1550 | else if (inst == 0x673d) /* move $s1, $sp */ | |
1551 | { | |
1552 | frame_addr = sp; | |
1553 | frame_reg = 17; | |
1554 | } | |
1555 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
1556 | { | |
1557 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1558 | frame_addr = sp + offset; | |
1559 | frame_reg = 17; | |
1560 | frame_adjust = offset; | |
1561 | } | |
1562 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
1563 | { | |
1564 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
1565 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1566 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
1567 | } |
1568 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
1569 | { | |
1570 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1571 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1572 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
1573 | } |
1574 | else if ((inst & 0xf81f) == 0xe809 | |
1575 | && (inst & 0x700) != 0x700) /* entry */ | |
1576 | entry_inst = inst; /* save for later processing */ | |
2207132d MR |
1577 | else if ((inst & 0xff80) == 0x6480) /* save */ |
1578 | { | |
1579 | save_inst = inst; /* save for later processing */ | |
1580 | if (prev_extend_bytes) /* extend */ | |
1581 | save_inst |= prev_inst << 16; | |
1582 | } | |
29639122 | 1583 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
95ac2dcf | 1584 | cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ |
29639122 JB |
1585 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
1586 | { | |
1587 | /* This instruction is part of the prologue, but we don't | |
1588 | need to do anything special to handle it. */ | |
1589 | } | |
1590 | else | |
1591 | { | |
1592 | /* This instruction is not an instruction typically found | |
1593 | in a prologue, so we must have reached the end of the | |
1594 | prologue. */ | |
1595 | if (end_prologue_addr == 0) | |
1596 | end_prologue_addr = cur_pc - prev_extend_bytes; | |
1597 | } | |
1598 | } | |
eec63939 | 1599 | |
29639122 JB |
1600 | /* The entry instruction is typically the first instruction in a function, |
1601 | and it stores registers at offsets relative to the value of the old SP | |
1602 | (before the prologue). But the value of the sp parameter to this | |
1603 | function is the new SP (after the prologue has been executed). So we | |
1604 | can't calculate those offsets until we've seen the entire prologue, | |
1605 | and can calculate what the old SP must have been. */ | |
1606 | if (entry_inst != 0) | |
1607 | { | |
1608 | int areg_count = (entry_inst >> 8) & 7; | |
1609 | int sreg_count = (entry_inst >> 6) & 3; | |
eec63939 | 1610 | |
29639122 JB |
1611 | /* The entry instruction always subtracts 32 from the SP. */ |
1612 | frame_offset += 32; | |
1613 | ||
1614 | /* Now we can calculate what the SP must have been at the | |
1615 | start of the function prologue. */ | |
1616 | sp += frame_offset; | |
1617 | ||
1618 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
1619 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
1620 | { | |
74ed0bb4 | 1621 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 1622 | offset += mips_abi_regsize (gdbarch); |
29639122 JB |
1623 | } |
1624 | ||
1625 | /* Check if the ra register was pushed on the stack. */ | |
1626 | offset = -4; | |
1627 | if (entry_inst & 0x20) | |
1628 | { | |
74ed0bb4 | 1629 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
72a155b4 | 1630 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
1631 | } |
1632 | ||
1633 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
1634 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1635 | { | |
74ed0bb4 | 1636 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 1637 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
1638 | } |
1639 | } | |
1640 | ||
2207132d MR |
1641 | /* The SAVE instruction is similar to ENTRY, except that defined by the |
1642 | MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the | |
1643 | size of the frame is specified as an immediate field of instruction | |
1644 | and an extended variation exists which lets additional registers and | |
1645 | frame space to be specified. The instruction always treats registers | |
1646 | as 32-bit so its usefulness for 64-bit ABIs is questionable. */ | |
1647 | if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4) | |
1648 | { | |
1649 | static int args_table[16] = { | |
1650 | 0, 0, 0, 0, 1, 1, 1, 1, | |
1651 | 2, 2, 2, 0, 3, 3, 4, -1, | |
1652 | }; | |
1653 | static int astatic_table[16] = { | |
1654 | 0, 1, 2, 3, 0, 1, 2, 3, | |
1655 | 0, 1, 2, 4, 0, 1, 0, -1, | |
1656 | }; | |
1657 | int aregs = (save_inst >> 16) & 0xf; | |
1658 | int xsregs = (save_inst >> 24) & 0x7; | |
1659 | int args = args_table[aregs]; | |
1660 | int astatic = astatic_table[aregs]; | |
1661 | long frame_size; | |
1662 | ||
1663 | if (args < 0) | |
1664 | { | |
1665 | warning (_("Invalid number of argument registers encoded in SAVE.")); | |
1666 | args = 0; | |
1667 | } | |
1668 | if (astatic < 0) | |
1669 | { | |
1670 | warning (_("Invalid number of static registers encoded in SAVE.")); | |
1671 | astatic = 0; | |
1672 | } | |
1673 | ||
1674 | /* For standard SAVE the frame size of 0 means 128. */ | |
1675 | frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf); | |
1676 | if (frame_size == 0 && (save_inst >> 16) == 0) | |
1677 | frame_size = 16; | |
1678 | frame_size *= 8; | |
1679 | frame_offset += frame_size; | |
1680 | ||
1681 | /* Now we can calculate what the SP must have been at the | |
1682 | start of the function prologue. */ | |
1683 | sp += frame_offset; | |
1684 | ||
1685 | /* Check if A0-A3 were saved in the caller's argument save area. */ | |
1686 | for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++) | |
1687 | { | |
74ed0bb4 | 1688 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1689 | offset += mips_abi_regsize (gdbarch); |
1690 | } | |
1691 | ||
1692 | offset = -4; | |
1693 | ||
1694 | /* Check if the RA register was pushed on the stack. */ | |
1695 | if (save_inst & 0x40) | |
1696 | { | |
74ed0bb4 | 1697 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
2207132d MR |
1698 | offset -= mips_abi_regsize (gdbarch); |
1699 | } | |
1700 | ||
1701 | /* Check if the S8 register was pushed on the stack. */ | |
1702 | if (xsregs > 6) | |
1703 | { | |
74ed0bb4 | 1704 | set_reg_offset (gdbarch, this_cache, 30, sp + offset); |
2207132d MR |
1705 | offset -= mips_abi_regsize (gdbarch); |
1706 | xsregs--; | |
1707 | } | |
1708 | /* Check if S2-S7 were pushed on the stack. */ | |
1709 | for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--) | |
1710 | { | |
74ed0bb4 | 1711 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1712 | offset -= mips_abi_regsize (gdbarch); |
1713 | } | |
1714 | ||
1715 | /* Check if the S1 register was pushed on the stack. */ | |
1716 | if (save_inst & 0x10) | |
1717 | { | |
74ed0bb4 | 1718 | set_reg_offset (gdbarch, this_cache, 17, sp + offset); |
2207132d MR |
1719 | offset -= mips_abi_regsize (gdbarch); |
1720 | } | |
1721 | /* Check if the S0 register was pushed on the stack. */ | |
1722 | if (save_inst & 0x20) | |
1723 | { | |
74ed0bb4 | 1724 | set_reg_offset (gdbarch, this_cache, 16, sp + offset); |
2207132d MR |
1725 | offset -= mips_abi_regsize (gdbarch); |
1726 | } | |
1727 | ||
1728 | /* Check if A0-A3 were pushed on the stack. */ | |
1729 | for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--) | |
1730 | { | |
74ed0bb4 | 1731 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1732 | offset -= mips_abi_regsize (gdbarch); |
1733 | } | |
1734 | } | |
1735 | ||
29639122 JB |
1736 | if (this_cache != NULL) |
1737 | { | |
1738 | this_cache->base = | |
b8a22b94 DJ |
1739 | (get_frame_register_signed (this_frame, |
1740 | gdbarch_num_regs (gdbarch) + frame_reg) | |
29639122 JB |
1741 | + frame_offset - frame_adjust); |
1742 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should | |
1743 | be able to get rid of the assignment below, evetually. But it's | |
1744 | still needed for now. */ | |
72a155b4 UW |
1745 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
1746 | + mips_regnum (gdbarch)->pc] | |
1747 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; | |
29639122 JB |
1748 | } |
1749 | ||
1750 | /* If we didn't reach the end of the prologue when scanning the function | |
1751 | instructions, then set end_prologue_addr to the address of the | |
1752 | instruction immediately after the last one we scanned. */ | |
1753 | if (end_prologue_addr == 0) | |
1754 | end_prologue_addr = cur_pc; | |
1755 | ||
1756 | return end_prologue_addr; | |
eec63939 AC |
1757 | } |
1758 | ||
29639122 JB |
1759 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). |
1760 | Procedures that use the 32-bit instruction set are handled by the | |
1761 | mips_insn32 unwinder. */ | |
1762 | ||
1763 | static struct mips_frame_cache * | |
b8a22b94 | 1764 | mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache) |
eec63939 | 1765 | { |
29639122 | 1766 | struct mips_frame_cache *cache; |
eec63939 AC |
1767 | |
1768 | if ((*this_cache) != NULL) | |
1769 | return (*this_cache); | |
29639122 JB |
1770 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
1771 | (*this_cache) = cache; | |
b8a22b94 | 1772 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
eec63939 | 1773 | |
29639122 JB |
1774 | /* Analyze the function prologue. */ |
1775 | { | |
b8a22b94 | 1776 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 1777 | CORE_ADDR start_addr; |
eec63939 | 1778 | |
29639122 JB |
1779 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
1780 | if (start_addr == 0) | |
74ed0bb4 | 1781 | start_addr = heuristic_proc_start (get_frame_arch (this_frame), pc); |
29639122 JB |
1782 | /* We can't analyze the prologue if we couldn't find the begining |
1783 | of the function. */ | |
1784 | if (start_addr == 0) | |
1785 | return cache; | |
eec63939 | 1786 | |
b8a22b94 | 1787 | mips16_scan_prologue (start_addr, pc, this_frame, *this_cache); |
29639122 JB |
1788 | } |
1789 | ||
3e8c568d | 1790 | /* gdbarch_sp_regnum contains the value and not the address. */ |
72a155b4 | 1791 | trad_frame_set_value (cache->saved_regs, |
b8a22b94 DJ |
1792 | gdbarch_num_regs (get_frame_arch (this_frame)) |
1793 | + MIPS_SP_REGNUM, | |
72a155b4 | 1794 | cache->base); |
eec63939 | 1795 | |
29639122 | 1796 | return (*this_cache); |
eec63939 AC |
1797 | } |
1798 | ||
1799 | static void | |
b8a22b94 | 1800 | mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 | 1801 | struct frame_id *this_id) |
eec63939 | 1802 | { |
b8a22b94 | 1803 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 | 1804 | this_cache); |
b8a22b94 | 1805 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
eec63939 AC |
1806 | } |
1807 | ||
b8a22b94 DJ |
1808 | static struct value * |
1809 | mips_insn16_frame_prev_register (struct frame_info *this_frame, | |
1810 | void **this_cache, int regnum) | |
eec63939 | 1811 | { |
b8a22b94 | 1812 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 | 1813 | this_cache); |
b8a22b94 DJ |
1814 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
1815 | } | |
1816 | ||
1817 | static int | |
1818 | mips_insn16_frame_sniffer (const struct frame_unwind *self, | |
1819 | struct frame_info *this_frame, void **this_cache) | |
1820 | { | |
1821 | CORE_ADDR pc = get_frame_pc (this_frame); | |
1822 | if (mips_pc_is_mips16 (pc)) | |
1823 | return 1; | |
1824 | return 0; | |
eec63939 AC |
1825 | } |
1826 | ||
29639122 | 1827 | static const struct frame_unwind mips_insn16_frame_unwind = |
eec63939 AC |
1828 | { |
1829 | NORMAL_FRAME, | |
29639122 | 1830 | mips_insn16_frame_this_id, |
b8a22b94 DJ |
1831 | mips_insn16_frame_prev_register, |
1832 | NULL, | |
1833 | mips_insn16_frame_sniffer | |
eec63939 AC |
1834 | }; |
1835 | ||
eec63939 | 1836 | static CORE_ADDR |
b8a22b94 | 1837 | mips_insn16_frame_base_address (struct frame_info *this_frame, |
29639122 | 1838 | void **this_cache) |
eec63939 | 1839 | { |
b8a22b94 | 1840 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 JB |
1841 | this_cache); |
1842 | return info->base; | |
eec63939 AC |
1843 | } |
1844 | ||
29639122 | 1845 | static const struct frame_base mips_insn16_frame_base = |
eec63939 | 1846 | { |
29639122 JB |
1847 | &mips_insn16_frame_unwind, |
1848 | mips_insn16_frame_base_address, | |
1849 | mips_insn16_frame_base_address, | |
1850 | mips_insn16_frame_base_address | |
eec63939 AC |
1851 | }; |
1852 | ||
1853 | static const struct frame_base * | |
b8a22b94 | 1854 | mips_insn16_frame_base_sniffer (struct frame_info *this_frame) |
eec63939 | 1855 | { |
b8a22b94 DJ |
1856 | CORE_ADDR pc = get_frame_pc (this_frame); |
1857 | if (mips_pc_is_mips16 (pc)) | |
29639122 | 1858 | return &mips_insn16_frame_base; |
eec63939 AC |
1859 | else |
1860 | return NULL; | |
edfae063 AC |
1861 | } |
1862 | ||
29639122 JB |
1863 | /* Mark all the registers as unset in the saved_regs array |
1864 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
1865 | ||
74ed0bb4 MD |
1866 | static void |
1867 | reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache) | |
c906108c | 1868 | { |
29639122 JB |
1869 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
1870 | return; | |
1871 | ||
1872 | { | |
74ed0bb4 | 1873 | const int num_regs = gdbarch_num_regs (gdbarch); |
29639122 | 1874 | int i; |
64159455 | 1875 | |
29639122 JB |
1876 | for (i = 0; i < num_regs; i++) |
1877 | { | |
1878 | this_cache->saved_regs[i].addr = -1; | |
1879 | } | |
1880 | } | |
c906108c SS |
1881 | } |
1882 | ||
29639122 JB |
1883 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1884 | the associated FRAME_CACHE if not null. | |
1885 | Return the address of the first instruction past the prologue. */ | |
c906108c | 1886 | |
875e1767 | 1887 | static CORE_ADDR |
29639122 | 1888 | mips32_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
b8a22b94 | 1889 | struct frame_info *this_frame, |
29639122 | 1890 | struct mips_frame_cache *this_cache) |
c906108c | 1891 | { |
29639122 JB |
1892 | CORE_ADDR cur_pc; |
1893 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ | |
1894 | CORE_ADDR sp; | |
1895 | long frame_offset; | |
1896 | int frame_reg = MIPS_SP_REGNUM; | |
8fa9cfa1 | 1897 | |
29639122 JB |
1898 | CORE_ADDR end_prologue_addr = 0; |
1899 | int seen_sp_adjust = 0; | |
1900 | int load_immediate_bytes = 0; | |
b8a22b94 | 1901 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
7d1e6fb8 | 1902 | int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8); |
8fa9cfa1 | 1903 | |
29639122 | 1904 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
1905 | THIS_FRAME. */ |
1906 | if (this_frame != NULL) | |
1907 | sp = get_frame_register_signed (this_frame, | |
1908 | gdbarch_num_regs (gdbarch) | |
1909 | + MIPS_SP_REGNUM); | |
8fa9cfa1 | 1910 | else |
29639122 | 1911 | sp = 0; |
9022177c | 1912 | |
29639122 JB |
1913 | if (limit_pc > start_pc + 200) |
1914 | limit_pc = start_pc + 200; | |
9022177c | 1915 | |
29639122 | 1916 | restart: |
9022177c | 1917 | |
29639122 | 1918 | frame_offset = 0; |
95ac2dcf | 1919 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) |
9022177c | 1920 | { |
29639122 JB |
1921 | unsigned long inst, high_word, low_word; |
1922 | int reg; | |
9022177c | 1923 | |
29639122 JB |
1924 | /* Fetch the instruction. */ |
1925 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
9022177c | 1926 | |
29639122 JB |
1927 | /* Save some code by pre-extracting some useful fields. */ |
1928 | high_word = (inst >> 16) & 0xffff; | |
1929 | low_word = inst & 0xffff; | |
1930 | reg = high_word & 0x1f; | |
fe29b929 | 1931 | |
29639122 JB |
1932 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
1933 | || high_word == 0x23bd /* addi $sp,$sp,-i */ | |
1934 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
1935 | { | |
1936 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
1937 | frame_offset += 0x10000 - low_word; | |
1938 | else | |
1939 | /* Exit loop if a positive stack adjustment is found, which | |
1940 | usually means that the stack cleanup code in the function | |
1941 | epilogue is reached. */ | |
1942 | break; | |
1943 | seen_sp_adjust = 1; | |
1944 | } | |
7d1e6fb8 KB |
1945 | else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ |
1946 | && !regsize_is_64_bits) | |
29639122 | 1947 | { |
74ed0bb4 | 1948 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
29639122 | 1949 | } |
7d1e6fb8 KB |
1950 | else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ |
1951 | && regsize_is_64_bits) | |
29639122 JB |
1952 | { |
1953 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ | |
74ed0bb4 | 1954 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
29639122 JB |
1955 | } |
1956 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
1957 | { | |
1958 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
1959 | if ((long) low_word != frame_offset) | |
1960 | frame_addr = sp + low_word; | |
b8a22b94 | 1961 | else if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
1962 | { |
1963 | unsigned alloca_adjust; | |
a4b8ebc8 | 1964 | |
29639122 | 1965 | frame_reg = 30; |
b8a22b94 DJ |
1966 | frame_addr = get_frame_register_signed |
1967 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 1968 | |
29639122 JB |
1969 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
1970 | if (alloca_adjust > 0) | |
1971 | { | |
1972 | /* FP > SP + frame_size. This may be because of | |
1973 | an alloca or somethings similar. Fix sp to | |
1974 | "pre-alloca" value, and try again. */ | |
1975 | sp += alloca_adjust; | |
1976 | /* Need to reset the status of all registers. Otherwise, | |
1977 | we will hit a guard that prevents the new address | |
1978 | for each register to be recomputed during the second | |
1979 | pass. */ | |
74ed0bb4 | 1980 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
1981 | goto restart; |
1982 | } | |
1983 | } | |
1984 | } | |
1985 | /* move $30,$sp. With different versions of gas this will be either | |
1986 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
1987 | Accept any one of these. */ | |
1988 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
1989 | { | |
1990 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
b8a22b94 | 1991 | if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
1992 | { |
1993 | unsigned alloca_adjust; | |
c906108c | 1994 | |
29639122 | 1995 | frame_reg = 30; |
b8a22b94 DJ |
1996 | frame_addr = get_frame_register_signed |
1997 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 1998 | |
29639122 JB |
1999 | alloca_adjust = (unsigned) (frame_addr - sp); |
2000 | if (alloca_adjust > 0) | |
2001 | { | |
2002 | /* FP > SP + frame_size. This may be because of | |
2003 | an alloca or somethings similar. Fix sp to | |
2004 | "pre-alloca" value, and try again. */ | |
2005 | sp = frame_addr; | |
2006 | /* Need to reset the status of all registers. Otherwise, | |
2007 | we will hit a guard that prevents the new address | |
2008 | for each register to be recomputed during the second | |
2009 | pass. */ | |
74ed0bb4 | 2010 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
2011 | goto restart; |
2012 | } | |
2013 | } | |
2014 | } | |
7d1e6fb8 KB |
2015 | else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */ |
2016 | && !regsize_is_64_bits) | |
29639122 | 2017 | { |
74ed0bb4 | 2018 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + low_word); |
29639122 JB |
2019 | } |
2020 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | |
2021 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ | |
2022 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | |
2023 | || high_word == 0x3c1c /* lui $gp,n */ | |
2024 | || high_word == 0x279c /* addiu $gp,$gp,n */ | |
2025 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
2026 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | |
2027 | ) | |
2028 | { | |
2029 | /* These instructions are part of the prologue, but we don't | |
2030 | need to do anything special to handle them. */ | |
2031 | } | |
2032 | /* The instructions below load $at or $t0 with an immediate | |
2033 | value in preparation for a stack adjustment via | |
2034 | subu $sp,$sp,[$at,$t0]. These instructions could also | |
2035 | initialize a local variable, so we accept them only before | |
2036 | a stack adjustment instruction was seen. */ | |
2037 | else if (!seen_sp_adjust | |
2038 | && (high_word == 0x3c01 /* lui $at,n */ | |
2039 | || high_word == 0x3c08 /* lui $t0,n */ | |
2040 | || high_word == 0x3421 /* ori $at,$at,n */ | |
2041 | || high_word == 0x3508 /* ori $t0,$t0,n */ | |
2042 | || high_word == 0x3401 /* ori $at,$zero,n */ | |
2043 | || high_word == 0x3408 /* ori $t0,$zero,n */ | |
2044 | )) | |
2045 | { | |
95ac2dcf | 2046 | load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ |
29639122 JB |
2047 | } |
2048 | else | |
2049 | { | |
2050 | /* This instruction is not an instruction typically found | |
2051 | in a prologue, so we must have reached the end of the | |
2052 | prologue. */ | |
2053 | /* FIXME: brobecker/2004-10-10: Can't we just break out of this | |
2054 | loop now? Why would we need to continue scanning the function | |
2055 | instructions? */ | |
2056 | if (end_prologue_addr == 0) | |
2057 | end_prologue_addr = cur_pc; | |
2058 | } | |
a4b8ebc8 | 2059 | } |
c906108c | 2060 | |
29639122 JB |
2061 | if (this_cache != NULL) |
2062 | { | |
2063 | this_cache->base = | |
b8a22b94 DJ |
2064 | (get_frame_register_signed (this_frame, |
2065 | gdbarch_num_regs (gdbarch) + frame_reg) | |
29639122 JB |
2066 | + frame_offset); |
2067 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of | |
2068 | this assignment below, eventually. But it's still needed | |
2069 | for now. */ | |
72a155b4 UW |
2070 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
2071 | + mips_regnum (gdbarch)->pc] | |
2072 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) | |
f57d151a | 2073 | + MIPS_RA_REGNUM]; |
29639122 | 2074 | } |
c906108c | 2075 | |
29639122 JB |
2076 | /* If we didn't reach the end of the prologue when scanning the function |
2077 | instructions, then set end_prologue_addr to the address of the | |
2078 | instruction immediately after the last one we scanned. */ | |
2079 | /* brobecker/2004-10-10: I don't think this would ever happen, but | |
2080 | we may as well be careful and do our best if we have a null | |
2081 | end_prologue_addr. */ | |
2082 | if (end_prologue_addr == 0) | |
2083 | end_prologue_addr = cur_pc; | |
2084 | ||
2085 | /* In a frameless function, we might have incorrectly | |
2086 | skipped some load immediate instructions. Undo the skipping | |
2087 | if the load immediate was not followed by a stack adjustment. */ | |
2088 | if (load_immediate_bytes && !seen_sp_adjust) | |
2089 | end_prologue_addr -= load_immediate_bytes; | |
c906108c | 2090 | |
29639122 | 2091 | return end_prologue_addr; |
c906108c SS |
2092 | } |
2093 | ||
29639122 JB |
2094 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
2095 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
2096 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
2097 | unwinder. */ | |
c906108c | 2098 | |
29639122 | 2099 | static struct mips_frame_cache * |
b8a22b94 | 2100 | mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache) |
c906108c | 2101 | { |
29639122 | 2102 | struct mips_frame_cache *cache; |
c906108c | 2103 | |
29639122 JB |
2104 | if ((*this_cache) != NULL) |
2105 | return (*this_cache); | |
c5aa993b | 2106 | |
29639122 JB |
2107 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
2108 | (*this_cache) = cache; | |
b8a22b94 | 2109 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
c5aa993b | 2110 | |
29639122 JB |
2111 | /* Analyze the function prologue. */ |
2112 | { | |
b8a22b94 | 2113 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 2114 | CORE_ADDR start_addr; |
c906108c | 2115 | |
29639122 JB |
2116 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
2117 | if (start_addr == 0) | |
74ed0bb4 | 2118 | start_addr = heuristic_proc_start (get_frame_arch (this_frame), pc); |
29639122 JB |
2119 | /* We can't analyze the prologue if we couldn't find the begining |
2120 | of the function. */ | |
2121 | if (start_addr == 0) | |
2122 | return cache; | |
c5aa993b | 2123 | |
b8a22b94 | 2124 | mips32_scan_prologue (start_addr, pc, this_frame, *this_cache); |
29639122 JB |
2125 | } |
2126 | ||
3e8c568d | 2127 | /* gdbarch_sp_regnum contains the value and not the address. */ |
f57d151a | 2128 | trad_frame_set_value (cache->saved_regs, |
b8a22b94 DJ |
2129 | gdbarch_num_regs (get_frame_arch (this_frame)) |
2130 | + MIPS_SP_REGNUM, | |
f57d151a | 2131 | cache->base); |
c5aa993b | 2132 | |
29639122 | 2133 | return (*this_cache); |
c906108c SS |
2134 | } |
2135 | ||
29639122 | 2136 | static void |
b8a22b94 | 2137 | mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 | 2138 | struct frame_id *this_id) |
c906108c | 2139 | { |
b8a22b94 | 2140 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 2141 | this_cache); |
b8a22b94 | 2142 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
29639122 | 2143 | } |
c906108c | 2144 | |
b8a22b94 DJ |
2145 | static struct value * |
2146 | mips_insn32_frame_prev_register (struct frame_info *this_frame, | |
2147 | void **this_cache, int regnum) | |
29639122 | 2148 | { |
b8a22b94 | 2149 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 2150 | this_cache); |
b8a22b94 DJ |
2151 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
2152 | } | |
2153 | ||
2154 | static int | |
2155 | mips_insn32_frame_sniffer (const struct frame_unwind *self, | |
2156 | struct frame_info *this_frame, void **this_cache) | |
2157 | { | |
2158 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2159 | if (! mips_pc_is_mips16 (pc)) | |
2160 | return 1; | |
2161 | return 0; | |
c906108c SS |
2162 | } |
2163 | ||
29639122 JB |
2164 | static const struct frame_unwind mips_insn32_frame_unwind = |
2165 | { | |
2166 | NORMAL_FRAME, | |
2167 | mips_insn32_frame_this_id, | |
b8a22b94 DJ |
2168 | mips_insn32_frame_prev_register, |
2169 | NULL, | |
2170 | mips_insn32_frame_sniffer | |
29639122 | 2171 | }; |
c906108c | 2172 | |
1c645fec | 2173 | static CORE_ADDR |
b8a22b94 | 2174 | mips_insn32_frame_base_address (struct frame_info *this_frame, |
29639122 | 2175 | void **this_cache) |
c906108c | 2176 | { |
b8a22b94 | 2177 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 JB |
2178 | this_cache); |
2179 | return info->base; | |
2180 | } | |
c906108c | 2181 | |
29639122 JB |
2182 | static const struct frame_base mips_insn32_frame_base = |
2183 | { | |
2184 | &mips_insn32_frame_unwind, | |
2185 | mips_insn32_frame_base_address, | |
2186 | mips_insn32_frame_base_address, | |
2187 | mips_insn32_frame_base_address | |
2188 | }; | |
1c645fec | 2189 | |
29639122 | 2190 | static const struct frame_base * |
b8a22b94 | 2191 | mips_insn32_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 2192 | { |
b8a22b94 DJ |
2193 | CORE_ADDR pc = get_frame_pc (this_frame); |
2194 | if (! mips_pc_is_mips16 (pc)) | |
29639122 | 2195 | return &mips_insn32_frame_base; |
a65bbe44 | 2196 | else |
29639122 JB |
2197 | return NULL; |
2198 | } | |
a65bbe44 | 2199 | |
29639122 | 2200 | static struct trad_frame_cache * |
b8a22b94 | 2201 | mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache) |
29639122 JB |
2202 | { |
2203 | CORE_ADDR pc; | |
2204 | CORE_ADDR start_addr; | |
2205 | CORE_ADDR stack_addr; | |
2206 | struct trad_frame_cache *this_trad_cache; | |
b8a22b94 DJ |
2207 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2208 | int num_regs = gdbarch_num_regs (gdbarch); | |
c906108c | 2209 | |
29639122 JB |
2210 | if ((*this_cache) != NULL) |
2211 | return (*this_cache); | |
b8a22b94 | 2212 | this_trad_cache = trad_frame_cache_zalloc (this_frame); |
29639122 | 2213 | (*this_cache) = this_trad_cache; |
1c645fec | 2214 | |
29639122 | 2215 | /* The return address is in the link register. */ |
3e8c568d | 2216 | trad_frame_set_reg_realreg (this_trad_cache, |
72a155b4 | 2217 | gdbarch_pc_regnum (gdbarch), |
b8a22b94 | 2218 | num_regs + MIPS_RA_REGNUM); |
1c645fec | 2219 | |
29639122 JB |
2220 | /* Frame ID, since it's a frameless / stackless function, no stack |
2221 | space is allocated and SP on entry is the current SP. */ | |
b8a22b94 | 2222 | pc = get_frame_pc (this_frame); |
29639122 | 2223 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
b8a22b94 DJ |
2224 | stack_addr = get_frame_register_signed (this_frame, |
2225 | num_regs + MIPS_SP_REGNUM); | |
aa6c981f | 2226 | trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr)); |
1c645fec | 2227 | |
29639122 JB |
2228 | /* Assume that the frame's base is the same as the |
2229 | stack-pointer. */ | |
2230 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
c906108c | 2231 | |
29639122 JB |
2232 | return this_trad_cache; |
2233 | } | |
c906108c | 2234 | |
29639122 | 2235 | static void |
b8a22b94 | 2236 | mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 JB |
2237 | struct frame_id *this_id) |
2238 | { | |
2239 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 2240 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
2241 | trad_frame_get_id (this_trad_cache, this_id); |
2242 | } | |
c906108c | 2243 | |
b8a22b94 DJ |
2244 | static struct value * |
2245 | mips_stub_frame_prev_register (struct frame_info *this_frame, | |
2246 | void **this_cache, int regnum) | |
29639122 JB |
2247 | { |
2248 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 DJ |
2249 | = mips_stub_frame_cache (this_frame, this_cache); |
2250 | return trad_frame_get_register (this_trad_cache, this_frame, regnum); | |
29639122 | 2251 | } |
c906108c | 2252 | |
b8a22b94 DJ |
2253 | static int |
2254 | mips_stub_frame_sniffer (const struct frame_unwind *self, | |
2255 | struct frame_info *this_frame, void **this_cache) | |
29639122 | 2256 | { |
aa6c981f | 2257 | gdb_byte dummy[4]; |
979b38e0 | 2258 | struct obj_section *s; |
b8a22b94 | 2259 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
979b38e0 | 2260 | |
aa6c981f | 2261 | /* Use the stub unwinder for unreadable code. */ |
b8a22b94 DJ |
2262 | if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) |
2263 | return 1; | |
aa6c981f | 2264 | |
29639122 | 2265 | if (in_plt_section (pc, NULL)) |
b8a22b94 | 2266 | return 1; |
979b38e0 DJ |
2267 | |
2268 | /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */ | |
2269 | s = find_pc_section (pc); | |
2270 | ||
2271 | if (s != NULL | |
2272 | && strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section), | |
2273 | ".MIPS.stubs") == 0) | |
b8a22b94 | 2274 | return 1; |
979b38e0 | 2275 | |
b8a22b94 | 2276 | return 0; |
29639122 | 2277 | } |
c906108c | 2278 | |
b8a22b94 DJ |
2279 | static const struct frame_unwind mips_stub_frame_unwind = |
2280 | { | |
2281 | NORMAL_FRAME, | |
2282 | mips_stub_frame_this_id, | |
2283 | mips_stub_frame_prev_register, | |
2284 | NULL, | |
2285 | mips_stub_frame_sniffer | |
2286 | }; | |
2287 | ||
29639122 | 2288 | static CORE_ADDR |
b8a22b94 | 2289 | mips_stub_frame_base_address (struct frame_info *this_frame, |
29639122 JB |
2290 | void **this_cache) |
2291 | { | |
2292 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 2293 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
2294 | return trad_frame_get_this_base (this_trad_cache); |
2295 | } | |
0fce0821 | 2296 | |
29639122 JB |
2297 | static const struct frame_base mips_stub_frame_base = |
2298 | { | |
2299 | &mips_stub_frame_unwind, | |
2300 | mips_stub_frame_base_address, | |
2301 | mips_stub_frame_base_address, | |
2302 | mips_stub_frame_base_address | |
2303 | }; | |
2304 | ||
2305 | static const struct frame_base * | |
b8a22b94 | 2306 | mips_stub_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 2307 | { |
b8a22b94 | 2308 | if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL)) |
29639122 JB |
2309 | return &mips_stub_frame_base; |
2310 | else | |
2311 | return NULL; | |
2312 | } | |
2313 | ||
29639122 | 2314 | /* mips_addr_bits_remove - remove useless address bits */ |
65596487 | 2315 | |
29639122 | 2316 | static CORE_ADDR |
24568a2c | 2317 | mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) |
65596487 | 2318 | { |
24568a2c | 2319 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
29639122 JB |
2320 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) |
2321 | /* This hack is a work-around for existing boards using PMON, the | |
2322 | simulator, and any other 64-bit targets that doesn't have true | |
2323 | 64-bit addressing. On these targets, the upper 32 bits of | |
2324 | addresses are ignored by the hardware. Thus, the PC or SP are | |
2325 | likely to have been sign extended to all 1s by instruction | |
2326 | sequences that load 32-bit addresses. For example, a typical | |
2327 | piece of code that loads an address is this: | |
65596487 | 2328 | |
29639122 JB |
2329 | lui $r2, <upper 16 bits> |
2330 | ori $r2, <lower 16 bits> | |
65596487 | 2331 | |
29639122 JB |
2332 | But the lui sign-extends the value such that the upper 32 bits |
2333 | may be all 1s. The workaround is simply to mask off these | |
2334 | bits. In the future, gcc may be changed to support true 64-bit | |
2335 | addressing, and this masking will have to be disabled. */ | |
2336 | return addr &= 0xffffffffUL; | |
2337 | else | |
2338 | return addr; | |
65596487 JB |
2339 | } |
2340 | ||
3d5f6d12 DJ |
2341 | /* Instructions used during single-stepping of atomic sequences. */ |
2342 | #define LL_OPCODE 0x30 | |
2343 | #define LLD_OPCODE 0x34 | |
2344 | #define SC_OPCODE 0x38 | |
2345 | #define SCD_OPCODE 0x3c | |
2346 | ||
2347 | /* Checks for an atomic sequence of instructions beginning with a LL/LLD | |
2348 | instruction and ending with a SC/SCD instruction. If such a sequence | |
2349 | is found, attempt to step through it. A breakpoint is placed at the end of | |
2350 | the sequence. */ | |
2351 | ||
2352 | static int | |
2353 | deal_with_atomic_sequence (CORE_ADDR pc) | |
2354 | { | |
2355 | CORE_ADDR breaks[2] = {-1, -1}; | |
2356 | CORE_ADDR loc = pc; | |
2357 | CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ | |
2358 | unsigned long insn; | |
2359 | int insn_count; | |
2360 | int index; | |
2361 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
2362 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
2363 | ||
2364 | if (pc & 0x01) | |
2365 | return 0; | |
2366 | ||
2367 | insn = mips_fetch_instruction (loc); | |
2368 | /* Assume all atomic sequences start with a ll/lld instruction. */ | |
2369 | if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE) | |
2370 | return 0; | |
2371 | ||
2372 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" | |
2373 | instructions. */ | |
2374 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
2375 | { | |
2376 | int is_branch = 0; | |
2377 | loc += MIPS_INSN32_SIZE; | |
2378 | insn = mips_fetch_instruction (loc); | |
2379 | ||
2380 | /* Assume that there is at most one branch in the atomic | |
2381 | sequence. If a branch is found, put a breakpoint in its | |
2382 | destination address. */ | |
2383 | switch (itype_op (insn)) | |
2384 | { | |
2385 | case 0: /* SPECIAL */ | |
2386 | if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */ | |
2387 | return 0; /* fallback to the standard single-step code. */ | |
2388 | break; | |
2389 | case 1: /* REGIMM */ | |
2390 | is_branch = ((itype_rt (insn) & 0xc0) == 0); /* B{LT,GE}Z* */ | |
2391 | break; | |
2392 | case 2: /* J */ | |
2393 | case 3: /* JAL */ | |
2394 | return 0; /* fallback to the standard single-step code. */ | |
2395 | case 4: /* BEQ */ | |
2396 | case 5: /* BNE */ | |
2397 | case 6: /* BLEZ */ | |
2398 | case 7: /* BGTZ */ | |
2399 | case 20: /* BEQL */ | |
2400 | case 21: /* BNEL */ | |
2401 | case 22: /* BLEZL */ | |
2402 | case 23: /* BGTTL */ | |
2403 | is_branch = 1; | |
2404 | break; | |
2405 | case 17: /* COP1 */ | |
2406 | case 18: /* COP2 */ | |
2407 | case 19: /* COP3 */ | |
2408 | is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */ | |
2409 | break; | |
2410 | } | |
2411 | if (is_branch) | |
2412 | { | |
2413 | branch_bp = loc + mips32_relative_offset (insn) + 4; | |
2414 | if (last_breakpoint >= 1) | |
2415 | return 0; /* More than one branch found, fallback to the | |
2416 | standard single-step code. */ | |
2417 | breaks[1] = branch_bp; | |
2418 | last_breakpoint++; | |
2419 | } | |
2420 | ||
2421 | if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE) | |
2422 | break; | |
2423 | } | |
2424 | ||
2425 | /* Assume that the atomic sequence ends with a sc/scd instruction. */ | |
2426 | if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE) | |
2427 | return 0; | |
2428 | ||
2429 | loc += MIPS_INSN32_SIZE; | |
2430 | ||
2431 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
2432 | breaks[0] = loc; | |
2433 | ||
2434 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
2435 | placed (branch instruction's destination) in the atomic sequence */ | |
2436 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) | |
2437 | last_breakpoint = 0; | |
2438 | ||
2439 | /* Effectively inserts the breakpoints. */ | |
2440 | for (index = 0; index <= last_breakpoint; index++) | |
2441 | insert_single_step_breakpoint (breaks[index]); | |
2442 | ||
2443 | return 1; | |
2444 | } | |
2445 | ||
29639122 JB |
2446 | /* mips_software_single_step() is called just before we want to resume |
2447 | the inferior, if we want to single-step it but there is no hardware | |
2448 | or kernel single-step support (MIPS on GNU/Linux for example). We find | |
e0cd558a | 2449 | the target of the coming instruction and breakpoint it. */ |
29639122 | 2450 | |
e6590a1b | 2451 | int |
0b1b3e42 | 2452 | mips_software_single_step (struct frame_info *frame) |
c906108c | 2453 | { |
8181d85f | 2454 | CORE_ADDR pc, next_pc; |
65596487 | 2455 | |
0b1b3e42 | 2456 | pc = get_frame_pc (frame); |
3d5f6d12 DJ |
2457 | if (deal_with_atomic_sequence (pc)) |
2458 | return 1; | |
2459 | ||
0b1b3e42 | 2460 | next_pc = mips_next_pc (frame, pc); |
e6590a1b | 2461 | |
e0cd558a | 2462 | insert_single_step_breakpoint (next_pc); |
e6590a1b | 2463 | return 1; |
29639122 | 2464 | } |
a65bbe44 | 2465 | |
29639122 JB |
2466 | /* Test whether the PC points to the return instruction at the |
2467 | end of a function. */ | |
65596487 | 2468 | |
29639122 JB |
2469 | static int |
2470 | mips_about_to_return (CORE_ADDR pc) | |
2471 | { | |
0fe7e7c8 | 2472 | if (mips_pc_is_mips16 (pc)) |
29639122 JB |
2473 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler |
2474 | generates a "jr $ra"; other times it generates code to load | |
2475 | the return address from the stack to an accessible register (such | |
2476 | as $a3), then a "jr" using that register. This second case | |
2477 | is almost impossible to distinguish from an indirect jump | |
2478 | used for switch statements, so we don't even try. */ | |
2479 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
2480 | else | |
2481 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
2482 | } | |
c906108c | 2483 | |
c906108c | 2484 | |
29639122 JB |
2485 | /* This fencepost looks highly suspicious to me. Removing it also |
2486 | seems suspicious as it could affect remote debugging across serial | |
2487 | lines. */ | |
c906108c | 2488 | |
29639122 | 2489 | static CORE_ADDR |
74ed0bb4 | 2490 | heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 JB |
2491 | { |
2492 | CORE_ADDR start_pc; | |
2493 | CORE_ADDR fence; | |
2494 | int instlen; | |
2495 | int seen_adjsp = 0; | |
65596487 | 2496 | |
74ed0bb4 | 2497 | pc = gdbarch_addr_bits_remove (gdbarch, pc); |
29639122 JB |
2498 | start_pc = pc; |
2499 | fence = start_pc - heuristic_fence_post; | |
2500 | if (start_pc == 0) | |
2501 | return 0; | |
65596487 | 2502 | |
29639122 JB |
2503 | if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
2504 | fence = VM_MIN_ADDRESS; | |
65596487 | 2505 | |
95ac2dcf | 2506 | instlen = mips_pc_is_mips16 (pc) ? MIPS_INSN16_SIZE : MIPS_INSN32_SIZE; |
98b4dd94 | 2507 | |
29639122 JB |
2508 | /* search back for previous return */ |
2509 | for (start_pc -= instlen;; start_pc -= instlen) | |
2510 | if (start_pc < fence) | |
2511 | { | |
2512 | /* It's not clear to me why we reach this point when | |
2513 | stop_soon, but with this test, at least we | |
2514 | don't print out warnings for every child forked (eg, on | |
2515 | decstation). 22apr93 rich@cygnus.com. */ | |
2516 | if (stop_soon == NO_STOP_QUIETLY) | |
2517 | { | |
2518 | static int blurb_printed = 0; | |
98b4dd94 | 2519 | |
8a3fe4f8 | 2520 | warning (_("GDB can't find the start of the function at 0x%s."), |
29639122 JB |
2521 | paddr_nz (pc)); |
2522 | ||
2523 | if (!blurb_printed) | |
2524 | { | |
2525 | /* This actually happens frequently in embedded | |
2526 | development, when you first connect to a board | |
2527 | and your stack pointer and pc are nowhere in | |
2528 | particular. This message needs to give people | |
2529 | in that situation enough information to | |
2530 | determine that it's no big deal. */ | |
2531 | printf_filtered ("\n\ | |
2532 | GDB is unable to find the start of the function at 0x%s\n\ | |
2533 | and thus can't determine the size of that function's stack frame.\n\ | |
2534 | This means that GDB may be unable to access that stack frame, or\n\ | |
2535 | the frames below it.\n\ | |
2536 | This problem is most likely caused by an invalid program counter or\n\ | |
2537 | stack pointer.\n\ | |
2538 | However, if you think GDB should simply search farther back\n\ | |
2539 | from 0x%s for code which looks like the beginning of a\n\ | |
2540 | function, you can increase the range of the search using the `set\n\ | |
2541 | heuristic-fence-post' command.\n", paddr_nz (pc), paddr_nz (pc)); | |
2542 | blurb_printed = 1; | |
2543 | } | |
2544 | } | |
2545 | ||
2546 | return 0; | |
2547 | } | |
0fe7e7c8 | 2548 | else if (mips_pc_is_mips16 (start_pc)) |
29639122 JB |
2549 | { |
2550 | unsigned short inst; | |
2551 | ||
2552 | /* On MIPS16, any one of the following is likely to be the | |
2553 | start of a function: | |
193774b3 MR |
2554 | extend save |
2555 | save | |
29639122 JB |
2556 | entry |
2557 | addiu sp,-n | |
2558 | daddiu sp,-n | |
2559 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
2560 | inst = mips_fetch_instruction (start_pc); | |
193774b3 MR |
2561 | if ((inst & 0xff80) == 0x6480) /* save */ |
2562 | { | |
2563 | if (start_pc - instlen >= fence) | |
2564 | { | |
2565 | inst = mips_fetch_instruction (start_pc - instlen); | |
2566 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
2567 | start_pc -= instlen; | |
2568 | } | |
2569 | break; | |
2570 | } | |
2571 | else if (((inst & 0xf81f) == 0xe809 | |
2572 | && (inst & 0x700) != 0x700) /* entry */ | |
2573 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
2574 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
2575 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
29639122 JB |
2576 | break; |
2577 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
2578 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2579 | seen_adjsp = 1; | |
2580 | else | |
2581 | seen_adjsp = 0; | |
2582 | } | |
2583 | else if (mips_about_to_return (start_pc)) | |
2584 | { | |
4c7d22cb | 2585 | /* Skip return and its delay slot. */ |
95ac2dcf | 2586 | start_pc += 2 * MIPS_INSN32_SIZE; |
29639122 JB |
2587 | break; |
2588 | } | |
2589 | ||
2590 | return start_pc; | |
c906108c SS |
2591 | } |
2592 | ||
6c0d6680 DJ |
2593 | struct mips_objfile_private |
2594 | { | |
2595 | bfd_size_type size; | |
2596 | char *contents; | |
2597 | }; | |
2598 | ||
f09ded24 AC |
2599 | /* According to the current ABI, should the type be passed in a |
2600 | floating-point register (assuming that there is space)? When there | |
a1f5b845 | 2601 | is no FPU, FP are not even considered as possible candidates for |
f09ded24 AC |
2602 | FP registers and, consequently this returns false - forces FP |
2603 | arguments into integer registers. */ | |
2604 | ||
2605 | static int | |
74ed0bb4 MD |
2606 | fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode, |
2607 | struct type *arg_type) | |
f09ded24 AC |
2608 | { |
2609 | return ((typecode == TYPE_CODE_FLT | |
74ed0bb4 | 2610 | || (MIPS_EABI (gdbarch) |
6d82d43b AC |
2611 | && (typecode == TYPE_CODE_STRUCT |
2612 | || typecode == TYPE_CODE_UNION) | |
f09ded24 | 2613 | && TYPE_NFIELDS (arg_type) == 1 |
b2d6f210 MS |
2614 | && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0))) |
2615 | == TYPE_CODE_FLT)) | |
74ed0bb4 | 2616 | && MIPS_FPU_TYPE(gdbarch) != MIPS_FPU_NONE); |
f09ded24 AC |
2617 | } |
2618 | ||
49e790b0 DJ |
2619 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
2620 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
2621 | ||
2622 | static int | |
2623 | mips_type_needs_double_align (struct type *type) | |
2624 | { | |
2625 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2626 | |
49e790b0 DJ |
2627 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2628 | return 1; | |
2629 | else if (typecode == TYPE_CODE_STRUCT) | |
2630 | { | |
2631 | if (TYPE_NFIELDS (type) < 1) | |
2632 | return 0; | |
2633 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2634 | } | |
2635 | else if (typecode == TYPE_CODE_UNION) | |
2636 | { | |
361d1df0 | 2637 | int i, n; |
49e790b0 DJ |
2638 | |
2639 | n = TYPE_NFIELDS (type); | |
2640 | for (i = 0; i < n; i++) | |
2641 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2642 | return 1; | |
2643 | return 0; | |
2644 | } | |
2645 | return 0; | |
2646 | } | |
2647 | ||
dc604539 AC |
2648 | /* Adjust the address downward (direction of stack growth) so that it |
2649 | is correctly aligned for a new stack frame. */ | |
2650 | static CORE_ADDR | |
2651 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2652 | { | |
5b03f266 | 2653 | return align_down (addr, 16); |
dc604539 AC |
2654 | } |
2655 | ||
f7ab6ec6 | 2656 | static CORE_ADDR |
7d9b040b | 2657 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
2658 | struct regcache *regcache, CORE_ADDR bp_addr, |
2659 | int nargs, struct value **args, CORE_ADDR sp, | |
2660 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
2661 | { |
2662 | int argreg; | |
2663 | int float_argreg; | |
2664 | int argnum; | |
2665 | int len = 0; | |
2666 | int stack_offset = 0; | |
480d3dd2 | 2667 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 2668 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
1a69e1e4 | 2669 | int regsize = mips_abi_regsize (gdbarch); |
c906108c | 2670 | |
25ab4790 AC |
2671 | /* For shared libraries, "t9" needs to point at the function |
2672 | address. */ | |
4c7d22cb | 2673 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
2674 | |
2675 | /* Set the return address register to point to the entry point of | |
2676 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 2677 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 2678 | |
c906108c | 2679 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2680 | are properly aligned. The stack has to be at least 64-bit |
2681 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2682 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2683 | aligned, so we round to this widest known alignment. */ | |
2684 | ||
5b03f266 AC |
2685 | sp = align_down (sp, 16); |
2686 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 2687 | |
46e0f506 | 2688 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2689 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2690 | passed in registers, but that's OK. */ |
c906108c | 2691 | for (argnum = 0; argnum < nargs; argnum++) |
1a69e1e4 | 2692 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize); |
5b03f266 | 2693 | sp -= align_up (len, 16); |
c906108c | 2694 | |
9ace0497 | 2695 | if (mips_debug) |
6d82d43b | 2696 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
2697 | "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n", |
2698 | paddr_nz (sp), (long) align_up (len, 16)); | |
9ace0497 | 2699 | |
c906108c | 2700 | /* Initialize the integer and float register pointers. */ |
4c7d22cb | 2701 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 2702 | float_argreg = mips_fpa0_regnum (gdbarch); |
c906108c | 2703 | |
46e0f506 | 2704 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2705 | if (struct_return) |
9ace0497 AC |
2706 | { |
2707 | if (mips_debug) | |
2708 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2709 | "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 2710 | argreg, paddr_nz (struct_addr)); |
9c9acae0 | 2711 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
9ace0497 | 2712 | } |
c906108c SS |
2713 | |
2714 | /* Now load as many as possible of the first arguments into | |
2715 | registers, and push the rest onto the stack. Loop thru args | |
2716 | from first to last. */ | |
2717 | for (argnum = 0; argnum < nargs; argnum++) | |
2718 | { | |
47a35522 MK |
2719 | const gdb_byte *val; |
2720 | gdb_byte valbuf[MAX_REGISTER_SIZE]; | |
ea7c478f | 2721 | struct value *arg = args[argnum]; |
4991999e | 2722 | struct type *arg_type = check_typedef (value_type (arg)); |
c906108c SS |
2723 | int len = TYPE_LENGTH (arg_type); |
2724 | enum type_code typecode = TYPE_CODE (arg_type); | |
2725 | ||
9ace0497 AC |
2726 | if (mips_debug) |
2727 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2728 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 2729 | argnum + 1, len, (int) typecode); |
9ace0497 | 2730 | |
c906108c | 2731 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 2732 | reference. */ |
1a69e1e4 | 2733 | if (len > regsize |
9ace0497 | 2734 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 2735 | { |
1a69e1e4 | 2736 | store_unsigned_integer (valbuf, regsize, VALUE_ADDRESS (arg)); |
c906108c | 2737 | typecode = TYPE_CODE_PTR; |
1a69e1e4 | 2738 | len = regsize; |
c906108c | 2739 | val = valbuf; |
9ace0497 AC |
2740 | if (mips_debug) |
2741 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
2742 | } |
2743 | else | |
47a35522 | 2744 | val = value_contents (arg); |
c906108c SS |
2745 | |
2746 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
2747 | even-numbered floating point register. Round the FP register |
2748 | up before the check to see if there are any FP registers | |
46e0f506 MS |
2749 | left. Non MIPS_EABI targets also pass the FP in the integer |
2750 | registers so also round up normal registers. */ | |
74ed0bb4 | 2751 | if (regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type)) |
acdb74a0 AC |
2752 | { |
2753 | if ((float_argreg & 1)) | |
2754 | float_argreg++; | |
2755 | } | |
c906108c SS |
2756 | |
2757 | /* Floating point arguments passed in registers have to be | |
2758 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2759 | are passed in register pairs; the even register gets |
2760 | the low word, and the odd register gets the high word. | |
2761 | On non-EABI processors, the first two floating point arguments are | |
2762 | also copied to general registers, because MIPS16 functions | |
2763 | don't use float registers for arguments. This duplication of | |
2764 | arguments in general registers can't hurt non-MIPS16 functions | |
2765 | because those registers are normally skipped. */ | |
1012bd0e EZ |
2766 | /* MIPS_EABI squeezes a struct that contains a single floating |
2767 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 2768 | stack. */ |
74ed0bb4 MD |
2769 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
2770 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
c906108c | 2771 | { |
6da397e0 KB |
2772 | /* EABI32 will pass doubles in consecutive registers, even on |
2773 | 64-bit cores. At one time, we used to check the size of | |
2774 | `float_argreg' to determine whether or not to pass doubles | |
2775 | in consecutive registers, but this is not sufficient for | |
2776 | making the ABI determination. */ | |
2777 | if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) | |
c906108c | 2778 | { |
72a155b4 | 2779 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 2780 | == BFD_ENDIAN_BIG ? 4 : 0; |
c906108c SS |
2781 | unsigned long regval; |
2782 | ||
2783 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 2784 | regval = extract_unsigned_integer (val + low_offset, 4); |
9ace0497 | 2785 | if (mips_debug) |
acdb74a0 | 2786 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2787 | float_argreg, phex (regval, 4)); |
9c9acae0 | 2788 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
c906108c SS |
2789 | |
2790 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 2791 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
9ace0497 | 2792 | if (mips_debug) |
acdb74a0 | 2793 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2794 | float_argreg, phex (regval, 4)); |
9c9acae0 | 2795 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
c906108c SS |
2796 | } |
2797 | else | |
2798 | { | |
2799 | /* This is a floating point value that fits entirely | |
2800 | in a single register. */ | |
53a5351d | 2801 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 2802 | above to ensure that it is even register aligned. */ |
9ace0497 AC |
2803 | LONGEST regval = extract_unsigned_integer (val, len); |
2804 | if (mips_debug) | |
acdb74a0 | 2805 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2806 | float_argreg, phex (regval, len)); |
9c9acae0 | 2807 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
c906108c SS |
2808 | } |
2809 | } | |
2810 | else | |
2811 | { | |
2812 | /* Copy the argument to general registers or the stack in | |
2813 | register-sized pieces. Large arguments are split between | |
2814 | registers and stack. */ | |
1a69e1e4 DJ |
2815 | /* Note: structs whose size is not a multiple of regsize |
2816 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
2817 | them in registers where gcc sometimes puts them on the |
2818 | stack. For maximum compatibility, we will put them in | |
2819 | both places. */ | |
1a69e1e4 | 2820 | int odd_sized_struct = (len > regsize && len % regsize != 0); |
46e0f506 | 2821 | |
f09ded24 | 2822 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 2823 | register are only written to memory. */ |
c906108c SS |
2824 | while (len > 0) |
2825 | { | |
ebafbe83 | 2826 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 2827 | int stack_used_p = 0; |
1a69e1e4 | 2828 | int partial_len = (len < regsize ? len : regsize); |
c906108c | 2829 | |
acdb74a0 AC |
2830 | if (mips_debug) |
2831 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2832 | partial_len); | |
2833 | ||
566f0f7a | 2834 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 2835 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
f09ded24 | 2836 | || odd_sized_struct |
74ed0bb4 | 2837 | || fp_register_arg_p (gdbarch, typecode, arg_type)) |
c906108c | 2838 | { |
c906108c SS |
2839 | /* Should shorter than int integer values be |
2840 | promoted to int before being stored? */ | |
c906108c | 2841 | int longword_offset = 0; |
9ace0497 | 2842 | CORE_ADDR addr; |
566f0f7a | 2843 | stack_used_p = 1; |
72a155b4 | 2844 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
7a292a7a | 2845 | { |
1a69e1e4 | 2846 | if (regsize == 8 |
480d3dd2 AC |
2847 | && (typecode == TYPE_CODE_INT |
2848 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 2849 | || typecode == TYPE_CODE_FLT) && len <= 4) |
1a69e1e4 | 2850 | longword_offset = regsize - len; |
480d3dd2 AC |
2851 | else if ((typecode == TYPE_CODE_STRUCT |
2852 | || typecode == TYPE_CODE_UNION) | |
1a69e1e4 DJ |
2853 | && TYPE_LENGTH (arg_type) < regsize) |
2854 | longword_offset = regsize - len; | |
7a292a7a | 2855 | } |
c5aa993b | 2856 | |
9ace0497 AC |
2857 | if (mips_debug) |
2858 | { | |
cb3d25d1 MS |
2859 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", |
2860 | paddr_nz (stack_offset)); | |
2861 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
2862 | paddr_nz (longword_offset)); | |
9ace0497 | 2863 | } |
361d1df0 | 2864 | |
9ace0497 AC |
2865 | addr = sp + stack_offset + longword_offset; |
2866 | ||
2867 | if (mips_debug) | |
2868 | { | |
2869 | int i; | |
6d82d43b | 2870 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 | 2871 | paddr_nz (addr)); |
9ace0497 AC |
2872 | for (i = 0; i < partial_len; i++) |
2873 | { | |
6d82d43b | 2874 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 2875 | val[i] & 0xff); |
9ace0497 AC |
2876 | } |
2877 | } | |
2878 | write_memory (addr, val, partial_len); | |
c906108c SS |
2879 | } |
2880 | ||
f09ded24 AC |
2881 | /* Note!!! This is NOT an else clause. Odd sized |
2882 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 2883 | arguments will not. */ |
566f0f7a | 2884 | /* Write this portion of the argument to a general |
6d82d43b | 2885 | purpose register. */ |
74ed0bb4 MD |
2886 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch) |
2887 | && !fp_register_arg_p (gdbarch, typecode, arg_type)) | |
c906108c | 2888 | { |
6d82d43b AC |
2889 | LONGEST regval = |
2890 | extract_unsigned_integer (val, partial_len); | |
c906108c | 2891 | |
9ace0497 | 2892 | if (mips_debug) |
acdb74a0 | 2893 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 2894 | argreg, |
1a69e1e4 | 2895 | phex (regval, regsize)); |
9c9acae0 | 2896 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
c906108c | 2897 | argreg++; |
c906108c | 2898 | } |
c5aa993b | 2899 | |
c906108c SS |
2900 | len -= partial_len; |
2901 | val += partial_len; | |
2902 | ||
566f0f7a | 2903 | /* Compute the the offset into the stack at which we |
6d82d43b | 2904 | will copy the next parameter. |
566f0f7a | 2905 | |
566f0f7a | 2906 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 2907 | only needs to be adjusted when it has been used. */ |
c906108c | 2908 | |
46e0f506 | 2909 | if (stack_used_p) |
1a69e1e4 | 2910 | stack_offset += align_up (partial_len, regsize); |
c906108c SS |
2911 | } |
2912 | } | |
9ace0497 AC |
2913 | if (mips_debug) |
2914 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
2915 | } |
2916 | ||
f10683bb | 2917 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 2918 | |
0f71a2f6 JM |
2919 | /* Return adjusted stack pointer. */ |
2920 | return sp; | |
2921 | } | |
2922 | ||
a1f5b845 | 2923 | /* Determine the return value convention being used. */ |
6d82d43b | 2924 | |
9c8fdbfa | 2925 | static enum return_value_convention |
c055b101 | 2926 | mips_eabi_return_value (struct gdbarch *gdbarch, struct type *func_type, |
9c8fdbfa | 2927 | struct type *type, struct regcache *regcache, |
47a35522 | 2928 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 2929 | { |
609ba780 JM |
2930 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2931 | int fp_return_type = 0; | |
2932 | int offset, regnum, xfer; | |
2933 | ||
9c8fdbfa AC |
2934 | if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
2935 | return RETURN_VALUE_STRUCT_CONVENTION; | |
609ba780 JM |
2936 | |
2937 | /* Floating point type? */ | |
2938 | if (tdep->mips_fpu_type != MIPS_FPU_NONE) | |
2939 | { | |
2940 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2941 | fp_return_type = 1; | |
2942 | /* Structs with a single field of float type | |
2943 | are returned in a floating point register. */ | |
2944 | if ((TYPE_CODE (type) == TYPE_CODE_STRUCT | |
2945 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
2946 | && TYPE_NFIELDS (type) == 1) | |
2947 | { | |
2948 | struct type *fieldtype = TYPE_FIELD_TYPE (type, 0); | |
2949 | ||
2950 | if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT) | |
2951 | fp_return_type = 1; | |
2952 | } | |
2953 | } | |
2954 | ||
2955 | if (fp_return_type) | |
2956 | { | |
2957 | /* A floating-point value belongs in the least significant part | |
2958 | of FP0/FP1. */ | |
2959 | if (mips_debug) | |
2960 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
2961 | regnum = mips_regnum (gdbarch)->fp0; | |
2962 | } | |
2963 | else | |
2964 | { | |
2965 | /* An integer value goes in V0/V1. */ | |
2966 | if (mips_debug) | |
2967 | fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n"); | |
2968 | regnum = MIPS_V0_REGNUM; | |
2969 | } | |
2970 | for (offset = 0; | |
2971 | offset < TYPE_LENGTH (type); | |
2972 | offset += mips_abi_regsize (gdbarch), regnum++) | |
2973 | { | |
2974 | xfer = mips_abi_regsize (gdbarch); | |
2975 | if (offset + xfer > TYPE_LENGTH (type)) | |
2976 | xfer = TYPE_LENGTH (type) - offset; | |
2977 | mips_xfer_register (gdbarch, regcache, | |
2978 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
2979 | gdbarch_byte_order (gdbarch), readbuf, writebuf, | |
2980 | offset); | |
2981 | } | |
2982 | ||
9c8fdbfa | 2983 | return RETURN_VALUE_REGISTER_CONVENTION; |
6d82d43b AC |
2984 | } |
2985 | ||
6d82d43b AC |
2986 | |
2987 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 2988 | |
8d26208a DJ |
2989 | /* Search for a naturally aligned double at OFFSET inside a struct |
2990 | ARG_TYPE. The N32 / N64 ABIs pass these in floating point | |
2991 | registers. */ | |
2992 | ||
2993 | static int | |
74ed0bb4 MD |
2994 | mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type, |
2995 | int offset) | |
8d26208a DJ |
2996 | { |
2997 | int i; | |
2998 | ||
2999 | if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT) | |
3000 | return 0; | |
3001 | ||
74ed0bb4 | 3002 | if (MIPS_FPU_TYPE (gdbarch) != MIPS_FPU_DOUBLE) |
8d26208a DJ |
3003 | return 0; |
3004 | ||
3005 | if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE) | |
3006 | return 0; | |
3007 | ||
3008 | for (i = 0; i < TYPE_NFIELDS (arg_type); i++) | |
3009 | { | |
3010 | int pos; | |
3011 | struct type *field_type; | |
3012 | ||
3013 | /* We're only looking at normal fields. */ | |
3014 | if (TYPE_FIELD_STATIC (arg_type, i) | |
3015 | || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0) | |
3016 | continue; | |
3017 | ||
3018 | /* If we have gone past the offset, there is no double to pass. */ | |
3019 | pos = TYPE_FIELD_BITPOS (arg_type, i) / 8; | |
3020 | if (pos > offset) | |
3021 | return 0; | |
3022 | ||
3023 | field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i)); | |
3024 | ||
3025 | /* If this field is entirely before the requested offset, go | |
3026 | on to the next one. */ | |
3027 | if (pos + TYPE_LENGTH (field_type) <= offset) | |
3028 | continue; | |
3029 | ||
3030 | /* If this is our special aligned double, we can stop. */ | |
3031 | if (TYPE_CODE (field_type) == TYPE_CODE_FLT | |
3032 | && TYPE_LENGTH (field_type) == MIPS64_REGSIZE) | |
3033 | return 1; | |
3034 | ||
3035 | /* This field starts at or before the requested offset, and | |
3036 | overlaps it. If it is a structure, recurse inwards. */ | |
74ed0bb4 | 3037 | return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos); |
8d26208a DJ |
3038 | } |
3039 | ||
3040 | return 0; | |
3041 | } | |
3042 | ||
f7ab6ec6 | 3043 | static CORE_ADDR |
7d9b040b | 3044 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3045 | struct regcache *regcache, CORE_ADDR bp_addr, |
3046 | int nargs, struct value **args, CORE_ADDR sp, | |
3047 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
3048 | { |
3049 | int argreg; | |
3050 | int float_argreg; | |
3051 | int argnum; | |
3052 | int len = 0; | |
3053 | int stack_offset = 0; | |
480d3dd2 | 3054 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 3055 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 3056 | |
25ab4790 AC |
3057 | /* For shared libraries, "t9" needs to point at the function |
3058 | address. */ | |
4c7d22cb | 3059 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
3060 | |
3061 | /* Set the return address register to point to the entry point of | |
3062 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3063 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 3064 | |
cb3d25d1 MS |
3065 | /* First ensure that the stack and structure return address (if any) |
3066 | are properly aligned. The stack has to be at least 64-bit | |
3067 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3068 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3069 | aligned, so we round to this widest known alignment. */ | |
3070 | ||
5b03f266 AC |
3071 | sp = align_down (sp, 16); |
3072 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
3073 | |
3074 | /* Now make space on the stack for the args. */ | |
3075 | for (argnum = 0; argnum < nargs; argnum++) | |
1a69e1e4 | 3076 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE); |
5b03f266 | 3077 | sp -= align_up (len, 16); |
cb3d25d1 MS |
3078 | |
3079 | if (mips_debug) | |
6d82d43b | 3080 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3081 | "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n", |
3082 | paddr_nz (sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
3083 | |
3084 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3085 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 3086 | float_argreg = mips_fpa0_regnum (gdbarch); |
cb3d25d1 | 3087 | |
46e0f506 | 3088 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
3089 | if (struct_return) |
3090 | { | |
3091 | if (mips_debug) | |
3092 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3093 | "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 3094 | argreg, paddr_nz (struct_addr)); |
9c9acae0 | 3095 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
cb3d25d1 MS |
3096 | } |
3097 | ||
3098 | /* Now load as many as possible of the first arguments into | |
3099 | registers, and push the rest onto the stack. Loop thru args | |
3100 | from first to last. */ | |
3101 | for (argnum = 0; argnum < nargs; argnum++) | |
3102 | { | |
47a35522 | 3103 | const gdb_byte *val; |
cb3d25d1 | 3104 | struct value *arg = args[argnum]; |
4991999e | 3105 | struct type *arg_type = check_typedef (value_type (arg)); |
cb3d25d1 MS |
3106 | int len = TYPE_LENGTH (arg_type); |
3107 | enum type_code typecode = TYPE_CODE (arg_type); | |
3108 | ||
3109 | if (mips_debug) | |
3110 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3111 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
3112 | argnum + 1, len, (int) typecode); |
3113 | ||
47a35522 | 3114 | val = value_contents (arg); |
cb3d25d1 | 3115 | |
5b68030f JM |
3116 | /* A 128-bit long double value requires an even-odd pair of |
3117 | floating-point registers. */ | |
3118 | if (len == 16 | |
3119 | && fp_register_arg_p (gdbarch, typecode, arg_type) | |
3120 | && (float_argreg & 1)) | |
3121 | { | |
3122 | float_argreg++; | |
3123 | argreg++; | |
3124 | } | |
3125 | ||
74ed0bb4 MD |
3126 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
3127 | && argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) | |
cb3d25d1 MS |
3128 | { |
3129 | /* This is a floating point value that fits entirely | |
5b68030f JM |
3130 | in a single register or a pair of registers. */ |
3131 | int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE); | |
3132 | LONGEST regval = extract_unsigned_integer (val, reglen); | |
cb3d25d1 MS |
3133 | if (mips_debug) |
3134 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5b68030f | 3135 | float_argreg, phex (regval, reglen)); |
8d26208a | 3136 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); |
cb3d25d1 MS |
3137 | |
3138 | if (mips_debug) | |
3139 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5b68030f | 3140 | argreg, phex (regval, reglen)); |
9c9acae0 | 3141 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a DJ |
3142 | float_argreg++; |
3143 | argreg++; | |
5b68030f JM |
3144 | if (len == 16) |
3145 | { | |
3146 | regval = extract_unsigned_integer (val + reglen, reglen); | |
3147 | if (mips_debug) | |
3148 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3149 | float_argreg, phex (regval, reglen)); | |
3150 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); | |
3151 | ||
3152 | if (mips_debug) | |
3153 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3154 | argreg, phex (regval, reglen)); | |
3155 | regcache_cooked_write_unsigned (regcache, argreg, regval); | |
3156 | float_argreg++; | |
3157 | argreg++; | |
3158 | } | |
cb3d25d1 MS |
3159 | } |
3160 | else | |
3161 | { | |
3162 | /* Copy the argument to general registers or the stack in | |
3163 | register-sized pieces. Large arguments are split between | |
3164 | registers and stack. */ | |
ab2e1992 MR |
3165 | /* For N32/N64, structs, unions, or other composite types are |
3166 | treated as a sequence of doublewords, and are passed in integer | |
3167 | or floating point registers as though they were simple scalar | |
3168 | parameters to the extent that they fit, with any excess on the | |
3169 | stack packed according to the normal memory layout of the | |
3170 | object. | |
3171 | The caller does not reserve space for the register arguments; | |
3172 | the callee is responsible for reserving it if required. */ | |
cb3d25d1 | 3173 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3174 | register are only written to memory. */ |
cb3d25d1 MS |
3175 | while (len > 0) |
3176 | { | |
ad018eee | 3177 | /* Remember if the argument was written to the stack. */ |
cb3d25d1 | 3178 | int stack_used_p = 0; |
1a69e1e4 | 3179 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
cb3d25d1 MS |
3180 | |
3181 | if (mips_debug) | |
3182 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3183 | partial_len); | |
3184 | ||
74ed0bb4 MD |
3185 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
3186 | gdb_assert (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)); | |
8d26208a | 3187 | |
cb3d25d1 | 3188 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 3189 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 MS |
3190 | { |
3191 | /* Should shorter than int integer values be | |
3192 | promoted to int before being stored? */ | |
3193 | int longword_offset = 0; | |
3194 | CORE_ADDR addr; | |
3195 | stack_used_p = 1; | |
72a155b4 | 3196 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
cb3d25d1 | 3197 | { |
1a69e1e4 | 3198 | if ((typecode == TYPE_CODE_INT |
5b68030f | 3199 | || typecode == TYPE_CODE_PTR) |
1a69e1e4 DJ |
3200 | && len <= 4) |
3201 | longword_offset = MIPS64_REGSIZE - len; | |
cb3d25d1 MS |
3202 | } |
3203 | ||
3204 | if (mips_debug) | |
3205 | { | |
3206 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3207 | paddr_nz (stack_offset)); | |
3208 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3209 | paddr_nz (longword_offset)); | |
3210 | } | |
3211 | ||
3212 | addr = sp + stack_offset + longword_offset; | |
3213 | ||
3214 | if (mips_debug) | |
3215 | { | |
3216 | int i; | |
6d82d43b | 3217 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 MS |
3218 | paddr_nz (addr)); |
3219 | for (i = 0; i < partial_len; i++) | |
3220 | { | |
6d82d43b | 3221 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
3222 | val[i] & 0xff); |
3223 | } | |
3224 | } | |
3225 | write_memory (addr, val, partial_len); | |
3226 | } | |
3227 | ||
3228 | /* Note!!! This is NOT an else clause. Odd sized | |
8d26208a | 3229 | structs may go thru BOTH paths. */ |
cb3d25d1 | 3230 | /* Write this portion of the argument to a general |
6d82d43b | 3231 | purpose register. */ |
74ed0bb4 | 3232 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 | 3233 | { |
5863b5d5 MR |
3234 | LONGEST regval; |
3235 | ||
3236 | /* Sign extend pointers, 32-bit integers and signed | |
3237 | 16-bit and 8-bit integers; everything else is taken | |
3238 | as is. */ | |
3239 | ||
3240 | if ((partial_len == 4 | |
3241 | && (typecode == TYPE_CODE_PTR | |
3242 | || typecode == TYPE_CODE_INT)) | |
3243 | || (partial_len < 4 | |
3244 | && typecode == TYPE_CODE_INT | |
3245 | && !TYPE_UNSIGNED (arg_type))) | |
3246 | regval = extract_signed_integer (val, partial_len); | |
3247 | else | |
3248 | regval = extract_unsigned_integer (val, partial_len); | |
cb3d25d1 MS |
3249 | |
3250 | /* A non-floating-point argument being passed in a | |
3251 | general register. If a struct or union, and if | |
3252 | the remaining length is smaller than the register | |
3253 | size, we have to adjust the register value on | |
3254 | big endian targets. | |
3255 | ||
3256 | It does not seem to be necessary to do the | |
1a69e1e4 | 3257 | same for integral types. */ |
cb3d25d1 | 3258 | |
72a155b4 | 3259 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3260 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
3261 | && (typecode == TYPE_CODE_STRUCT |
3262 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3263 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 3264 | * TARGET_CHAR_BIT); |
cb3d25d1 MS |
3265 | |
3266 | if (mips_debug) | |
3267 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3268 | argreg, | |
1a69e1e4 | 3269 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 3270 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a | 3271 | |
74ed0bb4 | 3272 | if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type, |
8d26208a DJ |
3273 | TYPE_LENGTH (arg_type) - len)) |
3274 | { | |
3275 | if (mips_debug) | |
3276 | fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s", | |
3277 | float_argreg, | |
3278 | phex (regval, MIPS64_REGSIZE)); | |
3279 | regcache_cooked_write_unsigned (regcache, float_argreg, | |
3280 | regval); | |
3281 | } | |
3282 | ||
3283 | float_argreg++; | |
cb3d25d1 MS |
3284 | argreg++; |
3285 | } | |
3286 | ||
3287 | len -= partial_len; | |
3288 | val += partial_len; | |
3289 | ||
3290 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3291 | will copy the next parameter. |
cb3d25d1 MS |
3292 | |
3293 | In N32 (N64?), the stack_offset only needs to be | |
3294 | adjusted when it has been used. */ | |
3295 | ||
3296 | if (stack_used_p) | |
1a69e1e4 | 3297 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
cb3d25d1 MS |
3298 | } |
3299 | } | |
3300 | if (mips_debug) | |
3301 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3302 | } | |
3303 | ||
f10683bb | 3304 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3305 | |
cb3d25d1 MS |
3306 | /* Return adjusted stack pointer. */ |
3307 | return sp; | |
3308 | } | |
3309 | ||
6d82d43b | 3310 | static enum return_value_convention |
c055b101 | 3311 | mips_n32n64_return_value (struct gdbarch *gdbarch, struct type *func_type, |
6d82d43b | 3312 | struct type *type, struct regcache *regcache, |
47a35522 | 3313 | gdb_byte *readbuf, const gdb_byte *writebuf) |
ebafbe83 | 3314 | { |
72a155b4 | 3315 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
b18bb924 MR |
3316 | |
3317 | /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004 | |
3318 | ||
3319 | Function results are returned in $2 (and $3 if needed), or $f0 (and $f2 | |
3320 | if needed), as appropriate for the type. Composite results (struct, | |
3321 | union, or array) are returned in $2/$f0 and $3/$f2 according to the | |
3322 | following rules: | |
3323 | ||
3324 | * A struct with only one or two floating point fields is returned in $f0 | |
3325 | (and $f2 if necessary). This is a generalization of the Fortran COMPLEX | |
3326 | case. | |
3327 | ||
3328 | * Any other struct or union results of at most 128 bits are returned in | |
3329 | $2 (first 64 bits) and $3 (remainder, if necessary). | |
3330 | ||
3331 | * Larger composite results are handled by converting the function to a | |
3332 | procedure with an implicit first parameter, which is a pointer to an area | |
3333 | reserved by the caller to receive the result. [The o32-bit ABI requires | |
3334 | that all composite results be handled by conversion to implicit first | |
3335 | parameters. The MIPS/SGI Fortran implementation has always made a | |
3336 | specific exception to return COMPLEX results in the floating point | |
3337 | registers.] */ | |
3338 | ||
3339 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY | |
1a69e1e4 | 3340 | || TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE) |
6d82d43b | 3341 | return RETURN_VALUE_STRUCT_CONVENTION; |
d05f6826 DJ |
3342 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3343 | && TYPE_LENGTH (type) == 16 | |
3344 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3345 | { | |
3346 | /* A 128-bit floating-point value fills both $f0 and $f2. The | |
3347 | two registers are used in the same as memory order, so the | |
3348 | eight bytes with the lower memory address are in $f0. */ | |
3349 | if (mips_debug) | |
3350 | fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n"); | |
ba32f989 | 3351 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3352 | gdbarch_num_regs (gdbarch) |
3353 | + mips_regnum (gdbarch)->fp0, | |
3354 | 8, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3355 | readbuf, writebuf, 0); |
ba32f989 | 3356 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3357 | gdbarch_num_regs (gdbarch) |
3358 | + mips_regnum (gdbarch)->fp0 + 2, | |
3359 | 8, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3360 | readbuf ? readbuf + 8 : readbuf, |
d05f6826 DJ |
3361 | writebuf ? writebuf + 8 : writebuf, 0); |
3362 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3363 | } | |
6d82d43b AC |
3364 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3365 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3366 | { | |
59aa1faa | 3367 | /* A single or double floating-point value that fits in FP0. */ |
6d82d43b AC |
3368 | if (mips_debug) |
3369 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 3370 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3371 | gdbarch_num_regs (gdbarch) |
3372 | + mips_regnum (gdbarch)->fp0, | |
6d82d43b | 3373 | TYPE_LENGTH (type), |
72a155b4 | 3374 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3375 | readbuf, writebuf, 0); |
6d82d43b AC |
3376 | return RETURN_VALUE_REGISTER_CONVENTION; |
3377 | } | |
3378 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3379 | && TYPE_NFIELDS (type) <= 2 | |
3380 | && TYPE_NFIELDS (type) >= 1 | |
3381 | && ((TYPE_NFIELDS (type) == 1 | |
b18bb924 | 3382 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b AC |
3383 | == TYPE_CODE_FLT)) |
3384 | || (TYPE_NFIELDS (type) == 2 | |
b18bb924 | 3385 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b | 3386 | == TYPE_CODE_FLT) |
b18bb924 | 3387 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1))) |
5b68030f | 3388 | == TYPE_CODE_FLT)))) |
6d82d43b AC |
3389 | { |
3390 | /* A struct that contains one or two floats. Each value is part | |
3391 | in the least significant part of their floating point | |
5b68030f | 3392 | register (or GPR, for soft float). */ |
6d82d43b AC |
3393 | int regnum; |
3394 | int field; | |
5b68030f JM |
3395 | for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE |
3396 | ? mips_regnum (gdbarch)->fp0 | |
3397 | : MIPS_V0_REGNUM); | |
6d82d43b AC |
3398 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
3399 | { | |
3400 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3401 | / TARGET_CHAR_BIT); | |
3402 | if (mips_debug) | |
3403 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3404 | offset); | |
5b68030f JM |
3405 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)) == 16) |
3406 | { | |
3407 | /* A 16-byte long double field goes in two consecutive | |
3408 | registers. */ | |
3409 | mips_xfer_register (gdbarch, regcache, | |
3410 | gdbarch_num_regs (gdbarch) + regnum, | |
3411 | 8, | |
3412 | gdbarch_byte_order (gdbarch), | |
3413 | readbuf, writebuf, offset); | |
3414 | mips_xfer_register (gdbarch, regcache, | |
3415 | gdbarch_num_regs (gdbarch) + regnum + 1, | |
3416 | 8, | |
3417 | gdbarch_byte_order (gdbarch), | |
3418 | readbuf, writebuf, offset + 8); | |
3419 | } | |
3420 | else | |
3421 | mips_xfer_register (gdbarch, regcache, | |
3422 | gdbarch_num_regs (gdbarch) + regnum, | |
3423 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
3424 | gdbarch_byte_order (gdbarch), | |
3425 | readbuf, writebuf, offset); | |
6d82d43b AC |
3426 | } |
3427 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3428 | } | |
3429 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3430 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3431 | { | |
3432 | /* A structure or union. Extract the left justified value, | |
3433 | regardless of the byte order. I.e. DO NOT USE | |
3434 | mips_xfer_lower. */ | |
3435 | int offset; | |
3436 | int regnum; | |
4c7d22cb | 3437 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3438 | offset < TYPE_LENGTH (type); |
72a155b4 | 3439 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3440 | { |
72a155b4 | 3441 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3442 | if (offset + xfer > TYPE_LENGTH (type)) |
3443 | xfer = TYPE_LENGTH (type) - offset; | |
3444 | if (mips_debug) | |
3445 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3446 | offset, xfer, regnum); | |
ba32f989 DJ |
3447 | mips_xfer_register (gdbarch, regcache, |
3448 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 UW |
3449 | xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf, |
3450 | offset); | |
6d82d43b AC |
3451 | } |
3452 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3453 | } | |
3454 | else | |
3455 | { | |
3456 | /* A scalar extract each part but least-significant-byte | |
3457 | justified. */ | |
3458 | int offset; | |
3459 | int regnum; | |
4c7d22cb | 3460 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3461 | offset < TYPE_LENGTH (type); |
72a155b4 | 3462 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3463 | { |
72a155b4 | 3464 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3465 | if (offset + xfer > TYPE_LENGTH (type)) |
3466 | xfer = TYPE_LENGTH (type) - offset; | |
3467 | if (mips_debug) | |
3468 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3469 | offset, xfer, regnum); | |
ba32f989 DJ |
3470 | mips_xfer_register (gdbarch, regcache, |
3471 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 3472 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 3473 | readbuf, writebuf, offset); |
6d82d43b AC |
3474 | } |
3475 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3476 | } | |
3477 | } | |
3478 | ||
3479 | /* O32 ABI stuff. */ | |
3480 | ||
3481 | static CORE_ADDR | |
7d9b040b | 3482 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3483 | struct regcache *regcache, CORE_ADDR bp_addr, |
3484 | int nargs, struct value **args, CORE_ADDR sp, | |
3485 | int struct_return, CORE_ADDR struct_addr) | |
3486 | { | |
3487 | int argreg; | |
3488 | int float_argreg; | |
3489 | int argnum; | |
3490 | int len = 0; | |
3491 | int stack_offset = 0; | |
3492 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
7d9b040b | 3493 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
3494 | |
3495 | /* For shared libraries, "t9" needs to point at the function | |
3496 | address. */ | |
4c7d22cb | 3497 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
6d82d43b AC |
3498 | |
3499 | /* Set the return address register to point to the entry point of | |
3500 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3501 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
6d82d43b AC |
3502 | |
3503 | /* First ensure that the stack and structure return address (if any) | |
3504 | are properly aligned. The stack has to be at least 64-bit | |
3505 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
3506 | aligned. For n32 and n64, stack frames need to be 128-bit |
3507 | aligned, so we round to this widest known alignment. */ | |
3508 | ||
5b03f266 AC |
3509 | sp = align_down (sp, 16); |
3510 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
3511 | |
3512 | /* Now make space on the stack for the args. */ | |
3513 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
3514 | { |
3515 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
3516 | int arglen = TYPE_LENGTH (arg_type); | |
3517 | ||
3518 | /* Align to double-word if necessary. */ | |
2afd3f0a | 3519 | if (mips_type_needs_double_align (arg_type)) |
1a69e1e4 | 3520 | len = align_up (len, MIPS32_REGSIZE * 2); |
968b5391 | 3521 | /* Allocate space on the stack. */ |
1a69e1e4 | 3522 | len += align_up (arglen, MIPS32_REGSIZE); |
968b5391 | 3523 | } |
5b03f266 | 3524 | sp -= align_up (len, 16); |
ebafbe83 MS |
3525 | |
3526 | if (mips_debug) | |
6d82d43b | 3527 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3528 | "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n", |
3529 | paddr_nz (sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
3530 | |
3531 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3532 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 3533 | float_argreg = mips_fpa0_regnum (gdbarch); |
ebafbe83 | 3534 | |
bcb0cc15 | 3535 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3536 | if (struct_return) |
3537 | { | |
3538 | if (mips_debug) | |
3539 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3540 | "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n", |
ebafbe83 | 3541 | argreg, paddr_nz (struct_addr)); |
9c9acae0 | 3542 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 3543 | stack_offset += MIPS32_REGSIZE; |
ebafbe83 MS |
3544 | } |
3545 | ||
3546 | /* Now load as many as possible of the first arguments into | |
3547 | registers, and push the rest onto the stack. Loop thru args | |
3548 | from first to last. */ | |
3549 | for (argnum = 0; argnum < nargs; argnum++) | |
3550 | { | |
47a35522 | 3551 | const gdb_byte *val; |
ebafbe83 | 3552 | struct value *arg = args[argnum]; |
4991999e | 3553 | struct type *arg_type = check_typedef (value_type (arg)); |
ebafbe83 MS |
3554 | int len = TYPE_LENGTH (arg_type); |
3555 | enum type_code typecode = TYPE_CODE (arg_type); | |
3556 | ||
3557 | if (mips_debug) | |
3558 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3559 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3560 | argnum + 1, len, (int) typecode); |
3561 | ||
47a35522 | 3562 | val = value_contents (arg); |
46cac009 AC |
3563 | |
3564 | /* 32-bit ABIs always start floating point arguments in an | |
3565 | even-numbered floating point register. Round the FP register | |
3566 | up before the check to see if there are any FP registers | |
3567 | left. O32/O64 targets also pass the FP in the integer | |
3568 | registers so also round up normal registers. */ | |
74ed0bb4 | 3569 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
46cac009 AC |
3570 | { |
3571 | if ((float_argreg & 1)) | |
3572 | float_argreg++; | |
3573 | } | |
3574 | ||
3575 | /* Floating point arguments passed in registers have to be | |
3576 | treated specially. On 32-bit architectures, doubles | |
3577 | are passed in register pairs; the even register gets | |
3578 | the low word, and the odd register gets the high word. | |
3579 | On O32/O64, the first two floating point arguments are | |
3580 | also copied to general registers, because MIPS16 functions | |
3581 | don't use float registers for arguments. This duplication of | |
3582 | arguments in general registers can't hurt non-MIPS16 functions | |
3583 | because those registers are normally skipped. */ | |
3584 | ||
74ed0bb4 MD |
3585 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
3586 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
46cac009 | 3587 | { |
8b07f6d8 | 3588 | if (register_size (gdbarch, float_argreg) < 8 && len == 8) |
46cac009 | 3589 | { |
72a155b4 | 3590 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 3591 | == BFD_ENDIAN_BIG ? 4 : 0; |
46cac009 AC |
3592 | unsigned long regval; |
3593 | ||
3594 | /* Write the low word of the double to the even register(s). */ | |
3595 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3596 | if (mips_debug) | |
3597 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3598 | float_argreg, phex (regval, 4)); | |
9c9acae0 | 3599 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
46cac009 AC |
3600 | if (mips_debug) |
3601 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3602 | argreg, phex (regval, 4)); | |
9c9acae0 | 3603 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3604 | |
3605 | /* Write the high word of the double to the odd register(s). */ | |
3606 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3607 | if (mips_debug) | |
3608 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3609 | float_argreg, phex (regval, 4)); | |
9c9acae0 | 3610 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
46cac009 AC |
3611 | |
3612 | if (mips_debug) | |
3613 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3614 | argreg, phex (regval, 4)); | |
9c9acae0 | 3615 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3616 | } |
3617 | else | |
3618 | { | |
3619 | /* This is a floating point value that fits entirely | |
3620 | in a single register. */ | |
3621 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 3622 | above to ensure that it is even register aligned. */ |
46cac009 AC |
3623 | LONGEST regval = extract_unsigned_integer (val, len); |
3624 | if (mips_debug) | |
3625 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3626 | float_argreg, phex (regval, len)); | |
9c9acae0 | 3627 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
5b68030f JM |
3628 | /* Although two FP registers are reserved for each |
3629 | argument, only one corresponding integer register is | |
3630 | reserved. */ | |
46cac009 AC |
3631 | if (mips_debug) |
3632 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3633 | argreg, phex (regval, len)); | |
5b68030f | 3634 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3635 | } |
3636 | /* Reserve space for the FP register. */ | |
1a69e1e4 | 3637 | stack_offset += align_up (len, MIPS32_REGSIZE); |
46cac009 AC |
3638 | } |
3639 | else | |
3640 | { | |
3641 | /* Copy the argument to general registers or the stack in | |
3642 | register-sized pieces. Large arguments are split between | |
3643 | registers and stack. */ | |
1a69e1e4 DJ |
3644 | /* Note: structs whose size is not a multiple of MIPS32_REGSIZE |
3645 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
3646 | them in registers where gcc sometimes puts them on the |
3647 | stack. For maximum compatibility, we will put them in | |
3648 | both places. */ | |
1a69e1e4 DJ |
3649 | int odd_sized_struct = (len > MIPS32_REGSIZE |
3650 | && len % MIPS32_REGSIZE != 0); | |
46cac009 AC |
3651 | /* Structures should be aligned to eight bytes (even arg registers) |
3652 | on MIPS_ABI_O32, if their first member has double precision. */ | |
2afd3f0a | 3653 | if (mips_type_needs_double_align (arg_type)) |
46cac009 AC |
3654 | { |
3655 | if ((argreg & 1)) | |
968b5391 MR |
3656 | { |
3657 | argreg++; | |
1a69e1e4 | 3658 | stack_offset += MIPS32_REGSIZE; |
968b5391 | 3659 | } |
46cac009 | 3660 | } |
46cac009 AC |
3661 | while (len > 0) |
3662 | { | |
3663 | /* Remember if the argument was written to the stack. */ | |
3664 | int stack_used_p = 0; | |
1a69e1e4 | 3665 | int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); |
46cac009 AC |
3666 | |
3667 | if (mips_debug) | |
3668 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3669 | partial_len); | |
3670 | ||
3671 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 3672 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 3673 | || odd_sized_struct) |
46cac009 AC |
3674 | { |
3675 | /* Should shorter than int integer values be | |
3676 | promoted to int before being stored? */ | |
3677 | int longword_offset = 0; | |
3678 | CORE_ADDR addr; | |
3679 | stack_used_p = 1; | |
46cac009 AC |
3680 | |
3681 | if (mips_debug) | |
3682 | { | |
3683 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3684 | paddr_nz (stack_offset)); | |
3685 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3686 | paddr_nz (longword_offset)); | |
3687 | } | |
3688 | ||
3689 | addr = sp + stack_offset + longword_offset; | |
3690 | ||
3691 | if (mips_debug) | |
3692 | { | |
3693 | int i; | |
6d82d43b | 3694 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
46cac009 AC |
3695 | paddr_nz (addr)); |
3696 | for (i = 0; i < partial_len; i++) | |
3697 | { | |
6d82d43b | 3698 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
3699 | val[i] & 0xff); |
3700 | } | |
3701 | } | |
3702 | write_memory (addr, val, partial_len); | |
3703 | } | |
3704 | ||
3705 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 3706 | structs may go thru BOTH paths. */ |
46cac009 | 3707 | /* Write this portion of the argument to a general |
6d82d43b | 3708 | purpose register. */ |
74ed0bb4 | 3709 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
46cac009 AC |
3710 | { |
3711 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 3712 | /* Value may need to be sign extended, because |
1b13c4f6 | 3713 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
3714 | |
3715 | /* A non-floating-point argument being passed in a | |
3716 | general register. If a struct or union, and if | |
3717 | the remaining length is smaller than the register | |
3718 | size, we have to adjust the register value on | |
3719 | big endian targets. | |
3720 | ||
3721 | It does not seem to be necessary to do the | |
3722 | same for integral types. | |
3723 | ||
3724 | Also don't do this adjustment on O64 binaries. | |
3725 | ||
3726 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3727 | outputting LE O32 with sizeof (struct) < | |
e914cb17 MR |
3728 | mips_abi_regsize(), generates a left shift |
3729 | as part of storing the argument in a register | |
3730 | (the left shift isn't generated when | |
1b13c4f6 | 3731 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
3732 | it is quite possible that this is GCC |
3733 | contradicting the LE/O32 ABI, GDB has not been | |
3734 | adjusted to accommodate this. Either someone | |
3735 | needs to demonstrate that the LE/O32 ABI | |
3736 | specifies such a left shift OR this new ABI gets | |
3737 | identified as such and GDB gets tweaked | |
3738 | accordingly. */ | |
3739 | ||
72a155b4 | 3740 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3741 | && partial_len < MIPS32_REGSIZE |
06f9a1af MR |
3742 | && (typecode == TYPE_CODE_STRUCT |
3743 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3744 | regval <<= ((MIPS32_REGSIZE - partial_len) |
9ecf7166 | 3745 | * TARGET_CHAR_BIT); |
46cac009 AC |
3746 | |
3747 | if (mips_debug) | |
3748 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3749 | argreg, | |
1a69e1e4 | 3750 | phex (regval, MIPS32_REGSIZE)); |
9c9acae0 | 3751 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
46cac009 AC |
3752 | argreg++; |
3753 | ||
3754 | /* Prevent subsequent floating point arguments from | |
3755 | being passed in floating point registers. */ | |
74ed0bb4 | 3756 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
46cac009 AC |
3757 | } |
3758 | ||
3759 | len -= partial_len; | |
3760 | val += partial_len; | |
3761 | ||
3762 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3763 | will copy the next parameter. |
46cac009 | 3764 | |
6d82d43b AC |
3765 | In older ABIs, the caller reserved space for |
3766 | registers that contained arguments. This was loosely | |
3767 | refered to as their "home". Consequently, space is | |
3768 | always allocated. */ | |
46cac009 | 3769 | |
1a69e1e4 | 3770 | stack_offset += align_up (partial_len, MIPS32_REGSIZE); |
46cac009 AC |
3771 | } |
3772 | } | |
3773 | if (mips_debug) | |
3774 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3775 | } | |
3776 | ||
f10683bb | 3777 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3778 | |
46cac009 AC |
3779 | /* Return adjusted stack pointer. */ |
3780 | return sp; | |
3781 | } | |
3782 | ||
6d82d43b | 3783 | static enum return_value_convention |
c055b101 CV |
3784 | mips_o32_return_value (struct gdbarch *gdbarch, struct type *func_type, |
3785 | struct type *type, struct regcache *regcache, | |
47a35522 | 3786 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 3787 | { |
72a155b4 | 3788 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
6d82d43b AC |
3789 | |
3790 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3791 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3792 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
3793 | return RETURN_VALUE_STRUCT_CONVENTION; | |
3794 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3795 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3796 | { | |
3797 | /* A single-precision floating-point value. It fits in the | |
3798 | least significant part of FP0. */ | |
3799 | if (mips_debug) | |
3800 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 3801 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3802 | gdbarch_num_regs (gdbarch) |
3803 | + mips_regnum (gdbarch)->fp0, | |
6d82d43b | 3804 | TYPE_LENGTH (type), |
72a155b4 | 3805 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3806 | readbuf, writebuf, 0); |
6d82d43b AC |
3807 | return RETURN_VALUE_REGISTER_CONVENTION; |
3808 | } | |
3809 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3810 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3811 | { | |
3812 | /* A double-precision floating-point value. The most | |
3813 | significant part goes in FP1, and the least significant in | |
3814 | FP0. */ | |
3815 | if (mips_debug) | |
3816 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
72a155b4 | 3817 | switch (gdbarch_byte_order (gdbarch)) |
6d82d43b AC |
3818 | { |
3819 | case BFD_ENDIAN_LITTLE: | |
ba32f989 | 3820 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3821 | gdbarch_num_regs (gdbarch) |
3822 | + mips_regnum (gdbarch)->fp0 + | |
3823 | 0, 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3824 | readbuf, writebuf, 0); |
ba32f989 | 3825 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3826 | gdbarch_num_regs (gdbarch) |
3827 | + mips_regnum (gdbarch)->fp0 + 1, | |
3828 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3829 | readbuf, writebuf, 4); |
6d82d43b AC |
3830 | break; |
3831 | case BFD_ENDIAN_BIG: | |
ba32f989 | 3832 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3833 | gdbarch_num_regs (gdbarch) |
3834 | + mips_regnum (gdbarch)->fp0 + 1, | |
3835 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3836 | readbuf, writebuf, 0); |
ba32f989 | 3837 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3838 | gdbarch_num_regs (gdbarch) |
3839 | + mips_regnum (gdbarch)->fp0 + 0, | |
3840 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3841 | readbuf, writebuf, 4); |
6d82d43b AC |
3842 | break; |
3843 | default: | |
e2e0b3e5 | 3844 | internal_error (__FILE__, __LINE__, _("bad switch")); |
6d82d43b AC |
3845 | } |
3846 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3847 | } | |
3848 | #if 0 | |
3849 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3850 | && TYPE_NFIELDS (type) <= 2 | |
3851 | && TYPE_NFIELDS (type) >= 1 | |
3852 | && ((TYPE_NFIELDS (type) == 1 | |
3853 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3854 | == TYPE_CODE_FLT)) | |
3855 | || (TYPE_NFIELDS (type) == 2 | |
3856 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3857 | == TYPE_CODE_FLT) | |
3858 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
3859 | == TYPE_CODE_FLT))) | |
3860 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3861 | { | |
3862 | /* A struct that contains one or two floats. Each value is part | |
3863 | in the least significant part of their floating point | |
3864 | register.. */ | |
870cd05e | 3865 | gdb_byte reg[MAX_REGISTER_SIZE]; |
6d82d43b AC |
3866 | int regnum; |
3867 | int field; | |
72a155b4 | 3868 | for (field = 0, regnum = mips_regnum (gdbarch)->fp0; |
6d82d43b AC |
3869 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
3870 | { | |
3871 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3872 | / TARGET_CHAR_BIT); | |
3873 | if (mips_debug) | |
3874 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3875 | offset); | |
ba32f989 DJ |
3876 | mips_xfer_register (gdbarch, regcache, |
3877 | gdbarch_num_regs (gdbarch) + regnum, | |
6d82d43b | 3878 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
72a155b4 | 3879 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3880 | readbuf, writebuf, offset); |
6d82d43b AC |
3881 | } |
3882 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3883 | } | |
3884 | #endif | |
3885 | #if 0 | |
3886 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3887 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3888 | { | |
3889 | /* A structure or union. Extract the left justified value, | |
3890 | regardless of the byte order. I.e. DO NOT USE | |
3891 | mips_xfer_lower. */ | |
3892 | int offset; | |
3893 | int regnum; | |
4c7d22cb | 3894 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3895 | offset < TYPE_LENGTH (type); |
72a155b4 | 3896 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3897 | { |
72a155b4 | 3898 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3899 | if (offset + xfer > TYPE_LENGTH (type)) |
3900 | xfer = TYPE_LENGTH (type) - offset; | |
3901 | if (mips_debug) | |
3902 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3903 | offset, xfer, regnum); | |
ba32f989 DJ |
3904 | mips_xfer_register (gdbarch, regcache, |
3905 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
6d82d43b AC |
3906 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
3907 | } | |
3908 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3909 | } | |
3910 | #endif | |
3911 | else | |
3912 | { | |
3913 | /* A scalar extract each part but least-significant-byte | |
3914 | justified. o32 thinks registers are 4 byte, regardless of | |
1a69e1e4 | 3915 | the ISA. */ |
6d82d43b AC |
3916 | int offset; |
3917 | int regnum; | |
4c7d22cb | 3918 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3919 | offset < TYPE_LENGTH (type); |
1a69e1e4 | 3920 | offset += MIPS32_REGSIZE, regnum++) |
6d82d43b | 3921 | { |
1a69e1e4 | 3922 | int xfer = MIPS32_REGSIZE; |
6d82d43b AC |
3923 | if (offset + xfer > TYPE_LENGTH (type)) |
3924 | xfer = TYPE_LENGTH (type) - offset; | |
3925 | if (mips_debug) | |
3926 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3927 | offset, xfer, regnum); | |
ba32f989 DJ |
3928 | mips_xfer_register (gdbarch, regcache, |
3929 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
72a155b4 | 3930 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3931 | readbuf, writebuf, offset); |
6d82d43b AC |
3932 | } |
3933 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3934 | } | |
3935 | } | |
3936 | ||
3937 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
3938 | ABI. */ | |
46cac009 AC |
3939 | |
3940 | static CORE_ADDR | |
7d9b040b | 3941 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3942 | struct regcache *regcache, CORE_ADDR bp_addr, |
3943 | int nargs, | |
3944 | struct value **args, CORE_ADDR sp, | |
3945 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
3946 | { |
3947 | int argreg; | |
3948 | int float_argreg; | |
3949 | int argnum; | |
3950 | int len = 0; | |
3951 | int stack_offset = 0; | |
480d3dd2 | 3952 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 3953 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 3954 | |
25ab4790 AC |
3955 | /* For shared libraries, "t9" needs to point at the function |
3956 | address. */ | |
4c7d22cb | 3957 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
3958 | |
3959 | /* Set the return address register to point to the entry point of | |
3960 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3961 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 3962 | |
46cac009 AC |
3963 | /* First ensure that the stack and structure return address (if any) |
3964 | are properly aligned. The stack has to be at least 64-bit | |
3965 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3966 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3967 | aligned, so we round to this widest known alignment. */ | |
3968 | ||
5b03f266 AC |
3969 | sp = align_down (sp, 16); |
3970 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
3971 | |
3972 | /* Now make space on the stack for the args. */ | |
3973 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
3974 | { |
3975 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
3976 | int arglen = TYPE_LENGTH (arg_type); | |
3977 | ||
968b5391 | 3978 | /* Allocate space on the stack. */ |
1a69e1e4 | 3979 | len += align_up (arglen, MIPS64_REGSIZE); |
968b5391 | 3980 | } |
5b03f266 | 3981 | sp -= align_up (len, 16); |
46cac009 AC |
3982 | |
3983 | if (mips_debug) | |
6d82d43b | 3984 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3985 | "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n", |
3986 | paddr_nz (sp), (long) align_up (len, 16)); | |
46cac009 AC |
3987 | |
3988 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3989 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 3990 | float_argreg = mips_fpa0_regnum (gdbarch); |
46cac009 AC |
3991 | |
3992 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
3993 | if (struct_return) | |
3994 | { | |
3995 | if (mips_debug) | |
3996 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3997 | "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n", |
46cac009 | 3998 | argreg, paddr_nz (struct_addr)); |
9c9acae0 | 3999 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 4000 | stack_offset += MIPS64_REGSIZE; |
46cac009 AC |
4001 | } |
4002 | ||
4003 | /* Now load as many as possible of the first arguments into | |
4004 | registers, and push the rest onto the stack. Loop thru args | |
4005 | from first to last. */ | |
4006 | for (argnum = 0; argnum < nargs; argnum++) | |
4007 | { | |
47a35522 | 4008 | const gdb_byte *val; |
46cac009 | 4009 | struct value *arg = args[argnum]; |
4991999e | 4010 | struct type *arg_type = check_typedef (value_type (arg)); |
46cac009 AC |
4011 | int len = TYPE_LENGTH (arg_type); |
4012 | enum type_code typecode = TYPE_CODE (arg_type); | |
4013 | ||
4014 | if (mips_debug) | |
4015 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4016 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
4017 | argnum + 1, len, (int) typecode); |
4018 | ||
47a35522 | 4019 | val = value_contents (arg); |
ebafbe83 | 4020 | |
ebafbe83 MS |
4021 | /* Floating point arguments passed in registers have to be |
4022 | treated specially. On 32-bit architectures, doubles | |
4023 | are passed in register pairs; the even register gets | |
4024 | the low word, and the odd register gets the high word. | |
4025 | On O32/O64, the first two floating point arguments are | |
4026 | also copied to general registers, because MIPS16 functions | |
4027 | don't use float registers for arguments. This duplication of | |
4028 | arguments in general registers can't hurt non-MIPS16 functions | |
4029 | because those registers are normally skipped. */ | |
4030 | ||
74ed0bb4 MD |
4031 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
4032 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
ebafbe83 | 4033 | { |
2afd3f0a MR |
4034 | LONGEST regval = extract_unsigned_integer (val, len); |
4035 | if (mips_debug) | |
4036 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4037 | float_argreg, phex (regval, len)); | |
9c9acae0 | 4038 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
2afd3f0a MR |
4039 | if (mips_debug) |
4040 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4041 | argreg, phex (regval, len)); | |
9c9acae0 | 4042 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
2afd3f0a | 4043 | argreg++; |
ebafbe83 | 4044 | /* Reserve space for the FP register. */ |
1a69e1e4 | 4045 | stack_offset += align_up (len, MIPS64_REGSIZE); |
ebafbe83 MS |
4046 | } |
4047 | else | |
4048 | { | |
4049 | /* Copy the argument to general registers or the stack in | |
4050 | register-sized pieces. Large arguments are split between | |
4051 | registers and stack. */ | |
1a69e1e4 | 4052 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
4053 | are treated specially: Irix cc passes them in registers |
4054 | where gcc sometimes puts them on the stack. For maximum | |
4055 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
4056 | int odd_sized_struct = (len > MIPS64_REGSIZE |
4057 | && len % MIPS64_REGSIZE != 0); | |
ebafbe83 MS |
4058 | while (len > 0) |
4059 | { | |
4060 | /* Remember if the argument was written to the stack. */ | |
4061 | int stack_used_p = 0; | |
1a69e1e4 | 4062 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
ebafbe83 MS |
4063 | |
4064 | if (mips_debug) | |
4065 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4066 | partial_len); | |
4067 | ||
4068 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 4069 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 4070 | || odd_sized_struct) |
ebafbe83 MS |
4071 | { |
4072 | /* Should shorter than int integer values be | |
4073 | promoted to int before being stored? */ | |
4074 | int longword_offset = 0; | |
4075 | CORE_ADDR addr; | |
4076 | stack_used_p = 1; | |
72a155b4 | 4077 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ebafbe83 | 4078 | { |
1a69e1e4 DJ |
4079 | if ((typecode == TYPE_CODE_INT |
4080 | || typecode == TYPE_CODE_PTR | |
4081 | || typecode == TYPE_CODE_FLT) | |
4082 | && len <= 4) | |
4083 | longword_offset = MIPS64_REGSIZE - len; | |
ebafbe83 MS |
4084 | } |
4085 | ||
4086 | if (mips_debug) | |
4087 | { | |
4088 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
4089 | paddr_nz (stack_offset)); | |
4090 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
4091 | paddr_nz (longword_offset)); | |
4092 | } | |
4093 | ||
4094 | addr = sp + stack_offset + longword_offset; | |
4095 | ||
4096 | if (mips_debug) | |
4097 | { | |
4098 | int i; | |
6d82d43b | 4099 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
ebafbe83 MS |
4100 | paddr_nz (addr)); |
4101 | for (i = 0; i < partial_len; i++) | |
4102 | { | |
6d82d43b | 4103 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
4104 | val[i] & 0xff); |
4105 | } | |
4106 | } | |
4107 | write_memory (addr, val, partial_len); | |
4108 | } | |
4109 | ||
4110 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 4111 | structs may go thru BOTH paths. */ |
ebafbe83 | 4112 | /* Write this portion of the argument to a general |
6d82d43b | 4113 | purpose register. */ |
74ed0bb4 | 4114 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
ebafbe83 MS |
4115 | { |
4116 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 4117 | /* Value may need to be sign extended, because |
1b13c4f6 | 4118 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
4119 | |
4120 | /* A non-floating-point argument being passed in a | |
4121 | general register. If a struct or union, and if | |
4122 | the remaining length is smaller than the register | |
4123 | size, we have to adjust the register value on | |
4124 | big endian targets. | |
4125 | ||
4126 | It does not seem to be necessary to do the | |
401835eb | 4127 | same for integral types. */ |
480d3dd2 | 4128 | |
72a155b4 | 4129 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 4130 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
4131 | && (typecode == TYPE_CODE_STRUCT |
4132 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 4133 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 4134 | * TARGET_CHAR_BIT); |
ebafbe83 MS |
4135 | |
4136 | if (mips_debug) | |
4137 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
4138 | argreg, | |
1a69e1e4 | 4139 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 4140 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
ebafbe83 MS |
4141 | argreg++; |
4142 | ||
4143 | /* Prevent subsequent floating point arguments from | |
4144 | being passed in floating point registers. */ | |
74ed0bb4 | 4145 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
ebafbe83 MS |
4146 | } |
4147 | ||
4148 | len -= partial_len; | |
4149 | val += partial_len; | |
4150 | ||
4151 | /* Compute the the offset into the stack at which we | |
6d82d43b | 4152 | will copy the next parameter. |
ebafbe83 | 4153 | |
6d82d43b AC |
4154 | In older ABIs, the caller reserved space for |
4155 | registers that contained arguments. This was loosely | |
4156 | refered to as their "home". Consequently, space is | |
4157 | always allocated. */ | |
ebafbe83 | 4158 | |
1a69e1e4 | 4159 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
ebafbe83 MS |
4160 | } |
4161 | } | |
4162 | if (mips_debug) | |
4163 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
4164 | } | |
4165 | ||
f10683bb | 4166 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4167 | |
ebafbe83 MS |
4168 | /* Return adjusted stack pointer. */ |
4169 | return sp; | |
4170 | } | |
4171 | ||
9c8fdbfa | 4172 | static enum return_value_convention |
c055b101 | 4173 | mips_o64_return_value (struct gdbarch *gdbarch, struct type *func_type, |
9c8fdbfa | 4174 | struct type *type, struct regcache *regcache, |
47a35522 | 4175 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 4176 | { |
72a155b4 | 4177 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7a076fd2 FF |
4178 | |
4179 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4180 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
4181 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
4182 | return RETURN_VALUE_STRUCT_CONVENTION; | |
74ed0bb4 | 4183 | else if (fp_register_arg_p (gdbarch, TYPE_CODE (type), type)) |
7a076fd2 FF |
4184 | { |
4185 | /* A floating-point value. It fits in the least significant | |
4186 | part of FP0. */ | |
4187 | if (mips_debug) | |
4188 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 4189 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4190 | gdbarch_num_regs (gdbarch) |
4191 | + mips_regnum (gdbarch)->fp0, | |
7a076fd2 | 4192 | TYPE_LENGTH (type), |
72a155b4 | 4193 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4194 | readbuf, writebuf, 0); |
7a076fd2 FF |
4195 | return RETURN_VALUE_REGISTER_CONVENTION; |
4196 | } | |
4197 | else | |
4198 | { | |
4199 | /* A scalar extract each part but least-significant-byte | |
4200 | justified. */ | |
4201 | int offset; | |
4202 | int regnum; | |
4203 | for (offset = 0, regnum = MIPS_V0_REGNUM; | |
4204 | offset < TYPE_LENGTH (type); | |
1a69e1e4 | 4205 | offset += MIPS64_REGSIZE, regnum++) |
7a076fd2 | 4206 | { |
1a69e1e4 | 4207 | int xfer = MIPS64_REGSIZE; |
7a076fd2 FF |
4208 | if (offset + xfer > TYPE_LENGTH (type)) |
4209 | xfer = TYPE_LENGTH (type) - offset; | |
4210 | if (mips_debug) | |
4211 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4212 | offset, xfer, regnum); | |
ba32f989 DJ |
4213 | mips_xfer_register (gdbarch, regcache, |
4214 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 4215 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 4216 | readbuf, writebuf, offset); |
7a076fd2 FF |
4217 | } |
4218 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4219 | } | |
6d82d43b AC |
4220 | } |
4221 | ||
dd824b04 DJ |
4222 | /* Floating point register management. |
4223 | ||
4224 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
4225 | 64bit operations, these early MIPS cpus treat fp register pairs | |
4226 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
4227 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
4228 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
4229 | double precision floats into two 32-bit chunks and store them in | |
4230 | consecutive fp regs. To display 64-bit floats stored in this | |
4231 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
4232 | Throw in user-configurable endianness and you have a real mess. | |
4233 | ||
4234 | The way this works is: | |
4235 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
4236 | double-precision value will be split across two logical registers. | |
4237 | The lower-numbered logical register will hold the low-order bits, | |
4238 | regardless of the processor's endianness. | |
4239 | - If we are on a 64-bit processor, and we are looking for a | |
4240 | single-precision value, it will be in the low ordered bits | |
4241 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
4242 | save slot in memory. | |
4243 | - If we are in 64-bit mode, everything is straightforward. | |
4244 | ||
4245 | Note that this code only deals with "live" registers at the top of the | |
4246 | stack. We will attempt to deal with saved registers later, when | |
4247 | the raw/cooked register interface is in place. (We need a general | |
4248 | interface that can deal with dynamic saved register sizes -- fp | |
4249 | regs could be 32 bits wide in one frame and 64 on the frame above | |
4250 | and below). */ | |
4251 | ||
67b2c998 DJ |
4252 | static struct type * |
4253 | mips_float_register_type (void) | |
4254 | { | |
8da61cc4 | 4255 | return builtin_type_ieee_single; |
67b2c998 DJ |
4256 | } |
4257 | ||
4258 | static struct type * | |
4259 | mips_double_register_type (void) | |
4260 | { | |
8da61cc4 | 4261 | return builtin_type_ieee_double; |
67b2c998 DJ |
4262 | } |
4263 | ||
dd824b04 DJ |
4264 | /* Copy a 32-bit single-precision value from the current frame |
4265 | into rare_buffer. */ | |
4266 | ||
4267 | static void | |
e11c53d2 | 4268 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
47a35522 | 4269 | gdb_byte *rare_buffer) |
dd824b04 | 4270 | { |
72a155b4 UW |
4271 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4272 | int raw_size = register_size (gdbarch, regno); | |
47a35522 | 4273 | gdb_byte *raw_buffer = alloca (raw_size); |
dd824b04 | 4274 | |
e11c53d2 | 4275 | if (!frame_register_read (frame, regno, raw_buffer)) |
c9f4d572 | 4276 | error (_("can't read register %d (%s)"), |
72a155b4 | 4277 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
4278 | if (raw_size == 8) |
4279 | { | |
4280 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 4281 | 32 bits. */ |
dd824b04 DJ |
4282 | int offset; |
4283 | ||
72a155b4 | 4284 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 DJ |
4285 | offset = 4; |
4286 | else | |
4287 | offset = 0; | |
4288 | ||
4289 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
4290 | } | |
4291 | else | |
4292 | { | |
4293 | memcpy (rare_buffer, raw_buffer, 4); | |
4294 | } | |
4295 | } | |
4296 | ||
4297 | /* Copy a 64-bit double-precision value from the current frame into | |
4298 | rare_buffer. This may include getting half of it from the next | |
4299 | register. */ | |
4300 | ||
4301 | static void | |
e11c53d2 | 4302 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
47a35522 | 4303 | gdb_byte *rare_buffer) |
dd824b04 | 4304 | { |
72a155b4 UW |
4305 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4306 | int raw_size = register_size (gdbarch, regno); | |
dd824b04 | 4307 | |
9c9acae0 | 4308 | if (raw_size == 8 && !mips2_fp_compat (frame)) |
dd824b04 DJ |
4309 | { |
4310 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 4311 | all 64 bits. */ |
e11c53d2 | 4312 | if (!frame_register_read (frame, regno, rare_buffer)) |
c9f4d572 | 4313 | error (_("can't read register %d (%s)"), |
72a155b4 | 4314 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
4315 | } |
4316 | else | |
4317 | { | |
72a155b4 | 4318 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
82e91389 | 4319 | |
72a155b4 | 4320 | if ((rawnum - mips_regnum (gdbarch)->fp0) & 1) |
dd824b04 | 4321 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
4322 | _("mips_read_fp_register_double: bad access to " |
4323 | "odd-numbered FP register")); | |
dd824b04 DJ |
4324 | |
4325 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 4326 | each register. */ |
72a155b4 | 4327 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 | 4328 | { |
e11c53d2 AC |
4329 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
4330 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 4331 | } |
361d1df0 | 4332 | else |
dd824b04 | 4333 | { |
e11c53d2 AC |
4334 | mips_read_fp_register_single (frame, regno, rare_buffer); |
4335 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
4336 | } |
4337 | } | |
4338 | } | |
4339 | ||
c906108c | 4340 | static void |
e11c53d2 AC |
4341 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
4342 | int regnum) | |
c5aa993b | 4343 | { /* do values for FP (float) regs */ |
72a155b4 | 4344 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 4345 | gdb_byte *raw_buffer; |
3903d437 AC |
4346 | double doub, flt1; /* doubles extracted from raw hex data */ |
4347 | int inv1, inv2; | |
c5aa993b | 4348 | |
72a155b4 | 4349 | raw_buffer = alloca (2 * register_size (gdbarch, mips_regnum (gdbarch)->fp0)); |
c906108c | 4350 | |
72a155b4 | 4351 | fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum)); |
c9f4d572 | 4352 | fprintf_filtered (file, "%*s", |
72a155b4 | 4353 | 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)), |
e11c53d2 | 4354 | ""); |
f0ef6b29 | 4355 | |
72a155b4 | 4356 | if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame)) |
c906108c | 4357 | { |
f0ef6b29 KB |
4358 | /* 4-byte registers: Print hex and floating. Also print even |
4359 | numbered registers as doubles. */ | |
e11c53d2 | 4360 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
67b2c998 | 4361 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c5aa993b | 4362 | |
6d82d43b AC |
4363 | print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w', |
4364 | file); | |
dd824b04 | 4365 | |
e11c53d2 | 4366 | fprintf_filtered (file, " flt: "); |
1adad886 | 4367 | if (inv1) |
e11c53d2 | 4368 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4369 | else |
e11c53d2 | 4370 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4371 | |
72a155b4 | 4372 | if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0) |
f0ef6b29 | 4373 | { |
e11c53d2 | 4374 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 | 4375 | doub = unpack_double (mips_double_register_type (), raw_buffer, |
6d82d43b | 4376 | &inv2); |
1adad886 | 4377 | |
e11c53d2 | 4378 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4379 | if (inv2) |
e11c53d2 | 4380 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 4381 | else |
e11c53d2 | 4382 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 4383 | } |
c906108c SS |
4384 | } |
4385 | else | |
dd824b04 | 4386 | { |
f0ef6b29 | 4387 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 4388 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
2f38ef89 | 4389 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c906108c | 4390 | |
e11c53d2 | 4391 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
4392 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2); |
4393 | ||
361d1df0 | 4394 | |
6d82d43b AC |
4395 | print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g', |
4396 | file); | |
f0ef6b29 | 4397 | |
e11c53d2 | 4398 | fprintf_filtered (file, " flt: "); |
1adad886 | 4399 | if (inv1) |
e11c53d2 | 4400 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 4401 | else |
e11c53d2 | 4402 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4403 | |
e11c53d2 | 4404 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4405 | if (inv2) |
e11c53d2 | 4406 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 4407 | else |
e11c53d2 | 4408 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
4409 | } |
4410 | } | |
4411 | ||
4412 | static void | |
e11c53d2 | 4413 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
0cc93a06 | 4414 | int regnum) |
f0ef6b29 | 4415 | { |
a4b8ebc8 | 4416 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 4417 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
f0ef6b29 | 4418 | int offset; |
1adad886 | 4419 | |
7b9ee6a8 | 4420 | if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 4421 | { |
e11c53d2 | 4422 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4423 | return; |
4424 | } | |
4425 | ||
4426 | /* Get the data in raw format. */ | |
e11c53d2 | 4427 | if (!frame_register_read (frame, regnum, raw_buffer)) |
f0ef6b29 | 4428 | { |
c9f4d572 | 4429 | fprintf_filtered (file, "%s: [Invalid]", |
72a155b4 | 4430 | gdbarch_register_name (gdbarch, regnum)); |
f0ef6b29 | 4431 | return; |
c906108c | 4432 | } |
f0ef6b29 | 4433 | |
72a155b4 | 4434 | fputs_filtered (gdbarch_register_name (gdbarch, regnum), file); |
f0ef6b29 KB |
4435 | |
4436 | /* The problem with printing numeric register names (r26, etc.) is that | |
4437 | the user can't use them on input. Probably the best solution is to | |
4438 | fix it so that either the numeric or the funky (a2, etc.) names | |
4439 | are accepted on input. */ | |
4440 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 4441 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 4442 | else |
e11c53d2 | 4443 | fprintf_filtered (file, ": "); |
f0ef6b29 | 4444 | |
72a155b4 | 4445 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b | 4446 | offset = |
72a155b4 | 4447 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
f0ef6b29 KB |
4448 | else |
4449 | offset = 0; | |
4450 | ||
6d82d43b | 4451 | print_scalar_formatted (raw_buffer + offset, |
7b9ee6a8 | 4452 | register_type (gdbarch, regnum), 'x', 0, |
6d82d43b | 4453 | file); |
c906108c SS |
4454 | } |
4455 | ||
f0ef6b29 KB |
4456 | /* Replacement for generic do_registers_info. |
4457 | Print regs in pretty columns. */ | |
4458 | ||
4459 | static int | |
e11c53d2 AC |
4460 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
4461 | int regnum) | |
f0ef6b29 | 4462 | { |
e11c53d2 AC |
4463 | fprintf_filtered (file, " "); |
4464 | mips_print_fp_register (file, frame, regnum); | |
4465 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
4466 | return regnum + 1; |
4467 | } | |
4468 | ||
4469 | ||
c906108c SS |
4470 | /* Print a row's worth of GP (int) registers, with name labels above */ |
4471 | ||
4472 | static int | |
e11c53d2 | 4473 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 4474 | int start_regnum) |
c906108c | 4475 | { |
a4b8ebc8 | 4476 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 4477 | /* do values for GP (int) regs */ |
47a35522 | 4478 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
d5ac5a39 | 4479 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */ |
c906108c | 4480 | int col, byte; |
a4b8ebc8 | 4481 | int regnum; |
c906108c SS |
4482 | |
4483 | /* For GP registers, we print a separate row of names above the vals */ | |
a4b8ebc8 | 4484 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
4485 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
4486 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 4487 | regnum++) |
c906108c | 4488 | { |
72a155b4 | 4489 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 4490 | continue; /* unused register */ |
7b9ee6a8 | 4491 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4492 | TYPE_CODE_FLT) |
c5aa993b | 4493 | break; /* end the row: reached FP register */ |
0cc93a06 | 4494 | /* Large registers are handled separately. */ |
72a155b4 | 4495 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
4496 | { |
4497 | if (col > 0) | |
4498 | break; /* End the row before this register. */ | |
4499 | ||
4500 | /* Print this register on a row by itself. */ | |
4501 | mips_print_register (file, frame, regnum); | |
4502 | fprintf_filtered (file, "\n"); | |
4503 | return regnum + 1; | |
4504 | } | |
d05f6826 DJ |
4505 | if (col == 0) |
4506 | fprintf_filtered (file, " "); | |
6d82d43b | 4507 | fprintf_filtered (file, |
72a155b4 UW |
4508 | mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s", |
4509 | gdbarch_register_name (gdbarch, regnum)); | |
c906108c SS |
4510 | col++; |
4511 | } | |
d05f6826 DJ |
4512 | |
4513 | if (col == 0) | |
4514 | return regnum; | |
4515 | ||
a4b8ebc8 | 4516 | /* print the R0 to R31 names */ |
72a155b4 | 4517 | if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS) |
f57d151a | 4518 | fprintf_filtered (file, "\n R%-4d", |
72a155b4 | 4519 | start_regnum % gdbarch_num_regs (gdbarch)); |
20e6603c AC |
4520 | else |
4521 | fprintf_filtered (file, "\n "); | |
c906108c | 4522 | |
c906108c | 4523 | /* now print the values in hex, 4 or 8 to the row */ |
a4b8ebc8 | 4524 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
4525 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
4526 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 4527 | regnum++) |
c906108c | 4528 | { |
72a155b4 | 4529 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 4530 | continue; /* unused register */ |
7b9ee6a8 | 4531 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4532 | TYPE_CODE_FLT) |
c5aa993b | 4533 | break; /* end row: reached FP register */ |
72a155b4 | 4534 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
4535 | break; /* End row: large register. */ |
4536 | ||
c906108c | 4537 | /* OK: get the data in raw format. */ |
e11c53d2 | 4538 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c9f4d572 | 4539 | error (_("can't read register %d (%s)"), |
72a155b4 | 4540 | regnum, gdbarch_register_name (gdbarch, regnum)); |
c906108c | 4541 | /* pad small registers */ |
4246e332 | 4542 | for (byte = 0; |
72a155b4 UW |
4543 | byte < (mips_abi_regsize (gdbarch) |
4544 | - register_size (gdbarch, regnum)); byte++) | |
c906108c SS |
4545 | printf_filtered (" "); |
4546 | /* Now print the register value in hex, endian order. */ | |
72a155b4 | 4547 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b | 4548 | for (byte = |
72a155b4 UW |
4549 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
4550 | byte < register_size (gdbarch, regnum); byte++) | |
47a35522 | 4551 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
c906108c | 4552 | else |
72a155b4 | 4553 | for (byte = register_size (gdbarch, regnum) - 1; |
6d82d43b | 4554 | byte >= 0; byte--) |
47a35522 | 4555 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
e11c53d2 | 4556 | fprintf_filtered (file, " "); |
c906108c SS |
4557 | col++; |
4558 | } | |
c5aa993b | 4559 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 4560 | fprintf_filtered (file, "\n"); |
c906108c SS |
4561 | |
4562 | return regnum; | |
4563 | } | |
4564 | ||
4565 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
4566 | ||
bf1f5b4c | 4567 | static void |
e11c53d2 AC |
4568 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4569 | struct frame_info *frame, int regnum, int all) | |
c906108c | 4570 | { |
c5aa993b | 4571 | if (regnum != -1) /* do one specified register */ |
c906108c | 4572 | { |
72a155b4 UW |
4573 | gdb_assert (regnum >= gdbarch_num_regs (gdbarch)); |
4574 | if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
8a3fe4f8 | 4575 | error (_("Not a valid register for the current processor type")); |
c906108c | 4576 | |
0cc93a06 | 4577 | mips_print_register (file, frame, regnum); |
e11c53d2 | 4578 | fprintf_filtered (file, "\n"); |
c906108c | 4579 | } |
c5aa993b JM |
4580 | else |
4581 | /* do all (or most) registers */ | |
c906108c | 4582 | { |
72a155b4 UW |
4583 | regnum = gdbarch_num_regs (gdbarch); |
4584 | while (regnum < gdbarch_num_regs (gdbarch) | |
4585 | + gdbarch_num_pseudo_regs (gdbarch)) | |
c906108c | 4586 | { |
7b9ee6a8 | 4587 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4588 | TYPE_CODE_FLT) |
e11c53d2 AC |
4589 | { |
4590 | if (all) /* true for "INFO ALL-REGISTERS" command */ | |
4591 | regnum = print_fp_register_row (file, frame, regnum); | |
4592 | else | |
4593 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
4594 | } | |
c906108c | 4595 | else |
e11c53d2 | 4596 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
4597 | } |
4598 | } | |
4599 | } | |
4600 | ||
c906108c SS |
4601 | /* Is this a branch with a delay slot? */ |
4602 | ||
c906108c | 4603 | static int |
acdb74a0 | 4604 | is_delayed (unsigned long insn) |
c906108c SS |
4605 | { |
4606 | int i; | |
4607 | for (i = 0; i < NUMOPCODES; ++i) | |
4608 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4609 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4610 | break; | |
4611 | return (i < NUMOPCODES | |
4612 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4613 | | INSN_COND_BRANCH_DELAY | |
4614 | | INSN_COND_BRANCH_LIKELY))); | |
4615 | } | |
4616 | ||
4617 | int | |
3352ef37 AC |
4618 | mips_single_step_through_delay (struct gdbarch *gdbarch, |
4619 | struct frame_info *frame) | |
c906108c | 4620 | { |
3352ef37 | 4621 | CORE_ADDR pc = get_frame_pc (frame); |
47a35522 | 4622 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
4623 | |
4624 | /* There is no branch delay slot on MIPS16. */ | |
0fe7e7c8 | 4625 | if (mips_pc_is_mips16 (pc)) |
c906108c SS |
4626 | return 0; |
4627 | ||
06648491 MK |
4628 | if (!breakpoint_here_p (pc + 4)) |
4629 | return 0; | |
4630 | ||
3352ef37 AC |
4631 | if (!safe_frame_unwind_memory (frame, pc, buf, sizeof buf)) |
4632 | /* If error reading memory, guess that it is not a delayed | |
4633 | branch. */ | |
c906108c | 4634 | return 0; |
4c7d22cb | 4635 | return is_delayed (extract_unsigned_integer (buf, sizeof buf)); |
c906108c SS |
4636 | } |
4637 | ||
6d82d43b AC |
4638 | /* To skip prologues, I use this predicate. Returns either PC itself |
4639 | if the code at PC does not look like a function prologue; otherwise | |
4640 | returns an address that (if we're lucky) follows the prologue. If | |
4641 | LENIENT, then we must skip everything which is involved in setting | |
4642 | up the frame (it's OK to skip more, just so long as we don't skip | |
4643 | anything which might clobber the registers which are being saved. | |
4644 | We must skip more in the case where part of the prologue is in the | |
4645 | delay slot of a non-prologue instruction). */ | |
4646 | ||
4647 | static CORE_ADDR | |
6093d2eb | 4648 | mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
6d82d43b | 4649 | { |
8b622e6a AC |
4650 | CORE_ADDR limit_pc; |
4651 | CORE_ADDR func_addr; | |
4652 | ||
6d82d43b AC |
4653 | /* See if we can determine the end of the prologue via the symbol table. |
4654 | If so, then return either PC, or the PC after the prologue, whichever | |
4655 | is greater. */ | |
8b622e6a AC |
4656 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
4657 | { | |
4658 | CORE_ADDR post_prologue_pc = skip_prologue_using_sal (func_addr); | |
4659 | if (post_prologue_pc != 0) | |
4660 | return max (pc, post_prologue_pc); | |
4661 | } | |
6d82d43b AC |
4662 | |
4663 | /* Can't determine prologue from the symbol table, need to examine | |
4664 | instructions. */ | |
4665 | ||
98b4dd94 JB |
4666 | /* Find an upper limit on the function prologue using the debug |
4667 | information. If the debug information could not be used to provide | |
4668 | that bound, then use an arbitrary large number as the upper bound. */ | |
4669 | limit_pc = skip_prologue_using_sal (pc); | |
4670 | if (limit_pc == 0) | |
4671 | limit_pc = pc + 100; /* Magic. */ | |
4672 | ||
0fe7e7c8 | 4673 | if (mips_pc_is_mips16 (pc)) |
a65bbe44 | 4674 | return mips16_scan_prologue (pc, limit_pc, NULL, NULL); |
6d82d43b | 4675 | else |
a65bbe44 | 4676 | return mips32_scan_prologue (pc, limit_pc, NULL, NULL); |
88658117 AC |
4677 | } |
4678 | ||
97ab0fdd MR |
4679 | /* Check whether the PC is in a function epilogue (32-bit version). |
4680 | This is a helper function for mips_in_function_epilogue_p. */ | |
4681 | static int | |
4682 | mips32_in_function_epilogue_p (CORE_ADDR pc) | |
4683 | { | |
4684 | CORE_ADDR func_addr = 0, func_end = 0; | |
4685 | ||
4686 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
4687 | { | |
4688 | /* The MIPS epilogue is max. 12 bytes long. */ | |
4689 | CORE_ADDR addr = func_end - 12; | |
4690 | ||
4691 | if (addr < func_addr + 4) | |
4692 | addr = func_addr + 4; | |
4693 | if (pc < addr) | |
4694 | return 0; | |
4695 | ||
4696 | for (; pc < func_end; pc += MIPS_INSN32_SIZE) | |
4697 | { | |
4698 | unsigned long high_word; | |
4699 | unsigned long inst; | |
4700 | ||
4701 | inst = mips_fetch_instruction (pc); | |
4702 | high_word = (inst >> 16) & 0xffff; | |
4703 | ||
4704 | if (high_word != 0x27bd /* addiu $sp,$sp,offset */ | |
4705 | && high_word != 0x67bd /* daddiu $sp,$sp,offset */ | |
4706 | && inst != 0x03e00008 /* jr $ra */ | |
4707 | && inst != 0x00000000) /* nop */ | |
4708 | return 0; | |
4709 | } | |
4710 | ||
4711 | return 1; | |
4712 | } | |
4713 | ||
4714 | return 0; | |
4715 | } | |
4716 | ||
4717 | /* Check whether the PC is in a function epilogue (16-bit version). | |
4718 | This is a helper function for mips_in_function_epilogue_p. */ | |
4719 | static int | |
4720 | mips16_in_function_epilogue_p (CORE_ADDR pc) | |
4721 | { | |
4722 | CORE_ADDR func_addr = 0, func_end = 0; | |
4723 | ||
4724 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
4725 | { | |
4726 | /* The MIPS epilogue is max. 12 bytes long. */ | |
4727 | CORE_ADDR addr = func_end - 12; | |
4728 | ||
4729 | if (addr < func_addr + 4) | |
4730 | addr = func_addr + 4; | |
4731 | if (pc < addr) | |
4732 | return 0; | |
4733 | ||
4734 | for (; pc < func_end; pc += MIPS_INSN16_SIZE) | |
4735 | { | |
4736 | unsigned short inst; | |
4737 | ||
4738 | inst = mips_fetch_instruction (pc); | |
4739 | ||
4740 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
4741 | continue; | |
4742 | ||
4743 | if (inst != 0x6300 /* addiu $sp,offset */ | |
4744 | && inst != 0xfb00 /* daddiu $sp,$sp,offset */ | |
4745 | && inst != 0xe820 /* jr $ra */ | |
4746 | && inst != 0xe8a0 /* jrc $ra */ | |
4747 | && inst != 0x6500) /* nop */ | |
4748 | return 0; | |
4749 | } | |
4750 | ||
4751 | return 1; | |
4752 | } | |
4753 | ||
4754 | return 0; | |
4755 | } | |
4756 | ||
4757 | /* The epilogue is defined here as the area at the end of a function, | |
4758 | after an instruction which destroys the function's stack frame. */ | |
4759 | static int | |
4760 | mips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
4761 | { | |
4762 | if (mips_pc_is_mips16 (pc)) | |
4763 | return mips16_in_function_epilogue_p (pc); | |
4764 | else | |
4765 | return mips32_in_function_epilogue_p (pc); | |
4766 | } | |
4767 | ||
a5ea2558 AC |
4768 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
4769 | used for all MIPS-specific commands. */ | |
4770 | ||
a5ea2558 | 4771 | static void |
acdb74a0 | 4772 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
4773 | { |
4774 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
4775 | } | |
4776 | ||
a5ea2558 | 4777 | static void |
acdb74a0 | 4778 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 4779 | { |
6d82d43b AC |
4780 | printf_unfiltered |
4781 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
4782 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
4783 | } | |
4784 | ||
c906108c SS |
4785 | /* Commands to show/set the MIPS FPU type. */ |
4786 | ||
c906108c | 4787 | static void |
acdb74a0 | 4788 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 4789 | { |
c906108c | 4790 | char *fpu; |
6ca0852e | 4791 | |
1cf3db46 | 4792 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips) |
6ca0852e UW |
4793 | { |
4794 | printf_unfiltered | |
4795 | ("The MIPS floating-point coprocessor is unknown " | |
4796 | "because the current architecture is not MIPS.\n"); | |
4797 | return; | |
4798 | } | |
4799 | ||
1cf3db46 | 4800 | switch (MIPS_FPU_TYPE (target_gdbarch)) |
c906108c SS |
4801 | { |
4802 | case MIPS_FPU_SINGLE: | |
4803 | fpu = "single-precision"; | |
4804 | break; | |
4805 | case MIPS_FPU_DOUBLE: | |
4806 | fpu = "double-precision"; | |
4807 | break; | |
4808 | case MIPS_FPU_NONE: | |
4809 | fpu = "absent (none)"; | |
4810 | break; | |
93d56215 | 4811 | default: |
e2e0b3e5 | 4812 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c SS |
4813 | } |
4814 | if (mips_fpu_type_auto) | |
6d82d43b AC |
4815 | printf_unfiltered |
4816 | ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
4817 | fpu); | |
c906108c | 4818 | else |
6d82d43b AC |
4819 | printf_unfiltered |
4820 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
4821 | } |
4822 | ||
4823 | ||
c906108c | 4824 | static void |
acdb74a0 | 4825 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 4826 | { |
6d82d43b AC |
4827 | printf_unfiltered |
4828 | ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
4829 | show_mipsfpu_command (args, from_tty); |
4830 | } | |
4831 | ||
c906108c | 4832 | static void |
acdb74a0 | 4833 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 4834 | { |
8d5838b5 AC |
4835 | struct gdbarch_info info; |
4836 | gdbarch_info_init (&info); | |
c906108c SS |
4837 | mips_fpu_type = MIPS_FPU_SINGLE; |
4838 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4839 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4840 | instead of relying on globals. Doing that would let generic code | |
4841 | handle the search for this specific architecture. */ | |
4842 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4843 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4844 | } |
4845 | ||
c906108c | 4846 | static void |
acdb74a0 | 4847 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 4848 | { |
8d5838b5 AC |
4849 | struct gdbarch_info info; |
4850 | gdbarch_info_init (&info); | |
c906108c SS |
4851 | mips_fpu_type = MIPS_FPU_DOUBLE; |
4852 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4853 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4854 | instead of relying on globals. Doing that would let generic code | |
4855 | handle the search for this specific architecture. */ | |
4856 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4857 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4858 | } |
4859 | ||
c906108c | 4860 | static void |
acdb74a0 | 4861 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 4862 | { |
8d5838b5 AC |
4863 | struct gdbarch_info info; |
4864 | gdbarch_info_init (&info); | |
c906108c SS |
4865 | mips_fpu_type = MIPS_FPU_NONE; |
4866 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4867 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4868 | instead of relying on globals. Doing that would let generic code | |
4869 | handle the search for this specific architecture. */ | |
4870 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4871 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4872 | } |
4873 | ||
c906108c | 4874 | static void |
acdb74a0 | 4875 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
4876 | { |
4877 | mips_fpu_type_auto = 1; | |
4878 | } | |
4879 | ||
c906108c | 4880 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
4881 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
4882 | the relevant processor still exists (it dates back to '94) and | |
4883 | secondly this is not the way to do this. The processor type should | |
4884 | be set by forcing an architecture change. */ | |
c906108c | 4885 | |
691c0433 AC |
4886 | void |
4887 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 4888 | { |
bb486190 UW |
4889 | struct regcache *regcache = get_current_regcache (); |
4890 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
4891 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
a9614958 | 4892 | ULONGEST prid; |
c906108c | 4893 | |
bb486190 | 4894 | regcache_cooked_read_unsigned (regcache, MIPS_PRID_REGNUM, &prid); |
c906108c | 4895 | if ((prid & ~0xf) == 0x700) |
691c0433 | 4896 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
4897 | } |
4898 | ||
4899 | /* Just like reinit_frame_cache, but with the right arguments to be | |
4900 | callable as an sfunc. */ | |
4901 | ||
4902 | static void | |
acdb74a0 AC |
4903 | reinit_frame_cache_sfunc (char *args, int from_tty, |
4904 | struct cmd_list_element *c) | |
c906108c SS |
4905 | { |
4906 | reinit_frame_cache (); | |
4907 | } | |
4908 | ||
a89aa300 AC |
4909 | static int |
4910 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 4911 | { |
d31431ed AC |
4912 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
4913 | disassembler needs to be able to locally determine the ISA, and | |
4914 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
4915 | work. */ | |
ec4045ea AC |
4916 | if (mips_pc_is_mips16 (memaddr)) |
4917 | info->mach = bfd_mach_mips16; | |
c906108c SS |
4918 | |
4919 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 4920 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 4921 | |
e5ab0dce | 4922 | /* Set the disassembler options. */ |
9dae60cc | 4923 | if (!info->disassembler_options) |
e5ab0dce AC |
4924 | /* This string is not recognized explicitly by the disassembler, |
4925 | but it tells the disassembler to not try to guess the ABI from | |
4926 | the bfd elf headers, such that, if the user overrides the ABI | |
4927 | of a program linked as NewABI, the disassembly will follow the | |
4928 | register naming conventions specified by the user. */ | |
4929 | info->disassembler_options = "gpr-names=32"; | |
4930 | ||
c906108c | 4931 | /* Call the appropriate disassembler based on the target endian-ness. */ |
40887e1a | 4932 | if (info->endian == BFD_ENDIAN_BIG) |
c906108c SS |
4933 | return print_insn_big_mips (memaddr, info); |
4934 | else | |
4935 | return print_insn_little_mips (memaddr, info); | |
4936 | } | |
4937 | ||
9dae60cc UW |
4938 | static int |
4939 | gdb_print_insn_mips_n32 (bfd_vma memaddr, struct disassemble_info *info) | |
4940 | { | |
4941 | /* Set up the disassembler info, so that we get the right | |
4942 | register names from libopcodes. */ | |
4943 | info->disassembler_options = "gpr-names=n32"; | |
4944 | info->flavour = bfd_target_elf_flavour; | |
4945 | ||
4946 | return gdb_print_insn_mips (memaddr, info); | |
4947 | } | |
4948 | ||
4949 | static int | |
4950 | gdb_print_insn_mips_n64 (bfd_vma memaddr, struct disassemble_info *info) | |
4951 | { | |
4952 | /* Set up the disassembler info, so that we get the right | |
4953 | register names from libopcodes. */ | |
4954 | info->disassembler_options = "gpr-names=64"; | |
4955 | info->flavour = bfd_target_elf_flavour; | |
4956 | ||
4957 | return gdb_print_insn_mips (memaddr, info); | |
4958 | } | |
4959 | ||
3b3b875c UW |
4960 | /* This function implements gdbarch_breakpoint_from_pc. It uses the program |
4961 | counter value to determine whether a 16- or 32-bit breakpoint should be used. | |
4962 | It returns a pointer to a string of bytes that encode a breakpoint | |
4963 | instruction, stores the length of the string to *lenptr, and adjusts pc (if | |
4964 | necessary) to point to the actual memory location where the breakpoint | |
4965 | should be inserted. */ | |
c906108c | 4966 | |
47a35522 | 4967 | static const gdb_byte * |
67d57894 | 4968 | mips_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr) |
c906108c | 4969 | { |
67d57894 | 4970 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
c906108c | 4971 | { |
0fe7e7c8 | 4972 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 4973 | { |
47a35522 | 4974 | static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
95404a3e | 4975 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 4976 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
4977 | return mips16_big_breakpoint; |
4978 | } | |
4979 | else | |
4980 | { | |
aaab4dba AC |
4981 | /* The IDT board uses an unusual breakpoint value, and |
4982 | sometimes gets confused when it sees the usual MIPS | |
4983 | breakpoint instruction. */ | |
47a35522 MK |
4984 | static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
4985 | static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
4986 | static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
c906108c | 4987 | |
c5aa993b | 4988 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
4989 | |
4990 | if (strcmp (target_shortname, "mips") == 0) | |
4991 | return idt_big_breakpoint; | |
4992 | else if (strcmp (target_shortname, "ddb") == 0 | |
4993 | || strcmp (target_shortname, "pmon") == 0 | |
4994 | || strcmp (target_shortname, "lsi") == 0) | |
4995 | return pmon_big_breakpoint; | |
4996 | else | |
4997 | return big_breakpoint; | |
4998 | } | |
4999 | } | |
5000 | else | |
5001 | { | |
0fe7e7c8 | 5002 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 5003 | { |
47a35522 | 5004 | static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
95404a3e | 5005 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5006 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
5007 | return mips16_little_breakpoint; |
5008 | } | |
5009 | else | |
5010 | { | |
47a35522 MK |
5011 | static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
5012 | static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
5013 | static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 5014 | |
c5aa993b | 5015 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
5016 | |
5017 | if (strcmp (target_shortname, "mips") == 0) | |
5018 | return idt_little_breakpoint; | |
5019 | else if (strcmp (target_shortname, "ddb") == 0 | |
5020 | || strcmp (target_shortname, "pmon") == 0 | |
5021 | || strcmp (target_shortname, "lsi") == 0) | |
5022 | return pmon_little_breakpoint; | |
5023 | else | |
5024 | return little_breakpoint; | |
5025 | } | |
5026 | } | |
5027 | } | |
5028 | ||
5029 | /* If PC is in a mips16 call or return stub, return the address of the target | |
5030 | PC, which is either the callee or the caller. There are several | |
5031 | cases which must be handled: | |
5032 | ||
5033 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 5034 | target PC is in $31 ($ra). |
c906108c | 5035 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 5036 | and the target PC is in $2. |
c906108c | 5037 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
5038 | before the jal instruction, this is effectively a call stub |
5039 | and the the target PC is in $2. Otherwise this is effectively | |
5040 | a return stub and the target PC is in $18. | |
c906108c SS |
5041 | |
5042 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
e7d6a6d2 | 5043 | gory details. */ |
c906108c | 5044 | |
757a7cc6 | 5045 | static CORE_ADDR |
52f729a7 | 5046 | mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
c906108c SS |
5047 | { |
5048 | char *name; | |
5049 | CORE_ADDR start_addr; | |
5050 | ||
5051 | /* Find the starting address and name of the function containing the PC. */ | |
5052 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
5053 | return 0; | |
5054 | ||
5055 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
5056 | target PC is in $31 ($ra). */ | |
5057 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5058 | || strcmp (name, "__mips16_ret_df") == 0) | |
52f729a7 | 5059 | return get_frame_register_signed (frame, MIPS_RA_REGNUM); |
c906108c SS |
5060 | |
5061 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5062 | { | |
5063 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
5064 | and the target PC is in $2. */ | |
5065 | if (name[19] >= '0' && name[19] <= '9') | |
52f729a7 | 5066 | return get_frame_register_signed (frame, 2); |
c906108c SS |
5067 | |
5068 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
5069 | before the jal instruction, this is effectively a call stub |
5070 | and the the target PC is in $2. Otherwise this is effectively | |
5071 | a return stub and the target PC is in $18. */ | |
c906108c SS |
5072 | else if (name[19] == 's' || name[19] == 'd') |
5073 | { | |
5074 | if (pc == start_addr) | |
5075 | { | |
5076 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
5077 | stub. Such a stub for a function bar might have a name |
5078 | like __fn_stub_bar, and might look like this: | |
5079 | mfc1 $4,$f13 | |
5080 | mfc1 $5,$f12 | |
5081 | mfc1 $6,$f15 | |
5082 | mfc1 $7,$f14 | |
5083 | la $1,bar (becomes a lui/addiu pair) | |
5084 | jr $1 | |
5085 | So scan down to the lui/addi and extract the target | |
5086 | address from those two instructions. */ | |
c906108c | 5087 | |
52f729a7 | 5088 | CORE_ADDR target_pc = get_frame_register_signed (frame, 2); |
d37cca3d | 5089 | ULONGEST inst; |
c906108c SS |
5090 | int i; |
5091 | ||
5092 | /* See if the name of the target function is __fn_stub_*. */ | |
6d82d43b AC |
5093 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == |
5094 | 0) | |
c906108c SS |
5095 | return target_pc; |
5096 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
5097 | && strcmp (name, "etext") != 0 | |
5098 | && strcmp (name, "_etext") != 0) | |
5099 | return target_pc; | |
5100 | ||
5101 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
5102 | The limit on the search is arbitrarily set to 20 |
5103 | instructions. FIXME. */ | |
95ac2dcf | 5104 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSN32_SIZE) |
c906108c | 5105 | { |
c5aa993b JM |
5106 | inst = mips_fetch_instruction (target_pc); |
5107 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
5108 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
5109 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
5110 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
5111 | } |
5112 | ||
5113 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
5114 | return target_pc; | |
5115 | } | |
5116 | else | |
5117 | /* This is the 'return' part of a call stub. The return | |
5118 | address is in $r18. */ | |
52f729a7 | 5119 | return get_frame_register_signed (frame, 18); |
c906108c SS |
5120 | } |
5121 | } | |
c5aa993b | 5122 | return 0; /* not a stub */ |
c906108c SS |
5123 | } |
5124 | ||
a4b8ebc8 | 5125 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
f57d151a | 5126 | [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
5127 | |
5128 | static int | |
d3f73121 | 5129 | mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 5130 | { |
a4b8ebc8 | 5131 | int regnum; |
2f38ef89 | 5132 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5133 | regnum = num; |
2f38ef89 | 5134 | else if (num >= 38 && num < 70) |
d3f73121 | 5135 | regnum = num + mips_regnum (gdbarch)->fp0 - 38; |
040b99fd | 5136 | else if (num == 70) |
d3f73121 | 5137 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 5138 | else if (num == 71) |
d3f73121 | 5139 | regnum = mips_regnum (gdbarch)->lo; |
2f38ef89 | 5140 | else |
a4b8ebc8 AC |
5141 | /* This will hopefully (eventually) provoke a warning. Should |
5142 | we be calling complaint() here? */ | |
d3f73121 MD |
5143 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
5144 | return gdbarch_num_regs (gdbarch) + regnum; | |
88c72b7d AC |
5145 | } |
5146 | ||
2f38ef89 | 5147 | |
a4b8ebc8 | 5148 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
f57d151a | 5149 | gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
5150 | |
5151 | static int | |
d3f73121 | 5152 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 5153 | { |
a4b8ebc8 | 5154 | int regnum; |
2f38ef89 | 5155 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5156 | regnum = num; |
2f38ef89 | 5157 | else if (num >= 32 && num < 64) |
d3f73121 | 5158 | regnum = num + mips_regnum (gdbarch)->fp0 - 32; |
040b99fd | 5159 | else if (num == 64) |
d3f73121 | 5160 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 5161 | else if (num == 65) |
d3f73121 | 5162 | regnum = mips_regnum (gdbarch)->lo; |
2f38ef89 | 5163 | else |
a4b8ebc8 AC |
5164 | /* This will hopefully (eventually) provoke a warning. Should we |
5165 | be calling complaint() here? */ | |
d3f73121 MD |
5166 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
5167 | return gdbarch_num_regs (gdbarch) + regnum; | |
a4b8ebc8 AC |
5168 | } |
5169 | ||
5170 | static int | |
e7faf938 | 5171 | mips_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
a4b8ebc8 AC |
5172 | { |
5173 | /* Only makes sense to supply raw registers. */ | |
e7faf938 | 5174 | gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)); |
a4b8ebc8 AC |
5175 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to |
5176 | decide if it is valid. Should instead define a standard sim/gdb | |
5177 | register numbering scheme. */ | |
e7faf938 MD |
5178 | if (gdbarch_register_name (gdbarch, |
5179 | gdbarch_num_regs (gdbarch) + regnum) != NULL | |
5180 | && gdbarch_register_name (gdbarch, | |
5181 | gdbarch_num_regs (gdbarch) + regnum)[0] != '\0') | |
a4b8ebc8 AC |
5182 | return regnum; |
5183 | else | |
6d82d43b | 5184 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
5185 | } |
5186 | ||
2f38ef89 | 5187 | |
4844f454 CV |
5188 | /* Convert an integer into an address. Extracting the value signed |
5189 | guarantees a correctly sign extended address. */ | |
fc0c74b1 AC |
5190 | |
5191 | static CORE_ADDR | |
79dd2d24 | 5192 | mips_integer_to_address (struct gdbarch *gdbarch, |
870cd05e | 5193 | struct type *type, const gdb_byte *buf) |
fc0c74b1 | 5194 | { |
4844f454 | 5195 | return (CORE_ADDR) extract_signed_integer (buf, TYPE_LENGTH (type)); |
fc0c74b1 AC |
5196 | } |
5197 | ||
82e91389 DJ |
5198 | /* Dummy virtual frame pointer method. This is no more or less accurate |
5199 | than most other architectures; we just need to be explicit about it, | |
5200 | because the pseudo-register gdbarch_sp_regnum will otherwise lead to | |
5201 | an assertion failure. */ | |
5202 | ||
5203 | static void | |
a54fba4c MD |
5204 | mips_virtual_frame_pointer (struct gdbarch *gdbarch, |
5205 | CORE_ADDR pc, int *reg, LONGEST *offset) | |
82e91389 DJ |
5206 | { |
5207 | *reg = MIPS_SP_REGNUM; | |
5208 | *offset = 0; | |
5209 | } | |
5210 | ||
caaa3122 DJ |
5211 | static void |
5212 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
5213 | { | |
5214 | enum mips_abi *abip = (enum mips_abi *) obj; | |
5215 | const char *name = bfd_get_section_name (abfd, sect); | |
5216 | ||
5217 | if (*abip != MIPS_ABI_UNKNOWN) | |
5218 | return; | |
5219 | ||
5220 | if (strncmp (name, ".mdebug.", 8) != 0) | |
5221 | return; | |
5222 | ||
5223 | if (strcmp (name, ".mdebug.abi32") == 0) | |
5224 | *abip = MIPS_ABI_O32; | |
5225 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
5226 | *abip = MIPS_ABI_N32; | |
62a49b2c | 5227 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 5228 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
5229 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
5230 | *abip = MIPS_ABI_O64; | |
5231 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
5232 | *abip = MIPS_ABI_EABI32; | |
5233 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
5234 | *abip = MIPS_ABI_EABI64; | |
5235 | else | |
8a3fe4f8 | 5236 | warning (_("unsupported ABI %s."), name + 8); |
caaa3122 DJ |
5237 | } |
5238 | ||
22e47e37 FF |
5239 | static void |
5240 | mips_find_long_section (bfd *abfd, asection *sect, void *obj) | |
5241 | { | |
5242 | int *lbp = (int *) obj; | |
5243 | const char *name = bfd_get_section_name (abfd, sect); | |
5244 | ||
5245 | if (strncmp (name, ".gcc_compiled_long32", 20) == 0) | |
5246 | *lbp = 32; | |
5247 | else if (strncmp (name, ".gcc_compiled_long64", 20) == 0) | |
5248 | *lbp = 64; | |
5249 | else if (strncmp (name, ".gcc_compiled_long", 18) == 0) | |
5250 | warning (_("unrecognized .gcc_compiled_longXX")); | |
5251 | } | |
5252 | ||
2e4ebe70 DJ |
5253 | static enum mips_abi |
5254 | global_mips_abi (void) | |
5255 | { | |
5256 | int i; | |
5257 | ||
5258 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
5259 | if (mips_abi_strings[i] == mips_abi_string) | |
5260 | return (enum mips_abi) i; | |
5261 | ||
e2e0b3e5 | 5262 | internal_error (__FILE__, __LINE__, _("unknown ABI string")); |
2e4ebe70 DJ |
5263 | } |
5264 | ||
29709017 DJ |
5265 | static void |
5266 | mips_register_g_packet_guesses (struct gdbarch *gdbarch) | |
5267 | { | |
29709017 DJ |
5268 | /* If the size matches the set of 32-bit or 64-bit integer registers, |
5269 | assume that's what we've got. */ | |
4eb0ad19 DJ |
5270 | register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32); |
5271 | register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64); | |
29709017 DJ |
5272 | |
5273 | /* If the size matches the full set of registers GDB traditionally | |
5274 | knows about, including floating point, for either 32-bit or | |
5275 | 64-bit, assume that's what we've got. */ | |
4eb0ad19 DJ |
5276 | register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32); |
5277 | register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64); | |
29709017 DJ |
5278 | |
5279 | /* Otherwise we don't have a useful guess. */ | |
5280 | } | |
5281 | ||
f8b73d13 DJ |
5282 | static struct value * |
5283 | value_of_mips_user_reg (struct frame_info *frame, const void *baton) | |
5284 | { | |
5285 | const int *reg_p = baton; | |
5286 | return value_of_register (*reg_p, frame); | |
5287 | } | |
5288 | ||
c2d11a7d | 5289 | static struct gdbarch * |
6d82d43b | 5290 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 5291 | { |
c2d11a7d JM |
5292 | struct gdbarch *gdbarch; |
5293 | struct gdbarch_tdep *tdep; | |
5294 | int elf_flags; | |
2e4ebe70 | 5295 | enum mips_abi mips_abi, found_abi, wanted_abi; |
f8b73d13 | 5296 | int i, num_regs; |
8d5838b5 | 5297 | enum mips_fpu_type fpu_type; |
f8b73d13 | 5298 | struct tdesc_arch_data *tdesc_data = NULL; |
609ca2b9 | 5299 | int elf_fpu_type = 0; |
f8b73d13 DJ |
5300 | |
5301 | /* Check any target description for validity. */ | |
5302 | if (tdesc_has_registers (info.target_desc)) | |
5303 | { | |
5304 | static const char *const mips_gprs[] = { | |
5305 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
5306 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
5307 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
5308 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
5309 | }; | |
5310 | static const char *const mips_fprs[] = { | |
5311 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
5312 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
5313 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
5314 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
5315 | }; | |
5316 | ||
5317 | const struct tdesc_feature *feature; | |
5318 | int valid_p; | |
5319 | ||
5320 | feature = tdesc_find_feature (info.target_desc, | |
5321 | "org.gnu.gdb.mips.cpu"); | |
5322 | if (feature == NULL) | |
5323 | return NULL; | |
5324 | ||
5325 | tdesc_data = tdesc_data_alloc (); | |
5326 | ||
5327 | valid_p = 1; | |
5328 | for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) | |
5329 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
5330 | mips_gprs[i]); | |
5331 | ||
5332 | ||
5333 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5334 | MIPS_EMBED_LO_REGNUM, "lo"); | |
5335 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5336 | MIPS_EMBED_HI_REGNUM, "hi"); | |
5337 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5338 | MIPS_EMBED_PC_REGNUM, "pc"); | |
5339 | ||
5340 | if (!valid_p) | |
5341 | { | |
5342 | tdesc_data_cleanup (tdesc_data); | |
5343 | return NULL; | |
5344 | } | |
5345 | ||
5346 | feature = tdesc_find_feature (info.target_desc, | |
5347 | "org.gnu.gdb.mips.cp0"); | |
5348 | if (feature == NULL) | |
5349 | { | |
5350 | tdesc_data_cleanup (tdesc_data); | |
5351 | return NULL; | |
5352 | } | |
5353 | ||
5354 | valid_p = 1; | |
5355 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5356 | MIPS_EMBED_BADVADDR_REGNUM, | |
5357 | "badvaddr"); | |
5358 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5359 | MIPS_PS_REGNUM, "status"); | |
5360 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5361 | MIPS_EMBED_CAUSE_REGNUM, "cause"); | |
5362 | ||
5363 | if (!valid_p) | |
5364 | { | |
5365 | tdesc_data_cleanup (tdesc_data); | |
5366 | return NULL; | |
5367 | } | |
5368 | ||
5369 | /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS | |
5370 | backend is not prepared for that, though. */ | |
5371 | feature = tdesc_find_feature (info.target_desc, | |
5372 | "org.gnu.gdb.mips.fpu"); | |
5373 | if (feature == NULL) | |
5374 | { | |
5375 | tdesc_data_cleanup (tdesc_data); | |
5376 | return NULL; | |
5377 | } | |
5378 | ||
5379 | valid_p = 1; | |
5380 | for (i = 0; i < 32; i++) | |
5381 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5382 | i + MIPS_EMBED_FP0_REGNUM, | |
5383 | mips_fprs[i]); | |
5384 | ||
5385 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5386 | MIPS_EMBED_FP0_REGNUM + 32, "fcsr"); | |
5387 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5388 | MIPS_EMBED_FP0_REGNUM + 33, "fir"); | |
5389 | ||
5390 | if (!valid_p) | |
5391 | { | |
5392 | tdesc_data_cleanup (tdesc_data); | |
5393 | return NULL; | |
5394 | } | |
5395 | ||
5396 | /* It would be nice to detect an attempt to use a 64-bit ABI | |
5397 | when only 32-bit registers are provided. */ | |
5398 | } | |
c2d11a7d | 5399 | |
ec03c1ac AC |
5400 | /* First of all, extract the elf_flags, if available. */ |
5401 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5402 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
5403 | else if (arches != NULL) |
5404 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
5405 | else |
5406 | elf_flags = 0; | |
5407 | if (gdbarch_debug) | |
5408 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5409 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 5410 | |
102182a9 | 5411 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
5412 | switch ((elf_flags & EF_MIPS_ABI)) |
5413 | { | |
5414 | case E_MIPS_ABI_O32: | |
ec03c1ac | 5415 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
5416 | break; |
5417 | case E_MIPS_ABI_O64: | |
ec03c1ac | 5418 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
5419 | break; |
5420 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 5421 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
5422 | break; |
5423 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 5424 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
5425 | break; |
5426 | default: | |
acdb74a0 | 5427 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 5428 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 5429 | else |
ec03c1ac | 5430 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
5431 | break; |
5432 | } | |
acdb74a0 | 5433 | |
caaa3122 | 5434 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
5435 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
5436 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 5437 | |
dc305454 | 5438 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
5439 | MIPS architecture (if there is one). */ |
5440 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
5441 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 5442 | |
32a6503c | 5443 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 5444 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
5445 | && info.bfd_arch_info != NULL |
5446 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5447 | { | |
5448 | switch (info.bfd_arch_info->mach) | |
5449 | { | |
5450 | case bfd_mach_mips3900: | |
ec03c1ac | 5451 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
5452 | break; |
5453 | case bfd_mach_mips4100: | |
5454 | case bfd_mach_mips5000: | |
ec03c1ac | 5455 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 5456 | break; |
1d06468c EZ |
5457 | case bfd_mach_mips8000: |
5458 | case bfd_mach_mips10000: | |
32a6503c KB |
5459 | /* On Irix, ELF64 executables use the N64 ABI. The |
5460 | pseudo-sections which describe the ABI aren't present | |
5461 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
5462 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
5463 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 5464 | found_abi = MIPS_ABI_N64; |
28d169de | 5465 | else |
ec03c1ac | 5466 | found_abi = MIPS_ABI_N32; |
1d06468c | 5467 | break; |
bf64bfd6 AC |
5468 | } |
5469 | } | |
2e4ebe70 | 5470 | |
26c53e50 DJ |
5471 | /* Default 64-bit objects to N64 instead of O32. */ |
5472 | if (found_abi == MIPS_ABI_UNKNOWN | |
5473 | && info.abfd != NULL | |
5474 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
5475 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
5476 | found_abi = MIPS_ABI_N64; | |
5477 | ||
ec03c1ac AC |
5478 | if (gdbarch_debug) |
5479 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
5480 | found_abi); | |
5481 | ||
5482 | /* What has the user specified from the command line? */ | |
5483 | wanted_abi = global_mips_abi (); | |
5484 | if (gdbarch_debug) | |
5485 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
5486 | wanted_abi); | |
2e4ebe70 DJ |
5487 | |
5488 | /* Now that we have found what the ABI for this binary would be, | |
5489 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
5490 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
5491 | mips_abi = wanted_abi; | |
ec03c1ac AC |
5492 | else if (found_abi != MIPS_ABI_UNKNOWN) |
5493 | mips_abi = found_abi; | |
5494 | else | |
5495 | mips_abi = MIPS_ABI_O32; | |
5496 | if (gdbarch_debug) | |
5497 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
5498 | mips_abi); | |
2e4ebe70 | 5499 | |
ec03c1ac | 5500 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 5501 | if (gdbarch_debug) |
ec03c1ac AC |
5502 | fprintf_unfiltered (gdb_stdlog, |
5503 | "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n", | |
5504 | mips64_transfers_32bit_regs_p); | |
0dadbba0 | 5505 | |
8d5838b5 | 5506 | /* Determine the MIPS FPU type. */ |
609ca2b9 DJ |
5507 | #ifdef HAVE_ELF |
5508 | if (info.abfd | |
5509 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5510 | elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
5511 | Tag_GNU_MIPS_ABI_FP); | |
5512 | #endif /* HAVE_ELF */ | |
5513 | ||
8d5838b5 AC |
5514 | if (!mips_fpu_type_auto) |
5515 | fpu_type = mips_fpu_type; | |
609ca2b9 DJ |
5516 | else if (elf_fpu_type != 0) |
5517 | { | |
5518 | switch (elf_fpu_type) | |
5519 | { | |
5520 | case 1: | |
5521 | fpu_type = MIPS_FPU_DOUBLE; | |
5522 | break; | |
5523 | case 2: | |
5524 | fpu_type = MIPS_FPU_SINGLE; | |
5525 | break; | |
5526 | case 3: | |
5527 | default: | |
5528 | /* Soft float or unknown. */ | |
5529 | fpu_type = MIPS_FPU_NONE; | |
5530 | break; | |
5531 | } | |
5532 | } | |
8d5838b5 AC |
5533 | else if (info.bfd_arch_info != NULL |
5534 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5535 | switch (info.bfd_arch_info->mach) | |
5536 | { | |
5537 | case bfd_mach_mips3900: | |
5538 | case bfd_mach_mips4100: | |
5539 | case bfd_mach_mips4111: | |
a9d61c86 | 5540 | case bfd_mach_mips4120: |
8d5838b5 AC |
5541 | fpu_type = MIPS_FPU_NONE; |
5542 | break; | |
5543 | case bfd_mach_mips4650: | |
5544 | fpu_type = MIPS_FPU_SINGLE; | |
5545 | break; | |
5546 | default: | |
5547 | fpu_type = MIPS_FPU_DOUBLE; | |
5548 | break; | |
5549 | } | |
5550 | else if (arches != NULL) | |
5551 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
5552 | else | |
5553 | fpu_type = MIPS_FPU_DOUBLE; | |
5554 | if (gdbarch_debug) | |
5555 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5556 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 5557 | |
29709017 DJ |
5558 | /* Check for blatant incompatibilities. */ |
5559 | ||
5560 | /* If we have only 32-bit registers, then we can't debug a 64-bit | |
5561 | ABI. */ | |
5562 | if (info.target_desc | |
5563 | && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL | |
5564 | && mips_abi != MIPS_ABI_EABI32 | |
5565 | && mips_abi != MIPS_ABI_O32) | |
f8b73d13 DJ |
5566 | { |
5567 | if (tdesc_data != NULL) | |
5568 | tdesc_data_cleanup (tdesc_data); | |
5569 | return NULL; | |
5570 | } | |
29709017 | 5571 | |
c2d11a7d JM |
5572 | /* try to find a pre-existing architecture */ |
5573 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
5574 | arches != NULL; | |
5575 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
5576 | { | |
5577 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 5578 | using. */ |
9103eae0 | 5579 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 5580 | continue; |
9103eae0 | 5581 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 5582 | continue; |
719ec221 AC |
5583 | /* Need to be pedantic about which register virtual size is |
5584 | used. */ | |
5585 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
5586 | != mips64_transfers_32bit_regs_p) | |
5587 | continue; | |
8d5838b5 AC |
5588 | /* Be pedantic about which FPU is selected. */ |
5589 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
5590 | continue; | |
f8b73d13 DJ |
5591 | |
5592 | if (tdesc_data != NULL) | |
5593 | tdesc_data_cleanup (tdesc_data); | |
4be87837 | 5594 | return arches->gdbarch; |
c2d11a7d JM |
5595 | } |
5596 | ||
102182a9 | 5597 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
5598 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
5599 | gdbarch = gdbarch_alloc (&info, tdep); | |
5600 | tdep->elf_flags = elf_flags; | |
719ec221 | 5601 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
5602 | tdep->found_abi = found_abi; |
5603 | tdep->mips_abi = mips_abi; | |
8d5838b5 | 5604 | tdep->mips_fpu_type = fpu_type; |
29709017 DJ |
5605 | tdep->register_size_valid_p = 0; |
5606 | tdep->register_size = 0; | |
5607 | ||
5608 | if (info.target_desc) | |
5609 | { | |
5610 | /* Some useful properties can be inferred from the target. */ | |
5611 | if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) | |
5612 | { | |
5613 | tdep->register_size_valid_p = 1; | |
5614 | tdep->register_size = 4; | |
5615 | } | |
5616 | else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) | |
5617 | { | |
5618 | tdep->register_size_valid_p = 1; | |
5619 | tdep->register_size = 8; | |
5620 | } | |
5621 | } | |
c2d11a7d | 5622 | |
102182a9 | 5623 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
5624 | set_gdbarch_short_bit (gdbarch, 16); |
5625 | set_gdbarch_int_bit (gdbarch, 32); | |
5626 | set_gdbarch_float_bit (gdbarch, 32); | |
5627 | set_gdbarch_double_bit (gdbarch, 64); | |
5628 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
5629 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
5630 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
5631 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 5632 | |
6d82d43b | 5633 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
5634 | mips_elf_make_msymbol_special); |
5635 | ||
16e109ca | 5636 | /* Fill in the OS dependant register numbers and names. */ |
56cea623 | 5637 | { |
16e109ca | 5638 | const char **reg_names; |
56cea623 AC |
5639 | struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, |
5640 | struct mips_regnum); | |
f8b73d13 DJ |
5641 | if (tdesc_has_registers (info.target_desc)) |
5642 | { | |
5643 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5644 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5645 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5646 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5647 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5648 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5649 | regnum->fp_control_status = 70; | |
5650 | regnum->fp_implementation_revision = 71; | |
5651 | num_regs = MIPS_LAST_EMBED_REGNUM + 1; | |
5652 | reg_names = NULL; | |
5653 | } | |
5654 | else if (info.osabi == GDB_OSABI_IRIX) | |
56cea623 AC |
5655 | { |
5656 | regnum->fp0 = 32; | |
5657 | regnum->pc = 64; | |
5658 | regnum->cause = 65; | |
5659 | regnum->badvaddr = 66; | |
5660 | regnum->hi = 67; | |
5661 | regnum->lo = 68; | |
5662 | regnum->fp_control_status = 69; | |
5663 | regnum->fp_implementation_revision = 70; | |
5664 | num_regs = 71; | |
16e109ca | 5665 | reg_names = mips_irix_reg_names; |
56cea623 AC |
5666 | } |
5667 | else | |
5668 | { | |
5669 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5670 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5671 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5672 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5673 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5674 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5675 | regnum->fp_control_status = 70; | |
5676 | regnum->fp_implementation_revision = 71; | |
5677 | num_regs = 90; | |
16e109ca AC |
5678 | if (info.bfd_arch_info != NULL |
5679 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
5680 | reg_names = mips_tx39_reg_names; | |
5681 | else | |
5682 | reg_names = mips_generic_reg_names; | |
56cea623 | 5683 | } |
3e8c568d | 5684 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been |
56cea623 | 5685 | replaced by read_pc? */ |
f10683bb MH |
5686 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); |
5687 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
56cea623 AC |
5688 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
5689 | set_gdbarch_num_regs (gdbarch, num_regs); | |
5690 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
16e109ca | 5691 | set_gdbarch_register_name (gdbarch, mips_register_name); |
82e91389 | 5692 | set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer); |
16e109ca AC |
5693 | tdep->mips_processor_reg_names = reg_names; |
5694 | tdep->regnum = regnum; | |
56cea623 | 5695 | } |
fe29b929 | 5696 | |
0dadbba0 | 5697 | switch (mips_abi) |
c2d11a7d | 5698 | { |
0dadbba0 | 5699 | case MIPS_ABI_O32: |
25ab4790 | 5700 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 5701 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
4c7d22cb | 5702 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 5703 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 5704 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5705 | set_gdbarch_long_bit (gdbarch, 32); |
5706 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5707 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5708 | break; | |
0dadbba0 | 5709 | case MIPS_ABI_O64: |
25ab4790 | 5710 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
9c8fdbfa | 5711 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
4c7d22cb | 5712 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 5713 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 5714 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5715 | set_gdbarch_long_bit (gdbarch, 32); |
5716 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5717 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5718 | break; | |
0dadbba0 | 5719 | case MIPS_ABI_EABI32: |
25ab4790 | 5720 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 5721 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 5722 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5723 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5724 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5725 | set_gdbarch_long_bit (gdbarch, 32); |
5726 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5727 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5728 | break; | |
0dadbba0 | 5729 | case MIPS_ABI_EABI64: |
25ab4790 | 5730 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 5731 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 5732 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5733 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5734 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5735 | set_gdbarch_long_bit (gdbarch, 64); |
5736 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5737 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5738 | break; | |
0dadbba0 | 5739 | case MIPS_ABI_N32: |
25ab4790 | 5740 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5741 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 5742 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5743 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5744 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
5745 | set_gdbarch_long_bit (gdbarch, 32); |
5746 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5747 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 5748 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 5749 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
28d169de KB |
5750 | break; |
5751 | case MIPS_ABI_N64: | |
25ab4790 | 5752 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5753 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 5754 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5755 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
5756 | tdep->default_mask_address_p = 0; |
5757 | set_gdbarch_long_bit (gdbarch, 64); | |
5758 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5759 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 5760 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 5761 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
0dadbba0 | 5762 | break; |
c2d11a7d | 5763 | default: |
e2e0b3e5 | 5764 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); |
c2d11a7d JM |
5765 | } |
5766 | ||
22e47e37 FF |
5767 | /* GCC creates a pseudo-section whose name specifies the size of |
5768 | longs, since -mlong32 or -mlong64 may be used independent of | |
5769 | other options. How those options affect pointer sizes is ABI and | |
5770 | architecture dependent, so use them to override the default sizes | |
5771 | set by the ABI. This table shows the relationship between ABI, | |
5772 | -mlongXX, and size of pointers: | |
5773 | ||
5774 | ABI -mlongXX ptr bits | |
5775 | --- -------- -------- | |
5776 | o32 32 32 | |
5777 | o32 64 32 | |
5778 | n32 32 32 | |
5779 | n32 64 64 | |
5780 | o64 32 32 | |
5781 | o64 64 64 | |
5782 | n64 32 32 | |
5783 | n64 64 64 | |
5784 | eabi32 32 32 | |
5785 | eabi32 64 32 | |
5786 | eabi64 32 32 | |
5787 | eabi64 64 64 | |
5788 | ||
5789 | Note that for o32 and eabi32, pointers are always 32 bits | |
5790 | regardless of any -mlongXX option. For all others, pointers and | |
5791 | longs are the same, as set by -mlongXX or set by defaults. | |
5792 | */ | |
5793 | ||
5794 | if (info.abfd != NULL) | |
5795 | { | |
5796 | int long_bit = 0; | |
5797 | ||
5798 | bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); | |
5799 | if (long_bit) | |
5800 | { | |
5801 | set_gdbarch_long_bit (gdbarch, long_bit); | |
5802 | switch (mips_abi) | |
5803 | { | |
5804 | case MIPS_ABI_O32: | |
5805 | case MIPS_ABI_EABI32: | |
5806 | break; | |
5807 | case MIPS_ABI_N32: | |
5808 | case MIPS_ABI_O64: | |
5809 | case MIPS_ABI_N64: | |
5810 | case MIPS_ABI_EABI64: | |
5811 | set_gdbarch_ptr_bit (gdbarch, long_bit); | |
5812 | break; | |
5813 | default: | |
5814 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); | |
5815 | } | |
5816 | } | |
5817 | } | |
5818 | ||
a5ea2558 AC |
5819 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
5820 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
5821 | comment: | |
5822 | ||
5823 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
5824 | flag in object files because to do so would make it impossible to | |
102182a9 | 5825 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 5826 | unnecessarily restrictive. |
361d1df0 | 5827 | |
a5ea2558 AC |
5828 | We could solve this problem by adding "-gp32" multilibs to gcc, |
5829 | but to set this flag before gcc is built with such multilibs will | |
5830 | break too many systems.'' | |
5831 | ||
5832 | But even more unhelpfully, the default linker output target for | |
5833 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
5834 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 5835 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
5836 | this flag to detect 32-bit mode would do the wrong thing given |
5837 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 5838 | as 32-bit programs by default. */ |
a5ea2558 | 5839 | |
6c997a34 | 5840 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 5841 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
c2d11a7d | 5842 | |
102182a9 MS |
5843 | /* Add/remove bits from an address. The MIPS needs be careful to |
5844 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
5845 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
5846 | ||
58dfe9ff AC |
5847 | /* Unwind the frame. */ |
5848 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
30244cd8 | 5849 | set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); |
b8a22b94 | 5850 | set_gdbarch_dummy_id (gdbarch, mips_dummy_id); |
10312cc4 | 5851 | |
102182a9 | 5852 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 5853 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
5854 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
5855 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
6d82d43b AC |
5856 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, |
5857 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 5858 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 5859 | |
c2d11a7d JM |
5860 | /* MIPS version of CALL_DUMMY */ |
5861 | ||
9710e734 AC |
5862 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
5863 | replaced by a command, and all targets will default to on stack | |
5864 | (regardless of the stack's execute status). */ | |
5865 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
dc604539 | 5866 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 5867 | |
87783b8b AC |
5868 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
5869 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
5870 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
5871 | ||
f7b9e9fc AC |
5872 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
5873 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
f7b9e9fc AC |
5874 | |
5875 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 5876 | |
97ab0fdd MR |
5877 | set_gdbarch_in_function_epilogue_p (gdbarch, mips_in_function_epilogue_p); |
5878 | ||
fc0c74b1 AC |
5879 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
5880 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
5881 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 5882 | |
a4b8ebc8 | 5883 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 5884 | |
e11c53d2 | 5885 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 5886 | |
9dae60cc UW |
5887 | if (mips_abi == MIPS_ABI_N32) |
5888 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n32); | |
5889 | else if (mips_abi == MIPS_ABI_N64) | |
5890 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n64); | |
5891 | else | |
5892 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); | |
e5ab0dce | 5893 | |
3a3bc038 AC |
5894 | /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT, |
5895 | HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT | |
5896 | need to all be folded into the target vector. Since they are | |
5897 | being used as guards for STOPPED_BY_WATCHPOINT, why not have | |
5898 | STOPPED_BY_WATCHPOINT return the type of watchpoint that the code | |
5899 | is sitting on? */ | |
5900 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
5901 | ||
e7d6a6d2 | 5902 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
757a7cc6 | 5903 | |
3352ef37 AC |
5904 | set_gdbarch_single_step_through_delay (gdbarch, mips_single_step_through_delay); |
5905 | ||
0d5de010 DJ |
5906 | /* Virtual tables. */ |
5907 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
5908 | ||
29709017 DJ |
5909 | mips_register_g_packet_guesses (gdbarch); |
5910 | ||
6de918a6 | 5911 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
822b6570 | 5912 | info.tdep_info = (void *) tdesc_data; |
6de918a6 | 5913 | gdbarch_init_osabi (info, gdbarch); |
757a7cc6 | 5914 | |
5792a79b | 5915 | /* Unwind the frame. */ |
b8a22b94 DJ |
5916 | dwarf2_append_unwinders (gdbarch); |
5917 | frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind); | |
5918 | frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind); | |
5919 | frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind); | |
2bd0c3d7 | 5920 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
eec63939 | 5921 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
45c9dd44 AC |
5922 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
5923 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); | |
5792a79b | 5924 | |
f8b73d13 DJ |
5925 | if (tdesc_data) |
5926 | { | |
5927 | set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); | |
7cc46491 | 5928 | tdesc_use_registers (gdbarch, info.target_desc, tdesc_data); |
f8b73d13 DJ |
5929 | |
5930 | /* Override the normal target description methods to handle our | |
5931 | dual real and pseudo registers. */ | |
5932 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
5933 | set_gdbarch_register_reggroup_p (gdbarch, mips_tdesc_register_reggroup_p); | |
5934 | ||
5935 | num_regs = gdbarch_num_regs (gdbarch); | |
5936 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
5937 | set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs); | |
5938 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
5939 | } | |
5940 | ||
5941 | /* Add ABI-specific aliases for the registers. */ | |
5942 | if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) | |
5943 | for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++) | |
5944 | user_reg_add (gdbarch, mips_n32_n64_aliases[i].name, | |
5945 | value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); | |
5946 | else | |
5947 | for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) | |
5948 | user_reg_add (gdbarch, mips_o32_aliases[i].name, | |
5949 | value_of_mips_user_reg, &mips_o32_aliases[i].regnum); | |
5950 | ||
5951 | /* Add some other standard aliases. */ | |
5952 | for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) | |
5953 | user_reg_add (gdbarch, mips_register_aliases[i].name, | |
5954 | value_of_mips_user_reg, &mips_register_aliases[i].regnum); | |
5955 | ||
4b9b3959 AC |
5956 | return gdbarch; |
5957 | } | |
5958 | ||
2e4ebe70 | 5959 | static void |
6d82d43b | 5960 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
5961 | { |
5962 | struct gdbarch_info info; | |
5963 | ||
5964 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
5965 | mips_gdbarch_init will take care of the rest. */ | |
5966 | gdbarch_info_init (&info); | |
5967 | gdbarch_update_p (info); | |
5968 | } | |
5969 | ||
ad188201 KB |
5970 | /* Print out which MIPS ABI is in use. */ |
5971 | ||
5972 | static void | |
1f8ca57c JB |
5973 | show_mips_abi (struct ui_file *file, |
5974 | int from_tty, | |
5975 | struct cmd_list_element *ignored_cmd, | |
5976 | const char *ignored_value) | |
ad188201 | 5977 | { |
1cf3db46 | 5978 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips) |
1f8ca57c JB |
5979 | fprintf_filtered |
5980 | (file, | |
5981 | "The MIPS ABI is unknown because the current architecture " | |
5982 | "is not MIPS.\n"); | |
ad188201 KB |
5983 | else |
5984 | { | |
5985 | enum mips_abi global_abi = global_mips_abi (); | |
1cf3db46 | 5986 | enum mips_abi actual_abi = mips_abi (target_gdbarch); |
ad188201 KB |
5987 | const char *actual_abi_str = mips_abi_strings[actual_abi]; |
5988 | ||
5989 | if (global_abi == MIPS_ABI_UNKNOWN) | |
1f8ca57c JB |
5990 | fprintf_filtered |
5991 | (file, | |
5992 | "The MIPS ABI is set automatically (currently \"%s\").\n", | |
6d82d43b | 5993 | actual_abi_str); |
ad188201 | 5994 | else if (global_abi == actual_abi) |
1f8ca57c JB |
5995 | fprintf_filtered |
5996 | (file, | |
5997 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6d82d43b | 5998 | actual_abi_str); |
ad188201 KB |
5999 | else |
6000 | { | |
6001 | /* Probably shouldn't happen... */ | |
1f8ca57c JB |
6002 | fprintf_filtered |
6003 | (file, | |
6004 | "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n", | |
6d82d43b | 6005 | actual_abi_str, mips_abi_strings[global_abi]); |
ad188201 KB |
6006 | } |
6007 | } | |
6008 | } | |
6009 | ||
4b9b3959 | 6010 | static void |
72a155b4 | 6011 | mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
4b9b3959 | 6012 | { |
72a155b4 | 6013 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4b9b3959 | 6014 | if (tdep != NULL) |
c2d11a7d | 6015 | { |
acdb74a0 AC |
6016 | int ef_mips_arch; |
6017 | int ef_mips_32bitmode; | |
f49e4e6d | 6018 | /* Determine the ISA. */ |
acdb74a0 AC |
6019 | switch (tdep->elf_flags & EF_MIPS_ARCH) |
6020 | { | |
6021 | case E_MIPS_ARCH_1: | |
6022 | ef_mips_arch = 1; | |
6023 | break; | |
6024 | case E_MIPS_ARCH_2: | |
6025 | ef_mips_arch = 2; | |
6026 | break; | |
6027 | case E_MIPS_ARCH_3: | |
6028 | ef_mips_arch = 3; | |
6029 | break; | |
6030 | case E_MIPS_ARCH_4: | |
93d56215 | 6031 | ef_mips_arch = 4; |
acdb74a0 AC |
6032 | break; |
6033 | default: | |
93d56215 | 6034 | ef_mips_arch = 0; |
acdb74a0 AC |
6035 | break; |
6036 | } | |
f49e4e6d | 6037 | /* Determine the size of a pointer. */ |
acdb74a0 | 6038 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); |
4b9b3959 AC |
6039 | fprintf_unfiltered (file, |
6040 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 6041 | tdep->elf_flags); |
4b9b3959 | 6042 | fprintf_unfiltered (file, |
acdb74a0 AC |
6043 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
6044 | ef_mips_32bitmode); | |
6045 | fprintf_unfiltered (file, | |
6046 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
6047 | ef_mips_arch); | |
6048 | fprintf_unfiltered (file, | |
6049 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 6050 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
6051 | fprintf_unfiltered (file, |
6052 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 6053 | mips_mask_address_p (tdep), |
4014092b | 6054 | tdep->default_mask_address_p); |
c2d11a7d | 6055 | } |
4b9b3959 AC |
6056 | fprintf_unfiltered (file, |
6057 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
6058 | MIPS_DEFAULT_FPU_TYPE, | |
6059 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6060 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6061 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6062 | : "???")); | |
74ed0bb4 MD |
6063 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", |
6064 | MIPS_EABI (gdbarch)); | |
4b9b3959 AC |
6065 | fprintf_unfiltered (file, |
6066 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
74ed0bb4 MD |
6067 | MIPS_FPU_TYPE (gdbarch), |
6068 | (MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_NONE ? "none" | |
6069 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_SINGLE ? "single" | |
6070 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_DOUBLE ? "double" | |
4b9b3959 | 6071 | : "???")); |
c2d11a7d JM |
6072 | } |
6073 | ||
6d82d43b | 6074 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 6075 | |
c906108c | 6076 | void |
acdb74a0 | 6077 | _initialize_mips_tdep (void) |
c906108c SS |
6078 | { |
6079 | static struct cmd_list_element *mipsfpulist = NULL; | |
6080 | struct cmd_list_element *c; | |
6081 | ||
6d82d43b | 6082 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
6083 | if (MIPS_ABI_LAST + 1 |
6084 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
e2e0b3e5 | 6085 | internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync")); |
2e4ebe70 | 6086 | |
4b9b3959 | 6087 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 6088 | |
8d5f9dcb DJ |
6089 | mips_pdr_data = register_objfile_data (); |
6090 | ||
4eb0ad19 DJ |
6091 | /* Create feature sets with the appropriate properties. The values |
6092 | are not important. */ | |
6093 | mips_tdesc_gp32 = allocate_target_description (); | |
6094 | set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, ""); | |
6095 | ||
6096 | mips_tdesc_gp64 = allocate_target_description (); | |
6097 | set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, ""); | |
6098 | ||
a5ea2558 AC |
6099 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
6100 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
1bedd215 | 6101 | _("Various MIPS specific commands."), |
a5ea2558 AC |
6102 | &setmipscmdlist, "set mips ", 0, &setlist); |
6103 | ||
6104 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
1bedd215 | 6105 | _("Various MIPS specific commands."), |
a5ea2558 AC |
6106 | &showmipscmdlist, "show mips ", 0, &showlist); |
6107 | ||
2e4ebe70 | 6108 | /* Allow the user to override the ABI. */ |
7ab04401 AC |
6109 | add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, |
6110 | &mips_abi_string, _("\ | |
6111 | Set the MIPS ABI used by this program."), _("\ | |
6112 | Show the MIPS ABI used by this program."), _("\ | |
6113 | This option can be set to one of:\n\ | |
6114 | auto - the default ABI associated with the current binary\n\ | |
6115 | o32\n\ | |
6116 | o64\n\ | |
6117 | n32\n\ | |
6118 | n64\n\ | |
6119 | eabi32\n\ | |
6120 | eabi64"), | |
6121 | mips_abi_update, | |
6122 | show_mips_abi, | |
6123 | &setmipscmdlist, &showmipscmdlist); | |
2e4ebe70 | 6124 | |
c906108c SS |
6125 | /* Let the user turn off floating point and set the fence post for |
6126 | heuristic_proc_start. */ | |
6127 | ||
6128 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
1bedd215 | 6129 | _("Set use of MIPS floating-point coprocessor."), |
c906108c SS |
6130 | &mipsfpulist, "set mipsfpu ", 0, &setlist); |
6131 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
1a966eab | 6132 | _("Select single-precision MIPS floating-point coprocessor."), |
c906108c SS |
6133 | &mipsfpulist); |
6134 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
1a966eab | 6135 | _("Select double-precision MIPS floating-point coprocessor."), |
c906108c SS |
6136 | &mipsfpulist); |
6137 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
6138 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
6139 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
6140 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
1a966eab | 6141 | _("Select no MIPS floating-point coprocessor."), &mipsfpulist); |
c906108c SS |
6142 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
6143 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
6144 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
6145 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
1a966eab | 6146 | _("Select MIPS floating-point coprocessor automatically."), |
c906108c SS |
6147 | &mipsfpulist); |
6148 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
1a966eab | 6149 | _("Show current use of MIPS floating-point coprocessor target."), |
c906108c SS |
6150 | &showlist); |
6151 | ||
c906108c SS |
6152 | /* We really would like to have both "0" and "unlimited" work, but |
6153 | command.c doesn't deal with that. So make it a var_zinteger | |
6154 | because the user can always use "999999" or some such for unlimited. */ | |
6bcadd06 | 6155 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
7915a72c AC |
6156 | &heuristic_fence_post, _("\ |
6157 | Set the distance searched for the start of a function."), _("\ | |
6158 | Show the distance searched for the start of a function."), _("\ | |
c906108c SS |
6159 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
6160 | program for the start of a function. This command sets the distance of the\n\ | |
7915a72c | 6161 | search. The only need to set it is when debugging a stripped executable."), |
2c5b56ce | 6162 | reinit_frame_cache_sfunc, |
7915a72c | 6163 | NULL, /* FIXME: i18n: The distance searched for the start of a function is %s. */ |
6bcadd06 | 6164 | &setlist, &showlist); |
c906108c SS |
6165 | |
6166 | /* Allow the user to control whether the upper bits of 64-bit | |
6167 | addresses should be zeroed. */ | |
7915a72c AC |
6168 | add_setshow_auto_boolean_cmd ("mask-address", no_class, |
6169 | &mask_address_var, _("\ | |
6170 | Set zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
6171 | Show zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
e9e68a56 | 6172 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ |
7915a72c | 6173 | allow GDB to determine the correct value."), |
08546159 AC |
6174 | NULL, show_mask_address, |
6175 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
6176 | |
6177 | /* Allow the user to control the size of 32 bit registers within the | |
6178 | raw remote packet. */ | |
b3f42336 | 6179 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
7915a72c AC |
6180 | &mips64_transfers_32bit_regs_p, _("\ |
6181 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
6182 | _("\ | |
6183 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
6184 | _("\ | |
719ec221 AC |
6185 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
6186 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
7915a72c | 6187 | 64 bits for others. Use \"off\" to disable compatibility mode"), |
2c5b56ce | 6188 | set_mips64_transfers_32bit_regs, |
7915a72c | 6189 | NULL, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */ |
7915a72c | 6190 | &setlist, &showlist); |
9ace0497 AC |
6191 | |
6192 | /* Debug this files internals. */ | |
6bcadd06 | 6193 | add_setshow_zinteger_cmd ("mips", class_maintenance, |
7915a72c AC |
6194 | &mips_debug, _("\ |
6195 | Set mips debugging."), _("\ | |
6196 | Show mips debugging."), _("\ | |
6197 | When non-zero, mips specific debugging is enabled."), | |
2c5b56ce | 6198 | NULL, |
7915a72c | 6199 | NULL, /* FIXME: i18n: Mips debugging is currently %s. */ |
6bcadd06 | 6200 | &setdebuglist, &showdebuglist); |
c906108c | 6201 | } |