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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
0b302171 | 3 | Copyright (C) 1988-2012 Free Software Foundation, Inc. |
bf64bfd6 | 4 | |
c906108c SS |
5 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
6 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
7 | ||
c5aa993b | 8 | This file is part of GDB. |
c906108c | 9 | |
c5aa993b JM |
10 | This program is free software; you can redistribute it and/or modify |
11 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 12 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 13 | (at your option) any later version. |
c906108c | 14 | |
c5aa993b JM |
15 | This program is distributed in the hope that it will be useful, |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
c906108c | 19 | |
c5aa993b | 20 | You should have received a copy of the GNU General Public License |
a9762ec7 | 21 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
22 | |
23 | #include "defs.h" | |
24 | #include "gdb_string.h" | |
5e2e9765 | 25 | #include "gdb_assert.h" |
c906108c SS |
26 | #include "frame.h" |
27 | #include "inferior.h" | |
28 | #include "symtab.h" | |
29 | #include "value.h" | |
30 | #include "gdbcmd.h" | |
31 | #include "language.h" | |
32 | #include "gdbcore.h" | |
33 | #include "symfile.h" | |
34 | #include "objfiles.h" | |
35 | #include "gdbtypes.h" | |
36 | #include "target.h" | |
28d069e6 | 37 | #include "arch-utils.h" |
4e052eda | 38 | #include "regcache.h" |
70f80edf | 39 | #include "osabi.h" |
d1973055 | 40 | #include "mips-tdep.h" |
fe898f56 | 41 | #include "block.h" |
a4b8ebc8 | 42 | #include "reggroups.h" |
c906108c | 43 | #include "opcode/mips.h" |
c2d11a7d JM |
44 | #include "elf/mips.h" |
45 | #include "elf-bfd.h" | |
2475bac3 | 46 | #include "symcat.h" |
a4b8ebc8 | 47 | #include "sim-regno.h" |
a89aa300 | 48 | #include "dis-asm.h" |
edfae063 AC |
49 | #include "frame-unwind.h" |
50 | #include "frame-base.h" | |
51 | #include "trad-frame.h" | |
7d9b040b | 52 | #include "infcall.h" |
fed7ba43 | 53 | #include "floatformat.h" |
29709017 DJ |
54 | #include "remote.h" |
55 | #include "target-descriptions.h" | |
2bd0c3d7 | 56 | #include "dwarf2-frame.h" |
f8b73d13 | 57 | #include "user-regs.h" |
79a45b7d | 58 | #include "valprint.h" |
175ff332 | 59 | #include "ax.h" |
c906108c | 60 | |
8d5f9dcb DJ |
61 | static const struct objfile_data *mips_pdr_data; |
62 | ||
5bbcb741 | 63 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 64 | |
24e05951 | 65 | /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ |
dd824b04 DJ |
66 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ |
67 | #define ST0_FR (1 << 26) | |
68 | ||
b0069a17 AC |
69 | /* The sizes of floating point registers. */ |
70 | ||
71 | enum | |
72 | { | |
73 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
74 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
75 | }; | |
76 | ||
1a69e1e4 DJ |
77 | enum |
78 | { | |
79 | MIPS32_REGSIZE = 4, | |
80 | MIPS64_REGSIZE = 8 | |
81 | }; | |
0dadbba0 | 82 | |
2e4ebe70 DJ |
83 | static const char *mips_abi_string; |
84 | ||
40478521 | 85 | static const char *const mips_abi_strings[] = { |
2e4ebe70 DJ |
86 | "auto", |
87 | "n32", | |
88 | "o32", | |
28d169de | 89 | "n64", |
2e4ebe70 DJ |
90 | "o64", |
91 | "eabi32", | |
92 | "eabi64", | |
93 | NULL | |
94 | }; | |
95 | ||
f8b73d13 DJ |
96 | /* The standard register names, and all the valid aliases for them. */ |
97 | struct register_alias | |
98 | { | |
99 | const char *name; | |
100 | int regnum; | |
101 | }; | |
102 | ||
103 | /* Aliases for o32 and most other ABIs. */ | |
104 | const struct register_alias mips_o32_aliases[] = { | |
105 | { "ta0", 12 }, | |
106 | { "ta1", 13 }, | |
107 | { "ta2", 14 }, | |
108 | { "ta3", 15 } | |
109 | }; | |
110 | ||
111 | /* Aliases for n32 and n64. */ | |
112 | const struct register_alias mips_n32_n64_aliases[] = { | |
113 | { "ta0", 8 }, | |
114 | { "ta1", 9 }, | |
115 | { "ta2", 10 }, | |
116 | { "ta3", 11 } | |
117 | }; | |
118 | ||
119 | /* Aliases for ABI-independent registers. */ | |
120 | const struct register_alias mips_register_aliases[] = { | |
121 | /* The architecture manuals specify these ABI-independent names for | |
122 | the GPRs. */ | |
123 | #define R(n) { "r" #n, n } | |
124 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
125 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
126 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
127 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
128 | #undef R | |
129 | ||
130 | /* k0 and k1 are sometimes called these instead (for "kernel | |
131 | temp"). */ | |
132 | { "kt0", 26 }, | |
133 | { "kt1", 27 }, | |
134 | ||
135 | /* This is the traditional GDB name for the CP0 status register. */ | |
136 | { "sr", MIPS_PS_REGNUM }, | |
137 | ||
138 | /* This is the traditional GDB name for the CP0 BadVAddr register. */ | |
139 | { "bad", MIPS_EMBED_BADVADDR_REGNUM }, | |
140 | ||
141 | /* This is the traditional GDB name for the FCSR. */ | |
142 | { "fsr", MIPS_EMBED_FP0_REGNUM + 32 } | |
143 | }; | |
144 | ||
865093a3 AR |
145 | const struct register_alias mips_numeric_register_aliases[] = { |
146 | #define R(n) { #n, n } | |
147 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
148 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
149 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
150 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
151 | #undef R | |
152 | }; | |
153 | ||
c906108c SS |
154 | #ifndef MIPS_DEFAULT_FPU_TYPE |
155 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
156 | #endif | |
157 | static int mips_fpu_type_auto = 1; | |
158 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 159 | |
9ace0497 | 160 | static int mips_debug = 0; |
7a292a7a | 161 | |
29709017 DJ |
162 | /* Properties (for struct target_desc) describing the g/G packet |
163 | layout. */ | |
164 | #define PROPERTY_GP32 "internal: transfers-32bit-registers" | |
165 | #define PROPERTY_GP64 "internal: transfers-64bit-registers" | |
166 | ||
4eb0ad19 DJ |
167 | struct target_desc *mips_tdesc_gp32; |
168 | struct target_desc *mips_tdesc_gp64; | |
169 | ||
56cea623 AC |
170 | const struct mips_regnum * |
171 | mips_regnum (struct gdbarch *gdbarch) | |
172 | { | |
173 | return gdbarch_tdep (gdbarch)->regnum; | |
174 | } | |
175 | ||
176 | static int | |
177 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
178 | { | |
179 | return mips_regnum (gdbarch)->fp0 + 12; | |
180 | } | |
181 | ||
004159a2 MR |
182 | /* Return 1 if REGNUM refers to a floating-point general register, raw |
183 | or cooked. Otherwise return 0. */ | |
184 | ||
185 | static int | |
186 | mips_float_register_p (struct gdbarch *gdbarch, int regnum) | |
187 | { | |
188 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
189 | ||
190 | return (rawnum >= mips_regnum (gdbarch)->fp0 | |
191 | && rawnum < mips_regnum (gdbarch)->fp0 + 32); | |
192 | } | |
193 | ||
74ed0bb4 MD |
194 | #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \ |
195 | == MIPS_ABI_EABI32 \ | |
196 | || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64) | |
c2d11a7d | 197 | |
025bb325 MS |
198 | #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \ |
199 | (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum) | |
c2d11a7d | 200 | |
025bb325 MS |
201 | #define MIPS_LAST_ARG_REGNUM(gdbarch) \ |
202 | (gdbarch_tdep (gdbarch)->mips_last_arg_regnum) | |
c2d11a7d | 203 | |
74ed0bb4 | 204 | #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type) |
c2d11a7d | 205 | |
d1973055 KB |
206 | /* Return the MIPS ABI associated with GDBARCH. */ |
207 | enum mips_abi | |
208 | mips_abi (struct gdbarch *gdbarch) | |
209 | { | |
210 | return gdbarch_tdep (gdbarch)->mips_abi; | |
211 | } | |
212 | ||
4246e332 | 213 | int |
1b13c4f6 | 214 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 | 215 | { |
29709017 DJ |
216 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
217 | ||
218 | /* If we know how big the registers are, use that size. */ | |
219 | if (tdep->register_size_valid_p) | |
220 | return tdep->register_size; | |
221 | ||
222 | /* Fall back to the previous behavior. */ | |
4246e332 AC |
223 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word |
224 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
225 | } | |
226 | ||
025bb325 | 227 | /* Return the currently configured (or set) saved register size. */ |
480d3dd2 | 228 | |
e6bc2e8a | 229 | unsigned int |
13326b4e | 230 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 231 | { |
1a69e1e4 DJ |
232 | switch (mips_abi (gdbarch)) |
233 | { | |
234 | case MIPS_ABI_EABI32: | |
235 | case MIPS_ABI_O32: | |
236 | return 4; | |
237 | case MIPS_ABI_N32: | |
238 | case MIPS_ABI_N64: | |
239 | case MIPS_ABI_O64: | |
240 | case MIPS_ABI_EABI64: | |
241 | return 8; | |
242 | case MIPS_ABI_UNKNOWN: | |
243 | case MIPS_ABI_LAST: | |
244 | default: | |
245 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
246 | } | |
d929b26f AC |
247 | } |
248 | ||
742c84f6 MR |
249 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
250 | functions to test, set, or clear bit 0 of addresses. */ | |
251 | ||
252 | static CORE_ADDR | |
253 | is_mips16_addr (CORE_ADDR addr) | |
254 | { | |
255 | return ((addr) & 1); | |
256 | } | |
257 | ||
258 | static CORE_ADDR | |
259 | unmake_mips16_addr (CORE_ADDR addr) | |
260 | { | |
261 | return ((addr) & ~(CORE_ADDR) 1); | |
262 | } | |
263 | ||
264 | static CORE_ADDR | |
265 | make_mips16_addr (CORE_ADDR addr) | |
266 | { | |
267 | return ((addr) | (CORE_ADDR) 1); | |
268 | } | |
269 | ||
71b8ef93 | 270 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 271 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 272 | "info" field is used for this purpose. |
5a89d8aa | 273 | |
95f1da47 | 274 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special", |
5a89d8aa MS |
275 | i.e. refers to a 16-bit function, and sets a "special" bit in a |
276 | minimal symbol to mark it as a 16-bit function | |
277 | ||
f594e5e9 | 278 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 279 | |
5a89d8aa | 280 | static void |
6d82d43b AC |
281 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
282 | { | |
7f0e6aae MR |
283 | if (ELF_ST_IS_MIPS16 (((elf_symbol_type *) |
284 | (sym))->internal_elf_sym.st_other)) | |
6d82d43b | 285 | { |
b887350f | 286 | MSYMBOL_TARGET_FLAG_1 (msym) = 1; |
6d82d43b | 287 | } |
5a89d8aa MS |
288 | } |
289 | ||
71b8ef93 MS |
290 | static int |
291 | msymbol_is_special (struct minimal_symbol *msym) | |
292 | { | |
b887350f | 293 | return MSYMBOL_TARGET_FLAG_1 (msym); |
71b8ef93 MS |
294 | } |
295 | ||
88658117 AC |
296 | /* XFER a value from the big/little/left end of the register. |
297 | Depending on the size of the value it might occupy the entire | |
298 | register or just part of it. Make an allowance for this, aligning | |
299 | things accordingly. */ | |
300 | ||
301 | static void | |
ba32f989 DJ |
302 | mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache, |
303 | int reg_num, int length, | |
870cd05e MK |
304 | enum bfd_endian endian, gdb_byte *in, |
305 | const gdb_byte *out, int buf_offset) | |
88658117 | 306 | { |
88658117 | 307 | int reg_offset = 0; |
72a155b4 UW |
308 | |
309 | gdb_assert (reg_num >= gdbarch_num_regs (gdbarch)); | |
cb1d2653 AC |
310 | /* Need to transfer the left or right part of the register, based on |
311 | the targets byte order. */ | |
88658117 AC |
312 | switch (endian) |
313 | { | |
314 | case BFD_ENDIAN_BIG: | |
72a155b4 | 315 | reg_offset = register_size (gdbarch, reg_num) - length; |
88658117 AC |
316 | break; |
317 | case BFD_ENDIAN_LITTLE: | |
318 | reg_offset = 0; | |
319 | break; | |
6d82d43b | 320 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
321 | reg_offset = 0; |
322 | break; | |
323 | default: | |
e2e0b3e5 | 324 | internal_error (__FILE__, __LINE__, _("bad switch")); |
88658117 AC |
325 | } |
326 | if (mips_debug) | |
cb1d2653 AC |
327 | fprintf_unfiltered (gdb_stderr, |
328 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
329 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
330 | if (mips_debug && out != NULL) |
331 | { | |
332 | int i; | |
cb1d2653 | 333 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 334 | for (i = 0; i < length; i++) |
cb1d2653 | 335 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
336 | } |
337 | if (in != NULL) | |
6d82d43b AC |
338 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
339 | in + buf_offset); | |
88658117 | 340 | if (out != NULL) |
6d82d43b AC |
341 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
342 | out + buf_offset); | |
88658117 AC |
343 | if (mips_debug && in != NULL) |
344 | { | |
345 | int i; | |
cb1d2653 | 346 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 347 | for (i = 0; i < length; i++) |
cb1d2653 | 348 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
349 | } |
350 | if (mips_debug) | |
351 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
352 | } | |
353 | ||
dd824b04 DJ |
354 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
355 | compatiblity mode. A return value of 1 means that we have | |
356 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
357 | ||
358 | static int | |
9c9acae0 | 359 | mips2_fp_compat (struct frame_info *frame) |
dd824b04 | 360 | { |
72a155b4 | 361 | struct gdbarch *gdbarch = get_frame_arch (frame); |
dd824b04 DJ |
362 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not |
363 | meaningful. */ | |
72a155b4 | 364 | if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4) |
dd824b04 DJ |
365 | return 0; |
366 | ||
367 | #if 0 | |
368 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
369 | in all the places we deal with FP registers. PR gdb/413. */ | |
370 | /* Otherwise check the FR bit in the status register - it controls | |
371 | the FP compatiblity mode. If it is clear we are in compatibility | |
372 | mode. */ | |
9c9acae0 | 373 | if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0) |
dd824b04 DJ |
374 | return 1; |
375 | #endif | |
361d1df0 | 376 | |
dd824b04 DJ |
377 | return 0; |
378 | } | |
379 | ||
7a292a7a | 380 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 381 | |
74ed0bb4 | 382 | static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR); |
c906108c | 383 | |
a14ed312 | 384 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 385 | |
025bb325 | 386 | /* The list of available "set mips " and "show mips " commands. */ |
acdb74a0 AC |
387 | |
388 | static struct cmd_list_element *setmipscmdlist = NULL; | |
389 | static struct cmd_list_element *showmipscmdlist = NULL; | |
390 | ||
5e2e9765 KB |
391 | /* Integer registers 0 thru 31 are handled explicitly by |
392 | mips_register_name(). Processor specific registers 32 and above | |
8a9fc081 | 393 | are listed in the following tables. */ |
691c0433 | 394 | |
6d82d43b AC |
395 | enum |
396 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
397 | |
398 | /* Generic MIPS. */ | |
399 | ||
400 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
401 | "sr", "lo", "hi", "bad", "cause", "pc", |
402 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
403 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
404 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
405 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
1faeff08 | 406 | "fsr", "fir", |
691c0433 AC |
407 | }; |
408 | ||
409 | /* Names of IDT R3041 registers. */ | |
410 | ||
411 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
412 | "sr", "lo", "hi", "bad", "cause", "pc", |
413 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
414 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
415 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
416 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
417 | "fsr", "fir", "", /*"fp" */ "", | |
418 | "", "", "bus", "ccfg", "", "", "", "", | |
419 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
420 | }; |
421 | ||
422 | /* Names of tx39 registers. */ | |
423 | ||
424 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
425 | "sr", "lo", "hi", "bad", "cause", "pc", |
426 | "", "", "", "", "", "", "", "", | |
427 | "", "", "", "", "", "", "", "", | |
428 | "", "", "", "", "", "", "", "", | |
429 | "", "", "", "", "", "", "", "", | |
430 | "", "", "", "", | |
431 | "", "", "", "", "", "", "", "", | |
1faeff08 | 432 | "", "", "config", "cache", "debug", "depc", "epc", |
691c0433 AC |
433 | }; |
434 | ||
435 | /* Names of IRIX registers. */ | |
436 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
437 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
438 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
439 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
440 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
441 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
442 | }; |
443 | ||
44099a67 | 444 | /* Names of registers with Linux kernels. */ |
1faeff08 MR |
445 | static const char *mips_linux_reg_names[NUM_MIPS_PROCESSOR_REGS] = { |
446 | "sr", "lo", "hi", "bad", "cause", "pc", | |
447 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
448 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
449 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
450 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
451 | "fsr", "fir" | |
452 | }; | |
453 | ||
cce74817 | 454 | |
5e2e9765 | 455 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 456 | static const char * |
d93859e2 | 457 | mips_register_name (struct gdbarch *gdbarch, int regno) |
cce74817 | 458 | { |
d93859e2 | 459 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
5e2e9765 KB |
460 | /* GPR names for all ABIs other than n32/n64. */ |
461 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
462 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
463 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
464 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
465 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
466 | }; |
467 | ||
468 | /* GPR names for n32 and n64 ABIs. */ | |
469 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
470 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
471 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
472 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
473 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
474 | }; |
475 | ||
d93859e2 | 476 | enum mips_abi abi = mips_abi (gdbarch); |
5e2e9765 | 477 | |
f57d151a | 478 | /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, |
6229fbea HZ |
479 | but then don't make the raw register names visible. This (upper) |
480 | range of user visible register numbers are the pseudo-registers. | |
481 | ||
482 | This approach was adopted accommodate the following scenario: | |
483 | It is possible to debug a 64-bit device using a 32-bit | |
484 | programming model. In such instances, the raw registers are | |
485 | configured to be 64-bits wide, while the pseudo registers are | |
486 | configured to be 32-bits wide. The registers that the user | |
487 | sees - the pseudo registers - match the users expectations | |
488 | given the programming model being used. */ | |
d93859e2 UW |
489 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
490 | if (regno < gdbarch_num_regs (gdbarch)) | |
a4b8ebc8 AC |
491 | return ""; |
492 | ||
5e2e9765 KB |
493 | /* The MIPS integer registers are always mapped from 0 to 31. The |
494 | names of the registers (which reflects the conventions regarding | |
495 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 496 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
497 | { |
498 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 499 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 500 | else |
a4b8ebc8 | 501 | return mips_gpr_names[rawnum]; |
5e2e9765 | 502 | } |
d93859e2 UW |
503 | else if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
504 | return tdesc_register_name (gdbarch, rawnum); | |
505 | else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch)) | |
691c0433 AC |
506 | { |
507 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
1faeff08 MR |
508 | if (tdep->mips_processor_reg_names[rawnum - 32]) |
509 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
510 | return ""; | |
691c0433 | 511 | } |
5e2e9765 KB |
512 | else |
513 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 514 | _("mips_register_name: bad register number %d"), rawnum); |
cce74817 | 515 | } |
5e2e9765 | 516 | |
a4b8ebc8 | 517 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 518 | |
a4b8ebc8 AC |
519 | static int |
520 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
521 | struct reggroup *reggroup) | |
522 | { | |
523 | int vector_p; | |
524 | int float_p; | |
525 | int raw_p; | |
72a155b4 UW |
526 | int rawnum = regnum % gdbarch_num_regs (gdbarch); |
527 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
a4b8ebc8 AC |
528 | if (reggroup == all_reggroup) |
529 | return pseudo; | |
530 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
531 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
532 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
533 | (gdbarch), as not all architectures are multi-arch. */ | |
72a155b4 UW |
534 | raw_p = rawnum < gdbarch_num_regs (gdbarch); |
535 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
536 | || gdbarch_register_name (gdbarch, regnum)[0] == '\0') | |
a4b8ebc8 AC |
537 | return 0; |
538 | if (reggroup == float_reggroup) | |
539 | return float_p && pseudo; | |
540 | if (reggroup == vector_reggroup) | |
541 | return vector_p && pseudo; | |
542 | if (reggroup == general_reggroup) | |
543 | return (!vector_p && !float_p) && pseudo; | |
544 | /* Save the pseudo registers. Need to make certain that any code | |
545 | extracting register values from a saved register cache also uses | |
546 | pseudo registers. */ | |
547 | if (reggroup == save_reggroup) | |
548 | return raw_p && pseudo; | |
549 | /* Restore the same pseudo register. */ | |
550 | if (reggroup == restore_reggroup) | |
551 | return raw_p && pseudo; | |
6d82d43b | 552 | return 0; |
a4b8ebc8 AC |
553 | } |
554 | ||
f8b73d13 DJ |
555 | /* Return the groups that a MIPS register can be categorised into. |
556 | This version is only used if we have a target description which | |
557 | describes real registers (and their groups). */ | |
558 | ||
559 | static int | |
560 | mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
561 | struct reggroup *reggroup) | |
562 | { | |
563 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
564 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
565 | int ret; | |
566 | ||
567 | /* Only save, restore, and display the pseudo registers. Need to | |
568 | make certain that any code extracting register values from a | |
569 | saved register cache also uses pseudo registers. | |
570 | ||
571 | Note: saving and restoring the pseudo registers is slightly | |
572 | strange; if we have 64 bits, we should save and restore all | |
573 | 64 bits. But this is hard and has little benefit. */ | |
574 | if (!pseudo) | |
575 | return 0; | |
576 | ||
577 | ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup); | |
578 | if (ret != -1) | |
579 | return ret; | |
580 | ||
581 | return mips_register_reggroup_p (gdbarch, regnum, reggroup); | |
582 | } | |
583 | ||
a4b8ebc8 | 584 | /* Map the symbol table registers which live in the range [1 * |
f57d151a | 585 | gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw |
47ebcfbe | 586 | registers. Take care of alignment and size problems. */ |
c5aa993b | 587 | |
05d1431c | 588 | static enum register_status |
a4b8ebc8 | 589 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
47a35522 | 590 | int cookednum, gdb_byte *buf) |
a4b8ebc8 | 591 | { |
72a155b4 UW |
592 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
593 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
594 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 595 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
05d1431c | 596 | return regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
597 | else if (register_size (gdbarch, rawnum) > |
598 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 599 | { |
8bdf35dc | 600 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
05d1431c | 601 | return regcache_raw_read_part (regcache, rawnum, 0, 4, buf); |
47ebcfbe | 602 | else |
8bdf35dc KB |
603 | { |
604 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
605 | LONGEST regval; | |
05d1431c PA |
606 | enum register_status status; |
607 | ||
608 | status = regcache_raw_read_signed (regcache, rawnum, ®val); | |
609 | if (status == REG_VALID) | |
610 | store_signed_integer (buf, 4, byte_order, regval); | |
611 | return status; | |
8bdf35dc | 612 | } |
47ebcfbe AC |
613 | } |
614 | else | |
e2e0b3e5 | 615 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 AC |
616 | } |
617 | ||
618 | static void | |
6d82d43b AC |
619 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
620 | struct regcache *regcache, int cookednum, | |
47a35522 | 621 | const gdb_byte *buf) |
a4b8ebc8 | 622 | { |
72a155b4 UW |
623 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
624 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
625 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 626 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 627 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
628 | else if (register_size (gdbarch, rawnum) > |
629 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 630 | { |
8bdf35dc | 631 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
47ebcfbe AC |
632 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); |
633 | else | |
8bdf35dc KB |
634 | { |
635 | /* Sign extend the shortened version of the register prior | |
636 | to placing it in the raw register. This is required for | |
637 | some mips64 parts in order to avoid unpredictable behavior. */ | |
638 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
639 | LONGEST regval = extract_signed_integer (buf, 4, byte_order); | |
640 | regcache_raw_write_signed (regcache, rawnum, regval); | |
641 | } | |
47ebcfbe AC |
642 | } |
643 | else | |
e2e0b3e5 | 644 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 | 645 | } |
c5aa993b | 646 | |
175ff332 HZ |
647 | static int |
648 | mips_ax_pseudo_register_collect (struct gdbarch *gdbarch, | |
649 | struct agent_expr *ax, int reg) | |
650 | { | |
651 | int rawnum = reg % gdbarch_num_regs (gdbarch); | |
652 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) | |
653 | && reg < 2 * gdbarch_num_regs (gdbarch)); | |
654 | ||
655 | ax_reg_mask (ax, rawnum); | |
656 | ||
657 | return 0; | |
658 | } | |
659 | ||
660 | static int | |
661 | mips_ax_pseudo_register_push_stack (struct gdbarch *gdbarch, | |
662 | struct agent_expr *ax, int reg) | |
663 | { | |
664 | int rawnum = reg % gdbarch_num_regs (gdbarch); | |
665 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) | |
666 | && reg < 2 * gdbarch_num_regs (gdbarch)); | |
667 | if (register_size (gdbarch, rawnum) >= register_size (gdbarch, reg)) | |
668 | { | |
669 | ax_reg (ax, rawnum); | |
670 | ||
671 | if (register_size (gdbarch, rawnum) > register_size (gdbarch, reg)) | |
672 | { | |
673 | if (!gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
674 | || gdbarch_byte_order (gdbarch) != BFD_ENDIAN_BIG) | |
675 | { | |
676 | ax_const_l (ax, 32); | |
677 | ax_simple (ax, aop_lsh); | |
678 | } | |
679 | ax_const_l (ax, 32); | |
680 | ax_simple (ax, aop_rsh_signed); | |
681 | } | |
682 | } | |
683 | else | |
684 | internal_error (__FILE__, __LINE__, _("bad register size")); | |
685 | ||
686 | return 0; | |
687 | } | |
688 | ||
c906108c | 689 | /* Table to translate MIPS16 register field to actual register number. */ |
6d82d43b | 690 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
691 | |
692 | /* Heuristic_proc_start may hunt through the text section for a long | |
693 | time across a 2400 baud serial line. Allows the user to limit this | |
694 | search. */ | |
695 | ||
696 | static unsigned int heuristic_fence_post = 0; | |
697 | ||
46cd78fb | 698 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
699 | register N. NOTE: This defines the pseudo register type so need to |
700 | rebuild the architecture vector. */ | |
43e526b9 JM |
701 | |
702 | static int mips64_transfers_32bit_regs_p = 0; | |
703 | ||
719ec221 AC |
704 | static void |
705 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
706 | struct cmd_list_element *c) | |
43e526b9 | 707 | { |
719ec221 AC |
708 | struct gdbarch_info info; |
709 | gdbarch_info_init (&info); | |
710 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
711 | instead of relying on globals. Doing that would let generic code | |
712 | handle the search for this specific architecture. */ | |
713 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 714 | { |
719ec221 | 715 | mips64_transfers_32bit_regs_p = 0; |
8a3fe4f8 | 716 | error (_("32-bit compatibility mode not supported")); |
a4b8ebc8 | 717 | } |
a4b8ebc8 AC |
718 | } |
719 | ||
47ebcfbe | 720 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 721 | |
ee51a8c7 KB |
722 | /* This predicate tests for the case of an 8 byte floating point |
723 | value that is being transferred to or from a pair of floating point | |
724 | registers each of which are (or are considered to be) only 4 bytes | |
725 | wide. */ | |
ff2e87ac | 726 | static int |
ee51a8c7 KB |
727 | mips_convert_register_float_case_p (struct gdbarch *gdbarch, int regnum, |
728 | struct type *type) | |
ff2e87ac | 729 | { |
0abe36f5 MD |
730 | return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
731 | && register_size (gdbarch, regnum) == 4 | |
004159a2 | 732 | && mips_float_register_p (gdbarch, regnum) |
6d82d43b | 733 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
734 | } |
735 | ||
ee51a8c7 KB |
736 | /* This predicate tests for the case of a value of less than 8 |
737 | bytes in width that is being transfered to or from an 8 byte | |
738 | general purpose register. */ | |
739 | static int | |
740 | mips_convert_register_gpreg_case_p (struct gdbarch *gdbarch, int regnum, | |
741 | struct type *type) | |
742 | { | |
743 | int num_regs = gdbarch_num_regs (gdbarch); | |
744 | ||
745 | return (register_size (gdbarch, regnum) == 8 | |
746 | && regnum % num_regs > 0 && regnum % num_regs < 32 | |
747 | && TYPE_LENGTH (type) < 8); | |
748 | } | |
749 | ||
750 | static int | |
025bb325 MS |
751 | mips_convert_register_p (struct gdbarch *gdbarch, |
752 | int regnum, struct type *type) | |
ee51a8c7 KB |
753 | { |
754 | return mips_convert_register_float_case_p (gdbarch, regnum, type) | |
755 | || mips_convert_register_gpreg_case_p (gdbarch, regnum, type); | |
756 | } | |
757 | ||
8dccd430 | 758 | static int |
ff2e87ac | 759 | mips_register_to_value (struct frame_info *frame, int regnum, |
8dccd430 PA |
760 | struct type *type, gdb_byte *to, |
761 | int *optimizedp, int *unavailablep) | |
102182a9 | 762 | { |
ee51a8c7 KB |
763 | struct gdbarch *gdbarch = get_frame_arch (frame); |
764 | ||
765 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
766 | { | |
767 | get_frame_register (frame, regnum + 0, to + 4); | |
768 | get_frame_register (frame, regnum + 1, to + 0); | |
8dccd430 PA |
769 | |
770 | if (!get_frame_register_bytes (frame, regnum + 0, 0, 4, to + 4, | |
771 | optimizedp, unavailablep)) | |
772 | return 0; | |
773 | ||
774 | if (!get_frame_register_bytes (frame, regnum + 1, 0, 4, to + 0, | |
775 | optimizedp, unavailablep)) | |
776 | return 0; | |
777 | *optimizedp = *unavailablep = 0; | |
778 | return 1; | |
ee51a8c7 KB |
779 | } |
780 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
781 | { | |
782 | int len = TYPE_LENGTH (type); | |
8dccd430 PA |
783 | CORE_ADDR offset; |
784 | ||
785 | offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 8 - len : 0; | |
786 | if (!get_frame_register_bytes (frame, regnum, offset, len, to, | |
787 | optimizedp, unavailablep)) | |
788 | return 0; | |
789 | ||
790 | *optimizedp = *unavailablep = 0; | |
791 | return 1; | |
ee51a8c7 KB |
792 | } |
793 | else | |
794 | { | |
795 | internal_error (__FILE__, __LINE__, | |
796 | _("mips_register_to_value: unrecognized case")); | |
797 | } | |
102182a9 MS |
798 | } |
799 | ||
42c466d7 | 800 | static void |
ff2e87ac | 801 | mips_value_to_register (struct frame_info *frame, int regnum, |
47a35522 | 802 | struct type *type, const gdb_byte *from) |
102182a9 | 803 | { |
ee51a8c7 KB |
804 | struct gdbarch *gdbarch = get_frame_arch (frame); |
805 | ||
806 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
807 | { | |
808 | put_frame_register (frame, regnum + 0, from + 4); | |
809 | put_frame_register (frame, regnum + 1, from + 0); | |
810 | } | |
811 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
812 | { | |
813 | gdb_byte fill[8]; | |
814 | int len = TYPE_LENGTH (type); | |
815 | ||
816 | /* Sign extend values, irrespective of type, that are stored to | |
817 | a 64-bit general purpose register. (32-bit unsigned values | |
818 | are stored as signed quantities within a 64-bit register. | |
819 | When performing an operation, in compiled code, that combines | |
820 | a 32-bit unsigned value with a signed 64-bit value, a type | |
821 | conversion is first performed that zeroes out the high 32 bits.) */ | |
822 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
823 | { | |
824 | if (from[0] & 0x80) | |
825 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, -1); | |
826 | else | |
827 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, 0); | |
828 | put_frame_register_bytes (frame, regnum, 0, 8 - len, fill); | |
829 | put_frame_register_bytes (frame, regnum, 8 - len, len, from); | |
830 | } | |
831 | else | |
832 | { | |
833 | if (from[len-1] & 0x80) | |
834 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, -1); | |
835 | else | |
836 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, 0); | |
837 | put_frame_register_bytes (frame, regnum, 0, len, from); | |
838 | put_frame_register_bytes (frame, regnum, len, 8 - len, fill); | |
839 | } | |
840 | } | |
841 | else | |
842 | { | |
843 | internal_error (__FILE__, __LINE__, | |
844 | _("mips_value_to_register: unrecognized case")); | |
845 | } | |
102182a9 MS |
846 | } |
847 | ||
a4b8ebc8 AC |
848 | /* Return the GDB type object for the "standard" data type of data in |
849 | register REG. */ | |
78fde5f8 KB |
850 | |
851 | static struct type * | |
a4b8ebc8 AC |
852 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
853 | { | |
72a155b4 | 854 | gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch)); |
004159a2 | 855 | if (mips_float_register_p (gdbarch, regnum)) |
a6425924 | 856 | { |
5ef80fb0 | 857 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 858 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
8da61cc4 | 859 | if (mips_isa_regsize (gdbarch) == 4) |
27067745 | 860 | return builtin_type (gdbarch)->builtin_float; |
8da61cc4 | 861 | else |
27067745 | 862 | return builtin_type (gdbarch)->builtin_double; |
a6425924 | 863 | } |
72a155b4 | 864 | else if (regnum < gdbarch_num_regs (gdbarch)) |
d5ac5a39 AC |
865 | { |
866 | /* The raw or ISA registers. These are all sized according to | |
867 | the ISA regsize. */ | |
868 | if (mips_isa_regsize (gdbarch) == 4) | |
df4df182 | 869 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 | 870 | else |
df4df182 | 871 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 872 | } |
78fde5f8 | 873 | else |
d5ac5a39 | 874 | { |
1faeff08 MR |
875 | int rawnum = regnum - gdbarch_num_regs (gdbarch); |
876 | ||
d5ac5a39 AC |
877 | /* The cooked or ABI registers. These are sized according to |
878 | the ABI (with a few complications). */ | |
1faeff08 MR |
879 | if (rawnum == mips_regnum (gdbarch)->fp_control_status |
880 | || rawnum == mips_regnum (gdbarch)->fp_implementation_revision) | |
881 | return builtin_type (gdbarch)->builtin_int32; | |
882 | else if (gdbarch_osabi (gdbarch) != GDB_OSABI_IRIX | |
883 | && gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX | |
884 | && rawnum >= MIPS_FIRST_EMBED_REGNUM | |
885 | && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
d5ac5a39 AC |
886 | /* The pseudo/cooked view of the embedded registers is always |
887 | 32-bit. The raw view is handled below. */ | |
df4df182 | 888 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
889 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
890 | /* The target, while possibly using a 64-bit register buffer, | |
891 | is only transfering 32-bits of each integer register. | |
892 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
df4df182 | 893 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
894 | else if (mips_abi_regsize (gdbarch) == 4) |
895 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
896 | 32- or 64-bit). */ | |
df4df182 | 897 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
898 | else |
899 | /* 64-bit ABI. */ | |
df4df182 | 900 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 901 | } |
78fde5f8 KB |
902 | } |
903 | ||
f8b73d13 DJ |
904 | /* Return the GDB type for the pseudo register REGNUM, which is the |
905 | ABI-level view. This function is only called if there is a target | |
906 | description which includes registers, so we know precisely the | |
907 | types of hardware registers. */ | |
908 | ||
909 | static struct type * | |
910 | mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
911 | { | |
912 | const int num_regs = gdbarch_num_regs (gdbarch); | |
913 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
914 | int rawnum = regnum % num_regs; | |
915 | struct type *rawtype; | |
916 | ||
917 | gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); | |
918 | ||
919 | /* Absent registers are still absent. */ | |
920 | rawtype = gdbarch_register_type (gdbarch, rawnum); | |
921 | if (TYPE_LENGTH (rawtype) == 0) | |
922 | return rawtype; | |
923 | ||
1faeff08 MR |
924 | if (rawnum >= mips_regnum (gdbarch)->fp0 |
925 | && rawnum < mips_regnum (gdbarch)->fp0 + 32) | |
f8b73d13 DJ |
926 | /* Present the floating point registers however the hardware did; |
927 | do not try to convert between FPU layouts. */ | |
928 | return rawtype; | |
929 | ||
f8b73d13 DJ |
930 | /* Use pointer types for registers if we can. For n32 we can not, |
931 | since we do not have a 64-bit pointer type. */ | |
0dfff4cb UW |
932 | if (mips_abi_regsize (gdbarch) |
933 | == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr)) | |
f8b73d13 | 934 | { |
1faeff08 MR |
935 | if (rawnum == MIPS_SP_REGNUM |
936 | || rawnum == mips_regnum (gdbarch)->badvaddr) | |
0dfff4cb | 937 | return builtin_type (gdbarch)->builtin_data_ptr; |
1faeff08 | 938 | else if (rawnum == mips_regnum (gdbarch)->pc) |
0dfff4cb | 939 | return builtin_type (gdbarch)->builtin_func_ptr; |
f8b73d13 DJ |
940 | } |
941 | ||
942 | if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8 | |
1faeff08 MR |
943 | && ((rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_PS_REGNUM) |
944 | || rawnum == mips_regnum (gdbarch)->lo | |
945 | || rawnum == mips_regnum (gdbarch)->hi | |
946 | || rawnum == mips_regnum (gdbarch)->badvaddr | |
947 | || rawnum == mips_regnum (gdbarch)->cause | |
948 | || rawnum == mips_regnum (gdbarch)->pc | |
949 | || (mips_regnum (gdbarch)->dspacc != -1 | |
950 | && rawnum >= mips_regnum (gdbarch)->dspacc | |
951 | && rawnum < mips_regnum (gdbarch)->dspacc + 6))) | |
df4df182 | 952 | return builtin_type (gdbarch)->builtin_int32; |
f8b73d13 | 953 | |
1faeff08 MR |
954 | if (gdbarch_osabi (gdbarch) != GDB_OSABI_IRIX |
955 | && gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX | |
956 | && rawnum >= MIPS_EMBED_FP0_REGNUM + 32 | |
957 | && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
958 | { | |
959 | /* The pseudo/cooked view of embedded registers is always | |
960 | 32-bit, even if the target transfers 64-bit values for them. | |
961 | New targets relying on XML descriptions should only transfer | |
962 | the necessary 32 bits, but older versions of GDB expected 64, | |
963 | so allow the target to provide 64 bits without interfering | |
964 | with the displayed type. */ | |
965 | return builtin_type (gdbarch)->builtin_int32; | |
966 | } | |
967 | ||
f8b73d13 DJ |
968 | /* For all other registers, pass through the hardware type. */ |
969 | return rawtype; | |
970 | } | |
bcb0cc15 | 971 | |
025bb325 | 972 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 973 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
974 | |
975 | static int | |
480d3dd2 | 976 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
977 | { |
978 | switch (mask_address_var) | |
979 | { | |
7f19b9a2 | 980 | case AUTO_BOOLEAN_TRUE: |
4014092b | 981 | return 1; |
7f19b9a2 | 982 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
983 | return 0; |
984 | break; | |
7f19b9a2 | 985 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 986 | return tdep->default_mask_address_p; |
4014092b | 987 | default: |
025bb325 MS |
988 | internal_error (__FILE__, __LINE__, |
989 | _("mips_mask_address_p: bad switch")); | |
4014092b | 990 | return -1; |
361d1df0 | 991 | } |
4014092b AC |
992 | } |
993 | ||
994 | static void | |
08546159 AC |
995 | show_mask_address (struct ui_file *file, int from_tty, |
996 | struct cmd_list_element *c, const char *value) | |
4014092b | 997 | { |
1cf3db46 | 998 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
08546159 AC |
999 | |
1000 | deprecated_show_value_hack (file, from_tty, c, value); | |
4014092b AC |
1001 | switch (mask_address_var) |
1002 | { | |
7f19b9a2 | 1003 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
1004 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
1005 | break; | |
7f19b9a2 | 1006 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
1007 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
1008 | break; | |
7f19b9a2 | 1009 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
1010 | printf_filtered |
1011 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
1012 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
1013 | break; |
1014 | default: | |
e2e0b3e5 | 1015 | internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); |
4014092b | 1016 | break; |
361d1df0 | 1017 | } |
4014092b | 1018 | } |
c906108c | 1019 | |
c906108c SS |
1020 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
1021 | ||
0fe7e7c8 AC |
1022 | int |
1023 | mips_pc_is_mips16 (CORE_ADDR memaddr) | |
c906108c SS |
1024 | { |
1025 | struct minimal_symbol *sym; | |
1026 | ||
91912e4d MR |
1027 | /* A flag indicating that this is a MIPS16 function is stored by |
1028 | elfread.c in the high bit of the info field. Use this to decide | |
1029 | if the function is MIPS16 or normal MIPS. Otherwise if bit 0 of | |
1030 | the address is set, assume this is a MIPS16 address. */ | |
c906108c SS |
1031 | sym = lookup_minimal_symbol_by_pc (memaddr); |
1032 | if (sym) | |
71b8ef93 | 1033 | return msymbol_is_special (sym); |
c906108c | 1034 | else |
91912e4d | 1035 | return is_mips16_addr (memaddr); |
c906108c SS |
1036 | } |
1037 | ||
14132e89 MR |
1038 | /* Various MIPS16 thunk (aka stub or trampoline) names. */ |
1039 | ||
1040 | static const char mips_str_mips16_call_stub[] = "__mips16_call_stub_"; | |
1041 | static const char mips_str_mips16_ret_stub[] = "__mips16_ret_"; | |
1042 | static const char mips_str_call_fp_stub[] = "__call_stub_fp_"; | |
1043 | static const char mips_str_call_stub[] = "__call_stub_"; | |
1044 | static const char mips_str_fn_stub[] = "__fn_stub_"; | |
1045 | ||
1046 | /* This is used as a PIC thunk prefix. */ | |
1047 | ||
1048 | static const char mips_str_pic[] = ".pic."; | |
1049 | ||
1050 | /* Return non-zero if the PC is inside a call thunk (aka stub or | |
1051 | trampoline) that should be treated as a temporary frame. */ | |
1052 | ||
1053 | static int | |
1054 | mips_in_frame_stub (CORE_ADDR pc) | |
1055 | { | |
1056 | CORE_ADDR start_addr; | |
1057 | const char *name; | |
1058 | ||
1059 | /* Find the starting address of the function containing the PC. */ | |
1060 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
1061 | return 0; | |
1062 | ||
1063 | /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */ | |
1064 | if (strncmp (name, mips_str_mips16_call_stub, | |
1065 | strlen (mips_str_mips16_call_stub)) == 0) | |
1066 | return 1; | |
1067 | /* If the PC is in __call_stub_*, this is a call/return or a call stub. */ | |
1068 | if (strncmp (name, mips_str_call_stub, strlen (mips_str_call_stub)) == 0) | |
1069 | return 1; | |
1070 | /* If the PC is in __fn_stub_*, this is a call stub. */ | |
1071 | if (strncmp (name, mips_str_fn_stub, strlen (mips_str_fn_stub)) == 0) | |
1072 | return 1; | |
1073 | ||
1074 | return 0; /* Not a stub. */ | |
1075 | } | |
1076 | ||
b2fa5097 | 1077 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
025bb325 | 1078 | all registers should be sign extended for simplicity? */ |
6c997a34 AC |
1079 | |
1080 | static CORE_ADDR | |
61a1198a | 1081 | mips_read_pc (struct regcache *regcache) |
6c997a34 | 1082 | { |
61a1198a UW |
1083 | ULONGEST pc; |
1084 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; | |
1085 | regcache_cooked_read_signed (regcache, regnum, &pc); | |
930bd0e0 KB |
1086 | if (is_mips16_addr (pc)) |
1087 | pc = unmake_mips16_addr (pc); | |
61a1198a | 1088 | return pc; |
b6cb9035 AC |
1089 | } |
1090 | ||
58dfe9ff AC |
1091 | static CORE_ADDR |
1092 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1093 | { | |
14132e89 | 1094 | CORE_ADDR pc; |
930bd0e0 KB |
1095 | |
1096 | pc = frame_unwind_register_signed | |
1097 | (next_frame, gdbarch_num_regs (gdbarch) + mips_regnum (gdbarch)->pc); | |
1098 | if (is_mips16_addr (pc)) | |
1099 | pc = unmake_mips16_addr (pc); | |
14132e89 MR |
1100 | /* macro/2012-04-20: This hack skips over MIPS16 call thunks as |
1101 | intermediate frames. In this case we can get the caller's address | |
1102 | from $ra, or if $ra contains an address within a thunk as well, then | |
1103 | it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10} | |
1104 | and thus the caller's address is in $s2. */ | |
1105 | if (frame_relative_level (next_frame) >= 0 && mips_in_frame_stub (pc)) | |
1106 | { | |
1107 | pc = frame_unwind_register_signed | |
1108 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM); | |
1109 | if (is_mips16_addr (pc)) | |
1110 | pc = unmake_mips16_addr (pc); | |
1111 | if (mips_in_frame_stub (pc)) | |
1112 | { | |
1113 | pc = frame_unwind_register_signed | |
1114 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); | |
1115 | if (is_mips16_addr (pc)) | |
1116 | pc = unmake_mips16_addr (pc); | |
1117 | } | |
1118 | } | |
930bd0e0 | 1119 | return pc; |
edfae063 AC |
1120 | } |
1121 | ||
30244cd8 UW |
1122 | static CORE_ADDR |
1123 | mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1124 | { | |
72a155b4 UW |
1125 | return frame_unwind_register_signed |
1126 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM); | |
30244cd8 UW |
1127 | } |
1128 | ||
b8a22b94 | 1129 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that |
edfae063 AC |
1130 | dummy frame. The frame ID's base needs to match the TOS value |
1131 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
1132 | breakpoint. */ | |
1133 | ||
1134 | static struct frame_id | |
b8a22b94 | 1135 | mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
edfae063 | 1136 | { |
f57d151a | 1137 | return frame_id_build |
b8a22b94 DJ |
1138 | (get_frame_register_signed (this_frame, |
1139 | gdbarch_num_regs (gdbarch) | |
1140 | + MIPS_SP_REGNUM), | |
1141 | get_frame_pc (this_frame)); | |
58dfe9ff AC |
1142 | } |
1143 | ||
b6cb9035 | 1144 | static void |
61a1198a | 1145 | mips_write_pc (struct regcache *regcache, CORE_ADDR pc) |
b6cb9035 | 1146 | { |
61a1198a | 1147 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; |
930bd0e0 KB |
1148 | if (mips_pc_is_mips16 (pc)) |
1149 | regcache_cooked_write_unsigned (regcache, regnum, make_mips16_addr (pc)); | |
1150 | else | |
1151 | regcache_cooked_write_unsigned (regcache, regnum, pc); | |
6c997a34 | 1152 | } |
c906108c | 1153 | |
c906108c SS |
1154 | /* Fetch and return instruction from the specified location. If the PC |
1155 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
1156 | ||
d37cca3d | 1157 | static ULONGEST |
e17a4113 | 1158 | mips_fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR addr) |
c906108c | 1159 | { |
e17a4113 | 1160 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 1161 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
1162 | int instlen; |
1163 | int status; | |
1164 | ||
0fe7e7c8 | 1165 | if (mips_pc_is_mips16 (addr)) |
c906108c | 1166 | { |
95ac2dcf | 1167 | instlen = MIPS_INSN16_SIZE; |
95404a3e | 1168 | addr = unmake_mips16_addr (addr); |
c906108c SS |
1169 | } |
1170 | else | |
95ac2dcf | 1171 | instlen = MIPS_INSN32_SIZE; |
8defab1a | 1172 | status = target_read_memory (addr, buf, instlen); |
c906108c SS |
1173 | if (status) |
1174 | memory_error (status, addr); | |
e17a4113 | 1175 | return extract_unsigned_integer (buf, instlen, byte_order); |
c906108c SS |
1176 | } |
1177 | ||
025bb325 | 1178 | /* These are the fields of 32 bit mips instructions. */ |
e135b889 DJ |
1179 | #define mips32_op(x) (x >> 26) |
1180 | #define itype_op(x) (x >> 26) | |
1181 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 1182 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 1183 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 1184 | |
e135b889 DJ |
1185 | #define jtype_op(x) (x >> 26) |
1186 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 1187 | |
e135b889 DJ |
1188 | #define rtype_op(x) (x >> 26) |
1189 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
1190 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
1191 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
1192 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
1193 | #define rtype_funct(x) (x & 0x3f) | |
c906108c | 1194 | |
06987e64 MK |
1195 | static LONGEST |
1196 | mips32_relative_offset (ULONGEST inst) | |
c5aa993b | 1197 | { |
06987e64 | 1198 | return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; |
c906108c SS |
1199 | } |
1200 | ||
a385295e MR |
1201 | /* Determine the address of the next instruction executed after the INST |
1202 | floating condition branch instruction at PC. COUNT specifies the | |
1203 | number of the floating condition bits tested by the branch. */ | |
1204 | ||
1205 | static CORE_ADDR | |
1206 | mips32_bc1_pc (struct gdbarch *gdbarch, struct frame_info *frame, | |
1207 | ULONGEST inst, CORE_ADDR pc, int count) | |
1208 | { | |
1209 | int fcsr = mips_regnum (gdbarch)->fp_control_status; | |
1210 | int cnum = (itype_rt (inst) >> 2) & (count - 1); | |
1211 | int tf = itype_rt (inst) & 1; | |
1212 | int mask = (1 << count) - 1; | |
1213 | ULONGEST fcs; | |
1214 | int cond; | |
1215 | ||
1216 | if (fcsr == -1) | |
1217 | /* No way to handle; it'll most likely trap anyway. */ | |
1218 | return pc; | |
1219 | ||
1220 | fcs = get_frame_register_unsigned (frame, fcsr); | |
1221 | cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); | |
1222 | ||
1223 | if (((cond >> cnum) & mask) != mask * !tf) | |
1224 | pc += mips32_relative_offset (inst); | |
1225 | else | |
1226 | pc += 4; | |
1227 | ||
1228 | return pc; | |
1229 | } | |
1230 | ||
f49e4e6d MS |
1231 | /* Determine where to set a single step breakpoint while considering |
1232 | branch prediction. */ | |
5a89d8aa | 1233 | static CORE_ADDR |
0b1b3e42 | 1234 | mips32_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c5aa993b | 1235 | { |
e17a4113 | 1236 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c5aa993b JM |
1237 | unsigned long inst; |
1238 | int op; | |
e17a4113 | 1239 | inst = mips_fetch_instruction (gdbarch, pc); |
025bb325 MS |
1240 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch |
1241 | instruction. */ | |
c5aa993b | 1242 | { |
e135b889 | 1243 | if (itype_op (inst) >> 2 == 5) |
6d82d43b | 1244 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 1245 | { |
e135b889 | 1246 | op = (itype_op (inst) & 0x03); |
c906108c SS |
1247 | switch (op) |
1248 | { | |
e135b889 DJ |
1249 | case 0: /* BEQL */ |
1250 | goto equal_branch; | |
1251 | case 1: /* BNEL */ | |
1252 | goto neq_branch; | |
1253 | case 2: /* BLEZL */ | |
1254 | goto less_branch; | |
313628cc | 1255 | case 3: /* BGTZL */ |
e135b889 | 1256 | goto greater_branch; |
c5aa993b JM |
1257 | default: |
1258 | pc += 4; | |
c906108c SS |
1259 | } |
1260 | } | |
e135b889 | 1261 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
6d82d43b | 1262 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
a385295e MR |
1263 | pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 1); |
1264 | else if (itype_op (inst) == 17 && itype_rs (inst) == 9 | |
1265 | && (itype_rt (inst) & 2) == 0) | |
1266 | /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */ | |
1267 | pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 2); | |
1268 | else if (itype_op (inst) == 17 && itype_rs (inst) == 10 | |
1269 | && (itype_rt (inst) & 2) == 0) | |
1270 | /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */ | |
1271 | pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 4); | |
9e8da49c MR |
1272 | else if (itype_op (inst) == 29) |
1273 | /* JALX: 011101 */ | |
1274 | /* The new PC will be alternate mode. */ | |
1275 | { | |
1276 | unsigned long reg; | |
1277 | ||
1278 | reg = jtype_target (inst) << 2; | |
1279 | /* Add 1 to indicate 16-bit mode -- invert ISA mode. */ | |
1280 | pc = ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + reg + 1; | |
1281 | } | |
c5aa993b | 1282 | else |
025bb325 | 1283 | pc += 4; /* Not a branch, next instruction is easy. */ |
c906108c SS |
1284 | } |
1285 | else | |
025bb325 | 1286 | { /* This gets way messy. */ |
c5aa993b | 1287 | |
025bb325 MS |
1288 | /* Further subdivide into SPECIAL, REGIMM and other. */ |
1289 | switch (op = itype_op (inst) & 0x07) /* Extract bits 28,27,26. */ | |
c906108c | 1290 | { |
c5aa993b JM |
1291 | case 0: /* SPECIAL */ |
1292 | op = rtype_funct (inst); | |
1293 | switch (op) | |
1294 | { | |
1295 | case 8: /* JR */ | |
1296 | case 9: /* JALR */ | |
025bb325 | 1297 | /* Set PC to that address. */ |
0b1b3e42 | 1298 | pc = get_frame_register_signed (frame, rtype_rs (inst)); |
c5aa993b | 1299 | break; |
e38d4e1a DJ |
1300 | case 12: /* SYSCALL */ |
1301 | { | |
1302 | struct gdbarch_tdep *tdep; | |
1303 | ||
1304 | tdep = gdbarch_tdep (get_frame_arch (frame)); | |
1305 | if (tdep->syscall_next_pc != NULL) | |
1306 | pc = tdep->syscall_next_pc (frame); | |
1307 | else | |
1308 | pc += 4; | |
1309 | } | |
1310 | break; | |
c5aa993b JM |
1311 | default: |
1312 | pc += 4; | |
1313 | } | |
1314 | ||
6d82d43b | 1315 | break; /* end SPECIAL */ |
025bb325 | 1316 | case 1: /* REGIMM */ |
c906108c | 1317 | { |
e135b889 DJ |
1318 | op = itype_rt (inst); /* branch condition */ |
1319 | switch (op) | |
c906108c | 1320 | { |
c5aa993b | 1321 | case 0: /* BLTZ */ |
e135b889 DJ |
1322 | case 2: /* BLTZL */ |
1323 | case 16: /* BLTZAL */ | |
c5aa993b | 1324 | case 18: /* BLTZALL */ |
c906108c | 1325 | less_branch: |
0b1b3e42 | 1326 | if (get_frame_register_signed (frame, itype_rs (inst)) < 0) |
c5aa993b JM |
1327 | pc += mips32_relative_offset (inst) + 4; |
1328 | else | |
1329 | pc += 8; /* after the delay slot */ | |
1330 | break; | |
e135b889 | 1331 | case 1: /* BGEZ */ |
c5aa993b JM |
1332 | case 3: /* BGEZL */ |
1333 | case 17: /* BGEZAL */ | |
1334 | case 19: /* BGEZALL */ | |
0b1b3e42 | 1335 | if (get_frame_register_signed (frame, itype_rs (inst)) >= 0) |
c5aa993b JM |
1336 | pc += mips32_relative_offset (inst) + 4; |
1337 | else | |
1338 | pc += 8; /* after the delay slot */ | |
1339 | break; | |
a385295e MR |
1340 | case 0x1c: /* BPOSGE32 */ |
1341 | case 0x1e: /* BPOSGE64 */ | |
1342 | pc += 4; | |
1343 | if (itype_rs (inst) == 0) | |
1344 | { | |
1345 | unsigned int pos = (op & 2) ? 64 : 32; | |
1346 | int dspctl = mips_regnum (gdbarch)->dspctl; | |
1347 | ||
1348 | if (dspctl == -1) | |
1349 | /* No way to handle; it'll most likely trap anyway. */ | |
1350 | break; | |
1351 | ||
1352 | if ((get_frame_register_unsigned (frame, | |
1353 | dspctl) & 0x7f) >= pos) | |
1354 | pc += mips32_relative_offset (inst); | |
1355 | else | |
1356 | pc += 4; | |
1357 | } | |
1358 | break; | |
e135b889 | 1359 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1360 | default: |
1361 | pc += 4; | |
c906108c SS |
1362 | } |
1363 | } | |
6d82d43b | 1364 | break; /* end REGIMM */ |
c5aa993b JM |
1365 | case 2: /* J */ |
1366 | case 3: /* JAL */ | |
1367 | { | |
1368 | unsigned long reg; | |
1369 | reg = jtype_target (inst) << 2; | |
025bb325 | 1370 | /* Upper four bits get never changed... */ |
5b652102 | 1371 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
c906108c | 1372 | } |
c5aa993b | 1373 | break; |
e135b889 | 1374 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1375 | equal_branch: |
0b1b3e42 UW |
1376 | if (get_frame_register_signed (frame, itype_rs (inst)) == |
1377 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1378 | pc += mips32_relative_offset (inst) + 4; |
1379 | else | |
1380 | pc += 8; | |
1381 | break; | |
e135b889 | 1382 | case 5: /* BNE, BNEL */ |
c5aa993b | 1383 | neq_branch: |
0b1b3e42 UW |
1384 | if (get_frame_register_signed (frame, itype_rs (inst)) != |
1385 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1386 | pc += mips32_relative_offset (inst) + 4; |
1387 | else | |
1388 | pc += 8; | |
1389 | break; | |
e135b889 | 1390 | case 6: /* BLEZ, BLEZL */ |
0b1b3e42 | 1391 | if (get_frame_register_signed (frame, itype_rs (inst)) <= 0) |
c5aa993b JM |
1392 | pc += mips32_relative_offset (inst) + 4; |
1393 | else | |
1394 | pc += 8; | |
1395 | break; | |
1396 | case 7: | |
e135b889 DJ |
1397 | default: |
1398 | greater_branch: /* BGTZ, BGTZL */ | |
0b1b3e42 | 1399 | if (get_frame_register_signed (frame, itype_rs (inst)) > 0) |
c5aa993b JM |
1400 | pc += mips32_relative_offset (inst) + 4; |
1401 | else | |
1402 | pc += 8; | |
1403 | break; | |
c5aa993b JM |
1404 | } /* switch */ |
1405 | } /* else */ | |
1406 | return pc; | |
1407 | } /* mips32_next_pc */ | |
c906108c SS |
1408 | |
1409 | /* Decoding the next place to set a breakpoint is irregular for the | |
025bb325 MS |
1410 | mips 16 variant, but fortunately, there fewer instructions. We have |
1411 | to cope ith extensions for 16 bit instructions and a pair of actual | |
1412 | 32 bit instructions. We dont want to set a single step instruction | |
1413 | on the extend instruction either. */ | |
c906108c SS |
1414 | |
1415 | /* Lots of mips16 instruction formats */ | |
1416 | /* Predicting jumps requires itype,ritype,i8type | |
025bb325 | 1417 | and their extensions extItype,extritype,extI8type. */ |
c906108c SS |
1418 | enum mips16_inst_fmts |
1419 | { | |
c5aa993b JM |
1420 | itype, /* 0 immediate 5,10 */ |
1421 | ritype, /* 1 5,3,8 */ | |
1422 | rrtype, /* 2 5,3,3,5 */ | |
1423 | rritype, /* 3 5,3,3,5 */ | |
1424 | rrrtype, /* 4 5,3,3,3,2 */ | |
1425 | rriatype, /* 5 5,3,3,1,4 */ | |
1426 | shifttype, /* 6 5,3,3,3,2 */ | |
1427 | i8type, /* 7 5,3,8 */ | |
1428 | i8movtype, /* 8 5,3,3,5 */ | |
1429 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1430 | i64type, /* 10 5,3,8 */ | |
1431 | ri64type, /* 11 5,3,3,5 */ | |
1432 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1433 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1434 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1435 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1436 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1437 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1438 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1439 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1440 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1441 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1442 | }; | |
12f02c2a | 1443 | /* I am heaping all the fields of the formats into one structure and |
025bb325 | 1444 | then, only the fields which are involved in instruction extension. */ |
c906108c | 1445 | struct upk_mips16 |
6d82d43b AC |
1446 | { |
1447 | CORE_ADDR offset; | |
025bb325 | 1448 | unsigned int regx; /* Function in i8 type. */ |
6d82d43b AC |
1449 | unsigned int regy; |
1450 | }; | |
c906108c SS |
1451 | |
1452 | ||
12f02c2a | 1453 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
c68cf8ad | 1454 | for the bits which make up the immediate extension. */ |
c906108c | 1455 | |
12f02c2a AC |
1456 | static CORE_ADDR |
1457 | extended_offset (unsigned int extension) | |
c906108c | 1458 | { |
12f02c2a | 1459 | CORE_ADDR value; |
130854df | 1460 | |
4c2051c6 | 1461 | value = (extension >> 16) & 0x1f; /* Extract 15:11. */ |
c5aa993b | 1462 | value = value << 6; |
4c2051c6 | 1463 | value |= (extension >> 21) & 0x3f; /* Extract 10:5. */ |
c5aa993b | 1464 | value = value << 5; |
130854df MR |
1465 | value |= extension & 0x1f; /* Extract 4:0. */ |
1466 | ||
c5aa993b | 1467 | return value; |
c906108c SS |
1468 | } |
1469 | ||
1470 | /* Only call this function if you know that this is an extendable | |
bcf1ea1e MR |
1471 | instruction. It won't malfunction, but why make excess remote memory |
1472 | references? If the immediate operands get sign extended or something, | |
1473 | do it after the extension is performed. */ | |
c906108c | 1474 | /* FIXME: Every one of these cases needs to worry about sign extension |
bcf1ea1e | 1475 | when the offset is to be used in relative addressing. */ |
c906108c | 1476 | |
12f02c2a | 1477 | static unsigned int |
e17a4113 | 1478 | fetch_mips_16 (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 1479 | { |
e17a4113 | 1480 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 1481 | gdb_byte buf[8]; |
025bb325 | 1482 | pc &= 0xfffffffe; /* Clear the low order bit. */ |
c5aa993b | 1483 | target_read_memory (pc, buf, 2); |
e17a4113 | 1484 | return extract_unsigned_integer (buf, 2, byte_order); |
c906108c SS |
1485 | } |
1486 | ||
1487 | static void | |
e17a4113 | 1488 | unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc, |
12f02c2a AC |
1489 | unsigned int extension, |
1490 | unsigned int inst, | |
6d82d43b | 1491 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 1492 | { |
12f02c2a AC |
1493 | CORE_ADDR offset; |
1494 | int regx; | |
1495 | int regy; | |
1496 | switch (insn_format) | |
c906108c | 1497 | { |
c5aa993b | 1498 | case itype: |
c906108c | 1499 | { |
12f02c2a AC |
1500 | CORE_ADDR value; |
1501 | if (extension) | |
c5aa993b | 1502 | { |
4c2051c6 MR |
1503 | value = extended_offset ((extension << 16) | inst); |
1504 | value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ | |
c906108c SS |
1505 | } |
1506 | else | |
c5aa993b | 1507 | { |
12f02c2a | 1508 | value = inst & 0x7ff; |
4c2051c6 | 1509 | value = (value ^ 0x400) - 0x400; /* Sign-extend. */ |
c906108c | 1510 | } |
12f02c2a AC |
1511 | offset = value; |
1512 | regx = -1; | |
1513 | regy = -1; | |
c906108c | 1514 | } |
c5aa993b JM |
1515 | break; |
1516 | case ritype: | |
1517 | case i8type: | |
025bb325 | 1518 | { /* A register identifier and an offset. */ |
c906108c | 1519 | /* Most of the fields are the same as I type but the |
025bb325 | 1520 | immediate value is of a different length. */ |
12f02c2a AC |
1521 | CORE_ADDR value; |
1522 | if (extension) | |
c906108c | 1523 | { |
4c2051c6 MR |
1524 | value = extended_offset ((extension << 16) | inst); |
1525 | value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ | |
c906108c | 1526 | } |
c5aa993b JM |
1527 | else |
1528 | { | |
4c2051c6 MR |
1529 | value = inst & 0xff; /* 8 bits */ |
1530 | value = (value ^ 0x80) - 0x80; /* Sign-extend. */ | |
c5aa993b | 1531 | } |
12f02c2a | 1532 | offset = value; |
4c2051c6 | 1533 | regx = (inst >> 8) & 0x07; /* i8 funct */ |
12f02c2a | 1534 | regy = -1; |
c5aa993b | 1535 | break; |
c906108c | 1536 | } |
c5aa993b | 1537 | case jalxtype: |
c906108c | 1538 | { |
c5aa993b | 1539 | unsigned long value; |
12f02c2a AC |
1540 | unsigned int nexthalf; |
1541 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b | 1542 | value = value << 16; |
025bb325 MS |
1543 | nexthalf = mips_fetch_instruction (gdbarch, pc + 2); /* low bit |
1544 | still set. */ | |
c5aa993b | 1545 | value |= nexthalf; |
12f02c2a AC |
1546 | offset = value; |
1547 | regx = -1; | |
1548 | regy = -1; | |
c5aa993b | 1549 | break; |
c906108c SS |
1550 | } |
1551 | default: | |
e2e0b3e5 | 1552 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c | 1553 | } |
12f02c2a AC |
1554 | upk->offset = offset; |
1555 | upk->regx = regx; | |
1556 | upk->regy = regy; | |
c906108c SS |
1557 | } |
1558 | ||
1559 | ||
c5aa993b JM |
1560 | static CORE_ADDR |
1561 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1562 | { |
5b652102 | 1563 | return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff))); |
c906108c SS |
1564 | } |
1565 | ||
12f02c2a | 1566 | static CORE_ADDR |
0b1b3e42 | 1567 | extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc, |
6d82d43b | 1568 | unsigned int extension, unsigned int insn) |
c906108c | 1569 | { |
e17a4113 | 1570 | struct gdbarch *gdbarch = get_frame_arch (frame); |
12f02c2a AC |
1571 | int op = (insn >> 11); |
1572 | switch (op) | |
c906108c | 1573 | { |
6d82d43b | 1574 | case 2: /* Branch */ |
12f02c2a AC |
1575 | { |
1576 | CORE_ADDR offset; | |
1577 | struct upk_mips16 upk; | |
e17a4113 | 1578 | unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk); |
4c2051c6 | 1579 | pc += (upk.offset << 1) + 2; |
12f02c2a AC |
1580 | break; |
1581 | } | |
025bb325 MS |
1582 | case 3: /* JAL , JALX - Watch out, these are 32 bit |
1583 | instructions. */ | |
12f02c2a AC |
1584 | { |
1585 | struct upk_mips16 upk; | |
e17a4113 | 1586 | unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk); |
12f02c2a AC |
1587 | pc = add_offset_16 (pc, upk.offset); |
1588 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
025bb325 | 1589 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode. */ |
12f02c2a AC |
1590 | else |
1591 | pc |= 0x01; | |
1592 | break; | |
1593 | } | |
6d82d43b | 1594 | case 4: /* beqz */ |
12f02c2a AC |
1595 | { |
1596 | struct upk_mips16 upk; | |
1597 | int reg; | |
e17a4113 | 1598 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
4c2051c6 | 1599 | reg = get_frame_register_signed (frame, mips16_to_32_reg[upk.regx]); |
12f02c2a AC |
1600 | if (reg == 0) |
1601 | pc += (upk.offset << 1) + 2; | |
1602 | else | |
1603 | pc += 2; | |
1604 | break; | |
1605 | } | |
6d82d43b | 1606 | case 5: /* bnez */ |
12f02c2a AC |
1607 | { |
1608 | struct upk_mips16 upk; | |
1609 | int reg; | |
e17a4113 | 1610 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
4c2051c6 | 1611 | reg = get_frame_register_signed (frame, mips16_to_32_reg[upk.regx]); |
12f02c2a AC |
1612 | if (reg != 0) |
1613 | pc += (upk.offset << 1) + 2; | |
1614 | else | |
1615 | pc += 2; | |
1616 | break; | |
1617 | } | |
6d82d43b | 1618 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
1619 | { |
1620 | struct upk_mips16 upk; | |
1621 | int reg; | |
e17a4113 | 1622 | unpack_mips16 (gdbarch, pc, extension, insn, i8type, &upk); |
12f02c2a | 1623 | /* upk.regx contains the opcode */ |
0b1b3e42 | 1624 | reg = get_frame_register_signed (frame, 24); /* Test register is 24 */ |
12f02c2a AC |
1625 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ |
1626 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1627 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1628 | pc += (upk.offset << 1) + 2; | |
1629 | else | |
1630 | pc += 2; | |
1631 | break; | |
1632 | } | |
6d82d43b | 1633 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
1634 | { |
1635 | struct upk_mips16 upk; | |
1636 | /* upk.fmt = rrtype; */ | |
1637 | op = insn & 0x1f; | |
1638 | if (op == 0) | |
c5aa993b | 1639 | { |
12f02c2a AC |
1640 | int reg; |
1641 | upk.regx = (insn >> 8) & 0x07; | |
1642 | upk.regy = (insn >> 5) & 0x07; | |
4c2051c6 MR |
1643 | if ((upk.regy & 1) == 0) |
1644 | reg = mips16_to_32_reg[upk.regx]; | |
1645 | else | |
1646 | reg = 31; /* Function return instruction. */ | |
0b1b3e42 | 1647 | pc = get_frame_register_signed (frame, reg); |
c906108c | 1648 | } |
12f02c2a | 1649 | else |
c5aa993b | 1650 | pc += 2; |
12f02c2a AC |
1651 | break; |
1652 | } | |
1653 | case 30: | |
1654 | /* This is an instruction extension. Fetch the real instruction | |
1655 | (which follows the extension) and decode things based on | |
025bb325 | 1656 | that. */ |
12f02c2a AC |
1657 | { |
1658 | pc += 2; | |
e17a4113 UW |
1659 | pc = extended_mips16_next_pc (frame, pc, insn, |
1660 | fetch_mips_16 (gdbarch, pc)); | |
12f02c2a AC |
1661 | break; |
1662 | } | |
1663 | default: | |
1664 | { | |
1665 | pc += 2; | |
1666 | break; | |
1667 | } | |
c906108c | 1668 | } |
c5aa993b | 1669 | return pc; |
12f02c2a | 1670 | } |
c906108c | 1671 | |
5a89d8aa | 1672 | static CORE_ADDR |
0b1b3e42 | 1673 | mips16_next_pc (struct frame_info *frame, CORE_ADDR pc) |
12f02c2a | 1674 | { |
e17a4113 UW |
1675 | struct gdbarch *gdbarch = get_frame_arch (frame); |
1676 | unsigned int insn = fetch_mips_16 (gdbarch, pc); | |
0b1b3e42 | 1677 | return extended_mips16_next_pc (frame, pc, 0, insn); |
12f02c2a AC |
1678 | } |
1679 | ||
1680 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1681 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a | 1682 | It works by decoding the current instruction and predicting where a |
025bb325 | 1683 | branch will go. This isnt hard because all the data is available. |
ce1f96de | 1684 | The MIPS32 and MIPS16 variants are quite different. */ |
ad527d2e | 1685 | static CORE_ADDR |
0b1b3e42 | 1686 | mips_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 1687 | { |
91912e4d | 1688 | if (mips_pc_is_mips16 (pc)) |
0b1b3e42 | 1689 | return mips16_next_pc (frame, pc); |
c5aa993b | 1690 | else |
0b1b3e42 | 1691 | return mips32_next_pc (frame, pc); |
12f02c2a | 1692 | } |
c906108c | 1693 | |
edfae063 AC |
1694 | struct mips_frame_cache |
1695 | { | |
1696 | CORE_ADDR base; | |
1697 | struct trad_frame_saved_reg *saved_regs; | |
1698 | }; | |
1699 | ||
29639122 JB |
1700 | /* Set a register's saved stack address in temp_saved_regs. If an |
1701 | address has already been set for this register, do nothing; this | |
1702 | way we will only recognize the first save of a given register in a | |
1703 | function prologue. | |
eec63939 | 1704 | |
f57d151a UW |
1705 | For simplicity, save the address in both [0 .. gdbarch_num_regs) and |
1706 | [gdbarch_num_regs .. 2*gdbarch_num_regs). | |
1707 | Strictly speaking, only the second range is used as it is only second | |
1708 | range (the ABI instead of ISA registers) that comes into play when finding | |
1709 | saved registers in a frame. */ | |
eec63939 AC |
1710 | |
1711 | static void | |
74ed0bb4 MD |
1712 | set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache, |
1713 | int regnum, CORE_ADDR offset) | |
eec63939 | 1714 | { |
29639122 JB |
1715 | if (this_cache != NULL |
1716 | && this_cache->saved_regs[regnum].addr == -1) | |
1717 | { | |
74ed0bb4 MD |
1718 | this_cache->saved_regs[regnum + 0 * gdbarch_num_regs (gdbarch)].addr |
1719 | = offset; | |
1720 | this_cache->saved_regs[regnum + 1 * gdbarch_num_regs (gdbarch)].addr | |
1721 | = offset; | |
29639122 | 1722 | } |
eec63939 AC |
1723 | } |
1724 | ||
eec63939 | 1725 | |
29639122 JB |
1726 | /* Fetch the immediate value from a MIPS16 instruction. |
1727 | If the previous instruction was an EXTEND, use it to extend | |
1728 | the upper bits of the immediate value. This is a helper function | |
1729 | for mips16_scan_prologue. */ | |
eec63939 | 1730 | |
29639122 JB |
1731 | static int |
1732 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ | |
1733 | unsigned short inst, /* current instruction */ | |
1734 | int nbits, /* number of bits in imm field */ | |
1735 | int scale, /* scale factor to be applied to imm */ | |
025bb325 | 1736 | int is_signed) /* is the imm field signed? */ |
eec63939 | 1737 | { |
29639122 | 1738 | int offset; |
eec63939 | 1739 | |
29639122 JB |
1740 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
1741 | { | |
1742 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
1743 | if (offset & 0x8000) /* check for negative extend */ | |
1744 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
1745 | return offset | (inst & 0x1f); | |
1746 | } | |
eec63939 | 1747 | else |
29639122 JB |
1748 | { |
1749 | int max_imm = 1 << nbits; | |
1750 | int mask = max_imm - 1; | |
1751 | int sign_bit = max_imm >> 1; | |
45c9dd44 | 1752 | |
29639122 JB |
1753 | offset = inst & mask; |
1754 | if (is_signed && (offset & sign_bit)) | |
1755 | offset = 0 - (max_imm - offset); | |
1756 | return offset * scale; | |
1757 | } | |
1758 | } | |
eec63939 | 1759 | |
65596487 | 1760 | |
29639122 JB |
1761 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1762 | the associated FRAME_CACHE if not null. | |
1763 | Return the address of the first instruction past the prologue. */ | |
eec63939 | 1764 | |
29639122 | 1765 | static CORE_ADDR |
e17a4113 UW |
1766 | mips16_scan_prologue (struct gdbarch *gdbarch, |
1767 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 1768 | struct frame_info *this_frame, |
29639122 JB |
1769 | struct mips_frame_cache *this_cache) |
1770 | { | |
1771 | CORE_ADDR cur_pc; | |
025bb325 | 1772 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer. */ |
29639122 JB |
1773 | CORE_ADDR sp; |
1774 | long frame_offset = 0; /* Size of stack frame. */ | |
1775 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
1776 | int frame_reg = MIPS_SP_REGNUM; | |
025bb325 | 1777 | unsigned short prev_inst = 0; /* saved copy of previous instruction. */ |
29639122 JB |
1778 | unsigned inst = 0; /* current instruction */ |
1779 | unsigned entry_inst = 0; /* the entry instruction */ | |
2207132d | 1780 | unsigned save_inst = 0; /* the save instruction */ |
29639122 | 1781 | int reg, offset; |
a343eb3c | 1782 | |
29639122 JB |
1783 | int extend_bytes = 0; |
1784 | int prev_extend_bytes; | |
1785 | CORE_ADDR end_prologue_addr = 0; | |
a343eb3c | 1786 | |
29639122 | 1787 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
1788 | THIS_FRAME. */ |
1789 | if (this_frame != NULL) | |
1790 | sp = get_frame_register_signed (this_frame, | |
1791 | gdbarch_num_regs (gdbarch) | |
1792 | + MIPS_SP_REGNUM); | |
29639122 JB |
1793 | else |
1794 | sp = 0; | |
eec63939 | 1795 | |
29639122 JB |
1796 | if (limit_pc > start_pc + 200) |
1797 | limit_pc = start_pc + 200; | |
eec63939 | 1798 | |
95ac2dcf | 1799 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) |
29639122 JB |
1800 | { |
1801 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1802 | the immediate offset extension from it in mips16_get_imm. */ | |
1803 | prev_inst = inst; | |
eec63939 | 1804 | |
025bb325 | 1805 | /* Fetch and decode the instruction. */ |
e17a4113 | 1806 | inst = (unsigned short) mips_fetch_instruction (gdbarch, cur_pc); |
eec63939 | 1807 | |
29639122 JB |
1808 | /* Normally we ignore extend instructions. However, if it is |
1809 | not followed by a valid prologue instruction, then this | |
1810 | instruction is not part of the prologue either. We must | |
1811 | remember in this case to adjust the end_prologue_addr back | |
1812 | over the extend. */ | |
1813 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
1814 | { | |
95ac2dcf | 1815 | extend_bytes = MIPS_INSN16_SIZE; |
29639122 JB |
1816 | continue; |
1817 | } | |
eec63939 | 1818 | |
29639122 JB |
1819 | prev_extend_bytes = extend_bytes; |
1820 | extend_bytes = 0; | |
eec63939 | 1821 | |
29639122 JB |
1822 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
1823 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1824 | { | |
1825 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
025bb325 | 1826 | if (offset < 0) /* Negative stack adjustment? */ |
29639122 JB |
1827 | frame_offset -= offset; |
1828 | else | |
1829 | /* Exit loop if a positive stack adjustment is found, which | |
1830 | usually means that the stack cleanup code in the function | |
1831 | epilogue is reached. */ | |
1832 | break; | |
1833 | } | |
1834 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
1835 | { | |
1836 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1837 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
74ed0bb4 | 1838 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
1839 | } |
1840 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
1841 | { | |
1842 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1843 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1844 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
1845 | } |
1846 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
1847 | { | |
1848 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
74ed0bb4 | 1849 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1850 | } |
1851 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
1852 | { | |
1853 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
74ed0bb4 | 1854 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1855 | } |
1856 | else if (inst == 0x673d) /* move $s1, $sp */ | |
1857 | { | |
1858 | frame_addr = sp; | |
1859 | frame_reg = 17; | |
1860 | } | |
1861 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
1862 | { | |
1863 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1864 | frame_addr = sp + offset; | |
1865 | frame_reg = 17; | |
1866 | frame_adjust = offset; | |
1867 | } | |
1868 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
1869 | { | |
1870 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
1871 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1872 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
1873 | } |
1874 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
1875 | { | |
1876 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1877 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1878 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
1879 | } |
1880 | else if ((inst & 0xf81f) == 0xe809 | |
1881 | && (inst & 0x700) != 0x700) /* entry */ | |
025bb325 | 1882 | entry_inst = inst; /* Save for later processing. */ |
2207132d MR |
1883 | else if ((inst & 0xff80) == 0x6480) /* save */ |
1884 | { | |
025bb325 | 1885 | save_inst = inst; /* Save for later processing. */ |
2207132d MR |
1886 | if (prev_extend_bytes) /* extend */ |
1887 | save_inst |= prev_inst << 16; | |
1888 | } | |
29639122 | 1889 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
95ac2dcf | 1890 | cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ |
29639122 JB |
1891 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
1892 | { | |
1893 | /* This instruction is part of the prologue, but we don't | |
1894 | need to do anything special to handle it. */ | |
1895 | } | |
1896 | else | |
1897 | { | |
1898 | /* This instruction is not an instruction typically found | |
1899 | in a prologue, so we must have reached the end of the | |
1900 | prologue. */ | |
1901 | if (end_prologue_addr == 0) | |
1902 | end_prologue_addr = cur_pc - prev_extend_bytes; | |
1903 | } | |
1904 | } | |
eec63939 | 1905 | |
29639122 JB |
1906 | /* The entry instruction is typically the first instruction in a function, |
1907 | and it stores registers at offsets relative to the value of the old SP | |
1908 | (before the prologue). But the value of the sp parameter to this | |
1909 | function is the new SP (after the prologue has been executed). So we | |
1910 | can't calculate those offsets until we've seen the entire prologue, | |
025bb325 | 1911 | and can calculate what the old SP must have been. */ |
29639122 JB |
1912 | if (entry_inst != 0) |
1913 | { | |
1914 | int areg_count = (entry_inst >> 8) & 7; | |
1915 | int sreg_count = (entry_inst >> 6) & 3; | |
eec63939 | 1916 | |
29639122 JB |
1917 | /* The entry instruction always subtracts 32 from the SP. */ |
1918 | frame_offset += 32; | |
1919 | ||
1920 | /* Now we can calculate what the SP must have been at the | |
1921 | start of the function prologue. */ | |
1922 | sp += frame_offset; | |
1923 | ||
1924 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
1925 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
1926 | { | |
74ed0bb4 | 1927 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 1928 | offset += mips_abi_regsize (gdbarch); |
29639122 JB |
1929 | } |
1930 | ||
1931 | /* Check if the ra register was pushed on the stack. */ | |
1932 | offset = -4; | |
1933 | if (entry_inst & 0x20) | |
1934 | { | |
74ed0bb4 | 1935 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
72a155b4 | 1936 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
1937 | } |
1938 | ||
1939 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
1940 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1941 | { | |
74ed0bb4 | 1942 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 1943 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
1944 | } |
1945 | } | |
1946 | ||
2207132d MR |
1947 | /* The SAVE instruction is similar to ENTRY, except that defined by the |
1948 | MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the | |
1949 | size of the frame is specified as an immediate field of instruction | |
1950 | and an extended variation exists which lets additional registers and | |
1951 | frame space to be specified. The instruction always treats registers | |
1952 | as 32-bit so its usefulness for 64-bit ABIs is questionable. */ | |
1953 | if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4) | |
1954 | { | |
1955 | static int args_table[16] = { | |
1956 | 0, 0, 0, 0, 1, 1, 1, 1, | |
1957 | 2, 2, 2, 0, 3, 3, 4, -1, | |
1958 | }; | |
1959 | static int astatic_table[16] = { | |
1960 | 0, 1, 2, 3, 0, 1, 2, 3, | |
1961 | 0, 1, 2, 4, 0, 1, 0, -1, | |
1962 | }; | |
1963 | int aregs = (save_inst >> 16) & 0xf; | |
1964 | int xsregs = (save_inst >> 24) & 0x7; | |
1965 | int args = args_table[aregs]; | |
1966 | int astatic = astatic_table[aregs]; | |
1967 | long frame_size; | |
1968 | ||
1969 | if (args < 0) | |
1970 | { | |
1971 | warning (_("Invalid number of argument registers encoded in SAVE.")); | |
1972 | args = 0; | |
1973 | } | |
1974 | if (astatic < 0) | |
1975 | { | |
1976 | warning (_("Invalid number of static registers encoded in SAVE.")); | |
1977 | astatic = 0; | |
1978 | } | |
1979 | ||
1980 | /* For standard SAVE the frame size of 0 means 128. */ | |
1981 | frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf); | |
1982 | if (frame_size == 0 && (save_inst >> 16) == 0) | |
1983 | frame_size = 16; | |
1984 | frame_size *= 8; | |
1985 | frame_offset += frame_size; | |
1986 | ||
1987 | /* Now we can calculate what the SP must have been at the | |
1988 | start of the function prologue. */ | |
1989 | sp += frame_offset; | |
1990 | ||
1991 | /* Check if A0-A3 were saved in the caller's argument save area. */ | |
1992 | for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++) | |
1993 | { | |
74ed0bb4 | 1994 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1995 | offset += mips_abi_regsize (gdbarch); |
1996 | } | |
1997 | ||
1998 | offset = -4; | |
1999 | ||
2000 | /* Check if the RA register was pushed on the stack. */ | |
2001 | if (save_inst & 0x40) | |
2002 | { | |
74ed0bb4 | 2003 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
2207132d MR |
2004 | offset -= mips_abi_regsize (gdbarch); |
2005 | } | |
2006 | ||
2007 | /* Check if the S8 register was pushed on the stack. */ | |
2008 | if (xsregs > 6) | |
2009 | { | |
74ed0bb4 | 2010 | set_reg_offset (gdbarch, this_cache, 30, sp + offset); |
2207132d MR |
2011 | offset -= mips_abi_regsize (gdbarch); |
2012 | xsregs--; | |
2013 | } | |
2014 | /* Check if S2-S7 were pushed on the stack. */ | |
2015 | for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--) | |
2016 | { | |
74ed0bb4 | 2017 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
2018 | offset -= mips_abi_regsize (gdbarch); |
2019 | } | |
2020 | ||
2021 | /* Check if the S1 register was pushed on the stack. */ | |
2022 | if (save_inst & 0x10) | |
2023 | { | |
74ed0bb4 | 2024 | set_reg_offset (gdbarch, this_cache, 17, sp + offset); |
2207132d MR |
2025 | offset -= mips_abi_regsize (gdbarch); |
2026 | } | |
2027 | /* Check if the S0 register was pushed on the stack. */ | |
2028 | if (save_inst & 0x20) | |
2029 | { | |
74ed0bb4 | 2030 | set_reg_offset (gdbarch, this_cache, 16, sp + offset); |
2207132d MR |
2031 | offset -= mips_abi_regsize (gdbarch); |
2032 | } | |
2033 | ||
2034 | /* Check if A0-A3 were pushed on the stack. */ | |
2035 | for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--) | |
2036 | { | |
74ed0bb4 | 2037 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
2038 | offset -= mips_abi_regsize (gdbarch); |
2039 | } | |
2040 | } | |
2041 | ||
29639122 JB |
2042 | if (this_cache != NULL) |
2043 | { | |
2044 | this_cache->base = | |
b8a22b94 DJ |
2045 | (get_frame_register_signed (this_frame, |
2046 | gdbarch_num_regs (gdbarch) + frame_reg) | |
29639122 JB |
2047 | + frame_offset - frame_adjust); |
2048 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should | |
025bb325 | 2049 | be able to get rid of the assignment below, evetually. But it's |
29639122 | 2050 | still needed for now. */ |
72a155b4 UW |
2051 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
2052 | + mips_regnum (gdbarch)->pc] | |
2053 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; | |
29639122 JB |
2054 | } |
2055 | ||
2056 | /* If we didn't reach the end of the prologue when scanning the function | |
2057 | instructions, then set end_prologue_addr to the address of the | |
2058 | instruction immediately after the last one we scanned. */ | |
2059 | if (end_prologue_addr == 0) | |
2060 | end_prologue_addr = cur_pc; | |
2061 | ||
2062 | return end_prologue_addr; | |
eec63939 AC |
2063 | } |
2064 | ||
29639122 JB |
2065 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). |
2066 | Procedures that use the 32-bit instruction set are handled by the | |
2067 | mips_insn32 unwinder. */ | |
2068 | ||
2069 | static struct mips_frame_cache * | |
b8a22b94 | 2070 | mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache) |
eec63939 | 2071 | { |
e17a4113 | 2072 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 2073 | struct mips_frame_cache *cache; |
eec63939 AC |
2074 | |
2075 | if ((*this_cache) != NULL) | |
2076 | return (*this_cache); | |
29639122 JB |
2077 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
2078 | (*this_cache) = cache; | |
b8a22b94 | 2079 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
eec63939 | 2080 | |
29639122 JB |
2081 | /* Analyze the function prologue. */ |
2082 | { | |
b8a22b94 | 2083 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 2084 | CORE_ADDR start_addr; |
eec63939 | 2085 | |
29639122 JB |
2086 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
2087 | if (start_addr == 0) | |
e17a4113 | 2088 | start_addr = heuristic_proc_start (gdbarch, pc); |
29639122 JB |
2089 | /* We can't analyze the prologue if we couldn't find the begining |
2090 | of the function. */ | |
2091 | if (start_addr == 0) | |
2092 | return cache; | |
eec63939 | 2093 | |
e17a4113 | 2094 | mips16_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); |
29639122 JB |
2095 | } |
2096 | ||
3e8c568d | 2097 | /* gdbarch_sp_regnum contains the value and not the address. */ |
72a155b4 | 2098 | trad_frame_set_value (cache->saved_regs, |
e17a4113 | 2099 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
72a155b4 | 2100 | cache->base); |
eec63939 | 2101 | |
29639122 | 2102 | return (*this_cache); |
eec63939 AC |
2103 | } |
2104 | ||
2105 | static void | |
b8a22b94 | 2106 | mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 | 2107 | struct frame_id *this_id) |
eec63939 | 2108 | { |
b8a22b94 | 2109 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 | 2110 | this_cache); |
21327321 DJ |
2111 | /* This marks the outermost frame. */ |
2112 | if (info->base == 0) | |
2113 | return; | |
b8a22b94 | 2114 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
eec63939 AC |
2115 | } |
2116 | ||
b8a22b94 DJ |
2117 | static struct value * |
2118 | mips_insn16_frame_prev_register (struct frame_info *this_frame, | |
2119 | void **this_cache, int regnum) | |
eec63939 | 2120 | { |
b8a22b94 | 2121 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 | 2122 | this_cache); |
b8a22b94 DJ |
2123 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
2124 | } | |
2125 | ||
2126 | static int | |
2127 | mips_insn16_frame_sniffer (const struct frame_unwind *self, | |
2128 | struct frame_info *this_frame, void **this_cache) | |
2129 | { | |
2130 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2131 | if (mips_pc_is_mips16 (pc)) | |
2132 | return 1; | |
2133 | return 0; | |
eec63939 AC |
2134 | } |
2135 | ||
29639122 | 2136 | static const struct frame_unwind mips_insn16_frame_unwind = |
eec63939 AC |
2137 | { |
2138 | NORMAL_FRAME, | |
8fbca658 | 2139 | default_frame_unwind_stop_reason, |
29639122 | 2140 | mips_insn16_frame_this_id, |
b8a22b94 DJ |
2141 | mips_insn16_frame_prev_register, |
2142 | NULL, | |
2143 | mips_insn16_frame_sniffer | |
eec63939 AC |
2144 | }; |
2145 | ||
eec63939 | 2146 | static CORE_ADDR |
b8a22b94 | 2147 | mips_insn16_frame_base_address (struct frame_info *this_frame, |
29639122 | 2148 | void **this_cache) |
eec63939 | 2149 | { |
b8a22b94 | 2150 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 JB |
2151 | this_cache); |
2152 | return info->base; | |
eec63939 AC |
2153 | } |
2154 | ||
29639122 | 2155 | static const struct frame_base mips_insn16_frame_base = |
eec63939 | 2156 | { |
29639122 JB |
2157 | &mips_insn16_frame_unwind, |
2158 | mips_insn16_frame_base_address, | |
2159 | mips_insn16_frame_base_address, | |
2160 | mips_insn16_frame_base_address | |
eec63939 AC |
2161 | }; |
2162 | ||
2163 | static const struct frame_base * | |
b8a22b94 | 2164 | mips_insn16_frame_base_sniffer (struct frame_info *this_frame) |
eec63939 | 2165 | { |
b8a22b94 DJ |
2166 | CORE_ADDR pc = get_frame_pc (this_frame); |
2167 | if (mips_pc_is_mips16 (pc)) | |
29639122 | 2168 | return &mips_insn16_frame_base; |
eec63939 AC |
2169 | else |
2170 | return NULL; | |
edfae063 AC |
2171 | } |
2172 | ||
29639122 JB |
2173 | /* Mark all the registers as unset in the saved_regs array |
2174 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
2175 | ||
74ed0bb4 MD |
2176 | static void |
2177 | reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache) | |
c906108c | 2178 | { |
29639122 JB |
2179 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
2180 | return; | |
2181 | ||
2182 | { | |
74ed0bb4 | 2183 | const int num_regs = gdbarch_num_regs (gdbarch); |
29639122 | 2184 | int i; |
64159455 | 2185 | |
29639122 JB |
2186 | for (i = 0; i < num_regs; i++) |
2187 | { | |
2188 | this_cache->saved_regs[i].addr = -1; | |
2189 | } | |
2190 | } | |
c906108c SS |
2191 | } |
2192 | ||
025bb325 | 2193 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
29639122 JB |
2194 | the associated FRAME_CACHE if not null. |
2195 | Return the address of the first instruction past the prologue. */ | |
c906108c | 2196 | |
875e1767 | 2197 | static CORE_ADDR |
e17a4113 UW |
2198 | mips32_scan_prologue (struct gdbarch *gdbarch, |
2199 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 2200 | struct frame_info *this_frame, |
29639122 | 2201 | struct mips_frame_cache *this_cache) |
c906108c | 2202 | { |
29639122 | 2203 | CORE_ADDR cur_pc; |
025bb325 MS |
2204 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for |
2205 | frame-pointer. */ | |
29639122 JB |
2206 | CORE_ADDR sp; |
2207 | long frame_offset; | |
2208 | int frame_reg = MIPS_SP_REGNUM; | |
8fa9cfa1 | 2209 | |
29639122 JB |
2210 | CORE_ADDR end_prologue_addr = 0; |
2211 | int seen_sp_adjust = 0; | |
2212 | int load_immediate_bytes = 0; | |
db5f024e | 2213 | int in_delay_slot = 0; |
7d1e6fb8 | 2214 | int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8); |
8fa9cfa1 | 2215 | |
29639122 | 2216 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
2217 | THIS_FRAME. */ |
2218 | if (this_frame != NULL) | |
2219 | sp = get_frame_register_signed (this_frame, | |
2220 | gdbarch_num_regs (gdbarch) | |
2221 | + MIPS_SP_REGNUM); | |
8fa9cfa1 | 2222 | else |
29639122 | 2223 | sp = 0; |
9022177c | 2224 | |
29639122 JB |
2225 | if (limit_pc > start_pc + 200) |
2226 | limit_pc = start_pc + 200; | |
9022177c | 2227 | |
29639122 | 2228 | restart: |
9022177c | 2229 | |
29639122 | 2230 | frame_offset = 0; |
95ac2dcf | 2231 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) |
9022177c | 2232 | { |
29639122 JB |
2233 | unsigned long inst, high_word, low_word; |
2234 | int reg; | |
9022177c | 2235 | |
025bb325 | 2236 | /* Fetch the instruction. */ |
e17a4113 | 2237 | inst = (unsigned long) mips_fetch_instruction (gdbarch, cur_pc); |
9022177c | 2238 | |
29639122 JB |
2239 | /* Save some code by pre-extracting some useful fields. */ |
2240 | high_word = (inst >> 16) & 0xffff; | |
2241 | low_word = inst & 0xffff; | |
2242 | reg = high_word & 0x1f; | |
fe29b929 | 2243 | |
025bb325 | 2244 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
29639122 JB |
2245 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
2246 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
2247 | { | |
025bb325 | 2248 | if (low_word & 0x8000) /* Negative stack adjustment? */ |
29639122 JB |
2249 | frame_offset += 0x10000 - low_word; |
2250 | else | |
2251 | /* Exit loop if a positive stack adjustment is found, which | |
2252 | usually means that the stack cleanup code in the function | |
2253 | epilogue is reached. */ | |
2254 | break; | |
2255 | seen_sp_adjust = 1; | |
2256 | } | |
7d1e6fb8 KB |
2257 | else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ |
2258 | && !regsize_is_64_bits) | |
29639122 | 2259 | { |
74ed0bb4 | 2260 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
29639122 | 2261 | } |
7d1e6fb8 KB |
2262 | else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ |
2263 | && regsize_is_64_bits) | |
29639122 JB |
2264 | { |
2265 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ | |
74ed0bb4 | 2266 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
29639122 JB |
2267 | } |
2268 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
2269 | { | |
2270 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
2271 | if ((long) low_word != frame_offset) | |
2272 | frame_addr = sp + low_word; | |
b8a22b94 | 2273 | else if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
2274 | { |
2275 | unsigned alloca_adjust; | |
a4b8ebc8 | 2276 | |
29639122 | 2277 | frame_reg = 30; |
b8a22b94 DJ |
2278 | frame_addr = get_frame_register_signed |
2279 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 2280 | |
29639122 JB |
2281 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
2282 | if (alloca_adjust > 0) | |
2283 | { | |
025bb325 | 2284 | /* FP > SP + frame_size. This may be because of |
29639122 JB |
2285 | an alloca or somethings similar. Fix sp to |
2286 | "pre-alloca" value, and try again. */ | |
2287 | sp += alloca_adjust; | |
2288 | /* Need to reset the status of all registers. Otherwise, | |
2289 | we will hit a guard that prevents the new address | |
2290 | for each register to be recomputed during the second | |
2291 | pass. */ | |
74ed0bb4 | 2292 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
2293 | goto restart; |
2294 | } | |
2295 | } | |
2296 | } | |
2297 | /* move $30,$sp. With different versions of gas this will be either | |
2298 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
2299 | Accept any one of these. */ | |
2300 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
2301 | { | |
2302 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
b8a22b94 | 2303 | if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
2304 | { |
2305 | unsigned alloca_adjust; | |
c906108c | 2306 | |
29639122 | 2307 | frame_reg = 30; |
b8a22b94 DJ |
2308 | frame_addr = get_frame_register_signed |
2309 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 2310 | |
29639122 JB |
2311 | alloca_adjust = (unsigned) (frame_addr - sp); |
2312 | if (alloca_adjust > 0) | |
2313 | { | |
025bb325 | 2314 | /* FP > SP + frame_size. This may be because of |
29639122 JB |
2315 | an alloca or somethings similar. Fix sp to |
2316 | "pre-alloca" value, and try again. */ | |
2317 | sp = frame_addr; | |
2318 | /* Need to reset the status of all registers. Otherwise, | |
2319 | we will hit a guard that prevents the new address | |
2320 | for each register to be recomputed during the second | |
2321 | pass. */ | |
74ed0bb4 | 2322 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
2323 | goto restart; |
2324 | } | |
2325 | } | |
2326 | } | |
7d1e6fb8 KB |
2327 | else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */ |
2328 | && !regsize_is_64_bits) | |
29639122 | 2329 | { |
74ed0bb4 | 2330 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + low_word); |
29639122 JB |
2331 | } |
2332 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | |
2333 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ | |
2334 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | |
2335 | || high_word == 0x3c1c /* lui $gp,n */ | |
2336 | || high_word == 0x279c /* addiu $gp,$gp,n */ | |
2337 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
2338 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | |
2339 | ) | |
19080931 MR |
2340 | { |
2341 | /* These instructions are part of the prologue, but we don't | |
2342 | need to do anything special to handle them. */ | |
2343 | } | |
29639122 JB |
2344 | /* The instructions below load $at or $t0 with an immediate |
2345 | value in preparation for a stack adjustment via | |
025bb325 | 2346 | subu $sp,$sp,[$at,$t0]. These instructions could also |
29639122 JB |
2347 | initialize a local variable, so we accept them only before |
2348 | a stack adjustment instruction was seen. */ | |
2349 | else if (!seen_sp_adjust | |
19080931 MR |
2350 | && (high_word == 0x3c01 /* lui $at,n */ |
2351 | || high_word == 0x3c08 /* lui $t0,n */ | |
2352 | || high_word == 0x3421 /* ori $at,$at,n */ | |
2353 | || high_word == 0x3508 /* ori $t0,$t0,n */ | |
2354 | || high_word == 0x3401 /* ori $at,$zero,n */ | |
2355 | || high_word == 0x3408 /* ori $t0,$zero,n */ | |
2356 | )) | |
2357 | { | |
2358 | if (end_prologue_addr == 0) | |
2359 | load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ | |
2360 | } | |
29639122 | 2361 | else |
19080931 MR |
2362 | { |
2363 | /* This instruction is not an instruction typically found | |
2364 | in a prologue, so we must have reached the end of the | |
2365 | prologue. */ | |
2366 | /* FIXME: brobecker/2004-10-10: Can't we just break out of this | |
2367 | loop now? Why would we need to continue scanning the function | |
2368 | instructions? */ | |
2369 | if (end_prologue_addr == 0) | |
2370 | end_prologue_addr = cur_pc; | |
2371 | ||
2372 | /* Check for branches and jumps. For now, only jump to | |
2373 | register are caught (i.e. returns). */ | |
2374 | if ((itype_op (inst) & 0x07) == 0 && rtype_funct (inst) == 8) | |
2375 | in_delay_slot = 1; | |
2376 | } | |
db5f024e DJ |
2377 | |
2378 | /* If the previous instruction was a jump, we must have reached | |
2379 | the end of the prologue by now. Stop scanning so that we do | |
2380 | not go past the function return. */ | |
2381 | if (in_delay_slot) | |
2382 | break; | |
a4b8ebc8 | 2383 | } |
c906108c | 2384 | |
29639122 JB |
2385 | if (this_cache != NULL) |
2386 | { | |
2387 | this_cache->base = | |
b8a22b94 DJ |
2388 | (get_frame_register_signed (this_frame, |
2389 | gdbarch_num_regs (gdbarch) + frame_reg) | |
29639122 JB |
2390 | + frame_offset); |
2391 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of | |
2392 | this assignment below, eventually. But it's still needed | |
2393 | for now. */ | |
72a155b4 UW |
2394 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
2395 | + mips_regnum (gdbarch)->pc] | |
2396 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) | |
f57d151a | 2397 | + MIPS_RA_REGNUM]; |
29639122 | 2398 | } |
c906108c | 2399 | |
29639122 JB |
2400 | /* If we didn't reach the end of the prologue when scanning the function |
2401 | instructions, then set end_prologue_addr to the address of the | |
2402 | instruction immediately after the last one we scanned. */ | |
2403 | /* brobecker/2004-10-10: I don't think this would ever happen, but | |
2404 | we may as well be careful and do our best if we have a null | |
2405 | end_prologue_addr. */ | |
2406 | if (end_prologue_addr == 0) | |
2407 | end_prologue_addr = cur_pc; | |
2408 | ||
2409 | /* In a frameless function, we might have incorrectly | |
025bb325 | 2410 | skipped some load immediate instructions. Undo the skipping |
29639122 JB |
2411 | if the load immediate was not followed by a stack adjustment. */ |
2412 | if (load_immediate_bytes && !seen_sp_adjust) | |
2413 | end_prologue_addr -= load_immediate_bytes; | |
c906108c | 2414 | |
29639122 | 2415 | return end_prologue_addr; |
c906108c SS |
2416 | } |
2417 | ||
29639122 JB |
2418 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
2419 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
2420 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
2421 | unwinder. */ | |
c906108c | 2422 | |
29639122 | 2423 | static struct mips_frame_cache * |
b8a22b94 | 2424 | mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache) |
c906108c | 2425 | { |
e17a4113 | 2426 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 2427 | struct mips_frame_cache *cache; |
c906108c | 2428 | |
29639122 JB |
2429 | if ((*this_cache) != NULL) |
2430 | return (*this_cache); | |
c5aa993b | 2431 | |
29639122 JB |
2432 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
2433 | (*this_cache) = cache; | |
b8a22b94 | 2434 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
c5aa993b | 2435 | |
29639122 JB |
2436 | /* Analyze the function prologue. */ |
2437 | { | |
b8a22b94 | 2438 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 2439 | CORE_ADDR start_addr; |
c906108c | 2440 | |
29639122 JB |
2441 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
2442 | if (start_addr == 0) | |
e17a4113 | 2443 | start_addr = heuristic_proc_start (gdbarch, pc); |
29639122 JB |
2444 | /* We can't analyze the prologue if we couldn't find the begining |
2445 | of the function. */ | |
2446 | if (start_addr == 0) | |
2447 | return cache; | |
c5aa993b | 2448 | |
e17a4113 | 2449 | mips32_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); |
29639122 JB |
2450 | } |
2451 | ||
3e8c568d | 2452 | /* gdbarch_sp_regnum contains the value and not the address. */ |
f57d151a | 2453 | trad_frame_set_value (cache->saved_regs, |
e17a4113 | 2454 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
f57d151a | 2455 | cache->base); |
c5aa993b | 2456 | |
29639122 | 2457 | return (*this_cache); |
c906108c SS |
2458 | } |
2459 | ||
29639122 | 2460 | static void |
b8a22b94 | 2461 | mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 | 2462 | struct frame_id *this_id) |
c906108c | 2463 | { |
b8a22b94 | 2464 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 2465 | this_cache); |
21327321 DJ |
2466 | /* This marks the outermost frame. */ |
2467 | if (info->base == 0) | |
2468 | return; | |
b8a22b94 | 2469 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
29639122 | 2470 | } |
c906108c | 2471 | |
b8a22b94 DJ |
2472 | static struct value * |
2473 | mips_insn32_frame_prev_register (struct frame_info *this_frame, | |
2474 | void **this_cache, int regnum) | |
29639122 | 2475 | { |
b8a22b94 | 2476 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 2477 | this_cache); |
b8a22b94 DJ |
2478 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
2479 | } | |
2480 | ||
2481 | static int | |
2482 | mips_insn32_frame_sniffer (const struct frame_unwind *self, | |
2483 | struct frame_info *this_frame, void **this_cache) | |
2484 | { | |
2485 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2486 | if (! mips_pc_is_mips16 (pc)) | |
2487 | return 1; | |
2488 | return 0; | |
c906108c SS |
2489 | } |
2490 | ||
29639122 JB |
2491 | static const struct frame_unwind mips_insn32_frame_unwind = |
2492 | { | |
2493 | NORMAL_FRAME, | |
8fbca658 | 2494 | default_frame_unwind_stop_reason, |
29639122 | 2495 | mips_insn32_frame_this_id, |
b8a22b94 DJ |
2496 | mips_insn32_frame_prev_register, |
2497 | NULL, | |
2498 | mips_insn32_frame_sniffer | |
29639122 | 2499 | }; |
c906108c | 2500 | |
1c645fec | 2501 | static CORE_ADDR |
b8a22b94 | 2502 | mips_insn32_frame_base_address (struct frame_info *this_frame, |
29639122 | 2503 | void **this_cache) |
c906108c | 2504 | { |
b8a22b94 | 2505 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 JB |
2506 | this_cache); |
2507 | return info->base; | |
2508 | } | |
c906108c | 2509 | |
29639122 JB |
2510 | static const struct frame_base mips_insn32_frame_base = |
2511 | { | |
2512 | &mips_insn32_frame_unwind, | |
2513 | mips_insn32_frame_base_address, | |
2514 | mips_insn32_frame_base_address, | |
2515 | mips_insn32_frame_base_address | |
2516 | }; | |
1c645fec | 2517 | |
29639122 | 2518 | static const struct frame_base * |
b8a22b94 | 2519 | mips_insn32_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 2520 | { |
b8a22b94 DJ |
2521 | CORE_ADDR pc = get_frame_pc (this_frame); |
2522 | if (! mips_pc_is_mips16 (pc)) | |
29639122 | 2523 | return &mips_insn32_frame_base; |
a65bbe44 | 2524 | else |
29639122 JB |
2525 | return NULL; |
2526 | } | |
a65bbe44 | 2527 | |
29639122 | 2528 | static struct trad_frame_cache * |
b8a22b94 | 2529 | mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache) |
29639122 JB |
2530 | { |
2531 | CORE_ADDR pc; | |
2532 | CORE_ADDR start_addr; | |
2533 | CORE_ADDR stack_addr; | |
2534 | struct trad_frame_cache *this_trad_cache; | |
b8a22b94 DJ |
2535 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2536 | int num_regs = gdbarch_num_regs (gdbarch); | |
c906108c | 2537 | |
29639122 JB |
2538 | if ((*this_cache) != NULL) |
2539 | return (*this_cache); | |
b8a22b94 | 2540 | this_trad_cache = trad_frame_cache_zalloc (this_frame); |
29639122 | 2541 | (*this_cache) = this_trad_cache; |
1c645fec | 2542 | |
29639122 | 2543 | /* The return address is in the link register. */ |
3e8c568d | 2544 | trad_frame_set_reg_realreg (this_trad_cache, |
72a155b4 | 2545 | gdbarch_pc_regnum (gdbarch), |
b8a22b94 | 2546 | num_regs + MIPS_RA_REGNUM); |
1c645fec | 2547 | |
29639122 JB |
2548 | /* Frame ID, since it's a frameless / stackless function, no stack |
2549 | space is allocated and SP on entry is the current SP. */ | |
b8a22b94 | 2550 | pc = get_frame_pc (this_frame); |
29639122 | 2551 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
b8a22b94 DJ |
2552 | stack_addr = get_frame_register_signed (this_frame, |
2553 | num_regs + MIPS_SP_REGNUM); | |
aa6c981f | 2554 | trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr)); |
1c645fec | 2555 | |
29639122 JB |
2556 | /* Assume that the frame's base is the same as the |
2557 | stack-pointer. */ | |
2558 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
c906108c | 2559 | |
29639122 JB |
2560 | return this_trad_cache; |
2561 | } | |
c906108c | 2562 | |
29639122 | 2563 | static void |
b8a22b94 | 2564 | mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 JB |
2565 | struct frame_id *this_id) |
2566 | { | |
2567 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 2568 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
2569 | trad_frame_get_id (this_trad_cache, this_id); |
2570 | } | |
c906108c | 2571 | |
b8a22b94 DJ |
2572 | static struct value * |
2573 | mips_stub_frame_prev_register (struct frame_info *this_frame, | |
2574 | void **this_cache, int regnum) | |
29639122 JB |
2575 | { |
2576 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 DJ |
2577 | = mips_stub_frame_cache (this_frame, this_cache); |
2578 | return trad_frame_get_register (this_trad_cache, this_frame, regnum); | |
29639122 | 2579 | } |
c906108c | 2580 | |
b8a22b94 DJ |
2581 | static int |
2582 | mips_stub_frame_sniffer (const struct frame_unwind *self, | |
2583 | struct frame_info *this_frame, void **this_cache) | |
29639122 | 2584 | { |
aa6c981f | 2585 | gdb_byte dummy[4]; |
979b38e0 | 2586 | struct obj_section *s; |
b8a22b94 | 2587 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
db5f024e | 2588 | struct minimal_symbol *msym; |
979b38e0 | 2589 | |
aa6c981f | 2590 | /* Use the stub unwinder for unreadable code. */ |
b8a22b94 DJ |
2591 | if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) |
2592 | return 1; | |
aa6c981f | 2593 | |
29639122 | 2594 | if (in_plt_section (pc, NULL)) |
b8a22b94 | 2595 | return 1; |
979b38e0 DJ |
2596 | |
2597 | /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */ | |
2598 | s = find_pc_section (pc); | |
2599 | ||
2600 | if (s != NULL | |
2601 | && strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section), | |
2602 | ".MIPS.stubs") == 0) | |
b8a22b94 | 2603 | return 1; |
979b38e0 | 2604 | |
db5f024e DJ |
2605 | /* Calling a PIC function from a non-PIC function passes through a |
2606 | stub. The stub for foo is named ".pic.foo". */ | |
2607 | msym = lookup_minimal_symbol_by_pc (pc); | |
2608 | if (msym != NULL | |
2609 | && SYMBOL_LINKAGE_NAME (msym) != NULL | |
2610 | && strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) == 0) | |
2611 | return 1; | |
2612 | ||
b8a22b94 | 2613 | return 0; |
29639122 | 2614 | } |
c906108c | 2615 | |
b8a22b94 DJ |
2616 | static const struct frame_unwind mips_stub_frame_unwind = |
2617 | { | |
2618 | NORMAL_FRAME, | |
8fbca658 | 2619 | default_frame_unwind_stop_reason, |
b8a22b94 DJ |
2620 | mips_stub_frame_this_id, |
2621 | mips_stub_frame_prev_register, | |
2622 | NULL, | |
2623 | mips_stub_frame_sniffer | |
2624 | }; | |
2625 | ||
29639122 | 2626 | static CORE_ADDR |
b8a22b94 | 2627 | mips_stub_frame_base_address (struct frame_info *this_frame, |
29639122 JB |
2628 | void **this_cache) |
2629 | { | |
2630 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 2631 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
2632 | return trad_frame_get_this_base (this_trad_cache); |
2633 | } | |
0fce0821 | 2634 | |
29639122 JB |
2635 | static const struct frame_base mips_stub_frame_base = |
2636 | { | |
2637 | &mips_stub_frame_unwind, | |
2638 | mips_stub_frame_base_address, | |
2639 | mips_stub_frame_base_address, | |
2640 | mips_stub_frame_base_address | |
2641 | }; | |
2642 | ||
2643 | static const struct frame_base * | |
b8a22b94 | 2644 | mips_stub_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 2645 | { |
b8a22b94 | 2646 | if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL)) |
29639122 JB |
2647 | return &mips_stub_frame_base; |
2648 | else | |
2649 | return NULL; | |
2650 | } | |
2651 | ||
29639122 | 2652 | /* mips_addr_bits_remove - remove useless address bits */ |
65596487 | 2653 | |
29639122 | 2654 | static CORE_ADDR |
24568a2c | 2655 | mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) |
65596487 | 2656 | { |
24568a2c | 2657 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
930bd0e0 KB |
2658 | |
2659 | if (is_mips16_addr (addr)) | |
2660 | addr = unmake_mips16_addr (addr); | |
2661 | ||
29639122 JB |
2662 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) |
2663 | /* This hack is a work-around for existing boards using PMON, the | |
2664 | simulator, and any other 64-bit targets that doesn't have true | |
2665 | 64-bit addressing. On these targets, the upper 32 bits of | |
2666 | addresses are ignored by the hardware. Thus, the PC or SP are | |
2667 | likely to have been sign extended to all 1s by instruction | |
2668 | sequences that load 32-bit addresses. For example, a typical | |
2669 | piece of code that loads an address is this: | |
65596487 | 2670 | |
29639122 JB |
2671 | lui $r2, <upper 16 bits> |
2672 | ori $r2, <lower 16 bits> | |
65596487 | 2673 | |
29639122 JB |
2674 | But the lui sign-extends the value such that the upper 32 bits |
2675 | may be all 1s. The workaround is simply to mask off these | |
2676 | bits. In the future, gcc may be changed to support true 64-bit | |
2677 | addressing, and this masking will have to be disabled. */ | |
2678 | return addr &= 0xffffffffUL; | |
2679 | else | |
2680 | return addr; | |
65596487 JB |
2681 | } |
2682 | ||
3d5f6d12 DJ |
2683 | /* Instructions used during single-stepping of atomic sequences. */ |
2684 | #define LL_OPCODE 0x30 | |
2685 | #define LLD_OPCODE 0x34 | |
2686 | #define SC_OPCODE 0x38 | |
2687 | #define SCD_OPCODE 0x3c | |
2688 | ||
2689 | /* Checks for an atomic sequence of instructions beginning with a LL/LLD | |
2690 | instruction and ending with a SC/SCD instruction. If such a sequence | |
2691 | is found, attempt to step through it. A breakpoint is placed at the end of | |
2692 | the sequence. */ | |
2693 | ||
2694 | static int | |
6c95b8df PA |
2695 | deal_with_atomic_sequence (struct gdbarch *gdbarch, |
2696 | struct address_space *aspace, CORE_ADDR pc) | |
3d5f6d12 DJ |
2697 | { |
2698 | CORE_ADDR breaks[2] = {-1, -1}; | |
2699 | CORE_ADDR loc = pc; | |
2700 | CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ | |
2701 | unsigned long insn; | |
2702 | int insn_count; | |
2703 | int index; | |
2704 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
2705 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
2706 | ||
2707 | if (pc & 0x01) | |
2708 | return 0; | |
2709 | ||
e17a4113 | 2710 | insn = mips_fetch_instruction (gdbarch, loc); |
3d5f6d12 DJ |
2711 | /* Assume all atomic sequences start with a ll/lld instruction. */ |
2712 | if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE) | |
2713 | return 0; | |
2714 | ||
2715 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" | |
2716 | instructions. */ | |
2717 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
2718 | { | |
2719 | int is_branch = 0; | |
2720 | loc += MIPS_INSN32_SIZE; | |
e17a4113 | 2721 | insn = mips_fetch_instruction (gdbarch, loc); |
3d5f6d12 DJ |
2722 | |
2723 | /* Assume that there is at most one branch in the atomic | |
2724 | sequence. If a branch is found, put a breakpoint in its | |
2725 | destination address. */ | |
2726 | switch (itype_op (insn)) | |
2727 | { | |
2728 | case 0: /* SPECIAL */ | |
2729 | if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */ | |
025bb325 | 2730 | return 0; /* fallback to the standard single-step code. */ |
3d5f6d12 DJ |
2731 | break; |
2732 | case 1: /* REGIMM */ | |
a385295e MR |
2733 | is_branch = ((itype_rt (insn) & 0xc) == 0 /* B{LT,GE}Z* */ |
2734 | || ((itype_rt (insn) & 0x1e) == 0 | |
2735 | && itype_rs (insn) == 0)); /* BPOSGE* */ | |
3d5f6d12 DJ |
2736 | break; |
2737 | case 2: /* J */ | |
2738 | case 3: /* JAL */ | |
025bb325 | 2739 | return 0; /* fallback to the standard single-step code. */ |
3d5f6d12 DJ |
2740 | case 4: /* BEQ */ |
2741 | case 5: /* BNE */ | |
2742 | case 6: /* BLEZ */ | |
2743 | case 7: /* BGTZ */ | |
2744 | case 20: /* BEQL */ | |
2745 | case 21: /* BNEL */ | |
2746 | case 22: /* BLEZL */ | |
2747 | case 23: /* BGTTL */ | |
2748 | is_branch = 1; | |
2749 | break; | |
2750 | case 17: /* COP1 */ | |
a385295e MR |
2751 | is_branch = ((itype_rs (insn) == 9 || itype_rs (insn) == 10) |
2752 | && (itype_rt (insn) & 0x2) == 0); | |
2753 | if (is_branch) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */ | |
2754 | break; | |
2755 | /* Fall through. */ | |
3d5f6d12 DJ |
2756 | case 18: /* COP2 */ |
2757 | case 19: /* COP3 */ | |
2758 | is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */ | |
2759 | break; | |
2760 | } | |
2761 | if (is_branch) | |
2762 | { | |
2763 | branch_bp = loc + mips32_relative_offset (insn) + 4; | |
2764 | if (last_breakpoint >= 1) | |
2765 | return 0; /* More than one branch found, fallback to the | |
2766 | standard single-step code. */ | |
2767 | breaks[1] = branch_bp; | |
2768 | last_breakpoint++; | |
2769 | } | |
2770 | ||
2771 | if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE) | |
2772 | break; | |
2773 | } | |
2774 | ||
2775 | /* Assume that the atomic sequence ends with a sc/scd instruction. */ | |
2776 | if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE) | |
2777 | return 0; | |
2778 | ||
2779 | loc += MIPS_INSN32_SIZE; | |
2780 | ||
2781 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
2782 | breaks[0] = loc; | |
2783 | ||
2784 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
025bb325 | 2785 | placed (branch instruction's destination) in the atomic sequence. */ |
3d5f6d12 DJ |
2786 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) |
2787 | last_breakpoint = 0; | |
2788 | ||
2789 | /* Effectively inserts the breakpoints. */ | |
2790 | for (index = 0; index <= last_breakpoint; index++) | |
6c95b8df | 2791 | insert_single_step_breakpoint (gdbarch, aspace, breaks[index]); |
3d5f6d12 DJ |
2792 | |
2793 | return 1; | |
2794 | } | |
2795 | ||
29639122 JB |
2796 | /* mips_software_single_step() is called just before we want to resume |
2797 | the inferior, if we want to single-step it but there is no hardware | |
2798 | or kernel single-step support (MIPS on GNU/Linux for example). We find | |
e0cd558a | 2799 | the target of the coming instruction and breakpoint it. */ |
29639122 | 2800 | |
e6590a1b | 2801 | int |
0b1b3e42 | 2802 | mips_software_single_step (struct frame_info *frame) |
c906108c | 2803 | { |
a6d9a66e | 2804 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6c95b8df | 2805 | struct address_space *aspace = get_frame_address_space (frame); |
8181d85f | 2806 | CORE_ADDR pc, next_pc; |
65596487 | 2807 | |
0b1b3e42 | 2808 | pc = get_frame_pc (frame); |
6c95b8df | 2809 | if (deal_with_atomic_sequence (gdbarch, aspace, pc)) |
3d5f6d12 DJ |
2810 | return 1; |
2811 | ||
0b1b3e42 | 2812 | next_pc = mips_next_pc (frame, pc); |
e6590a1b | 2813 | |
6c95b8df | 2814 | insert_single_step_breakpoint (gdbarch, aspace, next_pc); |
e6590a1b | 2815 | return 1; |
29639122 | 2816 | } |
a65bbe44 | 2817 | |
29639122 | 2818 | /* Test whether the PC points to the return instruction at the |
025bb325 | 2819 | end of a function. */ |
65596487 | 2820 | |
29639122 | 2821 | static int |
e17a4113 | 2822 | mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 | 2823 | { |
6321c22a MR |
2824 | ULONGEST insn; |
2825 | ULONGEST hint; | |
2826 | ||
2827 | /* This used to check for MIPS16, but this piece of code is never | |
2828 | called for MIPS16 functions. */ | |
2829 | gdb_assert (!mips_pc_is_mips16 (pc)); | |
2830 | ||
2831 | insn = mips_fetch_instruction (gdbarch, pc); | |
2832 | hint = 0x7c0; | |
2833 | return (insn & ~hint) == 0x3e00008; /* jr(.hb) $ra */ | |
29639122 | 2834 | } |
c906108c | 2835 | |
c906108c | 2836 | |
29639122 JB |
2837 | /* This fencepost looks highly suspicious to me. Removing it also |
2838 | seems suspicious as it could affect remote debugging across serial | |
2839 | lines. */ | |
c906108c | 2840 | |
29639122 | 2841 | static CORE_ADDR |
74ed0bb4 | 2842 | heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 JB |
2843 | { |
2844 | CORE_ADDR start_pc; | |
2845 | CORE_ADDR fence; | |
2846 | int instlen; | |
2847 | int seen_adjsp = 0; | |
d6b48e9c | 2848 | struct inferior *inf; |
65596487 | 2849 | |
74ed0bb4 | 2850 | pc = gdbarch_addr_bits_remove (gdbarch, pc); |
29639122 JB |
2851 | start_pc = pc; |
2852 | fence = start_pc - heuristic_fence_post; | |
2853 | if (start_pc == 0) | |
2854 | return 0; | |
65596487 | 2855 | |
29639122 JB |
2856 | if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
2857 | fence = VM_MIN_ADDRESS; | |
65596487 | 2858 | |
95ac2dcf | 2859 | instlen = mips_pc_is_mips16 (pc) ? MIPS_INSN16_SIZE : MIPS_INSN32_SIZE; |
98b4dd94 | 2860 | |
d6b48e9c PA |
2861 | inf = current_inferior (); |
2862 | ||
025bb325 | 2863 | /* Search back for previous return. */ |
29639122 JB |
2864 | for (start_pc -= instlen;; start_pc -= instlen) |
2865 | if (start_pc < fence) | |
2866 | { | |
2867 | /* It's not clear to me why we reach this point when | |
2868 | stop_soon, but with this test, at least we | |
2869 | don't print out warnings for every child forked (eg, on | |
2870 | decstation). 22apr93 rich@cygnus.com. */ | |
16c381f0 | 2871 | if (inf->control.stop_soon == NO_STOP_QUIETLY) |
29639122 JB |
2872 | { |
2873 | static int blurb_printed = 0; | |
98b4dd94 | 2874 | |
5af949e3 UW |
2875 | warning (_("GDB can't find the start of the function at %s."), |
2876 | paddress (gdbarch, pc)); | |
29639122 JB |
2877 | |
2878 | if (!blurb_printed) | |
2879 | { | |
2880 | /* This actually happens frequently in embedded | |
2881 | development, when you first connect to a board | |
2882 | and your stack pointer and pc are nowhere in | |
2883 | particular. This message needs to give people | |
2884 | in that situation enough information to | |
2885 | determine that it's no big deal. */ | |
2886 | printf_filtered ("\n\ | |
5af949e3 | 2887 | GDB is unable to find the start of the function at %s\n\ |
29639122 JB |
2888 | and thus can't determine the size of that function's stack frame.\n\ |
2889 | This means that GDB may be unable to access that stack frame, or\n\ | |
2890 | the frames below it.\n\ | |
2891 | This problem is most likely caused by an invalid program counter or\n\ | |
2892 | stack pointer.\n\ | |
2893 | However, if you think GDB should simply search farther back\n\ | |
5af949e3 | 2894 | from %s for code which looks like the beginning of a\n\ |
29639122 | 2895 | function, you can increase the range of the search using the `set\n\ |
5af949e3 UW |
2896 | heuristic-fence-post' command.\n", |
2897 | paddress (gdbarch, pc), paddress (gdbarch, pc)); | |
29639122 JB |
2898 | blurb_printed = 1; |
2899 | } | |
2900 | } | |
2901 | ||
2902 | return 0; | |
2903 | } | |
0fe7e7c8 | 2904 | else if (mips_pc_is_mips16 (start_pc)) |
29639122 JB |
2905 | { |
2906 | unsigned short inst; | |
2907 | ||
2908 | /* On MIPS16, any one of the following is likely to be the | |
2909 | start of a function: | |
193774b3 MR |
2910 | extend save |
2911 | save | |
29639122 JB |
2912 | entry |
2913 | addiu sp,-n | |
2914 | daddiu sp,-n | |
025bb325 | 2915 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */ |
e17a4113 | 2916 | inst = mips_fetch_instruction (gdbarch, start_pc); |
193774b3 MR |
2917 | if ((inst & 0xff80) == 0x6480) /* save */ |
2918 | { | |
2919 | if (start_pc - instlen >= fence) | |
2920 | { | |
e17a4113 | 2921 | inst = mips_fetch_instruction (gdbarch, start_pc - instlen); |
193774b3 MR |
2922 | if ((inst & 0xf800) == 0xf000) /* extend */ |
2923 | start_pc -= instlen; | |
2924 | } | |
2925 | break; | |
2926 | } | |
2927 | else if (((inst & 0xf81f) == 0xe809 | |
2928 | && (inst & 0x700) != 0x700) /* entry */ | |
2929 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
2930 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
2931 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
29639122 JB |
2932 | break; |
2933 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
2934 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2935 | seen_adjsp = 1; | |
2936 | else | |
2937 | seen_adjsp = 0; | |
2938 | } | |
e17a4113 | 2939 | else if (mips_about_to_return (gdbarch, start_pc)) |
29639122 | 2940 | { |
4c7d22cb | 2941 | /* Skip return and its delay slot. */ |
95ac2dcf | 2942 | start_pc += 2 * MIPS_INSN32_SIZE; |
29639122 JB |
2943 | break; |
2944 | } | |
2945 | ||
2946 | return start_pc; | |
c906108c SS |
2947 | } |
2948 | ||
6c0d6680 DJ |
2949 | struct mips_objfile_private |
2950 | { | |
2951 | bfd_size_type size; | |
2952 | char *contents; | |
2953 | }; | |
2954 | ||
f09ded24 AC |
2955 | /* According to the current ABI, should the type be passed in a |
2956 | floating-point register (assuming that there is space)? When there | |
a1f5b845 | 2957 | is no FPU, FP are not even considered as possible candidates for |
f09ded24 | 2958 | FP registers and, consequently this returns false - forces FP |
025bb325 | 2959 | arguments into integer registers. */ |
f09ded24 AC |
2960 | |
2961 | static int | |
74ed0bb4 MD |
2962 | fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode, |
2963 | struct type *arg_type) | |
f09ded24 AC |
2964 | { |
2965 | return ((typecode == TYPE_CODE_FLT | |
74ed0bb4 | 2966 | || (MIPS_EABI (gdbarch) |
6d82d43b AC |
2967 | && (typecode == TYPE_CODE_STRUCT |
2968 | || typecode == TYPE_CODE_UNION) | |
f09ded24 | 2969 | && TYPE_NFIELDS (arg_type) == 1 |
b2d6f210 MS |
2970 | && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0))) |
2971 | == TYPE_CODE_FLT)) | |
74ed0bb4 | 2972 | && MIPS_FPU_TYPE(gdbarch) != MIPS_FPU_NONE); |
f09ded24 AC |
2973 | } |
2974 | ||
49e790b0 | 2975 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
025bb325 | 2976 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ |
49e790b0 DJ |
2977 | |
2978 | static int | |
2979 | mips_type_needs_double_align (struct type *type) | |
2980 | { | |
2981 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2982 | |
49e790b0 DJ |
2983 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2984 | return 1; | |
2985 | else if (typecode == TYPE_CODE_STRUCT) | |
2986 | { | |
2987 | if (TYPE_NFIELDS (type) < 1) | |
2988 | return 0; | |
2989 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2990 | } | |
2991 | else if (typecode == TYPE_CODE_UNION) | |
2992 | { | |
361d1df0 | 2993 | int i, n; |
49e790b0 DJ |
2994 | |
2995 | n = TYPE_NFIELDS (type); | |
2996 | for (i = 0; i < n; i++) | |
2997 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2998 | return 1; | |
2999 | return 0; | |
3000 | } | |
3001 | return 0; | |
3002 | } | |
3003 | ||
dc604539 AC |
3004 | /* Adjust the address downward (direction of stack growth) so that it |
3005 | is correctly aligned for a new stack frame. */ | |
3006 | static CORE_ADDR | |
3007 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
3008 | { | |
5b03f266 | 3009 | return align_down (addr, 16); |
dc604539 AC |
3010 | } |
3011 | ||
8ae38c14 | 3012 | /* Implement the "push_dummy_code" gdbarch method. */ |
2c76a0c7 JB |
3013 | |
3014 | static CORE_ADDR | |
3015 | mips_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
3016 | CORE_ADDR funaddr, struct value **args, | |
3017 | int nargs, struct type *value_type, | |
3018 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, | |
3019 | struct regcache *regcache) | |
3020 | { | |
3021 | CORE_ADDR nop_addr; | |
3022 | static gdb_byte nop_insn[] = { 0, 0, 0, 0 }; | |
3023 | ||
3024 | /* Reserve enough room on the stack for our breakpoint instruction. */ | |
3025 | *bp_addr = sp - sizeof (nop_insn); | |
3026 | ||
3027 | /* The breakpoint layer automatically adjusts the address of | |
3028 | breakpoints inserted in a branch delay slot. With enough | |
3029 | bad luck, the 4 bytes located just before our breakpoint | |
3030 | instruction could look like a branch instruction, and thus | |
3031 | trigger the adjustement, and break the function call entirely. | |
3032 | So, we reserve those 4 bytes and write a nop instruction | |
3033 | to prevent that from happening. */ | |
3034 | nop_addr = *bp_addr - sizeof (nop_insn); | |
3035 | write_memory (nop_addr, nop_insn, sizeof (nop_insn)); | |
3036 | sp = mips_frame_align (gdbarch, nop_addr); | |
3037 | ||
3038 | /* Inferior resumes at the function entry point. */ | |
3039 | *real_pc = funaddr; | |
3040 | ||
3041 | return sp; | |
3042 | } | |
3043 | ||
f7ab6ec6 | 3044 | static CORE_ADDR |
7d9b040b | 3045 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3046 | struct regcache *regcache, CORE_ADDR bp_addr, |
3047 | int nargs, struct value **args, CORE_ADDR sp, | |
3048 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
3049 | { |
3050 | int argreg; | |
3051 | int float_argreg; | |
3052 | int argnum; | |
3053 | int len = 0; | |
3054 | int stack_offset = 0; | |
480d3dd2 | 3055 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 3056 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 3057 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
1a69e1e4 | 3058 | int regsize = mips_abi_regsize (gdbarch); |
c906108c | 3059 | |
25ab4790 AC |
3060 | /* For shared libraries, "t9" needs to point at the function |
3061 | address. */ | |
4c7d22cb | 3062 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
3063 | |
3064 | /* Set the return address register to point to the entry point of | |
3065 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3066 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 3067 | |
c906108c | 3068 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
3069 | are properly aligned. The stack has to be at least 64-bit |
3070 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3071 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3072 | aligned, so we round to this widest known alignment. */ | |
3073 | ||
5b03f266 AC |
3074 | sp = align_down (sp, 16); |
3075 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 3076 | |
46e0f506 | 3077 | /* Now make space on the stack for the args. We allocate more |
c906108c | 3078 | than necessary for EABI, because the first few arguments are |
46e0f506 | 3079 | passed in registers, but that's OK. */ |
c906108c | 3080 | for (argnum = 0; argnum < nargs; argnum++) |
1a69e1e4 | 3081 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize); |
5b03f266 | 3082 | sp -= align_up (len, 16); |
c906108c | 3083 | |
9ace0497 | 3084 | if (mips_debug) |
6d82d43b | 3085 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
3086 | "mips_eabi_push_dummy_call: sp=%s allocated %ld\n", |
3087 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
9ace0497 | 3088 | |
c906108c | 3089 | /* Initialize the integer and float register pointers. */ |
4c7d22cb | 3090 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 3091 | float_argreg = mips_fpa0_regnum (gdbarch); |
c906108c | 3092 | |
46e0f506 | 3093 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 3094 | if (struct_return) |
9ace0497 AC |
3095 | { |
3096 | if (mips_debug) | |
3097 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
3098 | "mips_eabi_push_dummy_call: " |
3099 | "struct_return reg=%d %s\n", | |
5af949e3 | 3100 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 3101 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
9ace0497 | 3102 | } |
c906108c SS |
3103 | |
3104 | /* Now load as many as possible of the first arguments into | |
3105 | registers, and push the rest onto the stack. Loop thru args | |
3106 | from first to last. */ | |
3107 | for (argnum = 0; argnum < nargs; argnum++) | |
3108 | { | |
47a35522 MK |
3109 | const gdb_byte *val; |
3110 | gdb_byte valbuf[MAX_REGISTER_SIZE]; | |
ea7c478f | 3111 | struct value *arg = args[argnum]; |
4991999e | 3112 | struct type *arg_type = check_typedef (value_type (arg)); |
c906108c SS |
3113 | int len = TYPE_LENGTH (arg_type); |
3114 | enum type_code typecode = TYPE_CODE (arg_type); | |
3115 | ||
9ace0497 AC |
3116 | if (mips_debug) |
3117 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3118 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 3119 | argnum + 1, len, (int) typecode); |
9ace0497 | 3120 | |
930bd0e0 KB |
3121 | /* Function pointer arguments to mips16 code need to be made into |
3122 | mips16 pointers. */ | |
3123 | if (typecode == TYPE_CODE_PTR | |
3124 | && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC) | |
3125 | { | |
3126 | CORE_ADDR addr = extract_signed_integer (value_contents (arg), | |
3127 | len, byte_order); | |
3128 | if (mips_pc_is_mips16 (addr)) | |
3129 | { | |
3130 | store_signed_integer (valbuf, len, byte_order, | |
3131 | make_mips16_addr (addr)); | |
3132 | val = valbuf; | |
3133 | } | |
3134 | else | |
3135 | val = value_contents (arg); | |
3136 | } | |
c906108c | 3137 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 3138 | reference. */ |
930bd0e0 | 3139 | else if (len > regsize |
9ace0497 | 3140 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 3141 | { |
e17a4113 UW |
3142 | store_unsigned_integer (valbuf, regsize, byte_order, |
3143 | value_address (arg)); | |
c906108c | 3144 | typecode = TYPE_CODE_PTR; |
1a69e1e4 | 3145 | len = regsize; |
c906108c | 3146 | val = valbuf; |
9ace0497 AC |
3147 | if (mips_debug) |
3148 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
3149 | } |
3150 | else | |
47a35522 | 3151 | val = value_contents (arg); |
c906108c SS |
3152 | |
3153 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
3154 | even-numbered floating point register. Round the FP register |
3155 | up before the check to see if there are any FP registers | |
46e0f506 MS |
3156 | left. Non MIPS_EABI targets also pass the FP in the integer |
3157 | registers so also round up normal registers. */ | |
74ed0bb4 | 3158 | if (regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type)) |
acdb74a0 AC |
3159 | { |
3160 | if ((float_argreg & 1)) | |
3161 | float_argreg++; | |
3162 | } | |
c906108c SS |
3163 | |
3164 | /* Floating point arguments passed in registers have to be | |
3165 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
3166 | are passed in register pairs; the even register gets |
3167 | the low word, and the odd register gets the high word. | |
3168 | On non-EABI processors, the first two floating point arguments are | |
3169 | also copied to general registers, because MIPS16 functions | |
3170 | don't use float registers for arguments. This duplication of | |
3171 | arguments in general registers can't hurt non-MIPS16 functions | |
3172 | because those registers are normally skipped. */ | |
1012bd0e EZ |
3173 | /* MIPS_EABI squeezes a struct that contains a single floating |
3174 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 3175 | stack. */ |
74ed0bb4 MD |
3176 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
3177 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
c906108c | 3178 | { |
6da397e0 KB |
3179 | /* EABI32 will pass doubles in consecutive registers, even on |
3180 | 64-bit cores. At one time, we used to check the size of | |
3181 | `float_argreg' to determine whether or not to pass doubles | |
3182 | in consecutive registers, but this is not sufficient for | |
3183 | making the ABI determination. */ | |
3184 | if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) | |
c906108c | 3185 | { |
72a155b4 | 3186 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 3187 | == BFD_ENDIAN_BIG ? 4 : 0; |
a8852dc5 | 3188 | long regval; |
c906108c SS |
3189 | |
3190 | /* Write the low word of the double to the even register(s). */ | |
a8852dc5 KB |
3191 | regval = extract_signed_integer (val + low_offset, |
3192 | 4, byte_order); | |
9ace0497 | 3193 | if (mips_debug) |
acdb74a0 | 3194 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 3195 | float_argreg, phex (regval, 4)); |
a8852dc5 | 3196 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
3197 | |
3198 | /* Write the high word of the double to the odd register(s). */ | |
a8852dc5 KB |
3199 | regval = extract_signed_integer (val + 4 - low_offset, |
3200 | 4, byte_order); | |
9ace0497 | 3201 | if (mips_debug) |
acdb74a0 | 3202 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 3203 | float_argreg, phex (regval, 4)); |
a8852dc5 | 3204 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
3205 | } |
3206 | else | |
3207 | { | |
3208 | /* This is a floating point value that fits entirely | |
3209 | in a single register. */ | |
53a5351d | 3210 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 3211 | above to ensure that it is even register aligned. */ |
a8852dc5 | 3212 | LONGEST regval = extract_signed_integer (val, len, byte_order); |
9ace0497 | 3213 | if (mips_debug) |
acdb74a0 | 3214 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 3215 | float_argreg, phex (regval, len)); |
a8852dc5 | 3216 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
3217 | } |
3218 | } | |
3219 | else | |
3220 | { | |
3221 | /* Copy the argument to general registers or the stack in | |
3222 | register-sized pieces. Large arguments are split between | |
3223 | registers and stack. */ | |
1a69e1e4 DJ |
3224 | /* Note: structs whose size is not a multiple of regsize |
3225 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
3226 | them in registers where gcc sometimes puts them on the |
3227 | stack. For maximum compatibility, we will put them in | |
3228 | both places. */ | |
1a69e1e4 | 3229 | int odd_sized_struct = (len > regsize && len % regsize != 0); |
46e0f506 | 3230 | |
f09ded24 | 3231 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3232 | register are only written to memory. */ |
c906108c SS |
3233 | while (len > 0) |
3234 | { | |
ebafbe83 | 3235 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 3236 | int stack_used_p = 0; |
1a69e1e4 | 3237 | int partial_len = (len < regsize ? len : regsize); |
c906108c | 3238 | |
acdb74a0 AC |
3239 | if (mips_debug) |
3240 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3241 | partial_len); | |
3242 | ||
566f0f7a | 3243 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 3244 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
f09ded24 | 3245 | || odd_sized_struct |
74ed0bb4 | 3246 | || fp_register_arg_p (gdbarch, typecode, arg_type)) |
c906108c | 3247 | { |
c906108c | 3248 | /* Should shorter than int integer values be |
025bb325 | 3249 | promoted to int before being stored? */ |
c906108c | 3250 | int longword_offset = 0; |
9ace0497 | 3251 | CORE_ADDR addr; |
566f0f7a | 3252 | stack_used_p = 1; |
72a155b4 | 3253 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
7a292a7a | 3254 | { |
1a69e1e4 | 3255 | if (regsize == 8 |
480d3dd2 AC |
3256 | && (typecode == TYPE_CODE_INT |
3257 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 3258 | || typecode == TYPE_CODE_FLT) && len <= 4) |
1a69e1e4 | 3259 | longword_offset = regsize - len; |
480d3dd2 AC |
3260 | else if ((typecode == TYPE_CODE_STRUCT |
3261 | || typecode == TYPE_CODE_UNION) | |
1a69e1e4 DJ |
3262 | && TYPE_LENGTH (arg_type) < regsize) |
3263 | longword_offset = regsize - len; | |
7a292a7a | 3264 | } |
c5aa993b | 3265 | |
9ace0497 AC |
3266 | if (mips_debug) |
3267 | { | |
5af949e3 UW |
3268 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
3269 | paddress (gdbarch, stack_offset)); | |
3270 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
3271 | paddress (gdbarch, longword_offset)); | |
9ace0497 | 3272 | } |
361d1df0 | 3273 | |
9ace0497 AC |
3274 | addr = sp + stack_offset + longword_offset; |
3275 | ||
3276 | if (mips_debug) | |
3277 | { | |
3278 | int i; | |
5af949e3 UW |
3279 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
3280 | paddress (gdbarch, addr)); | |
9ace0497 AC |
3281 | for (i = 0; i < partial_len; i++) |
3282 | { | |
6d82d43b | 3283 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 3284 | val[i] & 0xff); |
9ace0497 AC |
3285 | } |
3286 | } | |
3287 | write_memory (addr, val, partial_len); | |
c906108c SS |
3288 | } |
3289 | ||
f09ded24 AC |
3290 | /* Note!!! This is NOT an else clause. Odd sized |
3291 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 3292 | arguments will not. */ |
566f0f7a | 3293 | /* Write this portion of the argument to a general |
6d82d43b | 3294 | purpose register. */ |
74ed0bb4 MD |
3295 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch) |
3296 | && !fp_register_arg_p (gdbarch, typecode, arg_type)) | |
c906108c | 3297 | { |
6d82d43b | 3298 | LONGEST regval = |
a8852dc5 | 3299 | extract_signed_integer (val, partial_len, byte_order); |
c906108c | 3300 | |
9ace0497 | 3301 | if (mips_debug) |
acdb74a0 | 3302 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 3303 | argreg, |
1a69e1e4 | 3304 | phex (regval, regsize)); |
a8852dc5 | 3305 | regcache_cooked_write_signed (regcache, argreg, regval); |
c906108c | 3306 | argreg++; |
c906108c | 3307 | } |
c5aa993b | 3308 | |
c906108c SS |
3309 | len -= partial_len; |
3310 | val += partial_len; | |
3311 | ||
b021a221 MS |
3312 | /* Compute the offset into the stack at which we will |
3313 | copy the next parameter. | |
566f0f7a | 3314 | |
566f0f7a | 3315 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 3316 | only needs to be adjusted when it has been used. */ |
c906108c | 3317 | |
46e0f506 | 3318 | if (stack_used_p) |
1a69e1e4 | 3319 | stack_offset += align_up (partial_len, regsize); |
c906108c SS |
3320 | } |
3321 | } | |
9ace0497 AC |
3322 | if (mips_debug) |
3323 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
3324 | } |
3325 | ||
f10683bb | 3326 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3327 | |
0f71a2f6 JM |
3328 | /* Return adjusted stack pointer. */ |
3329 | return sp; | |
3330 | } | |
3331 | ||
a1f5b845 | 3332 | /* Determine the return value convention being used. */ |
6d82d43b | 3333 | |
9c8fdbfa | 3334 | static enum return_value_convention |
6a3a010b | 3335 | mips_eabi_return_value (struct gdbarch *gdbarch, struct value *function, |
9c8fdbfa | 3336 | struct type *type, struct regcache *regcache, |
47a35522 | 3337 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 3338 | { |
609ba780 JM |
3339 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3340 | int fp_return_type = 0; | |
3341 | int offset, regnum, xfer; | |
3342 | ||
9c8fdbfa AC |
3343 | if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
3344 | return RETURN_VALUE_STRUCT_CONVENTION; | |
609ba780 JM |
3345 | |
3346 | /* Floating point type? */ | |
3347 | if (tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3348 | { | |
3349 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
3350 | fp_return_type = 1; | |
3351 | /* Structs with a single field of float type | |
3352 | are returned in a floating point register. */ | |
3353 | if ((TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3354 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3355 | && TYPE_NFIELDS (type) == 1) | |
3356 | { | |
3357 | struct type *fieldtype = TYPE_FIELD_TYPE (type, 0); | |
3358 | ||
3359 | if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT) | |
3360 | fp_return_type = 1; | |
3361 | } | |
3362 | } | |
3363 | ||
3364 | if (fp_return_type) | |
3365 | { | |
3366 | /* A floating-point value belongs in the least significant part | |
3367 | of FP0/FP1. */ | |
3368 | if (mips_debug) | |
3369 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3370 | regnum = mips_regnum (gdbarch)->fp0; | |
3371 | } | |
3372 | else | |
3373 | { | |
3374 | /* An integer value goes in V0/V1. */ | |
3375 | if (mips_debug) | |
3376 | fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n"); | |
3377 | regnum = MIPS_V0_REGNUM; | |
3378 | } | |
3379 | for (offset = 0; | |
3380 | offset < TYPE_LENGTH (type); | |
3381 | offset += mips_abi_regsize (gdbarch), regnum++) | |
3382 | { | |
3383 | xfer = mips_abi_regsize (gdbarch); | |
3384 | if (offset + xfer > TYPE_LENGTH (type)) | |
3385 | xfer = TYPE_LENGTH (type) - offset; | |
3386 | mips_xfer_register (gdbarch, regcache, | |
3387 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
3388 | gdbarch_byte_order (gdbarch), readbuf, writebuf, | |
3389 | offset); | |
3390 | } | |
3391 | ||
9c8fdbfa | 3392 | return RETURN_VALUE_REGISTER_CONVENTION; |
6d82d43b AC |
3393 | } |
3394 | ||
6d82d43b AC |
3395 | |
3396 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 3397 | |
8d26208a DJ |
3398 | /* Search for a naturally aligned double at OFFSET inside a struct |
3399 | ARG_TYPE. The N32 / N64 ABIs pass these in floating point | |
3400 | registers. */ | |
3401 | ||
3402 | static int | |
74ed0bb4 MD |
3403 | mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type, |
3404 | int offset) | |
8d26208a DJ |
3405 | { |
3406 | int i; | |
3407 | ||
3408 | if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT) | |
3409 | return 0; | |
3410 | ||
74ed0bb4 | 3411 | if (MIPS_FPU_TYPE (gdbarch) != MIPS_FPU_DOUBLE) |
8d26208a DJ |
3412 | return 0; |
3413 | ||
3414 | if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE) | |
3415 | return 0; | |
3416 | ||
3417 | for (i = 0; i < TYPE_NFIELDS (arg_type); i++) | |
3418 | { | |
3419 | int pos; | |
3420 | struct type *field_type; | |
3421 | ||
3422 | /* We're only looking at normal fields. */ | |
5bc60cfb | 3423 | if (field_is_static (&TYPE_FIELD (arg_type, i)) |
8d26208a DJ |
3424 | || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0) |
3425 | continue; | |
3426 | ||
3427 | /* If we have gone past the offset, there is no double to pass. */ | |
3428 | pos = TYPE_FIELD_BITPOS (arg_type, i) / 8; | |
3429 | if (pos > offset) | |
3430 | return 0; | |
3431 | ||
3432 | field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i)); | |
3433 | ||
3434 | /* If this field is entirely before the requested offset, go | |
3435 | on to the next one. */ | |
3436 | if (pos + TYPE_LENGTH (field_type) <= offset) | |
3437 | continue; | |
3438 | ||
3439 | /* If this is our special aligned double, we can stop. */ | |
3440 | if (TYPE_CODE (field_type) == TYPE_CODE_FLT | |
3441 | && TYPE_LENGTH (field_type) == MIPS64_REGSIZE) | |
3442 | return 1; | |
3443 | ||
3444 | /* This field starts at or before the requested offset, and | |
3445 | overlaps it. If it is a structure, recurse inwards. */ | |
74ed0bb4 | 3446 | return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos); |
8d26208a DJ |
3447 | } |
3448 | ||
3449 | return 0; | |
3450 | } | |
3451 | ||
f7ab6ec6 | 3452 | static CORE_ADDR |
7d9b040b | 3453 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3454 | struct regcache *regcache, CORE_ADDR bp_addr, |
3455 | int nargs, struct value **args, CORE_ADDR sp, | |
3456 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
3457 | { |
3458 | int argreg; | |
3459 | int float_argreg; | |
3460 | int argnum; | |
3461 | int len = 0; | |
3462 | int stack_offset = 0; | |
480d3dd2 | 3463 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 3464 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 3465 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 3466 | |
25ab4790 AC |
3467 | /* For shared libraries, "t9" needs to point at the function |
3468 | address. */ | |
4c7d22cb | 3469 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
3470 | |
3471 | /* Set the return address register to point to the entry point of | |
3472 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3473 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 3474 | |
cb3d25d1 MS |
3475 | /* First ensure that the stack and structure return address (if any) |
3476 | are properly aligned. The stack has to be at least 64-bit | |
3477 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3478 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3479 | aligned, so we round to this widest known alignment. */ | |
3480 | ||
5b03f266 AC |
3481 | sp = align_down (sp, 16); |
3482 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
3483 | |
3484 | /* Now make space on the stack for the args. */ | |
3485 | for (argnum = 0; argnum < nargs; argnum++) | |
1a69e1e4 | 3486 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE); |
5b03f266 | 3487 | sp -= align_up (len, 16); |
cb3d25d1 MS |
3488 | |
3489 | if (mips_debug) | |
6d82d43b | 3490 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
3491 | "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n", |
3492 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
3493 | |
3494 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3495 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 3496 | float_argreg = mips_fpa0_regnum (gdbarch); |
cb3d25d1 | 3497 | |
46e0f506 | 3498 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
3499 | if (struct_return) |
3500 | { | |
3501 | if (mips_debug) | |
3502 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
3503 | "mips_n32n64_push_dummy_call: " |
3504 | "struct_return reg=%d %s\n", | |
5af949e3 | 3505 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 3506 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
cb3d25d1 MS |
3507 | } |
3508 | ||
3509 | /* Now load as many as possible of the first arguments into | |
3510 | registers, and push the rest onto the stack. Loop thru args | |
3511 | from first to last. */ | |
3512 | for (argnum = 0; argnum < nargs; argnum++) | |
3513 | { | |
47a35522 | 3514 | const gdb_byte *val; |
cb3d25d1 | 3515 | struct value *arg = args[argnum]; |
4991999e | 3516 | struct type *arg_type = check_typedef (value_type (arg)); |
cb3d25d1 MS |
3517 | int len = TYPE_LENGTH (arg_type); |
3518 | enum type_code typecode = TYPE_CODE (arg_type); | |
3519 | ||
3520 | if (mips_debug) | |
3521 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3522 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
3523 | argnum + 1, len, (int) typecode); |
3524 | ||
47a35522 | 3525 | val = value_contents (arg); |
cb3d25d1 | 3526 | |
5b68030f JM |
3527 | /* A 128-bit long double value requires an even-odd pair of |
3528 | floating-point registers. */ | |
3529 | if (len == 16 | |
3530 | && fp_register_arg_p (gdbarch, typecode, arg_type) | |
3531 | && (float_argreg & 1)) | |
3532 | { | |
3533 | float_argreg++; | |
3534 | argreg++; | |
3535 | } | |
3536 | ||
74ed0bb4 MD |
3537 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
3538 | && argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) | |
cb3d25d1 MS |
3539 | { |
3540 | /* This is a floating point value that fits entirely | |
5b68030f JM |
3541 | in a single register or a pair of registers. */ |
3542 | int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE); | |
e17a4113 | 3543 | LONGEST regval = extract_unsigned_integer (val, reglen, byte_order); |
cb3d25d1 MS |
3544 | if (mips_debug) |
3545 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5b68030f | 3546 | float_argreg, phex (regval, reglen)); |
8d26208a | 3547 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); |
cb3d25d1 MS |
3548 | |
3549 | if (mips_debug) | |
3550 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5b68030f | 3551 | argreg, phex (regval, reglen)); |
9c9acae0 | 3552 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a DJ |
3553 | float_argreg++; |
3554 | argreg++; | |
5b68030f JM |
3555 | if (len == 16) |
3556 | { | |
e17a4113 UW |
3557 | regval = extract_unsigned_integer (val + reglen, |
3558 | reglen, byte_order); | |
5b68030f JM |
3559 | if (mips_debug) |
3560 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3561 | float_argreg, phex (regval, reglen)); | |
3562 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); | |
3563 | ||
3564 | if (mips_debug) | |
3565 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3566 | argreg, phex (regval, reglen)); | |
3567 | regcache_cooked_write_unsigned (regcache, argreg, regval); | |
3568 | float_argreg++; | |
3569 | argreg++; | |
3570 | } | |
cb3d25d1 MS |
3571 | } |
3572 | else | |
3573 | { | |
3574 | /* Copy the argument to general registers or the stack in | |
3575 | register-sized pieces. Large arguments are split between | |
3576 | registers and stack. */ | |
ab2e1992 MR |
3577 | /* For N32/N64, structs, unions, or other composite types are |
3578 | treated as a sequence of doublewords, and are passed in integer | |
3579 | or floating point registers as though they were simple scalar | |
3580 | parameters to the extent that they fit, with any excess on the | |
3581 | stack packed according to the normal memory layout of the | |
3582 | object. | |
3583 | The caller does not reserve space for the register arguments; | |
3584 | the callee is responsible for reserving it if required. */ | |
cb3d25d1 | 3585 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3586 | register are only written to memory. */ |
cb3d25d1 MS |
3587 | while (len > 0) |
3588 | { | |
ad018eee | 3589 | /* Remember if the argument was written to the stack. */ |
cb3d25d1 | 3590 | int stack_used_p = 0; |
1a69e1e4 | 3591 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
cb3d25d1 MS |
3592 | |
3593 | if (mips_debug) | |
3594 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3595 | partial_len); | |
3596 | ||
74ed0bb4 MD |
3597 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
3598 | gdb_assert (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)); | |
8d26208a | 3599 | |
cb3d25d1 | 3600 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 3601 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 MS |
3602 | { |
3603 | /* Should shorter than int integer values be | |
025bb325 | 3604 | promoted to int before being stored? */ |
cb3d25d1 MS |
3605 | int longword_offset = 0; |
3606 | CORE_ADDR addr; | |
3607 | stack_used_p = 1; | |
72a155b4 | 3608 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
cb3d25d1 | 3609 | { |
1a69e1e4 | 3610 | if ((typecode == TYPE_CODE_INT |
5b68030f | 3611 | || typecode == TYPE_CODE_PTR) |
1a69e1e4 DJ |
3612 | && len <= 4) |
3613 | longword_offset = MIPS64_REGSIZE - len; | |
cb3d25d1 MS |
3614 | } |
3615 | ||
3616 | if (mips_debug) | |
3617 | { | |
5af949e3 UW |
3618 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
3619 | paddress (gdbarch, stack_offset)); | |
3620 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
3621 | paddress (gdbarch, longword_offset)); | |
cb3d25d1 MS |
3622 | } |
3623 | ||
3624 | addr = sp + stack_offset + longword_offset; | |
3625 | ||
3626 | if (mips_debug) | |
3627 | { | |
3628 | int i; | |
5af949e3 UW |
3629 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
3630 | paddress (gdbarch, addr)); | |
cb3d25d1 MS |
3631 | for (i = 0; i < partial_len; i++) |
3632 | { | |
6d82d43b | 3633 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
3634 | val[i] & 0xff); |
3635 | } | |
3636 | } | |
3637 | write_memory (addr, val, partial_len); | |
3638 | } | |
3639 | ||
3640 | /* Note!!! This is NOT an else clause. Odd sized | |
8d26208a | 3641 | structs may go thru BOTH paths. */ |
cb3d25d1 | 3642 | /* Write this portion of the argument to a general |
6d82d43b | 3643 | purpose register. */ |
74ed0bb4 | 3644 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 | 3645 | { |
5863b5d5 MR |
3646 | LONGEST regval; |
3647 | ||
3648 | /* Sign extend pointers, 32-bit integers and signed | |
3649 | 16-bit and 8-bit integers; everything else is taken | |
3650 | as is. */ | |
3651 | ||
3652 | if ((partial_len == 4 | |
3653 | && (typecode == TYPE_CODE_PTR | |
3654 | || typecode == TYPE_CODE_INT)) | |
3655 | || (partial_len < 4 | |
3656 | && typecode == TYPE_CODE_INT | |
3657 | && !TYPE_UNSIGNED (arg_type))) | |
e17a4113 UW |
3658 | regval = extract_signed_integer (val, partial_len, |
3659 | byte_order); | |
5863b5d5 | 3660 | else |
e17a4113 UW |
3661 | regval = extract_unsigned_integer (val, partial_len, |
3662 | byte_order); | |
cb3d25d1 MS |
3663 | |
3664 | /* A non-floating-point argument being passed in a | |
3665 | general register. If a struct or union, and if | |
3666 | the remaining length is smaller than the register | |
3667 | size, we have to adjust the register value on | |
3668 | big endian targets. | |
3669 | ||
3670 | It does not seem to be necessary to do the | |
1a69e1e4 | 3671 | same for integral types. */ |
cb3d25d1 | 3672 | |
72a155b4 | 3673 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3674 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
3675 | && (typecode == TYPE_CODE_STRUCT |
3676 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3677 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 3678 | * TARGET_CHAR_BIT); |
cb3d25d1 MS |
3679 | |
3680 | if (mips_debug) | |
3681 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3682 | argreg, | |
1a69e1e4 | 3683 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 3684 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a | 3685 | |
74ed0bb4 | 3686 | if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type, |
8d26208a DJ |
3687 | TYPE_LENGTH (arg_type) - len)) |
3688 | { | |
3689 | if (mips_debug) | |
3690 | fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s", | |
3691 | float_argreg, | |
3692 | phex (regval, MIPS64_REGSIZE)); | |
3693 | regcache_cooked_write_unsigned (regcache, float_argreg, | |
3694 | regval); | |
3695 | } | |
3696 | ||
3697 | float_argreg++; | |
cb3d25d1 MS |
3698 | argreg++; |
3699 | } | |
3700 | ||
3701 | len -= partial_len; | |
3702 | val += partial_len; | |
3703 | ||
b021a221 MS |
3704 | /* Compute the offset into the stack at which we will |
3705 | copy the next parameter. | |
cb3d25d1 MS |
3706 | |
3707 | In N32 (N64?), the stack_offset only needs to be | |
3708 | adjusted when it has been used. */ | |
3709 | ||
3710 | if (stack_used_p) | |
1a69e1e4 | 3711 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
cb3d25d1 MS |
3712 | } |
3713 | } | |
3714 | if (mips_debug) | |
3715 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3716 | } | |
3717 | ||
f10683bb | 3718 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3719 | |
cb3d25d1 MS |
3720 | /* Return adjusted stack pointer. */ |
3721 | return sp; | |
3722 | } | |
3723 | ||
6d82d43b | 3724 | static enum return_value_convention |
6a3a010b | 3725 | mips_n32n64_return_value (struct gdbarch *gdbarch, struct value *function, |
6d82d43b | 3726 | struct type *type, struct regcache *regcache, |
47a35522 | 3727 | gdb_byte *readbuf, const gdb_byte *writebuf) |
ebafbe83 | 3728 | { |
72a155b4 | 3729 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
b18bb924 MR |
3730 | |
3731 | /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004 | |
3732 | ||
3733 | Function results are returned in $2 (and $3 if needed), or $f0 (and $f2 | |
3734 | if needed), as appropriate for the type. Composite results (struct, | |
3735 | union, or array) are returned in $2/$f0 and $3/$f2 according to the | |
3736 | following rules: | |
3737 | ||
3738 | * A struct with only one or two floating point fields is returned in $f0 | |
3739 | (and $f2 if necessary). This is a generalization of the Fortran COMPLEX | |
3740 | case. | |
3741 | ||
f08877ba | 3742 | * Any other composite results of at most 128 bits are returned in |
b18bb924 MR |
3743 | $2 (first 64 bits) and $3 (remainder, if necessary). |
3744 | ||
3745 | * Larger composite results are handled by converting the function to a | |
3746 | procedure with an implicit first parameter, which is a pointer to an area | |
3747 | reserved by the caller to receive the result. [The o32-bit ABI requires | |
3748 | that all composite results be handled by conversion to implicit first | |
3749 | parameters. The MIPS/SGI Fortran implementation has always made a | |
3750 | specific exception to return COMPLEX results in the floating point | |
3751 | registers.] */ | |
3752 | ||
f08877ba | 3753 | if (TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE) |
6d82d43b | 3754 | return RETURN_VALUE_STRUCT_CONVENTION; |
d05f6826 DJ |
3755 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3756 | && TYPE_LENGTH (type) == 16 | |
3757 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3758 | { | |
3759 | /* A 128-bit floating-point value fills both $f0 and $f2. The | |
3760 | two registers are used in the same as memory order, so the | |
3761 | eight bytes with the lower memory address are in $f0. */ | |
3762 | if (mips_debug) | |
3763 | fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n"); | |
ba32f989 | 3764 | mips_xfer_register (gdbarch, regcache, |
dca9aa3a MR |
3765 | (gdbarch_num_regs (gdbarch) |
3766 | + mips_regnum (gdbarch)->fp0), | |
72a155b4 | 3767 | 8, gdbarch_byte_order (gdbarch), |
4c6b5505 | 3768 | readbuf, writebuf, 0); |
ba32f989 | 3769 | mips_xfer_register (gdbarch, regcache, |
dca9aa3a MR |
3770 | (gdbarch_num_regs (gdbarch) |
3771 | + mips_regnum (gdbarch)->fp0 + 2), | |
72a155b4 | 3772 | 8, gdbarch_byte_order (gdbarch), |
4c6b5505 | 3773 | readbuf ? readbuf + 8 : readbuf, |
d05f6826 DJ |
3774 | writebuf ? writebuf + 8 : writebuf, 0); |
3775 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3776 | } | |
6d82d43b AC |
3777 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3778 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3779 | { | |
59aa1faa | 3780 | /* A single or double floating-point value that fits in FP0. */ |
6d82d43b AC |
3781 | if (mips_debug) |
3782 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 3783 | mips_xfer_register (gdbarch, regcache, |
dca9aa3a MR |
3784 | (gdbarch_num_regs (gdbarch) |
3785 | + mips_regnum (gdbarch)->fp0), | |
6d82d43b | 3786 | TYPE_LENGTH (type), |
72a155b4 | 3787 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3788 | readbuf, writebuf, 0); |
6d82d43b AC |
3789 | return RETURN_VALUE_REGISTER_CONVENTION; |
3790 | } | |
3791 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3792 | && TYPE_NFIELDS (type) <= 2 | |
3793 | && TYPE_NFIELDS (type) >= 1 | |
3794 | && ((TYPE_NFIELDS (type) == 1 | |
b18bb924 | 3795 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b AC |
3796 | == TYPE_CODE_FLT)) |
3797 | || (TYPE_NFIELDS (type) == 2 | |
b18bb924 | 3798 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b | 3799 | == TYPE_CODE_FLT) |
b18bb924 | 3800 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1))) |
5b68030f | 3801 | == TYPE_CODE_FLT)))) |
6d82d43b AC |
3802 | { |
3803 | /* A struct that contains one or two floats. Each value is part | |
3804 | in the least significant part of their floating point | |
5b68030f | 3805 | register (or GPR, for soft float). */ |
6d82d43b AC |
3806 | int regnum; |
3807 | int field; | |
5b68030f JM |
3808 | for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE |
3809 | ? mips_regnum (gdbarch)->fp0 | |
3810 | : MIPS_V0_REGNUM); | |
6d82d43b AC |
3811 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
3812 | { | |
3813 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3814 | / TARGET_CHAR_BIT); | |
3815 | if (mips_debug) | |
3816 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3817 | offset); | |
5b68030f JM |
3818 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)) == 16) |
3819 | { | |
3820 | /* A 16-byte long double field goes in two consecutive | |
3821 | registers. */ | |
3822 | mips_xfer_register (gdbarch, regcache, | |
3823 | gdbarch_num_regs (gdbarch) + regnum, | |
3824 | 8, | |
3825 | gdbarch_byte_order (gdbarch), | |
3826 | readbuf, writebuf, offset); | |
3827 | mips_xfer_register (gdbarch, regcache, | |
3828 | gdbarch_num_regs (gdbarch) + regnum + 1, | |
3829 | 8, | |
3830 | gdbarch_byte_order (gdbarch), | |
3831 | readbuf, writebuf, offset + 8); | |
3832 | } | |
3833 | else | |
3834 | mips_xfer_register (gdbarch, regcache, | |
3835 | gdbarch_num_regs (gdbarch) + regnum, | |
3836 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
3837 | gdbarch_byte_order (gdbarch), | |
3838 | readbuf, writebuf, offset); | |
6d82d43b AC |
3839 | } |
3840 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3841 | } | |
3842 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
f08877ba JB |
3843 | || TYPE_CODE (type) == TYPE_CODE_UNION |
3844 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
6d82d43b | 3845 | { |
f08877ba | 3846 | /* A composite type. Extract the left justified value, |
6d82d43b AC |
3847 | regardless of the byte order. I.e. DO NOT USE |
3848 | mips_xfer_lower. */ | |
3849 | int offset; | |
3850 | int regnum; | |
4c7d22cb | 3851 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3852 | offset < TYPE_LENGTH (type); |
72a155b4 | 3853 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3854 | { |
72a155b4 | 3855 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3856 | if (offset + xfer > TYPE_LENGTH (type)) |
3857 | xfer = TYPE_LENGTH (type) - offset; | |
3858 | if (mips_debug) | |
3859 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3860 | offset, xfer, regnum); | |
ba32f989 DJ |
3861 | mips_xfer_register (gdbarch, regcache, |
3862 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 UW |
3863 | xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf, |
3864 | offset); | |
6d82d43b AC |
3865 | } |
3866 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3867 | } | |
3868 | else | |
3869 | { | |
3870 | /* A scalar extract each part but least-significant-byte | |
3871 | justified. */ | |
3872 | int offset; | |
3873 | int regnum; | |
4c7d22cb | 3874 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3875 | offset < TYPE_LENGTH (type); |
72a155b4 | 3876 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3877 | { |
72a155b4 | 3878 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3879 | if (offset + xfer > TYPE_LENGTH (type)) |
3880 | xfer = TYPE_LENGTH (type) - offset; | |
3881 | if (mips_debug) | |
3882 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3883 | offset, xfer, regnum); | |
ba32f989 DJ |
3884 | mips_xfer_register (gdbarch, regcache, |
3885 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 3886 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 3887 | readbuf, writebuf, offset); |
6d82d43b AC |
3888 | } |
3889 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3890 | } | |
3891 | } | |
3892 | ||
6a3a010b MR |
3893 | /* Which registers to use for passing floating-point values between |
3894 | function calls, one of floating-point, general and both kinds of | |
3895 | registers. O32 and O64 use different register kinds for standard | |
3896 | MIPS and MIPS16 code; to make the handling of cases where we may | |
3897 | not know what kind of code is being used (e.g. no debug information) | |
3898 | easier we sometimes use both kinds. */ | |
3899 | ||
3900 | enum mips_fval_reg | |
3901 | { | |
3902 | mips_fval_fpr, | |
3903 | mips_fval_gpr, | |
3904 | mips_fval_both | |
3905 | }; | |
3906 | ||
6d82d43b AC |
3907 | /* O32 ABI stuff. */ |
3908 | ||
3909 | static CORE_ADDR | |
7d9b040b | 3910 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3911 | struct regcache *regcache, CORE_ADDR bp_addr, |
3912 | int nargs, struct value **args, CORE_ADDR sp, | |
3913 | int struct_return, CORE_ADDR struct_addr) | |
3914 | { | |
3915 | int argreg; | |
3916 | int float_argreg; | |
3917 | int argnum; | |
3918 | int len = 0; | |
3919 | int stack_offset = 0; | |
3920 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
e17a4113 | 3921 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 3922 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
3923 | |
3924 | /* For shared libraries, "t9" needs to point at the function | |
3925 | address. */ | |
4c7d22cb | 3926 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
6d82d43b AC |
3927 | |
3928 | /* Set the return address register to point to the entry point of | |
3929 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3930 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
6d82d43b AC |
3931 | |
3932 | /* First ensure that the stack and structure return address (if any) | |
3933 | are properly aligned. The stack has to be at least 64-bit | |
3934 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
3935 | aligned. For n32 and n64, stack frames need to be 128-bit |
3936 | aligned, so we round to this widest known alignment. */ | |
3937 | ||
5b03f266 AC |
3938 | sp = align_down (sp, 16); |
3939 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
3940 | |
3941 | /* Now make space on the stack for the args. */ | |
3942 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
3943 | { |
3944 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
3945 | int arglen = TYPE_LENGTH (arg_type); | |
3946 | ||
3947 | /* Align to double-word if necessary. */ | |
2afd3f0a | 3948 | if (mips_type_needs_double_align (arg_type)) |
1a69e1e4 | 3949 | len = align_up (len, MIPS32_REGSIZE * 2); |
968b5391 | 3950 | /* Allocate space on the stack. */ |
1a69e1e4 | 3951 | len += align_up (arglen, MIPS32_REGSIZE); |
968b5391 | 3952 | } |
5b03f266 | 3953 | sp -= align_up (len, 16); |
ebafbe83 MS |
3954 | |
3955 | if (mips_debug) | |
6d82d43b | 3956 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
3957 | "mips_o32_push_dummy_call: sp=%s allocated %ld\n", |
3958 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
3959 | |
3960 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3961 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 3962 | float_argreg = mips_fpa0_regnum (gdbarch); |
ebafbe83 | 3963 | |
bcb0cc15 | 3964 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3965 | if (struct_return) |
3966 | { | |
3967 | if (mips_debug) | |
3968 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
3969 | "mips_o32_push_dummy_call: " |
3970 | "struct_return reg=%d %s\n", | |
5af949e3 | 3971 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 3972 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 3973 | stack_offset += MIPS32_REGSIZE; |
ebafbe83 MS |
3974 | } |
3975 | ||
3976 | /* Now load as many as possible of the first arguments into | |
3977 | registers, and push the rest onto the stack. Loop thru args | |
3978 | from first to last. */ | |
3979 | for (argnum = 0; argnum < nargs; argnum++) | |
3980 | { | |
47a35522 | 3981 | const gdb_byte *val; |
ebafbe83 | 3982 | struct value *arg = args[argnum]; |
4991999e | 3983 | struct type *arg_type = check_typedef (value_type (arg)); |
ebafbe83 MS |
3984 | int len = TYPE_LENGTH (arg_type); |
3985 | enum type_code typecode = TYPE_CODE (arg_type); | |
3986 | ||
3987 | if (mips_debug) | |
3988 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3989 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3990 | argnum + 1, len, (int) typecode); |
3991 | ||
47a35522 | 3992 | val = value_contents (arg); |
46cac009 AC |
3993 | |
3994 | /* 32-bit ABIs always start floating point arguments in an | |
3995 | even-numbered floating point register. Round the FP register | |
3996 | up before the check to see if there are any FP registers | |
6a3a010b MR |
3997 | left. O32 targets also pass the FP in the integer registers |
3998 | so also round up normal registers. */ | |
74ed0bb4 | 3999 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
46cac009 AC |
4000 | { |
4001 | if ((float_argreg & 1)) | |
4002 | float_argreg++; | |
4003 | } | |
4004 | ||
4005 | /* Floating point arguments passed in registers have to be | |
6a3a010b MR |
4006 | treated specially. On 32-bit architectures, doubles are |
4007 | passed in register pairs; the even FP register gets the | |
4008 | low word, and the odd FP register gets the high word. | |
4009 | On O32, the first two floating point arguments are also | |
4010 | copied to general registers, following their memory order, | |
4011 | because MIPS16 functions don't use float registers for | |
4012 | arguments. This duplication of arguments in general | |
4013 | registers can't hurt non-MIPS16 functions, because those | |
4014 | registers are normally skipped. */ | |
46cac009 | 4015 | |
74ed0bb4 MD |
4016 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
4017 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
46cac009 | 4018 | { |
8b07f6d8 | 4019 | if (register_size (gdbarch, float_argreg) < 8 && len == 8) |
46cac009 | 4020 | { |
6a3a010b MR |
4021 | int freg_offset = gdbarch_byte_order (gdbarch) |
4022 | == BFD_ENDIAN_BIG ? 1 : 0; | |
46cac009 AC |
4023 | unsigned long regval; |
4024 | ||
6a3a010b MR |
4025 | /* First word. */ |
4026 | regval = extract_unsigned_integer (val, 4, byte_order); | |
46cac009 AC |
4027 | if (mips_debug) |
4028 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
6a3a010b MR |
4029 | float_argreg + freg_offset, |
4030 | phex (regval, 4)); | |
025bb325 | 4031 | regcache_cooked_write_unsigned (regcache, |
6a3a010b MR |
4032 | float_argreg++ + freg_offset, |
4033 | regval); | |
46cac009 AC |
4034 | if (mips_debug) |
4035 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4036 | argreg, phex (regval, 4)); | |
9c9acae0 | 4037 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 | 4038 | |
6a3a010b MR |
4039 | /* Second word. */ |
4040 | regval = extract_unsigned_integer (val + 4, 4, byte_order); | |
46cac009 AC |
4041 | if (mips_debug) |
4042 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
6a3a010b MR |
4043 | float_argreg - freg_offset, |
4044 | phex (regval, 4)); | |
025bb325 | 4045 | regcache_cooked_write_unsigned (regcache, |
6a3a010b MR |
4046 | float_argreg++ - freg_offset, |
4047 | regval); | |
46cac009 AC |
4048 | if (mips_debug) |
4049 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4050 | argreg, phex (regval, 4)); | |
9c9acae0 | 4051 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
4052 | } |
4053 | else | |
4054 | { | |
4055 | /* This is a floating point value that fits entirely | |
4056 | in a single register. */ | |
4057 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 4058 | above to ensure that it is even register aligned. */ |
e17a4113 | 4059 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
46cac009 AC |
4060 | if (mips_debug) |
4061 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4062 | float_argreg, phex (regval, len)); | |
025bb325 MS |
4063 | regcache_cooked_write_unsigned (regcache, |
4064 | float_argreg++, regval); | |
5b68030f JM |
4065 | /* Although two FP registers are reserved for each |
4066 | argument, only one corresponding integer register is | |
4067 | reserved. */ | |
46cac009 AC |
4068 | if (mips_debug) |
4069 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4070 | argreg, phex (regval, len)); | |
5b68030f | 4071 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
4072 | } |
4073 | /* Reserve space for the FP register. */ | |
1a69e1e4 | 4074 | stack_offset += align_up (len, MIPS32_REGSIZE); |
46cac009 AC |
4075 | } |
4076 | else | |
4077 | { | |
4078 | /* Copy the argument to general registers or the stack in | |
4079 | register-sized pieces. Large arguments are split between | |
4080 | registers and stack. */ | |
1a69e1e4 DJ |
4081 | /* Note: structs whose size is not a multiple of MIPS32_REGSIZE |
4082 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
4083 | them in registers where gcc sometimes puts them on the |
4084 | stack. For maximum compatibility, we will put them in | |
4085 | both places. */ | |
1a69e1e4 DJ |
4086 | int odd_sized_struct = (len > MIPS32_REGSIZE |
4087 | && len % MIPS32_REGSIZE != 0); | |
46cac009 AC |
4088 | /* Structures should be aligned to eight bytes (even arg registers) |
4089 | on MIPS_ABI_O32, if their first member has double precision. */ | |
2afd3f0a | 4090 | if (mips_type_needs_double_align (arg_type)) |
46cac009 AC |
4091 | { |
4092 | if ((argreg & 1)) | |
968b5391 MR |
4093 | { |
4094 | argreg++; | |
1a69e1e4 | 4095 | stack_offset += MIPS32_REGSIZE; |
968b5391 | 4096 | } |
46cac009 | 4097 | } |
46cac009 AC |
4098 | while (len > 0) |
4099 | { | |
4100 | /* Remember if the argument was written to the stack. */ | |
4101 | int stack_used_p = 0; | |
1a69e1e4 | 4102 | int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); |
46cac009 AC |
4103 | |
4104 | if (mips_debug) | |
4105 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4106 | partial_len); | |
4107 | ||
4108 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 4109 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 4110 | || odd_sized_struct) |
46cac009 AC |
4111 | { |
4112 | /* Should shorter than int integer values be | |
025bb325 | 4113 | promoted to int before being stored? */ |
46cac009 AC |
4114 | int longword_offset = 0; |
4115 | CORE_ADDR addr; | |
4116 | stack_used_p = 1; | |
46cac009 AC |
4117 | |
4118 | if (mips_debug) | |
4119 | { | |
5af949e3 UW |
4120 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
4121 | paddress (gdbarch, stack_offset)); | |
4122 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
4123 | paddress (gdbarch, longword_offset)); | |
46cac009 AC |
4124 | } |
4125 | ||
4126 | addr = sp + stack_offset + longword_offset; | |
4127 | ||
4128 | if (mips_debug) | |
4129 | { | |
4130 | int i; | |
5af949e3 UW |
4131 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
4132 | paddress (gdbarch, addr)); | |
46cac009 AC |
4133 | for (i = 0; i < partial_len; i++) |
4134 | { | |
6d82d43b | 4135 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
4136 | val[i] & 0xff); |
4137 | } | |
4138 | } | |
4139 | write_memory (addr, val, partial_len); | |
4140 | } | |
4141 | ||
4142 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 4143 | structs may go thru BOTH paths. */ |
46cac009 | 4144 | /* Write this portion of the argument to a general |
6d82d43b | 4145 | purpose register. */ |
74ed0bb4 | 4146 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
46cac009 | 4147 | { |
e17a4113 UW |
4148 | LONGEST regval = extract_signed_integer (val, partial_len, |
4149 | byte_order); | |
4246e332 | 4150 | /* Value may need to be sign extended, because |
1b13c4f6 | 4151 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
4152 | |
4153 | /* A non-floating-point argument being passed in a | |
4154 | general register. If a struct or union, and if | |
4155 | the remaining length is smaller than the register | |
4156 | size, we have to adjust the register value on | |
4157 | big endian targets. | |
4158 | ||
4159 | It does not seem to be necessary to do the | |
4160 | same for integral types. | |
4161 | ||
4162 | Also don't do this adjustment on O64 binaries. | |
4163 | ||
4164 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
4165 | outputting LE O32 with sizeof (struct) < | |
e914cb17 MR |
4166 | mips_abi_regsize(), generates a left shift |
4167 | as part of storing the argument in a register | |
4168 | (the left shift isn't generated when | |
1b13c4f6 | 4169 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
4170 | it is quite possible that this is GCC |
4171 | contradicting the LE/O32 ABI, GDB has not been | |
4172 | adjusted to accommodate this. Either someone | |
4173 | needs to demonstrate that the LE/O32 ABI | |
4174 | specifies such a left shift OR this new ABI gets | |
4175 | identified as such and GDB gets tweaked | |
4176 | accordingly. */ | |
4177 | ||
72a155b4 | 4178 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 4179 | && partial_len < MIPS32_REGSIZE |
06f9a1af MR |
4180 | && (typecode == TYPE_CODE_STRUCT |
4181 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 4182 | regval <<= ((MIPS32_REGSIZE - partial_len) |
9ecf7166 | 4183 | * TARGET_CHAR_BIT); |
46cac009 AC |
4184 | |
4185 | if (mips_debug) | |
4186 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
4187 | argreg, | |
1a69e1e4 | 4188 | phex (regval, MIPS32_REGSIZE)); |
9c9acae0 | 4189 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
46cac009 AC |
4190 | argreg++; |
4191 | ||
4192 | /* Prevent subsequent floating point arguments from | |
4193 | being passed in floating point registers. */ | |
74ed0bb4 | 4194 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
46cac009 AC |
4195 | } |
4196 | ||
4197 | len -= partial_len; | |
4198 | val += partial_len; | |
4199 | ||
b021a221 MS |
4200 | /* Compute the offset into the stack at which we will |
4201 | copy the next parameter. | |
46cac009 | 4202 | |
6d82d43b AC |
4203 | In older ABIs, the caller reserved space for |
4204 | registers that contained arguments. This was loosely | |
4205 | refered to as their "home". Consequently, space is | |
4206 | always allocated. */ | |
46cac009 | 4207 | |
1a69e1e4 | 4208 | stack_offset += align_up (partial_len, MIPS32_REGSIZE); |
46cac009 AC |
4209 | } |
4210 | } | |
4211 | if (mips_debug) | |
4212 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
4213 | } | |
4214 | ||
f10683bb | 4215 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4216 | |
46cac009 AC |
4217 | /* Return adjusted stack pointer. */ |
4218 | return sp; | |
4219 | } | |
4220 | ||
6d82d43b | 4221 | static enum return_value_convention |
6a3a010b | 4222 | mips_o32_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 | 4223 | struct type *type, struct regcache *regcache, |
47a35522 | 4224 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 4225 | { |
6a3a010b | 4226 | CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0; |
72a155b4 | 4227 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
6a3a010b MR |
4228 | int mips16 = mips_pc_is_mips16 (func_addr); |
4229 | enum mips_fval_reg fval_reg; | |
6d82d43b | 4230 | |
6a3a010b | 4231 | fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both; |
6d82d43b AC |
4232 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
4233 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
4234 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
4235 | return RETURN_VALUE_STRUCT_CONVENTION; | |
4236 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4237 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4238 | { | |
6a3a010b MR |
4239 | /* A single-precision floating-point value. If reading in or copying, |
4240 | then we get it from/put it to FP0 for standard MIPS code or GPR2 | |
4241 | for MIPS16 code. If writing out only, then we put it to both FP0 | |
4242 | and GPR2. We do not support reading in with no function known, if | |
4243 | this safety check ever triggers, then we'll have to try harder. */ | |
4244 | gdb_assert (function || !readbuf); | |
6d82d43b | 4245 | if (mips_debug) |
6a3a010b MR |
4246 | switch (fval_reg) |
4247 | { | |
4248 | case mips_fval_fpr: | |
4249 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
4250 | break; | |
4251 | case mips_fval_gpr: | |
4252 | fprintf_unfiltered (gdb_stderr, "Return float in $2\n"); | |
4253 | break; | |
4254 | case mips_fval_both: | |
4255 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n"); | |
4256 | break; | |
4257 | } | |
4258 | if (fval_reg != mips_fval_gpr) | |
4259 | mips_xfer_register (gdbarch, regcache, | |
4260 | (gdbarch_num_regs (gdbarch) | |
4261 | + mips_regnum (gdbarch)->fp0), | |
4262 | TYPE_LENGTH (type), | |
4263 | gdbarch_byte_order (gdbarch), | |
4264 | readbuf, writebuf, 0); | |
4265 | if (fval_reg != mips_fval_fpr) | |
4266 | mips_xfer_register (gdbarch, regcache, | |
4267 | gdbarch_num_regs (gdbarch) + 2, | |
4268 | TYPE_LENGTH (type), | |
4269 | gdbarch_byte_order (gdbarch), | |
4270 | readbuf, writebuf, 0); | |
6d82d43b AC |
4271 | return RETURN_VALUE_REGISTER_CONVENTION; |
4272 | } | |
4273 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4274 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4275 | { | |
6a3a010b MR |
4276 | /* A double-precision floating-point value. If reading in or copying, |
4277 | then we get it from/put it to FP1 and FP0 for standard MIPS code or | |
4278 | GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it | |
4279 | to both FP1/FP0 and GPR2/GPR3. We do not support reading in with | |
4280 | no function known, if this safety check ever triggers, then we'll | |
4281 | have to try harder. */ | |
4282 | gdb_assert (function || !readbuf); | |
6d82d43b | 4283 | if (mips_debug) |
6a3a010b MR |
4284 | switch (fval_reg) |
4285 | { | |
4286 | case mips_fval_fpr: | |
4287 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
4288 | break; | |
4289 | case mips_fval_gpr: | |
4290 | fprintf_unfiltered (gdb_stderr, "Return float in $2/$3\n"); | |
4291 | break; | |
4292 | case mips_fval_both: | |
4293 | fprintf_unfiltered (gdb_stderr, | |
4294 | "Return float in $fp1/$fp0 and $2/$3\n"); | |
4295 | break; | |
4296 | } | |
4297 | if (fval_reg != mips_fval_gpr) | |
6d82d43b | 4298 | { |
6a3a010b MR |
4299 | /* The most significant part goes in FP1, and the least significant |
4300 | in FP0. */ | |
4301 | switch (gdbarch_byte_order (gdbarch)) | |
4302 | { | |
4303 | case BFD_ENDIAN_LITTLE: | |
4304 | mips_xfer_register (gdbarch, regcache, | |
4305 | (gdbarch_num_regs (gdbarch) | |
4306 | + mips_regnum (gdbarch)->fp0 + 0), | |
4307 | 4, gdbarch_byte_order (gdbarch), | |
4308 | readbuf, writebuf, 0); | |
4309 | mips_xfer_register (gdbarch, regcache, | |
4310 | (gdbarch_num_regs (gdbarch) | |
4311 | + mips_regnum (gdbarch)->fp0 + 1), | |
4312 | 4, gdbarch_byte_order (gdbarch), | |
4313 | readbuf, writebuf, 4); | |
4314 | break; | |
4315 | case BFD_ENDIAN_BIG: | |
4316 | mips_xfer_register (gdbarch, regcache, | |
4317 | (gdbarch_num_regs (gdbarch) | |
4318 | + mips_regnum (gdbarch)->fp0 + 1), | |
4319 | 4, gdbarch_byte_order (gdbarch), | |
4320 | readbuf, writebuf, 0); | |
4321 | mips_xfer_register (gdbarch, regcache, | |
4322 | (gdbarch_num_regs (gdbarch) | |
4323 | + mips_regnum (gdbarch)->fp0 + 0), | |
4324 | 4, gdbarch_byte_order (gdbarch), | |
4325 | readbuf, writebuf, 4); | |
4326 | break; | |
4327 | default: | |
4328 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
4329 | } | |
4330 | } | |
4331 | if (fval_reg != mips_fval_fpr) | |
4332 | { | |
4333 | /* The two 32-bit parts are always placed in GPR2 and GPR3 | |
4334 | following these registers' memory order. */ | |
ba32f989 | 4335 | mips_xfer_register (gdbarch, regcache, |
6a3a010b | 4336 | gdbarch_num_regs (gdbarch) + 2, |
72a155b4 | 4337 | 4, gdbarch_byte_order (gdbarch), |
4c6b5505 | 4338 | readbuf, writebuf, 0); |
ba32f989 | 4339 | mips_xfer_register (gdbarch, regcache, |
6a3a010b | 4340 | gdbarch_num_regs (gdbarch) + 3, |
72a155b4 | 4341 | 4, gdbarch_byte_order (gdbarch), |
4c6b5505 | 4342 | readbuf, writebuf, 4); |
6d82d43b AC |
4343 | } |
4344 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4345 | } | |
4346 | #if 0 | |
4347 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4348 | && TYPE_NFIELDS (type) <= 2 | |
4349 | && TYPE_NFIELDS (type) >= 1 | |
4350 | && ((TYPE_NFIELDS (type) == 1 | |
4351 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4352 | == TYPE_CODE_FLT)) | |
4353 | || (TYPE_NFIELDS (type) == 2 | |
4354 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4355 | == TYPE_CODE_FLT) | |
4356 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
4357 | == TYPE_CODE_FLT))) | |
4358 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4359 | { | |
4360 | /* A struct that contains one or two floats. Each value is part | |
4361 | in the least significant part of their floating point | |
4362 | register.. */ | |
870cd05e | 4363 | gdb_byte reg[MAX_REGISTER_SIZE]; |
6d82d43b AC |
4364 | int regnum; |
4365 | int field; | |
72a155b4 | 4366 | for (field = 0, regnum = mips_regnum (gdbarch)->fp0; |
6d82d43b AC |
4367 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
4368 | { | |
4369 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
4370 | / TARGET_CHAR_BIT); | |
4371 | if (mips_debug) | |
4372 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
4373 | offset); | |
ba32f989 DJ |
4374 | mips_xfer_register (gdbarch, regcache, |
4375 | gdbarch_num_regs (gdbarch) + regnum, | |
6d82d43b | 4376 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
72a155b4 | 4377 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4378 | readbuf, writebuf, offset); |
6d82d43b AC |
4379 | } |
4380 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4381 | } | |
4382 | #endif | |
4383 | #if 0 | |
4384 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4385 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4386 | { | |
4387 | /* A structure or union. Extract the left justified value, | |
4388 | regardless of the byte order. I.e. DO NOT USE | |
4389 | mips_xfer_lower. */ | |
4390 | int offset; | |
4391 | int regnum; | |
4c7d22cb | 4392 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 4393 | offset < TYPE_LENGTH (type); |
72a155b4 | 4394 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 4395 | { |
72a155b4 | 4396 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
4397 | if (offset + xfer > TYPE_LENGTH (type)) |
4398 | xfer = TYPE_LENGTH (type) - offset; | |
4399 | if (mips_debug) | |
4400 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
4401 | offset, xfer, regnum); | |
ba32f989 DJ |
4402 | mips_xfer_register (gdbarch, regcache, |
4403 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
6d82d43b AC |
4404 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
4405 | } | |
4406 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4407 | } | |
4408 | #endif | |
4409 | else | |
4410 | { | |
4411 | /* A scalar extract each part but least-significant-byte | |
4412 | justified. o32 thinks registers are 4 byte, regardless of | |
1a69e1e4 | 4413 | the ISA. */ |
6d82d43b AC |
4414 | int offset; |
4415 | int regnum; | |
4c7d22cb | 4416 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 4417 | offset < TYPE_LENGTH (type); |
1a69e1e4 | 4418 | offset += MIPS32_REGSIZE, regnum++) |
6d82d43b | 4419 | { |
1a69e1e4 | 4420 | int xfer = MIPS32_REGSIZE; |
6d82d43b AC |
4421 | if (offset + xfer > TYPE_LENGTH (type)) |
4422 | xfer = TYPE_LENGTH (type) - offset; | |
4423 | if (mips_debug) | |
4424 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4425 | offset, xfer, regnum); | |
ba32f989 DJ |
4426 | mips_xfer_register (gdbarch, regcache, |
4427 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
72a155b4 | 4428 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4429 | readbuf, writebuf, offset); |
6d82d43b AC |
4430 | } |
4431 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4432 | } | |
4433 | } | |
4434 | ||
4435 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
4436 | ABI. */ | |
46cac009 AC |
4437 | |
4438 | static CORE_ADDR | |
7d9b040b | 4439 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4440 | struct regcache *regcache, CORE_ADDR bp_addr, |
4441 | int nargs, | |
4442 | struct value **args, CORE_ADDR sp, | |
4443 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
4444 | { |
4445 | int argreg; | |
4446 | int float_argreg; | |
4447 | int argnum; | |
4448 | int len = 0; | |
4449 | int stack_offset = 0; | |
480d3dd2 | 4450 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 4451 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 4452 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 4453 | |
25ab4790 AC |
4454 | /* For shared libraries, "t9" needs to point at the function |
4455 | address. */ | |
4c7d22cb | 4456 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
4457 | |
4458 | /* Set the return address register to point to the entry point of | |
4459 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 4460 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 4461 | |
46cac009 AC |
4462 | /* First ensure that the stack and structure return address (if any) |
4463 | are properly aligned. The stack has to be at least 64-bit | |
4464 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4465 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4466 | aligned, so we round to this widest known alignment. */ | |
4467 | ||
5b03f266 AC |
4468 | sp = align_down (sp, 16); |
4469 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
4470 | |
4471 | /* Now make space on the stack for the args. */ | |
4472 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
4473 | { |
4474 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
4475 | int arglen = TYPE_LENGTH (arg_type); | |
4476 | ||
968b5391 | 4477 | /* Allocate space on the stack. */ |
1a69e1e4 | 4478 | len += align_up (arglen, MIPS64_REGSIZE); |
968b5391 | 4479 | } |
5b03f266 | 4480 | sp -= align_up (len, 16); |
46cac009 AC |
4481 | |
4482 | if (mips_debug) | |
6d82d43b | 4483 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
4484 | "mips_o64_push_dummy_call: sp=%s allocated %ld\n", |
4485 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
46cac009 AC |
4486 | |
4487 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 4488 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 4489 | float_argreg = mips_fpa0_regnum (gdbarch); |
46cac009 AC |
4490 | |
4491 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
4492 | if (struct_return) | |
4493 | { | |
4494 | if (mips_debug) | |
4495 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
4496 | "mips_o64_push_dummy_call: " |
4497 | "struct_return reg=%d %s\n", | |
5af949e3 | 4498 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 4499 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 4500 | stack_offset += MIPS64_REGSIZE; |
46cac009 AC |
4501 | } |
4502 | ||
4503 | /* Now load as many as possible of the first arguments into | |
4504 | registers, and push the rest onto the stack. Loop thru args | |
4505 | from first to last. */ | |
4506 | for (argnum = 0; argnum < nargs; argnum++) | |
4507 | { | |
47a35522 | 4508 | const gdb_byte *val; |
930bd0e0 | 4509 | gdb_byte valbuf[MAX_REGISTER_SIZE]; |
46cac009 | 4510 | struct value *arg = args[argnum]; |
4991999e | 4511 | struct type *arg_type = check_typedef (value_type (arg)); |
46cac009 AC |
4512 | int len = TYPE_LENGTH (arg_type); |
4513 | enum type_code typecode = TYPE_CODE (arg_type); | |
4514 | ||
4515 | if (mips_debug) | |
4516 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4517 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
4518 | argnum + 1, len, (int) typecode); |
4519 | ||
47a35522 | 4520 | val = value_contents (arg); |
ebafbe83 | 4521 | |
930bd0e0 KB |
4522 | /* Function pointer arguments to mips16 code need to be made into |
4523 | mips16 pointers. */ | |
4524 | if (typecode == TYPE_CODE_PTR | |
4525 | && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC) | |
4526 | { | |
4527 | CORE_ADDR addr = extract_signed_integer (value_contents (arg), | |
4528 | len, byte_order); | |
4529 | if (mips_pc_is_mips16 (addr)) | |
4530 | { | |
4531 | store_signed_integer (valbuf, len, byte_order, | |
4532 | make_mips16_addr (addr)); | |
4533 | val = valbuf; | |
4534 | } | |
4535 | } | |
4536 | ||
ebafbe83 | 4537 | /* Floating point arguments passed in registers have to be |
6a3a010b MR |
4538 | treated specially. On 32-bit architectures, doubles are |
4539 | passed in register pairs; the even FP register gets the | |
4540 | low word, and the odd FP register gets the high word. | |
4541 | On O64, the first two floating point arguments are also | |
4542 | copied to general registers, because MIPS16 functions | |
4543 | don't use float registers for arguments. This duplication | |
4544 | of arguments in general registers can't hurt non-MIPS16 | |
4545 | functions because those registers are normally skipped. */ | |
ebafbe83 | 4546 | |
74ed0bb4 MD |
4547 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
4548 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
ebafbe83 | 4549 | { |
e17a4113 | 4550 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
2afd3f0a MR |
4551 | if (mips_debug) |
4552 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4553 | float_argreg, phex (regval, len)); | |
9c9acae0 | 4554 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
2afd3f0a MR |
4555 | if (mips_debug) |
4556 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4557 | argreg, phex (regval, len)); | |
9c9acae0 | 4558 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
2afd3f0a | 4559 | argreg++; |
ebafbe83 | 4560 | /* Reserve space for the FP register. */ |
1a69e1e4 | 4561 | stack_offset += align_up (len, MIPS64_REGSIZE); |
ebafbe83 MS |
4562 | } |
4563 | else | |
4564 | { | |
4565 | /* Copy the argument to general registers or the stack in | |
4566 | register-sized pieces. Large arguments are split between | |
4567 | registers and stack. */ | |
1a69e1e4 | 4568 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
4569 | are treated specially: Irix cc passes them in registers |
4570 | where gcc sometimes puts them on the stack. For maximum | |
4571 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
4572 | int odd_sized_struct = (len > MIPS64_REGSIZE |
4573 | && len % MIPS64_REGSIZE != 0); | |
ebafbe83 MS |
4574 | while (len > 0) |
4575 | { | |
4576 | /* Remember if the argument was written to the stack. */ | |
4577 | int stack_used_p = 0; | |
1a69e1e4 | 4578 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
ebafbe83 MS |
4579 | |
4580 | if (mips_debug) | |
4581 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4582 | partial_len); | |
4583 | ||
4584 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 4585 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 4586 | || odd_sized_struct) |
ebafbe83 MS |
4587 | { |
4588 | /* Should shorter than int integer values be | |
025bb325 | 4589 | promoted to int before being stored? */ |
ebafbe83 MS |
4590 | int longword_offset = 0; |
4591 | CORE_ADDR addr; | |
4592 | stack_used_p = 1; | |
72a155b4 | 4593 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ebafbe83 | 4594 | { |
1a69e1e4 DJ |
4595 | if ((typecode == TYPE_CODE_INT |
4596 | || typecode == TYPE_CODE_PTR | |
4597 | || typecode == TYPE_CODE_FLT) | |
4598 | && len <= 4) | |
4599 | longword_offset = MIPS64_REGSIZE - len; | |
ebafbe83 MS |
4600 | } |
4601 | ||
4602 | if (mips_debug) | |
4603 | { | |
5af949e3 UW |
4604 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
4605 | paddress (gdbarch, stack_offset)); | |
4606 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
4607 | paddress (gdbarch, longword_offset)); | |
ebafbe83 MS |
4608 | } |
4609 | ||
4610 | addr = sp + stack_offset + longword_offset; | |
4611 | ||
4612 | if (mips_debug) | |
4613 | { | |
4614 | int i; | |
5af949e3 UW |
4615 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
4616 | paddress (gdbarch, addr)); | |
ebafbe83 MS |
4617 | for (i = 0; i < partial_len; i++) |
4618 | { | |
6d82d43b | 4619 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
4620 | val[i] & 0xff); |
4621 | } | |
4622 | } | |
4623 | write_memory (addr, val, partial_len); | |
4624 | } | |
4625 | ||
4626 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 4627 | structs may go thru BOTH paths. */ |
ebafbe83 | 4628 | /* Write this portion of the argument to a general |
6d82d43b | 4629 | purpose register. */ |
74ed0bb4 | 4630 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
ebafbe83 | 4631 | { |
e17a4113 UW |
4632 | LONGEST regval = extract_signed_integer (val, partial_len, |
4633 | byte_order); | |
4246e332 | 4634 | /* Value may need to be sign extended, because |
1b13c4f6 | 4635 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
4636 | |
4637 | /* A non-floating-point argument being passed in a | |
4638 | general register. If a struct or union, and if | |
4639 | the remaining length is smaller than the register | |
4640 | size, we have to adjust the register value on | |
4641 | big endian targets. | |
4642 | ||
4643 | It does not seem to be necessary to do the | |
025bb325 | 4644 | same for integral types. */ |
480d3dd2 | 4645 | |
72a155b4 | 4646 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 4647 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
4648 | && (typecode == TYPE_CODE_STRUCT |
4649 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 4650 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 4651 | * TARGET_CHAR_BIT); |
ebafbe83 MS |
4652 | |
4653 | if (mips_debug) | |
4654 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
4655 | argreg, | |
1a69e1e4 | 4656 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 4657 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
ebafbe83 MS |
4658 | argreg++; |
4659 | ||
4660 | /* Prevent subsequent floating point arguments from | |
4661 | being passed in floating point registers. */ | |
74ed0bb4 | 4662 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
ebafbe83 MS |
4663 | } |
4664 | ||
4665 | len -= partial_len; | |
4666 | val += partial_len; | |
4667 | ||
b021a221 MS |
4668 | /* Compute the offset into the stack at which we will |
4669 | copy the next parameter. | |
ebafbe83 | 4670 | |
6d82d43b AC |
4671 | In older ABIs, the caller reserved space for |
4672 | registers that contained arguments. This was loosely | |
4673 | refered to as their "home". Consequently, space is | |
4674 | always allocated. */ | |
ebafbe83 | 4675 | |
1a69e1e4 | 4676 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
ebafbe83 MS |
4677 | } |
4678 | } | |
4679 | if (mips_debug) | |
4680 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
4681 | } | |
4682 | ||
f10683bb | 4683 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4684 | |
ebafbe83 MS |
4685 | /* Return adjusted stack pointer. */ |
4686 | return sp; | |
4687 | } | |
4688 | ||
9c8fdbfa | 4689 | static enum return_value_convention |
6a3a010b | 4690 | mips_o64_return_value (struct gdbarch *gdbarch, struct value *function, |
9c8fdbfa | 4691 | struct type *type, struct regcache *regcache, |
47a35522 | 4692 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 4693 | { |
6a3a010b | 4694 | CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0; |
72a155b4 | 4695 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
6a3a010b MR |
4696 | int mips16 = mips_pc_is_mips16 (func_addr); |
4697 | enum mips_fval_reg fval_reg; | |
7a076fd2 | 4698 | |
6a3a010b | 4699 | fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both; |
7a076fd2 FF |
4700 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
4701 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
4702 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
4703 | return RETURN_VALUE_STRUCT_CONVENTION; | |
74ed0bb4 | 4704 | else if (fp_register_arg_p (gdbarch, TYPE_CODE (type), type)) |
7a076fd2 | 4705 | { |
6a3a010b MR |
4706 | /* A floating-point value. If reading in or copying, then we get it |
4707 | from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code. | |
4708 | If writing out only, then we put it to both FP0 and GPR2. We do | |
4709 | not support reading in with no function known, if this safety | |
4710 | check ever triggers, then we'll have to try harder. */ | |
4711 | gdb_assert (function || !readbuf); | |
7a076fd2 | 4712 | if (mips_debug) |
6a3a010b MR |
4713 | switch (fval_reg) |
4714 | { | |
4715 | case mips_fval_fpr: | |
4716 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
4717 | break; | |
4718 | case mips_fval_gpr: | |
4719 | fprintf_unfiltered (gdb_stderr, "Return float in $2\n"); | |
4720 | break; | |
4721 | case mips_fval_both: | |
4722 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n"); | |
4723 | break; | |
4724 | } | |
4725 | if (fval_reg != mips_fval_gpr) | |
4726 | mips_xfer_register (gdbarch, regcache, | |
4727 | (gdbarch_num_regs (gdbarch) | |
4728 | + mips_regnum (gdbarch)->fp0), | |
4729 | TYPE_LENGTH (type), | |
4730 | gdbarch_byte_order (gdbarch), | |
4731 | readbuf, writebuf, 0); | |
4732 | if (fval_reg != mips_fval_fpr) | |
4733 | mips_xfer_register (gdbarch, regcache, | |
4734 | gdbarch_num_regs (gdbarch) + 2, | |
4735 | TYPE_LENGTH (type), | |
4736 | gdbarch_byte_order (gdbarch), | |
4737 | readbuf, writebuf, 0); | |
7a076fd2 FF |
4738 | return RETURN_VALUE_REGISTER_CONVENTION; |
4739 | } | |
4740 | else | |
4741 | { | |
4742 | /* A scalar extract each part but least-significant-byte | |
025bb325 | 4743 | justified. */ |
7a076fd2 FF |
4744 | int offset; |
4745 | int regnum; | |
4746 | for (offset = 0, regnum = MIPS_V0_REGNUM; | |
4747 | offset < TYPE_LENGTH (type); | |
1a69e1e4 | 4748 | offset += MIPS64_REGSIZE, regnum++) |
7a076fd2 | 4749 | { |
1a69e1e4 | 4750 | int xfer = MIPS64_REGSIZE; |
7a076fd2 FF |
4751 | if (offset + xfer > TYPE_LENGTH (type)) |
4752 | xfer = TYPE_LENGTH (type) - offset; | |
4753 | if (mips_debug) | |
4754 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4755 | offset, xfer, regnum); | |
ba32f989 DJ |
4756 | mips_xfer_register (gdbarch, regcache, |
4757 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 4758 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 4759 | readbuf, writebuf, offset); |
7a076fd2 FF |
4760 | } |
4761 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4762 | } | |
6d82d43b AC |
4763 | } |
4764 | ||
dd824b04 DJ |
4765 | /* Floating point register management. |
4766 | ||
4767 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
4768 | 64bit operations, these early MIPS cpus treat fp register pairs | |
4769 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
4770 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
4771 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
4772 | double precision floats into two 32-bit chunks and store them in | |
4773 | consecutive fp regs. To display 64-bit floats stored in this | |
4774 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
4775 | Throw in user-configurable endianness and you have a real mess. | |
4776 | ||
4777 | The way this works is: | |
4778 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
4779 | double-precision value will be split across two logical registers. | |
4780 | The lower-numbered logical register will hold the low-order bits, | |
4781 | regardless of the processor's endianness. | |
4782 | - If we are on a 64-bit processor, and we are looking for a | |
4783 | single-precision value, it will be in the low ordered bits | |
4784 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
4785 | save slot in memory. | |
4786 | - If we are in 64-bit mode, everything is straightforward. | |
4787 | ||
4788 | Note that this code only deals with "live" registers at the top of the | |
4789 | stack. We will attempt to deal with saved registers later, when | |
025bb325 | 4790 | the raw/cooked register interface is in place. (We need a general |
dd824b04 DJ |
4791 | interface that can deal with dynamic saved register sizes -- fp |
4792 | regs could be 32 bits wide in one frame and 64 on the frame above | |
4793 | and below). */ | |
4794 | ||
4795 | /* Copy a 32-bit single-precision value from the current frame | |
4796 | into rare_buffer. */ | |
4797 | ||
4798 | static void | |
e11c53d2 | 4799 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
47a35522 | 4800 | gdb_byte *rare_buffer) |
dd824b04 | 4801 | { |
72a155b4 UW |
4802 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4803 | int raw_size = register_size (gdbarch, regno); | |
47a35522 | 4804 | gdb_byte *raw_buffer = alloca (raw_size); |
dd824b04 | 4805 | |
e11c53d2 | 4806 | if (!frame_register_read (frame, regno, raw_buffer)) |
c9f4d572 | 4807 | error (_("can't read register %d (%s)"), |
72a155b4 | 4808 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
4809 | if (raw_size == 8) |
4810 | { | |
4811 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 4812 | 32 bits. */ |
dd824b04 DJ |
4813 | int offset; |
4814 | ||
72a155b4 | 4815 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 DJ |
4816 | offset = 4; |
4817 | else | |
4818 | offset = 0; | |
4819 | ||
4820 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
4821 | } | |
4822 | else | |
4823 | { | |
4824 | memcpy (rare_buffer, raw_buffer, 4); | |
4825 | } | |
4826 | } | |
4827 | ||
4828 | /* Copy a 64-bit double-precision value from the current frame into | |
4829 | rare_buffer. This may include getting half of it from the next | |
4830 | register. */ | |
4831 | ||
4832 | static void | |
e11c53d2 | 4833 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
47a35522 | 4834 | gdb_byte *rare_buffer) |
dd824b04 | 4835 | { |
72a155b4 UW |
4836 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4837 | int raw_size = register_size (gdbarch, regno); | |
dd824b04 | 4838 | |
9c9acae0 | 4839 | if (raw_size == 8 && !mips2_fp_compat (frame)) |
dd824b04 DJ |
4840 | { |
4841 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 4842 | all 64 bits. */ |
e11c53d2 | 4843 | if (!frame_register_read (frame, regno, rare_buffer)) |
c9f4d572 | 4844 | error (_("can't read register %d (%s)"), |
72a155b4 | 4845 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
4846 | } |
4847 | else | |
4848 | { | |
72a155b4 | 4849 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
82e91389 | 4850 | |
72a155b4 | 4851 | if ((rawnum - mips_regnum (gdbarch)->fp0) & 1) |
dd824b04 | 4852 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
4853 | _("mips_read_fp_register_double: bad access to " |
4854 | "odd-numbered FP register")); | |
dd824b04 DJ |
4855 | |
4856 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 4857 | each register. */ |
72a155b4 | 4858 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 | 4859 | { |
e11c53d2 AC |
4860 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
4861 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 4862 | } |
361d1df0 | 4863 | else |
dd824b04 | 4864 | { |
e11c53d2 AC |
4865 | mips_read_fp_register_single (frame, regno, rare_buffer); |
4866 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
4867 | } |
4868 | } | |
4869 | } | |
4870 | ||
c906108c | 4871 | static void |
e11c53d2 AC |
4872 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
4873 | int regnum) | |
025bb325 | 4874 | { /* Do values for FP (float) regs. */ |
72a155b4 | 4875 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 4876 | gdb_byte *raw_buffer; |
025bb325 | 4877 | double doub, flt1; /* Doubles extracted from raw hex data. */ |
3903d437 | 4878 | int inv1, inv2; |
c5aa993b | 4879 | |
025bb325 MS |
4880 | raw_buffer = alloca (2 * register_size (gdbarch, |
4881 | mips_regnum (gdbarch)->fp0)); | |
c906108c | 4882 | |
72a155b4 | 4883 | fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum)); |
c9f4d572 | 4884 | fprintf_filtered (file, "%*s", |
72a155b4 | 4885 | 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)), |
e11c53d2 | 4886 | ""); |
f0ef6b29 | 4887 | |
72a155b4 | 4888 | if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame)) |
c906108c | 4889 | { |
79a45b7d TT |
4890 | struct value_print_options opts; |
4891 | ||
f0ef6b29 KB |
4892 | /* 4-byte registers: Print hex and floating. Also print even |
4893 | numbered registers as doubles. */ | |
e11c53d2 | 4894 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
025bb325 MS |
4895 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, |
4896 | raw_buffer, &inv1); | |
c5aa993b | 4897 | |
79a45b7d | 4898 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
4899 | print_scalar_formatted (raw_buffer, |
4900 | builtin_type (gdbarch)->builtin_uint32, | |
4901 | &opts, 'w', file); | |
dd824b04 | 4902 | |
e11c53d2 | 4903 | fprintf_filtered (file, " flt: "); |
1adad886 | 4904 | if (inv1) |
e11c53d2 | 4905 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4906 | else |
e11c53d2 | 4907 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4908 | |
72a155b4 | 4909 | if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0) |
f0ef6b29 | 4910 | { |
e11c53d2 | 4911 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
27067745 UW |
4912 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
4913 | raw_buffer, &inv2); | |
1adad886 | 4914 | |
e11c53d2 | 4915 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4916 | if (inv2) |
e11c53d2 | 4917 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 4918 | else |
e11c53d2 | 4919 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 4920 | } |
c906108c SS |
4921 | } |
4922 | else | |
dd824b04 | 4923 | { |
79a45b7d TT |
4924 | struct value_print_options opts; |
4925 | ||
f0ef6b29 | 4926 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 4927 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
27067745 UW |
4928 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, |
4929 | raw_buffer, &inv1); | |
c906108c | 4930 | |
e11c53d2 | 4931 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
27067745 UW |
4932 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
4933 | raw_buffer, &inv2); | |
f0ef6b29 | 4934 | |
79a45b7d | 4935 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
4936 | print_scalar_formatted (raw_buffer, |
4937 | builtin_type (gdbarch)->builtin_uint64, | |
4938 | &opts, 'g', file); | |
f0ef6b29 | 4939 | |
e11c53d2 | 4940 | fprintf_filtered (file, " flt: "); |
1adad886 | 4941 | if (inv1) |
e11c53d2 | 4942 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 4943 | else |
e11c53d2 | 4944 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4945 | |
e11c53d2 | 4946 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4947 | if (inv2) |
e11c53d2 | 4948 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 4949 | else |
e11c53d2 | 4950 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
4951 | } |
4952 | } | |
4953 | ||
4954 | static void | |
e11c53d2 | 4955 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
0cc93a06 | 4956 | int regnum) |
f0ef6b29 | 4957 | { |
a4b8ebc8 | 4958 | struct gdbarch *gdbarch = get_frame_arch (frame); |
f0ef6b29 | 4959 | int offset; |
79a45b7d | 4960 | struct value_print_options opts; |
de15c4ab | 4961 | struct value *val; |
1adad886 | 4962 | |
004159a2 | 4963 | if (mips_float_register_p (gdbarch, regnum)) |
f0ef6b29 | 4964 | { |
e11c53d2 | 4965 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4966 | return; |
4967 | } | |
4968 | ||
de15c4ab PA |
4969 | val = get_frame_register_value (frame, regnum); |
4970 | if (value_optimized_out (val)) | |
f0ef6b29 | 4971 | { |
c9f4d572 | 4972 | fprintf_filtered (file, "%s: [Invalid]", |
72a155b4 | 4973 | gdbarch_register_name (gdbarch, regnum)); |
f0ef6b29 | 4974 | return; |
c906108c | 4975 | } |
f0ef6b29 | 4976 | |
72a155b4 | 4977 | fputs_filtered (gdbarch_register_name (gdbarch, regnum), file); |
f0ef6b29 KB |
4978 | |
4979 | /* The problem with printing numeric register names (r26, etc.) is that | |
4980 | the user can't use them on input. Probably the best solution is to | |
4981 | fix it so that either the numeric or the funky (a2, etc.) names | |
4982 | are accepted on input. */ | |
4983 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 4984 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 4985 | else |
e11c53d2 | 4986 | fprintf_filtered (file, ": "); |
f0ef6b29 | 4987 | |
79a45b7d | 4988 | get_formatted_print_options (&opts, 'x'); |
de15c4ab PA |
4989 | val_print_scalar_formatted (value_type (val), |
4990 | value_contents_for_printing (val), | |
4991 | value_embedded_offset (val), | |
4992 | val, | |
4993 | &opts, 0, file); | |
c906108c SS |
4994 | } |
4995 | ||
f0ef6b29 KB |
4996 | /* Replacement for generic do_registers_info. |
4997 | Print regs in pretty columns. */ | |
4998 | ||
4999 | static int | |
e11c53d2 AC |
5000 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
5001 | int regnum) | |
f0ef6b29 | 5002 | { |
e11c53d2 AC |
5003 | fprintf_filtered (file, " "); |
5004 | mips_print_fp_register (file, frame, regnum); | |
5005 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
5006 | return regnum + 1; |
5007 | } | |
5008 | ||
5009 | ||
025bb325 | 5010 | /* Print a row's worth of GP (int) registers, with name labels above. */ |
c906108c SS |
5011 | |
5012 | static int | |
e11c53d2 | 5013 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 5014 | int start_regnum) |
c906108c | 5015 | { |
a4b8ebc8 | 5016 | struct gdbarch *gdbarch = get_frame_arch (frame); |
025bb325 | 5017 | /* Do values for GP (int) regs. */ |
47a35522 | 5018 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
025bb325 MS |
5019 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols |
5020 | per row. */ | |
c906108c | 5021 | int col, byte; |
a4b8ebc8 | 5022 | int regnum; |
c906108c | 5023 | |
025bb325 | 5024 | /* For GP registers, we print a separate row of names above the vals. */ |
a4b8ebc8 | 5025 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
5026 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
5027 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 5028 | regnum++) |
c906108c | 5029 | { |
72a155b4 | 5030 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 5031 | continue; /* unused register */ |
004159a2 | 5032 | if (mips_float_register_p (gdbarch, regnum)) |
025bb325 | 5033 | break; /* End the row: reached FP register. */ |
0cc93a06 | 5034 | /* Large registers are handled separately. */ |
72a155b4 | 5035 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
5036 | { |
5037 | if (col > 0) | |
5038 | break; /* End the row before this register. */ | |
5039 | ||
5040 | /* Print this register on a row by itself. */ | |
5041 | mips_print_register (file, frame, regnum); | |
5042 | fprintf_filtered (file, "\n"); | |
5043 | return regnum + 1; | |
5044 | } | |
d05f6826 DJ |
5045 | if (col == 0) |
5046 | fprintf_filtered (file, " "); | |
6d82d43b | 5047 | fprintf_filtered (file, |
72a155b4 UW |
5048 | mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s", |
5049 | gdbarch_register_name (gdbarch, regnum)); | |
c906108c SS |
5050 | col++; |
5051 | } | |
d05f6826 DJ |
5052 | |
5053 | if (col == 0) | |
5054 | return regnum; | |
5055 | ||
025bb325 | 5056 | /* Print the R0 to R31 names. */ |
72a155b4 | 5057 | if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS) |
f57d151a | 5058 | fprintf_filtered (file, "\n R%-4d", |
72a155b4 | 5059 | start_regnum % gdbarch_num_regs (gdbarch)); |
20e6603c AC |
5060 | else |
5061 | fprintf_filtered (file, "\n "); | |
c906108c | 5062 | |
025bb325 | 5063 | /* Now print the values in hex, 4 or 8 to the row. */ |
a4b8ebc8 | 5064 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
5065 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
5066 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 5067 | regnum++) |
c906108c | 5068 | { |
72a155b4 | 5069 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 5070 | continue; /* unused register */ |
004159a2 | 5071 | if (mips_float_register_p (gdbarch, regnum)) |
025bb325 | 5072 | break; /* End row: reached FP register. */ |
72a155b4 | 5073 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
5074 | break; /* End row: large register. */ |
5075 | ||
c906108c | 5076 | /* OK: get the data in raw format. */ |
e11c53d2 | 5077 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c9f4d572 | 5078 | error (_("can't read register %d (%s)"), |
72a155b4 | 5079 | regnum, gdbarch_register_name (gdbarch, regnum)); |
c906108c | 5080 | /* pad small registers */ |
4246e332 | 5081 | for (byte = 0; |
72a155b4 UW |
5082 | byte < (mips_abi_regsize (gdbarch) |
5083 | - register_size (gdbarch, regnum)); byte++) | |
c906108c | 5084 | printf_filtered (" "); |
025bb325 | 5085 | /* Now print the register value in hex, endian order. */ |
72a155b4 | 5086 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b | 5087 | for (byte = |
72a155b4 UW |
5088 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
5089 | byte < register_size (gdbarch, regnum); byte++) | |
47a35522 | 5090 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
c906108c | 5091 | else |
72a155b4 | 5092 | for (byte = register_size (gdbarch, regnum) - 1; |
6d82d43b | 5093 | byte >= 0; byte--) |
47a35522 | 5094 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
e11c53d2 | 5095 | fprintf_filtered (file, " "); |
c906108c SS |
5096 | col++; |
5097 | } | |
025bb325 | 5098 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 5099 | fprintf_filtered (file, "\n"); |
c906108c SS |
5100 | |
5101 | return regnum; | |
5102 | } | |
5103 | ||
025bb325 | 5104 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */ |
c906108c | 5105 | |
bf1f5b4c | 5106 | static void |
e11c53d2 AC |
5107 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
5108 | struct frame_info *frame, int regnum, int all) | |
c906108c | 5109 | { |
025bb325 | 5110 | if (regnum != -1) /* Do one specified register. */ |
c906108c | 5111 | { |
72a155b4 UW |
5112 | gdb_assert (regnum >= gdbarch_num_regs (gdbarch)); |
5113 | if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
8a3fe4f8 | 5114 | error (_("Not a valid register for the current processor type")); |
c906108c | 5115 | |
0cc93a06 | 5116 | mips_print_register (file, frame, regnum); |
e11c53d2 | 5117 | fprintf_filtered (file, "\n"); |
c906108c | 5118 | } |
c5aa993b | 5119 | else |
025bb325 | 5120 | /* Do all (or most) registers. */ |
c906108c | 5121 | { |
72a155b4 UW |
5122 | regnum = gdbarch_num_regs (gdbarch); |
5123 | while (regnum < gdbarch_num_regs (gdbarch) | |
5124 | + gdbarch_num_pseudo_regs (gdbarch)) | |
c906108c | 5125 | { |
004159a2 | 5126 | if (mips_float_register_p (gdbarch, regnum)) |
e11c53d2 | 5127 | { |
025bb325 | 5128 | if (all) /* True for "INFO ALL-REGISTERS" command. */ |
e11c53d2 AC |
5129 | regnum = print_fp_register_row (file, frame, regnum); |
5130 | else | |
025bb325 | 5131 | regnum += MIPS_NUMREGS; /* Skip floating point regs. */ |
e11c53d2 | 5132 | } |
c906108c | 5133 | else |
e11c53d2 | 5134 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
5135 | } |
5136 | } | |
5137 | } | |
5138 | ||
c906108c SS |
5139 | /* Is this a branch with a delay slot? */ |
5140 | ||
c906108c | 5141 | static int |
acdb74a0 | 5142 | is_delayed (unsigned long insn) |
c906108c SS |
5143 | { |
5144 | int i; | |
5145 | for (i = 0; i < NUMOPCODES; ++i) | |
5146 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
5147 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
5148 | break; | |
5149 | return (i < NUMOPCODES | |
5150 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
5151 | | INSN_COND_BRANCH_DELAY | |
5152 | | INSN_COND_BRANCH_LIKELY))); | |
5153 | } | |
5154 | ||
63807e1d | 5155 | static int |
3352ef37 AC |
5156 | mips_single_step_through_delay (struct gdbarch *gdbarch, |
5157 | struct frame_info *frame) | |
c906108c | 5158 | { |
e17a4113 | 5159 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
3352ef37 | 5160 | CORE_ADDR pc = get_frame_pc (frame); |
47a35522 | 5161 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
5162 | |
5163 | /* There is no branch delay slot on MIPS16. */ | |
0fe7e7c8 | 5164 | if (mips_pc_is_mips16 (pc)) |
c906108c SS |
5165 | return 0; |
5166 | ||
6c95b8df | 5167 | if (!breakpoint_here_p (get_frame_address_space (frame), pc + 4)) |
06648491 MK |
5168 | return 0; |
5169 | ||
3352ef37 AC |
5170 | if (!safe_frame_unwind_memory (frame, pc, buf, sizeof buf)) |
5171 | /* If error reading memory, guess that it is not a delayed | |
5172 | branch. */ | |
c906108c | 5173 | return 0; |
e17a4113 | 5174 | return is_delayed (extract_unsigned_integer (buf, sizeof buf, byte_order)); |
c906108c SS |
5175 | } |
5176 | ||
6d82d43b AC |
5177 | /* To skip prologues, I use this predicate. Returns either PC itself |
5178 | if the code at PC does not look like a function prologue; otherwise | |
5179 | returns an address that (if we're lucky) follows the prologue. If | |
5180 | LENIENT, then we must skip everything which is involved in setting | |
5181 | up the frame (it's OK to skip more, just so long as we don't skip | |
5182 | anything which might clobber the registers which are being saved. | |
5183 | We must skip more in the case where part of the prologue is in the | |
5184 | delay slot of a non-prologue instruction). */ | |
5185 | ||
5186 | static CORE_ADDR | |
6093d2eb | 5187 | mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
6d82d43b | 5188 | { |
8b622e6a AC |
5189 | CORE_ADDR limit_pc; |
5190 | CORE_ADDR func_addr; | |
5191 | ||
6d82d43b AC |
5192 | /* See if we can determine the end of the prologue via the symbol table. |
5193 | If so, then return either PC, or the PC after the prologue, whichever | |
5194 | is greater. */ | |
8b622e6a AC |
5195 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
5196 | { | |
d80b854b UW |
5197 | CORE_ADDR post_prologue_pc |
5198 | = skip_prologue_using_sal (gdbarch, func_addr); | |
8b622e6a AC |
5199 | if (post_prologue_pc != 0) |
5200 | return max (pc, post_prologue_pc); | |
5201 | } | |
6d82d43b AC |
5202 | |
5203 | /* Can't determine prologue from the symbol table, need to examine | |
5204 | instructions. */ | |
5205 | ||
98b4dd94 JB |
5206 | /* Find an upper limit on the function prologue using the debug |
5207 | information. If the debug information could not be used to provide | |
5208 | that bound, then use an arbitrary large number as the upper bound. */ | |
d80b854b | 5209 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
98b4dd94 JB |
5210 | if (limit_pc == 0) |
5211 | limit_pc = pc + 100; /* Magic. */ | |
5212 | ||
0fe7e7c8 | 5213 | if (mips_pc_is_mips16 (pc)) |
e17a4113 | 5214 | return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
6d82d43b | 5215 | else |
e17a4113 | 5216 | return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
88658117 AC |
5217 | } |
5218 | ||
97ab0fdd MR |
5219 | /* Check whether the PC is in a function epilogue (32-bit version). |
5220 | This is a helper function for mips_in_function_epilogue_p. */ | |
5221 | static int | |
e17a4113 | 5222 | mips32_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
5223 | { |
5224 | CORE_ADDR func_addr = 0, func_end = 0; | |
5225 | ||
5226 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
5227 | { | |
5228 | /* The MIPS epilogue is max. 12 bytes long. */ | |
5229 | CORE_ADDR addr = func_end - 12; | |
5230 | ||
5231 | if (addr < func_addr + 4) | |
5232 | addr = func_addr + 4; | |
5233 | if (pc < addr) | |
5234 | return 0; | |
5235 | ||
5236 | for (; pc < func_end; pc += MIPS_INSN32_SIZE) | |
5237 | { | |
5238 | unsigned long high_word; | |
5239 | unsigned long inst; | |
5240 | ||
e17a4113 | 5241 | inst = mips_fetch_instruction (gdbarch, pc); |
97ab0fdd MR |
5242 | high_word = (inst >> 16) & 0xffff; |
5243 | ||
5244 | if (high_word != 0x27bd /* addiu $sp,$sp,offset */ | |
5245 | && high_word != 0x67bd /* daddiu $sp,$sp,offset */ | |
5246 | && inst != 0x03e00008 /* jr $ra */ | |
5247 | && inst != 0x00000000) /* nop */ | |
5248 | return 0; | |
5249 | } | |
5250 | ||
5251 | return 1; | |
5252 | } | |
5253 | ||
5254 | return 0; | |
5255 | } | |
5256 | ||
5257 | /* Check whether the PC is in a function epilogue (16-bit version). | |
5258 | This is a helper function for mips_in_function_epilogue_p. */ | |
5259 | static int | |
e17a4113 | 5260 | mips16_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
5261 | { |
5262 | CORE_ADDR func_addr = 0, func_end = 0; | |
5263 | ||
5264 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
5265 | { | |
5266 | /* The MIPS epilogue is max. 12 bytes long. */ | |
5267 | CORE_ADDR addr = func_end - 12; | |
5268 | ||
5269 | if (addr < func_addr + 4) | |
5270 | addr = func_addr + 4; | |
5271 | if (pc < addr) | |
5272 | return 0; | |
5273 | ||
5274 | for (; pc < func_end; pc += MIPS_INSN16_SIZE) | |
5275 | { | |
5276 | unsigned short inst; | |
5277 | ||
e17a4113 | 5278 | inst = mips_fetch_instruction (gdbarch, pc); |
97ab0fdd MR |
5279 | |
5280 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
5281 | continue; | |
5282 | ||
5283 | if (inst != 0x6300 /* addiu $sp,offset */ | |
5284 | && inst != 0xfb00 /* daddiu $sp,$sp,offset */ | |
5285 | && inst != 0xe820 /* jr $ra */ | |
5286 | && inst != 0xe8a0 /* jrc $ra */ | |
5287 | && inst != 0x6500) /* nop */ | |
5288 | return 0; | |
5289 | } | |
5290 | ||
5291 | return 1; | |
5292 | } | |
5293 | ||
5294 | return 0; | |
5295 | } | |
5296 | ||
5297 | /* The epilogue is defined here as the area at the end of a function, | |
5298 | after an instruction which destroys the function's stack frame. */ | |
5299 | static int | |
5300 | mips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
5301 | { | |
5302 | if (mips_pc_is_mips16 (pc)) | |
e17a4113 | 5303 | return mips16_in_function_epilogue_p (gdbarch, pc); |
97ab0fdd | 5304 | else |
e17a4113 | 5305 | return mips32_in_function_epilogue_p (gdbarch, pc); |
97ab0fdd MR |
5306 | } |
5307 | ||
025bb325 | 5308 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
a5ea2558 AC |
5309 | used for all MIPS-specific commands. */ |
5310 | ||
a5ea2558 | 5311 | static void |
acdb74a0 | 5312 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
5313 | { |
5314 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
5315 | } | |
5316 | ||
a5ea2558 | 5317 | static void |
acdb74a0 | 5318 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 5319 | { |
6d82d43b AC |
5320 | printf_unfiltered |
5321 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
5322 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
5323 | } | |
5324 | ||
c906108c SS |
5325 | /* Commands to show/set the MIPS FPU type. */ |
5326 | ||
c906108c | 5327 | static void |
acdb74a0 | 5328 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 5329 | { |
c906108c | 5330 | char *fpu; |
6ca0852e | 5331 | |
1cf3db46 | 5332 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips) |
6ca0852e UW |
5333 | { |
5334 | printf_unfiltered | |
5335 | ("The MIPS floating-point coprocessor is unknown " | |
5336 | "because the current architecture is not MIPS.\n"); | |
5337 | return; | |
5338 | } | |
5339 | ||
1cf3db46 | 5340 | switch (MIPS_FPU_TYPE (target_gdbarch)) |
c906108c SS |
5341 | { |
5342 | case MIPS_FPU_SINGLE: | |
5343 | fpu = "single-precision"; | |
5344 | break; | |
5345 | case MIPS_FPU_DOUBLE: | |
5346 | fpu = "double-precision"; | |
5347 | break; | |
5348 | case MIPS_FPU_NONE: | |
5349 | fpu = "absent (none)"; | |
5350 | break; | |
93d56215 | 5351 | default: |
e2e0b3e5 | 5352 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c SS |
5353 | } |
5354 | if (mips_fpu_type_auto) | |
025bb325 MS |
5355 | printf_unfiltered ("The MIPS floating-point coprocessor " |
5356 | "is set automatically (currently %s)\n", | |
5357 | fpu); | |
c906108c | 5358 | else |
6d82d43b AC |
5359 | printf_unfiltered |
5360 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
5361 | } |
5362 | ||
5363 | ||
c906108c | 5364 | static void |
acdb74a0 | 5365 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 5366 | { |
025bb325 MS |
5367 | printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", " |
5368 | "\"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
5369 | show_mipsfpu_command (args, from_tty); |
5370 | } | |
5371 | ||
c906108c | 5372 | static void |
acdb74a0 | 5373 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 5374 | { |
8d5838b5 AC |
5375 | struct gdbarch_info info; |
5376 | gdbarch_info_init (&info); | |
c906108c SS |
5377 | mips_fpu_type = MIPS_FPU_SINGLE; |
5378 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5379 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5380 | instead of relying on globals. Doing that would let generic code | |
5381 | handle the search for this specific architecture. */ | |
5382 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 5383 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
5384 | } |
5385 | ||
c906108c | 5386 | static void |
acdb74a0 | 5387 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 5388 | { |
8d5838b5 AC |
5389 | struct gdbarch_info info; |
5390 | gdbarch_info_init (&info); | |
c906108c SS |
5391 | mips_fpu_type = MIPS_FPU_DOUBLE; |
5392 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5393 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5394 | instead of relying on globals. Doing that would let generic code | |
5395 | handle the search for this specific architecture. */ | |
5396 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 5397 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
5398 | } |
5399 | ||
c906108c | 5400 | static void |
acdb74a0 | 5401 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 5402 | { |
8d5838b5 AC |
5403 | struct gdbarch_info info; |
5404 | gdbarch_info_init (&info); | |
c906108c SS |
5405 | mips_fpu_type = MIPS_FPU_NONE; |
5406 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5407 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5408 | instead of relying on globals. Doing that would let generic code | |
5409 | handle the search for this specific architecture. */ | |
5410 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 5411 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
5412 | } |
5413 | ||
c906108c | 5414 | static void |
acdb74a0 | 5415 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
5416 | { |
5417 | mips_fpu_type_auto = 1; | |
5418 | } | |
5419 | ||
c906108c | 5420 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
5421 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
5422 | the relevant processor still exists (it dates back to '94) and | |
5423 | secondly this is not the way to do this. The processor type should | |
5424 | be set by forcing an architecture change. */ | |
c906108c | 5425 | |
691c0433 AC |
5426 | void |
5427 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 5428 | { |
bb486190 UW |
5429 | struct regcache *regcache = get_current_regcache (); |
5430 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
5431 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
a9614958 | 5432 | ULONGEST prid; |
c906108c | 5433 | |
bb486190 | 5434 | regcache_cooked_read_unsigned (regcache, MIPS_PRID_REGNUM, &prid); |
c906108c | 5435 | if ((prid & ~0xf) == 0x700) |
691c0433 | 5436 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
5437 | } |
5438 | ||
5439 | /* Just like reinit_frame_cache, but with the right arguments to be | |
5440 | callable as an sfunc. */ | |
5441 | ||
5442 | static void | |
acdb74a0 AC |
5443 | reinit_frame_cache_sfunc (char *args, int from_tty, |
5444 | struct cmd_list_element *c) | |
c906108c SS |
5445 | { |
5446 | reinit_frame_cache (); | |
5447 | } | |
5448 | ||
a89aa300 AC |
5449 | static int |
5450 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 5451 | { |
d31431ed AC |
5452 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
5453 | disassembler needs to be able to locally determine the ISA, and | |
5454 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
5455 | work. */ | |
ec4045ea AC |
5456 | if (mips_pc_is_mips16 (memaddr)) |
5457 | info->mach = bfd_mach_mips16; | |
c906108c SS |
5458 | |
5459 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 5460 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 5461 | |
e5ab0dce | 5462 | /* Set the disassembler options. */ |
9dae60cc | 5463 | if (!info->disassembler_options) |
e5ab0dce AC |
5464 | /* This string is not recognized explicitly by the disassembler, |
5465 | but it tells the disassembler to not try to guess the ABI from | |
5466 | the bfd elf headers, such that, if the user overrides the ABI | |
5467 | of a program linked as NewABI, the disassembly will follow the | |
5468 | register naming conventions specified by the user. */ | |
5469 | info->disassembler_options = "gpr-names=32"; | |
5470 | ||
c906108c | 5471 | /* Call the appropriate disassembler based on the target endian-ness. */ |
40887e1a | 5472 | if (info->endian == BFD_ENDIAN_BIG) |
c906108c SS |
5473 | return print_insn_big_mips (memaddr, info); |
5474 | else | |
5475 | return print_insn_little_mips (memaddr, info); | |
5476 | } | |
5477 | ||
9dae60cc UW |
5478 | static int |
5479 | gdb_print_insn_mips_n32 (bfd_vma memaddr, struct disassemble_info *info) | |
5480 | { | |
5481 | /* Set up the disassembler info, so that we get the right | |
5482 | register names from libopcodes. */ | |
5483 | info->disassembler_options = "gpr-names=n32"; | |
5484 | info->flavour = bfd_target_elf_flavour; | |
5485 | ||
5486 | return gdb_print_insn_mips (memaddr, info); | |
5487 | } | |
5488 | ||
5489 | static int | |
5490 | gdb_print_insn_mips_n64 (bfd_vma memaddr, struct disassemble_info *info) | |
5491 | { | |
5492 | /* Set up the disassembler info, so that we get the right | |
5493 | register names from libopcodes. */ | |
5494 | info->disassembler_options = "gpr-names=64"; | |
5495 | info->flavour = bfd_target_elf_flavour; | |
5496 | ||
5497 | return gdb_print_insn_mips (memaddr, info); | |
5498 | } | |
5499 | ||
025bb325 MS |
5500 | /* This function implements gdbarch_breakpoint_from_pc. It uses the |
5501 | program counter value to determine whether a 16- or 32-bit breakpoint | |
5502 | should be used. It returns a pointer to a string of bytes that encode a | |
5503 | breakpoint instruction, stores the length of the string to *lenptr, and | |
5504 | adjusts pc (if necessary) to point to the actual memory location where | |
5505 | the breakpoint should be inserted. */ | |
c906108c | 5506 | |
47a35522 | 5507 | static const gdb_byte * |
025bb325 MS |
5508 | mips_breakpoint_from_pc (struct gdbarch *gdbarch, |
5509 | CORE_ADDR *pcptr, int *lenptr) | |
c906108c | 5510 | { |
67d57894 | 5511 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
c906108c | 5512 | { |
0fe7e7c8 | 5513 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 5514 | { |
47a35522 | 5515 | static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
95404a3e | 5516 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5517 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
5518 | return mips16_big_breakpoint; |
5519 | } | |
5520 | else | |
5521 | { | |
aaab4dba AC |
5522 | /* The IDT board uses an unusual breakpoint value, and |
5523 | sometimes gets confused when it sees the usual MIPS | |
5524 | breakpoint instruction. */ | |
47a35522 MK |
5525 | static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
5526 | static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
5527 | static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
f2ec0ecf | 5528 | /* Likewise, IRIX appears to expect a different breakpoint, |
025bb325 | 5529 | although this is not apparent until you try to use pthreads. */ |
f2ec0ecf | 5530 | static gdb_byte irix_big_breakpoint[] = { 0, 0, 0, 0xd }; |
c906108c | 5531 | |
c5aa993b | 5532 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
5533 | |
5534 | if (strcmp (target_shortname, "mips") == 0) | |
5535 | return idt_big_breakpoint; | |
5536 | else if (strcmp (target_shortname, "ddb") == 0 | |
5537 | || strcmp (target_shortname, "pmon") == 0 | |
5538 | || strcmp (target_shortname, "lsi") == 0) | |
5539 | return pmon_big_breakpoint; | |
f2ec0ecf JB |
5540 | else if (gdbarch_osabi (gdbarch) == GDB_OSABI_IRIX) |
5541 | return irix_big_breakpoint; | |
c906108c SS |
5542 | else |
5543 | return big_breakpoint; | |
5544 | } | |
5545 | } | |
5546 | else | |
5547 | { | |
0fe7e7c8 | 5548 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 5549 | { |
47a35522 | 5550 | static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
95404a3e | 5551 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5552 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
5553 | return mips16_little_breakpoint; |
5554 | } | |
5555 | else | |
5556 | { | |
47a35522 MK |
5557 | static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
5558 | static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
5559 | static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 5560 | |
c5aa993b | 5561 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
5562 | |
5563 | if (strcmp (target_shortname, "mips") == 0) | |
5564 | return idt_little_breakpoint; | |
5565 | else if (strcmp (target_shortname, "ddb") == 0 | |
5566 | || strcmp (target_shortname, "pmon") == 0 | |
5567 | || strcmp (target_shortname, "lsi") == 0) | |
5568 | return pmon_little_breakpoint; | |
5569 | else | |
5570 | return little_breakpoint; | |
5571 | } | |
5572 | } | |
5573 | } | |
5574 | ||
c8cef75f MR |
5575 | /* Return non-zero if the ADDR instruction has a branch delay slot |
5576 | (i.e. it is a jump or branch instruction). This function is based | |
5577 | on mips32_next_pc. */ | |
5578 | ||
5579 | static int | |
5580 | mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr) | |
5581 | { | |
5582 | gdb_byte buf[MIPS_INSN32_SIZE]; | |
5583 | unsigned long inst; | |
5584 | int status; | |
5585 | int op; | |
a385295e MR |
5586 | int rs; |
5587 | int rt; | |
c8cef75f MR |
5588 | |
5589 | status = target_read_memory (addr, buf, MIPS_INSN32_SIZE); | |
5590 | if (status) | |
5591 | return 0; | |
5592 | ||
5593 | inst = mips_fetch_instruction (gdbarch, addr); | |
5594 | op = itype_op (inst); | |
5595 | if ((inst & 0xe0000000) != 0) | |
a385295e MR |
5596 | { |
5597 | rs = itype_rs (inst); | |
5598 | rt = itype_rt (inst); | |
5599 | return (op >> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ | |
5600 | || op == 29 /* JALX: bits 011101 */ | |
5601 | || (op == 17 | |
5602 | && (rs == 8 | |
c8cef75f | 5603 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
a385295e MR |
5604 | || (rs == 9 && (rt & 0x2) == 0) |
5605 | /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */ | |
5606 | || (rs == 10 && (rt & 0x2) == 0)))); | |
5607 | /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */ | |
5608 | } | |
c8cef75f MR |
5609 | else |
5610 | switch (op & 0x07) /* extract bits 28,27,26 */ | |
5611 | { | |
5612 | case 0: /* SPECIAL */ | |
5613 | op = rtype_funct (inst); | |
5614 | return (op == 8 /* JR */ | |
5615 | || op == 9); /* JALR */ | |
5616 | break; /* end SPECIAL */ | |
5617 | case 1: /* REGIMM */ | |
a385295e MR |
5618 | rs = itype_rs (inst); |
5619 | rt = itype_rt (inst); /* branch condition */ | |
5620 | return ((rt & 0xc) == 0 | |
c8cef75f MR |
5621 | /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */ |
5622 | /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */ | |
a385295e MR |
5623 | || ((rt & 0x1e) == 0x1c && rs == 0)); |
5624 | /* BPOSGE32, BPOSGE64: bits 1110x */ | |
c8cef75f MR |
5625 | break; /* end REGIMM */ |
5626 | default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */ | |
5627 | return 1; | |
5628 | break; | |
5629 | } | |
5630 | } | |
5631 | ||
5632 | /* Return non-zero if the ADDR instruction, which must be a 32-bit | |
5633 | instruction if MUSTBE32 is set or can be any instruction otherwise, | |
5634 | has a branch delay slot (i.e. it is a non-compact jump instruction). */ | |
5635 | ||
5636 | static int | |
5637 | mips16_instruction_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr, | |
5638 | int mustbe32) | |
5639 | { | |
5640 | gdb_byte buf[MIPS_INSN16_SIZE]; | |
5641 | unsigned short inst; | |
5642 | int status; | |
5643 | ||
5644 | status = target_read_memory (addr, buf, MIPS_INSN16_SIZE); | |
5645 | if (status) | |
5646 | return 0; | |
5647 | ||
5648 | inst = mips_fetch_instruction (gdbarch, addr); | |
5649 | if (!mustbe32) | |
5650 | return (inst & 0xf89f) == 0xe800; /* JR/JALR (16-bit instruction) */ | |
5651 | return (inst & 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */ | |
5652 | } | |
5653 | ||
5654 | /* Calculate the starting address of the MIPS memory segment BPADDR is in. | |
5655 | This assumes KSSEG exists. */ | |
5656 | ||
5657 | static CORE_ADDR | |
5658 | mips_segment_boundary (CORE_ADDR bpaddr) | |
5659 | { | |
5660 | CORE_ADDR mask = CORE_ADDR_MAX; | |
5661 | int segsize; | |
5662 | ||
5663 | if (sizeof (CORE_ADDR) == 8) | |
5664 | /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid | |
5665 | a compiler warning produced where CORE_ADDR is a 32-bit type even | |
5666 | though in that case this is dead code). */ | |
5667 | switch (bpaddr >> ((sizeof (CORE_ADDR) << 3) - 2) & 3) | |
5668 | { | |
5669 | case 3: | |
5670 | if (bpaddr == (bfd_signed_vma) (int32_t) bpaddr) | |
5671 | segsize = 29; /* 32-bit compatibility segment */ | |
5672 | else | |
5673 | segsize = 62; /* xkseg */ | |
5674 | break; | |
5675 | case 2: /* xkphys */ | |
5676 | segsize = 59; | |
5677 | break; | |
5678 | default: /* xksseg (1), xkuseg/kuseg (0) */ | |
5679 | segsize = 62; | |
5680 | break; | |
5681 | } | |
5682 | else if (bpaddr & 0x80000000) /* kernel segment */ | |
5683 | segsize = 29; | |
5684 | else | |
5685 | segsize = 31; /* user segment */ | |
5686 | mask <<= segsize; | |
5687 | return bpaddr & mask; | |
5688 | } | |
5689 | ||
5690 | /* Move the breakpoint at BPADDR out of any branch delay slot by shifting | |
5691 | it backwards if necessary. Return the address of the new location. */ | |
5692 | ||
5693 | static CORE_ADDR | |
5694 | mips_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) | |
5695 | { | |
5696 | CORE_ADDR prev_addr, next_addr; | |
5697 | CORE_ADDR boundary; | |
5698 | CORE_ADDR func_addr; | |
5699 | ||
5700 | /* If a breakpoint is set on the instruction in a branch delay slot, | |
5701 | GDB gets confused. When the breakpoint is hit, the PC isn't on | |
5702 | the instruction in the branch delay slot, the PC will point to | |
5703 | the branch instruction. Since the PC doesn't match any known | |
5704 | breakpoints, GDB reports a trap exception. | |
5705 | ||
5706 | There are two possible fixes for this problem. | |
5707 | ||
5708 | 1) When the breakpoint gets hit, see if the BD bit is set in the | |
5709 | Cause register (which indicates the last exception occurred in a | |
5710 | branch delay slot). If the BD bit is set, fix the PC to point to | |
5711 | the instruction in the branch delay slot. | |
5712 | ||
5713 | 2) When the user sets the breakpoint, don't allow him to set the | |
5714 | breakpoint on the instruction in the branch delay slot. Instead | |
5715 | move the breakpoint to the branch instruction (which will have | |
5716 | the same result). | |
5717 | ||
5718 | The problem with the first solution is that if the user then | |
5719 | single-steps the processor, the branch instruction will get | |
5720 | skipped (since GDB thinks the PC is on the instruction in the | |
5721 | branch delay slot). | |
5722 | ||
5723 | So, we'll use the second solution. To do this we need to know if | |
5724 | the instruction we're trying to set the breakpoint on is in the | |
5725 | branch delay slot. */ | |
5726 | ||
5727 | boundary = mips_segment_boundary (bpaddr); | |
5728 | ||
5729 | /* Make sure we don't scan back before the beginning of the current | |
5730 | function, since we may fetch constant data or insns that look like | |
5731 | a jump. Of course we might do that anyway if the compiler has | |
5732 | moved constants inline. :-( */ | |
5733 | if (find_pc_partial_function (bpaddr, NULL, &func_addr, NULL) | |
5734 | && func_addr > boundary && func_addr <= bpaddr) | |
5735 | boundary = func_addr; | |
5736 | ||
5737 | if (!mips_pc_is_mips16 (bpaddr)) | |
5738 | { | |
5739 | if (bpaddr == boundary) | |
5740 | return bpaddr; | |
5741 | ||
5742 | /* If the previous instruction has a branch delay slot, we have | |
5743 | to move the breakpoint to the branch instruction. */ | |
5744 | prev_addr = bpaddr - 4; | |
5745 | if (mips32_instruction_has_delay_slot (gdbarch, prev_addr)) | |
5746 | bpaddr = prev_addr; | |
5747 | } | |
5748 | else | |
5749 | { | |
5750 | struct minimal_symbol *sym; | |
5751 | CORE_ADDR addr, jmpaddr; | |
5752 | int i; | |
5753 | ||
5754 | boundary = unmake_mips16_addr (boundary); | |
5755 | ||
5756 | /* The only MIPS16 instructions with delay slots are JAL, JALX, | |
5757 | JALR and JR. An absolute JAL/JALX is always 4 bytes long, | |
5758 | so try for that first, then try the 2 byte JALR/JR. | |
5759 | FIXME: We have to assume that bpaddr is not the second half | |
5760 | of an extended instruction. */ | |
5761 | ||
5762 | jmpaddr = 0; | |
5763 | addr = bpaddr; | |
5764 | for (i = 1; i < 4; i++) | |
5765 | { | |
5766 | if (unmake_mips16_addr (addr) == boundary) | |
5767 | break; | |
5768 | addr -= 2; | |
5769 | if (i == 1 && mips16_instruction_has_delay_slot (gdbarch, addr, 0)) | |
5770 | /* Looks like a JR/JALR at [target-1], but it could be | |
5771 | the second word of a previous JAL/JALX, so record it | |
5772 | and check back one more. */ | |
5773 | jmpaddr = addr; | |
5774 | else if (i > 1 | |
5775 | && mips16_instruction_has_delay_slot (gdbarch, addr, 1)) | |
5776 | { | |
5777 | if (i == 2) | |
5778 | /* Looks like a JAL/JALX at [target-2], but it could also | |
5779 | be the second word of a previous JAL/JALX, record it, | |
5780 | and check back one more. */ | |
5781 | jmpaddr = addr; | |
5782 | else | |
5783 | /* Looks like a JAL/JALX at [target-3], so any previously | |
5784 | recorded JAL/JALX or JR/JALR must be wrong, because: | |
5785 | ||
5786 | >-3: JAL | |
5787 | -2: JAL-ext (can't be JAL/JALX) | |
5788 | -1: bdslot (can't be JR/JALR) | |
5789 | 0: target insn | |
5790 | ||
5791 | Of course it could be another JAL-ext which looks | |
5792 | like a JAL, but in that case we'd have broken out | |
5793 | of this loop at [target-2]: | |
5794 | ||
5795 | -4: JAL | |
5796 | >-3: JAL-ext | |
5797 | -2: bdslot (can't be jmp) | |
5798 | -1: JR/JALR | |
5799 | 0: target insn */ | |
5800 | jmpaddr = 0; | |
5801 | } | |
5802 | else | |
5803 | { | |
5804 | /* Not a jump instruction: if we're at [target-1] this | |
5805 | could be the second word of a JAL/JALX, so continue; | |
5806 | otherwise we're done. */ | |
5807 | if (i > 1) | |
5808 | break; | |
5809 | } | |
5810 | } | |
5811 | ||
5812 | if (jmpaddr) | |
5813 | bpaddr = jmpaddr; | |
5814 | } | |
5815 | ||
5816 | return bpaddr; | |
5817 | } | |
5818 | ||
14132e89 MR |
5819 | /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16 |
5820 | call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */ | |
5821 | ||
5822 | static int | |
5823 | mips_is_stub_suffix (const char *suffix, int zero) | |
5824 | { | |
5825 | switch (suffix[0]) | |
5826 | { | |
5827 | case '0': | |
5828 | return zero && suffix[1] == '\0'; | |
5829 | case '1': | |
5830 | return suffix[1] == '\0' || (suffix[1] == '0' && suffix[2] == '\0'); | |
5831 | case '2': | |
5832 | case '5': | |
5833 | case '6': | |
5834 | case '9': | |
5835 | return suffix[1] == '\0'; | |
5836 | default: | |
5837 | return 0; | |
5838 | } | |
5839 | } | |
5840 | ||
5841 | /* Return non-zero if MODE is one of the mode infixes used for MIPS16 | |
5842 | call stubs, one of sf, df, sc, or dc. */ | |
5843 | ||
5844 | static int | |
5845 | mips_is_stub_mode (const char *mode) | |
5846 | { | |
5847 | return ((mode[0] == 's' || mode[0] == 'd') | |
5848 | && (mode[1] == 'f' || mode[1] == 'c')); | |
5849 | } | |
5850 | ||
5851 | /* Code at PC is a compiler-generated stub. Such a stub for a function | |
5852 | bar might have a name like __fn_stub_bar, and might look like this: | |
5853 | ||
5854 | mfc1 $4, $f13 | |
5855 | mfc1 $5, $f12 | |
5856 | mfc1 $6, $f15 | |
5857 | mfc1 $7, $f14 | |
5858 | ||
5859 | followed by (or interspersed with): | |
5860 | ||
5861 | j bar | |
5862 | ||
5863 | or: | |
5864 | ||
5865 | lui $25, %hi(bar) | |
5866 | addiu $25, $25, %lo(bar) | |
5867 | jr $25 | |
5868 | ||
5869 | ($1 may be used in old code; for robustness we accept any register) | |
5870 | or, in PIC code: | |
5871 | ||
5872 | lui $28, %hi(_gp_disp) | |
5873 | addiu $28, $28, %lo(_gp_disp) | |
5874 | addu $28, $28, $25 | |
5875 | lw $25, %got(bar) | |
5876 | addiu $25, $25, %lo(bar) | |
5877 | jr $25 | |
5878 | ||
5879 | In the case of a __call_stub_bar stub, the sequence to set up | |
5880 | arguments might look like this: | |
5881 | ||
5882 | mtc1 $4, $f13 | |
5883 | mtc1 $5, $f12 | |
5884 | mtc1 $6, $f15 | |
5885 | mtc1 $7, $f14 | |
5886 | ||
5887 | followed by (or interspersed with) one of the jump sequences above. | |
5888 | ||
5889 | In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead | |
5890 | of J or JR, respectively, followed by: | |
5891 | ||
5892 | mfc1 $2, $f0 | |
5893 | mfc1 $3, $f1 | |
5894 | jr $18 | |
5895 | ||
5896 | We are at the beginning of the stub here, and scan down and extract | |
5897 | the target address from the jump immediate instruction or, if a jump | |
5898 | register instruction is used, from the register referred. Return | |
5899 | the value of PC calculated or 0 if inconclusive. | |
5900 | ||
5901 | The limit on the search is arbitrarily set to 20 instructions. FIXME. */ | |
5902 | ||
5903 | static CORE_ADDR | |
5904 | mips_get_mips16_fn_stub_pc (struct frame_info *frame, CORE_ADDR pc) | |
5905 | { | |
5906 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
5907 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
5908 | int addrreg = MIPS_ZERO_REGNUM; | |
5909 | CORE_ADDR start_pc = pc; | |
5910 | CORE_ADDR target_pc = 0; | |
5911 | CORE_ADDR addr = 0; | |
5912 | CORE_ADDR gp = 0; | |
5913 | int status = 0; | |
5914 | int i; | |
5915 | ||
5916 | for (i = 0; | |
5917 | status == 0 && target_pc == 0 && i < 20; | |
5918 | i++, pc += MIPS_INSN32_SIZE) | |
5919 | { | |
5920 | ULONGEST inst = mips_fetch_instruction (gdbarch, pc); | |
5921 | CORE_ADDR imm; | |
5922 | int rt; | |
5923 | int rs; | |
5924 | int rd; | |
5925 | ||
5926 | switch (itype_op (inst)) | |
5927 | { | |
5928 | case 0: /* SPECIAL */ | |
5929 | switch (rtype_funct (inst)) | |
5930 | { | |
5931 | case 8: /* JR */ | |
5932 | case 9: /* JALR */ | |
5933 | rs = rtype_rs (inst); | |
5934 | if (rs == MIPS_GP_REGNUM) | |
5935 | target_pc = gp; /* Hmm... */ | |
5936 | else if (rs == addrreg) | |
5937 | target_pc = addr; | |
5938 | break; | |
5939 | ||
5940 | case 0x21: /* ADDU */ | |
5941 | rt = rtype_rt (inst); | |
5942 | rs = rtype_rs (inst); | |
5943 | rd = rtype_rd (inst); | |
5944 | if (rd == MIPS_GP_REGNUM | |
5945 | && ((rs == MIPS_GP_REGNUM && rt == MIPS_T9_REGNUM) | |
5946 | || (rs == MIPS_T9_REGNUM && rt == MIPS_GP_REGNUM))) | |
5947 | gp += start_pc; | |
5948 | break; | |
5949 | } | |
5950 | break; | |
5951 | ||
5952 | case 2: /* J */ | |
5953 | case 3: /* JAL */ | |
5954 | target_pc = jtype_target (inst) << 2; | |
5955 | target_pc += ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); | |
5956 | break; | |
5957 | ||
5958 | case 9: /* ADDIU */ | |
5959 | rt = itype_rt (inst); | |
5960 | rs = itype_rs (inst); | |
5961 | if (rt == rs) | |
5962 | { | |
5963 | imm = (itype_immediate (inst) ^ 0x8000) - 0x8000; | |
5964 | if (rt == MIPS_GP_REGNUM) | |
5965 | gp += imm; | |
5966 | else if (rt == addrreg) | |
5967 | addr += imm; | |
5968 | } | |
5969 | break; | |
5970 | ||
5971 | case 0xf: /* LUI */ | |
5972 | rt = itype_rt (inst); | |
5973 | imm = ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 16; | |
5974 | if (rt == MIPS_GP_REGNUM) | |
5975 | gp = imm; | |
5976 | else if (rt != MIPS_ZERO_REGNUM) | |
5977 | { | |
5978 | addrreg = rt; | |
5979 | addr = imm; | |
5980 | } | |
5981 | break; | |
5982 | ||
5983 | case 0x23: /* LW */ | |
5984 | rt = itype_rt (inst); | |
5985 | rs = itype_rs (inst); | |
5986 | imm = (itype_immediate (inst) ^ 0x8000) - 0x8000; | |
5987 | if (gp != 0 && rs == MIPS_GP_REGNUM) | |
5988 | { | |
5989 | gdb_byte buf[4]; | |
5990 | ||
5991 | memset (buf, 0, sizeof (buf)); | |
5992 | status = target_read_memory (gp + imm, buf, sizeof (buf)); | |
5993 | addrreg = rt; | |
5994 | addr = extract_signed_integer (buf, sizeof (buf), byte_order); | |
5995 | } | |
5996 | break; | |
5997 | } | |
5998 | } | |
5999 | ||
6000 | return target_pc; | |
6001 | } | |
6002 | ||
6003 | /* If PC is in a MIPS16 call or return stub, return the address of the | |
6004 | target PC, which is either the callee or the caller. There are several | |
c906108c SS |
6005 | cases which must be handled: |
6006 | ||
14132e89 MR |
6007 | * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub |
6008 | and the target PC is in $31 ($ra). | |
c906108c | 6009 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
14132e89 MR |
6010 | and the target PC is in $2. |
6011 | * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10}, | |
6012 | i.e. before the JALR instruction, this is effectively a call stub | |
6013 | and the target PC is in $2. Otherwise this is effectively | |
6014 | a return stub and the target PC is in $18. | |
6015 | * If the PC is at the start of __call_stub_fp_*, i.e. before the | |
6016 | JAL or JALR instruction, this is effectively a call stub and the | |
6017 | target PC is buried in the instruction stream. Otherwise this | |
6018 | is effectively a return stub and the target PC is in $18. | |
6019 | * If the PC is in __call_stub_* or in __fn_stub_*, this is a call | |
6020 | stub and the target PC is buried in the instruction stream. | |
6021 | ||
6022 | See the source code for the stubs in gcc/config/mips/mips16.S, or the | |
6023 | stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the | |
e7d6a6d2 | 6024 | gory details. */ |
c906108c | 6025 | |
757a7cc6 | 6026 | static CORE_ADDR |
db5f024e | 6027 | mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 6028 | { |
e17a4113 | 6029 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 6030 | CORE_ADDR start_addr; |
14132e89 MR |
6031 | const char *name; |
6032 | size_t prefixlen; | |
c906108c SS |
6033 | |
6034 | /* Find the starting address and name of the function containing the PC. */ | |
6035 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
6036 | return 0; | |
6037 | ||
14132e89 MR |
6038 | /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub |
6039 | and the target PC is in $31 ($ra). */ | |
6040 | prefixlen = strlen (mips_str_mips16_ret_stub); | |
6041 | if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0 | |
6042 | && mips_is_stub_mode (name + prefixlen) | |
6043 | && name[prefixlen + 2] == '\0') | |
6044 | return get_frame_register_signed | |
6045 | (frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM); | |
6046 | ||
6047 | /* If the PC is in __mips16_call_stub_*, this is one of the call | |
6048 | call/return stubs. */ | |
6049 | prefixlen = strlen (mips_str_mips16_call_stub); | |
6050 | if (strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0) | |
c906108c SS |
6051 | { |
6052 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
6053 | and the target PC is in $2. */ | |
14132e89 MR |
6054 | if (mips_is_stub_suffix (name + prefixlen, 0)) |
6055 | return get_frame_register_signed | |
6056 | (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); | |
c906108c | 6057 | |
14132e89 MR |
6058 | /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10}, |
6059 | i.e. before the JALR instruction, this is effectively a call stub | |
b021a221 | 6060 | and the target PC is in $2. Otherwise this is effectively |
c5aa993b | 6061 | a return stub and the target PC is in $18. */ |
14132e89 MR |
6062 | else if (mips_is_stub_mode (name + prefixlen) |
6063 | && name[prefixlen + 2] == '_' | |
6064 | && mips_is_stub_suffix (name + prefixlen + 3, 0)) | |
c906108c SS |
6065 | { |
6066 | if (pc == start_addr) | |
14132e89 MR |
6067 | /* This is the 'call' part of a call stub. The return |
6068 | address is in $2. */ | |
6069 | return get_frame_register_signed | |
6070 | (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); | |
c906108c SS |
6071 | else |
6072 | /* This is the 'return' part of a call stub. The return | |
14132e89 MR |
6073 | address is in $18. */ |
6074 | return get_frame_register_signed | |
6075 | (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); | |
c906108c | 6076 | } |
14132e89 MR |
6077 | else |
6078 | return 0; /* Not a stub. */ | |
6079 | } | |
6080 | ||
6081 | /* If the PC is in __call_stub_* or __fn_stub*, this is one of the | |
6082 | compiler-generated call or call/return stubs. */ | |
6083 | if (strncmp (name, mips_str_fn_stub, strlen (mips_str_fn_stub)) == 0 | |
6084 | || strncmp (name, mips_str_call_stub, strlen (mips_str_call_stub)) == 0) | |
6085 | { | |
6086 | if (pc == start_addr) | |
6087 | /* This is the 'call' part of a call stub. Call this helper | |
6088 | to scan through this code for interesting instructions | |
6089 | and determine the final PC. */ | |
6090 | return mips_get_mips16_fn_stub_pc (frame, pc); | |
6091 | else | |
6092 | /* This is the 'return' part of a call stub. The return address | |
6093 | is in $18. */ | |
6094 | return get_frame_register_signed | |
6095 | (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); | |
c906108c | 6096 | } |
14132e89 MR |
6097 | |
6098 | return 0; /* Not a stub. */ | |
6099 | } | |
6100 | ||
6101 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
6102 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
6103 | ||
6104 | static int | |
6105 | mips_in_return_stub (struct gdbarch *gdbarch, CORE_ADDR pc, const char *name) | |
6106 | { | |
6107 | CORE_ADDR start_addr; | |
6108 | size_t prefixlen; | |
6109 | ||
6110 | /* Find the starting address of the function containing the PC. */ | |
6111 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
6112 | return 0; | |
6113 | ||
6114 | /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at | |
6115 | the start, i.e. after the JALR instruction, this is effectively | |
6116 | a return stub. */ | |
6117 | prefixlen = strlen (mips_str_mips16_call_stub); | |
6118 | if (pc != start_addr | |
6119 | && strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0 | |
6120 | && mips_is_stub_mode (name + prefixlen) | |
6121 | && name[prefixlen + 2] == '_' | |
6122 | && mips_is_stub_suffix (name + prefixlen + 3, 1)) | |
6123 | return 1; | |
6124 | ||
6125 | /* If the PC is in __call_stub_fp_* but not at the start, i.e. after | |
6126 | the JAL or JALR instruction, this is effectively a return stub. */ | |
6127 | prefixlen = strlen (mips_str_call_fp_stub); | |
6128 | if (pc != start_addr | |
6129 | && strncmp (name, mips_str_call_fp_stub, prefixlen) == 0) | |
6130 | return 1; | |
6131 | ||
6132 | /* Consume the .pic. prefix of any PIC stub, this function must return | |
6133 | true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub | |
6134 | or the call stub path will trigger in handle_inferior_event causing | |
6135 | it to go astray. */ | |
6136 | prefixlen = strlen (mips_str_pic); | |
6137 | if (strncmp (name, mips_str_pic, prefixlen) == 0) | |
6138 | name += prefixlen; | |
6139 | ||
6140 | /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */ | |
6141 | prefixlen = strlen (mips_str_mips16_ret_stub); | |
6142 | if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0 | |
6143 | && mips_is_stub_mode (name + prefixlen) | |
6144 | && name[prefixlen + 2] == '\0') | |
6145 | return 1; | |
6146 | ||
6147 | return 0; /* Not a stub. */ | |
c906108c SS |
6148 | } |
6149 | ||
db5f024e DJ |
6150 | /* If the current PC is the start of a non-PIC-to-PIC stub, return the |
6151 | PC of the stub target. The stub just loads $t9 and jumps to it, | |
6152 | so that $t9 has the correct value at function entry. */ | |
6153 | ||
6154 | static CORE_ADDR | |
6155 | mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
6156 | { | |
e17a4113 UW |
6157 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6158 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
db5f024e DJ |
6159 | struct minimal_symbol *msym; |
6160 | int i; | |
6161 | gdb_byte stub_code[16]; | |
6162 | int32_t stub_words[4]; | |
6163 | ||
6164 | /* The stub for foo is named ".pic.foo", and is either two | |
6165 | instructions inserted before foo or a three instruction sequence | |
6166 | which jumps to foo. */ | |
6167 | msym = lookup_minimal_symbol_by_pc (pc); | |
6168 | if (msym == NULL | |
6169 | || SYMBOL_VALUE_ADDRESS (msym) != pc | |
6170 | || SYMBOL_LINKAGE_NAME (msym) == NULL | |
6171 | || strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) != 0) | |
6172 | return 0; | |
6173 | ||
6174 | /* A two-instruction header. */ | |
6175 | if (MSYMBOL_SIZE (msym) == 8) | |
6176 | return pc + 8; | |
6177 | ||
6178 | /* A three-instruction (plus delay slot) trampoline. */ | |
6179 | if (MSYMBOL_SIZE (msym) == 16) | |
6180 | { | |
6181 | if (target_read_memory (pc, stub_code, 16) != 0) | |
6182 | return 0; | |
6183 | for (i = 0; i < 4; i++) | |
e17a4113 UW |
6184 | stub_words[i] = extract_unsigned_integer (stub_code + i * 4, |
6185 | 4, byte_order); | |
db5f024e DJ |
6186 | |
6187 | /* A stub contains these instructions: | |
6188 | lui t9, %hi(target) | |
6189 | j target | |
6190 | addiu t9, t9, %lo(target) | |
6191 | nop | |
6192 | ||
6193 | This works even for N64, since stubs are only generated with | |
6194 | -msym32. */ | |
6195 | if ((stub_words[0] & 0xffff0000U) == 0x3c190000 | |
6196 | && (stub_words[1] & 0xfc000000U) == 0x08000000 | |
6197 | && (stub_words[2] & 0xffff0000U) == 0x27390000 | |
6198 | && stub_words[3] == 0x00000000) | |
34b192ce MR |
6199 | return ((((stub_words[0] & 0x0000ffff) << 16) |
6200 | + (stub_words[2] & 0x0000ffff)) ^ 0x8000) - 0x8000; | |
db5f024e DJ |
6201 | } |
6202 | ||
6203 | /* Not a recognized stub. */ | |
6204 | return 0; | |
6205 | } | |
6206 | ||
6207 | static CORE_ADDR | |
6208 | mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
6209 | { | |
14132e89 | 6210 | CORE_ADDR requested_pc = pc; |
db5f024e | 6211 | CORE_ADDR target_pc; |
14132e89 MR |
6212 | CORE_ADDR new_pc; |
6213 | ||
6214 | do | |
6215 | { | |
6216 | target_pc = pc; | |
db5f024e | 6217 | |
14132e89 MR |
6218 | new_pc = mips_skip_mips16_trampoline_code (frame, pc); |
6219 | if (new_pc) | |
6220 | { | |
6221 | pc = new_pc; | |
6222 | if (is_mips16_addr (pc)) | |
6223 | pc = unmake_mips16_addr (pc); | |
6224 | } | |
db5f024e | 6225 | |
14132e89 MR |
6226 | new_pc = find_solib_trampoline_target (frame, pc); |
6227 | if (new_pc) | |
6228 | { | |
6229 | pc = new_pc; | |
6230 | if (is_mips16_addr (pc)) | |
6231 | pc = unmake_mips16_addr (pc); | |
6232 | } | |
db5f024e | 6233 | |
14132e89 MR |
6234 | new_pc = mips_skip_pic_trampoline_code (frame, pc); |
6235 | if (new_pc) | |
6236 | { | |
6237 | pc = new_pc; | |
6238 | if (is_mips16_addr (pc)) | |
6239 | pc = unmake_mips16_addr (pc); | |
6240 | } | |
6241 | } | |
6242 | while (pc != target_pc); | |
db5f024e | 6243 | |
14132e89 | 6244 | return pc != requested_pc ? pc : 0; |
db5f024e DJ |
6245 | } |
6246 | ||
a4b8ebc8 | 6247 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
f57d151a | 6248 | [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
6249 | |
6250 | static int | |
d3f73121 | 6251 | mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 6252 | { |
a4b8ebc8 | 6253 | int regnum; |
2f38ef89 | 6254 | if (num >= 0 && num < 32) |
a4b8ebc8 | 6255 | regnum = num; |
2f38ef89 | 6256 | else if (num >= 38 && num < 70) |
d3f73121 | 6257 | regnum = num + mips_regnum (gdbarch)->fp0 - 38; |
040b99fd | 6258 | else if (num == 70) |
d3f73121 | 6259 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 6260 | else if (num == 71) |
d3f73121 | 6261 | regnum = mips_regnum (gdbarch)->lo; |
1faeff08 MR |
6262 | else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 72 && num < 78) |
6263 | regnum = num + mips_regnum (gdbarch)->dspacc - 72; | |
2f38ef89 | 6264 | else |
a4b8ebc8 AC |
6265 | /* This will hopefully (eventually) provoke a warning. Should |
6266 | we be calling complaint() here? */ | |
d3f73121 MD |
6267 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
6268 | return gdbarch_num_regs (gdbarch) + regnum; | |
88c72b7d AC |
6269 | } |
6270 | ||
2f38ef89 | 6271 | |
a4b8ebc8 | 6272 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
f57d151a | 6273 | gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
6274 | |
6275 | static int | |
d3f73121 | 6276 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 6277 | { |
a4b8ebc8 | 6278 | int regnum; |
2f38ef89 | 6279 | if (num >= 0 && num < 32) |
a4b8ebc8 | 6280 | regnum = num; |
2f38ef89 | 6281 | else if (num >= 32 && num < 64) |
d3f73121 | 6282 | regnum = num + mips_regnum (gdbarch)->fp0 - 32; |
040b99fd | 6283 | else if (num == 64) |
d3f73121 | 6284 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 6285 | else if (num == 65) |
d3f73121 | 6286 | regnum = mips_regnum (gdbarch)->lo; |
1faeff08 MR |
6287 | else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 66 && num < 72) |
6288 | regnum = num + mips_regnum (gdbarch)->dspacc - 66; | |
2f38ef89 | 6289 | else |
a4b8ebc8 AC |
6290 | /* This will hopefully (eventually) provoke a warning. Should we |
6291 | be calling complaint() here? */ | |
d3f73121 MD |
6292 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
6293 | return gdbarch_num_regs (gdbarch) + regnum; | |
a4b8ebc8 AC |
6294 | } |
6295 | ||
6296 | static int | |
e7faf938 | 6297 | mips_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
a4b8ebc8 AC |
6298 | { |
6299 | /* Only makes sense to supply raw registers. */ | |
e7faf938 | 6300 | gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)); |
a4b8ebc8 AC |
6301 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to |
6302 | decide if it is valid. Should instead define a standard sim/gdb | |
6303 | register numbering scheme. */ | |
e7faf938 MD |
6304 | if (gdbarch_register_name (gdbarch, |
6305 | gdbarch_num_regs (gdbarch) + regnum) != NULL | |
6306 | && gdbarch_register_name (gdbarch, | |
025bb325 MS |
6307 | gdbarch_num_regs (gdbarch) |
6308 | + regnum)[0] != '\0') | |
a4b8ebc8 AC |
6309 | return regnum; |
6310 | else | |
6d82d43b | 6311 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
6312 | } |
6313 | ||
2f38ef89 | 6314 | |
4844f454 CV |
6315 | /* Convert an integer into an address. Extracting the value signed |
6316 | guarantees a correctly sign extended address. */ | |
fc0c74b1 AC |
6317 | |
6318 | static CORE_ADDR | |
79dd2d24 | 6319 | mips_integer_to_address (struct gdbarch *gdbarch, |
870cd05e | 6320 | struct type *type, const gdb_byte *buf) |
fc0c74b1 | 6321 | { |
e17a4113 UW |
6322 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
6323 | return extract_signed_integer (buf, TYPE_LENGTH (type), byte_order); | |
fc0c74b1 AC |
6324 | } |
6325 | ||
82e91389 DJ |
6326 | /* Dummy virtual frame pointer method. This is no more or less accurate |
6327 | than most other architectures; we just need to be explicit about it, | |
6328 | because the pseudo-register gdbarch_sp_regnum will otherwise lead to | |
6329 | an assertion failure. */ | |
6330 | ||
6331 | static void | |
a54fba4c MD |
6332 | mips_virtual_frame_pointer (struct gdbarch *gdbarch, |
6333 | CORE_ADDR pc, int *reg, LONGEST *offset) | |
82e91389 DJ |
6334 | { |
6335 | *reg = MIPS_SP_REGNUM; | |
6336 | *offset = 0; | |
6337 | } | |
6338 | ||
caaa3122 DJ |
6339 | static void |
6340 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
6341 | { | |
6342 | enum mips_abi *abip = (enum mips_abi *) obj; | |
6343 | const char *name = bfd_get_section_name (abfd, sect); | |
6344 | ||
6345 | if (*abip != MIPS_ABI_UNKNOWN) | |
6346 | return; | |
6347 | ||
6348 | if (strncmp (name, ".mdebug.", 8) != 0) | |
6349 | return; | |
6350 | ||
6351 | if (strcmp (name, ".mdebug.abi32") == 0) | |
6352 | *abip = MIPS_ABI_O32; | |
6353 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
6354 | *abip = MIPS_ABI_N32; | |
62a49b2c | 6355 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 6356 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
6357 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
6358 | *abip = MIPS_ABI_O64; | |
6359 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
6360 | *abip = MIPS_ABI_EABI32; | |
6361 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
6362 | *abip = MIPS_ABI_EABI64; | |
6363 | else | |
8a3fe4f8 | 6364 | warning (_("unsupported ABI %s."), name + 8); |
caaa3122 DJ |
6365 | } |
6366 | ||
22e47e37 FF |
6367 | static void |
6368 | mips_find_long_section (bfd *abfd, asection *sect, void *obj) | |
6369 | { | |
6370 | int *lbp = (int *) obj; | |
6371 | const char *name = bfd_get_section_name (abfd, sect); | |
6372 | ||
6373 | if (strncmp (name, ".gcc_compiled_long32", 20) == 0) | |
6374 | *lbp = 32; | |
6375 | else if (strncmp (name, ".gcc_compiled_long64", 20) == 0) | |
6376 | *lbp = 64; | |
6377 | else if (strncmp (name, ".gcc_compiled_long", 18) == 0) | |
6378 | warning (_("unrecognized .gcc_compiled_longXX")); | |
6379 | } | |
6380 | ||
2e4ebe70 DJ |
6381 | static enum mips_abi |
6382 | global_mips_abi (void) | |
6383 | { | |
6384 | int i; | |
6385 | ||
6386 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
6387 | if (mips_abi_strings[i] == mips_abi_string) | |
6388 | return (enum mips_abi) i; | |
6389 | ||
e2e0b3e5 | 6390 | internal_error (__FILE__, __LINE__, _("unknown ABI string")); |
2e4ebe70 DJ |
6391 | } |
6392 | ||
29709017 DJ |
6393 | static void |
6394 | mips_register_g_packet_guesses (struct gdbarch *gdbarch) | |
6395 | { | |
29709017 DJ |
6396 | /* If the size matches the set of 32-bit or 64-bit integer registers, |
6397 | assume that's what we've got. */ | |
4eb0ad19 DJ |
6398 | register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32); |
6399 | register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64); | |
29709017 DJ |
6400 | |
6401 | /* If the size matches the full set of registers GDB traditionally | |
6402 | knows about, including floating point, for either 32-bit or | |
6403 | 64-bit, assume that's what we've got. */ | |
4eb0ad19 DJ |
6404 | register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32); |
6405 | register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64); | |
29709017 DJ |
6406 | |
6407 | /* Otherwise we don't have a useful guess. */ | |
6408 | } | |
6409 | ||
f8b73d13 DJ |
6410 | static struct value * |
6411 | value_of_mips_user_reg (struct frame_info *frame, const void *baton) | |
6412 | { | |
6413 | const int *reg_p = baton; | |
6414 | return value_of_register (*reg_p, frame); | |
6415 | } | |
6416 | ||
c2d11a7d | 6417 | static struct gdbarch * |
6d82d43b | 6418 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 6419 | { |
c2d11a7d JM |
6420 | struct gdbarch *gdbarch; |
6421 | struct gdbarch_tdep *tdep; | |
6422 | int elf_flags; | |
2e4ebe70 | 6423 | enum mips_abi mips_abi, found_abi, wanted_abi; |
f8b73d13 | 6424 | int i, num_regs; |
8d5838b5 | 6425 | enum mips_fpu_type fpu_type; |
f8b73d13 | 6426 | struct tdesc_arch_data *tdesc_data = NULL; |
609ca2b9 | 6427 | int elf_fpu_type = 0; |
1faeff08 MR |
6428 | const char **reg_names; |
6429 | struct mips_regnum mips_regnum, *regnum; | |
6430 | int dspacc; | |
6431 | int dspctl; | |
6432 | ||
6433 | /* Fill in the OS dependent register numbers and names. */ | |
6434 | if (info.osabi == GDB_OSABI_IRIX) | |
6435 | { | |
6436 | mips_regnum.fp0 = 32; | |
6437 | mips_regnum.pc = 64; | |
6438 | mips_regnum.cause = 65; | |
6439 | mips_regnum.badvaddr = 66; | |
6440 | mips_regnum.hi = 67; | |
6441 | mips_regnum.lo = 68; | |
6442 | mips_regnum.fp_control_status = 69; | |
6443 | mips_regnum.fp_implementation_revision = 70; | |
6444 | mips_regnum.dspacc = dspacc = -1; | |
6445 | mips_regnum.dspctl = dspctl = -1; | |
6446 | num_regs = 71; | |
6447 | reg_names = mips_irix_reg_names; | |
6448 | } | |
6449 | else if (info.osabi == GDB_OSABI_LINUX) | |
6450 | { | |
6451 | mips_regnum.fp0 = 38; | |
6452 | mips_regnum.pc = 37; | |
6453 | mips_regnum.cause = 36; | |
6454 | mips_regnum.badvaddr = 35; | |
6455 | mips_regnum.hi = 34; | |
6456 | mips_regnum.lo = 33; | |
6457 | mips_regnum.fp_control_status = 70; | |
6458 | mips_regnum.fp_implementation_revision = 71; | |
6459 | mips_regnum.dspacc = -1; | |
6460 | mips_regnum.dspctl = -1; | |
6461 | dspacc = 72; | |
6462 | dspctl = 78; | |
6463 | num_regs = 79; | |
6464 | reg_names = mips_linux_reg_names; | |
6465 | } | |
6466 | else | |
6467 | { | |
6468 | mips_regnum.lo = MIPS_EMBED_LO_REGNUM; | |
6469 | mips_regnum.hi = MIPS_EMBED_HI_REGNUM; | |
6470 | mips_regnum.badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
6471 | mips_regnum.cause = MIPS_EMBED_CAUSE_REGNUM; | |
6472 | mips_regnum.pc = MIPS_EMBED_PC_REGNUM; | |
6473 | mips_regnum.fp0 = MIPS_EMBED_FP0_REGNUM; | |
6474 | mips_regnum.fp_control_status = 70; | |
6475 | mips_regnum.fp_implementation_revision = 71; | |
6476 | mips_regnum.dspacc = dspacc = -1; | |
6477 | mips_regnum.dspctl = dspctl = -1; | |
6478 | num_regs = MIPS_LAST_EMBED_REGNUM + 1; | |
6479 | if (info.bfd_arch_info != NULL | |
6480 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
6481 | reg_names = mips_tx39_reg_names; | |
6482 | else | |
6483 | reg_names = mips_generic_reg_names; | |
6484 | } | |
f8b73d13 DJ |
6485 | |
6486 | /* Check any target description for validity. */ | |
6487 | if (tdesc_has_registers (info.target_desc)) | |
6488 | { | |
6489 | static const char *const mips_gprs[] = { | |
6490 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
6491 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
6492 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
6493 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
6494 | }; | |
6495 | static const char *const mips_fprs[] = { | |
6496 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
6497 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
6498 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
6499 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
6500 | }; | |
6501 | ||
6502 | const struct tdesc_feature *feature; | |
6503 | int valid_p; | |
6504 | ||
6505 | feature = tdesc_find_feature (info.target_desc, | |
6506 | "org.gnu.gdb.mips.cpu"); | |
6507 | if (feature == NULL) | |
6508 | return NULL; | |
6509 | ||
6510 | tdesc_data = tdesc_data_alloc (); | |
6511 | ||
6512 | valid_p = 1; | |
6513 | for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) | |
6514 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
6515 | mips_gprs[i]); | |
6516 | ||
6517 | ||
6518 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 6519 | mips_regnum.lo, "lo"); |
f8b73d13 | 6520 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
1faeff08 | 6521 | mips_regnum.hi, "hi"); |
f8b73d13 | 6522 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
1faeff08 | 6523 | mips_regnum.pc, "pc"); |
f8b73d13 DJ |
6524 | |
6525 | if (!valid_p) | |
6526 | { | |
6527 | tdesc_data_cleanup (tdesc_data); | |
6528 | return NULL; | |
6529 | } | |
6530 | ||
6531 | feature = tdesc_find_feature (info.target_desc, | |
6532 | "org.gnu.gdb.mips.cp0"); | |
6533 | if (feature == NULL) | |
6534 | { | |
6535 | tdesc_data_cleanup (tdesc_data); | |
6536 | return NULL; | |
6537 | } | |
6538 | ||
6539 | valid_p = 1; | |
6540 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 6541 | mips_regnum.badvaddr, "badvaddr"); |
f8b73d13 DJ |
6542 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
6543 | MIPS_PS_REGNUM, "status"); | |
6544 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 6545 | mips_regnum.cause, "cause"); |
f8b73d13 DJ |
6546 | |
6547 | if (!valid_p) | |
6548 | { | |
6549 | tdesc_data_cleanup (tdesc_data); | |
6550 | return NULL; | |
6551 | } | |
6552 | ||
6553 | /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS | |
6554 | backend is not prepared for that, though. */ | |
6555 | feature = tdesc_find_feature (info.target_desc, | |
6556 | "org.gnu.gdb.mips.fpu"); | |
6557 | if (feature == NULL) | |
6558 | { | |
6559 | tdesc_data_cleanup (tdesc_data); | |
6560 | return NULL; | |
6561 | } | |
6562 | ||
6563 | valid_p = 1; | |
6564 | for (i = 0; i < 32; i++) | |
6565 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 6566 | i + mips_regnum.fp0, mips_fprs[i]); |
f8b73d13 DJ |
6567 | |
6568 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 MR |
6569 | mips_regnum.fp_control_status, |
6570 | "fcsr"); | |
6571 | valid_p | |
6572 | &= tdesc_numbered_register (feature, tdesc_data, | |
6573 | mips_regnum.fp_implementation_revision, | |
6574 | "fir"); | |
f8b73d13 DJ |
6575 | |
6576 | if (!valid_p) | |
6577 | { | |
6578 | tdesc_data_cleanup (tdesc_data); | |
6579 | return NULL; | |
6580 | } | |
6581 | ||
1faeff08 MR |
6582 | if (dspacc >= 0) |
6583 | { | |
6584 | feature = tdesc_find_feature (info.target_desc, | |
6585 | "org.gnu.gdb.mips.dsp"); | |
6586 | /* The DSP registers are optional; it's OK if they are absent. */ | |
6587 | if (feature != NULL) | |
6588 | { | |
6589 | i = 0; | |
6590 | valid_p = 1; | |
6591 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6592 | dspacc + i++, "hi1"); | |
6593 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6594 | dspacc + i++, "lo1"); | |
6595 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6596 | dspacc + i++, "hi2"); | |
6597 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6598 | dspacc + i++, "lo2"); | |
6599 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6600 | dspacc + i++, "hi3"); | |
6601 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6602 | dspacc + i++, "lo3"); | |
6603 | ||
6604 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6605 | dspctl, "dspctl"); | |
6606 | ||
6607 | if (!valid_p) | |
6608 | { | |
6609 | tdesc_data_cleanup (tdesc_data); | |
6610 | return NULL; | |
6611 | } | |
6612 | ||
6613 | mips_regnum.dspacc = dspacc; | |
6614 | mips_regnum.dspctl = dspctl; | |
6615 | } | |
6616 | } | |
6617 | ||
f8b73d13 DJ |
6618 | /* It would be nice to detect an attempt to use a 64-bit ABI |
6619 | when only 32-bit registers are provided. */ | |
1faeff08 | 6620 | reg_names = NULL; |
f8b73d13 | 6621 | } |
c2d11a7d | 6622 | |
ec03c1ac AC |
6623 | /* First of all, extract the elf_flags, if available. */ |
6624 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
6625 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
6626 | else if (arches != NULL) |
6627 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
6628 | else |
6629 | elf_flags = 0; | |
6630 | if (gdbarch_debug) | |
6631 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 6632 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 6633 | |
102182a9 | 6634 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
6635 | switch ((elf_flags & EF_MIPS_ABI)) |
6636 | { | |
6637 | case E_MIPS_ABI_O32: | |
ec03c1ac | 6638 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
6639 | break; |
6640 | case E_MIPS_ABI_O64: | |
ec03c1ac | 6641 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
6642 | break; |
6643 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 6644 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
6645 | break; |
6646 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 6647 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
6648 | break; |
6649 | default: | |
acdb74a0 | 6650 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 6651 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 6652 | else |
ec03c1ac | 6653 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
6654 | break; |
6655 | } | |
acdb74a0 | 6656 | |
caaa3122 | 6657 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
6658 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
6659 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 6660 | |
dc305454 | 6661 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
6662 | MIPS architecture (if there is one). */ |
6663 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
6664 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 6665 | |
32a6503c | 6666 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 6667 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
6668 | && info.bfd_arch_info != NULL |
6669 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
6670 | { | |
6671 | switch (info.bfd_arch_info->mach) | |
6672 | { | |
6673 | case bfd_mach_mips3900: | |
ec03c1ac | 6674 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
6675 | break; |
6676 | case bfd_mach_mips4100: | |
6677 | case bfd_mach_mips5000: | |
ec03c1ac | 6678 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 6679 | break; |
1d06468c EZ |
6680 | case bfd_mach_mips8000: |
6681 | case bfd_mach_mips10000: | |
32a6503c KB |
6682 | /* On Irix, ELF64 executables use the N64 ABI. The |
6683 | pseudo-sections which describe the ABI aren't present | |
6684 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
6685 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
6686 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 6687 | found_abi = MIPS_ABI_N64; |
28d169de | 6688 | else |
ec03c1ac | 6689 | found_abi = MIPS_ABI_N32; |
1d06468c | 6690 | break; |
bf64bfd6 AC |
6691 | } |
6692 | } | |
2e4ebe70 | 6693 | |
26c53e50 DJ |
6694 | /* Default 64-bit objects to N64 instead of O32. */ |
6695 | if (found_abi == MIPS_ABI_UNKNOWN | |
6696 | && info.abfd != NULL | |
6697 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
6698 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
6699 | found_abi = MIPS_ABI_N64; | |
6700 | ||
ec03c1ac AC |
6701 | if (gdbarch_debug) |
6702 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
6703 | found_abi); | |
6704 | ||
6705 | /* What has the user specified from the command line? */ | |
6706 | wanted_abi = global_mips_abi (); | |
6707 | if (gdbarch_debug) | |
6708 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
6709 | wanted_abi); | |
2e4ebe70 DJ |
6710 | |
6711 | /* Now that we have found what the ABI for this binary would be, | |
6712 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
6713 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
6714 | mips_abi = wanted_abi; | |
ec03c1ac AC |
6715 | else if (found_abi != MIPS_ABI_UNKNOWN) |
6716 | mips_abi = found_abi; | |
6717 | else | |
6718 | mips_abi = MIPS_ABI_O32; | |
6719 | if (gdbarch_debug) | |
6720 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
6721 | mips_abi); | |
2e4ebe70 | 6722 | |
ec03c1ac | 6723 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 6724 | if (gdbarch_debug) |
ec03c1ac | 6725 | fprintf_unfiltered (gdb_stdlog, |
025bb325 MS |
6726 | "mips_gdbarch_init: " |
6727 | "mips64_transfers_32bit_regs_p = %d\n", | |
ec03c1ac | 6728 | mips64_transfers_32bit_regs_p); |
0dadbba0 | 6729 | |
8d5838b5 | 6730 | /* Determine the MIPS FPU type. */ |
609ca2b9 DJ |
6731 | #ifdef HAVE_ELF |
6732 | if (info.abfd | |
6733 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
6734 | elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
6735 | Tag_GNU_MIPS_ABI_FP); | |
6736 | #endif /* HAVE_ELF */ | |
6737 | ||
8d5838b5 AC |
6738 | if (!mips_fpu_type_auto) |
6739 | fpu_type = mips_fpu_type; | |
609ca2b9 DJ |
6740 | else if (elf_fpu_type != 0) |
6741 | { | |
6742 | switch (elf_fpu_type) | |
6743 | { | |
6744 | case 1: | |
6745 | fpu_type = MIPS_FPU_DOUBLE; | |
6746 | break; | |
6747 | case 2: | |
6748 | fpu_type = MIPS_FPU_SINGLE; | |
6749 | break; | |
6750 | case 3: | |
6751 | default: | |
6752 | /* Soft float or unknown. */ | |
6753 | fpu_type = MIPS_FPU_NONE; | |
6754 | break; | |
6755 | } | |
6756 | } | |
8d5838b5 AC |
6757 | else if (info.bfd_arch_info != NULL |
6758 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
6759 | switch (info.bfd_arch_info->mach) | |
6760 | { | |
6761 | case bfd_mach_mips3900: | |
6762 | case bfd_mach_mips4100: | |
6763 | case bfd_mach_mips4111: | |
a9d61c86 | 6764 | case bfd_mach_mips4120: |
8d5838b5 AC |
6765 | fpu_type = MIPS_FPU_NONE; |
6766 | break; | |
6767 | case bfd_mach_mips4650: | |
6768 | fpu_type = MIPS_FPU_SINGLE; | |
6769 | break; | |
6770 | default: | |
6771 | fpu_type = MIPS_FPU_DOUBLE; | |
6772 | break; | |
6773 | } | |
6774 | else if (arches != NULL) | |
6775 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
6776 | else | |
6777 | fpu_type = MIPS_FPU_DOUBLE; | |
6778 | if (gdbarch_debug) | |
6779 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 6780 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 6781 | |
29709017 DJ |
6782 | /* Check for blatant incompatibilities. */ |
6783 | ||
6784 | /* If we have only 32-bit registers, then we can't debug a 64-bit | |
6785 | ABI. */ | |
6786 | if (info.target_desc | |
6787 | && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL | |
6788 | && mips_abi != MIPS_ABI_EABI32 | |
6789 | && mips_abi != MIPS_ABI_O32) | |
f8b73d13 DJ |
6790 | { |
6791 | if (tdesc_data != NULL) | |
6792 | tdesc_data_cleanup (tdesc_data); | |
6793 | return NULL; | |
6794 | } | |
29709017 | 6795 | |
025bb325 | 6796 | /* Try to find a pre-existing architecture. */ |
c2d11a7d JM |
6797 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
6798 | arches != NULL; | |
6799 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
6800 | { | |
6801 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 6802 | using. */ |
9103eae0 | 6803 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 6804 | continue; |
9103eae0 | 6805 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 6806 | continue; |
719ec221 AC |
6807 | /* Need to be pedantic about which register virtual size is |
6808 | used. */ | |
6809 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
6810 | != mips64_transfers_32bit_regs_p) | |
6811 | continue; | |
8d5838b5 AC |
6812 | /* Be pedantic about which FPU is selected. */ |
6813 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
6814 | continue; | |
f8b73d13 DJ |
6815 | |
6816 | if (tdesc_data != NULL) | |
6817 | tdesc_data_cleanup (tdesc_data); | |
4be87837 | 6818 | return arches->gdbarch; |
c2d11a7d JM |
6819 | } |
6820 | ||
102182a9 | 6821 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
6822 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
6823 | gdbarch = gdbarch_alloc (&info, tdep); | |
6824 | tdep->elf_flags = elf_flags; | |
719ec221 | 6825 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
6826 | tdep->found_abi = found_abi; |
6827 | tdep->mips_abi = mips_abi; | |
8d5838b5 | 6828 | tdep->mips_fpu_type = fpu_type; |
29709017 DJ |
6829 | tdep->register_size_valid_p = 0; |
6830 | tdep->register_size = 0; | |
50e8a0d5 HZ |
6831 | tdep->gregset = NULL; |
6832 | tdep->gregset64 = NULL; | |
6833 | tdep->fpregset = NULL; | |
6834 | tdep->fpregset64 = NULL; | |
29709017 DJ |
6835 | |
6836 | if (info.target_desc) | |
6837 | { | |
6838 | /* Some useful properties can be inferred from the target. */ | |
6839 | if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) | |
6840 | { | |
6841 | tdep->register_size_valid_p = 1; | |
6842 | tdep->register_size = 4; | |
6843 | } | |
6844 | else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) | |
6845 | { | |
6846 | tdep->register_size_valid_p = 1; | |
6847 | tdep->register_size = 8; | |
6848 | } | |
6849 | } | |
c2d11a7d | 6850 | |
102182a9 | 6851 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
6852 | set_gdbarch_short_bit (gdbarch, 16); |
6853 | set_gdbarch_int_bit (gdbarch, 32); | |
6854 | set_gdbarch_float_bit (gdbarch, 32); | |
6855 | set_gdbarch_double_bit (gdbarch, 64); | |
6856 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
6857 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
6858 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
6859 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 6860 | |
175ff332 HZ |
6861 | set_gdbarch_ax_pseudo_register_collect (gdbarch, |
6862 | mips_ax_pseudo_register_collect); | |
6863 | set_gdbarch_ax_pseudo_register_push_stack | |
6864 | (gdbarch, mips_ax_pseudo_register_push_stack); | |
6865 | ||
6d82d43b | 6866 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
6867 | mips_elf_make_msymbol_special); |
6868 | ||
1faeff08 MR |
6869 | regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, struct mips_regnum); |
6870 | *regnum = mips_regnum; | |
1faeff08 MR |
6871 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
6872 | set_gdbarch_num_regs (gdbarch, num_regs); | |
6873 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
6874 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
6875 | set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer); | |
6876 | tdep->mips_processor_reg_names = reg_names; | |
6877 | tdep->regnum = regnum; | |
fe29b929 | 6878 | |
0dadbba0 | 6879 | switch (mips_abi) |
c2d11a7d | 6880 | { |
0dadbba0 | 6881 | case MIPS_ABI_O32: |
25ab4790 | 6882 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 6883 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
4c7d22cb | 6884 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 6885 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 6886 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6887 | set_gdbarch_long_bit (gdbarch, 32); |
6888 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6889 | set_gdbarch_long_long_bit (gdbarch, 64); | |
6890 | break; | |
0dadbba0 | 6891 | case MIPS_ABI_O64: |
25ab4790 | 6892 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
9c8fdbfa | 6893 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
4c7d22cb | 6894 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 6895 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 6896 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6897 | set_gdbarch_long_bit (gdbarch, 32); |
6898 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6899 | set_gdbarch_long_long_bit (gdbarch, 64); | |
6900 | break; | |
0dadbba0 | 6901 | case MIPS_ABI_EABI32: |
25ab4790 | 6902 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 6903 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 6904 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 6905 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 6906 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6907 | set_gdbarch_long_bit (gdbarch, 32); |
6908 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6909 | set_gdbarch_long_long_bit (gdbarch, 64); | |
6910 | break; | |
0dadbba0 | 6911 | case MIPS_ABI_EABI64: |
25ab4790 | 6912 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 6913 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 6914 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 6915 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 6916 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6917 | set_gdbarch_long_bit (gdbarch, 64); |
6918 | set_gdbarch_ptr_bit (gdbarch, 64); | |
6919 | set_gdbarch_long_long_bit (gdbarch, 64); | |
6920 | break; | |
0dadbba0 | 6921 | case MIPS_ABI_N32: |
25ab4790 | 6922 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 6923 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 6924 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 6925 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 6926 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
6927 | set_gdbarch_long_bit (gdbarch, 32); |
6928 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6929 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 6930 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 6931 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
28d169de KB |
6932 | break; |
6933 | case MIPS_ABI_N64: | |
25ab4790 | 6934 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 6935 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 6936 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 6937 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
6938 | tdep->default_mask_address_p = 0; |
6939 | set_gdbarch_long_bit (gdbarch, 64); | |
6940 | set_gdbarch_ptr_bit (gdbarch, 64); | |
6941 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 6942 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 6943 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
0dadbba0 | 6944 | break; |
c2d11a7d | 6945 | default: |
e2e0b3e5 | 6946 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); |
c2d11a7d JM |
6947 | } |
6948 | ||
22e47e37 FF |
6949 | /* GCC creates a pseudo-section whose name specifies the size of |
6950 | longs, since -mlong32 or -mlong64 may be used independent of | |
6951 | other options. How those options affect pointer sizes is ABI and | |
6952 | architecture dependent, so use them to override the default sizes | |
6953 | set by the ABI. This table shows the relationship between ABI, | |
6954 | -mlongXX, and size of pointers: | |
6955 | ||
6956 | ABI -mlongXX ptr bits | |
6957 | --- -------- -------- | |
6958 | o32 32 32 | |
6959 | o32 64 32 | |
6960 | n32 32 32 | |
6961 | n32 64 64 | |
6962 | o64 32 32 | |
6963 | o64 64 64 | |
6964 | n64 32 32 | |
6965 | n64 64 64 | |
6966 | eabi32 32 32 | |
6967 | eabi32 64 32 | |
6968 | eabi64 32 32 | |
6969 | eabi64 64 64 | |
6970 | ||
6971 | Note that for o32 and eabi32, pointers are always 32 bits | |
6972 | regardless of any -mlongXX option. For all others, pointers and | |
025bb325 | 6973 | longs are the same, as set by -mlongXX or set by defaults. */ |
22e47e37 FF |
6974 | |
6975 | if (info.abfd != NULL) | |
6976 | { | |
6977 | int long_bit = 0; | |
6978 | ||
6979 | bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); | |
6980 | if (long_bit) | |
6981 | { | |
6982 | set_gdbarch_long_bit (gdbarch, long_bit); | |
6983 | switch (mips_abi) | |
6984 | { | |
6985 | case MIPS_ABI_O32: | |
6986 | case MIPS_ABI_EABI32: | |
6987 | break; | |
6988 | case MIPS_ABI_N32: | |
6989 | case MIPS_ABI_O64: | |
6990 | case MIPS_ABI_N64: | |
6991 | case MIPS_ABI_EABI64: | |
6992 | set_gdbarch_ptr_bit (gdbarch, long_bit); | |
6993 | break; | |
6994 | default: | |
6995 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); | |
6996 | } | |
6997 | } | |
6998 | } | |
6999 | ||
a5ea2558 AC |
7000 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
7001 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
7002 | comment: | |
7003 | ||
7004 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
7005 | flag in object files because to do so would make it impossible to | |
102182a9 | 7006 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 7007 | unnecessarily restrictive. |
361d1df0 | 7008 | |
a5ea2558 AC |
7009 | We could solve this problem by adding "-gp32" multilibs to gcc, |
7010 | but to set this flag before gcc is built with such multilibs will | |
7011 | break too many systems.'' | |
7012 | ||
7013 | But even more unhelpfully, the default linker output target for | |
7014 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
7015 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 7016 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
7017 | this flag to detect 32-bit mode would do the wrong thing given |
7018 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 7019 | as 32-bit programs by default. */ |
a5ea2558 | 7020 | |
6c997a34 | 7021 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 7022 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
c2d11a7d | 7023 | |
102182a9 MS |
7024 | /* Add/remove bits from an address. The MIPS needs be careful to |
7025 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
7026 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
7027 | ||
58dfe9ff AC |
7028 | /* Unwind the frame. */ |
7029 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
30244cd8 | 7030 | set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); |
b8a22b94 | 7031 | set_gdbarch_dummy_id (gdbarch, mips_dummy_id); |
10312cc4 | 7032 | |
102182a9 | 7033 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 7034 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
7035 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
7036 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
6d82d43b AC |
7037 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, |
7038 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 7039 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 7040 | |
025bb325 | 7041 | /* MIPS version of CALL_DUMMY. */ |
c2d11a7d | 7042 | |
2c76a0c7 JB |
7043 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
7044 | set_gdbarch_push_dummy_code (gdbarch, mips_push_dummy_code); | |
dc604539 | 7045 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 7046 | |
87783b8b AC |
7047 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
7048 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
7049 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
7050 | ||
f7b9e9fc AC |
7051 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
7052 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
c8cef75f MR |
7053 | set_gdbarch_adjust_breakpoint_address (gdbarch, |
7054 | mips_adjust_breakpoint_address); | |
f7b9e9fc AC |
7055 | |
7056 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 7057 | |
97ab0fdd MR |
7058 | set_gdbarch_in_function_epilogue_p (gdbarch, mips_in_function_epilogue_p); |
7059 | ||
fc0c74b1 AC |
7060 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
7061 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
7062 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 7063 | |
a4b8ebc8 | 7064 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 7065 | |
e11c53d2 | 7066 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 7067 | |
9dae60cc UW |
7068 | if (mips_abi == MIPS_ABI_N32) |
7069 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n32); | |
7070 | else if (mips_abi == MIPS_ABI_N64) | |
7071 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n64); | |
7072 | else | |
7073 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); | |
e5ab0dce | 7074 | |
d92524f1 PM |
7075 | /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint, |
7076 | HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint | |
3a3bc038 | 7077 | need to all be folded into the target vector. Since they are |
d92524f1 PM |
7078 | being used as guards for target_stopped_by_watchpoint, why not have |
7079 | target_stopped_by_watchpoint return the type of watchpoint that the code | |
3a3bc038 AC |
7080 | is sitting on? */ |
7081 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
7082 | ||
e7d6a6d2 | 7083 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
757a7cc6 | 7084 | |
14132e89 MR |
7085 | /* NOTE drow/2012-04-25: We overload the core solib trampoline code |
7086 | to support MIPS16. This is a bad thing. Make sure not to do it | |
7087 | if we have an OS ABI that actually supports shared libraries, since | |
7088 | shared library support is more important. If we have an OS someday | |
7089 | that supports both shared libraries and MIPS16, we'll have to find | |
7090 | a better place for these. | |
7091 | macro/2012-04-25: But that applies to return trampolines only and | |
7092 | currently no MIPS OS ABI uses shared libraries that have them. */ | |
7093 | set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); | |
7094 | ||
025bb325 MS |
7095 | set_gdbarch_single_step_through_delay (gdbarch, |
7096 | mips_single_step_through_delay); | |
3352ef37 | 7097 | |
0d5de010 DJ |
7098 | /* Virtual tables. */ |
7099 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
7100 | ||
29709017 DJ |
7101 | mips_register_g_packet_guesses (gdbarch); |
7102 | ||
6de918a6 | 7103 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
822b6570 | 7104 | info.tdep_info = (void *) tdesc_data; |
6de918a6 | 7105 | gdbarch_init_osabi (info, gdbarch); |
757a7cc6 | 7106 | |
9aac7884 MR |
7107 | /* The hook may have adjusted num_regs, fetch the final value and |
7108 | set pc_regnum and sp_regnum now that it has been fixed. */ | |
7109 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been | |
7110 | replaced by gdbarch_read_pc? */ | |
7111 | num_regs = gdbarch_num_regs (gdbarch); | |
7112 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); | |
7113 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
7114 | ||
5792a79b | 7115 | /* Unwind the frame. */ |
b8a22b94 DJ |
7116 | dwarf2_append_unwinders (gdbarch); |
7117 | frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind); | |
7118 | frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind); | |
7119 | frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind); | |
2bd0c3d7 | 7120 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
eec63939 | 7121 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
45c9dd44 AC |
7122 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
7123 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); | |
5792a79b | 7124 | |
f8b73d13 DJ |
7125 | if (tdesc_data) |
7126 | { | |
7127 | set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); | |
7cc46491 | 7128 | tdesc_use_registers (gdbarch, info.target_desc, tdesc_data); |
f8b73d13 DJ |
7129 | |
7130 | /* Override the normal target description methods to handle our | |
7131 | dual real and pseudo registers. */ | |
7132 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
025bb325 MS |
7133 | set_gdbarch_register_reggroup_p (gdbarch, |
7134 | mips_tdesc_register_reggroup_p); | |
f8b73d13 DJ |
7135 | |
7136 | num_regs = gdbarch_num_regs (gdbarch); | |
7137 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
7138 | set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs); | |
7139 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
7140 | } | |
7141 | ||
7142 | /* Add ABI-specific aliases for the registers. */ | |
7143 | if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) | |
7144 | for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++) | |
7145 | user_reg_add (gdbarch, mips_n32_n64_aliases[i].name, | |
7146 | value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); | |
7147 | else | |
7148 | for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) | |
7149 | user_reg_add (gdbarch, mips_o32_aliases[i].name, | |
7150 | value_of_mips_user_reg, &mips_o32_aliases[i].regnum); | |
7151 | ||
7152 | /* Add some other standard aliases. */ | |
7153 | for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) | |
7154 | user_reg_add (gdbarch, mips_register_aliases[i].name, | |
7155 | value_of_mips_user_reg, &mips_register_aliases[i].regnum); | |
7156 | ||
865093a3 AR |
7157 | for (i = 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++) |
7158 | user_reg_add (gdbarch, mips_numeric_register_aliases[i].name, | |
7159 | value_of_mips_user_reg, | |
7160 | &mips_numeric_register_aliases[i].regnum); | |
7161 | ||
4b9b3959 AC |
7162 | return gdbarch; |
7163 | } | |
7164 | ||
2e4ebe70 | 7165 | static void |
6d82d43b | 7166 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
7167 | { |
7168 | struct gdbarch_info info; | |
7169 | ||
7170 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
7171 | mips_gdbarch_init will take care of the rest. */ | |
7172 | gdbarch_info_init (&info); | |
7173 | gdbarch_update_p (info); | |
7174 | } | |
7175 | ||
ad188201 KB |
7176 | /* Print out which MIPS ABI is in use. */ |
7177 | ||
7178 | static void | |
1f8ca57c JB |
7179 | show_mips_abi (struct ui_file *file, |
7180 | int from_tty, | |
7181 | struct cmd_list_element *ignored_cmd, | |
7182 | const char *ignored_value) | |
ad188201 | 7183 | { |
1cf3db46 | 7184 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips) |
1f8ca57c JB |
7185 | fprintf_filtered |
7186 | (file, | |
7187 | "The MIPS ABI is unknown because the current architecture " | |
7188 | "is not MIPS.\n"); | |
ad188201 KB |
7189 | else |
7190 | { | |
7191 | enum mips_abi global_abi = global_mips_abi (); | |
1cf3db46 | 7192 | enum mips_abi actual_abi = mips_abi (target_gdbarch); |
ad188201 KB |
7193 | const char *actual_abi_str = mips_abi_strings[actual_abi]; |
7194 | ||
7195 | if (global_abi == MIPS_ABI_UNKNOWN) | |
1f8ca57c JB |
7196 | fprintf_filtered |
7197 | (file, | |
7198 | "The MIPS ABI is set automatically (currently \"%s\").\n", | |
6d82d43b | 7199 | actual_abi_str); |
ad188201 | 7200 | else if (global_abi == actual_abi) |
1f8ca57c JB |
7201 | fprintf_filtered |
7202 | (file, | |
7203 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6d82d43b | 7204 | actual_abi_str); |
ad188201 KB |
7205 | else |
7206 | { | |
7207 | /* Probably shouldn't happen... */ | |
025bb325 MS |
7208 | fprintf_filtered (file, |
7209 | "The (auto detected) MIPS ABI \"%s\" is in use " | |
7210 | "even though the user setting was \"%s\".\n", | |
6d82d43b | 7211 | actual_abi_str, mips_abi_strings[global_abi]); |
ad188201 KB |
7212 | } |
7213 | } | |
7214 | } | |
7215 | ||
4b9b3959 | 7216 | static void |
72a155b4 | 7217 | mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
4b9b3959 | 7218 | { |
72a155b4 | 7219 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4b9b3959 | 7220 | if (tdep != NULL) |
c2d11a7d | 7221 | { |
acdb74a0 AC |
7222 | int ef_mips_arch; |
7223 | int ef_mips_32bitmode; | |
f49e4e6d | 7224 | /* Determine the ISA. */ |
acdb74a0 AC |
7225 | switch (tdep->elf_flags & EF_MIPS_ARCH) |
7226 | { | |
7227 | case E_MIPS_ARCH_1: | |
7228 | ef_mips_arch = 1; | |
7229 | break; | |
7230 | case E_MIPS_ARCH_2: | |
7231 | ef_mips_arch = 2; | |
7232 | break; | |
7233 | case E_MIPS_ARCH_3: | |
7234 | ef_mips_arch = 3; | |
7235 | break; | |
7236 | case E_MIPS_ARCH_4: | |
93d56215 | 7237 | ef_mips_arch = 4; |
acdb74a0 AC |
7238 | break; |
7239 | default: | |
93d56215 | 7240 | ef_mips_arch = 0; |
acdb74a0 AC |
7241 | break; |
7242 | } | |
f49e4e6d | 7243 | /* Determine the size of a pointer. */ |
acdb74a0 | 7244 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); |
4b9b3959 AC |
7245 | fprintf_unfiltered (file, |
7246 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 7247 | tdep->elf_flags); |
4b9b3959 | 7248 | fprintf_unfiltered (file, |
acdb74a0 AC |
7249 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
7250 | ef_mips_32bitmode); | |
7251 | fprintf_unfiltered (file, | |
7252 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
7253 | ef_mips_arch); | |
7254 | fprintf_unfiltered (file, | |
7255 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 7256 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b | 7257 | fprintf_unfiltered (file, |
025bb325 MS |
7258 | "mips_dump_tdep: " |
7259 | "mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 7260 | mips_mask_address_p (tdep), |
4014092b | 7261 | tdep->default_mask_address_p); |
c2d11a7d | 7262 | } |
4b9b3959 AC |
7263 | fprintf_unfiltered (file, |
7264 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
7265 | MIPS_DEFAULT_FPU_TYPE, | |
7266 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
7267 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
7268 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
7269 | : "???")); | |
74ed0bb4 MD |
7270 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", |
7271 | MIPS_EABI (gdbarch)); | |
4b9b3959 AC |
7272 | fprintf_unfiltered (file, |
7273 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
74ed0bb4 MD |
7274 | MIPS_FPU_TYPE (gdbarch), |
7275 | (MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_NONE ? "none" | |
7276 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_SINGLE ? "single" | |
7277 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_DOUBLE ? "double" | |
4b9b3959 | 7278 | : "???")); |
c2d11a7d JM |
7279 | } |
7280 | ||
025bb325 | 7281 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 7282 | |
c906108c | 7283 | void |
acdb74a0 | 7284 | _initialize_mips_tdep (void) |
c906108c SS |
7285 | { |
7286 | static struct cmd_list_element *mipsfpulist = NULL; | |
7287 | struct cmd_list_element *c; | |
7288 | ||
6d82d43b | 7289 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
7290 | if (MIPS_ABI_LAST + 1 |
7291 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
e2e0b3e5 | 7292 | internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync")); |
2e4ebe70 | 7293 | |
4b9b3959 | 7294 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 7295 | |
8d5f9dcb DJ |
7296 | mips_pdr_data = register_objfile_data (); |
7297 | ||
4eb0ad19 DJ |
7298 | /* Create feature sets with the appropriate properties. The values |
7299 | are not important. */ | |
7300 | mips_tdesc_gp32 = allocate_target_description (); | |
7301 | set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, ""); | |
7302 | ||
7303 | mips_tdesc_gp64 = allocate_target_description (); | |
7304 | set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, ""); | |
7305 | ||
025bb325 | 7306 | /* Add root prefix command for all "set mips"/"show mips" commands. */ |
a5ea2558 | 7307 | add_prefix_cmd ("mips", no_class, set_mips_command, |
1bedd215 | 7308 | _("Various MIPS specific commands."), |
a5ea2558 AC |
7309 | &setmipscmdlist, "set mips ", 0, &setlist); |
7310 | ||
7311 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
1bedd215 | 7312 | _("Various MIPS specific commands."), |
a5ea2558 AC |
7313 | &showmipscmdlist, "show mips ", 0, &showlist); |
7314 | ||
025bb325 | 7315 | /* Allow the user to override the ABI. */ |
7ab04401 AC |
7316 | add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, |
7317 | &mips_abi_string, _("\ | |
7318 | Set the MIPS ABI used by this program."), _("\ | |
7319 | Show the MIPS ABI used by this program."), _("\ | |
7320 | This option can be set to one of:\n\ | |
7321 | auto - the default ABI associated with the current binary\n\ | |
7322 | o32\n\ | |
7323 | o64\n\ | |
7324 | n32\n\ | |
7325 | n64\n\ | |
7326 | eabi32\n\ | |
7327 | eabi64"), | |
7328 | mips_abi_update, | |
7329 | show_mips_abi, | |
7330 | &setmipscmdlist, &showmipscmdlist); | |
2e4ebe70 | 7331 | |
c906108c SS |
7332 | /* Let the user turn off floating point and set the fence post for |
7333 | heuristic_proc_start. */ | |
7334 | ||
7335 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
1bedd215 | 7336 | _("Set use of MIPS floating-point coprocessor."), |
c906108c SS |
7337 | &mipsfpulist, "set mipsfpu ", 0, &setlist); |
7338 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
1a966eab | 7339 | _("Select single-precision MIPS floating-point coprocessor."), |
c906108c SS |
7340 | &mipsfpulist); |
7341 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
1a966eab | 7342 | _("Select double-precision MIPS floating-point coprocessor."), |
c906108c SS |
7343 | &mipsfpulist); |
7344 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
7345 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
7346 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
7347 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
1a966eab | 7348 | _("Select no MIPS floating-point coprocessor."), &mipsfpulist); |
c906108c SS |
7349 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
7350 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
7351 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
7352 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
1a966eab | 7353 | _("Select MIPS floating-point coprocessor automatically."), |
c906108c SS |
7354 | &mipsfpulist); |
7355 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
1a966eab | 7356 | _("Show current use of MIPS floating-point coprocessor target."), |
c906108c SS |
7357 | &showlist); |
7358 | ||
c906108c SS |
7359 | /* We really would like to have both "0" and "unlimited" work, but |
7360 | command.c doesn't deal with that. So make it a var_zinteger | |
7361 | because the user can always use "999999" or some such for unlimited. */ | |
6bcadd06 | 7362 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
7915a72c AC |
7363 | &heuristic_fence_post, _("\ |
7364 | Set the distance searched for the start of a function."), _("\ | |
7365 | Show the distance searched for the start of a function."), _("\ | |
c906108c SS |
7366 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
7367 | program for the start of a function. This command sets the distance of the\n\ | |
7915a72c | 7368 | search. The only need to set it is when debugging a stripped executable."), |
2c5b56ce | 7369 | reinit_frame_cache_sfunc, |
025bb325 MS |
7370 | NULL, /* FIXME: i18n: The distance searched for |
7371 | the start of a function is %s. */ | |
6bcadd06 | 7372 | &setlist, &showlist); |
c906108c SS |
7373 | |
7374 | /* Allow the user to control whether the upper bits of 64-bit | |
7375 | addresses should be zeroed. */ | |
7915a72c AC |
7376 | add_setshow_auto_boolean_cmd ("mask-address", no_class, |
7377 | &mask_address_var, _("\ | |
7378 | Set zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
7379 | Show zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
cce7e648 | 7380 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\ |
7915a72c | 7381 | allow GDB to determine the correct value."), |
08546159 AC |
7382 | NULL, show_mask_address, |
7383 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
7384 | |
7385 | /* Allow the user to control the size of 32 bit registers within the | |
7386 | raw remote packet. */ | |
b3f42336 | 7387 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
7915a72c AC |
7388 | &mips64_transfers_32bit_regs_p, _("\ |
7389 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
7390 | _("\ | |
7391 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
7392 | _("\ | |
719ec221 AC |
7393 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
7394 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
7915a72c | 7395 | 64 bits for others. Use \"off\" to disable compatibility mode"), |
2c5b56ce | 7396 | set_mips64_transfers_32bit_regs, |
025bb325 MS |
7397 | NULL, /* FIXME: i18n: Compatibility with 64-bit |
7398 | MIPS target that transfers 32-bit | |
7399 | quantities is %s. */ | |
7915a72c | 7400 | &setlist, &showlist); |
9ace0497 | 7401 | |
025bb325 | 7402 | /* Debug this files internals. */ |
6bcadd06 | 7403 | add_setshow_zinteger_cmd ("mips", class_maintenance, |
7915a72c AC |
7404 | &mips_debug, _("\ |
7405 | Set mips debugging."), _("\ | |
7406 | Show mips debugging."), _("\ | |
7407 | When non-zero, mips specific debugging is enabled."), | |
2c5b56ce | 7408 | NULL, |
025bb325 MS |
7409 | NULL, /* FIXME: i18n: Mips debugging is |
7410 | currently %s. */ | |
6bcadd06 | 7411 | &setdebuglist, &showdebuglist); |
c906108c | 7412 | } |