Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
cda5a58a | 3 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, |
1e698235 | 4 | 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. |
bf64bfd6 | 5 | |
c906108c SS |
6 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
7 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
8 | ||
c5aa993b | 9 | This file is part of GDB. |
c906108c | 10 | |
c5aa993b JM |
11 | This program is free software; you can redistribute it and/or modify |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2 of the License, or | |
14 | (at your option) any later version. | |
c906108c | 15 | |
c5aa993b JM |
16 | This program is distributed in the hope that it will be useful, |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
c906108c | 20 | |
c5aa993b JM |
21 | You should have received a copy of the GNU General Public License |
22 | along with this program; if not, write to the Free Software | |
23 | Foundation, Inc., 59 Temple Place - Suite 330, | |
24 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
25 | |
26 | #include "defs.h" | |
27 | #include "gdb_string.h" | |
5e2e9765 | 28 | #include "gdb_assert.h" |
c906108c SS |
29 | #include "frame.h" |
30 | #include "inferior.h" | |
31 | #include "symtab.h" | |
32 | #include "value.h" | |
33 | #include "gdbcmd.h" | |
34 | #include "language.h" | |
35 | #include "gdbcore.h" | |
36 | #include "symfile.h" | |
37 | #include "objfiles.h" | |
38 | #include "gdbtypes.h" | |
39 | #include "target.h" | |
28d069e6 | 40 | #include "arch-utils.h" |
4e052eda | 41 | #include "regcache.h" |
70f80edf | 42 | #include "osabi.h" |
d1973055 | 43 | #include "mips-tdep.h" |
fe898f56 | 44 | #include "block.h" |
a4b8ebc8 | 45 | #include "reggroups.h" |
c906108c | 46 | #include "opcode/mips.h" |
c2d11a7d JM |
47 | #include "elf/mips.h" |
48 | #include "elf-bfd.h" | |
2475bac3 | 49 | #include "symcat.h" |
a4b8ebc8 | 50 | #include "sim-regno.h" |
a89aa300 | 51 | #include "dis-asm.h" |
c906108c | 52 | |
e0f7ec59 | 53 | static void set_reg_offset (CORE_ADDR *saved_regs, int regnum, CORE_ADDR off); |
5bbcb741 | 54 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 55 | |
dd824b04 DJ |
56 | /* A useful bit in the CP0 status register (PS_REGNUM). */ |
57 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ | |
58 | #define ST0_FR (1 << 26) | |
59 | ||
b0069a17 AC |
60 | /* The sizes of floating point registers. */ |
61 | ||
62 | enum | |
63 | { | |
64 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
65 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
66 | }; | |
67 | ||
0dadbba0 | 68 | |
2e4ebe70 DJ |
69 | static const char *mips_abi_string; |
70 | ||
71 | static const char *mips_abi_strings[] = { | |
72 | "auto", | |
73 | "n32", | |
74 | "o32", | |
28d169de | 75 | "n64", |
2e4ebe70 DJ |
76 | "o64", |
77 | "eabi32", | |
78 | "eabi64", | |
79 | NULL | |
80 | }; | |
81 | ||
cce74817 | 82 | struct frame_extra_info |
c5aa993b JM |
83 | { |
84 | mips_extra_func_info_t proc_desc; | |
85 | int num_args; | |
86 | }; | |
cce74817 | 87 | |
d929b26f AC |
88 | /* Various MIPS ISA options (related to stack analysis) can be |
89 | overridden dynamically. Establish an enum/array for managing | |
90 | them. */ | |
91 | ||
53904c9e AC |
92 | static const char size_auto[] = "auto"; |
93 | static const char size_32[] = "32"; | |
94 | static const char size_64[] = "64"; | |
d929b26f | 95 | |
53904c9e | 96 | static const char *size_enums[] = { |
d929b26f AC |
97 | size_auto, |
98 | size_32, | |
99 | size_64, | |
a5ea2558 AC |
100 | 0 |
101 | }; | |
102 | ||
7a292a7a SS |
103 | /* Some MIPS boards don't support floating point while others only |
104 | support single-precision floating-point operations. See also | |
105 | FP_REGISTER_DOUBLE. */ | |
c906108c SS |
106 | |
107 | enum mips_fpu_type | |
c5aa993b JM |
108 | { |
109 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
110 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
111 | MIPS_FPU_NONE /* No floating point. */ | |
112 | }; | |
c906108c SS |
113 | |
114 | #ifndef MIPS_DEFAULT_FPU_TYPE | |
115 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
116 | #endif | |
117 | static int mips_fpu_type_auto = 1; | |
118 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 119 | |
9ace0497 | 120 | static int mips_debug = 0; |
7a292a7a | 121 | |
c2d11a7d JM |
122 | /* MIPS specific per-architecture information */ |
123 | struct gdbarch_tdep | |
124 | { | |
125 | /* from the elf header */ | |
126 | int elf_flags; | |
70f80edf | 127 | |
c2d11a7d | 128 | /* mips options */ |
0dadbba0 | 129 | enum mips_abi mips_abi; |
2e4ebe70 | 130 | enum mips_abi found_abi; |
c2d11a7d JM |
131 | enum mips_fpu_type mips_fpu_type; |
132 | int mips_last_arg_regnum; | |
133 | int mips_last_fp_arg_regnum; | |
a5ea2558 | 134 | int mips_default_saved_regsize; |
c2d11a7d | 135 | int mips_fp_register_double; |
d929b26f | 136 | int mips_default_stack_argsize; |
4014092b | 137 | int default_mask_address_p; |
719ec221 AC |
138 | /* Is the target using 64-bit raw integer registers but only |
139 | storing a left-aligned 32-bit value in each? */ | |
140 | int mips64_transfers_32bit_regs_p; | |
56cea623 AC |
141 | /* Indexes for various registers. IRIX and embedded have |
142 | different values. This contains the "public" fields. Don't | |
143 | add any that do not need to be public. */ | |
144 | const struct mips_regnum *regnum; | |
691c0433 AC |
145 | /* Register names table for the current register set. */ |
146 | const char **mips_processor_reg_names; | |
c2d11a7d JM |
147 | }; |
148 | ||
56cea623 AC |
149 | const struct mips_regnum * |
150 | mips_regnum (struct gdbarch *gdbarch) | |
151 | { | |
152 | return gdbarch_tdep (gdbarch)->regnum; | |
153 | } | |
154 | ||
155 | static int | |
156 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
157 | { | |
158 | return mips_regnum (gdbarch)->fp0 + 12; | |
159 | } | |
160 | ||
0dadbba0 | 161 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \ |
216a600b | 162 | || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64) |
c2d11a7d | 163 | |
c2d11a7d | 164 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 165 | |
c2d11a7d | 166 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 167 | |
c2d11a7d | 168 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) |
c2d11a7d | 169 | |
d929b26f AC |
170 | /* Return the currently configured (or set) saved register size. */ |
171 | ||
a5ea2558 | 172 | #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize) |
c2d11a7d | 173 | |
53904c9e | 174 | static const char *mips_saved_regsize_string = size_auto; |
d929b26f AC |
175 | |
176 | #define MIPS_SAVED_REGSIZE (mips_saved_regsize()) | |
177 | ||
95404a3e AC |
178 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
179 | functions to test, set, or clear bit 0 of addresses. */ | |
180 | ||
181 | static CORE_ADDR | |
182 | is_mips16_addr (CORE_ADDR addr) | |
183 | { | |
184 | return ((addr) & 1); | |
185 | } | |
186 | ||
187 | static CORE_ADDR | |
188 | make_mips16_addr (CORE_ADDR addr) | |
189 | { | |
190 | return ((addr) | 1); | |
191 | } | |
192 | ||
193 | static CORE_ADDR | |
194 | unmake_mips16_addr (CORE_ADDR addr) | |
195 | { | |
196 | return ((addr) & ~1); | |
197 | } | |
198 | ||
22540ece AC |
199 | /* Return the contents of register REGNUM as a signed integer. */ |
200 | ||
201 | static LONGEST | |
202 | read_signed_register (int regnum) | |
203 | { | |
719ec221 | 204 | void *buf = alloca (register_size (current_gdbarch, regnum)); |
22540ece | 205 | deprecated_read_register_gen (regnum, buf); |
719ec221 | 206 | return (extract_signed_integer (buf, register_size (current_gdbarch, regnum))); |
22540ece AC |
207 | } |
208 | ||
209 | static LONGEST | |
210 | read_signed_register_pid (int regnum, ptid_t ptid) | |
211 | { | |
212 | ptid_t save_ptid; | |
213 | LONGEST retval; | |
214 | ||
215 | if (ptid_equal (ptid, inferior_ptid)) | |
216 | return read_signed_register (regnum); | |
217 | ||
218 | save_ptid = inferior_ptid; | |
219 | ||
220 | inferior_ptid = ptid; | |
221 | ||
222 | retval = read_signed_register (regnum); | |
223 | ||
224 | inferior_ptid = save_ptid; | |
225 | ||
226 | return retval; | |
227 | } | |
228 | ||
d1973055 KB |
229 | /* Return the MIPS ABI associated with GDBARCH. */ |
230 | enum mips_abi | |
231 | mips_abi (struct gdbarch *gdbarch) | |
232 | { | |
233 | return gdbarch_tdep (gdbarch)->mips_abi; | |
234 | } | |
235 | ||
4246e332 AC |
236 | int |
237 | mips_regsize (struct gdbarch *gdbarch) | |
238 | { | |
239 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word | |
240 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
241 | } | |
242 | ||
d929b26f | 243 | static unsigned int |
acdb74a0 | 244 | mips_saved_regsize (void) |
d929b26f AC |
245 | { |
246 | if (mips_saved_regsize_string == size_auto) | |
247 | return MIPS_DEFAULT_SAVED_REGSIZE; | |
248 | else if (mips_saved_regsize_string == size_64) | |
249 | return 8; | |
250 | else /* if (mips_saved_regsize_string == size_32) */ | |
251 | return 4; | |
252 | } | |
253 | ||
71b8ef93 | 254 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 255 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 256 | "info" field is used for this purpose. |
5a89d8aa MS |
257 | |
258 | ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special", | |
259 | i.e. refers to a 16-bit function, and sets a "special" bit in a | |
260 | minimal symbol to mark it as a 16-bit function | |
261 | ||
f594e5e9 | 262 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 263 | |
5a89d8aa MS |
264 | static void |
265 | mips_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym) | |
266 | { | |
267 | if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_MIPS16) | |
268 | { | |
269 | MSYMBOL_INFO (msym) = (char *) | |
270 | (((long) MSYMBOL_INFO (msym)) | 0x80000000); | |
271 | SYMBOL_VALUE_ADDRESS (msym) |= 1; | |
272 | } | |
273 | } | |
274 | ||
71b8ef93 MS |
275 | static int |
276 | msymbol_is_special (struct minimal_symbol *msym) | |
277 | { | |
278 | return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0); | |
279 | } | |
280 | ||
88658117 AC |
281 | /* XFER a value from the big/little/left end of the register. |
282 | Depending on the size of the value it might occupy the entire | |
283 | register or just part of it. Make an allowance for this, aligning | |
284 | things accordingly. */ | |
285 | ||
286 | static void | |
287 | mips_xfer_register (struct regcache *regcache, int reg_num, int length, | |
288 | enum bfd_endian endian, bfd_byte *in, const bfd_byte *out, | |
289 | int buf_offset) | |
290 | { | |
d9d9c31f | 291 | bfd_byte reg[MAX_REGISTER_SIZE]; |
88658117 | 292 | int reg_offset = 0; |
a4b8ebc8 | 293 | gdb_assert (reg_num >= NUM_REGS); |
cb1d2653 AC |
294 | /* Need to transfer the left or right part of the register, based on |
295 | the targets byte order. */ | |
88658117 AC |
296 | switch (endian) |
297 | { | |
298 | case BFD_ENDIAN_BIG: | |
719ec221 | 299 | reg_offset = register_size (current_gdbarch, reg_num) - length; |
88658117 AC |
300 | break; |
301 | case BFD_ENDIAN_LITTLE: | |
302 | reg_offset = 0; | |
303 | break; | |
304 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ | |
305 | reg_offset = 0; | |
306 | break; | |
307 | default: | |
308 | internal_error (__FILE__, __LINE__, "bad switch"); | |
309 | } | |
310 | if (mips_debug) | |
cb1d2653 AC |
311 | fprintf_unfiltered (gdb_stderr, |
312 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
313 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
314 | if (mips_debug && out != NULL) |
315 | { | |
316 | int i; | |
cb1d2653 | 317 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 318 | for (i = 0; i < length; i++) |
cb1d2653 | 319 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
320 | } |
321 | if (in != NULL) | |
a4b8ebc8 | 322 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, in + buf_offset); |
88658117 | 323 | if (out != NULL) |
a4b8ebc8 | 324 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, out + buf_offset); |
88658117 AC |
325 | if (mips_debug && in != NULL) |
326 | { | |
327 | int i; | |
cb1d2653 | 328 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 329 | for (i = 0; i < length; i++) |
cb1d2653 | 330 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
331 | } |
332 | if (mips_debug) | |
333 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
334 | } | |
335 | ||
dd824b04 DJ |
336 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
337 | compatiblity mode. A return value of 1 means that we have | |
338 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
339 | ||
340 | static int | |
341 | mips2_fp_compat (void) | |
342 | { | |
343 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not | |
344 | meaningful. */ | |
56cea623 | 345 | if (register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) == 4) |
dd824b04 DJ |
346 | return 0; |
347 | ||
348 | #if 0 | |
349 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
350 | in all the places we deal with FP registers. PR gdb/413. */ | |
351 | /* Otherwise check the FR bit in the status register - it controls | |
352 | the FP compatiblity mode. If it is clear we are in compatibility | |
353 | mode. */ | |
354 | if ((read_register (PS_REGNUM) & ST0_FR) == 0) | |
355 | return 1; | |
356 | #endif | |
361d1df0 | 357 | |
dd824b04 DJ |
358 | return 0; |
359 | } | |
360 | ||
c2d11a7d JM |
361 | /* Indicate that the ABI makes use of double-precision registers |
362 | provided by the FPU (rather than combining pairs of registers to | |
8fa9cfa1 | 363 | form double-precision values). See also MIPS_FPU_TYPE. */ |
c2d11a7d | 364 | #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double) |
c2d11a7d | 365 | |
d929b26f AC |
366 | /* The amount of space reserved on the stack for registers. This is |
367 | different to MIPS_SAVED_REGSIZE as it determines the alignment of | |
368 | data allocated after the registers have run out. */ | |
369 | ||
0dadbba0 | 370 | #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize) |
d929b26f AC |
371 | |
372 | #define MIPS_STACK_ARGSIZE (mips_stack_argsize ()) | |
373 | ||
53904c9e | 374 | static const char *mips_stack_argsize_string = size_auto; |
d929b26f AC |
375 | |
376 | static unsigned int | |
377 | mips_stack_argsize (void) | |
378 | { | |
379 | if (mips_stack_argsize_string == size_auto) | |
380 | return MIPS_DEFAULT_STACK_ARGSIZE; | |
381 | else if (mips_stack_argsize_string == size_64) | |
382 | return 8; | |
383 | else /* if (mips_stack_argsize_string == size_32) */ | |
384 | return 4; | |
385 | } | |
386 | ||
92e1c15c | 387 | #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p) |
92e1c15c | 388 | |
7a292a7a | 389 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 390 | |
570b8f7c AC |
391 | static mips_extra_func_info_t heuristic_proc_desc (CORE_ADDR, CORE_ADDR, |
392 | struct frame_info *, int); | |
c906108c | 393 | |
a14ed312 | 394 | static CORE_ADDR heuristic_proc_start (CORE_ADDR); |
c906108c | 395 | |
a14ed312 | 396 | static CORE_ADDR read_next_frame_reg (struct frame_info *, int); |
c906108c | 397 | |
a14ed312 | 398 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 399 | |
570b8f7c AC |
400 | static mips_extra_func_info_t find_proc_desc (CORE_ADDR pc, |
401 | struct frame_info *next_frame, | |
402 | int cur_frame); | |
c906108c | 403 | |
a14ed312 KB |
404 | static CORE_ADDR after_prologue (CORE_ADDR pc, |
405 | mips_extra_func_info_t proc_desc); | |
c906108c | 406 | |
67b2c998 DJ |
407 | static struct type *mips_float_register_type (void); |
408 | static struct type *mips_double_register_type (void); | |
409 | ||
acdb74a0 AC |
410 | /* The list of available "set mips " and "show mips " commands */ |
411 | ||
412 | static struct cmd_list_element *setmipscmdlist = NULL; | |
413 | static struct cmd_list_element *showmipscmdlist = NULL; | |
414 | ||
5e2e9765 KB |
415 | /* Integer registers 0 thru 31 are handled explicitly by |
416 | mips_register_name(). Processor specific registers 32 and above | |
691c0433 AC |
417 | are listed in the followign tables. */ |
418 | ||
419 | enum { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
420 | ||
421 | /* Generic MIPS. */ | |
422 | ||
423 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
424 | "sr", "lo", "hi", "bad", "cause","pc", | |
425 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
426 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
427 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
428 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
429 | "fsr", "fir", ""/*"fp"*/, "", | |
430 | "", "", "", "", "", "", "", "", | |
431 | "", "", "", "", "", "", "", "", | |
432 | }; | |
433 | ||
434 | /* Names of IDT R3041 registers. */ | |
435 | ||
436 | static const char *mips_r3041_reg_names[] = { | |
437 | "sr", "lo", "hi", "bad", "cause","pc", | |
438 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
439 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
440 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
441 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
442 | "fsr", "fir", "",/*"fp"*/ "", | |
443 | "", "", "bus", "ccfg", "", "", "", "", | |
444 | "", "", "port", "cmp", "", "", "epc", "prid", | |
445 | }; | |
446 | ||
447 | /* Names of tx39 registers. */ | |
448 | ||
449 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
450 | "sr", "lo", "hi", "bad", "cause","pc", | |
451 | "", "", "", "", "", "", "", "", | |
452 | "", "", "", "", "", "", "", "", | |
453 | "", "", "", "", "", "", "", "", | |
454 | "", "", "", "", "", "", "", "", | |
455 | "", "", "", "", | |
456 | "", "", "", "", "", "", "", "", | |
457 | "", "", "config", "cache", "debug", "depc", "epc", "" | |
458 | }; | |
459 | ||
460 | /* Names of IRIX registers. */ | |
461 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
462 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
463 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
464 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
465 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
466 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
467 | }; | |
468 | ||
cce74817 | 469 | |
5e2e9765 | 470 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 471 | static const char * |
5e2e9765 | 472 | mips_register_name (int regno) |
cce74817 | 473 | { |
691c0433 | 474 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
5e2e9765 KB |
475 | /* GPR names for all ABIs other than n32/n64. */ |
476 | static char *mips_gpr_names[] = { | |
477 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
478 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
479 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
480 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
481 | }; | |
482 | ||
483 | /* GPR names for n32 and n64 ABIs. */ | |
484 | static char *mips_n32_n64_gpr_names[] = { | |
485 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
486 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
487 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
488 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
489 | }; | |
490 | ||
491 | enum mips_abi abi = mips_abi (current_gdbarch); | |
492 | ||
a4b8ebc8 AC |
493 | /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then |
494 | don't make the raw register names visible. */ | |
495 | int rawnum = regno % NUM_REGS; | |
496 | if (regno < NUM_REGS) | |
497 | return ""; | |
498 | ||
5e2e9765 KB |
499 | /* The MIPS integer registers are always mapped from 0 to 31. The |
500 | names of the registers (which reflects the conventions regarding | |
501 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 502 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
503 | { |
504 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 505 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 506 | else |
a4b8ebc8 | 507 | return mips_gpr_names[rawnum]; |
5e2e9765 | 508 | } |
a4b8ebc8 | 509 | else if (32 <= rawnum && rawnum < NUM_REGS) |
691c0433 AC |
510 | { |
511 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
512 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
513 | } | |
5e2e9765 KB |
514 | else |
515 | internal_error (__FILE__, __LINE__, | |
a4b8ebc8 | 516 | "mips_register_name: bad register number %d", rawnum); |
cce74817 | 517 | } |
5e2e9765 | 518 | |
a4b8ebc8 | 519 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 520 | |
a4b8ebc8 AC |
521 | static int |
522 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
523 | struct reggroup *reggroup) | |
524 | { | |
525 | int vector_p; | |
526 | int float_p; | |
527 | int raw_p; | |
528 | int rawnum = regnum % NUM_REGS; | |
529 | int pseudo = regnum / NUM_REGS; | |
530 | if (reggroup == all_reggroup) | |
531 | return pseudo; | |
532 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
533 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
534 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
535 | (gdbarch), as not all architectures are multi-arch. */ | |
536 | raw_p = rawnum < NUM_REGS; | |
537 | if (REGISTER_NAME (regnum) == NULL | |
538 | || REGISTER_NAME (regnum)[0] == '\0') | |
539 | return 0; | |
540 | if (reggroup == float_reggroup) | |
541 | return float_p && pseudo; | |
542 | if (reggroup == vector_reggroup) | |
543 | return vector_p && pseudo; | |
544 | if (reggroup == general_reggroup) | |
545 | return (!vector_p && !float_p) && pseudo; | |
546 | /* Save the pseudo registers. Need to make certain that any code | |
547 | extracting register values from a saved register cache also uses | |
548 | pseudo registers. */ | |
549 | if (reggroup == save_reggroup) | |
550 | return raw_p && pseudo; | |
551 | /* Restore the same pseudo register. */ | |
552 | if (reggroup == restore_reggroup) | |
553 | return raw_p && pseudo; | |
554 | return 0; | |
555 | } | |
556 | ||
557 | /* Map the symbol table registers which live in the range [1 * | |
558 | NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw | |
47ebcfbe | 559 | registers. Take care of alignment and size problems. */ |
c5aa993b | 560 | |
a4b8ebc8 AC |
561 | static void |
562 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
563 | int cookednum, void *buf) | |
564 | { | |
47ebcfbe | 565 | int rawnum = cookednum % NUM_REGS; |
a4b8ebc8 | 566 | gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); |
47ebcfbe AC |
567 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
568 | return regcache_raw_read (regcache, rawnum, buf); | |
569 | else if (register_size (gdbarch, rawnum) > register_size (gdbarch, cookednum)) | |
570 | { | |
571 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
572 | || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
573 | regcache_raw_read_part (regcache, rawnum, 0, 4, buf); | |
574 | else | |
575 | regcache_raw_read_part (regcache, rawnum, 4, 4, buf); | |
576 | } | |
577 | else | |
578 | internal_error (__FILE__, __LINE__, "bad register size"); | |
a4b8ebc8 AC |
579 | } |
580 | ||
581 | static void | |
582 | mips_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
583 | int cookednum, const void *buf) | |
584 | { | |
47ebcfbe | 585 | int rawnum = cookednum % NUM_REGS; |
a4b8ebc8 | 586 | gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); |
47ebcfbe AC |
587 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
588 | return regcache_raw_write (regcache, rawnum, buf); | |
589 | else if (register_size (gdbarch, rawnum) > register_size (gdbarch, cookednum)) | |
590 | { | |
591 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
592 | || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
593 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); | |
594 | else | |
595 | regcache_raw_write_part (regcache, rawnum, 4, 4, buf); | |
596 | } | |
597 | else | |
598 | internal_error (__FILE__, __LINE__, "bad register size"); | |
a4b8ebc8 | 599 | } |
c5aa993b | 600 | |
c906108c | 601 | /* Table to translate MIPS16 register field to actual register number. */ |
c5aa993b JM |
602 | static int mips16_to_32_reg[8] = |
603 | {16, 17, 2, 3, 4, 5, 6, 7}; | |
c906108c SS |
604 | |
605 | /* Heuristic_proc_start may hunt through the text section for a long | |
606 | time across a 2400 baud serial line. Allows the user to limit this | |
607 | search. */ | |
608 | ||
609 | static unsigned int heuristic_fence_post = 0; | |
610 | ||
c5aa993b JM |
611 | #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ |
612 | #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */ | |
c906108c SS |
613 | #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) |
614 | #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) | |
615 | #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust) | |
616 | #define PROC_REG_MASK(proc) ((proc)->pdr.regmask) | |
617 | #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) | |
618 | #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) | |
619 | #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) | |
620 | #define PROC_PC_REG(proc) ((proc)->pdr.pcreg) | |
6c0d6680 DJ |
621 | /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long, |
622 | this will corrupt pdr.iline. Fortunately we don't use it. */ | |
c906108c SS |
623 | #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) |
624 | #define _PROC_MAGIC_ 0x0F0F0F0F | |
625 | #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_) | |
626 | #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_) | |
627 | ||
628 | struct linked_proc_info | |
c5aa993b JM |
629 | { |
630 | struct mips_extra_func_info info; | |
631 | struct linked_proc_info *next; | |
632 | } | |
633 | *linked_proc_desc_table = NULL; | |
c906108c | 634 | |
46cd78fb | 635 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
636 | register N. NOTE: This defines the pseudo register type so need to |
637 | rebuild the architecture vector. */ | |
43e526b9 JM |
638 | |
639 | static int mips64_transfers_32bit_regs_p = 0; | |
640 | ||
719ec221 AC |
641 | static void |
642 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
643 | struct cmd_list_element *c) | |
43e526b9 | 644 | { |
719ec221 AC |
645 | struct gdbarch_info info; |
646 | gdbarch_info_init (&info); | |
647 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
648 | instead of relying on globals. Doing that would let generic code | |
649 | handle the search for this specific architecture. */ | |
650 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 651 | { |
719ec221 AC |
652 | mips64_transfers_32bit_regs_p = 0; |
653 | error ("32-bit compatibility mode not supported"); | |
a4b8ebc8 | 654 | } |
a4b8ebc8 AC |
655 | } |
656 | ||
47ebcfbe | 657 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 658 | |
ff2e87ac AC |
659 | static int |
660 | mips_convert_register_p (int regnum, struct type *type) | |
661 | { | |
662 | return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
719ec221 | 663 | && register_size (current_gdbarch, regnum) == 4 |
56cea623 | 664 | && (regnum) >= mips_regnum (current_gdbarch)->fp0 && (regnum) < mips_regnum (current_gdbarch)->fp0 + 32 |
ff2e87ac AC |
665 | && TYPE_CODE(type) == TYPE_CODE_FLT |
666 | && TYPE_LENGTH(type) == 8); | |
667 | } | |
668 | ||
42c466d7 | 669 | static void |
ff2e87ac AC |
670 | mips_register_to_value (struct frame_info *frame, int regnum, |
671 | struct type *type, void *to) | |
102182a9 | 672 | { |
7f5f525d AC |
673 | get_frame_register (frame, regnum + 0, (char *) to + 4); |
674 | get_frame_register (frame, regnum + 1, (char *) to + 0); | |
102182a9 MS |
675 | } |
676 | ||
42c466d7 | 677 | static void |
ff2e87ac AC |
678 | mips_value_to_register (struct frame_info *frame, int regnum, |
679 | struct type *type, const void *from) | |
102182a9 | 680 | { |
ff2e87ac AC |
681 | put_frame_register (frame, regnum + 0, (const char *) from + 4); |
682 | put_frame_register (frame, regnum + 1, (const char *) from + 0); | |
102182a9 MS |
683 | } |
684 | ||
a4b8ebc8 AC |
685 | /* Return the GDB type object for the "standard" data type of data in |
686 | register REG. */ | |
78fde5f8 KB |
687 | |
688 | static struct type * | |
a4b8ebc8 AC |
689 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
690 | { | |
5ef80fb0 | 691 | gdb_assert (regnum >= 0 && regnum < 2 * NUM_REGS); |
56cea623 AC |
692 | if ((regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0 |
693 | && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32) | |
a6425924 | 694 | { |
5ef80fb0 AC |
695 | /* The floating-point registers raw, or cooked, always match |
696 | mips_regsize(), and also map 1:1, byte for byte. */ | |
697 | switch (gdbarch_byte_order (gdbarch)) | |
698 | { | |
699 | case BFD_ENDIAN_BIG: | |
700 | if (mips_regsize (gdbarch) == 4) | |
701 | return builtin_type_ieee_single_big; | |
702 | else | |
703 | return builtin_type_ieee_double_big; | |
704 | case BFD_ENDIAN_LITTLE: | |
705 | if (mips_regsize (gdbarch) == 4) | |
706 | return builtin_type_ieee_single_little; | |
707 | else | |
708 | return builtin_type_ieee_double_little; | |
709 | case BFD_ENDIAN_UNKNOWN: | |
710 | default: | |
711 | internal_error (__FILE__, __LINE__, "bad switch"); | |
712 | } | |
a6425924 | 713 | } |
56cea623 | 714 | else if (regnum >= (NUM_REGS + mips_regnum (current_gdbarch)->fp_control_status) |
5ef80fb0 AC |
715 | && regnum <= NUM_REGS + LAST_EMBED_REGNUM) |
716 | /* The pseudo/cooked view of the embedded registers is always | |
717 | 32-bit. The raw view is handled below. */ | |
718 | return builtin_type_int32; | |
719ec221 AC |
719 | else if (regnum >= NUM_REGS && mips_regsize (gdbarch) |
720 | && gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) | |
721 | /* The target, while using a 64-bit register buffer, is only | |
722 | transfering 32-bits of each integer register. Reflect this in | |
723 | the cooked/pseudo register value. */ | |
724 | return builtin_type_int32; | |
5ef80fb0 AC |
725 | else if (mips_regsize (gdbarch) == 8) |
726 | /* 64-bit ISA. */ | |
727 | return builtin_type_int64; | |
78fde5f8 | 728 | else |
5ef80fb0 AC |
729 | /* 32-bit ISA. */ |
730 | return builtin_type_int32; | |
78fde5f8 KB |
731 | } |
732 | ||
bcb0cc15 MS |
733 | /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */ |
734 | ||
735 | static CORE_ADDR | |
736 | mips_read_sp (void) | |
737 | { | |
e227b13c | 738 | return read_signed_register (SP_REGNUM); |
bcb0cc15 MS |
739 | } |
740 | ||
c906108c | 741 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 742 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
743 | |
744 | static int | |
745 | mips_mask_address_p (void) | |
746 | { | |
747 | switch (mask_address_var) | |
748 | { | |
7f19b9a2 | 749 | case AUTO_BOOLEAN_TRUE: |
4014092b | 750 | return 1; |
7f19b9a2 | 751 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
752 | return 0; |
753 | break; | |
7f19b9a2 | 754 | case AUTO_BOOLEAN_AUTO: |
92e1c15c | 755 | return MIPS_DEFAULT_MASK_ADDRESS_P; |
4014092b | 756 | default: |
8e65ff28 AC |
757 | internal_error (__FILE__, __LINE__, |
758 | "mips_mask_address_p: bad switch"); | |
4014092b | 759 | return -1; |
361d1df0 | 760 | } |
4014092b AC |
761 | } |
762 | ||
763 | static void | |
e9e68a56 | 764 | show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c) |
4014092b AC |
765 | { |
766 | switch (mask_address_var) | |
767 | { | |
7f19b9a2 | 768 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
769 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
770 | break; | |
7f19b9a2 | 771 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
772 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
773 | break; | |
7f19b9a2 | 774 | case AUTO_BOOLEAN_AUTO: |
4014092b AC |
775 | printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n", |
776 | mips_mask_address_p () ? "enabled" : "disabled"); | |
777 | break; | |
778 | default: | |
8e65ff28 AC |
779 | internal_error (__FILE__, __LINE__, |
780 | "show_mask_address: bad switch"); | |
4014092b | 781 | break; |
361d1df0 | 782 | } |
4014092b | 783 | } |
c906108c SS |
784 | |
785 | /* Should call_function allocate stack space for a struct return? */ | |
cb811fe7 | 786 | |
f7ab6ec6 | 787 | static int |
cb811fe7 | 788 | mips_eabi_use_struct_convention (int gcc_p, struct type *type) |
c906108c | 789 | { |
cb811fe7 MS |
790 | return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE); |
791 | } | |
792 | ||
8b389c40 MS |
793 | /* Should call_function pass struct by reference? |
794 | For each architecture, structs are passed either by | |
795 | value or by reference, depending on their size. */ | |
796 | ||
797 | static int | |
798 | mips_eabi_reg_struct_has_addr (int gcc_p, struct type *type) | |
799 | { | |
800 | enum type_code typecode = TYPE_CODE (check_typedef (type)); | |
801 | int len = TYPE_LENGTH (check_typedef (type)); | |
802 | ||
803 | if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
804 | return (len > MIPS_SAVED_REGSIZE); | |
805 | ||
806 | return 0; | |
807 | } | |
808 | ||
809 | static int | |
810 | mips_n32n64_reg_struct_has_addr (int gcc_p, struct type *type) | |
811 | { | |
812 | return 0; /* Assumption: N32/N64 never passes struct by ref. */ | |
813 | } | |
814 | ||
f7ab6ec6 | 815 | static int |
8b389c40 MS |
816 | mips_o32_reg_struct_has_addr (int gcc_p, struct type *type) |
817 | { | |
818 | return 0; /* Assumption: O32/O64 never passes struct by ref. */ | |
819 | } | |
820 | ||
c906108c SS |
821 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
822 | ||
823 | static int | |
824 | pc_is_mips16 (bfd_vma memaddr) | |
825 | { | |
826 | struct minimal_symbol *sym; | |
827 | ||
828 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
95404a3e | 829 | if (is_mips16_addr (memaddr)) |
c906108c SS |
830 | return 1; |
831 | ||
832 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
833 | the high bit of the info field. Use this to decide if the function is | |
834 | MIPS16 or normal MIPS. */ | |
835 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
836 | if (sym) | |
71b8ef93 | 837 | return msymbol_is_special (sym); |
c906108c SS |
838 | else |
839 | return 0; | |
840 | } | |
841 | ||
6c997a34 AC |
842 | /* MIPS believes that the PC has a sign extended value. Perhaphs the |
843 | all registers should be sign extended for simplicity? */ | |
844 | ||
845 | static CORE_ADDR | |
39f77062 | 846 | mips_read_pc (ptid_t ptid) |
6c997a34 | 847 | { |
39f77062 | 848 | return read_signed_register_pid (PC_REGNUM, ptid); |
6c997a34 | 849 | } |
c906108c SS |
850 | |
851 | /* This returns the PC of the first inst after the prologue. If we can't | |
852 | find the prologue, then return 0. */ | |
853 | ||
854 | static CORE_ADDR | |
acdb74a0 AC |
855 | after_prologue (CORE_ADDR pc, |
856 | mips_extra_func_info_t proc_desc) | |
c906108c SS |
857 | { |
858 | struct symtab_and_line sal; | |
859 | CORE_ADDR func_addr, func_end; | |
860 | ||
479412cd DJ |
861 | /* Pass cur_frame == 0 to find_proc_desc. We should not attempt |
862 | to read the stack pointer from the current machine state, because | |
863 | the current machine state has nothing to do with the information | |
864 | we need from the proc_desc; and the process may or may not exist | |
865 | right now. */ | |
c906108c | 866 | if (!proc_desc) |
479412cd | 867 | proc_desc = find_proc_desc (pc, NULL, 0); |
c906108c SS |
868 | |
869 | if (proc_desc) | |
870 | { | |
871 | /* If function is frameless, then we need to do it the hard way. I | |
c5aa993b | 872 | strongly suspect that frameless always means prologueless... */ |
c906108c SS |
873 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM |
874 | && PROC_FRAME_OFFSET (proc_desc) == 0) | |
875 | return 0; | |
876 | } | |
877 | ||
878 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
879 | return 0; /* Unknown */ | |
880 | ||
881 | sal = find_pc_line (func_addr, 0); | |
882 | ||
883 | if (sal.end < func_end) | |
884 | return sal.end; | |
885 | ||
886 | /* The line after the prologue is after the end of the function. In this | |
887 | case, tell the caller to find the prologue the hard way. */ | |
888 | ||
889 | return 0; | |
890 | } | |
891 | ||
892 | /* Decode a MIPS32 instruction that saves a register in the stack, and | |
893 | set the appropriate bit in the general register mask or float register mask | |
894 | to indicate which register is saved. This is a helper function | |
895 | for mips_find_saved_regs. */ | |
896 | ||
897 | static void | |
acdb74a0 AC |
898 | mips32_decode_reg_save (t_inst inst, unsigned long *gen_mask, |
899 | unsigned long *float_mask) | |
c906108c SS |
900 | { |
901 | int reg; | |
902 | ||
903 | if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */ | |
904 | || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */ | |
905 | || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */ | |
906 | { | |
907 | /* It might be possible to use the instruction to | |
c5aa993b JM |
908 | find the offset, rather than the code below which |
909 | is based on things being in a certain order in the | |
910 | frame, but figuring out what the instruction's offset | |
911 | is relative to might be a little tricky. */ | |
c906108c SS |
912 | reg = (inst & 0x001f0000) >> 16; |
913 | *gen_mask |= (1 << reg); | |
914 | } | |
915 | else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */ | |
c5aa993b JM |
916 | || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */ |
917 | || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */ | |
c906108c SS |
918 | |
919 | { | |
920 | reg = ((inst & 0x001f0000) >> 16); | |
921 | *float_mask |= (1 << reg); | |
922 | } | |
923 | } | |
924 | ||
925 | /* Decode a MIPS16 instruction that saves a register in the stack, and | |
926 | set the appropriate bit in the general register or float register mask | |
927 | to indicate which register is saved. This is a helper function | |
928 | for mips_find_saved_regs. */ | |
929 | ||
930 | static void | |
acdb74a0 | 931 | mips16_decode_reg_save (t_inst inst, unsigned long *gen_mask) |
c906108c | 932 | { |
c5aa993b | 933 | if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ |
c906108c SS |
934 | { |
935 | int reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
936 | *gen_mask |= (1 << reg); | |
937 | } | |
c5aa993b | 938 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ |
c906108c SS |
939 | { |
940 | int reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
941 | *gen_mask |= (1 << reg); | |
942 | } | |
c5aa993b | 943 | else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */ |
c906108c SS |
944 | || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ |
945 | *gen_mask |= (1 << RA_REGNUM); | |
946 | } | |
947 | ||
948 | ||
949 | /* Fetch and return instruction from the specified location. If the PC | |
950 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
951 | ||
952 | static t_inst | |
acdb74a0 | 953 | mips_fetch_instruction (CORE_ADDR addr) |
c906108c SS |
954 | { |
955 | char buf[MIPS_INSTLEN]; | |
956 | int instlen; | |
957 | int status; | |
958 | ||
959 | if (pc_is_mips16 (addr)) | |
960 | { | |
961 | instlen = MIPS16_INSTLEN; | |
95404a3e | 962 | addr = unmake_mips16_addr (addr); |
c906108c SS |
963 | } |
964 | else | |
c5aa993b | 965 | instlen = MIPS_INSTLEN; |
c906108c SS |
966 | status = read_memory_nobpt (addr, buf, instlen); |
967 | if (status) | |
968 | memory_error (status, addr); | |
969 | return extract_unsigned_integer (buf, instlen); | |
970 | } | |
971 | ||
972 | ||
973 | /* These the fields of 32 bit mips instructions */ | |
e135b889 DJ |
974 | #define mips32_op(x) (x >> 26) |
975 | #define itype_op(x) (x >> 26) | |
976 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 977 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 978 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 979 | |
e135b889 DJ |
980 | #define jtype_op(x) (x >> 26) |
981 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 982 | |
e135b889 DJ |
983 | #define rtype_op(x) (x >> 26) |
984 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
985 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
986 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
987 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
988 | #define rtype_funct(x) (x & 0x3f) | |
c906108c SS |
989 | |
990 | static CORE_ADDR | |
c5aa993b JM |
991 | mips32_relative_offset (unsigned long inst) |
992 | { | |
993 | long x; | |
994 | x = itype_immediate (inst); | |
995 | if (x & 0x8000) /* sign bit set */ | |
c906108c | 996 | { |
c5aa993b | 997 | x |= 0xffff0000; /* sign extension */ |
c906108c | 998 | } |
c5aa993b JM |
999 | x = x << 2; |
1000 | return x; | |
c906108c SS |
1001 | } |
1002 | ||
1003 | /* Determine whate to set a single step breakpoint while considering | |
1004 | branch prediction */ | |
5a89d8aa | 1005 | static CORE_ADDR |
c5aa993b JM |
1006 | mips32_next_pc (CORE_ADDR pc) |
1007 | { | |
1008 | unsigned long inst; | |
1009 | int op; | |
1010 | inst = mips_fetch_instruction (pc); | |
e135b889 | 1011 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 1012 | { |
e135b889 DJ |
1013 | if (itype_op (inst) >> 2 == 5) |
1014 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ | |
c5aa993b | 1015 | { |
e135b889 | 1016 | op = (itype_op (inst) & 0x03); |
c906108c SS |
1017 | switch (op) |
1018 | { | |
e135b889 DJ |
1019 | case 0: /* BEQL */ |
1020 | goto equal_branch; | |
1021 | case 1: /* BNEL */ | |
1022 | goto neq_branch; | |
1023 | case 2: /* BLEZL */ | |
1024 | goto less_branch; | |
1025 | case 3: /* BGTZ */ | |
1026 | goto greater_branch; | |
c5aa993b JM |
1027 | default: |
1028 | pc += 4; | |
c906108c SS |
1029 | } |
1030 | } | |
e135b889 DJ |
1031 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
1032 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ | |
1033 | { | |
1034 | int tf = itype_rt (inst) & 0x01; | |
1035 | int cnum = itype_rt (inst) >> 2; | |
56cea623 | 1036 | int fcrcs = read_signed_register (mips_regnum (current_gdbarch)->fp_control_status); |
e135b889 DJ |
1037 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); |
1038 | ||
1039 | if (((cond >> cnum) & 0x01) == tf) | |
1040 | pc += mips32_relative_offset (inst) + 4; | |
1041 | else | |
1042 | pc += 8; | |
1043 | } | |
c5aa993b JM |
1044 | else |
1045 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
1046 | } |
1047 | else | |
c5aa993b JM |
1048 | { /* This gets way messy */ |
1049 | ||
c906108c | 1050 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 1051 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 1052 | { |
c5aa993b JM |
1053 | case 0: /* SPECIAL */ |
1054 | op = rtype_funct (inst); | |
1055 | switch (op) | |
1056 | { | |
1057 | case 8: /* JR */ | |
1058 | case 9: /* JALR */ | |
6c997a34 AC |
1059 | /* Set PC to that address */ |
1060 | pc = read_signed_register (rtype_rs (inst)); | |
c5aa993b JM |
1061 | break; |
1062 | default: | |
1063 | pc += 4; | |
1064 | } | |
1065 | ||
e135b889 | 1066 | break; /* end SPECIAL */ |
c5aa993b | 1067 | case 1: /* REGIMM */ |
c906108c | 1068 | { |
e135b889 DJ |
1069 | op = itype_rt (inst); /* branch condition */ |
1070 | switch (op) | |
c906108c | 1071 | { |
c5aa993b | 1072 | case 0: /* BLTZ */ |
e135b889 DJ |
1073 | case 2: /* BLTZL */ |
1074 | case 16: /* BLTZAL */ | |
c5aa993b | 1075 | case 18: /* BLTZALL */ |
c906108c | 1076 | less_branch: |
6c997a34 | 1077 | if (read_signed_register (itype_rs (inst)) < 0) |
c5aa993b JM |
1078 | pc += mips32_relative_offset (inst) + 4; |
1079 | else | |
1080 | pc += 8; /* after the delay slot */ | |
1081 | break; | |
e135b889 | 1082 | case 1: /* BGEZ */ |
c5aa993b JM |
1083 | case 3: /* BGEZL */ |
1084 | case 17: /* BGEZAL */ | |
1085 | case 19: /* BGEZALL */ | |
c906108c | 1086 | greater_equal_branch: |
6c997a34 | 1087 | if (read_signed_register (itype_rs (inst)) >= 0) |
c5aa993b JM |
1088 | pc += mips32_relative_offset (inst) + 4; |
1089 | else | |
1090 | pc += 8; /* after the delay slot */ | |
1091 | break; | |
e135b889 | 1092 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1093 | default: |
1094 | pc += 4; | |
c906108c SS |
1095 | } |
1096 | } | |
e135b889 | 1097 | break; /* end REGIMM */ |
c5aa993b JM |
1098 | case 2: /* J */ |
1099 | case 3: /* JAL */ | |
1100 | { | |
1101 | unsigned long reg; | |
1102 | reg = jtype_target (inst) << 2; | |
e135b889 | 1103 | /* Upper four bits get never changed... */ |
c5aa993b | 1104 | pc = reg + ((pc + 4) & 0xf0000000); |
c906108c | 1105 | } |
c5aa993b JM |
1106 | break; |
1107 | /* FIXME case JALX : */ | |
1108 | { | |
1109 | unsigned long reg; | |
1110 | reg = jtype_target (inst) << 2; | |
1111 | pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */ | |
c906108c SS |
1112 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1113 | } | |
c5aa993b | 1114 | break; /* The new PC will be alternate mode */ |
e135b889 | 1115 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1116 | equal_branch: |
6c997a34 AC |
1117 | if (read_signed_register (itype_rs (inst)) == |
1118 | read_signed_register (itype_rt (inst))) | |
c5aa993b JM |
1119 | pc += mips32_relative_offset (inst) + 4; |
1120 | else | |
1121 | pc += 8; | |
1122 | break; | |
e135b889 | 1123 | case 5: /* BNE, BNEL */ |
c5aa993b | 1124 | neq_branch: |
6c997a34 | 1125 | if (read_signed_register (itype_rs (inst)) != |
e135b889 | 1126 | read_signed_register (itype_rt (inst))) |
c5aa993b JM |
1127 | pc += mips32_relative_offset (inst) + 4; |
1128 | else | |
1129 | pc += 8; | |
1130 | break; | |
e135b889 | 1131 | case 6: /* BLEZ, BLEZL */ |
c906108c | 1132 | less_zero_branch: |
6c997a34 | 1133 | if (read_signed_register (itype_rs (inst) <= 0)) |
c5aa993b JM |
1134 | pc += mips32_relative_offset (inst) + 4; |
1135 | else | |
1136 | pc += 8; | |
1137 | break; | |
1138 | case 7: | |
e135b889 DJ |
1139 | default: |
1140 | greater_branch: /* BGTZ, BGTZL */ | |
6c997a34 | 1141 | if (read_signed_register (itype_rs (inst) > 0)) |
c5aa993b JM |
1142 | pc += mips32_relative_offset (inst) + 4; |
1143 | else | |
1144 | pc += 8; | |
1145 | break; | |
c5aa993b JM |
1146 | } /* switch */ |
1147 | } /* else */ | |
1148 | return pc; | |
1149 | } /* mips32_next_pc */ | |
c906108c SS |
1150 | |
1151 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 1152 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
1153 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
1154 | We dont want to set a single step instruction on the extend instruction | |
1155 | either. | |
c5aa993b | 1156 | */ |
c906108c SS |
1157 | |
1158 | /* Lots of mips16 instruction formats */ | |
1159 | /* Predicting jumps requires itype,ritype,i8type | |
1160 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 1161 | */ |
c906108c SS |
1162 | enum mips16_inst_fmts |
1163 | { | |
c5aa993b JM |
1164 | itype, /* 0 immediate 5,10 */ |
1165 | ritype, /* 1 5,3,8 */ | |
1166 | rrtype, /* 2 5,3,3,5 */ | |
1167 | rritype, /* 3 5,3,3,5 */ | |
1168 | rrrtype, /* 4 5,3,3,3,2 */ | |
1169 | rriatype, /* 5 5,3,3,1,4 */ | |
1170 | shifttype, /* 6 5,3,3,3,2 */ | |
1171 | i8type, /* 7 5,3,8 */ | |
1172 | i8movtype, /* 8 5,3,3,5 */ | |
1173 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1174 | i64type, /* 10 5,3,8 */ | |
1175 | ri64type, /* 11 5,3,3,5 */ | |
1176 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1177 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1178 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1179 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1180 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1181 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1182 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1183 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1184 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1185 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1186 | }; | |
12f02c2a AC |
1187 | /* I am heaping all the fields of the formats into one structure and |
1188 | then, only the fields which are involved in instruction extension */ | |
c906108c | 1189 | struct upk_mips16 |
c5aa993b | 1190 | { |
12f02c2a | 1191 | CORE_ADDR offset; |
c5aa993b JM |
1192 | unsigned int regx; /* Function in i8 type */ |
1193 | unsigned int regy; | |
1194 | }; | |
c906108c SS |
1195 | |
1196 | ||
12f02c2a AC |
1197 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
1198 | for the bits which make up the immediatate extension. */ | |
c906108c | 1199 | |
12f02c2a AC |
1200 | static CORE_ADDR |
1201 | extended_offset (unsigned int extension) | |
c906108c | 1202 | { |
12f02c2a | 1203 | CORE_ADDR value; |
c5aa993b JM |
1204 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1205 | value = value << 6; | |
1206 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
1207 | value = value << 5; | |
1208 | value |= extension & 0x01f; /* extract 4:0 */ | |
1209 | return value; | |
c906108c SS |
1210 | } |
1211 | ||
1212 | /* Only call this function if you know that this is an extendable | |
1213 | instruction, It wont malfunction, but why make excess remote memory references? | |
1214 | If the immediate operands get sign extended or somthing, do it after | |
1215 | the extension is performed. | |
c5aa993b | 1216 | */ |
c906108c SS |
1217 | /* FIXME: Every one of these cases needs to worry about sign extension |
1218 | when the offset is to be used in relative addressing */ | |
1219 | ||
1220 | ||
12f02c2a | 1221 | static unsigned int |
c5aa993b | 1222 | fetch_mips_16 (CORE_ADDR pc) |
c906108c | 1223 | { |
c5aa993b JM |
1224 | char buf[8]; |
1225 | pc &= 0xfffffffe; /* clear the low order bit */ | |
1226 | target_read_memory (pc, buf, 2); | |
1227 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
1228 | } |
1229 | ||
1230 | static void | |
c5aa993b | 1231 | unpack_mips16 (CORE_ADDR pc, |
12f02c2a AC |
1232 | unsigned int extension, |
1233 | unsigned int inst, | |
1234 | enum mips16_inst_fmts insn_format, | |
c5aa993b | 1235 | struct upk_mips16 *upk) |
c906108c | 1236 | { |
12f02c2a AC |
1237 | CORE_ADDR offset; |
1238 | int regx; | |
1239 | int regy; | |
1240 | switch (insn_format) | |
c906108c | 1241 | { |
c5aa993b | 1242 | case itype: |
c906108c | 1243 | { |
12f02c2a AC |
1244 | CORE_ADDR value; |
1245 | if (extension) | |
c5aa993b JM |
1246 | { |
1247 | value = extended_offset (extension); | |
1248 | value = value << 11; /* rom for the original value */ | |
12f02c2a | 1249 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1250 | } |
1251 | else | |
c5aa993b | 1252 | { |
12f02c2a | 1253 | value = inst & 0x7ff; |
c5aa993b | 1254 | /* FIXME : Consider sign extension */ |
c906108c | 1255 | } |
12f02c2a AC |
1256 | offset = value; |
1257 | regx = -1; | |
1258 | regy = -1; | |
c906108c | 1259 | } |
c5aa993b JM |
1260 | break; |
1261 | case ritype: | |
1262 | case i8type: | |
1263 | { /* A register identifier and an offset */ | |
c906108c SS |
1264 | /* Most of the fields are the same as I type but the |
1265 | immediate value is of a different length */ | |
12f02c2a AC |
1266 | CORE_ADDR value; |
1267 | if (extension) | |
c906108c | 1268 | { |
c5aa993b JM |
1269 | value = extended_offset (extension); |
1270 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1271 | value |= inst & 0xff; /* eleven bits from instruction */ |
1272 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1273 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1274 | { | |
1275 | value &= ~0x3fff; /* remove the sign bit */ | |
1276 | value = -value; | |
c906108c SS |
1277 | } |
1278 | } | |
c5aa993b JM |
1279 | else |
1280 | { | |
12f02c2a AC |
1281 | value = inst & 0xff; /* 8 bits */ |
1282 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1283 | /* FIXME: Do sign extension , this format needs it */ |
1284 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1285 | { | |
1286 | value &= 0xef; /* remove the sign bit */ | |
1287 | value = -value; | |
1288 | } | |
c5aa993b | 1289 | } |
12f02c2a AC |
1290 | offset = value; |
1291 | regy = -1; | |
c5aa993b | 1292 | break; |
c906108c | 1293 | } |
c5aa993b | 1294 | case jalxtype: |
c906108c | 1295 | { |
c5aa993b | 1296 | unsigned long value; |
12f02c2a AC |
1297 | unsigned int nexthalf; |
1298 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b JM |
1299 | value = value << 16; |
1300 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
1301 | value |= nexthalf; | |
12f02c2a AC |
1302 | offset = value; |
1303 | regx = -1; | |
1304 | regy = -1; | |
c5aa993b | 1305 | break; |
c906108c SS |
1306 | } |
1307 | default: | |
8e65ff28 AC |
1308 | internal_error (__FILE__, __LINE__, |
1309 | "bad switch"); | |
c906108c | 1310 | } |
12f02c2a AC |
1311 | upk->offset = offset; |
1312 | upk->regx = regx; | |
1313 | upk->regy = regy; | |
c906108c SS |
1314 | } |
1315 | ||
1316 | ||
c5aa993b JM |
1317 | static CORE_ADDR |
1318 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1319 | { |
c5aa993b | 1320 | return ((offset << 2) | ((pc + 2) & (0xf0000000))); |
c906108c SS |
1321 | } |
1322 | ||
12f02c2a AC |
1323 | static CORE_ADDR |
1324 | extended_mips16_next_pc (CORE_ADDR pc, | |
1325 | unsigned int extension, | |
1326 | unsigned int insn) | |
c906108c | 1327 | { |
12f02c2a AC |
1328 | int op = (insn >> 11); |
1329 | switch (op) | |
c906108c | 1330 | { |
12f02c2a AC |
1331 | case 2: /* Branch */ |
1332 | { | |
1333 | CORE_ADDR offset; | |
1334 | struct upk_mips16 upk; | |
1335 | unpack_mips16 (pc, extension, insn, itype, &upk); | |
1336 | offset = upk.offset; | |
1337 | if (offset & 0x800) | |
1338 | { | |
1339 | offset &= 0xeff; | |
1340 | offset = -offset; | |
1341 | } | |
1342 | pc += (offset << 1) + 2; | |
1343 | break; | |
1344 | } | |
1345 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ | |
1346 | { | |
1347 | struct upk_mips16 upk; | |
1348 | unpack_mips16 (pc, extension, insn, jalxtype, &upk); | |
1349 | pc = add_offset_16 (pc, upk.offset); | |
1350 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1351 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1352 | else | |
1353 | pc |= 0x01; | |
1354 | break; | |
1355 | } | |
1356 | case 4: /* beqz */ | |
1357 | { | |
1358 | struct upk_mips16 upk; | |
1359 | int reg; | |
1360 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1361 | reg = read_signed_register (upk.regx); | |
1362 | if (reg == 0) | |
1363 | pc += (upk.offset << 1) + 2; | |
1364 | else | |
1365 | pc += 2; | |
1366 | break; | |
1367 | } | |
1368 | case 5: /* bnez */ | |
1369 | { | |
1370 | struct upk_mips16 upk; | |
1371 | int reg; | |
1372 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1373 | reg = read_signed_register (upk.regx); | |
1374 | if (reg != 0) | |
1375 | pc += (upk.offset << 1) + 2; | |
1376 | else | |
1377 | pc += 2; | |
1378 | break; | |
1379 | } | |
1380 | case 12: /* I8 Formats btez btnez */ | |
1381 | { | |
1382 | struct upk_mips16 upk; | |
1383 | int reg; | |
1384 | unpack_mips16 (pc, extension, insn, i8type, &upk); | |
1385 | /* upk.regx contains the opcode */ | |
1386 | reg = read_signed_register (24); /* Test register is 24 */ | |
1387 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ | |
1388 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1389 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1390 | pc += (upk.offset << 1) + 2; | |
1391 | else | |
1392 | pc += 2; | |
1393 | break; | |
1394 | } | |
1395 | case 29: /* RR Formats JR, JALR, JALR-RA */ | |
1396 | { | |
1397 | struct upk_mips16 upk; | |
1398 | /* upk.fmt = rrtype; */ | |
1399 | op = insn & 0x1f; | |
1400 | if (op == 0) | |
c5aa993b | 1401 | { |
12f02c2a AC |
1402 | int reg; |
1403 | upk.regx = (insn >> 8) & 0x07; | |
1404 | upk.regy = (insn >> 5) & 0x07; | |
1405 | switch (upk.regy) | |
c5aa993b | 1406 | { |
12f02c2a AC |
1407 | case 0: |
1408 | reg = upk.regx; | |
1409 | break; | |
1410 | case 1: | |
1411 | reg = 31; | |
1412 | break; /* Function return instruction */ | |
1413 | case 2: | |
1414 | reg = upk.regx; | |
1415 | break; | |
1416 | default: | |
1417 | reg = 31; | |
1418 | break; /* BOGUS Guess */ | |
c906108c | 1419 | } |
12f02c2a | 1420 | pc = read_signed_register (reg); |
c906108c | 1421 | } |
12f02c2a | 1422 | else |
c5aa993b | 1423 | pc += 2; |
12f02c2a AC |
1424 | break; |
1425 | } | |
1426 | case 30: | |
1427 | /* This is an instruction extension. Fetch the real instruction | |
1428 | (which follows the extension) and decode things based on | |
1429 | that. */ | |
1430 | { | |
1431 | pc += 2; | |
1432 | pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc)); | |
1433 | break; | |
1434 | } | |
1435 | default: | |
1436 | { | |
1437 | pc += 2; | |
1438 | break; | |
1439 | } | |
c906108c | 1440 | } |
c5aa993b | 1441 | return pc; |
12f02c2a | 1442 | } |
c906108c | 1443 | |
5a89d8aa | 1444 | static CORE_ADDR |
12f02c2a AC |
1445 | mips16_next_pc (CORE_ADDR pc) |
1446 | { | |
1447 | unsigned int insn = fetch_mips_16 (pc); | |
1448 | return extended_mips16_next_pc (pc, 0, insn); | |
1449 | } | |
1450 | ||
1451 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1452 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1453 | It works by decoding the current instruction and predicting where a |
1454 | branch will go. This isnt hard because all the data is available. | |
1455 | The MIPS32 and MIPS16 variants are quite different */ | |
c5aa993b JM |
1456 | CORE_ADDR |
1457 | mips_next_pc (CORE_ADDR pc) | |
c906108c | 1458 | { |
c5aa993b JM |
1459 | if (pc & 0x01) |
1460 | return mips16_next_pc (pc); | |
1461 | else | |
1462 | return mips32_next_pc (pc); | |
12f02c2a | 1463 | } |
c906108c | 1464 | |
e0f7ec59 AC |
1465 | /* Set up the 'saved_regs' array. This is a data structure containing |
1466 | the addresses on the stack where each register has been saved, for | |
1467 | each stack frame. Registers that have not been saved will have | |
1468 | zero here. The stack pointer register is special: rather than the | |
1469 | address where the stack register has been saved, | |
1470 | saved_regs[SP_REGNUM] will have the actual value of the previous | |
1471 | frame's stack register. */ | |
c906108c | 1472 | |
d28e01f4 | 1473 | static void |
acdb74a0 | 1474 | mips_find_saved_regs (struct frame_info *fci) |
c906108c SS |
1475 | { |
1476 | int ireg; | |
c906108c SS |
1477 | /* r0 bit means kernel trap */ |
1478 | int kernel_trap; | |
1479 | /* What registers have been saved? Bitmasks. */ | |
1480 | unsigned long gen_mask, float_mask; | |
1481 | mips_extra_func_info_t proc_desc; | |
1482 | t_inst inst; | |
e0f7ec59 | 1483 | CORE_ADDR *saved_regs; |
c906108c | 1484 | |
1b1d3794 | 1485 | if (deprecated_get_frame_saved_regs (fci) != NULL) |
e0f7ec59 AC |
1486 | return; |
1487 | saved_regs = frame_saved_regs_zalloc (fci); | |
c906108c SS |
1488 | |
1489 | /* If it is the frame for sigtramp, the saved registers are located | |
e0f7ec59 AC |
1490 | in a sigcontext structure somewhere on the stack. If the stack |
1491 | layout for sigtramp changes we might have to change these | |
1492 | constants and the companion fixup_sigtramp in mdebugread.c */ | |
c906108c | 1493 | #ifndef SIGFRAME_BASE |
e0f7ec59 AC |
1494 | /* To satisfy alignment restrictions, sigcontext is located 4 bytes |
1495 | above the sigtramp frame. */ | |
4246e332 | 1496 | #define SIGFRAME_BASE mips_regsize (current_gdbarch) |
c906108c | 1497 | /* FIXME! Are these correct?? */ |
4246e332 AC |
1498 | #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * mips_regsize (current_gdbarch)) |
1499 | #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * mips_regsize (current_gdbarch)) | |
c906108c | 1500 | #define SIGFRAME_FPREGSAVE_OFF \ |
4246e332 | 1501 | (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * mips_regsize (current_gdbarch) + 3 * mips_regsize (current_gdbarch)) |
c906108c | 1502 | #endif |
5a203e44 | 1503 | if ((get_frame_type (fci) == SIGTRAMP_FRAME)) |
c906108c SS |
1504 | { |
1505 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) | |
1506 | { | |
e0f7ec59 | 1507 | CORE_ADDR reg_position = (get_frame_base (fci) + SIGFRAME_REGSAVE_OFF |
10a08821 | 1508 | + ireg * mips_regsize (current_gdbarch)); |
e0f7ec59 | 1509 | set_reg_offset (saved_regs, ireg, reg_position); |
c906108c SS |
1510 | } |
1511 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) | |
1512 | { | |
e0f7ec59 AC |
1513 | CORE_ADDR reg_position = (get_frame_base (fci) |
1514 | + SIGFRAME_FPREGSAVE_OFF | |
10a08821 | 1515 | + ireg * mips_regsize (current_gdbarch)); |
56cea623 | 1516 | set_reg_offset (saved_regs, mips_regnum (current_gdbarch)->fp0 + ireg, reg_position); |
c906108c | 1517 | } |
e0f7ec59 AC |
1518 | |
1519 | set_reg_offset (saved_regs, PC_REGNUM, get_frame_base (fci) + SIGFRAME_PC_OFF); | |
1520 | /* SP_REGNUM, contains the value and not the address. */ | |
1521 | set_reg_offset (saved_regs, SP_REGNUM, get_frame_base (fci)); | |
c906108c SS |
1522 | return; |
1523 | } | |
1524 | ||
da50a4b7 | 1525 | proc_desc = get_frame_extra_info (fci)->proc_desc; |
c906108c | 1526 | if (proc_desc == NULL) |
e0f7ec59 AC |
1527 | /* I'm not sure how/whether this can happen. Normally when we |
1528 | can't find a proc_desc, we "synthesize" one using | |
1529 | heuristic_proc_desc and set the saved_regs right away. */ | |
c906108c SS |
1530 | return; |
1531 | ||
c5aa993b JM |
1532 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; |
1533 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc); | |
1534 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc); | |
c906108c | 1535 | |
e0f7ec59 AC |
1536 | if (/* In any frame other than the innermost or a frame interrupted |
1537 | by a signal, we assume that all registers have been saved. | |
1538 | This assumes that all register saves in a function happen | |
1539 | before the first function call. */ | |
11c02a10 AC |
1540 | (get_next_frame (fci) == NULL |
1541 | || (get_frame_type (get_next_frame (fci)) == SIGTRAMP_FRAME)) | |
c906108c | 1542 | |
e0f7ec59 | 1543 | /* In a dummy frame we know exactly where things are saved. */ |
c5aa993b | 1544 | && !PROC_DESC_IS_DUMMY (proc_desc) |
c906108c | 1545 | |
e0f7ec59 AC |
1546 | /* Don't bother unless we are inside a function prologue. |
1547 | Outside the prologue, we know where everything is. */ | |
c906108c | 1548 | |
50abf9e5 | 1549 | && in_prologue (get_frame_pc (fci), PROC_LOW_ADDR (proc_desc)) |
c906108c | 1550 | |
e0f7ec59 AC |
1551 | /* Not sure exactly what kernel_trap means, but if it means the |
1552 | kernel saves the registers without a prologue doing it, we | |
1553 | better not examine the prologue to see whether registers | |
1554 | have been saved yet. */ | |
c5aa993b | 1555 | && !kernel_trap) |
c906108c | 1556 | { |
e0f7ec59 AC |
1557 | /* We need to figure out whether the registers that the |
1558 | proc_desc claims are saved have been saved yet. */ | |
c906108c SS |
1559 | |
1560 | CORE_ADDR addr; | |
1561 | ||
1562 | /* Bitmasks; set if we have found a save for the register. */ | |
1563 | unsigned long gen_save_found = 0; | |
1564 | unsigned long float_save_found = 0; | |
1565 | int instlen; | |
1566 | ||
1567 | /* If the address is odd, assume this is MIPS16 code. */ | |
1568 | addr = PROC_LOW_ADDR (proc_desc); | |
1569 | instlen = pc_is_mips16 (addr) ? MIPS16_INSTLEN : MIPS_INSTLEN; | |
1570 | ||
e0f7ec59 AC |
1571 | /* Scan through this function's instructions preceding the |
1572 | current PC, and look for those that save registers. */ | |
50abf9e5 | 1573 | while (addr < get_frame_pc (fci)) |
c906108c SS |
1574 | { |
1575 | inst = mips_fetch_instruction (addr); | |
1576 | if (pc_is_mips16 (addr)) | |
1577 | mips16_decode_reg_save (inst, &gen_save_found); | |
1578 | else | |
1579 | mips32_decode_reg_save (inst, &gen_save_found, &float_save_found); | |
1580 | addr += instlen; | |
1581 | } | |
1582 | gen_mask = gen_save_found; | |
1583 | float_mask = float_save_found; | |
1584 | } | |
1585 | ||
e0f7ec59 AC |
1586 | /* Fill in the offsets for the registers which gen_mask says were |
1587 | saved. */ | |
1588 | { | |
1589 | CORE_ADDR reg_position = (get_frame_base (fci) | |
1590 | + PROC_REG_OFFSET (proc_desc)); | |
1591 | for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1) | |
1592 | if (gen_mask & 0x80000000) | |
1593 | { | |
1594 | set_reg_offset (saved_regs, ireg, reg_position); | |
1595 | reg_position -= MIPS_SAVED_REGSIZE; | |
1596 | } | |
1597 | } | |
c906108c | 1598 | |
e0f7ec59 AC |
1599 | /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse |
1600 | order of that normally used by gcc. Therefore, we have to fetch | |
1601 | the first instruction of the function, and if it's an entry | |
1602 | instruction that saves $s0 or $s1, correct their saved addresses. */ | |
c906108c SS |
1603 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) |
1604 | { | |
1605 | inst = mips_fetch_instruction (PROC_LOW_ADDR (proc_desc)); | |
e0f7ec59 AC |
1606 | if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) |
1607 | /* entry */ | |
c906108c SS |
1608 | { |
1609 | int reg; | |
1610 | int sreg_count = (inst >> 6) & 3; | |
c5aa993b | 1611 | |
c906108c | 1612 | /* Check if the ra register was pushed on the stack. */ |
e0f7ec59 AC |
1613 | CORE_ADDR reg_position = (get_frame_base (fci) |
1614 | + PROC_REG_OFFSET (proc_desc)); | |
c906108c | 1615 | if (inst & 0x20) |
7a292a7a | 1616 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c | 1617 | |
e0f7ec59 AC |
1618 | /* Check if the s0 and s1 registers were pushed on the |
1619 | stack. */ | |
c5aa993b | 1620 | for (reg = 16; reg < sreg_count + 16; reg++) |
c906108c | 1621 | { |
e0f7ec59 | 1622 | set_reg_offset (saved_regs, reg, reg_position); |
7a292a7a | 1623 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1624 | } |
1625 | } | |
1626 | } | |
1627 | ||
e0f7ec59 AC |
1628 | /* Fill in the offsets for the registers which float_mask says were |
1629 | saved. */ | |
1630 | { | |
1631 | CORE_ADDR reg_position = (get_frame_base (fci) | |
1632 | + PROC_FREG_OFFSET (proc_desc)); | |
6acdf5c7 | 1633 | |
e0f7ec59 AC |
1634 | /* Fill in the offsets for the float registers which float_mask |
1635 | says were saved. */ | |
1636 | for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1) | |
1637 | if (float_mask & 0x80000000) | |
1638 | { | |
c57bb9fa AC |
1639 | if (MIPS_SAVED_REGSIZE == 4 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
1640 | { | |
1641 | /* On a big endian 32 bit ABI, floating point registers | |
1642 | are paired to form doubles such that the most | |
1643 | significant part is in $f[N+1] and the least | |
1644 | significant in $f[N] vis: $f[N+1] ||| $f[N]. The | |
1645 | registers are also spilled as a pair and stored as a | |
1646 | double. | |
1647 | ||
1648 | When little-endian the least significant part is | |
1649 | stored first leading to the memory order $f[N] and | |
1650 | then $f[N+1]. | |
1651 | ||
ce2826aa | 1652 | Unfortunately, when big-endian the most significant |
c57bb9fa AC |
1653 | part of the double is stored first, and the least |
1654 | significant is stored second. This leads to the | |
1655 | registers being ordered in memory as firt $f[N+1] and | |
1656 | then $f[N]. | |
1657 | ||
1658 | For the big-endian case make certain that the | |
1659 | addresses point at the correct (swapped) locations | |
1660 | $f[N] and $f[N+1] pair (keep in mind that | |
1661 | reg_position is decremented each time through the | |
1662 | loop). */ | |
1663 | if ((ireg & 1)) | |
56cea623 | 1664 | set_reg_offset (saved_regs, mips_regnum (current_gdbarch)->fp0 + ireg, |
c57bb9fa AC |
1665 | reg_position - MIPS_SAVED_REGSIZE); |
1666 | else | |
56cea623 | 1667 | set_reg_offset (saved_regs, mips_regnum (current_gdbarch)->fp0 + ireg, |
c57bb9fa AC |
1668 | reg_position + MIPS_SAVED_REGSIZE); |
1669 | } | |
1670 | else | |
56cea623 | 1671 | set_reg_offset (saved_regs, mips_regnum (current_gdbarch)->fp0 + ireg, reg_position); |
e0f7ec59 AC |
1672 | reg_position -= MIPS_SAVED_REGSIZE; |
1673 | } | |
c906108c | 1674 | |
e0f7ec59 AC |
1675 | set_reg_offset (saved_regs, PC_REGNUM, saved_regs[RA_REGNUM]); |
1676 | } | |
d28e01f4 | 1677 | |
e0f7ec59 AC |
1678 | /* SP_REGNUM, contains the value and not the address. */ |
1679 | set_reg_offset (saved_regs, SP_REGNUM, get_frame_base (fci)); | |
d28e01f4 KB |
1680 | } |
1681 | ||
c906108c | 1682 | static CORE_ADDR |
acdb74a0 | 1683 | read_next_frame_reg (struct frame_info *fi, int regno) |
c906108c | 1684 | { |
a4b8ebc8 AC |
1685 | /* Always a pseudo. */ |
1686 | gdb_assert (regno >= NUM_REGS); | |
f796e4be | 1687 | if (fi == NULL) |
c906108c | 1688 | { |
a4b8ebc8 AC |
1689 | LONGEST val; |
1690 | regcache_cooked_read_signed (current_regcache, regno, &val); | |
1691 | return val; | |
f796e4be | 1692 | } |
a4b8ebc8 AC |
1693 | else if ((regno % NUM_REGS) == SP_REGNUM) |
1694 | /* The SP_REGNUM is special, its value is stored in saved_regs. | |
1695 | In fact, it is so special that it can even only be fetched | |
1696 | using a raw register number! Once this code as been converted | |
1697 | to frame-unwind the problem goes away. */ | |
1698 | return frame_unwind_register_signed (fi, regno % NUM_REGS); | |
f796e4be | 1699 | else |
a4b8ebc8 | 1700 | return frame_unwind_register_signed (fi, regno); |
64159455 | 1701 | |
c906108c SS |
1702 | } |
1703 | ||
1704 | /* mips_addr_bits_remove - remove useless address bits */ | |
1705 | ||
875e1767 | 1706 | static CORE_ADDR |
acdb74a0 | 1707 | mips_addr_bits_remove (CORE_ADDR addr) |
c906108c | 1708 | { |
8fa9cfa1 AC |
1709 | if (mips_mask_address_p () |
1710 | && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) | |
1711 | /* This hack is a work-around for existing boards using PMON, the | |
1712 | simulator, and any other 64-bit targets that doesn't have true | |
1713 | 64-bit addressing. On these targets, the upper 32 bits of | |
1714 | addresses are ignored by the hardware. Thus, the PC or SP are | |
1715 | likely to have been sign extended to all 1s by instruction | |
1716 | sequences that load 32-bit addresses. For example, a typical | |
1717 | piece of code that loads an address is this: | |
1718 | ||
1719 | lui $r2, <upper 16 bits> | |
1720 | ori $r2, <lower 16 bits> | |
1721 | ||
1722 | But the lui sign-extends the value such that the upper 32 bits | |
1723 | may be all 1s. The workaround is simply to mask off these | |
1724 | bits. In the future, gcc may be changed to support true 64-bit | |
1725 | addressing, and this masking will have to be disabled. */ | |
1726 | return addr &= 0xffffffffUL; | |
1727 | else | |
1728 | return addr; | |
c906108c SS |
1729 | } |
1730 | ||
9022177c DJ |
1731 | /* mips_software_single_step() is called just before we want to resume |
1732 | the inferior, if we want to single-step it but there is no hardware | |
75c9abc6 | 1733 | or kernel single-step support (MIPS on GNU/Linux for example). We find |
9022177c DJ |
1734 | the target of the coming instruction and breakpoint it. |
1735 | ||
1736 | single_step is also called just after the inferior stops. If we had | |
1737 | set up a simulated single-step, we undo our damage. */ | |
1738 | ||
1739 | void | |
1740 | mips_software_single_step (enum target_signal sig, int insert_breakpoints_p) | |
1741 | { | |
1742 | static CORE_ADDR next_pc; | |
1743 | typedef char binsn_quantum[BREAKPOINT_MAX]; | |
1744 | static binsn_quantum break_mem; | |
1745 | CORE_ADDR pc; | |
1746 | ||
1747 | if (insert_breakpoints_p) | |
1748 | { | |
1749 | pc = read_register (PC_REGNUM); | |
1750 | next_pc = mips_next_pc (pc); | |
1751 | ||
1752 | target_insert_breakpoint (next_pc, break_mem); | |
1753 | } | |
1754 | else | |
1755 | target_remove_breakpoint (next_pc, break_mem); | |
1756 | } | |
1757 | ||
97f46953 | 1758 | static CORE_ADDR |
acdb74a0 | 1759 | mips_init_frame_pc_first (int fromleaf, struct frame_info *prev) |
c906108c SS |
1760 | { |
1761 | CORE_ADDR pc, tmp; | |
1762 | ||
11c02a10 | 1763 | pc = ((fromleaf) |
6913c89a | 1764 | ? DEPRECATED_SAVED_PC_AFTER_CALL (get_next_frame (prev)) |
11c02a10 | 1765 | : get_next_frame (prev) |
8bedc050 | 1766 | ? DEPRECATED_FRAME_SAVED_PC (get_next_frame (prev)) |
11c02a10 | 1767 | : read_pc ()); |
5a89d8aa | 1768 | tmp = SKIP_TRAMPOLINE_CODE (pc); |
97f46953 | 1769 | return tmp ? tmp : pc; |
c906108c SS |
1770 | } |
1771 | ||
1772 | ||
f7ab6ec6 | 1773 | static CORE_ADDR |
acdb74a0 | 1774 | mips_frame_saved_pc (struct frame_info *frame) |
c906108c SS |
1775 | { |
1776 | CORE_ADDR saved_pc; | |
c906108c | 1777 | |
50abf9e5 | 1778 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0)) |
cedea778 AC |
1779 | { |
1780 | LONGEST tmp; | |
a4b8ebc8 AC |
1781 | /* Always unwind the cooked PC register value. */ |
1782 | frame_unwind_signed_register (frame, NUM_REGS + PC_REGNUM, &tmp); | |
cedea778 AC |
1783 | saved_pc = tmp; |
1784 | } | |
c906108c | 1785 | else |
a4b8ebc8 AC |
1786 | { |
1787 | mips_extra_func_info_t proc_desc | |
1788 | = get_frame_extra_info (frame)->proc_desc; | |
1789 | if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) | |
1790 | saved_pc = read_memory_integer (get_frame_base (frame) - MIPS_SAVED_REGSIZE, MIPS_SAVED_REGSIZE); | |
1791 | else | |
1792 | { | |
1793 | /* We have to get the saved pc from the sigcontext if it is | |
1794 | a signal handler frame. */ | |
1795 | int pcreg = (get_frame_type (frame) == SIGTRAMP_FRAME ? PC_REGNUM | |
1796 | : proc_desc ? PROC_PC_REG (proc_desc) : RA_REGNUM); | |
1797 | saved_pc = read_next_frame_reg (frame, NUM_REGS + pcreg); | |
1798 | } | |
1799 | } | |
c906108c SS |
1800 | return ADDR_BITS_REMOVE (saved_pc); |
1801 | } | |
1802 | ||
1803 | static struct mips_extra_func_info temp_proc_desc; | |
fe29b929 KB |
1804 | |
1805 | /* This hack will go away once the get_prev_frame() code has been | |
1806 | modified to set the frame's type first. That is BEFORE init extra | |
1807 | frame info et.al. is called. This is because it will become | |
1808 | possible to skip the init extra info call for sigtramp and dummy | |
1809 | frames. */ | |
1810 | static CORE_ADDR *temp_saved_regs; | |
c906108c | 1811 | |
e0f7ec59 AC |
1812 | /* Set a register's saved stack address in temp_saved_regs. If an |
1813 | address has already been set for this register, do nothing; this | |
1814 | way we will only recognize the first save of a given register in a | |
a4b8ebc8 AC |
1815 | function prologue. |
1816 | ||
1817 | For simplicity, save the address in both [0 .. NUM_REGS) and | |
1818 | [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range | |
1819 | is used as it is only second range (the ABI instead of ISA | |
1820 | registers) that comes into play when finding saved registers in a | |
1821 | frame. */ | |
c906108c SS |
1822 | |
1823 | static void | |
e0f7ec59 | 1824 | set_reg_offset (CORE_ADDR *saved_regs, int regno, CORE_ADDR offset) |
c906108c | 1825 | { |
e0f7ec59 | 1826 | if (saved_regs[regno] == 0) |
a4b8ebc8 AC |
1827 | { |
1828 | saved_regs[regno + 0 * NUM_REGS] = offset; | |
1829 | saved_regs[regno + 1 * NUM_REGS] = offset; | |
1830 | } | |
c906108c SS |
1831 | } |
1832 | ||
1833 | ||
1834 | /* Test whether the PC points to the return instruction at the | |
1835 | end of a function. */ | |
1836 | ||
c5aa993b | 1837 | static int |
acdb74a0 | 1838 | mips_about_to_return (CORE_ADDR pc) |
c906108c SS |
1839 | { |
1840 | if (pc_is_mips16 (pc)) | |
1841 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler | |
1842 | generates a "jr $ra"; other times it generates code to load | |
1843 | the return address from the stack to an accessible register (such | |
1844 | as $a3), then a "jr" using that register. This second case | |
1845 | is almost impossible to distinguish from an indirect jump | |
1846 | used for switch statements, so we don't even try. */ | |
1847 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
1848 | else | |
1849 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
1850 | } | |
1851 | ||
1852 | ||
1853 | /* This fencepost looks highly suspicious to me. Removing it also | |
1854 | seems suspicious as it could affect remote debugging across serial | |
1855 | lines. */ | |
1856 | ||
1857 | static CORE_ADDR | |
acdb74a0 | 1858 | heuristic_proc_start (CORE_ADDR pc) |
c906108c | 1859 | { |
c5aa993b JM |
1860 | CORE_ADDR start_pc; |
1861 | CORE_ADDR fence; | |
1862 | int instlen; | |
1863 | int seen_adjsp = 0; | |
c906108c | 1864 | |
c5aa993b JM |
1865 | pc = ADDR_BITS_REMOVE (pc); |
1866 | start_pc = pc; | |
1867 | fence = start_pc - heuristic_fence_post; | |
1868 | if (start_pc == 0) | |
1869 | return 0; | |
c906108c | 1870 | |
c5aa993b JM |
1871 | if (heuristic_fence_post == UINT_MAX |
1872 | || fence < VM_MIN_ADDRESS) | |
1873 | fence = VM_MIN_ADDRESS; | |
c906108c | 1874 | |
c5aa993b | 1875 | instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN; |
c906108c | 1876 | |
c5aa993b JM |
1877 | /* search back for previous return */ |
1878 | for (start_pc -= instlen;; start_pc -= instlen) | |
1879 | if (start_pc < fence) | |
1880 | { | |
1881 | /* It's not clear to me why we reach this point when | |
c0236d92 | 1882 | stop_soon, but with this test, at least we |
c5aa993b JM |
1883 | don't print out warnings for every child forked (eg, on |
1884 | decstation). 22apr93 rich@cygnus.com. */ | |
c0236d92 | 1885 | if (stop_soon == NO_STOP_QUIETLY) |
c906108c | 1886 | { |
c5aa993b JM |
1887 | static int blurb_printed = 0; |
1888 | ||
1889 | warning ("Warning: GDB can't find the start of the function at 0x%s.", | |
1890 | paddr_nz (pc)); | |
1891 | ||
1892 | if (!blurb_printed) | |
c906108c | 1893 | { |
c5aa993b JM |
1894 | /* This actually happens frequently in embedded |
1895 | development, when you first connect to a board | |
1896 | and your stack pointer and pc are nowhere in | |
1897 | particular. This message needs to give people | |
1898 | in that situation enough information to | |
1899 | determine that it's no big deal. */ | |
1900 | printf_filtered ("\n\ | |
cd0fc7c3 SS |
1901 | GDB is unable to find the start of the function at 0x%s\n\ |
1902 | and thus can't determine the size of that function's stack frame.\n\ | |
1903 | This means that GDB may be unable to access that stack frame, or\n\ | |
1904 | the frames below it.\n\ | |
1905 | This problem is most likely caused by an invalid program counter or\n\ | |
1906 | stack pointer.\n\ | |
1907 | However, if you think GDB should simply search farther back\n\ | |
1908 | from 0x%s for code which looks like the beginning of a\n\ | |
1909 | function, you can increase the range of the search using the `set\n\ | |
1910 | heuristic-fence-post' command.\n", | |
c5aa993b JM |
1911 | paddr_nz (pc), paddr_nz (pc)); |
1912 | blurb_printed = 1; | |
c906108c | 1913 | } |
c906108c SS |
1914 | } |
1915 | ||
c5aa993b JM |
1916 | return 0; |
1917 | } | |
1918 | else if (pc_is_mips16 (start_pc)) | |
1919 | { | |
1920 | unsigned short inst; | |
1921 | ||
1922 | /* On MIPS16, any one of the following is likely to be the | |
1923 | start of a function: | |
1924 | entry | |
1925 | addiu sp,-n | |
1926 | daddiu sp,-n | |
1927 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
1928 | inst = mips_fetch_instruction (start_pc); | |
1929 | if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
1930 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
1931 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
1932 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
1933 | break; | |
1934 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
1935 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1936 | seen_adjsp = 1; | |
1937 | else | |
1938 | seen_adjsp = 0; | |
1939 | } | |
1940 | else if (mips_about_to_return (start_pc)) | |
1941 | { | |
1942 | start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */ | |
1943 | break; | |
1944 | } | |
1945 | ||
c5aa993b | 1946 | return start_pc; |
c906108c SS |
1947 | } |
1948 | ||
1949 | /* Fetch the immediate value from a MIPS16 instruction. | |
1950 | If the previous instruction was an EXTEND, use it to extend | |
1951 | the upper bits of the immediate value. This is a helper function | |
1952 | for mips16_heuristic_proc_desc. */ | |
1953 | ||
1954 | static int | |
acdb74a0 AC |
1955 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ |
1956 | unsigned short inst, /* current instruction */ | |
1957 | int nbits, /* number of bits in imm field */ | |
1958 | int scale, /* scale factor to be applied to imm */ | |
1959 | int is_signed) /* is the imm field signed? */ | |
c906108c SS |
1960 | { |
1961 | int offset; | |
1962 | ||
1963 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ | |
1964 | { | |
1965 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
c5aa993b | 1966 | if (offset & 0x8000) /* check for negative extend */ |
c906108c SS |
1967 | offset = 0 - (0x10000 - (offset & 0xffff)); |
1968 | return offset | (inst & 0x1f); | |
1969 | } | |
1970 | else | |
1971 | { | |
1972 | int max_imm = 1 << nbits; | |
1973 | int mask = max_imm - 1; | |
1974 | int sign_bit = max_imm >> 1; | |
1975 | ||
1976 | offset = inst & mask; | |
1977 | if (is_signed && (offset & sign_bit)) | |
1978 | offset = 0 - (max_imm - offset); | |
1979 | return offset * scale; | |
1980 | } | |
1981 | } | |
1982 | ||
1983 | ||
1984 | /* Fill in values in temp_proc_desc based on the MIPS16 instruction | |
1985 | stream from start_pc to limit_pc. */ | |
1986 | ||
1987 | static void | |
acdb74a0 AC |
1988 | mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
1989 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
1990 | { |
1991 | CORE_ADDR cur_pc; | |
1992 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
1993 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
1994 | unsigned inst = 0; /* current instruction */ | |
1995 | unsigned entry_inst = 0; /* the entry instruction */ | |
1996 | int reg, offset; | |
1997 | ||
c5aa993b JM |
1998 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */ |
1999 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ | |
c906108c SS |
2000 | |
2001 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN) | |
2002 | { | |
2003 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
2004 | the immediate offset extension from it in mips16_get_imm. */ | |
2005 | prev_inst = inst; | |
2006 | ||
2007 | /* Fetch and decode the instruction. */ | |
2008 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
c5aa993b | 2009 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
c906108c SS |
2010 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ |
2011 | { | |
2012 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
c5aa993b JM |
2013 | if (offset < 0) /* negative stack adjustment? */ |
2014 | PROC_FRAME_OFFSET (&temp_proc_desc) -= offset; | |
c906108c SS |
2015 | else |
2016 | /* Exit loop if a positive stack adjustment is found, which | |
2017 | usually means that the stack cleanup code in the function | |
2018 | epilogue is reached. */ | |
2019 | break; | |
2020 | } | |
2021 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
2022 | { | |
2023 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2024 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
c5aa993b | 2025 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
e0f7ec59 | 2026 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c906108c SS |
2027 | } |
2028 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
2029 | { | |
2030 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
2031 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2032 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
e0f7ec59 | 2033 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c906108c SS |
2034 | } |
2035 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
2036 | { | |
2037 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
c5aa993b | 2038 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
e0f7ec59 | 2039 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
c906108c SS |
2040 | } |
2041 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
2042 | { | |
2043 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
c5aa993b | 2044 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
e0f7ec59 | 2045 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
c906108c | 2046 | } |
c5aa993b | 2047 | else if (inst == 0x673d) /* move $s1, $sp */ |
c906108c SS |
2048 | { |
2049 | frame_addr = sp; | |
2050 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
2051 | } | |
2052 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
2053 | { | |
2054 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2055 | frame_addr = sp + offset; | |
2056 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
2057 | PROC_FRAME_ADJUST (&temp_proc_desc) = offset; | |
2058 | } | |
2059 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
2060 | { | |
2061 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
2062 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2063 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2064 | set_reg_offset (temp_saved_regs, reg, frame_addr + offset); |
c906108c SS |
2065 | } |
2066 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
2067 | { | |
2068 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
2069 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2070 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2071 | set_reg_offset (temp_saved_regs, reg, frame_addr + offset); |
c906108c | 2072 | } |
c5aa993b JM |
2073 | else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
2074 | entry_inst = inst; /* save for later processing */ | |
c906108c | 2075 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
c5aa993b | 2076 | cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */ |
c906108c SS |
2077 | } |
2078 | ||
c5aa993b JM |
2079 | /* The entry instruction is typically the first instruction in a function, |
2080 | and it stores registers at offsets relative to the value of the old SP | |
2081 | (before the prologue). But the value of the sp parameter to this | |
2082 | function is the new SP (after the prologue has been executed). So we | |
2083 | can't calculate those offsets until we've seen the entire prologue, | |
2084 | and can calculate what the old SP must have been. */ | |
2085 | if (entry_inst != 0) | |
2086 | { | |
2087 | int areg_count = (entry_inst >> 8) & 7; | |
2088 | int sreg_count = (entry_inst >> 6) & 3; | |
c906108c | 2089 | |
c5aa993b JM |
2090 | /* The entry instruction always subtracts 32 from the SP. */ |
2091 | PROC_FRAME_OFFSET (&temp_proc_desc) += 32; | |
c906108c | 2092 | |
c5aa993b JM |
2093 | /* Now we can calculate what the SP must have been at the |
2094 | start of the function prologue. */ | |
2095 | sp += PROC_FRAME_OFFSET (&temp_proc_desc); | |
c906108c | 2096 | |
c5aa993b JM |
2097 | /* Check if a0-a3 were saved in the caller's argument save area. */ |
2098 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
2099 | { | |
2100 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
e0f7ec59 | 2101 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c5aa993b JM |
2102 | offset += MIPS_SAVED_REGSIZE; |
2103 | } | |
c906108c | 2104 | |
c5aa993b JM |
2105 | /* Check if the ra register was pushed on the stack. */ |
2106 | offset = -4; | |
2107 | if (entry_inst & 0x20) | |
2108 | { | |
2109 | PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM; | |
e0f7ec59 | 2110 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
c5aa993b JM |
2111 | offset -= MIPS_SAVED_REGSIZE; |
2112 | } | |
c906108c | 2113 | |
c5aa993b JM |
2114 | /* Check if the s0 and s1 registers were pushed on the stack. */ |
2115 | for (reg = 16; reg < sreg_count + 16; reg++) | |
2116 | { | |
2117 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
e0f7ec59 | 2118 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c5aa993b JM |
2119 | offset -= MIPS_SAVED_REGSIZE; |
2120 | } | |
2121 | } | |
c906108c SS |
2122 | } |
2123 | ||
2124 | static void | |
fba45db2 KB |
2125 | mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
2126 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
2127 | { |
2128 | CORE_ADDR cur_pc; | |
c5aa993b | 2129 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ |
c906108c | 2130 | restart: |
fe29b929 | 2131 | temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); |
cce74817 | 2132 | memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c5aa993b | 2133 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; |
c906108c SS |
2134 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ |
2135 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN) | |
2136 | { | |
2137 | unsigned long inst, high_word, low_word; | |
2138 | int reg; | |
2139 | ||
2140 | /* Fetch the instruction. */ | |
2141 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
2142 | ||
2143 | /* Save some code by pre-extracting some useful fields. */ | |
2144 | high_word = (inst >> 16) & 0xffff; | |
2145 | low_word = inst & 0xffff; | |
2146 | reg = high_word & 0x1f; | |
2147 | ||
c5aa993b | 2148 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
c906108c SS |
2149 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
2150 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
2151 | { | |
2152 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
c5aa993b | 2153 | PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word; |
c906108c SS |
2154 | else |
2155 | /* Exit loop if a positive stack adjustment is found, which | |
2156 | usually means that the stack cleanup code in the function | |
2157 | epilogue is reached. */ | |
2158 | break; | |
2159 | } | |
2160 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
2161 | { | |
c5aa993b | 2162 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2163 | set_reg_offset (temp_saved_regs, reg, sp + low_word); |
c906108c SS |
2164 | } |
2165 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
2166 | { | |
2167 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra, | |
2168 | but the register size used is only 32 bits. Make the address | |
2169 | for the saved register point to the lower 32 bits. */ | |
c5aa993b | 2170 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
4246e332 | 2171 | set_reg_offset (temp_saved_regs, reg, sp + low_word + 8 - mips_regsize (current_gdbarch)); |
c906108c | 2172 | } |
c5aa993b | 2173 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ |
c906108c SS |
2174 | { |
2175 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
c5aa993b JM |
2176 | if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc)) |
2177 | frame_addr = sp + low_word; | |
c906108c SS |
2178 | else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) |
2179 | { | |
2180 | unsigned alloca_adjust; | |
2181 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
a4b8ebc8 | 2182 | frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); |
c5aa993b | 2183 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
c906108c SS |
2184 | if (alloca_adjust > 0) |
2185 | { | |
2186 | /* FP > SP + frame_size. This may be because | |
2187 | * of an alloca or somethings similar. | |
2188 | * Fix sp to "pre-alloca" value, and try again. | |
2189 | */ | |
2190 | sp += alloca_adjust; | |
2191 | goto restart; | |
2192 | } | |
2193 | } | |
2194 | } | |
c5aa993b JM |
2195 | /* move $30,$sp. With different versions of gas this will be either |
2196 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
2197 | Accept any one of these. */ | |
c906108c SS |
2198 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) |
2199 | { | |
2200 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
2201 | if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) | |
2202 | { | |
2203 | unsigned alloca_adjust; | |
2204 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
a4b8ebc8 | 2205 | frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); |
c5aa993b | 2206 | alloca_adjust = (unsigned) (frame_addr - sp); |
c906108c SS |
2207 | if (alloca_adjust > 0) |
2208 | { | |
2209 | /* FP > SP + frame_size. This may be because | |
2210 | * of an alloca or somethings similar. | |
2211 | * Fix sp to "pre-alloca" value, and try again. | |
2212 | */ | |
2213 | sp += alloca_adjust; | |
2214 | goto restart; | |
2215 | } | |
2216 | } | |
2217 | } | |
c5aa993b | 2218 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ |
c906108c | 2219 | { |
c5aa993b | 2220 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2221 | set_reg_offset (temp_saved_regs, reg, frame_addr + low_word); |
c906108c SS |
2222 | } |
2223 | } | |
2224 | } | |
2225 | ||
2226 | static mips_extra_func_info_t | |
acdb74a0 | 2227 | heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
479412cd | 2228 | struct frame_info *next_frame, int cur_frame) |
c906108c | 2229 | { |
479412cd DJ |
2230 | CORE_ADDR sp; |
2231 | ||
2232 | if (cur_frame) | |
a4b8ebc8 | 2233 | sp = read_next_frame_reg (next_frame, NUM_REGS + SP_REGNUM); |
479412cd DJ |
2234 | else |
2235 | sp = 0; | |
c906108c | 2236 | |
c5aa993b JM |
2237 | if (start_pc == 0) |
2238 | return NULL; | |
2239 | memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc)); | |
fe29b929 | 2240 | temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); |
3758ac48 | 2241 | memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
2242 | PROC_LOW_ADDR (&temp_proc_desc) = start_pc; |
2243 | PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM; | |
2244 | PROC_PC_REG (&temp_proc_desc) = RA_REGNUM; | |
2245 | ||
2246 | if (start_pc + 200 < limit_pc) | |
2247 | limit_pc = start_pc + 200; | |
2248 | if (pc_is_mips16 (start_pc)) | |
2249 | mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
2250 | else | |
2251 | mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
2252 | return &temp_proc_desc; | |
2253 | } | |
2254 | ||
6c0d6680 DJ |
2255 | struct mips_objfile_private |
2256 | { | |
2257 | bfd_size_type size; | |
2258 | char *contents; | |
2259 | }; | |
2260 | ||
2261 | /* Global used to communicate between non_heuristic_proc_desc and | |
2262 | compare_pdr_entries within qsort (). */ | |
2263 | static bfd *the_bfd; | |
2264 | ||
2265 | static int | |
2266 | compare_pdr_entries (const void *a, const void *b) | |
2267 | { | |
2268 | CORE_ADDR lhs = bfd_get_32 (the_bfd, (bfd_byte *) a); | |
2269 | CORE_ADDR rhs = bfd_get_32 (the_bfd, (bfd_byte *) b); | |
2270 | ||
2271 | if (lhs < rhs) | |
2272 | return -1; | |
2273 | else if (lhs == rhs) | |
2274 | return 0; | |
2275 | else | |
2276 | return 1; | |
2277 | } | |
2278 | ||
c906108c | 2279 | static mips_extra_func_info_t |
acdb74a0 | 2280 | non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr) |
c906108c SS |
2281 | { |
2282 | CORE_ADDR startaddr; | |
2283 | mips_extra_func_info_t proc_desc; | |
c5aa993b | 2284 | struct block *b = block_for_pc (pc); |
c906108c | 2285 | struct symbol *sym; |
6c0d6680 DJ |
2286 | struct obj_section *sec; |
2287 | struct mips_objfile_private *priv; | |
2288 | ||
ae45cd16 | 2289 | if (DEPRECATED_PC_IN_CALL_DUMMY (pc, 0, 0)) |
6c0d6680 | 2290 | return NULL; |
c906108c SS |
2291 | |
2292 | find_pc_partial_function (pc, NULL, &startaddr, NULL); | |
2293 | if (addrptr) | |
2294 | *addrptr = startaddr; | |
6c0d6680 DJ |
2295 | |
2296 | priv = NULL; | |
2297 | ||
2298 | sec = find_pc_section (pc); | |
2299 | if (sec != NULL) | |
c906108c | 2300 | { |
6c0d6680 DJ |
2301 | priv = (struct mips_objfile_private *) sec->objfile->obj_private; |
2302 | ||
2303 | /* Search the ".pdr" section generated by GAS. This includes most of | |
2304 | the information normally found in ECOFF PDRs. */ | |
2305 | ||
2306 | the_bfd = sec->objfile->obfd; | |
2307 | if (priv == NULL | |
2308 | && (the_bfd->format == bfd_object | |
2309 | && bfd_get_flavour (the_bfd) == bfd_target_elf_flavour | |
2310 | && elf_elfheader (the_bfd)->e_ident[EI_CLASS] == ELFCLASS64)) | |
2311 | { | |
2312 | /* Right now GAS only outputs the address as a four-byte sequence. | |
2313 | This means that we should not bother with this method on 64-bit | |
2314 | targets (until that is fixed). */ | |
2315 | ||
2316 | priv = obstack_alloc (& sec->objfile->psymbol_obstack, | |
2317 | sizeof (struct mips_objfile_private)); | |
2318 | priv->size = 0; | |
2319 | sec->objfile->obj_private = priv; | |
2320 | } | |
2321 | else if (priv == NULL) | |
2322 | { | |
2323 | asection *bfdsec; | |
2324 | ||
2325 | priv = obstack_alloc (& sec->objfile->psymbol_obstack, | |
2326 | sizeof (struct mips_objfile_private)); | |
2327 | ||
2328 | bfdsec = bfd_get_section_by_name (sec->objfile->obfd, ".pdr"); | |
2329 | if (bfdsec != NULL) | |
2330 | { | |
2331 | priv->size = bfd_section_size (sec->objfile->obfd, bfdsec); | |
2332 | priv->contents = obstack_alloc (& sec->objfile->psymbol_obstack, | |
2333 | priv->size); | |
2334 | bfd_get_section_contents (sec->objfile->obfd, bfdsec, | |
2335 | priv->contents, 0, priv->size); | |
2336 | ||
2337 | /* In general, the .pdr section is sorted. However, in the | |
2338 | presence of multiple code sections (and other corner cases) | |
2339 | it can become unsorted. Sort it so that we can use a faster | |
2340 | binary search. */ | |
2341 | qsort (priv->contents, priv->size / 32, 32, compare_pdr_entries); | |
2342 | } | |
2343 | else | |
2344 | priv->size = 0; | |
2345 | ||
2346 | sec->objfile->obj_private = priv; | |
2347 | } | |
2348 | the_bfd = NULL; | |
2349 | ||
2350 | if (priv->size != 0) | |
2351 | { | |
2352 | int low, mid, high; | |
2353 | char *ptr; | |
2354 | ||
2355 | low = 0; | |
2356 | high = priv->size / 32; | |
2357 | ||
2358 | do | |
2359 | { | |
2360 | CORE_ADDR pdr_pc; | |
2361 | ||
2362 | mid = (low + high) / 2; | |
2363 | ||
2364 | ptr = priv->contents + mid * 32; | |
2365 | pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr); | |
2366 | pdr_pc += ANOFFSET (sec->objfile->section_offsets, | |
2367 | SECT_OFF_TEXT (sec->objfile)); | |
2368 | if (pdr_pc == startaddr) | |
2369 | break; | |
2370 | if (pdr_pc > startaddr) | |
2371 | high = mid; | |
2372 | else | |
2373 | low = mid + 1; | |
2374 | } | |
2375 | while (low != high); | |
2376 | ||
2377 | if (low != high) | |
2378 | { | |
2379 | struct symbol *sym = find_pc_function (pc); | |
2380 | ||
2381 | /* Fill in what we need of the proc_desc. */ | |
2382 | proc_desc = (mips_extra_func_info_t) | |
2383 | obstack_alloc (&sec->objfile->psymbol_obstack, | |
2384 | sizeof (struct mips_extra_func_info)); | |
2385 | PROC_LOW_ADDR (proc_desc) = startaddr; | |
2386 | ||
2387 | /* Only used for dummy frames. */ | |
2388 | PROC_HIGH_ADDR (proc_desc) = 0; | |
2389 | ||
2390 | PROC_FRAME_OFFSET (proc_desc) | |
2391 | = bfd_get_32 (sec->objfile->obfd, ptr + 20); | |
2392 | PROC_FRAME_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2393 | ptr + 24); | |
2394 | PROC_FRAME_ADJUST (proc_desc) = 0; | |
2395 | PROC_REG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2396 | ptr + 4); | |
2397 | PROC_FREG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2398 | ptr + 12); | |
2399 | PROC_REG_OFFSET (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2400 | ptr + 8); | |
2401 | PROC_FREG_OFFSET (proc_desc) | |
2402 | = bfd_get_32 (sec->objfile->obfd, ptr + 16); | |
2403 | PROC_PC_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2404 | ptr + 28); | |
2405 | proc_desc->pdr.isym = (long) sym; | |
2406 | ||
2407 | return proc_desc; | |
2408 | } | |
2409 | } | |
c906108c SS |
2410 | } |
2411 | ||
6c0d6680 DJ |
2412 | if (b == NULL) |
2413 | return NULL; | |
2414 | ||
2415 | if (startaddr > BLOCK_START (b)) | |
2416 | { | |
2417 | /* This is the "pathological" case referred to in a comment in | |
2418 | print_frame_info. It might be better to move this check into | |
2419 | symbol reading. */ | |
2420 | return NULL; | |
2421 | } | |
2422 | ||
176620f1 | 2423 | sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_DOMAIN, 0, NULL); |
6c0d6680 | 2424 | |
c906108c SS |
2425 | /* If we never found a PDR for this function in symbol reading, then |
2426 | examine prologues to find the information. */ | |
2427 | if (sym) | |
2428 | { | |
2429 | proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); | |
2430 | if (PROC_FRAME_REG (proc_desc) == -1) | |
2431 | return NULL; | |
2432 | else | |
2433 | return proc_desc; | |
2434 | } | |
2435 | else | |
2436 | return NULL; | |
2437 | } | |
2438 | ||
2439 | ||
2440 | static mips_extra_func_info_t | |
479412cd | 2441 | find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame) |
c906108c SS |
2442 | { |
2443 | mips_extra_func_info_t proc_desc; | |
4e0df2df | 2444 | CORE_ADDR startaddr = 0; |
c906108c SS |
2445 | |
2446 | proc_desc = non_heuristic_proc_desc (pc, &startaddr); | |
2447 | ||
2448 | if (proc_desc) | |
2449 | { | |
2450 | /* IF this is the topmost frame AND | |
2451 | * (this proc does not have debugging information OR | |
2452 | * the PC is in the procedure prologue) | |
2453 | * THEN create a "heuristic" proc_desc (by analyzing | |
2454 | * the actual code) to replace the "official" proc_desc. | |
2455 | */ | |
2456 | if (next_frame == NULL) | |
2457 | { | |
2458 | struct symtab_and_line val; | |
2459 | struct symbol *proc_symbol = | |
c86b5b38 | 2460 | PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc); |
c906108c SS |
2461 | |
2462 | if (proc_symbol) | |
2463 | { | |
2464 | val = find_pc_line (BLOCK_START | |
c5aa993b | 2465 | (SYMBOL_BLOCK_VALUE (proc_symbol)), |
c906108c SS |
2466 | 0); |
2467 | val.pc = val.end ? val.end : pc; | |
2468 | } | |
2469 | if (!proc_symbol || pc < val.pc) | |
2470 | { | |
2471 | mips_extra_func_info_t found_heuristic = | |
c86b5b38 MS |
2472 | heuristic_proc_desc (PROC_LOW_ADDR (proc_desc), |
2473 | pc, next_frame, cur_frame); | |
c906108c SS |
2474 | if (found_heuristic) |
2475 | proc_desc = found_heuristic; | |
2476 | } | |
2477 | } | |
2478 | } | |
2479 | else | |
2480 | { | |
2481 | /* Is linked_proc_desc_table really necessary? It only seems to be used | |
c5aa993b JM |
2482 | by procedure call dummys. However, the procedures being called ought |
2483 | to have their own proc_descs, and even if they don't, | |
2484 | heuristic_proc_desc knows how to create them! */ | |
c906108c | 2485 | |
aa1ee363 | 2486 | struct linked_proc_info *link; |
c906108c SS |
2487 | |
2488 | for (link = linked_proc_desc_table; link; link = link->next) | |
c5aa993b JM |
2489 | if (PROC_LOW_ADDR (&link->info) <= pc |
2490 | && PROC_HIGH_ADDR (&link->info) > pc) | |
c906108c SS |
2491 | return &link->info; |
2492 | ||
2493 | if (startaddr == 0) | |
2494 | startaddr = heuristic_proc_start (pc); | |
2495 | ||
2496 | proc_desc = | |
479412cd | 2497 | heuristic_proc_desc (startaddr, pc, next_frame, cur_frame); |
c906108c SS |
2498 | } |
2499 | return proc_desc; | |
2500 | } | |
2501 | ||
2502 | static CORE_ADDR | |
acdb74a0 AC |
2503 | get_frame_pointer (struct frame_info *frame, |
2504 | mips_extra_func_info_t proc_desc) | |
c906108c | 2505 | { |
a4b8ebc8 | 2506 | return (read_next_frame_reg (frame, NUM_REGS + PROC_FRAME_REG (proc_desc)) |
e227b13c AC |
2507 | + PROC_FRAME_OFFSET (proc_desc) |
2508 | - PROC_FRAME_ADJUST (proc_desc)); | |
c906108c SS |
2509 | } |
2510 | ||
5a89d8aa | 2511 | static mips_extra_func_info_t cached_proc_desc; |
c906108c | 2512 | |
f7ab6ec6 | 2513 | static CORE_ADDR |
acdb74a0 | 2514 | mips_frame_chain (struct frame_info *frame) |
c906108c SS |
2515 | { |
2516 | mips_extra_func_info_t proc_desc; | |
2517 | CORE_ADDR tmp; | |
8bedc050 | 2518 | CORE_ADDR saved_pc = DEPRECATED_FRAME_SAVED_PC (frame); |
c906108c | 2519 | |
627b3ba2 | 2520 | if (saved_pc == 0 || deprecated_inside_entry_file (saved_pc)) |
c906108c SS |
2521 | return 0; |
2522 | ||
2523 | /* Check if the PC is inside a call stub. If it is, fetch the | |
2524 | PC of the caller of that stub. */ | |
5a89d8aa | 2525 | if ((tmp = SKIP_TRAMPOLINE_CODE (saved_pc)) != 0) |
c906108c SS |
2526 | saved_pc = tmp; |
2527 | ||
ae45cd16 | 2528 | if (DEPRECATED_PC_IN_CALL_DUMMY (saved_pc, 0, 0)) |
cedea778 AC |
2529 | { |
2530 | /* A dummy frame, uses SP not FP. Get the old SP value. If all | |
2531 | is well, frame->frame the bottom of the current frame will | |
2532 | contain that value. */ | |
1e2330ba | 2533 | return get_frame_base (frame); |
cedea778 AC |
2534 | } |
2535 | ||
c906108c | 2536 | /* Look up the procedure descriptor for this PC. */ |
479412cd | 2537 | proc_desc = find_proc_desc (saved_pc, frame, 1); |
c906108c SS |
2538 | if (!proc_desc) |
2539 | return 0; | |
2540 | ||
2541 | cached_proc_desc = proc_desc; | |
2542 | ||
2543 | /* If no frame pointer and frame size is zero, we must be at end | |
2544 | of stack (or otherwise hosed). If we don't check frame size, | |
2545 | we loop forever if we see a zero size frame. */ | |
2546 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM | |
2547 | && PROC_FRAME_OFFSET (proc_desc) == 0 | |
7807aa61 MS |
2548 | /* The previous frame from a sigtramp frame might be frameless |
2549 | and have frame size zero. */ | |
5a203e44 | 2550 | && !(get_frame_type (frame) == SIGTRAMP_FRAME) |
cedea778 AC |
2551 | /* For a generic dummy frame, let get_frame_pointer() unwind a |
2552 | register value saved as part of the dummy frame call. */ | |
50abf9e5 | 2553 | && !(DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0))) |
c906108c SS |
2554 | return 0; |
2555 | else | |
2556 | return get_frame_pointer (frame, proc_desc); | |
2557 | } | |
2558 | ||
f7ab6ec6 | 2559 | static void |
acdb74a0 | 2560 | mips_init_extra_frame_info (int fromleaf, struct frame_info *fci) |
c906108c SS |
2561 | { |
2562 | int regnum; | |
f2c16bd6 KB |
2563 | mips_extra_func_info_t proc_desc; |
2564 | ||
2565 | if (get_frame_type (fci) == DUMMY_FRAME) | |
2566 | return; | |
c906108c | 2567 | |
f796e4be KB |
2568 | /* Use proc_desc calculated in frame_chain. When there is no |
2569 | next frame, i.e, get_next_frame (fci) == NULL, we call | |
2570 | find_proc_desc () to calculate it, passing an explicit | |
2571 | NULL as the frame parameter. */ | |
f2c16bd6 | 2572 | proc_desc = |
11c02a10 AC |
2573 | get_next_frame (fci) |
2574 | ? cached_proc_desc | |
f796e4be KB |
2575 | : find_proc_desc (get_frame_pc (fci), |
2576 | NULL /* i.e, get_next_frame (fci) */, | |
2577 | 1); | |
c906108c | 2578 | |
a00a19e9 | 2579 | frame_extra_info_zalloc (fci, sizeof (struct frame_extra_info)); |
cce74817 | 2580 | |
7b5849cc | 2581 | deprecated_set_frame_saved_regs_hack (fci, NULL); |
da50a4b7 | 2582 | get_frame_extra_info (fci)->proc_desc = |
c906108c SS |
2583 | proc_desc == &temp_proc_desc ? 0 : proc_desc; |
2584 | if (proc_desc) | |
2585 | { | |
2586 | /* Fixup frame-pointer - only needed for top frame */ | |
2587 | /* This may not be quite right, if proc has a real frame register. | |
c5aa993b JM |
2588 | Get the value of the frame relative sp, procedure might have been |
2589 | interrupted by a signal at it's very start. */ | |
50abf9e5 | 2590 | if (get_frame_pc (fci) == PROC_LOW_ADDR (proc_desc) |
c906108c | 2591 | && !PROC_DESC_IS_DUMMY (proc_desc)) |
a4b8ebc8 | 2592 | deprecated_update_frame_base_hack (fci, read_next_frame_reg (get_next_frame (fci), NUM_REGS + SP_REGNUM)); |
50abf9e5 | 2593 | else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fci), 0, 0)) |
cedea778 AC |
2594 | /* Do not ``fix'' fci->frame. It will have the value of the |
2595 | generic dummy frame's top-of-stack (since the draft | |
2596 | fci->frame is obtained by returning the unwound stack | |
2597 | pointer) and that is what we want. That way the fci->frame | |
2598 | value will match the top-of-stack value that was saved as | |
2599 | part of the dummy frames data. */ | |
2600 | /* Do nothing. */; | |
c906108c | 2601 | else |
11c02a10 | 2602 | deprecated_update_frame_base_hack (fci, get_frame_pointer (get_next_frame (fci), proc_desc)); |
c906108c SS |
2603 | |
2604 | if (proc_desc == &temp_proc_desc) | |
2605 | { | |
2606 | char *name; | |
2607 | ||
2608 | /* Do not set the saved registers for a sigtramp frame, | |
5a203e44 AC |
2609 | mips_find_saved_registers will do that for us. We can't |
2610 | use (get_frame_type (fci) == SIGTRAMP_FRAME), it is not | |
2611 | yet set. */ | |
2612 | /* FIXME: cagney/2002-11-18: This problem will go away once | |
2613 | frame.c:get_prev_frame() is modified to set the frame's | |
2614 | type before calling functions like this. */ | |
50abf9e5 | 2615 | find_pc_partial_function (get_frame_pc (fci), &name, |
c5aa993b | 2616 | (CORE_ADDR *) NULL, (CORE_ADDR *) NULL); |
50abf9e5 | 2617 | if (!PC_IN_SIGTRAMP (get_frame_pc (fci), name)) |
c906108c | 2618 | { |
c5aa993b | 2619 | frame_saved_regs_zalloc (fci); |
e0f7ec59 AC |
2620 | /* Set value of previous frame's stack pointer. |
2621 | Remember that saved_regs[SP_REGNUM] is special in | |
2622 | that it contains the value of the stack pointer | |
2623 | register. The other saved_regs values are addresses | |
2624 | (in the inferior) at which a given register's value | |
2625 | may be found. */ | |
2626 | set_reg_offset (temp_saved_regs, SP_REGNUM, | |
2627 | get_frame_base (fci)); | |
2628 | set_reg_offset (temp_saved_regs, PC_REGNUM, | |
2629 | temp_saved_regs[RA_REGNUM]); | |
1b1d3794 | 2630 | memcpy (deprecated_get_frame_saved_regs (fci), temp_saved_regs, |
e0f7ec59 | 2631 | SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
2632 | } |
2633 | } | |
2634 | ||
2635 | /* hack: if argument regs are saved, guess these contain args */ | |
cce74817 | 2636 | /* assume we can't tell how many args for now */ |
da50a4b7 | 2637 | get_frame_extra_info (fci)->num_args = -1; |
c906108c SS |
2638 | for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--) |
2639 | { | |
c5aa993b | 2640 | if (PROC_REG_MASK (proc_desc) & (1 << regnum)) |
c906108c | 2641 | { |
da50a4b7 | 2642 | get_frame_extra_info (fci)->num_args = regnum - A0_REGNUM + 1; |
c906108c SS |
2643 | break; |
2644 | } | |
c5aa993b | 2645 | } |
c906108c SS |
2646 | } |
2647 | } | |
2648 | ||
2649 | /* MIPS stack frames are almost impenetrable. When execution stops, | |
2650 | we basically have to look at symbol information for the function | |
2651 | that we stopped in, which tells us *which* register (if any) is | |
2652 | the base of the frame pointer, and what offset from that register | |
361d1df0 | 2653 | the frame itself is at. |
c906108c SS |
2654 | |
2655 | This presents a problem when trying to examine a stack in memory | |
2656 | (that isn't executing at the moment), using the "frame" command. We | |
2657 | don't have a PC, nor do we have any registers except SP. | |
2658 | ||
2659 | This routine takes two arguments, SP and PC, and tries to make the | |
2660 | cached frames look as if these two arguments defined a frame on the | |
2661 | cache. This allows the rest of info frame to extract the important | |
2662 | arguments without difficulty. */ | |
2663 | ||
2664 | struct frame_info * | |
acdb74a0 | 2665 | setup_arbitrary_frame (int argc, CORE_ADDR *argv) |
c906108c SS |
2666 | { |
2667 | if (argc != 2) | |
2668 | error ("MIPS frame specifications require two arguments: sp and pc"); | |
2669 | ||
2670 | return create_new_frame (argv[0], argv[1]); | |
2671 | } | |
2672 | ||
f09ded24 AC |
2673 | /* According to the current ABI, should the type be passed in a |
2674 | floating-point register (assuming that there is space)? When there | |
2675 | is no FPU, FP are not even considered as possibile candidates for | |
2676 | FP registers and, consequently this returns false - forces FP | |
2677 | arguments into integer registers. */ | |
2678 | ||
2679 | static int | |
2680 | fp_register_arg_p (enum type_code typecode, struct type *arg_type) | |
2681 | { | |
2682 | return ((typecode == TYPE_CODE_FLT | |
2683 | || (MIPS_EABI | |
2684 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
2685 | && TYPE_NFIELDS (arg_type) == 1 | |
2686 | && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT)) | |
c86b5b38 | 2687 | && MIPS_FPU_TYPE != MIPS_FPU_NONE); |
f09ded24 AC |
2688 | } |
2689 | ||
49e790b0 DJ |
2690 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
2691 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
2692 | ||
2693 | static int | |
2694 | mips_type_needs_double_align (struct type *type) | |
2695 | { | |
2696 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2697 | |
49e790b0 DJ |
2698 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2699 | return 1; | |
2700 | else if (typecode == TYPE_CODE_STRUCT) | |
2701 | { | |
2702 | if (TYPE_NFIELDS (type) < 1) | |
2703 | return 0; | |
2704 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2705 | } | |
2706 | else if (typecode == TYPE_CODE_UNION) | |
2707 | { | |
361d1df0 | 2708 | int i, n; |
49e790b0 DJ |
2709 | |
2710 | n = TYPE_NFIELDS (type); | |
2711 | for (i = 0; i < n; i++) | |
2712 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2713 | return 1; | |
2714 | return 0; | |
2715 | } | |
2716 | return 0; | |
2717 | } | |
2718 | ||
dc604539 AC |
2719 | /* Adjust the address downward (direction of stack growth) so that it |
2720 | is correctly aligned for a new stack frame. */ | |
2721 | static CORE_ADDR | |
2722 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2723 | { | |
5b03f266 | 2724 | return align_down (addr, 16); |
dc604539 AC |
2725 | } |
2726 | ||
f7ab6ec6 | 2727 | static CORE_ADDR |
25ab4790 AC |
2728 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
2729 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
2730 | struct value **args, CORE_ADDR sp, int struct_return, | |
2731 | CORE_ADDR struct_addr) | |
c906108c SS |
2732 | { |
2733 | int argreg; | |
2734 | int float_argreg; | |
2735 | int argnum; | |
2736 | int len = 0; | |
2737 | int stack_offset = 0; | |
2738 | ||
25ab4790 AC |
2739 | /* For shared libraries, "t9" needs to point at the function |
2740 | address. */ | |
2741 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
2742 | ||
2743 | /* Set the return address register to point to the entry point of | |
2744 | the program, where a breakpoint lies in wait. */ | |
2745 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
2746 | ||
c906108c | 2747 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2748 | are properly aligned. The stack has to be at least 64-bit |
2749 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2750 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2751 | aligned, so we round to this widest known alignment. */ | |
2752 | ||
5b03f266 AC |
2753 | sp = align_down (sp, 16); |
2754 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 2755 | |
46e0f506 | 2756 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2757 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2758 | passed in registers, but that's OK. */ |
c906108c | 2759 | for (argnum = 0; argnum < nargs; argnum++) |
5b03f266 | 2760 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
46e0f506 | 2761 | MIPS_STACK_ARGSIZE); |
5b03f266 | 2762 | sp -= align_up (len, 16); |
c906108c | 2763 | |
9ace0497 | 2764 | if (mips_debug) |
46e0f506 | 2765 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
2766 | "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n", |
2767 | paddr_nz (sp), (long) align_up (len, 16)); | |
9ace0497 | 2768 | |
c906108c SS |
2769 | /* Initialize the integer and float register pointers. */ |
2770 | argreg = A0_REGNUM; | |
56cea623 | 2771 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
c906108c | 2772 | |
46e0f506 | 2773 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2774 | if (struct_return) |
9ace0497 AC |
2775 | { |
2776 | if (mips_debug) | |
2777 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2778 | "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 2779 | argreg, paddr_nz (struct_addr)); |
9ace0497 AC |
2780 | write_register (argreg++, struct_addr); |
2781 | } | |
c906108c SS |
2782 | |
2783 | /* Now load as many as possible of the first arguments into | |
2784 | registers, and push the rest onto the stack. Loop thru args | |
2785 | from first to last. */ | |
2786 | for (argnum = 0; argnum < nargs; argnum++) | |
2787 | { | |
2788 | char *val; | |
d9d9c31f | 2789 | char valbuf[MAX_REGISTER_SIZE]; |
ea7c478f | 2790 | struct value *arg = args[argnum]; |
c906108c SS |
2791 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); |
2792 | int len = TYPE_LENGTH (arg_type); | |
2793 | enum type_code typecode = TYPE_CODE (arg_type); | |
2794 | ||
9ace0497 AC |
2795 | if (mips_debug) |
2796 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2797 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 2798 | argnum + 1, len, (int) typecode); |
9ace0497 | 2799 | |
c906108c | 2800 | /* The EABI passes structures that do not fit in a register by |
46e0f506 MS |
2801 | reference. */ |
2802 | if (len > MIPS_SAVED_REGSIZE | |
9ace0497 | 2803 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 2804 | { |
fbd9dcd3 | 2805 | store_unsigned_integer (valbuf, MIPS_SAVED_REGSIZE, VALUE_ADDRESS (arg)); |
c906108c | 2806 | typecode = TYPE_CODE_PTR; |
7a292a7a | 2807 | len = MIPS_SAVED_REGSIZE; |
c906108c | 2808 | val = valbuf; |
9ace0497 AC |
2809 | if (mips_debug) |
2810 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
2811 | } |
2812 | else | |
c5aa993b | 2813 | val = (char *) VALUE_CONTENTS (arg); |
c906108c SS |
2814 | |
2815 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
2816 | even-numbered floating point register. Round the FP register |
2817 | up before the check to see if there are any FP registers | |
46e0f506 MS |
2818 | left. Non MIPS_EABI targets also pass the FP in the integer |
2819 | registers so also round up normal registers. */ | |
acdb74a0 AC |
2820 | if (!FP_REGISTER_DOUBLE |
2821 | && fp_register_arg_p (typecode, arg_type)) | |
2822 | { | |
2823 | if ((float_argreg & 1)) | |
2824 | float_argreg++; | |
2825 | } | |
c906108c SS |
2826 | |
2827 | /* Floating point arguments passed in registers have to be | |
2828 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2829 | are passed in register pairs; the even register gets |
2830 | the low word, and the odd register gets the high word. | |
2831 | On non-EABI processors, the first two floating point arguments are | |
2832 | also copied to general registers, because MIPS16 functions | |
2833 | don't use float registers for arguments. This duplication of | |
2834 | arguments in general registers can't hurt non-MIPS16 functions | |
2835 | because those registers are normally skipped. */ | |
1012bd0e EZ |
2836 | /* MIPS_EABI squeezes a struct that contains a single floating |
2837 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 2838 | stack. */ |
f09ded24 AC |
2839 | if (fp_register_arg_p (typecode, arg_type) |
2840 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
c906108c SS |
2841 | { |
2842 | if (!FP_REGISTER_DOUBLE && len == 8) | |
2843 | { | |
d7449b42 | 2844 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
c906108c SS |
2845 | unsigned long regval; |
2846 | ||
2847 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 2848 | regval = extract_unsigned_integer (val + low_offset, 4); |
9ace0497 | 2849 | if (mips_debug) |
acdb74a0 | 2850 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2851 | float_argreg, phex (regval, 4)); |
c906108c | 2852 | write_register (float_argreg++, regval); |
c906108c SS |
2853 | |
2854 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 2855 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
9ace0497 | 2856 | if (mips_debug) |
acdb74a0 | 2857 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2858 | float_argreg, phex (regval, 4)); |
c906108c | 2859 | write_register (float_argreg++, regval); |
c906108c SS |
2860 | } |
2861 | else | |
2862 | { | |
2863 | /* This is a floating point value that fits entirely | |
2864 | in a single register. */ | |
53a5351d | 2865 | /* On 32 bit ABI's the float_argreg is further adjusted |
46e0f506 | 2866 | above to ensure that it is even register aligned. */ |
9ace0497 AC |
2867 | LONGEST regval = extract_unsigned_integer (val, len); |
2868 | if (mips_debug) | |
acdb74a0 | 2869 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2870 | float_argreg, phex (regval, len)); |
c906108c | 2871 | write_register (float_argreg++, regval); |
c906108c SS |
2872 | } |
2873 | } | |
2874 | else | |
2875 | { | |
2876 | /* Copy the argument to general registers or the stack in | |
2877 | register-sized pieces. Large arguments are split between | |
2878 | registers and stack. */ | |
4246e332 AC |
2879 | /* Note: structs whose size is not a multiple of |
2880 | mips_regsize() are treated specially: Irix cc passes them | |
2881 | in registers where gcc sometimes puts them on the stack. | |
2882 | For maximum compatibility, we will put them in both | |
2883 | places. */ | |
c5aa993b | 2884 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && |
7a292a7a | 2885 | (len % MIPS_SAVED_REGSIZE != 0)); |
46e0f506 | 2886 | |
f09ded24 | 2887 | /* Note: Floating-point values that didn't fit into an FP |
46e0f506 | 2888 | register are only written to memory. */ |
c906108c SS |
2889 | while (len > 0) |
2890 | { | |
ebafbe83 | 2891 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 2892 | int stack_used_p = 0; |
46e0f506 MS |
2893 | int partial_len = |
2894 | len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE; | |
c906108c | 2895 | |
acdb74a0 AC |
2896 | if (mips_debug) |
2897 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2898 | partial_len); | |
2899 | ||
566f0f7a | 2900 | /* Write this portion of the argument to the stack. */ |
f09ded24 AC |
2901 | if (argreg > MIPS_LAST_ARG_REGNUM |
2902 | || odd_sized_struct | |
2903 | || fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2904 | { |
c906108c SS |
2905 | /* Should shorter than int integer values be |
2906 | promoted to int before being stored? */ | |
c906108c | 2907 | int longword_offset = 0; |
9ace0497 | 2908 | CORE_ADDR addr; |
566f0f7a | 2909 | stack_used_p = 1; |
d7449b42 | 2910 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
7a292a7a | 2911 | { |
d929b26f | 2912 | if (MIPS_STACK_ARGSIZE == 8 && |
7a292a7a SS |
2913 | (typecode == TYPE_CODE_INT || |
2914 | typecode == TYPE_CODE_PTR || | |
2915 | typecode == TYPE_CODE_FLT) && len <= 4) | |
d929b26f | 2916 | longword_offset = MIPS_STACK_ARGSIZE - len; |
7a292a7a SS |
2917 | else if ((typecode == TYPE_CODE_STRUCT || |
2918 | typecode == TYPE_CODE_UNION) && | |
d929b26f AC |
2919 | TYPE_LENGTH (arg_type) < MIPS_STACK_ARGSIZE) |
2920 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
7a292a7a | 2921 | } |
c5aa993b | 2922 | |
9ace0497 AC |
2923 | if (mips_debug) |
2924 | { | |
cb3d25d1 MS |
2925 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", |
2926 | paddr_nz (stack_offset)); | |
2927 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
2928 | paddr_nz (longword_offset)); | |
9ace0497 | 2929 | } |
361d1df0 | 2930 | |
9ace0497 AC |
2931 | addr = sp + stack_offset + longword_offset; |
2932 | ||
2933 | if (mips_debug) | |
2934 | { | |
2935 | int i; | |
cb3d25d1 MS |
2936 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
2937 | paddr_nz (addr)); | |
9ace0497 AC |
2938 | for (i = 0; i < partial_len; i++) |
2939 | { | |
cb3d25d1 MS |
2940 | fprintf_unfiltered (gdb_stdlog, "%02x", |
2941 | val[i] & 0xff); | |
9ace0497 AC |
2942 | } |
2943 | } | |
2944 | write_memory (addr, val, partial_len); | |
c906108c SS |
2945 | } |
2946 | ||
f09ded24 AC |
2947 | /* Note!!! This is NOT an else clause. Odd sized |
2948 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 2949 | arguments will not. */ |
566f0f7a | 2950 | /* Write this portion of the argument to a general |
46e0f506 | 2951 | purpose register. */ |
f09ded24 AC |
2952 | if (argreg <= MIPS_LAST_ARG_REGNUM |
2953 | && !fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2954 | { |
9ace0497 | 2955 | LONGEST regval = extract_unsigned_integer (val, partial_len); |
c906108c | 2956 | |
9ace0497 | 2957 | if (mips_debug) |
acdb74a0 | 2958 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 AC |
2959 | argreg, |
2960 | phex (regval, MIPS_SAVED_REGSIZE)); | |
c906108c SS |
2961 | write_register (argreg, regval); |
2962 | argreg++; | |
c906108c | 2963 | } |
c5aa993b | 2964 | |
c906108c SS |
2965 | len -= partial_len; |
2966 | val += partial_len; | |
2967 | ||
566f0f7a AC |
2968 | /* Compute the the offset into the stack at which we |
2969 | will copy the next parameter. | |
2970 | ||
566f0f7a | 2971 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 2972 | only needs to be adjusted when it has been used. */ |
c906108c | 2973 | |
46e0f506 | 2974 | if (stack_used_p) |
5b03f266 | 2975 | stack_offset += align_up (partial_len, MIPS_STACK_ARGSIZE); |
c906108c SS |
2976 | } |
2977 | } | |
9ace0497 AC |
2978 | if (mips_debug) |
2979 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
2980 | } |
2981 | ||
310e9b6a AC |
2982 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
2983 | ||
0f71a2f6 JM |
2984 | /* Return adjusted stack pointer. */ |
2985 | return sp; | |
2986 | } | |
2987 | ||
25ab4790 | 2988 | /* N32/N64 version of push_dummy_call. */ |
ebafbe83 | 2989 | |
f7ab6ec6 | 2990 | static CORE_ADDR |
25ab4790 AC |
2991 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
2992 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
2993 | struct value **args, CORE_ADDR sp, int struct_return, | |
2994 | CORE_ADDR struct_addr) | |
cb3d25d1 MS |
2995 | { |
2996 | int argreg; | |
2997 | int float_argreg; | |
2998 | int argnum; | |
2999 | int len = 0; | |
3000 | int stack_offset = 0; | |
3001 | ||
25ab4790 AC |
3002 | /* For shared libraries, "t9" needs to point at the function |
3003 | address. */ | |
3004 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3005 | ||
3006 | /* Set the return address register to point to the entry point of | |
3007 | the program, where a breakpoint lies in wait. */ | |
3008 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3009 | ||
cb3d25d1 MS |
3010 | /* First ensure that the stack and structure return address (if any) |
3011 | are properly aligned. The stack has to be at least 64-bit | |
3012 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3013 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3014 | aligned, so we round to this widest known alignment. */ | |
3015 | ||
5b03f266 AC |
3016 | sp = align_down (sp, 16); |
3017 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
3018 | |
3019 | /* Now make space on the stack for the args. */ | |
3020 | for (argnum = 0; argnum < nargs; argnum++) | |
5b03f266 | 3021 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
cb3d25d1 | 3022 | MIPS_STACK_ARGSIZE); |
5b03f266 | 3023 | sp -= align_up (len, 16); |
cb3d25d1 MS |
3024 | |
3025 | if (mips_debug) | |
3026 | fprintf_unfiltered (gdb_stdlog, | |
5b03f266 AC |
3027 | "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n", |
3028 | paddr_nz (sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
3029 | |
3030 | /* Initialize the integer and float register pointers. */ | |
3031 | argreg = A0_REGNUM; | |
56cea623 | 3032 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
cb3d25d1 | 3033 | |
46e0f506 | 3034 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
3035 | if (struct_return) |
3036 | { | |
3037 | if (mips_debug) | |
3038 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3039 | "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 MS |
3040 | argreg, paddr_nz (struct_addr)); |
3041 | write_register (argreg++, struct_addr); | |
3042 | } | |
3043 | ||
3044 | /* Now load as many as possible of the first arguments into | |
3045 | registers, and push the rest onto the stack. Loop thru args | |
3046 | from first to last. */ | |
3047 | for (argnum = 0; argnum < nargs; argnum++) | |
3048 | { | |
3049 | char *val; | |
d9d9c31f | 3050 | char valbuf[MAX_REGISTER_SIZE]; |
cb3d25d1 MS |
3051 | struct value *arg = args[argnum]; |
3052 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3053 | int len = TYPE_LENGTH (arg_type); | |
3054 | enum type_code typecode = TYPE_CODE (arg_type); | |
3055 | ||
3056 | if (mips_debug) | |
3057 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3058 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
3059 | argnum + 1, len, (int) typecode); |
3060 | ||
3061 | val = (char *) VALUE_CONTENTS (arg); | |
3062 | ||
3063 | if (fp_register_arg_p (typecode, arg_type) | |
3064 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3065 | { | |
3066 | /* This is a floating point value that fits entirely | |
3067 | in a single register. */ | |
3068 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3069 | above to ensure that it is even register aligned. */ | |
3070 | LONGEST regval = extract_unsigned_integer (val, len); | |
3071 | if (mips_debug) | |
3072 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3073 | float_argreg, phex (regval, len)); | |
3074 | write_register (float_argreg++, regval); | |
3075 | ||
3076 | if (mips_debug) | |
3077 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3078 | argreg, phex (regval, len)); | |
3079 | write_register (argreg, regval); | |
3080 | argreg += 1; | |
3081 | } | |
3082 | else | |
3083 | { | |
3084 | /* Copy the argument to general registers or the stack in | |
3085 | register-sized pieces. Large arguments are split between | |
3086 | registers and stack. */ | |
4246e332 AC |
3087 | /* Note: structs whose size is not a multiple of |
3088 | mips_regsize() are treated specially: Irix cc passes them | |
3089 | in registers where gcc sometimes puts them on the stack. | |
3090 | For maximum compatibility, we will put them in both | |
3091 | places. */ | |
cb3d25d1 MS |
3092 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && |
3093 | (len % MIPS_SAVED_REGSIZE != 0)); | |
3094 | /* Note: Floating-point values that didn't fit into an FP | |
3095 | register are only written to memory. */ | |
3096 | while (len > 0) | |
3097 | { | |
3098 | /* Rememer if the argument was written to the stack. */ | |
3099 | int stack_used_p = 0; | |
3100 | int partial_len = len < MIPS_SAVED_REGSIZE ? | |
3101 | len : MIPS_SAVED_REGSIZE; | |
3102 | ||
3103 | if (mips_debug) | |
3104 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3105 | partial_len); | |
3106 | ||
3107 | /* Write this portion of the argument to the stack. */ | |
3108 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3109 | || odd_sized_struct | |
3110 | || fp_register_arg_p (typecode, arg_type)) | |
3111 | { | |
3112 | /* Should shorter than int integer values be | |
3113 | promoted to int before being stored? */ | |
3114 | int longword_offset = 0; | |
3115 | CORE_ADDR addr; | |
3116 | stack_used_p = 1; | |
3117 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3118 | { | |
3119 | if (MIPS_STACK_ARGSIZE == 8 && | |
3120 | (typecode == TYPE_CODE_INT || | |
3121 | typecode == TYPE_CODE_PTR || | |
3122 | typecode == TYPE_CODE_FLT) && len <= 4) | |
3123 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
cb3d25d1 MS |
3124 | } |
3125 | ||
3126 | if (mips_debug) | |
3127 | { | |
3128 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3129 | paddr_nz (stack_offset)); | |
3130 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3131 | paddr_nz (longword_offset)); | |
3132 | } | |
3133 | ||
3134 | addr = sp + stack_offset + longword_offset; | |
3135 | ||
3136 | if (mips_debug) | |
3137 | { | |
3138 | int i; | |
3139 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", | |
3140 | paddr_nz (addr)); | |
3141 | for (i = 0; i < partial_len; i++) | |
3142 | { | |
3143 | fprintf_unfiltered (gdb_stdlog, "%02x", | |
3144 | val[i] & 0xff); | |
3145 | } | |
3146 | } | |
3147 | write_memory (addr, val, partial_len); | |
3148 | } | |
3149 | ||
3150 | /* Note!!! This is NOT an else clause. Odd sized | |
3151 | structs may go thru BOTH paths. Floating point | |
3152 | arguments will not. */ | |
3153 | /* Write this portion of the argument to a general | |
3154 | purpose register. */ | |
3155 | if (argreg <= MIPS_LAST_ARG_REGNUM | |
3156 | && !fp_register_arg_p (typecode, arg_type)) | |
3157 | { | |
3158 | LONGEST regval = extract_unsigned_integer (val, partial_len); | |
3159 | ||
3160 | /* A non-floating-point argument being passed in a | |
3161 | general register. If a struct or union, and if | |
3162 | the remaining length is smaller than the register | |
3163 | size, we have to adjust the register value on | |
3164 | big endian targets. | |
3165 | ||
3166 | It does not seem to be necessary to do the | |
3167 | same for integral types. | |
3168 | ||
3169 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3170 | outputting LE O32 with sizeof (struct) < | |
3171 | MIPS_SAVED_REGSIZE, generates a left shift as | |
3172 | part of storing the argument in a register a | |
3173 | register (the left shift isn't generated when | |
3174 | sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it | |
3175 | is quite possible that this is GCC contradicting | |
3176 | the LE/O32 ABI, GDB has not been adjusted to | |
3177 | accommodate this. Either someone needs to | |
3178 | demonstrate that the LE/O32 ABI specifies such a | |
3179 | left shift OR this new ABI gets identified as | |
3180 | such and GDB gets tweaked accordingly. */ | |
3181 | ||
3182 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3183 | && partial_len < MIPS_SAVED_REGSIZE | |
3184 | && (typecode == TYPE_CODE_STRUCT || | |
3185 | typecode == TYPE_CODE_UNION)) | |
3186 | regval <<= ((MIPS_SAVED_REGSIZE - partial_len) * | |
3187 | TARGET_CHAR_BIT); | |
3188 | ||
3189 | if (mips_debug) | |
3190 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3191 | argreg, | |
3192 | phex (regval, MIPS_SAVED_REGSIZE)); | |
3193 | write_register (argreg, regval); | |
3194 | argreg++; | |
3195 | } | |
3196 | ||
3197 | len -= partial_len; | |
3198 | val += partial_len; | |
3199 | ||
3200 | /* Compute the the offset into the stack at which we | |
3201 | will copy the next parameter. | |
3202 | ||
3203 | In N32 (N64?), the stack_offset only needs to be | |
3204 | adjusted when it has been used. */ | |
3205 | ||
3206 | if (stack_used_p) | |
5b03f266 | 3207 | stack_offset += align_up (partial_len, MIPS_STACK_ARGSIZE); |
cb3d25d1 MS |
3208 | } |
3209 | } | |
3210 | if (mips_debug) | |
3211 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3212 | } | |
3213 | ||
310e9b6a AC |
3214 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
3215 | ||
cb3d25d1 MS |
3216 | /* Return adjusted stack pointer. */ |
3217 | return sp; | |
3218 | } | |
3219 | ||
25ab4790 | 3220 | /* O32 version of push_dummy_call. */ |
ebafbe83 | 3221 | |
46cac009 | 3222 | static CORE_ADDR |
25ab4790 AC |
3223 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
3224 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
3225 | struct value **args, CORE_ADDR sp, int struct_return, | |
3226 | CORE_ADDR struct_addr) | |
ebafbe83 MS |
3227 | { |
3228 | int argreg; | |
3229 | int float_argreg; | |
3230 | int argnum; | |
3231 | int len = 0; | |
3232 | int stack_offset = 0; | |
ebafbe83 | 3233 | |
25ab4790 AC |
3234 | /* For shared libraries, "t9" needs to point at the function |
3235 | address. */ | |
3236 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3237 | ||
3238 | /* Set the return address register to point to the entry point of | |
3239 | the program, where a breakpoint lies in wait. */ | |
3240 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3241 | ||
ebafbe83 MS |
3242 | /* First ensure that the stack and structure return address (if any) |
3243 | are properly aligned. The stack has to be at least 64-bit | |
3244 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3245 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3246 | aligned, so we round to this widest known alignment. */ | |
3247 | ||
5b03f266 AC |
3248 | sp = align_down (sp, 16); |
3249 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
3250 | |
3251 | /* Now make space on the stack for the args. */ | |
3252 | for (argnum = 0; argnum < nargs; argnum++) | |
5b03f266 | 3253 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
ebafbe83 | 3254 | MIPS_STACK_ARGSIZE); |
5b03f266 | 3255 | sp -= align_up (len, 16); |
ebafbe83 MS |
3256 | |
3257 | if (mips_debug) | |
3258 | fprintf_unfiltered (gdb_stdlog, | |
5b03f266 AC |
3259 | "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n", |
3260 | paddr_nz (sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
3261 | |
3262 | /* Initialize the integer and float register pointers. */ | |
3263 | argreg = A0_REGNUM; | |
56cea623 | 3264 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
ebafbe83 | 3265 | |
bcb0cc15 | 3266 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3267 | if (struct_return) |
3268 | { | |
3269 | if (mips_debug) | |
3270 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3271 | "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n", |
ebafbe83 MS |
3272 | argreg, paddr_nz (struct_addr)); |
3273 | write_register (argreg++, struct_addr); | |
3274 | stack_offset += MIPS_STACK_ARGSIZE; | |
3275 | } | |
3276 | ||
3277 | /* Now load as many as possible of the first arguments into | |
3278 | registers, and push the rest onto the stack. Loop thru args | |
3279 | from first to last. */ | |
3280 | for (argnum = 0; argnum < nargs; argnum++) | |
3281 | { | |
3282 | char *val; | |
d9d9c31f | 3283 | char valbuf[MAX_REGISTER_SIZE]; |
ebafbe83 MS |
3284 | struct value *arg = args[argnum]; |
3285 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3286 | int len = TYPE_LENGTH (arg_type); | |
3287 | enum type_code typecode = TYPE_CODE (arg_type); | |
3288 | ||
3289 | if (mips_debug) | |
3290 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3291 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3292 | argnum + 1, len, (int) typecode); |
3293 | ||
3294 | val = (char *) VALUE_CONTENTS (arg); | |
3295 | ||
3296 | /* 32-bit ABIs always start floating point arguments in an | |
3297 | even-numbered floating point register. Round the FP register | |
3298 | up before the check to see if there are any FP registers | |
3299 | left. O32/O64 targets also pass the FP in the integer | |
3300 | registers so also round up normal registers. */ | |
3301 | if (!FP_REGISTER_DOUBLE | |
3302 | && fp_register_arg_p (typecode, arg_type)) | |
3303 | { | |
3304 | if ((float_argreg & 1)) | |
3305 | float_argreg++; | |
3306 | } | |
3307 | ||
3308 | /* Floating point arguments passed in registers have to be | |
3309 | treated specially. On 32-bit architectures, doubles | |
3310 | are passed in register pairs; the even register gets | |
3311 | the low word, and the odd register gets the high word. | |
3312 | On O32/O64, the first two floating point arguments are | |
3313 | also copied to general registers, because MIPS16 functions | |
3314 | don't use float registers for arguments. This duplication of | |
3315 | arguments in general registers can't hurt non-MIPS16 functions | |
3316 | because those registers are normally skipped. */ | |
3317 | ||
3318 | if (fp_register_arg_p (typecode, arg_type) | |
3319 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3320 | { | |
3321 | if (!FP_REGISTER_DOUBLE && len == 8) | |
3322 | { | |
3323 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
3324 | unsigned long regval; | |
3325 | ||
3326 | /* Write the low word of the double to the even register(s). */ | |
3327 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3328 | if (mips_debug) | |
3329 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3330 | float_argreg, phex (regval, 4)); | |
3331 | write_register (float_argreg++, regval); | |
3332 | if (mips_debug) | |
3333 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3334 | argreg, phex (regval, 4)); | |
3335 | write_register (argreg++, regval); | |
3336 | ||
3337 | /* Write the high word of the double to the odd register(s). */ | |
3338 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3339 | if (mips_debug) | |
3340 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3341 | float_argreg, phex (regval, 4)); | |
3342 | write_register (float_argreg++, regval); | |
3343 | ||
3344 | if (mips_debug) | |
3345 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3346 | argreg, phex (regval, 4)); | |
3347 | write_register (argreg++, regval); | |
3348 | } | |
3349 | else | |
3350 | { | |
3351 | /* This is a floating point value that fits entirely | |
3352 | in a single register. */ | |
3353 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3354 | above to ensure that it is even register aligned. */ | |
3355 | LONGEST regval = extract_unsigned_integer (val, len); | |
3356 | if (mips_debug) | |
3357 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3358 | float_argreg, phex (regval, len)); | |
3359 | write_register (float_argreg++, regval); | |
3360 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
3361 | registers for each argument. The below is (my | |
3362 | guess) to ensure that the corresponding integer | |
3363 | register has reserved the same space. */ | |
3364 | if (mips_debug) | |
3365 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3366 | argreg, phex (regval, len)); | |
3367 | write_register (argreg, regval); | |
3368 | argreg += FP_REGISTER_DOUBLE ? 1 : 2; | |
3369 | } | |
3370 | /* Reserve space for the FP register. */ | |
5b03f266 | 3371 | stack_offset += align_up (len, MIPS_STACK_ARGSIZE); |
46cac009 AC |
3372 | } |
3373 | else | |
3374 | { | |
3375 | /* Copy the argument to general registers or the stack in | |
3376 | register-sized pieces. Large arguments are split between | |
3377 | registers and stack. */ | |
4246e332 AC |
3378 | /* Note: structs whose size is not a multiple of |
3379 | mips_regsize() are treated specially: Irix cc passes them | |
3380 | in registers where gcc sometimes puts them on the stack. | |
3381 | For maximum compatibility, we will put them in both | |
3382 | places. */ | |
46cac009 AC |
3383 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && |
3384 | (len % MIPS_SAVED_REGSIZE != 0)); | |
3385 | /* Structures should be aligned to eight bytes (even arg registers) | |
3386 | on MIPS_ABI_O32, if their first member has double precision. */ | |
3387 | if (MIPS_SAVED_REGSIZE < 8 | |
3388 | && mips_type_needs_double_align (arg_type)) | |
3389 | { | |
3390 | if ((argreg & 1)) | |
3391 | argreg++; | |
3392 | } | |
3393 | /* Note: Floating-point values that didn't fit into an FP | |
3394 | register are only written to memory. */ | |
3395 | while (len > 0) | |
3396 | { | |
3397 | /* Remember if the argument was written to the stack. */ | |
3398 | int stack_used_p = 0; | |
3399 | int partial_len = | |
3400 | len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE; | |
3401 | ||
3402 | if (mips_debug) | |
3403 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3404 | partial_len); | |
3405 | ||
3406 | /* Write this portion of the argument to the stack. */ | |
3407 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3408 | || odd_sized_struct | |
3409 | || fp_register_arg_p (typecode, arg_type)) | |
3410 | { | |
3411 | /* Should shorter than int integer values be | |
3412 | promoted to int before being stored? */ | |
3413 | int longword_offset = 0; | |
3414 | CORE_ADDR addr; | |
3415 | stack_used_p = 1; | |
3416 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3417 | { | |
3418 | if (MIPS_STACK_ARGSIZE == 8 && | |
3419 | (typecode == TYPE_CODE_INT || | |
3420 | typecode == TYPE_CODE_PTR || | |
3421 | typecode == TYPE_CODE_FLT) && len <= 4) | |
3422 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
3423 | } | |
3424 | ||
3425 | if (mips_debug) | |
3426 | { | |
3427 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3428 | paddr_nz (stack_offset)); | |
3429 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3430 | paddr_nz (longword_offset)); | |
3431 | } | |
3432 | ||
3433 | addr = sp + stack_offset + longword_offset; | |
3434 | ||
3435 | if (mips_debug) | |
3436 | { | |
3437 | int i; | |
3438 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", | |
3439 | paddr_nz (addr)); | |
3440 | for (i = 0; i < partial_len; i++) | |
3441 | { | |
3442 | fprintf_unfiltered (gdb_stdlog, "%02x", | |
3443 | val[i] & 0xff); | |
3444 | } | |
3445 | } | |
3446 | write_memory (addr, val, partial_len); | |
3447 | } | |
3448 | ||
3449 | /* Note!!! This is NOT an else clause. Odd sized | |
3450 | structs may go thru BOTH paths. Floating point | |
3451 | arguments will not. */ | |
3452 | /* Write this portion of the argument to a general | |
3453 | purpose register. */ | |
3454 | if (argreg <= MIPS_LAST_ARG_REGNUM | |
3455 | && !fp_register_arg_p (typecode, arg_type)) | |
3456 | { | |
3457 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 AC |
3458 | /* Value may need to be sign extended, because |
3459 | mips_regsize() != MIPS_SAVED_REGSIZE. */ | |
46cac009 AC |
3460 | |
3461 | /* A non-floating-point argument being passed in a | |
3462 | general register. If a struct or union, and if | |
3463 | the remaining length is smaller than the register | |
3464 | size, we have to adjust the register value on | |
3465 | big endian targets. | |
3466 | ||
3467 | It does not seem to be necessary to do the | |
3468 | same for integral types. | |
3469 | ||
3470 | Also don't do this adjustment on O64 binaries. | |
3471 | ||
3472 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3473 | outputting LE O32 with sizeof (struct) < | |
3474 | MIPS_SAVED_REGSIZE, generates a left shift as | |
3475 | part of storing the argument in a register a | |
3476 | register (the left shift isn't generated when | |
3477 | sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it | |
3478 | is quite possible that this is GCC contradicting | |
3479 | the LE/O32 ABI, GDB has not been adjusted to | |
3480 | accommodate this. Either someone needs to | |
3481 | demonstrate that the LE/O32 ABI specifies such a | |
3482 | left shift OR this new ABI gets identified as | |
3483 | such and GDB gets tweaked accordingly. */ | |
3484 | ||
3485 | if (MIPS_SAVED_REGSIZE < 8 | |
3486 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3487 | && partial_len < MIPS_SAVED_REGSIZE | |
3488 | && (typecode == TYPE_CODE_STRUCT || | |
3489 | typecode == TYPE_CODE_UNION)) | |
3490 | regval <<= ((MIPS_SAVED_REGSIZE - partial_len) * | |
3491 | TARGET_CHAR_BIT); | |
3492 | ||
3493 | if (mips_debug) | |
3494 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3495 | argreg, | |
3496 | phex (regval, MIPS_SAVED_REGSIZE)); | |
3497 | write_register (argreg, regval); | |
3498 | argreg++; | |
3499 | ||
3500 | /* Prevent subsequent floating point arguments from | |
3501 | being passed in floating point registers. */ | |
3502 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3503 | } | |
3504 | ||
3505 | len -= partial_len; | |
3506 | val += partial_len; | |
3507 | ||
3508 | /* Compute the the offset into the stack at which we | |
3509 | will copy the next parameter. | |
3510 | ||
3511 | In older ABIs, the caller reserved space for | |
3512 | registers that contained arguments. This was loosely | |
3513 | refered to as their "home". Consequently, space is | |
3514 | always allocated. */ | |
3515 | ||
5b03f266 | 3516 | stack_offset += align_up (partial_len, MIPS_STACK_ARGSIZE); |
46cac009 AC |
3517 | } |
3518 | } | |
3519 | if (mips_debug) | |
3520 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3521 | } | |
3522 | ||
310e9b6a AC |
3523 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
3524 | ||
46cac009 AC |
3525 | /* Return adjusted stack pointer. */ |
3526 | return sp; | |
3527 | } | |
3528 | ||
25ab4790 | 3529 | /* O64 version of push_dummy_call. */ |
46cac009 AC |
3530 | |
3531 | static CORE_ADDR | |
25ab4790 AC |
3532 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
3533 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
3534 | struct value **args, CORE_ADDR sp, int struct_return, | |
3535 | CORE_ADDR struct_addr) | |
46cac009 AC |
3536 | { |
3537 | int argreg; | |
3538 | int float_argreg; | |
3539 | int argnum; | |
3540 | int len = 0; | |
3541 | int stack_offset = 0; | |
3542 | ||
25ab4790 AC |
3543 | /* For shared libraries, "t9" needs to point at the function |
3544 | address. */ | |
3545 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3546 | ||
3547 | /* Set the return address register to point to the entry point of | |
3548 | the program, where a breakpoint lies in wait. */ | |
3549 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3550 | ||
46cac009 AC |
3551 | /* First ensure that the stack and structure return address (if any) |
3552 | are properly aligned. The stack has to be at least 64-bit | |
3553 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3554 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3555 | aligned, so we round to this widest known alignment. */ | |
3556 | ||
5b03f266 AC |
3557 | sp = align_down (sp, 16); |
3558 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
3559 | |
3560 | /* Now make space on the stack for the args. */ | |
3561 | for (argnum = 0; argnum < nargs; argnum++) | |
5b03f266 | 3562 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
46cac009 | 3563 | MIPS_STACK_ARGSIZE); |
5b03f266 | 3564 | sp -= align_up (len, 16); |
46cac009 AC |
3565 | |
3566 | if (mips_debug) | |
3567 | fprintf_unfiltered (gdb_stdlog, | |
5b03f266 AC |
3568 | "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n", |
3569 | paddr_nz (sp), (long) align_up (len, 16)); | |
46cac009 AC |
3570 | |
3571 | /* Initialize the integer and float register pointers. */ | |
3572 | argreg = A0_REGNUM; | |
56cea623 | 3573 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
46cac009 AC |
3574 | |
3575 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
3576 | if (struct_return) | |
3577 | { | |
3578 | if (mips_debug) | |
3579 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3580 | "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n", |
46cac009 AC |
3581 | argreg, paddr_nz (struct_addr)); |
3582 | write_register (argreg++, struct_addr); | |
3583 | stack_offset += MIPS_STACK_ARGSIZE; | |
3584 | } | |
3585 | ||
3586 | /* Now load as many as possible of the first arguments into | |
3587 | registers, and push the rest onto the stack. Loop thru args | |
3588 | from first to last. */ | |
3589 | for (argnum = 0; argnum < nargs; argnum++) | |
3590 | { | |
3591 | char *val; | |
d9d9c31f | 3592 | char valbuf[MAX_REGISTER_SIZE]; |
46cac009 AC |
3593 | struct value *arg = args[argnum]; |
3594 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3595 | int len = TYPE_LENGTH (arg_type); | |
3596 | enum type_code typecode = TYPE_CODE (arg_type); | |
3597 | ||
3598 | if (mips_debug) | |
3599 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3600 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
3601 | argnum + 1, len, (int) typecode); |
3602 | ||
3603 | val = (char *) VALUE_CONTENTS (arg); | |
3604 | ||
3605 | /* 32-bit ABIs always start floating point arguments in an | |
3606 | even-numbered floating point register. Round the FP register | |
3607 | up before the check to see if there are any FP registers | |
3608 | left. O32/O64 targets also pass the FP in the integer | |
3609 | registers so also round up normal registers. */ | |
3610 | if (!FP_REGISTER_DOUBLE | |
3611 | && fp_register_arg_p (typecode, arg_type)) | |
3612 | { | |
3613 | if ((float_argreg & 1)) | |
3614 | float_argreg++; | |
3615 | } | |
3616 | ||
3617 | /* Floating point arguments passed in registers have to be | |
3618 | treated specially. On 32-bit architectures, doubles | |
3619 | are passed in register pairs; the even register gets | |
3620 | the low word, and the odd register gets the high word. | |
3621 | On O32/O64, the first two floating point arguments are | |
3622 | also copied to general registers, because MIPS16 functions | |
3623 | don't use float registers for arguments. This duplication of | |
3624 | arguments in general registers can't hurt non-MIPS16 functions | |
3625 | because those registers are normally skipped. */ | |
3626 | ||
3627 | if (fp_register_arg_p (typecode, arg_type) | |
3628 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3629 | { | |
3630 | if (!FP_REGISTER_DOUBLE && len == 8) | |
3631 | { | |
3632 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
3633 | unsigned long regval; | |
3634 | ||
3635 | /* Write the low word of the double to the even register(s). */ | |
3636 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3637 | if (mips_debug) | |
3638 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3639 | float_argreg, phex (regval, 4)); | |
3640 | write_register (float_argreg++, regval); | |
3641 | if (mips_debug) | |
3642 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3643 | argreg, phex (regval, 4)); | |
3644 | write_register (argreg++, regval); | |
3645 | ||
3646 | /* Write the high word of the double to the odd register(s). */ | |
3647 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3648 | if (mips_debug) | |
3649 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3650 | float_argreg, phex (regval, 4)); | |
3651 | write_register (float_argreg++, regval); | |
3652 | ||
3653 | if (mips_debug) | |
3654 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3655 | argreg, phex (regval, 4)); | |
3656 | write_register (argreg++, regval); | |
3657 | } | |
3658 | else | |
3659 | { | |
3660 | /* This is a floating point value that fits entirely | |
3661 | in a single register. */ | |
3662 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3663 | above to ensure that it is even register aligned. */ | |
3664 | LONGEST regval = extract_unsigned_integer (val, len); | |
3665 | if (mips_debug) | |
3666 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3667 | float_argreg, phex (regval, len)); | |
3668 | write_register (float_argreg++, regval); | |
3669 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
3670 | registers for each argument. The below is (my | |
3671 | guess) to ensure that the corresponding integer | |
3672 | register has reserved the same space. */ | |
3673 | if (mips_debug) | |
3674 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3675 | argreg, phex (regval, len)); | |
3676 | write_register (argreg, regval); | |
3677 | argreg += FP_REGISTER_DOUBLE ? 1 : 2; | |
3678 | } | |
3679 | /* Reserve space for the FP register. */ | |
5b03f266 | 3680 | stack_offset += align_up (len, MIPS_STACK_ARGSIZE); |
ebafbe83 MS |
3681 | } |
3682 | else | |
3683 | { | |
3684 | /* Copy the argument to general registers or the stack in | |
3685 | register-sized pieces. Large arguments are split between | |
3686 | registers and stack. */ | |
4246e332 AC |
3687 | /* Note: structs whose size is not a multiple of |
3688 | mips_regsize() are treated specially: Irix cc passes them | |
3689 | in registers where gcc sometimes puts them on the stack. | |
3690 | For maximum compatibility, we will put them in both | |
3691 | places. */ | |
ebafbe83 MS |
3692 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && |
3693 | (len % MIPS_SAVED_REGSIZE != 0)); | |
3694 | /* Structures should be aligned to eight bytes (even arg registers) | |
3695 | on MIPS_ABI_O32, if their first member has double precision. */ | |
3696 | if (MIPS_SAVED_REGSIZE < 8 | |
3697 | && mips_type_needs_double_align (arg_type)) | |
3698 | { | |
3699 | if ((argreg & 1)) | |
3700 | argreg++; | |
3701 | } | |
3702 | /* Note: Floating-point values that didn't fit into an FP | |
3703 | register are only written to memory. */ | |
3704 | while (len > 0) | |
3705 | { | |
3706 | /* Remember if the argument was written to the stack. */ | |
3707 | int stack_used_p = 0; | |
3708 | int partial_len = | |
3709 | len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE; | |
3710 | ||
3711 | if (mips_debug) | |
3712 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3713 | partial_len); | |
3714 | ||
3715 | /* Write this portion of the argument to the stack. */ | |
3716 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3717 | || odd_sized_struct | |
3718 | || fp_register_arg_p (typecode, arg_type)) | |
3719 | { | |
3720 | /* Should shorter than int integer values be | |
3721 | promoted to int before being stored? */ | |
3722 | int longword_offset = 0; | |
3723 | CORE_ADDR addr; | |
3724 | stack_used_p = 1; | |
3725 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3726 | { | |
3727 | if (MIPS_STACK_ARGSIZE == 8 && | |
3728 | (typecode == TYPE_CODE_INT || | |
3729 | typecode == TYPE_CODE_PTR || | |
3730 | typecode == TYPE_CODE_FLT) && len <= 4) | |
3731 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
3732 | } | |
3733 | ||
3734 | if (mips_debug) | |
3735 | { | |
3736 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3737 | paddr_nz (stack_offset)); | |
3738 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3739 | paddr_nz (longword_offset)); | |
3740 | } | |
3741 | ||
3742 | addr = sp + stack_offset + longword_offset; | |
3743 | ||
3744 | if (mips_debug) | |
3745 | { | |
3746 | int i; | |
3747 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", | |
3748 | paddr_nz (addr)); | |
3749 | for (i = 0; i < partial_len; i++) | |
3750 | { | |
3751 | fprintf_unfiltered (gdb_stdlog, "%02x", | |
3752 | val[i] & 0xff); | |
3753 | } | |
3754 | } | |
3755 | write_memory (addr, val, partial_len); | |
3756 | } | |
3757 | ||
3758 | /* Note!!! This is NOT an else clause. Odd sized | |
3759 | structs may go thru BOTH paths. Floating point | |
3760 | arguments will not. */ | |
3761 | /* Write this portion of the argument to a general | |
3762 | purpose register. */ | |
3763 | if (argreg <= MIPS_LAST_ARG_REGNUM | |
3764 | && !fp_register_arg_p (typecode, arg_type)) | |
3765 | { | |
3766 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 AC |
3767 | /* Value may need to be sign extended, because |
3768 | mips_regsize() != MIPS_SAVED_REGSIZE. */ | |
ebafbe83 MS |
3769 | |
3770 | /* A non-floating-point argument being passed in a | |
3771 | general register. If a struct or union, and if | |
3772 | the remaining length is smaller than the register | |
3773 | size, we have to adjust the register value on | |
3774 | big endian targets. | |
3775 | ||
3776 | It does not seem to be necessary to do the | |
3777 | same for integral types. | |
3778 | ||
3779 | Also don't do this adjustment on O64 binaries. | |
3780 | ||
3781 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3782 | outputting LE O32 with sizeof (struct) < | |
3783 | MIPS_SAVED_REGSIZE, generates a left shift as | |
3784 | part of storing the argument in a register a | |
3785 | register (the left shift isn't generated when | |
3786 | sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it | |
3787 | is quite possible that this is GCC contradicting | |
3788 | the LE/O32 ABI, GDB has not been adjusted to | |
3789 | accommodate this. Either someone needs to | |
3790 | demonstrate that the LE/O32 ABI specifies such a | |
3791 | left shift OR this new ABI gets identified as | |
3792 | such and GDB gets tweaked accordingly. */ | |
3793 | ||
3794 | if (MIPS_SAVED_REGSIZE < 8 | |
3795 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3796 | && partial_len < MIPS_SAVED_REGSIZE | |
3797 | && (typecode == TYPE_CODE_STRUCT || | |
3798 | typecode == TYPE_CODE_UNION)) | |
3799 | regval <<= ((MIPS_SAVED_REGSIZE - partial_len) * | |
3800 | TARGET_CHAR_BIT); | |
3801 | ||
3802 | if (mips_debug) | |
3803 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3804 | argreg, | |
3805 | phex (regval, MIPS_SAVED_REGSIZE)); | |
3806 | write_register (argreg, regval); | |
3807 | argreg++; | |
3808 | ||
3809 | /* Prevent subsequent floating point arguments from | |
3810 | being passed in floating point registers. */ | |
3811 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3812 | } | |
3813 | ||
3814 | len -= partial_len; | |
3815 | val += partial_len; | |
3816 | ||
3817 | /* Compute the the offset into the stack at which we | |
3818 | will copy the next parameter. | |
3819 | ||
3820 | In older ABIs, the caller reserved space for | |
3821 | registers that contained arguments. This was loosely | |
3822 | refered to as their "home". Consequently, space is | |
3823 | always allocated. */ | |
3824 | ||
5b03f266 | 3825 | stack_offset += align_up (partial_len, MIPS_STACK_ARGSIZE); |
ebafbe83 MS |
3826 | } |
3827 | } | |
3828 | if (mips_debug) | |
3829 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3830 | } | |
3831 | ||
310e9b6a AC |
3832 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
3833 | ||
ebafbe83 MS |
3834 | /* Return adjusted stack pointer. */ |
3835 | return sp; | |
3836 | } | |
3837 | ||
f7ab6ec6 | 3838 | static void |
acdb74a0 | 3839 | mips_pop_frame (void) |
c906108c | 3840 | { |
52f0bd74 | 3841 | int regnum; |
c906108c | 3842 | struct frame_info *frame = get_current_frame (); |
c193f6ac | 3843 | CORE_ADDR new_sp = get_frame_base (frame); |
e227b13c | 3844 | mips_extra_func_info_t proc_desc; |
c906108c | 3845 | |
50abf9e5 | 3846 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0)) |
cedea778 AC |
3847 | { |
3848 | generic_pop_dummy_frame (); | |
3849 | flush_cached_frames (); | |
3850 | return; | |
3851 | } | |
3852 | ||
e227b13c | 3853 | proc_desc = get_frame_extra_info (frame)->proc_desc; |
8bedc050 | 3854 | write_register (PC_REGNUM, DEPRECATED_FRAME_SAVED_PC (frame)); |
e0f7ec59 | 3855 | mips_find_saved_regs (frame); |
c906108c | 3856 | for (regnum = 0; regnum < NUM_REGS; regnum++) |
21f87145 | 3857 | if (regnum != SP_REGNUM && regnum != PC_REGNUM |
1b1d3794 | 3858 | && deprecated_get_frame_saved_regs (frame)[regnum]) |
21f87145 MS |
3859 | { |
3860 | /* Floating point registers must not be sign extended, | |
3861 | in case MIPS_SAVED_REGSIZE = 4 but sizeof (FP0_REGNUM) == 8. */ | |
3862 | ||
56cea623 | 3863 | if (mips_regnum (current_gdbarch)->fp0 <= regnum && regnum < mips_regnum (current_gdbarch)->fp0 + 32) |
21f87145 | 3864 | write_register (regnum, |
1b1d3794 | 3865 | read_memory_unsigned_integer (deprecated_get_frame_saved_regs (frame)[regnum], |
21f87145 MS |
3866 | MIPS_SAVED_REGSIZE)); |
3867 | else | |
3868 | write_register (regnum, | |
1b1d3794 | 3869 | read_memory_integer (deprecated_get_frame_saved_regs (frame)[regnum], |
21f87145 MS |
3870 | MIPS_SAVED_REGSIZE)); |
3871 | } | |
757a7cc6 | 3872 | |
c906108c SS |
3873 | write_register (SP_REGNUM, new_sp); |
3874 | flush_cached_frames (); | |
3875 | ||
c5aa993b | 3876 | if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) |
c906108c SS |
3877 | { |
3878 | struct linked_proc_info *pi_ptr, *prev_ptr; | |
3879 | ||
3880 | for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL; | |
3881 | pi_ptr != NULL; | |
3882 | prev_ptr = pi_ptr, pi_ptr = pi_ptr->next) | |
3883 | { | |
3884 | if (&pi_ptr->info == proc_desc) | |
3885 | break; | |
3886 | } | |
3887 | ||
3888 | if (pi_ptr == NULL) | |
3889 | error ("Can't locate dummy extra frame info\n"); | |
3890 | ||
3891 | if (prev_ptr != NULL) | |
3892 | prev_ptr->next = pi_ptr->next; | |
3893 | else | |
3894 | linked_proc_desc_table = pi_ptr->next; | |
3895 | ||
b8c9b27d | 3896 | xfree (pi_ptr); |
c906108c | 3897 | |
56cea623 | 3898 | write_register (mips_regnum (current_gdbarch)->hi, |
c5aa993b | 3899 | read_memory_integer (new_sp - 2 * MIPS_SAVED_REGSIZE, |
7a292a7a | 3900 | MIPS_SAVED_REGSIZE)); |
56cea623 | 3901 | write_register (mips_regnum (current_gdbarch)->lo, |
c5aa993b | 3902 | read_memory_integer (new_sp - 3 * MIPS_SAVED_REGSIZE, |
7a292a7a | 3903 | MIPS_SAVED_REGSIZE)); |
c906108c | 3904 | if (MIPS_FPU_TYPE != MIPS_FPU_NONE) |
56cea623 | 3905 | write_register (mips_regnum (current_gdbarch)->fp_control_status, |
c5aa993b | 3906 | read_memory_integer (new_sp - 4 * MIPS_SAVED_REGSIZE, |
7a292a7a | 3907 | MIPS_SAVED_REGSIZE)); |
c906108c SS |
3908 | } |
3909 | } | |
3910 | ||
dd824b04 DJ |
3911 | /* Floating point register management. |
3912 | ||
3913 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
3914 | 64bit operations, these early MIPS cpus treat fp register pairs | |
3915 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
3916 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
3917 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
3918 | double precision floats into two 32-bit chunks and store them in | |
3919 | consecutive fp regs. To display 64-bit floats stored in this | |
3920 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
3921 | Throw in user-configurable endianness and you have a real mess. | |
3922 | ||
3923 | The way this works is: | |
3924 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
3925 | double-precision value will be split across two logical registers. | |
3926 | The lower-numbered logical register will hold the low-order bits, | |
3927 | regardless of the processor's endianness. | |
3928 | - If we are on a 64-bit processor, and we are looking for a | |
3929 | single-precision value, it will be in the low ordered bits | |
3930 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
3931 | save slot in memory. | |
3932 | - If we are in 64-bit mode, everything is straightforward. | |
3933 | ||
3934 | Note that this code only deals with "live" registers at the top of the | |
3935 | stack. We will attempt to deal with saved registers later, when | |
3936 | the raw/cooked register interface is in place. (We need a general | |
3937 | interface that can deal with dynamic saved register sizes -- fp | |
3938 | regs could be 32 bits wide in one frame and 64 on the frame above | |
3939 | and below). */ | |
3940 | ||
67b2c998 DJ |
3941 | static struct type * |
3942 | mips_float_register_type (void) | |
3943 | { | |
361d1df0 | 3944 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
3945 | return builtin_type_ieee_single_big; |
3946 | else | |
3947 | return builtin_type_ieee_single_little; | |
3948 | } | |
3949 | ||
3950 | static struct type * | |
3951 | mips_double_register_type (void) | |
3952 | { | |
361d1df0 | 3953 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
3954 | return builtin_type_ieee_double_big; |
3955 | else | |
3956 | return builtin_type_ieee_double_little; | |
3957 | } | |
3958 | ||
dd824b04 DJ |
3959 | /* Copy a 32-bit single-precision value from the current frame |
3960 | into rare_buffer. */ | |
3961 | ||
3962 | static void | |
e11c53d2 AC |
3963 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
3964 | char *rare_buffer) | |
dd824b04 | 3965 | { |
719ec221 | 3966 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 DJ |
3967 | char *raw_buffer = alloca (raw_size); |
3968 | ||
e11c53d2 | 3969 | if (!frame_register_read (frame, regno, raw_buffer)) |
dd824b04 DJ |
3970 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
3971 | if (raw_size == 8) | |
3972 | { | |
3973 | /* We have a 64-bit value for this register. Find the low-order | |
3974 | 32 bits. */ | |
3975 | int offset; | |
3976 | ||
3977 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3978 | offset = 4; | |
3979 | else | |
3980 | offset = 0; | |
3981 | ||
3982 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
3983 | } | |
3984 | else | |
3985 | { | |
3986 | memcpy (rare_buffer, raw_buffer, 4); | |
3987 | } | |
3988 | } | |
3989 | ||
3990 | /* Copy a 64-bit double-precision value from the current frame into | |
3991 | rare_buffer. This may include getting half of it from the next | |
3992 | register. */ | |
3993 | ||
3994 | static void | |
e11c53d2 AC |
3995 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
3996 | char *rare_buffer) | |
dd824b04 | 3997 | { |
719ec221 | 3998 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 DJ |
3999 | |
4000 | if (raw_size == 8 && !mips2_fp_compat ()) | |
4001 | { | |
4002 | /* We have a 64-bit value for this register, and we should use | |
4003 | all 64 bits. */ | |
e11c53d2 | 4004 | if (!frame_register_read (frame, regno, rare_buffer)) |
dd824b04 DJ |
4005 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
4006 | } | |
4007 | else | |
4008 | { | |
56cea623 | 4009 | if ((regno - mips_regnum (current_gdbarch)->fp0) & 1) |
dd824b04 DJ |
4010 | internal_error (__FILE__, __LINE__, |
4011 | "mips_read_fp_register_double: bad access to " | |
4012 | "odd-numbered FP register"); | |
4013 | ||
4014 | /* mips_read_fp_register_single will find the correct 32 bits from | |
4015 | each register. */ | |
4016 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
4017 | { | |
e11c53d2 AC |
4018 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
4019 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 4020 | } |
361d1df0 | 4021 | else |
dd824b04 | 4022 | { |
e11c53d2 AC |
4023 | mips_read_fp_register_single (frame, regno, rare_buffer); |
4024 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
4025 | } |
4026 | } | |
4027 | } | |
4028 | ||
c906108c | 4029 | static void |
e11c53d2 AC |
4030 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
4031 | int regnum) | |
c5aa993b | 4032 | { /* do values for FP (float) regs */ |
dd824b04 | 4033 | char *raw_buffer; |
c906108c | 4034 | double doub, flt1, flt2; /* doubles extracted from raw hex data */ |
f0ef6b29 | 4035 | int inv1, inv2, namelen; |
c5aa993b | 4036 | |
56cea623 | 4037 | raw_buffer = (char *) alloca (2 * register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0)); |
c906108c | 4038 | |
e11c53d2 AC |
4039 | fprintf_filtered (file, "%s:", REGISTER_NAME (regnum)); |
4040 | fprintf_filtered (file, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum)), | |
4041 | ""); | |
f0ef6b29 | 4042 | |
719ec221 | 4043 | if (register_size (current_gdbarch, regnum) == 4 || mips2_fp_compat ()) |
c906108c | 4044 | { |
f0ef6b29 KB |
4045 | /* 4-byte registers: Print hex and floating. Also print even |
4046 | numbered registers as doubles. */ | |
e11c53d2 | 4047 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
67b2c998 | 4048 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c5aa993b | 4049 | |
e11c53d2 | 4050 | print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w', file); |
dd824b04 | 4051 | |
e11c53d2 | 4052 | fprintf_filtered (file, " flt: "); |
1adad886 | 4053 | if (inv1) |
e11c53d2 | 4054 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4055 | else |
e11c53d2 | 4056 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4057 | |
f0ef6b29 KB |
4058 | if (regnum % 2 == 0) |
4059 | { | |
e11c53d2 | 4060 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
4061 | doub = unpack_double (mips_double_register_type (), raw_buffer, |
4062 | &inv2); | |
1adad886 | 4063 | |
e11c53d2 | 4064 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4065 | if (inv2) |
e11c53d2 | 4066 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 4067 | else |
e11c53d2 | 4068 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 4069 | } |
c906108c SS |
4070 | } |
4071 | else | |
dd824b04 | 4072 | { |
f0ef6b29 | 4073 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 4074 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
2f38ef89 | 4075 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c906108c | 4076 | |
e11c53d2 | 4077 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
4078 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2); |
4079 | ||
361d1df0 | 4080 | |
e11c53d2 | 4081 | print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g', file); |
f0ef6b29 | 4082 | |
e11c53d2 | 4083 | fprintf_filtered (file, " flt: "); |
1adad886 | 4084 | if (inv1) |
e11c53d2 | 4085 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 4086 | else |
e11c53d2 | 4087 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4088 | |
e11c53d2 | 4089 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4090 | if (inv2) |
e11c53d2 | 4091 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 4092 | else |
e11c53d2 | 4093 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
4094 | } |
4095 | } | |
4096 | ||
4097 | static void | |
e11c53d2 AC |
4098 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
4099 | int regnum, int all) | |
f0ef6b29 | 4100 | { |
a4b8ebc8 | 4101 | struct gdbarch *gdbarch = get_frame_arch (frame); |
d9d9c31f | 4102 | char raw_buffer[MAX_REGISTER_SIZE]; |
f0ef6b29 | 4103 | int offset; |
1adad886 | 4104 | |
a4b8ebc8 | 4105 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 4106 | { |
e11c53d2 | 4107 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4108 | return; |
4109 | } | |
4110 | ||
4111 | /* Get the data in raw format. */ | |
e11c53d2 | 4112 | if (!frame_register_read (frame, regnum, raw_buffer)) |
f0ef6b29 | 4113 | { |
e11c53d2 | 4114 | fprintf_filtered (file, "%s: [Invalid]", REGISTER_NAME (regnum)); |
f0ef6b29 | 4115 | return; |
c906108c | 4116 | } |
f0ef6b29 | 4117 | |
e11c53d2 | 4118 | fputs_filtered (REGISTER_NAME (regnum), file); |
f0ef6b29 KB |
4119 | |
4120 | /* The problem with printing numeric register names (r26, etc.) is that | |
4121 | the user can't use them on input. Probably the best solution is to | |
4122 | fix it so that either the numeric or the funky (a2, etc.) names | |
4123 | are accepted on input. */ | |
4124 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 4125 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 4126 | else |
e11c53d2 | 4127 | fprintf_filtered (file, ": "); |
f0ef6b29 KB |
4128 | |
4129 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
719ec221 | 4130 | offset = register_size (current_gdbarch, regnum) - register_size (current_gdbarch, regnum); |
f0ef6b29 KB |
4131 | else |
4132 | offset = 0; | |
4133 | ||
a4b8ebc8 | 4134 | print_scalar_formatted (raw_buffer + offset, gdbarch_register_type (gdbarch, regnum), |
e11c53d2 | 4135 | 'x', 0, file); |
c906108c SS |
4136 | } |
4137 | ||
f0ef6b29 KB |
4138 | /* Replacement for generic do_registers_info. |
4139 | Print regs in pretty columns. */ | |
4140 | ||
4141 | static int | |
e11c53d2 AC |
4142 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
4143 | int regnum) | |
f0ef6b29 | 4144 | { |
e11c53d2 AC |
4145 | fprintf_filtered (file, " "); |
4146 | mips_print_fp_register (file, frame, regnum); | |
4147 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
4148 | return regnum + 1; |
4149 | } | |
4150 | ||
4151 | ||
c906108c SS |
4152 | /* Print a row's worth of GP (int) registers, with name labels above */ |
4153 | ||
4154 | static int | |
e11c53d2 | 4155 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 4156 | int start_regnum) |
c906108c | 4157 | { |
a4b8ebc8 | 4158 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 4159 | /* do values for GP (int) regs */ |
d9d9c31f | 4160 | char raw_buffer[MAX_REGISTER_SIZE]; |
4246e332 | 4161 | int ncols = (mips_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */ |
c906108c | 4162 | int col, byte; |
a4b8ebc8 | 4163 | int regnum; |
c906108c SS |
4164 | |
4165 | /* For GP registers, we print a separate row of names above the vals */ | |
e11c53d2 | 4166 | fprintf_filtered (file, " "); |
a4b8ebc8 AC |
4167 | for (col = 0, regnum = start_regnum; |
4168 | col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; | |
4169 | regnum++) | |
c906108c SS |
4170 | { |
4171 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 4172 | continue; /* unused register */ |
a4b8ebc8 | 4173 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
c5aa993b | 4174 | break; /* end the row: reached FP register */ |
4246e332 | 4175 | fprintf_filtered (file, mips_regsize (current_gdbarch) == 8 ? "%17s" : "%9s", |
e11c53d2 | 4176 | REGISTER_NAME (regnum)); |
c906108c SS |
4177 | col++; |
4178 | } | |
a4b8ebc8 | 4179 | /* print the R0 to R31 names */ |
20e6603c AC |
4180 | if ((start_regnum % NUM_REGS) < MIPS_NUMREGS) |
4181 | fprintf_filtered (file, "\n R%-4d", start_regnum % NUM_REGS); | |
4182 | else | |
4183 | fprintf_filtered (file, "\n "); | |
c906108c | 4184 | |
c906108c | 4185 | /* now print the values in hex, 4 or 8 to the row */ |
a4b8ebc8 AC |
4186 | for (col = 0, regnum = start_regnum; |
4187 | col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; | |
4188 | regnum++) | |
c906108c SS |
4189 | { |
4190 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 4191 | continue; /* unused register */ |
a4b8ebc8 | 4192 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
c5aa993b | 4193 | break; /* end row: reached FP register */ |
c906108c | 4194 | /* OK: get the data in raw format. */ |
e11c53d2 | 4195 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c906108c SS |
4196 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); |
4197 | /* pad small registers */ | |
4246e332 AC |
4198 | for (byte = 0; |
4199 | byte < (mips_regsize (current_gdbarch) | |
c73e8f27 | 4200 | - register_size (current_gdbarch, regnum)); |
4246e332 | 4201 | byte++) |
c906108c SS |
4202 | printf_filtered (" "); |
4203 | /* Now print the register value in hex, endian order. */ | |
d7449b42 | 4204 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
719ec221 AC |
4205 | for (byte = register_size (current_gdbarch, regnum) - register_size (current_gdbarch, regnum); |
4206 | byte < register_size (current_gdbarch, regnum); | |
43e526b9 | 4207 | byte++) |
e11c53d2 | 4208 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); |
c906108c | 4209 | else |
c73e8f27 | 4210 | for (byte = register_size (current_gdbarch, regnum) - 1; |
43e526b9 JM |
4211 | byte >= 0; |
4212 | byte--) | |
e11c53d2 AC |
4213 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); |
4214 | fprintf_filtered (file, " "); | |
c906108c SS |
4215 | col++; |
4216 | } | |
c5aa993b | 4217 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 4218 | fprintf_filtered (file, "\n"); |
c906108c SS |
4219 | |
4220 | return regnum; | |
4221 | } | |
4222 | ||
4223 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
4224 | ||
bf1f5b4c | 4225 | static void |
e11c53d2 AC |
4226 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4227 | struct frame_info *frame, int regnum, int all) | |
c906108c | 4228 | { |
c5aa993b | 4229 | if (regnum != -1) /* do one specified register */ |
c906108c | 4230 | { |
a4b8ebc8 | 4231 | gdb_assert (regnum >= NUM_REGS); |
c906108c SS |
4232 | if (*(REGISTER_NAME (regnum)) == '\0') |
4233 | error ("Not a valid register for the current processor type"); | |
4234 | ||
e11c53d2 AC |
4235 | mips_print_register (file, frame, regnum, 0); |
4236 | fprintf_filtered (file, "\n"); | |
c906108c | 4237 | } |
c5aa993b JM |
4238 | else |
4239 | /* do all (or most) registers */ | |
c906108c | 4240 | { |
a4b8ebc8 AC |
4241 | regnum = NUM_REGS; |
4242 | while (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
c906108c | 4243 | { |
a4b8ebc8 | 4244 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
e11c53d2 AC |
4245 | { |
4246 | if (all) /* true for "INFO ALL-REGISTERS" command */ | |
4247 | regnum = print_fp_register_row (file, frame, regnum); | |
4248 | else | |
4249 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
4250 | } | |
c906108c | 4251 | else |
e11c53d2 | 4252 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
4253 | } |
4254 | } | |
4255 | } | |
4256 | ||
c906108c SS |
4257 | /* Is this a branch with a delay slot? */ |
4258 | ||
a14ed312 | 4259 | static int is_delayed (unsigned long); |
c906108c SS |
4260 | |
4261 | static int | |
acdb74a0 | 4262 | is_delayed (unsigned long insn) |
c906108c SS |
4263 | { |
4264 | int i; | |
4265 | for (i = 0; i < NUMOPCODES; ++i) | |
4266 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4267 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4268 | break; | |
4269 | return (i < NUMOPCODES | |
4270 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4271 | | INSN_COND_BRANCH_DELAY | |
4272 | | INSN_COND_BRANCH_LIKELY))); | |
4273 | } | |
4274 | ||
4275 | int | |
acdb74a0 | 4276 | mips_step_skips_delay (CORE_ADDR pc) |
c906108c SS |
4277 | { |
4278 | char buf[MIPS_INSTLEN]; | |
4279 | ||
4280 | /* There is no branch delay slot on MIPS16. */ | |
4281 | if (pc_is_mips16 (pc)) | |
4282 | return 0; | |
4283 | ||
4284 | if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0) | |
4285 | /* If error reading memory, guess that it is not a delayed branch. */ | |
4286 | return 0; | |
c5aa993b | 4287 | return is_delayed ((unsigned long) extract_unsigned_integer (buf, MIPS_INSTLEN)); |
c906108c SS |
4288 | } |
4289 | ||
4290 | ||
74da7425 AC |
4291 | /* Given PC at the function's start address, attempt to find the |
4292 | prologue end using SAL information. Return zero if the skip fails. | |
4293 | ||
4294 | A non-optimized prologue traditionally has one SAL for the function | |
4295 | and a second for the function body. A single line function has | |
4296 | them both pointing at the same line. | |
4297 | ||
4298 | An optimized prologue is similar but the prologue may contain | |
4299 | instructions (SALs) from the instruction body. Need to skip those | |
4300 | while not getting into the function body. | |
4301 | ||
4302 | The functions end point and an increasing SAL line are used as | |
4303 | indicators of the prologue's endpoint. | |
4304 | ||
4305 | This code is based on the function refine_prologue_limit (versions | |
4306 | found in both ia64 and ppc). */ | |
4307 | ||
4308 | static CORE_ADDR | |
4309 | skip_prologue_using_sal (CORE_ADDR func_addr) | |
4310 | { | |
4311 | struct symtab_and_line prologue_sal; | |
4312 | CORE_ADDR start_pc; | |
4313 | CORE_ADDR end_pc; | |
4314 | ||
4315 | /* Get an initial range for the function. */ | |
4316 | find_pc_partial_function (func_addr, NULL, &start_pc, &end_pc); | |
4317 | start_pc += FUNCTION_START_OFFSET; | |
4318 | ||
4319 | prologue_sal = find_pc_line (start_pc, 0); | |
4320 | if (prologue_sal.line != 0) | |
4321 | { | |
4322 | while (prologue_sal.end < end_pc) | |
4323 | { | |
4324 | struct symtab_and_line sal; | |
4325 | ||
4326 | sal = find_pc_line (prologue_sal.end, 0); | |
4327 | if (sal.line == 0) | |
4328 | break; | |
4329 | /* Assume that a consecutive SAL for the same (or larger) | |
4330 | line mark the prologue -> body transition. */ | |
4331 | if (sal.line >= prologue_sal.line) | |
4332 | break; | |
4333 | /* The case in which compiler's optimizer/scheduler has | |
4334 | moved instructions into the prologue. We look ahead in | |
4335 | the function looking for address ranges whose | |
4336 | corresponding line number is less the first one that we | |
4337 | found for the function. This is more conservative then | |
4338 | refine_prologue_limit which scans a large number of SALs | |
4339 | looking for any in the prologue */ | |
4340 | prologue_sal = sal; | |
4341 | } | |
4342 | } | |
4343 | return prologue_sal.end; | |
4344 | } | |
4345 | ||
c906108c SS |
4346 | /* Skip the PC past function prologue instructions (32-bit version). |
4347 | This is a helper function for mips_skip_prologue. */ | |
4348 | ||
4349 | static CORE_ADDR | |
f7b9e9fc | 4350 | mips32_skip_prologue (CORE_ADDR pc) |
c906108c | 4351 | { |
c5aa993b JM |
4352 | t_inst inst; |
4353 | CORE_ADDR end_pc; | |
4354 | int seen_sp_adjust = 0; | |
4355 | int load_immediate_bytes = 0; | |
4356 | ||
74da7425 AC |
4357 | /* Find an upper bound on the prologue. */ |
4358 | end_pc = skip_prologue_using_sal (pc); | |
4359 | if (end_pc == 0) | |
4360 | end_pc = pc + 100; /* Magic. */ | |
4361 | ||
c5aa993b JM |
4362 | /* Skip the typical prologue instructions. These are the stack adjustment |
4363 | instruction and the instructions that save registers on the stack | |
4364 | or in the gcc frame. */ | |
74da7425 | 4365 | for (; pc < end_pc; pc += MIPS_INSTLEN) |
c5aa993b JM |
4366 | { |
4367 | unsigned long high_word; | |
c906108c | 4368 | |
c5aa993b JM |
4369 | inst = mips_fetch_instruction (pc); |
4370 | high_word = (inst >> 16) & 0xffff; | |
c906108c | 4371 | |
c5aa993b JM |
4372 | if (high_word == 0x27bd /* addiu $sp,$sp,offset */ |
4373 | || high_word == 0x67bd) /* daddiu $sp,$sp,offset */ | |
4374 | seen_sp_adjust = 1; | |
4375 | else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */ | |
4376 | inst == 0x03a8e823) /* subu $sp,$sp,$t0 */ | |
4377 | seen_sp_adjust = 1; | |
4378 | else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */ | |
4379 | || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */ | |
4380 | && (inst & 0x001F0000)) /* reg != $zero */ | |
4381 | continue; | |
4382 | ||
4383 | else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */ | |
4384 | continue; | |
4385 | else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000)) | |
4386 | /* sx reg,n($s8) */ | |
4387 | continue; /* reg != $zero */ | |
4388 | ||
4389 | /* move $s8,$sp. With different versions of gas this will be either | |
4390 | `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'. | |
4391 | Accept any one of these. */ | |
4392 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
4393 | continue; | |
4394 | ||
4395 | else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */ | |
4396 | continue; | |
4397 | else if (high_word == 0x3c1c) /* lui $gp,n */ | |
4398 | continue; | |
4399 | else if (high_word == 0x279c) /* addiu $gp,$gp,n */ | |
4400 | continue; | |
4401 | else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
4402 | || inst == 0x033ce021) /* addu $gp,$t9,$gp */ | |
4403 | continue; | |
4404 | /* The following instructions load $at or $t0 with an immediate | |
4405 | value in preparation for a stack adjustment via | |
4406 | subu $sp,$sp,[$at,$t0]. These instructions could also initialize | |
4407 | a local variable, so we accept them only before a stack adjustment | |
4408 | instruction was seen. */ | |
4409 | else if (!seen_sp_adjust) | |
4410 | { | |
4411 | if (high_word == 0x3c01 || /* lui $at,n */ | |
4412 | high_word == 0x3c08) /* lui $t0,n */ | |
4413 | { | |
4414 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
4415 | continue; | |
4416 | } | |
4417 | else if (high_word == 0x3421 || /* ori $at,$at,n */ | |
4418 | high_word == 0x3508 || /* ori $t0,$t0,n */ | |
4419 | high_word == 0x3401 || /* ori $at,$zero,n */ | |
4420 | high_word == 0x3408) /* ori $t0,$zero,n */ | |
4421 | { | |
4422 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
4423 | continue; | |
4424 | } | |
4425 | else | |
4426 | break; | |
4427 | } | |
4428 | else | |
4429 | break; | |
c906108c SS |
4430 | } |
4431 | ||
c5aa993b JM |
4432 | /* In a frameless function, we might have incorrectly |
4433 | skipped some load immediate instructions. Undo the skipping | |
4434 | if the load immediate was not followed by a stack adjustment. */ | |
4435 | if (load_immediate_bytes && !seen_sp_adjust) | |
4436 | pc -= load_immediate_bytes; | |
4437 | return pc; | |
c906108c SS |
4438 | } |
4439 | ||
4440 | /* Skip the PC past function prologue instructions (16-bit version). | |
4441 | This is a helper function for mips_skip_prologue. */ | |
4442 | ||
4443 | static CORE_ADDR | |
f7b9e9fc | 4444 | mips16_skip_prologue (CORE_ADDR pc) |
c906108c | 4445 | { |
c5aa993b JM |
4446 | CORE_ADDR end_pc; |
4447 | int extend_bytes = 0; | |
4448 | int prev_extend_bytes; | |
c906108c | 4449 | |
c5aa993b JM |
4450 | /* Table of instructions likely to be found in a function prologue. */ |
4451 | static struct | |
c906108c SS |
4452 | { |
4453 | unsigned short inst; | |
4454 | unsigned short mask; | |
c5aa993b JM |
4455 | } |
4456 | table[] = | |
4457 | { | |
c906108c | 4458 | { |
c5aa993b JM |
4459 | 0x6300, 0xff00 |
4460 | } | |
4461 | , /* addiu $sp,offset */ | |
4462 | { | |
4463 | 0xfb00, 0xff00 | |
4464 | } | |
4465 | , /* daddiu $sp,offset */ | |
4466 | { | |
4467 | 0xd000, 0xf800 | |
4468 | } | |
4469 | , /* sw reg,n($sp) */ | |
4470 | { | |
4471 | 0xf900, 0xff00 | |
4472 | } | |
4473 | , /* sd reg,n($sp) */ | |
4474 | { | |
4475 | 0x6200, 0xff00 | |
4476 | } | |
4477 | , /* sw $ra,n($sp) */ | |
4478 | { | |
4479 | 0xfa00, 0xff00 | |
4480 | } | |
4481 | , /* sd $ra,n($sp) */ | |
4482 | { | |
4483 | 0x673d, 0xffff | |
4484 | } | |
4485 | , /* move $s1,sp */ | |
4486 | { | |
4487 | 0xd980, 0xff80 | |
4488 | } | |
4489 | , /* sw $a0-$a3,n($s1) */ | |
4490 | { | |
4491 | 0x6704, 0xff1c | |
4492 | } | |
4493 | , /* move reg,$a0-$a3 */ | |
4494 | { | |
4495 | 0xe809, 0xf81f | |
4496 | } | |
4497 | , /* entry pseudo-op */ | |
4498 | { | |
4499 | 0x0100, 0xff00 | |
4500 | } | |
4501 | , /* addiu $s1,$sp,n */ | |
4502 | { | |
4503 | 0, 0 | |
4504 | } /* end of table marker */ | |
4505 | }; | |
4506 | ||
74da7425 AC |
4507 | /* Find an upper bound on the prologue. */ |
4508 | end_pc = skip_prologue_using_sal (pc); | |
4509 | if (end_pc == 0) | |
4510 | end_pc = pc + 100; /* Magic. */ | |
4511 | ||
c5aa993b JM |
4512 | /* Skip the typical prologue instructions. These are the stack adjustment |
4513 | instruction and the instructions that save registers on the stack | |
4514 | or in the gcc frame. */ | |
74da7425 | 4515 | for (; pc < end_pc; pc += MIPS16_INSTLEN) |
c5aa993b JM |
4516 | { |
4517 | unsigned short inst; | |
4518 | int i; | |
c906108c | 4519 | |
c5aa993b | 4520 | inst = mips_fetch_instruction (pc); |
c906108c | 4521 | |
c5aa993b JM |
4522 | /* Normally we ignore an extend instruction. However, if it is |
4523 | not followed by a valid prologue instruction, we must adjust | |
4524 | the pc back over the extend so that it won't be considered | |
4525 | part of the prologue. */ | |
4526 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
4527 | { | |
4528 | extend_bytes = MIPS16_INSTLEN; | |
4529 | continue; | |
4530 | } | |
4531 | prev_extend_bytes = extend_bytes; | |
4532 | extend_bytes = 0; | |
c906108c | 4533 | |
c5aa993b JM |
4534 | /* Check for other valid prologue instructions besides extend. */ |
4535 | for (i = 0; table[i].mask != 0; i++) | |
4536 | if ((inst & table[i].mask) == table[i].inst) /* found, get out */ | |
4537 | break; | |
4538 | if (table[i].mask != 0) /* it was in table? */ | |
4539 | continue; /* ignore it */ | |
4540 | else | |
4541 | /* non-prologue */ | |
4542 | { | |
4543 | /* Return the current pc, adjusted backwards by 2 if | |
4544 | the previous instruction was an extend. */ | |
4545 | return pc - prev_extend_bytes; | |
4546 | } | |
c906108c SS |
4547 | } |
4548 | return pc; | |
4549 | } | |
4550 | ||
4551 | /* To skip prologues, I use this predicate. Returns either PC itself | |
4552 | if the code at PC does not look like a function prologue; otherwise | |
4553 | returns an address that (if we're lucky) follows the prologue. If | |
4554 | LENIENT, then we must skip everything which is involved in setting | |
4555 | up the frame (it's OK to skip more, just so long as we don't skip | |
4556 | anything which might clobber the registers which are being saved. | |
4557 | We must skip more in the case where part of the prologue is in the | |
4558 | delay slot of a non-prologue instruction). */ | |
4559 | ||
f7ab6ec6 | 4560 | static CORE_ADDR |
f7b9e9fc | 4561 | mips_skip_prologue (CORE_ADDR pc) |
c906108c SS |
4562 | { |
4563 | /* See if we can determine the end of the prologue via the symbol table. | |
4564 | If so, then return either PC, or the PC after the prologue, whichever | |
4565 | is greater. */ | |
4566 | ||
4567 | CORE_ADDR post_prologue_pc = after_prologue (pc, NULL); | |
4568 | ||
4569 | if (post_prologue_pc != 0) | |
4570 | return max (pc, post_prologue_pc); | |
4571 | ||
4572 | /* Can't determine prologue from the symbol table, need to examine | |
4573 | instructions. */ | |
4574 | ||
4575 | if (pc_is_mips16 (pc)) | |
f7b9e9fc | 4576 | return mips16_skip_prologue (pc); |
c906108c | 4577 | else |
f7b9e9fc | 4578 | return mips32_skip_prologue (pc); |
c906108c | 4579 | } |
c906108c | 4580 | |
7a292a7a SS |
4581 | /* Determine how a return value is stored within the MIPS register |
4582 | file, given the return type `valtype'. */ | |
4583 | ||
4584 | struct return_value_word | |
4585 | { | |
4586 | int len; | |
4587 | int reg; | |
4588 | int reg_offset; | |
4589 | int buf_offset; | |
4590 | }; | |
4591 | ||
7a292a7a | 4592 | static void |
acdb74a0 AC |
4593 | return_value_location (struct type *valtype, |
4594 | struct return_value_word *hi, | |
4595 | struct return_value_word *lo) | |
7a292a7a SS |
4596 | { |
4597 | int len = TYPE_LENGTH (valtype); | |
c5aa993b | 4598 | |
7a292a7a SS |
4599 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT |
4600 | && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8)) | |
4601 | || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4))) | |
4602 | { | |
4603 | if (!FP_REGISTER_DOUBLE && len == 8) | |
4604 | { | |
4605 | /* We need to break a 64bit float in two 32 bit halves and | |
c5aa993b | 4606 | spread them across a floating-point register pair. */ |
d7449b42 AC |
4607 | lo->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
4608 | hi->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 0 : 4; | |
4609 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
56cea623 | 4610 | && register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) == 8) |
7a292a7a SS |
4611 | ? 4 : 0); |
4612 | hi->reg_offset = lo->reg_offset; | |
56cea623 AC |
4613 | lo->reg = mips_regnum (current_gdbarch)->fp0 + 0; |
4614 | hi->reg = mips_regnum (current_gdbarch)->fp0 + 1; | |
7a292a7a SS |
4615 | lo->len = 4; |
4616 | hi->len = 4; | |
4617 | } | |
4618 | else | |
4619 | { | |
4620 | /* The floating point value fits in a single floating-point | |
c5aa993b | 4621 | register. */ |
d7449b42 | 4622 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
56cea623 | 4623 | && register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) == 8 |
7a292a7a SS |
4624 | && len == 4) |
4625 | ? 4 : 0); | |
56cea623 | 4626 | lo->reg = mips_regnum (current_gdbarch)->fp0; |
7a292a7a SS |
4627 | lo->len = len; |
4628 | lo->buf_offset = 0; | |
4629 | hi->len = 0; | |
4630 | hi->reg_offset = 0; | |
4631 | hi->buf_offset = 0; | |
4632 | hi->reg = 0; | |
4633 | } | |
4634 | } | |
4635 | else | |
4636 | { | |
4637 | /* Locate a result possibly spread across two registers. */ | |
4638 | int regnum = 2; | |
4639 | lo->reg = regnum + 0; | |
4640 | hi->reg = regnum + 1; | |
d7449b42 | 4641 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
4642 | && len < MIPS_SAVED_REGSIZE) |
4643 | { | |
bf1f5b4c MS |
4644 | /* "un-left-justify" the value in the low register */ |
4645 | lo->reg_offset = MIPS_SAVED_REGSIZE - len; | |
bcb0cc15 | 4646 | lo->len = len; |
bf1f5b4c | 4647 | hi->reg_offset = 0; |
7a292a7a SS |
4648 | hi->len = 0; |
4649 | } | |
d7449b42 | 4650 | else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
4651 | && len > MIPS_SAVED_REGSIZE /* odd-size structs */ |
4652 | && len < MIPS_SAVED_REGSIZE * 2 | |
4653 | && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || | |
4654 | TYPE_CODE (valtype) == TYPE_CODE_UNION)) | |
4655 | { | |
4656 | /* "un-left-justify" the value spread across two registers. */ | |
4657 | lo->reg_offset = 2 * MIPS_SAVED_REGSIZE - len; | |
4658 | lo->len = MIPS_SAVED_REGSIZE - lo->reg_offset; | |
4659 | hi->reg_offset = 0; | |
4660 | hi->len = len - lo->len; | |
4661 | } | |
4662 | else | |
4663 | { | |
4664 | /* Only perform a partial copy of the second register. */ | |
4665 | lo->reg_offset = 0; | |
4666 | hi->reg_offset = 0; | |
4667 | if (len > MIPS_SAVED_REGSIZE) | |
4668 | { | |
4669 | lo->len = MIPS_SAVED_REGSIZE; | |
4670 | hi->len = len - MIPS_SAVED_REGSIZE; | |
4671 | } | |
4672 | else | |
4673 | { | |
4674 | lo->len = len; | |
4675 | hi->len = 0; | |
4676 | } | |
4677 | } | |
d7449b42 | 4678 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
719ec221 | 4679 | && register_size (current_gdbarch, regnum) == 8 |
7a292a7a SS |
4680 | && MIPS_SAVED_REGSIZE == 4) |
4681 | { | |
4682 | /* Account for the fact that only the least-signficant part | |
c5aa993b | 4683 | of the register is being used */ |
7a292a7a SS |
4684 | lo->reg_offset += 4; |
4685 | hi->reg_offset += 4; | |
4686 | } | |
4687 | lo->buf_offset = 0; | |
4688 | hi->buf_offset = lo->len; | |
4689 | } | |
4690 | } | |
4691 | ||
4692 | /* Given a return value in `regbuf' with a type `valtype', extract and | |
4693 | copy its value into `valbuf'. */ | |
4694 | ||
46cac009 AC |
4695 | static void |
4696 | mips_eabi_extract_return_value (struct type *valtype, | |
b8b527c5 | 4697 | char regbuf[], |
46cac009 AC |
4698 | char *valbuf) |
4699 | { | |
4700 | struct return_value_word lo; | |
4701 | struct return_value_word hi; | |
4702 | return_value_location (valtype, &hi, &lo); | |
4703 | ||
4704 | memcpy (valbuf + lo.buf_offset, | |
62700349 | 4705 | regbuf + DEPRECATED_REGISTER_BYTE (lo.reg) + lo.reg_offset, |
46cac009 AC |
4706 | lo.len); |
4707 | ||
4708 | if (hi.len > 0) | |
4709 | memcpy (valbuf + hi.buf_offset, | |
62700349 | 4710 | regbuf + DEPRECATED_REGISTER_BYTE (hi.reg) + hi.reg_offset, |
46cac009 AC |
4711 | hi.len); |
4712 | } | |
4713 | ||
46cac009 AC |
4714 | static void |
4715 | mips_o64_extract_return_value (struct type *valtype, | |
b8b527c5 | 4716 | char regbuf[], |
46cac009 AC |
4717 | char *valbuf) |
4718 | { | |
4719 | struct return_value_word lo; | |
4720 | struct return_value_word hi; | |
4721 | return_value_location (valtype, &hi, &lo); | |
4722 | ||
4723 | memcpy (valbuf + lo.buf_offset, | |
62700349 | 4724 | regbuf + DEPRECATED_REGISTER_BYTE (lo.reg) + lo.reg_offset, |
46cac009 AC |
4725 | lo.len); |
4726 | ||
4727 | if (hi.len > 0) | |
4728 | memcpy (valbuf + hi.buf_offset, | |
62700349 | 4729 | regbuf + DEPRECATED_REGISTER_BYTE (hi.reg) + hi.reg_offset, |
46cac009 AC |
4730 | hi.len); |
4731 | } | |
4732 | ||
7a292a7a SS |
4733 | /* Given a return value in `valbuf' with a type `valtype', write it's |
4734 | value into the appropriate register. */ | |
4735 | ||
46cac009 AC |
4736 | static void |
4737 | mips_eabi_store_return_value (struct type *valtype, char *valbuf) | |
4738 | { | |
d9d9c31f | 4739 | char raw_buffer[MAX_REGISTER_SIZE]; |
46cac009 AC |
4740 | struct return_value_word lo; |
4741 | struct return_value_word hi; | |
4742 | return_value_location (valtype, &hi, &lo); | |
4743 | ||
4744 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4745 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
62700349 | 4746 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg), raw_buffer, |
719ec221 | 4747 | register_size (current_gdbarch, lo.reg)); |
46cac009 AC |
4748 | |
4749 | if (hi.len > 0) | |
4750 | { | |
4751 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4752 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
62700349 | 4753 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg), raw_buffer, |
719ec221 | 4754 | register_size (current_gdbarch, hi.reg)); |
46cac009 AC |
4755 | } |
4756 | } | |
4757 | ||
4758 | static void | |
cb1d2653 | 4759 | mips_o64_store_return_value (struct type *valtype, char *valbuf) |
46cac009 | 4760 | { |
d9d9c31f | 4761 | char raw_buffer[MAX_REGISTER_SIZE]; |
46cac009 AC |
4762 | struct return_value_word lo; |
4763 | struct return_value_word hi; | |
4764 | return_value_location (valtype, &hi, &lo); | |
4765 | ||
4766 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4767 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
62700349 | 4768 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg), raw_buffer, |
719ec221 | 4769 | register_size (current_gdbarch, lo.reg)); |
46cac009 AC |
4770 | |
4771 | if (hi.len > 0) | |
4772 | { | |
4773 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4774 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
62700349 | 4775 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg), raw_buffer, |
719ec221 | 4776 | register_size (current_gdbarch, hi.reg)); |
46cac009 AC |
4777 | } |
4778 | } | |
4779 | ||
cb1d2653 AC |
4780 | /* O32 ABI stuff. */ |
4781 | ||
29dfb2ac AC |
4782 | static enum return_value_convention |
4783 | mips_o32_return_value (struct gdbarch *gdbarch, struct type *type, | |
4784 | struct regcache *regcache, | |
4785 | void *readbuf, const void *writebuf) | |
46cac009 | 4786 | { |
cb1d2653 | 4787 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
29dfb2ac AC |
4788 | |
4789 | if (TYPE_CODE (type)== TYPE_CODE_STRUCT | |
4790 | || TYPE_CODE (type)== TYPE_CODE_UNION | |
4791 | || TYPE_CODE (type)== TYPE_CODE_ARRAY) | |
4792 | return RETURN_VALUE_STRUCT_CONVENTION; | |
4793 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4794 | && TYPE_LENGTH (type) == 4 | |
4795 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
46cac009 | 4796 | { |
cb1d2653 AC |
4797 | /* A single-precision floating-point value. It fits in the |
4798 | least significant part of FP0. */ | |
4799 | if (mips_debug) | |
4800 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
29dfb2ac AC |
4801 | mips_xfer_register (regcache, |
4802 | NUM_REGS + mips_regnum (current_gdbarch)->fp0, | |
4803 | TYPE_LENGTH (type), | |
4804 | TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
4805 | return RETURN_VALUE_REGISTER_CONVENTION; | |
cb1d2653 AC |
4806 | } |
4807 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4808 | && TYPE_LENGTH (type) == 8 | |
4809 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4810 | { | |
a4b8ebc8 AC |
4811 | /* A double-precision floating-point value. The most |
4812 | significant part goes in FP1, and the least significant in | |
4813 | FP0. */ | |
cb1d2653 | 4814 | if (mips_debug) |
a4b8ebc8 | 4815 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); |
cb1d2653 AC |
4816 | switch (TARGET_BYTE_ORDER) |
4817 | { | |
4818 | case BFD_ENDIAN_LITTLE: | |
29dfb2ac AC |
4819 | mips_xfer_register (regcache, |
4820 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + 0, | |
4821 | 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
4822 | mips_xfer_register (regcache, | |
4823 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + 1, | |
4824 | 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4); | |
cb1d2653 AC |
4825 | break; |
4826 | case BFD_ENDIAN_BIG: | |
29dfb2ac AC |
4827 | mips_xfer_register (regcache, |
4828 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + 1, | |
4829 | 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
4830 | mips_xfer_register (regcache, | |
4831 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + 0, | |
4832 | 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4); | |
cb1d2653 AC |
4833 | break; |
4834 | default: | |
4835 | internal_error (__FILE__, __LINE__, "bad switch"); | |
4836 | } | |
29dfb2ac | 4837 | return RETURN_VALUE_REGISTER_CONVENTION; |
cb1d2653 AC |
4838 | } |
4839 | #if 0 | |
4840 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4841 | && TYPE_NFIELDS (type) <= 2 | |
4842 | && TYPE_NFIELDS (type) >= 1 | |
4843 | && ((TYPE_NFIELDS (type) == 1 | |
4844 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4845 | == TYPE_CODE_FLT)) | |
4846 | || (TYPE_NFIELDS (type) == 2 | |
4847 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4848 | == TYPE_CODE_FLT) | |
4849 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
4850 | == TYPE_CODE_FLT))) | |
4851 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4852 | { | |
4853 | /* A struct that contains one or two floats. Each value is part | |
4854 | in the least significant part of their floating point | |
4855 | register.. */ | |
d9d9c31f | 4856 | bfd_byte reg[MAX_REGISTER_SIZE]; |
cb1d2653 AC |
4857 | int regnum; |
4858 | int field; | |
56cea623 | 4859 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; |
cb1d2653 AC |
4860 | field < TYPE_NFIELDS (type); |
4861 | field++, regnum += 2) | |
4862 | { | |
4863 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
4864 | / TARGET_CHAR_BIT); | |
4865 | if (mips_debug) | |
4866 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", offset); | |
a4b8ebc8 AC |
4867 | mips_xfer_register (regcache, NUM_REGS + regnum, |
4868 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
29dfb2ac | 4869 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); |
cb1d2653 | 4870 | } |
29dfb2ac | 4871 | return RETURN_VALUE_REGISTER_CONVENTION; |
cb1d2653 AC |
4872 | } |
4873 | #endif | |
4874 | #if 0 | |
4875 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4876 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4877 | { | |
4878 | /* A structure or union. Extract the left justified value, | |
4879 | regardless of the byte order. I.e. DO NOT USE | |
4880 | mips_xfer_lower. */ | |
4881 | int offset; | |
4882 | int regnum; | |
4883 | for (offset = 0, regnum = V0_REGNUM; | |
4884 | offset < TYPE_LENGTH (type); | |
719ec221 | 4885 | offset += register_size (current_gdbarch, regnum), regnum++) |
cb1d2653 | 4886 | { |
719ec221 | 4887 | int xfer = register_size (current_gdbarch, regnum); |
cb1d2653 AC |
4888 | if (offset + xfer > TYPE_LENGTH (type)) |
4889 | xfer = TYPE_LENGTH (type) - offset; | |
4890 | if (mips_debug) | |
4891 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
4892 | offset, xfer, regnum); | |
a4b8ebc8 | 4893 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, |
29dfb2ac | 4894 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
cb1d2653 | 4895 | } |
29dfb2ac | 4896 | return RETURN_VALUE_REGISTER_CONVENTION; |
cb1d2653 AC |
4897 | } |
4898 | #endif | |
4899 | else | |
4900 | { | |
4901 | /* A scalar extract each part but least-significant-byte | |
4902 | justified. o32 thinks registers are 4 byte, regardless of | |
4903 | the ISA. mips_stack_argsize controls this. */ | |
4904 | int offset; | |
4905 | int regnum; | |
4906 | for (offset = 0, regnum = V0_REGNUM; | |
4907 | offset < TYPE_LENGTH (type); | |
4908 | offset += mips_stack_argsize (), regnum++) | |
4909 | { | |
4910 | int xfer = mips_stack_argsize (); | |
4911 | int pos = 0; | |
4912 | if (offset + xfer > TYPE_LENGTH (type)) | |
4913 | xfer = TYPE_LENGTH (type) - offset; | |
4914 | if (mips_debug) | |
4915 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4916 | offset, xfer, regnum); | |
a4b8ebc8 | 4917 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, |
29dfb2ac | 4918 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); |
cb1d2653 | 4919 | } |
29dfb2ac | 4920 | return RETURN_VALUE_REGISTER_CONVENTION; |
46cac009 AC |
4921 | } |
4922 | } | |
4923 | ||
cb1d2653 AC |
4924 | /* N32/N44 ABI stuff. */ |
4925 | ||
29dfb2ac AC |
4926 | static enum return_value_convention |
4927 | mips_n32n64_return_value (struct gdbarch *gdbarch, | |
4928 | struct type *type, struct regcache *regcache, | |
4929 | void *readbuf, const void *writebuf) | |
c906108c | 4930 | { |
88658117 | 4931 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
29dfb2ac AC |
4932 | if (TYPE_CODE (type)== TYPE_CODE_STRUCT |
4933 | || TYPE_CODE (type)== TYPE_CODE_UNION | |
4934 | || TYPE_CODE (type)== TYPE_CODE_ARRAY | |
4935 | || TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE) | |
4936 | return RETURN_VALUE_STRUCT_CONVENTION; | |
4937 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4938 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
7a292a7a | 4939 | { |
88658117 AC |
4940 | /* A floating-point value belongs in the least significant part |
4941 | of FP0. */ | |
4942 | if (mips_debug) | |
4943 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
29dfb2ac AC |
4944 | mips_xfer_register (regcache, |
4945 | NUM_REGS + mips_regnum (current_gdbarch)->fp0, | |
4946 | TYPE_LENGTH (type), | |
4947 | TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
4948 | return RETURN_VALUE_REGISTER_CONVENTION; | |
88658117 AC |
4949 | } |
4950 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4951 | && TYPE_NFIELDS (type) <= 2 | |
4952 | && TYPE_NFIELDS (type) >= 1 | |
4953 | && ((TYPE_NFIELDS (type) == 1 | |
4954 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4955 | == TYPE_CODE_FLT)) | |
4956 | || (TYPE_NFIELDS (type) == 2 | |
4957 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4958 | == TYPE_CODE_FLT) | |
4959 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
4960 | == TYPE_CODE_FLT))) | |
4961 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4962 | { | |
4963 | /* A struct that contains one or two floats. Each value is part | |
4964 | in the least significant part of their floating point | |
4965 | register.. */ | |
d9d9c31f | 4966 | bfd_byte reg[MAX_REGISTER_SIZE]; |
88658117 AC |
4967 | int regnum; |
4968 | int field; | |
56cea623 | 4969 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; |
88658117 AC |
4970 | field < TYPE_NFIELDS (type); |
4971 | field++, regnum += 2) | |
4972 | { | |
4973 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
4974 | / TARGET_CHAR_BIT); | |
4975 | if (mips_debug) | |
4976 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", offset); | |
a4b8ebc8 AC |
4977 | mips_xfer_register (regcache, NUM_REGS + regnum, |
4978 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
29dfb2ac | 4979 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); |
88658117 | 4980 | } |
29dfb2ac | 4981 | return RETURN_VALUE_REGISTER_CONVENTION; |
7a292a7a | 4982 | } |
88658117 AC |
4983 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
4984 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4985 | { | |
4986 | /* A structure or union. Extract the left justified value, | |
4987 | regardless of the byte order. I.e. DO NOT USE | |
4988 | mips_xfer_lower. */ | |
4989 | int offset; | |
4990 | int regnum; | |
4991 | for (offset = 0, regnum = V0_REGNUM; | |
4992 | offset < TYPE_LENGTH (type); | |
719ec221 | 4993 | offset += register_size (current_gdbarch, regnum), regnum++) |
88658117 | 4994 | { |
719ec221 | 4995 | int xfer = register_size (current_gdbarch, regnum); |
88658117 AC |
4996 | if (offset + xfer > TYPE_LENGTH (type)) |
4997 | xfer = TYPE_LENGTH (type) - offset; | |
4998 | if (mips_debug) | |
4999 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
5000 | offset, xfer, regnum); | |
a4b8ebc8 | 5001 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, |
29dfb2ac | 5002 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
88658117 | 5003 | } |
29dfb2ac | 5004 | return RETURN_VALUE_REGISTER_CONVENTION; |
88658117 AC |
5005 | } |
5006 | else | |
5007 | { | |
5008 | /* A scalar extract each part but least-significant-byte | |
5009 | justified. */ | |
5010 | int offset; | |
5011 | int regnum; | |
5012 | for (offset = 0, regnum = V0_REGNUM; | |
5013 | offset < TYPE_LENGTH (type); | |
719ec221 | 5014 | offset += register_size (current_gdbarch, regnum), regnum++) |
88658117 | 5015 | { |
719ec221 | 5016 | int xfer = register_size (current_gdbarch, regnum); |
88658117 AC |
5017 | int pos = 0; |
5018 | if (offset + xfer > TYPE_LENGTH (type)) | |
5019 | xfer = TYPE_LENGTH (type) - offset; | |
5020 | if (mips_debug) | |
5021 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
5022 | offset, xfer, regnum); | |
a4b8ebc8 | 5023 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, |
29dfb2ac | 5024 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); |
88658117 | 5025 | } |
29dfb2ac | 5026 | return RETURN_VALUE_REGISTER_CONVENTION; |
88658117 AC |
5027 | } |
5028 | } | |
5029 | ||
2f1488ce | 5030 | static CORE_ADDR |
6672060b | 5031 | mips_extract_struct_value_address (struct regcache *regcache) |
2f1488ce MS |
5032 | { |
5033 | /* FIXME: This will only work at random. The caller passes the | |
5034 | struct_return address in V0, but it is not preserved. It may | |
5035 | still be there, or this may be a random value. */ | |
77d8f2b4 MS |
5036 | LONGEST val; |
5037 | ||
5038 | regcache_cooked_read_signed (regcache, V0_REGNUM, &val); | |
6672060b | 5039 | return val; |
2f1488ce MS |
5040 | } |
5041 | ||
c906108c SS |
5042 | /* Exported procedure: Is PC in the signal trampoline code */ |
5043 | ||
102182a9 MS |
5044 | static int |
5045 | mips_pc_in_sigtramp (CORE_ADDR pc, char *ignore) | |
c906108c SS |
5046 | { |
5047 | if (sigtramp_address == 0) | |
5048 | fixup_sigtramp (); | |
5049 | return (pc >= sigtramp_address && pc < sigtramp_end); | |
5050 | } | |
5051 | ||
a5ea2558 AC |
5052 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
5053 | used for all MIPS-specific commands. */ | |
5054 | ||
a5ea2558 | 5055 | static void |
acdb74a0 | 5056 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
5057 | { |
5058 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
5059 | } | |
5060 | ||
a5ea2558 | 5061 | static void |
acdb74a0 | 5062 | set_mips_command (char *args, int from_tty) |
a5ea2558 AC |
5063 | { |
5064 | printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
5065 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); | |
5066 | } | |
5067 | ||
c906108c SS |
5068 | /* Commands to show/set the MIPS FPU type. */ |
5069 | ||
c906108c | 5070 | static void |
acdb74a0 | 5071 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 5072 | { |
c906108c SS |
5073 | char *fpu; |
5074 | switch (MIPS_FPU_TYPE) | |
5075 | { | |
5076 | case MIPS_FPU_SINGLE: | |
5077 | fpu = "single-precision"; | |
5078 | break; | |
5079 | case MIPS_FPU_DOUBLE: | |
5080 | fpu = "double-precision"; | |
5081 | break; | |
5082 | case MIPS_FPU_NONE: | |
5083 | fpu = "absent (none)"; | |
5084 | break; | |
93d56215 AC |
5085 | default: |
5086 | internal_error (__FILE__, __LINE__, "bad switch"); | |
c906108c SS |
5087 | } |
5088 | if (mips_fpu_type_auto) | |
5089 | printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
5090 | fpu); | |
5091 | else | |
5092 | printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n", | |
5093 | fpu); | |
5094 | } | |
5095 | ||
5096 | ||
c906108c | 5097 | static void |
acdb74a0 | 5098 | set_mipsfpu_command (char *args, int from_tty) |
c906108c SS |
5099 | { |
5100 | printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
5101 | show_mipsfpu_command (args, from_tty); | |
5102 | } | |
5103 | ||
c906108c | 5104 | static void |
acdb74a0 | 5105 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c SS |
5106 | { |
5107 | mips_fpu_type = MIPS_FPU_SINGLE; | |
5108 | mips_fpu_type_auto = 0; | |
9e364162 | 5109 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_SINGLE; |
c906108c SS |
5110 | } |
5111 | ||
c906108c | 5112 | static void |
acdb74a0 | 5113 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c SS |
5114 | { |
5115 | mips_fpu_type = MIPS_FPU_DOUBLE; | |
5116 | mips_fpu_type_auto = 0; | |
9e364162 | 5117 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_DOUBLE; |
c906108c SS |
5118 | } |
5119 | ||
c906108c | 5120 | static void |
acdb74a0 | 5121 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c SS |
5122 | { |
5123 | mips_fpu_type = MIPS_FPU_NONE; | |
5124 | mips_fpu_type_auto = 0; | |
9e364162 | 5125 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_NONE; |
c906108c SS |
5126 | } |
5127 | ||
c906108c | 5128 | static void |
acdb74a0 | 5129 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
5130 | { |
5131 | mips_fpu_type_auto = 1; | |
5132 | } | |
5133 | ||
c906108c | 5134 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
5135 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
5136 | the relevant processor still exists (it dates back to '94) and | |
5137 | secondly this is not the way to do this. The processor type should | |
5138 | be set by forcing an architecture change. */ | |
c906108c | 5139 | |
691c0433 AC |
5140 | void |
5141 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 5142 | { |
691c0433 | 5143 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
5144 | CORE_ADDR prid; |
5145 | ||
5146 | prid = read_register (PRID_REGNUM); | |
5147 | ||
5148 | if ((prid & ~0xf) == 0x700) | |
691c0433 | 5149 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
5150 | } |
5151 | ||
5152 | /* Just like reinit_frame_cache, but with the right arguments to be | |
5153 | callable as an sfunc. */ | |
5154 | ||
5155 | static void | |
acdb74a0 AC |
5156 | reinit_frame_cache_sfunc (char *args, int from_tty, |
5157 | struct cmd_list_element *c) | |
c906108c SS |
5158 | { |
5159 | reinit_frame_cache (); | |
5160 | } | |
5161 | ||
a89aa300 AC |
5162 | static int |
5163 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 5164 | { |
e5ab0dce | 5165 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
5166 | mips_extra_func_info_t proc_desc; |
5167 | ||
5168 | /* Search for the function containing this address. Set the low bit | |
5169 | of the address when searching, in case we were given an even address | |
5170 | that is the start of a 16-bit function. If we didn't do this, | |
5171 | the search would fail because the symbol table says the function | |
5172 | starts at an odd address, i.e. 1 byte past the given address. */ | |
5173 | memaddr = ADDR_BITS_REMOVE (memaddr); | |
95404a3e | 5174 | proc_desc = non_heuristic_proc_desc (make_mips16_addr (memaddr), NULL); |
c906108c SS |
5175 | |
5176 | /* Make an attempt to determine if this is a 16-bit function. If | |
5177 | the procedure descriptor exists and the address therein is odd, | |
5178 | it's definitely a 16-bit function. Otherwise, we have to just | |
5179 | guess that if the address passed in is odd, it's 16-bits. */ | |
d31431ed AC |
5180 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
5181 | disassembler needs to be able to locally determine the ISA, and | |
5182 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
5183 | work. */ | |
c906108c | 5184 | if (proc_desc) |
d31431ed AC |
5185 | { |
5186 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) | |
5187 | info->mach = bfd_mach_mips16; | |
5188 | } | |
c906108c | 5189 | else |
d31431ed AC |
5190 | { |
5191 | if (pc_is_mips16 (memaddr)) | |
5192 | info->mach = bfd_mach_mips16; | |
5193 | } | |
c906108c SS |
5194 | |
5195 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 5196 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 5197 | |
e5ab0dce AC |
5198 | /* Set the disassembler options. */ |
5199 | if (tdep->mips_abi == MIPS_ABI_N32 | |
5200 | || tdep->mips_abi == MIPS_ABI_N64) | |
5201 | { | |
5202 | /* Set up the disassembler info, so that we get the right | |
5203 | register names from libopcodes. */ | |
5204 | if (tdep->mips_abi == MIPS_ABI_N32) | |
5205 | info->disassembler_options = "gpr-names=n32"; | |
5206 | else | |
5207 | info->disassembler_options = "gpr-names=64"; | |
5208 | info->flavour = bfd_target_elf_flavour; | |
5209 | } | |
5210 | else | |
5211 | /* This string is not recognized explicitly by the disassembler, | |
5212 | but it tells the disassembler to not try to guess the ABI from | |
5213 | the bfd elf headers, such that, if the user overrides the ABI | |
5214 | of a program linked as NewABI, the disassembly will follow the | |
5215 | register naming conventions specified by the user. */ | |
5216 | info->disassembler_options = "gpr-names=32"; | |
5217 | ||
c906108c | 5218 | /* Call the appropriate disassembler based on the target endian-ness. */ |
d7449b42 | 5219 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
5220 | return print_insn_big_mips (memaddr, info); |
5221 | else | |
5222 | return print_insn_little_mips (memaddr, info); | |
5223 | } | |
5224 | ||
c906108c SS |
5225 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program |
5226 | counter value to determine whether a 16- or 32-bit breakpoint should be | |
5227 | used. It returns a pointer to a string of bytes that encode a breakpoint | |
5228 | instruction, stores the length of the string to *lenptr, and adjusts pc | |
5229 | (if necessary) to point to the actual memory location where the | |
5230 | breakpoint should be inserted. */ | |
5231 | ||
f7ab6ec6 | 5232 | static const unsigned char * |
acdb74a0 | 5233 | mips_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr) |
c906108c | 5234 | { |
d7449b42 | 5235 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
5236 | { |
5237 | if (pc_is_mips16 (*pcptr)) | |
5238 | { | |
aaab4dba | 5239 | static unsigned char mips16_big_breakpoint[] = {0xe8, 0xa5}; |
95404a3e | 5240 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5241 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
5242 | return mips16_big_breakpoint; |
5243 | } | |
5244 | else | |
5245 | { | |
aaab4dba AC |
5246 | /* The IDT board uses an unusual breakpoint value, and |
5247 | sometimes gets confused when it sees the usual MIPS | |
5248 | breakpoint instruction. */ | |
5249 | static unsigned char big_breakpoint[] = {0, 0x5, 0, 0xd}; | |
5250 | static unsigned char pmon_big_breakpoint[] = {0, 0, 0, 0xd}; | |
5251 | static unsigned char idt_big_breakpoint[] = {0, 0, 0x0a, 0xd}; | |
c906108c | 5252 | |
c5aa993b | 5253 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
5254 | |
5255 | if (strcmp (target_shortname, "mips") == 0) | |
5256 | return idt_big_breakpoint; | |
5257 | else if (strcmp (target_shortname, "ddb") == 0 | |
5258 | || strcmp (target_shortname, "pmon") == 0 | |
5259 | || strcmp (target_shortname, "lsi") == 0) | |
5260 | return pmon_big_breakpoint; | |
5261 | else | |
5262 | return big_breakpoint; | |
5263 | } | |
5264 | } | |
5265 | else | |
5266 | { | |
5267 | if (pc_is_mips16 (*pcptr)) | |
5268 | { | |
aaab4dba | 5269 | static unsigned char mips16_little_breakpoint[] = {0xa5, 0xe8}; |
95404a3e | 5270 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5271 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
5272 | return mips16_little_breakpoint; |
5273 | } | |
5274 | else | |
5275 | { | |
aaab4dba AC |
5276 | static unsigned char little_breakpoint[] = {0xd, 0, 0x5, 0}; |
5277 | static unsigned char pmon_little_breakpoint[] = {0xd, 0, 0, 0}; | |
5278 | static unsigned char idt_little_breakpoint[] = {0xd, 0x0a, 0, 0}; | |
c906108c | 5279 | |
c5aa993b | 5280 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
5281 | |
5282 | if (strcmp (target_shortname, "mips") == 0) | |
5283 | return idt_little_breakpoint; | |
5284 | else if (strcmp (target_shortname, "ddb") == 0 | |
5285 | || strcmp (target_shortname, "pmon") == 0 | |
5286 | || strcmp (target_shortname, "lsi") == 0) | |
5287 | return pmon_little_breakpoint; | |
5288 | else | |
5289 | return little_breakpoint; | |
5290 | } | |
5291 | } | |
5292 | } | |
5293 | ||
5294 | /* If PC is in a mips16 call or return stub, return the address of the target | |
5295 | PC, which is either the callee or the caller. There are several | |
5296 | cases which must be handled: | |
5297 | ||
5298 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 5299 | target PC is in $31 ($ra). |
c906108c | 5300 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 5301 | and the target PC is in $2. |
c906108c | 5302 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
5303 | before the jal instruction, this is effectively a call stub |
5304 | and the the target PC is in $2. Otherwise this is effectively | |
5305 | a return stub and the target PC is in $18. | |
c906108c SS |
5306 | |
5307 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
5308 | gory details. | |
5309 | ||
5310 | This function implements the SKIP_TRAMPOLINE_CODE macro. | |
c5aa993b | 5311 | */ |
c906108c | 5312 | |
757a7cc6 | 5313 | static CORE_ADDR |
acdb74a0 | 5314 | mips_skip_stub (CORE_ADDR pc) |
c906108c SS |
5315 | { |
5316 | char *name; | |
5317 | CORE_ADDR start_addr; | |
5318 | ||
5319 | /* Find the starting address and name of the function containing the PC. */ | |
5320 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
5321 | return 0; | |
5322 | ||
5323 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
5324 | target PC is in $31 ($ra). */ | |
5325 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5326 | || strcmp (name, "__mips16_ret_df") == 0) | |
6c997a34 | 5327 | return read_signed_register (RA_REGNUM); |
c906108c SS |
5328 | |
5329 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5330 | { | |
5331 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
5332 | and the target PC is in $2. */ | |
5333 | if (name[19] >= '0' && name[19] <= '9') | |
6c997a34 | 5334 | return read_signed_register (2); |
c906108c SS |
5335 | |
5336 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
5337 | before the jal instruction, this is effectively a call stub |
5338 | and the the target PC is in $2. Otherwise this is effectively | |
5339 | a return stub and the target PC is in $18. */ | |
c906108c SS |
5340 | else if (name[19] == 's' || name[19] == 'd') |
5341 | { | |
5342 | if (pc == start_addr) | |
5343 | { | |
5344 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
5345 | stub. Such a stub for a function bar might have a name |
5346 | like __fn_stub_bar, and might look like this: | |
5347 | mfc1 $4,$f13 | |
5348 | mfc1 $5,$f12 | |
5349 | mfc1 $6,$f15 | |
5350 | mfc1 $7,$f14 | |
5351 | la $1,bar (becomes a lui/addiu pair) | |
5352 | jr $1 | |
5353 | So scan down to the lui/addi and extract the target | |
5354 | address from those two instructions. */ | |
c906108c | 5355 | |
6c997a34 | 5356 | CORE_ADDR target_pc = read_signed_register (2); |
c906108c SS |
5357 | t_inst inst; |
5358 | int i; | |
5359 | ||
5360 | /* See if the name of the target function is __fn_stub_*. */ | |
5361 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == 0) | |
5362 | return target_pc; | |
5363 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
5364 | && strcmp (name, "etext") != 0 | |
5365 | && strcmp (name, "_etext") != 0) | |
5366 | return target_pc; | |
5367 | ||
5368 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
5369 | The limit on the search is arbitrarily set to 20 |
5370 | instructions. FIXME. */ | |
c906108c SS |
5371 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN) |
5372 | { | |
c5aa993b JM |
5373 | inst = mips_fetch_instruction (target_pc); |
5374 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
5375 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
5376 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
5377 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
5378 | } |
5379 | ||
5380 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
5381 | return target_pc; | |
5382 | } | |
5383 | else | |
5384 | /* This is the 'return' part of a call stub. The return | |
5385 | address is in $r18. */ | |
6c997a34 | 5386 | return read_signed_register (18); |
c906108c SS |
5387 | } |
5388 | } | |
c5aa993b | 5389 | return 0; /* not a stub */ |
c906108c SS |
5390 | } |
5391 | ||
5392 | ||
5393 | /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline). | |
5394 | This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */ | |
5395 | ||
757a7cc6 | 5396 | static int |
acdb74a0 | 5397 | mips_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
5398 | { |
5399 | CORE_ADDR start_addr; | |
5400 | ||
5401 | /* Find the starting address of the function containing the PC. If the | |
5402 | caller didn't give us a name, look it up at the same time. */ | |
5403 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0) | |
5404 | return 0; | |
5405 | ||
5406 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5407 | { | |
5408 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */ | |
5409 | if (name[19] >= '0' && name[19] <= '9') | |
5410 | return 1; | |
5411 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b | 5412 | before the jal instruction, this is effectively a call stub. */ |
c906108c SS |
5413 | else if (name[19] == 's' || name[19] == 'd') |
5414 | return pc == start_addr; | |
5415 | } | |
5416 | ||
c5aa993b | 5417 | return 0; /* not a stub */ |
c906108c SS |
5418 | } |
5419 | ||
5420 | ||
5421 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
5422 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
5423 | ||
e41b17f0 | 5424 | static int |
acdb74a0 | 5425 | mips_in_return_stub (CORE_ADDR pc, char *name) |
c906108c SS |
5426 | { |
5427 | CORE_ADDR start_addr; | |
5428 | ||
5429 | /* Find the starting address of the function containing the PC. */ | |
5430 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
5431 | return 0; | |
5432 | ||
5433 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */ | |
5434 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5435 | || strcmp (name, "__mips16_ret_df") == 0) | |
5436 | return 1; | |
5437 | ||
5438 | /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start, | |
c5aa993b | 5439 | i.e. after the jal instruction, this is effectively a return stub. */ |
c906108c SS |
5440 | if (strncmp (name, "__mips16_call_stub_", 19) == 0 |
5441 | && (name[19] == 's' || name[19] == 'd') | |
5442 | && pc != start_addr) | |
5443 | return 1; | |
5444 | ||
c5aa993b | 5445 | return 0; /* not a stub */ |
c906108c SS |
5446 | } |
5447 | ||
5448 | ||
5449 | /* Return non-zero if the PC is in a library helper function that should | |
5450 | be ignored. This implements the IGNORE_HELPER_CALL macro. */ | |
5451 | ||
5452 | int | |
acdb74a0 | 5453 | mips_ignore_helper (CORE_ADDR pc) |
c906108c SS |
5454 | { |
5455 | char *name; | |
5456 | ||
5457 | /* Find the starting address and name of the function containing the PC. */ | |
5458 | if (find_pc_partial_function (pc, &name, NULL, NULL) == 0) | |
5459 | return 0; | |
5460 | ||
5461 | /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function | |
5462 | that we want to ignore. */ | |
5463 | return (strcmp (name, "__mips16_ret_sf") == 0 | |
5464 | || strcmp (name, "__mips16_ret_df") == 0); | |
5465 | } | |
5466 | ||
5467 | ||
47a8d4ba AC |
5468 | /* When debugging a 64 MIPS target running a 32 bit ABI, the size of |
5469 | the register stored on the stack (32) is different to its real raw | |
5470 | size (64). The below ensures that registers are fetched from the | |
5471 | stack using their ABI size and then stored into the RAW_BUFFER | |
5472 | using their raw size. | |
5473 | ||
5474 | The alternative to adding this function would be to add an ABI | |
5475 | macro - REGISTER_STACK_SIZE(). */ | |
5476 | ||
5477 | static void | |
acdb74a0 | 5478 | mips_get_saved_register (char *raw_buffer, |
795e1e11 | 5479 | int *optimizedp, |
acdb74a0 AC |
5480 | CORE_ADDR *addrp, |
5481 | struct frame_info *frame, | |
5482 | int regnum, | |
795e1e11 | 5483 | enum lval_type *lvalp) |
47a8d4ba | 5484 | { |
795e1e11 AC |
5485 | CORE_ADDR addrx; |
5486 | enum lval_type lvalx; | |
5487 | int optimizedx; | |
6e51443a | 5488 | int realnumx; |
47a8d4ba | 5489 | |
a4b8ebc8 AC |
5490 | /* Always a pseudo. */ |
5491 | gdb_assert (regnum >= NUM_REGS); | |
47a8d4ba | 5492 | |
795e1e11 AC |
5493 | /* Make certain that all needed parameters are present. */ |
5494 | if (addrp == NULL) | |
5495 | addrp = &addrx; | |
5496 | if (lvalp == NULL) | |
5497 | lvalp = &lvalx; | |
5498 | if (optimizedp == NULL) | |
5499 | optimizedp = &optimizedx; | |
a4b8ebc8 AC |
5500 | |
5501 | if ((regnum % NUM_REGS) == SP_REGNUM) | |
5502 | /* The SP_REGNUM is special, its value is stored in saved_regs. | |
5503 | In fact, it is so special that it can even only be fetched | |
5504 | using a raw register number! Once this code as been converted | |
5505 | to frame-unwind the problem goes away. */ | |
5506 | frame_register_unwind (deprecated_get_next_frame_hack (frame), | |
5507 | regnum % NUM_REGS, optimizedp, lvalp, addrp, | |
5508 | &realnumx, raw_buffer); | |
5509 | else | |
5510 | /* Get it from the next frame. */ | |
5511 | frame_register_unwind (deprecated_get_next_frame_hack (frame), | |
5512 | regnum, optimizedp, lvalp, addrp, | |
5513 | &realnumx, raw_buffer); | |
47a8d4ba | 5514 | } |
2acceee2 | 5515 | |
f7b9e9fc AC |
5516 | /* Immediately after a function call, return the saved pc. |
5517 | Can't always go through the frames for this because on some machines | |
5518 | the new frame is not set up until the new function executes | |
5519 | some instructions. */ | |
5520 | ||
5521 | static CORE_ADDR | |
5522 | mips_saved_pc_after_call (struct frame_info *frame) | |
5523 | { | |
6c997a34 | 5524 | return read_signed_register (RA_REGNUM); |
f7b9e9fc AC |
5525 | } |
5526 | ||
5527 | ||
a4b8ebc8 AC |
5528 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
5529 | [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */ | |
88c72b7d AC |
5530 | |
5531 | static int | |
5532 | mips_stab_reg_to_regnum (int num) | |
5533 | { | |
a4b8ebc8 | 5534 | int regnum; |
2f38ef89 | 5535 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5536 | regnum = num; |
2f38ef89 | 5537 | else if (num >= 38 && num < 70) |
56cea623 | 5538 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 38; |
040b99fd | 5539 | else if (num == 70) |
56cea623 | 5540 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 5541 | else if (num == 71) |
56cea623 | 5542 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 5543 | else |
a4b8ebc8 AC |
5544 | /* This will hopefully (eventually) provoke a warning. Should |
5545 | we be calling complaint() here? */ | |
5546 | return NUM_REGS + NUM_PSEUDO_REGS; | |
5547 | return NUM_REGS + regnum; | |
88c72b7d AC |
5548 | } |
5549 | ||
2f38ef89 | 5550 | |
a4b8ebc8 AC |
5551 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
5552 | NUM_REGS .. 2 * NUM_REGS) REGNUM. */ | |
88c72b7d AC |
5553 | |
5554 | static int | |
2f38ef89 | 5555 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num) |
88c72b7d | 5556 | { |
a4b8ebc8 | 5557 | int regnum; |
2f38ef89 | 5558 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5559 | regnum = num; |
2f38ef89 | 5560 | else if (num >= 32 && num < 64) |
56cea623 | 5561 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 32; |
040b99fd | 5562 | else if (num == 64) |
56cea623 | 5563 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 5564 | else if (num == 65) |
56cea623 | 5565 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 5566 | else |
a4b8ebc8 AC |
5567 | /* This will hopefully (eventually) provoke a warning. Should we |
5568 | be calling complaint() here? */ | |
5569 | return NUM_REGS + NUM_PSEUDO_REGS; | |
5570 | return NUM_REGS + regnum; | |
5571 | } | |
5572 | ||
5573 | static int | |
5574 | mips_register_sim_regno (int regnum) | |
5575 | { | |
5576 | /* Only makes sense to supply raw registers. */ | |
5577 | gdb_assert (regnum >= 0 && regnum < NUM_REGS); | |
5578 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to | |
5579 | decide if it is valid. Should instead define a standard sim/gdb | |
5580 | register numbering scheme. */ | |
5581 | if (REGISTER_NAME (NUM_REGS + regnum) != NULL | |
5582 | && REGISTER_NAME (NUM_REGS + regnum)[0] != '\0') | |
5583 | return regnum; | |
5584 | else | |
5585 | return LEGACY_SIM_REGNO_IGNORE; | |
88c72b7d AC |
5586 | } |
5587 | ||
2f38ef89 | 5588 | |
fc0c74b1 AC |
5589 | /* Convert an integer into an address. By first converting the value |
5590 | into a pointer and then extracting it signed, the address is | |
5591 | guarenteed to be correctly sign extended. */ | |
5592 | ||
5593 | static CORE_ADDR | |
5594 | mips_integer_to_address (struct type *type, void *buf) | |
5595 | { | |
5596 | char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5597 | LONGEST val = unpack_long (type, buf); | |
5598 | store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val); | |
5599 | return extract_signed_integer (tmp, | |
5600 | TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5601 | } | |
5602 | ||
caaa3122 DJ |
5603 | static void |
5604 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
5605 | { | |
5606 | enum mips_abi *abip = (enum mips_abi *) obj; | |
5607 | const char *name = bfd_get_section_name (abfd, sect); | |
5608 | ||
5609 | if (*abip != MIPS_ABI_UNKNOWN) | |
5610 | return; | |
5611 | ||
5612 | if (strncmp (name, ".mdebug.", 8) != 0) | |
5613 | return; | |
5614 | ||
5615 | if (strcmp (name, ".mdebug.abi32") == 0) | |
5616 | *abip = MIPS_ABI_O32; | |
5617 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
5618 | *abip = MIPS_ABI_N32; | |
62a49b2c | 5619 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 5620 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
5621 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
5622 | *abip = MIPS_ABI_O64; | |
5623 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
5624 | *abip = MIPS_ABI_EABI32; | |
5625 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
5626 | *abip = MIPS_ABI_EABI64; | |
5627 | else | |
5628 | warning ("unsupported ABI %s.", name + 8); | |
5629 | } | |
5630 | ||
2e4ebe70 DJ |
5631 | static enum mips_abi |
5632 | global_mips_abi (void) | |
5633 | { | |
5634 | int i; | |
5635 | ||
5636 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
5637 | if (mips_abi_strings[i] == mips_abi_string) | |
5638 | return (enum mips_abi) i; | |
5639 | ||
5640 | internal_error (__FILE__, __LINE__, | |
5641 | "unknown ABI string"); | |
5642 | } | |
5643 | ||
c2d11a7d | 5644 | static struct gdbarch * |
acdb74a0 AC |
5645 | mips_gdbarch_init (struct gdbarch_info info, |
5646 | struct gdbarch_list *arches) | |
c2d11a7d | 5647 | { |
c2d11a7d JM |
5648 | struct gdbarch *gdbarch; |
5649 | struct gdbarch_tdep *tdep; | |
5650 | int elf_flags; | |
2e4ebe70 | 5651 | enum mips_abi mips_abi, found_abi, wanted_abi; |
a4b8ebc8 | 5652 | int num_regs; |
c2d11a7d | 5653 | |
70f80edf JT |
5654 | elf_flags = 0; |
5655 | ||
5656 | if (info.abfd) | |
5657 | { | |
5658 | /* First of all, extract the elf_flags, if available. */ | |
5659 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5660 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
70f80edf | 5661 | } |
c2d11a7d | 5662 | |
102182a9 | 5663 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
5664 | switch ((elf_flags & EF_MIPS_ABI)) |
5665 | { | |
5666 | case E_MIPS_ABI_O32: | |
5667 | mips_abi = MIPS_ABI_O32; | |
5668 | break; | |
5669 | case E_MIPS_ABI_O64: | |
5670 | mips_abi = MIPS_ABI_O64; | |
5671 | break; | |
5672 | case E_MIPS_ABI_EABI32: | |
5673 | mips_abi = MIPS_ABI_EABI32; | |
5674 | break; | |
5675 | case E_MIPS_ABI_EABI64: | |
4a7f7ba8 | 5676 | mips_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
5677 | break; |
5678 | default: | |
acdb74a0 AC |
5679 | if ((elf_flags & EF_MIPS_ABI2)) |
5680 | mips_abi = MIPS_ABI_N32; | |
5681 | else | |
5682 | mips_abi = MIPS_ABI_UNKNOWN; | |
0dadbba0 AC |
5683 | break; |
5684 | } | |
acdb74a0 | 5685 | |
caaa3122 DJ |
5686 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
5687 | if (mips_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) | |
5688 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &mips_abi); | |
5689 | ||
2e4ebe70 DJ |
5690 | /* If we have no bfd, then mips_abi will still be MIPS_ABI_UNKNOWN. |
5691 | Use the ABI from the last architecture if there is one. */ | |
5692 | if (info.abfd == NULL && arches != NULL) | |
5693 | mips_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
5694 | ||
32a6503c | 5695 | /* Try the architecture for any hint of the correct ABI. */ |
bf64bfd6 AC |
5696 | if (mips_abi == MIPS_ABI_UNKNOWN |
5697 | && info.bfd_arch_info != NULL | |
5698 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5699 | { | |
5700 | switch (info.bfd_arch_info->mach) | |
5701 | { | |
5702 | case bfd_mach_mips3900: | |
5703 | mips_abi = MIPS_ABI_EABI32; | |
5704 | break; | |
5705 | case bfd_mach_mips4100: | |
5706 | case bfd_mach_mips5000: | |
5707 | mips_abi = MIPS_ABI_EABI64; | |
5708 | break; | |
1d06468c EZ |
5709 | case bfd_mach_mips8000: |
5710 | case bfd_mach_mips10000: | |
32a6503c KB |
5711 | /* On Irix, ELF64 executables use the N64 ABI. The |
5712 | pseudo-sections which describe the ABI aren't present | |
5713 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
5714 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
5715 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
5716 | mips_abi = MIPS_ABI_N64; | |
5717 | else | |
5718 | mips_abi = MIPS_ABI_N32; | |
1d06468c | 5719 | break; |
bf64bfd6 AC |
5720 | } |
5721 | } | |
2e4ebe70 | 5722 | |
2e4ebe70 DJ |
5723 | if (mips_abi == MIPS_ABI_UNKNOWN) |
5724 | mips_abi = MIPS_ABI_O32; | |
5725 | ||
5726 | /* Now that we have found what the ABI for this binary would be, | |
5727 | check whether the user is overriding it. */ | |
5728 | found_abi = mips_abi; | |
5729 | wanted_abi = global_mips_abi (); | |
5730 | if (wanted_abi != MIPS_ABI_UNKNOWN) | |
5731 | mips_abi = wanted_abi; | |
5732 | ||
4b9b3959 AC |
5733 | if (gdbarch_debug) |
5734 | { | |
5735 | fprintf_unfiltered (gdb_stdlog, | |
9ace0497 | 5736 | "mips_gdbarch_init: elf_flags = 0x%08x\n", |
4b9b3959 | 5737 | elf_flags); |
4b9b3959 AC |
5738 | fprintf_unfiltered (gdb_stdlog, |
5739 | "mips_gdbarch_init: mips_abi = %d\n", | |
5740 | mips_abi); | |
2e4ebe70 DJ |
5741 | fprintf_unfiltered (gdb_stdlog, |
5742 | "mips_gdbarch_init: found_mips_abi = %d\n", | |
5743 | found_abi); | |
4b9b3959 | 5744 | } |
0dadbba0 | 5745 | |
c2d11a7d JM |
5746 | /* try to find a pre-existing architecture */ |
5747 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
5748 | arches != NULL; | |
5749 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
5750 | { | |
5751 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 5752 | using. */ |
9103eae0 | 5753 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 5754 | continue; |
9103eae0 | 5755 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 5756 | continue; |
719ec221 AC |
5757 | /* Need to be pedantic about which register virtual size is |
5758 | used. */ | |
5759 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
5760 | != mips64_transfers_32bit_regs_p) | |
5761 | continue; | |
4be87837 | 5762 | return arches->gdbarch; |
c2d11a7d JM |
5763 | } |
5764 | ||
102182a9 | 5765 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
5766 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
5767 | gdbarch = gdbarch_alloc (&info, tdep); | |
5768 | tdep->elf_flags = elf_flags; | |
719ec221 | 5769 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
c2d11a7d | 5770 | |
102182a9 | 5771 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
5772 | set_gdbarch_short_bit (gdbarch, 16); |
5773 | set_gdbarch_int_bit (gdbarch, 32); | |
5774 | set_gdbarch_float_bit (gdbarch, 32); | |
5775 | set_gdbarch_double_bit (gdbarch, 64); | |
5776 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
5777 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
5778 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
5779 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
2e4ebe70 | 5780 | tdep->found_abi = found_abi; |
0dadbba0 | 5781 | tdep->mips_abi = mips_abi; |
1d06468c | 5782 | |
f7ab6ec6 MS |
5783 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
5784 | mips_elf_make_msymbol_special); | |
5785 | ||
56cea623 AC |
5786 | /* Fill in the OS dependant register numbers. */ |
5787 | { | |
5788 | struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, | |
5789 | struct mips_regnum); | |
5790 | tdep->regnum = regnum; | |
5791 | if (info.osabi == GDB_OSABI_IRIX) | |
5792 | { | |
5793 | regnum->fp0 = 32; | |
5794 | regnum->pc = 64; | |
5795 | regnum->cause = 65; | |
5796 | regnum->badvaddr = 66; | |
5797 | regnum->hi = 67; | |
5798 | regnum->lo = 68; | |
5799 | regnum->fp_control_status = 69; | |
5800 | regnum->fp_implementation_revision = 70; | |
5801 | num_regs = 71; | |
5802 | } | |
5803 | else | |
5804 | { | |
5805 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5806 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5807 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5808 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5809 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5810 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5811 | regnum->fp_control_status = 70; | |
5812 | regnum->fp_implementation_revision = 71; | |
5813 | num_regs = 90; | |
5814 | } | |
5815 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been | |
5816 | replaced by read_pc? */ | |
5817 | set_gdbarch_pc_regnum (gdbarch, regnum->pc); | |
5818 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); | |
5819 | set_gdbarch_num_regs (gdbarch, num_regs); | |
5820 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
5821 | } | |
fe29b929 | 5822 | |
0dadbba0 | 5823 | switch (mips_abi) |
c2d11a7d | 5824 | { |
0dadbba0 | 5825 | case MIPS_ABI_O32: |
25ab4790 | 5826 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 5827 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
a5ea2558 | 5828 | tdep->mips_default_saved_regsize = 4; |
0dadbba0 | 5829 | tdep->mips_default_stack_argsize = 4; |
c2d11a7d | 5830 | tdep->mips_fp_register_double = 0; |
acdb74a0 | 5831 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
56cea623 | 5832 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 5833 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5834 | set_gdbarch_long_bit (gdbarch, 32); |
5835 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5836 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
5837 | set_gdbarch_deprecated_reg_struct_has_addr |
5838 | (gdbarch, mips_o32_reg_struct_has_addr); | |
c2d11a7d | 5839 | break; |
0dadbba0 | 5840 | case MIPS_ABI_O64: |
25ab4790 | 5841 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
ebba8386 | 5842 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_o64_store_return_value); |
46cac009 | 5843 | set_gdbarch_deprecated_extract_return_value (gdbarch, mips_o64_extract_return_value); |
a5ea2558 | 5844 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 | 5845 | tdep->mips_default_stack_argsize = 8; |
c2d11a7d | 5846 | tdep->mips_fp_register_double = 1; |
acdb74a0 | 5847 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
56cea623 | 5848 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 5849 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5850 | set_gdbarch_long_bit (gdbarch, 32); |
5851 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5852 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
5853 | set_gdbarch_deprecated_reg_struct_has_addr |
5854 | (gdbarch, mips_o32_reg_struct_has_addr); | |
b060cbea | 5855 | set_gdbarch_use_struct_convention (gdbarch, always_use_struct_convention); |
c2d11a7d | 5856 | break; |
0dadbba0 | 5857 | case MIPS_ABI_EABI32: |
25ab4790 | 5858 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
ebba8386 | 5859 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_eabi_store_return_value); |
46cac009 | 5860 | set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value); |
a5ea2558 | 5861 | tdep->mips_default_saved_regsize = 4; |
0dadbba0 | 5862 | tdep->mips_default_stack_argsize = 4; |
c2d11a7d | 5863 | tdep->mips_fp_register_double = 0; |
acdb74a0 | 5864 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 5865 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5866 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5867 | set_gdbarch_long_bit (gdbarch, 32); |
5868 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5869 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
5870 | set_gdbarch_deprecated_reg_struct_has_addr |
5871 | (gdbarch, mips_eabi_reg_struct_has_addr); | |
cb811fe7 MS |
5872 | set_gdbarch_use_struct_convention (gdbarch, |
5873 | mips_eabi_use_struct_convention); | |
c2d11a7d | 5874 | break; |
0dadbba0 | 5875 | case MIPS_ABI_EABI64: |
25ab4790 | 5876 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
ebba8386 | 5877 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_eabi_store_return_value); |
46cac009 | 5878 | set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value); |
a5ea2558 | 5879 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 | 5880 | tdep->mips_default_stack_argsize = 8; |
c2d11a7d | 5881 | tdep->mips_fp_register_double = 1; |
acdb74a0 | 5882 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 5883 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5884 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5885 | set_gdbarch_long_bit (gdbarch, 64); |
5886 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5887 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
5888 | set_gdbarch_deprecated_reg_struct_has_addr |
5889 | (gdbarch, mips_eabi_reg_struct_has_addr); | |
cb811fe7 MS |
5890 | set_gdbarch_use_struct_convention (gdbarch, |
5891 | mips_eabi_use_struct_convention); | |
c2d11a7d | 5892 | break; |
0dadbba0 | 5893 | case MIPS_ABI_N32: |
25ab4790 | 5894 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5895 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
63db5580 | 5896 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 AC |
5897 | tdep->mips_default_stack_argsize = 8; |
5898 | tdep->mips_fp_register_double = 1; | |
acdb74a0 | 5899 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 5900 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5901 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
5902 | set_gdbarch_long_bit (gdbarch, 32); |
5903 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5904 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
5905 | set_gdbarch_deprecated_reg_struct_has_addr |
5906 | (gdbarch, mips_n32n64_reg_struct_has_addr); | |
28d169de KB |
5907 | break; |
5908 | case MIPS_ABI_N64: | |
25ab4790 | 5909 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5910 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
28d169de KB |
5911 | tdep->mips_default_saved_regsize = 8; |
5912 | tdep->mips_default_stack_argsize = 8; | |
5913 | tdep->mips_fp_register_double = 1; | |
5914 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; | |
56cea623 | 5915 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
5916 | tdep->default_mask_address_p = 0; |
5917 | set_gdbarch_long_bit (gdbarch, 64); | |
5918 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5919 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
5920 | set_gdbarch_deprecated_reg_struct_has_addr |
5921 | (gdbarch, mips_n32n64_reg_struct_has_addr); | |
0dadbba0 | 5922 | break; |
c2d11a7d | 5923 | default: |
2e4ebe70 DJ |
5924 | internal_error (__FILE__, __LINE__, |
5925 | "unknown ABI in switch"); | |
c2d11a7d JM |
5926 | } |
5927 | ||
a5ea2558 AC |
5928 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
5929 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
5930 | comment: | |
5931 | ||
5932 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
5933 | flag in object files because to do so would make it impossible to | |
102182a9 | 5934 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 5935 | unnecessarily restrictive. |
361d1df0 | 5936 | |
a5ea2558 AC |
5937 | We could solve this problem by adding "-gp32" multilibs to gcc, |
5938 | but to set this flag before gcc is built with such multilibs will | |
5939 | break too many systems.'' | |
5940 | ||
5941 | But even more unhelpfully, the default linker output target for | |
5942 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
5943 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 5944 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
5945 | this flag to detect 32-bit mode would do the wrong thing given |
5946 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 5947 | as 32-bit programs by default. */ |
a5ea2558 | 5948 | |
c2d11a7d JM |
5949 | /* enable/disable the MIPS FPU */ |
5950 | if (!mips_fpu_type_auto) | |
5951 | tdep->mips_fpu_type = mips_fpu_type; | |
5952 | else if (info.bfd_arch_info != NULL | |
5953 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5954 | switch (info.bfd_arch_info->mach) | |
5955 | { | |
b0069a17 | 5956 | case bfd_mach_mips3900: |
c2d11a7d | 5957 | case bfd_mach_mips4100: |
ed9a39eb | 5958 | case bfd_mach_mips4111: |
c2d11a7d JM |
5959 | tdep->mips_fpu_type = MIPS_FPU_NONE; |
5960 | break; | |
bf64bfd6 AC |
5961 | case bfd_mach_mips4650: |
5962 | tdep->mips_fpu_type = MIPS_FPU_SINGLE; | |
5963 | break; | |
c2d11a7d JM |
5964 | default: |
5965 | tdep->mips_fpu_type = MIPS_FPU_DOUBLE; | |
5966 | break; | |
5967 | } | |
5968 | else | |
5969 | tdep->mips_fpu_type = MIPS_FPU_DOUBLE; | |
5970 | ||
691c0433 | 5971 | /* MIPS version of register names. */ |
c2d11a7d | 5972 | set_gdbarch_register_name (gdbarch, mips_register_name); |
691c0433 AC |
5973 | if (info.osabi == GDB_OSABI_IRIX) |
5974 | tdep->mips_processor_reg_names = mips_irix_reg_names; | |
5975 | else if (info.bfd_arch_info != NULL && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
5976 | tdep->mips_processor_reg_names = mips_tx39_reg_names; | |
5977 | else | |
5978 | tdep->mips_processor_reg_names = mips_generic_reg_names; | |
6c997a34 | 5979 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
c2d11a7d | 5980 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); |
0ba6dca9 | 5981 | set_gdbarch_deprecated_target_read_fp (gdbarch, mips_read_sp); /* Draft FRAME base. */ |
bcb0cc15 | 5982 | set_gdbarch_read_sp (gdbarch, mips_read_sp); |
c2d11a7d | 5983 | |
102182a9 MS |
5984 | /* Add/remove bits from an address. The MIPS needs be careful to |
5985 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
5986 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
5987 | ||
10312cc4 | 5988 | /* There's a mess in stack frame creation. See comments in |
2ca6c561 AC |
5989 | blockframe.c near reference to DEPRECATED_INIT_FRAME_PC_FIRST. */ |
5990 | set_gdbarch_deprecated_init_frame_pc_first (gdbarch, mips_init_frame_pc_first); | |
10312cc4 | 5991 | |
102182a9 | 5992 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 5993 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
2f38ef89 KB |
5994 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum); |
5995 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
5996 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 5997 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 5998 | |
c2d11a7d | 5999 | /* Initialize a frame */ |
e0f7ec59 | 6000 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, mips_find_saved_regs); |
e9582e71 | 6001 | set_gdbarch_deprecated_init_extra_frame_info (gdbarch, mips_init_extra_frame_info); |
c2d11a7d JM |
6002 | |
6003 | /* MIPS version of CALL_DUMMY */ | |
6004 | ||
9710e734 AC |
6005 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
6006 | replaced by a command, and all targets will default to on stack | |
6007 | (regardless of the stack's execute status). */ | |
6008 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
749b82f6 | 6009 | set_gdbarch_deprecated_pop_frame (gdbarch, mips_pop_frame); |
dc604539 | 6010 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
a59fe496 | 6011 | set_gdbarch_deprecated_save_dummy_frame_tos (gdbarch, generic_save_dummy_frame_tos); |
d05285fa | 6012 | |
618ce49f | 6013 | set_gdbarch_deprecated_frame_chain (gdbarch, mips_frame_chain); |
b5d1566e MS |
6014 | set_gdbarch_frameless_function_invocation (gdbarch, |
6015 | generic_frameless_function_invocation_not); | |
8bedc050 | 6016 | set_gdbarch_deprecated_frame_saved_pc (gdbarch, mips_frame_saved_pc); |
b5d1566e MS |
6017 | set_gdbarch_frame_args_skip (gdbarch, 0); |
6018 | ||
129c1cd6 | 6019 | set_gdbarch_deprecated_get_saved_register (gdbarch, mips_get_saved_register); |
c2d11a7d | 6020 | |
f7b9e9fc AC |
6021 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
6022 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
6023 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
f7b9e9fc AC |
6024 | |
6025 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
6913c89a | 6026 | set_gdbarch_deprecated_saved_pc_after_call (gdbarch, mips_saved_pc_after_call); |
f7b9e9fc | 6027 | |
fc0c74b1 AC |
6028 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
6029 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
6030 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 6031 | |
102182a9 MS |
6032 | set_gdbarch_function_start_offset (gdbarch, 0); |
6033 | ||
a4b8ebc8 | 6034 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 6035 | |
e11c53d2 | 6036 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
102182a9 | 6037 | set_gdbarch_pc_in_sigtramp (gdbarch, mips_pc_in_sigtramp); |
bf1f5b4c | 6038 | |
e5ab0dce AC |
6039 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); |
6040 | ||
3a3bc038 AC |
6041 | /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT, |
6042 | HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT | |
6043 | need to all be folded into the target vector. Since they are | |
6044 | being used as guards for STOPPED_BY_WATCHPOINT, why not have | |
6045 | STOPPED_BY_WATCHPOINT return the type of watchpoint that the code | |
6046 | is sitting on? */ | |
6047 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
6048 | ||
70f80edf | 6049 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
4be87837 | 6050 | gdbarch_init_osabi (info, gdbarch); |
70f80edf | 6051 | |
2f1488ce MS |
6052 | set_gdbarch_extract_struct_value_address (gdbarch, |
6053 | mips_extract_struct_value_address); | |
757a7cc6 MS |
6054 | |
6055 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_stub); | |
6056 | ||
6057 | set_gdbarch_in_solib_call_trampoline (gdbarch, mips_in_call_stub); | |
e41b17f0 | 6058 | set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); |
757a7cc6 | 6059 | |
4b9b3959 AC |
6060 | return gdbarch; |
6061 | } | |
6062 | ||
2e4ebe70 DJ |
6063 | static void |
6064 | mips_abi_update (char *ignore_args, int from_tty, | |
6065 | struct cmd_list_element *c) | |
6066 | { | |
6067 | struct gdbarch_info info; | |
6068 | ||
6069 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
6070 | mips_gdbarch_init will take care of the rest. */ | |
6071 | gdbarch_info_init (&info); | |
6072 | gdbarch_update_p (info); | |
6073 | } | |
6074 | ||
ad188201 KB |
6075 | /* Print out which MIPS ABI is in use. */ |
6076 | ||
6077 | static void | |
6078 | show_mips_abi (char *ignore_args, int from_tty) | |
6079 | { | |
6080 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips) | |
6081 | printf_filtered ( | |
6082 | "The MIPS ABI is unknown because the current architecture is not MIPS.\n"); | |
6083 | else | |
6084 | { | |
6085 | enum mips_abi global_abi = global_mips_abi (); | |
6086 | enum mips_abi actual_abi = mips_abi (current_gdbarch); | |
6087 | const char *actual_abi_str = mips_abi_strings[actual_abi]; | |
6088 | ||
6089 | if (global_abi == MIPS_ABI_UNKNOWN) | |
6090 | printf_filtered ("The MIPS ABI is set automatically (currently \"%s\").\n", | |
6091 | actual_abi_str); | |
6092 | else if (global_abi == actual_abi) | |
6093 | printf_filtered ( | |
6094 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6095 | actual_abi_str); | |
6096 | else | |
6097 | { | |
6098 | /* Probably shouldn't happen... */ | |
6099 | printf_filtered ( | |
6100 | "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n", | |
6101 | actual_abi_str, | |
6102 | mips_abi_strings[global_abi]); | |
6103 | } | |
6104 | } | |
6105 | } | |
6106 | ||
4b9b3959 AC |
6107 | static void |
6108 | mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
6109 | { | |
6110 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
6111 | if (tdep != NULL) | |
c2d11a7d | 6112 | { |
acdb74a0 AC |
6113 | int ef_mips_arch; |
6114 | int ef_mips_32bitmode; | |
6115 | /* determine the ISA */ | |
6116 | switch (tdep->elf_flags & EF_MIPS_ARCH) | |
6117 | { | |
6118 | case E_MIPS_ARCH_1: | |
6119 | ef_mips_arch = 1; | |
6120 | break; | |
6121 | case E_MIPS_ARCH_2: | |
6122 | ef_mips_arch = 2; | |
6123 | break; | |
6124 | case E_MIPS_ARCH_3: | |
6125 | ef_mips_arch = 3; | |
6126 | break; | |
6127 | case E_MIPS_ARCH_4: | |
93d56215 | 6128 | ef_mips_arch = 4; |
acdb74a0 AC |
6129 | break; |
6130 | default: | |
93d56215 | 6131 | ef_mips_arch = 0; |
acdb74a0 AC |
6132 | break; |
6133 | } | |
6134 | /* determine the size of a pointer */ | |
6135 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); | |
4b9b3959 AC |
6136 | fprintf_unfiltered (file, |
6137 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 6138 | tdep->elf_flags); |
4b9b3959 | 6139 | fprintf_unfiltered (file, |
acdb74a0 AC |
6140 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
6141 | ef_mips_32bitmode); | |
6142 | fprintf_unfiltered (file, | |
6143 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
6144 | ef_mips_arch); | |
6145 | fprintf_unfiltered (file, | |
6146 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6147 | tdep->mips_abi, | |
2e4ebe70 | 6148 | mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
6149 | fprintf_unfiltered (file, |
6150 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
6151 | mips_mask_address_p (), | |
6152 | tdep->default_mask_address_p); | |
c2d11a7d | 6153 | } |
4b9b3959 AC |
6154 | fprintf_unfiltered (file, |
6155 | "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n", | |
6156 | FP_REGISTER_DOUBLE); | |
6157 | fprintf_unfiltered (file, | |
6158 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
6159 | MIPS_DEFAULT_FPU_TYPE, | |
6160 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6161 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6162 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6163 | : "???")); | |
6164 | fprintf_unfiltered (file, | |
6165 | "mips_dump_tdep: MIPS_EABI = %d\n", | |
6166 | MIPS_EABI); | |
4b9b3959 AC |
6167 | fprintf_unfiltered (file, |
6168 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
6169 | MIPS_FPU_TYPE, | |
6170 | (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6171 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6172 | : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6173 | : "???")); | |
6174 | fprintf_unfiltered (file, | |
6175 | "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n", | |
6176 | MIPS_DEFAULT_SAVED_REGSIZE); | |
4b9b3959 AC |
6177 | fprintf_unfiltered (file, |
6178 | "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n", | |
6179 | FP_REGISTER_DOUBLE); | |
4b9b3959 AC |
6180 | fprintf_unfiltered (file, |
6181 | "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n", | |
6182 | MIPS_DEFAULT_STACK_ARGSIZE); | |
6183 | fprintf_unfiltered (file, | |
6184 | "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n", | |
6185 | MIPS_STACK_ARGSIZE); | |
2475bac3 AC |
6186 | fprintf_unfiltered (file, |
6187 | "mips_dump_tdep: A0_REGNUM = %d\n", | |
6188 | A0_REGNUM); | |
6189 | fprintf_unfiltered (file, | |
6190 | "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n", | |
6191 | XSTRING (ADDR_BITS_REMOVE(ADDR))); | |
6192 | fprintf_unfiltered (file, | |
6193 | "mips_dump_tdep: ATTACH_DETACH # %s\n", | |
6194 | XSTRING (ATTACH_DETACH)); | |
2475bac3 AC |
6195 | fprintf_unfiltered (file, |
6196 | "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n", | |
6197 | XSTRING (DWARF_REG_TO_REGNUM (REGNUM))); | |
6198 | fprintf_unfiltered (file, | |
6199 | "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n", | |
6200 | XSTRING (ECOFF_REG_TO_REGNUM (REGNUM))); | |
2475bac3 AC |
6201 | fprintf_unfiltered (file, |
6202 | "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n", | |
6203 | FIRST_EMBED_REGNUM); | |
2475bac3 AC |
6204 | fprintf_unfiltered (file, |
6205 | "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n", | |
6206 | XSTRING (IGNORE_HELPER_CALL (PC))); | |
2475bac3 AC |
6207 | fprintf_unfiltered (file, |
6208 | "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n", | |
6209 | XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME))); | |
6210 | fprintf_unfiltered (file, | |
6211 | "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n", | |
6212 | XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME))); | |
2475bac3 AC |
6213 | fprintf_unfiltered (file, |
6214 | "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n", | |
6215 | LAST_EMBED_REGNUM); | |
2475bac3 AC |
6216 | #ifdef MACHINE_CPROC_FP_OFFSET |
6217 | fprintf_unfiltered (file, | |
6218 | "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n", | |
6219 | MACHINE_CPROC_FP_OFFSET); | |
6220 | #endif | |
6221 | #ifdef MACHINE_CPROC_PC_OFFSET | |
6222 | fprintf_unfiltered (file, | |
6223 | "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n", | |
6224 | MACHINE_CPROC_PC_OFFSET); | |
6225 | #endif | |
6226 | #ifdef MACHINE_CPROC_SP_OFFSET | |
6227 | fprintf_unfiltered (file, | |
6228 | "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n", | |
6229 | MACHINE_CPROC_SP_OFFSET); | |
6230 | #endif | |
2475bac3 AC |
6231 | fprintf_unfiltered (file, |
6232 | "mips_dump_tdep: MIPS16_INSTLEN = %d\n", | |
6233 | MIPS16_INSTLEN); | |
2475bac3 AC |
6234 | fprintf_unfiltered (file, |
6235 | "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n"); | |
6236 | fprintf_unfiltered (file, | |
6237 | "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n"); | |
6238 | fprintf_unfiltered (file, | |
6239 | "mips_dump_tdep: MIPS_INSTLEN = %d\n", | |
6240 | MIPS_INSTLEN); | |
6241 | fprintf_unfiltered (file, | |
acdb74a0 AC |
6242 | "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n", |
6243 | MIPS_LAST_ARG_REGNUM, | |
6244 | MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1); | |
2475bac3 AC |
6245 | fprintf_unfiltered (file, |
6246 | "mips_dump_tdep: MIPS_NUMREGS = %d\n", | |
6247 | MIPS_NUMREGS); | |
2475bac3 AC |
6248 | fprintf_unfiltered (file, |
6249 | "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n", | |
6250 | MIPS_SAVED_REGSIZE); | |
2475bac3 AC |
6251 | fprintf_unfiltered (file, |
6252 | "mips_dump_tdep: PRID_REGNUM = %d\n", | |
6253 | PRID_REGNUM); | |
2475bac3 AC |
6254 | fprintf_unfiltered (file, |
6255 | "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n"); | |
6256 | fprintf_unfiltered (file, | |
6257 | "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n"); | |
6258 | fprintf_unfiltered (file, | |
6259 | "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n"); | |
6260 | fprintf_unfiltered (file, | |
6261 | "mips_dump_tdep: PROC_FRAME_REG = function?\n"); | |
6262 | fprintf_unfiltered (file, | |
6263 | "mips_dump_tdep: PROC_FREG_MASK = function?\n"); | |
6264 | fprintf_unfiltered (file, | |
6265 | "mips_dump_tdep: PROC_FREG_OFFSET = function?\n"); | |
6266 | fprintf_unfiltered (file, | |
6267 | "mips_dump_tdep: PROC_HIGH_ADDR = function?\n"); | |
6268 | fprintf_unfiltered (file, | |
6269 | "mips_dump_tdep: PROC_LOW_ADDR = function?\n"); | |
6270 | fprintf_unfiltered (file, | |
6271 | "mips_dump_tdep: PROC_PC_REG = function?\n"); | |
6272 | fprintf_unfiltered (file, | |
6273 | "mips_dump_tdep: PROC_REG_MASK = function?\n"); | |
6274 | fprintf_unfiltered (file, | |
6275 | "mips_dump_tdep: PROC_REG_OFFSET = function?\n"); | |
6276 | fprintf_unfiltered (file, | |
6277 | "mips_dump_tdep: PROC_SYMBOL = function?\n"); | |
6278 | fprintf_unfiltered (file, | |
6279 | "mips_dump_tdep: PS_REGNUM = %d\n", | |
6280 | PS_REGNUM); | |
2475bac3 AC |
6281 | fprintf_unfiltered (file, |
6282 | "mips_dump_tdep: RA_REGNUM = %d\n", | |
6283 | RA_REGNUM); | |
2475bac3 AC |
6284 | #ifdef SAVED_BYTES |
6285 | fprintf_unfiltered (file, | |
6286 | "mips_dump_tdep: SAVED_BYTES = %d\n", | |
6287 | SAVED_BYTES); | |
6288 | #endif | |
6289 | #ifdef SAVED_FP | |
6290 | fprintf_unfiltered (file, | |
6291 | "mips_dump_tdep: SAVED_FP = %d\n", | |
6292 | SAVED_FP); | |
6293 | #endif | |
6294 | #ifdef SAVED_PC | |
6295 | fprintf_unfiltered (file, | |
6296 | "mips_dump_tdep: SAVED_PC = %d\n", | |
6297 | SAVED_PC); | |
6298 | #endif | |
6299 | fprintf_unfiltered (file, | |
6300 | "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n", | |
6301 | XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS))); | |
6302 | fprintf_unfiltered (file, | |
6303 | "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n"); | |
6304 | fprintf_unfiltered (file, | |
6305 | "mips_dump_tdep: SIGFRAME_BASE = %d\n", | |
6306 | SIGFRAME_BASE); | |
6307 | fprintf_unfiltered (file, | |
6308 | "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n", | |
6309 | SIGFRAME_FPREGSAVE_OFF); | |
6310 | fprintf_unfiltered (file, | |
6311 | "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n", | |
6312 | SIGFRAME_PC_OFF); | |
6313 | fprintf_unfiltered (file, | |
6314 | "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n", | |
6315 | SIGFRAME_REGSAVE_OFF); | |
2475bac3 AC |
6316 | fprintf_unfiltered (file, |
6317 | "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n", | |
6318 | XSTRING (SKIP_TRAMPOLINE_CODE (PC))); | |
6319 | fprintf_unfiltered (file, | |
6320 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n", | |
6321 | XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P))); | |
6322 | fprintf_unfiltered (file, | |
b0ed3589 AC |
6323 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n", |
6324 | SOFTWARE_SINGLE_STEP_P ()); | |
2475bac3 AC |
6325 | fprintf_unfiltered (file, |
6326 | "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n", | |
6327 | XSTRING (STAB_REG_TO_REGNUM (REGNUM))); | |
6328 | #ifdef STACK_END_ADDR | |
6329 | fprintf_unfiltered (file, | |
6330 | "mips_dump_tdep: STACK_END_ADDR = %d\n", | |
6331 | STACK_END_ADDR); | |
6332 | #endif | |
6333 | fprintf_unfiltered (file, | |
6334 | "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n", | |
6335 | XSTRING (STEP_SKIPS_DELAY (PC))); | |
6336 | fprintf_unfiltered (file, | |
6337 | "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n", | |
6338 | STEP_SKIPS_DELAY_P); | |
6339 | fprintf_unfiltered (file, | |
6340 | "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n", | |
6341 | XSTRING (STOPPED_BY_WATCHPOINT (WS))); | |
6342 | fprintf_unfiltered (file, | |
6343 | "mips_dump_tdep: T9_REGNUM = %d\n", | |
6344 | T9_REGNUM); | |
6345 | fprintf_unfiltered (file, | |
6346 | "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n"); | |
6347 | fprintf_unfiltered (file, | |
6348 | "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n", | |
6349 | XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE,CNT,OTHERTYPE))); | |
6350 | fprintf_unfiltered (file, | |
6351 | "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n", | |
6352 | XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS)); | |
2475bac3 AC |
6353 | #ifdef TRACE_CLEAR |
6354 | fprintf_unfiltered (file, | |
6355 | "mips_dump_tdep: TRACE_CLEAR # %s\n", | |
6356 | XSTRING (TRACE_CLEAR (THREAD, STATE))); | |
6357 | #endif | |
6358 | #ifdef TRACE_FLAVOR | |
6359 | fprintf_unfiltered (file, | |
6360 | "mips_dump_tdep: TRACE_FLAVOR = %d\n", | |
6361 | TRACE_FLAVOR); | |
6362 | #endif | |
6363 | #ifdef TRACE_FLAVOR_SIZE | |
6364 | fprintf_unfiltered (file, | |
6365 | "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n", | |
6366 | TRACE_FLAVOR_SIZE); | |
6367 | #endif | |
6368 | #ifdef TRACE_SET | |
6369 | fprintf_unfiltered (file, | |
6370 | "mips_dump_tdep: TRACE_SET # %s\n", | |
6371 | XSTRING (TRACE_SET (X,STATE))); | |
6372 | #endif | |
2475bac3 AC |
6373 | #ifdef UNUSED_REGNUM |
6374 | fprintf_unfiltered (file, | |
6375 | "mips_dump_tdep: UNUSED_REGNUM = %d\n", | |
6376 | UNUSED_REGNUM); | |
6377 | #endif | |
6378 | fprintf_unfiltered (file, | |
6379 | "mips_dump_tdep: V0_REGNUM = %d\n", | |
6380 | V0_REGNUM); | |
6381 | fprintf_unfiltered (file, | |
6382 | "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n", | |
6383 | (long) VM_MIN_ADDRESS); | |
2475bac3 AC |
6384 | fprintf_unfiltered (file, |
6385 | "mips_dump_tdep: ZERO_REGNUM = %d\n", | |
6386 | ZERO_REGNUM); | |
6387 | fprintf_unfiltered (file, | |
6388 | "mips_dump_tdep: _PROC_MAGIC_ = %d\n", | |
6389 | _PROC_MAGIC_); | |
c2d11a7d JM |
6390 | } |
6391 | ||
a78f21af AC |
6392 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
6393 | ||
c906108c | 6394 | void |
acdb74a0 | 6395 | _initialize_mips_tdep (void) |
c906108c SS |
6396 | { |
6397 | static struct cmd_list_element *mipsfpulist = NULL; | |
6398 | struct cmd_list_element *c; | |
6399 | ||
2e4ebe70 DJ |
6400 | mips_abi_string = mips_abi_strings [MIPS_ABI_UNKNOWN]; |
6401 | if (MIPS_ABI_LAST + 1 | |
6402 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
6403 | internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync"); | |
6404 | ||
4b9b3959 | 6405 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 6406 | |
a5ea2558 AC |
6407 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
6408 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
6409 | "Various MIPS specific commands.", | |
6410 | &setmipscmdlist, "set mips ", 0, &setlist); | |
6411 | ||
6412 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
6413 | "Various MIPS specific commands.", | |
6414 | &showmipscmdlist, "show mips ", 0, &showlist); | |
6415 | ||
6416 | /* Allow the user to override the saved register size. */ | |
6417 | add_show_from_set (add_set_enum_cmd ("saved-gpreg-size", | |
1ed2a135 AC |
6418 | class_obscure, |
6419 | size_enums, | |
6420 | &mips_saved_regsize_string, "\ | |
a5ea2558 AC |
6421 | Set size of general purpose registers saved on the stack.\n\ |
6422 | This option can be set to one of:\n\ | |
6423 | 32 - Force GDB to treat saved GP registers as 32-bit\n\ | |
6424 | 64 - Force GDB to treat saved GP registers as 64-bit\n\ | |
6425 | auto - Allow GDB to use the target's default setting or autodetect the\n\ | |
6426 | saved GP register size from information contained in the executable.\n\ | |
6427 | (default: auto)", | |
1ed2a135 | 6428 | &setmipscmdlist), |
a5ea2558 AC |
6429 | &showmipscmdlist); |
6430 | ||
d929b26f AC |
6431 | /* Allow the user to override the argument stack size. */ |
6432 | add_show_from_set (add_set_enum_cmd ("stack-arg-size", | |
6433 | class_obscure, | |
6434 | size_enums, | |
1ed2a135 | 6435 | &mips_stack_argsize_string, "\ |
d929b26f AC |
6436 | Set the amount of stack space reserved for each argument.\n\ |
6437 | This option can be set to one of:\n\ | |
6438 | 32 - Force GDB to allocate 32-bit chunks per argument\n\ | |
6439 | 64 - Force GDB to allocate 64-bit chunks per argument\n\ | |
6440 | auto - Allow GDB to determine the correct setting from the current\n\ | |
6441 | target and executable (default)", | |
6442 | &setmipscmdlist), | |
6443 | &showmipscmdlist); | |
6444 | ||
2e4ebe70 DJ |
6445 | /* Allow the user to override the ABI. */ |
6446 | c = add_set_enum_cmd | |
6447 | ("abi", class_obscure, mips_abi_strings, &mips_abi_string, | |
6448 | "Set the ABI used by this program.\n" | |
6449 | "This option can be set to one of:\n" | |
6450 | " auto - the default ABI associated with the current binary\n" | |
6451 | " o32\n" | |
6452 | " o64\n" | |
6453 | " n32\n" | |
f3a7b3a5 | 6454 | " n64\n" |
2e4ebe70 DJ |
6455 | " eabi32\n" |
6456 | " eabi64", | |
6457 | &setmipscmdlist); | |
2e4ebe70 | 6458 | set_cmd_sfunc (c, mips_abi_update); |
ad188201 KB |
6459 | add_cmd ("abi", class_obscure, show_mips_abi, |
6460 | "Show ABI in use by MIPS target", &showmipscmdlist); | |
2e4ebe70 | 6461 | |
c906108c SS |
6462 | /* Let the user turn off floating point and set the fence post for |
6463 | heuristic_proc_start. */ | |
6464 | ||
6465 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
6466 | "Set use of MIPS floating-point coprocessor.", | |
6467 | &mipsfpulist, "set mipsfpu ", 0, &setlist); | |
6468 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
6469 | "Select single-precision MIPS floating-point coprocessor.", | |
6470 | &mipsfpulist); | |
6471 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
8e1a459b | 6472 | "Select double-precision MIPS floating-point coprocessor.", |
c906108c SS |
6473 | &mipsfpulist); |
6474 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
6475 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
6476 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
6477 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
6478 | "Select no MIPS floating-point coprocessor.", | |
6479 | &mipsfpulist); | |
6480 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); | |
6481 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
6482 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
6483 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
6484 | "Select MIPS floating-point coprocessor automatically.", | |
6485 | &mipsfpulist); | |
6486 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
6487 | "Show current use of MIPS floating-point coprocessor target.", | |
6488 | &showlist); | |
6489 | ||
c906108c SS |
6490 | /* We really would like to have both "0" and "unlimited" work, but |
6491 | command.c doesn't deal with that. So make it a var_zinteger | |
6492 | because the user can always use "999999" or some such for unlimited. */ | |
6493 | c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger, | |
6494 | (char *) &heuristic_fence_post, | |
6495 | "\ | |
6496 | Set the distance searched for the start of a function.\n\ | |
6497 | If you are debugging a stripped executable, GDB needs to search through the\n\ | |
6498 | program for the start of a function. This command sets the distance of the\n\ | |
6499 | search. The only need to set it is when debugging a stripped executable.", | |
6500 | &setlist); | |
6501 | /* We need to throw away the frame cache when we set this, since it | |
6502 | might change our ability to get backtraces. */ | |
9f60d481 | 6503 | set_cmd_sfunc (c, reinit_frame_cache_sfunc); |
c906108c SS |
6504 | add_show_from_set (c, &showlist); |
6505 | ||
6506 | /* Allow the user to control whether the upper bits of 64-bit | |
6507 | addresses should be zeroed. */ | |
e9e68a56 AC |
6508 | add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, "\ |
6509 | Set zeroing of upper 32 bits of 64-bit addresses.\n\ | |
6510 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ | |
6511 | allow GDB to determine the correct value.\n", "\ | |
6512 | Show zeroing of upper 32 bits of 64-bit addresses.", | |
6513 | NULL, show_mask_address, | |
6514 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
6515 | |
6516 | /* Allow the user to control the size of 32 bit registers within the | |
6517 | raw remote packet. */ | |
719ec221 AC |
6518 | add_setshow_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
6519 | var_boolean, &mips64_transfers_32bit_regs_p, "\ | |
6520 | Set compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\ | |
6521 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ | |
6522 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
6523 | 64 bits for others. Use \"off\" to disable compatibility mode", "\ | |
6524 | Show compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\ | |
43e526b9 JM |
6525 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
6526 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
6527 | 64 bits for others. Use \"off\" to disable compatibility mode", | |
719ec221 AC |
6528 | set_mips64_transfers_32bit_regs, NULL, |
6529 | &setlist, &showlist); | |
9ace0497 AC |
6530 | |
6531 | /* Debug this files internals. */ | |
6532 | add_show_from_set (add_set_cmd ("mips", class_maintenance, var_zinteger, | |
6533 | &mips_debug, "Set mips debugging.\n\ | |
6534 | When non-zero, mips specific debugging is enabled.", &setdebuglist), | |
6535 | &showdebuglist); | |
c906108c | 6536 | } |