Commit | Line | Data |
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7d9884b9 | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
18b46e7c | 2 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995 |
0434c1a0 | 3 | Free Software Foundation, Inc. |
bd5635a1 RP |
4 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
5 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
6 | ||
7 | This file is part of GDB. | |
8 | ||
361bf6ee | 9 | This program is free software; you can redistribute it and/or modify |
bd5635a1 | 10 | it under the terms of the GNU General Public License as published by |
361bf6ee JG |
11 | the Free Software Foundation; either version 2 of the License, or |
12 | (at your option) any later version. | |
bd5635a1 | 13 | |
361bf6ee | 14 | This program is distributed in the hope that it will be useful, |
bd5635a1 RP |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
361bf6ee JG |
20 | along with this program; if not, write to the Free Software |
21 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
bd5635a1 | 22 | |
bd5635a1 | 23 | #include "defs.h" |
bd5635a1 RP |
24 | #include "frame.h" |
25 | #include "inferior.h" | |
26 | #include "symtab.h" | |
27 | #include "value.h" | |
28 | #include "gdbcmd.h" | |
ef08856f | 29 | #include "language.h" |
bd5635a1 | 30 | #include "gdbcore.h" |
62a469e1 SG |
31 | #include "symfile.h" |
32 | #include "objfiles.h" | |
3fed1c4a | 33 | #include "gdbtypes.h" |
bd5635a1 | 34 | |
ee5fb959 JK |
35 | #include "opcode/mips.h" |
36 | ||
bd5635a1 | 37 | #define VM_MIN_ADDRESS (unsigned)0x400000 |
70126bf9 KH |
38 | |
39 | /* FIXME: Put this declaration in frame.h. */ | |
40 | extern struct obstack frame_cache_obstack; | |
bd5635a1 | 41 | \f |
002a422b | 42 | #if 0 |
ee5fb959 | 43 | static int mips_in_lenient_prologue PARAMS ((CORE_ADDR, CORE_ADDR)); |
002a422b | 44 | #endif |
ee5fb959 | 45 | |
e4dbd248 PS |
46 | static void mips_set_fpu_command PARAMS ((char *, int, |
47 | struct cmd_list_element *)); | |
48 | ||
49 | static void mips_show_fpu_command PARAMS ((char *, int, | |
50 | struct cmd_list_element *)); | |
51 | ||
9f9f94aa SS |
52 | void mips_set_processor_type_command PARAMS ((char *, int)); |
53 | ||
1d9489c1 JK |
54 | int mips_set_processor_type PARAMS ((char *)); |
55 | ||
56 | static void mips_show_processor_type_command PARAMS ((char *, int)); | |
57 | ||
9f9f94aa SS |
58 | static void reinit_frame_cache_sfunc PARAMS ((char *, int, |
59 | struct cmd_list_element *)); | |
60 | ||
61 | /* This value is the model of MIPS in use. It is derived from the value | |
62 | of the PrID register. */ | |
63 | ||
64 | char *mips_processor_type; | |
65 | ||
66 | char *tmp_mips_processor_type; | |
67 | ||
c2a0f1cb ILT |
68 | /* Some MIPS boards don't support floating point, so we permit the |
69 | user to turn it off. */ | |
9f9f94aa | 70 | |
e4dbd248 PS |
71 | enum mips_fpu_type mips_fpu; |
72 | ||
73 | static char *mips_fpu_string; | |
c2a0f1cb | 74 | |
9f9f94aa SS |
75 | /* A set of original names, to be used when restoring back to generic |
76 | registers from a specific set. */ | |
77 | ||
78 | char *mips_generic_reg_names[] = REGISTER_NAMES; | |
79 | ||
80 | /* Names of IDT R3041 registers. */ | |
81 | ||
82 | char *mips_r3041_reg_names[] = { | |
83 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
84 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
85 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
86 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
87 | "sr", "lo", "hi", "bad", "cause","pc", | |
88 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
89 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
90 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
91 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
92 | "fsr", "fir", "fp", "", | |
93 | "", "", "bus", "ccfg", "", "", "", "", | |
94 | "", "", "port", "cmp", "", "", "epc", "prid", | |
95 | }; | |
96 | ||
97 | /* Names of IDT R3051 registers. */ | |
98 | ||
99 | char *mips_r3051_reg_names[] = { | |
100 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
101 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
102 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
103 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
104 | "sr", "lo", "hi", "bad", "cause","pc", | |
105 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
106 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
107 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
108 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
109 | "fsr", "fir", "fp", "", | |
110 | "inx", "rand", "elo", "", "ctxt", "", "", "", | |
111 | "", "", "ehi", "", "", "", "epc", "prid", | |
112 | }; | |
113 | ||
114 | /* Names of IDT R3081 registers. */ | |
115 | ||
116 | char *mips_r3081_reg_names[] = { | |
117 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
118 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
119 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
120 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
121 | "sr", "lo", "hi", "bad", "cause","pc", | |
122 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
123 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
124 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
125 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
126 | "fsr", "fir", "fp", "", | |
127 | "inx", "rand", "elo", "cfg", "ctxt", "", "", "", | |
128 | "", "", "ehi", "", "", "", "epc", "prid", | |
129 | }; | |
130 | ||
e4dbd248 PS |
131 | /* Names of LSI 33k registers. */ |
132 | ||
133 | char *mips_lsi33k_reg_names[] = { | |
134 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
135 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
136 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
137 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
138 | "epc", "hi", "lo", "sr", "cause","badvaddr", | |
139 | "dcic", "bpc", "bda", "", "", "", "", "", | |
140 | "", "", "", "", "", "", "", "", | |
141 | "", "", "", "", "", "", "", "", | |
142 | "", "", "", "", "", "", "", "", | |
143 | "", "", "", "", | |
144 | "", "", "", "", "", "", "", "", | |
145 | "", "", "", "", "", "", "", "", | |
146 | }; | |
147 | ||
9f9f94aa SS |
148 | struct { |
149 | char *name; | |
150 | char **regnames; | |
151 | } mips_processor_type_table[] = { | |
152 | { "generic", mips_generic_reg_names }, | |
153 | { "r3041", mips_r3041_reg_names }, | |
154 | { "r3051", mips_r3051_reg_names }, | |
155 | { "r3071", mips_r3081_reg_names }, | |
156 | { "r3081", mips_r3081_reg_names }, | |
e4dbd248 | 157 | { "lsi33k", mips_lsi33k_reg_names }, |
9f9f94aa SS |
158 | { NULL, NULL } |
159 | }; | |
160 | ||
3127785a RP |
161 | /* Heuristic_proc_start may hunt through the text section for a long |
162 | time across a 2400 baud serial line. Allows the user to limit this | |
163 | search. */ | |
9f9f94aa | 164 | |
3127785a RP |
165 | static unsigned int heuristic_fence_post = 0; |
166 | ||
0f552c5f JG |
167 | #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ |
168 | #define PROC_HIGH_ADDR(proc) ((proc)->pdr.iline) /* upper address bound */ | |
169 | #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) | |
170 | #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) | |
171 | #define PROC_REG_MASK(proc) ((proc)->pdr.regmask) | |
172 | #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) | |
173 | #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) | |
174 | #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) | |
175 | #define PROC_PC_REG(proc) ((proc)->pdr.pcreg) | |
176 | #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) | |
bd5635a1 | 177 | #define _PROC_MAGIC_ 0x0F0F0F0F |
0f552c5f JG |
178 | #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_) |
179 | #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_) | |
bd5635a1 RP |
180 | |
181 | struct linked_proc_info | |
182 | { | |
183 | struct mips_extra_func_info info; | |
184 | struct linked_proc_info *next; | |
dac4929a | 185 | } *linked_proc_desc_table = NULL; |
bd5635a1 RP |
186 | |
187 | \f | |
70126bf9 KH |
188 | /* Guaranteed to set fci->saved_regs to some values (it never leaves it |
189 | NULL). */ | |
190 | ||
191 | void | |
192 | mips_find_saved_regs (fci) | |
9f9f94aa | 193 | struct frame_info *fci; |
70126bf9 KH |
194 | { |
195 | int ireg; | |
196 | CORE_ADDR reg_position; | |
197 | /* r0 bit means kernel trap */ | |
198 | int kernel_trap; | |
199 | /* What registers have been saved? Bitmasks. */ | |
200 | unsigned long gen_mask, float_mask; | |
201 | mips_extra_func_info_t proc_desc; | |
202 | ||
203 | fci->saved_regs = (struct frame_saved_regs *) | |
204 | obstack_alloc (&frame_cache_obstack, sizeof(struct frame_saved_regs)); | |
205 | memset (fci->saved_regs, 0, sizeof (struct frame_saved_regs)); | |
206 | ||
e4dbd248 PS |
207 | /* If it is the frame for sigtramp, the saved registers are located |
208 | in a sigcontext structure somewhere on the stack. | |
209 | If the stack layout for sigtramp changes we might have to change these | |
210 | constants and the companion fixup_sigtramp in mdebugread.c */ | |
211 | #ifndef SIGFRAME_BASE | |
212 | /* To satisfy alignment restrictions, sigcontext is located 4 bytes | |
213 | above the sigtramp frame. */ | |
214 | #define SIGFRAME_BASE 4 | |
215 | #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * 4) | |
216 | #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * 4) | |
217 | #define SIGFRAME_FPREGSAVE_OFF (SIGFRAME_REGSAVE_OFF + 32 * 4 + 3 * 4) | |
218 | #endif | |
219 | #ifndef SIGFRAME_REG_SIZE | |
220 | #define SIGFRAME_REG_SIZE 4 | |
221 | #endif | |
222 | if (fci->signal_handler_caller) | |
223 | { | |
224 | for (ireg = 0; ireg < 32; ireg++) | |
225 | { | |
226 | reg_position = fci->frame + SIGFRAME_REGSAVE_OFF | |
227 | + ireg * SIGFRAME_REG_SIZE; | |
228 | fci->saved_regs->regs[ireg] = reg_position; | |
229 | } | |
230 | for (ireg = 0; ireg < 32; ireg++) | |
231 | { | |
232 | reg_position = fci->frame + SIGFRAME_FPREGSAVE_OFF | |
233 | + ireg * SIGFRAME_REG_SIZE; | |
234 | fci->saved_regs->regs[FP0_REGNUM + ireg] = reg_position; | |
235 | } | |
236 | fci->saved_regs->regs[PC_REGNUM] = fci->frame + SIGFRAME_PC_OFF; | |
237 | return; | |
238 | } | |
239 | ||
70126bf9 KH |
240 | proc_desc = fci->proc_desc; |
241 | if (proc_desc == NULL) | |
242 | /* I'm not sure how/whether this can happen. Normally when we can't | |
243 | find a proc_desc, we "synthesize" one using heuristic_proc_desc | |
244 | and set the saved_regs right away. */ | |
245 | return; | |
246 | ||
247 | kernel_trap = PROC_REG_MASK(proc_desc) & 1; | |
248 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK(proc_desc); | |
249 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK(proc_desc); | |
250 | ||
251 | if (/* In any frame other than the innermost, we assume that all | |
252 | registers have been saved. This assumes that all register | |
253 | saves in a function happen before the first function | |
254 | call. */ | |
255 | fci->next == NULL | |
256 | ||
257 | /* In a dummy frame we know exactly where things are saved. */ | |
258 | && !PROC_DESC_IS_DUMMY (proc_desc) | |
259 | ||
260 | /* Not sure exactly what kernel_trap means, but if it means | |
261 | the kernel saves the registers without a prologue doing it, | |
262 | we better not examine the prologue to see whether registers | |
263 | have been saved yet. */ | |
264 | && !kernel_trap) | |
265 | { | |
266 | /* We need to figure out whether the registers that the proc_desc | |
267 | claims are saved have been saved yet. */ | |
268 | ||
269 | CORE_ADDR addr; | |
270 | int status; | |
271 | char buf[4]; | |
272 | unsigned long inst; | |
273 | ||
274 | /* Bitmasks; set if we have found a save for the register. */ | |
275 | unsigned long gen_save_found = 0; | |
276 | unsigned long float_save_found = 0; | |
277 | ||
278 | for (addr = PROC_LOW_ADDR (proc_desc); | |
279 | addr < fci->pc /*&& (gen_mask != gen_save_found | |
280 | || float_mask != float_save_found)*/; | |
281 | addr += 4) | |
282 | { | |
283 | status = read_memory_nobpt (addr, buf, 4); | |
284 | if (status) | |
285 | memory_error (status, addr); | |
286 | inst = extract_unsigned_integer (buf, 4); | |
287 | if (/* sw reg,n($sp) */ | |
288 | (inst & 0xffe00000) == 0xafa00000 | |
289 | ||
290 | /* sw reg,n($r30) */ | |
291 | || (inst & 0xffe00000) == 0xafc00000 | |
292 | ||
293 | /* sd reg,n($sp) */ | |
294 | || (inst & 0xffe00000) == 0xffa00000) | |
295 | { | |
296 | /* It might be possible to use the instruction to | |
297 | find the offset, rather than the code below which | |
298 | is based on things being in a certain order in the | |
299 | frame, but figuring out what the instruction's offset | |
300 | is relative to might be a little tricky. */ | |
301 | int reg = (inst & 0x001f0000) >> 16; | |
302 | gen_save_found |= (1 << reg); | |
303 | } | |
304 | else if (/* swc1 freg,n($sp) */ | |
305 | (inst & 0xffe00000) == 0xe7a00000 | |
306 | ||
307 | /* swc1 freg,n($r30) */ | |
308 | || (inst & 0xffe00000) == 0xe7c00000 | |
309 | ||
310 | /* sdc1 freg,n($sp) */ | |
311 | || (inst & 0xffe00000) == 0xf7a00000) | |
312 | ||
313 | { | |
314 | int reg = ((inst & 0x001f0000) >> 16); | |
315 | float_save_found |= (1 << reg); | |
316 | } | |
317 | } | |
318 | gen_mask = gen_save_found; | |
319 | float_mask = float_save_found; | |
320 | } | |
321 | ||
322 | /* Fill in the offsets for the registers which gen_mask says | |
323 | were saved. */ | |
324 | reg_position = fci->frame + PROC_REG_OFFSET (proc_desc); | |
325 | for (ireg= 31; gen_mask; --ireg, gen_mask <<= 1) | |
326 | if (gen_mask & 0x80000000) | |
327 | { | |
328 | fci->saved_regs->regs[ireg] = reg_position; | |
329 | reg_position -= MIPS_REGSIZE; | |
330 | } | |
331 | /* Fill in the offsets for the registers which float_mask says | |
332 | were saved. */ | |
333 | reg_position = fci->frame + PROC_FREG_OFFSET (proc_desc); | |
334 | ||
335 | /* The freg_offset points to where the first *double* register | |
336 | is saved. So skip to the high-order word. */ | |
337 | reg_position += 4; | |
338 | for (ireg = 31; float_mask; --ireg, float_mask <<= 1) | |
339 | if (float_mask & 0x80000000) | |
340 | { | |
341 | fci->saved_regs->regs[FP0_REGNUM+ireg] = reg_position; | |
342 | reg_position -= MIPS_REGSIZE; | |
343 | } | |
344 | ||
345 | fci->saved_regs->regs[PC_REGNUM] = fci->saved_regs->regs[RA_REGNUM]; | |
346 | } | |
bd5635a1 | 347 | |
0f552c5f | 348 | static int |
bd5635a1 | 349 | read_next_frame_reg(fi, regno) |
9f9f94aa | 350 | struct frame_info *fi; |
bd5635a1 RP |
351 | int regno; |
352 | { | |
bd5635a1 | 353 | for (; fi; fi = fi->next) |
70126bf9 | 354 | { |
e4dbd248 PS |
355 | /* We have to get the saved sp from the sigcontext |
356 | if it is a signal handler frame. */ | |
357 | if (regno == SP_REGNUM && !fi->signal_handler_caller) | |
358 | return fi->frame; | |
70126bf9 KH |
359 | else |
360 | { | |
361 | if (fi->saved_regs == NULL) | |
362 | mips_find_saved_regs (fi); | |
363 | if (fi->saved_regs->regs[regno]) | |
364 | return read_memory_integer(fi->saved_regs->regs[regno], MIPS_REGSIZE); | |
365 | } | |
366 | } | |
367 | return read_register (regno); | |
bd5635a1 RP |
368 | } |
369 | ||
370 | int | |
371 | mips_frame_saved_pc(frame) | |
9f9f94aa | 372 | struct frame_info *frame; |
bd5635a1 | 373 | { |
0f552c5f | 374 | mips_extra_func_info_t proc_desc = frame->proc_desc; |
0434c1a0 PS |
375 | /* We have to get the saved pc from the sigcontext |
376 | if it is a signal handler frame. */ | |
377 | int pcreg = frame->signal_handler_caller ? PC_REGNUM | |
378 | : (proc_desc ? PROC_PC_REG(proc_desc) : RA_REGNUM); | |
0f552c5f | 379 | |
bd5635a1 RP |
380 | if (proc_desc && PROC_DESC_IS_DUMMY(proc_desc)) |
381 | return read_memory_integer(frame->frame - 4, 4); | |
0f552c5f | 382 | |
bd5635a1 RP |
383 | return read_next_frame_reg(frame, pcreg); |
384 | } | |
385 | ||
386 | static struct mips_extra_func_info temp_proc_desc; | |
387 | static struct frame_saved_regs temp_saved_regs; | |
388 | ||
a8172eea RP |
389 | /* This fencepost looks highly suspicious to me. Removing it also |
390 | seems suspicious as it could affect remote debugging across serial | |
3127785a | 391 | lines. */ |
a8172eea | 392 | |
0f552c5f JG |
393 | static CORE_ADDR |
394 | heuristic_proc_start(pc) | |
bd5635a1 RP |
395 | CORE_ADDR pc; |
396 | { | |
bd5635a1 | 397 | CORE_ADDR start_pc = pc; |
3127785a | 398 | CORE_ADDR fence = start_pc - heuristic_fence_post; |
0f552c5f JG |
399 | |
400 | if (start_pc == 0) return 0; | |
3127785a RP |
401 | |
402 | if (heuristic_fence_post == UINT_MAX | |
403 | || fence < VM_MIN_ADDRESS) | |
404 | fence = VM_MIN_ADDRESS; | |
0f552c5f | 405 | |
bd5635a1 RP |
406 | /* search back for previous return */ |
407 | for (start_pc -= 4; ; start_pc -= 4) | |
a8172eea RP |
408 | if (start_pc < fence) |
409 | { | |
3127785a RP |
410 | /* It's not clear to me why we reach this point when |
411 | stop_soon_quietly, but with this test, at least we | |
412 | don't print out warnings for every child forked (eg, on | |
413 | decstation). 22apr93 rich@cygnus.com. */ | |
414 | if (!stop_soon_quietly) | |
415 | { | |
23d35572 JK |
416 | static int blurb_printed = 0; |
417 | ||
3127785a RP |
418 | if (fence == VM_MIN_ADDRESS) |
419 | warning("Hit beginning of text section without finding"); | |
420 | else | |
421 | warning("Hit heuristic-fence-post without finding"); | |
422 | ||
23d35572 JK |
423 | warning("enclosing function for address 0x%x", pc); |
424 | if (!blurb_printed) | |
425 | { | |
426 | printf_filtered ("\ | |
427 | This warning occurs if you are debugging a function without any symbols\n\ | |
428 | (for example, in a stripped executable). In that case, you may wish to\n\ | |
429 | increase the size of the search with the `set heuristic-fence-post' command.\n\ | |
430 | \n\ | |
431 | Otherwise, you told GDB there was a function where there isn't one, or\n\ | |
432 | (more likely) you have encountered a bug in GDB.\n"); | |
433 | blurb_printed = 1; | |
434 | } | |
3127785a RP |
435 | } |
436 | ||
a8172eea RP |
437 | return 0; |
438 | } | |
bd5635a1 RP |
439 | else if (ABOUT_TO_RETURN(start_pc)) |
440 | break; | |
441 | ||
442 | start_pc += 8; /* skip return, and its delay slot */ | |
443 | #if 0 | |
444 | /* skip nops (usually 1) 0 - is this */ | |
445 | while (start_pc < pc && read_memory_integer (start_pc, 4) == 0) | |
446 | start_pc += 4; | |
447 | #endif | |
448 | return start_pc; | |
449 | } | |
450 | ||
0f552c5f | 451 | static mips_extra_func_info_t |
bd5635a1 RP |
452 | heuristic_proc_desc(start_pc, limit_pc, next_frame) |
453 | CORE_ADDR start_pc, limit_pc; | |
9f9f94aa | 454 | struct frame_info *next_frame; |
bd5635a1 | 455 | { |
ac57e5ad | 456 | CORE_ADDR sp = read_next_frame_reg (next_frame, SP_REGNUM); |
bd5635a1 RP |
457 | CORE_ADDR cur_pc; |
458 | int frame_size; | |
459 | int has_frame_reg = 0; | |
e03c0cc6 | 460 | int reg30 = 0; /* Value of $r30. Used by gcc for frame-pointer */ |
bd5635a1 RP |
461 | unsigned long reg_mask = 0; |
462 | ||
463 | if (start_pc == 0) return NULL; | |
9f9f94aa SS |
464 | memset (&temp_proc_desc, '\0', sizeof(temp_proc_desc)); |
465 | memset (&temp_saved_regs, '\0', sizeof(struct frame_saved_regs)); | |
466 | PROC_LOW_ADDR (&temp_proc_desc) = start_pc; | |
a70dc898 | 467 | |
9f9f94aa SS |
468 | if (start_pc + 200 < limit_pc) |
469 | limit_pc = start_pc + 200; | |
bd5635a1 RP |
470 | restart: |
471 | frame_size = 0; | |
472 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += 4) { | |
34df79fc | 473 | char buf[4]; |
bd5635a1 RP |
474 | unsigned long word; |
475 | int status; | |
476 | ||
34df79fc JK |
477 | status = read_memory_nobpt (cur_pc, buf, 4); |
478 | if (status) memory_error (status, cur_pc); | |
479 | word = extract_unsigned_integer (buf, 4); | |
480 | ||
bd5635a1 RP |
481 | if ((word & 0xFFFF0000) == 0x27bd0000) /* addiu $sp,$sp,-i */ |
482 | frame_size += (-word) & 0xFFFF; | |
483 | else if ((word & 0xFFFF0000) == 0x23bd0000) /* addu $sp,$sp,-i */ | |
484 | frame_size += (-word) & 0xFFFF; | |
485 | else if ((word & 0xFFE00000) == 0xafa00000) { /* sw reg,offset($sp) */ | |
486 | int reg = (word & 0x001F0000) >> 16; | |
487 | reg_mask |= 1 << reg; | |
002a422b | 488 | temp_saved_regs.regs[reg] = sp + (word & 0xffff); |
bd5635a1 RP |
489 | } |
490 | else if ((word & 0xFFFF0000) == 0x27be0000) { /* addiu $30,$sp,size */ | |
002a422b JK |
491 | if ((word & 0xffff) != frame_size) |
492 | reg30 = sp + (word & 0xffff); | |
bd5635a1 RP |
493 | else if (!has_frame_reg) { |
494 | int alloca_adjust; | |
495 | has_frame_reg = 1; | |
496 | reg30 = read_next_frame_reg(next_frame, 30); | |
002a422b | 497 | alloca_adjust = reg30 - (sp + (word & 0xffff)); |
bd5635a1 RP |
498 | if (alloca_adjust > 0) { |
499 | /* FP > SP + frame_size. This may be because | |
e03c0cc6 | 500 | * of an alloca or somethings similar. |
bd5635a1 RP |
501 | * Fix sp to "pre-alloca" value, and try again. |
502 | */ | |
503 | sp += alloca_adjust; | |
504 | goto restart; | |
505 | } | |
506 | } | |
507 | } | |
508 | else if ((word & 0xFFE00000) == 0xafc00000) { /* sw reg,offset($30) */ | |
509 | int reg = (word & 0x001F0000) >> 16; | |
510 | reg_mask |= 1 << reg; | |
002a422b | 511 | temp_saved_regs.regs[reg] = reg30 + (word & 0xffff); |
bd5635a1 RP |
512 | } |
513 | } | |
514 | if (has_frame_reg) { | |
515 | PROC_FRAME_REG(&temp_proc_desc) = 30; | |
516 | PROC_FRAME_OFFSET(&temp_proc_desc) = 0; | |
517 | } | |
518 | else { | |
519 | PROC_FRAME_REG(&temp_proc_desc) = SP_REGNUM; | |
520 | PROC_FRAME_OFFSET(&temp_proc_desc) = frame_size; | |
521 | } | |
522 | PROC_REG_MASK(&temp_proc_desc) = reg_mask; | |
523 | PROC_PC_REG(&temp_proc_desc) = RA_REGNUM; | |
524 | return &temp_proc_desc; | |
525 | } | |
526 | ||
0f552c5f | 527 | static mips_extra_func_info_t |
9f9f94aa SS |
528 | find_proc_desc (pc, next_frame) |
529 | CORE_ADDR pc; | |
530 | struct frame_info *next_frame; | |
bd5635a1 RP |
531 | { |
532 | mips_extra_func_info_t proc_desc; | |
0f552c5f | 533 | struct block *b = block_for_pc(pc); |
48be4c35 JK |
534 | struct symbol *sym; |
535 | CORE_ADDR startaddr; | |
536 | ||
537 | find_pc_partial_function (pc, NULL, &startaddr, NULL); | |
538 | if (b == NULL) | |
539 | sym = NULL; | |
540 | else | |
541 | { | |
542 | if (startaddr > BLOCK_START (b)) | |
543 | /* This is the "pathological" case referred to in a comment in | |
544 | print_frame_info. It might be better to move this check into | |
545 | symbol reading. */ | |
546 | sym = NULL; | |
547 | else | |
548 | sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_NAMESPACE, | |
549 | 0, NULL); | |
550 | } | |
0f552c5f | 551 | |
e4dbd248 PS |
552 | /* If we never found a PDR for this function in symbol reading, then |
553 | examine prologues to find the information. */ | |
554 | if (sym && ((mips_extra_func_info_t) SYMBOL_VALUE (sym))->pdr.framereg == -1) | |
555 | sym = NULL; | |
556 | ||
0f552c5f | 557 | if (sym) |
bd5635a1 RP |
558 | { |
559 | /* IF this is the topmost frame AND | |
560 | * (this proc does not have debugging information OR | |
561 | * the PC is in the procedure prologue) | |
be772100 | 562 | * THEN create a "heuristic" proc_desc (by analyzing |
bd5635a1 RP |
563 | * the actual code) to replace the "official" proc_desc. |
564 | */ | |
9f9f94aa | 565 | proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); |
bd5635a1 RP |
566 | if (next_frame == NULL) { |
567 | struct symtab_and_line val; | |
568 | struct symbol *proc_symbol = | |
569 | PROC_DESC_IS_DUMMY(proc_desc) ? 0 : PROC_SYMBOL(proc_desc); | |
0f552c5f | 570 | |
bd5635a1 RP |
571 | if (proc_symbol) { |
572 | val = find_pc_line (BLOCK_START | |
573 | (SYMBOL_BLOCK_VALUE(proc_symbol)), | |
574 | 0); | |
575 | val.pc = val.end ? val.end : pc; | |
576 | } | |
577 | if (!proc_symbol || pc < val.pc) { | |
578 | mips_extra_func_info_t found_heuristic = | |
9f9f94aa SS |
579 | heuristic_proc_desc (PROC_LOW_ADDR (proc_desc), |
580 | pc, next_frame); | |
581 | if (found_heuristic) | |
582 | proc_desc = found_heuristic; | |
bd5635a1 RP |
583 | } |
584 | } | |
585 | } | |
586 | else | |
587 | { | |
0f552c5f JG |
588 | /* Is linked_proc_desc_table really necessary? It only seems to be used |
589 | by procedure call dummys. However, the procedures being called ought | |
590 | to have their own proc_descs, and even if they don't, | |
591 | heuristic_proc_desc knows how to create them! */ | |
592 | ||
bd5635a1 | 593 | register struct linked_proc_info *link; |
9f9f94aa | 594 | |
bd5635a1 | 595 | for (link = linked_proc_desc_table; link; link = link->next) |
9f9f94aa SS |
596 | if (PROC_LOW_ADDR(&link->info) <= pc |
597 | && PROC_HIGH_ADDR(&link->info) > pc) | |
598 | return &link->info; | |
23d35572 | 599 | |
48be4c35 JK |
600 | if (startaddr == 0) |
601 | startaddr = heuristic_proc_start (pc); | |
602 | ||
bd5635a1 | 603 | proc_desc = |
48be4c35 | 604 | heuristic_proc_desc (startaddr, pc, next_frame); |
bd5635a1 RP |
605 | } |
606 | return proc_desc; | |
607 | } | |
608 | ||
609 | mips_extra_func_info_t cached_proc_desc; | |
610 | ||
9f9f94aa | 611 | CORE_ADDR |
0f552c5f | 612 | mips_frame_chain(frame) |
9f9f94aa | 613 | struct frame_info *frame; |
bd5635a1 | 614 | { |
bd5635a1 RP |
615 | mips_extra_func_info_t proc_desc; |
616 | CORE_ADDR saved_pc = FRAME_SAVED_PC(frame); | |
be772100 | 617 | |
0f552c5f JG |
618 | if (saved_pc == 0 || inside_entry_file (saved_pc)) |
619 | return 0; | |
620 | ||
bd5635a1 | 621 | proc_desc = find_proc_desc(saved_pc, frame); |
0f552c5f JG |
622 | if (!proc_desc) |
623 | return 0; | |
624 | ||
bd5635a1 | 625 | cached_proc_desc = proc_desc; |
e797b4bc JK |
626 | |
627 | /* If no frame pointer and frame size is zero, we must be at end | |
628 | of stack (or otherwise hosed). If we don't check frame size, | |
629 | we loop forever if we see a zero size frame. */ | |
630 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM | |
3f528883 | 631 | && PROC_FRAME_OFFSET (proc_desc) == 0 |
199b2450 TL |
632 | /* The previous frame from a sigtramp frame might be frameless |
633 | and have frame size zero. */ | |
634 | && !frame->signal_handler_caller) | |
bdef72d2 JK |
635 | return 0; |
636 | else | |
637 | return read_next_frame_reg(frame, PROC_FRAME_REG(proc_desc)) | |
638 | + PROC_FRAME_OFFSET(proc_desc); | |
bd5635a1 RP |
639 | } |
640 | ||
641 | void | |
642 | init_extra_frame_info(fci) | |
643 | struct frame_info *fci; | |
644 | { | |
bd5635a1 | 645 | /* Use proc_desc calculated in frame_chain */ |
ee5fb959 JK |
646 | mips_extra_func_info_t proc_desc = |
647 | fci->next ? cached_proc_desc : find_proc_desc(fci->pc, fci->next); | |
0f552c5f | 648 | |
70126bf9 | 649 | fci->saved_regs = NULL; |
bd5635a1 | 650 | fci->proc_desc = |
ee5fb959 | 651 | proc_desc == &temp_proc_desc ? 0 : proc_desc; |
bd5635a1 RP |
652 | if (proc_desc) |
653 | { | |
c2a0f1cb | 654 | /* Fixup frame-pointer - only needed for top frame */ |
5efd597b PS |
655 | /* This may not be quite right, if proc has a real frame register. |
656 | Get the value of the frame relative sp, procedure might have been | |
657 | interrupted by a signal at it's very start. */ | |
70126bf9 KH |
658 | if (fci->pc == PROC_LOW_ADDR (proc_desc) |
659 | && !PROC_DESC_IS_DUMMY (proc_desc)) | |
660 | fci->frame = read_next_frame_reg (fci->next, SP_REGNUM); | |
c2a0f1cb | 661 | else |
70126bf9 KH |
662 | fci->frame = |
663 | read_next_frame_reg (fci->next, PROC_FRAME_REG (proc_desc)) | |
664 | + PROC_FRAME_OFFSET (proc_desc); | |
bd5635a1 | 665 | |
48be4c35 | 666 | if (proc_desc == &temp_proc_desc) |
ee5fb959 | 667 | { |
70126bf9 KH |
668 | fci->saved_regs = (struct frame_saved_regs*) |
669 | obstack_alloc (&frame_cache_obstack, | |
670 | sizeof (struct frame_saved_regs)); | |
671 | *fci->saved_regs = temp_saved_regs; | |
672 | fci->saved_regs->regs[PC_REGNUM] = fci->saved_regs->regs[RA_REGNUM]; | |
ee5fb959 | 673 | } |
bd5635a1 RP |
674 | |
675 | /* hack: if argument regs are saved, guess these contain args */ | |
676 | if ((PROC_REG_MASK(proc_desc) & 0xF0) == 0) fci->num_args = -1; | |
677 | else if ((PROC_REG_MASK(proc_desc) & 0x80) == 0) fci->num_args = 4; | |
678 | else if ((PROC_REG_MASK(proc_desc) & 0x40) == 0) fci->num_args = 3; | |
679 | else if ((PROC_REG_MASK(proc_desc) & 0x20) == 0) fci->num_args = 2; | |
680 | else if ((PROC_REG_MASK(proc_desc) & 0x10) == 0) fci->num_args = 1; | |
bd5635a1 | 681 | } |
bd5635a1 RP |
682 | } |
683 | ||
a70dc898 RP |
684 | /* MIPS stack frames are almost impenetrable. When execution stops, |
685 | we basically have to look at symbol information for the function | |
686 | that we stopped in, which tells us *which* register (if any) is | |
687 | the base of the frame pointer, and what offset from that register | |
688 | the frame itself is at. | |
689 | ||
690 | This presents a problem when trying to examine a stack in memory | |
691 | (that isn't executing at the moment), using the "frame" command. We | |
692 | don't have a PC, nor do we have any registers except SP. | |
693 | ||
694 | This routine takes two arguments, SP and PC, and tries to make the | |
695 | cached frames look as if these two arguments defined a frame on the | |
696 | cache. This allows the rest of info frame to extract the important | |
697 | arguments without difficulty. */ | |
698 | ||
9f9f94aa | 699 | struct frame_info * |
c2a0f1cb ILT |
700 | setup_arbitrary_frame (argc, argv) |
701 | int argc; | |
9f9f94aa | 702 | CORE_ADDR *argv; |
a70dc898 | 703 | { |
c2a0f1cb ILT |
704 | if (argc != 2) |
705 | error ("MIPS frame specifications require two arguments: sp and pc"); | |
706 | ||
707 | return create_new_frame (argv[0], argv[1]); | |
a70dc898 RP |
708 | } |
709 | ||
bd5635a1 | 710 | |
0f552c5f JG |
711 | CORE_ADDR |
712 | mips_push_arguments(nargs, args, sp, struct_return, struct_addr) | |
bd5635a1 | 713 | int nargs; |
ac57e5ad | 714 | value_ptr *args; |
bd5635a1 RP |
715 | CORE_ADDR sp; |
716 | int struct_return; | |
717 | CORE_ADDR struct_addr; | |
718 | { | |
bd5635a1 | 719 | register i; |
70126bf9 | 720 | int accumulate_size = struct_return ? MIPS_REGSIZE : 0; |
bd5635a1 RP |
721 | struct mips_arg { char *contents; int len; int offset; }; |
722 | struct mips_arg *mips_args = | |
70126bf9 | 723 | (struct mips_arg*)alloca((nargs + 4) * sizeof(struct mips_arg)); |
bd5635a1 | 724 | register struct mips_arg *m_arg; |
70126bf9 KH |
725 | int fake_args = 0; |
726 | ||
bd5635a1 | 727 | for (i = 0, m_arg = mips_args; i < nargs; i++, m_arg++) { |
e4dbd248 | 728 | value_ptr arg = args[i]; |
bd5635a1 RP |
729 | m_arg->len = TYPE_LENGTH (VALUE_TYPE (arg)); |
730 | /* This entire mips-specific routine is because doubles must be aligned | |
731 | * on 8-byte boundaries. It still isn't quite right, because MIPS decided | |
732 | * to align 'struct {int a, b}' on 4-byte boundaries (even though this | |
733 | * breaks their varargs implementation...). A correct solution | |
734 | * requires an simulation of gcc's 'alignof' (and use of 'alignof' | |
735 | * in stdarg.h/varargs.h). | |
70126bf9 KH |
736 | * On the 64 bit r4000 we always pass the first four arguments |
737 | * using eight bytes each, so that we can load them up correctly | |
738 | * in CALL_DUMMY. | |
bd5635a1 | 739 | */ |
70126bf9 KH |
740 | if (m_arg->len > 4) |
741 | accumulate_size = (accumulate_size + 7) & -8; | |
bd5635a1 | 742 | m_arg->offset = accumulate_size; |
bd5635a1 | 743 | m_arg->contents = VALUE_CONTENTS(arg); |
9f9f94aa SS |
744 | if (! GDB_TARGET_IS_MIPS64) |
745 | accumulate_size = (accumulate_size + m_arg->len + 3) & -4; | |
70126bf9 KH |
746 | else |
747 | { | |
9f9f94aa SS |
748 | if (accumulate_size >= 4 * MIPS_REGSIZE) |
749 | accumulate_size = (accumulate_size + m_arg->len + 3) &~ 4; | |
750 | else | |
70126bf9 | 751 | { |
9f9f94aa SS |
752 | static char zeroes[8] = { 0 }; |
753 | int len = m_arg->len; | |
754 | ||
755 | if (len < 8) | |
756 | { | |
757 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
758 | m_arg->offset += 8 - len; | |
759 | ++m_arg; | |
760 | m_arg->len = 8 - len; | |
761 | m_arg->contents = zeroes; | |
762 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
763 | m_arg->offset = accumulate_size; | |
764 | else | |
765 | m_arg->offset = accumulate_size + len; | |
766 | ++fake_args; | |
767 | } | |
768 | accumulate_size = (accumulate_size + len + 7) & ~8; | |
70126bf9 | 769 | } |
70126bf9 | 770 | } |
bd5635a1 RP |
771 | } |
772 | accumulate_size = (accumulate_size + 7) & (-8); | |
70126bf9 KH |
773 | if (accumulate_size < 4 * MIPS_REGSIZE) |
774 | accumulate_size = 4 * MIPS_REGSIZE; | |
bd5635a1 | 775 | sp -= accumulate_size; |
70126bf9 | 776 | for (i = nargs + fake_args; m_arg--, --i >= 0; ) |
bd5635a1 | 777 | write_memory(sp + m_arg->offset, m_arg->contents, m_arg->len); |
5efd597b PS |
778 | if (struct_return) |
779 | { | |
780 | char buf[TARGET_PTR_BIT / HOST_CHAR_BIT]; | |
781 | ||
782 | store_address (buf, sizeof buf, struct_addr); | |
783 | write_memory (sp, buf, sizeof buf); | |
784 | } | |
bd5635a1 RP |
785 | return sp; |
786 | } | |
787 | ||
788 | /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<31. */ | |
e03c0cc6 | 789 | #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1)) |
bd5635a1 RP |
790 | |
791 | void | |
792 | mips_push_dummy_frame() | |
793 | { | |
5efd597b | 794 | char buffer[MAX_REGISTER_RAW_SIZE]; |
bd5635a1 RP |
795 | int ireg; |
796 | struct linked_proc_info *link = (struct linked_proc_info*) | |
797 | xmalloc(sizeof(struct linked_proc_info)); | |
798 | mips_extra_func_info_t proc_desc = &link->info; | |
799 | CORE_ADDR sp = read_register (SP_REGNUM); | |
800 | CORE_ADDR save_address; | |
bd5635a1 RP |
801 | link->next = linked_proc_desc_table; |
802 | linked_proc_desc_table = link; | |
803 | #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */ | |
804 | #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<31) | |
805 | #define GEN_REG_SAVE_COUNT 22 | |
806 | #define FLOAT_REG_SAVE_MASK MASK(0,19) | |
807 | #define FLOAT_REG_SAVE_COUNT 20 | |
e4dbd248 PS |
808 | #define FLOAT_SINGLE_REG_SAVE_MASK \ |
809 | ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0)) | |
810 | #define FLOAT_SINGLE_REG_SAVE_COUNT 10 | |
bd5635a1 RP |
811 | #define SPECIAL_REG_SAVE_COUNT 4 |
812 | /* | |
813 | * The registers we must save are all those not preserved across | |
814 | * procedure calls. Dest_Reg (see tm-mips.h) must also be saved. | |
815 | * In addition, we must save the PC, and PUSH_FP_REGNUM. | |
816 | * (Ideally, we should also save MDLO/-HI and FP Control/Status reg.) | |
817 | * | |
818 | * Dummy frame layout: | |
819 | * (high memory) | |
820 | * Saved PC | |
821 | * Saved MMHI, MMLO, FPC_CSR | |
822 | * Saved R31 | |
823 | * Saved R28 | |
824 | * ... | |
825 | * Saved R1 | |
826 | * Saved D18 (i.e. F19, F18) | |
827 | * ... | |
828 | * Saved D0 (i.e. F1, F0) | |
c2a0f1cb | 829 | * CALL_DUMMY (subroutine stub; see tm-mips.h) |
bd5635a1 RP |
830 | * Parameter build area (not yet implemented) |
831 | * (low memory) | |
832 | */ | |
833 | PROC_REG_MASK(proc_desc) = GEN_REG_SAVE_MASK; | |
e4dbd248 PS |
834 | switch (mips_fpu) |
835 | { | |
836 | case MIPS_FPU_DOUBLE: | |
837 | PROC_FREG_MASK(proc_desc) = FLOAT_REG_SAVE_MASK; | |
838 | break; | |
839 | case MIPS_FPU_SINGLE: | |
840 | PROC_FREG_MASK(proc_desc) = FLOAT_SINGLE_REG_SAVE_MASK; | |
841 | break; | |
842 | case MIPS_FPU_NONE: | |
843 | PROC_FREG_MASK(proc_desc) = 0; | |
844 | break; | |
845 | } | |
bd5635a1 RP |
846 | PROC_REG_OFFSET(proc_desc) = /* offset of (Saved R31) from FP */ |
847 | -sizeof(long) - 4 * SPECIAL_REG_SAVE_COUNT; | |
848 | PROC_FREG_OFFSET(proc_desc) = /* offset of (Saved D18) from FP */ | |
849 | -sizeof(double) - 4 * (SPECIAL_REG_SAVE_COUNT + GEN_REG_SAVE_COUNT); | |
850 | /* save general registers */ | |
851 | save_address = sp + PROC_REG_OFFSET(proc_desc); | |
852 | for (ireg = 32; --ireg >= 0; ) | |
853 | if (PROC_REG_MASK(proc_desc) & (1 << ireg)) | |
854 | { | |
3fed1c4a JK |
855 | read_register_gen (ireg, buffer); |
856 | ||
857 | /* Need to fix the save_address decrement below, and also make sure | |
858 | that we don't run into problems with the size of the dummy frame | |
859 | or any of the offsets within it. */ | |
860 | if (REGISTER_RAW_SIZE (ireg) > 4) | |
861 | error ("Cannot call functions on mips64"); | |
862 | ||
5efd597b | 863 | write_memory (save_address, buffer, REGISTER_RAW_SIZE (ireg)); |
bd5635a1 RP |
864 | save_address -= 4; |
865 | } | |
0b0d6c3f PS |
866 | /* save floating-points registers starting with high order word */ |
867 | save_address = sp + PROC_FREG_OFFSET(proc_desc) + 4; | |
bd5635a1 RP |
868 | for (ireg = 32; --ireg >= 0; ) |
869 | if (PROC_FREG_MASK(proc_desc) & (1 << ireg)) | |
870 | { | |
3fed1c4a JK |
871 | read_register_gen (ireg + FP0_REGNUM, buffer); |
872 | ||
873 | if (REGISTER_RAW_SIZE (ireg + FP0_REGNUM) > 4) | |
874 | error ("Cannot call functions on mips64"); | |
875 | ||
876 | write_memory (save_address, buffer, | |
877 | REGISTER_RAW_SIZE (ireg + FP0_REGNUM)); | |
bd5635a1 RP |
878 | save_address -= 4; |
879 | } | |
880 | write_register (PUSH_FP_REGNUM, sp); | |
881 | PROC_FRAME_REG(proc_desc) = PUSH_FP_REGNUM; | |
882 | PROC_FRAME_OFFSET(proc_desc) = 0; | |
3fed1c4a | 883 | read_register_gen (PC_REGNUM, buffer); |
5efd597b | 884 | write_memory (sp - 4, buffer, REGISTER_RAW_SIZE (PC_REGNUM)); |
3fed1c4a | 885 | read_register_gen (HI_REGNUM, buffer); |
5efd597b | 886 | write_memory (sp - 8, buffer, REGISTER_RAW_SIZE (HI_REGNUM)); |
3fed1c4a | 887 | read_register_gen (LO_REGNUM, buffer); |
5efd597b | 888 | write_memory (sp - 12, buffer, REGISTER_RAW_SIZE (LO_REGNUM)); |
e4dbd248 | 889 | if (mips_fpu != MIPS_FPU_NONE) |
3fed1c4a JK |
890 | read_register_gen (FCRCS_REGNUM, buffer); |
891 | else | |
892 | memset (buffer, 0, REGISTER_RAW_SIZE (FCRCS_REGNUM)); | |
5efd597b | 893 | write_memory (sp - 16, buffer, REGISTER_RAW_SIZE (FCRCS_REGNUM)); |
e4dbd248 PS |
894 | sp -= 4 * (GEN_REG_SAVE_COUNT + SPECIAL_REG_SAVE_COUNT); |
895 | if (mips_fpu == MIPS_FPU_DOUBLE) | |
896 | sp -= 4 * FLOAT_REG_SAVE_COUNT; | |
897 | else if (mips_fpu == MIPS_FPU_SINGLE) | |
898 | sp -= 4 * FLOAT_SINGLE_REG_SAVE_COUNT; | |
bd5635a1 RP |
899 | write_register (SP_REGNUM, sp); |
900 | PROC_LOW_ADDR(proc_desc) = sp - CALL_DUMMY_SIZE + CALL_DUMMY_START_OFFSET; | |
901 | PROC_HIGH_ADDR(proc_desc) = sp; | |
902 | SET_PROC_DESC_IS_DUMMY(proc_desc); | |
903 | PROC_PC_REG(proc_desc) = RA_REGNUM; | |
904 | } | |
905 | ||
906 | void | |
907 | mips_pop_frame() | |
dac4929a SG |
908 | { |
909 | register int regnum; | |
9f9f94aa SS |
910 | struct frame_info *frame = get_current_frame (); |
911 | CORE_ADDR new_sp = FRAME_FP (frame); | |
dac4929a | 912 | |
a70dc898 | 913 | mips_extra_func_info_t proc_desc = frame->proc_desc; |
dac4929a SG |
914 | |
915 | write_register (PC_REGNUM, FRAME_SAVED_PC(frame)); | |
70126bf9 KH |
916 | if (frame->saved_regs == NULL) |
917 | mips_find_saved_regs (frame); | |
dac4929a SG |
918 | if (proc_desc) |
919 | { | |
920 | for (regnum = 32; --regnum >= 0; ) | |
921 | if (PROC_REG_MASK(proc_desc) & (1 << regnum)) | |
922 | write_register (regnum, | |
923 | read_memory_integer (frame->saved_regs->regs[regnum], | |
924 | 4)); | |
925 | for (regnum = 32; --regnum >= 0; ) | |
926 | if (PROC_FREG_MASK(proc_desc) & (1 << regnum)) | |
927 | write_register (regnum + FP0_REGNUM, | |
928 | read_memory_integer (frame->saved_regs->regs[regnum + FP0_REGNUM], 4)); | |
929 | } | |
930 | write_register (SP_REGNUM, new_sp); | |
931 | flush_cached_frames (); | |
dac4929a | 932 | |
199b2450 | 933 | if (proc_desc && PROC_DESC_IS_DUMMY(proc_desc)) |
bd5635a1 | 934 | { |
dac4929a SG |
935 | struct linked_proc_info *pi_ptr, *prev_ptr; |
936 | ||
937 | for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL; | |
938 | pi_ptr != NULL; | |
939 | prev_ptr = pi_ptr, pi_ptr = pi_ptr->next) | |
940 | { | |
941 | if (&pi_ptr->info == proc_desc) | |
942 | break; | |
943 | } | |
944 | ||
945 | if (pi_ptr == NULL) | |
946 | error ("Can't locate dummy extra frame info\n"); | |
947 | ||
948 | if (prev_ptr != NULL) | |
949 | prev_ptr->next = pi_ptr->next; | |
950 | else | |
951 | linked_proc_desc_table = pi_ptr->next; | |
952 | ||
953 | free (pi_ptr); | |
954 | ||
bd5635a1 RP |
955 | write_register (HI_REGNUM, read_memory_integer(new_sp - 8, 4)); |
956 | write_register (LO_REGNUM, read_memory_integer(new_sp - 12, 4)); | |
e4dbd248 | 957 | if (mips_fpu != MIPS_FPU_NONE) |
c2a0f1cb | 958 | write_register (FCRCS_REGNUM, read_memory_integer(new_sp - 16, 4)); |
bd5635a1 | 959 | } |
bd5635a1 RP |
960 | } |
961 | ||
0f552c5f | 962 | static void |
a70dc898 | 963 | mips_print_register (regnum, all) |
bd5635a1 RP |
964 | int regnum, all; |
965 | { | |
e4dbd248 | 966 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; |
bd5635a1 | 967 | |
48be4c35 JK |
968 | /* Get the data in raw format. */ |
969 | if (read_relative_register_raw_bytes (regnum, raw_buffer)) | |
970 | { | |
971 | printf_filtered ("%s: [Invalid]", reg_names[regnum]); | |
972 | return; | |
973 | } | |
974 | ||
975 | /* If an even floating pointer register, also print as double. */ | |
976 | if (regnum >= FP0_REGNUM && regnum < FP0_REGNUM+32 | |
e4dbd248 PS |
977 | && !((regnum-FP0_REGNUM) & 1)) |
978 | { | |
979 | char dbuffer[MAX_REGISTER_RAW_SIZE]; | |
48be4c35 | 980 | |
e4dbd248 PS |
981 | read_relative_register_raw_bytes (regnum, dbuffer); |
982 | read_relative_register_raw_bytes (regnum+1, dbuffer+4); | |
ac8cf67d | 983 | #ifdef REGISTER_CONVERT_TO_TYPE |
e4dbd248 | 984 | REGISTER_CONVERT_TO_TYPE(regnum, builtin_type_double, dbuffer); |
ac8cf67d | 985 | #endif |
e4dbd248 PS |
986 | printf_filtered ("(d%d: ", regnum-FP0_REGNUM); |
987 | val_print (builtin_type_double, dbuffer, 0, | |
988 | gdb_stdout, 0, 1, 0, Val_pretty_default); | |
989 | printf_filtered ("); "); | |
990 | } | |
199b2450 | 991 | fputs_filtered (reg_names[regnum], gdb_stdout); |
48be4c35 JK |
992 | |
993 | /* The problem with printing numeric register names (r26, etc.) is that | |
994 | the user can't use them on input. Probably the best solution is to | |
995 | fix it so that either the numeric or the funky (a2, etc.) names | |
996 | are accepted on input. */ | |
997 | if (regnum < 32) | |
998 | printf_filtered ("(r%d): ", regnum); | |
999 | else | |
1000 | printf_filtered (": "); | |
bd5635a1 | 1001 | |
48be4c35 | 1002 | /* If virtual format is floating, print it that way. */ |
ac57e5ad | 1003 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
48be4c35 | 1004 | val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, |
199b2450 | 1005 | gdb_stdout, 0, 1, 0, Val_pretty_default); |
48be4c35 JK |
1006 | /* Else print as integer in hex. */ |
1007 | else | |
ac57e5ad SS |
1008 | print_scalar_formatted (raw_buffer, REGISTER_VIRTUAL_TYPE (regnum), |
1009 | 'x', 0, gdb_stdout); | |
bd5635a1 RP |
1010 | } |
1011 | ||
d8b3b00e | 1012 | /* Replacement for generic do_registers_info. */ |
9f9f94aa | 1013 | |
0f552c5f | 1014 | void |
361bf6ee | 1015 | mips_do_registers_info (regnum, fpregs) |
bd5635a1 | 1016 | int regnum; |
361bf6ee | 1017 | int fpregs; |
bd5635a1 | 1018 | { |
9f9f94aa SS |
1019 | if (regnum != -1) |
1020 | { | |
1021 | if (*(reg_names[regnum]) == '\0') | |
1022 | error ("Not a valid register for the current processor type"); | |
1023 | ||
bd5635a1 RP |
1024 | mips_print_register (regnum, 0); |
1025 | printf_filtered ("\n"); | |
9f9f94aa SS |
1026 | } |
1027 | else | |
1028 | { | |
1029 | int did_newline; | |
1030 | ||
1031 | for (regnum = 0; regnum < NUM_REGS; ) | |
1032 | { | |
1033 | if (((!fpregs) && regnum >= FP0_REGNUM && regnum <= FCRIR_REGNUM) | |
1034 | || *(reg_names[regnum]) == '\0') | |
1035 | { | |
1036 | regnum++; | |
1037 | continue; | |
1038 | } | |
bd5635a1 RP |
1039 | mips_print_register (regnum, 1); |
1040 | regnum++; | |
9f9f94aa SS |
1041 | printf_filtered ("; "); |
1042 | did_newline = 0; | |
1043 | if ((regnum & 3) == 0) | |
1044 | { | |
1045 | printf_filtered ("\n"); | |
1046 | did_newline = 1; | |
1047 | } | |
1048 | } | |
1049 | if (!did_newline) | |
1050 | printf_filtered ("\n"); | |
1051 | } | |
bd5635a1 | 1052 | } |
9f9f94aa | 1053 | |
bd5635a1 RP |
1054 | /* Return number of args passed to a frame. described by FIP. |
1055 | Can return -1, meaning no way to tell. */ | |
1056 | ||
0f552c5f | 1057 | int |
9f9f94aa SS |
1058 | mips_frame_num_args (frame) |
1059 | struct frame_info *frame; | |
bd5635a1 | 1060 | { |
9f9f94aa SS |
1061 | #if 0 /* FIXME Use or lose this! */ |
1062 | struct chain_info_t *p; | |
bd5635a1 | 1063 | |
9f9f94aa SS |
1064 | p = mips_find_cached_frame (FRAME_FP (frame)); |
1065 | if (p->valid) | |
1066 | return p->the_info.numargs; | |
bd5635a1 | 1067 | #endif |
9f9f94aa | 1068 | return -1; |
bd5635a1 | 1069 | } |
407a8389 | 1070 | \f |
427fec5d | 1071 | /* Is this a branch with a delay slot? */ |
9f9f94aa | 1072 | |
b5aff268 JK |
1073 | static int is_delayed PARAMS ((unsigned long)); |
1074 | ||
ee5fb959 JK |
1075 | static int |
1076 | is_delayed (insn) | |
1077 | unsigned long insn; | |
1078 | { | |
1079 | int i; | |
1080 | for (i = 0; i < NUMOPCODES; ++i) | |
1081 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
1082 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
1083 | break; | |
427fec5d JK |
1084 | return (i < NUMOPCODES |
1085 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
1086 | | INSN_COND_BRANCH_DELAY | |
1087 | | INSN_COND_BRANCH_LIKELY))); | |
ee5fb959 | 1088 | } |
b5aff268 JK |
1089 | |
1090 | int | |
1091 | mips_step_skips_delay (pc) | |
1092 | CORE_ADDR pc; | |
1093 | { | |
1094 | char buf[4]; | |
1095 | ||
1096 | if (target_read_memory (pc, buf, 4) != 0) | |
1097 | /* If error reading memory, guess that it is not a delayed branch. */ | |
1098 | return 0; | |
1099 | return is_delayed (extract_unsigned_integer (buf, 4)); | |
1100 | } | |
ee5fb959 JK |
1101 | |
1102 | /* To skip prologues, I use this predicate. Returns either PC itself | |
1103 | if the code at PC does not look like a function prologue; otherwise | |
1104 | returns an address that (if we're lucky) follows the prologue. If | |
1105 | LENIENT, then we must skip everything which is involved in setting | |
1106 | up the frame (it's OK to skip more, just so long as we don't skip | |
1107 | anything which might clobber the registers which are being saved. | |
1108 | We must skip more in the case where part of the prologue is in the | |
1109 | delay slot of a non-prologue instruction). */ | |
bd5635a1 | 1110 | |
be772100 | 1111 | CORE_ADDR |
ee5fb959 | 1112 | mips_skip_prologue (pc, lenient) |
bd5635a1 | 1113 | CORE_ADDR pc; |
ee5fb959 | 1114 | int lenient; |
bd5635a1 | 1115 | { |
bd5635a1 | 1116 | unsigned long inst; |
d747e0af | 1117 | int offset; |
0b0d6c3f | 1118 | int seen_sp_adjust = 0; |
ac57e5ad | 1119 | int load_immediate_bytes = 0; |
bd5635a1 | 1120 | |
e157305c PS |
1121 | /* Skip the typical prologue instructions. These are the stack adjustment |
1122 | instruction and the instructions that save registers on the stack | |
1123 | or in the gcc frame. */ | |
ee5fb959 JK |
1124 | for (offset = 0; offset < 100; offset += 4) |
1125 | { | |
1126 | char buf[4]; | |
1127 | int status; | |
1128 | ||
1129 | status = read_memory_nobpt (pc + offset, buf, 4); | |
1130 | if (status) | |
1131 | memory_error (status, pc + offset); | |
1132 | inst = extract_unsigned_integer (buf, 4); | |
1133 | ||
002a422b | 1134 | #if 0 |
ee5fb959 JK |
1135 | if (lenient && is_delayed (inst)) |
1136 | continue; | |
002a422b | 1137 | #endif |
ee5fb959 | 1138 | |
e157305c | 1139 | if ((inst & 0xffff0000) == 0x27bd0000) /* addiu $sp,$sp,offset */ |
0b0d6c3f | 1140 | seen_sp_adjust = 1; |
ac57e5ad SS |
1141 | else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */ |
1142 | inst == 0x03a8e823) /* subu $sp,$sp,$t0 */ | |
1143 | seen_sp_adjust = 1; | |
e157305c PS |
1144 | else if ((inst & 0xFFE00000) == 0xAFA00000 && (inst & 0x001F0000)) |
1145 | continue; /* sw reg,n($sp) */ | |
1146 | /* reg != $zero */ | |
1147 | else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */ | |
1148 | continue; | |
1149 | else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000)) | |
1150 | /* sx reg,n($s8) */ | |
1151 | continue; /* reg != $zero */ | |
1d9489c1 JK |
1152 | |
1153 | /* move $s8,$sp. With different versions of gas this will be either | |
1154 | `addu $s8,$sp,$zero' or `or $s8,$sp,$zero'. Accept either. */ | |
1155 | else if (inst == 0x03A0F021 || inst == 0x03a0f025) | |
0b0d6c3f | 1156 | continue; |
1d9489c1 | 1157 | |
1b71de8e PS |
1158 | else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */ |
1159 | continue; | |
e03c0cc6 ILT |
1160 | else if ((inst & 0xffff0000) == 0x3c1c0000) /* lui $gp,n */ |
1161 | continue; | |
1162 | else if ((inst & 0xffff0000) == 0x279c0000) /* addiu $gp,$gp,n */ | |
1163 | continue; | |
1164 | else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
1165 | || inst == 0x033ce021) /* addu $gp,$t9,$gp */ | |
1166 | continue; | |
ac57e5ad SS |
1167 | /* The following instructions load $at or $t0 with an immediate |
1168 | value in preparation for a stack adjustment via | |
1169 | subu $sp,$sp,[$at,$t0]. These instructions could also initialize | |
1170 | a local variable, so we accept them only before a stack adjustment | |
1171 | instruction was seen. */ | |
1172 | else if (!seen_sp_adjust) | |
1173 | { | |
1174 | if ((inst & 0xffff0000) == 0x3c010000 || /* lui $at,n */ | |
1175 | (inst & 0xffff0000) == 0x3c080000) /* lui $t0,n */ | |
1176 | { | |
1177 | load_immediate_bytes += 4; | |
1178 | continue; | |
1179 | } | |
1180 | else if ((inst & 0xffff0000) == 0x34210000 || /* ori $at,$at,n */ | |
1181 | (inst & 0xffff0000) == 0x35080000 || /* ori $t0,$t0,n */ | |
1182 | (inst & 0xffff0000) == 0x34010000 || /* ori $at,$zero,n */ | |
1183 | (inst & 0xffff0000) == 0x34080000) /* ori $t0,$zero,n */ | |
1184 | { | |
1185 | load_immediate_bytes += 4; | |
1186 | continue; | |
1187 | } | |
1188 | else | |
1189 | break; | |
1190 | } | |
0b0d6c3f | 1191 | else |
ac57e5ad | 1192 | break; |
d747e0af | 1193 | } |
e157305c | 1194 | |
ac57e5ad SS |
1195 | /* In a frameless function, we might have incorrectly |
1196 | skipped some load immediate instructions. Undo the skipping | |
1197 | if the load immediate was not followed by a stack adjustment. */ | |
1198 | if (load_immediate_bytes && !seen_sp_adjust) | |
1199 | offset -= load_immediate_bytes; | |
1200 | return pc + offset; | |
bd5635a1 | 1201 | } |
c2a0f1cb | 1202 | |
002a422b JK |
1203 | #if 0 |
1204 | /* The lenient prologue stuff should be superceded by the code in | |
1205 | init_extra_frame_info which looks to see whether the stores mentioned | |
1206 | in the proc_desc have actually taken place. */ | |
1207 | ||
ee5fb959 JK |
1208 | /* Is address PC in the prologue (loosely defined) for function at |
1209 | STARTADDR? */ | |
1210 | ||
1211 | static int | |
1212 | mips_in_lenient_prologue (startaddr, pc) | |
1213 | CORE_ADDR startaddr; | |
1214 | CORE_ADDR pc; | |
1215 | { | |
1216 | CORE_ADDR end_prologue = mips_skip_prologue (startaddr, 1); | |
1217 | return pc >= startaddr && pc < end_prologue; | |
1218 | } | |
002a422b | 1219 | #endif |
ee5fb959 | 1220 | |
ac8cf67d PS |
1221 | /* Given a return value in `regbuf' with a type `valtype', |
1222 | extract and copy its value into `valbuf'. */ | |
1223 | void | |
1224 | mips_extract_return_value (valtype, regbuf, valbuf) | |
1225 | struct type *valtype; | |
1226 | char regbuf[REGISTER_BYTES]; | |
1227 | char *valbuf; | |
1228 | { | |
1229 | int regnum; | |
92a6d600 | 1230 | int offset = 0; |
ac8cf67d | 1231 | |
e4dbd248 PS |
1232 | regnum = 2; |
1233 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT | |
1234 | && (mips_fpu == MIPS_FPU_DOUBLE | |
1235 | || (mips_fpu == MIPS_FPU_SINGLE && TYPE_LENGTH (valtype) <= 4))) | |
1236 | regnum = FP0_REGNUM; | |
ac8cf67d | 1237 | |
92a6d600 PS |
1238 | if (TARGET_BYTE_ORDER == BIG_ENDIAN |
1239 | && TYPE_CODE (valtype) != TYPE_CODE_FLT | |
1240 | && TYPE_LENGTH (valtype) < REGISTER_RAW_SIZE (regnum)) | |
1241 | offset = REGISTER_RAW_SIZE (regnum) - TYPE_LENGTH (valtype); | |
1242 | ||
1243 | memcpy (valbuf, regbuf + REGISTER_BYTE (regnum) + offset, | |
1244 | TYPE_LENGTH (valtype)); | |
ac8cf67d PS |
1245 | #ifdef REGISTER_CONVERT_TO_TYPE |
1246 | REGISTER_CONVERT_TO_TYPE(regnum, valtype, valbuf); | |
1247 | #endif | |
1248 | } | |
1249 | ||
1250 | /* Given a return value in `regbuf' with a type `valtype', | |
1251 | write it's value into the appropriate register. */ | |
1252 | void | |
1253 | mips_store_return_value (valtype, valbuf) | |
1254 | struct type *valtype; | |
1255 | char *valbuf; | |
1256 | { | |
1257 | int regnum; | |
1258 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; | |
1259 | ||
e4dbd248 PS |
1260 | regnum = 2; |
1261 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT | |
1262 | && (mips_fpu == MIPS_FPU_DOUBLE | |
1263 | || (mips_fpu == MIPS_FPU_SINGLE && TYPE_LENGTH (valtype) <= 4))) | |
1264 | regnum = FP0_REGNUM; | |
1265 | ||
ac8cf67d PS |
1266 | memcpy(raw_buffer, valbuf, TYPE_LENGTH (valtype)); |
1267 | ||
1268 | #ifdef REGISTER_CONVERT_FROM_TYPE | |
1269 | REGISTER_CONVERT_FROM_TYPE(regnum, valtype, raw_buffer); | |
1270 | #endif | |
1271 | ||
1272 | write_register_bytes(REGISTER_BYTE (regnum), raw_buffer, TYPE_LENGTH (valtype)); | |
1273 | } | |
1274 | ||
e03c0cc6 ILT |
1275 | /* These exist in mdebugread.c. */ |
1276 | extern CORE_ADDR sigtramp_address, sigtramp_end; | |
1277 | extern void fixup_sigtramp PARAMS ((void)); | |
1278 | ||
1279 | /* Exported procedure: Is PC in the signal trampoline code */ | |
1280 | ||
1281 | int | |
1282 | in_sigtramp (pc, ignore) | |
1283 | CORE_ADDR pc; | |
1284 | char *ignore; /* function name */ | |
1285 | { | |
1286 | if (sigtramp_address == 0) | |
1287 | fixup_sigtramp (); | |
1288 | return (pc >= sigtramp_address && pc < sigtramp_end); | |
1289 | } | |
1290 | ||
e4dbd248 PS |
1291 | /* Command to set FPU type. mips_fpu_string will have been set to the |
1292 | user's argument. Set mips_fpu based on mips_fpu_string, and then | |
1293 | canonicalize mips_fpu_string. */ | |
1294 | ||
1295 | /*ARGSUSED*/ | |
1296 | static void | |
1297 | mips_set_fpu_command (args, from_tty, c) | |
1298 | char *args; | |
1299 | int from_tty; | |
1300 | struct cmd_list_element *c; | |
1301 | { | |
1302 | char *err = NULL; | |
1303 | ||
1304 | if (mips_fpu_string == NULL || *mips_fpu_string == '\0') | |
1305 | mips_fpu = MIPS_FPU_DOUBLE; | |
1306 | else if (strcasecmp (mips_fpu_string, "double") == 0 | |
1307 | || strcasecmp (mips_fpu_string, "on") == 0 | |
1308 | || strcasecmp (mips_fpu_string, "1") == 0 | |
1309 | || strcasecmp (mips_fpu_string, "yes") == 0) | |
1310 | mips_fpu = MIPS_FPU_DOUBLE; | |
1311 | else if (strcasecmp (mips_fpu_string, "none") == 0 | |
1312 | || strcasecmp (mips_fpu_string, "off") == 0 | |
1313 | || strcasecmp (mips_fpu_string, "0") == 0 | |
1314 | || strcasecmp (mips_fpu_string, "no") == 0) | |
1315 | mips_fpu = MIPS_FPU_NONE; | |
1316 | else if (strcasecmp (mips_fpu_string, "single") == 0) | |
1317 | mips_fpu = MIPS_FPU_SINGLE; | |
1318 | else | |
1319 | err = strsave (mips_fpu_string); | |
1320 | ||
1321 | if (mips_fpu_string != NULL) | |
1322 | free (mips_fpu_string); | |
1323 | ||
1324 | switch (mips_fpu) | |
1325 | { | |
1326 | case MIPS_FPU_DOUBLE: | |
1327 | mips_fpu_string = strsave ("double"); | |
1328 | break; | |
1329 | case MIPS_FPU_SINGLE: | |
1330 | mips_fpu_string = strsave ("single"); | |
1331 | break; | |
1332 | case MIPS_FPU_NONE: | |
1333 | mips_fpu_string = strsave ("none"); | |
1334 | break; | |
1335 | } | |
1336 | ||
1337 | if (err != NULL) | |
1338 | { | |
1339 | struct cleanup *cleanups = make_cleanup (free, err); | |
1340 | error ("Unknown FPU type `%s'. Use `double', `none', or `single'.", | |
1341 | err); | |
1342 | do_cleanups (cleanups); | |
1343 | } | |
1344 | } | |
1345 | ||
1346 | static void | |
1347 | mips_show_fpu_command (args, from_tty, c) | |
1348 | char *args; | |
1349 | int from_tty; | |
1350 | struct cmd_list_element *c; | |
1351 | { | |
1352 | } | |
1353 | ||
9f9f94aa SS |
1354 | /* Command to set the processor type. */ |
1355 | ||
1356 | void | |
1357 | mips_set_processor_type_command (args, from_tty) | |
1358 | char *args; | |
1359 | int from_tty; | |
1360 | { | |
1361 | int i; | |
1362 | ||
1363 | if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0') | |
1364 | { | |
1365 | printf_unfiltered ("The known MIPS processor types are as follows:\n\n"); | |
1366 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
1367 | printf_unfiltered ("%s\n", mips_processor_type_table[i].name); | |
1368 | ||
1369 | /* Restore the value. */ | |
1370 | tmp_mips_processor_type = strsave (mips_processor_type); | |
1371 | ||
1372 | return; | |
1373 | } | |
1374 | ||
1375 | if (!mips_set_processor_type (tmp_mips_processor_type)) | |
1376 | { | |
1377 | error ("Unknown processor type `%s'.", tmp_mips_processor_type); | |
1378 | /* Restore its value. */ | |
1379 | tmp_mips_processor_type = strsave (mips_processor_type); | |
1380 | } | |
1381 | } | |
1382 | ||
1383 | static void | |
1384 | mips_show_processor_type_command (args, from_tty) | |
1385 | char *args; | |
1386 | int from_tty; | |
1387 | { | |
1388 | } | |
1389 | ||
1390 | /* Modify the actual processor type. */ | |
1391 | ||
1392 | int | |
1393 | mips_set_processor_type (str) | |
1394 | char *str; | |
1395 | { | |
1396 | int i, j; | |
1397 | ||
1398 | if (str == NULL) | |
1d9489c1 | 1399 | return 0; |
9f9f94aa SS |
1400 | |
1401 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
1402 | { | |
1403 | if (strcasecmp (str, mips_processor_type_table[i].name) == 0) | |
1404 | { | |
1405 | mips_processor_type = str; | |
1406 | ||
1407 | for (j = 0; j < NUM_REGS; ++j) | |
1408 | reg_names[j] = mips_processor_type_table[i].regnames[j]; | |
1409 | ||
1410 | return 1; | |
1411 | ||
1412 | /* FIXME tweak fpu flag too */ | |
1413 | } | |
1414 | } | |
1415 | ||
1416 | return 0; | |
1417 | } | |
1418 | ||
1419 | /* Attempt to identify the particular processor model by reading the | |
1420 | processor id. */ | |
1421 | ||
1422 | char * | |
1423 | mips_read_processor_type () | |
1424 | { | |
1425 | int prid; | |
1426 | ||
1427 | prid = read_register (PRID_REGNUM); | |
1428 | ||
1429 | if (prid & ~0xf == 0x700) | |
1430 | return savestring ("r3041", strlen("r3041")); | |
1431 | ||
1432 | return NULL; | |
1433 | } | |
427fec5d JK |
1434 | |
1435 | /* Just like reinit_frame_cache, but with the right arguments to be | |
1436 | callable as an sfunc. */ | |
9f9f94aa | 1437 | |
427fec5d JK |
1438 | static void |
1439 | reinit_frame_cache_sfunc (args, from_tty, c) | |
1440 | char *args; | |
1441 | int from_tty; | |
1442 | struct cmd_list_element *c; | |
1443 | { | |
1444 | reinit_frame_cache (); | |
1445 | } | |
c2a0f1cb | 1446 | |
18b46e7c SS |
1447 | int |
1448 | gdb_print_insn_mips (memaddr, info) | |
1449 | bfd_vma memaddr; | |
1450 | disassemble_info *info; | |
1451 | { | |
1452 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
1453 | return print_insn_big_mips (memaddr, info); | |
1454 | else | |
1455 | return print_insn_little_mips (memaddr, info); | |
1456 | } | |
1457 | ||
c2a0f1cb ILT |
1458 | void |
1459 | _initialize_mips_tdep () | |
1460 | { | |
427fec5d JK |
1461 | struct cmd_list_element *c; |
1462 | ||
18b46e7c SS |
1463 | tm_print_insn = gdb_print_insn_mips; |
1464 | ||
427fec5d JK |
1465 | /* Let the user turn off floating point and set the fence post for |
1466 | heuristic_proc_start. */ | |
1467 | ||
e4dbd248 PS |
1468 | c = add_set_cmd ("mipsfpu", class_support, var_string_noescape, |
1469 | (char *) &mips_fpu_string, | |
1470 | "Set use of floating point coprocessor.\n\ | |
1471 | Set to `none' to avoid using floating point instructions when calling\n\ | |
1472 | functions or dealing with return values. Set to `single' to use only\n\ | |
1473 | single precision floating point as on the R4650. Set to `double' for\n\ | |
1474 | normal floating point support.", | |
1475 | &setlist); | |
1476 | c->function.sfunc = mips_set_fpu_command; | |
1477 | c = add_show_from_set (c, &showlist); | |
1478 | c->function.sfunc = mips_show_fpu_command; | |
1479 | ||
1480 | mips_fpu = MIPS_FPU_DOUBLE; | |
1481 | mips_fpu_string = strsave ("double"); | |
3127785a | 1482 | |
9f9f94aa SS |
1483 | c = add_set_cmd ("processor", class_support, var_string_noescape, |
1484 | (char *) &tmp_mips_processor_type, | |
1485 | "Set the type of MIPS processor in use.\n\ | |
1486 | Set this to be able to access processor-type-specific registers.\n\ | |
1487 | ", | |
1488 | &setlist); | |
1489 | c->function.cfunc = mips_set_processor_type_command; | |
1490 | c = add_show_from_set (c, &showlist); | |
1491 | c->function.cfunc = mips_show_processor_type_command; | |
1492 | ||
1493 | tmp_mips_processor_type = strsave (DEFAULT_MIPS_TYPE); | |
1494 | mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE), 0); | |
1495 | ||
bdef72d2 JK |
1496 | /* We really would like to have both "0" and "unlimited" work, but |
1497 | command.c doesn't deal with that. So make it a var_zinteger | |
1498 | because the user can always use "999999" or some such for unlimited. */ | |
1499 | c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger, | |
427fec5d JK |
1500 | (char *) &heuristic_fence_post, |
1501 | "\ | |
23d35572 JK |
1502 | Set the distance searched for the start of a function.\n\ |
1503 | If you are debugging a stripped executable, GDB needs to search through the\n\ | |
1504 | program for the start of a function. This command sets the distance of the\n\ | |
1505 | search. The only need to set it is when debugging a stripped executable.", | |
427fec5d JK |
1506 | &setlist); |
1507 | /* We need to throw away the frame cache when we set this, since it | |
1508 | might change our ability to get backtraces. */ | |
1509 | c->function.sfunc = reinit_frame_cache_sfunc; | |
1510 | add_show_from_set (c, &showlist); | |
c2a0f1cb | 1511 | } |