Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
cda5a58a | 3 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, |
1e698235 | 4 | 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. |
bf64bfd6 | 5 | |
c906108c SS |
6 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
7 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
8 | ||
c5aa993b | 9 | This file is part of GDB. |
c906108c | 10 | |
c5aa993b JM |
11 | This program is free software; you can redistribute it and/or modify |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2 of the License, or | |
14 | (at your option) any later version. | |
c906108c | 15 | |
c5aa993b JM |
16 | This program is distributed in the hope that it will be useful, |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
c906108c | 20 | |
c5aa993b JM |
21 | You should have received a copy of the GNU General Public License |
22 | along with this program; if not, write to the Free Software | |
23 | Foundation, Inc., 59 Temple Place - Suite 330, | |
24 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
25 | |
26 | #include "defs.h" | |
27 | #include "gdb_string.h" | |
5e2e9765 | 28 | #include "gdb_assert.h" |
c906108c SS |
29 | #include "frame.h" |
30 | #include "inferior.h" | |
31 | #include "symtab.h" | |
32 | #include "value.h" | |
33 | #include "gdbcmd.h" | |
34 | #include "language.h" | |
35 | #include "gdbcore.h" | |
36 | #include "symfile.h" | |
37 | #include "objfiles.h" | |
38 | #include "gdbtypes.h" | |
39 | #include "target.h" | |
28d069e6 | 40 | #include "arch-utils.h" |
4e052eda | 41 | #include "regcache.h" |
70f80edf | 42 | #include "osabi.h" |
d1973055 | 43 | #include "mips-tdep.h" |
fe898f56 | 44 | #include "block.h" |
a4b8ebc8 | 45 | #include "reggroups.h" |
c906108c | 46 | #include "opcode/mips.h" |
c2d11a7d JM |
47 | #include "elf/mips.h" |
48 | #include "elf-bfd.h" | |
2475bac3 | 49 | #include "symcat.h" |
a4b8ebc8 | 50 | #include "sim-regno.h" |
a89aa300 | 51 | #include "dis-asm.h" |
c906108c | 52 | |
e0f7ec59 | 53 | static void set_reg_offset (CORE_ADDR *saved_regs, int regnum, CORE_ADDR off); |
5bbcb741 | 54 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 55 | |
dd824b04 DJ |
56 | /* A useful bit in the CP0 status register (PS_REGNUM). */ |
57 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ | |
58 | #define ST0_FR (1 << 26) | |
59 | ||
b0069a17 AC |
60 | /* The sizes of floating point registers. */ |
61 | ||
62 | enum | |
63 | { | |
64 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
65 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
66 | }; | |
67 | ||
0dadbba0 | 68 | |
2e4ebe70 DJ |
69 | static const char *mips_abi_string; |
70 | ||
71 | static const char *mips_abi_strings[] = { | |
72 | "auto", | |
73 | "n32", | |
74 | "o32", | |
28d169de | 75 | "n64", |
2e4ebe70 DJ |
76 | "o64", |
77 | "eabi32", | |
78 | "eabi64", | |
79 | NULL | |
80 | }; | |
81 | ||
cce74817 | 82 | struct frame_extra_info |
c5aa993b JM |
83 | { |
84 | mips_extra_func_info_t proc_desc; | |
85 | int num_args; | |
86 | }; | |
cce74817 | 87 | |
d929b26f AC |
88 | /* Various MIPS ISA options (related to stack analysis) can be |
89 | overridden dynamically. Establish an enum/array for managing | |
90 | them. */ | |
91 | ||
53904c9e AC |
92 | static const char size_auto[] = "auto"; |
93 | static const char size_32[] = "32"; | |
94 | static const char size_64[] = "64"; | |
d929b26f | 95 | |
53904c9e | 96 | static const char *size_enums[] = { |
d929b26f AC |
97 | size_auto, |
98 | size_32, | |
99 | size_64, | |
a5ea2558 AC |
100 | 0 |
101 | }; | |
102 | ||
7a292a7a SS |
103 | /* Some MIPS boards don't support floating point while others only |
104 | support single-precision floating-point operations. See also | |
105 | FP_REGISTER_DOUBLE. */ | |
c906108c SS |
106 | |
107 | enum mips_fpu_type | |
c5aa993b JM |
108 | { |
109 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
110 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
111 | MIPS_FPU_NONE /* No floating point. */ | |
112 | }; | |
c906108c SS |
113 | |
114 | #ifndef MIPS_DEFAULT_FPU_TYPE | |
115 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
116 | #endif | |
117 | static int mips_fpu_type_auto = 1; | |
118 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 119 | |
9ace0497 | 120 | static int mips_debug = 0; |
7a292a7a | 121 | |
c2d11a7d JM |
122 | /* MIPS specific per-architecture information */ |
123 | struct gdbarch_tdep | |
124 | { | |
125 | /* from the elf header */ | |
126 | int elf_flags; | |
70f80edf | 127 | |
c2d11a7d | 128 | /* mips options */ |
0dadbba0 | 129 | enum mips_abi mips_abi; |
2e4ebe70 | 130 | enum mips_abi found_abi; |
c2d11a7d JM |
131 | enum mips_fpu_type mips_fpu_type; |
132 | int mips_last_arg_regnum; | |
133 | int mips_last_fp_arg_regnum; | |
a5ea2558 | 134 | int mips_default_saved_regsize; |
c2d11a7d | 135 | int mips_fp_register_double; |
d929b26f | 136 | int mips_default_stack_argsize; |
4014092b | 137 | int default_mask_address_p; |
719ec221 AC |
138 | /* Is the target using 64-bit raw integer registers but only |
139 | storing a left-aligned 32-bit value in each? */ | |
140 | int mips64_transfers_32bit_regs_p; | |
56cea623 AC |
141 | /* Indexes for various registers. IRIX and embedded have |
142 | different values. This contains the "public" fields. Don't | |
143 | add any that do not need to be public. */ | |
144 | const struct mips_regnum *regnum; | |
691c0433 AC |
145 | /* Register names table for the current register set. */ |
146 | const char **mips_processor_reg_names; | |
c2d11a7d JM |
147 | }; |
148 | ||
56cea623 AC |
149 | const struct mips_regnum * |
150 | mips_regnum (struct gdbarch *gdbarch) | |
151 | { | |
152 | return gdbarch_tdep (gdbarch)->regnum; | |
153 | } | |
154 | ||
155 | static int | |
156 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
157 | { | |
158 | return mips_regnum (gdbarch)->fp0 + 12; | |
159 | } | |
160 | ||
0dadbba0 | 161 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \ |
216a600b | 162 | || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64) |
c2d11a7d | 163 | |
c2d11a7d | 164 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 165 | |
c2d11a7d | 166 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 167 | |
c2d11a7d | 168 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) |
c2d11a7d | 169 | |
d929b26f AC |
170 | /* Return the currently configured (or set) saved register size. */ |
171 | ||
a5ea2558 | 172 | #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize) |
c2d11a7d | 173 | |
53904c9e | 174 | static const char *mips_saved_regsize_string = size_auto; |
d929b26f AC |
175 | |
176 | #define MIPS_SAVED_REGSIZE (mips_saved_regsize()) | |
177 | ||
95404a3e AC |
178 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
179 | functions to test, set, or clear bit 0 of addresses. */ | |
180 | ||
181 | static CORE_ADDR | |
182 | is_mips16_addr (CORE_ADDR addr) | |
183 | { | |
184 | return ((addr) & 1); | |
185 | } | |
186 | ||
187 | static CORE_ADDR | |
188 | make_mips16_addr (CORE_ADDR addr) | |
189 | { | |
190 | return ((addr) | 1); | |
191 | } | |
192 | ||
193 | static CORE_ADDR | |
194 | unmake_mips16_addr (CORE_ADDR addr) | |
195 | { | |
196 | return ((addr) & ~1); | |
197 | } | |
198 | ||
22540ece AC |
199 | /* Return the contents of register REGNUM as a signed integer. */ |
200 | ||
201 | static LONGEST | |
202 | read_signed_register (int regnum) | |
203 | { | |
719ec221 | 204 | void *buf = alloca (register_size (current_gdbarch, regnum)); |
22540ece | 205 | deprecated_read_register_gen (regnum, buf); |
719ec221 | 206 | return (extract_signed_integer (buf, register_size (current_gdbarch, regnum))); |
22540ece AC |
207 | } |
208 | ||
209 | static LONGEST | |
210 | read_signed_register_pid (int regnum, ptid_t ptid) | |
211 | { | |
212 | ptid_t save_ptid; | |
213 | LONGEST retval; | |
214 | ||
215 | if (ptid_equal (ptid, inferior_ptid)) | |
216 | return read_signed_register (regnum); | |
217 | ||
218 | save_ptid = inferior_ptid; | |
219 | ||
220 | inferior_ptid = ptid; | |
221 | ||
222 | retval = read_signed_register (regnum); | |
223 | ||
224 | inferior_ptid = save_ptid; | |
225 | ||
226 | return retval; | |
227 | } | |
228 | ||
d1973055 KB |
229 | /* Return the MIPS ABI associated with GDBARCH. */ |
230 | enum mips_abi | |
231 | mips_abi (struct gdbarch *gdbarch) | |
232 | { | |
233 | return gdbarch_tdep (gdbarch)->mips_abi; | |
234 | } | |
235 | ||
4246e332 AC |
236 | int |
237 | mips_regsize (struct gdbarch *gdbarch) | |
238 | { | |
239 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word | |
240 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
241 | } | |
242 | ||
d929b26f | 243 | static unsigned int |
acdb74a0 | 244 | mips_saved_regsize (void) |
d929b26f AC |
245 | { |
246 | if (mips_saved_regsize_string == size_auto) | |
247 | return MIPS_DEFAULT_SAVED_REGSIZE; | |
248 | else if (mips_saved_regsize_string == size_64) | |
249 | return 8; | |
250 | else /* if (mips_saved_regsize_string == size_32) */ | |
251 | return 4; | |
252 | } | |
253 | ||
71b8ef93 | 254 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 255 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 256 | "info" field is used for this purpose. |
5a89d8aa MS |
257 | |
258 | ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special", | |
259 | i.e. refers to a 16-bit function, and sets a "special" bit in a | |
260 | minimal symbol to mark it as a 16-bit function | |
261 | ||
f594e5e9 | 262 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 263 | |
5a89d8aa MS |
264 | static void |
265 | mips_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym) | |
266 | { | |
267 | if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_MIPS16) | |
268 | { | |
269 | MSYMBOL_INFO (msym) = (char *) | |
270 | (((long) MSYMBOL_INFO (msym)) | 0x80000000); | |
271 | SYMBOL_VALUE_ADDRESS (msym) |= 1; | |
272 | } | |
273 | } | |
274 | ||
71b8ef93 MS |
275 | static int |
276 | msymbol_is_special (struct minimal_symbol *msym) | |
277 | { | |
278 | return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0); | |
279 | } | |
280 | ||
88658117 AC |
281 | /* XFER a value from the big/little/left end of the register. |
282 | Depending on the size of the value it might occupy the entire | |
283 | register or just part of it. Make an allowance for this, aligning | |
284 | things accordingly. */ | |
285 | ||
286 | static void | |
287 | mips_xfer_register (struct regcache *regcache, int reg_num, int length, | |
288 | enum bfd_endian endian, bfd_byte *in, const bfd_byte *out, | |
289 | int buf_offset) | |
290 | { | |
d9d9c31f | 291 | bfd_byte reg[MAX_REGISTER_SIZE]; |
88658117 | 292 | int reg_offset = 0; |
a4b8ebc8 | 293 | gdb_assert (reg_num >= NUM_REGS); |
cb1d2653 AC |
294 | /* Need to transfer the left or right part of the register, based on |
295 | the targets byte order. */ | |
88658117 AC |
296 | switch (endian) |
297 | { | |
298 | case BFD_ENDIAN_BIG: | |
719ec221 | 299 | reg_offset = register_size (current_gdbarch, reg_num) - length; |
88658117 AC |
300 | break; |
301 | case BFD_ENDIAN_LITTLE: | |
302 | reg_offset = 0; | |
303 | break; | |
304 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ | |
305 | reg_offset = 0; | |
306 | break; | |
307 | default: | |
308 | internal_error (__FILE__, __LINE__, "bad switch"); | |
309 | } | |
310 | if (mips_debug) | |
cb1d2653 AC |
311 | fprintf_unfiltered (gdb_stderr, |
312 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
313 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
314 | if (mips_debug && out != NULL) |
315 | { | |
316 | int i; | |
cb1d2653 | 317 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 318 | for (i = 0; i < length; i++) |
cb1d2653 | 319 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
320 | } |
321 | if (in != NULL) | |
a4b8ebc8 | 322 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, in + buf_offset); |
88658117 | 323 | if (out != NULL) |
a4b8ebc8 | 324 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, out + buf_offset); |
88658117 AC |
325 | if (mips_debug && in != NULL) |
326 | { | |
327 | int i; | |
cb1d2653 | 328 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 329 | for (i = 0; i < length; i++) |
cb1d2653 | 330 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
331 | } |
332 | if (mips_debug) | |
333 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
334 | } | |
335 | ||
dd824b04 DJ |
336 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
337 | compatiblity mode. A return value of 1 means that we have | |
338 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
339 | ||
340 | static int | |
341 | mips2_fp_compat (void) | |
342 | { | |
343 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not | |
344 | meaningful. */ | |
56cea623 | 345 | if (register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) == 4) |
dd824b04 DJ |
346 | return 0; |
347 | ||
348 | #if 0 | |
349 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
350 | in all the places we deal with FP registers. PR gdb/413. */ | |
351 | /* Otherwise check the FR bit in the status register - it controls | |
352 | the FP compatiblity mode. If it is clear we are in compatibility | |
353 | mode. */ | |
354 | if ((read_register (PS_REGNUM) & ST0_FR) == 0) | |
355 | return 1; | |
356 | #endif | |
361d1df0 | 357 | |
dd824b04 DJ |
358 | return 0; |
359 | } | |
360 | ||
c2d11a7d JM |
361 | /* Indicate that the ABI makes use of double-precision registers |
362 | provided by the FPU (rather than combining pairs of registers to | |
8fa9cfa1 | 363 | form double-precision values). See also MIPS_FPU_TYPE. */ |
c2d11a7d | 364 | #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double) |
c2d11a7d | 365 | |
d929b26f AC |
366 | /* The amount of space reserved on the stack for registers. This is |
367 | different to MIPS_SAVED_REGSIZE as it determines the alignment of | |
368 | data allocated after the registers have run out. */ | |
369 | ||
0dadbba0 | 370 | #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize) |
d929b26f AC |
371 | |
372 | #define MIPS_STACK_ARGSIZE (mips_stack_argsize ()) | |
373 | ||
53904c9e | 374 | static const char *mips_stack_argsize_string = size_auto; |
d929b26f AC |
375 | |
376 | static unsigned int | |
377 | mips_stack_argsize (void) | |
378 | { | |
379 | if (mips_stack_argsize_string == size_auto) | |
380 | return MIPS_DEFAULT_STACK_ARGSIZE; | |
381 | else if (mips_stack_argsize_string == size_64) | |
382 | return 8; | |
383 | else /* if (mips_stack_argsize_string == size_32) */ | |
384 | return 4; | |
385 | } | |
386 | ||
92e1c15c | 387 | #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p) |
92e1c15c | 388 | |
7a292a7a | 389 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 390 | |
570b8f7c AC |
391 | static mips_extra_func_info_t heuristic_proc_desc (CORE_ADDR, CORE_ADDR, |
392 | struct frame_info *, int); | |
c906108c | 393 | |
a14ed312 | 394 | static CORE_ADDR heuristic_proc_start (CORE_ADDR); |
c906108c | 395 | |
a14ed312 | 396 | static CORE_ADDR read_next_frame_reg (struct frame_info *, int); |
c906108c | 397 | |
a14ed312 | 398 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 399 | |
570b8f7c AC |
400 | static mips_extra_func_info_t find_proc_desc (CORE_ADDR pc, |
401 | struct frame_info *next_frame, | |
402 | int cur_frame); | |
c906108c | 403 | |
a14ed312 KB |
404 | static CORE_ADDR after_prologue (CORE_ADDR pc, |
405 | mips_extra_func_info_t proc_desc); | |
c906108c | 406 | |
67b2c998 DJ |
407 | static struct type *mips_float_register_type (void); |
408 | static struct type *mips_double_register_type (void); | |
409 | ||
acdb74a0 AC |
410 | /* The list of available "set mips " and "show mips " commands */ |
411 | ||
412 | static struct cmd_list_element *setmipscmdlist = NULL; | |
413 | static struct cmd_list_element *showmipscmdlist = NULL; | |
414 | ||
5e2e9765 KB |
415 | /* Integer registers 0 thru 31 are handled explicitly by |
416 | mips_register_name(). Processor specific registers 32 and above | |
691c0433 AC |
417 | are listed in the followign tables. */ |
418 | ||
419 | enum { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
420 | ||
421 | /* Generic MIPS. */ | |
422 | ||
423 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
424 | "sr", "lo", "hi", "bad", "cause","pc", | |
425 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
426 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
427 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
428 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
429 | "fsr", "fir", ""/*"fp"*/, "", | |
430 | "", "", "", "", "", "", "", "", | |
431 | "", "", "", "", "", "", "", "", | |
432 | }; | |
433 | ||
434 | /* Names of IDT R3041 registers. */ | |
435 | ||
436 | static const char *mips_r3041_reg_names[] = { | |
437 | "sr", "lo", "hi", "bad", "cause","pc", | |
438 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
439 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
440 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
441 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
442 | "fsr", "fir", "",/*"fp"*/ "", | |
443 | "", "", "bus", "ccfg", "", "", "", "", | |
444 | "", "", "port", "cmp", "", "", "epc", "prid", | |
445 | }; | |
446 | ||
447 | /* Names of tx39 registers. */ | |
448 | ||
449 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
450 | "sr", "lo", "hi", "bad", "cause","pc", | |
451 | "", "", "", "", "", "", "", "", | |
452 | "", "", "", "", "", "", "", "", | |
453 | "", "", "", "", "", "", "", "", | |
454 | "", "", "", "", "", "", "", "", | |
455 | "", "", "", "", | |
456 | "", "", "", "", "", "", "", "", | |
457 | "", "", "config", "cache", "debug", "depc", "epc", "" | |
458 | }; | |
459 | ||
460 | /* Names of IRIX registers. */ | |
461 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
462 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
463 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
464 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
465 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
466 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
467 | }; | |
468 | ||
cce74817 | 469 | |
5e2e9765 | 470 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 471 | static const char * |
5e2e9765 | 472 | mips_register_name (int regno) |
cce74817 | 473 | { |
691c0433 | 474 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
5e2e9765 KB |
475 | /* GPR names for all ABIs other than n32/n64. */ |
476 | static char *mips_gpr_names[] = { | |
477 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
478 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
479 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
480 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
481 | }; | |
482 | ||
483 | /* GPR names for n32 and n64 ABIs. */ | |
484 | static char *mips_n32_n64_gpr_names[] = { | |
485 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
486 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
487 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
488 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
489 | }; | |
490 | ||
491 | enum mips_abi abi = mips_abi (current_gdbarch); | |
492 | ||
a4b8ebc8 AC |
493 | /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then |
494 | don't make the raw register names visible. */ | |
495 | int rawnum = regno % NUM_REGS; | |
496 | if (regno < NUM_REGS) | |
497 | return ""; | |
498 | ||
5e2e9765 KB |
499 | /* The MIPS integer registers are always mapped from 0 to 31. The |
500 | names of the registers (which reflects the conventions regarding | |
501 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 502 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
503 | { |
504 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 505 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 506 | else |
a4b8ebc8 | 507 | return mips_gpr_names[rawnum]; |
5e2e9765 | 508 | } |
a4b8ebc8 | 509 | else if (32 <= rawnum && rawnum < NUM_REGS) |
691c0433 AC |
510 | { |
511 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
512 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
513 | } | |
5e2e9765 KB |
514 | else |
515 | internal_error (__FILE__, __LINE__, | |
a4b8ebc8 | 516 | "mips_register_name: bad register number %d", rawnum); |
cce74817 | 517 | } |
5e2e9765 | 518 | |
a4b8ebc8 | 519 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 520 | |
a4b8ebc8 AC |
521 | static int |
522 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
523 | struct reggroup *reggroup) | |
524 | { | |
525 | int vector_p; | |
526 | int float_p; | |
527 | int raw_p; | |
528 | int rawnum = regnum % NUM_REGS; | |
529 | int pseudo = regnum / NUM_REGS; | |
530 | if (reggroup == all_reggroup) | |
531 | return pseudo; | |
532 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
533 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
534 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
535 | (gdbarch), as not all architectures are multi-arch. */ | |
536 | raw_p = rawnum < NUM_REGS; | |
537 | if (REGISTER_NAME (regnum) == NULL | |
538 | || REGISTER_NAME (regnum)[0] == '\0') | |
539 | return 0; | |
540 | if (reggroup == float_reggroup) | |
541 | return float_p && pseudo; | |
542 | if (reggroup == vector_reggroup) | |
543 | return vector_p && pseudo; | |
544 | if (reggroup == general_reggroup) | |
545 | return (!vector_p && !float_p) && pseudo; | |
546 | /* Save the pseudo registers. Need to make certain that any code | |
547 | extracting register values from a saved register cache also uses | |
548 | pseudo registers. */ | |
549 | if (reggroup == save_reggroup) | |
550 | return raw_p && pseudo; | |
551 | /* Restore the same pseudo register. */ | |
552 | if (reggroup == restore_reggroup) | |
553 | return raw_p && pseudo; | |
554 | return 0; | |
555 | } | |
556 | ||
557 | /* Map the symbol table registers which live in the range [1 * | |
558 | NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw | |
47ebcfbe | 559 | registers. Take care of alignment and size problems. */ |
c5aa993b | 560 | |
a4b8ebc8 AC |
561 | static void |
562 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
563 | int cookednum, void *buf) | |
564 | { | |
47ebcfbe | 565 | int rawnum = cookednum % NUM_REGS; |
a4b8ebc8 | 566 | gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); |
47ebcfbe AC |
567 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
568 | return regcache_raw_read (regcache, rawnum, buf); | |
569 | else if (register_size (gdbarch, rawnum) > register_size (gdbarch, cookednum)) | |
570 | { | |
571 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
572 | || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
573 | regcache_raw_read_part (regcache, rawnum, 0, 4, buf); | |
574 | else | |
575 | regcache_raw_read_part (regcache, rawnum, 4, 4, buf); | |
576 | } | |
577 | else | |
578 | internal_error (__FILE__, __LINE__, "bad register size"); | |
a4b8ebc8 AC |
579 | } |
580 | ||
581 | static void | |
582 | mips_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
583 | int cookednum, const void *buf) | |
584 | { | |
47ebcfbe | 585 | int rawnum = cookednum % NUM_REGS; |
a4b8ebc8 | 586 | gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); |
47ebcfbe AC |
587 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
588 | return regcache_raw_write (regcache, rawnum, buf); | |
589 | else if (register_size (gdbarch, rawnum) > register_size (gdbarch, cookednum)) | |
590 | { | |
591 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
592 | || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
593 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); | |
594 | else | |
595 | regcache_raw_write_part (regcache, rawnum, 4, 4, buf); | |
596 | } | |
597 | else | |
598 | internal_error (__FILE__, __LINE__, "bad register size"); | |
a4b8ebc8 | 599 | } |
c5aa993b | 600 | |
c906108c | 601 | /* Table to translate MIPS16 register field to actual register number. */ |
c5aa993b JM |
602 | static int mips16_to_32_reg[8] = |
603 | {16, 17, 2, 3, 4, 5, 6, 7}; | |
c906108c SS |
604 | |
605 | /* Heuristic_proc_start may hunt through the text section for a long | |
606 | time across a 2400 baud serial line. Allows the user to limit this | |
607 | search. */ | |
608 | ||
609 | static unsigned int heuristic_fence_post = 0; | |
610 | ||
c5aa993b JM |
611 | #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ |
612 | #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */ | |
c906108c SS |
613 | #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) |
614 | #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) | |
615 | #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust) | |
616 | #define PROC_REG_MASK(proc) ((proc)->pdr.regmask) | |
617 | #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) | |
618 | #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) | |
619 | #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) | |
620 | #define PROC_PC_REG(proc) ((proc)->pdr.pcreg) | |
6c0d6680 DJ |
621 | /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long, |
622 | this will corrupt pdr.iline. Fortunately we don't use it. */ | |
c906108c SS |
623 | #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) |
624 | #define _PROC_MAGIC_ 0x0F0F0F0F | |
625 | #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_) | |
626 | #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_) | |
627 | ||
628 | struct linked_proc_info | |
c5aa993b JM |
629 | { |
630 | struct mips_extra_func_info info; | |
631 | struct linked_proc_info *next; | |
632 | } | |
633 | *linked_proc_desc_table = NULL; | |
c906108c | 634 | |
46cd78fb | 635 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
636 | register N. NOTE: This defines the pseudo register type so need to |
637 | rebuild the architecture vector. */ | |
43e526b9 JM |
638 | |
639 | static int mips64_transfers_32bit_regs_p = 0; | |
640 | ||
719ec221 AC |
641 | static void |
642 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
643 | struct cmd_list_element *c) | |
43e526b9 | 644 | { |
719ec221 AC |
645 | struct gdbarch_info info; |
646 | gdbarch_info_init (&info); | |
647 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
648 | instead of relying on globals. Doing that would let generic code | |
649 | handle the search for this specific architecture. */ | |
650 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 651 | { |
719ec221 AC |
652 | mips64_transfers_32bit_regs_p = 0; |
653 | error ("32-bit compatibility mode not supported"); | |
a4b8ebc8 | 654 | } |
a4b8ebc8 AC |
655 | } |
656 | ||
47ebcfbe | 657 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 658 | |
ff2e87ac AC |
659 | static int |
660 | mips_convert_register_p (int regnum, struct type *type) | |
661 | { | |
662 | return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
719ec221 | 663 | && register_size (current_gdbarch, regnum) == 4 |
56cea623 | 664 | && (regnum) >= mips_regnum (current_gdbarch)->fp0 && (regnum) < mips_regnum (current_gdbarch)->fp0 + 32 |
ff2e87ac AC |
665 | && TYPE_CODE(type) == TYPE_CODE_FLT |
666 | && TYPE_LENGTH(type) == 8); | |
667 | } | |
668 | ||
42c466d7 | 669 | static void |
ff2e87ac AC |
670 | mips_register_to_value (struct frame_info *frame, int regnum, |
671 | struct type *type, void *to) | |
102182a9 | 672 | { |
7f5f525d AC |
673 | get_frame_register (frame, regnum + 0, (char *) to + 4); |
674 | get_frame_register (frame, regnum + 1, (char *) to + 0); | |
102182a9 MS |
675 | } |
676 | ||
42c466d7 | 677 | static void |
ff2e87ac AC |
678 | mips_value_to_register (struct frame_info *frame, int regnum, |
679 | struct type *type, const void *from) | |
102182a9 | 680 | { |
ff2e87ac AC |
681 | put_frame_register (frame, regnum + 0, (const char *) from + 4); |
682 | put_frame_register (frame, regnum + 1, (const char *) from + 0); | |
102182a9 MS |
683 | } |
684 | ||
a4b8ebc8 AC |
685 | /* Return the GDB type object for the "standard" data type of data in |
686 | register REG. */ | |
78fde5f8 KB |
687 | |
688 | static struct type * | |
a4b8ebc8 AC |
689 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
690 | { | |
5ef80fb0 | 691 | gdb_assert (regnum >= 0 && regnum < 2 * NUM_REGS); |
56cea623 AC |
692 | if ((regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0 |
693 | && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32) | |
a6425924 | 694 | { |
5ef80fb0 AC |
695 | /* The floating-point registers raw, or cooked, always match |
696 | mips_regsize(), and also map 1:1, byte for byte. */ | |
697 | switch (gdbarch_byte_order (gdbarch)) | |
698 | { | |
699 | case BFD_ENDIAN_BIG: | |
700 | if (mips_regsize (gdbarch) == 4) | |
701 | return builtin_type_ieee_single_big; | |
702 | else | |
703 | return builtin_type_ieee_double_big; | |
704 | case BFD_ENDIAN_LITTLE: | |
705 | if (mips_regsize (gdbarch) == 4) | |
706 | return builtin_type_ieee_single_little; | |
707 | else | |
708 | return builtin_type_ieee_double_little; | |
709 | case BFD_ENDIAN_UNKNOWN: | |
710 | default: | |
711 | internal_error (__FILE__, __LINE__, "bad switch"); | |
712 | } | |
a6425924 | 713 | } |
56cea623 | 714 | else if (regnum >= (NUM_REGS + mips_regnum (current_gdbarch)->fp_control_status) |
5ef80fb0 AC |
715 | && regnum <= NUM_REGS + LAST_EMBED_REGNUM) |
716 | /* The pseudo/cooked view of the embedded registers is always | |
717 | 32-bit. The raw view is handled below. */ | |
718 | return builtin_type_int32; | |
719ec221 AC |
719 | else if (regnum >= NUM_REGS && mips_regsize (gdbarch) |
720 | && gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) | |
721 | /* The target, while using a 64-bit register buffer, is only | |
722 | transfering 32-bits of each integer register. Reflect this in | |
723 | the cooked/pseudo register value. */ | |
724 | return builtin_type_int32; | |
5ef80fb0 AC |
725 | else if (mips_regsize (gdbarch) == 8) |
726 | /* 64-bit ISA. */ | |
727 | return builtin_type_int64; | |
78fde5f8 | 728 | else |
5ef80fb0 AC |
729 | /* 32-bit ISA. */ |
730 | return builtin_type_int32; | |
78fde5f8 KB |
731 | } |
732 | ||
bcb0cc15 MS |
733 | /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */ |
734 | ||
735 | static CORE_ADDR | |
736 | mips_read_sp (void) | |
737 | { | |
e227b13c | 738 | return read_signed_register (SP_REGNUM); |
bcb0cc15 MS |
739 | } |
740 | ||
c906108c | 741 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 742 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
743 | |
744 | static int | |
745 | mips_mask_address_p (void) | |
746 | { | |
747 | switch (mask_address_var) | |
748 | { | |
7f19b9a2 | 749 | case AUTO_BOOLEAN_TRUE: |
4014092b | 750 | return 1; |
7f19b9a2 | 751 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
752 | return 0; |
753 | break; | |
7f19b9a2 | 754 | case AUTO_BOOLEAN_AUTO: |
92e1c15c | 755 | return MIPS_DEFAULT_MASK_ADDRESS_P; |
4014092b | 756 | default: |
8e65ff28 AC |
757 | internal_error (__FILE__, __LINE__, |
758 | "mips_mask_address_p: bad switch"); | |
4014092b | 759 | return -1; |
361d1df0 | 760 | } |
4014092b AC |
761 | } |
762 | ||
763 | static void | |
e9e68a56 | 764 | show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c) |
4014092b AC |
765 | { |
766 | switch (mask_address_var) | |
767 | { | |
7f19b9a2 | 768 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
769 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
770 | break; | |
7f19b9a2 | 771 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
772 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
773 | break; | |
7f19b9a2 | 774 | case AUTO_BOOLEAN_AUTO: |
4014092b AC |
775 | printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n", |
776 | mips_mask_address_p () ? "enabled" : "disabled"); | |
777 | break; | |
778 | default: | |
8e65ff28 AC |
779 | internal_error (__FILE__, __LINE__, |
780 | "show_mask_address: bad switch"); | |
4014092b | 781 | break; |
361d1df0 | 782 | } |
4014092b | 783 | } |
c906108c SS |
784 | |
785 | /* Should call_function allocate stack space for a struct return? */ | |
cb811fe7 | 786 | |
f7ab6ec6 | 787 | static int |
cb811fe7 | 788 | mips_eabi_use_struct_convention (int gcc_p, struct type *type) |
c906108c | 789 | { |
cb811fe7 MS |
790 | return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE); |
791 | } | |
792 | ||
8b389c40 MS |
793 | /* Should call_function pass struct by reference? |
794 | For each architecture, structs are passed either by | |
795 | value or by reference, depending on their size. */ | |
796 | ||
797 | static int | |
798 | mips_eabi_reg_struct_has_addr (int gcc_p, struct type *type) | |
799 | { | |
800 | enum type_code typecode = TYPE_CODE (check_typedef (type)); | |
801 | int len = TYPE_LENGTH (check_typedef (type)); | |
802 | ||
803 | if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
804 | return (len > MIPS_SAVED_REGSIZE); | |
805 | ||
806 | return 0; | |
807 | } | |
808 | ||
809 | static int | |
810 | mips_n32n64_reg_struct_has_addr (int gcc_p, struct type *type) | |
811 | { | |
812 | return 0; /* Assumption: N32/N64 never passes struct by ref. */ | |
813 | } | |
814 | ||
f7ab6ec6 | 815 | static int |
8b389c40 MS |
816 | mips_o32_reg_struct_has_addr (int gcc_p, struct type *type) |
817 | { | |
818 | return 0; /* Assumption: O32/O64 never passes struct by ref. */ | |
819 | } | |
820 | ||
c906108c SS |
821 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
822 | ||
823 | static int | |
824 | pc_is_mips16 (bfd_vma memaddr) | |
825 | { | |
826 | struct minimal_symbol *sym; | |
827 | ||
828 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
95404a3e | 829 | if (is_mips16_addr (memaddr)) |
c906108c SS |
830 | return 1; |
831 | ||
832 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
833 | the high bit of the info field. Use this to decide if the function is | |
834 | MIPS16 or normal MIPS. */ | |
835 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
836 | if (sym) | |
71b8ef93 | 837 | return msymbol_is_special (sym); |
c906108c SS |
838 | else |
839 | return 0; | |
840 | } | |
841 | ||
6c997a34 AC |
842 | /* MIPS believes that the PC has a sign extended value. Perhaphs the |
843 | all registers should be sign extended for simplicity? */ | |
844 | ||
845 | static CORE_ADDR | |
39f77062 | 846 | mips_read_pc (ptid_t ptid) |
6c997a34 | 847 | { |
39f77062 | 848 | return read_signed_register_pid (PC_REGNUM, ptid); |
6c997a34 | 849 | } |
c906108c SS |
850 | |
851 | /* This returns the PC of the first inst after the prologue. If we can't | |
852 | find the prologue, then return 0. */ | |
853 | ||
854 | static CORE_ADDR | |
acdb74a0 AC |
855 | after_prologue (CORE_ADDR pc, |
856 | mips_extra_func_info_t proc_desc) | |
c906108c SS |
857 | { |
858 | struct symtab_and_line sal; | |
859 | CORE_ADDR func_addr, func_end; | |
860 | ||
479412cd DJ |
861 | /* Pass cur_frame == 0 to find_proc_desc. We should not attempt |
862 | to read the stack pointer from the current machine state, because | |
863 | the current machine state has nothing to do with the information | |
864 | we need from the proc_desc; and the process may or may not exist | |
865 | right now. */ | |
c906108c | 866 | if (!proc_desc) |
479412cd | 867 | proc_desc = find_proc_desc (pc, NULL, 0); |
c906108c SS |
868 | |
869 | if (proc_desc) | |
870 | { | |
871 | /* If function is frameless, then we need to do it the hard way. I | |
c5aa993b | 872 | strongly suspect that frameless always means prologueless... */ |
c906108c SS |
873 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM |
874 | && PROC_FRAME_OFFSET (proc_desc) == 0) | |
875 | return 0; | |
876 | } | |
877 | ||
878 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
879 | return 0; /* Unknown */ | |
880 | ||
881 | sal = find_pc_line (func_addr, 0); | |
882 | ||
883 | if (sal.end < func_end) | |
884 | return sal.end; | |
885 | ||
886 | /* The line after the prologue is after the end of the function. In this | |
887 | case, tell the caller to find the prologue the hard way. */ | |
888 | ||
889 | return 0; | |
890 | } | |
891 | ||
892 | /* Decode a MIPS32 instruction that saves a register in the stack, and | |
893 | set the appropriate bit in the general register mask or float register mask | |
894 | to indicate which register is saved. This is a helper function | |
895 | for mips_find_saved_regs. */ | |
896 | ||
897 | static void | |
acdb74a0 AC |
898 | mips32_decode_reg_save (t_inst inst, unsigned long *gen_mask, |
899 | unsigned long *float_mask) | |
c906108c SS |
900 | { |
901 | int reg; | |
902 | ||
903 | if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */ | |
904 | || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */ | |
905 | || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */ | |
906 | { | |
907 | /* It might be possible to use the instruction to | |
c5aa993b JM |
908 | find the offset, rather than the code below which |
909 | is based on things being in a certain order in the | |
910 | frame, but figuring out what the instruction's offset | |
911 | is relative to might be a little tricky. */ | |
c906108c SS |
912 | reg = (inst & 0x001f0000) >> 16; |
913 | *gen_mask |= (1 << reg); | |
914 | } | |
915 | else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */ | |
c5aa993b JM |
916 | || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */ |
917 | || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */ | |
c906108c SS |
918 | |
919 | { | |
920 | reg = ((inst & 0x001f0000) >> 16); | |
921 | *float_mask |= (1 << reg); | |
922 | } | |
923 | } | |
924 | ||
925 | /* Decode a MIPS16 instruction that saves a register in the stack, and | |
926 | set the appropriate bit in the general register or float register mask | |
927 | to indicate which register is saved. This is a helper function | |
928 | for mips_find_saved_regs. */ | |
929 | ||
930 | static void | |
acdb74a0 | 931 | mips16_decode_reg_save (t_inst inst, unsigned long *gen_mask) |
c906108c | 932 | { |
c5aa993b | 933 | if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ |
c906108c SS |
934 | { |
935 | int reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
936 | *gen_mask |= (1 << reg); | |
937 | } | |
c5aa993b | 938 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ |
c906108c SS |
939 | { |
940 | int reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
941 | *gen_mask |= (1 << reg); | |
942 | } | |
c5aa993b | 943 | else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */ |
c906108c SS |
944 | || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ |
945 | *gen_mask |= (1 << RA_REGNUM); | |
946 | } | |
947 | ||
948 | ||
949 | /* Fetch and return instruction from the specified location. If the PC | |
950 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
951 | ||
952 | static t_inst | |
acdb74a0 | 953 | mips_fetch_instruction (CORE_ADDR addr) |
c906108c SS |
954 | { |
955 | char buf[MIPS_INSTLEN]; | |
956 | int instlen; | |
957 | int status; | |
958 | ||
959 | if (pc_is_mips16 (addr)) | |
960 | { | |
961 | instlen = MIPS16_INSTLEN; | |
95404a3e | 962 | addr = unmake_mips16_addr (addr); |
c906108c SS |
963 | } |
964 | else | |
c5aa993b | 965 | instlen = MIPS_INSTLEN; |
c906108c SS |
966 | status = read_memory_nobpt (addr, buf, instlen); |
967 | if (status) | |
968 | memory_error (status, addr); | |
969 | return extract_unsigned_integer (buf, instlen); | |
970 | } | |
971 | ||
972 | ||
973 | /* These the fields of 32 bit mips instructions */ | |
e135b889 DJ |
974 | #define mips32_op(x) (x >> 26) |
975 | #define itype_op(x) (x >> 26) | |
976 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 977 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 978 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 979 | |
e135b889 DJ |
980 | #define jtype_op(x) (x >> 26) |
981 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 982 | |
e135b889 DJ |
983 | #define rtype_op(x) (x >> 26) |
984 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
985 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
986 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
987 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
988 | #define rtype_funct(x) (x & 0x3f) | |
c906108c SS |
989 | |
990 | static CORE_ADDR | |
c5aa993b JM |
991 | mips32_relative_offset (unsigned long inst) |
992 | { | |
993 | long x; | |
994 | x = itype_immediate (inst); | |
995 | if (x & 0x8000) /* sign bit set */ | |
c906108c | 996 | { |
c5aa993b | 997 | x |= 0xffff0000; /* sign extension */ |
c906108c | 998 | } |
c5aa993b JM |
999 | x = x << 2; |
1000 | return x; | |
c906108c SS |
1001 | } |
1002 | ||
1003 | /* Determine whate to set a single step breakpoint while considering | |
1004 | branch prediction */ | |
5a89d8aa | 1005 | static CORE_ADDR |
c5aa993b JM |
1006 | mips32_next_pc (CORE_ADDR pc) |
1007 | { | |
1008 | unsigned long inst; | |
1009 | int op; | |
1010 | inst = mips_fetch_instruction (pc); | |
e135b889 | 1011 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 1012 | { |
e135b889 DJ |
1013 | if (itype_op (inst) >> 2 == 5) |
1014 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ | |
c5aa993b | 1015 | { |
e135b889 | 1016 | op = (itype_op (inst) & 0x03); |
c906108c SS |
1017 | switch (op) |
1018 | { | |
e135b889 DJ |
1019 | case 0: /* BEQL */ |
1020 | goto equal_branch; | |
1021 | case 1: /* BNEL */ | |
1022 | goto neq_branch; | |
1023 | case 2: /* BLEZL */ | |
1024 | goto less_branch; | |
1025 | case 3: /* BGTZ */ | |
1026 | goto greater_branch; | |
c5aa993b JM |
1027 | default: |
1028 | pc += 4; | |
c906108c SS |
1029 | } |
1030 | } | |
e135b889 DJ |
1031 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
1032 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ | |
1033 | { | |
1034 | int tf = itype_rt (inst) & 0x01; | |
1035 | int cnum = itype_rt (inst) >> 2; | |
56cea623 | 1036 | int fcrcs = read_signed_register (mips_regnum (current_gdbarch)->fp_control_status); |
e135b889 DJ |
1037 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); |
1038 | ||
1039 | if (((cond >> cnum) & 0x01) == tf) | |
1040 | pc += mips32_relative_offset (inst) + 4; | |
1041 | else | |
1042 | pc += 8; | |
1043 | } | |
c5aa993b JM |
1044 | else |
1045 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
1046 | } |
1047 | else | |
c5aa993b JM |
1048 | { /* This gets way messy */ |
1049 | ||
c906108c | 1050 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 1051 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 1052 | { |
c5aa993b JM |
1053 | case 0: /* SPECIAL */ |
1054 | op = rtype_funct (inst); | |
1055 | switch (op) | |
1056 | { | |
1057 | case 8: /* JR */ | |
1058 | case 9: /* JALR */ | |
6c997a34 AC |
1059 | /* Set PC to that address */ |
1060 | pc = read_signed_register (rtype_rs (inst)); | |
c5aa993b JM |
1061 | break; |
1062 | default: | |
1063 | pc += 4; | |
1064 | } | |
1065 | ||
e135b889 | 1066 | break; /* end SPECIAL */ |
c5aa993b | 1067 | case 1: /* REGIMM */ |
c906108c | 1068 | { |
e135b889 DJ |
1069 | op = itype_rt (inst); /* branch condition */ |
1070 | switch (op) | |
c906108c | 1071 | { |
c5aa993b | 1072 | case 0: /* BLTZ */ |
e135b889 DJ |
1073 | case 2: /* BLTZL */ |
1074 | case 16: /* BLTZAL */ | |
c5aa993b | 1075 | case 18: /* BLTZALL */ |
c906108c | 1076 | less_branch: |
6c997a34 | 1077 | if (read_signed_register (itype_rs (inst)) < 0) |
c5aa993b JM |
1078 | pc += mips32_relative_offset (inst) + 4; |
1079 | else | |
1080 | pc += 8; /* after the delay slot */ | |
1081 | break; | |
e135b889 | 1082 | case 1: /* BGEZ */ |
c5aa993b JM |
1083 | case 3: /* BGEZL */ |
1084 | case 17: /* BGEZAL */ | |
1085 | case 19: /* BGEZALL */ | |
c906108c | 1086 | greater_equal_branch: |
6c997a34 | 1087 | if (read_signed_register (itype_rs (inst)) >= 0) |
c5aa993b JM |
1088 | pc += mips32_relative_offset (inst) + 4; |
1089 | else | |
1090 | pc += 8; /* after the delay slot */ | |
1091 | break; | |
e135b889 | 1092 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1093 | default: |
1094 | pc += 4; | |
c906108c SS |
1095 | } |
1096 | } | |
e135b889 | 1097 | break; /* end REGIMM */ |
c5aa993b JM |
1098 | case 2: /* J */ |
1099 | case 3: /* JAL */ | |
1100 | { | |
1101 | unsigned long reg; | |
1102 | reg = jtype_target (inst) << 2; | |
e135b889 | 1103 | /* Upper four bits get never changed... */ |
c5aa993b | 1104 | pc = reg + ((pc + 4) & 0xf0000000); |
c906108c | 1105 | } |
c5aa993b JM |
1106 | break; |
1107 | /* FIXME case JALX : */ | |
1108 | { | |
1109 | unsigned long reg; | |
1110 | reg = jtype_target (inst) << 2; | |
1111 | pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */ | |
c906108c SS |
1112 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1113 | } | |
c5aa993b | 1114 | break; /* The new PC will be alternate mode */ |
e135b889 | 1115 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1116 | equal_branch: |
6c997a34 AC |
1117 | if (read_signed_register (itype_rs (inst)) == |
1118 | read_signed_register (itype_rt (inst))) | |
c5aa993b JM |
1119 | pc += mips32_relative_offset (inst) + 4; |
1120 | else | |
1121 | pc += 8; | |
1122 | break; | |
e135b889 | 1123 | case 5: /* BNE, BNEL */ |
c5aa993b | 1124 | neq_branch: |
6c997a34 | 1125 | if (read_signed_register (itype_rs (inst)) != |
e135b889 | 1126 | read_signed_register (itype_rt (inst))) |
c5aa993b JM |
1127 | pc += mips32_relative_offset (inst) + 4; |
1128 | else | |
1129 | pc += 8; | |
1130 | break; | |
e135b889 | 1131 | case 6: /* BLEZ, BLEZL */ |
c906108c | 1132 | less_zero_branch: |
6c997a34 | 1133 | if (read_signed_register (itype_rs (inst) <= 0)) |
c5aa993b JM |
1134 | pc += mips32_relative_offset (inst) + 4; |
1135 | else | |
1136 | pc += 8; | |
1137 | break; | |
1138 | case 7: | |
e135b889 DJ |
1139 | default: |
1140 | greater_branch: /* BGTZ, BGTZL */ | |
6c997a34 | 1141 | if (read_signed_register (itype_rs (inst) > 0)) |
c5aa993b JM |
1142 | pc += mips32_relative_offset (inst) + 4; |
1143 | else | |
1144 | pc += 8; | |
1145 | break; | |
c5aa993b JM |
1146 | } /* switch */ |
1147 | } /* else */ | |
1148 | return pc; | |
1149 | } /* mips32_next_pc */ | |
c906108c SS |
1150 | |
1151 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 1152 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
1153 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
1154 | We dont want to set a single step instruction on the extend instruction | |
1155 | either. | |
c5aa993b | 1156 | */ |
c906108c SS |
1157 | |
1158 | /* Lots of mips16 instruction formats */ | |
1159 | /* Predicting jumps requires itype,ritype,i8type | |
1160 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 1161 | */ |
c906108c SS |
1162 | enum mips16_inst_fmts |
1163 | { | |
c5aa993b JM |
1164 | itype, /* 0 immediate 5,10 */ |
1165 | ritype, /* 1 5,3,8 */ | |
1166 | rrtype, /* 2 5,3,3,5 */ | |
1167 | rritype, /* 3 5,3,3,5 */ | |
1168 | rrrtype, /* 4 5,3,3,3,2 */ | |
1169 | rriatype, /* 5 5,3,3,1,4 */ | |
1170 | shifttype, /* 6 5,3,3,3,2 */ | |
1171 | i8type, /* 7 5,3,8 */ | |
1172 | i8movtype, /* 8 5,3,3,5 */ | |
1173 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1174 | i64type, /* 10 5,3,8 */ | |
1175 | ri64type, /* 11 5,3,3,5 */ | |
1176 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1177 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1178 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1179 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1180 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1181 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1182 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1183 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1184 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1185 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1186 | }; | |
12f02c2a AC |
1187 | /* I am heaping all the fields of the formats into one structure and |
1188 | then, only the fields which are involved in instruction extension */ | |
c906108c | 1189 | struct upk_mips16 |
c5aa993b | 1190 | { |
12f02c2a | 1191 | CORE_ADDR offset; |
c5aa993b JM |
1192 | unsigned int regx; /* Function in i8 type */ |
1193 | unsigned int regy; | |
1194 | }; | |
c906108c SS |
1195 | |
1196 | ||
12f02c2a AC |
1197 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
1198 | for the bits which make up the immediatate extension. */ | |
c906108c | 1199 | |
12f02c2a AC |
1200 | static CORE_ADDR |
1201 | extended_offset (unsigned int extension) | |
c906108c | 1202 | { |
12f02c2a | 1203 | CORE_ADDR value; |
c5aa993b JM |
1204 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1205 | value = value << 6; | |
1206 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
1207 | value = value << 5; | |
1208 | value |= extension & 0x01f; /* extract 4:0 */ | |
1209 | return value; | |
c906108c SS |
1210 | } |
1211 | ||
1212 | /* Only call this function if you know that this is an extendable | |
1213 | instruction, It wont malfunction, but why make excess remote memory references? | |
1214 | If the immediate operands get sign extended or somthing, do it after | |
1215 | the extension is performed. | |
c5aa993b | 1216 | */ |
c906108c SS |
1217 | /* FIXME: Every one of these cases needs to worry about sign extension |
1218 | when the offset is to be used in relative addressing */ | |
1219 | ||
1220 | ||
12f02c2a | 1221 | static unsigned int |
c5aa993b | 1222 | fetch_mips_16 (CORE_ADDR pc) |
c906108c | 1223 | { |
c5aa993b JM |
1224 | char buf[8]; |
1225 | pc &= 0xfffffffe; /* clear the low order bit */ | |
1226 | target_read_memory (pc, buf, 2); | |
1227 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
1228 | } |
1229 | ||
1230 | static void | |
c5aa993b | 1231 | unpack_mips16 (CORE_ADDR pc, |
12f02c2a AC |
1232 | unsigned int extension, |
1233 | unsigned int inst, | |
1234 | enum mips16_inst_fmts insn_format, | |
c5aa993b | 1235 | struct upk_mips16 *upk) |
c906108c | 1236 | { |
12f02c2a AC |
1237 | CORE_ADDR offset; |
1238 | int regx; | |
1239 | int regy; | |
1240 | switch (insn_format) | |
c906108c | 1241 | { |
c5aa993b | 1242 | case itype: |
c906108c | 1243 | { |
12f02c2a AC |
1244 | CORE_ADDR value; |
1245 | if (extension) | |
c5aa993b JM |
1246 | { |
1247 | value = extended_offset (extension); | |
1248 | value = value << 11; /* rom for the original value */ | |
12f02c2a | 1249 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1250 | } |
1251 | else | |
c5aa993b | 1252 | { |
12f02c2a | 1253 | value = inst & 0x7ff; |
c5aa993b | 1254 | /* FIXME : Consider sign extension */ |
c906108c | 1255 | } |
12f02c2a AC |
1256 | offset = value; |
1257 | regx = -1; | |
1258 | regy = -1; | |
c906108c | 1259 | } |
c5aa993b JM |
1260 | break; |
1261 | case ritype: | |
1262 | case i8type: | |
1263 | { /* A register identifier and an offset */ | |
c906108c SS |
1264 | /* Most of the fields are the same as I type but the |
1265 | immediate value is of a different length */ | |
12f02c2a AC |
1266 | CORE_ADDR value; |
1267 | if (extension) | |
c906108c | 1268 | { |
c5aa993b JM |
1269 | value = extended_offset (extension); |
1270 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1271 | value |= inst & 0xff; /* eleven bits from instruction */ |
1272 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1273 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1274 | { | |
1275 | value &= ~0x3fff; /* remove the sign bit */ | |
1276 | value = -value; | |
c906108c SS |
1277 | } |
1278 | } | |
c5aa993b JM |
1279 | else |
1280 | { | |
12f02c2a AC |
1281 | value = inst & 0xff; /* 8 bits */ |
1282 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1283 | /* FIXME: Do sign extension , this format needs it */ |
1284 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1285 | { | |
1286 | value &= 0xef; /* remove the sign bit */ | |
1287 | value = -value; | |
1288 | } | |
c5aa993b | 1289 | } |
12f02c2a AC |
1290 | offset = value; |
1291 | regy = -1; | |
c5aa993b | 1292 | break; |
c906108c | 1293 | } |
c5aa993b | 1294 | case jalxtype: |
c906108c | 1295 | { |
c5aa993b | 1296 | unsigned long value; |
12f02c2a AC |
1297 | unsigned int nexthalf; |
1298 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b JM |
1299 | value = value << 16; |
1300 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
1301 | value |= nexthalf; | |
12f02c2a AC |
1302 | offset = value; |
1303 | regx = -1; | |
1304 | regy = -1; | |
c5aa993b | 1305 | break; |
c906108c SS |
1306 | } |
1307 | default: | |
8e65ff28 AC |
1308 | internal_error (__FILE__, __LINE__, |
1309 | "bad switch"); | |
c906108c | 1310 | } |
12f02c2a AC |
1311 | upk->offset = offset; |
1312 | upk->regx = regx; | |
1313 | upk->regy = regy; | |
c906108c SS |
1314 | } |
1315 | ||
1316 | ||
c5aa993b JM |
1317 | static CORE_ADDR |
1318 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1319 | { |
c5aa993b | 1320 | return ((offset << 2) | ((pc + 2) & (0xf0000000))); |
c906108c SS |
1321 | } |
1322 | ||
12f02c2a AC |
1323 | static CORE_ADDR |
1324 | extended_mips16_next_pc (CORE_ADDR pc, | |
1325 | unsigned int extension, | |
1326 | unsigned int insn) | |
c906108c | 1327 | { |
12f02c2a AC |
1328 | int op = (insn >> 11); |
1329 | switch (op) | |
c906108c | 1330 | { |
12f02c2a AC |
1331 | case 2: /* Branch */ |
1332 | { | |
1333 | CORE_ADDR offset; | |
1334 | struct upk_mips16 upk; | |
1335 | unpack_mips16 (pc, extension, insn, itype, &upk); | |
1336 | offset = upk.offset; | |
1337 | if (offset & 0x800) | |
1338 | { | |
1339 | offset &= 0xeff; | |
1340 | offset = -offset; | |
1341 | } | |
1342 | pc += (offset << 1) + 2; | |
1343 | break; | |
1344 | } | |
1345 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ | |
1346 | { | |
1347 | struct upk_mips16 upk; | |
1348 | unpack_mips16 (pc, extension, insn, jalxtype, &upk); | |
1349 | pc = add_offset_16 (pc, upk.offset); | |
1350 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1351 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1352 | else | |
1353 | pc |= 0x01; | |
1354 | break; | |
1355 | } | |
1356 | case 4: /* beqz */ | |
1357 | { | |
1358 | struct upk_mips16 upk; | |
1359 | int reg; | |
1360 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1361 | reg = read_signed_register (upk.regx); | |
1362 | if (reg == 0) | |
1363 | pc += (upk.offset << 1) + 2; | |
1364 | else | |
1365 | pc += 2; | |
1366 | break; | |
1367 | } | |
1368 | case 5: /* bnez */ | |
1369 | { | |
1370 | struct upk_mips16 upk; | |
1371 | int reg; | |
1372 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1373 | reg = read_signed_register (upk.regx); | |
1374 | if (reg != 0) | |
1375 | pc += (upk.offset << 1) + 2; | |
1376 | else | |
1377 | pc += 2; | |
1378 | break; | |
1379 | } | |
1380 | case 12: /* I8 Formats btez btnez */ | |
1381 | { | |
1382 | struct upk_mips16 upk; | |
1383 | int reg; | |
1384 | unpack_mips16 (pc, extension, insn, i8type, &upk); | |
1385 | /* upk.regx contains the opcode */ | |
1386 | reg = read_signed_register (24); /* Test register is 24 */ | |
1387 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ | |
1388 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1389 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1390 | pc += (upk.offset << 1) + 2; | |
1391 | else | |
1392 | pc += 2; | |
1393 | break; | |
1394 | } | |
1395 | case 29: /* RR Formats JR, JALR, JALR-RA */ | |
1396 | { | |
1397 | struct upk_mips16 upk; | |
1398 | /* upk.fmt = rrtype; */ | |
1399 | op = insn & 0x1f; | |
1400 | if (op == 0) | |
c5aa993b | 1401 | { |
12f02c2a AC |
1402 | int reg; |
1403 | upk.regx = (insn >> 8) & 0x07; | |
1404 | upk.regy = (insn >> 5) & 0x07; | |
1405 | switch (upk.regy) | |
c5aa993b | 1406 | { |
12f02c2a AC |
1407 | case 0: |
1408 | reg = upk.regx; | |
1409 | break; | |
1410 | case 1: | |
1411 | reg = 31; | |
1412 | break; /* Function return instruction */ | |
1413 | case 2: | |
1414 | reg = upk.regx; | |
1415 | break; | |
1416 | default: | |
1417 | reg = 31; | |
1418 | break; /* BOGUS Guess */ | |
c906108c | 1419 | } |
12f02c2a | 1420 | pc = read_signed_register (reg); |
c906108c | 1421 | } |
12f02c2a | 1422 | else |
c5aa993b | 1423 | pc += 2; |
12f02c2a AC |
1424 | break; |
1425 | } | |
1426 | case 30: | |
1427 | /* This is an instruction extension. Fetch the real instruction | |
1428 | (which follows the extension) and decode things based on | |
1429 | that. */ | |
1430 | { | |
1431 | pc += 2; | |
1432 | pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc)); | |
1433 | break; | |
1434 | } | |
1435 | default: | |
1436 | { | |
1437 | pc += 2; | |
1438 | break; | |
1439 | } | |
c906108c | 1440 | } |
c5aa993b | 1441 | return pc; |
12f02c2a | 1442 | } |
c906108c | 1443 | |
5a89d8aa | 1444 | static CORE_ADDR |
12f02c2a AC |
1445 | mips16_next_pc (CORE_ADDR pc) |
1446 | { | |
1447 | unsigned int insn = fetch_mips_16 (pc); | |
1448 | return extended_mips16_next_pc (pc, 0, insn); | |
1449 | } | |
1450 | ||
1451 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1452 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1453 | It works by decoding the current instruction and predicting where a |
1454 | branch will go. This isnt hard because all the data is available. | |
1455 | The MIPS32 and MIPS16 variants are quite different */ | |
c5aa993b JM |
1456 | CORE_ADDR |
1457 | mips_next_pc (CORE_ADDR pc) | |
c906108c | 1458 | { |
c5aa993b JM |
1459 | if (pc & 0x01) |
1460 | return mips16_next_pc (pc); | |
1461 | else | |
1462 | return mips32_next_pc (pc); | |
12f02c2a | 1463 | } |
c906108c | 1464 | |
e0f7ec59 AC |
1465 | /* Set up the 'saved_regs' array. This is a data structure containing |
1466 | the addresses on the stack where each register has been saved, for | |
1467 | each stack frame. Registers that have not been saved will have | |
1468 | zero here. The stack pointer register is special: rather than the | |
1469 | address where the stack register has been saved, | |
1470 | saved_regs[SP_REGNUM] will have the actual value of the previous | |
1471 | frame's stack register. */ | |
c906108c | 1472 | |
d28e01f4 | 1473 | static void |
acdb74a0 | 1474 | mips_find_saved_regs (struct frame_info *fci) |
c906108c SS |
1475 | { |
1476 | int ireg; | |
c906108c SS |
1477 | /* r0 bit means kernel trap */ |
1478 | int kernel_trap; | |
1479 | /* What registers have been saved? Bitmasks. */ | |
1480 | unsigned long gen_mask, float_mask; | |
1481 | mips_extra_func_info_t proc_desc; | |
1482 | t_inst inst; | |
e0f7ec59 | 1483 | CORE_ADDR *saved_regs; |
c906108c | 1484 | |
1b1d3794 | 1485 | if (deprecated_get_frame_saved_regs (fci) != NULL) |
e0f7ec59 AC |
1486 | return; |
1487 | saved_regs = frame_saved_regs_zalloc (fci); | |
c906108c SS |
1488 | |
1489 | /* If it is the frame for sigtramp, the saved registers are located | |
e0f7ec59 AC |
1490 | in a sigcontext structure somewhere on the stack. If the stack |
1491 | layout for sigtramp changes we might have to change these | |
1492 | constants and the companion fixup_sigtramp in mdebugread.c */ | |
c906108c | 1493 | #ifndef SIGFRAME_BASE |
e0f7ec59 AC |
1494 | /* To satisfy alignment restrictions, sigcontext is located 4 bytes |
1495 | above the sigtramp frame. */ | |
4246e332 | 1496 | #define SIGFRAME_BASE mips_regsize (current_gdbarch) |
c906108c | 1497 | /* FIXME! Are these correct?? */ |
4246e332 AC |
1498 | #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * mips_regsize (current_gdbarch)) |
1499 | #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * mips_regsize (current_gdbarch)) | |
c906108c | 1500 | #define SIGFRAME_FPREGSAVE_OFF \ |
4246e332 | 1501 | (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * mips_regsize (current_gdbarch) + 3 * mips_regsize (current_gdbarch)) |
c906108c | 1502 | #endif |
5a203e44 | 1503 | if ((get_frame_type (fci) == SIGTRAMP_FRAME)) |
c906108c SS |
1504 | { |
1505 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) | |
1506 | { | |
e0f7ec59 | 1507 | CORE_ADDR reg_position = (get_frame_base (fci) + SIGFRAME_REGSAVE_OFF |
10a08821 | 1508 | + ireg * mips_regsize (current_gdbarch)); |
e0f7ec59 | 1509 | set_reg_offset (saved_regs, ireg, reg_position); |
c906108c SS |
1510 | } |
1511 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) | |
1512 | { | |
e0f7ec59 AC |
1513 | CORE_ADDR reg_position = (get_frame_base (fci) |
1514 | + SIGFRAME_FPREGSAVE_OFF | |
10a08821 | 1515 | + ireg * mips_regsize (current_gdbarch)); |
56cea623 | 1516 | set_reg_offset (saved_regs, mips_regnum (current_gdbarch)->fp0 + ireg, reg_position); |
c906108c | 1517 | } |
e0f7ec59 AC |
1518 | |
1519 | set_reg_offset (saved_regs, PC_REGNUM, get_frame_base (fci) + SIGFRAME_PC_OFF); | |
1520 | /* SP_REGNUM, contains the value and not the address. */ | |
1521 | set_reg_offset (saved_regs, SP_REGNUM, get_frame_base (fci)); | |
c906108c SS |
1522 | return; |
1523 | } | |
1524 | ||
da50a4b7 | 1525 | proc_desc = get_frame_extra_info (fci)->proc_desc; |
c906108c | 1526 | if (proc_desc == NULL) |
e0f7ec59 AC |
1527 | /* I'm not sure how/whether this can happen. Normally when we |
1528 | can't find a proc_desc, we "synthesize" one using | |
1529 | heuristic_proc_desc and set the saved_regs right away. */ | |
c906108c SS |
1530 | return; |
1531 | ||
c5aa993b JM |
1532 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; |
1533 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc); | |
1534 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc); | |
c906108c | 1535 | |
e0f7ec59 AC |
1536 | if (/* In any frame other than the innermost or a frame interrupted |
1537 | by a signal, we assume that all registers have been saved. | |
1538 | This assumes that all register saves in a function happen | |
1539 | before the first function call. */ | |
11c02a10 AC |
1540 | (get_next_frame (fci) == NULL |
1541 | || (get_frame_type (get_next_frame (fci)) == SIGTRAMP_FRAME)) | |
c906108c | 1542 | |
e0f7ec59 | 1543 | /* In a dummy frame we know exactly where things are saved. */ |
c5aa993b | 1544 | && !PROC_DESC_IS_DUMMY (proc_desc) |
c906108c | 1545 | |
e0f7ec59 AC |
1546 | /* Don't bother unless we are inside a function prologue. |
1547 | Outside the prologue, we know where everything is. */ | |
c906108c | 1548 | |
50abf9e5 | 1549 | && in_prologue (get_frame_pc (fci), PROC_LOW_ADDR (proc_desc)) |
c906108c | 1550 | |
e0f7ec59 AC |
1551 | /* Not sure exactly what kernel_trap means, but if it means the |
1552 | kernel saves the registers without a prologue doing it, we | |
1553 | better not examine the prologue to see whether registers | |
1554 | have been saved yet. */ | |
c5aa993b | 1555 | && !kernel_trap) |
c906108c | 1556 | { |
e0f7ec59 AC |
1557 | /* We need to figure out whether the registers that the |
1558 | proc_desc claims are saved have been saved yet. */ | |
c906108c SS |
1559 | |
1560 | CORE_ADDR addr; | |
1561 | ||
1562 | /* Bitmasks; set if we have found a save for the register. */ | |
1563 | unsigned long gen_save_found = 0; | |
1564 | unsigned long float_save_found = 0; | |
1565 | int instlen; | |
1566 | ||
1567 | /* If the address is odd, assume this is MIPS16 code. */ | |
1568 | addr = PROC_LOW_ADDR (proc_desc); | |
1569 | instlen = pc_is_mips16 (addr) ? MIPS16_INSTLEN : MIPS_INSTLEN; | |
1570 | ||
e0f7ec59 AC |
1571 | /* Scan through this function's instructions preceding the |
1572 | current PC, and look for those that save registers. */ | |
50abf9e5 | 1573 | while (addr < get_frame_pc (fci)) |
c906108c SS |
1574 | { |
1575 | inst = mips_fetch_instruction (addr); | |
1576 | if (pc_is_mips16 (addr)) | |
1577 | mips16_decode_reg_save (inst, &gen_save_found); | |
1578 | else | |
1579 | mips32_decode_reg_save (inst, &gen_save_found, &float_save_found); | |
1580 | addr += instlen; | |
1581 | } | |
1582 | gen_mask = gen_save_found; | |
1583 | float_mask = float_save_found; | |
1584 | } | |
1585 | ||
e0f7ec59 AC |
1586 | /* Fill in the offsets for the registers which gen_mask says were |
1587 | saved. */ | |
1588 | { | |
1589 | CORE_ADDR reg_position = (get_frame_base (fci) | |
1590 | + PROC_REG_OFFSET (proc_desc)); | |
1591 | for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1) | |
1592 | if (gen_mask & 0x80000000) | |
1593 | { | |
1594 | set_reg_offset (saved_regs, ireg, reg_position); | |
1595 | reg_position -= MIPS_SAVED_REGSIZE; | |
1596 | } | |
1597 | } | |
c906108c | 1598 | |
e0f7ec59 AC |
1599 | /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse |
1600 | order of that normally used by gcc. Therefore, we have to fetch | |
1601 | the first instruction of the function, and if it's an entry | |
1602 | instruction that saves $s0 or $s1, correct their saved addresses. */ | |
c906108c SS |
1603 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) |
1604 | { | |
1605 | inst = mips_fetch_instruction (PROC_LOW_ADDR (proc_desc)); | |
e0f7ec59 AC |
1606 | if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) |
1607 | /* entry */ | |
c906108c SS |
1608 | { |
1609 | int reg; | |
1610 | int sreg_count = (inst >> 6) & 3; | |
c5aa993b | 1611 | |
c906108c | 1612 | /* Check if the ra register was pushed on the stack. */ |
e0f7ec59 AC |
1613 | CORE_ADDR reg_position = (get_frame_base (fci) |
1614 | + PROC_REG_OFFSET (proc_desc)); | |
c906108c | 1615 | if (inst & 0x20) |
7a292a7a | 1616 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c | 1617 | |
e0f7ec59 AC |
1618 | /* Check if the s0 and s1 registers were pushed on the |
1619 | stack. */ | |
c5aa993b | 1620 | for (reg = 16; reg < sreg_count + 16; reg++) |
c906108c | 1621 | { |
e0f7ec59 | 1622 | set_reg_offset (saved_regs, reg, reg_position); |
7a292a7a | 1623 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1624 | } |
1625 | } | |
1626 | } | |
1627 | ||
e0f7ec59 AC |
1628 | /* Fill in the offsets for the registers which float_mask says were |
1629 | saved. */ | |
1630 | { | |
1631 | CORE_ADDR reg_position = (get_frame_base (fci) | |
1632 | + PROC_FREG_OFFSET (proc_desc)); | |
6acdf5c7 | 1633 | |
e0f7ec59 AC |
1634 | /* Fill in the offsets for the float registers which float_mask |
1635 | says were saved. */ | |
1636 | for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1) | |
1637 | if (float_mask & 0x80000000) | |
1638 | { | |
c57bb9fa AC |
1639 | if (MIPS_SAVED_REGSIZE == 4 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
1640 | { | |
1641 | /* On a big endian 32 bit ABI, floating point registers | |
1642 | are paired to form doubles such that the most | |
1643 | significant part is in $f[N+1] and the least | |
1644 | significant in $f[N] vis: $f[N+1] ||| $f[N]. The | |
1645 | registers are also spilled as a pair and stored as a | |
1646 | double. | |
1647 | ||
1648 | When little-endian the least significant part is | |
1649 | stored first leading to the memory order $f[N] and | |
1650 | then $f[N+1]. | |
1651 | ||
ce2826aa | 1652 | Unfortunately, when big-endian the most significant |
c57bb9fa AC |
1653 | part of the double is stored first, and the least |
1654 | significant is stored second. This leads to the | |
1655 | registers being ordered in memory as firt $f[N+1] and | |
1656 | then $f[N]. | |
1657 | ||
1658 | For the big-endian case make certain that the | |
1659 | addresses point at the correct (swapped) locations | |
1660 | $f[N] and $f[N+1] pair (keep in mind that | |
1661 | reg_position is decremented each time through the | |
1662 | loop). */ | |
1663 | if ((ireg & 1)) | |
56cea623 | 1664 | set_reg_offset (saved_regs, mips_regnum (current_gdbarch)->fp0 + ireg, |
c57bb9fa AC |
1665 | reg_position - MIPS_SAVED_REGSIZE); |
1666 | else | |
56cea623 | 1667 | set_reg_offset (saved_regs, mips_regnum (current_gdbarch)->fp0 + ireg, |
c57bb9fa AC |
1668 | reg_position + MIPS_SAVED_REGSIZE); |
1669 | } | |
1670 | else | |
56cea623 | 1671 | set_reg_offset (saved_regs, mips_regnum (current_gdbarch)->fp0 + ireg, reg_position); |
e0f7ec59 AC |
1672 | reg_position -= MIPS_SAVED_REGSIZE; |
1673 | } | |
c906108c | 1674 | |
e0f7ec59 AC |
1675 | set_reg_offset (saved_regs, PC_REGNUM, saved_regs[RA_REGNUM]); |
1676 | } | |
d28e01f4 | 1677 | |
e0f7ec59 AC |
1678 | /* SP_REGNUM, contains the value and not the address. */ |
1679 | set_reg_offset (saved_regs, SP_REGNUM, get_frame_base (fci)); | |
d28e01f4 KB |
1680 | } |
1681 | ||
c906108c | 1682 | static CORE_ADDR |
acdb74a0 | 1683 | read_next_frame_reg (struct frame_info *fi, int regno) |
c906108c | 1684 | { |
a4b8ebc8 AC |
1685 | /* Always a pseudo. */ |
1686 | gdb_assert (regno >= NUM_REGS); | |
f796e4be | 1687 | if (fi == NULL) |
c906108c | 1688 | { |
a4b8ebc8 AC |
1689 | LONGEST val; |
1690 | regcache_cooked_read_signed (current_regcache, regno, &val); | |
1691 | return val; | |
f796e4be | 1692 | } |
a4b8ebc8 AC |
1693 | else if ((regno % NUM_REGS) == SP_REGNUM) |
1694 | /* The SP_REGNUM is special, its value is stored in saved_regs. | |
1695 | In fact, it is so special that it can even only be fetched | |
1696 | using a raw register number! Once this code as been converted | |
1697 | to frame-unwind the problem goes away. */ | |
1698 | return frame_unwind_register_signed (fi, regno % NUM_REGS); | |
f796e4be | 1699 | else |
a4b8ebc8 | 1700 | return frame_unwind_register_signed (fi, regno); |
64159455 | 1701 | |
c906108c SS |
1702 | } |
1703 | ||
1704 | /* mips_addr_bits_remove - remove useless address bits */ | |
1705 | ||
875e1767 | 1706 | static CORE_ADDR |
acdb74a0 | 1707 | mips_addr_bits_remove (CORE_ADDR addr) |
c906108c | 1708 | { |
8fa9cfa1 AC |
1709 | if (mips_mask_address_p () |
1710 | && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) | |
1711 | /* This hack is a work-around for existing boards using PMON, the | |
1712 | simulator, and any other 64-bit targets that doesn't have true | |
1713 | 64-bit addressing. On these targets, the upper 32 bits of | |
1714 | addresses are ignored by the hardware. Thus, the PC or SP are | |
1715 | likely to have been sign extended to all 1s by instruction | |
1716 | sequences that load 32-bit addresses. For example, a typical | |
1717 | piece of code that loads an address is this: | |
1718 | ||
1719 | lui $r2, <upper 16 bits> | |
1720 | ori $r2, <lower 16 bits> | |
1721 | ||
1722 | But the lui sign-extends the value such that the upper 32 bits | |
1723 | may be all 1s. The workaround is simply to mask off these | |
1724 | bits. In the future, gcc may be changed to support true 64-bit | |
1725 | addressing, and this masking will have to be disabled. */ | |
1726 | return addr &= 0xffffffffUL; | |
1727 | else | |
1728 | return addr; | |
c906108c SS |
1729 | } |
1730 | ||
9022177c DJ |
1731 | /* mips_software_single_step() is called just before we want to resume |
1732 | the inferior, if we want to single-step it but there is no hardware | |
75c9abc6 | 1733 | or kernel single-step support (MIPS on GNU/Linux for example). We find |
9022177c DJ |
1734 | the target of the coming instruction and breakpoint it. |
1735 | ||
1736 | single_step is also called just after the inferior stops. If we had | |
1737 | set up a simulated single-step, we undo our damage. */ | |
1738 | ||
1739 | void | |
1740 | mips_software_single_step (enum target_signal sig, int insert_breakpoints_p) | |
1741 | { | |
1742 | static CORE_ADDR next_pc; | |
1743 | typedef char binsn_quantum[BREAKPOINT_MAX]; | |
1744 | static binsn_quantum break_mem; | |
1745 | CORE_ADDR pc; | |
1746 | ||
1747 | if (insert_breakpoints_p) | |
1748 | { | |
1749 | pc = read_register (PC_REGNUM); | |
1750 | next_pc = mips_next_pc (pc); | |
1751 | ||
1752 | target_insert_breakpoint (next_pc, break_mem); | |
1753 | } | |
1754 | else | |
1755 | target_remove_breakpoint (next_pc, break_mem); | |
1756 | } | |
1757 | ||
97f46953 | 1758 | static CORE_ADDR |
acdb74a0 | 1759 | mips_init_frame_pc_first (int fromleaf, struct frame_info *prev) |
c906108c SS |
1760 | { |
1761 | CORE_ADDR pc, tmp; | |
1762 | ||
11c02a10 | 1763 | pc = ((fromleaf) |
6913c89a | 1764 | ? DEPRECATED_SAVED_PC_AFTER_CALL (get_next_frame (prev)) |
11c02a10 | 1765 | : get_next_frame (prev) |
8bedc050 | 1766 | ? DEPRECATED_FRAME_SAVED_PC (get_next_frame (prev)) |
11c02a10 | 1767 | : read_pc ()); |
5a89d8aa | 1768 | tmp = SKIP_TRAMPOLINE_CODE (pc); |
97f46953 | 1769 | return tmp ? tmp : pc; |
c906108c SS |
1770 | } |
1771 | ||
1772 | ||
f7ab6ec6 | 1773 | static CORE_ADDR |
acdb74a0 | 1774 | mips_frame_saved_pc (struct frame_info *frame) |
c906108c SS |
1775 | { |
1776 | CORE_ADDR saved_pc; | |
c906108c | 1777 | |
50abf9e5 | 1778 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0)) |
cedea778 | 1779 | { |
a4b8ebc8 | 1780 | /* Always unwind the cooked PC register value. */ |
dd3ecc14 | 1781 | saved_pc = frame_unwind_register_signed (frame, NUM_REGS + PC_REGNUM); |
cedea778 | 1782 | } |
c906108c | 1783 | else |
a4b8ebc8 AC |
1784 | { |
1785 | mips_extra_func_info_t proc_desc | |
1786 | = get_frame_extra_info (frame)->proc_desc; | |
1787 | if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) | |
1788 | saved_pc = read_memory_integer (get_frame_base (frame) - MIPS_SAVED_REGSIZE, MIPS_SAVED_REGSIZE); | |
1789 | else | |
1790 | { | |
1791 | /* We have to get the saved pc from the sigcontext if it is | |
1792 | a signal handler frame. */ | |
1793 | int pcreg = (get_frame_type (frame) == SIGTRAMP_FRAME ? PC_REGNUM | |
1794 | : proc_desc ? PROC_PC_REG (proc_desc) : RA_REGNUM); | |
1795 | saved_pc = read_next_frame_reg (frame, NUM_REGS + pcreg); | |
1796 | } | |
1797 | } | |
c906108c SS |
1798 | return ADDR_BITS_REMOVE (saved_pc); |
1799 | } | |
1800 | ||
1801 | static struct mips_extra_func_info temp_proc_desc; | |
fe29b929 KB |
1802 | |
1803 | /* This hack will go away once the get_prev_frame() code has been | |
1804 | modified to set the frame's type first. That is BEFORE init extra | |
1805 | frame info et.al. is called. This is because it will become | |
1806 | possible to skip the init extra info call for sigtramp and dummy | |
1807 | frames. */ | |
1808 | static CORE_ADDR *temp_saved_regs; | |
c906108c | 1809 | |
e0f7ec59 AC |
1810 | /* Set a register's saved stack address in temp_saved_regs. If an |
1811 | address has already been set for this register, do nothing; this | |
1812 | way we will only recognize the first save of a given register in a | |
a4b8ebc8 AC |
1813 | function prologue. |
1814 | ||
1815 | For simplicity, save the address in both [0 .. NUM_REGS) and | |
1816 | [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range | |
1817 | is used as it is only second range (the ABI instead of ISA | |
1818 | registers) that comes into play when finding saved registers in a | |
1819 | frame. */ | |
c906108c SS |
1820 | |
1821 | static void | |
e0f7ec59 | 1822 | set_reg_offset (CORE_ADDR *saved_regs, int regno, CORE_ADDR offset) |
c906108c | 1823 | { |
e0f7ec59 | 1824 | if (saved_regs[regno] == 0) |
a4b8ebc8 AC |
1825 | { |
1826 | saved_regs[regno + 0 * NUM_REGS] = offset; | |
1827 | saved_regs[regno + 1 * NUM_REGS] = offset; | |
1828 | } | |
c906108c SS |
1829 | } |
1830 | ||
1831 | ||
1832 | /* Test whether the PC points to the return instruction at the | |
1833 | end of a function. */ | |
1834 | ||
c5aa993b | 1835 | static int |
acdb74a0 | 1836 | mips_about_to_return (CORE_ADDR pc) |
c906108c SS |
1837 | { |
1838 | if (pc_is_mips16 (pc)) | |
1839 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler | |
1840 | generates a "jr $ra"; other times it generates code to load | |
1841 | the return address from the stack to an accessible register (such | |
1842 | as $a3), then a "jr" using that register. This second case | |
1843 | is almost impossible to distinguish from an indirect jump | |
1844 | used for switch statements, so we don't even try. */ | |
1845 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
1846 | else | |
1847 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
1848 | } | |
1849 | ||
1850 | ||
1851 | /* This fencepost looks highly suspicious to me. Removing it also | |
1852 | seems suspicious as it could affect remote debugging across serial | |
1853 | lines. */ | |
1854 | ||
1855 | static CORE_ADDR | |
acdb74a0 | 1856 | heuristic_proc_start (CORE_ADDR pc) |
c906108c | 1857 | { |
c5aa993b JM |
1858 | CORE_ADDR start_pc; |
1859 | CORE_ADDR fence; | |
1860 | int instlen; | |
1861 | int seen_adjsp = 0; | |
c906108c | 1862 | |
c5aa993b JM |
1863 | pc = ADDR_BITS_REMOVE (pc); |
1864 | start_pc = pc; | |
1865 | fence = start_pc - heuristic_fence_post; | |
1866 | if (start_pc == 0) | |
1867 | return 0; | |
c906108c | 1868 | |
c5aa993b JM |
1869 | if (heuristic_fence_post == UINT_MAX |
1870 | || fence < VM_MIN_ADDRESS) | |
1871 | fence = VM_MIN_ADDRESS; | |
c906108c | 1872 | |
c5aa993b | 1873 | instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN; |
c906108c | 1874 | |
c5aa993b JM |
1875 | /* search back for previous return */ |
1876 | for (start_pc -= instlen;; start_pc -= instlen) | |
1877 | if (start_pc < fence) | |
1878 | { | |
1879 | /* It's not clear to me why we reach this point when | |
c0236d92 | 1880 | stop_soon, but with this test, at least we |
c5aa993b JM |
1881 | don't print out warnings for every child forked (eg, on |
1882 | decstation). 22apr93 rich@cygnus.com. */ | |
c0236d92 | 1883 | if (stop_soon == NO_STOP_QUIETLY) |
c906108c | 1884 | { |
c5aa993b JM |
1885 | static int blurb_printed = 0; |
1886 | ||
1887 | warning ("Warning: GDB can't find the start of the function at 0x%s.", | |
1888 | paddr_nz (pc)); | |
1889 | ||
1890 | if (!blurb_printed) | |
c906108c | 1891 | { |
c5aa993b JM |
1892 | /* This actually happens frequently in embedded |
1893 | development, when you first connect to a board | |
1894 | and your stack pointer and pc are nowhere in | |
1895 | particular. This message needs to give people | |
1896 | in that situation enough information to | |
1897 | determine that it's no big deal. */ | |
1898 | printf_filtered ("\n\ | |
cd0fc7c3 SS |
1899 | GDB is unable to find the start of the function at 0x%s\n\ |
1900 | and thus can't determine the size of that function's stack frame.\n\ | |
1901 | This means that GDB may be unable to access that stack frame, or\n\ | |
1902 | the frames below it.\n\ | |
1903 | This problem is most likely caused by an invalid program counter or\n\ | |
1904 | stack pointer.\n\ | |
1905 | However, if you think GDB should simply search farther back\n\ | |
1906 | from 0x%s for code which looks like the beginning of a\n\ | |
1907 | function, you can increase the range of the search using the `set\n\ | |
1908 | heuristic-fence-post' command.\n", | |
c5aa993b JM |
1909 | paddr_nz (pc), paddr_nz (pc)); |
1910 | blurb_printed = 1; | |
c906108c | 1911 | } |
c906108c SS |
1912 | } |
1913 | ||
c5aa993b JM |
1914 | return 0; |
1915 | } | |
1916 | else if (pc_is_mips16 (start_pc)) | |
1917 | { | |
1918 | unsigned short inst; | |
1919 | ||
1920 | /* On MIPS16, any one of the following is likely to be the | |
1921 | start of a function: | |
1922 | entry | |
1923 | addiu sp,-n | |
1924 | daddiu sp,-n | |
1925 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
1926 | inst = mips_fetch_instruction (start_pc); | |
1927 | if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
1928 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
1929 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
1930 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
1931 | break; | |
1932 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
1933 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1934 | seen_adjsp = 1; | |
1935 | else | |
1936 | seen_adjsp = 0; | |
1937 | } | |
1938 | else if (mips_about_to_return (start_pc)) | |
1939 | { | |
1940 | start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */ | |
1941 | break; | |
1942 | } | |
1943 | ||
c5aa993b | 1944 | return start_pc; |
c906108c SS |
1945 | } |
1946 | ||
1947 | /* Fetch the immediate value from a MIPS16 instruction. | |
1948 | If the previous instruction was an EXTEND, use it to extend | |
1949 | the upper bits of the immediate value. This is a helper function | |
1950 | for mips16_heuristic_proc_desc. */ | |
1951 | ||
1952 | static int | |
acdb74a0 AC |
1953 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ |
1954 | unsigned short inst, /* current instruction */ | |
1955 | int nbits, /* number of bits in imm field */ | |
1956 | int scale, /* scale factor to be applied to imm */ | |
1957 | int is_signed) /* is the imm field signed? */ | |
c906108c SS |
1958 | { |
1959 | int offset; | |
1960 | ||
1961 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ | |
1962 | { | |
1963 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
c5aa993b | 1964 | if (offset & 0x8000) /* check for negative extend */ |
c906108c SS |
1965 | offset = 0 - (0x10000 - (offset & 0xffff)); |
1966 | return offset | (inst & 0x1f); | |
1967 | } | |
1968 | else | |
1969 | { | |
1970 | int max_imm = 1 << nbits; | |
1971 | int mask = max_imm - 1; | |
1972 | int sign_bit = max_imm >> 1; | |
1973 | ||
1974 | offset = inst & mask; | |
1975 | if (is_signed && (offset & sign_bit)) | |
1976 | offset = 0 - (max_imm - offset); | |
1977 | return offset * scale; | |
1978 | } | |
1979 | } | |
1980 | ||
1981 | ||
1982 | /* Fill in values in temp_proc_desc based on the MIPS16 instruction | |
1983 | stream from start_pc to limit_pc. */ | |
1984 | ||
1985 | static void | |
acdb74a0 AC |
1986 | mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
1987 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
1988 | { |
1989 | CORE_ADDR cur_pc; | |
1990 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
1991 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
1992 | unsigned inst = 0; /* current instruction */ | |
1993 | unsigned entry_inst = 0; /* the entry instruction */ | |
1994 | int reg, offset; | |
1995 | ||
c5aa993b JM |
1996 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */ |
1997 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ | |
c906108c SS |
1998 | |
1999 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN) | |
2000 | { | |
2001 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
2002 | the immediate offset extension from it in mips16_get_imm. */ | |
2003 | prev_inst = inst; | |
2004 | ||
2005 | /* Fetch and decode the instruction. */ | |
2006 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
c5aa993b | 2007 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
c906108c SS |
2008 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ |
2009 | { | |
2010 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
c5aa993b JM |
2011 | if (offset < 0) /* negative stack adjustment? */ |
2012 | PROC_FRAME_OFFSET (&temp_proc_desc) -= offset; | |
c906108c SS |
2013 | else |
2014 | /* Exit loop if a positive stack adjustment is found, which | |
2015 | usually means that the stack cleanup code in the function | |
2016 | epilogue is reached. */ | |
2017 | break; | |
2018 | } | |
2019 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
2020 | { | |
2021 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2022 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
c5aa993b | 2023 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
e0f7ec59 | 2024 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c906108c SS |
2025 | } |
2026 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
2027 | { | |
2028 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
2029 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2030 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
e0f7ec59 | 2031 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c906108c SS |
2032 | } |
2033 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
2034 | { | |
2035 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
c5aa993b | 2036 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
e0f7ec59 | 2037 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
c906108c SS |
2038 | } |
2039 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
2040 | { | |
2041 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
c5aa993b | 2042 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
e0f7ec59 | 2043 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
c906108c | 2044 | } |
c5aa993b | 2045 | else if (inst == 0x673d) /* move $s1, $sp */ |
c906108c SS |
2046 | { |
2047 | frame_addr = sp; | |
2048 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
2049 | } | |
2050 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
2051 | { | |
2052 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2053 | frame_addr = sp + offset; | |
2054 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
2055 | PROC_FRAME_ADJUST (&temp_proc_desc) = offset; | |
2056 | } | |
2057 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
2058 | { | |
2059 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
2060 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2061 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2062 | set_reg_offset (temp_saved_regs, reg, frame_addr + offset); |
c906108c SS |
2063 | } |
2064 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
2065 | { | |
2066 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
2067 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2068 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2069 | set_reg_offset (temp_saved_regs, reg, frame_addr + offset); |
c906108c | 2070 | } |
c5aa993b JM |
2071 | else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
2072 | entry_inst = inst; /* save for later processing */ | |
c906108c | 2073 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
c5aa993b | 2074 | cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */ |
c906108c SS |
2075 | } |
2076 | ||
c5aa993b JM |
2077 | /* The entry instruction is typically the first instruction in a function, |
2078 | and it stores registers at offsets relative to the value of the old SP | |
2079 | (before the prologue). But the value of the sp parameter to this | |
2080 | function is the new SP (after the prologue has been executed). So we | |
2081 | can't calculate those offsets until we've seen the entire prologue, | |
2082 | and can calculate what the old SP must have been. */ | |
2083 | if (entry_inst != 0) | |
2084 | { | |
2085 | int areg_count = (entry_inst >> 8) & 7; | |
2086 | int sreg_count = (entry_inst >> 6) & 3; | |
c906108c | 2087 | |
c5aa993b JM |
2088 | /* The entry instruction always subtracts 32 from the SP. */ |
2089 | PROC_FRAME_OFFSET (&temp_proc_desc) += 32; | |
c906108c | 2090 | |
c5aa993b JM |
2091 | /* Now we can calculate what the SP must have been at the |
2092 | start of the function prologue. */ | |
2093 | sp += PROC_FRAME_OFFSET (&temp_proc_desc); | |
c906108c | 2094 | |
c5aa993b JM |
2095 | /* Check if a0-a3 were saved in the caller's argument save area. */ |
2096 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
2097 | { | |
2098 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
e0f7ec59 | 2099 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c5aa993b JM |
2100 | offset += MIPS_SAVED_REGSIZE; |
2101 | } | |
c906108c | 2102 | |
c5aa993b JM |
2103 | /* Check if the ra register was pushed on the stack. */ |
2104 | offset = -4; | |
2105 | if (entry_inst & 0x20) | |
2106 | { | |
2107 | PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM; | |
e0f7ec59 | 2108 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
c5aa993b JM |
2109 | offset -= MIPS_SAVED_REGSIZE; |
2110 | } | |
c906108c | 2111 | |
c5aa993b JM |
2112 | /* Check if the s0 and s1 registers were pushed on the stack. */ |
2113 | for (reg = 16; reg < sreg_count + 16; reg++) | |
2114 | { | |
2115 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
e0f7ec59 | 2116 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c5aa993b JM |
2117 | offset -= MIPS_SAVED_REGSIZE; |
2118 | } | |
2119 | } | |
c906108c SS |
2120 | } |
2121 | ||
2122 | static void | |
fba45db2 KB |
2123 | mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
2124 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
2125 | { |
2126 | CORE_ADDR cur_pc; | |
c5aa993b | 2127 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ |
c906108c | 2128 | restart: |
fe29b929 | 2129 | temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); |
cce74817 | 2130 | memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c5aa993b | 2131 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; |
c906108c SS |
2132 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ |
2133 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN) | |
2134 | { | |
2135 | unsigned long inst, high_word, low_word; | |
2136 | int reg; | |
2137 | ||
2138 | /* Fetch the instruction. */ | |
2139 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
2140 | ||
2141 | /* Save some code by pre-extracting some useful fields. */ | |
2142 | high_word = (inst >> 16) & 0xffff; | |
2143 | low_word = inst & 0xffff; | |
2144 | reg = high_word & 0x1f; | |
2145 | ||
c5aa993b | 2146 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
c906108c SS |
2147 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
2148 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
2149 | { | |
2150 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
c5aa993b | 2151 | PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word; |
c906108c SS |
2152 | else |
2153 | /* Exit loop if a positive stack adjustment is found, which | |
2154 | usually means that the stack cleanup code in the function | |
2155 | epilogue is reached. */ | |
2156 | break; | |
2157 | } | |
2158 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
2159 | { | |
c5aa993b | 2160 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2161 | set_reg_offset (temp_saved_regs, reg, sp + low_word); |
c906108c SS |
2162 | } |
2163 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
2164 | { | |
2165 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra, | |
2166 | but the register size used is only 32 bits. Make the address | |
2167 | for the saved register point to the lower 32 bits. */ | |
c5aa993b | 2168 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
4246e332 | 2169 | set_reg_offset (temp_saved_regs, reg, sp + low_word + 8 - mips_regsize (current_gdbarch)); |
c906108c | 2170 | } |
c5aa993b | 2171 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ |
c906108c SS |
2172 | { |
2173 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
c5aa993b JM |
2174 | if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc)) |
2175 | frame_addr = sp + low_word; | |
c906108c SS |
2176 | else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) |
2177 | { | |
2178 | unsigned alloca_adjust; | |
2179 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
a4b8ebc8 | 2180 | frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); |
c5aa993b | 2181 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
c906108c SS |
2182 | if (alloca_adjust > 0) |
2183 | { | |
2184 | /* FP > SP + frame_size. This may be because | |
2185 | * of an alloca or somethings similar. | |
2186 | * Fix sp to "pre-alloca" value, and try again. | |
2187 | */ | |
2188 | sp += alloca_adjust; | |
2189 | goto restart; | |
2190 | } | |
2191 | } | |
2192 | } | |
c5aa993b JM |
2193 | /* move $30,$sp. With different versions of gas this will be either |
2194 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
2195 | Accept any one of these. */ | |
c906108c SS |
2196 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) |
2197 | { | |
2198 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
2199 | if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) | |
2200 | { | |
2201 | unsigned alloca_adjust; | |
2202 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
a4b8ebc8 | 2203 | frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); |
c5aa993b | 2204 | alloca_adjust = (unsigned) (frame_addr - sp); |
c906108c SS |
2205 | if (alloca_adjust > 0) |
2206 | { | |
2207 | /* FP > SP + frame_size. This may be because | |
2208 | * of an alloca or somethings similar. | |
2209 | * Fix sp to "pre-alloca" value, and try again. | |
2210 | */ | |
2211 | sp += alloca_adjust; | |
2212 | goto restart; | |
2213 | } | |
2214 | } | |
2215 | } | |
c5aa993b | 2216 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ |
c906108c | 2217 | { |
c5aa993b | 2218 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2219 | set_reg_offset (temp_saved_regs, reg, frame_addr + low_word); |
c906108c SS |
2220 | } |
2221 | } | |
2222 | } | |
2223 | ||
2224 | static mips_extra_func_info_t | |
acdb74a0 | 2225 | heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
479412cd | 2226 | struct frame_info *next_frame, int cur_frame) |
c906108c | 2227 | { |
479412cd DJ |
2228 | CORE_ADDR sp; |
2229 | ||
2230 | if (cur_frame) | |
a4b8ebc8 | 2231 | sp = read_next_frame_reg (next_frame, NUM_REGS + SP_REGNUM); |
479412cd DJ |
2232 | else |
2233 | sp = 0; | |
c906108c | 2234 | |
c5aa993b JM |
2235 | if (start_pc == 0) |
2236 | return NULL; | |
2237 | memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc)); | |
fe29b929 | 2238 | temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); |
3758ac48 | 2239 | memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
2240 | PROC_LOW_ADDR (&temp_proc_desc) = start_pc; |
2241 | PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM; | |
2242 | PROC_PC_REG (&temp_proc_desc) = RA_REGNUM; | |
2243 | ||
2244 | if (start_pc + 200 < limit_pc) | |
2245 | limit_pc = start_pc + 200; | |
2246 | if (pc_is_mips16 (start_pc)) | |
2247 | mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
2248 | else | |
2249 | mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
2250 | return &temp_proc_desc; | |
2251 | } | |
2252 | ||
6c0d6680 DJ |
2253 | struct mips_objfile_private |
2254 | { | |
2255 | bfd_size_type size; | |
2256 | char *contents; | |
2257 | }; | |
2258 | ||
2259 | /* Global used to communicate between non_heuristic_proc_desc and | |
2260 | compare_pdr_entries within qsort (). */ | |
2261 | static bfd *the_bfd; | |
2262 | ||
2263 | static int | |
2264 | compare_pdr_entries (const void *a, const void *b) | |
2265 | { | |
2266 | CORE_ADDR lhs = bfd_get_32 (the_bfd, (bfd_byte *) a); | |
2267 | CORE_ADDR rhs = bfd_get_32 (the_bfd, (bfd_byte *) b); | |
2268 | ||
2269 | if (lhs < rhs) | |
2270 | return -1; | |
2271 | else if (lhs == rhs) | |
2272 | return 0; | |
2273 | else | |
2274 | return 1; | |
2275 | } | |
2276 | ||
c906108c | 2277 | static mips_extra_func_info_t |
acdb74a0 | 2278 | non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr) |
c906108c SS |
2279 | { |
2280 | CORE_ADDR startaddr; | |
2281 | mips_extra_func_info_t proc_desc; | |
c5aa993b | 2282 | struct block *b = block_for_pc (pc); |
c906108c | 2283 | struct symbol *sym; |
6c0d6680 DJ |
2284 | struct obj_section *sec; |
2285 | struct mips_objfile_private *priv; | |
2286 | ||
ae45cd16 | 2287 | if (DEPRECATED_PC_IN_CALL_DUMMY (pc, 0, 0)) |
6c0d6680 | 2288 | return NULL; |
c906108c SS |
2289 | |
2290 | find_pc_partial_function (pc, NULL, &startaddr, NULL); | |
2291 | if (addrptr) | |
2292 | *addrptr = startaddr; | |
6c0d6680 DJ |
2293 | |
2294 | priv = NULL; | |
2295 | ||
2296 | sec = find_pc_section (pc); | |
2297 | if (sec != NULL) | |
c906108c | 2298 | { |
6c0d6680 DJ |
2299 | priv = (struct mips_objfile_private *) sec->objfile->obj_private; |
2300 | ||
2301 | /* Search the ".pdr" section generated by GAS. This includes most of | |
2302 | the information normally found in ECOFF PDRs. */ | |
2303 | ||
2304 | the_bfd = sec->objfile->obfd; | |
2305 | if (priv == NULL | |
2306 | && (the_bfd->format == bfd_object | |
2307 | && bfd_get_flavour (the_bfd) == bfd_target_elf_flavour | |
2308 | && elf_elfheader (the_bfd)->e_ident[EI_CLASS] == ELFCLASS64)) | |
2309 | { | |
2310 | /* Right now GAS only outputs the address as a four-byte sequence. | |
2311 | This means that we should not bother with this method on 64-bit | |
2312 | targets (until that is fixed). */ | |
2313 | ||
2314 | priv = obstack_alloc (& sec->objfile->psymbol_obstack, | |
2315 | sizeof (struct mips_objfile_private)); | |
2316 | priv->size = 0; | |
2317 | sec->objfile->obj_private = priv; | |
2318 | } | |
2319 | else if (priv == NULL) | |
2320 | { | |
2321 | asection *bfdsec; | |
2322 | ||
2323 | priv = obstack_alloc (& sec->objfile->psymbol_obstack, | |
2324 | sizeof (struct mips_objfile_private)); | |
2325 | ||
2326 | bfdsec = bfd_get_section_by_name (sec->objfile->obfd, ".pdr"); | |
2327 | if (bfdsec != NULL) | |
2328 | { | |
2329 | priv->size = bfd_section_size (sec->objfile->obfd, bfdsec); | |
2330 | priv->contents = obstack_alloc (& sec->objfile->psymbol_obstack, | |
2331 | priv->size); | |
2332 | bfd_get_section_contents (sec->objfile->obfd, bfdsec, | |
2333 | priv->contents, 0, priv->size); | |
2334 | ||
2335 | /* In general, the .pdr section is sorted. However, in the | |
2336 | presence of multiple code sections (and other corner cases) | |
2337 | it can become unsorted. Sort it so that we can use a faster | |
2338 | binary search. */ | |
2339 | qsort (priv->contents, priv->size / 32, 32, compare_pdr_entries); | |
2340 | } | |
2341 | else | |
2342 | priv->size = 0; | |
2343 | ||
2344 | sec->objfile->obj_private = priv; | |
2345 | } | |
2346 | the_bfd = NULL; | |
2347 | ||
2348 | if (priv->size != 0) | |
2349 | { | |
2350 | int low, mid, high; | |
2351 | char *ptr; | |
2352 | ||
2353 | low = 0; | |
2354 | high = priv->size / 32; | |
2355 | ||
2356 | do | |
2357 | { | |
2358 | CORE_ADDR pdr_pc; | |
2359 | ||
2360 | mid = (low + high) / 2; | |
2361 | ||
2362 | ptr = priv->contents + mid * 32; | |
2363 | pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr); | |
2364 | pdr_pc += ANOFFSET (sec->objfile->section_offsets, | |
2365 | SECT_OFF_TEXT (sec->objfile)); | |
2366 | if (pdr_pc == startaddr) | |
2367 | break; | |
2368 | if (pdr_pc > startaddr) | |
2369 | high = mid; | |
2370 | else | |
2371 | low = mid + 1; | |
2372 | } | |
2373 | while (low != high); | |
2374 | ||
2375 | if (low != high) | |
2376 | { | |
2377 | struct symbol *sym = find_pc_function (pc); | |
2378 | ||
2379 | /* Fill in what we need of the proc_desc. */ | |
2380 | proc_desc = (mips_extra_func_info_t) | |
2381 | obstack_alloc (&sec->objfile->psymbol_obstack, | |
2382 | sizeof (struct mips_extra_func_info)); | |
2383 | PROC_LOW_ADDR (proc_desc) = startaddr; | |
2384 | ||
2385 | /* Only used for dummy frames. */ | |
2386 | PROC_HIGH_ADDR (proc_desc) = 0; | |
2387 | ||
2388 | PROC_FRAME_OFFSET (proc_desc) | |
2389 | = bfd_get_32 (sec->objfile->obfd, ptr + 20); | |
2390 | PROC_FRAME_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2391 | ptr + 24); | |
2392 | PROC_FRAME_ADJUST (proc_desc) = 0; | |
2393 | PROC_REG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2394 | ptr + 4); | |
2395 | PROC_FREG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2396 | ptr + 12); | |
2397 | PROC_REG_OFFSET (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2398 | ptr + 8); | |
2399 | PROC_FREG_OFFSET (proc_desc) | |
2400 | = bfd_get_32 (sec->objfile->obfd, ptr + 16); | |
2401 | PROC_PC_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2402 | ptr + 28); | |
2403 | proc_desc->pdr.isym = (long) sym; | |
2404 | ||
2405 | return proc_desc; | |
2406 | } | |
2407 | } | |
c906108c SS |
2408 | } |
2409 | ||
6c0d6680 DJ |
2410 | if (b == NULL) |
2411 | return NULL; | |
2412 | ||
2413 | if (startaddr > BLOCK_START (b)) | |
2414 | { | |
2415 | /* This is the "pathological" case referred to in a comment in | |
2416 | print_frame_info. It might be better to move this check into | |
2417 | symbol reading. */ | |
2418 | return NULL; | |
2419 | } | |
2420 | ||
176620f1 | 2421 | sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_DOMAIN, 0, NULL); |
6c0d6680 | 2422 | |
c906108c SS |
2423 | /* If we never found a PDR for this function in symbol reading, then |
2424 | examine prologues to find the information. */ | |
2425 | if (sym) | |
2426 | { | |
2427 | proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); | |
2428 | if (PROC_FRAME_REG (proc_desc) == -1) | |
2429 | return NULL; | |
2430 | else | |
2431 | return proc_desc; | |
2432 | } | |
2433 | else | |
2434 | return NULL; | |
2435 | } | |
2436 | ||
2437 | ||
2438 | static mips_extra_func_info_t | |
479412cd | 2439 | find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame) |
c906108c SS |
2440 | { |
2441 | mips_extra_func_info_t proc_desc; | |
4e0df2df | 2442 | CORE_ADDR startaddr = 0; |
c906108c SS |
2443 | |
2444 | proc_desc = non_heuristic_proc_desc (pc, &startaddr); | |
2445 | ||
2446 | if (proc_desc) | |
2447 | { | |
2448 | /* IF this is the topmost frame AND | |
2449 | * (this proc does not have debugging information OR | |
2450 | * the PC is in the procedure prologue) | |
2451 | * THEN create a "heuristic" proc_desc (by analyzing | |
2452 | * the actual code) to replace the "official" proc_desc. | |
2453 | */ | |
2454 | if (next_frame == NULL) | |
2455 | { | |
2456 | struct symtab_and_line val; | |
2457 | struct symbol *proc_symbol = | |
c86b5b38 | 2458 | PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc); |
c906108c SS |
2459 | |
2460 | if (proc_symbol) | |
2461 | { | |
2462 | val = find_pc_line (BLOCK_START | |
c5aa993b | 2463 | (SYMBOL_BLOCK_VALUE (proc_symbol)), |
c906108c SS |
2464 | 0); |
2465 | val.pc = val.end ? val.end : pc; | |
2466 | } | |
2467 | if (!proc_symbol || pc < val.pc) | |
2468 | { | |
2469 | mips_extra_func_info_t found_heuristic = | |
c86b5b38 MS |
2470 | heuristic_proc_desc (PROC_LOW_ADDR (proc_desc), |
2471 | pc, next_frame, cur_frame); | |
c906108c SS |
2472 | if (found_heuristic) |
2473 | proc_desc = found_heuristic; | |
2474 | } | |
2475 | } | |
2476 | } | |
2477 | else | |
2478 | { | |
2479 | /* Is linked_proc_desc_table really necessary? It only seems to be used | |
c5aa993b JM |
2480 | by procedure call dummys. However, the procedures being called ought |
2481 | to have their own proc_descs, and even if they don't, | |
2482 | heuristic_proc_desc knows how to create them! */ | |
c906108c | 2483 | |
aa1ee363 | 2484 | struct linked_proc_info *link; |
c906108c SS |
2485 | |
2486 | for (link = linked_proc_desc_table; link; link = link->next) | |
c5aa993b JM |
2487 | if (PROC_LOW_ADDR (&link->info) <= pc |
2488 | && PROC_HIGH_ADDR (&link->info) > pc) | |
c906108c SS |
2489 | return &link->info; |
2490 | ||
2491 | if (startaddr == 0) | |
2492 | startaddr = heuristic_proc_start (pc); | |
2493 | ||
2494 | proc_desc = | |
479412cd | 2495 | heuristic_proc_desc (startaddr, pc, next_frame, cur_frame); |
c906108c SS |
2496 | } |
2497 | return proc_desc; | |
2498 | } | |
2499 | ||
2500 | static CORE_ADDR | |
acdb74a0 AC |
2501 | get_frame_pointer (struct frame_info *frame, |
2502 | mips_extra_func_info_t proc_desc) | |
c906108c | 2503 | { |
a4b8ebc8 | 2504 | return (read_next_frame_reg (frame, NUM_REGS + PROC_FRAME_REG (proc_desc)) |
e227b13c AC |
2505 | + PROC_FRAME_OFFSET (proc_desc) |
2506 | - PROC_FRAME_ADJUST (proc_desc)); | |
c906108c SS |
2507 | } |
2508 | ||
5a89d8aa | 2509 | static mips_extra_func_info_t cached_proc_desc; |
c906108c | 2510 | |
f7ab6ec6 | 2511 | static CORE_ADDR |
acdb74a0 | 2512 | mips_frame_chain (struct frame_info *frame) |
c906108c SS |
2513 | { |
2514 | mips_extra_func_info_t proc_desc; | |
2515 | CORE_ADDR tmp; | |
8bedc050 | 2516 | CORE_ADDR saved_pc = DEPRECATED_FRAME_SAVED_PC (frame); |
c906108c | 2517 | |
c906108c SS |
2518 | /* Check if the PC is inside a call stub. If it is, fetch the |
2519 | PC of the caller of that stub. */ | |
5a89d8aa | 2520 | if ((tmp = SKIP_TRAMPOLINE_CODE (saved_pc)) != 0) |
c906108c SS |
2521 | saved_pc = tmp; |
2522 | ||
ae45cd16 | 2523 | if (DEPRECATED_PC_IN_CALL_DUMMY (saved_pc, 0, 0)) |
cedea778 AC |
2524 | { |
2525 | /* A dummy frame, uses SP not FP. Get the old SP value. If all | |
2526 | is well, frame->frame the bottom of the current frame will | |
2527 | contain that value. */ | |
1e2330ba | 2528 | return get_frame_base (frame); |
cedea778 AC |
2529 | } |
2530 | ||
c906108c | 2531 | /* Look up the procedure descriptor for this PC. */ |
479412cd | 2532 | proc_desc = find_proc_desc (saved_pc, frame, 1); |
c906108c SS |
2533 | if (!proc_desc) |
2534 | return 0; | |
2535 | ||
2536 | cached_proc_desc = proc_desc; | |
2537 | ||
2538 | /* If no frame pointer and frame size is zero, we must be at end | |
2539 | of stack (or otherwise hosed). If we don't check frame size, | |
2540 | we loop forever if we see a zero size frame. */ | |
2541 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM | |
2542 | && PROC_FRAME_OFFSET (proc_desc) == 0 | |
7807aa61 MS |
2543 | /* The previous frame from a sigtramp frame might be frameless |
2544 | and have frame size zero. */ | |
5a203e44 | 2545 | && !(get_frame_type (frame) == SIGTRAMP_FRAME) |
cedea778 AC |
2546 | /* For a generic dummy frame, let get_frame_pointer() unwind a |
2547 | register value saved as part of the dummy frame call. */ | |
50abf9e5 | 2548 | && !(DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0))) |
c906108c SS |
2549 | return 0; |
2550 | else | |
2551 | return get_frame_pointer (frame, proc_desc); | |
2552 | } | |
2553 | ||
f7ab6ec6 | 2554 | static void |
acdb74a0 | 2555 | mips_init_extra_frame_info (int fromleaf, struct frame_info *fci) |
c906108c SS |
2556 | { |
2557 | int regnum; | |
f2c16bd6 KB |
2558 | mips_extra_func_info_t proc_desc; |
2559 | ||
2560 | if (get_frame_type (fci) == DUMMY_FRAME) | |
2561 | return; | |
c906108c | 2562 | |
f796e4be KB |
2563 | /* Use proc_desc calculated in frame_chain. When there is no |
2564 | next frame, i.e, get_next_frame (fci) == NULL, we call | |
2565 | find_proc_desc () to calculate it, passing an explicit | |
2566 | NULL as the frame parameter. */ | |
f2c16bd6 | 2567 | proc_desc = |
11c02a10 AC |
2568 | get_next_frame (fci) |
2569 | ? cached_proc_desc | |
f796e4be KB |
2570 | : find_proc_desc (get_frame_pc (fci), |
2571 | NULL /* i.e, get_next_frame (fci) */, | |
2572 | 1); | |
c906108c | 2573 | |
a00a19e9 | 2574 | frame_extra_info_zalloc (fci, sizeof (struct frame_extra_info)); |
cce74817 | 2575 | |
da50a4b7 | 2576 | get_frame_extra_info (fci)->proc_desc = |
c906108c SS |
2577 | proc_desc == &temp_proc_desc ? 0 : proc_desc; |
2578 | if (proc_desc) | |
2579 | { | |
2580 | /* Fixup frame-pointer - only needed for top frame */ | |
2581 | /* This may not be quite right, if proc has a real frame register. | |
c5aa993b JM |
2582 | Get the value of the frame relative sp, procedure might have been |
2583 | interrupted by a signal at it's very start. */ | |
50abf9e5 | 2584 | if (get_frame_pc (fci) == PROC_LOW_ADDR (proc_desc) |
c906108c | 2585 | && !PROC_DESC_IS_DUMMY (proc_desc)) |
a4b8ebc8 | 2586 | deprecated_update_frame_base_hack (fci, read_next_frame_reg (get_next_frame (fci), NUM_REGS + SP_REGNUM)); |
50abf9e5 | 2587 | else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fci), 0, 0)) |
cedea778 AC |
2588 | /* Do not ``fix'' fci->frame. It will have the value of the |
2589 | generic dummy frame's top-of-stack (since the draft | |
2590 | fci->frame is obtained by returning the unwound stack | |
2591 | pointer) and that is what we want. That way the fci->frame | |
2592 | value will match the top-of-stack value that was saved as | |
2593 | part of the dummy frames data. */ | |
2594 | /* Do nothing. */; | |
c906108c | 2595 | else |
11c02a10 | 2596 | deprecated_update_frame_base_hack (fci, get_frame_pointer (get_next_frame (fci), proc_desc)); |
c906108c SS |
2597 | |
2598 | if (proc_desc == &temp_proc_desc) | |
2599 | { | |
2600 | char *name; | |
2601 | ||
2602 | /* Do not set the saved registers for a sigtramp frame, | |
5a203e44 AC |
2603 | mips_find_saved_registers will do that for us. We can't |
2604 | use (get_frame_type (fci) == SIGTRAMP_FRAME), it is not | |
2605 | yet set. */ | |
2606 | /* FIXME: cagney/2002-11-18: This problem will go away once | |
2607 | frame.c:get_prev_frame() is modified to set the frame's | |
2608 | type before calling functions like this. */ | |
50abf9e5 | 2609 | find_pc_partial_function (get_frame_pc (fci), &name, |
c5aa993b | 2610 | (CORE_ADDR *) NULL, (CORE_ADDR *) NULL); |
50abf9e5 | 2611 | if (!PC_IN_SIGTRAMP (get_frame_pc (fci), name)) |
c906108c | 2612 | { |
c5aa993b | 2613 | frame_saved_regs_zalloc (fci); |
e0f7ec59 AC |
2614 | /* Set value of previous frame's stack pointer. |
2615 | Remember that saved_regs[SP_REGNUM] is special in | |
2616 | that it contains the value of the stack pointer | |
2617 | register. The other saved_regs values are addresses | |
2618 | (in the inferior) at which a given register's value | |
2619 | may be found. */ | |
2620 | set_reg_offset (temp_saved_regs, SP_REGNUM, | |
2621 | get_frame_base (fci)); | |
2622 | set_reg_offset (temp_saved_regs, PC_REGNUM, | |
2623 | temp_saved_regs[RA_REGNUM]); | |
1b1d3794 | 2624 | memcpy (deprecated_get_frame_saved_regs (fci), temp_saved_regs, |
e0f7ec59 | 2625 | SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
2626 | } |
2627 | } | |
2628 | ||
2629 | /* hack: if argument regs are saved, guess these contain args */ | |
cce74817 | 2630 | /* assume we can't tell how many args for now */ |
da50a4b7 | 2631 | get_frame_extra_info (fci)->num_args = -1; |
c906108c SS |
2632 | for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--) |
2633 | { | |
c5aa993b | 2634 | if (PROC_REG_MASK (proc_desc) & (1 << regnum)) |
c906108c | 2635 | { |
da50a4b7 | 2636 | get_frame_extra_info (fci)->num_args = regnum - A0_REGNUM + 1; |
c906108c SS |
2637 | break; |
2638 | } | |
c5aa993b | 2639 | } |
c906108c SS |
2640 | } |
2641 | } | |
2642 | ||
2643 | /* MIPS stack frames are almost impenetrable. When execution stops, | |
2644 | we basically have to look at symbol information for the function | |
2645 | that we stopped in, which tells us *which* register (if any) is | |
2646 | the base of the frame pointer, and what offset from that register | |
361d1df0 | 2647 | the frame itself is at. |
c906108c SS |
2648 | |
2649 | This presents a problem when trying to examine a stack in memory | |
2650 | (that isn't executing at the moment), using the "frame" command. We | |
2651 | don't have a PC, nor do we have any registers except SP. | |
2652 | ||
2653 | This routine takes two arguments, SP and PC, and tries to make the | |
2654 | cached frames look as if these two arguments defined a frame on the | |
2655 | cache. This allows the rest of info frame to extract the important | |
2656 | arguments without difficulty. */ | |
2657 | ||
2658 | struct frame_info * | |
acdb74a0 | 2659 | setup_arbitrary_frame (int argc, CORE_ADDR *argv) |
c906108c SS |
2660 | { |
2661 | if (argc != 2) | |
2662 | error ("MIPS frame specifications require two arguments: sp and pc"); | |
2663 | ||
2664 | return create_new_frame (argv[0], argv[1]); | |
2665 | } | |
2666 | ||
f09ded24 AC |
2667 | /* According to the current ABI, should the type be passed in a |
2668 | floating-point register (assuming that there is space)? When there | |
2669 | is no FPU, FP are not even considered as possibile candidates for | |
2670 | FP registers and, consequently this returns false - forces FP | |
2671 | arguments into integer registers. */ | |
2672 | ||
2673 | static int | |
2674 | fp_register_arg_p (enum type_code typecode, struct type *arg_type) | |
2675 | { | |
2676 | return ((typecode == TYPE_CODE_FLT | |
2677 | || (MIPS_EABI | |
2678 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
2679 | && TYPE_NFIELDS (arg_type) == 1 | |
2680 | && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT)) | |
c86b5b38 | 2681 | && MIPS_FPU_TYPE != MIPS_FPU_NONE); |
f09ded24 AC |
2682 | } |
2683 | ||
49e790b0 DJ |
2684 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
2685 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
2686 | ||
2687 | static int | |
2688 | mips_type_needs_double_align (struct type *type) | |
2689 | { | |
2690 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2691 | |
49e790b0 DJ |
2692 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2693 | return 1; | |
2694 | else if (typecode == TYPE_CODE_STRUCT) | |
2695 | { | |
2696 | if (TYPE_NFIELDS (type) < 1) | |
2697 | return 0; | |
2698 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2699 | } | |
2700 | else if (typecode == TYPE_CODE_UNION) | |
2701 | { | |
361d1df0 | 2702 | int i, n; |
49e790b0 DJ |
2703 | |
2704 | n = TYPE_NFIELDS (type); | |
2705 | for (i = 0; i < n; i++) | |
2706 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2707 | return 1; | |
2708 | return 0; | |
2709 | } | |
2710 | return 0; | |
2711 | } | |
2712 | ||
dc604539 AC |
2713 | /* Adjust the address downward (direction of stack growth) so that it |
2714 | is correctly aligned for a new stack frame. */ | |
2715 | static CORE_ADDR | |
2716 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2717 | { | |
5b03f266 | 2718 | return align_down (addr, 16); |
dc604539 AC |
2719 | } |
2720 | ||
f7ab6ec6 | 2721 | static CORE_ADDR |
25ab4790 AC |
2722 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
2723 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
2724 | struct value **args, CORE_ADDR sp, int struct_return, | |
2725 | CORE_ADDR struct_addr) | |
c906108c SS |
2726 | { |
2727 | int argreg; | |
2728 | int float_argreg; | |
2729 | int argnum; | |
2730 | int len = 0; | |
2731 | int stack_offset = 0; | |
2732 | ||
25ab4790 AC |
2733 | /* For shared libraries, "t9" needs to point at the function |
2734 | address. */ | |
2735 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
2736 | ||
2737 | /* Set the return address register to point to the entry point of | |
2738 | the program, where a breakpoint lies in wait. */ | |
2739 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
2740 | ||
c906108c | 2741 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2742 | are properly aligned. The stack has to be at least 64-bit |
2743 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2744 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2745 | aligned, so we round to this widest known alignment. */ | |
2746 | ||
5b03f266 AC |
2747 | sp = align_down (sp, 16); |
2748 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 2749 | |
46e0f506 | 2750 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2751 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2752 | passed in registers, but that's OK. */ |
c906108c | 2753 | for (argnum = 0; argnum < nargs; argnum++) |
5b03f266 | 2754 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
46e0f506 | 2755 | MIPS_STACK_ARGSIZE); |
5b03f266 | 2756 | sp -= align_up (len, 16); |
c906108c | 2757 | |
9ace0497 | 2758 | if (mips_debug) |
46e0f506 | 2759 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
2760 | "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n", |
2761 | paddr_nz (sp), (long) align_up (len, 16)); | |
9ace0497 | 2762 | |
c906108c SS |
2763 | /* Initialize the integer and float register pointers. */ |
2764 | argreg = A0_REGNUM; | |
56cea623 | 2765 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
c906108c | 2766 | |
46e0f506 | 2767 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2768 | if (struct_return) |
9ace0497 AC |
2769 | { |
2770 | if (mips_debug) | |
2771 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2772 | "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 2773 | argreg, paddr_nz (struct_addr)); |
9ace0497 AC |
2774 | write_register (argreg++, struct_addr); |
2775 | } | |
c906108c SS |
2776 | |
2777 | /* Now load as many as possible of the first arguments into | |
2778 | registers, and push the rest onto the stack. Loop thru args | |
2779 | from first to last. */ | |
2780 | for (argnum = 0; argnum < nargs; argnum++) | |
2781 | { | |
2782 | char *val; | |
d9d9c31f | 2783 | char valbuf[MAX_REGISTER_SIZE]; |
ea7c478f | 2784 | struct value *arg = args[argnum]; |
c906108c SS |
2785 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); |
2786 | int len = TYPE_LENGTH (arg_type); | |
2787 | enum type_code typecode = TYPE_CODE (arg_type); | |
2788 | ||
9ace0497 AC |
2789 | if (mips_debug) |
2790 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2791 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 2792 | argnum + 1, len, (int) typecode); |
9ace0497 | 2793 | |
c906108c | 2794 | /* The EABI passes structures that do not fit in a register by |
46e0f506 MS |
2795 | reference. */ |
2796 | if (len > MIPS_SAVED_REGSIZE | |
9ace0497 | 2797 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 2798 | { |
fbd9dcd3 | 2799 | store_unsigned_integer (valbuf, MIPS_SAVED_REGSIZE, VALUE_ADDRESS (arg)); |
c906108c | 2800 | typecode = TYPE_CODE_PTR; |
7a292a7a | 2801 | len = MIPS_SAVED_REGSIZE; |
c906108c | 2802 | val = valbuf; |
9ace0497 AC |
2803 | if (mips_debug) |
2804 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
2805 | } |
2806 | else | |
c5aa993b | 2807 | val = (char *) VALUE_CONTENTS (arg); |
c906108c SS |
2808 | |
2809 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
2810 | even-numbered floating point register. Round the FP register |
2811 | up before the check to see if there are any FP registers | |
46e0f506 MS |
2812 | left. Non MIPS_EABI targets also pass the FP in the integer |
2813 | registers so also round up normal registers. */ | |
acdb74a0 AC |
2814 | if (!FP_REGISTER_DOUBLE |
2815 | && fp_register_arg_p (typecode, arg_type)) | |
2816 | { | |
2817 | if ((float_argreg & 1)) | |
2818 | float_argreg++; | |
2819 | } | |
c906108c SS |
2820 | |
2821 | /* Floating point arguments passed in registers have to be | |
2822 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2823 | are passed in register pairs; the even register gets |
2824 | the low word, and the odd register gets the high word. | |
2825 | On non-EABI processors, the first two floating point arguments are | |
2826 | also copied to general registers, because MIPS16 functions | |
2827 | don't use float registers for arguments. This duplication of | |
2828 | arguments in general registers can't hurt non-MIPS16 functions | |
2829 | because those registers are normally skipped. */ | |
1012bd0e EZ |
2830 | /* MIPS_EABI squeezes a struct that contains a single floating |
2831 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 2832 | stack. */ |
f09ded24 AC |
2833 | if (fp_register_arg_p (typecode, arg_type) |
2834 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
c906108c SS |
2835 | { |
2836 | if (!FP_REGISTER_DOUBLE && len == 8) | |
2837 | { | |
d7449b42 | 2838 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
c906108c SS |
2839 | unsigned long regval; |
2840 | ||
2841 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 2842 | regval = extract_unsigned_integer (val + low_offset, 4); |
9ace0497 | 2843 | if (mips_debug) |
acdb74a0 | 2844 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2845 | float_argreg, phex (regval, 4)); |
c906108c | 2846 | write_register (float_argreg++, regval); |
c906108c SS |
2847 | |
2848 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 2849 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
9ace0497 | 2850 | if (mips_debug) |
acdb74a0 | 2851 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2852 | float_argreg, phex (regval, 4)); |
c906108c | 2853 | write_register (float_argreg++, regval); |
c906108c SS |
2854 | } |
2855 | else | |
2856 | { | |
2857 | /* This is a floating point value that fits entirely | |
2858 | in a single register. */ | |
53a5351d | 2859 | /* On 32 bit ABI's the float_argreg is further adjusted |
46e0f506 | 2860 | above to ensure that it is even register aligned. */ |
9ace0497 AC |
2861 | LONGEST regval = extract_unsigned_integer (val, len); |
2862 | if (mips_debug) | |
acdb74a0 | 2863 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2864 | float_argreg, phex (regval, len)); |
c906108c | 2865 | write_register (float_argreg++, regval); |
c906108c SS |
2866 | } |
2867 | } | |
2868 | else | |
2869 | { | |
2870 | /* Copy the argument to general registers or the stack in | |
2871 | register-sized pieces. Large arguments are split between | |
2872 | registers and stack. */ | |
4246e332 AC |
2873 | /* Note: structs whose size is not a multiple of |
2874 | mips_regsize() are treated specially: Irix cc passes them | |
2875 | in registers where gcc sometimes puts them on the stack. | |
2876 | For maximum compatibility, we will put them in both | |
2877 | places. */ | |
c5aa993b | 2878 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && |
7a292a7a | 2879 | (len % MIPS_SAVED_REGSIZE != 0)); |
46e0f506 | 2880 | |
f09ded24 | 2881 | /* Note: Floating-point values that didn't fit into an FP |
46e0f506 | 2882 | register are only written to memory. */ |
c906108c SS |
2883 | while (len > 0) |
2884 | { | |
ebafbe83 | 2885 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 2886 | int stack_used_p = 0; |
46e0f506 MS |
2887 | int partial_len = |
2888 | len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE; | |
c906108c | 2889 | |
acdb74a0 AC |
2890 | if (mips_debug) |
2891 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2892 | partial_len); | |
2893 | ||
566f0f7a | 2894 | /* Write this portion of the argument to the stack. */ |
f09ded24 AC |
2895 | if (argreg > MIPS_LAST_ARG_REGNUM |
2896 | || odd_sized_struct | |
2897 | || fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2898 | { |
c906108c SS |
2899 | /* Should shorter than int integer values be |
2900 | promoted to int before being stored? */ | |
c906108c | 2901 | int longword_offset = 0; |
9ace0497 | 2902 | CORE_ADDR addr; |
566f0f7a | 2903 | stack_used_p = 1; |
d7449b42 | 2904 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
7a292a7a | 2905 | { |
d929b26f | 2906 | if (MIPS_STACK_ARGSIZE == 8 && |
7a292a7a SS |
2907 | (typecode == TYPE_CODE_INT || |
2908 | typecode == TYPE_CODE_PTR || | |
2909 | typecode == TYPE_CODE_FLT) && len <= 4) | |
d929b26f | 2910 | longword_offset = MIPS_STACK_ARGSIZE - len; |
7a292a7a SS |
2911 | else if ((typecode == TYPE_CODE_STRUCT || |
2912 | typecode == TYPE_CODE_UNION) && | |
d929b26f AC |
2913 | TYPE_LENGTH (arg_type) < MIPS_STACK_ARGSIZE) |
2914 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
7a292a7a | 2915 | } |
c5aa993b | 2916 | |
9ace0497 AC |
2917 | if (mips_debug) |
2918 | { | |
cb3d25d1 MS |
2919 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", |
2920 | paddr_nz (stack_offset)); | |
2921 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
2922 | paddr_nz (longword_offset)); | |
9ace0497 | 2923 | } |
361d1df0 | 2924 | |
9ace0497 AC |
2925 | addr = sp + stack_offset + longword_offset; |
2926 | ||
2927 | if (mips_debug) | |
2928 | { | |
2929 | int i; | |
cb3d25d1 MS |
2930 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
2931 | paddr_nz (addr)); | |
9ace0497 AC |
2932 | for (i = 0; i < partial_len; i++) |
2933 | { | |
cb3d25d1 MS |
2934 | fprintf_unfiltered (gdb_stdlog, "%02x", |
2935 | val[i] & 0xff); | |
9ace0497 AC |
2936 | } |
2937 | } | |
2938 | write_memory (addr, val, partial_len); | |
c906108c SS |
2939 | } |
2940 | ||
f09ded24 AC |
2941 | /* Note!!! This is NOT an else clause. Odd sized |
2942 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 2943 | arguments will not. */ |
566f0f7a | 2944 | /* Write this portion of the argument to a general |
46e0f506 | 2945 | purpose register. */ |
f09ded24 AC |
2946 | if (argreg <= MIPS_LAST_ARG_REGNUM |
2947 | && !fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2948 | { |
9ace0497 | 2949 | LONGEST regval = extract_unsigned_integer (val, partial_len); |
c906108c | 2950 | |
9ace0497 | 2951 | if (mips_debug) |
acdb74a0 | 2952 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 AC |
2953 | argreg, |
2954 | phex (regval, MIPS_SAVED_REGSIZE)); | |
c906108c SS |
2955 | write_register (argreg, regval); |
2956 | argreg++; | |
c906108c | 2957 | } |
c5aa993b | 2958 | |
c906108c SS |
2959 | len -= partial_len; |
2960 | val += partial_len; | |
2961 | ||
566f0f7a AC |
2962 | /* Compute the the offset into the stack at which we |
2963 | will copy the next parameter. | |
2964 | ||
566f0f7a | 2965 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 2966 | only needs to be adjusted when it has been used. */ |
c906108c | 2967 | |
46e0f506 | 2968 | if (stack_used_p) |
5b03f266 | 2969 | stack_offset += align_up (partial_len, MIPS_STACK_ARGSIZE); |
c906108c SS |
2970 | } |
2971 | } | |
9ace0497 AC |
2972 | if (mips_debug) |
2973 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
2974 | } |
2975 | ||
310e9b6a AC |
2976 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
2977 | ||
0f71a2f6 JM |
2978 | /* Return adjusted stack pointer. */ |
2979 | return sp; | |
2980 | } | |
2981 | ||
25ab4790 | 2982 | /* N32/N64 version of push_dummy_call. */ |
ebafbe83 | 2983 | |
f7ab6ec6 | 2984 | static CORE_ADDR |
25ab4790 AC |
2985 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
2986 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
2987 | struct value **args, CORE_ADDR sp, int struct_return, | |
2988 | CORE_ADDR struct_addr) | |
cb3d25d1 MS |
2989 | { |
2990 | int argreg; | |
2991 | int float_argreg; | |
2992 | int argnum; | |
2993 | int len = 0; | |
2994 | int stack_offset = 0; | |
2995 | ||
25ab4790 AC |
2996 | /* For shared libraries, "t9" needs to point at the function |
2997 | address. */ | |
2998 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
2999 | ||
3000 | /* Set the return address register to point to the entry point of | |
3001 | the program, where a breakpoint lies in wait. */ | |
3002 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3003 | ||
cb3d25d1 MS |
3004 | /* First ensure that the stack and structure return address (if any) |
3005 | are properly aligned. The stack has to be at least 64-bit | |
3006 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3007 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3008 | aligned, so we round to this widest known alignment. */ | |
3009 | ||
5b03f266 AC |
3010 | sp = align_down (sp, 16); |
3011 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
3012 | |
3013 | /* Now make space on the stack for the args. */ | |
3014 | for (argnum = 0; argnum < nargs; argnum++) | |
5b03f266 | 3015 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
cb3d25d1 | 3016 | MIPS_STACK_ARGSIZE); |
5b03f266 | 3017 | sp -= align_up (len, 16); |
cb3d25d1 MS |
3018 | |
3019 | if (mips_debug) | |
3020 | fprintf_unfiltered (gdb_stdlog, | |
5b03f266 AC |
3021 | "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n", |
3022 | paddr_nz (sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
3023 | |
3024 | /* Initialize the integer and float register pointers. */ | |
3025 | argreg = A0_REGNUM; | |
56cea623 | 3026 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
cb3d25d1 | 3027 | |
46e0f506 | 3028 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
3029 | if (struct_return) |
3030 | { | |
3031 | if (mips_debug) | |
3032 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3033 | "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 MS |
3034 | argreg, paddr_nz (struct_addr)); |
3035 | write_register (argreg++, struct_addr); | |
3036 | } | |
3037 | ||
3038 | /* Now load as many as possible of the first arguments into | |
3039 | registers, and push the rest onto the stack. Loop thru args | |
3040 | from first to last. */ | |
3041 | for (argnum = 0; argnum < nargs; argnum++) | |
3042 | { | |
3043 | char *val; | |
d9d9c31f | 3044 | char valbuf[MAX_REGISTER_SIZE]; |
cb3d25d1 MS |
3045 | struct value *arg = args[argnum]; |
3046 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3047 | int len = TYPE_LENGTH (arg_type); | |
3048 | enum type_code typecode = TYPE_CODE (arg_type); | |
3049 | ||
3050 | if (mips_debug) | |
3051 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3052 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
3053 | argnum + 1, len, (int) typecode); |
3054 | ||
3055 | val = (char *) VALUE_CONTENTS (arg); | |
3056 | ||
3057 | if (fp_register_arg_p (typecode, arg_type) | |
3058 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3059 | { | |
3060 | /* This is a floating point value that fits entirely | |
3061 | in a single register. */ | |
3062 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3063 | above to ensure that it is even register aligned. */ | |
3064 | LONGEST regval = extract_unsigned_integer (val, len); | |
3065 | if (mips_debug) | |
3066 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3067 | float_argreg, phex (regval, len)); | |
3068 | write_register (float_argreg++, regval); | |
3069 | ||
3070 | if (mips_debug) | |
3071 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3072 | argreg, phex (regval, len)); | |
3073 | write_register (argreg, regval); | |
3074 | argreg += 1; | |
3075 | } | |
3076 | else | |
3077 | { | |
3078 | /* Copy the argument to general registers or the stack in | |
3079 | register-sized pieces. Large arguments are split between | |
3080 | registers and stack. */ | |
4246e332 AC |
3081 | /* Note: structs whose size is not a multiple of |
3082 | mips_regsize() are treated specially: Irix cc passes them | |
3083 | in registers where gcc sometimes puts them on the stack. | |
3084 | For maximum compatibility, we will put them in both | |
3085 | places. */ | |
cb3d25d1 MS |
3086 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && |
3087 | (len % MIPS_SAVED_REGSIZE != 0)); | |
3088 | /* Note: Floating-point values that didn't fit into an FP | |
3089 | register are only written to memory. */ | |
3090 | while (len > 0) | |
3091 | { | |
3092 | /* Rememer if the argument was written to the stack. */ | |
3093 | int stack_used_p = 0; | |
3094 | int partial_len = len < MIPS_SAVED_REGSIZE ? | |
3095 | len : MIPS_SAVED_REGSIZE; | |
3096 | ||
3097 | if (mips_debug) | |
3098 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3099 | partial_len); | |
3100 | ||
3101 | /* Write this portion of the argument to the stack. */ | |
3102 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3103 | || odd_sized_struct | |
3104 | || fp_register_arg_p (typecode, arg_type)) | |
3105 | { | |
3106 | /* Should shorter than int integer values be | |
3107 | promoted to int before being stored? */ | |
3108 | int longword_offset = 0; | |
3109 | CORE_ADDR addr; | |
3110 | stack_used_p = 1; | |
3111 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3112 | { | |
3113 | if (MIPS_STACK_ARGSIZE == 8 && | |
3114 | (typecode == TYPE_CODE_INT || | |
3115 | typecode == TYPE_CODE_PTR || | |
3116 | typecode == TYPE_CODE_FLT) && len <= 4) | |
3117 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
cb3d25d1 MS |
3118 | } |
3119 | ||
3120 | if (mips_debug) | |
3121 | { | |
3122 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3123 | paddr_nz (stack_offset)); | |
3124 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3125 | paddr_nz (longword_offset)); | |
3126 | } | |
3127 | ||
3128 | addr = sp + stack_offset + longword_offset; | |
3129 | ||
3130 | if (mips_debug) | |
3131 | { | |
3132 | int i; | |
3133 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", | |
3134 | paddr_nz (addr)); | |
3135 | for (i = 0; i < partial_len; i++) | |
3136 | { | |
3137 | fprintf_unfiltered (gdb_stdlog, "%02x", | |
3138 | val[i] & 0xff); | |
3139 | } | |
3140 | } | |
3141 | write_memory (addr, val, partial_len); | |
3142 | } | |
3143 | ||
3144 | /* Note!!! This is NOT an else clause. Odd sized | |
3145 | structs may go thru BOTH paths. Floating point | |
3146 | arguments will not. */ | |
3147 | /* Write this portion of the argument to a general | |
3148 | purpose register. */ | |
3149 | if (argreg <= MIPS_LAST_ARG_REGNUM | |
3150 | && !fp_register_arg_p (typecode, arg_type)) | |
3151 | { | |
3152 | LONGEST regval = extract_unsigned_integer (val, partial_len); | |
3153 | ||
3154 | /* A non-floating-point argument being passed in a | |
3155 | general register. If a struct or union, and if | |
3156 | the remaining length is smaller than the register | |
3157 | size, we have to adjust the register value on | |
3158 | big endian targets. | |
3159 | ||
3160 | It does not seem to be necessary to do the | |
3161 | same for integral types. | |
3162 | ||
3163 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3164 | outputting LE O32 with sizeof (struct) < | |
3165 | MIPS_SAVED_REGSIZE, generates a left shift as | |
3166 | part of storing the argument in a register a | |
3167 | register (the left shift isn't generated when | |
3168 | sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it | |
3169 | is quite possible that this is GCC contradicting | |
3170 | the LE/O32 ABI, GDB has not been adjusted to | |
3171 | accommodate this. Either someone needs to | |
3172 | demonstrate that the LE/O32 ABI specifies such a | |
3173 | left shift OR this new ABI gets identified as | |
3174 | such and GDB gets tweaked accordingly. */ | |
3175 | ||
3176 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3177 | && partial_len < MIPS_SAVED_REGSIZE | |
3178 | && (typecode == TYPE_CODE_STRUCT || | |
3179 | typecode == TYPE_CODE_UNION)) | |
3180 | regval <<= ((MIPS_SAVED_REGSIZE - partial_len) * | |
3181 | TARGET_CHAR_BIT); | |
3182 | ||
3183 | if (mips_debug) | |
3184 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3185 | argreg, | |
3186 | phex (regval, MIPS_SAVED_REGSIZE)); | |
3187 | write_register (argreg, regval); | |
3188 | argreg++; | |
3189 | } | |
3190 | ||
3191 | len -= partial_len; | |
3192 | val += partial_len; | |
3193 | ||
3194 | /* Compute the the offset into the stack at which we | |
3195 | will copy the next parameter. | |
3196 | ||
3197 | In N32 (N64?), the stack_offset only needs to be | |
3198 | adjusted when it has been used. */ | |
3199 | ||
3200 | if (stack_used_p) | |
5b03f266 | 3201 | stack_offset += align_up (partial_len, MIPS_STACK_ARGSIZE); |
cb3d25d1 MS |
3202 | } |
3203 | } | |
3204 | if (mips_debug) | |
3205 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3206 | } | |
3207 | ||
310e9b6a AC |
3208 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
3209 | ||
cb3d25d1 MS |
3210 | /* Return adjusted stack pointer. */ |
3211 | return sp; | |
3212 | } | |
3213 | ||
25ab4790 | 3214 | /* O32 version of push_dummy_call. */ |
ebafbe83 | 3215 | |
46cac009 | 3216 | static CORE_ADDR |
25ab4790 AC |
3217 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
3218 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
3219 | struct value **args, CORE_ADDR sp, int struct_return, | |
3220 | CORE_ADDR struct_addr) | |
ebafbe83 MS |
3221 | { |
3222 | int argreg; | |
3223 | int float_argreg; | |
3224 | int argnum; | |
3225 | int len = 0; | |
3226 | int stack_offset = 0; | |
ebafbe83 | 3227 | |
25ab4790 AC |
3228 | /* For shared libraries, "t9" needs to point at the function |
3229 | address. */ | |
3230 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3231 | ||
3232 | /* Set the return address register to point to the entry point of | |
3233 | the program, where a breakpoint lies in wait. */ | |
3234 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3235 | ||
ebafbe83 MS |
3236 | /* First ensure that the stack and structure return address (if any) |
3237 | are properly aligned. The stack has to be at least 64-bit | |
3238 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3239 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3240 | aligned, so we round to this widest known alignment. */ | |
3241 | ||
5b03f266 AC |
3242 | sp = align_down (sp, 16); |
3243 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
3244 | |
3245 | /* Now make space on the stack for the args. */ | |
3246 | for (argnum = 0; argnum < nargs; argnum++) | |
5b03f266 | 3247 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
ebafbe83 | 3248 | MIPS_STACK_ARGSIZE); |
5b03f266 | 3249 | sp -= align_up (len, 16); |
ebafbe83 MS |
3250 | |
3251 | if (mips_debug) | |
3252 | fprintf_unfiltered (gdb_stdlog, | |
5b03f266 AC |
3253 | "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n", |
3254 | paddr_nz (sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
3255 | |
3256 | /* Initialize the integer and float register pointers. */ | |
3257 | argreg = A0_REGNUM; | |
56cea623 | 3258 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
ebafbe83 | 3259 | |
bcb0cc15 | 3260 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3261 | if (struct_return) |
3262 | { | |
3263 | if (mips_debug) | |
3264 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3265 | "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n", |
ebafbe83 MS |
3266 | argreg, paddr_nz (struct_addr)); |
3267 | write_register (argreg++, struct_addr); | |
3268 | stack_offset += MIPS_STACK_ARGSIZE; | |
3269 | } | |
3270 | ||
3271 | /* Now load as many as possible of the first arguments into | |
3272 | registers, and push the rest onto the stack. Loop thru args | |
3273 | from first to last. */ | |
3274 | for (argnum = 0; argnum < nargs; argnum++) | |
3275 | { | |
3276 | char *val; | |
d9d9c31f | 3277 | char valbuf[MAX_REGISTER_SIZE]; |
ebafbe83 MS |
3278 | struct value *arg = args[argnum]; |
3279 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3280 | int len = TYPE_LENGTH (arg_type); | |
3281 | enum type_code typecode = TYPE_CODE (arg_type); | |
3282 | ||
3283 | if (mips_debug) | |
3284 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3285 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3286 | argnum + 1, len, (int) typecode); |
3287 | ||
3288 | val = (char *) VALUE_CONTENTS (arg); | |
3289 | ||
3290 | /* 32-bit ABIs always start floating point arguments in an | |
3291 | even-numbered floating point register. Round the FP register | |
3292 | up before the check to see if there are any FP registers | |
3293 | left. O32/O64 targets also pass the FP in the integer | |
3294 | registers so also round up normal registers. */ | |
3295 | if (!FP_REGISTER_DOUBLE | |
3296 | && fp_register_arg_p (typecode, arg_type)) | |
3297 | { | |
3298 | if ((float_argreg & 1)) | |
3299 | float_argreg++; | |
3300 | } | |
3301 | ||
3302 | /* Floating point arguments passed in registers have to be | |
3303 | treated specially. On 32-bit architectures, doubles | |
3304 | are passed in register pairs; the even register gets | |
3305 | the low word, and the odd register gets the high word. | |
3306 | On O32/O64, the first two floating point arguments are | |
3307 | also copied to general registers, because MIPS16 functions | |
3308 | don't use float registers for arguments. This duplication of | |
3309 | arguments in general registers can't hurt non-MIPS16 functions | |
3310 | because those registers are normally skipped. */ | |
3311 | ||
3312 | if (fp_register_arg_p (typecode, arg_type) | |
3313 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3314 | { | |
3315 | if (!FP_REGISTER_DOUBLE && len == 8) | |
3316 | { | |
3317 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
3318 | unsigned long regval; | |
3319 | ||
3320 | /* Write the low word of the double to the even register(s). */ | |
3321 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3322 | if (mips_debug) | |
3323 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3324 | float_argreg, phex (regval, 4)); | |
3325 | write_register (float_argreg++, regval); | |
3326 | if (mips_debug) | |
3327 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3328 | argreg, phex (regval, 4)); | |
3329 | write_register (argreg++, regval); | |
3330 | ||
3331 | /* Write the high word of the double to the odd register(s). */ | |
3332 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3333 | if (mips_debug) | |
3334 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3335 | float_argreg, phex (regval, 4)); | |
3336 | write_register (float_argreg++, regval); | |
3337 | ||
3338 | if (mips_debug) | |
3339 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3340 | argreg, phex (regval, 4)); | |
3341 | write_register (argreg++, regval); | |
3342 | } | |
3343 | else | |
3344 | { | |
3345 | /* This is a floating point value that fits entirely | |
3346 | in a single register. */ | |
3347 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3348 | above to ensure that it is even register aligned. */ | |
3349 | LONGEST regval = extract_unsigned_integer (val, len); | |
3350 | if (mips_debug) | |
3351 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3352 | float_argreg, phex (regval, len)); | |
3353 | write_register (float_argreg++, regval); | |
3354 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
3355 | registers for each argument. The below is (my | |
3356 | guess) to ensure that the corresponding integer | |
3357 | register has reserved the same space. */ | |
3358 | if (mips_debug) | |
3359 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3360 | argreg, phex (regval, len)); | |
3361 | write_register (argreg, regval); | |
3362 | argreg += FP_REGISTER_DOUBLE ? 1 : 2; | |
3363 | } | |
3364 | /* Reserve space for the FP register. */ | |
5b03f266 | 3365 | stack_offset += align_up (len, MIPS_STACK_ARGSIZE); |
46cac009 AC |
3366 | } |
3367 | else | |
3368 | { | |
3369 | /* Copy the argument to general registers or the stack in | |
3370 | register-sized pieces. Large arguments are split between | |
3371 | registers and stack. */ | |
4246e332 AC |
3372 | /* Note: structs whose size is not a multiple of |
3373 | mips_regsize() are treated specially: Irix cc passes them | |
3374 | in registers where gcc sometimes puts them on the stack. | |
3375 | For maximum compatibility, we will put them in both | |
3376 | places. */ | |
46cac009 AC |
3377 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && |
3378 | (len % MIPS_SAVED_REGSIZE != 0)); | |
3379 | /* Structures should be aligned to eight bytes (even arg registers) | |
3380 | on MIPS_ABI_O32, if their first member has double precision. */ | |
3381 | if (MIPS_SAVED_REGSIZE < 8 | |
3382 | && mips_type_needs_double_align (arg_type)) | |
3383 | { | |
3384 | if ((argreg & 1)) | |
3385 | argreg++; | |
3386 | } | |
3387 | /* Note: Floating-point values that didn't fit into an FP | |
3388 | register are only written to memory. */ | |
3389 | while (len > 0) | |
3390 | { | |
3391 | /* Remember if the argument was written to the stack. */ | |
3392 | int stack_used_p = 0; | |
3393 | int partial_len = | |
3394 | len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE; | |
3395 | ||
3396 | if (mips_debug) | |
3397 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3398 | partial_len); | |
3399 | ||
3400 | /* Write this portion of the argument to the stack. */ | |
3401 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3402 | || odd_sized_struct | |
3403 | || fp_register_arg_p (typecode, arg_type)) | |
3404 | { | |
3405 | /* Should shorter than int integer values be | |
3406 | promoted to int before being stored? */ | |
3407 | int longword_offset = 0; | |
3408 | CORE_ADDR addr; | |
3409 | stack_used_p = 1; | |
3410 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3411 | { | |
3412 | if (MIPS_STACK_ARGSIZE == 8 && | |
3413 | (typecode == TYPE_CODE_INT || | |
3414 | typecode == TYPE_CODE_PTR || | |
3415 | typecode == TYPE_CODE_FLT) && len <= 4) | |
3416 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
3417 | } | |
3418 | ||
3419 | if (mips_debug) | |
3420 | { | |
3421 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3422 | paddr_nz (stack_offset)); | |
3423 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3424 | paddr_nz (longword_offset)); | |
3425 | } | |
3426 | ||
3427 | addr = sp + stack_offset + longword_offset; | |
3428 | ||
3429 | if (mips_debug) | |
3430 | { | |
3431 | int i; | |
3432 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", | |
3433 | paddr_nz (addr)); | |
3434 | for (i = 0; i < partial_len; i++) | |
3435 | { | |
3436 | fprintf_unfiltered (gdb_stdlog, "%02x", | |
3437 | val[i] & 0xff); | |
3438 | } | |
3439 | } | |
3440 | write_memory (addr, val, partial_len); | |
3441 | } | |
3442 | ||
3443 | /* Note!!! This is NOT an else clause. Odd sized | |
3444 | structs may go thru BOTH paths. Floating point | |
3445 | arguments will not. */ | |
3446 | /* Write this portion of the argument to a general | |
3447 | purpose register. */ | |
3448 | if (argreg <= MIPS_LAST_ARG_REGNUM | |
3449 | && !fp_register_arg_p (typecode, arg_type)) | |
3450 | { | |
3451 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 AC |
3452 | /* Value may need to be sign extended, because |
3453 | mips_regsize() != MIPS_SAVED_REGSIZE. */ | |
46cac009 AC |
3454 | |
3455 | /* A non-floating-point argument being passed in a | |
3456 | general register. If a struct or union, and if | |
3457 | the remaining length is smaller than the register | |
3458 | size, we have to adjust the register value on | |
3459 | big endian targets. | |
3460 | ||
3461 | It does not seem to be necessary to do the | |
3462 | same for integral types. | |
3463 | ||
3464 | Also don't do this adjustment on O64 binaries. | |
3465 | ||
3466 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3467 | outputting LE O32 with sizeof (struct) < | |
3468 | MIPS_SAVED_REGSIZE, generates a left shift as | |
3469 | part of storing the argument in a register a | |
3470 | register (the left shift isn't generated when | |
3471 | sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it | |
3472 | is quite possible that this is GCC contradicting | |
3473 | the LE/O32 ABI, GDB has not been adjusted to | |
3474 | accommodate this. Either someone needs to | |
3475 | demonstrate that the LE/O32 ABI specifies such a | |
3476 | left shift OR this new ABI gets identified as | |
3477 | such and GDB gets tweaked accordingly. */ | |
3478 | ||
3479 | if (MIPS_SAVED_REGSIZE < 8 | |
3480 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3481 | && partial_len < MIPS_SAVED_REGSIZE | |
3482 | && (typecode == TYPE_CODE_STRUCT || | |
3483 | typecode == TYPE_CODE_UNION)) | |
3484 | regval <<= ((MIPS_SAVED_REGSIZE - partial_len) * | |
3485 | TARGET_CHAR_BIT); | |
3486 | ||
3487 | if (mips_debug) | |
3488 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3489 | argreg, | |
3490 | phex (regval, MIPS_SAVED_REGSIZE)); | |
3491 | write_register (argreg, regval); | |
3492 | argreg++; | |
3493 | ||
3494 | /* Prevent subsequent floating point arguments from | |
3495 | being passed in floating point registers. */ | |
3496 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3497 | } | |
3498 | ||
3499 | len -= partial_len; | |
3500 | val += partial_len; | |
3501 | ||
3502 | /* Compute the the offset into the stack at which we | |
3503 | will copy the next parameter. | |
3504 | ||
3505 | In older ABIs, the caller reserved space for | |
3506 | registers that contained arguments. This was loosely | |
3507 | refered to as their "home". Consequently, space is | |
3508 | always allocated. */ | |
3509 | ||
5b03f266 | 3510 | stack_offset += align_up (partial_len, MIPS_STACK_ARGSIZE); |
46cac009 AC |
3511 | } |
3512 | } | |
3513 | if (mips_debug) | |
3514 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3515 | } | |
3516 | ||
310e9b6a AC |
3517 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
3518 | ||
46cac009 AC |
3519 | /* Return adjusted stack pointer. */ |
3520 | return sp; | |
3521 | } | |
3522 | ||
25ab4790 | 3523 | /* O64 version of push_dummy_call. */ |
46cac009 AC |
3524 | |
3525 | static CORE_ADDR | |
25ab4790 AC |
3526 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
3527 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
3528 | struct value **args, CORE_ADDR sp, int struct_return, | |
3529 | CORE_ADDR struct_addr) | |
46cac009 AC |
3530 | { |
3531 | int argreg; | |
3532 | int float_argreg; | |
3533 | int argnum; | |
3534 | int len = 0; | |
3535 | int stack_offset = 0; | |
3536 | ||
25ab4790 AC |
3537 | /* For shared libraries, "t9" needs to point at the function |
3538 | address. */ | |
3539 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3540 | ||
3541 | /* Set the return address register to point to the entry point of | |
3542 | the program, where a breakpoint lies in wait. */ | |
3543 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3544 | ||
46cac009 AC |
3545 | /* First ensure that the stack and structure return address (if any) |
3546 | are properly aligned. The stack has to be at least 64-bit | |
3547 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3548 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3549 | aligned, so we round to this widest known alignment. */ | |
3550 | ||
5b03f266 AC |
3551 | sp = align_down (sp, 16); |
3552 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
3553 | |
3554 | /* Now make space on the stack for the args. */ | |
3555 | for (argnum = 0; argnum < nargs; argnum++) | |
5b03f266 | 3556 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
46cac009 | 3557 | MIPS_STACK_ARGSIZE); |
5b03f266 | 3558 | sp -= align_up (len, 16); |
46cac009 AC |
3559 | |
3560 | if (mips_debug) | |
3561 | fprintf_unfiltered (gdb_stdlog, | |
5b03f266 AC |
3562 | "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n", |
3563 | paddr_nz (sp), (long) align_up (len, 16)); | |
46cac009 AC |
3564 | |
3565 | /* Initialize the integer and float register pointers. */ | |
3566 | argreg = A0_REGNUM; | |
56cea623 | 3567 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
46cac009 AC |
3568 | |
3569 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
3570 | if (struct_return) | |
3571 | { | |
3572 | if (mips_debug) | |
3573 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3574 | "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n", |
46cac009 AC |
3575 | argreg, paddr_nz (struct_addr)); |
3576 | write_register (argreg++, struct_addr); | |
3577 | stack_offset += MIPS_STACK_ARGSIZE; | |
3578 | } | |
3579 | ||
3580 | /* Now load as many as possible of the first arguments into | |
3581 | registers, and push the rest onto the stack. Loop thru args | |
3582 | from first to last. */ | |
3583 | for (argnum = 0; argnum < nargs; argnum++) | |
3584 | { | |
3585 | char *val; | |
d9d9c31f | 3586 | char valbuf[MAX_REGISTER_SIZE]; |
46cac009 AC |
3587 | struct value *arg = args[argnum]; |
3588 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3589 | int len = TYPE_LENGTH (arg_type); | |
3590 | enum type_code typecode = TYPE_CODE (arg_type); | |
3591 | ||
3592 | if (mips_debug) | |
3593 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3594 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
3595 | argnum + 1, len, (int) typecode); |
3596 | ||
3597 | val = (char *) VALUE_CONTENTS (arg); | |
3598 | ||
3599 | /* 32-bit ABIs always start floating point arguments in an | |
3600 | even-numbered floating point register. Round the FP register | |
3601 | up before the check to see if there are any FP registers | |
3602 | left. O32/O64 targets also pass the FP in the integer | |
3603 | registers so also round up normal registers. */ | |
3604 | if (!FP_REGISTER_DOUBLE | |
3605 | && fp_register_arg_p (typecode, arg_type)) | |
3606 | { | |
3607 | if ((float_argreg & 1)) | |
3608 | float_argreg++; | |
3609 | } | |
3610 | ||
3611 | /* Floating point arguments passed in registers have to be | |
3612 | treated specially. On 32-bit architectures, doubles | |
3613 | are passed in register pairs; the even register gets | |
3614 | the low word, and the odd register gets the high word. | |
3615 | On O32/O64, the first two floating point arguments are | |
3616 | also copied to general registers, because MIPS16 functions | |
3617 | don't use float registers for arguments. This duplication of | |
3618 | arguments in general registers can't hurt non-MIPS16 functions | |
3619 | because those registers are normally skipped. */ | |
3620 | ||
3621 | if (fp_register_arg_p (typecode, arg_type) | |
3622 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3623 | { | |
3624 | if (!FP_REGISTER_DOUBLE && len == 8) | |
3625 | { | |
3626 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
3627 | unsigned long regval; | |
3628 | ||
3629 | /* Write the low word of the double to the even register(s). */ | |
3630 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3631 | if (mips_debug) | |
3632 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3633 | float_argreg, phex (regval, 4)); | |
3634 | write_register (float_argreg++, regval); | |
3635 | if (mips_debug) | |
3636 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3637 | argreg, phex (regval, 4)); | |
3638 | write_register (argreg++, regval); | |
3639 | ||
3640 | /* Write the high word of the double to the odd register(s). */ | |
3641 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3642 | if (mips_debug) | |
3643 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3644 | float_argreg, phex (regval, 4)); | |
3645 | write_register (float_argreg++, regval); | |
3646 | ||
3647 | if (mips_debug) | |
3648 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3649 | argreg, phex (regval, 4)); | |
3650 | write_register (argreg++, regval); | |
3651 | } | |
3652 | else | |
3653 | { | |
3654 | /* This is a floating point value that fits entirely | |
3655 | in a single register. */ | |
3656 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3657 | above to ensure that it is even register aligned. */ | |
3658 | LONGEST regval = extract_unsigned_integer (val, len); | |
3659 | if (mips_debug) | |
3660 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3661 | float_argreg, phex (regval, len)); | |
3662 | write_register (float_argreg++, regval); | |
3663 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
3664 | registers for each argument. The below is (my | |
3665 | guess) to ensure that the corresponding integer | |
3666 | register has reserved the same space. */ | |
3667 | if (mips_debug) | |
3668 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3669 | argreg, phex (regval, len)); | |
3670 | write_register (argreg, regval); | |
3671 | argreg += FP_REGISTER_DOUBLE ? 1 : 2; | |
3672 | } | |
3673 | /* Reserve space for the FP register. */ | |
5b03f266 | 3674 | stack_offset += align_up (len, MIPS_STACK_ARGSIZE); |
ebafbe83 MS |
3675 | } |
3676 | else | |
3677 | { | |
3678 | /* Copy the argument to general registers or the stack in | |
3679 | register-sized pieces. Large arguments are split between | |
3680 | registers and stack. */ | |
4246e332 AC |
3681 | /* Note: structs whose size is not a multiple of |
3682 | mips_regsize() are treated specially: Irix cc passes them | |
3683 | in registers where gcc sometimes puts them on the stack. | |
3684 | For maximum compatibility, we will put them in both | |
3685 | places. */ | |
ebafbe83 MS |
3686 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && |
3687 | (len % MIPS_SAVED_REGSIZE != 0)); | |
3688 | /* Structures should be aligned to eight bytes (even arg registers) | |
3689 | on MIPS_ABI_O32, if their first member has double precision. */ | |
3690 | if (MIPS_SAVED_REGSIZE < 8 | |
3691 | && mips_type_needs_double_align (arg_type)) | |
3692 | { | |
3693 | if ((argreg & 1)) | |
3694 | argreg++; | |
3695 | } | |
3696 | /* Note: Floating-point values that didn't fit into an FP | |
3697 | register are only written to memory. */ | |
3698 | while (len > 0) | |
3699 | { | |
3700 | /* Remember if the argument was written to the stack. */ | |
3701 | int stack_used_p = 0; | |
3702 | int partial_len = | |
3703 | len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE; | |
3704 | ||
3705 | if (mips_debug) | |
3706 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3707 | partial_len); | |
3708 | ||
3709 | /* Write this portion of the argument to the stack. */ | |
3710 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3711 | || odd_sized_struct | |
3712 | || fp_register_arg_p (typecode, arg_type)) | |
3713 | { | |
3714 | /* Should shorter than int integer values be | |
3715 | promoted to int before being stored? */ | |
3716 | int longword_offset = 0; | |
3717 | CORE_ADDR addr; | |
3718 | stack_used_p = 1; | |
3719 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3720 | { | |
3721 | if (MIPS_STACK_ARGSIZE == 8 && | |
3722 | (typecode == TYPE_CODE_INT || | |
3723 | typecode == TYPE_CODE_PTR || | |
3724 | typecode == TYPE_CODE_FLT) && len <= 4) | |
3725 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
3726 | } | |
3727 | ||
3728 | if (mips_debug) | |
3729 | { | |
3730 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3731 | paddr_nz (stack_offset)); | |
3732 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3733 | paddr_nz (longword_offset)); | |
3734 | } | |
3735 | ||
3736 | addr = sp + stack_offset + longword_offset; | |
3737 | ||
3738 | if (mips_debug) | |
3739 | { | |
3740 | int i; | |
3741 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", | |
3742 | paddr_nz (addr)); | |
3743 | for (i = 0; i < partial_len; i++) | |
3744 | { | |
3745 | fprintf_unfiltered (gdb_stdlog, "%02x", | |
3746 | val[i] & 0xff); | |
3747 | } | |
3748 | } | |
3749 | write_memory (addr, val, partial_len); | |
3750 | } | |
3751 | ||
3752 | /* Note!!! This is NOT an else clause. Odd sized | |
3753 | structs may go thru BOTH paths. Floating point | |
3754 | arguments will not. */ | |
3755 | /* Write this portion of the argument to a general | |
3756 | purpose register. */ | |
3757 | if (argreg <= MIPS_LAST_ARG_REGNUM | |
3758 | && !fp_register_arg_p (typecode, arg_type)) | |
3759 | { | |
3760 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 AC |
3761 | /* Value may need to be sign extended, because |
3762 | mips_regsize() != MIPS_SAVED_REGSIZE. */ | |
ebafbe83 MS |
3763 | |
3764 | /* A non-floating-point argument being passed in a | |
3765 | general register. If a struct or union, and if | |
3766 | the remaining length is smaller than the register | |
3767 | size, we have to adjust the register value on | |
3768 | big endian targets. | |
3769 | ||
3770 | It does not seem to be necessary to do the | |
3771 | same for integral types. | |
3772 | ||
3773 | Also don't do this adjustment on O64 binaries. | |
3774 | ||
3775 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3776 | outputting LE O32 with sizeof (struct) < | |
3777 | MIPS_SAVED_REGSIZE, generates a left shift as | |
3778 | part of storing the argument in a register a | |
3779 | register (the left shift isn't generated when | |
3780 | sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it | |
3781 | is quite possible that this is GCC contradicting | |
3782 | the LE/O32 ABI, GDB has not been adjusted to | |
3783 | accommodate this. Either someone needs to | |
3784 | demonstrate that the LE/O32 ABI specifies such a | |
3785 | left shift OR this new ABI gets identified as | |
3786 | such and GDB gets tweaked accordingly. */ | |
3787 | ||
3788 | if (MIPS_SAVED_REGSIZE < 8 | |
3789 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3790 | && partial_len < MIPS_SAVED_REGSIZE | |
3791 | && (typecode == TYPE_CODE_STRUCT || | |
3792 | typecode == TYPE_CODE_UNION)) | |
3793 | regval <<= ((MIPS_SAVED_REGSIZE - partial_len) * | |
3794 | TARGET_CHAR_BIT); | |
3795 | ||
3796 | if (mips_debug) | |
3797 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3798 | argreg, | |
3799 | phex (regval, MIPS_SAVED_REGSIZE)); | |
3800 | write_register (argreg, regval); | |
3801 | argreg++; | |
3802 | ||
3803 | /* Prevent subsequent floating point arguments from | |
3804 | being passed in floating point registers. */ | |
3805 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3806 | } | |
3807 | ||
3808 | len -= partial_len; | |
3809 | val += partial_len; | |
3810 | ||
3811 | /* Compute the the offset into the stack at which we | |
3812 | will copy the next parameter. | |
3813 | ||
3814 | In older ABIs, the caller reserved space for | |
3815 | registers that contained arguments. This was loosely | |
3816 | refered to as their "home". Consequently, space is | |
3817 | always allocated. */ | |
3818 | ||
5b03f266 | 3819 | stack_offset += align_up (partial_len, MIPS_STACK_ARGSIZE); |
ebafbe83 MS |
3820 | } |
3821 | } | |
3822 | if (mips_debug) | |
3823 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3824 | } | |
3825 | ||
310e9b6a AC |
3826 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
3827 | ||
ebafbe83 MS |
3828 | /* Return adjusted stack pointer. */ |
3829 | return sp; | |
3830 | } | |
3831 | ||
f7ab6ec6 | 3832 | static void |
acdb74a0 | 3833 | mips_pop_frame (void) |
c906108c | 3834 | { |
52f0bd74 | 3835 | int regnum; |
c906108c | 3836 | struct frame_info *frame = get_current_frame (); |
c193f6ac | 3837 | CORE_ADDR new_sp = get_frame_base (frame); |
e227b13c | 3838 | mips_extra_func_info_t proc_desc; |
c906108c | 3839 | |
50abf9e5 | 3840 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0)) |
cedea778 AC |
3841 | { |
3842 | generic_pop_dummy_frame (); | |
3843 | flush_cached_frames (); | |
3844 | return; | |
3845 | } | |
3846 | ||
e227b13c | 3847 | proc_desc = get_frame_extra_info (frame)->proc_desc; |
8bedc050 | 3848 | write_register (PC_REGNUM, DEPRECATED_FRAME_SAVED_PC (frame)); |
e0f7ec59 | 3849 | mips_find_saved_regs (frame); |
c906108c | 3850 | for (regnum = 0; regnum < NUM_REGS; regnum++) |
21f87145 | 3851 | if (regnum != SP_REGNUM && regnum != PC_REGNUM |
1b1d3794 | 3852 | && deprecated_get_frame_saved_regs (frame)[regnum]) |
21f87145 MS |
3853 | { |
3854 | /* Floating point registers must not be sign extended, | |
3855 | in case MIPS_SAVED_REGSIZE = 4 but sizeof (FP0_REGNUM) == 8. */ | |
3856 | ||
56cea623 | 3857 | if (mips_regnum (current_gdbarch)->fp0 <= regnum && regnum < mips_regnum (current_gdbarch)->fp0 + 32) |
21f87145 | 3858 | write_register (regnum, |
1b1d3794 | 3859 | read_memory_unsigned_integer (deprecated_get_frame_saved_regs (frame)[regnum], |
21f87145 MS |
3860 | MIPS_SAVED_REGSIZE)); |
3861 | else | |
3862 | write_register (regnum, | |
1b1d3794 | 3863 | read_memory_integer (deprecated_get_frame_saved_regs (frame)[regnum], |
21f87145 MS |
3864 | MIPS_SAVED_REGSIZE)); |
3865 | } | |
757a7cc6 | 3866 | |
c906108c SS |
3867 | write_register (SP_REGNUM, new_sp); |
3868 | flush_cached_frames (); | |
3869 | ||
c5aa993b | 3870 | if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) |
c906108c SS |
3871 | { |
3872 | struct linked_proc_info *pi_ptr, *prev_ptr; | |
3873 | ||
3874 | for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL; | |
3875 | pi_ptr != NULL; | |
3876 | prev_ptr = pi_ptr, pi_ptr = pi_ptr->next) | |
3877 | { | |
3878 | if (&pi_ptr->info == proc_desc) | |
3879 | break; | |
3880 | } | |
3881 | ||
3882 | if (pi_ptr == NULL) | |
3883 | error ("Can't locate dummy extra frame info\n"); | |
3884 | ||
3885 | if (prev_ptr != NULL) | |
3886 | prev_ptr->next = pi_ptr->next; | |
3887 | else | |
3888 | linked_proc_desc_table = pi_ptr->next; | |
3889 | ||
b8c9b27d | 3890 | xfree (pi_ptr); |
c906108c | 3891 | |
56cea623 | 3892 | write_register (mips_regnum (current_gdbarch)->hi, |
c5aa993b | 3893 | read_memory_integer (new_sp - 2 * MIPS_SAVED_REGSIZE, |
7a292a7a | 3894 | MIPS_SAVED_REGSIZE)); |
56cea623 | 3895 | write_register (mips_regnum (current_gdbarch)->lo, |
c5aa993b | 3896 | read_memory_integer (new_sp - 3 * MIPS_SAVED_REGSIZE, |
7a292a7a | 3897 | MIPS_SAVED_REGSIZE)); |
c906108c | 3898 | if (MIPS_FPU_TYPE != MIPS_FPU_NONE) |
56cea623 | 3899 | write_register (mips_regnum (current_gdbarch)->fp_control_status, |
c5aa993b | 3900 | read_memory_integer (new_sp - 4 * MIPS_SAVED_REGSIZE, |
7a292a7a | 3901 | MIPS_SAVED_REGSIZE)); |
c906108c SS |
3902 | } |
3903 | } | |
3904 | ||
dd824b04 DJ |
3905 | /* Floating point register management. |
3906 | ||
3907 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
3908 | 64bit operations, these early MIPS cpus treat fp register pairs | |
3909 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
3910 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
3911 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
3912 | double precision floats into two 32-bit chunks and store them in | |
3913 | consecutive fp regs. To display 64-bit floats stored in this | |
3914 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
3915 | Throw in user-configurable endianness and you have a real mess. | |
3916 | ||
3917 | The way this works is: | |
3918 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
3919 | double-precision value will be split across two logical registers. | |
3920 | The lower-numbered logical register will hold the low-order bits, | |
3921 | regardless of the processor's endianness. | |
3922 | - If we are on a 64-bit processor, and we are looking for a | |
3923 | single-precision value, it will be in the low ordered bits | |
3924 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
3925 | save slot in memory. | |
3926 | - If we are in 64-bit mode, everything is straightforward. | |
3927 | ||
3928 | Note that this code only deals with "live" registers at the top of the | |
3929 | stack. We will attempt to deal with saved registers later, when | |
3930 | the raw/cooked register interface is in place. (We need a general | |
3931 | interface that can deal with dynamic saved register sizes -- fp | |
3932 | regs could be 32 bits wide in one frame and 64 on the frame above | |
3933 | and below). */ | |
3934 | ||
67b2c998 DJ |
3935 | static struct type * |
3936 | mips_float_register_type (void) | |
3937 | { | |
361d1df0 | 3938 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
3939 | return builtin_type_ieee_single_big; |
3940 | else | |
3941 | return builtin_type_ieee_single_little; | |
3942 | } | |
3943 | ||
3944 | static struct type * | |
3945 | mips_double_register_type (void) | |
3946 | { | |
361d1df0 | 3947 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
3948 | return builtin_type_ieee_double_big; |
3949 | else | |
3950 | return builtin_type_ieee_double_little; | |
3951 | } | |
3952 | ||
dd824b04 DJ |
3953 | /* Copy a 32-bit single-precision value from the current frame |
3954 | into rare_buffer. */ | |
3955 | ||
3956 | static void | |
e11c53d2 AC |
3957 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
3958 | char *rare_buffer) | |
dd824b04 | 3959 | { |
719ec221 | 3960 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 DJ |
3961 | char *raw_buffer = alloca (raw_size); |
3962 | ||
e11c53d2 | 3963 | if (!frame_register_read (frame, regno, raw_buffer)) |
dd824b04 DJ |
3964 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
3965 | if (raw_size == 8) | |
3966 | { | |
3967 | /* We have a 64-bit value for this register. Find the low-order | |
3968 | 32 bits. */ | |
3969 | int offset; | |
3970 | ||
3971 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3972 | offset = 4; | |
3973 | else | |
3974 | offset = 0; | |
3975 | ||
3976 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
3977 | } | |
3978 | else | |
3979 | { | |
3980 | memcpy (rare_buffer, raw_buffer, 4); | |
3981 | } | |
3982 | } | |
3983 | ||
3984 | /* Copy a 64-bit double-precision value from the current frame into | |
3985 | rare_buffer. This may include getting half of it from the next | |
3986 | register. */ | |
3987 | ||
3988 | static void | |
e11c53d2 AC |
3989 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
3990 | char *rare_buffer) | |
dd824b04 | 3991 | { |
719ec221 | 3992 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 DJ |
3993 | |
3994 | if (raw_size == 8 && !mips2_fp_compat ()) | |
3995 | { | |
3996 | /* We have a 64-bit value for this register, and we should use | |
3997 | all 64 bits. */ | |
e11c53d2 | 3998 | if (!frame_register_read (frame, regno, rare_buffer)) |
dd824b04 DJ |
3999 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
4000 | } | |
4001 | else | |
4002 | { | |
56cea623 | 4003 | if ((regno - mips_regnum (current_gdbarch)->fp0) & 1) |
dd824b04 DJ |
4004 | internal_error (__FILE__, __LINE__, |
4005 | "mips_read_fp_register_double: bad access to " | |
4006 | "odd-numbered FP register"); | |
4007 | ||
4008 | /* mips_read_fp_register_single will find the correct 32 bits from | |
4009 | each register. */ | |
4010 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
4011 | { | |
e11c53d2 AC |
4012 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
4013 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 4014 | } |
361d1df0 | 4015 | else |
dd824b04 | 4016 | { |
e11c53d2 AC |
4017 | mips_read_fp_register_single (frame, regno, rare_buffer); |
4018 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
4019 | } |
4020 | } | |
4021 | } | |
4022 | ||
c906108c | 4023 | static void |
e11c53d2 AC |
4024 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
4025 | int regnum) | |
c5aa993b | 4026 | { /* do values for FP (float) regs */ |
dd824b04 | 4027 | char *raw_buffer; |
c906108c | 4028 | double doub, flt1, flt2; /* doubles extracted from raw hex data */ |
f0ef6b29 | 4029 | int inv1, inv2, namelen; |
c5aa993b | 4030 | |
56cea623 | 4031 | raw_buffer = (char *) alloca (2 * register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0)); |
c906108c | 4032 | |
e11c53d2 AC |
4033 | fprintf_filtered (file, "%s:", REGISTER_NAME (regnum)); |
4034 | fprintf_filtered (file, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum)), | |
4035 | ""); | |
f0ef6b29 | 4036 | |
719ec221 | 4037 | if (register_size (current_gdbarch, regnum) == 4 || mips2_fp_compat ()) |
c906108c | 4038 | { |
f0ef6b29 KB |
4039 | /* 4-byte registers: Print hex and floating. Also print even |
4040 | numbered registers as doubles. */ | |
e11c53d2 | 4041 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
67b2c998 | 4042 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c5aa993b | 4043 | |
e11c53d2 | 4044 | print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w', file); |
dd824b04 | 4045 | |
e11c53d2 | 4046 | fprintf_filtered (file, " flt: "); |
1adad886 | 4047 | if (inv1) |
e11c53d2 | 4048 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4049 | else |
e11c53d2 | 4050 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4051 | |
f0ef6b29 KB |
4052 | if (regnum % 2 == 0) |
4053 | { | |
e11c53d2 | 4054 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
4055 | doub = unpack_double (mips_double_register_type (), raw_buffer, |
4056 | &inv2); | |
1adad886 | 4057 | |
e11c53d2 | 4058 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4059 | if (inv2) |
e11c53d2 | 4060 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 4061 | else |
e11c53d2 | 4062 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 4063 | } |
c906108c SS |
4064 | } |
4065 | else | |
dd824b04 | 4066 | { |
f0ef6b29 | 4067 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 4068 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
2f38ef89 | 4069 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c906108c | 4070 | |
e11c53d2 | 4071 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
4072 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2); |
4073 | ||
361d1df0 | 4074 | |
e11c53d2 | 4075 | print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g', file); |
f0ef6b29 | 4076 | |
e11c53d2 | 4077 | fprintf_filtered (file, " flt: "); |
1adad886 | 4078 | if (inv1) |
e11c53d2 | 4079 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 4080 | else |
e11c53d2 | 4081 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4082 | |
e11c53d2 | 4083 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4084 | if (inv2) |
e11c53d2 | 4085 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 4086 | else |
e11c53d2 | 4087 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
4088 | } |
4089 | } | |
4090 | ||
4091 | static void | |
e11c53d2 AC |
4092 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
4093 | int regnum, int all) | |
f0ef6b29 | 4094 | { |
a4b8ebc8 | 4095 | struct gdbarch *gdbarch = get_frame_arch (frame); |
d9d9c31f | 4096 | char raw_buffer[MAX_REGISTER_SIZE]; |
f0ef6b29 | 4097 | int offset; |
1adad886 | 4098 | |
a4b8ebc8 | 4099 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 4100 | { |
e11c53d2 | 4101 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4102 | return; |
4103 | } | |
4104 | ||
4105 | /* Get the data in raw format. */ | |
e11c53d2 | 4106 | if (!frame_register_read (frame, regnum, raw_buffer)) |
f0ef6b29 | 4107 | { |
e11c53d2 | 4108 | fprintf_filtered (file, "%s: [Invalid]", REGISTER_NAME (regnum)); |
f0ef6b29 | 4109 | return; |
c906108c | 4110 | } |
f0ef6b29 | 4111 | |
e11c53d2 | 4112 | fputs_filtered (REGISTER_NAME (regnum), file); |
f0ef6b29 KB |
4113 | |
4114 | /* The problem with printing numeric register names (r26, etc.) is that | |
4115 | the user can't use them on input. Probably the best solution is to | |
4116 | fix it so that either the numeric or the funky (a2, etc.) names | |
4117 | are accepted on input. */ | |
4118 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 4119 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 4120 | else |
e11c53d2 | 4121 | fprintf_filtered (file, ": "); |
f0ef6b29 KB |
4122 | |
4123 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
719ec221 | 4124 | offset = register_size (current_gdbarch, regnum) - register_size (current_gdbarch, regnum); |
f0ef6b29 KB |
4125 | else |
4126 | offset = 0; | |
4127 | ||
a4b8ebc8 | 4128 | print_scalar_formatted (raw_buffer + offset, gdbarch_register_type (gdbarch, regnum), |
e11c53d2 | 4129 | 'x', 0, file); |
c906108c SS |
4130 | } |
4131 | ||
f0ef6b29 KB |
4132 | /* Replacement for generic do_registers_info. |
4133 | Print regs in pretty columns. */ | |
4134 | ||
4135 | static int | |
e11c53d2 AC |
4136 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
4137 | int regnum) | |
f0ef6b29 | 4138 | { |
e11c53d2 AC |
4139 | fprintf_filtered (file, " "); |
4140 | mips_print_fp_register (file, frame, regnum); | |
4141 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
4142 | return regnum + 1; |
4143 | } | |
4144 | ||
4145 | ||
c906108c SS |
4146 | /* Print a row's worth of GP (int) registers, with name labels above */ |
4147 | ||
4148 | static int | |
e11c53d2 | 4149 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 4150 | int start_regnum) |
c906108c | 4151 | { |
a4b8ebc8 | 4152 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 4153 | /* do values for GP (int) regs */ |
d9d9c31f | 4154 | char raw_buffer[MAX_REGISTER_SIZE]; |
4246e332 | 4155 | int ncols = (mips_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */ |
c906108c | 4156 | int col, byte; |
a4b8ebc8 | 4157 | int regnum; |
c906108c SS |
4158 | |
4159 | /* For GP registers, we print a separate row of names above the vals */ | |
e11c53d2 | 4160 | fprintf_filtered (file, " "); |
a4b8ebc8 AC |
4161 | for (col = 0, regnum = start_regnum; |
4162 | col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; | |
4163 | regnum++) | |
c906108c SS |
4164 | { |
4165 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 4166 | continue; /* unused register */ |
a4b8ebc8 | 4167 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
c5aa993b | 4168 | break; /* end the row: reached FP register */ |
4246e332 | 4169 | fprintf_filtered (file, mips_regsize (current_gdbarch) == 8 ? "%17s" : "%9s", |
e11c53d2 | 4170 | REGISTER_NAME (regnum)); |
c906108c SS |
4171 | col++; |
4172 | } | |
a4b8ebc8 | 4173 | /* print the R0 to R31 names */ |
20e6603c AC |
4174 | if ((start_regnum % NUM_REGS) < MIPS_NUMREGS) |
4175 | fprintf_filtered (file, "\n R%-4d", start_regnum % NUM_REGS); | |
4176 | else | |
4177 | fprintf_filtered (file, "\n "); | |
c906108c | 4178 | |
c906108c | 4179 | /* now print the values in hex, 4 or 8 to the row */ |
a4b8ebc8 AC |
4180 | for (col = 0, regnum = start_regnum; |
4181 | col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; | |
4182 | regnum++) | |
c906108c SS |
4183 | { |
4184 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 4185 | continue; /* unused register */ |
a4b8ebc8 | 4186 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
c5aa993b | 4187 | break; /* end row: reached FP register */ |
c906108c | 4188 | /* OK: get the data in raw format. */ |
e11c53d2 | 4189 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c906108c SS |
4190 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); |
4191 | /* pad small registers */ | |
4246e332 AC |
4192 | for (byte = 0; |
4193 | byte < (mips_regsize (current_gdbarch) | |
c73e8f27 | 4194 | - register_size (current_gdbarch, regnum)); |
4246e332 | 4195 | byte++) |
c906108c SS |
4196 | printf_filtered (" "); |
4197 | /* Now print the register value in hex, endian order. */ | |
d7449b42 | 4198 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
719ec221 AC |
4199 | for (byte = register_size (current_gdbarch, regnum) - register_size (current_gdbarch, regnum); |
4200 | byte < register_size (current_gdbarch, regnum); | |
43e526b9 | 4201 | byte++) |
e11c53d2 | 4202 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); |
c906108c | 4203 | else |
c73e8f27 | 4204 | for (byte = register_size (current_gdbarch, regnum) - 1; |
43e526b9 JM |
4205 | byte >= 0; |
4206 | byte--) | |
e11c53d2 AC |
4207 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); |
4208 | fprintf_filtered (file, " "); | |
c906108c SS |
4209 | col++; |
4210 | } | |
c5aa993b | 4211 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 4212 | fprintf_filtered (file, "\n"); |
c906108c SS |
4213 | |
4214 | return regnum; | |
4215 | } | |
4216 | ||
4217 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
4218 | ||
bf1f5b4c | 4219 | static void |
e11c53d2 AC |
4220 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4221 | struct frame_info *frame, int regnum, int all) | |
c906108c | 4222 | { |
c5aa993b | 4223 | if (regnum != -1) /* do one specified register */ |
c906108c | 4224 | { |
a4b8ebc8 | 4225 | gdb_assert (regnum >= NUM_REGS); |
c906108c SS |
4226 | if (*(REGISTER_NAME (regnum)) == '\0') |
4227 | error ("Not a valid register for the current processor type"); | |
4228 | ||
e11c53d2 AC |
4229 | mips_print_register (file, frame, regnum, 0); |
4230 | fprintf_filtered (file, "\n"); | |
c906108c | 4231 | } |
c5aa993b JM |
4232 | else |
4233 | /* do all (or most) registers */ | |
c906108c | 4234 | { |
a4b8ebc8 AC |
4235 | regnum = NUM_REGS; |
4236 | while (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
c906108c | 4237 | { |
a4b8ebc8 | 4238 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
e11c53d2 AC |
4239 | { |
4240 | if (all) /* true for "INFO ALL-REGISTERS" command */ | |
4241 | regnum = print_fp_register_row (file, frame, regnum); | |
4242 | else | |
4243 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
4244 | } | |
c906108c | 4245 | else |
e11c53d2 | 4246 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
4247 | } |
4248 | } | |
4249 | } | |
4250 | ||
c906108c SS |
4251 | /* Is this a branch with a delay slot? */ |
4252 | ||
a14ed312 | 4253 | static int is_delayed (unsigned long); |
c906108c SS |
4254 | |
4255 | static int | |
acdb74a0 | 4256 | is_delayed (unsigned long insn) |
c906108c SS |
4257 | { |
4258 | int i; | |
4259 | for (i = 0; i < NUMOPCODES; ++i) | |
4260 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4261 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4262 | break; | |
4263 | return (i < NUMOPCODES | |
4264 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4265 | | INSN_COND_BRANCH_DELAY | |
4266 | | INSN_COND_BRANCH_LIKELY))); | |
4267 | } | |
4268 | ||
4269 | int | |
acdb74a0 | 4270 | mips_step_skips_delay (CORE_ADDR pc) |
c906108c SS |
4271 | { |
4272 | char buf[MIPS_INSTLEN]; | |
4273 | ||
4274 | /* There is no branch delay slot on MIPS16. */ | |
4275 | if (pc_is_mips16 (pc)) | |
4276 | return 0; | |
4277 | ||
4278 | if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0) | |
4279 | /* If error reading memory, guess that it is not a delayed branch. */ | |
4280 | return 0; | |
c5aa993b | 4281 | return is_delayed ((unsigned long) extract_unsigned_integer (buf, MIPS_INSTLEN)); |
c906108c SS |
4282 | } |
4283 | ||
4284 | ||
74da7425 AC |
4285 | /* Given PC at the function's start address, attempt to find the |
4286 | prologue end using SAL information. Return zero if the skip fails. | |
4287 | ||
4288 | A non-optimized prologue traditionally has one SAL for the function | |
4289 | and a second for the function body. A single line function has | |
4290 | them both pointing at the same line. | |
4291 | ||
4292 | An optimized prologue is similar but the prologue may contain | |
4293 | instructions (SALs) from the instruction body. Need to skip those | |
4294 | while not getting into the function body. | |
4295 | ||
4296 | The functions end point and an increasing SAL line are used as | |
4297 | indicators of the prologue's endpoint. | |
4298 | ||
4299 | This code is based on the function refine_prologue_limit (versions | |
4300 | found in both ia64 and ppc). */ | |
4301 | ||
4302 | static CORE_ADDR | |
4303 | skip_prologue_using_sal (CORE_ADDR func_addr) | |
4304 | { | |
4305 | struct symtab_and_line prologue_sal; | |
4306 | CORE_ADDR start_pc; | |
4307 | CORE_ADDR end_pc; | |
4308 | ||
4309 | /* Get an initial range for the function. */ | |
4310 | find_pc_partial_function (func_addr, NULL, &start_pc, &end_pc); | |
4311 | start_pc += FUNCTION_START_OFFSET; | |
4312 | ||
4313 | prologue_sal = find_pc_line (start_pc, 0); | |
4314 | if (prologue_sal.line != 0) | |
4315 | { | |
4316 | while (prologue_sal.end < end_pc) | |
4317 | { | |
4318 | struct symtab_and_line sal; | |
4319 | ||
4320 | sal = find_pc_line (prologue_sal.end, 0); | |
4321 | if (sal.line == 0) | |
4322 | break; | |
4323 | /* Assume that a consecutive SAL for the same (or larger) | |
4324 | line mark the prologue -> body transition. */ | |
4325 | if (sal.line >= prologue_sal.line) | |
4326 | break; | |
4327 | /* The case in which compiler's optimizer/scheduler has | |
4328 | moved instructions into the prologue. We look ahead in | |
4329 | the function looking for address ranges whose | |
4330 | corresponding line number is less the first one that we | |
4331 | found for the function. This is more conservative then | |
4332 | refine_prologue_limit which scans a large number of SALs | |
4333 | looking for any in the prologue */ | |
4334 | prologue_sal = sal; | |
4335 | } | |
4336 | } | |
4337 | return prologue_sal.end; | |
4338 | } | |
4339 | ||
c906108c SS |
4340 | /* Skip the PC past function prologue instructions (32-bit version). |
4341 | This is a helper function for mips_skip_prologue. */ | |
4342 | ||
4343 | static CORE_ADDR | |
f7b9e9fc | 4344 | mips32_skip_prologue (CORE_ADDR pc) |
c906108c | 4345 | { |
c5aa993b JM |
4346 | t_inst inst; |
4347 | CORE_ADDR end_pc; | |
4348 | int seen_sp_adjust = 0; | |
4349 | int load_immediate_bytes = 0; | |
4350 | ||
74da7425 AC |
4351 | /* Find an upper bound on the prologue. */ |
4352 | end_pc = skip_prologue_using_sal (pc); | |
4353 | if (end_pc == 0) | |
4354 | end_pc = pc + 100; /* Magic. */ | |
4355 | ||
c5aa993b JM |
4356 | /* Skip the typical prologue instructions. These are the stack adjustment |
4357 | instruction and the instructions that save registers on the stack | |
4358 | or in the gcc frame. */ | |
74da7425 | 4359 | for (; pc < end_pc; pc += MIPS_INSTLEN) |
c5aa993b JM |
4360 | { |
4361 | unsigned long high_word; | |
c906108c | 4362 | |
c5aa993b JM |
4363 | inst = mips_fetch_instruction (pc); |
4364 | high_word = (inst >> 16) & 0xffff; | |
c906108c | 4365 | |
c5aa993b JM |
4366 | if (high_word == 0x27bd /* addiu $sp,$sp,offset */ |
4367 | || high_word == 0x67bd) /* daddiu $sp,$sp,offset */ | |
4368 | seen_sp_adjust = 1; | |
4369 | else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */ | |
4370 | inst == 0x03a8e823) /* subu $sp,$sp,$t0 */ | |
4371 | seen_sp_adjust = 1; | |
4372 | else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */ | |
4373 | || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */ | |
4374 | && (inst & 0x001F0000)) /* reg != $zero */ | |
4375 | continue; | |
4376 | ||
4377 | else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */ | |
4378 | continue; | |
4379 | else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000)) | |
4380 | /* sx reg,n($s8) */ | |
4381 | continue; /* reg != $zero */ | |
4382 | ||
4383 | /* move $s8,$sp. With different versions of gas this will be either | |
4384 | `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'. | |
4385 | Accept any one of these. */ | |
4386 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
4387 | continue; | |
4388 | ||
4389 | else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */ | |
4390 | continue; | |
4391 | else if (high_word == 0x3c1c) /* lui $gp,n */ | |
4392 | continue; | |
4393 | else if (high_word == 0x279c) /* addiu $gp,$gp,n */ | |
4394 | continue; | |
4395 | else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
4396 | || inst == 0x033ce021) /* addu $gp,$t9,$gp */ | |
4397 | continue; | |
4398 | /* The following instructions load $at or $t0 with an immediate | |
4399 | value in preparation for a stack adjustment via | |
4400 | subu $sp,$sp,[$at,$t0]. These instructions could also initialize | |
4401 | a local variable, so we accept them only before a stack adjustment | |
4402 | instruction was seen. */ | |
4403 | else if (!seen_sp_adjust) | |
4404 | { | |
4405 | if (high_word == 0x3c01 || /* lui $at,n */ | |
4406 | high_word == 0x3c08) /* lui $t0,n */ | |
4407 | { | |
4408 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
4409 | continue; | |
4410 | } | |
4411 | else if (high_word == 0x3421 || /* ori $at,$at,n */ | |
4412 | high_word == 0x3508 || /* ori $t0,$t0,n */ | |
4413 | high_word == 0x3401 || /* ori $at,$zero,n */ | |
4414 | high_word == 0x3408) /* ori $t0,$zero,n */ | |
4415 | { | |
4416 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
4417 | continue; | |
4418 | } | |
4419 | else | |
4420 | break; | |
4421 | } | |
4422 | else | |
4423 | break; | |
c906108c SS |
4424 | } |
4425 | ||
c5aa993b JM |
4426 | /* In a frameless function, we might have incorrectly |
4427 | skipped some load immediate instructions. Undo the skipping | |
4428 | if the load immediate was not followed by a stack adjustment. */ | |
4429 | if (load_immediate_bytes && !seen_sp_adjust) | |
4430 | pc -= load_immediate_bytes; | |
4431 | return pc; | |
c906108c SS |
4432 | } |
4433 | ||
4434 | /* Skip the PC past function prologue instructions (16-bit version). | |
4435 | This is a helper function for mips_skip_prologue. */ | |
4436 | ||
4437 | static CORE_ADDR | |
f7b9e9fc | 4438 | mips16_skip_prologue (CORE_ADDR pc) |
c906108c | 4439 | { |
c5aa993b JM |
4440 | CORE_ADDR end_pc; |
4441 | int extend_bytes = 0; | |
4442 | int prev_extend_bytes; | |
c906108c | 4443 | |
c5aa993b JM |
4444 | /* Table of instructions likely to be found in a function prologue. */ |
4445 | static struct | |
c906108c SS |
4446 | { |
4447 | unsigned short inst; | |
4448 | unsigned short mask; | |
c5aa993b JM |
4449 | } |
4450 | table[] = | |
4451 | { | |
c906108c | 4452 | { |
c5aa993b JM |
4453 | 0x6300, 0xff00 |
4454 | } | |
4455 | , /* addiu $sp,offset */ | |
4456 | { | |
4457 | 0xfb00, 0xff00 | |
4458 | } | |
4459 | , /* daddiu $sp,offset */ | |
4460 | { | |
4461 | 0xd000, 0xf800 | |
4462 | } | |
4463 | , /* sw reg,n($sp) */ | |
4464 | { | |
4465 | 0xf900, 0xff00 | |
4466 | } | |
4467 | , /* sd reg,n($sp) */ | |
4468 | { | |
4469 | 0x6200, 0xff00 | |
4470 | } | |
4471 | , /* sw $ra,n($sp) */ | |
4472 | { | |
4473 | 0xfa00, 0xff00 | |
4474 | } | |
4475 | , /* sd $ra,n($sp) */ | |
4476 | { | |
4477 | 0x673d, 0xffff | |
4478 | } | |
4479 | , /* move $s1,sp */ | |
4480 | { | |
4481 | 0xd980, 0xff80 | |
4482 | } | |
4483 | , /* sw $a0-$a3,n($s1) */ | |
4484 | { | |
4485 | 0x6704, 0xff1c | |
4486 | } | |
4487 | , /* move reg,$a0-$a3 */ | |
4488 | { | |
4489 | 0xe809, 0xf81f | |
4490 | } | |
4491 | , /* entry pseudo-op */ | |
4492 | { | |
4493 | 0x0100, 0xff00 | |
4494 | } | |
4495 | , /* addiu $s1,$sp,n */ | |
4496 | { | |
4497 | 0, 0 | |
4498 | } /* end of table marker */ | |
4499 | }; | |
4500 | ||
74da7425 AC |
4501 | /* Find an upper bound on the prologue. */ |
4502 | end_pc = skip_prologue_using_sal (pc); | |
4503 | if (end_pc == 0) | |
4504 | end_pc = pc + 100; /* Magic. */ | |
4505 | ||
c5aa993b JM |
4506 | /* Skip the typical prologue instructions. These are the stack adjustment |
4507 | instruction and the instructions that save registers on the stack | |
4508 | or in the gcc frame. */ | |
74da7425 | 4509 | for (; pc < end_pc; pc += MIPS16_INSTLEN) |
c5aa993b JM |
4510 | { |
4511 | unsigned short inst; | |
4512 | int i; | |
c906108c | 4513 | |
c5aa993b | 4514 | inst = mips_fetch_instruction (pc); |
c906108c | 4515 | |
c5aa993b JM |
4516 | /* Normally we ignore an extend instruction. However, if it is |
4517 | not followed by a valid prologue instruction, we must adjust | |
4518 | the pc back over the extend so that it won't be considered | |
4519 | part of the prologue. */ | |
4520 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
4521 | { | |
4522 | extend_bytes = MIPS16_INSTLEN; | |
4523 | continue; | |
4524 | } | |
4525 | prev_extend_bytes = extend_bytes; | |
4526 | extend_bytes = 0; | |
c906108c | 4527 | |
c5aa993b JM |
4528 | /* Check for other valid prologue instructions besides extend. */ |
4529 | for (i = 0; table[i].mask != 0; i++) | |
4530 | if ((inst & table[i].mask) == table[i].inst) /* found, get out */ | |
4531 | break; | |
4532 | if (table[i].mask != 0) /* it was in table? */ | |
4533 | continue; /* ignore it */ | |
4534 | else | |
4535 | /* non-prologue */ | |
4536 | { | |
4537 | /* Return the current pc, adjusted backwards by 2 if | |
4538 | the previous instruction was an extend. */ | |
4539 | return pc - prev_extend_bytes; | |
4540 | } | |
c906108c SS |
4541 | } |
4542 | return pc; | |
4543 | } | |
4544 | ||
4545 | /* To skip prologues, I use this predicate. Returns either PC itself | |
4546 | if the code at PC does not look like a function prologue; otherwise | |
4547 | returns an address that (if we're lucky) follows the prologue. If | |
4548 | LENIENT, then we must skip everything which is involved in setting | |
4549 | up the frame (it's OK to skip more, just so long as we don't skip | |
4550 | anything which might clobber the registers which are being saved. | |
4551 | We must skip more in the case where part of the prologue is in the | |
4552 | delay slot of a non-prologue instruction). */ | |
4553 | ||
f7ab6ec6 | 4554 | static CORE_ADDR |
f7b9e9fc | 4555 | mips_skip_prologue (CORE_ADDR pc) |
c906108c SS |
4556 | { |
4557 | /* See if we can determine the end of the prologue via the symbol table. | |
4558 | If so, then return either PC, or the PC after the prologue, whichever | |
4559 | is greater. */ | |
4560 | ||
4561 | CORE_ADDR post_prologue_pc = after_prologue (pc, NULL); | |
4562 | ||
4563 | if (post_prologue_pc != 0) | |
4564 | return max (pc, post_prologue_pc); | |
4565 | ||
4566 | /* Can't determine prologue from the symbol table, need to examine | |
4567 | instructions. */ | |
4568 | ||
4569 | if (pc_is_mips16 (pc)) | |
f7b9e9fc | 4570 | return mips16_skip_prologue (pc); |
c906108c | 4571 | else |
f7b9e9fc | 4572 | return mips32_skip_prologue (pc); |
c906108c | 4573 | } |
c906108c | 4574 | |
7a292a7a SS |
4575 | /* Determine how a return value is stored within the MIPS register |
4576 | file, given the return type `valtype'. */ | |
4577 | ||
4578 | struct return_value_word | |
4579 | { | |
4580 | int len; | |
4581 | int reg; | |
4582 | int reg_offset; | |
4583 | int buf_offset; | |
4584 | }; | |
4585 | ||
7a292a7a | 4586 | static void |
acdb74a0 AC |
4587 | return_value_location (struct type *valtype, |
4588 | struct return_value_word *hi, | |
4589 | struct return_value_word *lo) | |
7a292a7a SS |
4590 | { |
4591 | int len = TYPE_LENGTH (valtype); | |
c5aa993b | 4592 | |
7a292a7a SS |
4593 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT |
4594 | && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8)) | |
4595 | || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4))) | |
4596 | { | |
4597 | if (!FP_REGISTER_DOUBLE && len == 8) | |
4598 | { | |
4599 | /* We need to break a 64bit float in two 32 bit halves and | |
c5aa993b | 4600 | spread them across a floating-point register pair. */ |
d7449b42 AC |
4601 | lo->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
4602 | hi->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 0 : 4; | |
4603 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
56cea623 | 4604 | && register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) == 8) |
7a292a7a SS |
4605 | ? 4 : 0); |
4606 | hi->reg_offset = lo->reg_offset; | |
56cea623 AC |
4607 | lo->reg = mips_regnum (current_gdbarch)->fp0 + 0; |
4608 | hi->reg = mips_regnum (current_gdbarch)->fp0 + 1; | |
7a292a7a SS |
4609 | lo->len = 4; |
4610 | hi->len = 4; | |
4611 | } | |
4612 | else | |
4613 | { | |
4614 | /* The floating point value fits in a single floating-point | |
c5aa993b | 4615 | register. */ |
d7449b42 | 4616 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
56cea623 | 4617 | && register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) == 8 |
7a292a7a SS |
4618 | && len == 4) |
4619 | ? 4 : 0); | |
56cea623 | 4620 | lo->reg = mips_regnum (current_gdbarch)->fp0; |
7a292a7a SS |
4621 | lo->len = len; |
4622 | lo->buf_offset = 0; | |
4623 | hi->len = 0; | |
4624 | hi->reg_offset = 0; | |
4625 | hi->buf_offset = 0; | |
4626 | hi->reg = 0; | |
4627 | } | |
4628 | } | |
4629 | else | |
4630 | { | |
4631 | /* Locate a result possibly spread across two registers. */ | |
4632 | int regnum = 2; | |
4633 | lo->reg = regnum + 0; | |
4634 | hi->reg = regnum + 1; | |
d7449b42 | 4635 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
4636 | && len < MIPS_SAVED_REGSIZE) |
4637 | { | |
bf1f5b4c MS |
4638 | /* "un-left-justify" the value in the low register */ |
4639 | lo->reg_offset = MIPS_SAVED_REGSIZE - len; | |
bcb0cc15 | 4640 | lo->len = len; |
bf1f5b4c | 4641 | hi->reg_offset = 0; |
7a292a7a SS |
4642 | hi->len = 0; |
4643 | } | |
d7449b42 | 4644 | else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
4645 | && len > MIPS_SAVED_REGSIZE /* odd-size structs */ |
4646 | && len < MIPS_SAVED_REGSIZE * 2 | |
4647 | && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || | |
4648 | TYPE_CODE (valtype) == TYPE_CODE_UNION)) | |
4649 | { | |
4650 | /* "un-left-justify" the value spread across two registers. */ | |
4651 | lo->reg_offset = 2 * MIPS_SAVED_REGSIZE - len; | |
4652 | lo->len = MIPS_SAVED_REGSIZE - lo->reg_offset; | |
4653 | hi->reg_offset = 0; | |
4654 | hi->len = len - lo->len; | |
4655 | } | |
4656 | else | |
4657 | { | |
4658 | /* Only perform a partial copy of the second register. */ | |
4659 | lo->reg_offset = 0; | |
4660 | hi->reg_offset = 0; | |
4661 | if (len > MIPS_SAVED_REGSIZE) | |
4662 | { | |
4663 | lo->len = MIPS_SAVED_REGSIZE; | |
4664 | hi->len = len - MIPS_SAVED_REGSIZE; | |
4665 | } | |
4666 | else | |
4667 | { | |
4668 | lo->len = len; | |
4669 | hi->len = 0; | |
4670 | } | |
4671 | } | |
d7449b42 | 4672 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
719ec221 | 4673 | && register_size (current_gdbarch, regnum) == 8 |
7a292a7a SS |
4674 | && MIPS_SAVED_REGSIZE == 4) |
4675 | { | |
4676 | /* Account for the fact that only the least-signficant part | |
c5aa993b | 4677 | of the register is being used */ |
7a292a7a SS |
4678 | lo->reg_offset += 4; |
4679 | hi->reg_offset += 4; | |
4680 | } | |
4681 | lo->buf_offset = 0; | |
4682 | hi->buf_offset = lo->len; | |
4683 | } | |
4684 | } | |
4685 | ||
4686 | /* Given a return value in `regbuf' with a type `valtype', extract and | |
4687 | copy its value into `valbuf'. */ | |
4688 | ||
46cac009 AC |
4689 | static void |
4690 | mips_eabi_extract_return_value (struct type *valtype, | |
b8b527c5 | 4691 | char regbuf[], |
46cac009 AC |
4692 | char *valbuf) |
4693 | { | |
4694 | struct return_value_word lo; | |
4695 | struct return_value_word hi; | |
4696 | return_value_location (valtype, &hi, &lo); | |
4697 | ||
4698 | memcpy (valbuf + lo.buf_offset, | |
78c63a3b | 4699 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + lo.reg) + lo.reg_offset, |
46cac009 AC |
4700 | lo.len); |
4701 | ||
4702 | if (hi.len > 0) | |
4703 | memcpy (valbuf + hi.buf_offset, | |
78c63a3b | 4704 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + hi.reg) + hi.reg_offset, |
46cac009 AC |
4705 | hi.len); |
4706 | } | |
4707 | ||
46cac009 AC |
4708 | static void |
4709 | mips_o64_extract_return_value (struct type *valtype, | |
b8b527c5 | 4710 | char regbuf[], |
46cac009 AC |
4711 | char *valbuf) |
4712 | { | |
4713 | struct return_value_word lo; | |
4714 | struct return_value_word hi; | |
4715 | return_value_location (valtype, &hi, &lo); | |
4716 | ||
4717 | memcpy (valbuf + lo.buf_offset, | |
78c63a3b | 4718 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + lo.reg) + lo.reg_offset, |
46cac009 AC |
4719 | lo.len); |
4720 | ||
4721 | if (hi.len > 0) | |
4722 | memcpy (valbuf + hi.buf_offset, | |
78c63a3b | 4723 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + hi.reg) + hi.reg_offset, |
46cac009 AC |
4724 | hi.len); |
4725 | } | |
4726 | ||
7a292a7a SS |
4727 | /* Given a return value in `valbuf' with a type `valtype', write it's |
4728 | value into the appropriate register. */ | |
4729 | ||
46cac009 AC |
4730 | static void |
4731 | mips_eabi_store_return_value (struct type *valtype, char *valbuf) | |
4732 | { | |
d9d9c31f | 4733 | char raw_buffer[MAX_REGISTER_SIZE]; |
46cac009 AC |
4734 | struct return_value_word lo; |
4735 | struct return_value_word hi; | |
4736 | return_value_location (valtype, &hi, &lo); | |
4737 | ||
4738 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4739 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
62700349 | 4740 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg), raw_buffer, |
719ec221 | 4741 | register_size (current_gdbarch, lo.reg)); |
46cac009 AC |
4742 | |
4743 | if (hi.len > 0) | |
4744 | { | |
4745 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4746 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
62700349 | 4747 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg), raw_buffer, |
719ec221 | 4748 | register_size (current_gdbarch, hi.reg)); |
46cac009 AC |
4749 | } |
4750 | } | |
4751 | ||
4752 | static void | |
cb1d2653 | 4753 | mips_o64_store_return_value (struct type *valtype, char *valbuf) |
46cac009 | 4754 | { |
d9d9c31f | 4755 | char raw_buffer[MAX_REGISTER_SIZE]; |
46cac009 AC |
4756 | struct return_value_word lo; |
4757 | struct return_value_word hi; | |
4758 | return_value_location (valtype, &hi, &lo); | |
4759 | ||
4760 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4761 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
62700349 | 4762 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg), raw_buffer, |
719ec221 | 4763 | register_size (current_gdbarch, lo.reg)); |
46cac009 AC |
4764 | |
4765 | if (hi.len > 0) | |
4766 | { | |
4767 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4768 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
62700349 | 4769 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg), raw_buffer, |
719ec221 | 4770 | register_size (current_gdbarch, hi.reg)); |
46cac009 AC |
4771 | } |
4772 | } | |
4773 | ||
cb1d2653 AC |
4774 | /* O32 ABI stuff. */ |
4775 | ||
29dfb2ac AC |
4776 | static enum return_value_convention |
4777 | mips_o32_return_value (struct gdbarch *gdbarch, struct type *type, | |
4778 | struct regcache *regcache, | |
4779 | void *readbuf, const void *writebuf) | |
46cac009 | 4780 | { |
cb1d2653 | 4781 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
29dfb2ac AC |
4782 | |
4783 | if (TYPE_CODE (type)== TYPE_CODE_STRUCT | |
4784 | || TYPE_CODE (type)== TYPE_CODE_UNION | |
4785 | || TYPE_CODE (type)== TYPE_CODE_ARRAY) | |
4786 | return RETURN_VALUE_STRUCT_CONVENTION; | |
4787 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4788 | && TYPE_LENGTH (type) == 4 | |
4789 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
46cac009 | 4790 | { |
cb1d2653 AC |
4791 | /* A single-precision floating-point value. It fits in the |
4792 | least significant part of FP0. */ | |
4793 | if (mips_debug) | |
4794 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
29dfb2ac AC |
4795 | mips_xfer_register (regcache, |
4796 | NUM_REGS + mips_regnum (current_gdbarch)->fp0, | |
4797 | TYPE_LENGTH (type), | |
4798 | TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
4799 | return RETURN_VALUE_REGISTER_CONVENTION; | |
cb1d2653 AC |
4800 | } |
4801 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4802 | && TYPE_LENGTH (type) == 8 | |
4803 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4804 | { | |
a4b8ebc8 AC |
4805 | /* A double-precision floating-point value. The most |
4806 | significant part goes in FP1, and the least significant in | |
4807 | FP0. */ | |
cb1d2653 | 4808 | if (mips_debug) |
a4b8ebc8 | 4809 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); |
cb1d2653 AC |
4810 | switch (TARGET_BYTE_ORDER) |
4811 | { | |
4812 | case BFD_ENDIAN_LITTLE: | |
29dfb2ac AC |
4813 | mips_xfer_register (regcache, |
4814 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + 0, | |
4815 | 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
4816 | mips_xfer_register (regcache, | |
4817 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + 1, | |
4818 | 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4); | |
cb1d2653 AC |
4819 | break; |
4820 | case BFD_ENDIAN_BIG: | |
29dfb2ac AC |
4821 | mips_xfer_register (regcache, |
4822 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + 1, | |
4823 | 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
4824 | mips_xfer_register (regcache, | |
4825 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + 0, | |
4826 | 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4); | |
cb1d2653 AC |
4827 | break; |
4828 | default: | |
4829 | internal_error (__FILE__, __LINE__, "bad switch"); | |
4830 | } | |
29dfb2ac | 4831 | return RETURN_VALUE_REGISTER_CONVENTION; |
cb1d2653 AC |
4832 | } |
4833 | #if 0 | |
4834 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4835 | && TYPE_NFIELDS (type) <= 2 | |
4836 | && TYPE_NFIELDS (type) >= 1 | |
4837 | && ((TYPE_NFIELDS (type) == 1 | |
4838 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4839 | == TYPE_CODE_FLT)) | |
4840 | || (TYPE_NFIELDS (type) == 2 | |
4841 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4842 | == TYPE_CODE_FLT) | |
4843 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
4844 | == TYPE_CODE_FLT))) | |
4845 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4846 | { | |
4847 | /* A struct that contains one or two floats. Each value is part | |
4848 | in the least significant part of their floating point | |
4849 | register.. */ | |
d9d9c31f | 4850 | bfd_byte reg[MAX_REGISTER_SIZE]; |
cb1d2653 AC |
4851 | int regnum; |
4852 | int field; | |
56cea623 | 4853 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; |
cb1d2653 AC |
4854 | field < TYPE_NFIELDS (type); |
4855 | field++, regnum += 2) | |
4856 | { | |
4857 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
4858 | / TARGET_CHAR_BIT); | |
4859 | if (mips_debug) | |
4860 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", offset); | |
a4b8ebc8 AC |
4861 | mips_xfer_register (regcache, NUM_REGS + regnum, |
4862 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
29dfb2ac | 4863 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); |
cb1d2653 | 4864 | } |
29dfb2ac | 4865 | return RETURN_VALUE_REGISTER_CONVENTION; |
cb1d2653 AC |
4866 | } |
4867 | #endif | |
4868 | #if 0 | |
4869 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4870 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4871 | { | |
4872 | /* A structure or union. Extract the left justified value, | |
4873 | regardless of the byte order. I.e. DO NOT USE | |
4874 | mips_xfer_lower. */ | |
4875 | int offset; | |
4876 | int regnum; | |
4877 | for (offset = 0, regnum = V0_REGNUM; | |
4878 | offset < TYPE_LENGTH (type); | |
719ec221 | 4879 | offset += register_size (current_gdbarch, regnum), regnum++) |
cb1d2653 | 4880 | { |
719ec221 | 4881 | int xfer = register_size (current_gdbarch, regnum); |
cb1d2653 AC |
4882 | if (offset + xfer > TYPE_LENGTH (type)) |
4883 | xfer = TYPE_LENGTH (type) - offset; | |
4884 | if (mips_debug) | |
4885 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
4886 | offset, xfer, regnum); | |
a4b8ebc8 | 4887 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, |
29dfb2ac | 4888 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
cb1d2653 | 4889 | } |
29dfb2ac | 4890 | return RETURN_VALUE_REGISTER_CONVENTION; |
cb1d2653 AC |
4891 | } |
4892 | #endif | |
4893 | else | |
4894 | { | |
4895 | /* A scalar extract each part but least-significant-byte | |
4896 | justified. o32 thinks registers are 4 byte, regardless of | |
4897 | the ISA. mips_stack_argsize controls this. */ | |
4898 | int offset; | |
4899 | int regnum; | |
4900 | for (offset = 0, regnum = V0_REGNUM; | |
4901 | offset < TYPE_LENGTH (type); | |
4902 | offset += mips_stack_argsize (), regnum++) | |
4903 | { | |
4904 | int xfer = mips_stack_argsize (); | |
4905 | int pos = 0; | |
4906 | if (offset + xfer > TYPE_LENGTH (type)) | |
4907 | xfer = TYPE_LENGTH (type) - offset; | |
4908 | if (mips_debug) | |
4909 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4910 | offset, xfer, regnum); | |
a4b8ebc8 | 4911 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, |
29dfb2ac | 4912 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); |
cb1d2653 | 4913 | } |
29dfb2ac | 4914 | return RETURN_VALUE_REGISTER_CONVENTION; |
46cac009 AC |
4915 | } |
4916 | } | |
4917 | ||
cb1d2653 AC |
4918 | /* N32/N44 ABI stuff. */ |
4919 | ||
29dfb2ac AC |
4920 | static enum return_value_convention |
4921 | mips_n32n64_return_value (struct gdbarch *gdbarch, | |
4922 | struct type *type, struct regcache *regcache, | |
4923 | void *readbuf, const void *writebuf) | |
c906108c | 4924 | { |
88658117 | 4925 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
29dfb2ac AC |
4926 | if (TYPE_CODE (type)== TYPE_CODE_STRUCT |
4927 | || TYPE_CODE (type)== TYPE_CODE_UNION | |
4928 | || TYPE_CODE (type)== TYPE_CODE_ARRAY | |
4929 | || TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE) | |
4930 | return RETURN_VALUE_STRUCT_CONVENTION; | |
4931 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4932 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
7a292a7a | 4933 | { |
88658117 AC |
4934 | /* A floating-point value belongs in the least significant part |
4935 | of FP0. */ | |
4936 | if (mips_debug) | |
4937 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
29dfb2ac AC |
4938 | mips_xfer_register (regcache, |
4939 | NUM_REGS + mips_regnum (current_gdbarch)->fp0, | |
4940 | TYPE_LENGTH (type), | |
4941 | TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
4942 | return RETURN_VALUE_REGISTER_CONVENTION; | |
88658117 AC |
4943 | } |
4944 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4945 | && TYPE_NFIELDS (type) <= 2 | |
4946 | && TYPE_NFIELDS (type) >= 1 | |
4947 | && ((TYPE_NFIELDS (type) == 1 | |
4948 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4949 | == TYPE_CODE_FLT)) | |
4950 | || (TYPE_NFIELDS (type) == 2 | |
4951 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4952 | == TYPE_CODE_FLT) | |
4953 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
4954 | == TYPE_CODE_FLT))) | |
4955 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4956 | { | |
4957 | /* A struct that contains one or two floats. Each value is part | |
4958 | in the least significant part of their floating point | |
4959 | register.. */ | |
d9d9c31f | 4960 | bfd_byte reg[MAX_REGISTER_SIZE]; |
88658117 AC |
4961 | int regnum; |
4962 | int field; | |
56cea623 | 4963 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; |
88658117 AC |
4964 | field < TYPE_NFIELDS (type); |
4965 | field++, regnum += 2) | |
4966 | { | |
4967 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
4968 | / TARGET_CHAR_BIT); | |
4969 | if (mips_debug) | |
4970 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", offset); | |
a4b8ebc8 AC |
4971 | mips_xfer_register (regcache, NUM_REGS + regnum, |
4972 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
29dfb2ac | 4973 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); |
88658117 | 4974 | } |
29dfb2ac | 4975 | return RETURN_VALUE_REGISTER_CONVENTION; |
7a292a7a | 4976 | } |
88658117 AC |
4977 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
4978 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4979 | { | |
4980 | /* A structure or union. Extract the left justified value, | |
4981 | regardless of the byte order. I.e. DO NOT USE | |
4982 | mips_xfer_lower. */ | |
4983 | int offset; | |
4984 | int regnum; | |
4985 | for (offset = 0, regnum = V0_REGNUM; | |
4986 | offset < TYPE_LENGTH (type); | |
719ec221 | 4987 | offset += register_size (current_gdbarch, regnum), regnum++) |
88658117 | 4988 | { |
719ec221 | 4989 | int xfer = register_size (current_gdbarch, regnum); |
88658117 AC |
4990 | if (offset + xfer > TYPE_LENGTH (type)) |
4991 | xfer = TYPE_LENGTH (type) - offset; | |
4992 | if (mips_debug) | |
4993 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
4994 | offset, xfer, regnum); | |
a4b8ebc8 | 4995 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, |
29dfb2ac | 4996 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
88658117 | 4997 | } |
29dfb2ac | 4998 | return RETURN_VALUE_REGISTER_CONVENTION; |
88658117 AC |
4999 | } |
5000 | else | |
5001 | { | |
5002 | /* A scalar extract each part but least-significant-byte | |
5003 | justified. */ | |
5004 | int offset; | |
5005 | int regnum; | |
5006 | for (offset = 0, regnum = V0_REGNUM; | |
5007 | offset < TYPE_LENGTH (type); | |
719ec221 | 5008 | offset += register_size (current_gdbarch, regnum), regnum++) |
88658117 | 5009 | { |
719ec221 | 5010 | int xfer = register_size (current_gdbarch, regnum); |
88658117 AC |
5011 | int pos = 0; |
5012 | if (offset + xfer > TYPE_LENGTH (type)) | |
5013 | xfer = TYPE_LENGTH (type) - offset; | |
5014 | if (mips_debug) | |
5015 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
5016 | offset, xfer, regnum); | |
a4b8ebc8 | 5017 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, |
29dfb2ac | 5018 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); |
88658117 | 5019 | } |
29dfb2ac | 5020 | return RETURN_VALUE_REGISTER_CONVENTION; |
88658117 AC |
5021 | } |
5022 | } | |
5023 | ||
2f1488ce | 5024 | static CORE_ADDR |
6672060b | 5025 | mips_extract_struct_value_address (struct regcache *regcache) |
2f1488ce MS |
5026 | { |
5027 | /* FIXME: This will only work at random. The caller passes the | |
5028 | struct_return address in V0, but it is not preserved. It may | |
5029 | still be there, or this may be a random value. */ | |
77d8f2b4 MS |
5030 | LONGEST val; |
5031 | ||
5032 | regcache_cooked_read_signed (regcache, V0_REGNUM, &val); | |
6672060b | 5033 | return val; |
2f1488ce MS |
5034 | } |
5035 | ||
c906108c SS |
5036 | /* Exported procedure: Is PC in the signal trampoline code */ |
5037 | ||
102182a9 MS |
5038 | static int |
5039 | mips_pc_in_sigtramp (CORE_ADDR pc, char *ignore) | |
c906108c SS |
5040 | { |
5041 | if (sigtramp_address == 0) | |
5042 | fixup_sigtramp (); | |
5043 | return (pc >= sigtramp_address && pc < sigtramp_end); | |
5044 | } | |
5045 | ||
a5ea2558 AC |
5046 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
5047 | used for all MIPS-specific commands. */ | |
5048 | ||
a5ea2558 | 5049 | static void |
acdb74a0 | 5050 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
5051 | { |
5052 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
5053 | } | |
5054 | ||
a5ea2558 | 5055 | static void |
acdb74a0 | 5056 | set_mips_command (char *args, int from_tty) |
a5ea2558 AC |
5057 | { |
5058 | printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
5059 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); | |
5060 | } | |
5061 | ||
c906108c SS |
5062 | /* Commands to show/set the MIPS FPU type. */ |
5063 | ||
c906108c | 5064 | static void |
acdb74a0 | 5065 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 5066 | { |
c906108c SS |
5067 | char *fpu; |
5068 | switch (MIPS_FPU_TYPE) | |
5069 | { | |
5070 | case MIPS_FPU_SINGLE: | |
5071 | fpu = "single-precision"; | |
5072 | break; | |
5073 | case MIPS_FPU_DOUBLE: | |
5074 | fpu = "double-precision"; | |
5075 | break; | |
5076 | case MIPS_FPU_NONE: | |
5077 | fpu = "absent (none)"; | |
5078 | break; | |
93d56215 AC |
5079 | default: |
5080 | internal_error (__FILE__, __LINE__, "bad switch"); | |
c906108c SS |
5081 | } |
5082 | if (mips_fpu_type_auto) | |
5083 | printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
5084 | fpu); | |
5085 | else | |
5086 | printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n", | |
5087 | fpu); | |
5088 | } | |
5089 | ||
5090 | ||
c906108c | 5091 | static void |
acdb74a0 | 5092 | set_mipsfpu_command (char *args, int from_tty) |
c906108c SS |
5093 | { |
5094 | printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
5095 | show_mipsfpu_command (args, from_tty); | |
5096 | } | |
5097 | ||
c906108c | 5098 | static void |
acdb74a0 | 5099 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c SS |
5100 | { |
5101 | mips_fpu_type = MIPS_FPU_SINGLE; | |
5102 | mips_fpu_type_auto = 0; | |
9e364162 | 5103 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_SINGLE; |
c906108c SS |
5104 | } |
5105 | ||
c906108c | 5106 | static void |
acdb74a0 | 5107 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c SS |
5108 | { |
5109 | mips_fpu_type = MIPS_FPU_DOUBLE; | |
5110 | mips_fpu_type_auto = 0; | |
9e364162 | 5111 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_DOUBLE; |
c906108c SS |
5112 | } |
5113 | ||
c906108c | 5114 | static void |
acdb74a0 | 5115 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c SS |
5116 | { |
5117 | mips_fpu_type = MIPS_FPU_NONE; | |
5118 | mips_fpu_type_auto = 0; | |
9e364162 | 5119 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_NONE; |
c906108c SS |
5120 | } |
5121 | ||
c906108c | 5122 | static void |
acdb74a0 | 5123 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
5124 | { |
5125 | mips_fpu_type_auto = 1; | |
5126 | } | |
5127 | ||
c906108c | 5128 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
5129 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
5130 | the relevant processor still exists (it dates back to '94) and | |
5131 | secondly this is not the way to do this. The processor type should | |
5132 | be set by forcing an architecture change. */ | |
c906108c | 5133 | |
691c0433 AC |
5134 | void |
5135 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 5136 | { |
691c0433 | 5137 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
5138 | CORE_ADDR prid; |
5139 | ||
5140 | prid = read_register (PRID_REGNUM); | |
5141 | ||
5142 | if ((prid & ~0xf) == 0x700) | |
691c0433 | 5143 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
5144 | } |
5145 | ||
5146 | /* Just like reinit_frame_cache, but with the right arguments to be | |
5147 | callable as an sfunc. */ | |
5148 | ||
5149 | static void | |
acdb74a0 AC |
5150 | reinit_frame_cache_sfunc (char *args, int from_tty, |
5151 | struct cmd_list_element *c) | |
c906108c SS |
5152 | { |
5153 | reinit_frame_cache (); | |
5154 | } | |
5155 | ||
a89aa300 AC |
5156 | static int |
5157 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 5158 | { |
e5ab0dce | 5159 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
5160 | mips_extra_func_info_t proc_desc; |
5161 | ||
5162 | /* Search for the function containing this address. Set the low bit | |
5163 | of the address when searching, in case we were given an even address | |
5164 | that is the start of a 16-bit function. If we didn't do this, | |
5165 | the search would fail because the symbol table says the function | |
5166 | starts at an odd address, i.e. 1 byte past the given address. */ | |
5167 | memaddr = ADDR_BITS_REMOVE (memaddr); | |
95404a3e | 5168 | proc_desc = non_heuristic_proc_desc (make_mips16_addr (memaddr), NULL); |
c906108c SS |
5169 | |
5170 | /* Make an attempt to determine if this is a 16-bit function. If | |
5171 | the procedure descriptor exists and the address therein is odd, | |
5172 | it's definitely a 16-bit function. Otherwise, we have to just | |
5173 | guess that if the address passed in is odd, it's 16-bits. */ | |
d31431ed AC |
5174 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
5175 | disassembler needs to be able to locally determine the ISA, and | |
5176 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
5177 | work. */ | |
c906108c | 5178 | if (proc_desc) |
d31431ed AC |
5179 | { |
5180 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) | |
5181 | info->mach = bfd_mach_mips16; | |
5182 | } | |
c906108c | 5183 | else |
d31431ed AC |
5184 | { |
5185 | if (pc_is_mips16 (memaddr)) | |
5186 | info->mach = bfd_mach_mips16; | |
5187 | } | |
c906108c SS |
5188 | |
5189 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 5190 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 5191 | |
e5ab0dce AC |
5192 | /* Set the disassembler options. */ |
5193 | if (tdep->mips_abi == MIPS_ABI_N32 | |
5194 | || tdep->mips_abi == MIPS_ABI_N64) | |
5195 | { | |
5196 | /* Set up the disassembler info, so that we get the right | |
5197 | register names from libopcodes. */ | |
5198 | if (tdep->mips_abi == MIPS_ABI_N32) | |
5199 | info->disassembler_options = "gpr-names=n32"; | |
5200 | else | |
5201 | info->disassembler_options = "gpr-names=64"; | |
5202 | info->flavour = bfd_target_elf_flavour; | |
5203 | } | |
5204 | else | |
5205 | /* This string is not recognized explicitly by the disassembler, | |
5206 | but it tells the disassembler to not try to guess the ABI from | |
5207 | the bfd elf headers, such that, if the user overrides the ABI | |
5208 | of a program linked as NewABI, the disassembly will follow the | |
5209 | register naming conventions specified by the user. */ | |
5210 | info->disassembler_options = "gpr-names=32"; | |
5211 | ||
c906108c | 5212 | /* Call the appropriate disassembler based on the target endian-ness. */ |
d7449b42 | 5213 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
5214 | return print_insn_big_mips (memaddr, info); |
5215 | else | |
5216 | return print_insn_little_mips (memaddr, info); | |
5217 | } | |
5218 | ||
c906108c SS |
5219 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program |
5220 | counter value to determine whether a 16- or 32-bit breakpoint should be | |
5221 | used. It returns a pointer to a string of bytes that encode a breakpoint | |
5222 | instruction, stores the length of the string to *lenptr, and adjusts pc | |
5223 | (if necessary) to point to the actual memory location where the | |
5224 | breakpoint should be inserted. */ | |
5225 | ||
f7ab6ec6 | 5226 | static const unsigned char * |
acdb74a0 | 5227 | mips_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr) |
c906108c | 5228 | { |
d7449b42 | 5229 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
5230 | { |
5231 | if (pc_is_mips16 (*pcptr)) | |
5232 | { | |
aaab4dba | 5233 | static unsigned char mips16_big_breakpoint[] = {0xe8, 0xa5}; |
95404a3e | 5234 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5235 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
5236 | return mips16_big_breakpoint; |
5237 | } | |
5238 | else | |
5239 | { | |
aaab4dba AC |
5240 | /* The IDT board uses an unusual breakpoint value, and |
5241 | sometimes gets confused when it sees the usual MIPS | |
5242 | breakpoint instruction. */ | |
5243 | static unsigned char big_breakpoint[] = {0, 0x5, 0, 0xd}; | |
5244 | static unsigned char pmon_big_breakpoint[] = {0, 0, 0, 0xd}; | |
5245 | static unsigned char idt_big_breakpoint[] = {0, 0, 0x0a, 0xd}; | |
c906108c | 5246 | |
c5aa993b | 5247 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
5248 | |
5249 | if (strcmp (target_shortname, "mips") == 0) | |
5250 | return idt_big_breakpoint; | |
5251 | else if (strcmp (target_shortname, "ddb") == 0 | |
5252 | || strcmp (target_shortname, "pmon") == 0 | |
5253 | || strcmp (target_shortname, "lsi") == 0) | |
5254 | return pmon_big_breakpoint; | |
5255 | else | |
5256 | return big_breakpoint; | |
5257 | } | |
5258 | } | |
5259 | else | |
5260 | { | |
5261 | if (pc_is_mips16 (*pcptr)) | |
5262 | { | |
aaab4dba | 5263 | static unsigned char mips16_little_breakpoint[] = {0xa5, 0xe8}; |
95404a3e | 5264 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5265 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
5266 | return mips16_little_breakpoint; |
5267 | } | |
5268 | else | |
5269 | { | |
aaab4dba AC |
5270 | static unsigned char little_breakpoint[] = {0xd, 0, 0x5, 0}; |
5271 | static unsigned char pmon_little_breakpoint[] = {0xd, 0, 0, 0}; | |
5272 | static unsigned char idt_little_breakpoint[] = {0xd, 0x0a, 0, 0}; | |
c906108c | 5273 | |
c5aa993b | 5274 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
5275 | |
5276 | if (strcmp (target_shortname, "mips") == 0) | |
5277 | return idt_little_breakpoint; | |
5278 | else if (strcmp (target_shortname, "ddb") == 0 | |
5279 | || strcmp (target_shortname, "pmon") == 0 | |
5280 | || strcmp (target_shortname, "lsi") == 0) | |
5281 | return pmon_little_breakpoint; | |
5282 | else | |
5283 | return little_breakpoint; | |
5284 | } | |
5285 | } | |
5286 | } | |
5287 | ||
5288 | /* If PC is in a mips16 call or return stub, return the address of the target | |
5289 | PC, which is either the callee or the caller. There are several | |
5290 | cases which must be handled: | |
5291 | ||
5292 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 5293 | target PC is in $31 ($ra). |
c906108c | 5294 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 5295 | and the target PC is in $2. |
c906108c | 5296 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
5297 | before the jal instruction, this is effectively a call stub |
5298 | and the the target PC is in $2. Otherwise this is effectively | |
5299 | a return stub and the target PC is in $18. | |
c906108c SS |
5300 | |
5301 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
5302 | gory details. | |
5303 | ||
5304 | This function implements the SKIP_TRAMPOLINE_CODE macro. | |
c5aa993b | 5305 | */ |
c906108c | 5306 | |
757a7cc6 | 5307 | static CORE_ADDR |
acdb74a0 | 5308 | mips_skip_stub (CORE_ADDR pc) |
c906108c SS |
5309 | { |
5310 | char *name; | |
5311 | CORE_ADDR start_addr; | |
5312 | ||
5313 | /* Find the starting address and name of the function containing the PC. */ | |
5314 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
5315 | return 0; | |
5316 | ||
5317 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
5318 | target PC is in $31 ($ra). */ | |
5319 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5320 | || strcmp (name, "__mips16_ret_df") == 0) | |
6c997a34 | 5321 | return read_signed_register (RA_REGNUM); |
c906108c SS |
5322 | |
5323 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5324 | { | |
5325 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
5326 | and the target PC is in $2. */ | |
5327 | if (name[19] >= '0' && name[19] <= '9') | |
6c997a34 | 5328 | return read_signed_register (2); |
c906108c SS |
5329 | |
5330 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
5331 | before the jal instruction, this is effectively a call stub |
5332 | and the the target PC is in $2. Otherwise this is effectively | |
5333 | a return stub and the target PC is in $18. */ | |
c906108c SS |
5334 | else if (name[19] == 's' || name[19] == 'd') |
5335 | { | |
5336 | if (pc == start_addr) | |
5337 | { | |
5338 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
5339 | stub. Such a stub for a function bar might have a name |
5340 | like __fn_stub_bar, and might look like this: | |
5341 | mfc1 $4,$f13 | |
5342 | mfc1 $5,$f12 | |
5343 | mfc1 $6,$f15 | |
5344 | mfc1 $7,$f14 | |
5345 | la $1,bar (becomes a lui/addiu pair) | |
5346 | jr $1 | |
5347 | So scan down to the lui/addi and extract the target | |
5348 | address from those two instructions. */ | |
c906108c | 5349 | |
6c997a34 | 5350 | CORE_ADDR target_pc = read_signed_register (2); |
c906108c SS |
5351 | t_inst inst; |
5352 | int i; | |
5353 | ||
5354 | /* See if the name of the target function is __fn_stub_*. */ | |
5355 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == 0) | |
5356 | return target_pc; | |
5357 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
5358 | && strcmp (name, "etext") != 0 | |
5359 | && strcmp (name, "_etext") != 0) | |
5360 | return target_pc; | |
5361 | ||
5362 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
5363 | The limit on the search is arbitrarily set to 20 |
5364 | instructions. FIXME. */ | |
c906108c SS |
5365 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN) |
5366 | { | |
c5aa993b JM |
5367 | inst = mips_fetch_instruction (target_pc); |
5368 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
5369 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
5370 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
5371 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
5372 | } |
5373 | ||
5374 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
5375 | return target_pc; | |
5376 | } | |
5377 | else | |
5378 | /* This is the 'return' part of a call stub. The return | |
5379 | address is in $r18. */ | |
6c997a34 | 5380 | return read_signed_register (18); |
c906108c SS |
5381 | } |
5382 | } | |
c5aa993b | 5383 | return 0; /* not a stub */ |
c906108c SS |
5384 | } |
5385 | ||
5386 | ||
5387 | /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline). | |
5388 | This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */ | |
5389 | ||
757a7cc6 | 5390 | static int |
acdb74a0 | 5391 | mips_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
5392 | { |
5393 | CORE_ADDR start_addr; | |
5394 | ||
5395 | /* Find the starting address of the function containing the PC. If the | |
5396 | caller didn't give us a name, look it up at the same time. */ | |
5397 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0) | |
5398 | return 0; | |
5399 | ||
5400 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5401 | { | |
5402 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */ | |
5403 | if (name[19] >= '0' && name[19] <= '9') | |
5404 | return 1; | |
5405 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b | 5406 | before the jal instruction, this is effectively a call stub. */ |
c906108c SS |
5407 | else if (name[19] == 's' || name[19] == 'd') |
5408 | return pc == start_addr; | |
5409 | } | |
5410 | ||
c5aa993b | 5411 | return 0; /* not a stub */ |
c906108c SS |
5412 | } |
5413 | ||
5414 | ||
5415 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
5416 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
5417 | ||
e41b17f0 | 5418 | static int |
acdb74a0 | 5419 | mips_in_return_stub (CORE_ADDR pc, char *name) |
c906108c SS |
5420 | { |
5421 | CORE_ADDR start_addr; | |
5422 | ||
5423 | /* Find the starting address of the function containing the PC. */ | |
5424 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
5425 | return 0; | |
5426 | ||
5427 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */ | |
5428 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5429 | || strcmp (name, "__mips16_ret_df") == 0) | |
5430 | return 1; | |
5431 | ||
5432 | /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start, | |
c5aa993b | 5433 | i.e. after the jal instruction, this is effectively a return stub. */ |
c906108c SS |
5434 | if (strncmp (name, "__mips16_call_stub_", 19) == 0 |
5435 | && (name[19] == 's' || name[19] == 'd') | |
5436 | && pc != start_addr) | |
5437 | return 1; | |
5438 | ||
c5aa993b | 5439 | return 0; /* not a stub */ |
c906108c SS |
5440 | } |
5441 | ||
5442 | ||
5443 | /* Return non-zero if the PC is in a library helper function that should | |
5444 | be ignored. This implements the IGNORE_HELPER_CALL macro. */ | |
5445 | ||
5446 | int | |
acdb74a0 | 5447 | mips_ignore_helper (CORE_ADDR pc) |
c906108c SS |
5448 | { |
5449 | char *name; | |
5450 | ||
5451 | /* Find the starting address and name of the function containing the PC. */ | |
5452 | if (find_pc_partial_function (pc, &name, NULL, NULL) == 0) | |
5453 | return 0; | |
5454 | ||
5455 | /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function | |
5456 | that we want to ignore. */ | |
5457 | return (strcmp (name, "__mips16_ret_sf") == 0 | |
5458 | || strcmp (name, "__mips16_ret_df") == 0); | |
5459 | } | |
5460 | ||
5461 | ||
47a8d4ba AC |
5462 | /* When debugging a 64 MIPS target running a 32 bit ABI, the size of |
5463 | the register stored on the stack (32) is different to its real raw | |
5464 | size (64). The below ensures that registers are fetched from the | |
5465 | stack using their ABI size and then stored into the RAW_BUFFER | |
5466 | using their raw size. | |
5467 | ||
5468 | The alternative to adding this function would be to add an ABI | |
5469 | macro - REGISTER_STACK_SIZE(). */ | |
5470 | ||
5471 | static void | |
acdb74a0 | 5472 | mips_get_saved_register (char *raw_buffer, |
795e1e11 | 5473 | int *optimizedp, |
acdb74a0 AC |
5474 | CORE_ADDR *addrp, |
5475 | struct frame_info *frame, | |
5476 | int regnum, | |
795e1e11 | 5477 | enum lval_type *lvalp) |
47a8d4ba | 5478 | { |
795e1e11 AC |
5479 | CORE_ADDR addrx; |
5480 | enum lval_type lvalx; | |
5481 | int optimizedx; | |
6e51443a | 5482 | int realnumx; |
47a8d4ba | 5483 | |
a4b8ebc8 AC |
5484 | /* Always a pseudo. */ |
5485 | gdb_assert (regnum >= NUM_REGS); | |
47a8d4ba | 5486 | |
795e1e11 AC |
5487 | /* Make certain that all needed parameters are present. */ |
5488 | if (addrp == NULL) | |
5489 | addrp = &addrx; | |
5490 | if (lvalp == NULL) | |
5491 | lvalp = &lvalx; | |
5492 | if (optimizedp == NULL) | |
5493 | optimizedp = &optimizedx; | |
a4b8ebc8 AC |
5494 | |
5495 | if ((regnum % NUM_REGS) == SP_REGNUM) | |
5496 | /* The SP_REGNUM is special, its value is stored in saved_regs. | |
5497 | In fact, it is so special that it can even only be fetched | |
5498 | using a raw register number! Once this code as been converted | |
5499 | to frame-unwind the problem goes away. */ | |
5500 | frame_register_unwind (deprecated_get_next_frame_hack (frame), | |
5501 | regnum % NUM_REGS, optimizedp, lvalp, addrp, | |
5502 | &realnumx, raw_buffer); | |
5503 | else | |
5504 | /* Get it from the next frame. */ | |
5505 | frame_register_unwind (deprecated_get_next_frame_hack (frame), | |
5506 | regnum, optimizedp, lvalp, addrp, | |
5507 | &realnumx, raw_buffer); | |
47a8d4ba | 5508 | } |
2acceee2 | 5509 | |
f7b9e9fc AC |
5510 | /* Immediately after a function call, return the saved pc. |
5511 | Can't always go through the frames for this because on some machines | |
5512 | the new frame is not set up until the new function executes | |
5513 | some instructions. */ | |
5514 | ||
5515 | static CORE_ADDR | |
5516 | mips_saved_pc_after_call (struct frame_info *frame) | |
5517 | { | |
6c997a34 | 5518 | return read_signed_register (RA_REGNUM); |
f7b9e9fc AC |
5519 | } |
5520 | ||
5521 | ||
a4b8ebc8 AC |
5522 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
5523 | [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */ | |
88c72b7d AC |
5524 | |
5525 | static int | |
5526 | mips_stab_reg_to_regnum (int num) | |
5527 | { | |
a4b8ebc8 | 5528 | int regnum; |
2f38ef89 | 5529 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5530 | regnum = num; |
2f38ef89 | 5531 | else if (num >= 38 && num < 70) |
56cea623 | 5532 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 38; |
040b99fd | 5533 | else if (num == 70) |
56cea623 | 5534 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 5535 | else if (num == 71) |
56cea623 | 5536 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 5537 | else |
a4b8ebc8 AC |
5538 | /* This will hopefully (eventually) provoke a warning. Should |
5539 | we be calling complaint() here? */ | |
5540 | return NUM_REGS + NUM_PSEUDO_REGS; | |
5541 | return NUM_REGS + regnum; | |
88c72b7d AC |
5542 | } |
5543 | ||
2f38ef89 | 5544 | |
a4b8ebc8 AC |
5545 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
5546 | NUM_REGS .. 2 * NUM_REGS) REGNUM. */ | |
88c72b7d AC |
5547 | |
5548 | static int | |
2f38ef89 | 5549 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num) |
88c72b7d | 5550 | { |
a4b8ebc8 | 5551 | int regnum; |
2f38ef89 | 5552 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5553 | regnum = num; |
2f38ef89 | 5554 | else if (num >= 32 && num < 64) |
56cea623 | 5555 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 32; |
040b99fd | 5556 | else if (num == 64) |
56cea623 | 5557 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 5558 | else if (num == 65) |
56cea623 | 5559 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 5560 | else |
a4b8ebc8 AC |
5561 | /* This will hopefully (eventually) provoke a warning. Should we |
5562 | be calling complaint() here? */ | |
5563 | return NUM_REGS + NUM_PSEUDO_REGS; | |
5564 | return NUM_REGS + regnum; | |
5565 | } | |
5566 | ||
5567 | static int | |
5568 | mips_register_sim_regno (int regnum) | |
5569 | { | |
5570 | /* Only makes sense to supply raw registers. */ | |
5571 | gdb_assert (regnum >= 0 && regnum < NUM_REGS); | |
5572 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to | |
5573 | decide if it is valid. Should instead define a standard sim/gdb | |
5574 | register numbering scheme. */ | |
5575 | if (REGISTER_NAME (NUM_REGS + regnum) != NULL | |
5576 | && REGISTER_NAME (NUM_REGS + regnum)[0] != '\0') | |
5577 | return regnum; | |
5578 | else | |
5579 | return LEGACY_SIM_REGNO_IGNORE; | |
88c72b7d AC |
5580 | } |
5581 | ||
2f38ef89 | 5582 | |
fc0c74b1 AC |
5583 | /* Convert an integer into an address. By first converting the value |
5584 | into a pointer and then extracting it signed, the address is | |
5585 | guarenteed to be correctly sign extended. */ | |
5586 | ||
5587 | static CORE_ADDR | |
5588 | mips_integer_to_address (struct type *type, void *buf) | |
5589 | { | |
5590 | char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5591 | LONGEST val = unpack_long (type, buf); | |
5592 | store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val); | |
5593 | return extract_signed_integer (tmp, | |
5594 | TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5595 | } | |
5596 | ||
caaa3122 DJ |
5597 | static void |
5598 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
5599 | { | |
5600 | enum mips_abi *abip = (enum mips_abi *) obj; | |
5601 | const char *name = bfd_get_section_name (abfd, sect); | |
5602 | ||
5603 | if (*abip != MIPS_ABI_UNKNOWN) | |
5604 | return; | |
5605 | ||
5606 | if (strncmp (name, ".mdebug.", 8) != 0) | |
5607 | return; | |
5608 | ||
5609 | if (strcmp (name, ".mdebug.abi32") == 0) | |
5610 | *abip = MIPS_ABI_O32; | |
5611 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
5612 | *abip = MIPS_ABI_N32; | |
62a49b2c | 5613 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 5614 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
5615 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
5616 | *abip = MIPS_ABI_O64; | |
5617 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
5618 | *abip = MIPS_ABI_EABI32; | |
5619 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
5620 | *abip = MIPS_ABI_EABI64; | |
5621 | else | |
5622 | warning ("unsupported ABI %s.", name + 8); | |
5623 | } | |
5624 | ||
2e4ebe70 DJ |
5625 | static enum mips_abi |
5626 | global_mips_abi (void) | |
5627 | { | |
5628 | int i; | |
5629 | ||
5630 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
5631 | if (mips_abi_strings[i] == mips_abi_string) | |
5632 | return (enum mips_abi) i; | |
5633 | ||
5634 | internal_error (__FILE__, __LINE__, | |
5635 | "unknown ABI string"); | |
5636 | } | |
5637 | ||
c2d11a7d | 5638 | static struct gdbarch * |
acdb74a0 AC |
5639 | mips_gdbarch_init (struct gdbarch_info info, |
5640 | struct gdbarch_list *arches) | |
c2d11a7d | 5641 | { |
c2d11a7d JM |
5642 | struct gdbarch *gdbarch; |
5643 | struct gdbarch_tdep *tdep; | |
5644 | int elf_flags; | |
2e4ebe70 | 5645 | enum mips_abi mips_abi, found_abi, wanted_abi; |
a4b8ebc8 | 5646 | int num_regs; |
c2d11a7d | 5647 | |
70f80edf JT |
5648 | elf_flags = 0; |
5649 | ||
5650 | if (info.abfd) | |
5651 | { | |
5652 | /* First of all, extract the elf_flags, if available. */ | |
5653 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5654 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
70f80edf | 5655 | } |
c2d11a7d | 5656 | |
102182a9 | 5657 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
5658 | switch ((elf_flags & EF_MIPS_ABI)) |
5659 | { | |
5660 | case E_MIPS_ABI_O32: | |
5661 | mips_abi = MIPS_ABI_O32; | |
5662 | break; | |
5663 | case E_MIPS_ABI_O64: | |
5664 | mips_abi = MIPS_ABI_O64; | |
5665 | break; | |
5666 | case E_MIPS_ABI_EABI32: | |
5667 | mips_abi = MIPS_ABI_EABI32; | |
5668 | break; | |
5669 | case E_MIPS_ABI_EABI64: | |
4a7f7ba8 | 5670 | mips_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
5671 | break; |
5672 | default: | |
acdb74a0 AC |
5673 | if ((elf_flags & EF_MIPS_ABI2)) |
5674 | mips_abi = MIPS_ABI_N32; | |
5675 | else | |
5676 | mips_abi = MIPS_ABI_UNKNOWN; | |
0dadbba0 AC |
5677 | break; |
5678 | } | |
acdb74a0 | 5679 | |
caaa3122 DJ |
5680 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
5681 | if (mips_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) | |
5682 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &mips_abi); | |
5683 | ||
2e4ebe70 DJ |
5684 | /* If we have no bfd, then mips_abi will still be MIPS_ABI_UNKNOWN. |
5685 | Use the ABI from the last architecture if there is one. */ | |
5686 | if (info.abfd == NULL && arches != NULL) | |
5687 | mips_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
5688 | ||
32a6503c | 5689 | /* Try the architecture for any hint of the correct ABI. */ |
bf64bfd6 AC |
5690 | if (mips_abi == MIPS_ABI_UNKNOWN |
5691 | && info.bfd_arch_info != NULL | |
5692 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5693 | { | |
5694 | switch (info.bfd_arch_info->mach) | |
5695 | { | |
5696 | case bfd_mach_mips3900: | |
5697 | mips_abi = MIPS_ABI_EABI32; | |
5698 | break; | |
5699 | case bfd_mach_mips4100: | |
5700 | case bfd_mach_mips5000: | |
5701 | mips_abi = MIPS_ABI_EABI64; | |
5702 | break; | |
1d06468c EZ |
5703 | case bfd_mach_mips8000: |
5704 | case bfd_mach_mips10000: | |
32a6503c KB |
5705 | /* On Irix, ELF64 executables use the N64 ABI. The |
5706 | pseudo-sections which describe the ABI aren't present | |
5707 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
5708 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
5709 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
5710 | mips_abi = MIPS_ABI_N64; | |
5711 | else | |
5712 | mips_abi = MIPS_ABI_N32; | |
1d06468c | 5713 | break; |
bf64bfd6 AC |
5714 | } |
5715 | } | |
2e4ebe70 | 5716 | |
2e4ebe70 DJ |
5717 | if (mips_abi == MIPS_ABI_UNKNOWN) |
5718 | mips_abi = MIPS_ABI_O32; | |
5719 | ||
5720 | /* Now that we have found what the ABI for this binary would be, | |
5721 | check whether the user is overriding it. */ | |
5722 | found_abi = mips_abi; | |
5723 | wanted_abi = global_mips_abi (); | |
5724 | if (wanted_abi != MIPS_ABI_UNKNOWN) | |
5725 | mips_abi = wanted_abi; | |
5726 | ||
4b9b3959 AC |
5727 | if (gdbarch_debug) |
5728 | { | |
5729 | fprintf_unfiltered (gdb_stdlog, | |
9ace0497 | 5730 | "mips_gdbarch_init: elf_flags = 0x%08x\n", |
4b9b3959 | 5731 | elf_flags); |
4b9b3959 AC |
5732 | fprintf_unfiltered (gdb_stdlog, |
5733 | "mips_gdbarch_init: mips_abi = %d\n", | |
5734 | mips_abi); | |
2e4ebe70 DJ |
5735 | fprintf_unfiltered (gdb_stdlog, |
5736 | "mips_gdbarch_init: found_mips_abi = %d\n", | |
5737 | found_abi); | |
4b9b3959 | 5738 | } |
0dadbba0 | 5739 | |
c2d11a7d JM |
5740 | /* try to find a pre-existing architecture */ |
5741 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
5742 | arches != NULL; | |
5743 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
5744 | { | |
5745 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 5746 | using. */ |
9103eae0 | 5747 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 5748 | continue; |
9103eae0 | 5749 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 5750 | continue; |
719ec221 AC |
5751 | /* Need to be pedantic about which register virtual size is |
5752 | used. */ | |
5753 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
5754 | != mips64_transfers_32bit_regs_p) | |
5755 | continue; | |
4be87837 | 5756 | return arches->gdbarch; |
c2d11a7d JM |
5757 | } |
5758 | ||
102182a9 | 5759 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
5760 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
5761 | gdbarch = gdbarch_alloc (&info, tdep); | |
5762 | tdep->elf_flags = elf_flags; | |
719ec221 | 5763 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
c2d11a7d | 5764 | |
102182a9 | 5765 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
5766 | set_gdbarch_short_bit (gdbarch, 16); |
5767 | set_gdbarch_int_bit (gdbarch, 32); | |
5768 | set_gdbarch_float_bit (gdbarch, 32); | |
5769 | set_gdbarch_double_bit (gdbarch, 64); | |
5770 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
5771 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
5772 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
5773 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
2e4ebe70 | 5774 | tdep->found_abi = found_abi; |
0dadbba0 | 5775 | tdep->mips_abi = mips_abi; |
1d06468c | 5776 | |
f7ab6ec6 MS |
5777 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
5778 | mips_elf_make_msymbol_special); | |
5779 | ||
56cea623 AC |
5780 | /* Fill in the OS dependant register numbers. */ |
5781 | { | |
5782 | struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, | |
5783 | struct mips_regnum); | |
5784 | tdep->regnum = regnum; | |
5785 | if (info.osabi == GDB_OSABI_IRIX) | |
5786 | { | |
5787 | regnum->fp0 = 32; | |
5788 | regnum->pc = 64; | |
5789 | regnum->cause = 65; | |
5790 | regnum->badvaddr = 66; | |
5791 | regnum->hi = 67; | |
5792 | regnum->lo = 68; | |
5793 | regnum->fp_control_status = 69; | |
5794 | regnum->fp_implementation_revision = 70; | |
5795 | num_regs = 71; | |
5796 | } | |
5797 | else | |
5798 | { | |
5799 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5800 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5801 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5802 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5803 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5804 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5805 | regnum->fp_control_status = 70; | |
5806 | regnum->fp_implementation_revision = 71; | |
5807 | num_regs = 90; | |
5808 | } | |
5809 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been | |
5810 | replaced by read_pc? */ | |
5811 | set_gdbarch_pc_regnum (gdbarch, regnum->pc); | |
5812 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); | |
5813 | set_gdbarch_num_regs (gdbarch, num_regs); | |
5814 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
5815 | } | |
fe29b929 | 5816 | |
0dadbba0 | 5817 | switch (mips_abi) |
c2d11a7d | 5818 | { |
0dadbba0 | 5819 | case MIPS_ABI_O32: |
25ab4790 | 5820 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 5821 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
a5ea2558 | 5822 | tdep->mips_default_saved_regsize = 4; |
0dadbba0 | 5823 | tdep->mips_default_stack_argsize = 4; |
c2d11a7d | 5824 | tdep->mips_fp_register_double = 0; |
acdb74a0 | 5825 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
56cea623 | 5826 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 5827 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5828 | set_gdbarch_long_bit (gdbarch, 32); |
5829 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5830 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
5831 | set_gdbarch_deprecated_reg_struct_has_addr |
5832 | (gdbarch, mips_o32_reg_struct_has_addr); | |
c2d11a7d | 5833 | break; |
0dadbba0 | 5834 | case MIPS_ABI_O64: |
25ab4790 | 5835 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
ebba8386 | 5836 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_o64_store_return_value); |
46cac009 | 5837 | set_gdbarch_deprecated_extract_return_value (gdbarch, mips_o64_extract_return_value); |
a5ea2558 | 5838 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 | 5839 | tdep->mips_default_stack_argsize = 8; |
c2d11a7d | 5840 | tdep->mips_fp_register_double = 1; |
acdb74a0 | 5841 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
56cea623 | 5842 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 5843 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5844 | set_gdbarch_long_bit (gdbarch, 32); |
5845 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5846 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
5847 | set_gdbarch_deprecated_reg_struct_has_addr |
5848 | (gdbarch, mips_o32_reg_struct_has_addr); | |
b060cbea | 5849 | set_gdbarch_use_struct_convention (gdbarch, always_use_struct_convention); |
c2d11a7d | 5850 | break; |
0dadbba0 | 5851 | case MIPS_ABI_EABI32: |
25ab4790 | 5852 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
ebba8386 | 5853 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_eabi_store_return_value); |
46cac009 | 5854 | set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value); |
a5ea2558 | 5855 | tdep->mips_default_saved_regsize = 4; |
0dadbba0 | 5856 | tdep->mips_default_stack_argsize = 4; |
c2d11a7d | 5857 | tdep->mips_fp_register_double = 0; |
acdb74a0 | 5858 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 5859 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5860 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5861 | set_gdbarch_long_bit (gdbarch, 32); |
5862 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5863 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
5864 | set_gdbarch_deprecated_reg_struct_has_addr |
5865 | (gdbarch, mips_eabi_reg_struct_has_addr); | |
cb811fe7 MS |
5866 | set_gdbarch_use_struct_convention (gdbarch, |
5867 | mips_eabi_use_struct_convention); | |
c2d11a7d | 5868 | break; |
0dadbba0 | 5869 | case MIPS_ABI_EABI64: |
25ab4790 | 5870 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
ebba8386 | 5871 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_eabi_store_return_value); |
46cac009 | 5872 | set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value); |
a5ea2558 | 5873 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 | 5874 | tdep->mips_default_stack_argsize = 8; |
c2d11a7d | 5875 | tdep->mips_fp_register_double = 1; |
acdb74a0 | 5876 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 5877 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5878 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5879 | set_gdbarch_long_bit (gdbarch, 64); |
5880 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5881 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
5882 | set_gdbarch_deprecated_reg_struct_has_addr |
5883 | (gdbarch, mips_eabi_reg_struct_has_addr); | |
cb811fe7 MS |
5884 | set_gdbarch_use_struct_convention (gdbarch, |
5885 | mips_eabi_use_struct_convention); | |
c2d11a7d | 5886 | break; |
0dadbba0 | 5887 | case MIPS_ABI_N32: |
25ab4790 | 5888 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5889 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
63db5580 | 5890 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 AC |
5891 | tdep->mips_default_stack_argsize = 8; |
5892 | tdep->mips_fp_register_double = 1; | |
acdb74a0 | 5893 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 5894 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5895 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
5896 | set_gdbarch_long_bit (gdbarch, 32); |
5897 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5898 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
5899 | set_gdbarch_deprecated_reg_struct_has_addr |
5900 | (gdbarch, mips_n32n64_reg_struct_has_addr); | |
28d169de KB |
5901 | break; |
5902 | case MIPS_ABI_N64: | |
25ab4790 | 5903 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5904 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
28d169de KB |
5905 | tdep->mips_default_saved_regsize = 8; |
5906 | tdep->mips_default_stack_argsize = 8; | |
5907 | tdep->mips_fp_register_double = 1; | |
5908 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; | |
56cea623 | 5909 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
5910 | tdep->default_mask_address_p = 0; |
5911 | set_gdbarch_long_bit (gdbarch, 64); | |
5912 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5913 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
5914 | set_gdbarch_deprecated_reg_struct_has_addr |
5915 | (gdbarch, mips_n32n64_reg_struct_has_addr); | |
0dadbba0 | 5916 | break; |
c2d11a7d | 5917 | default: |
2e4ebe70 DJ |
5918 | internal_error (__FILE__, __LINE__, |
5919 | "unknown ABI in switch"); | |
c2d11a7d JM |
5920 | } |
5921 | ||
a5ea2558 AC |
5922 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
5923 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
5924 | comment: | |
5925 | ||
5926 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
5927 | flag in object files because to do so would make it impossible to | |
102182a9 | 5928 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 5929 | unnecessarily restrictive. |
361d1df0 | 5930 | |
a5ea2558 AC |
5931 | We could solve this problem by adding "-gp32" multilibs to gcc, |
5932 | but to set this flag before gcc is built with such multilibs will | |
5933 | break too many systems.'' | |
5934 | ||
5935 | But even more unhelpfully, the default linker output target for | |
5936 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
5937 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 5938 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
5939 | this flag to detect 32-bit mode would do the wrong thing given |
5940 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 5941 | as 32-bit programs by default. */ |
a5ea2558 | 5942 | |
c2d11a7d JM |
5943 | /* enable/disable the MIPS FPU */ |
5944 | if (!mips_fpu_type_auto) | |
5945 | tdep->mips_fpu_type = mips_fpu_type; | |
5946 | else if (info.bfd_arch_info != NULL | |
5947 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5948 | switch (info.bfd_arch_info->mach) | |
5949 | { | |
b0069a17 | 5950 | case bfd_mach_mips3900: |
c2d11a7d | 5951 | case bfd_mach_mips4100: |
ed9a39eb | 5952 | case bfd_mach_mips4111: |
c2d11a7d JM |
5953 | tdep->mips_fpu_type = MIPS_FPU_NONE; |
5954 | break; | |
bf64bfd6 AC |
5955 | case bfd_mach_mips4650: |
5956 | tdep->mips_fpu_type = MIPS_FPU_SINGLE; | |
5957 | break; | |
c2d11a7d JM |
5958 | default: |
5959 | tdep->mips_fpu_type = MIPS_FPU_DOUBLE; | |
5960 | break; | |
5961 | } | |
5962 | else | |
5963 | tdep->mips_fpu_type = MIPS_FPU_DOUBLE; | |
5964 | ||
691c0433 | 5965 | /* MIPS version of register names. */ |
c2d11a7d | 5966 | set_gdbarch_register_name (gdbarch, mips_register_name); |
691c0433 AC |
5967 | if (info.osabi == GDB_OSABI_IRIX) |
5968 | tdep->mips_processor_reg_names = mips_irix_reg_names; | |
5969 | else if (info.bfd_arch_info != NULL && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
5970 | tdep->mips_processor_reg_names = mips_tx39_reg_names; | |
5971 | else | |
5972 | tdep->mips_processor_reg_names = mips_generic_reg_names; | |
6c997a34 | 5973 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
c2d11a7d | 5974 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); |
0ba6dca9 | 5975 | set_gdbarch_deprecated_target_read_fp (gdbarch, mips_read_sp); /* Draft FRAME base. */ |
bcb0cc15 | 5976 | set_gdbarch_read_sp (gdbarch, mips_read_sp); |
c2d11a7d | 5977 | |
102182a9 MS |
5978 | /* Add/remove bits from an address. The MIPS needs be careful to |
5979 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
5980 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
5981 | ||
10312cc4 | 5982 | /* There's a mess in stack frame creation. See comments in |
2ca6c561 AC |
5983 | blockframe.c near reference to DEPRECATED_INIT_FRAME_PC_FIRST. */ |
5984 | set_gdbarch_deprecated_init_frame_pc_first (gdbarch, mips_init_frame_pc_first); | |
10312cc4 | 5985 | |
102182a9 | 5986 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 5987 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
2f38ef89 KB |
5988 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum); |
5989 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
5990 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 5991 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 5992 | |
c2d11a7d | 5993 | /* Initialize a frame */ |
e0f7ec59 | 5994 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, mips_find_saved_regs); |
e9582e71 | 5995 | set_gdbarch_deprecated_init_extra_frame_info (gdbarch, mips_init_extra_frame_info); |
c2d11a7d JM |
5996 | |
5997 | /* MIPS version of CALL_DUMMY */ | |
5998 | ||
9710e734 AC |
5999 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
6000 | replaced by a command, and all targets will default to on stack | |
6001 | (regardless of the stack's execute status). */ | |
6002 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
749b82f6 | 6003 | set_gdbarch_deprecated_pop_frame (gdbarch, mips_pop_frame); |
dc604539 | 6004 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
a59fe496 | 6005 | set_gdbarch_deprecated_save_dummy_frame_tos (gdbarch, generic_save_dummy_frame_tos); |
d05285fa | 6006 | |
618ce49f | 6007 | set_gdbarch_deprecated_frame_chain (gdbarch, mips_frame_chain); |
b5d1566e MS |
6008 | set_gdbarch_frameless_function_invocation (gdbarch, |
6009 | generic_frameless_function_invocation_not); | |
8bedc050 | 6010 | set_gdbarch_deprecated_frame_saved_pc (gdbarch, mips_frame_saved_pc); |
b5d1566e MS |
6011 | set_gdbarch_frame_args_skip (gdbarch, 0); |
6012 | ||
129c1cd6 | 6013 | set_gdbarch_deprecated_get_saved_register (gdbarch, mips_get_saved_register); |
c2d11a7d | 6014 | |
f7b9e9fc AC |
6015 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
6016 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
6017 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
f7b9e9fc AC |
6018 | |
6019 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
6913c89a | 6020 | set_gdbarch_deprecated_saved_pc_after_call (gdbarch, mips_saved_pc_after_call); |
f7b9e9fc | 6021 | |
fc0c74b1 AC |
6022 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
6023 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
6024 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 6025 | |
102182a9 MS |
6026 | set_gdbarch_function_start_offset (gdbarch, 0); |
6027 | ||
a4b8ebc8 | 6028 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 6029 | |
e11c53d2 | 6030 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
102182a9 | 6031 | set_gdbarch_pc_in_sigtramp (gdbarch, mips_pc_in_sigtramp); |
bf1f5b4c | 6032 | |
e5ab0dce AC |
6033 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); |
6034 | ||
3a3bc038 AC |
6035 | /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT, |
6036 | HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT | |
6037 | need to all be folded into the target vector. Since they are | |
6038 | being used as guards for STOPPED_BY_WATCHPOINT, why not have | |
6039 | STOPPED_BY_WATCHPOINT return the type of watchpoint that the code | |
6040 | is sitting on? */ | |
6041 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
6042 | ||
70f80edf | 6043 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
4be87837 | 6044 | gdbarch_init_osabi (info, gdbarch); |
70f80edf | 6045 | |
2f1488ce MS |
6046 | set_gdbarch_extract_struct_value_address (gdbarch, |
6047 | mips_extract_struct_value_address); | |
757a7cc6 MS |
6048 | |
6049 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_stub); | |
6050 | ||
6051 | set_gdbarch_in_solib_call_trampoline (gdbarch, mips_in_call_stub); | |
e41b17f0 | 6052 | set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); |
757a7cc6 | 6053 | |
4b9b3959 AC |
6054 | return gdbarch; |
6055 | } | |
6056 | ||
2e4ebe70 DJ |
6057 | static void |
6058 | mips_abi_update (char *ignore_args, int from_tty, | |
6059 | struct cmd_list_element *c) | |
6060 | { | |
6061 | struct gdbarch_info info; | |
6062 | ||
6063 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
6064 | mips_gdbarch_init will take care of the rest. */ | |
6065 | gdbarch_info_init (&info); | |
6066 | gdbarch_update_p (info); | |
6067 | } | |
6068 | ||
ad188201 KB |
6069 | /* Print out which MIPS ABI is in use. */ |
6070 | ||
6071 | static void | |
6072 | show_mips_abi (char *ignore_args, int from_tty) | |
6073 | { | |
6074 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips) | |
6075 | printf_filtered ( | |
6076 | "The MIPS ABI is unknown because the current architecture is not MIPS.\n"); | |
6077 | else | |
6078 | { | |
6079 | enum mips_abi global_abi = global_mips_abi (); | |
6080 | enum mips_abi actual_abi = mips_abi (current_gdbarch); | |
6081 | const char *actual_abi_str = mips_abi_strings[actual_abi]; | |
6082 | ||
6083 | if (global_abi == MIPS_ABI_UNKNOWN) | |
6084 | printf_filtered ("The MIPS ABI is set automatically (currently \"%s\").\n", | |
6085 | actual_abi_str); | |
6086 | else if (global_abi == actual_abi) | |
6087 | printf_filtered ( | |
6088 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6089 | actual_abi_str); | |
6090 | else | |
6091 | { | |
6092 | /* Probably shouldn't happen... */ | |
6093 | printf_filtered ( | |
6094 | "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n", | |
6095 | actual_abi_str, | |
6096 | mips_abi_strings[global_abi]); | |
6097 | } | |
6098 | } | |
6099 | } | |
6100 | ||
4b9b3959 AC |
6101 | static void |
6102 | mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
6103 | { | |
6104 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
6105 | if (tdep != NULL) | |
c2d11a7d | 6106 | { |
acdb74a0 AC |
6107 | int ef_mips_arch; |
6108 | int ef_mips_32bitmode; | |
6109 | /* determine the ISA */ | |
6110 | switch (tdep->elf_flags & EF_MIPS_ARCH) | |
6111 | { | |
6112 | case E_MIPS_ARCH_1: | |
6113 | ef_mips_arch = 1; | |
6114 | break; | |
6115 | case E_MIPS_ARCH_2: | |
6116 | ef_mips_arch = 2; | |
6117 | break; | |
6118 | case E_MIPS_ARCH_3: | |
6119 | ef_mips_arch = 3; | |
6120 | break; | |
6121 | case E_MIPS_ARCH_4: | |
93d56215 | 6122 | ef_mips_arch = 4; |
acdb74a0 AC |
6123 | break; |
6124 | default: | |
93d56215 | 6125 | ef_mips_arch = 0; |
acdb74a0 AC |
6126 | break; |
6127 | } | |
6128 | /* determine the size of a pointer */ | |
6129 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); | |
4b9b3959 AC |
6130 | fprintf_unfiltered (file, |
6131 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 6132 | tdep->elf_flags); |
4b9b3959 | 6133 | fprintf_unfiltered (file, |
acdb74a0 AC |
6134 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
6135 | ef_mips_32bitmode); | |
6136 | fprintf_unfiltered (file, | |
6137 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
6138 | ef_mips_arch); | |
6139 | fprintf_unfiltered (file, | |
6140 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6141 | tdep->mips_abi, | |
2e4ebe70 | 6142 | mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
6143 | fprintf_unfiltered (file, |
6144 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
6145 | mips_mask_address_p (), | |
6146 | tdep->default_mask_address_p); | |
c2d11a7d | 6147 | } |
4b9b3959 AC |
6148 | fprintf_unfiltered (file, |
6149 | "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n", | |
6150 | FP_REGISTER_DOUBLE); | |
6151 | fprintf_unfiltered (file, | |
6152 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
6153 | MIPS_DEFAULT_FPU_TYPE, | |
6154 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6155 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6156 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6157 | : "???")); | |
6158 | fprintf_unfiltered (file, | |
6159 | "mips_dump_tdep: MIPS_EABI = %d\n", | |
6160 | MIPS_EABI); | |
4b9b3959 AC |
6161 | fprintf_unfiltered (file, |
6162 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
6163 | MIPS_FPU_TYPE, | |
6164 | (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6165 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6166 | : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6167 | : "???")); | |
6168 | fprintf_unfiltered (file, | |
6169 | "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n", | |
6170 | MIPS_DEFAULT_SAVED_REGSIZE); | |
4b9b3959 AC |
6171 | fprintf_unfiltered (file, |
6172 | "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n", | |
6173 | FP_REGISTER_DOUBLE); | |
4b9b3959 AC |
6174 | fprintf_unfiltered (file, |
6175 | "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n", | |
6176 | MIPS_DEFAULT_STACK_ARGSIZE); | |
6177 | fprintf_unfiltered (file, | |
6178 | "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n", | |
6179 | MIPS_STACK_ARGSIZE); | |
2475bac3 AC |
6180 | fprintf_unfiltered (file, |
6181 | "mips_dump_tdep: A0_REGNUM = %d\n", | |
6182 | A0_REGNUM); | |
6183 | fprintf_unfiltered (file, | |
6184 | "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n", | |
6185 | XSTRING (ADDR_BITS_REMOVE(ADDR))); | |
6186 | fprintf_unfiltered (file, | |
6187 | "mips_dump_tdep: ATTACH_DETACH # %s\n", | |
6188 | XSTRING (ATTACH_DETACH)); | |
2475bac3 AC |
6189 | fprintf_unfiltered (file, |
6190 | "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n", | |
6191 | XSTRING (DWARF_REG_TO_REGNUM (REGNUM))); | |
6192 | fprintf_unfiltered (file, | |
6193 | "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n", | |
6194 | XSTRING (ECOFF_REG_TO_REGNUM (REGNUM))); | |
2475bac3 AC |
6195 | fprintf_unfiltered (file, |
6196 | "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n", | |
6197 | FIRST_EMBED_REGNUM); | |
2475bac3 AC |
6198 | fprintf_unfiltered (file, |
6199 | "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n", | |
6200 | XSTRING (IGNORE_HELPER_CALL (PC))); | |
2475bac3 AC |
6201 | fprintf_unfiltered (file, |
6202 | "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n", | |
6203 | XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME))); | |
6204 | fprintf_unfiltered (file, | |
6205 | "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n", | |
6206 | XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME))); | |
2475bac3 AC |
6207 | fprintf_unfiltered (file, |
6208 | "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n", | |
6209 | LAST_EMBED_REGNUM); | |
2475bac3 AC |
6210 | #ifdef MACHINE_CPROC_FP_OFFSET |
6211 | fprintf_unfiltered (file, | |
6212 | "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n", | |
6213 | MACHINE_CPROC_FP_OFFSET); | |
6214 | #endif | |
6215 | #ifdef MACHINE_CPROC_PC_OFFSET | |
6216 | fprintf_unfiltered (file, | |
6217 | "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n", | |
6218 | MACHINE_CPROC_PC_OFFSET); | |
6219 | #endif | |
6220 | #ifdef MACHINE_CPROC_SP_OFFSET | |
6221 | fprintf_unfiltered (file, | |
6222 | "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n", | |
6223 | MACHINE_CPROC_SP_OFFSET); | |
6224 | #endif | |
2475bac3 AC |
6225 | fprintf_unfiltered (file, |
6226 | "mips_dump_tdep: MIPS16_INSTLEN = %d\n", | |
6227 | MIPS16_INSTLEN); | |
2475bac3 AC |
6228 | fprintf_unfiltered (file, |
6229 | "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n"); | |
6230 | fprintf_unfiltered (file, | |
6231 | "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n"); | |
6232 | fprintf_unfiltered (file, | |
6233 | "mips_dump_tdep: MIPS_INSTLEN = %d\n", | |
6234 | MIPS_INSTLEN); | |
6235 | fprintf_unfiltered (file, | |
acdb74a0 AC |
6236 | "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n", |
6237 | MIPS_LAST_ARG_REGNUM, | |
6238 | MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1); | |
2475bac3 AC |
6239 | fprintf_unfiltered (file, |
6240 | "mips_dump_tdep: MIPS_NUMREGS = %d\n", | |
6241 | MIPS_NUMREGS); | |
2475bac3 AC |
6242 | fprintf_unfiltered (file, |
6243 | "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n", | |
6244 | MIPS_SAVED_REGSIZE); | |
2475bac3 AC |
6245 | fprintf_unfiltered (file, |
6246 | "mips_dump_tdep: PRID_REGNUM = %d\n", | |
6247 | PRID_REGNUM); | |
2475bac3 AC |
6248 | fprintf_unfiltered (file, |
6249 | "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n"); | |
6250 | fprintf_unfiltered (file, | |
6251 | "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n"); | |
6252 | fprintf_unfiltered (file, | |
6253 | "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n"); | |
6254 | fprintf_unfiltered (file, | |
6255 | "mips_dump_tdep: PROC_FRAME_REG = function?\n"); | |
6256 | fprintf_unfiltered (file, | |
6257 | "mips_dump_tdep: PROC_FREG_MASK = function?\n"); | |
6258 | fprintf_unfiltered (file, | |
6259 | "mips_dump_tdep: PROC_FREG_OFFSET = function?\n"); | |
6260 | fprintf_unfiltered (file, | |
6261 | "mips_dump_tdep: PROC_HIGH_ADDR = function?\n"); | |
6262 | fprintf_unfiltered (file, | |
6263 | "mips_dump_tdep: PROC_LOW_ADDR = function?\n"); | |
6264 | fprintf_unfiltered (file, | |
6265 | "mips_dump_tdep: PROC_PC_REG = function?\n"); | |
6266 | fprintf_unfiltered (file, | |
6267 | "mips_dump_tdep: PROC_REG_MASK = function?\n"); | |
6268 | fprintf_unfiltered (file, | |
6269 | "mips_dump_tdep: PROC_REG_OFFSET = function?\n"); | |
6270 | fprintf_unfiltered (file, | |
6271 | "mips_dump_tdep: PROC_SYMBOL = function?\n"); | |
6272 | fprintf_unfiltered (file, | |
6273 | "mips_dump_tdep: PS_REGNUM = %d\n", | |
6274 | PS_REGNUM); | |
2475bac3 AC |
6275 | fprintf_unfiltered (file, |
6276 | "mips_dump_tdep: RA_REGNUM = %d\n", | |
6277 | RA_REGNUM); | |
2475bac3 AC |
6278 | #ifdef SAVED_BYTES |
6279 | fprintf_unfiltered (file, | |
6280 | "mips_dump_tdep: SAVED_BYTES = %d\n", | |
6281 | SAVED_BYTES); | |
6282 | #endif | |
6283 | #ifdef SAVED_FP | |
6284 | fprintf_unfiltered (file, | |
6285 | "mips_dump_tdep: SAVED_FP = %d\n", | |
6286 | SAVED_FP); | |
6287 | #endif | |
6288 | #ifdef SAVED_PC | |
6289 | fprintf_unfiltered (file, | |
6290 | "mips_dump_tdep: SAVED_PC = %d\n", | |
6291 | SAVED_PC); | |
6292 | #endif | |
6293 | fprintf_unfiltered (file, | |
6294 | "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n", | |
6295 | XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS))); | |
6296 | fprintf_unfiltered (file, | |
6297 | "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n"); | |
6298 | fprintf_unfiltered (file, | |
6299 | "mips_dump_tdep: SIGFRAME_BASE = %d\n", | |
6300 | SIGFRAME_BASE); | |
6301 | fprintf_unfiltered (file, | |
6302 | "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n", | |
6303 | SIGFRAME_FPREGSAVE_OFF); | |
6304 | fprintf_unfiltered (file, | |
6305 | "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n", | |
6306 | SIGFRAME_PC_OFF); | |
6307 | fprintf_unfiltered (file, | |
6308 | "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n", | |
6309 | SIGFRAME_REGSAVE_OFF); | |
2475bac3 AC |
6310 | fprintf_unfiltered (file, |
6311 | "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n", | |
6312 | XSTRING (SKIP_TRAMPOLINE_CODE (PC))); | |
6313 | fprintf_unfiltered (file, | |
6314 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n", | |
6315 | XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P))); | |
6316 | fprintf_unfiltered (file, | |
b0ed3589 AC |
6317 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n", |
6318 | SOFTWARE_SINGLE_STEP_P ()); | |
2475bac3 AC |
6319 | fprintf_unfiltered (file, |
6320 | "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n", | |
6321 | XSTRING (STAB_REG_TO_REGNUM (REGNUM))); | |
6322 | #ifdef STACK_END_ADDR | |
6323 | fprintf_unfiltered (file, | |
6324 | "mips_dump_tdep: STACK_END_ADDR = %d\n", | |
6325 | STACK_END_ADDR); | |
6326 | #endif | |
6327 | fprintf_unfiltered (file, | |
6328 | "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n", | |
6329 | XSTRING (STEP_SKIPS_DELAY (PC))); | |
6330 | fprintf_unfiltered (file, | |
6331 | "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n", | |
6332 | STEP_SKIPS_DELAY_P); | |
6333 | fprintf_unfiltered (file, | |
6334 | "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n", | |
6335 | XSTRING (STOPPED_BY_WATCHPOINT (WS))); | |
6336 | fprintf_unfiltered (file, | |
6337 | "mips_dump_tdep: T9_REGNUM = %d\n", | |
6338 | T9_REGNUM); | |
6339 | fprintf_unfiltered (file, | |
6340 | "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n"); | |
6341 | fprintf_unfiltered (file, | |
6342 | "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n", | |
6343 | XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE,CNT,OTHERTYPE))); | |
6344 | fprintf_unfiltered (file, | |
6345 | "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n", | |
6346 | XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS)); | |
2475bac3 AC |
6347 | #ifdef TRACE_CLEAR |
6348 | fprintf_unfiltered (file, | |
6349 | "mips_dump_tdep: TRACE_CLEAR # %s\n", | |
6350 | XSTRING (TRACE_CLEAR (THREAD, STATE))); | |
6351 | #endif | |
6352 | #ifdef TRACE_FLAVOR | |
6353 | fprintf_unfiltered (file, | |
6354 | "mips_dump_tdep: TRACE_FLAVOR = %d\n", | |
6355 | TRACE_FLAVOR); | |
6356 | #endif | |
6357 | #ifdef TRACE_FLAVOR_SIZE | |
6358 | fprintf_unfiltered (file, | |
6359 | "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n", | |
6360 | TRACE_FLAVOR_SIZE); | |
6361 | #endif | |
6362 | #ifdef TRACE_SET | |
6363 | fprintf_unfiltered (file, | |
6364 | "mips_dump_tdep: TRACE_SET # %s\n", | |
6365 | XSTRING (TRACE_SET (X,STATE))); | |
6366 | #endif | |
2475bac3 AC |
6367 | #ifdef UNUSED_REGNUM |
6368 | fprintf_unfiltered (file, | |
6369 | "mips_dump_tdep: UNUSED_REGNUM = %d\n", | |
6370 | UNUSED_REGNUM); | |
6371 | #endif | |
6372 | fprintf_unfiltered (file, | |
6373 | "mips_dump_tdep: V0_REGNUM = %d\n", | |
6374 | V0_REGNUM); | |
6375 | fprintf_unfiltered (file, | |
6376 | "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n", | |
6377 | (long) VM_MIN_ADDRESS); | |
2475bac3 AC |
6378 | fprintf_unfiltered (file, |
6379 | "mips_dump_tdep: ZERO_REGNUM = %d\n", | |
6380 | ZERO_REGNUM); | |
6381 | fprintf_unfiltered (file, | |
6382 | "mips_dump_tdep: _PROC_MAGIC_ = %d\n", | |
6383 | _PROC_MAGIC_); | |
c2d11a7d JM |
6384 | } |
6385 | ||
a78f21af AC |
6386 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
6387 | ||
c906108c | 6388 | void |
acdb74a0 | 6389 | _initialize_mips_tdep (void) |
c906108c SS |
6390 | { |
6391 | static struct cmd_list_element *mipsfpulist = NULL; | |
6392 | struct cmd_list_element *c; | |
6393 | ||
2e4ebe70 DJ |
6394 | mips_abi_string = mips_abi_strings [MIPS_ABI_UNKNOWN]; |
6395 | if (MIPS_ABI_LAST + 1 | |
6396 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
6397 | internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync"); | |
6398 | ||
4b9b3959 | 6399 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 6400 | |
a5ea2558 AC |
6401 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
6402 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
6403 | "Various MIPS specific commands.", | |
6404 | &setmipscmdlist, "set mips ", 0, &setlist); | |
6405 | ||
6406 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
6407 | "Various MIPS specific commands.", | |
6408 | &showmipscmdlist, "show mips ", 0, &showlist); | |
6409 | ||
6410 | /* Allow the user to override the saved register size. */ | |
6411 | add_show_from_set (add_set_enum_cmd ("saved-gpreg-size", | |
1ed2a135 AC |
6412 | class_obscure, |
6413 | size_enums, | |
6414 | &mips_saved_regsize_string, "\ | |
a5ea2558 AC |
6415 | Set size of general purpose registers saved on the stack.\n\ |
6416 | This option can be set to one of:\n\ | |
6417 | 32 - Force GDB to treat saved GP registers as 32-bit\n\ | |
6418 | 64 - Force GDB to treat saved GP registers as 64-bit\n\ | |
6419 | auto - Allow GDB to use the target's default setting or autodetect the\n\ | |
6420 | saved GP register size from information contained in the executable.\n\ | |
6421 | (default: auto)", | |
1ed2a135 | 6422 | &setmipscmdlist), |
a5ea2558 AC |
6423 | &showmipscmdlist); |
6424 | ||
d929b26f AC |
6425 | /* Allow the user to override the argument stack size. */ |
6426 | add_show_from_set (add_set_enum_cmd ("stack-arg-size", | |
6427 | class_obscure, | |
6428 | size_enums, | |
1ed2a135 | 6429 | &mips_stack_argsize_string, "\ |
d929b26f AC |
6430 | Set the amount of stack space reserved for each argument.\n\ |
6431 | This option can be set to one of:\n\ | |
6432 | 32 - Force GDB to allocate 32-bit chunks per argument\n\ | |
6433 | 64 - Force GDB to allocate 64-bit chunks per argument\n\ | |
6434 | auto - Allow GDB to determine the correct setting from the current\n\ | |
6435 | target and executable (default)", | |
6436 | &setmipscmdlist), | |
6437 | &showmipscmdlist); | |
6438 | ||
2e4ebe70 DJ |
6439 | /* Allow the user to override the ABI. */ |
6440 | c = add_set_enum_cmd | |
6441 | ("abi", class_obscure, mips_abi_strings, &mips_abi_string, | |
6442 | "Set the ABI used by this program.\n" | |
6443 | "This option can be set to one of:\n" | |
6444 | " auto - the default ABI associated with the current binary\n" | |
6445 | " o32\n" | |
6446 | " o64\n" | |
6447 | " n32\n" | |
f3a7b3a5 | 6448 | " n64\n" |
2e4ebe70 DJ |
6449 | " eabi32\n" |
6450 | " eabi64", | |
6451 | &setmipscmdlist); | |
2e4ebe70 | 6452 | set_cmd_sfunc (c, mips_abi_update); |
ad188201 KB |
6453 | add_cmd ("abi", class_obscure, show_mips_abi, |
6454 | "Show ABI in use by MIPS target", &showmipscmdlist); | |
2e4ebe70 | 6455 | |
c906108c SS |
6456 | /* Let the user turn off floating point and set the fence post for |
6457 | heuristic_proc_start. */ | |
6458 | ||
6459 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
6460 | "Set use of MIPS floating-point coprocessor.", | |
6461 | &mipsfpulist, "set mipsfpu ", 0, &setlist); | |
6462 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
6463 | "Select single-precision MIPS floating-point coprocessor.", | |
6464 | &mipsfpulist); | |
6465 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
8e1a459b | 6466 | "Select double-precision MIPS floating-point coprocessor.", |
c906108c SS |
6467 | &mipsfpulist); |
6468 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
6469 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
6470 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
6471 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
6472 | "Select no MIPS floating-point coprocessor.", | |
6473 | &mipsfpulist); | |
6474 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); | |
6475 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
6476 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
6477 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
6478 | "Select MIPS floating-point coprocessor automatically.", | |
6479 | &mipsfpulist); | |
6480 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
6481 | "Show current use of MIPS floating-point coprocessor target.", | |
6482 | &showlist); | |
6483 | ||
c906108c SS |
6484 | /* We really would like to have both "0" and "unlimited" work, but |
6485 | command.c doesn't deal with that. So make it a var_zinteger | |
6486 | because the user can always use "999999" or some such for unlimited. */ | |
6487 | c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger, | |
6488 | (char *) &heuristic_fence_post, | |
6489 | "\ | |
6490 | Set the distance searched for the start of a function.\n\ | |
6491 | If you are debugging a stripped executable, GDB needs to search through the\n\ | |
6492 | program for the start of a function. This command sets the distance of the\n\ | |
6493 | search. The only need to set it is when debugging a stripped executable.", | |
6494 | &setlist); | |
6495 | /* We need to throw away the frame cache when we set this, since it | |
6496 | might change our ability to get backtraces. */ | |
9f60d481 | 6497 | set_cmd_sfunc (c, reinit_frame_cache_sfunc); |
c906108c SS |
6498 | add_show_from_set (c, &showlist); |
6499 | ||
6500 | /* Allow the user to control whether the upper bits of 64-bit | |
6501 | addresses should be zeroed. */ | |
e9e68a56 AC |
6502 | add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, "\ |
6503 | Set zeroing of upper 32 bits of 64-bit addresses.\n\ | |
6504 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ | |
6505 | allow GDB to determine the correct value.\n", "\ | |
6506 | Show zeroing of upper 32 bits of 64-bit addresses.", | |
6507 | NULL, show_mask_address, | |
6508 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
6509 | |
6510 | /* Allow the user to control the size of 32 bit registers within the | |
6511 | raw remote packet. */ | |
719ec221 AC |
6512 | add_setshow_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
6513 | var_boolean, &mips64_transfers_32bit_regs_p, "\ | |
6514 | Set compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\ | |
6515 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ | |
6516 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
6517 | 64 bits for others. Use \"off\" to disable compatibility mode", "\ | |
6518 | Show compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\ | |
43e526b9 JM |
6519 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
6520 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
6521 | 64 bits for others. Use \"off\" to disable compatibility mode", | |
719ec221 AC |
6522 | set_mips64_transfers_32bit_regs, NULL, |
6523 | &setlist, &showlist); | |
9ace0497 AC |
6524 | |
6525 | /* Debug this files internals. */ | |
6526 | add_show_from_set (add_set_cmd ("mips", class_maintenance, var_zinteger, | |
6527 | &mips_debug, "Set mips debugging.\n\ | |
6528 | When non-zero, mips specific debugging is enabled.", &setdebuglist), | |
6529 | &showdebuglist); | |
c906108c | 6530 | } |