Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
cda5a58a | 3 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, |
47a35522 MK |
4 | 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 |
5 | Free Software Foundation, Inc. | |
bf64bfd6 | 6 | |
c906108c SS |
7 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
8 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
9 | ||
c5aa993b | 10 | This file is part of GDB. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is free software; you can redistribute it and/or modify |
13 | it under the terms of the GNU General Public License as published by | |
14 | the Free Software Foundation; either version 2 of the License, or | |
15 | (at your option) any later version. | |
c906108c | 16 | |
c5aa993b JM |
17 | This program is distributed in the hope that it will be useful, |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
c906108c | 21 | |
c5aa993b JM |
22 | You should have received a copy of the GNU General Public License |
23 | along with this program; if not, write to the Free Software | |
24 | Foundation, Inc., 59 Temple Place - Suite 330, | |
25 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
26 | |
27 | #include "defs.h" | |
28 | #include "gdb_string.h" | |
5e2e9765 | 29 | #include "gdb_assert.h" |
c906108c SS |
30 | #include "frame.h" |
31 | #include "inferior.h" | |
32 | #include "symtab.h" | |
33 | #include "value.h" | |
34 | #include "gdbcmd.h" | |
35 | #include "language.h" | |
36 | #include "gdbcore.h" | |
37 | #include "symfile.h" | |
38 | #include "objfiles.h" | |
39 | #include "gdbtypes.h" | |
40 | #include "target.h" | |
28d069e6 | 41 | #include "arch-utils.h" |
4e052eda | 42 | #include "regcache.h" |
70f80edf | 43 | #include "osabi.h" |
d1973055 | 44 | #include "mips-tdep.h" |
fe898f56 | 45 | #include "block.h" |
a4b8ebc8 | 46 | #include "reggroups.h" |
c906108c | 47 | #include "opcode/mips.h" |
c2d11a7d JM |
48 | #include "elf/mips.h" |
49 | #include "elf-bfd.h" | |
2475bac3 | 50 | #include "symcat.h" |
a4b8ebc8 | 51 | #include "sim-regno.h" |
a89aa300 | 52 | #include "dis-asm.h" |
edfae063 AC |
53 | #include "frame-unwind.h" |
54 | #include "frame-base.h" | |
55 | #include "trad-frame.h" | |
7d9b040b | 56 | #include "infcall.h" |
fed7ba43 | 57 | #include "floatformat.h" |
c906108c | 58 | |
8d5f9dcb DJ |
59 | static const struct objfile_data *mips_pdr_data; |
60 | ||
5bbcb741 | 61 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 62 | |
24e05951 | 63 | /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ |
dd824b04 DJ |
64 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ |
65 | #define ST0_FR (1 << 26) | |
66 | ||
b0069a17 AC |
67 | /* The sizes of floating point registers. */ |
68 | ||
69 | enum | |
70 | { | |
71 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
72 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
73 | }; | |
74 | ||
0dadbba0 | 75 | |
2e4ebe70 DJ |
76 | static const char *mips_abi_string; |
77 | ||
78 | static const char *mips_abi_strings[] = { | |
79 | "auto", | |
80 | "n32", | |
81 | "o32", | |
28d169de | 82 | "n64", |
2e4ebe70 DJ |
83 | "o64", |
84 | "eabi32", | |
85 | "eabi64", | |
86 | NULL | |
87 | }; | |
88 | ||
d929b26f AC |
89 | /* Various MIPS ISA options (related to stack analysis) can be |
90 | overridden dynamically. Establish an enum/array for managing | |
91 | them. */ | |
92 | ||
53904c9e AC |
93 | static const char size_auto[] = "auto"; |
94 | static const char size_32[] = "32"; | |
95 | static const char size_64[] = "64"; | |
d929b26f | 96 | |
53904c9e | 97 | static const char *size_enums[] = { |
d929b26f AC |
98 | size_auto, |
99 | size_32, | |
100 | size_64, | |
a5ea2558 AC |
101 | 0 |
102 | }; | |
103 | ||
7a292a7a | 104 | /* Some MIPS boards don't support floating point while others only |
ceae6e75 | 105 | support single-precision floating-point operations. */ |
c906108c SS |
106 | |
107 | enum mips_fpu_type | |
6d82d43b AC |
108 | { |
109 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
110 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
111 | MIPS_FPU_NONE /* No floating point. */ | |
112 | }; | |
c906108c SS |
113 | |
114 | #ifndef MIPS_DEFAULT_FPU_TYPE | |
115 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
116 | #endif | |
117 | static int mips_fpu_type_auto = 1; | |
118 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 119 | |
9ace0497 | 120 | static int mips_debug = 0; |
7a292a7a | 121 | |
c2d11a7d JM |
122 | /* MIPS specific per-architecture information */ |
123 | struct gdbarch_tdep | |
6d82d43b AC |
124 | { |
125 | /* from the elf header */ | |
126 | int elf_flags; | |
127 | ||
128 | /* mips options */ | |
129 | enum mips_abi mips_abi; | |
130 | enum mips_abi found_abi; | |
131 | enum mips_fpu_type mips_fpu_type; | |
132 | int mips_last_arg_regnum; | |
133 | int mips_last_fp_arg_regnum; | |
6d82d43b AC |
134 | int default_mask_address_p; |
135 | /* Is the target using 64-bit raw integer registers but only | |
136 | storing a left-aligned 32-bit value in each? */ | |
137 | int mips64_transfers_32bit_regs_p; | |
138 | /* Indexes for various registers. IRIX and embedded have | |
139 | different values. This contains the "public" fields. Don't | |
140 | add any that do not need to be public. */ | |
141 | const struct mips_regnum *regnum; | |
142 | /* Register names table for the current register set. */ | |
143 | const char **mips_processor_reg_names; | |
144 | }; | |
c2d11a7d | 145 | |
fed7ba43 JB |
146 | static int |
147 | n32n64_floatformat_always_valid (const struct floatformat *fmt, | |
2244f671 | 148 | const void *from) |
fed7ba43 JB |
149 | { |
150 | return 1; | |
151 | } | |
152 | ||
153 | /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long. | |
154 | They are implemented as a pair of 64bit doubles where the high | |
155 | part holds the result of the operation rounded to double, and | |
156 | the low double holds the difference between the exact result and | |
157 | the rounded result. So "high" + "low" contains the result with | |
158 | added precision. Unfortunately, the floatformat structure used | |
159 | by GDB is not powerful enough to describe this format. As a temporary | |
160 | measure, we define a 128bit floatformat that only uses the high part. | |
161 | We lose a bit of precision but that's probably the best we can do | |
162 | for now with the current infrastructure. */ | |
163 | ||
164 | static const struct floatformat floatformat_n32n64_long_double_big = | |
165 | { | |
166 | floatformat_big, 128, 0, 1, 11, 1023, 2047, 12, 52, | |
167 | floatformat_intbit_no, | |
168 | "floatformat_ieee_double_big", | |
169 | n32n64_floatformat_always_valid | |
170 | }; | |
171 | ||
56cea623 AC |
172 | const struct mips_regnum * |
173 | mips_regnum (struct gdbarch *gdbarch) | |
174 | { | |
175 | return gdbarch_tdep (gdbarch)->regnum; | |
176 | } | |
177 | ||
178 | static int | |
179 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
180 | { | |
181 | return mips_regnum (gdbarch)->fp0 + 12; | |
182 | } | |
183 | ||
0dadbba0 | 184 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \ |
216a600b | 185 | || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64) |
c2d11a7d | 186 | |
c2d11a7d | 187 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 188 | |
c2d11a7d | 189 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 190 | |
c2d11a7d | 191 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) |
c2d11a7d | 192 | |
95404a3e AC |
193 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
194 | functions to test, set, or clear bit 0 of addresses. */ | |
195 | ||
196 | static CORE_ADDR | |
197 | is_mips16_addr (CORE_ADDR addr) | |
198 | { | |
199 | return ((addr) & 1); | |
200 | } | |
201 | ||
95404a3e AC |
202 | static CORE_ADDR |
203 | unmake_mips16_addr (CORE_ADDR addr) | |
204 | { | |
205 | return ((addr) & ~1); | |
206 | } | |
207 | ||
22540ece AC |
208 | /* Return the contents of register REGNUM as a signed integer. */ |
209 | ||
210 | static LONGEST | |
211 | read_signed_register (int regnum) | |
212 | { | |
1d93fe1a AC |
213 | LONGEST val; |
214 | regcache_cooked_read_signed (current_regcache, regnum, &val); | |
215 | return val; | |
22540ece AC |
216 | } |
217 | ||
218 | static LONGEST | |
219 | read_signed_register_pid (int regnum, ptid_t ptid) | |
220 | { | |
221 | ptid_t save_ptid; | |
222 | LONGEST retval; | |
223 | ||
224 | if (ptid_equal (ptid, inferior_ptid)) | |
225 | return read_signed_register (regnum); | |
226 | ||
227 | save_ptid = inferior_ptid; | |
228 | ||
229 | inferior_ptid = ptid; | |
230 | ||
231 | retval = read_signed_register (regnum); | |
232 | ||
233 | inferior_ptid = save_ptid; | |
234 | ||
235 | return retval; | |
236 | } | |
237 | ||
d1973055 KB |
238 | /* Return the MIPS ABI associated with GDBARCH. */ |
239 | enum mips_abi | |
240 | mips_abi (struct gdbarch *gdbarch) | |
241 | { | |
242 | return gdbarch_tdep (gdbarch)->mips_abi; | |
243 | } | |
244 | ||
4246e332 | 245 | int |
1b13c4f6 | 246 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 AC |
247 | { |
248 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word | |
249 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
250 | } | |
251 | ||
480d3dd2 AC |
252 | /* Return the currently configured (or set) saved register size. */ |
253 | ||
1b13c4f6 | 254 | static const char *mips_abi_regsize_string = size_auto; |
480d3dd2 | 255 | |
e6bc2e8a | 256 | unsigned int |
13326b4e | 257 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 258 | { |
1b13c4f6 | 259 | if (mips_abi_regsize_string == size_auto) |
13326b4e AC |
260 | switch (mips_abi (gdbarch)) |
261 | { | |
262 | case MIPS_ABI_EABI32: | |
263 | case MIPS_ABI_O32: | |
264 | return 4; | |
265 | case MIPS_ABI_N32: | |
266 | case MIPS_ABI_N64: | |
267 | case MIPS_ABI_O64: | |
268 | case MIPS_ABI_EABI64: | |
269 | return 8; | |
270 | case MIPS_ABI_UNKNOWN: | |
271 | case MIPS_ABI_LAST: | |
272 | default: | |
e2e0b3e5 | 273 | internal_error (__FILE__, __LINE__, _("bad switch")); |
13326b4e | 274 | } |
1b13c4f6 | 275 | else if (mips_abi_regsize_string == size_64) |
d929b26f | 276 | return 8; |
1b13c4f6 | 277 | else /* if (mips_abi_regsize_string == size_32) */ |
d929b26f AC |
278 | return 4; |
279 | } | |
280 | ||
71b8ef93 | 281 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 282 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 283 | "info" field is used for this purpose. |
5a89d8aa MS |
284 | |
285 | ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special", | |
286 | i.e. refers to a 16-bit function, and sets a "special" bit in a | |
287 | minimal symbol to mark it as a 16-bit function | |
288 | ||
f594e5e9 | 289 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 290 | |
5a89d8aa | 291 | static void |
6d82d43b AC |
292 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
293 | { | |
294 | if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16) | |
295 | { | |
296 | MSYMBOL_INFO (msym) = (char *) | |
297 | (((long) MSYMBOL_INFO (msym)) | 0x80000000); | |
298 | SYMBOL_VALUE_ADDRESS (msym) |= 1; | |
299 | } | |
5a89d8aa MS |
300 | } |
301 | ||
71b8ef93 MS |
302 | static int |
303 | msymbol_is_special (struct minimal_symbol *msym) | |
304 | { | |
305 | return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0); | |
306 | } | |
307 | ||
88658117 AC |
308 | /* XFER a value from the big/little/left end of the register. |
309 | Depending on the size of the value it might occupy the entire | |
310 | register or just part of it. Make an allowance for this, aligning | |
311 | things accordingly. */ | |
312 | ||
313 | static void | |
314 | mips_xfer_register (struct regcache *regcache, int reg_num, int length, | |
870cd05e MK |
315 | enum bfd_endian endian, gdb_byte *in, |
316 | const gdb_byte *out, int buf_offset) | |
88658117 | 317 | { |
88658117 | 318 | int reg_offset = 0; |
a4b8ebc8 | 319 | gdb_assert (reg_num >= NUM_REGS); |
cb1d2653 AC |
320 | /* Need to transfer the left or right part of the register, based on |
321 | the targets byte order. */ | |
88658117 AC |
322 | switch (endian) |
323 | { | |
324 | case BFD_ENDIAN_BIG: | |
719ec221 | 325 | reg_offset = register_size (current_gdbarch, reg_num) - length; |
88658117 AC |
326 | break; |
327 | case BFD_ENDIAN_LITTLE: | |
328 | reg_offset = 0; | |
329 | break; | |
6d82d43b | 330 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
331 | reg_offset = 0; |
332 | break; | |
333 | default: | |
e2e0b3e5 | 334 | internal_error (__FILE__, __LINE__, _("bad switch")); |
88658117 AC |
335 | } |
336 | if (mips_debug) | |
cb1d2653 AC |
337 | fprintf_unfiltered (gdb_stderr, |
338 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
339 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
340 | if (mips_debug && out != NULL) |
341 | { | |
342 | int i; | |
cb1d2653 | 343 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 344 | for (i = 0; i < length; i++) |
cb1d2653 | 345 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
346 | } |
347 | if (in != NULL) | |
6d82d43b AC |
348 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
349 | in + buf_offset); | |
88658117 | 350 | if (out != NULL) |
6d82d43b AC |
351 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
352 | out + buf_offset); | |
88658117 AC |
353 | if (mips_debug && in != NULL) |
354 | { | |
355 | int i; | |
cb1d2653 | 356 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 357 | for (i = 0; i < length; i++) |
cb1d2653 | 358 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
359 | } |
360 | if (mips_debug) | |
361 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
362 | } | |
363 | ||
dd824b04 DJ |
364 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
365 | compatiblity mode. A return value of 1 means that we have | |
366 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
367 | ||
368 | static int | |
369 | mips2_fp_compat (void) | |
370 | { | |
371 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not | |
372 | meaningful. */ | |
6d82d43b AC |
373 | if (register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) == |
374 | 4) | |
dd824b04 DJ |
375 | return 0; |
376 | ||
377 | #if 0 | |
378 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
379 | in all the places we deal with FP registers. PR gdb/413. */ | |
380 | /* Otherwise check the FR bit in the status register - it controls | |
381 | the FP compatiblity mode. If it is clear we are in compatibility | |
382 | mode. */ | |
24e05951 | 383 | if ((read_register (MIPS_PS_REGNUM) & ST0_FR) == 0) |
dd824b04 DJ |
384 | return 1; |
385 | #endif | |
361d1df0 | 386 | |
dd824b04 DJ |
387 | return 0; |
388 | } | |
389 | ||
d929b26f | 390 | /* The amount of space reserved on the stack for registers. This is |
1b13c4f6 | 391 | different to MIPS_ABI_REGSIZE as it determines the alignment of |
d929b26f AC |
392 | data allocated after the registers have run out. */ |
393 | ||
53904c9e | 394 | static const char *mips_stack_argsize_string = size_auto; |
d929b26f AC |
395 | |
396 | static unsigned int | |
13326b4e | 397 | mips_stack_argsize (struct gdbarch *gdbarch) |
d929b26f AC |
398 | { |
399 | if (mips_stack_argsize_string == size_auto) | |
13326b4e | 400 | return mips_abi_regsize (gdbarch); |
d929b26f AC |
401 | else if (mips_stack_argsize_string == size_64) |
402 | return 8; | |
6d82d43b | 403 | else /* if (mips_stack_argsize_string == size_32) */ |
d929b26f AC |
404 | return 4; |
405 | } | |
406 | ||
7a292a7a | 407 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 408 | |
a14ed312 | 409 | static CORE_ADDR heuristic_proc_start (CORE_ADDR); |
c906108c | 410 | |
a14ed312 | 411 | static CORE_ADDR read_next_frame_reg (struct frame_info *, int); |
c906108c | 412 | |
a14ed312 | 413 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 414 | |
67b2c998 DJ |
415 | static struct type *mips_float_register_type (void); |
416 | static struct type *mips_double_register_type (void); | |
417 | ||
acdb74a0 AC |
418 | /* The list of available "set mips " and "show mips " commands */ |
419 | ||
420 | static struct cmd_list_element *setmipscmdlist = NULL; | |
421 | static struct cmd_list_element *showmipscmdlist = NULL; | |
422 | ||
5e2e9765 KB |
423 | /* Integer registers 0 thru 31 are handled explicitly by |
424 | mips_register_name(). Processor specific registers 32 and above | |
691c0433 AC |
425 | are listed in the followign tables. */ |
426 | ||
6d82d43b AC |
427 | enum |
428 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
429 | |
430 | /* Generic MIPS. */ | |
431 | ||
432 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
433 | "sr", "lo", "hi", "bad", "cause", "pc", |
434 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
435 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
436 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
437 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
438 | "fsr", "fir", "" /*"fp" */ , "", | |
439 | "", "", "", "", "", "", "", "", | |
440 | "", "", "", "", "", "", "", "", | |
691c0433 AC |
441 | }; |
442 | ||
443 | /* Names of IDT R3041 registers. */ | |
444 | ||
445 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
446 | "sr", "lo", "hi", "bad", "cause", "pc", |
447 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
448 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
449 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
450 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
451 | "fsr", "fir", "", /*"fp" */ "", | |
452 | "", "", "bus", "ccfg", "", "", "", "", | |
453 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
454 | }; |
455 | ||
456 | /* Names of tx39 registers. */ | |
457 | ||
458 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
459 | "sr", "lo", "hi", "bad", "cause", "pc", |
460 | "", "", "", "", "", "", "", "", | |
461 | "", "", "", "", "", "", "", "", | |
462 | "", "", "", "", "", "", "", "", | |
463 | "", "", "", "", "", "", "", "", | |
464 | "", "", "", "", | |
465 | "", "", "", "", "", "", "", "", | |
466 | "", "", "config", "cache", "debug", "depc", "epc", "" | |
691c0433 AC |
467 | }; |
468 | ||
469 | /* Names of IRIX registers. */ | |
470 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
471 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
472 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
473 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
474 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
475 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
476 | }; |
477 | ||
cce74817 | 478 | |
5e2e9765 | 479 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 480 | static const char * |
5e2e9765 | 481 | mips_register_name (int regno) |
cce74817 | 482 | { |
691c0433 | 483 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
5e2e9765 KB |
484 | /* GPR names for all ABIs other than n32/n64. */ |
485 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
486 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
487 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
488 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
489 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
490 | }; |
491 | ||
492 | /* GPR names for n32 and n64 ABIs. */ | |
493 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
494 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
495 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
496 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
497 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
498 | }; |
499 | ||
500 | enum mips_abi abi = mips_abi (current_gdbarch); | |
501 | ||
a4b8ebc8 AC |
502 | /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then |
503 | don't make the raw register names visible. */ | |
504 | int rawnum = regno % NUM_REGS; | |
505 | if (regno < NUM_REGS) | |
506 | return ""; | |
507 | ||
5e2e9765 KB |
508 | /* The MIPS integer registers are always mapped from 0 to 31. The |
509 | names of the registers (which reflects the conventions regarding | |
510 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 511 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
512 | { |
513 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 514 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 515 | else |
a4b8ebc8 | 516 | return mips_gpr_names[rawnum]; |
5e2e9765 | 517 | } |
a4b8ebc8 | 518 | else if (32 <= rawnum && rawnum < NUM_REGS) |
691c0433 AC |
519 | { |
520 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
521 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
522 | } | |
5e2e9765 KB |
523 | else |
524 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 525 | _("mips_register_name: bad register number %d"), rawnum); |
cce74817 | 526 | } |
5e2e9765 | 527 | |
a4b8ebc8 | 528 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 529 | |
a4b8ebc8 AC |
530 | static int |
531 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
532 | struct reggroup *reggroup) | |
533 | { | |
534 | int vector_p; | |
535 | int float_p; | |
536 | int raw_p; | |
537 | int rawnum = regnum % NUM_REGS; | |
538 | int pseudo = regnum / NUM_REGS; | |
539 | if (reggroup == all_reggroup) | |
540 | return pseudo; | |
541 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
542 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
543 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
544 | (gdbarch), as not all architectures are multi-arch. */ | |
545 | raw_p = rawnum < NUM_REGS; | |
6d82d43b | 546 | if (REGISTER_NAME (regnum) == NULL || REGISTER_NAME (regnum)[0] == '\0') |
a4b8ebc8 AC |
547 | return 0; |
548 | if (reggroup == float_reggroup) | |
549 | return float_p && pseudo; | |
550 | if (reggroup == vector_reggroup) | |
551 | return vector_p && pseudo; | |
552 | if (reggroup == general_reggroup) | |
553 | return (!vector_p && !float_p) && pseudo; | |
554 | /* Save the pseudo registers. Need to make certain that any code | |
555 | extracting register values from a saved register cache also uses | |
556 | pseudo registers. */ | |
557 | if (reggroup == save_reggroup) | |
558 | return raw_p && pseudo; | |
559 | /* Restore the same pseudo register. */ | |
560 | if (reggroup == restore_reggroup) | |
561 | return raw_p && pseudo; | |
6d82d43b | 562 | return 0; |
a4b8ebc8 AC |
563 | } |
564 | ||
565 | /* Map the symbol table registers which live in the range [1 * | |
566 | NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw | |
47ebcfbe | 567 | registers. Take care of alignment and size problems. */ |
c5aa993b | 568 | |
a4b8ebc8 AC |
569 | static void |
570 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
47a35522 | 571 | int cookednum, gdb_byte *buf) |
a4b8ebc8 | 572 | { |
47ebcfbe | 573 | int rawnum = cookednum % NUM_REGS; |
a4b8ebc8 | 574 | gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); |
47ebcfbe | 575 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 576 | regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
577 | else if (register_size (gdbarch, rawnum) > |
578 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
579 | { |
580 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
581 | || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
582 | regcache_raw_read_part (regcache, rawnum, 0, 4, buf); | |
583 | else | |
584 | regcache_raw_read_part (regcache, rawnum, 4, 4, buf); | |
585 | } | |
586 | else | |
e2e0b3e5 | 587 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 AC |
588 | } |
589 | ||
590 | static void | |
6d82d43b AC |
591 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
592 | struct regcache *regcache, int cookednum, | |
47a35522 | 593 | const gdb_byte *buf) |
a4b8ebc8 | 594 | { |
47ebcfbe | 595 | int rawnum = cookednum % NUM_REGS; |
a4b8ebc8 | 596 | gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); |
47ebcfbe | 597 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 598 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
599 | else if (register_size (gdbarch, rawnum) > |
600 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
601 | { |
602 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
603 | || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
604 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); | |
605 | else | |
606 | regcache_raw_write_part (regcache, rawnum, 4, 4, buf); | |
607 | } | |
608 | else | |
e2e0b3e5 | 609 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 | 610 | } |
c5aa993b | 611 | |
c906108c | 612 | /* Table to translate MIPS16 register field to actual register number. */ |
6d82d43b | 613 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
614 | |
615 | /* Heuristic_proc_start may hunt through the text section for a long | |
616 | time across a 2400 baud serial line. Allows the user to limit this | |
617 | search. */ | |
618 | ||
619 | static unsigned int heuristic_fence_post = 0; | |
620 | ||
46cd78fb | 621 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
622 | register N. NOTE: This defines the pseudo register type so need to |
623 | rebuild the architecture vector. */ | |
43e526b9 JM |
624 | |
625 | static int mips64_transfers_32bit_regs_p = 0; | |
626 | ||
719ec221 AC |
627 | static void |
628 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
629 | struct cmd_list_element *c) | |
43e526b9 | 630 | { |
719ec221 AC |
631 | struct gdbarch_info info; |
632 | gdbarch_info_init (&info); | |
633 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
634 | instead of relying on globals. Doing that would let generic code | |
635 | handle the search for this specific architecture. */ | |
636 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 637 | { |
719ec221 | 638 | mips64_transfers_32bit_regs_p = 0; |
8a3fe4f8 | 639 | error (_("32-bit compatibility mode not supported")); |
a4b8ebc8 | 640 | } |
a4b8ebc8 AC |
641 | } |
642 | ||
47ebcfbe | 643 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 644 | |
ff2e87ac AC |
645 | static int |
646 | mips_convert_register_p (int regnum, struct type *type) | |
647 | { | |
648 | return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
719ec221 | 649 | && register_size (current_gdbarch, regnum) == 4 |
87783b8b AC |
650 | && (regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0 |
651 | && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32 | |
6d82d43b | 652 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
653 | } |
654 | ||
42c466d7 | 655 | static void |
ff2e87ac | 656 | mips_register_to_value (struct frame_info *frame, int regnum, |
47a35522 | 657 | struct type *type, gdb_byte *to) |
102182a9 | 658 | { |
47a35522 MK |
659 | get_frame_register (frame, regnum + 0, to + 4); |
660 | get_frame_register (frame, regnum + 1, to + 0); | |
102182a9 MS |
661 | } |
662 | ||
42c466d7 | 663 | static void |
ff2e87ac | 664 | mips_value_to_register (struct frame_info *frame, int regnum, |
47a35522 | 665 | struct type *type, const gdb_byte *from) |
102182a9 | 666 | { |
47a35522 MK |
667 | put_frame_register (frame, regnum + 0, from + 4); |
668 | put_frame_register (frame, regnum + 1, from + 0); | |
102182a9 MS |
669 | } |
670 | ||
a4b8ebc8 AC |
671 | /* Return the GDB type object for the "standard" data type of data in |
672 | register REG. */ | |
78fde5f8 KB |
673 | |
674 | static struct type * | |
a4b8ebc8 AC |
675 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
676 | { | |
5ef80fb0 | 677 | gdb_assert (regnum >= 0 && regnum < 2 * NUM_REGS); |
56cea623 AC |
678 | if ((regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0 |
679 | && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32) | |
a6425924 | 680 | { |
5ef80fb0 | 681 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 682 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
5ef80fb0 AC |
683 | switch (gdbarch_byte_order (gdbarch)) |
684 | { | |
685 | case BFD_ENDIAN_BIG: | |
1b13c4f6 | 686 | if (mips_isa_regsize (gdbarch) == 4) |
5ef80fb0 AC |
687 | return builtin_type_ieee_single_big; |
688 | else | |
689 | return builtin_type_ieee_double_big; | |
690 | case BFD_ENDIAN_LITTLE: | |
1b13c4f6 | 691 | if (mips_isa_regsize (gdbarch) == 4) |
5ef80fb0 AC |
692 | return builtin_type_ieee_single_little; |
693 | else | |
694 | return builtin_type_ieee_double_little; | |
695 | case BFD_ENDIAN_UNKNOWN: | |
696 | default: | |
e2e0b3e5 | 697 | internal_error (__FILE__, __LINE__, _("bad switch")); |
5ef80fb0 | 698 | } |
a6425924 | 699 | } |
d5ac5a39 AC |
700 | else if (regnum < NUM_REGS) |
701 | { | |
702 | /* The raw or ISA registers. These are all sized according to | |
703 | the ISA regsize. */ | |
704 | if (mips_isa_regsize (gdbarch) == 4) | |
705 | return builtin_type_int32; | |
706 | else | |
707 | return builtin_type_int64; | |
708 | } | |
78fde5f8 | 709 | else |
d5ac5a39 AC |
710 | { |
711 | /* The cooked or ABI registers. These are sized according to | |
712 | the ABI (with a few complications). */ | |
713 | if (regnum >= (NUM_REGS | |
714 | + mips_regnum (current_gdbarch)->fp_control_status) | |
607fc93c | 715 | && regnum <= NUM_REGS + MIPS_LAST_EMBED_REGNUM) |
d5ac5a39 AC |
716 | /* The pseudo/cooked view of the embedded registers is always |
717 | 32-bit. The raw view is handled below. */ | |
718 | return builtin_type_int32; | |
719 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) | |
720 | /* The target, while possibly using a 64-bit register buffer, | |
721 | is only transfering 32-bits of each integer register. | |
722 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
723 | return builtin_type_int32; | |
724 | else if (mips_abi_regsize (gdbarch) == 4) | |
725 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
726 | 32- or 64-bit). */ | |
727 | return builtin_type_int32; | |
728 | else | |
729 | /* 64-bit ABI. */ | |
730 | return builtin_type_int64; | |
731 | } | |
78fde5f8 KB |
732 | } |
733 | ||
bcb0cc15 MS |
734 | /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */ |
735 | ||
736 | static CORE_ADDR | |
737 | mips_read_sp (void) | |
738 | { | |
f10683bb | 739 | return read_signed_register (MIPS_SP_REGNUM); |
bcb0cc15 MS |
740 | } |
741 | ||
c906108c | 742 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 743 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
744 | |
745 | static int | |
480d3dd2 | 746 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
747 | { |
748 | switch (mask_address_var) | |
749 | { | |
7f19b9a2 | 750 | case AUTO_BOOLEAN_TRUE: |
4014092b | 751 | return 1; |
7f19b9a2 | 752 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
753 | return 0; |
754 | break; | |
7f19b9a2 | 755 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 756 | return tdep->default_mask_address_p; |
4014092b | 757 | default: |
e2e0b3e5 | 758 | internal_error (__FILE__, __LINE__, _("mips_mask_address_p: bad switch")); |
4014092b | 759 | return -1; |
361d1df0 | 760 | } |
4014092b AC |
761 | } |
762 | ||
763 | static void | |
08546159 AC |
764 | show_mask_address (struct ui_file *file, int from_tty, |
765 | struct cmd_list_element *c, const char *value) | |
4014092b | 766 | { |
480d3dd2 | 767 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
08546159 AC |
768 | |
769 | deprecated_show_value_hack (file, from_tty, c, value); | |
4014092b AC |
770 | switch (mask_address_var) |
771 | { | |
7f19b9a2 | 772 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
773 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
774 | break; | |
7f19b9a2 | 775 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
776 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
777 | break; | |
7f19b9a2 | 778 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
779 | printf_filtered |
780 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
781 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
782 | break; |
783 | default: | |
e2e0b3e5 | 784 | internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); |
4014092b | 785 | break; |
361d1df0 | 786 | } |
4014092b | 787 | } |
c906108c | 788 | |
c906108c SS |
789 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
790 | ||
0fe7e7c8 AC |
791 | int |
792 | mips_pc_is_mips16 (CORE_ADDR memaddr) | |
c906108c SS |
793 | { |
794 | struct minimal_symbol *sym; | |
795 | ||
796 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
95404a3e | 797 | if (is_mips16_addr (memaddr)) |
c906108c SS |
798 | return 1; |
799 | ||
800 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
801 | the high bit of the info field. Use this to decide if the function is | |
802 | MIPS16 or normal MIPS. */ | |
803 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
804 | if (sym) | |
71b8ef93 | 805 | return msymbol_is_special (sym); |
c906108c SS |
806 | else |
807 | return 0; | |
808 | } | |
809 | ||
b2fa5097 | 810 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
6c997a34 AC |
811 | all registers should be sign extended for simplicity? */ |
812 | ||
813 | static CORE_ADDR | |
39f77062 | 814 | mips_read_pc (ptid_t ptid) |
6c997a34 | 815 | { |
b6cb9035 AC |
816 | return read_signed_register_pid (mips_regnum (current_gdbarch)->pc, ptid); |
817 | } | |
818 | ||
58dfe9ff AC |
819 | static CORE_ADDR |
820 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
821 | { | |
edfae063 AC |
822 | return frame_unwind_register_signed (next_frame, |
823 | NUM_REGS + mips_regnum (gdbarch)->pc); | |
824 | } | |
825 | ||
826 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that | |
827 | dummy frame. The frame ID's base needs to match the TOS value | |
828 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
829 | breakpoint. */ | |
830 | ||
831 | static struct frame_id | |
832 | mips_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
833 | { | |
f10683bb | 834 | return frame_id_build (frame_unwind_register_signed (next_frame, NUM_REGS + MIPS_SP_REGNUM), |
edfae063 | 835 | frame_pc_unwind (next_frame)); |
58dfe9ff AC |
836 | } |
837 | ||
b6cb9035 AC |
838 | static void |
839 | mips_write_pc (CORE_ADDR pc, ptid_t ptid) | |
840 | { | |
841 | write_register_pid (mips_regnum (current_gdbarch)->pc, pc, ptid); | |
6c997a34 | 842 | } |
c906108c | 843 | |
c906108c SS |
844 | /* Fetch and return instruction from the specified location. If the PC |
845 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
846 | ||
d37cca3d | 847 | static ULONGEST |
acdb74a0 | 848 | mips_fetch_instruction (CORE_ADDR addr) |
c906108c | 849 | { |
47a35522 | 850 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
851 | int instlen; |
852 | int status; | |
853 | ||
0fe7e7c8 | 854 | if (mips_pc_is_mips16 (addr)) |
c906108c | 855 | { |
95ac2dcf | 856 | instlen = MIPS_INSN16_SIZE; |
95404a3e | 857 | addr = unmake_mips16_addr (addr); |
c906108c SS |
858 | } |
859 | else | |
95ac2dcf | 860 | instlen = MIPS_INSN32_SIZE; |
1f602b35 | 861 | status = deprecated_read_memory_nobpt (addr, buf, instlen); |
c906108c SS |
862 | if (status) |
863 | memory_error (status, addr); | |
864 | return extract_unsigned_integer (buf, instlen); | |
865 | } | |
866 | ||
c906108c | 867 | /* These the fields of 32 bit mips instructions */ |
e135b889 DJ |
868 | #define mips32_op(x) (x >> 26) |
869 | #define itype_op(x) (x >> 26) | |
870 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 871 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 872 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 873 | |
e135b889 DJ |
874 | #define jtype_op(x) (x >> 26) |
875 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 876 | |
e135b889 DJ |
877 | #define rtype_op(x) (x >> 26) |
878 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
879 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
880 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
881 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
882 | #define rtype_funct(x) (x & 0x3f) | |
c906108c | 883 | |
06987e64 MK |
884 | static LONGEST |
885 | mips32_relative_offset (ULONGEST inst) | |
c5aa993b | 886 | { |
06987e64 | 887 | return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; |
c906108c SS |
888 | } |
889 | ||
890 | /* Determine whate to set a single step breakpoint while considering | |
891 | branch prediction */ | |
5a89d8aa | 892 | static CORE_ADDR |
c5aa993b JM |
893 | mips32_next_pc (CORE_ADDR pc) |
894 | { | |
895 | unsigned long inst; | |
896 | int op; | |
897 | inst = mips_fetch_instruction (pc); | |
e135b889 | 898 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 899 | { |
e135b889 | 900 | if (itype_op (inst) >> 2 == 5) |
6d82d43b | 901 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 902 | { |
e135b889 | 903 | op = (itype_op (inst) & 0x03); |
c906108c SS |
904 | switch (op) |
905 | { | |
e135b889 DJ |
906 | case 0: /* BEQL */ |
907 | goto equal_branch; | |
908 | case 1: /* BNEL */ | |
909 | goto neq_branch; | |
910 | case 2: /* BLEZL */ | |
911 | goto less_branch; | |
912 | case 3: /* BGTZ */ | |
913 | goto greater_branch; | |
c5aa993b JM |
914 | default: |
915 | pc += 4; | |
c906108c SS |
916 | } |
917 | } | |
e135b889 | 918 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
6d82d43b | 919 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
e135b889 DJ |
920 | { |
921 | int tf = itype_rt (inst) & 0x01; | |
922 | int cnum = itype_rt (inst) >> 2; | |
6d82d43b AC |
923 | int fcrcs = |
924 | read_signed_register (mips_regnum (current_gdbarch)-> | |
925 | fp_control_status); | |
e135b889 DJ |
926 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); |
927 | ||
928 | if (((cond >> cnum) & 0x01) == tf) | |
929 | pc += mips32_relative_offset (inst) + 4; | |
930 | else | |
931 | pc += 8; | |
932 | } | |
c5aa993b JM |
933 | else |
934 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
935 | } |
936 | else | |
c5aa993b JM |
937 | { /* This gets way messy */ |
938 | ||
c906108c | 939 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 940 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 941 | { |
c5aa993b JM |
942 | case 0: /* SPECIAL */ |
943 | op = rtype_funct (inst); | |
944 | switch (op) | |
945 | { | |
946 | case 8: /* JR */ | |
947 | case 9: /* JALR */ | |
6c997a34 AC |
948 | /* Set PC to that address */ |
949 | pc = read_signed_register (rtype_rs (inst)); | |
c5aa993b JM |
950 | break; |
951 | default: | |
952 | pc += 4; | |
953 | } | |
954 | ||
6d82d43b | 955 | break; /* end SPECIAL */ |
c5aa993b | 956 | case 1: /* REGIMM */ |
c906108c | 957 | { |
e135b889 DJ |
958 | op = itype_rt (inst); /* branch condition */ |
959 | switch (op) | |
c906108c | 960 | { |
c5aa993b | 961 | case 0: /* BLTZ */ |
e135b889 DJ |
962 | case 2: /* BLTZL */ |
963 | case 16: /* BLTZAL */ | |
c5aa993b | 964 | case 18: /* BLTZALL */ |
c906108c | 965 | less_branch: |
6c997a34 | 966 | if (read_signed_register (itype_rs (inst)) < 0) |
c5aa993b JM |
967 | pc += mips32_relative_offset (inst) + 4; |
968 | else | |
969 | pc += 8; /* after the delay slot */ | |
970 | break; | |
e135b889 | 971 | case 1: /* BGEZ */ |
c5aa993b JM |
972 | case 3: /* BGEZL */ |
973 | case 17: /* BGEZAL */ | |
974 | case 19: /* BGEZALL */ | |
6c997a34 | 975 | if (read_signed_register (itype_rs (inst)) >= 0) |
c5aa993b JM |
976 | pc += mips32_relative_offset (inst) + 4; |
977 | else | |
978 | pc += 8; /* after the delay slot */ | |
979 | break; | |
e135b889 | 980 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
981 | default: |
982 | pc += 4; | |
c906108c SS |
983 | } |
984 | } | |
6d82d43b | 985 | break; /* end REGIMM */ |
c5aa993b JM |
986 | case 2: /* J */ |
987 | case 3: /* JAL */ | |
988 | { | |
989 | unsigned long reg; | |
990 | reg = jtype_target (inst) << 2; | |
e135b889 | 991 | /* Upper four bits get never changed... */ |
c5aa993b | 992 | pc = reg + ((pc + 4) & 0xf0000000); |
c906108c | 993 | } |
c5aa993b JM |
994 | break; |
995 | /* FIXME case JALX : */ | |
996 | { | |
997 | unsigned long reg; | |
998 | reg = jtype_target (inst) << 2; | |
999 | pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */ | |
c906108c SS |
1000 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1001 | } | |
c5aa993b | 1002 | break; /* The new PC will be alternate mode */ |
e135b889 | 1003 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1004 | equal_branch: |
6c997a34 AC |
1005 | if (read_signed_register (itype_rs (inst)) == |
1006 | read_signed_register (itype_rt (inst))) | |
c5aa993b JM |
1007 | pc += mips32_relative_offset (inst) + 4; |
1008 | else | |
1009 | pc += 8; | |
1010 | break; | |
e135b889 | 1011 | case 5: /* BNE, BNEL */ |
c5aa993b | 1012 | neq_branch: |
6c997a34 | 1013 | if (read_signed_register (itype_rs (inst)) != |
e135b889 | 1014 | read_signed_register (itype_rt (inst))) |
c5aa993b JM |
1015 | pc += mips32_relative_offset (inst) + 4; |
1016 | else | |
1017 | pc += 8; | |
1018 | break; | |
e135b889 | 1019 | case 6: /* BLEZ, BLEZL */ |
1fd8cd20 | 1020 | if (read_signed_register (itype_rs (inst)) <= 0) |
c5aa993b JM |
1021 | pc += mips32_relative_offset (inst) + 4; |
1022 | else | |
1023 | pc += 8; | |
1024 | break; | |
1025 | case 7: | |
e135b889 DJ |
1026 | default: |
1027 | greater_branch: /* BGTZ, BGTZL */ | |
1fd8cd20 | 1028 | if (read_signed_register (itype_rs (inst)) > 0) |
c5aa993b JM |
1029 | pc += mips32_relative_offset (inst) + 4; |
1030 | else | |
1031 | pc += 8; | |
1032 | break; | |
c5aa993b JM |
1033 | } /* switch */ |
1034 | } /* else */ | |
1035 | return pc; | |
1036 | } /* mips32_next_pc */ | |
c906108c SS |
1037 | |
1038 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 1039 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
1040 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
1041 | We dont want to set a single step instruction on the extend instruction | |
1042 | either. | |
c5aa993b | 1043 | */ |
c906108c SS |
1044 | |
1045 | /* Lots of mips16 instruction formats */ | |
1046 | /* Predicting jumps requires itype,ritype,i8type | |
1047 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 1048 | */ |
c906108c SS |
1049 | enum mips16_inst_fmts |
1050 | { | |
c5aa993b JM |
1051 | itype, /* 0 immediate 5,10 */ |
1052 | ritype, /* 1 5,3,8 */ | |
1053 | rrtype, /* 2 5,3,3,5 */ | |
1054 | rritype, /* 3 5,3,3,5 */ | |
1055 | rrrtype, /* 4 5,3,3,3,2 */ | |
1056 | rriatype, /* 5 5,3,3,1,4 */ | |
1057 | shifttype, /* 6 5,3,3,3,2 */ | |
1058 | i8type, /* 7 5,3,8 */ | |
1059 | i8movtype, /* 8 5,3,3,5 */ | |
1060 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1061 | i64type, /* 10 5,3,8 */ | |
1062 | ri64type, /* 11 5,3,3,5 */ | |
1063 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1064 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1065 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1066 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1067 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1068 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1069 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1070 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1071 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1072 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1073 | }; | |
12f02c2a AC |
1074 | /* I am heaping all the fields of the formats into one structure and |
1075 | then, only the fields which are involved in instruction extension */ | |
c906108c | 1076 | struct upk_mips16 |
6d82d43b AC |
1077 | { |
1078 | CORE_ADDR offset; | |
1079 | unsigned int regx; /* Function in i8 type */ | |
1080 | unsigned int regy; | |
1081 | }; | |
c906108c SS |
1082 | |
1083 | ||
12f02c2a AC |
1084 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
1085 | for the bits which make up the immediatate extension. */ | |
c906108c | 1086 | |
12f02c2a AC |
1087 | static CORE_ADDR |
1088 | extended_offset (unsigned int extension) | |
c906108c | 1089 | { |
12f02c2a | 1090 | CORE_ADDR value; |
c5aa993b JM |
1091 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1092 | value = value << 6; | |
1093 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
1094 | value = value << 5; | |
1095 | value |= extension & 0x01f; /* extract 4:0 */ | |
1096 | return value; | |
c906108c SS |
1097 | } |
1098 | ||
1099 | /* Only call this function if you know that this is an extendable | |
1100 | instruction, It wont malfunction, but why make excess remote memory references? | |
1101 | If the immediate operands get sign extended or somthing, do it after | |
1102 | the extension is performed. | |
c5aa993b | 1103 | */ |
c906108c SS |
1104 | /* FIXME: Every one of these cases needs to worry about sign extension |
1105 | when the offset is to be used in relative addressing */ | |
1106 | ||
1107 | ||
12f02c2a | 1108 | static unsigned int |
c5aa993b | 1109 | fetch_mips_16 (CORE_ADDR pc) |
c906108c | 1110 | { |
47a35522 | 1111 | gdb_byte buf[8]; |
c5aa993b JM |
1112 | pc &= 0xfffffffe; /* clear the low order bit */ |
1113 | target_read_memory (pc, buf, 2); | |
1114 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
1115 | } |
1116 | ||
1117 | static void | |
c5aa993b | 1118 | unpack_mips16 (CORE_ADDR pc, |
12f02c2a AC |
1119 | unsigned int extension, |
1120 | unsigned int inst, | |
6d82d43b | 1121 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 1122 | { |
12f02c2a AC |
1123 | CORE_ADDR offset; |
1124 | int regx; | |
1125 | int regy; | |
1126 | switch (insn_format) | |
c906108c | 1127 | { |
c5aa993b | 1128 | case itype: |
c906108c | 1129 | { |
12f02c2a AC |
1130 | CORE_ADDR value; |
1131 | if (extension) | |
c5aa993b JM |
1132 | { |
1133 | value = extended_offset (extension); | |
1134 | value = value << 11; /* rom for the original value */ | |
6d82d43b | 1135 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1136 | } |
1137 | else | |
c5aa993b | 1138 | { |
12f02c2a | 1139 | value = inst & 0x7ff; |
c5aa993b | 1140 | /* FIXME : Consider sign extension */ |
c906108c | 1141 | } |
12f02c2a AC |
1142 | offset = value; |
1143 | regx = -1; | |
1144 | regy = -1; | |
c906108c | 1145 | } |
c5aa993b JM |
1146 | break; |
1147 | case ritype: | |
1148 | case i8type: | |
1149 | { /* A register identifier and an offset */ | |
c906108c SS |
1150 | /* Most of the fields are the same as I type but the |
1151 | immediate value is of a different length */ | |
12f02c2a AC |
1152 | CORE_ADDR value; |
1153 | if (extension) | |
c906108c | 1154 | { |
c5aa993b JM |
1155 | value = extended_offset (extension); |
1156 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1157 | value |= inst & 0xff; /* eleven bits from instruction */ |
1158 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1159 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1160 | { | |
1161 | value &= ~0x3fff; /* remove the sign bit */ | |
1162 | value = -value; | |
c906108c SS |
1163 | } |
1164 | } | |
c5aa993b JM |
1165 | else |
1166 | { | |
12f02c2a AC |
1167 | value = inst & 0xff; /* 8 bits */ |
1168 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1169 | /* FIXME: Do sign extension , this format needs it */ |
1170 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1171 | { | |
1172 | value &= 0xef; /* remove the sign bit */ | |
1173 | value = -value; | |
1174 | } | |
c5aa993b | 1175 | } |
12f02c2a AC |
1176 | offset = value; |
1177 | regy = -1; | |
c5aa993b | 1178 | break; |
c906108c | 1179 | } |
c5aa993b | 1180 | case jalxtype: |
c906108c | 1181 | { |
c5aa993b | 1182 | unsigned long value; |
12f02c2a AC |
1183 | unsigned int nexthalf; |
1184 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b JM |
1185 | value = value << 16; |
1186 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
1187 | value |= nexthalf; | |
12f02c2a AC |
1188 | offset = value; |
1189 | regx = -1; | |
1190 | regy = -1; | |
c5aa993b | 1191 | break; |
c906108c SS |
1192 | } |
1193 | default: | |
e2e0b3e5 | 1194 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c | 1195 | } |
12f02c2a AC |
1196 | upk->offset = offset; |
1197 | upk->regx = regx; | |
1198 | upk->regy = regy; | |
c906108c SS |
1199 | } |
1200 | ||
1201 | ||
c5aa993b JM |
1202 | static CORE_ADDR |
1203 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1204 | { |
c5aa993b | 1205 | return ((offset << 2) | ((pc + 2) & (0xf0000000))); |
c906108c SS |
1206 | } |
1207 | ||
12f02c2a AC |
1208 | static CORE_ADDR |
1209 | extended_mips16_next_pc (CORE_ADDR pc, | |
6d82d43b | 1210 | unsigned int extension, unsigned int insn) |
c906108c | 1211 | { |
12f02c2a AC |
1212 | int op = (insn >> 11); |
1213 | switch (op) | |
c906108c | 1214 | { |
6d82d43b | 1215 | case 2: /* Branch */ |
12f02c2a AC |
1216 | { |
1217 | CORE_ADDR offset; | |
1218 | struct upk_mips16 upk; | |
1219 | unpack_mips16 (pc, extension, insn, itype, &upk); | |
1220 | offset = upk.offset; | |
1221 | if (offset & 0x800) | |
1222 | { | |
1223 | offset &= 0xeff; | |
1224 | offset = -offset; | |
1225 | } | |
1226 | pc += (offset << 1) + 2; | |
1227 | break; | |
1228 | } | |
6d82d43b | 1229 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ |
12f02c2a AC |
1230 | { |
1231 | struct upk_mips16 upk; | |
1232 | unpack_mips16 (pc, extension, insn, jalxtype, &upk); | |
1233 | pc = add_offset_16 (pc, upk.offset); | |
1234 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1235 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1236 | else | |
1237 | pc |= 0x01; | |
1238 | break; | |
1239 | } | |
6d82d43b | 1240 | case 4: /* beqz */ |
12f02c2a AC |
1241 | { |
1242 | struct upk_mips16 upk; | |
1243 | int reg; | |
1244 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1245 | reg = read_signed_register (upk.regx); | |
1246 | if (reg == 0) | |
1247 | pc += (upk.offset << 1) + 2; | |
1248 | else | |
1249 | pc += 2; | |
1250 | break; | |
1251 | } | |
6d82d43b | 1252 | case 5: /* bnez */ |
12f02c2a AC |
1253 | { |
1254 | struct upk_mips16 upk; | |
1255 | int reg; | |
1256 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1257 | reg = read_signed_register (upk.regx); | |
1258 | if (reg != 0) | |
1259 | pc += (upk.offset << 1) + 2; | |
1260 | else | |
1261 | pc += 2; | |
1262 | break; | |
1263 | } | |
6d82d43b | 1264 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
1265 | { |
1266 | struct upk_mips16 upk; | |
1267 | int reg; | |
1268 | unpack_mips16 (pc, extension, insn, i8type, &upk); | |
1269 | /* upk.regx contains the opcode */ | |
1270 | reg = read_signed_register (24); /* Test register is 24 */ | |
1271 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ | |
1272 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1273 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1274 | pc += (upk.offset << 1) + 2; | |
1275 | else | |
1276 | pc += 2; | |
1277 | break; | |
1278 | } | |
6d82d43b | 1279 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
1280 | { |
1281 | struct upk_mips16 upk; | |
1282 | /* upk.fmt = rrtype; */ | |
1283 | op = insn & 0x1f; | |
1284 | if (op == 0) | |
c5aa993b | 1285 | { |
12f02c2a AC |
1286 | int reg; |
1287 | upk.regx = (insn >> 8) & 0x07; | |
1288 | upk.regy = (insn >> 5) & 0x07; | |
1289 | switch (upk.regy) | |
c5aa993b | 1290 | { |
12f02c2a AC |
1291 | case 0: |
1292 | reg = upk.regx; | |
1293 | break; | |
1294 | case 1: | |
1295 | reg = 31; | |
6d82d43b | 1296 | break; /* Function return instruction */ |
12f02c2a AC |
1297 | case 2: |
1298 | reg = upk.regx; | |
1299 | break; | |
1300 | default: | |
1301 | reg = 31; | |
6d82d43b | 1302 | break; /* BOGUS Guess */ |
c906108c | 1303 | } |
12f02c2a | 1304 | pc = read_signed_register (reg); |
c906108c | 1305 | } |
12f02c2a | 1306 | else |
c5aa993b | 1307 | pc += 2; |
12f02c2a AC |
1308 | break; |
1309 | } | |
1310 | case 30: | |
1311 | /* This is an instruction extension. Fetch the real instruction | |
1312 | (which follows the extension) and decode things based on | |
1313 | that. */ | |
1314 | { | |
1315 | pc += 2; | |
1316 | pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc)); | |
1317 | break; | |
1318 | } | |
1319 | default: | |
1320 | { | |
1321 | pc += 2; | |
1322 | break; | |
1323 | } | |
c906108c | 1324 | } |
c5aa993b | 1325 | return pc; |
12f02c2a | 1326 | } |
c906108c | 1327 | |
5a89d8aa | 1328 | static CORE_ADDR |
12f02c2a AC |
1329 | mips16_next_pc (CORE_ADDR pc) |
1330 | { | |
1331 | unsigned int insn = fetch_mips_16 (pc); | |
1332 | return extended_mips16_next_pc (pc, 0, insn); | |
1333 | } | |
1334 | ||
1335 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1336 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1337 | It works by decoding the current instruction and predicting where a |
1338 | branch will go. This isnt hard because all the data is available. | |
1339 | The MIPS32 and MIPS16 variants are quite different */ | |
c5aa993b JM |
1340 | CORE_ADDR |
1341 | mips_next_pc (CORE_ADDR pc) | |
c906108c | 1342 | { |
c5aa993b JM |
1343 | if (pc & 0x01) |
1344 | return mips16_next_pc (pc); | |
1345 | else | |
1346 | return mips32_next_pc (pc); | |
12f02c2a | 1347 | } |
c906108c | 1348 | |
edfae063 AC |
1349 | struct mips_frame_cache |
1350 | { | |
1351 | CORE_ADDR base; | |
1352 | struct trad_frame_saved_reg *saved_regs; | |
1353 | }; | |
1354 | ||
29639122 JB |
1355 | /* Set a register's saved stack address in temp_saved_regs. If an |
1356 | address has already been set for this register, do nothing; this | |
1357 | way we will only recognize the first save of a given register in a | |
1358 | function prologue. | |
eec63939 | 1359 | |
29639122 JB |
1360 | For simplicity, save the address in both [0 .. NUM_REGS) and |
1361 | [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range | |
1362 | is used as it is only second range (the ABI instead of ISA | |
1363 | registers) that comes into play when finding saved registers in a | |
1364 | frame. */ | |
eec63939 AC |
1365 | |
1366 | static void | |
29639122 JB |
1367 | set_reg_offset (struct mips_frame_cache *this_cache, int regnum, |
1368 | CORE_ADDR offset) | |
eec63939 | 1369 | { |
29639122 JB |
1370 | if (this_cache != NULL |
1371 | && this_cache->saved_regs[regnum].addr == -1) | |
1372 | { | |
1373 | this_cache->saved_regs[regnum + 0 * NUM_REGS].addr = offset; | |
1374 | this_cache->saved_regs[regnum + 1 * NUM_REGS].addr = offset; | |
1375 | } | |
eec63939 AC |
1376 | } |
1377 | ||
eec63939 | 1378 | |
29639122 JB |
1379 | /* Fetch the immediate value from a MIPS16 instruction. |
1380 | If the previous instruction was an EXTEND, use it to extend | |
1381 | the upper bits of the immediate value. This is a helper function | |
1382 | for mips16_scan_prologue. */ | |
eec63939 | 1383 | |
29639122 JB |
1384 | static int |
1385 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ | |
1386 | unsigned short inst, /* current instruction */ | |
1387 | int nbits, /* number of bits in imm field */ | |
1388 | int scale, /* scale factor to be applied to imm */ | |
1389 | int is_signed) /* is the imm field signed? */ | |
eec63939 | 1390 | { |
29639122 | 1391 | int offset; |
eec63939 | 1392 | |
29639122 JB |
1393 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
1394 | { | |
1395 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
1396 | if (offset & 0x8000) /* check for negative extend */ | |
1397 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
1398 | return offset | (inst & 0x1f); | |
1399 | } | |
eec63939 | 1400 | else |
29639122 JB |
1401 | { |
1402 | int max_imm = 1 << nbits; | |
1403 | int mask = max_imm - 1; | |
1404 | int sign_bit = max_imm >> 1; | |
45c9dd44 | 1405 | |
29639122 JB |
1406 | offset = inst & mask; |
1407 | if (is_signed && (offset & sign_bit)) | |
1408 | offset = 0 - (max_imm - offset); | |
1409 | return offset * scale; | |
1410 | } | |
1411 | } | |
eec63939 | 1412 | |
65596487 | 1413 | |
29639122 JB |
1414 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1415 | the associated FRAME_CACHE if not null. | |
1416 | Return the address of the first instruction past the prologue. */ | |
eec63939 | 1417 | |
29639122 JB |
1418 | static CORE_ADDR |
1419 | mips16_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
1420 | struct frame_info *next_frame, | |
1421 | struct mips_frame_cache *this_cache) | |
1422 | { | |
1423 | CORE_ADDR cur_pc; | |
1424 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
1425 | CORE_ADDR sp; | |
1426 | long frame_offset = 0; /* Size of stack frame. */ | |
1427 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
1428 | int frame_reg = MIPS_SP_REGNUM; | |
1429 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
1430 | unsigned inst = 0; /* current instruction */ | |
1431 | unsigned entry_inst = 0; /* the entry instruction */ | |
1432 | int reg, offset; | |
a343eb3c | 1433 | |
29639122 JB |
1434 | int extend_bytes = 0; |
1435 | int prev_extend_bytes; | |
1436 | CORE_ADDR end_prologue_addr = 0; | |
a343eb3c | 1437 | |
29639122 JB |
1438 | /* Can be called when there's no process, and hence when there's no |
1439 | NEXT_FRAME. */ | |
1440 | if (next_frame != NULL) | |
1441 | sp = read_next_frame_reg (next_frame, NUM_REGS + MIPS_SP_REGNUM); | |
1442 | else | |
1443 | sp = 0; | |
eec63939 | 1444 | |
29639122 JB |
1445 | if (limit_pc > start_pc + 200) |
1446 | limit_pc = start_pc + 200; | |
eec63939 | 1447 | |
95ac2dcf | 1448 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) |
29639122 JB |
1449 | { |
1450 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1451 | the immediate offset extension from it in mips16_get_imm. */ | |
1452 | prev_inst = inst; | |
eec63939 | 1453 | |
29639122 JB |
1454 | /* Fetch and decode the instruction. */ |
1455 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
eec63939 | 1456 | |
29639122 JB |
1457 | /* Normally we ignore extend instructions. However, if it is |
1458 | not followed by a valid prologue instruction, then this | |
1459 | instruction is not part of the prologue either. We must | |
1460 | remember in this case to adjust the end_prologue_addr back | |
1461 | over the extend. */ | |
1462 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
1463 | { | |
95ac2dcf | 1464 | extend_bytes = MIPS_INSN16_SIZE; |
29639122 JB |
1465 | continue; |
1466 | } | |
eec63939 | 1467 | |
29639122 JB |
1468 | prev_extend_bytes = extend_bytes; |
1469 | extend_bytes = 0; | |
eec63939 | 1470 | |
29639122 JB |
1471 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
1472 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1473 | { | |
1474 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
1475 | if (offset < 0) /* negative stack adjustment? */ | |
1476 | frame_offset -= offset; | |
1477 | else | |
1478 | /* Exit loop if a positive stack adjustment is found, which | |
1479 | usually means that the stack cleanup code in the function | |
1480 | epilogue is reached. */ | |
1481 | break; | |
1482 | } | |
1483 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
1484 | { | |
1485 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1486 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
1487 | set_reg_offset (this_cache, reg, sp + offset); | |
1488 | } | |
1489 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
1490 | { | |
1491 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1492 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1493 | set_reg_offset (this_cache, reg, sp + offset); | |
1494 | } | |
1495 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
1496 | { | |
1497 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
4c7d22cb | 1498 | set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1499 | } |
1500 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
1501 | { | |
1502 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
4c7d22cb | 1503 | set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1504 | } |
1505 | else if (inst == 0x673d) /* move $s1, $sp */ | |
1506 | { | |
1507 | frame_addr = sp; | |
1508 | frame_reg = 17; | |
1509 | } | |
1510 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
1511 | { | |
1512 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1513 | frame_addr = sp + offset; | |
1514 | frame_reg = 17; | |
1515 | frame_adjust = offset; | |
1516 | } | |
1517 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
1518 | { | |
1519 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
1520 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1521 | set_reg_offset (this_cache, reg, frame_addr + offset); | |
1522 | } | |
1523 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
1524 | { | |
1525 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1526 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1527 | set_reg_offset (this_cache, reg, frame_addr + offset); | |
1528 | } | |
1529 | else if ((inst & 0xf81f) == 0xe809 | |
1530 | && (inst & 0x700) != 0x700) /* entry */ | |
1531 | entry_inst = inst; /* save for later processing */ | |
1532 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ | |
95ac2dcf | 1533 | cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ |
29639122 JB |
1534 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
1535 | { | |
1536 | /* This instruction is part of the prologue, but we don't | |
1537 | need to do anything special to handle it. */ | |
1538 | } | |
1539 | else | |
1540 | { | |
1541 | /* This instruction is not an instruction typically found | |
1542 | in a prologue, so we must have reached the end of the | |
1543 | prologue. */ | |
1544 | if (end_prologue_addr == 0) | |
1545 | end_prologue_addr = cur_pc - prev_extend_bytes; | |
1546 | } | |
1547 | } | |
eec63939 | 1548 | |
29639122 JB |
1549 | /* The entry instruction is typically the first instruction in a function, |
1550 | and it stores registers at offsets relative to the value of the old SP | |
1551 | (before the prologue). But the value of the sp parameter to this | |
1552 | function is the new SP (after the prologue has been executed). So we | |
1553 | can't calculate those offsets until we've seen the entire prologue, | |
1554 | and can calculate what the old SP must have been. */ | |
1555 | if (entry_inst != 0) | |
1556 | { | |
1557 | int areg_count = (entry_inst >> 8) & 7; | |
1558 | int sreg_count = (entry_inst >> 6) & 3; | |
eec63939 | 1559 | |
29639122 JB |
1560 | /* The entry instruction always subtracts 32 from the SP. */ |
1561 | frame_offset += 32; | |
1562 | ||
1563 | /* Now we can calculate what the SP must have been at the | |
1564 | start of the function prologue. */ | |
1565 | sp += frame_offset; | |
1566 | ||
1567 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
1568 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
1569 | { | |
1570 | set_reg_offset (this_cache, reg, sp + offset); | |
1571 | offset += mips_abi_regsize (current_gdbarch); | |
1572 | } | |
1573 | ||
1574 | /* Check if the ra register was pushed on the stack. */ | |
1575 | offset = -4; | |
1576 | if (entry_inst & 0x20) | |
1577 | { | |
4c7d22cb | 1578 | set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1579 | offset -= mips_abi_regsize (current_gdbarch); |
1580 | } | |
1581 | ||
1582 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
1583 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1584 | { | |
1585 | set_reg_offset (this_cache, reg, sp + offset); | |
1586 | offset -= mips_abi_regsize (current_gdbarch); | |
1587 | } | |
1588 | } | |
1589 | ||
1590 | if (this_cache != NULL) | |
1591 | { | |
1592 | this_cache->base = | |
1593 | (frame_unwind_register_signed (next_frame, NUM_REGS + frame_reg) | |
1594 | + frame_offset - frame_adjust); | |
1595 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should | |
1596 | be able to get rid of the assignment below, evetually. But it's | |
1597 | still needed for now. */ | |
1598 | this_cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc] | |
4c7d22cb | 1599 | = this_cache->saved_regs[NUM_REGS + MIPS_RA_REGNUM]; |
29639122 JB |
1600 | } |
1601 | ||
1602 | /* If we didn't reach the end of the prologue when scanning the function | |
1603 | instructions, then set end_prologue_addr to the address of the | |
1604 | instruction immediately after the last one we scanned. */ | |
1605 | if (end_prologue_addr == 0) | |
1606 | end_prologue_addr = cur_pc; | |
1607 | ||
1608 | return end_prologue_addr; | |
eec63939 AC |
1609 | } |
1610 | ||
29639122 JB |
1611 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). |
1612 | Procedures that use the 32-bit instruction set are handled by the | |
1613 | mips_insn32 unwinder. */ | |
1614 | ||
1615 | static struct mips_frame_cache * | |
1616 | mips_insn16_frame_cache (struct frame_info *next_frame, void **this_cache) | |
eec63939 | 1617 | { |
29639122 | 1618 | struct mips_frame_cache *cache; |
eec63939 AC |
1619 | |
1620 | if ((*this_cache) != NULL) | |
1621 | return (*this_cache); | |
29639122 JB |
1622 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
1623 | (*this_cache) = cache; | |
1624 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
eec63939 | 1625 | |
29639122 JB |
1626 | /* Analyze the function prologue. */ |
1627 | { | |
1628 | const CORE_ADDR pc = frame_pc_unwind (next_frame); | |
1629 | CORE_ADDR start_addr; | |
eec63939 | 1630 | |
29639122 JB |
1631 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
1632 | if (start_addr == 0) | |
1633 | start_addr = heuristic_proc_start (pc); | |
1634 | /* We can't analyze the prologue if we couldn't find the begining | |
1635 | of the function. */ | |
1636 | if (start_addr == 0) | |
1637 | return cache; | |
eec63939 | 1638 | |
29639122 JB |
1639 | mips16_scan_prologue (start_addr, pc, next_frame, *this_cache); |
1640 | } | |
1641 | ||
1642 | /* SP_REGNUM, contains the value and not the address. */ | |
1643 | trad_frame_set_value (cache->saved_regs, NUM_REGS + MIPS_SP_REGNUM, cache->base); | |
eec63939 | 1644 | |
29639122 | 1645 | return (*this_cache); |
eec63939 AC |
1646 | } |
1647 | ||
1648 | static void | |
29639122 JB |
1649 | mips_insn16_frame_this_id (struct frame_info *next_frame, void **this_cache, |
1650 | struct frame_id *this_id) | |
eec63939 | 1651 | { |
29639122 JB |
1652 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
1653 | this_cache); | |
1654 | (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame)); | |
eec63939 AC |
1655 | } |
1656 | ||
1657 | static void | |
29639122 | 1658 | mips_insn16_frame_prev_register (struct frame_info *next_frame, |
eec63939 AC |
1659 | void **this_cache, |
1660 | int regnum, int *optimizedp, | |
1661 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
a8a0fc4c | 1662 | int *realnump, gdb_byte *valuep) |
eec63939 | 1663 | { |
29639122 JB |
1664 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
1665 | this_cache); | |
1666 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, | |
1667 | optimizedp, lvalp, addrp, realnump, valuep); | |
eec63939 AC |
1668 | } |
1669 | ||
29639122 | 1670 | static const struct frame_unwind mips_insn16_frame_unwind = |
eec63939 AC |
1671 | { |
1672 | NORMAL_FRAME, | |
29639122 JB |
1673 | mips_insn16_frame_this_id, |
1674 | mips_insn16_frame_prev_register | |
eec63939 AC |
1675 | }; |
1676 | ||
1677 | static const struct frame_unwind * | |
29639122 | 1678 | mips_insn16_frame_sniffer (struct frame_info *next_frame) |
eec63939 AC |
1679 | { |
1680 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
0fe7e7c8 | 1681 | if (mips_pc_is_mips16 (pc)) |
29639122 JB |
1682 | return &mips_insn16_frame_unwind; |
1683 | return NULL; | |
eec63939 AC |
1684 | } |
1685 | ||
1686 | static CORE_ADDR | |
29639122 JB |
1687 | mips_insn16_frame_base_address (struct frame_info *next_frame, |
1688 | void **this_cache) | |
eec63939 | 1689 | { |
29639122 JB |
1690 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
1691 | this_cache); | |
1692 | return info->base; | |
eec63939 AC |
1693 | } |
1694 | ||
29639122 | 1695 | static const struct frame_base mips_insn16_frame_base = |
eec63939 | 1696 | { |
29639122 JB |
1697 | &mips_insn16_frame_unwind, |
1698 | mips_insn16_frame_base_address, | |
1699 | mips_insn16_frame_base_address, | |
1700 | mips_insn16_frame_base_address | |
eec63939 AC |
1701 | }; |
1702 | ||
1703 | static const struct frame_base * | |
29639122 | 1704 | mips_insn16_frame_base_sniffer (struct frame_info *next_frame) |
eec63939 | 1705 | { |
29639122 JB |
1706 | if (mips_insn16_frame_sniffer (next_frame) != NULL) |
1707 | return &mips_insn16_frame_base; | |
eec63939 AC |
1708 | else |
1709 | return NULL; | |
edfae063 AC |
1710 | } |
1711 | ||
29639122 JB |
1712 | /* Mark all the registers as unset in the saved_regs array |
1713 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
1714 | ||
1715 | void | |
1716 | reset_saved_regs (struct mips_frame_cache *this_cache) | |
c906108c | 1717 | { |
29639122 JB |
1718 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
1719 | return; | |
1720 | ||
1721 | { | |
1722 | const int num_regs = NUM_REGS; | |
1723 | int i; | |
64159455 | 1724 | |
29639122 JB |
1725 | for (i = 0; i < num_regs; i++) |
1726 | { | |
1727 | this_cache->saved_regs[i].addr = -1; | |
1728 | } | |
1729 | } | |
c906108c SS |
1730 | } |
1731 | ||
29639122 JB |
1732 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1733 | the associated FRAME_CACHE if not null. | |
1734 | Return the address of the first instruction past the prologue. */ | |
c906108c | 1735 | |
875e1767 | 1736 | static CORE_ADDR |
29639122 JB |
1737 | mips32_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
1738 | struct frame_info *next_frame, | |
1739 | struct mips_frame_cache *this_cache) | |
c906108c | 1740 | { |
29639122 JB |
1741 | CORE_ADDR cur_pc; |
1742 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ | |
1743 | CORE_ADDR sp; | |
1744 | long frame_offset; | |
1745 | int frame_reg = MIPS_SP_REGNUM; | |
8fa9cfa1 | 1746 | |
29639122 JB |
1747 | CORE_ADDR end_prologue_addr = 0; |
1748 | int seen_sp_adjust = 0; | |
1749 | int load_immediate_bytes = 0; | |
8fa9cfa1 | 1750 | |
29639122 JB |
1751 | /* Can be called when there's no process, and hence when there's no |
1752 | NEXT_FRAME. */ | |
1753 | if (next_frame != NULL) | |
1754 | sp = read_next_frame_reg (next_frame, NUM_REGS + MIPS_SP_REGNUM); | |
8fa9cfa1 | 1755 | else |
29639122 | 1756 | sp = 0; |
9022177c | 1757 | |
29639122 JB |
1758 | if (limit_pc > start_pc + 200) |
1759 | limit_pc = start_pc + 200; | |
9022177c | 1760 | |
29639122 | 1761 | restart: |
9022177c | 1762 | |
29639122 | 1763 | frame_offset = 0; |
95ac2dcf | 1764 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) |
9022177c | 1765 | { |
29639122 JB |
1766 | unsigned long inst, high_word, low_word; |
1767 | int reg; | |
9022177c | 1768 | |
29639122 JB |
1769 | /* Fetch the instruction. */ |
1770 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
9022177c | 1771 | |
29639122 JB |
1772 | /* Save some code by pre-extracting some useful fields. */ |
1773 | high_word = (inst >> 16) & 0xffff; | |
1774 | low_word = inst & 0xffff; | |
1775 | reg = high_word & 0x1f; | |
fe29b929 | 1776 | |
29639122 JB |
1777 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
1778 | || high_word == 0x23bd /* addi $sp,$sp,-i */ | |
1779 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
1780 | { | |
1781 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
1782 | frame_offset += 0x10000 - low_word; | |
1783 | else | |
1784 | /* Exit loop if a positive stack adjustment is found, which | |
1785 | usually means that the stack cleanup code in the function | |
1786 | epilogue is reached. */ | |
1787 | break; | |
1788 | seen_sp_adjust = 1; | |
1789 | } | |
1790 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
1791 | { | |
1792 | set_reg_offset (this_cache, reg, sp + low_word); | |
1793 | } | |
1794 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
1795 | { | |
1796 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ | |
1797 | set_reg_offset (this_cache, reg, sp + low_word); | |
1798 | } | |
1799 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
1800 | { | |
1801 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
1802 | if ((long) low_word != frame_offset) | |
1803 | frame_addr = sp + low_word; | |
1804 | else if (frame_reg == MIPS_SP_REGNUM) | |
1805 | { | |
1806 | unsigned alloca_adjust; | |
a4b8ebc8 | 1807 | |
29639122 JB |
1808 | frame_reg = 30; |
1809 | frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); | |
1810 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); | |
1811 | if (alloca_adjust > 0) | |
1812 | { | |
1813 | /* FP > SP + frame_size. This may be because of | |
1814 | an alloca or somethings similar. Fix sp to | |
1815 | "pre-alloca" value, and try again. */ | |
1816 | sp += alloca_adjust; | |
1817 | /* Need to reset the status of all registers. Otherwise, | |
1818 | we will hit a guard that prevents the new address | |
1819 | for each register to be recomputed during the second | |
1820 | pass. */ | |
1821 | reset_saved_regs (this_cache); | |
1822 | goto restart; | |
1823 | } | |
1824 | } | |
1825 | } | |
1826 | /* move $30,$sp. With different versions of gas this will be either | |
1827 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
1828 | Accept any one of these. */ | |
1829 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
1830 | { | |
1831 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
1832 | if (frame_reg == MIPS_SP_REGNUM) | |
1833 | { | |
1834 | unsigned alloca_adjust; | |
c906108c | 1835 | |
29639122 JB |
1836 | frame_reg = 30; |
1837 | frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); | |
1838 | alloca_adjust = (unsigned) (frame_addr - sp); | |
1839 | if (alloca_adjust > 0) | |
1840 | { | |
1841 | /* FP > SP + frame_size. This may be because of | |
1842 | an alloca or somethings similar. Fix sp to | |
1843 | "pre-alloca" value, and try again. */ | |
1844 | sp = frame_addr; | |
1845 | /* Need to reset the status of all registers. Otherwise, | |
1846 | we will hit a guard that prevents the new address | |
1847 | for each register to be recomputed during the second | |
1848 | pass. */ | |
1849 | reset_saved_regs (this_cache); | |
1850 | goto restart; | |
1851 | } | |
1852 | } | |
1853 | } | |
1854 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ | |
1855 | { | |
1856 | set_reg_offset (this_cache, reg, frame_addr + low_word); | |
1857 | } | |
1858 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | |
1859 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ | |
1860 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | |
1861 | || high_word == 0x3c1c /* lui $gp,n */ | |
1862 | || high_word == 0x279c /* addiu $gp,$gp,n */ | |
1863 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
1864 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | |
1865 | ) | |
1866 | { | |
1867 | /* These instructions are part of the prologue, but we don't | |
1868 | need to do anything special to handle them. */ | |
1869 | } | |
1870 | /* The instructions below load $at or $t0 with an immediate | |
1871 | value in preparation for a stack adjustment via | |
1872 | subu $sp,$sp,[$at,$t0]. These instructions could also | |
1873 | initialize a local variable, so we accept them only before | |
1874 | a stack adjustment instruction was seen. */ | |
1875 | else if (!seen_sp_adjust | |
1876 | && (high_word == 0x3c01 /* lui $at,n */ | |
1877 | || high_word == 0x3c08 /* lui $t0,n */ | |
1878 | || high_word == 0x3421 /* ori $at,$at,n */ | |
1879 | || high_word == 0x3508 /* ori $t0,$t0,n */ | |
1880 | || high_word == 0x3401 /* ori $at,$zero,n */ | |
1881 | || high_word == 0x3408 /* ori $t0,$zero,n */ | |
1882 | )) | |
1883 | { | |
95ac2dcf | 1884 | load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ |
29639122 JB |
1885 | } |
1886 | else | |
1887 | { | |
1888 | /* This instruction is not an instruction typically found | |
1889 | in a prologue, so we must have reached the end of the | |
1890 | prologue. */ | |
1891 | /* FIXME: brobecker/2004-10-10: Can't we just break out of this | |
1892 | loop now? Why would we need to continue scanning the function | |
1893 | instructions? */ | |
1894 | if (end_prologue_addr == 0) | |
1895 | end_prologue_addr = cur_pc; | |
1896 | } | |
a4b8ebc8 | 1897 | } |
c906108c | 1898 | |
29639122 JB |
1899 | if (this_cache != NULL) |
1900 | { | |
1901 | this_cache->base = | |
1902 | (frame_unwind_register_signed (next_frame, NUM_REGS + frame_reg) | |
1903 | + frame_offset); | |
1904 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of | |
1905 | this assignment below, eventually. But it's still needed | |
1906 | for now. */ | |
1907 | this_cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc] | |
4c7d22cb | 1908 | = this_cache->saved_regs[NUM_REGS + MIPS_RA_REGNUM]; |
29639122 | 1909 | } |
c906108c | 1910 | |
29639122 JB |
1911 | /* If we didn't reach the end of the prologue when scanning the function |
1912 | instructions, then set end_prologue_addr to the address of the | |
1913 | instruction immediately after the last one we scanned. */ | |
1914 | /* brobecker/2004-10-10: I don't think this would ever happen, but | |
1915 | we may as well be careful and do our best if we have a null | |
1916 | end_prologue_addr. */ | |
1917 | if (end_prologue_addr == 0) | |
1918 | end_prologue_addr = cur_pc; | |
1919 | ||
1920 | /* In a frameless function, we might have incorrectly | |
1921 | skipped some load immediate instructions. Undo the skipping | |
1922 | if the load immediate was not followed by a stack adjustment. */ | |
1923 | if (load_immediate_bytes && !seen_sp_adjust) | |
1924 | end_prologue_addr -= load_immediate_bytes; | |
c906108c | 1925 | |
29639122 | 1926 | return end_prologue_addr; |
c906108c SS |
1927 | } |
1928 | ||
29639122 JB |
1929 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
1930 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
1931 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
1932 | unwinder. */ | |
c906108c | 1933 | |
29639122 JB |
1934 | static struct mips_frame_cache * |
1935 | mips_insn32_frame_cache (struct frame_info *next_frame, void **this_cache) | |
c906108c | 1936 | { |
29639122 | 1937 | struct mips_frame_cache *cache; |
c906108c | 1938 | |
29639122 JB |
1939 | if ((*this_cache) != NULL) |
1940 | return (*this_cache); | |
c5aa993b | 1941 | |
29639122 JB |
1942 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
1943 | (*this_cache) = cache; | |
1944 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
c5aa993b | 1945 | |
29639122 JB |
1946 | /* Analyze the function prologue. */ |
1947 | { | |
1948 | const CORE_ADDR pc = frame_pc_unwind (next_frame); | |
1949 | CORE_ADDR start_addr; | |
c906108c | 1950 | |
29639122 JB |
1951 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
1952 | if (start_addr == 0) | |
1953 | start_addr = heuristic_proc_start (pc); | |
1954 | /* We can't analyze the prologue if we couldn't find the begining | |
1955 | of the function. */ | |
1956 | if (start_addr == 0) | |
1957 | return cache; | |
c5aa993b | 1958 | |
29639122 JB |
1959 | mips32_scan_prologue (start_addr, pc, next_frame, *this_cache); |
1960 | } | |
1961 | ||
1962 | /* SP_REGNUM, contains the value and not the address. */ | |
1963 | trad_frame_set_value (cache->saved_regs, NUM_REGS + MIPS_SP_REGNUM, cache->base); | |
c5aa993b | 1964 | |
29639122 | 1965 | return (*this_cache); |
c906108c SS |
1966 | } |
1967 | ||
29639122 JB |
1968 | static void |
1969 | mips_insn32_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
1970 | struct frame_id *this_id) | |
c906108c | 1971 | { |
29639122 JB |
1972 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, |
1973 | this_cache); | |
1974 | (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame)); | |
1975 | } | |
c906108c | 1976 | |
29639122 JB |
1977 | static void |
1978 | mips_insn32_frame_prev_register (struct frame_info *next_frame, | |
1979 | void **this_cache, | |
1980 | int regnum, int *optimizedp, | |
1981 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
a8a0fc4c | 1982 | int *realnump, gdb_byte *valuep) |
29639122 JB |
1983 | { |
1984 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, | |
1985 | this_cache); | |
1986 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, | |
1987 | optimizedp, lvalp, addrp, realnump, valuep); | |
c906108c SS |
1988 | } |
1989 | ||
29639122 JB |
1990 | static const struct frame_unwind mips_insn32_frame_unwind = |
1991 | { | |
1992 | NORMAL_FRAME, | |
1993 | mips_insn32_frame_this_id, | |
1994 | mips_insn32_frame_prev_register | |
1995 | }; | |
c906108c | 1996 | |
29639122 JB |
1997 | static const struct frame_unwind * |
1998 | mips_insn32_frame_sniffer (struct frame_info *next_frame) | |
1999 | { | |
2000 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
0fe7e7c8 | 2001 | if (! mips_pc_is_mips16 (pc)) |
29639122 JB |
2002 | return &mips_insn32_frame_unwind; |
2003 | return NULL; | |
2004 | } | |
c906108c | 2005 | |
1c645fec | 2006 | static CORE_ADDR |
29639122 JB |
2007 | mips_insn32_frame_base_address (struct frame_info *next_frame, |
2008 | void **this_cache) | |
c906108c | 2009 | { |
29639122 JB |
2010 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, |
2011 | this_cache); | |
2012 | return info->base; | |
2013 | } | |
c906108c | 2014 | |
29639122 JB |
2015 | static const struct frame_base mips_insn32_frame_base = |
2016 | { | |
2017 | &mips_insn32_frame_unwind, | |
2018 | mips_insn32_frame_base_address, | |
2019 | mips_insn32_frame_base_address, | |
2020 | mips_insn32_frame_base_address | |
2021 | }; | |
1c645fec | 2022 | |
29639122 JB |
2023 | static const struct frame_base * |
2024 | mips_insn32_frame_base_sniffer (struct frame_info *next_frame) | |
2025 | { | |
2026 | if (mips_insn32_frame_sniffer (next_frame) != NULL) | |
2027 | return &mips_insn32_frame_base; | |
a65bbe44 | 2028 | else |
29639122 JB |
2029 | return NULL; |
2030 | } | |
a65bbe44 | 2031 | |
29639122 JB |
2032 | static struct trad_frame_cache * |
2033 | mips_stub_frame_cache (struct frame_info *next_frame, void **this_cache) | |
2034 | { | |
2035 | CORE_ADDR pc; | |
2036 | CORE_ADDR start_addr; | |
2037 | CORE_ADDR stack_addr; | |
2038 | struct trad_frame_cache *this_trad_cache; | |
c906108c | 2039 | |
29639122 JB |
2040 | if ((*this_cache) != NULL) |
2041 | return (*this_cache); | |
2042 | this_trad_cache = trad_frame_cache_zalloc (next_frame); | |
2043 | (*this_cache) = this_trad_cache; | |
1c645fec | 2044 | |
29639122 | 2045 | /* The return address is in the link register. */ |
4c7d22cb | 2046 | trad_frame_set_reg_realreg (this_trad_cache, PC_REGNUM, MIPS_RA_REGNUM); |
1c645fec | 2047 | |
29639122 JB |
2048 | /* Frame ID, since it's a frameless / stackless function, no stack |
2049 | space is allocated and SP on entry is the current SP. */ | |
2050 | pc = frame_pc_unwind (next_frame); | |
2051 | find_pc_partial_function (pc, NULL, &start_addr, NULL); | |
4c7d22cb | 2052 | stack_addr = frame_unwind_register_signed (next_frame, MIPS_SP_REGNUM); |
29639122 | 2053 | trad_frame_set_id (this_trad_cache, frame_id_build (start_addr, stack_addr)); |
1c645fec | 2054 | |
29639122 JB |
2055 | /* Assume that the frame's base is the same as the |
2056 | stack-pointer. */ | |
2057 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
c906108c | 2058 | |
29639122 JB |
2059 | return this_trad_cache; |
2060 | } | |
c906108c | 2061 | |
29639122 JB |
2062 | static void |
2063 | mips_stub_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
2064 | struct frame_id *this_id) | |
2065 | { | |
2066 | struct trad_frame_cache *this_trad_cache | |
2067 | = mips_stub_frame_cache (next_frame, this_cache); | |
2068 | trad_frame_get_id (this_trad_cache, this_id); | |
2069 | } | |
c906108c | 2070 | |
29639122 JB |
2071 | static void |
2072 | mips_stub_frame_prev_register (struct frame_info *next_frame, | |
2073 | void **this_cache, | |
2074 | int regnum, int *optimizedp, | |
2075 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
a8a0fc4c | 2076 | int *realnump, gdb_byte *valuep) |
29639122 JB |
2077 | { |
2078 | struct trad_frame_cache *this_trad_cache | |
2079 | = mips_stub_frame_cache (next_frame, this_cache); | |
2080 | trad_frame_get_register (this_trad_cache, next_frame, regnum, optimizedp, | |
2081 | lvalp, addrp, realnump, valuep); | |
2082 | } | |
c906108c | 2083 | |
29639122 JB |
2084 | static const struct frame_unwind mips_stub_frame_unwind = |
2085 | { | |
2086 | NORMAL_FRAME, | |
2087 | mips_stub_frame_this_id, | |
2088 | mips_stub_frame_prev_register | |
2089 | }; | |
c906108c | 2090 | |
29639122 JB |
2091 | static const struct frame_unwind * |
2092 | mips_stub_frame_sniffer (struct frame_info *next_frame) | |
2093 | { | |
979b38e0 | 2094 | struct obj_section *s; |
29639122 | 2095 | CORE_ADDR pc = frame_pc_unwind (next_frame); |
979b38e0 | 2096 | |
29639122 JB |
2097 | if (in_plt_section (pc, NULL)) |
2098 | return &mips_stub_frame_unwind; | |
979b38e0 DJ |
2099 | |
2100 | /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */ | |
2101 | s = find_pc_section (pc); | |
2102 | ||
2103 | if (s != NULL | |
2104 | && strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section), | |
2105 | ".MIPS.stubs") == 0) | |
2106 | return &mips_stub_frame_unwind; | |
2107 | ||
2108 | return NULL; | |
29639122 | 2109 | } |
c906108c | 2110 | |
29639122 JB |
2111 | static CORE_ADDR |
2112 | mips_stub_frame_base_address (struct frame_info *next_frame, | |
2113 | void **this_cache) | |
2114 | { | |
2115 | struct trad_frame_cache *this_trad_cache | |
2116 | = mips_stub_frame_cache (next_frame, this_cache); | |
2117 | return trad_frame_get_this_base (this_trad_cache); | |
2118 | } | |
0fce0821 | 2119 | |
29639122 JB |
2120 | static const struct frame_base mips_stub_frame_base = |
2121 | { | |
2122 | &mips_stub_frame_unwind, | |
2123 | mips_stub_frame_base_address, | |
2124 | mips_stub_frame_base_address, | |
2125 | mips_stub_frame_base_address | |
2126 | }; | |
2127 | ||
2128 | static const struct frame_base * | |
2129 | mips_stub_frame_base_sniffer (struct frame_info *next_frame) | |
2130 | { | |
2131 | if (mips_stub_frame_sniffer (next_frame) != NULL) | |
2132 | return &mips_stub_frame_base; | |
2133 | else | |
2134 | return NULL; | |
2135 | } | |
2136 | ||
2137 | static CORE_ADDR | |
2138 | read_next_frame_reg (struct frame_info *fi, int regno) | |
2139 | { | |
2140 | /* Always a pseudo. */ | |
2141 | gdb_assert (regno >= NUM_REGS); | |
2142 | if (fi == NULL) | |
0fce0821 | 2143 | { |
29639122 JB |
2144 | LONGEST val; |
2145 | regcache_cooked_read_signed (current_regcache, regno, &val); | |
2146 | return val; | |
0fce0821 | 2147 | } |
29639122 JB |
2148 | else |
2149 | return frame_unwind_register_signed (fi, regno); | |
1c645fec | 2150 | |
c906108c SS |
2151 | } |
2152 | ||
29639122 | 2153 | /* mips_addr_bits_remove - remove useless address bits */ |
65596487 | 2154 | |
29639122 JB |
2155 | static CORE_ADDR |
2156 | mips_addr_bits_remove (CORE_ADDR addr) | |
65596487 | 2157 | { |
29639122 JB |
2158 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2159 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) | |
2160 | /* This hack is a work-around for existing boards using PMON, the | |
2161 | simulator, and any other 64-bit targets that doesn't have true | |
2162 | 64-bit addressing. On these targets, the upper 32 bits of | |
2163 | addresses are ignored by the hardware. Thus, the PC or SP are | |
2164 | likely to have been sign extended to all 1s by instruction | |
2165 | sequences that load 32-bit addresses. For example, a typical | |
2166 | piece of code that loads an address is this: | |
65596487 | 2167 | |
29639122 JB |
2168 | lui $r2, <upper 16 bits> |
2169 | ori $r2, <lower 16 bits> | |
65596487 | 2170 | |
29639122 JB |
2171 | But the lui sign-extends the value such that the upper 32 bits |
2172 | may be all 1s. The workaround is simply to mask off these | |
2173 | bits. In the future, gcc may be changed to support true 64-bit | |
2174 | addressing, and this masking will have to be disabled. */ | |
2175 | return addr &= 0xffffffffUL; | |
2176 | else | |
2177 | return addr; | |
65596487 JB |
2178 | } |
2179 | ||
29639122 JB |
2180 | /* mips_software_single_step() is called just before we want to resume |
2181 | the inferior, if we want to single-step it but there is no hardware | |
2182 | or kernel single-step support (MIPS on GNU/Linux for example). We find | |
2183 | the target of the coming instruction and breakpoint it. | |
1e05a7bf | 2184 | |
29639122 JB |
2185 | single_step is also called just after the inferior stops. If we had |
2186 | set up a simulated single-step, we undo our damage. */ | |
2187 | ||
2188 | void | |
2189 | mips_software_single_step (enum target_signal sig, int insert_breakpoints_p) | |
c906108c | 2190 | { |
29639122 JB |
2191 | static CORE_ADDR next_pc; |
2192 | typedef char binsn_quantum[BREAKPOINT_MAX]; | |
2193 | static binsn_quantum break_mem; | |
2194 | CORE_ADDR pc; | |
65596487 | 2195 | |
29639122 JB |
2196 | if (insert_breakpoints_p) |
2197 | { | |
2198 | pc = read_register (mips_regnum (current_gdbarch)->pc); | |
2199 | next_pc = mips_next_pc (pc); | |
98b4dd94 | 2200 | |
29639122 JB |
2201 | target_insert_breakpoint (next_pc, break_mem); |
2202 | } | |
a65bbe44 | 2203 | else |
29639122 JB |
2204 | target_remove_breakpoint (next_pc, break_mem); |
2205 | } | |
a65bbe44 | 2206 | |
29639122 JB |
2207 | /* Test whether the PC points to the return instruction at the |
2208 | end of a function. */ | |
65596487 | 2209 | |
29639122 JB |
2210 | static int |
2211 | mips_about_to_return (CORE_ADDR pc) | |
2212 | { | |
0fe7e7c8 | 2213 | if (mips_pc_is_mips16 (pc)) |
29639122 JB |
2214 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler |
2215 | generates a "jr $ra"; other times it generates code to load | |
2216 | the return address from the stack to an accessible register (such | |
2217 | as $a3), then a "jr" using that register. This second case | |
2218 | is almost impossible to distinguish from an indirect jump | |
2219 | used for switch statements, so we don't even try. */ | |
2220 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
2221 | else | |
2222 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
2223 | } | |
c906108c | 2224 | |
c906108c | 2225 | |
29639122 JB |
2226 | /* This fencepost looks highly suspicious to me. Removing it also |
2227 | seems suspicious as it could affect remote debugging across serial | |
2228 | lines. */ | |
c906108c | 2229 | |
29639122 JB |
2230 | static CORE_ADDR |
2231 | heuristic_proc_start (CORE_ADDR pc) | |
2232 | { | |
2233 | CORE_ADDR start_pc; | |
2234 | CORE_ADDR fence; | |
2235 | int instlen; | |
2236 | int seen_adjsp = 0; | |
65596487 | 2237 | |
29639122 JB |
2238 | pc = ADDR_BITS_REMOVE (pc); |
2239 | start_pc = pc; | |
2240 | fence = start_pc - heuristic_fence_post; | |
2241 | if (start_pc == 0) | |
2242 | return 0; | |
65596487 | 2243 | |
29639122 JB |
2244 | if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
2245 | fence = VM_MIN_ADDRESS; | |
65596487 | 2246 | |
95ac2dcf | 2247 | instlen = mips_pc_is_mips16 (pc) ? MIPS_INSN16_SIZE : MIPS_INSN32_SIZE; |
98b4dd94 | 2248 | |
29639122 JB |
2249 | /* search back for previous return */ |
2250 | for (start_pc -= instlen;; start_pc -= instlen) | |
2251 | if (start_pc < fence) | |
2252 | { | |
2253 | /* It's not clear to me why we reach this point when | |
2254 | stop_soon, but with this test, at least we | |
2255 | don't print out warnings for every child forked (eg, on | |
2256 | decstation). 22apr93 rich@cygnus.com. */ | |
2257 | if (stop_soon == NO_STOP_QUIETLY) | |
2258 | { | |
2259 | static int blurb_printed = 0; | |
98b4dd94 | 2260 | |
8a3fe4f8 | 2261 | warning (_("GDB can't find the start of the function at 0x%s."), |
29639122 JB |
2262 | paddr_nz (pc)); |
2263 | ||
2264 | if (!blurb_printed) | |
2265 | { | |
2266 | /* This actually happens frequently in embedded | |
2267 | development, when you first connect to a board | |
2268 | and your stack pointer and pc are nowhere in | |
2269 | particular. This message needs to give people | |
2270 | in that situation enough information to | |
2271 | determine that it's no big deal. */ | |
2272 | printf_filtered ("\n\ | |
2273 | GDB is unable to find the start of the function at 0x%s\n\ | |
2274 | and thus can't determine the size of that function's stack frame.\n\ | |
2275 | This means that GDB may be unable to access that stack frame, or\n\ | |
2276 | the frames below it.\n\ | |
2277 | This problem is most likely caused by an invalid program counter or\n\ | |
2278 | stack pointer.\n\ | |
2279 | However, if you think GDB should simply search farther back\n\ | |
2280 | from 0x%s for code which looks like the beginning of a\n\ | |
2281 | function, you can increase the range of the search using the `set\n\ | |
2282 | heuristic-fence-post' command.\n", paddr_nz (pc), paddr_nz (pc)); | |
2283 | blurb_printed = 1; | |
2284 | } | |
2285 | } | |
2286 | ||
2287 | return 0; | |
2288 | } | |
0fe7e7c8 | 2289 | else if (mips_pc_is_mips16 (start_pc)) |
29639122 JB |
2290 | { |
2291 | unsigned short inst; | |
2292 | ||
2293 | /* On MIPS16, any one of the following is likely to be the | |
2294 | start of a function: | |
2295 | entry | |
2296 | addiu sp,-n | |
2297 | daddiu sp,-n | |
2298 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
2299 | inst = mips_fetch_instruction (start_pc); | |
2300 | if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
2301 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
2302 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
2303 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
2304 | break; | |
2305 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
2306 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2307 | seen_adjsp = 1; | |
2308 | else | |
2309 | seen_adjsp = 0; | |
2310 | } | |
2311 | else if (mips_about_to_return (start_pc)) | |
2312 | { | |
4c7d22cb | 2313 | /* Skip return and its delay slot. */ |
95ac2dcf | 2314 | start_pc += 2 * MIPS_INSN32_SIZE; |
29639122 JB |
2315 | break; |
2316 | } | |
2317 | ||
2318 | return start_pc; | |
c906108c SS |
2319 | } |
2320 | ||
6c0d6680 DJ |
2321 | struct mips_objfile_private |
2322 | { | |
2323 | bfd_size_type size; | |
2324 | char *contents; | |
2325 | }; | |
2326 | ||
f09ded24 AC |
2327 | /* According to the current ABI, should the type be passed in a |
2328 | floating-point register (assuming that there is space)? When there | |
2329 | is no FPU, FP are not even considered as possibile candidates for | |
2330 | FP registers and, consequently this returns false - forces FP | |
2331 | arguments into integer registers. */ | |
2332 | ||
2333 | static int | |
2334 | fp_register_arg_p (enum type_code typecode, struct type *arg_type) | |
2335 | { | |
2336 | return ((typecode == TYPE_CODE_FLT | |
2337 | || (MIPS_EABI | |
6d82d43b AC |
2338 | && (typecode == TYPE_CODE_STRUCT |
2339 | || typecode == TYPE_CODE_UNION) | |
f09ded24 AC |
2340 | && TYPE_NFIELDS (arg_type) == 1 |
2341 | && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT)) | |
c86b5b38 | 2342 | && MIPS_FPU_TYPE != MIPS_FPU_NONE); |
f09ded24 AC |
2343 | } |
2344 | ||
49e790b0 DJ |
2345 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
2346 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
2347 | ||
2348 | static int | |
2349 | mips_type_needs_double_align (struct type *type) | |
2350 | { | |
2351 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2352 | |
49e790b0 DJ |
2353 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2354 | return 1; | |
2355 | else if (typecode == TYPE_CODE_STRUCT) | |
2356 | { | |
2357 | if (TYPE_NFIELDS (type) < 1) | |
2358 | return 0; | |
2359 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2360 | } | |
2361 | else if (typecode == TYPE_CODE_UNION) | |
2362 | { | |
361d1df0 | 2363 | int i, n; |
49e790b0 DJ |
2364 | |
2365 | n = TYPE_NFIELDS (type); | |
2366 | for (i = 0; i < n; i++) | |
2367 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2368 | return 1; | |
2369 | return 0; | |
2370 | } | |
2371 | return 0; | |
2372 | } | |
2373 | ||
dc604539 AC |
2374 | /* Adjust the address downward (direction of stack growth) so that it |
2375 | is correctly aligned for a new stack frame. */ | |
2376 | static CORE_ADDR | |
2377 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2378 | { | |
5b03f266 | 2379 | return align_down (addr, 16); |
dc604539 AC |
2380 | } |
2381 | ||
f7ab6ec6 | 2382 | static CORE_ADDR |
7d9b040b | 2383 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
2384 | struct regcache *regcache, CORE_ADDR bp_addr, |
2385 | int nargs, struct value **args, CORE_ADDR sp, | |
2386 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
2387 | { |
2388 | int argreg; | |
2389 | int float_argreg; | |
2390 | int argnum; | |
2391 | int len = 0; | |
2392 | int stack_offset = 0; | |
480d3dd2 | 2393 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 2394 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
c906108c | 2395 | |
25ab4790 AC |
2396 | /* For shared libraries, "t9" needs to point at the function |
2397 | address. */ | |
4c7d22cb | 2398 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
2399 | |
2400 | /* Set the return address register to point to the entry point of | |
2401 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 2402 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 2403 | |
c906108c | 2404 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2405 | are properly aligned. The stack has to be at least 64-bit |
2406 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2407 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2408 | aligned, so we round to this widest known alignment. */ | |
2409 | ||
5b03f266 AC |
2410 | sp = align_down (sp, 16); |
2411 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 2412 | |
46e0f506 | 2413 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2414 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2415 | passed in registers, but that's OK. */ |
c906108c | 2416 | for (argnum = 0; argnum < nargs; argnum++) |
4991999e | 2417 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), |
13326b4e | 2418 | mips_stack_argsize (gdbarch)); |
5b03f266 | 2419 | sp -= align_up (len, 16); |
c906108c | 2420 | |
9ace0497 | 2421 | if (mips_debug) |
6d82d43b | 2422 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
2423 | "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n", |
2424 | paddr_nz (sp), (long) align_up (len, 16)); | |
9ace0497 | 2425 | |
c906108c | 2426 | /* Initialize the integer and float register pointers. */ |
4c7d22cb | 2427 | argreg = MIPS_A0_REGNUM; |
56cea623 | 2428 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
c906108c | 2429 | |
46e0f506 | 2430 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2431 | if (struct_return) |
9ace0497 AC |
2432 | { |
2433 | if (mips_debug) | |
2434 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2435 | "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 2436 | argreg, paddr_nz (struct_addr)); |
9ace0497 AC |
2437 | write_register (argreg++, struct_addr); |
2438 | } | |
c906108c SS |
2439 | |
2440 | /* Now load as many as possible of the first arguments into | |
2441 | registers, and push the rest onto the stack. Loop thru args | |
2442 | from first to last. */ | |
2443 | for (argnum = 0; argnum < nargs; argnum++) | |
2444 | { | |
47a35522 MK |
2445 | const gdb_byte *val; |
2446 | gdb_byte valbuf[MAX_REGISTER_SIZE]; | |
ea7c478f | 2447 | struct value *arg = args[argnum]; |
4991999e | 2448 | struct type *arg_type = check_typedef (value_type (arg)); |
c906108c SS |
2449 | int len = TYPE_LENGTH (arg_type); |
2450 | enum type_code typecode = TYPE_CODE (arg_type); | |
2451 | ||
9ace0497 AC |
2452 | if (mips_debug) |
2453 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2454 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 2455 | argnum + 1, len, (int) typecode); |
9ace0497 | 2456 | |
c906108c | 2457 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 2458 | reference. */ |
13326b4e | 2459 | if (len > mips_abi_regsize (gdbarch) |
9ace0497 | 2460 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 2461 | { |
13326b4e | 2462 | store_unsigned_integer (valbuf, mips_abi_regsize (gdbarch), |
480d3dd2 | 2463 | VALUE_ADDRESS (arg)); |
c906108c | 2464 | typecode = TYPE_CODE_PTR; |
13326b4e | 2465 | len = mips_abi_regsize (gdbarch); |
c906108c | 2466 | val = valbuf; |
9ace0497 AC |
2467 | if (mips_debug) |
2468 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
2469 | } |
2470 | else | |
47a35522 | 2471 | val = value_contents (arg); |
c906108c SS |
2472 | |
2473 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
2474 | even-numbered floating point register. Round the FP register |
2475 | up before the check to see if there are any FP registers | |
46e0f506 MS |
2476 | left. Non MIPS_EABI targets also pass the FP in the integer |
2477 | registers so also round up normal registers. */ | |
ceae6e75 AC |
2478 | if (mips_abi_regsize (gdbarch) < 8 |
2479 | && fp_register_arg_p (typecode, arg_type)) | |
acdb74a0 AC |
2480 | { |
2481 | if ((float_argreg & 1)) | |
2482 | float_argreg++; | |
2483 | } | |
c906108c SS |
2484 | |
2485 | /* Floating point arguments passed in registers have to be | |
2486 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2487 | are passed in register pairs; the even register gets |
2488 | the low word, and the odd register gets the high word. | |
2489 | On non-EABI processors, the first two floating point arguments are | |
2490 | also copied to general registers, because MIPS16 functions | |
2491 | don't use float registers for arguments. This duplication of | |
2492 | arguments in general registers can't hurt non-MIPS16 functions | |
2493 | because those registers are normally skipped. */ | |
1012bd0e EZ |
2494 | /* MIPS_EABI squeezes a struct that contains a single floating |
2495 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 2496 | stack. */ |
f09ded24 AC |
2497 | if (fp_register_arg_p (typecode, arg_type) |
2498 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
c906108c | 2499 | { |
ceae6e75 | 2500 | if (mips_abi_regsize (gdbarch) < 8 && len == 8) |
c906108c | 2501 | { |
d7449b42 | 2502 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
c906108c SS |
2503 | unsigned long regval; |
2504 | ||
2505 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 2506 | regval = extract_unsigned_integer (val + low_offset, 4); |
9ace0497 | 2507 | if (mips_debug) |
acdb74a0 | 2508 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2509 | float_argreg, phex (regval, 4)); |
c906108c | 2510 | write_register (float_argreg++, regval); |
c906108c SS |
2511 | |
2512 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 2513 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
9ace0497 | 2514 | if (mips_debug) |
acdb74a0 | 2515 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2516 | float_argreg, phex (regval, 4)); |
c906108c | 2517 | write_register (float_argreg++, regval); |
c906108c SS |
2518 | } |
2519 | else | |
2520 | { | |
2521 | /* This is a floating point value that fits entirely | |
2522 | in a single register. */ | |
53a5351d | 2523 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 2524 | above to ensure that it is even register aligned. */ |
9ace0497 AC |
2525 | LONGEST regval = extract_unsigned_integer (val, len); |
2526 | if (mips_debug) | |
acdb74a0 | 2527 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2528 | float_argreg, phex (regval, len)); |
c906108c | 2529 | write_register (float_argreg++, regval); |
c906108c SS |
2530 | } |
2531 | } | |
2532 | else | |
2533 | { | |
2534 | /* Copy the argument to general registers or the stack in | |
2535 | register-sized pieces. Large arguments are split between | |
2536 | registers and stack. */ | |
4246e332 | 2537 | /* Note: structs whose size is not a multiple of |
d5ac5a39 AC |
2538 | mips_abi_regsize() are treated specially: Irix cc passes |
2539 | them in registers where gcc sometimes puts them on the | |
2540 | stack. For maximum compatibility, we will put them in | |
2541 | both places. */ | |
13326b4e AC |
2542 | int odd_sized_struct = ((len > mips_abi_regsize (gdbarch)) |
2543 | && (len % mips_abi_regsize (gdbarch) != 0)); | |
46e0f506 | 2544 | |
f09ded24 | 2545 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 2546 | register are only written to memory. */ |
c906108c SS |
2547 | while (len > 0) |
2548 | { | |
ebafbe83 | 2549 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 2550 | int stack_used_p = 0; |
13326b4e AC |
2551 | int partial_len = (len < mips_abi_regsize (gdbarch) |
2552 | ? len : mips_abi_regsize (gdbarch)); | |
c906108c | 2553 | |
acdb74a0 AC |
2554 | if (mips_debug) |
2555 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2556 | partial_len); | |
2557 | ||
566f0f7a | 2558 | /* Write this portion of the argument to the stack. */ |
f09ded24 AC |
2559 | if (argreg > MIPS_LAST_ARG_REGNUM |
2560 | || odd_sized_struct | |
2561 | || fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2562 | { |
c906108c SS |
2563 | /* Should shorter than int integer values be |
2564 | promoted to int before being stored? */ | |
c906108c | 2565 | int longword_offset = 0; |
9ace0497 | 2566 | CORE_ADDR addr; |
566f0f7a | 2567 | stack_used_p = 1; |
d7449b42 | 2568 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
7a292a7a | 2569 | { |
13326b4e | 2570 | if (mips_stack_argsize (gdbarch) == 8 |
480d3dd2 AC |
2571 | && (typecode == TYPE_CODE_INT |
2572 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 2573 | || typecode == TYPE_CODE_FLT) && len <= 4) |
13326b4e | 2574 | longword_offset = mips_stack_argsize (gdbarch) - len; |
480d3dd2 AC |
2575 | else if ((typecode == TYPE_CODE_STRUCT |
2576 | || typecode == TYPE_CODE_UNION) | |
2577 | && (TYPE_LENGTH (arg_type) | |
13326b4e AC |
2578 | < mips_stack_argsize (gdbarch))) |
2579 | longword_offset = mips_stack_argsize (gdbarch) - len; | |
7a292a7a | 2580 | } |
c5aa993b | 2581 | |
9ace0497 AC |
2582 | if (mips_debug) |
2583 | { | |
cb3d25d1 MS |
2584 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", |
2585 | paddr_nz (stack_offset)); | |
2586 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
2587 | paddr_nz (longword_offset)); | |
9ace0497 | 2588 | } |
361d1df0 | 2589 | |
9ace0497 AC |
2590 | addr = sp + stack_offset + longword_offset; |
2591 | ||
2592 | if (mips_debug) | |
2593 | { | |
2594 | int i; | |
6d82d43b | 2595 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 | 2596 | paddr_nz (addr)); |
9ace0497 AC |
2597 | for (i = 0; i < partial_len; i++) |
2598 | { | |
6d82d43b | 2599 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 2600 | val[i] & 0xff); |
9ace0497 AC |
2601 | } |
2602 | } | |
2603 | write_memory (addr, val, partial_len); | |
c906108c SS |
2604 | } |
2605 | ||
f09ded24 AC |
2606 | /* Note!!! This is NOT an else clause. Odd sized |
2607 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 2608 | arguments will not. */ |
566f0f7a | 2609 | /* Write this portion of the argument to a general |
6d82d43b | 2610 | purpose register. */ |
f09ded24 AC |
2611 | if (argreg <= MIPS_LAST_ARG_REGNUM |
2612 | && !fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2613 | { |
6d82d43b AC |
2614 | LONGEST regval = |
2615 | extract_unsigned_integer (val, partial_len); | |
c906108c | 2616 | |
9ace0497 | 2617 | if (mips_debug) |
acdb74a0 | 2618 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 2619 | argreg, |
6d82d43b | 2620 | phex (regval, |
13326b4e | 2621 | mips_abi_regsize (gdbarch))); |
c906108c SS |
2622 | write_register (argreg, regval); |
2623 | argreg++; | |
c906108c | 2624 | } |
c5aa993b | 2625 | |
c906108c SS |
2626 | len -= partial_len; |
2627 | val += partial_len; | |
2628 | ||
566f0f7a | 2629 | /* Compute the the offset into the stack at which we |
6d82d43b | 2630 | will copy the next parameter. |
566f0f7a | 2631 | |
566f0f7a | 2632 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 2633 | only needs to be adjusted when it has been used. */ |
c906108c | 2634 | |
46e0f506 | 2635 | if (stack_used_p) |
480d3dd2 | 2636 | stack_offset += align_up (partial_len, |
13326b4e | 2637 | mips_stack_argsize (gdbarch)); |
c906108c SS |
2638 | } |
2639 | } | |
9ace0497 AC |
2640 | if (mips_debug) |
2641 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
2642 | } |
2643 | ||
f10683bb | 2644 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 2645 | |
0f71a2f6 JM |
2646 | /* Return adjusted stack pointer. */ |
2647 | return sp; | |
2648 | } | |
2649 | ||
9c8fdbfa | 2650 | /* Determin the return value convention being used. */ |
6d82d43b | 2651 | |
9c8fdbfa AC |
2652 | static enum return_value_convention |
2653 | mips_eabi_return_value (struct gdbarch *gdbarch, | |
2654 | struct type *type, struct regcache *regcache, | |
47a35522 | 2655 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 2656 | { |
9c8fdbfa AC |
2657 | if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
2658 | return RETURN_VALUE_STRUCT_CONVENTION; | |
2659 | if (readbuf) | |
2660 | memset (readbuf, 0, TYPE_LENGTH (type)); | |
2661 | return RETURN_VALUE_REGISTER_CONVENTION; | |
6d82d43b AC |
2662 | } |
2663 | ||
6d82d43b AC |
2664 | |
2665 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 2666 | |
f7ab6ec6 | 2667 | static CORE_ADDR |
7d9b040b | 2668 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
2669 | struct regcache *regcache, CORE_ADDR bp_addr, |
2670 | int nargs, struct value **args, CORE_ADDR sp, | |
2671 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
2672 | { |
2673 | int argreg; | |
2674 | int float_argreg; | |
2675 | int argnum; | |
2676 | int len = 0; | |
2677 | int stack_offset = 0; | |
480d3dd2 | 2678 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 2679 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 2680 | |
25ab4790 AC |
2681 | /* For shared libraries, "t9" needs to point at the function |
2682 | address. */ | |
4c7d22cb | 2683 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
2684 | |
2685 | /* Set the return address register to point to the entry point of | |
2686 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 2687 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 2688 | |
cb3d25d1 MS |
2689 | /* First ensure that the stack and structure return address (if any) |
2690 | are properly aligned. The stack has to be at least 64-bit | |
2691 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2692 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2693 | aligned, so we round to this widest known alignment. */ | |
2694 | ||
5b03f266 AC |
2695 | sp = align_down (sp, 16); |
2696 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
2697 | |
2698 | /* Now make space on the stack for the args. */ | |
2699 | for (argnum = 0; argnum < nargs; argnum++) | |
4991999e | 2700 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), |
13326b4e | 2701 | mips_stack_argsize (gdbarch)); |
5b03f266 | 2702 | sp -= align_up (len, 16); |
cb3d25d1 MS |
2703 | |
2704 | if (mips_debug) | |
6d82d43b | 2705 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
2706 | "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n", |
2707 | paddr_nz (sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
2708 | |
2709 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 2710 | argreg = MIPS_A0_REGNUM; |
56cea623 | 2711 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
cb3d25d1 | 2712 | |
46e0f506 | 2713 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
2714 | if (struct_return) |
2715 | { | |
2716 | if (mips_debug) | |
2717 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2718 | "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 MS |
2719 | argreg, paddr_nz (struct_addr)); |
2720 | write_register (argreg++, struct_addr); | |
2721 | } | |
2722 | ||
2723 | /* Now load as many as possible of the first arguments into | |
2724 | registers, and push the rest onto the stack. Loop thru args | |
2725 | from first to last. */ | |
2726 | for (argnum = 0; argnum < nargs; argnum++) | |
2727 | { | |
47a35522 | 2728 | const gdb_byte *val; |
cb3d25d1 | 2729 | struct value *arg = args[argnum]; |
4991999e | 2730 | struct type *arg_type = check_typedef (value_type (arg)); |
cb3d25d1 MS |
2731 | int len = TYPE_LENGTH (arg_type); |
2732 | enum type_code typecode = TYPE_CODE (arg_type); | |
2733 | ||
2734 | if (mips_debug) | |
2735 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2736 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
2737 | argnum + 1, len, (int) typecode); |
2738 | ||
47a35522 | 2739 | val = value_contents (arg); |
cb3d25d1 MS |
2740 | |
2741 | if (fp_register_arg_p (typecode, arg_type) | |
2742 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
2743 | { | |
2744 | /* This is a floating point value that fits entirely | |
2745 | in a single register. */ | |
2746 | /* On 32 bit ABI's the float_argreg is further adjusted | |
2747 | above to ensure that it is even register aligned. */ | |
2748 | LONGEST regval = extract_unsigned_integer (val, len); | |
2749 | if (mips_debug) | |
2750 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
2751 | float_argreg, phex (regval, len)); | |
2752 | write_register (float_argreg++, regval); | |
2753 | ||
2754 | if (mips_debug) | |
2755 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
2756 | argreg, phex (regval, len)); | |
2757 | write_register (argreg, regval); | |
2758 | argreg += 1; | |
2759 | } | |
2760 | else | |
2761 | { | |
2762 | /* Copy the argument to general registers or the stack in | |
2763 | register-sized pieces. Large arguments are split between | |
2764 | registers and stack. */ | |
4246e332 | 2765 | /* Note: structs whose size is not a multiple of |
d5ac5a39 AC |
2766 | mips_abi_regsize() are treated specially: Irix cc passes |
2767 | them in registers where gcc sometimes puts them on the | |
2768 | stack. For maximum compatibility, we will put them in | |
2769 | both places. */ | |
13326b4e AC |
2770 | int odd_sized_struct = ((len > mips_abi_regsize (gdbarch)) |
2771 | && (len % mips_abi_regsize (gdbarch) != 0)); | |
cb3d25d1 | 2772 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 2773 | register are only written to memory. */ |
cb3d25d1 MS |
2774 | while (len > 0) |
2775 | { | |
2776 | /* Rememer if the argument was written to the stack. */ | |
2777 | int stack_used_p = 0; | |
13326b4e AC |
2778 | int partial_len = (len < mips_abi_regsize (gdbarch) |
2779 | ? len : mips_abi_regsize (gdbarch)); | |
cb3d25d1 MS |
2780 | |
2781 | if (mips_debug) | |
2782 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2783 | partial_len); | |
2784 | ||
2785 | /* Write this portion of the argument to the stack. */ | |
2786 | if (argreg > MIPS_LAST_ARG_REGNUM | |
2787 | || odd_sized_struct | |
2788 | || fp_register_arg_p (typecode, arg_type)) | |
2789 | { | |
2790 | /* Should shorter than int integer values be | |
2791 | promoted to int before being stored? */ | |
2792 | int longword_offset = 0; | |
2793 | CORE_ADDR addr; | |
2794 | stack_used_p = 1; | |
2795 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
2796 | { | |
13326b4e | 2797 | if (mips_stack_argsize (gdbarch) == 8 |
480d3dd2 AC |
2798 | && (typecode == TYPE_CODE_INT |
2799 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 2800 | || typecode == TYPE_CODE_FLT) && len <= 4) |
13326b4e | 2801 | longword_offset = mips_stack_argsize (gdbarch) - len; |
cb3d25d1 MS |
2802 | } |
2803 | ||
2804 | if (mips_debug) | |
2805 | { | |
2806 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
2807 | paddr_nz (stack_offset)); | |
2808 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
2809 | paddr_nz (longword_offset)); | |
2810 | } | |
2811 | ||
2812 | addr = sp + stack_offset + longword_offset; | |
2813 | ||
2814 | if (mips_debug) | |
2815 | { | |
2816 | int i; | |
6d82d43b | 2817 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 MS |
2818 | paddr_nz (addr)); |
2819 | for (i = 0; i < partial_len; i++) | |
2820 | { | |
6d82d43b | 2821 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
2822 | val[i] & 0xff); |
2823 | } | |
2824 | } | |
2825 | write_memory (addr, val, partial_len); | |
2826 | } | |
2827 | ||
2828 | /* Note!!! This is NOT an else clause. Odd sized | |
2829 | structs may go thru BOTH paths. Floating point | |
2830 | arguments will not. */ | |
2831 | /* Write this portion of the argument to a general | |
6d82d43b | 2832 | purpose register. */ |
cb3d25d1 MS |
2833 | if (argreg <= MIPS_LAST_ARG_REGNUM |
2834 | && !fp_register_arg_p (typecode, arg_type)) | |
2835 | { | |
6d82d43b AC |
2836 | LONGEST regval = |
2837 | extract_unsigned_integer (val, partial_len); | |
cb3d25d1 MS |
2838 | |
2839 | /* A non-floating-point argument being passed in a | |
2840 | general register. If a struct or union, and if | |
2841 | the remaining length is smaller than the register | |
2842 | size, we have to adjust the register value on | |
2843 | big endian targets. | |
2844 | ||
2845 | It does not seem to be necessary to do the | |
2846 | same for integral types. | |
2847 | ||
2848 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
2849 | outputting LE O32 with sizeof (struct) < | |
1b13c4f6 | 2850 | mips_abi_regsize(), generates a left shift as |
cb3d25d1 MS |
2851 | part of storing the argument in a register a |
2852 | register (the left shift isn't generated when | |
1b13c4f6 | 2853 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
2854 | it is quite possible that this is GCC |
2855 | contradicting the LE/O32 ABI, GDB has not been | |
2856 | adjusted to accommodate this. Either someone | |
2857 | needs to demonstrate that the LE/O32 ABI | |
2858 | specifies such a left shift OR this new ABI gets | |
2859 | identified as such and GDB gets tweaked | |
2860 | accordingly. */ | |
cb3d25d1 MS |
2861 | |
2862 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
13326b4e | 2863 | && partial_len < mips_abi_regsize (gdbarch) |
cb3d25d1 MS |
2864 | && (typecode == TYPE_CODE_STRUCT || |
2865 | typecode == TYPE_CODE_UNION)) | |
13326b4e | 2866 | regval <<= ((mips_abi_regsize (gdbarch) - partial_len) * |
cb3d25d1 MS |
2867 | TARGET_CHAR_BIT); |
2868 | ||
2869 | if (mips_debug) | |
2870 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
2871 | argreg, | |
6d82d43b | 2872 | phex (regval, |
13326b4e | 2873 | mips_abi_regsize (gdbarch))); |
cb3d25d1 MS |
2874 | write_register (argreg, regval); |
2875 | argreg++; | |
2876 | } | |
2877 | ||
2878 | len -= partial_len; | |
2879 | val += partial_len; | |
2880 | ||
2881 | /* Compute the the offset into the stack at which we | |
6d82d43b | 2882 | will copy the next parameter. |
cb3d25d1 MS |
2883 | |
2884 | In N32 (N64?), the stack_offset only needs to be | |
2885 | adjusted when it has been used. */ | |
2886 | ||
2887 | if (stack_used_p) | |
480d3dd2 | 2888 | stack_offset += align_up (partial_len, |
13326b4e | 2889 | mips_stack_argsize (gdbarch)); |
cb3d25d1 MS |
2890 | } |
2891 | } | |
2892 | if (mips_debug) | |
2893 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
2894 | } | |
2895 | ||
f10683bb | 2896 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 2897 | |
cb3d25d1 MS |
2898 | /* Return adjusted stack pointer. */ |
2899 | return sp; | |
2900 | } | |
2901 | ||
6d82d43b AC |
2902 | static enum return_value_convention |
2903 | mips_n32n64_return_value (struct gdbarch *gdbarch, | |
2904 | struct type *type, struct regcache *regcache, | |
47a35522 | 2905 | gdb_byte *readbuf, const gdb_byte *writebuf) |
ebafbe83 | 2906 | { |
6d82d43b AC |
2907 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2908 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
2909 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
2910 | || TYPE_CODE (type) == TYPE_CODE_ARRAY | |
13326b4e | 2911 | || TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
6d82d43b AC |
2912 | return RETURN_VALUE_STRUCT_CONVENTION; |
2913 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
2914 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
2915 | { | |
2916 | /* A floating-point value belongs in the least significant part | |
2917 | of FP0. */ | |
2918 | if (mips_debug) | |
2919 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
2920 | mips_xfer_register (regcache, | |
2921 | NUM_REGS + mips_regnum (current_gdbarch)->fp0, | |
2922 | TYPE_LENGTH (type), | |
2923 | TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
2924 | return RETURN_VALUE_REGISTER_CONVENTION; | |
2925 | } | |
2926 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
2927 | && TYPE_NFIELDS (type) <= 2 | |
2928 | && TYPE_NFIELDS (type) >= 1 | |
2929 | && ((TYPE_NFIELDS (type) == 1 | |
2930 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
2931 | == TYPE_CODE_FLT)) | |
2932 | || (TYPE_NFIELDS (type) == 2 | |
2933 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
2934 | == TYPE_CODE_FLT) | |
2935 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
2936 | == TYPE_CODE_FLT))) | |
2937 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
2938 | { | |
2939 | /* A struct that contains one or two floats. Each value is part | |
2940 | in the least significant part of their floating point | |
2941 | register.. */ | |
6d82d43b AC |
2942 | int regnum; |
2943 | int field; | |
2944 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; | |
2945 | field < TYPE_NFIELDS (type); field++, regnum += 2) | |
2946 | { | |
2947 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
2948 | / TARGET_CHAR_BIT); | |
2949 | if (mips_debug) | |
2950 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
2951 | offset); | |
2952 | mips_xfer_register (regcache, NUM_REGS + regnum, | |
2953 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
2954 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
2955 | } | |
2956 | return RETURN_VALUE_REGISTER_CONVENTION; | |
2957 | } | |
2958 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
2959 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
2960 | { | |
2961 | /* A structure or union. Extract the left justified value, | |
2962 | regardless of the byte order. I.e. DO NOT USE | |
2963 | mips_xfer_lower. */ | |
2964 | int offset; | |
2965 | int regnum; | |
4c7d22cb | 2966 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b AC |
2967 | offset < TYPE_LENGTH (type); |
2968 | offset += register_size (current_gdbarch, regnum), regnum++) | |
2969 | { | |
2970 | int xfer = register_size (current_gdbarch, regnum); | |
2971 | if (offset + xfer > TYPE_LENGTH (type)) | |
2972 | xfer = TYPE_LENGTH (type) - offset; | |
2973 | if (mips_debug) | |
2974 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
2975 | offset, xfer, regnum); | |
2976 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
2977 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); | |
2978 | } | |
2979 | return RETURN_VALUE_REGISTER_CONVENTION; | |
2980 | } | |
2981 | else | |
2982 | { | |
2983 | /* A scalar extract each part but least-significant-byte | |
2984 | justified. */ | |
2985 | int offset; | |
2986 | int regnum; | |
4c7d22cb | 2987 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b AC |
2988 | offset < TYPE_LENGTH (type); |
2989 | offset += register_size (current_gdbarch, regnum), regnum++) | |
2990 | { | |
2991 | int xfer = register_size (current_gdbarch, regnum); | |
6d82d43b AC |
2992 | if (offset + xfer > TYPE_LENGTH (type)) |
2993 | xfer = TYPE_LENGTH (type) - offset; | |
2994 | if (mips_debug) | |
2995 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
2996 | offset, xfer, regnum); | |
2997 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
2998 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
2999 | } | |
3000 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3001 | } | |
3002 | } | |
3003 | ||
3004 | /* O32 ABI stuff. */ | |
3005 | ||
3006 | static CORE_ADDR | |
7d9b040b | 3007 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3008 | struct regcache *regcache, CORE_ADDR bp_addr, |
3009 | int nargs, struct value **args, CORE_ADDR sp, | |
3010 | int struct_return, CORE_ADDR struct_addr) | |
3011 | { | |
3012 | int argreg; | |
3013 | int float_argreg; | |
3014 | int argnum; | |
3015 | int len = 0; | |
3016 | int stack_offset = 0; | |
3017 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
7d9b040b | 3018 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
3019 | |
3020 | /* For shared libraries, "t9" needs to point at the function | |
3021 | address. */ | |
4c7d22cb | 3022 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
6d82d43b AC |
3023 | |
3024 | /* Set the return address register to point to the entry point of | |
3025 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3026 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
6d82d43b AC |
3027 | |
3028 | /* First ensure that the stack and structure return address (if any) | |
3029 | are properly aligned. The stack has to be at least 64-bit | |
3030 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
3031 | aligned. For n32 and n64, stack frames need to be 128-bit |
3032 | aligned, so we round to this widest known alignment. */ | |
3033 | ||
5b03f266 AC |
3034 | sp = align_down (sp, 16); |
3035 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
3036 | |
3037 | /* Now make space on the stack for the args. */ | |
3038 | for (argnum = 0; argnum < nargs; argnum++) | |
4991999e | 3039 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), |
13326b4e | 3040 | mips_stack_argsize (gdbarch)); |
5b03f266 | 3041 | sp -= align_up (len, 16); |
ebafbe83 MS |
3042 | |
3043 | if (mips_debug) | |
6d82d43b | 3044 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3045 | "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n", |
3046 | paddr_nz (sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
3047 | |
3048 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3049 | argreg = MIPS_A0_REGNUM; |
56cea623 | 3050 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
ebafbe83 | 3051 | |
bcb0cc15 | 3052 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3053 | if (struct_return) |
3054 | { | |
3055 | if (mips_debug) | |
3056 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3057 | "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n", |
ebafbe83 MS |
3058 | argreg, paddr_nz (struct_addr)); |
3059 | write_register (argreg++, struct_addr); | |
13326b4e | 3060 | stack_offset += mips_stack_argsize (gdbarch); |
ebafbe83 MS |
3061 | } |
3062 | ||
3063 | /* Now load as many as possible of the first arguments into | |
3064 | registers, and push the rest onto the stack. Loop thru args | |
3065 | from first to last. */ | |
3066 | for (argnum = 0; argnum < nargs; argnum++) | |
3067 | { | |
47a35522 | 3068 | const gdb_byte *val; |
ebafbe83 | 3069 | struct value *arg = args[argnum]; |
4991999e | 3070 | struct type *arg_type = check_typedef (value_type (arg)); |
ebafbe83 MS |
3071 | int len = TYPE_LENGTH (arg_type); |
3072 | enum type_code typecode = TYPE_CODE (arg_type); | |
3073 | ||
3074 | if (mips_debug) | |
3075 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3076 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3077 | argnum + 1, len, (int) typecode); |
3078 | ||
47a35522 | 3079 | val = value_contents (arg); |
46cac009 AC |
3080 | |
3081 | /* 32-bit ABIs always start floating point arguments in an | |
3082 | even-numbered floating point register. Round the FP register | |
3083 | up before the check to see if there are any FP registers | |
3084 | left. O32/O64 targets also pass the FP in the integer | |
3085 | registers so also round up normal registers. */ | |
ceae6e75 AC |
3086 | if (mips_abi_regsize (gdbarch) < 8 |
3087 | && fp_register_arg_p (typecode, arg_type)) | |
46cac009 AC |
3088 | { |
3089 | if ((float_argreg & 1)) | |
3090 | float_argreg++; | |
3091 | } | |
3092 | ||
3093 | /* Floating point arguments passed in registers have to be | |
3094 | treated specially. On 32-bit architectures, doubles | |
3095 | are passed in register pairs; the even register gets | |
3096 | the low word, and the odd register gets the high word. | |
3097 | On O32/O64, the first two floating point arguments are | |
3098 | also copied to general registers, because MIPS16 functions | |
3099 | don't use float registers for arguments. This duplication of | |
3100 | arguments in general registers can't hurt non-MIPS16 functions | |
3101 | because those registers are normally skipped. */ | |
3102 | ||
3103 | if (fp_register_arg_p (typecode, arg_type) | |
3104 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3105 | { | |
ceae6e75 | 3106 | if (mips_abi_regsize (gdbarch) < 8 && len == 8) |
46cac009 AC |
3107 | { |
3108 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
3109 | unsigned long regval; | |
3110 | ||
3111 | /* Write the low word of the double to the even register(s). */ | |
3112 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3113 | if (mips_debug) | |
3114 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3115 | float_argreg, phex (regval, 4)); | |
3116 | write_register (float_argreg++, regval); | |
3117 | if (mips_debug) | |
3118 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3119 | argreg, phex (regval, 4)); | |
3120 | write_register (argreg++, regval); | |
3121 | ||
3122 | /* Write the high word of the double to the odd register(s). */ | |
3123 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3124 | if (mips_debug) | |
3125 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3126 | float_argreg, phex (regval, 4)); | |
3127 | write_register (float_argreg++, regval); | |
3128 | ||
3129 | if (mips_debug) | |
3130 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3131 | argreg, phex (regval, 4)); | |
3132 | write_register (argreg++, regval); | |
3133 | } | |
3134 | else | |
3135 | { | |
3136 | /* This is a floating point value that fits entirely | |
3137 | in a single register. */ | |
3138 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 3139 | above to ensure that it is even register aligned. */ |
46cac009 AC |
3140 | LONGEST regval = extract_unsigned_integer (val, len); |
3141 | if (mips_debug) | |
3142 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3143 | float_argreg, phex (regval, len)); | |
3144 | write_register (float_argreg++, regval); | |
3145 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
6d82d43b AC |
3146 | registers for each argument. The below is (my |
3147 | guess) to ensure that the corresponding integer | |
3148 | register has reserved the same space. */ | |
46cac009 AC |
3149 | if (mips_debug) |
3150 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3151 | argreg, phex (regval, len)); | |
3152 | write_register (argreg, regval); | |
ceae6e75 | 3153 | argreg += (mips_abi_regsize (gdbarch) == 8) ? 1 : 2; |
46cac009 AC |
3154 | } |
3155 | /* Reserve space for the FP register. */ | |
13326b4e | 3156 | stack_offset += align_up (len, mips_stack_argsize (gdbarch)); |
46cac009 AC |
3157 | } |
3158 | else | |
3159 | { | |
3160 | /* Copy the argument to general registers or the stack in | |
3161 | register-sized pieces. Large arguments are split between | |
3162 | registers and stack. */ | |
4246e332 | 3163 | /* Note: structs whose size is not a multiple of |
d5ac5a39 AC |
3164 | mips_abi_regsize() are treated specially: Irix cc passes |
3165 | them in registers where gcc sometimes puts them on the | |
3166 | stack. For maximum compatibility, we will put them in | |
3167 | both places. */ | |
13326b4e AC |
3168 | int odd_sized_struct = ((len > mips_abi_regsize (gdbarch)) |
3169 | && (len % mips_abi_regsize (gdbarch) != 0)); | |
46cac009 AC |
3170 | /* Structures should be aligned to eight bytes (even arg registers) |
3171 | on MIPS_ABI_O32, if their first member has double precision. */ | |
13326b4e | 3172 | if (mips_abi_regsize (gdbarch) < 8 |
46cac009 AC |
3173 | && mips_type_needs_double_align (arg_type)) |
3174 | { | |
3175 | if ((argreg & 1)) | |
6d82d43b | 3176 | argreg++; |
46cac009 AC |
3177 | } |
3178 | /* Note: Floating-point values that didn't fit into an FP | |
6d82d43b | 3179 | register are only written to memory. */ |
46cac009 AC |
3180 | while (len > 0) |
3181 | { | |
3182 | /* Remember if the argument was written to the stack. */ | |
3183 | int stack_used_p = 0; | |
13326b4e AC |
3184 | int partial_len = (len < mips_abi_regsize (gdbarch) |
3185 | ? len : mips_abi_regsize (gdbarch)); | |
46cac009 AC |
3186 | |
3187 | if (mips_debug) | |
3188 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3189 | partial_len); | |
3190 | ||
3191 | /* Write this portion of the argument to the stack. */ | |
3192 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3193 | || odd_sized_struct | |
3194 | || fp_register_arg_p (typecode, arg_type)) | |
3195 | { | |
3196 | /* Should shorter than int integer values be | |
3197 | promoted to int before being stored? */ | |
3198 | int longword_offset = 0; | |
3199 | CORE_ADDR addr; | |
3200 | stack_used_p = 1; | |
3201 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3202 | { | |
13326b4e | 3203 | if (mips_stack_argsize (gdbarch) == 8 |
480d3dd2 AC |
3204 | && (typecode == TYPE_CODE_INT |
3205 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 3206 | || typecode == TYPE_CODE_FLT) && len <= 4) |
13326b4e | 3207 | longword_offset = mips_stack_argsize (gdbarch) - len; |
46cac009 AC |
3208 | } |
3209 | ||
3210 | if (mips_debug) | |
3211 | { | |
3212 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3213 | paddr_nz (stack_offset)); | |
3214 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3215 | paddr_nz (longword_offset)); | |
3216 | } | |
3217 | ||
3218 | addr = sp + stack_offset + longword_offset; | |
3219 | ||
3220 | if (mips_debug) | |
3221 | { | |
3222 | int i; | |
6d82d43b | 3223 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
46cac009 AC |
3224 | paddr_nz (addr)); |
3225 | for (i = 0; i < partial_len; i++) | |
3226 | { | |
6d82d43b | 3227 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
3228 | val[i] & 0xff); |
3229 | } | |
3230 | } | |
3231 | write_memory (addr, val, partial_len); | |
3232 | } | |
3233 | ||
3234 | /* Note!!! This is NOT an else clause. Odd sized | |
3235 | structs may go thru BOTH paths. Floating point | |
3236 | arguments will not. */ | |
3237 | /* Write this portion of the argument to a general | |
6d82d43b | 3238 | purpose register. */ |
46cac009 AC |
3239 | if (argreg <= MIPS_LAST_ARG_REGNUM |
3240 | && !fp_register_arg_p (typecode, arg_type)) | |
3241 | { | |
3242 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 3243 | /* Value may need to be sign extended, because |
1b13c4f6 | 3244 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
3245 | |
3246 | /* A non-floating-point argument being passed in a | |
3247 | general register. If a struct or union, and if | |
3248 | the remaining length is smaller than the register | |
3249 | size, we have to adjust the register value on | |
3250 | big endian targets. | |
3251 | ||
3252 | It does not seem to be necessary to do the | |
3253 | same for integral types. | |
3254 | ||
3255 | Also don't do this adjustment on O64 binaries. | |
3256 | ||
3257 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3258 | outputting LE O32 with sizeof (struct) < | |
1b13c4f6 | 3259 | mips_abi_regsize(), generates a left shift as |
46cac009 AC |
3260 | part of storing the argument in a register a |
3261 | register (the left shift isn't generated when | |
1b13c4f6 | 3262 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
3263 | it is quite possible that this is GCC |
3264 | contradicting the LE/O32 ABI, GDB has not been | |
3265 | adjusted to accommodate this. Either someone | |
3266 | needs to demonstrate that the LE/O32 ABI | |
3267 | specifies such a left shift OR this new ABI gets | |
3268 | identified as such and GDB gets tweaked | |
3269 | accordingly. */ | |
3270 | ||
13326b4e | 3271 | if (mips_abi_regsize (gdbarch) < 8 |
46cac009 | 3272 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
13326b4e | 3273 | && partial_len < mips_abi_regsize (gdbarch) |
46cac009 AC |
3274 | && (typecode == TYPE_CODE_STRUCT || |
3275 | typecode == TYPE_CODE_UNION)) | |
13326b4e | 3276 | regval <<= ((mips_abi_regsize (gdbarch) - partial_len) * |
46cac009 AC |
3277 | TARGET_CHAR_BIT); |
3278 | ||
3279 | if (mips_debug) | |
3280 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3281 | argreg, | |
6d82d43b | 3282 | phex (regval, |
13326b4e | 3283 | mips_abi_regsize (gdbarch))); |
46cac009 AC |
3284 | write_register (argreg, regval); |
3285 | argreg++; | |
3286 | ||
3287 | /* Prevent subsequent floating point arguments from | |
3288 | being passed in floating point registers. */ | |
3289 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3290 | } | |
3291 | ||
3292 | len -= partial_len; | |
3293 | val += partial_len; | |
3294 | ||
3295 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3296 | will copy the next parameter. |
46cac009 | 3297 | |
6d82d43b AC |
3298 | In older ABIs, the caller reserved space for |
3299 | registers that contained arguments. This was loosely | |
3300 | refered to as their "home". Consequently, space is | |
3301 | always allocated. */ | |
46cac009 | 3302 | |
480d3dd2 | 3303 | stack_offset += align_up (partial_len, |
13326b4e | 3304 | mips_stack_argsize (gdbarch)); |
46cac009 AC |
3305 | } |
3306 | } | |
3307 | if (mips_debug) | |
3308 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3309 | } | |
3310 | ||
f10683bb | 3311 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3312 | |
46cac009 AC |
3313 | /* Return adjusted stack pointer. */ |
3314 | return sp; | |
3315 | } | |
3316 | ||
6d82d43b AC |
3317 | static enum return_value_convention |
3318 | mips_o32_return_value (struct gdbarch *gdbarch, struct type *type, | |
3319 | struct regcache *regcache, | |
47a35522 | 3320 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b AC |
3321 | { |
3322 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3323 | ||
3324 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3325 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3326 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
3327 | return RETURN_VALUE_STRUCT_CONVENTION; | |
3328 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3329 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3330 | { | |
3331 | /* A single-precision floating-point value. It fits in the | |
3332 | least significant part of FP0. */ | |
3333 | if (mips_debug) | |
3334 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3335 | mips_xfer_register (regcache, | |
3336 | NUM_REGS + mips_regnum (current_gdbarch)->fp0, | |
3337 | TYPE_LENGTH (type), | |
3338 | TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
3339 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3340 | } | |
3341 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3342 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3343 | { | |
3344 | /* A double-precision floating-point value. The most | |
3345 | significant part goes in FP1, and the least significant in | |
3346 | FP0. */ | |
3347 | if (mips_debug) | |
3348 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
3349 | switch (TARGET_BYTE_ORDER) | |
3350 | { | |
3351 | case BFD_ENDIAN_LITTLE: | |
3352 | mips_xfer_register (regcache, | |
3353 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
3354 | 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
3355 | mips_xfer_register (regcache, | |
3356 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
3357 | 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4); | |
3358 | break; | |
3359 | case BFD_ENDIAN_BIG: | |
3360 | mips_xfer_register (regcache, | |
3361 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
3362 | 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
3363 | mips_xfer_register (regcache, | |
3364 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
3365 | 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4); | |
3366 | break; | |
3367 | default: | |
e2e0b3e5 | 3368 | internal_error (__FILE__, __LINE__, _("bad switch")); |
6d82d43b AC |
3369 | } |
3370 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3371 | } | |
3372 | #if 0 | |
3373 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3374 | && TYPE_NFIELDS (type) <= 2 | |
3375 | && TYPE_NFIELDS (type) >= 1 | |
3376 | && ((TYPE_NFIELDS (type) == 1 | |
3377 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3378 | == TYPE_CODE_FLT)) | |
3379 | || (TYPE_NFIELDS (type) == 2 | |
3380 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3381 | == TYPE_CODE_FLT) | |
3382 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
3383 | == TYPE_CODE_FLT))) | |
3384 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3385 | { | |
3386 | /* A struct that contains one or two floats. Each value is part | |
3387 | in the least significant part of their floating point | |
3388 | register.. */ | |
870cd05e | 3389 | gdb_byte reg[MAX_REGISTER_SIZE]; |
6d82d43b AC |
3390 | int regnum; |
3391 | int field; | |
3392 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; | |
3393 | field < TYPE_NFIELDS (type); field++, regnum += 2) | |
3394 | { | |
3395 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3396 | / TARGET_CHAR_BIT); | |
3397 | if (mips_debug) | |
3398 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3399 | offset); | |
3400 | mips_xfer_register (regcache, NUM_REGS + regnum, | |
3401 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
3402 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
3403 | } | |
3404 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3405 | } | |
3406 | #endif | |
3407 | #if 0 | |
3408 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3409 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3410 | { | |
3411 | /* A structure or union. Extract the left justified value, | |
3412 | regardless of the byte order. I.e. DO NOT USE | |
3413 | mips_xfer_lower. */ | |
3414 | int offset; | |
3415 | int regnum; | |
4c7d22cb | 3416 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b AC |
3417 | offset < TYPE_LENGTH (type); |
3418 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3419 | { | |
3420 | int xfer = register_size (current_gdbarch, regnum); | |
3421 | if (offset + xfer > TYPE_LENGTH (type)) | |
3422 | xfer = TYPE_LENGTH (type) - offset; | |
3423 | if (mips_debug) | |
3424 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3425 | offset, xfer, regnum); | |
3426 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
3427 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); | |
3428 | } | |
3429 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3430 | } | |
3431 | #endif | |
3432 | else | |
3433 | { | |
3434 | /* A scalar extract each part but least-significant-byte | |
3435 | justified. o32 thinks registers are 4 byte, regardless of | |
3436 | the ISA. mips_stack_argsize controls this. */ | |
3437 | int offset; | |
3438 | int regnum; | |
4c7d22cb | 3439 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3440 | offset < TYPE_LENGTH (type); |
13326b4e | 3441 | offset += mips_stack_argsize (gdbarch), regnum++) |
6d82d43b | 3442 | { |
13326b4e | 3443 | int xfer = mips_stack_argsize (gdbarch); |
6d82d43b AC |
3444 | if (offset + xfer > TYPE_LENGTH (type)) |
3445 | xfer = TYPE_LENGTH (type) - offset; | |
3446 | if (mips_debug) | |
3447 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3448 | offset, xfer, regnum); | |
3449 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
3450 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
3451 | } | |
3452 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3453 | } | |
3454 | } | |
3455 | ||
3456 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
3457 | ABI. */ | |
46cac009 AC |
3458 | |
3459 | static CORE_ADDR | |
7d9b040b | 3460 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3461 | struct regcache *regcache, CORE_ADDR bp_addr, |
3462 | int nargs, | |
3463 | struct value **args, CORE_ADDR sp, | |
3464 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
3465 | { |
3466 | int argreg; | |
3467 | int float_argreg; | |
3468 | int argnum; | |
3469 | int len = 0; | |
3470 | int stack_offset = 0; | |
480d3dd2 | 3471 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 3472 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 3473 | |
25ab4790 AC |
3474 | /* For shared libraries, "t9" needs to point at the function |
3475 | address. */ | |
4c7d22cb | 3476 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
3477 | |
3478 | /* Set the return address register to point to the entry point of | |
3479 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3480 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 3481 | |
46cac009 AC |
3482 | /* First ensure that the stack and structure return address (if any) |
3483 | are properly aligned. The stack has to be at least 64-bit | |
3484 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3485 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3486 | aligned, so we round to this widest known alignment. */ | |
3487 | ||
5b03f266 AC |
3488 | sp = align_down (sp, 16); |
3489 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
3490 | |
3491 | /* Now make space on the stack for the args. */ | |
3492 | for (argnum = 0; argnum < nargs; argnum++) | |
4991999e | 3493 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), |
13326b4e | 3494 | mips_stack_argsize (gdbarch)); |
5b03f266 | 3495 | sp -= align_up (len, 16); |
46cac009 AC |
3496 | |
3497 | if (mips_debug) | |
6d82d43b | 3498 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3499 | "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n", |
3500 | paddr_nz (sp), (long) align_up (len, 16)); | |
46cac009 AC |
3501 | |
3502 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3503 | argreg = MIPS_A0_REGNUM; |
56cea623 | 3504 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
46cac009 AC |
3505 | |
3506 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
3507 | if (struct_return) | |
3508 | { | |
3509 | if (mips_debug) | |
3510 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3511 | "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n", |
46cac009 AC |
3512 | argreg, paddr_nz (struct_addr)); |
3513 | write_register (argreg++, struct_addr); | |
13326b4e | 3514 | stack_offset += mips_stack_argsize (gdbarch); |
46cac009 AC |
3515 | } |
3516 | ||
3517 | /* Now load as many as possible of the first arguments into | |
3518 | registers, and push the rest onto the stack. Loop thru args | |
3519 | from first to last. */ | |
3520 | for (argnum = 0; argnum < nargs; argnum++) | |
3521 | { | |
47a35522 | 3522 | const gdb_byte *val; |
46cac009 | 3523 | struct value *arg = args[argnum]; |
4991999e | 3524 | struct type *arg_type = check_typedef (value_type (arg)); |
46cac009 AC |
3525 | int len = TYPE_LENGTH (arg_type); |
3526 | enum type_code typecode = TYPE_CODE (arg_type); | |
3527 | ||
3528 | if (mips_debug) | |
3529 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3530 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
3531 | argnum + 1, len, (int) typecode); |
3532 | ||
47a35522 | 3533 | val = value_contents (arg); |
ebafbe83 MS |
3534 | |
3535 | /* 32-bit ABIs always start floating point arguments in an | |
3536 | even-numbered floating point register. Round the FP register | |
3537 | up before the check to see if there are any FP registers | |
3538 | left. O32/O64 targets also pass the FP in the integer | |
3539 | registers so also round up normal registers. */ | |
ceae6e75 AC |
3540 | if (mips_abi_regsize (gdbarch) < 8 |
3541 | && fp_register_arg_p (typecode, arg_type)) | |
ebafbe83 MS |
3542 | { |
3543 | if ((float_argreg & 1)) | |
3544 | float_argreg++; | |
3545 | } | |
3546 | ||
3547 | /* Floating point arguments passed in registers have to be | |
3548 | treated specially. On 32-bit architectures, doubles | |
3549 | are passed in register pairs; the even register gets | |
3550 | the low word, and the odd register gets the high word. | |
3551 | On O32/O64, the first two floating point arguments are | |
3552 | also copied to general registers, because MIPS16 functions | |
3553 | don't use float registers for arguments. This duplication of | |
3554 | arguments in general registers can't hurt non-MIPS16 functions | |
3555 | because those registers are normally skipped. */ | |
3556 | ||
3557 | if (fp_register_arg_p (typecode, arg_type) | |
3558 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3559 | { | |
ceae6e75 | 3560 | if (mips_abi_regsize (gdbarch) < 8 && len == 8) |
ebafbe83 MS |
3561 | { |
3562 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
3563 | unsigned long regval; | |
3564 | ||
3565 | /* Write the low word of the double to the even register(s). */ | |
3566 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3567 | if (mips_debug) | |
3568 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3569 | float_argreg, phex (regval, 4)); | |
3570 | write_register (float_argreg++, regval); | |
3571 | if (mips_debug) | |
3572 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3573 | argreg, phex (regval, 4)); | |
3574 | write_register (argreg++, regval); | |
3575 | ||
3576 | /* Write the high word of the double to the odd register(s). */ | |
3577 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3578 | if (mips_debug) | |
3579 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3580 | float_argreg, phex (regval, 4)); | |
3581 | write_register (float_argreg++, regval); | |
3582 | ||
3583 | if (mips_debug) | |
3584 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3585 | argreg, phex (regval, 4)); | |
3586 | write_register (argreg++, regval); | |
3587 | } | |
3588 | else | |
3589 | { | |
3590 | /* This is a floating point value that fits entirely | |
3591 | in a single register. */ | |
3592 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 3593 | above to ensure that it is even register aligned. */ |
ebafbe83 MS |
3594 | LONGEST regval = extract_unsigned_integer (val, len); |
3595 | if (mips_debug) | |
3596 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3597 | float_argreg, phex (regval, len)); | |
3598 | write_register (float_argreg++, regval); | |
3599 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
6d82d43b AC |
3600 | registers for each argument. The below is (my |
3601 | guess) to ensure that the corresponding integer | |
3602 | register has reserved the same space. */ | |
ebafbe83 MS |
3603 | if (mips_debug) |
3604 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3605 | argreg, phex (regval, len)); | |
3606 | write_register (argreg, regval); | |
ceae6e75 | 3607 | argreg += (mips_abi_regsize (gdbarch) == 8) ? 1 : 2; |
ebafbe83 MS |
3608 | } |
3609 | /* Reserve space for the FP register. */ | |
13326b4e | 3610 | stack_offset += align_up (len, mips_stack_argsize (gdbarch)); |
ebafbe83 MS |
3611 | } |
3612 | else | |
3613 | { | |
3614 | /* Copy the argument to general registers or the stack in | |
3615 | register-sized pieces. Large arguments are split between | |
3616 | registers and stack. */ | |
4246e332 | 3617 | /* Note: structs whose size is not a multiple of |
d5ac5a39 AC |
3618 | mips_abi_regsize() are treated specially: Irix cc passes |
3619 | them in registers where gcc sometimes puts them on the | |
3620 | stack. For maximum compatibility, we will put them in | |
3621 | both places. */ | |
13326b4e AC |
3622 | int odd_sized_struct = ((len > mips_abi_regsize (gdbarch)) |
3623 | && (len % mips_abi_regsize (gdbarch) != 0)); | |
ebafbe83 MS |
3624 | /* Structures should be aligned to eight bytes (even arg registers) |
3625 | on MIPS_ABI_O32, if their first member has double precision. */ | |
13326b4e | 3626 | if (mips_abi_regsize (gdbarch) < 8 |
ebafbe83 MS |
3627 | && mips_type_needs_double_align (arg_type)) |
3628 | { | |
3629 | if ((argreg & 1)) | |
6d82d43b | 3630 | argreg++; |
ebafbe83 MS |
3631 | } |
3632 | /* Note: Floating-point values that didn't fit into an FP | |
6d82d43b | 3633 | register are only written to memory. */ |
ebafbe83 MS |
3634 | while (len > 0) |
3635 | { | |
3636 | /* Remember if the argument was written to the stack. */ | |
3637 | int stack_used_p = 0; | |
13326b4e AC |
3638 | int partial_len = (len < mips_abi_regsize (gdbarch) |
3639 | ? len : mips_abi_regsize (gdbarch)); | |
ebafbe83 MS |
3640 | |
3641 | if (mips_debug) | |
3642 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3643 | partial_len); | |
3644 | ||
3645 | /* Write this portion of the argument to the stack. */ | |
3646 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3647 | || odd_sized_struct | |
3648 | || fp_register_arg_p (typecode, arg_type)) | |
3649 | { | |
3650 | /* Should shorter than int integer values be | |
3651 | promoted to int before being stored? */ | |
3652 | int longword_offset = 0; | |
3653 | CORE_ADDR addr; | |
3654 | stack_used_p = 1; | |
3655 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3656 | { | |
13326b4e | 3657 | if (mips_stack_argsize (gdbarch) == 8 |
480d3dd2 AC |
3658 | && (typecode == TYPE_CODE_INT |
3659 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 3660 | || typecode == TYPE_CODE_FLT) && len <= 4) |
13326b4e | 3661 | longword_offset = mips_stack_argsize (gdbarch) - len; |
ebafbe83 MS |
3662 | } |
3663 | ||
3664 | if (mips_debug) | |
3665 | { | |
3666 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3667 | paddr_nz (stack_offset)); | |
3668 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3669 | paddr_nz (longword_offset)); | |
3670 | } | |
3671 | ||
3672 | addr = sp + stack_offset + longword_offset; | |
3673 | ||
3674 | if (mips_debug) | |
3675 | { | |
3676 | int i; | |
6d82d43b | 3677 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
ebafbe83 MS |
3678 | paddr_nz (addr)); |
3679 | for (i = 0; i < partial_len; i++) | |
3680 | { | |
6d82d43b | 3681 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
3682 | val[i] & 0xff); |
3683 | } | |
3684 | } | |
3685 | write_memory (addr, val, partial_len); | |
3686 | } | |
3687 | ||
3688 | /* Note!!! This is NOT an else clause. Odd sized | |
3689 | structs may go thru BOTH paths. Floating point | |
3690 | arguments will not. */ | |
3691 | /* Write this portion of the argument to a general | |
6d82d43b | 3692 | purpose register. */ |
ebafbe83 MS |
3693 | if (argreg <= MIPS_LAST_ARG_REGNUM |
3694 | && !fp_register_arg_p (typecode, arg_type)) | |
3695 | { | |
3696 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 3697 | /* Value may need to be sign extended, because |
1b13c4f6 | 3698 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
3699 | |
3700 | /* A non-floating-point argument being passed in a | |
3701 | general register. If a struct or union, and if | |
3702 | the remaining length is smaller than the register | |
3703 | size, we have to adjust the register value on | |
3704 | big endian targets. | |
3705 | ||
3706 | It does not seem to be necessary to do the | |
3707 | same for integral types. | |
3708 | ||
3709 | Also don't do this adjustment on O64 binaries. | |
3710 | ||
3711 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3712 | outputting LE O32 with sizeof (struct) < | |
1b13c4f6 | 3713 | mips_abi_regsize(), generates a left shift as |
ebafbe83 MS |
3714 | part of storing the argument in a register a |
3715 | register (the left shift isn't generated when | |
1b13c4f6 | 3716 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
3717 | it is quite possible that this is GCC |
3718 | contradicting the LE/O32 ABI, GDB has not been | |
3719 | adjusted to accommodate this. Either someone | |
3720 | needs to demonstrate that the LE/O32 ABI | |
3721 | specifies such a left shift OR this new ABI gets | |
3722 | identified as such and GDB gets tweaked | |
3723 | accordingly. */ | |
3724 | ||
13326b4e | 3725 | if (mips_abi_regsize (gdbarch) < 8 |
ebafbe83 | 3726 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
13326b4e | 3727 | && partial_len < mips_abi_regsize (gdbarch) |
ebafbe83 MS |
3728 | && (typecode == TYPE_CODE_STRUCT || |
3729 | typecode == TYPE_CODE_UNION)) | |
13326b4e | 3730 | regval <<= ((mips_abi_regsize (gdbarch) - partial_len) * |
ebafbe83 MS |
3731 | TARGET_CHAR_BIT); |
3732 | ||
3733 | if (mips_debug) | |
3734 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3735 | argreg, | |
6d82d43b | 3736 | phex (regval, |
13326b4e | 3737 | mips_abi_regsize (gdbarch))); |
ebafbe83 MS |
3738 | write_register (argreg, regval); |
3739 | argreg++; | |
3740 | ||
3741 | /* Prevent subsequent floating point arguments from | |
3742 | being passed in floating point registers. */ | |
3743 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3744 | } | |
3745 | ||
3746 | len -= partial_len; | |
3747 | val += partial_len; | |
3748 | ||
3749 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3750 | will copy the next parameter. |
ebafbe83 | 3751 | |
6d82d43b AC |
3752 | In older ABIs, the caller reserved space for |
3753 | registers that contained arguments. This was loosely | |
3754 | refered to as their "home". Consequently, space is | |
3755 | always allocated. */ | |
ebafbe83 | 3756 | |
480d3dd2 | 3757 | stack_offset += align_up (partial_len, |
13326b4e | 3758 | mips_stack_argsize (gdbarch)); |
ebafbe83 MS |
3759 | } |
3760 | } | |
3761 | if (mips_debug) | |
3762 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3763 | } | |
3764 | ||
f10683bb | 3765 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3766 | |
ebafbe83 MS |
3767 | /* Return adjusted stack pointer. */ |
3768 | return sp; | |
3769 | } | |
3770 | ||
9c8fdbfa AC |
3771 | static enum return_value_convention |
3772 | mips_o64_return_value (struct gdbarch *gdbarch, | |
3773 | struct type *type, struct regcache *regcache, | |
47a35522 | 3774 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 3775 | { |
9c8fdbfa | 3776 | return RETURN_VALUE_STRUCT_CONVENTION; |
6d82d43b AC |
3777 | } |
3778 | ||
dd824b04 DJ |
3779 | /* Floating point register management. |
3780 | ||
3781 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
3782 | 64bit operations, these early MIPS cpus treat fp register pairs | |
3783 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
3784 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
3785 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
3786 | double precision floats into two 32-bit chunks and store them in | |
3787 | consecutive fp regs. To display 64-bit floats stored in this | |
3788 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
3789 | Throw in user-configurable endianness and you have a real mess. | |
3790 | ||
3791 | The way this works is: | |
3792 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
3793 | double-precision value will be split across two logical registers. | |
3794 | The lower-numbered logical register will hold the low-order bits, | |
3795 | regardless of the processor's endianness. | |
3796 | - If we are on a 64-bit processor, and we are looking for a | |
3797 | single-precision value, it will be in the low ordered bits | |
3798 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
3799 | save slot in memory. | |
3800 | - If we are in 64-bit mode, everything is straightforward. | |
3801 | ||
3802 | Note that this code only deals with "live" registers at the top of the | |
3803 | stack. We will attempt to deal with saved registers later, when | |
3804 | the raw/cooked register interface is in place. (We need a general | |
3805 | interface that can deal with dynamic saved register sizes -- fp | |
3806 | regs could be 32 bits wide in one frame and 64 on the frame above | |
3807 | and below). */ | |
3808 | ||
67b2c998 DJ |
3809 | static struct type * |
3810 | mips_float_register_type (void) | |
3811 | { | |
361d1df0 | 3812 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
3813 | return builtin_type_ieee_single_big; |
3814 | else | |
3815 | return builtin_type_ieee_single_little; | |
3816 | } | |
3817 | ||
3818 | static struct type * | |
3819 | mips_double_register_type (void) | |
3820 | { | |
361d1df0 | 3821 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
3822 | return builtin_type_ieee_double_big; |
3823 | else | |
3824 | return builtin_type_ieee_double_little; | |
3825 | } | |
3826 | ||
dd824b04 DJ |
3827 | /* Copy a 32-bit single-precision value from the current frame |
3828 | into rare_buffer. */ | |
3829 | ||
3830 | static void | |
e11c53d2 | 3831 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
47a35522 | 3832 | gdb_byte *rare_buffer) |
dd824b04 | 3833 | { |
719ec221 | 3834 | int raw_size = register_size (current_gdbarch, regno); |
47a35522 | 3835 | gdb_byte *raw_buffer = alloca (raw_size); |
dd824b04 | 3836 | |
e11c53d2 | 3837 | if (!frame_register_read (frame, regno, raw_buffer)) |
8a3fe4f8 | 3838 | error (_("can't read register %d (%s)"), regno, REGISTER_NAME (regno)); |
dd824b04 DJ |
3839 | if (raw_size == 8) |
3840 | { | |
3841 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 3842 | 32 bits. */ |
dd824b04 DJ |
3843 | int offset; |
3844 | ||
3845 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3846 | offset = 4; | |
3847 | else | |
3848 | offset = 0; | |
3849 | ||
3850 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
3851 | } | |
3852 | else | |
3853 | { | |
3854 | memcpy (rare_buffer, raw_buffer, 4); | |
3855 | } | |
3856 | } | |
3857 | ||
3858 | /* Copy a 64-bit double-precision value from the current frame into | |
3859 | rare_buffer. This may include getting half of it from the next | |
3860 | register. */ | |
3861 | ||
3862 | static void | |
e11c53d2 | 3863 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
47a35522 | 3864 | gdb_byte *rare_buffer) |
dd824b04 | 3865 | { |
719ec221 | 3866 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 DJ |
3867 | |
3868 | if (raw_size == 8 && !mips2_fp_compat ()) | |
3869 | { | |
3870 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 3871 | all 64 bits. */ |
e11c53d2 | 3872 | if (!frame_register_read (frame, regno, rare_buffer)) |
8a3fe4f8 | 3873 | error (_("can't read register %d (%s)"), regno, REGISTER_NAME (regno)); |
dd824b04 DJ |
3874 | } |
3875 | else | |
3876 | { | |
56cea623 | 3877 | if ((regno - mips_regnum (current_gdbarch)->fp0) & 1) |
dd824b04 | 3878 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
3879 | _("mips_read_fp_register_double: bad access to " |
3880 | "odd-numbered FP register")); | |
dd824b04 DJ |
3881 | |
3882 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 3883 | each register. */ |
dd824b04 DJ |
3884 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
3885 | { | |
e11c53d2 AC |
3886 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
3887 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 3888 | } |
361d1df0 | 3889 | else |
dd824b04 | 3890 | { |
e11c53d2 AC |
3891 | mips_read_fp_register_single (frame, regno, rare_buffer); |
3892 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
3893 | } |
3894 | } | |
3895 | } | |
3896 | ||
c906108c | 3897 | static void |
e11c53d2 AC |
3898 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
3899 | int regnum) | |
c5aa993b | 3900 | { /* do values for FP (float) regs */ |
47a35522 | 3901 | gdb_byte *raw_buffer; |
3903d437 AC |
3902 | double doub, flt1; /* doubles extracted from raw hex data */ |
3903 | int inv1, inv2; | |
c5aa993b | 3904 | |
47a35522 MK |
3905 | raw_buffer = alloca (2 * register_size (current_gdbarch, |
3906 | mips_regnum (current_gdbarch)->fp0)); | |
c906108c | 3907 | |
e11c53d2 AC |
3908 | fprintf_filtered (file, "%s:", REGISTER_NAME (regnum)); |
3909 | fprintf_filtered (file, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum)), | |
3910 | ""); | |
f0ef6b29 | 3911 | |
719ec221 | 3912 | if (register_size (current_gdbarch, regnum) == 4 || mips2_fp_compat ()) |
c906108c | 3913 | { |
f0ef6b29 KB |
3914 | /* 4-byte registers: Print hex and floating. Also print even |
3915 | numbered registers as doubles. */ | |
e11c53d2 | 3916 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
67b2c998 | 3917 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c5aa993b | 3918 | |
6d82d43b AC |
3919 | print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w', |
3920 | file); | |
dd824b04 | 3921 | |
e11c53d2 | 3922 | fprintf_filtered (file, " flt: "); |
1adad886 | 3923 | if (inv1) |
e11c53d2 | 3924 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 3925 | else |
e11c53d2 | 3926 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 3927 | |
f0ef6b29 KB |
3928 | if (regnum % 2 == 0) |
3929 | { | |
e11c53d2 | 3930 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 | 3931 | doub = unpack_double (mips_double_register_type (), raw_buffer, |
6d82d43b | 3932 | &inv2); |
1adad886 | 3933 | |
e11c53d2 | 3934 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 3935 | if (inv2) |
e11c53d2 | 3936 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 3937 | else |
e11c53d2 | 3938 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 3939 | } |
c906108c SS |
3940 | } |
3941 | else | |
dd824b04 | 3942 | { |
f0ef6b29 | 3943 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 3944 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
2f38ef89 | 3945 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c906108c | 3946 | |
e11c53d2 | 3947 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
3948 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2); |
3949 | ||
361d1df0 | 3950 | |
6d82d43b AC |
3951 | print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g', |
3952 | file); | |
f0ef6b29 | 3953 | |
e11c53d2 | 3954 | fprintf_filtered (file, " flt: "); |
1adad886 | 3955 | if (inv1) |
e11c53d2 | 3956 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 3957 | else |
e11c53d2 | 3958 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 3959 | |
e11c53d2 | 3960 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 3961 | if (inv2) |
e11c53d2 | 3962 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 3963 | else |
e11c53d2 | 3964 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
3965 | } |
3966 | } | |
3967 | ||
3968 | static void | |
e11c53d2 AC |
3969 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
3970 | int regnum, int all) | |
f0ef6b29 | 3971 | { |
a4b8ebc8 | 3972 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 3973 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
f0ef6b29 | 3974 | int offset; |
1adad886 | 3975 | |
a4b8ebc8 | 3976 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 3977 | { |
e11c53d2 | 3978 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
3979 | return; |
3980 | } | |
3981 | ||
3982 | /* Get the data in raw format. */ | |
e11c53d2 | 3983 | if (!frame_register_read (frame, regnum, raw_buffer)) |
f0ef6b29 | 3984 | { |
e11c53d2 | 3985 | fprintf_filtered (file, "%s: [Invalid]", REGISTER_NAME (regnum)); |
f0ef6b29 | 3986 | return; |
c906108c | 3987 | } |
f0ef6b29 | 3988 | |
e11c53d2 | 3989 | fputs_filtered (REGISTER_NAME (regnum), file); |
f0ef6b29 KB |
3990 | |
3991 | /* The problem with printing numeric register names (r26, etc.) is that | |
3992 | the user can't use them on input. Probably the best solution is to | |
3993 | fix it so that either the numeric or the funky (a2, etc.) names | |
3994 | are accepted on input. */ | |
3995 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 3996 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 3997 | else |
e11c53d2 | 3998 | fprintf_filtered (file, ": "); |
f0ef6b29 KB |
3999 | |
4000 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
6d82d43b AC |
4001 | offset = |
4002 | register_size (current_gdbarch, | |
4003 | regnum) - register_size (current_gdbarch, regnum); | |
f0ef6b29 KB |
4004 | else |
4005 | offset = 0; | |
4006 | ||
6d82d43b AC |
4007 | print_scalar_formatted (raw_buffer + offset, |
4008 | gdbarch_register_type (gdbarch, regnum), 'x', 0, | |
4009 | file); | |
c906108c SS |
4010 | } |
4011 | ||
f0ef6b29 KB |
4012 | /* Replacement for generic do_registers_info. |
4013 | Print regs in pretty columns. */ | |
4014 | ||
4015 | static int | |
e11c53d2 AC |
4016 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
4017 | int regnum) | |
f0ef6b29 | 4018 | { |
e11c53d2 AC |
4019 | fprintf_filtered (file, " "); |
4020 | mips_print_fp_register (file, frame, regnum); | |
4021 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
4022 | return regnum + 1; |
4023 | } | |
4024 | ||
4025 | ||
c906108c SS |
4026 | /* Print a row's worth of GP (int) registers, with name labels above */ |
4027 | ||
4028 | static int | |
e11c53d2 | 4029 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 4030 | int start_regnum) |
c906108c | 4031 | { |
a4b8ebc8 | 4032 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 4033 | /* do values for GP (int) regs */ |
47a35522 | 4034 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
d5ac5a39 | 4035 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */ |
c906108c | 4036 | int col, byte; |
a4b8ebc8 | 4037 | int regnum; |
c906108c SS |
4038 | |
4039 | /* For GP registers, we print a separate row of names above the vals */ | |
e11c53d2 | 4040 | fprintf_filtered (file, " "); |
a4b8ebc8 | 4041 | for (col = 0, regnum = start_regnum; |
6d82d43b | 4042 | col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++) |
c906108c SS |
4043 | { |
4044 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 4045 | continue; /* unused register */ |
6d82d43b AC |
4046 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
4047 | TYPE_CODE_FLT) | |
c5aa993b | 4048 | break; /* end the row: reached FP register */ |
6d82d43b | 4049 | fprintf_filtered (file, |
d5ac5a39 | 4050 | mips_abi_regsize (current_gdbarch) == 8 ? "%17s" : "%9s", |
e11c53d2 | 4051 | REGISTER_NAME (regnum)); |
c906108c SS |
4052 | col++; |
4053 | } | |
a4b8ebc8 | 4054 | /* print the R0 to R31 names */ |
20e6603c AC |
4055 | if ((start_regnum % NUM_REGS) < MIPS_NUMREGS) |
4056 | fprintf_filtered (file, "\n R%-4d", start_regnum % NUM_REGS); | |
4057 | else | |
4058 | fprintf_filtered (file, "\n "); | |
c906108c | 4059 | |
c906108c | 4060 | /* now print the values in hex, 4 or 8 to the row */ |
a4b8ebc8 | 4061 | for (col = 0, regnum = start_regnum; |
6d82d43b | 4062 | col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++) |
c906108c SS |
4063 | { |
4064 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 4065 | continue; /* unused register */ |
6d82d43b AC |
4066 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
4067 | TYPE_CODE_FLT) | |
c5aa993b | 4068 | break; /* end row: reached FP register */ |
c906108c | 4069 | /* OK: get the data in raw format. */ |
e11c53d2 | 4070 | if (!frame_register_read (frame, regnum, raw_buffer)) |
8a3fe4f8 | 4071 | error (_("can't read register %d (%s)"), regnum, REGISTER_NAME (regnum)); |
c906108c | 4072 | /* pad small registers */ |
4246e332 | 4073 | for (byte = 0; |
d5ac5a39 | 4074 | byte < (mips_abi_regsize (current_gdbarch) |
6d82d43b | 4075 | - register_size (current_gdbarch, regnum)); byte++) |
c906108c SS |
4076 | printf_filtered (" "); |
4077 | /* Now print the register value in hex, endian order. */ | |
d7449b42 | 4078 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
6d82d43b AC |
4079 | for (byte = |
4080 | register_size (current_gdbarch, | |
4081 | regnum) - register_size (current_gdbarch, regnum); | |
4082 | byte < register_size (current_gdbarch, regnum); byte++) | |
47a35522 | 4083 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
c906108c | 4084 | else |
c73e8f27 | 4085 | for (byte = register_size (current_gdbarch, regnum) - 1; |
6d82d43b | 4086 | byte >= 0; byte--) |
47a35522 | 4087 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
e11c53d2 | 4088 | fprintf_filtered (file, " "); |
c906108c SS |
4089 | col++; |
4090 | } | |
c5aa993b | 4091 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 4092 | fprintf_filtered (file, "\n"); |
c906108c SS |
4093 | |
4094 | return regnum; | |
4095 | } | |
4096 | ||
4097 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
4098 | ||
bf1f5b4c | 4099 | static void |
e11c53d2 AC |
4100 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4101 | struct frame_info *frame, int regnum, int all) | |
c906108c | 4102 | { |
c5aa993b | 4103 | if (regnum != -1) /* do one specified register */ |
c906108c | 4104 | { |
a4b8ebc8 | 4105 | gdb_assert (regnum >= NUM_REGS); |
c906108c | 4106 | if (*(REGISTER_NAME (regnum)) == '\0') |
8a3fe4f8 | 4107 | error (_("Not a valid register for the current processor type")); |
c906108c | 4108 | |
e11c53d2 AC |
4109 | mips_print_register (file, frame, regnum, 0); |
4110 | fprintf_filtered (file, "\n"); | |
c906108c | 4111 | } |
c5aa993b JM |
4112 | else |
4113 | /* do all (or most) registers */ | |
c906108c | 4114 | { |
a4b8ebc8 AC |
4115 | regnum = NUM_REGS; |
4116 | while (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
c906108c | 4117 | { |
6d82d43b AC |
4118 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
4119 | TYPE_CODE_FLT) | |
e11c53d2 AC |
4120 | { |
4121 | if (all) /* true for "INFO ALL-REGISTERS" command */ | |
4122 | regnum = print_fp_register_row (file, frame, regnum); | |
4123 | else | |
4124 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
4125 | } | |
c906108c | 4126 | else |
e11c53d2 | 4127 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
4128 | } |
4129 | } | |
4130 | } | |
4131 | ||
c906108c SS |
4132 | /* Is this a branch with a delay slot? */ |
4133 | ||
c906108c | 4134 | static int |
acdb74a0 | 4135 | is_delayed (unsigned long insn) |
c906108c SS |
4136 | { |
4137 | int i; | |
4138 | for (i = 0; i < NUMOPCODES; ++i) | |
4139 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4140 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4141 | break; | |
4142 | return (i < NUMOPCODES | |
4143 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4144 | | INSN_COND_BRANCH_DELAY | |
4145 | | INSN_COND_BRANCH_LIKELY))); | |
4146 | } | |
4147 | ||
4148 | int | |
3352ef37 AC |
4149 | mips_single_step_through_delay (struct gdbarch *gdbarch, |
4150 | struct frame_info *frame) | |
c906108c | 4151 | { |
3352ef37 | 4152 | CORE_ADDR pc = get_frame_pc (frame); |
47a35522 | 4153 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
4154 | |
4155 | /* There is no branch delay slot on MIPS16. */ | |
0fe7e7c8 | 4156 | if (mips_pc_is_mips16 (pc)) |
c906108c SS |
4157 | return 0; |
4158 | ||
06648491 MK |
4159 | if (!breakpoint_here_p (pc + 4)) |
4160 | return 0; | |
4161 | ||
3352ef37 AC |
4162 | if (!safe_frame_unwind_memory (frame, pc, buf, sizeof buf)) |
4163 | /* If error reading memory, guess that it is not a delayed | |
4164 | branch. */ | |
c906108c | 4165 | return 0; |
4c7d22cb | 4166 | return is_delayed (extract_unsigned_integer (buf, sizeof buf)); |
c906108c SS |
4167 | } |
4168 | ||
6d82d43b AC |
4169 | /* To skip prologues, I use this predicate. Returns either PC itself |
4170 | if the code at PC does not look like a function prologue; otherwise | |
4171 | returns an address that (if we're lucky) follows the prologue. If | |
4172 | LENIENT, then we must skip everything which is involved in setting | |
4173 | up the frame (it's OK to skip more, just so long as we don't skip | |
4174 | anything which might clobber the registers which are being saved. | |
4175 | We must skip more in the case where part of the prologue is in the | |
4176 | delay slot of a non-prologue instruction). */ | |
4177 | ||
4178 | static CORE_ADDR | |
4179 | mips_skip_prologue (CORE_ADDR pc) | |
4180 | { | |
8b622e6a AC |
4181 | CORE_ADDR limit_pc; |
4182 | CORE_ADDR func_addr; | |
4183 | ||
6d82d43b AC |
4184 | /* See if we can determine the end of the prologue via the symbol table. |
4185 | If so, then return either PC, or the PC after the prologue, whichever | |
4186 | is greater. */ | |
8b622e6a AC |
4187 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
4188 | { | |
4189 | CORE_ADDR post_prologue_pc = skip_prologue_using_sal (func_addr); | |
4190 | if (post_prologue_pc != 0) | |
4191 | return max (pc, post_prologue_pc); | |
4192 | } | |
6d82d43b AC |
4193 | |
4194 | /* Can't determine prologue from the symbol table, need to examine | |
4195 | instructions. */ | |
4196 | ||
98b4dd94 JB |
4197 | /* Find an upper limit on the function prologue using the debug |
4198 | information. If the debug information could not be used to provide | |
4199 | that bound, then use an arbitrary large number as the upper bound. */ | |
4200 | limit_pc = skip_prologue_using_sal (pc); | |
4201 | if (limit_pc == 0) | |
4202 | limit_pc = pc + 100; /* Magic. */ | |
4203 | ||
0fe7e7c8 | 4204 | if (mips_pc_is_mips16 (pc)) |
a65bbe44 | 4205 | return mips16_scan_prologue (pc, limit_pc, NULL, NULL); |
6d82d43b | 4206 | else |
a65bbe44 | 4207 | return mips32_scan_prologue (pc, limit_pc, NULL, NULL); |
88658117 AC |
4208 | } |
4209 | ||
a5ea2558 AC |
4210 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
4211 | used for all MIPS-specific commands. */ | |
4212 | ||
a5ea2558 | 4213 | static void |
acdb74a0 | 4214 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
4215 | { |
4216 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
4217 | } | |
4218 | ||
a5ea2558 | 4219 | static void |
acdb74a0 | 4220 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 4221 | { |
6d82d43b AC |
4222 | printf_unfiltered |
4223 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
4224 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
4225 | } | |
4226 | ||
c906108c SS |
4227 | /* Commands to show/set the MIPS FPU type. */ |
4228 | ||
c906108c | 4229 | static void |
acdb74a0 | 4230 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 4231 | { |
c906108c SS |
4232 | char *fpu; |
4233 | switch (MIPS_FPU_TYPE) | |
4234 | { | |
4235 | case MIPS_FPU_SINGLE: | |
4236 | fpu = "single-precision"; | |
4237 | break; | |
4238 | case MIPS_FPU_DOUBLE: | |
4239 | fpu = "double-precision"; | |
4240 | break; | |
4241 | case MIPS_FPU_NONE: | |
4242 | fpu = "absent (none)"; | |
4243 | break; | |
93d56215 | 4244 | default: |
e2e0b3e5 | 4245 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c SS |
4246 | } |
4247 | if (mips_fpu_type_auto) | |
6d82d43b AC |
4248 | printf_unfiltered |
4249 | ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
4250 | fpu); | |
c906108c | 4251 | else |
6d82d43b AC |
4252 | printf_unfiltered |
4253 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
4254 | } |
4255 | ||
4256 | ||
c906108c | 4257 | static void |
acdb74a0 | 4258 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 4259 | { |
6d82d43b AC |
4260 | printf_unfiltered |
4261 | ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
4262 | show_mipsfpu_command (args, from_tty); |
4263 | } | |
4264 | ||
c906108c | 4265 | static void |
acdb74a0 | 4266 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 4267 | { |
8d5838b5 AC |
4268 | struct gdbarch_info info; |
4269 | gdbarch_info_init (&info); | |
c906108c SS |
4270 | mips_fpu_type = MIPS_FPU_SINGLE; |
4271 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4272 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4273 | instead of relying on globals. Doing that would let generic code | |
4274 | handle the search for this specific architecture. */ | |
4275 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4276 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4277 | } |
4278 | ||
c906108c | 4279 | static void |
acdb74a0 | 4280 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 4281 | { |
8d5838b5 AC |
4282 | struct gdbarch_info info; |
4283 | gdbarch_info_init (&info); | |
c906108c SS |
4284 | mips_fpu_type = MIPS_FPU_DOUBLE; |
4285 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4286 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4287 | instead of relying on globals. Doing that would let generic code | |
4288 | handle the search for this specific architecture. */ | |
4289 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4290 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4291 | } |
4292 | ||
c906108c | 4293 | static void |
acdb74a0 | 4294 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 4295 | { |
8d5838b5 AC |
4296 | struct gdbarch_info info; |
4297 | gdbarch_info_init (&info); | |
c906108c SS |
4298 | mips_fpu_type = MIPS_FPU_NONE; |
4299 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4300 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4301 | instead of relying on globals. Doing that would let generic code | |
4302 | handle the search for this specific architecture. */ | |
4303 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4304 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4305 | } |
4306 | ||
c906108c | 4307 | static void |
acdb74a0 | 4308 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
4309 | { |
4310 | mips_fpu_type_auto = 1; | |
4311 | } | |
4312 | ||
c906108c | 4313 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
4314 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
4315 | the relevant processor still exists (it dates back to '94) and | |
4316 | secondly this is not the way to do this. The processor type should | |
4317 | be set by forcing an architecture change. */ | |
c906108c | 4318 | |
691c0433 AC |
4319 | void |
4320 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 4321 | { |
691c0433 | 4322 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
4323 | CORE_ADDR prid; |
4324 | ||
a5c9623c | 4325 | prid = read_register (MIPS_PRID_REGNUM); |
c906108c SS |
4326 | |
4327 | if ((prid & ~0xf) == 0x700) | |
691c0433 | 4328 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
4329 | } |
4330 | ||
4331 | /* Just like reinit_frame_cache, but with the right arguments to be | |
4332 | callable as an sfunc. */ | |
4333 | ||
4334 | static void | |
acdb74a0 AC |
4335 | reinit_frame_cache_sfunc (char *args, int from_tty, |
4336 | struct cmd_list_element *c) | |
c906108c SS |
4337 | { |
4338 | reinit_frame_cache (); | |
4339 | } | |
4340 | ||
a89aa300 AC |
4341 | static int |
4342 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 4343 | { |
e5ab0dce | 4344 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c | 4345 | |
d31431ed AC |
4346 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
4347 | disassembler needs to be able to locally determine the ISA, and | |
4348 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
4349 | work. */ | |
ec4045ea AC |
4350 | if (mips_pc_is_mips16 (memaddr)) |
4351 | info->mach = bfd_mach_mips16; | |
c906108c SS |
4352 | |
4353 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 4354 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 4355 | |
e5ab0dce | 4356 | /* Set the disassembler options. */ |
6d82d43b | 4357 | if (tdep->mips_abi == MIPS_ABI_N32 || tdep->mips_abi == MIPS_ABI_N64) |
e5ab0dce AC |
4358 | { |
4359 | /* Set up the disassembler info, so that we get the right | |
6d82d43b | 4360 | register names from libopcodes. */ |
e5ab0dce AC |
4361 | if (tdep->mips_abi == MIPS_ABI_N32) |
4362 | info->disassembler_options = "gpr-names=n32"; | |
4363 | else | |
4364 | info->disassembler_options = "gpr-names=64"; | |
4365 | info->flavour = bfd_target_elf_flavour; | |
4366 | } | |
4367 | else | |
4368 | /* This string is not recognized explicitly by the disassembler, | |
4369 | but it tells the disassembler to not try to guess the ABI from | |
4370 | the bfd elf headers, such that, if the user overrides the ABI | |
4371 | of a program linked as NewABI, the disassembly will follow the | |
4372 | register naming conventions specified by the user. */ | |
4373 | info->disassembler_options = "gpr-names=32"; | |
4374 | ||
c906108c | 4375 | /* Call the appropriate disassembler based on the target endian-ness. */ |
d7449b42 | 4376 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
4377 | return print_insn_big_mips (memaddr, info); |
4378 | else | |
4379 | return print_insn_little_mips (memaddr, info); | |
4380 | } | |
4381 | ||
c906108c SS |
4382 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program |
4383 | counter value to determine whether a 16- or 32-bit breakpoint should be | |
4384 | used. It returns a pointer to a string of bytes that encode a breakpoint | |
4385 | instruction, stores the length of the string to *lenptr, and adjusts pc | |
4386 | (if necessary) to point to the actual memory location where the | |
4387 | breakpoint should be inserted. */ | |
4388 | ||
47a35522 | 4389 | static const gdb_byte * |
6d82d43b | 4390 | mips_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c | 4391 | { |
d7449b42 | 4392 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c | 4393 | { |
0fe7e7c8 | 4394 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 4395 | { |
47a35522 | 4396 | static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
95404a3e | 4397 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 4398 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
4399 | return mips16_big_breakpoint; |
4400 | } | |
4401 | else | |
4402 | { | |
aaab4dba AC |
4403 | /* The IDT board uses an unusual breakpoint value, and |
4404 | sometimes gets confused when it sees the usual MIPS | |
4405 | breakpoint instruction. */ | |
47a35522 MK |
4406 | static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
4407 | static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
4408 | static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
c906108c | 4409 | |
c5aa993b | 4410 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
4411 | |
4412 | if (strcmp (target_shortname, "mips") == 0) | |
4413 | return idt_big_breakpoint; | |
4414 | else if (strcmp (target_shortname, "ddb") == 0 | |
4415 | || strcmp (target_shortname, "pmon") == 0 | |
4416 | || strcmp (target_shortname, "lsi") == 0) | |
4417 | return pmon_big_breakpoint; | |
4418 | else | |
4419 | return big_breakpoint; | |
4420 | } | |
4421 | } | |
4422 | else | |
4423 | { | |
0fe7e7c8 | 4424 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 4425 | { |
47a35522 | 4426 | static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
95404a3e | 4427 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 4428 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
4429 | return mips16_little_breakpoint; |
4430 | } | |
4431 | else | |
4432 | { | |
47a35522 MK |
4433 | static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
4434 | static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
4435 | static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 4436 | |
c5aa993b | 4437 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
4438 | |
4439 | if (strcmp (target_shortname, "mips") == 0) | |
4440 | return idt_little_breakpoint; | |
4441 | else if (strcmp (target_shortname, "ddb") == 0 | |
4442 | || strcmp (target_shortname, "pmon") == 0 | |
4443 | || strcmp (target_shortname, "lsi") == 0) | |
4444 | return pmon_little_breakpoint; | |
4445 | else | |
4446 | return little_breakpoint; | |
4447 | } | |
4448 | } | |
4449 | } | |
4450 | ||
4451 | /* If PC is in a mips16 call or return stub, return the address of the target | |
4452 | PC, which is either the callee or the caller. There are several | |
4453 | cases which must be handled: | |
4454 | ||
4455 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 4456 | target PC is in $31 ($ra). |
c906108c | 4457 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 4458 | and the target PC is in $2. |
c906108c | 4459 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
4460 | before the jal instruction, this is effectively a call stub |
4461 | and the the target PC is in $2. Otherwise this is effectively | |
4462 | a return stub and the target PC is in $18. | |
c906108c SS |
4463 | |
4464 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
e7d6a6d2 | 4465 | gory details. */ |
c906108c | 4466 | |
757a7cc6 | 4467 | static CORE_ADDR |
e7d6a6d2 | 4468 | mips_skip_trampoline_code (CORE_ADDR pc) |
c906108c SS |
4469 | { |
4470 | char *name; | |
4471 | CORE_ADDR start_addr; | |
4472 | ||
4473 | /* Find the starting address and name of the function containing the PC. */ | |
4474 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
4475 | return 0; | |
4476 | ||
4477 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
4478 | target PC is in $31 ($ra). */ | |
4479 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
4480 | || strcmp (name, "__mips16_ret_df") == 0) | |
4c7d22cb | 4481 | return read_signed_register (MIPS_RA_REGNUM); |
c906108c SS |
4482 | |
4483 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
4484 | { | |
4485 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
4486 | and the target PC is in $2. */ | |
4487 | if (name[19] >= '0' && name[19] <= '9') | |
6c997a34 | 4488 | return read_signed_register (2); |
c906108c SS |
4489 | |
4490 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
4491 | before the jal instruction, this is effectively a call stub |
4492 | and the the target PC is in $2. Otherwise this is effectively | |
4493 | a return stub and the target PC is in $18. */ | |
c906108c SS |
4494 | else if (name[19] == 's' || name[19] == 'd') |
4495 | { | |
4496 | if (pc == start_addr) | |
4497 | { | |
4498 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
4499 | stub. Such a stub for a function bar might have a name |
4500 | like __fn_stub_bar, and might look like this: | |
4501 | mfc1 $4,$f13 | |
4502 | mfc1 $5,$f12 | |
4503 | mfc1 $6,$f15 | |
4504 | mfc1 $7,$f14 | |
4505 | la $1,bar (becomes a lui/addiu pair) | |
4506 | jr $1 | |
4507 | So scan down to the lui/addi and extract the target | |
4508 | address from those two instructions. */ | |
c906108c | 4509 | |
6c997a34 | 4510 | CORE_ADDR target_pc = read_signed_register (2); |
d37cca3d | 4511 | ULONGEST inst; |
c906108c SS |
4512 | int i; |
4513 | ||
4514 | /* See if the name of the target function is __fn_stub_*. */ | |
6d82d43b AC |
4515 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == |
4516 | 0) | |
c906108c SS |
4517 | return target_pc; |
4518 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
4519 | && strcmp (name, "etext") != 0 | |
4520 | && strcmp (name, "_etext") != 0) | |
4521 | return target_pc; | |
4522 | ||
4523 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
4524 | The limit on the search is arbitrarily set to 20 |
4525 | instructions. FIXME. */ | |
95ac2dcf | 4526 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSN32_SIZE) |
c906108c | 4527 | { |
c5aa993b JM |
4528 | inst = mips_fetch_instruction (target_pc); |
4529 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
4530 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
4531 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
4532 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
4533 | } |
4534 | ||
4535 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
4536 | return target_pc; | |
4537 | } | |
4538 | else | |
4539 | /* This is the 'return' part of a call stub. The return | |
4540 | address is in $r18. */ | |
6c997a34 | 4541 | return read_signed_register (18); |
c906108c SS |
4542 | } |
4543 | } | |
c5aa993b | 4544 | return 0; /* not a stub */ |
c906108c SS |
4545 | } |
4546 | ||
a4b8ebc8 AC |
4547 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
4548 | [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */ | |
88c72b7d AC |
4549 | |
4550 | static int | |
4551 | mips_stab_reg_to_regnum (int num) | |
4552 | { | |
a4b8ebc8 | 4553 | int regnum; |
2f38ef89 | 4554 | if (num >= 0 && num < 32) |
a4b8ebc8 | 4555 | regnum = num; |
2f38ef89 | 4556 | else if (num >= 38 && num < 70) |
56cea623 | 4557 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 38; |
040b99fd | 4558 | else if (num == 70) |
56cea623 | 4559 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 4560 | else if (num == 71) |
56cea623 | 4561 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 4562 | else |
a4b8ebc8 AC |
4563 | /* This will hopefully (eventually) provoke a warning. Should |
4564 | we be calling complaint() here? */ | |
4565 | return NUM_REGS + NUM_PSEUDO_REGS; | |
4566 | return NUM_REGS + regnum; | |
88c72b7d AC |
4567 | } |
4568 | ||
2f38ef89 | 4569 | |
a4b8ebc8 AC |
4570 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
4571 | NUM_REGS .. 2 * NUM_REGS) REGNUM. */ | |
88c72b7d AC |
4572 | |
4573 | static int | |
2f38ef89 | 4574 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num) |
88c72b7d | 4575 | { |
a4b8ebc8 | 4576 | int regnum; |
2f38ef89 | 4577 | if (num >= 0 && num < 32) |
a4b8ebc8 | 4578 | regnum = num; |
2f38ef89 | 4579 | else if (num >= 32 && num < 64) |
56cea623 | 4580 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 32; |
040b99fd | 4581 | else if (num == 64) |
56cea623 | 4582 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 4583 | else if (num == 65) |
56cea623 | 4584 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 4585 | else |
a4b8ebc8 AC |
4586 | /* This will hopefully (eventually) provoke a warning. Should we |
4587 | be calling complaint() here? */ | |
4588 | return NUM_REGS + NUM_PSEUDO_REGS; | |
4589 | return NUM_REGS + regnum; | |
4590 | } | |
4591 | ||
4592 | static int | |
4593 | mips_register_sim_regno (int regnum) | |
4594 | { | |
4595 | /* Only makes sense to supply raw registers. */ | |
4596 | gdb_assert (regnum >= 0 && regnum < NUM_REGS); | |
4597 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to | |
4598 | decide if it is valid. Should instead define a standard sim/gdb | |
4599 | register numbering scheme. */ | |
4600 | if (REGISTER_NAME (NUM_REGS + regnum) != NULL | |
4601 | && REGISTER_NAME (NUM_REGS + regnum)[0] != '\0') | |
4602 | return regnum; | |
4603 | else | |
6d82d43b | 4604 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
4605 | } |
4606 | ||
2f38ef89 | 4607 | |
fc0c74b1 AC |
4608 | /* Convert an integer into an address. By first converting the value |
4609 | into a pointer and then extracting it signed, the address is | |
4610 | guarenteed to be correctly sign extended. */ | |
4611 | ||
4612 | static CORE_ADDR | |
79dd2d24 | 4613 | mips_integer_to_address (struct gdbarch *gdbarch, |
870cd05e | 4614 | struct type *type, const gdb_byte *buf) |
fc0c74b1 | 4615 | { |
47a35522 | 4616 | gdb_byte *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr)); |
fc0c74b1 AC |
4617 | LONGEST val = unpack_long (type, buf); |
4618 | store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val); | |
4619 | return extract_signed_integer (tmp, | |
4620 | TYPE_LENGTH (builtin_type_void_data_ptr)); | |
4621 | } | |
4622 | ||
caaa3122 DJ |
4623 | static void |
4624 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
4625 | { | |
4626 | enum mips_abi *abip = (enum mips_abi *) obj; | |
4627 | const char *name = bfd_get_section_name (abfd, sect); | |
4628 | ||
4629 | if (*abip != MIPS_ABI_UNKNOWN) | |
4630 | return; | |
4631 | ||
4632 | if (strncmp (name, ".mdebug.", 8) != 0) | |
4633 | return; | |
4634 | ||
4635 | if (strcmp (name, ".mdebug.abi32") == 0) | |
4636 | *abip = MIPS_ABI_O32; | |
4637 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
4638 | *abip = MIPS_ABI_N32; | |
62a49b2c | 4639 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 4640 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
4641 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
4642 | *abip = MIPS_ABI_O64; | |
4643 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
4644 | *abip = MIPS_ABI_EABI32; | |
4645 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
4646 | *abip = MIPS_ABI_EABI64; | |
4647 | else | |
8a3fe4f8 | 4648 | warning (_("unsupported ABI %s."), name + 8); |
caaa3122 DJ |
4649 | } |
4650 | ||
2e4ebe70 DJ |
4651 | static enum mips_abi |
4652 | global_mips_abi (void) | |
4653 | { | |
4654 | int i; | |
4655 | ||
4656 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
4657 | if (mips_abi_strings[i] == mips_abi_string) | |
4658 | return (enum mips_abi) i; | |
4659 | ||
e2e0b3e5 | 4660 | internal_error (__FILE__, __LINE__, _("unknown ABI string")); |
2e4ebe70 DJ |
4661 | } |
4662 | ||
c2d11a7d | 4663 | static struct gdbarch * |
6d82d43b | 4664 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 4665 | { |
c2d11a7d JM |
4666 | struct gdbarch *gdbarch; |
4667 | struct gdbarch_tdep *tdep; | |
4668 | int elf_flags; | |
2e4ebe70 | 4669 | enum mips_abi mips_abi, found_abi, wanted_abi; |
a4b8ebc8 | 4670 | int num_regs; |
8d5838b5 | 4671 | enum mips_fpu_type fpu_type; |
c2d11a7d | 4672 | |
ec03c1ac AC |
4673 | /* First of all, extract the elf_flags, if available. */ |
4674 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
4675 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
4676 | else if (arches != NULL) |
4677 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
4678 | else |
4679 | elf_flags = 0; | |
4680 | if (gdbarch_debug) | |
4681 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 4682 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 4683 | |
102182a9 | 4684 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
4685 | switch ((elf_flags & EF_MIPS_ABI)) |
4686 | { | |
4687 | case E_MIPS_ABI_O32: | |
ec03c1ac | 4688 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
4689 | break; |
4690 | case E_MIPS_ABI_O64: | |
ec03c1ac | 4691 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
4692 | break; |
4693 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 4694 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
4695 | break; |
4696 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 4697 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
4698 | break; |
4699 | default: | |
acdb74a0 | 4700 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 4701 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 4702 | else |
ec03c1ac | 4703 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
4704 | break; |
4705 | } | |
acdb74a0 | 4706 | |
caaa3122 | 4707 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
4708 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
4709 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 4710 | |
dc305454 | 4711 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
4712 | MIPS architecture (if there is one). */ |
4713 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
4714 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 4715 | |
32a6503c | 4716 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 4717 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
4718 | && info.bfd_arch_info != NULL |
4719 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
4720 | { | |
4721 | switch (info.bfd_arch_info->mach) | |
4722 | { | |
4723 | case bfd_mach_mips3900: | |
ec03c1ac | 4724 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
4725 | break; |
4726 | case bfd_mach_mips4100: | |
4727 | case bfd_mach_mips5000: | |
ec03c1ac | 4728 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 4729 | break; |
1d06468c EZ |
4730 | case bfd_mach_mips8000: |
4731 | case bfd_mach_mips10000: | |
32a6503c KB |
4732 | /* On Irix, ELF64 executables use the N64 ABI. The |
4733 | pseudo-sections which describe the ABI aren't present | |
4734 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
4735 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
4736 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 4737 | found_abi = MIPS_ABI_N64; |
28d169de | 4738 | else |
ec03c1ac | 4739 | found_abi = MIPS_ABI_N32; |
1d06468c | 4740 | break; |
bf64bfd6 AC |
4741 | } |
4742 | } | |
2e4ebe70 | 4743 | |
ec03c1ac AC |
4744 | if (gdbarch_debug) |
4745 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
4746 | found_abi); | |
4747 | ||
4748 | /* What has the user specified from the command line? */ | |
4749 | wanted_abi = global_mips_abi (); | |
4750 | if (gdbarch_debug) | |
4751 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
4752 | wanted_abi); | |
2e4ebe70 DJ |
4753 | |
4754 | /* Now that we have found what the ABI for this binary would be, | |
4755 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
4756 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
4757 | mips_abi = wanted_abi; | |
ec03c1ac AC |
4758 | else if (found_abi != MIPS_ABI_UNKNOWN) |
4759 | mips_abi = found_abi; | |
4760 | else | |
4761 | mips_abi = MIPS_ABI_O32; | |
4762 | if (gdbarch_debug) | |
4763 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
4764 | mips_abi); | |
2e4ebe70 | 4765 | |
ec03c1ac | 4766 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 4767 | if (gdbarch_debug) |
ec03c1ac AC |
4768 | fprintf_unfiltered (gdb_stdlog, |
4769 | "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n", | |
4770 | mips64_transfers_32bit_regs_p); | |
0dadbba0 | 4771 | |
8d5838b5 AC |
4772 | /* Determine the MIPS FPU type. */ |
4773 | if (!mips_fpu_type_auto) | |
4774 | fpu_type = mips_fpu_type; | |
4775 | else if (info.bfd_arch_info != NULL | |
4776 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
4777 | switch (info.bfd_arch_info->mach) | |
4778 | { | |
4779 | case bfd_mach_mips3900: | |
4780 | case bfd_mach_mips4100: | |
4781 | case bfd_mach_mips4111: | |
a9d61c86 | 4782 | case bfd_mach_mips4120: |
8d5838b5 AC |
4783 | fpu_type = MIPS_FPU_NONE; |
4784 | break; | |
4785 | case bfd_mach_mips4650: | |
4786 | fpu_type = MIPS_FPU_SINGLE; | |
4787 | break; | |
4788 | default: | |
4789 | fpu_type = MIPS_FPU_DOUBLE; | |
4790 | break; | |
4791 | } | |
4792 | else if (arches != NULL) | |
4793 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
4794 | else | |
4795 | fpu_type = MIPS_FPU_DOUBLE; | |
4796 | if (gdbarch_debug) | |
4797 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 4798 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 4799 | |
c2d11a7d JM |
4800 | /* try to find a pre-existing architecture */ |
4801 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
4802 | arches != NULL; | |
4803 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
4804 | { | |
4805 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 4806 | using. */ |
9103eae0 | 4807 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 4808 | continue; |
9103eae0 | 4809 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 4810 | continue; |
719ec221 AC |
4811 | /* Need to be pedantic about which register virtual size is |
4812 | used. */ | |
4813 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
4814 | != mips64_transfers_32bit_regs_p) | |
4815 | continue; | |
8d5838b5 AC |
4816 | /* Be pedantic about which FPU is selected. */ |
4817 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
4818 | continue; | |
4be87837 | 4819 | return arches->gdbarch; |
c2d11a7d JM |
4820 | } |
4821 | ||
102182a9 | 4822 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
4823 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
4824 | gdbarch = gdbarch_alloc (&info, tdep); | |
4825 | tdep->elf_flags = elf_flags; | |
719ec221 | 4826 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
4827 | tdep->found_abi = found_abi; |
4828 | tdep->mips_abi = mips_abi; | |
8d5838b5 | 4829 | tdep->mips_fpu_type = fpu_type; |
c2d11a7d | 4830 | |
102182a9 | 4831 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
4832 | set_gdbarch_short_bit (gdbarch, 16); |
4833 | set_gdbarch_int_bit (gdbarch, 32); | |
4834 | set_gdbarch_float_bit (gdbarch, 32); | |
4835 | set_gdbarch_double_bit (gdbarch, 64); | |
4836 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
4837 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
4838 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
4839 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 4840 | |
6d82d43b | 4841 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
4842 | mips_elf_make_msymbol_special); |
4843 | ||
16e109ca | 4844 | /* Fill in the OS dependant register numbers and names. */ |
56cea623 | 4845 | { |
16e109ca | 4846 | const char **reg_names; |
56cea623 AC |
4847 | struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, |
4848 | struct mips_regnum); | |
56cea623 AC |
4849 | if (info.osabi == GDB_OSABI_IRIX) |
4850 | { | |
4851 | regnum->fp0 = 32; | |
4852 | regnum->pc = 64; | |
4853 | regnum->cause = 65; | |
4854 | regnum->badvaddr = 66; | |
4855 | regnum->hi = 67; | |
4856 | regnum->lo = 68; | |
4857 | regnum->fp_control_status = 69; | |
4858 | regnum->fp_implementation_revision = 70; | |
4859 | num_regs = 71; | |
16e109ca | 4860 | reg_names = mips_irix_reg_names; |
56cea623 AC |
4861 | } |
4862 | else | |
4863 | { | |
4864 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
4865 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
4866 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
4867 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
4868 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
4869 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
4870 | regnum->fp_control_status = 70; | |
4871 | regnum->fp_implementation_revision = 71; | |
4872 | num_regs = 90; | |
16e109ca AC |
4873 | if (info.bfd_arch_info != NULL |
4874 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
4875 | reg_names = mips_tx39_reg_names; | |
4876 | else | |
4877 | reg_names = mips_generic_reg_names; | |
56cea623 AC |
4878 | } |
4879 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been | |
4880 | replaced by read_pc? */ | |
f10683bb MH |
4881 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); |
4882 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
56cea623 AC |
4883 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
4884 | set_gdbarch_num_regs (gdbarch, num_regs); | |
4885 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
16e109ca AC |
4886 | set_gdbarch_register_name (gdbarch, mips_register_name); |
4887 | tdep->mips_processor_reg_names = reg_names; | |
4888 | tdep->regnum = regnum; | |
56cea623 | 4889 | } |
fe29b929 | 4890 | |
0dadbba0 | 4891 | switch (mips_abi) |
c2d11a7d | 4892 | { |
0dadbba0 | 4893 | case MIPS_ABI_O32: |
25ab4790 | 4894 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 4895 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
4c7d22cb | 4896 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 4897 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 4898 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
4899 | set_gdbarch_long_bit (gdbarch, 32); |
4900 | set_gdbarch_ptr_bit (gdbarch, 32); | |
4901 | set_gdbarch_long_long_bit (gdbarch, 64); | |
4902 | break; | |
0dadbba0 | 4903 | case MIPS_ABI_O64: |
25ab4790 | 4904 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
9c8fdbfa | 4905 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
4c7d22cb | 4906 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 4907 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 4908 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
4909 | set_gdbarch_long_bit (gdbarch, 32); |
4910 | set_gdbarch_ptr_bit (gdbarch, 32); | |
4911 | set_gdbarch_long_long_bit (gdbarch, 64); | |
4912 | break; | |
0dadbba0 | 4913 | case MIPS_ABI_EABI32: |
25ab4790 | 4914 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 4915 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 4916 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 4917 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 4918 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
4919 | set_gdbarch_long_bit (gdbarch, 32); |
4920 | set_gdbarch_ptr_bit (gdbarch, 32); | |
4921 | set_gdbarch_long_long_bit (gdbarch, 64); | |
4922 | break; | |
0dadbba0 | 4923 | case MIPS_ABI_EABI64: |
25ab4790 | 4924 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 4925 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 4926 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 4927 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 4928 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
4929 | set_gdbarch_long_bit (gdbarch, 64); |
4930 | set_gdbarch_ptr_bit (gdbarch, 64); | |
4931 | set_gdbarch_long_long_bit (gdbarch, 64); | |
4932 | break; | |
0dadbba0 | 4933 | case MIPS_ABI_N32: |
25ab4790 | 4934 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 4935 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 4936 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 4937 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 4938 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
4939 | set_gdbarch_long_bit (gdbarch, 32); |
4940 | set_gdbarch_ptr_bit (gdbarch, 32); | |
4941 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 JB |
4942 | set_gdbarch_long_double_bit (gdbarch, 128); |
4943 | set_gdbarch_long_double_format (gdbarch, | |
4944 | &floatformat_n32n64_long_double_big); | |
28d169de KB |
4945 | break; |
4946 | case MIPS_ABI_N64: | |
25ab4790 | 4947 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 4948 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 4949 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 4950 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
4951 | tdep->default_mask_address_p = 0; |
4952 | set_gdbarch_long_bit (gdbarch, 64); | |
4953 | set_gdbarch_ptr_bit (gdbarch, 64); | |
4954 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 JB |
4955 | set_gdbarch_long_double_bit (gdbarch, 128); |
4956 | set_gdbarch_long_double_format (gdbarch, | |
4957 | &floatformat_n32n64_long_double_big); | |
0dadbba0 | 4958 | break; |
c2d11a7d | 4959 | default: |
e2e0b3e5 | 4960 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); |
c2d11a7d JM |
4961 | } |
4962 | ||
a5ea2558 AC |
4963 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
4964 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
4965 | comment: | |
4966 | ||
4967 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
4968 | flag in object files because to do so would make it impossible to | |
102182a9 | 4969 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 4970 | unnecessarily restrictive. |
361d1df0 | 4971 | |
a5ea2558 AC |
4972 | We could solve this problem by adding "-gp32" multilibs to gcc, |
4973 | but to set this flag before gcc is built with such multilibs will | |
4974 | break too many systems.'' | |
4975 | ||
4976 | But even more unhelpfully, the default linker output target for | |
4977 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
4978 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 4979 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
4980 | this flag to detect 32-bit mode would do the wrong thing given |
4981 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 4982 | as 32-bit programs by default. */ |
a5ea2558 | 4983 | |
6c997a34 | 4984 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 4985 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
bcb0cc15 | 4986 | set_gdbarch_read_sp (gdbarch, mips_read_sp); |
c2d11a7d | 4987 | |
102182a9 MS |
4988 | /* Add/remove bits from an address. The MIPS needs be careful to |
4989 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
4990 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
4991 | ||
58dfe9ff AC |
4992 | /* Unwind the frame. */ |
4993 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
edfae063 | 4994 | set_gdbarch_unwind_dummy_id (gdbarch, mips_unwind_dummy_id); |
10312cc4 | 4995 | |
102182a9 | 4996 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 4997 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
4998 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
4999 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
5000 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, | |
5001 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
5002 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, | |
5003 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 5004 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 5005 | |
c2d11a7d JM |
5006 | /* MIPS version of CALL_DUMMY */ |
5007 | ||
9710e734 AC |
5008 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
5009 | replaced by a command, and all targets will default to on stack | |
5010 | (regardless of the stack's execute status). */ | |
5011 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
dc604539 | 5012 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 5013 | |
87783b8b AC |
5014 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
5015 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
5016 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
5017 | ||
f7b9e9fc AC |
5018 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
5019 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
f7b9e9fc AC |
5020 | |
5021 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 5022 | |
fc0c74b1 AC |
5023 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
5024 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
5025 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 5026 | |
a4b8ebc8 | 5027 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 5028 | |
e11c53d2 | 5029 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 5030 | |
e5ab0dce AC |
5031 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); |
5032 | ||
3a3bc038 AC |
5033 | /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT, |
5034 | HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT | |
5035 | need to all be folded into the target vector. Since they are | |
5036 | being used as guards for STOPPED_BY_WATCHPOINT, why not have | |
5037 | STOPPED_BY_WATCHPOINT return the type of watchpoint that the code | |
5038 | is sitting on? */ | |
5039 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
5040 | ||
e7d6a6d2 | 5041 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
757a7cc6 | 5042 | |
3352ef37 AC |
5043 | set_gdbarch_single_step_through_delay (gdbarch, mips_single_step_through_delay); |
5044 | ||
6de918a6 DJ |
5045 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
5046 | gdbarch_init_osabi (info, gdbarch); | |
757a7cc6 | 5047 | |
5792a79b | 5048 | /* Unwind the frame. */ |
eec63939 | 5049 | frame_unwind_append_sniffer (gdbarch, mips_stub_frame_sniffer); |
45c9dd44 AC |
5050 | frame_unwind_append_sniffer (gdbarch, mips_insn16_frame_sniffer); |
5051 | frame_unwind_append_sniffer (gdbarch, mips_insn32_frame_sniffer); | |
eec63939 | 5052 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
45c9dd44 AC |
5053 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
5054 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); | |
5792a79b | 5055 | |
4b9b3959 AC |
5056 | return gdbarch; |
5057 | } | |
5058 | ||
2e4ebe70 | 5059 | static void |
6d82d43b | 5060 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
5061 | { |
5062 | struct gdbarch_info info; | |
5063 | ||
5064 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
5065 | mips_gdbarch_init will take care of the rest. */ | |
5066 | gdbarch_info_init (&info); | |
5067 | gdbarch_update_p (info); | |
5068 | } | |
5069 | ||
ad188201 KB |
5070 | /* Print out which MIPS ABI is in use. */ |
5071 | ||
5072 | static void | |
1f8ca57c JB |
5073 | show_mips_abi (struct ui_file *file, |
5074 | int from_tty, | |
5075 | struct cmd_list_element *ignored_cmd, | |
5076 | const char *ignored_value) | |
ad188201 KB |
5077 | { |
5078 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips) | |
1f8ca57c JB |
5079 | fprintf_filtered |
5080 | (file, | |
5081 | "The MIPS ABI is unknown because the current architecture " | |
5082 | "is not MIPS.\n"); | |
ad188201 KB |
5083 | else |
5084 | { | |
5085 | enum mips_abi global_abi = global_mips_abi (); | |
5086 | enum mips_abi actual_abi = mips_abi (current_gdbarch); | |
5087 | const char *actual_abi_str = mips_abi_strings[actual_abi]; | |
5088 | ||
5089 | if (global_abi == MIPS_ABI_UNKNOWN) | |
1f8ca57c JB |
5090 | fprintf_filtered |
5091 | (file, | |
5092 | "The MIPS ABI is set automatically (currently \"%s\").\n", | |
6d82d43b | 5093 | actual_abi_str); |
ad188201 | 5094 | else if (global_abi == actual_abi) |
1f8ca57c JB |
5095 | fprintf_filtered |
5096 | (file, | |
5097 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6d82d43b | 5098 | actual_abi_str); |
ad188201 KB |
5099 | else |
5100 | { | |
5101 | /* Probably shouldn't happen... */ | |
1f8ca57c JB |
5102 | fprintf_filtered |
5103 | (file, | |
5104 | "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n", | |
6d82d43b | 5105 | actual_abi_str, mips_abi_strings[global_abi]); |
ad188201 KB |
5106 | } |
5107 | } | |
5108 | } | |
5109 | ||
4b9b3959 AC |
5110 | static void |
5111 | mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
5112 | { | |
5113 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
5114 | if (tdep != NULL) | |
c2d11a7d | 5115 | { |
acdb74a0 AC |
5116 | int ef_mips_arch; |
5117 | int ef_mips_32bitmode; | |
5118 | /* determine the ISA */ | |
5119 | switch (tdep->elf_flags & EF_MIPS_ARCH) | |
5120 | { | |
5121 | case E_MIPS_ARCH_1: | |
5122 | ef_mips_arch = 1; | |
5123 | break; | |
5124 | case E_MIPS_ARCH_2: | |
5125 | ef_mips_arch = 2; | |
5126 | break; | |
5127 | case E_MIPS_ARCH_3: | |
5128 | ef_mips_arch = 3; | |
5129 | break; | |
5130 | case E_MIPS_ARCH_4: | |
93d56215 | 5131 | ef_mips_arch = 4; |
acdb74a0 AC |
5132 | break; |
5133 | default: | |
93d56215 | 5134 | ef_mips_arch = 0; |
acdb74a0 AC |
5135 | break; |
5136 | } | |
5137 | /* determine the size of a pointer */ | |
5138 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); | |
4b9b3959 AC |
5139 | fprintf_unfiltered (file, |
5140 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 5141 | tdep->elf_flags); |
4b9b3959 | 5142 | fprintf_unfiltered (file, |
acdb74a0 AC |
5143 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
5144 | ef_mips_32bitmode); | |
5145 | fprintf_unfiltered (file, | |
5146 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
5147 | ef_mips_arch); | |
5148 | fprintf_unfiltered (file, | |
5149 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 5150 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
5151 | fprintf_unfiltered (file, |
5152 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 5153 | mips_mask_address_p (tdep), |
4014092b | 5154 | tdep->default_mask_address_p); |
c2d11a7d | 5155 | } |
4b9b3959 AC |
5156 | fprintf_unfiltered (file, |
5157 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
5158 | MIPS_DEFAULT_FPU_TYPE, | |
5159 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
5160 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
5161 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
5162 | : "???")); | |
6d82d43b | 5163 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI); |
4b9b3959 AC |
5164 | fprintf_unfiltered (file, |
5165 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
5166 | MIPS_FPU_TYPE, | |
5167 | (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
5168 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
5169 | : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
5170 | : "???")); | |
4b9b3959 | 5171 | fprintf_unfiltered (file, |
480d3dd2 | 5172 | "mips_dump_tdep: mips_stack_argsize() = %d\n", |
13326b4e | 5173 | mips_stack_argsize (current_gdbarch)); |
c2d11a7d JM |
5174 | } |
5175 | ||
6d82d43b | 5176 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 5177 | |
c906108c | 5178 | void |
acdb74a0 | 5179 | _initialize_mips_tdep (void) |
c906108c SS |
5180 | { |
5181 | static struct cmd_list_element *mipsfpulist = NULL; | |
5182 | struct cmd_list_element *c; | |
5183 | ||
6d82d43b | 5184 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
5185 | if (MIPS_ABI_LAST + 1 |
5186 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
e2e0b3e5 | 5187 | internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync")); |
2e4ebe70 | 5188 | |
4b9b3959 | 5189 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 5190 | |
8d5f9dcb DJ |
5191 | mips_pdr_data = register_objfile_data (); |
5192 | ||
a5ea2558 AC |
5193 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
5194 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
1bedd215 | 5195 | _("Various MIPS specific commands."), |
a5ea2558 AC |
5196 | &setmipscmdlist, "set mips ", 0, &setlist); |
5197 | ||
5198 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
1bedd215 | 5199 | _("Various MIPS specific commands."), |
a5ea2558 AC |
5200 | &showmipscmdlist, "show mips ", 0, &showlist); |
5201 | ||
5202 | /* Allow the user to override the saved register size. */ | |
1b295c3d | 5203 | add_setshow_enum_cmd ("saved-gpreg-size", class_obscure, |
7915a72c AC |
5204 | size_enums, &mips_abi_regsize_string, _("\ |
5205 | Set size of general purpose registers saved on the stack."), _("\ | |
5206 | Show size of general purpose registers saved on the stack."), _("\ | |
a5ea2558 AC |
5207 | This option can be set to one of:\n\ |
5208 | 32 - Force GDB to treat saved GP registers as 32-bit\n\ | |
5209 | 64 - Force GDB to treat saved GP registers as 64-bit\n\ | |
5210 | auto - Allow GDB to use the target's default setting or autodetect the\n\ | |
7915a72c AC |
5211 | saved GP register size from information contained in the\n\ |
5212 | executable (default)."), | |
2c5b56ce | 5213 | NULL, |
7915a72c | 5214 | NULL, /* FIXME: i18n: Size of general purpose registers saved on the stack is %s. */ |
2c5b56ce | 5215 | &setmipscmdlist, &showmipscmdlist); |
a5ea2558 | 5216 | |
d929b26f | 5217 | /* Allow the user to override the argument stack size. */ |
1b295c3d | 5218 | add_setshow_enum_cmd ("stack-arg-size", class_obscure, |
7915a72c AC |
5219 | size_enums, &mips_stack_argsize_string, _("\ |
5220 | Set the amount of stack space reserved for each argument."), _("\ | |
5221 | Show the amount of stack space reserved for each argument."), _("\ | |
d929b26f AC |
5222 | This option can be set to one of:\n\ |
5223 | 32 - Force GDB to allocate 32-bit chunks per argument\n\ | |
5224 | 64 - Force GDB to allocate 64-bit chunks per argument\n\ | |
5225 | auto - Allow GDB to determine the correct setting from the current\n\ | |
7915a72c | 5226 | target and executable (default)"), |
2c5b56ce | 5227 | NULL, |
7915a72c | 5228 | NULL, /* FIXME: i18n: The amount of stack space reserved for each argument is %s. */ |
2c5b56ce | 5229 | &setmipscmdlist, &showmipscmdlist); |
d929b26f | 5230 | |
2e4ebe70 | 5231 | /* Allow the user to override the ABI. */ |
7ab04401 AC |
5232 | add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, |
5233 | &mips_abi_string, _("\ | |
5234 | Set the MIPS ABI used by this program."), _("\ | |
5235 | Show the MIPS ABI used by this program."), _("\ | |
5236 | This option can be set to one of:\n\ | |
5237 | auto - the default ABI associated with the current binary\n\ | |
5238 | o32\n\ | |
5239 | o64\n\ | |
5240 | n32\n\ | |
5241 | n64\n\ | |
5242 | eabi32\n\ | |
5243 | eabi64"), | |
5244 | mips_abi_update, | |
5245 | show_mips_abi, | |
5246 | &setmipscmdlist, &showmipscmdlist); | |
2e4ebe70 | 5247 | |
c906108c SS |
5248 | /* Let the user turn off floating point and set the fence post for |
5249 | heuristic_proc_start. */ | |
5250 | ||
5251 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
1bedd215 | 5252 | _("Set use of MIPS floating-point coprocessor."), |
c906108c SS |
5253 | &mipsfpulist, "set mipsfpu ", 0, &setlist); |
5254 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
1a966eab | 5255 | _("Select single-precision MIPS floating-point coprocessor."), |
c906108c SS |
5256 | &mipsfpulist); |
5257 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
1a966eab | 5258 | _("Select double-precision MIPS floating-point coprocessor."), |
c906108c SS |
5259 | &mipsfpulist); |
5260 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
5261 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
5262 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
5263 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
1a966eab | 5264 | _("Select no MIPS floating-point coprocessor."), &mipsfpulist); |
c906108c SS |
5265 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
5266 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
5267 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
5268 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
1a966eab | 5269 | _("Select MIPS floating-point coprocessor automatically."), |
c906108c SS |
5270 | &mipsfpulist); |
5271 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
1a966eab | 5272 | _("Show current use of MIPS floating-point coprocessor target."), |
c906108c SS |
5273 | &showlist); |
5274 | ||
c906108c SS |
5275 | /* We really would like to have both "0" and "unlimited" work, but |
5276 | command.c doesn't deal with that. So make it a var_zinteger | |
5277 | because the user can always use "999999" or some such for unlimited. */ | |
6bcadd06 | 5278 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
7915a72c AC |
5279 | &heuristic_fence_post, _("\ |
5280 | Set the distance searched for the start of a function."), _("\ | |
5281 | Show the distance searched for the start of a function."), _("\ | |
c906108c SS |
5282 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
5283 | program for the start of a function. This command sets the distance of the\n\ | |
7915a72c | 5284 | search. The only need to set it is when debugging a stripped executable."), |
2c5b56ce | 5285 | reinit_frame_cache_sfunc, |
7915a72c | 5286 | NULL, /* FIXME: i18n: The distance searched for the start of a function is %s. */ |
6bcadd06 | 5287 | &setlist, &showlist); |
c906108c SS |
5288 | |
5289 | /* Allow the user to control whether the upper bits of 64-bit | |
5290 | addresses should be zeroed. */ | |
7915a72c AC |
5291 | add_setshow_auto_boolean_cmd ("mask-address", no_class, |
5292 | &mask_address_var, _("\ | |
5293 | Set zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
5294 | Show zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
e9e68a56 | 5295 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ |
7915a72c | 5296 | allow GDB to determine the correct value."), |
08546159 AC |
5297 | NULL, show_mask_address, |
5298 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
5299 | |
5300 | /* Allow the user to control the size of 32 bit registers within the | |
5301 | raw remote packet. */ | |
b3f42336 | 5302 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
7915a72c AC |
5303 | &mips64_transfers_32bit_regs_p, _("\ |
5304 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
5305 | _("\ | |
5306 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
5307 | _("\ | |
719ec221 AC |
5308 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
5309 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
7915a72c | 5310 | 64 bits for others. Use \"off\" to disable compatibility mode"), |
2c5b56ce | 5311 | set_mips64_transfers_32bit_regs, |
7915a72c | 5312 | NULL, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */ |
7915a72c | 5313 | &setlist, &showlist); |
9ace0497 AC |
5314 | |
5315 | /* Debug this files internals. */ | |
6bcadd06 | 5316 | add_setshow_zinteger_cmd ("mips", class_maintenance, |
7915a72c AC |
5317 | &mips_debug, _("\ |
5318 | Set mips debugging."), _("\ | |
5319 | Show mips debugging."), _("\ | |
5320 | When non-zero, mips specific debugging is enabled."), | |
2c5b56ce | 5321 | NULL, |
7915a72c | 5322 | NULL, /* FIXME: i18n: Mips debugging is currently %s. */ |
6bcadd06 | 5323 | &setdebuglist, &showdebuglist); |
c906108c | 5324 | } |