Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
61baf725 | 3 | Copyright (C) 1988-2017 Free Software Foundation, Inc. |
bf64bfd6 | 4 | |
c906108c SS |
5 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
6 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
7 | ||
c5aa993b | 8 | This file is part of GDB. |
c906108c | 9 | |
c5aa993b JM |
10 | This program is free software; you can redistribute it and/or modify |
11 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 12 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 13 | (at your option) any later version. |
c906108c | 14 | |
c5aa993b JM |
15 | This program is distributed in the hope that it will be useful, |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
c906108c | 19 | |
c5aa993b | 20 | You should have received a copy of the GNU General Public License |
a9762ec7 | 21 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
22 | |
23 | #include "defs.h" | |
c906108c SS |
24 | #include "frame.h" |
25 | #include "inferior.h" | |
26 | #include "symtab.h" | |
27 | #include "value.h" | |
28 | #include "gdbcmd.h" | |
29 | #include "language.h" | |
30 | #include "gdbcore.h" | |
31 | #include "symfile.h" | |
32 | #include "objfiles.h" | |
33 | #include "gdbtypes.h" | |
34 | #include "target.h" | |
28d069e6 | 35 | #include "arch-utils.h" |
4e052eda | 36 | #include "regcache.h" |
70f80edf | 37 | #include "osabi.h" |
d1973055 | 38 | #include "mips-tdep.h" |
fe898f56 | 39 | #include "block.h" |
a4b8ebc8 | 40 | #include "reggroups.h" |
c906108c | 41 | #include "opcode/mips.h" |
c2d11a7d JM |
42 | #include "elf/mips.h" |
43 | #include "elf-bfd.h" | |
2475bac3 | 44 | #include "symcat.h" |
a4b8ebc8 | 45 | #include "sim-regno.h" |
a89aa300 | 46 | #include "dis-asm.h" |
e47ad6c0 | 47 | #include "disasm.h" |
edfae063 AC |
48 | #include "frame-unwind.h" |
49 | #include "frame-base.h" | |
50 | #include "trad-frame.h" | |
7d9b040b | 51 | #include "infcall.h" |
fed7ba43 | 52 | #include "floatformat.h" |
29709017 DJ |
53 | #include "remote.h" |
54 | #include "target-descriptions.h" | |
2bd0c3d7 | 55 | #include "dwarf2-frame.h" |
f8b73d13 | 56 | #include "user-regs.h" |
79a45b7d | 57 | #include "valprint.h" |
175ff332 | 58 | #include "ax.h" |
325fac50 | 59 | #include <algorithm> |
c906108c | 60 | |
8d5f9dcb DJ |
61 | static const struct objfile_data *mips_pdr_data; |
62 | ||
5bbcb741 | 63 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 64 | |
ab50adb6 MR |
65 | static int mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, |
66 | ULONGEST inst); | |
67 | static int micromips_instruction_has_delay_slot (ULONGEST insn, int mustbe32); | |
68 | static int mips16_instruction_has_delay_slot (unsigned short inst, | |
69 | int mustbe32); | |
70 | ||
71 | static int mips32_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, | |
72 | CORE_ADDR addr); | |
73 | static int micromips_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, | |
74 | CORE_ADDR addr, int mustbe32); | |
75 | static int mips16_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, | |
76 | CORE_ADDR addr, int mustbe32); | |
4cc0665f | 77 | |
1bab7383 YQ |
78 | static void mips_print_float_info (struct gdbarch *, struct ui_file *, |
79 | struct frame_info *, const char *); | |
80 | ||
24e05951 | 81 | /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ |
dd824b04 DJ |
82 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ |
83 | #define ST0_FR (1 << 26) | |
84 | ||
b0069a17 AC |
85 | /* The sizes of floating point registers. */ |
86 | ||
87 | enum | |
88 | { | |
89 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
90 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
91 | }; | |
92 | ||
1a69e1e4 DJ |
93 | enum |
94 | { | |
95 | MIPS32_REGSIZE = 4, | |
96 | MIPS64_REGSIZE = 8 | |
97 | }; | |
0dadbba0 | 98 | |
2e4ebe70 DJ |
99 | static const char *mips_abi_string; |
100 | ||
40478521 | 101 | static const char *const mips_abi_strings[] = { |
2e4ebe70 DJ |
102 | "auto", |
103 | "n32", | |
104 | "o32", | |
28d169de | 105 | "n64", |
2e4ebe70 DJ |
106 | "o64", |
107 | "eabi32", | |
108 | "eabi64", | |
109 | NULL | |
110 | }; | |
111 | ||
44f1c4d7 YQ |
112 | /* Enum describing the different kinds of breakpoints. */ |
113 | ||
114 | enum mips_breakpoint_kind | |
115 | { | |
116 | /* 16-bit MIPS16 mode breakpoint. */ | |
117 | MIPS_BP_KIND_MIPS16 = 2, | |
118 | ||
119 | /* 16-bit microMIPS mode breakpoint. */ | |
120 | MIPS_BP_KIND_MICROMIPS16 = 3, | |
121 | ||
122 | /* 32-bit standard MIPS mode breakpoint. */ | |
123 | MIPS_BP_KIND_MIPS32 = 4, | |
124 | ||
125 | /* 32-bit microMIPS mode breakpoint. */ | |
126 | MIPS_BP_KIND_MICROMIPS32 = 5, | |
127 | }; | |
128 | ||
4cc0665f MR |
129 | /* For backwards compatibility we default to MIPS16. This flag is |
130 | overridden as soon as unambiguous ELF file flags tell us the | |
131 | compressed ISA encoding used. */ | |
132 | static const char mips_compression_mips16[] = "mips16"; | |
133 | static const char mips_compression_micromips[] = "micromips"; | |
134 | static const char *const mips_compression_strings[] = | |
135 | { | |
136 | mips_compression_mips16, | |
137 | mips_compression_micromips, | |
138 | NULL | |
139 | }; | |
140 | ||
141 | static const char *mips_compression_string = mips_compression_mips16; | |
142 | ||
f8b73d13 DJ |
143 | /* The standard register names, and all the valid aliases for them. */ |
144 | struct register_alias | |
145 | { | |
146 | const char *name; | |
147 | int regnum; | |
148 | }; | |
149 | ||
150 | /* Aliases for o32 and most other ABIs. */ | |
151 | const struct register_alias mips_o32_aliases[] = { | |
152 | { "ta0", 12 }, | |
153 | { "ta1", 13 }, | |
154 | { "ta2", 14 }, | |
155 | { "ta3", 15 } | |
156 | }; | |
157 | ||
158 | /* Aliases for n32 and n64. */ | |
159 | const struct register_alias mips_n32_n64_aliases[] = { | |
160 | { "ta0", 8 }, | |
161 | { "ta1", 9 }, | |
162 | { "ta2", 10 }, | |
163 | { "ta3", 11 } | |
164 | }; | |
165 | ||
166 | /* Aliases for ABI-independent registers. */ | |
167 | const struct register_alias mips_register_aliases[] = { | |
168 | /* The architecture manuals specify these ABI-independent names for | |
169 | the GPRs. */ | |
170 | #define R(n) { "r" #n, n } | |
171 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
172 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
173 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
174 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
175 | #undef R | |
176 | ||
177 | /* k0 and k1 are sometimes called these instead (for "kernel | |
178 | temp"). */ | |
179 | { "kt0", 26 }, | |
180 | { "kt1", 27 }, | |
181 | ||
182 | /* This is the traditional GDB name for the CP0 status register. */ | |
183 | { "sr", MIPS_PS_REGNUM }, | |
184 | ||
185 | /* This is the traditional GDB name for the CP0 BadVAddr register. */ | |
186 | { "bad", MIPS_EMBED_BADVADDR_REGNUM }, | |
187 | ||
188 | /* This is the traditional GDB name for the FCSR. */ | |
189 | { "fsr", MIPS_EMBED_FP0_REGNUM + 32 } | |
190 | }; | |
191 | ||
865093a3 AR |
192 | const struct register_alias mips_numeric_register_aliases[] = { |
193 | #define R(n) { #n, n } | |
194 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
195 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
196 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
197 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
198 | #undef R | |
199 | }; | |
200 | ||
c906108c SS |
201 | #ifndef MIPS_DEFAULT_FPU_TYPE |
202 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
203 | #endif | |
204 | static int mips_fpu_type_auto = 1; | |
205 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 206 | |
ccce17b0 | 207 | static unsigned int mips_debug = 0; |
7a292a7a | 208 | |
29709017 DJ |
209 | /* Properties (for struct target_desc) describing the g/G packet |
210 | layout. */ | |
211 | #define PROPERTY_GP32 "internal: transfers-32bit-registers" | |
212 | #define PROPERTY_GP64 "internal: transfers-64bit-registers" | |
213 | ||
4eb0ad19 DJ |
214 | struct target_desc *mips_tdesc_gp32; |
215 | struct target_desc *mips_tdesc_gp64; | |
216 | ||
56cea623 AC |
217 | const struct mips_regnum * |
218 | mips_regnum (struct gdbarch *gdbarch) | |
219 | { | |
220 | return gdbarch_tdep (gdbarch)->regnum; | |
221 | } | |
222 | ||
223 | static int | |
224 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
225 | { | |
226 | return mips_regnum (gdbarch)->fp0 + 12; | |
227 | } | |
228 | ||
004159a2 MR |
229 | /* Return 1 if REGNUM refers to a floating-point general register, raw |
230 | or cooked. Otherwise return 0. */ | |
231 | ||
232 | static int | |
233 | mips_float_register_p (struct gdbarch *gdbarch, int regnum) | |
234 | { | |
235 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
236 | ||
237 | return (rawnum >= mips_regnum (gdbarch)->fp0 | |
238 | && rawnum < mips_regnum (gdbarch)->fp0 + 32); | |
239 | } | |
240 | ||
74ed0bb4 MD |
241 | #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \ |
242 | == MIPS_ABI_EABI32 \ | |
243 | || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64) | |
c2d11a7d | 244 | |
025bb325 MS |
245 | #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \ |
246 | (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum) | |
c2d11a7d | 247 | |
025bb325 MS |
248 | #define MIPS_LAST_ARG_REGNUM(gdbarch) \ |
249 | (gdbarch_tdep (gdbarch)->mips_last_arg_regnum) | |
c2d11a7d | 250 | |
74ed0bb4 | 251 | #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type) |
c2d11a7d | 252 | |
d1973055 KB |
253 | /* Return the MIPS ABI associated with GDBARCH. */ |
254 | enum mips_abi | |
255 | mips_abi (struct gdbarch *gdbarch) | |
256 | { | |
257 | return gdbarch_tdep (gdbarch)->mips_abi; | |
258 | } | |
259 | ||
4246e332 | 260 | int |
1b13c4f6 | 261 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 | 262 | { |
29709017 DJ |
263 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
264 | ||
265 | /* If we know how big the registers are, use that size. */ | |
266 | if (tdep->register_size_valid_p) | |
267 | return tdep->register_size; | |
268 | ||
269 | /* Fall back to the previous behavior. */ | |
4246e332 AC |
270 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word |
271 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
272 | } | |
273 | ||
025bb325 | 274 | /* Return the currently configured (or set) saved register size. */ |
480d3dd2 | 275 | |
e6bc2e8a | 276 | unsigned int |
13326b4e | 277 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 278 | { |
1a69e1e4 DJ |
279 | switch (mips_abi (gdbarch)) |
280 | { | |
281 | case MIPS_ABI_EABI32: | |
282 | case MIPS_ABI_O32: | |
283 | return 4; | |
284 | case MIPS_ABI_N32: | |
285 | case MIPS_ABI_N64: | |
286 | case MIPS_ABI_O64: | |
287 | case MIPS_ABI_EABI64: | |
288 | return 8; | |
289 | case MIPS_ABI_UNKNOWN: | |
290 | case MIPS_ABI_LAST: | |
291 | default: | |
292 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
293 | } | |
d929b26f AC |
294 | } |
295 | ||
4cc0665f MR |
296 | /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here |
297 | are some functions to handle addresses associated with compressed | |
298 | code including but not limited to testing, setting, or clearing | |
299 | bit 0 of such addresses. */ | |
742c84f6 | 300 | |
4cc0665f MR |
301 | /* Return one iff compressed code is the MIPS16 instruction set. */ |
302 | ||
303 | static int | |
304 | is_mips16_isa (struct gdbarch *gdbarch) | |
305 | { | |
306 | return gdbarch_tdep (gdbarch)->mips_isa == ISA_MIPS16; | |
307 | } | |
308 | ||
309 | /* Return one iff compressed code is the microMIPS instruction set. */ | |
310 | ||
311 | static int | |
312 | is_micromips_isa (struct gdbarch *gdbarch) | |
313 | { | |
314 | return gdbarch_tdep (gdbarch)->mips_isa == ISA_MICROMIPS; | |
315 | } | |
316 | ||
317 | /* Return one iff ADDR denotes compressed code. */ | |
318 | ||
319 | static int | |
320 | is_compact_addr (CORE_ADDR addr) | |
742c84f6 MR |
321 | { |
322 | return ((addr) & 1); | |
323 | } | |
324 | ||
4cc0665f MR |
325 | /* Return one iff ADDR denotes standard ISA code. */ |
326 | ||
327 | static int | |
328 | is_mips_addr (CORE_ADDR addr) | |
329 | { | |
330 | return !is_compact_addr (addr); | |
331 | } | |
332 | ||
333 | /* Return one iff ADDR denotes MIPS16 code. */ | |
334 | ||
335 | static int | |
336 | is_mips16_addr (struct gdbarch *gdbarch, CORE_ADDR addr) | |
337 | { | |
338 | return is_compact_addr (addr) && is_mips16_isa (gdbarch); | |
339 | } | |
340 | ||
341 | /* Return one iff ADDR denotes microMIPS code. */ | |
342 | ||
343 | static int | |
344 | is_micromips_addr (struct gdbarch *gdbarch, CORE_ADDR addr) | |
345 | { | |
346 | return is_compact_addr (addr) && is_micromips_isa (gdbarch); | |
347 | } | |
348 | ||
349 | /* Strip the ISA (compression) bit off from ADDR. */ | |
350 | ||
742c84f6 | 351 | static CORE_ADDR |
4cc0665f | 352 | unmake_compact_addr (CORE_ADDR addr) |
742c84f6 MR |
353 | { |
354 | return ((addr) & ~(CORE_ADDR) 1); | |
355 | } | |
356 | ||
4cc0665f MR |
357 | /* Add the ISA (compression) bit to ADDR. */ |
358 | ||
742c84f6 | 359 | static CORE_ADDR |
4cc0665f | 360 | make_compact_addr (CORE_ADDR addr) |
742c84f6 MR |
361 | { |
362 | return ((addr) | (CORE_ADDR) 1); | |
363 | } | |
364 | ||
3e29f34a MR |
365 | /* Extern version of unmake_compact_addr; we use a separate function |
366 | so that unmake_compact_addr can be inlined throughout this file. */ | |
367 | ||
368 | CORE_ADDR | |
369 | mips_unmake_compact_addr (CORE_ADDR addr) | |
370 | { | |
371 | return unmake_compact_addr (addr); | |
372 | } | |
373 | ||
71b8ef93 | 374 | /* Functions for setting and testing a bit in a minimal symbol that |
4cc0665f MR |
375 | marks it as MIPS16 or microMIPS function. The MSB of the minimal |
376 | symbol's "info" field is used for this purpose. | |
5a89d8aa | 377 | |
4cc0665f MR |
378 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is |
379 | "special", i.e. refers to a MIPS16 or microMIPS function, and sets | |
380 | one of the "special" bits in a minimal symbol to mark it accordingly. | |
381 | The test checks an ELF-private flag that is valid for true function | |
1bbce132 MR |
382 | symbols only; for synthetic symbols such as for PLT stubs that have |
383 | no ELF-private part at all the MIPS BFD backend arranges for this | |
384 | information to be carried in the asymbol's udata field instead. | |
5a89d8aa | 385 | |
4cc0665f MR |
386 | msymbol_is_mips16 and msymbol_is_micromips test the "special" bit |
387 | in a minimal symbol. */ | |
5a89d8aa | 388 | |
5a89d8aa | 389 | static void |
6d82d43b AC |
390 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
391 | { | |
4cc0665f | 392 | elf_symbol_type *elfsym = (elf_symbol_type *) sym; |
1bbce132 | 393 | unsigned char st_other; |
4cc0665f | 394 | |
1bbce132 MR |
395 | if ((sym->flags & BSF_SYNTHETIC) == 0) |
396 | st_other = elfsym->internal_elf_sym.st_other; | |
397 | else if ((sym->flags & BSF_FUNCTION) != 0) | |
398 | st_other = sym->udata.i; | |
399 | else | |
4cc0665f MR |
400 | return; |
401 | ||
1bbce132 | 402 | if (ELF_ST_IS_MICROMIPS (st_other)) |
3e29f34a | 403 | { |
f161c171 | 404 | MSYMBOL_TARGET_FLAG_MICROMIPS (msym) = 1; |
3e29f34a MR |
405 | SET_MSYMBOL_VALUE_ADDRESS (msym, MSYMBOL_VALUE_RAW_ADDRESS (msym) | 1); |
406 | } | |
1bbce132 | 407 | else if (ELF_ST_IS_MIPS16 (st_other)) |
3e29f34a | 408 | { |
f161c171 | 409 | MSYMBOL_TARGET_FLAG_MIPS16 (msym) = 1; |
3e29f34a MR |
410 | SET_MSYMBOL_VALUE_ADDRESS (msym, MSYMBOL_VALUE_RAW_ADDRESS (msym) | 1); |
411 | } | |
4cc0665f MR |
412 | } |
413 | ||
414 | /* Return one iff MSYM refers to standard ISA code. */ | |
415 | ||
416 | static int | |
417 | msymbol_is_mips (struct minimal_symbol *msym) | |
418 | { | |
f161c171 MR |
419 | return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym) |
420 | | MSYMBOL_TARGET_FLAG_MICROMIPS (msym)); | |
5a89d8aa MS |
421 | } |
422 | ||
4cc0665f MR |
423 | /* Return one iff MSYM refers to MIPS16 code. */ |
424 | ||
71b8ef93 | 425 | static int |
4cc0665f | 426 | msymbol_is_mips16 (struct minimal_symbol *msym) |
71b8ef93 | 427 | { |
f161c171 | 428 | return MSYMBOL_TARGET_FLAG_MIPS16 (msym); |
71b8ef93 MS |
429 | } |
430 | ||
4cc0665f MR |
431 | /* Return one iff MSYM refers to microMIPS code. */ |
432 | ||
433 | static int | |
434 | msymbol_is_micromips (struct minimal_symbol *msym) | |
435 | { | |
f161c171 | 436 | return MSYMBOL_TARGET_FLAG_MICROMIPS (msym); |
4cc0665f MR |
437 | } |
438 | ||
3e29f34a MR |
439 | /* Set the ISA bit in the main symbol too, complementing the corresponding |
440 | minimal symbol setting and reflecting the run-time value of the symbol. | |
441 | The need for comes from the ISA bit having been cleared as code in | |
442 | `_bfd_mips_elf_symbol_processing' separated it into the ELF symbol's | |
443 | `st_other' STO_MIPS16 or STO_MICROMIPS annotation, making the values | |
444 | of symbols referring to compressed code different in GDB to the values | |
445 | used by actual code. That in turn makes them evaluate incorrectly in | |
446 | expressions, producing results different to what the same expressions | |
447 | yield when compiled into the program being debugged. */ | |
448 | ||
449 | static void | |
450 | mips_make_symbol_special (struct symbol *sym, struct objfile *objfile) | |
451 | { | |
452 | if (SYMBOL_CLASS (sym) == LOC_BLOCK) | |
453 | { | |
454 | /* We are in symbol reading so it is OK to cast away constness. */ | |
455 | struct block *block = (struct block *) SYMBOL_BLOCK_VALUE (sym); | |
456 | CORE_ADDR compact_block_start; | |
457 | struct bound_minimal_symbol msym; | |
458 | ||
459 | compact_block_start = BLOCK_START (block) | 1; | |
460 | msym = lookup_minimal_symbol_by_pc (compact_block_start); | |
461 | if (msym.minsym && !msymbol_is_mips (msym.minsym)) | |
462 | { | |
463 | BLOCK_START (block) = compact_block_start; | |
464 | } | |
465 | } | |
466 | } | |
467 | ||
88658117 AC |
468 | /* XFER a value from the big/little/left end of the register. |
469 | Depending on the size of the value it might occupy the entire | |
470 | register or just part of it. Make an allowance for this, aligning | |
471 | things accordingly. */ | |
472 | ||
473 | static void | |
ba32f989 DJ |
474 | mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache, |
475 | int reg_num, int length, | |
870cd05e MK |
476 | enum bfd_endian endian, gdb_byte *in, |
477 | const gdb_byte *out, int buf_offset) | |
88658117 | 478 | { |
88658117 | 479 | int reg_offset = 0; |
72a155b4 UW |
480 | |
481 | gdb_assert (reg_num >= gdbarch_num_regs (gdbarch)); | |
cb1d2653 AC |
482 | /* Need to transfer the left or right part of the register, based on |
483 | the targets byte order. */ | |
88658117 AC |
484 | switch (endian) |
485 | { | |
486 | case BFD_ENDIAN_BIG: | |
72a155b4 | 487 | reg_offset = register_size (gdbarch, reg_num) - length; |
88658117 AC |
488 | break; |
489 | case BFD_ENDIAN_LITTLE: | |
490 | reg_offset = 0; | |
491 | break; | |
6d82d43b | 492 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
493 | reg_offset = 0; |
494 | break; | |
495 | default: | |
e2e0b3e5 | 496 | internal_error (__FILE__, __LINE__, _("bad switch")); |
88658117 AC |
497 | } |
498 | if (mips_debug) | |
cb1d2653 AC |
499 | fprintf_unfiltered (gdb_stderr, |
500 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
501 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
502 | if (mips_debug && out != NULL) |
503 | { | |
504 | int i; | |
cb1d2653 | 505 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 506 | for (i = 0; i < length; i++) |
cb1d2653 | 507 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
508 | } |
509 | if (in != NULL) | |
6d82d43b AC |
510 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
511 | in + buf_offset); | |
88658117 | 512 | if (out != NULL) |
6d82d43b AC |
513 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
514 | out + buf_offset); | |
88658117 AC |
515 | if (mips_debug && in != NULL) |
516 | { | |
517 | int i; | |
cb1d2653 | 518 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 519 | for (i = 0; i < length; i++) |
cb1d2653 | 520 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
521 | } |
522 | if (mips_debug) | |
523 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
524 | } | |
525 | ||
dd824b04 DJ |
526 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
527 | compatiblity mode. A return value of 1 means that we have | |
528 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
529 | ||
530 | static int | |
9c9acae0 | 531 | mips2_fp_compat (struct frame_info *frame) |
dd824b04 | 532 | { |
72a155b4 | 533 | struct gdbarch *gdbarch = get_frame_arch (frame); |
dd824b04 DJ |
534 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not |
535 | meaningful. */ | |
72a155b4 | 536 | if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4) |
dd824b04 DJ |
537 | return 0; |
538 | ||
539 | #if 0 | |
540 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
541 | in all the places we deal with FP registers. PR gdb/413. */ | |
542 | /* Otherwise check the FR bit in the status register - it controls | |
543 | the FP compatiblity mode. If it is clear we are in compatibility | |
544 | mode. */ | |
9c9acae0 | 545 | if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0) |
dd824b04 DJ |
546 | return 1; |
547 | #endif | |
361d1df0 | 548 | |
dd824b04 DJ |
549 | return 0; |
550 | } | |
551 | ||
7a292a7a | 552 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 553 | |
74ed0bb4 | 554 | static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR); |
c906108c | 555 | |
a14ed312 | 556 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 557 | |
025bb325 | 558 | /* The list of available "set mips " and "show mips " commands. */ |
acdb74a0 AC |
559 | |
560 | static struct cmd_list_element *setmipscmdlist = NULL; | |
561 | static struct cmd_list_element *showmipscmdlist = NULL; | |
562 | ||
5e2e9765 KB |
563 | /* Integer registers 0 thru 31 are handled explicitly by |
564 | mips_register_name(). Processor specific registers 32 and above | |
8a9fc081 | 565 | are listed in the following tables. */ |
691c0433 | 566 | |
6d82d43b AC |
567 | enum |
568 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
569 | |
570 | /* Generic MIPS. */ | |
571 | ||
572 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
573 | "sr", "lo", "hi", "bad", "cause", "pc", |
574 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
575 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
576 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
577 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
1faeff08 | 578 | "fsr", "fir", |
691c0433 AC |
579 | }; |
580 | ||
691c0433 AC |
581 | /* Names of tx39 registers. */ |
582 | ||
583 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
584 | "sr", "lo", "hi", "bad", "cause", "pc", |
585 | "", "", "", "", "", "", "", "", | |
586 | "", "", "", "", "", "", "", "", | |
587 | "", "", "", "", "", "", "", "", | |
588 | "", "", "", "", "", "", "", "", | |
589 | "", "", "", "", | |
590 | "", "", "", "", "", "", "", "", | |
1faeff08 | 591 | "", "", "config", "cache", "debug", "depc", "epc", |
691c0433 AC |
592 | }; |
593 | ||
44099a67 | 594 | /* Names of registers with Linux kernels. */ |
1faeff08 MR |
595 | static const char *mips_linux_reg_names[NUM_MIPS_PROCESSOR_REGS] = { |
596 | "sr", "lo", "hi", "bad", "cause", "pc", | |
597 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
598 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
599 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
600 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
601 | "fsr", "fir" | |
602 | }; | |
603 | ||
cce74817 | 604 | |
5e2e9765 | 605 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 606 | static const char * |
d93859e2 | 607 | mips_register_name (struct gdbarch *gdbarch, int regno) |
cce74817 | 608 | { |
d93859e2 | 609 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
5e2e9765 KB |
610 | /* GPR names for all ABIs other than n32/n64. */ |
611 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
612 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
613 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
614 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
615 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
616 | }; |
617 | ||
618 | /* GPR names for n32 and n64 ABIs. */ | |
619 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
620 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
621 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
622 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
623 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
624 | }; |
625 | ||
d93859e2 | 626 | enum mips_abi abi = mips_abi (gdbarch); |
5e2e9765 | 627 | |
f57d151a | 628 | /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, |
6229fbea HZ |
629 | but then don't make the raw register names visible. This (upper) |
630 | range of user visible register numbers are the pseudo-registers. | |
631 | ||
632 | This approach was adopted accommodate the following scenario: | |
633 | It is possible to debug a 64-bit device using a 32-bit | |
634 | programming model. In such instances, the raw registers are | |
635 | configured to be 64-bits wide, while the pseudo registers are | |
636 | configured to be 32-bits wide. The registers that the user | |
637 | sees - the pseudo registers - match the users expectations | |
638 | given the programming model being used. */ | |
d93859e2 UW |
639 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
640 | if (regno < gdbarch_num_regs (gdbarch)) | |
a4b8ebc8 AC |
641 | return ""; |
642 | ||
5e2e9765 KB |
643 | /* The MIPS integer registers are always mapped from 0 to 31. The |
644 | names of the registers (which reflects the conventions regarding | |
645 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 646 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
647 | { |
648 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 649 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 650 | else |
a4b8ebc8 | 651 | return mips_gpr_names[rawnum]; |
5e2e9765 | 652 | } |
d93859e2 UW |
653 | else if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
654 | return tdesc_register_name (gdbarch, rawnum); | |
655 | else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch)) | |
691c0433 AC |
656 | { |
657 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
1faeff08 MR |
658 | if (tdep->mips_processor_reg_names[rawnum - 32]) |
659 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
660 | return ""; | |
691c0433 | 661 | } |
5e2e9765 KB |
662 | else |
663 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 664 | _("mips_register_name: bad register number %d"), rawnum); |
cce74817 | 665 | } |
5e2e9765 | 666 | |
a4b8ebc8 | 667 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 668 | |
a4b8ebc8 AC |
669 | static int |
670 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
671 | struct reggroup *reggroup) | |
672 | { | |
673 | int vector_p; | |
674 | int float_p; | |
675 | int raw_p; | |
72a155b4 UW |
676 | int rawnum = regnum % gdbarch_num_regs (gdbarch); |
677 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
a4b8ebc8 AC |
678 | if (reggroup == all_reggroup) |
679 | return pseudo; | |
680 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
681 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
682 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
683 | (gdbarch), as not all architectures are multi-arch. */ | |
72a155b4 UW |
684 | raw_p = rawnum < gdbarch_num_regs (gdbarch); |
685 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
686 | || gdbarch_register_name (gdbarch, regnum)[0] == '\0') | |
a4b8ebc8 AC |
687 | return 0; |
688 | if (reggroup == float_reggroup) | |
689 | return float_p && pseudo; | |
690 | if (reggroup == vector_reggroup) | |
691 | return vector_p && pseudo; | |
692 | if (reggroup == general_reggroup) | |
693 | return (!vector_p && !float_p) && pseudo; | |
694 | /* Save the pseudo registers. Need to make certain that any code | |
695 | extracting register values from a saved register cache also uses | |
696 | pseudo registers. */ | |
697 | if (reggroup == save_reggroup) | |
698 | return raw_p && pseudo; | |
699 | /* Restore the same pseudo register. */ | |
700 | if (reggroup == restore_reggroup) | |
701 | return raw_p && pseudo; | |
6d82d43b | 702 | return 0; |
a4b8ebc8 AC |
703 | } |
704 | ||
f8b73d13 DJ |
705 | /* Return the groups that a MIPS register can be categorised into. |
706 | This version is only used if we have a target description which | |
707 | describes real registers (and their groups). */ | |
708 | ||
709 | static int | |
710 | mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
711 | struct reggroup *reggroup) | |
712 | { | |
713 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
714 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
715 | int ret; | |
716 | ||
717 | /* Only save, restore, and display the pseudo registers. Need to | |
718 | make certain that any code extracting register values from a | |
719 | saved register cache also uses pseudo registers. | |
720 | ||
721 | Note: saving and restoring the pseudo registers is slightly | |
722 | strange; if we have 64 bits, we should save and restore all | |
723 | 64 bits. But this is hard and has little benefit. */ | |
724 | if (!pseudo) | |
725 | return 0; | |
726 | ||
727 | ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup); | |
728 | if (ret != -1) | |
729 | return ret; | |
730 | ||
731 | return mips_register_reggroup_p (gdbarch, regnum, reggroup); | |
732 | } | |
733 | ||
a4b8ebc8 | 734 | /* Map the symbol table registers which live in the range [1 * |
f57d151a | 735 | gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw |
47ebcfbe | 736 | registers. Take care of alignment and size problems. */ |
c5aa993b | 737 | |
05d1431c | 738 | static enum register_status |
a4b8ebc8 | 739 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
47a35522 | 740 | int cookednum, gdb_byte *buf) |
a4b8ebc8 | 741 | { |
72a155b4 UW |
742 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
743 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
744 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 745 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
05d1431c | 746 | return regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
747 | else if (register_size (gdbarch, rawnum) > |
748 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 749 | { |
8bdf35dc | 750 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
05d1431c | 751 | return regcache_raw_read_part (regcache, rawnum, 0, 4, buf); |
47ebcfbe | 752 | else |
8bdf35dc KB |
753 | { |
754 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
755 | LONGEST regval; | |
05d1431c PA |
756 | enum register_status status; |
757 | ||
758 | status = regcache_raw_read_signed (regcache, rawnum, ®val); | |
759 | if (status == REG_VALID) | |
760 | store_signed_integer (buf, 4, byte_order, regval); | |
761 | return status; | |
8bdf35dc | 762 | } |
47ebcfbe AC |
763 | } |
764 | else | |
e2e0b3e5 | 765 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 AC |
766 | } |
767 | ||
768 | static void | |
6d82d43b AC |
769 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
770 | struct regcache *regcache, int cookednum, | |
47a35522 | 771 | const gdb_byte *buf) |
a4b8ebc8 | 772 | { |
72a155b4 UW |
773 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
774 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
775 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 776 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 777 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
778 | else if (register_size (gdbarch, rawnum) > |
779 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 780 | { |
8bdf35dc | 781 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
47ebcfbe AC |
782 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); |
783 | else | |
8bdf35dc KB |
784 | { |
785 | /* Sign extend the shortened version of the register prior | |
786 | to placing it in the raw register. This is required for | |
787 | some mips64 parts in order to avoid unpredictable behavior. */ | |
788 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
789 | LONGEST regval = extract_signed_integer (buf, 4, byte_order); | |
790 | regcache_raw_write_signed (regcache, rawnum, regval); | |
791 | } | |
47ebcfbe AC |
792 | } |
793 | else | |
e2e0b3e5 | 794 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 | 795 | } |
c5aa993b | 796 | |
175ff332 HZ |
797 | static int |
798 | mips_ax_pseudo_register_collect (struct gdbarch *gdbarch, | |
799 | struct agent_expr *ax, int reg) | |
800 | { | |
801 | int rawnum = reg % gdbarch_num_regs (gdbarch); | |
802 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) | |
803 | && reg < 2 * gdbarch_num_regs (gdbarch)); | |
804 | ||
805 | ax_reg_mask (ax, rawnum); | |
806 | ||
807 | return 0; | |
808 | } | |
809 | ||
810 | static int | |
811 | mips_ax_pseudo_register_push_stack (struct gdbarch *gdbarch, | |
812 | struct agent_expr *ax, int reg) | |
813 | { | |
814 | int rawnum = reg % gdbarch_num_regs (gdbarch); | |
815 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) | |
816 | && reg < 2 * gdbarch_num_regs (gdbarch)); | |
817 | if (register_size (gdbarch, rawnum) >= register_size (gdbarch, reg)) | |
818 | { | |
819 | ax_reg (ax, rawnum); | |
820 | ||
821 | if (register_size (gdbarch, rawnum) > register_size (gdbarch, reg)) | |
822 | { | |
823 | if (!gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
824 | || gdbarch_byte_order (gdbarch) != BFD_ENDIAN_BIG) | |
825 | { | |
826 | ax_const_l (ax, 32); | |
827 | ax_simple (ax, aop_lsh); | |
828 | } | |
829 | ax_const_l (ax, 32); | |
830 | ax_simple (ax, aop_rsh_signed); | |
831 | } | |
832 | } | |
833 | else | |
834 | internal_error (__FILE__, __LINE__, _("bad register size")); | |
835 | ||
836 | return 0; | |
837 | } | |
838 | ||
4cc0665f | 839 | /* Table to translate 3-bit register field to actual register number. */ |
d467df4e | 840 | static const signed char mips_reg3_to_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
841 | |
842 | /* Heuristic_proc_start may hunt through the text section for a long | |
843 | time across a 2400 baud serial line. Allows the user to limit this | |
844 | search. */ | |
845 | ||
44096aee | 846 | static int heuristic_fence_post = 0; |
c906108c | 847 | |
46cd78fb | 848 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
849 | register N. NOTE: This defines the pseudo register type so need to |
850 | rebuild the architecture vector. */ | |
43e526b9 JM |
851 | |
852 | static int mips64_transfers_32bit_regs_p = 0; | |
853 | ||
719ec221 AC |
854 | static void |
855 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
856 | struct cmd_list_element *c) | |
43e526b9 | 857 | { |
719ec221 AC |
858 | struct gdbarch_info info; |
859 | gdbarch_info_init (&info); | |
860 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
861 | instead of relying on globals. Doing that would let generic code | |
862 | handle the search for this specific architecture. */ | |
863 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 864 | { |
719ec221 | 865 | mips64_transfers_32bit_regs_p = 0; |
8a3fe4f8 | 866 | error (_("32-bit compatibility mode not supported")); |
a4b8ebc8 | 867 | } |
a4b8ebc8 AC |
868 | } |
869 | ||
47ebcfbe | 870 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 871 | |
ee51a8c7 KB |
872 | /* This predicate tests for the case of an 8 byte floating point |
873 | value that is being transferred to or from a pair of floating point | |
874 | registers each of which are (or are considered to be) only 4 bytes | |
875 | wide. */ | |
ff2e87ac | 876 | static int |
ee51a8c7 KB |
877 | mips_convert_register_float_case_p (struct gdbarch *gdbarch, int regnum, |
878 | struct type *type) | |
ff2e87ac | 879 | { |
0abe36f5 MD |
880 | return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
881 | && register_size (gdbarch, regnum) == 4 | |
004159a2 | 882 | && mips_float_register_p (gdbarch, regnum) |
6d82d43b | 883 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
884 | } |
885 | ||
ee51a8c7 KB |
886 | /* This predicate tests for the case of a value of less than 8 |
887 | bytes in width that is being transfered to or from an 8 byte | |
888 | general purpose register. */ | |
889 | static int | |
890 | mips_convert_register_gpreg_case_p (struct gdbarch *gdbarch, int regnum, | |
891 | struct type *type) | |
892 | { | |
893 | int num_regs = gdbarch_num_regs (gdbarch); | |
894 | ||
895 | return (register_size (gdbarch, regnum) == 8 | |
896 | && regnum % num_regs > 0 && regnum % num_regs < 32 | |
897 | && TYPE_LENGTH (type) < 8); | |
898 | } | |
899 | ||
900 | static int | |
025bb325 MS |
901 | mips_convert_register_p (struct gdbarch *gdbarch, |
902 | int regnum, struct type *type) | |
ee51a8c7 | 903 | { |
eaa05d59 MR |
904 | return (mips_convert_register_float_case_p (gdbarch, regnum, type) |
905 | || mips_convert_register_gpreg_case_p (gdbarch, regnum, type)); | |
ee51a8c7 KB |
906 | } |
907 | ||
8dccd430 | 908 | static int |
ff2e87ac | 909 | mips_register_to_value (struct frame_info *frame, int regnum, |
8dccd430 PA |
910 | struct type *type, gdb_byte *to, |
911 | int *optimizedp, int *unavailablep) | |
102182a9 | 912 | { |
ee51a8c7 KB |
913 | struct gdbarch *gdbarch = get_frame_arch (frame); |
914 | ||
915 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
916 | { | |
917 | get_frame_register (frame, regnum + 0, to + 4); | |
918 | get_frame_register (frame, regnum + 1, to + 0); | |
8dccd430 PA |
919 | |
920 | if (!get_frame_register_bytes (frame, regnum + 0, 0, 4, to + 4, | |
921 | optimizedp, unavailablep)) | |
922 | return 0; | |
923 | ||
924 | if (!get_frame_register_bytes (frame, regnum + 1, 0, 4, to + 0, | |
925 | optimizedp, unavailablep)) | |
926 | return 0; | |
927 | *optimizedp = *unavailablep = 0; | |
928 | return 1; | |
ee51a8c7 KB |
929 | } |
930 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
931 | { | |
932 | int len = TYPE_LENGTH (type); | |
8dccd430 PA |
933 | CORE_ADDR offset; |
934 | ||
935 | offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 8 - len : 0; | |
936 | if (!get_frame_register_bytes (frame, regnum, offset, len, to, | |
937 | optimizedp, unavailablep)) | |
938 | return 0; | |
939 | ||
940 | *optimizedp = *unavailablep = 0; | |
941 | return 1; | |
ee51a8c7 KB |
942 | } |
943 | else | |
944 | { | |
945 | internal_error (__FILE__, __LINE__, | |
946 | _("mips_register_to_value: unrecognized case")); | |
947 | } | |
102182a9 MS |
948 | } |
949 | ||
42c466d7 | 950 | static void |
ff2e87ac | 951 | mips_value_to_register (struct frame_info *frame, int regnum, |
47a35522 | 952 | struct type *type, const gdb_byte *from) |
102182a9 | 953 | { |
ee51a8c7 KB |
954 | struct gdbarch *gdbarch = get_frame_arch (frame); |
955 | ||
956 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
957 | { | |
958 | put_frame_register (frame, regnum + 0, from + 4); | |
959 | put_frame_register (frame, regnum + 1, from + 0); | |
960 | } | |
961 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
962 | { | |
963 | gdb_byte fill[8]; | |
964 | int len = TYPE_LENGTH (type); | |
965 | ||
966 | /* Sign extend values, irrespective of type, that are stored to | |
967 | a 64-bit general purpose register. (32-bit unsigned values | |
968 | are stored as signed quantities within a 64-bit register. | |
969 | When performing an operation, in compiled code, that combines | |
970 | a 32-bit unsigned value with a signed 64-bit value, a type | |
971 | conversion is first performed that zeroes out the high 32 bits.) */ | |
972 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
973 | { | |
974 | if (from[0] & 0x80) | |
975 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, -1); | |
976 | else | |
977 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, 0); | |
978 | put_frame_register_bytes (frame, regnum, 0, 8 - len, fill); | |
979 | put_frame_register_bytes (frame, regnum, 8 - len, len, from); | |
980 | } | |
981 | else | |
982 | { | |
983 | if (from[len-1] & 0x80) | |
984 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, -1); | |
985 | else | |
986 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, 0); | |
987 | put_frame_register_bytes (frame, regnum, 0, len, from); | |
988 | put_frame_register_bytes (frame, regnum, len, 8 - len, fill); | |
989 | } | |
990 | } | |
991 | else | |
992 | { | |
993 | internal_error (__FILE__, __LINE__, | |
994 | _("mips_value_to_register: unrecognized case")); | |
995 | } | |
102182a9 MS |
996 | } |
997 | ||
a4b8ebc8 AC |
998 | /* Return the GDB type object for the "standard" data type of data in |
999 | register REG. */ | |
78fde5f8 KB |
1000 | |
1001 | static struct type * | |
a4b8ebc8 AC |
1002 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
1003 | { | |
72a155b4 | 1004 | gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch)); |
004159a2 | 1005 | if (mips_float_register_p (gdbarch, regnum)) |
a6425924 | 1006 | { |
5ef80fb0 | 1007 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 1008 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
8da61cc4 | 1009 | if (mips_isa_regsize (gdbarch) == 4) |
27067745 | 1010 | return builtin_type (gdbarch)->builtin_float; |
8da61cc4 | 1011 | else |
27067745 | 1012 | return builtin_type (gdbarch)->builtin_double; |
a6425924 | 1013 | } |
72a155b4 | 1014 | else if (regnum < gdbarch_num_regs (gdbarch)) |
d5ac5a39 AC |
1015 | { |
1016 | /* The raw or ISA registers. These are all sized according to | |
1017 | the ISA regsize. */ | |
1018 | if (mips_isa_regsize (gdbarch) == 4) | |
df4df182 | 1019 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 | 1020 | else |
df4df182 | 1021 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 1022 | } |
78fde5f8 | 1023 | else |
d5ac5a39 | 1024 | { |
1faeff08 MR |
1025 | int rawnum = regnum - gdbarch_num_regs (gdbarch); |
1026 | ||
d5ac5a39 AC |
1027 | /* The cooked or ABI registers. These are sized according to |
1028 | the ABI (with a few complications). */ | |
1faeff08 MR |
1029 | if (rawnum == mips_regnum (gdbarch)->fp_control_status |
1030 | || rawnum == mips_regnum (gdbarch)->fp_implementation_revision) | |
1031 | return builtin_type (gdbarch)->builtin_int32; | |
de4bfa86 | 1032 | else if (gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX |
1faeff08 MR |
1033 | && rawnum >= MIPS_FIRST_EMBED_REGNUM |
1034 | && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
d5ac5a39 AC |
1035 | /* The pseudo/cooked view of the embedded registers is always |
1036 | 32-bit. The raw view is handled below. */ | |
df4df182 | 1037 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
1038 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
1039 | /* The target, while possibly using a 64-bit register buffer, | |
1040 | is only transfering 32-bits of each integer register. | |
1041 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
df4df182 | 1042 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
1043 | else if (mips_abi_regsize (gdbarch) == 4) |
1044 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
1045 | 32- or 64-bit). */ | |
df4df182 | 1046 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
1047 | else |
1048 | /* 64-bit ABI. */ | |
df4df182 | 1049 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 1050 | } |
78fde5f8 KB |
1051 | } |
1052 | ||
f8b73d13 DJ |
1053 | /* Return the GDB type for the pseudo register REGNUM, which is the |
1054 | ABI-level view. This function is only called if there is a target | |
1055 | description which includes registers, so we know precisely the | |
1056 | types of hardware registers. */ | |
1057 | ||
1058 | static struct type * | |
1059 | mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
1060 | { | |
1061 | const int num_regs = gdbarch_num_regs (gdbarch); | |
f8b73d13 DJ |
1062 | int rawnum = regnum % num_regs; |
1063 | struct type *rawtype; | |
1064 | ||
1065 | gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); | |
1066 | ||
1067 | /* Absent registers are still absent. */ | |
1068 | rawtype = gdbarch_register_type (gdbarch, rawnum); | |
1069 | if (TYPE_LENGTH (rawtype) == 0) | |
1070 | return rawtype; | |
1071 | ||
a6912260 MR |
1072 | /* Present the floating point registers however the hardware did; |
1073 | do not try to convert between FPU layouts. */ | |
de13fcf2 | 1074 | if (mips_float_register_p (gdbarch, rawnum)) |
f8b73d13 DJ |
1075 | return rawtype; |
1076 | ||
78b86327 MR |
1077 | /* Floating-point control registers are always 32-bit even though for |
1078 | backwards compatibility reasons 64-bit targets will transfer them | |
1079 | as 64-bit quantities even if using XML descriptions. */ | |
1080 | if (rawnum == mips_regnum (gdbarch)->fp_control_status | |
1081 | || rawnum == mips_regnum (gdbarch)->fp_implementation_revision) | |
1082 | return builtin_type (gdbarch)->builtin_int32; | |
1083 | ||
f8b73d13 DJ |
1084 | /* Use pointer types for registers if we can. For n32 we can not, |
1085 | since we do not have a 64-bit pointer type. */ | |
0dfff4cb UW |
1086 | if (mips_abi_regsize (gdbarch) |
1087 | == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr)) | |
f8b73d13 | 1088 | { |
1faeff08 MR |
1089 | if (rawnum == MIPS_SP_REGNUM |
1090 | || rawnum == mips_regnum (gdbarch)->badvaddr) | |
0dfff4cb | 1091 | return builtin_type (gdbarch)->builtin_data_ptr; |
1faeff08 | 1092 | else if (rawnum == mips_regnum (gdbarch)->pc) |
0dfff4cb | 1093 | return builtin_type (gdbarch)->builtin_func_ptr; |
f8b73d13 DJ |
1094 | } |
1095 | ||
1096 | if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8 | |
1faeff08 MR |
1097 | && ((rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_PS_REGNUM) |
1098 | || rawnum == mips_regnum (gdbarch)->lo | |
1099 | || rawnum == mips_regnum (gdbarch)->hi | |
1100 | || rawnum == mips_regnum (gdbarch)->badvaddr | |
1101 | || rawnum == mips_regnum (gdbarch)->cause | |
1102 | || rawnum == mips_regnum (gdbarch)->pc | |
1103 | || (mips_regnum (gdbarch)->dspacc != -1 | |
1104 | && rawnum >= mips_regnum (gdbarch)->dspacc | |
1105 | && rawnum < mips_regnum (gdbarch)->dspacc + 6))) | |
df4df182 | 1106 | return builtin_type (gdbarch)->builtin_int32; |
f8b73d13 | 1107 | |
a6912260 MR |
1108 | /* The pseudo/cooked view of embedded registers is always |
1109 | 32-bit, even if the target transfers 64-bit values for them. | |
1110 | New targets relying on XML descriptions should only transfer | |
1111 | the necessary 32 bits, but older versions of GDB expected 64, | |
1112 | so allow the target to provide 64 bits without interfering | |
1113 | with the displayed type. */ | |
de4bfa86 | 1114 | if (gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX |
78b86327 | 1115 | && rawnum >= MIPS_FIRST_EMBED_REGNUM |
1faeff08 | 1116 | && rawnum <= MIPS_LAST_EMBED_REGNUM) |
a6912260 | 1117 | return builtin_type (gdbarch)->builtin_int32; |
1faeff08 | 1118 | |
f8b73d13 DJ |
1119 | /* For all other registers, pass through the hardware type. */ |
1120 | return rawtype; | |
1121 | } | |
bcb0cc15 | 1122 | |
025bb325 | 1123 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 1124 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
1125 | |
1126 | static int | |
480d3dd2 | 1127 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
1128 | { |
1129 | switch (mask_address_var) | |
1130 | { | |
7f19b9a2 | 1131 | case AUTO_BOOLEAN_TRUE: |
4014092b | 1132 | return 1; |
7f19b9a2 | 1133 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
1134 | return 0; |
1135 | break; | |
7f19b9a2 | 1136 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 1137 | return tdep->default_mask_address_p; |
4014092b | 1138 | default: |
025bb325 MS |
1139 | internal_error (__FILE__, __LINE__, |
1140 | _("mips_mask_address_p: bad switch")); | |
4014092b | 1141 | return -1; |
361d1df0 | 1142 | } |
4014092b AC |
1143 | } |
1144 | ||
1145 | static void | |
08546159 AC |
1146 | show_mask_address (struct ui_file *file, int from_tty, |
1147 | struct cmd_list_element *c, const char *value) | |
4014092b | 1148 | { |
f5656ead | 1149 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ()); |
08546159 AC |
1150 | |
1151 | deprecated_show_value_hack (file, from_tty, c, value); | |
4014092b AC |
1152 | switch (mask_address_var) |
1153 | { | |
7f19b9a2 | 1154 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
1155 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
1156 | break; | |
7f19b9a2 | 1157 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
1158 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
1159 | break; | |
7f19b9a2 | 1160 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
1161 | printf_filtered |
1162 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
1163 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
1164 | break; |
1165 | default: | |
e2e0b3e5 | 1166 | internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); |
4014092b | 1167 | break; |
361d1df0 | 1168 | } |
4014092b | 1169 | } |
c906108c | 1170 | |
4cc0665f MR |
1171 | /* Tell if the program counter value in MEMADDR is in a standard ISA |
1172 | function. */ | |
1173 | ||
1174 | int | |
1175 | mips_pc_is_mips (CORE_ADDR memaddr) | |
1176 | { | |
7cbd4a93 | 1177 | struct bound_minimal_symbol sym; |
4cc0665f MR |
1178 | |
1179 | /* Flags indicating that this is a MIPS16 or microMIPS function is | |
1180 | stored by elfread.c in the high bit of the info field. Use this | |
1181 | to decide if the function is standard MIPS. Otherwise if bit 0 | |
1182 | of the address is clear, then this is a standard MIPS function. */ | |
3e29f34a | 1183 | sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); |
7cbd4a93 TT |
1184 | if (sym.minsym) |
1185 | return msymbol_is_mips (sym.minsym); | |
4cc0665f MR |
1186 | else |
1187 | return is_mips_addr (memaddr); | |
1188 | } | |
1189 | ||
c906108c SS |
1190 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
1191 | ||
0fe7e7c8 | 1192 | int |
4cc0665f | 1193 | mips_pc_is_mips16 (struct gdbarch *gdbarch, CORE_ADDR memaddr) |
c906108c | 1194 | { |
7cbd4a93 | 1195 | struct bound_minimal_symbol sym; |
c906108c | 1196 | |
91912e4d MR |
1197 | /* A flag indicating that this is a MIPS16 function is stored by |
1198 | elfread.c in the high bit of the info field. Use this to decide | |
4cc0665f MR |
1199 | if the function is MIPS16. Otherwise if bit 0 of the address is |
1200 | set, then ELF file flags will tell if this is a MIPS16 function. */ | |
3e29f34a | 1201 | sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); |
7cbd4a93 TT |
1202 | if (sym.minsym) |
1203 | return msymbol_is_mips16 (sym.minsym); | |
4cc0665f MR |
1204 | else |
1205 | return is_mips16_addr (gdbarch, memaddr); | |
1206 | } | |
1207 | ||
1208 | /* Tell if the program counter value in MEMADDR is in a microMIPS function. */ | |
1209 | ||
1210 | int | |
1211 | mips_pc_is_micromips (struct gdbarch *gdbarch, CORE_ADDR memaddr) | |
1212 | { | |
7cbd4a93 | 1213 | struct bound_minimal_symbol sym; |
4cc0665f MR |
1214 | |
1215 | /* A flag indicating that this is a microMIPS function is stored by | |
1216 | elfread.c in the high bit of the info field. Use this to decide | |
1217 | if the function is microMIPS. Otherwise if bit 0 of the address | |
1218 | is set, then ELF file flags will tell if this is a microMIPS | |
1219 | function. */ | |
3e29f34a | 1220 | sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); |
7cbd4a93 TT |
1221 | if (sym.minsym) |
1222 | return msymbol_is_micromips (sym.minsym); | |
4cc0665f MR |
1223 | else |
1224 | return is_micromips_addr (gdbarch, memaddr); | |
1225 | } | |
1226 | ||
1227 | /* Tell the ISA type of the function the program counter value in MEMADDR | |
1228 | is in. */ | |
1229 | ||
1230 | static enum mips_isa | |
1231 | mips_pc_isa (struct gdbarch *gdbarch, CORE_ADDR memaddr) | |
1232 | { | |
7cbd4a93 | 1233 | struct bound_minimal_symbol sym; |
4cc0665f MR |
1234 | |
1235 | /* A flag indicating that this is a MIPS16 or a microMIPS function | |
1236 | is stored by elfread.c in the high bit of the info field. Use | |
1237 | this to decide if the function is MIPS16 or microMIPS or normal | |
1238 | MIPS. Otherwise if bit 0 of the address is set, then ELF file | |
1239 | flags will tell if this is a MIPS16 or a microMIPS function. */ | |
3e29f34a | 1240 | sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); |
7cbd4a93 | 1241 | if (sym.minsym) |
4cc0665f | 1242 | { |
7cbd4a93 | 1243 | if (msymbol_is_micromips (sym.minsym)) |
4cc0665f | 1244 | return ISA_MICROMIPS; |
7cbd4a93 | 1245 | else if (msymbol_is_mips16 (sym.minsym)) |
4cc0665f MR |
1246 | return ISA_MIPS16; |
1247 | else | |
1248 | return ISA_MIPS; | |
1249 | } | |
c906108c | 1250 | else |
4cc0665f MR |
1251 | { |
1252 | if (is_mips_addr (memaddr)) | |
1253 | return ISA_MIPS; | |
1254 | else if (is_micromips_addr (gdbarch, memaddr)) | |
1255 | return ISA_MICROMIPS; | |
1256 | else | |
1257 | return ISA_MIPS16; | |
1258 | } | |
c906108c SS |
1259 | } |
1260 | ||
3e29f34a MR |
1261 | /* Set the ISA bit correctly in the PC, used by DWARF-2 machinery. |
1262 | The need for comes from the ISA bit having been cleared, making | |
1263 | addresses in FDE, range records, etc. referring to compressed code | |
1264 | different to those in line information, the symbol table and finally | |
1265 | the PC register. That in turn confuses many operations. */ | |
1266 | ||
1267 | static CORE_ADDR | |
1268 | mips_adjust_dwarf2_addr (CORE_ADDR pc) | |
1269 | { | |
1270 | pc = unmake_compact_addr (pc); | |
1271 | return mips_pc_is_mips (pc) ? pc : make_compact_addr (pc); | |
1272 | } | |
1273 | ||
1274 | /* Recalculate the line record requested so that the resulting PC has | |
1275 | the ISA bit set correctly, used by DWARF-2 machinery. The need for | |
1276 | this adjustment comes from some records associated with compressed | |
1277 | code having the ISA bit cleared, most notably at function prologue | |
1278 | ends. The ISA bit is in this context retrieved from the minimal | |
1279 | symbol covering the address requested, which in turn has been | |
1280 | constructed from the binary's symbol table rather than DWARF-2 | |
1281 | information. The correct setting of the ISA bit is required for | |
1282 | breakpoint addresses to correctly match against the stop PC. | |
1283 | ||
1284 | As line entries can specify relative address adjustments we need to | |
1285 | keep track of the absolute value of the last line address recorded | |
1286 | in line information, so that we can calculate the actual address to | |
1287 | apply the ISA bit adjustment to. We use PC for this tracking and | |
1288 | keep the original address there. | |
1289 | ||
1290 | As such relative address adjustments can be odd within compressed | |
1291 | code we need to keep track of the last line address with the ISA | |
1292 | bit adjustment applied too, as the original address may or may not | |
1293 | have had the ISA bit set. We use ADJ_PC for this tracking and keep | |
1294 | the adjusted address there. | |
1295 | ||
1296 | For relative address adjustments we then use these variables to | |
1297 | calculate the address intended by line information, which will be | |
1298 | PC-relative, and return an updated adjustment carrying ISA bit | |
1299 | information, which will be ADJ_PC-relative. For absolute address | |
1300 | adjustments we just return the same address that we store in ADJ_PC | |
1301 | too. | |
1302 | ||
1303 | As the first line entry can be relative to an implied address value | |
1304 | of 0 we need to have the initial address set up that we store in PC | |
1305 | and ADJ_PC. This is arranged with a call from `dwarf_decode_lines_1' | |
1306 | that sets PC to 0 and ADJ_PC accordingly, usually 0 as well. */ | |
1307 | ||
1308 | static CORE_ADDR | |
1309 | mips_adjust_dwarf2_line (CORE_ADDR addr, int rel) | |
1310 | { | |
1311 | static CORE_ADDR adj_pc; | |
1312 | static CORE_ADDR pc; | |
1313 | CORE_ADDR isa_pc; | |
1314 | ||
1315 | pc = rel ? pc + addr : addr; | |
1316 | isa_pc = mips_adjust_dwarf2_addr (pc); | |
1317 | addr = rel ? isa_pc - adj_pc : isa_pc; | |
1318 | adj_pc = isa_pc; | |
1319 | return addr; | |
1320 | } | |
1321 | ||
14132e89 MR |
1322 | /* Various MIPS16 thunk (aka stub or trampoline) names. */ |
1323 | ||
1324 | static const char mips_str_mips16_call_stub[] = "__mips16_call_stub_"; | |
1325 | static const char mips_str_mips16_ret_stub[] = "__mips16_ret_"; | |
1326 | static const char mips_str_call_fp_stub[] = "__call_stub_fp_"; | |
1327 | static const char mips_str_call_stub[] = "__call_stub_"; | |
1328 | static const char mips_str_fn_stub[] = "__fn_stub_"; | |
1329 | ||
1330 | /* This is used as a PIC thunk prefix. */ | |
1331 | ||
1332 | static const char mips_str_pic[] = ".pic."; | |
1333 | ||
1334 | /* Return non-zero if the PC is inside a call thunk (aka stub or | |
1335 | trampoline) that should be treated as a temporary frame. */ | |
1336 | ||
1337 | static int | |
1338 | mips_in_frame_stub (CORE_ADDR pc) | |
1339 | { | |
1340 | CORE_ADDR start_addr; | |
1341 | const char *name; | |
1342 | ||
1343 | /* Find the starting address of the function containing the PC. */ | |
1344 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
1345 | return 0; | |
1346 | ||
1347 | /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */ | |
61012eef | 1348 | if (startswith (name, mips_str_mips16_call_stub)) |
14132e89 MR |
1349 | return 1; |
1350 | /* If the PC is in __call_stub_*, this is a call/return or a call stub. */ | |
61012eef | 1351 | if (startswith (name, mips_str_call_stub)) |
14132e89 MR |
1352 | return 1; |
1353 | /* If the PC is in __fn_stub_*, this is a call stub. */ | |
61012eef | 1354 | if (startswith (name, mips_str_fn_stub)) |
14132e89 MR |
1355 | return 1; |
1356 | ||
1357 | return 0; /* Not a stub. */ | |
1358 | } | |
1359 | ||
b2fa5097 | 1360 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
025bb325 | 1361 | all registers should be sign extended for simplicity? */ |
6c997a34 AC |
1362 | |
1363 | static CORE_ADDR | |
61a1198a | 1364 | mips_read_pc (struct regcache *regcache) |
6c997a34 | 1365 | { |
8376de04 | 1366 | int regnum = gdbarch_pc_regnum (get_regcache_arch (regcache)); |
70242eb1 | 1367 | LONGEST pc; |
8376de04 | 1368 | |
61a1198a UW |
1369 | regcache_cooked_read_signed (regcache, regnum, &pc); |
1370 | return pc; | |
b6cb9035 AC |
1371 | } |
1372 | ||
58dfe9ff AC |
1373 | static CORE_ADDR |
1374 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1375 | { | |
14132e89 | 1376 | CORE_ADDR pc; |
930bd0e0 | 1377 | |
8376de04 | 1378 | pc = frame_unwind_register_signed (next_frame, gdbarch_pc_regnum (gdbarch)); |
14132e89 MR |
1379 | /* macro/2012-04-20: This hack skips over MIPS16 call thunks as |
1380 | intermediate frames. In this case we can get the caller's address | |
1381 | from $ra, or if $ra contains an address within a thunk as well, then | |
1382 | it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10} | |
1383 | and thus the caller's address is in $s2. */ | |
1384 | if (frame_relative_level (next_frame) >= 0 && mips_in_frame_stub (pc)) | |
1385 | { | |
1386 | pc = frame_unwind_register_signed | |
1387 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM); | |
14132e89 | 1388 | if (mips_in_frame_stub (pc)) |
3e29f34a MR |
1389 | pc = frame_unwind_register_signed |
1390 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); | |
14132e89 | 1391 | } |
930bd0e0 | 1392 | return pc; |
edfae063 AC |
1393 | } |
1394 | ||
30244cd8 UW |
1395 | static CORE_ADDR |
1396 | mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1397 | { | |
72a155b4 UW |
1398 | return frame_unwind_register_signed |
1399 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM); | |
30244cd8 UW |
1400 | } |
1401 | ||
b8a22b94 | 1402 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that |
edfae063 AC |
1403 | dummy frame. The frame ID's base needs to match the TOS value |
1404 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
1405 | breakpoint. */ | |
1406 | ||
1407 | static struct frame_id | |
b8a22b94 | 1408 | mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
edfae063 | 1409 | { |
f57d151a | 1410 | return frame_id_build |
b8a22b94 DJ |
1411 | (get_frame_register_signed (this_frame, |
1412 | gdbarch_num_regs (gdbarch) | |
1413 | + MIPS_SP_REGNUM), | |
1414 | get_frame_pc (this_frame)); | |
58dfe9ff AC |
1415 | } |
1416 | ||
5a439849 MR |
1417 | /* Implement the "write_pc" gdbarch method. */ |
1418 | ||
1419 | void | |
61a1198a | 1420 | mips_write_pc (struct regcache *regcache, CORE_ADDR pc) |
b6cb9035 | 1421 | { |
8376de04 MR |
1422 | int regnum = gdbarch_pc_regnum (get_regcache_arch (regcache)); |
1423 | ||
3e29f34a | 1424 | regcache_cooked_write_unsigned (regcache, regnum, pc); |
6c997a34 | 1425 | } |
c906108c | 1426 | |
4cc0665f MR |
1427 | /* Fetch and return instruction from the specified location. Handle |
1428 | MIPS16/microMIPS as appropriate. */ | |
c906108c | 1429 | |
d37cca3d | 1430 | static ULONGEST |
4cc0665f | 1431 | mips_fetch_instruction (struct gdbarch *gdbarch, |
d09f2c3f | 1432 | enum mips_isa isa, CORE_ADDR addr, int *errp) |
c906108c | 1433 | { |
e17a4113 | 1434 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 1435 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c | 1436 | int instlen; |
d09f2c3f | 1437 | int err; |
c906108c | 1438 | |
4cc0665f | 1439 | switch (isa) |
c906108c | 1440 | { |
4cc0665f MR |
1441 | case ISA_MICROMIPS: |
1442 | case ISA_MIPS16: | |
95ac2dcf | 1443 | instlen = MIPS_INSN16_SIZE; |
4cc0665f MR |
1444 | addr = unmake_compact_addr (addr); |
1445 | break; | |
1446 | case ISA_MIPS: | |
1447 | instlen = MIPS_INSN32_SIZE; | |
1448 | break; | |
1449 | default: | |
1450 | internal_error (__FILE__, __LINE__, _("invalid ISA")); | |
1451 | break; | |
c906108c | 1452 | } |
d09f2c3f PA |
1453 | err = target_read_memory (addr, buf, instlen); |
1454 | if (errp != NULL) | |
1455 | *errp = err; | |
1456 | if (err != 0) | |
4cc0665f | 1457 | { |
d09f2c3f PA |
1458 | if (errp == NULL) |
1459 | memory_error (TARGET_XFER_E_IO, addr); | |
4cc0665f MR |
1460 | return 0; |
1461 | } | |
e17a4113 | 1462 | return extract_unsigned_integer (buf, instlen, byte_order); |
c906108c SS |
1463 | } |
1464 | ||
025bb325 | 1465 | /* These are the fields of 32 bit mips instructions. */ |
e135b889 DJ |
1466 | #define mips32_op(x) (x >> 26) |
1467 | #define itype_op(x) (x >> 26) | |
1468 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 1469 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 1470 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 1471 | |
e135b889 DJ |
1472 | #define jtype_op(x) (x >> 26) |
1473 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 1474 | |
e135b889 DJ |
1475 | #define rtype_op(x) (x >> 26) |
1476 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
1477 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
1478 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
1479 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
1480 | #define rtype_funct(x) (x & 0x3f) | |
c906108c | 1481 | |
4cc0665f MR |
1482 | /* MicroMIPS instruction fields. */ |
1483 | #define micromips_op(x) ((x) >> 10) | |
1484 | ||
1485 | /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest | |
1486 | bit and the size respectively of the field extracted. */ | |
1487 | #define b0s4_imm(x) ((x) & 0xf) | |
1488 | #define b0s5_imm(x) ((x) & 0x1f) | |
1489 | #define b0s5_reg(x) ((x) & 0x1f) | |
1490 | #define b0s7_imm(x) ((x) & 0x7f) | |
1491 | #define b0s10_imm(x) ((x) & 0x3ff) | |
1492 | #define b1s4_imm(x) (((x) >> 1) & 0xf) | |
1493 | #define b1s9_imm(x) (((x) >> 1) & 0x1ff) | |
1494 | #define b2s3_cc(x) (((x) >> 2) & 0x7) | |
1495 | #define b4s2_regl(x) (((x) >> 4) & 0x3) | |
1496 | #define b5s5_op(x) (((x) >> 5) & 0x1f) | |
1497 | #define b5s5_reg(x) (((x) >> 5) & 0x1f) | |
1498 | #define b6s4_op(x) (((x) >> 6) & 0xf) | |
1499 | #define b7s3_reg(x) (((x) >> 7) & 0x7) | |
1500 | ||
1501 | /* 32-bit instruction formats, B and S refer to the lowest bit and the size | |
1502 | respectively of the field extracted. */ | |
1503 | #define b0s6_op(x) ((x) & 0x3f) | |
1504 | #define b0s11_op(x) ((x) & 0x7ff) | |
1505 | #define b0s12_imm(x) ((x) & 0xfff) | |
1506 | #define b0s16_imm(x) ((x) & 0xffff) | |
1507 | #define b0s26_imm(x) ((x) & 0x3ffffff) | |
1508 | #define b6s10_ext(x) (((x) >> 6) & 0x3ff) | |
1509 | #define b11s5_reg(x) (((x) >> 11) & 0x1f) | |
1510 | #define b12s4_op(x) (((x) >> 12) & 0xf) | |
1511 | ||
1512 | /* Return the size in bytes of the instruction INSN encoded in the ISA | |
1513 | instruction set. */ | |
1514 | ||
1515 | static int | |
1516 | mips_insn_size (enum mips_isa isa, ULONGEST insn) | |
1517 | { | |
1518 | switch (isa) | |
1519 | { | |
1520 | case ISA_MICROMIPS: | |
100b4f2e MR |
1521 | if ((micromips_op (insn) & 0x4) == 0x4 |
1522 | || (micromips_op (insn) & 0x7) == 0x0) | |
4cc0665f MR |
1523 | return 2 * MIPS_INSN16_SIZE; |
1524 | else | |
1525 | return MIPS_INSN16_SIZE; | |
1526 | case ISA_MIPS16: | |
1527 | if ((insn & 0xf800) == 0xf000) | |
1528 | return 2 * MIPS_INSN16_SIZE; | |
1529 | else | |
1530 | return MIPS_INSN16_SIZE; | |
1531 | case ISA_MIPS: | |
1532 | return MIPS_INSN32_SIZE; | |
1533 | } | |
1534 | internal_error (__FILE__, __LINE__, _("invalid ISA")); | |
1535 | } | |
1536 | ||
06987e64 MK |
1537 | static LONGEST |
1538 | mips32_relative_offset (ULONGEST inst) | |
c5aa993b | 1539 | { |
06987e64 | 1540 | return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; |
c906108c SS |
1541 | } |
1542 | ||
a385295e MR |
1543 | /* Determine the address of the next instruction executed after the INST |
1544 | floating condition branch instruction at PC. COUNT specifies the | |
1545 | number of the floating condition bits tested by the branch. */ | |
1546 | ||
1547 | static CORE_ADDR | |
7113a196 | 1548 | mips32_bc1_pc (struct gdbarch *gdbarch, struct regcache *regcache, |
a385295e MR |
1549 | ULONGEST inst, CORE_ADDR pc, int count) |
1550 | { | |
1551 | int fcsr = mips_regnum (gdbarch)->fp_control_status; | |
1552 | int cnum = (itype_rt (inst) >> 2) & (count - 1); | |
1553 | int tf = itype_rt (inst) & 1; | |
1554 | int mask = (1 << count) - 1; | |
1555 | ULONGEST fcs; | |
1556 | int cond; | |
1557 | ||
1558 | if (fcsr == -1) | |
1559 | /* No way to handle; it'll most likely trap anyway. */ | |
1560 | return pc; | |
1561 | ||
7113a196 | 1562 | fcs = regcache_raw_get_unsigned (regcache, fcsr); |
a385295e MR |
1563 | cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); |
1564 | ||
1565 | if (((cond >> cnum) & mask) != mask * !tf) | |
1566 | pc += mips32_relative_offset (inst); | |
1567 | else | |
1568 | pc += 4; | |
1569 | ||
1570 | return pc; | |
1571 | } | |
1572 | ||
f94363d7 AP |
1573 | /* Return nonzero if the gdbarch is an Octeon series. */ |
1574 | ||
1575 | static int | |
1576 | is_octeon (struct gdbarch *gdbarch) | |
1577 | { | |
1578 | const struct bfd_arch_info *info = gdbarch_bfd_arch_info (gdbarch); | |
1579 | ||
1580 | return (info->mach == bfd_mach_mips_octeon | |
1581 | || info->mach == bfd_mach_mips_octeonp | |
1582 | || info->mach == bfd_mach_mips_octeon2); | |
1583 | } | |
1584 | ||
1585 | /* Return true if the OP represents the Octeon's BBIT instruction. */ | |
1586 | ||
1587 | static int | |
1588 | is_octeon_bbit_op (int op, struct gdbarch *gdbarch) | |
1589 | { | |
1590 | if (!is_octeon (gdbarch)) | |
1591 | return 0; | |
1592 | /* BBIT0 is encoded as LWC2: 110 010. */ | |
1593 | /* BBIT032 is encoded as LDC2: 110 110. */ | |
1594 | /* BBIT1 is encoded as SWC2: 111 010. */ | |
1595 | /* BBIT132 is encoded as SDC2: 111 110. */ | |
1596 | if (op == 50 || op == 54 || op == 58 || op == 62) | |
1597 | return 1; | |
1598 | return 0; | |
1599 | } | |
1600 | ||
1601 | ||
f49e4e6d MS |
1602 | /* Determine where to set a single step breakpoint while considering |
1603 | branch prediction. */ | |
78a59c2f | 1604 | |
5a89d8aa | 1605 | static CORE_ADDR |
7113a196 | 1606 | mips32_next_pc (struct regcache *regcache, CORE_ADDR pc) |
c5aa993b | 1607 | { |
7113a196 | 1608 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
c5aa993b JM |
1609 | unsigned long inst; |
1610 | int op; | |
4cc0665f | 1611 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
4f5bcb50 | 1612 | op = itype_op (inst); |
025bb325 MS |
1613 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch |
1614 | instruction. */ | |
c5aa993b | 1615 | { |
4f5bcb50 | 1616 | if (op >> 2 == 5) |
6d82d43b | 1617 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 1618 | { |
4f5bcb50 | 1619 | switch (op & 0x03) |
c906108c | 1620 | { |
e135b889 DJ |
1621 | case 0: /* BEQL */ |
1622 | goto equal_branch; | |
1623 | case 1: /* BNEL */ | |
1624 | goto neq_branch; | |
1625 | case 2: /* BLEZL */ | |
1626 | goto less_branch; | |
313628cc | 1627 | case 3: /* BGTZL */ |
e135b889 | 1628 | goto greater_branch; |
c5aa993b JM |
1629 | default: |
1630 | pc += 4; | |
c906108c SS |
1631 | } |
1632 | } | |
4f5bcb50 | 1633 | else if (op == 17 && itype_rs (inst) == 8) |
6d82d43b | 1634 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
7113a196 | 1635 | pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 1); |
4f5bcb50 | 1636 | else if (op == 17 && itype_rs (inst) == 9 |
a385295e MR |
1637 | && (itype_rt (inst) & 2) == 0) |
1638 | /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */ | |
7113a196 | 1639 | pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 2); |
4f5bcb50 | 1640 | else if (op == 17 && itype_rs (inst) == 10 |
a385295e MR |
1641 | && (itype_rt (inst) & 2) == 0) |
1642 | /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */ | |
7113a196 | 1643 | pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 4); |
4f5bcb50 | 1644 | else if (op == 29) |
9e8da49c MR |
1645 | /* JALX: 011101 */ |
1646 | /* The new PC will be alternate mode. */ | |
1647 | { | |
1648 | unsigned long reg; | |
1649 | ||
1650 | reg = jtype_target (inst) << 2; | |
1651 | /* Add 1 to indicate 16-bit mode -- invert ISA mode. */ | |
1652 | pc = ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + reg + 1; | |
1653 | } | |
f94363d7 AP |
1654 | else if (is_octeon_bbit_op (op, gdbarch)) |
1655 | { | |
1656 | int bit, branch_if; | |
1657 | ||
1658 | branch_if = op == 58 || op == 62; | |
1659 | bit = itype_rt (inst); | |
1660 | ||
1661 | /* Take into account the *32 instructions. */ | |
1662 | if (op == 54 || op == 62) | |
1663 | bit += 32; | |
1664 | ||
7113a196 YQ |
1665 | if (((regcache_raw_get_signed (regcache, |
1666 | itype_rs (inst)) >> bit) & 1) | |
f94363d7 AP |
1667 | == branch_if) |
1668 | pc += mips32_relative_offset (inst) + 4; | |
1669 | else | |
1670 | pc += 8; /* After the delay slot. */ | |
1671 | } | |
1672 | ||
c5aa993b | 1673 | else |
025bb325 | 1674 | pc += 4; /* Not a branch, next instruction is easy. */ |
c906108c SS |
1675 | } |
1676 | else | |
025bb325 | 1677 | { /* This gets way messy. */ |
c5aa993b | 1678 | |
025bb325 | 1679 | /* Further subdivide into SPECIAL, REGIMM and other. */ |
4f5bcb50 | 1680 | switch (op & 0x07) /* Extract bits 28,27,26. */ |
c906108c | 1681 | { |
c5aa993b JM |
1682 | case 0: /* SPECIAL */ |
1683 | op = rtype_funct (inst); | |
1684 | switch (op) | |
1685 | { | |
1686 | case 8: /* JR */ | |
1687 | case 9: /* JALR */ | |
025bb325 | 1688 | /* Set PC to that address. */ |
7113a196 | 1689 | pc = regcache_raw_get_signed (regcache, rtype_rs (inst)); |
c5aa993b | 1690 | break; |
e38d4e1a DJ |
1691 | case 12: /* SYSCALL */ |
1692 | { | |
1693 | struct gdbarch_tdep *tdep; | |
1694 | ||
7113a196 | 1695 | tdep = gdbarch_tdep (gdbarch); |
e38d4e1a | 1696 | if (tdep->syscall_next_pc != NULL) |
7113a196 | 1697 | pc = tdep->syscall_next_pc (get_current_frame ()); |
e38d4e1a DJ |
1698 | else |
1699 | pc += 4; | |
1700 | } | |
1701 | break; | |
c5aa993b JM |
1702 | default: |
1703 | pc += 4; | |
1704 | } | |
1705 | ||
6d82d43b | 1706 | break; /* end SPECIAL */ |
025bb325 | 1707 | case 1: /* REGIMM */ |
c906108c | 1708 | { |
e135b889 DJ |
1709 | op = itype_rt (inst); /* branch condition */ |
1710 | switch (op) | |
c906108c | 1711 | { |
c5aa993b | 1712 | case 0: /* BLTZ */ |
e135b889 DJ |
1713 | case 2: /* BLTZL */ |
1714 | case 16: /* BLTZAL */ | |
c5aa993b | 1715 | case 18: /* BLTZALL */ |
c906108c | 1716 | less_branch: |
7113a196 | 1717 | if (regcache_raw_get_signed (regcache, itype_rs (inst)) < 0) |
c5aa993b JM |
1718 | pc += mips32_relative_offset (inst) + 4; |
1719 | else | |
1720 | pc += 8; /* after the delay slot */ | |
1721 | break; | |
e135b889 | 1722 | case 1: /* BGEZ */ |
c5aa993b JM |
1723 | case 3: /* BGEZL */ |
1724 | case 17: /* BGEZAL */ | |
1725 | case 19: /* BGEZALL */ | |
7113a196 | 1726 | if (regcache_raw_get_signed (regcache, itype_rs (inst)) >= 0) |
c5aa993b JM |
1727 | pc += mips32_relative_offset (inst) + 4; |
1728 | else | |
1729 | pc += 8; /* after the delay slot */ | |
1730 | break; | |
a385295e MR |
1731 | case 0x1c: /* BPOSGE32 */ |
1732 | case 0x1e: /* BPOSGE64 */ | |
1733 | pc += 4; | |
1734 | if (itype_rs (inst) == 0) | |
1735 | { | |
1736 | unsigned int pos = (op & 2) ? 64 : 32; | |
1737 | int dspctl = mips_regnum (gdbarch)->dspctl; | |
1738 | ||
1739 | if (dspctl == -1) | |
1740 | /* No way to handle; it'll most likely trap anyway. */ | |
1741 | break; | |
1742 | ||
7113a196 YQ |
1743 | if ((regcache_raw_get_unsigned (regcache, |
1744 | dspctl) & 0x7f) >= pos) | |
a385295e MR |
1745 | pc += mips32_relative_offset (inst); |
1746 | else | |
1747 | pc += 4; | |
1748 | } | |
1749 | break; | |
e135b889 | 1750 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1751 | default: |
1752 | pc += 4; | |
c906108c SS |
1753 | } |
1754 | } | |
6d82d43b | 1755 | break; /* end REGIMM */ |
c5aa993b JM |
1756 | case 2: /* J */ |
1757 | case 3: /* JAL */ | |
1758 | { | |
1759 | unsigned long reg; | |
1760 | reg = jtype_target (inst) << 2; | |
025bb325 | 1761 | /* Upper four bits get never changed... */ |
5b652102 | 1762 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
c906108c | 1763 | } |
c5aa993b | 1764 | break; |
e135b889 | 1765 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1766 | equal_branch: |
7113a196 YQ |
1767 | if (regcache_raw_get_signed (regcache, itype_rs (inst)) == |
1768 | regcache_raw_get_signed (regcache, itype_rt (inst))) | |
c5aa993b JM |
1769 | pc += mips32_relative_offset (inst) + 4; |
1770 | else | |
1771 | pc += 8; | |
1772 | break; | |
e135b889 | 1773 | case 5: /* BNE, BNEL */ |
c5aa993b | 1774 | neq_branch: |
7113a196 YQ |
1775 | if (regcache_raw_get_signed (regcache, itype_rs (inst)) != |
1776 | regcache_raw_get_signed (regcache, itype_rt (inst))) | |
c5aa993b JM |
1777 | pc += mips32_relative_offset (inst) + 4; |
1778 | else | |
1779 | pc += 8; | |
1780 | break; | |
e135b889 | 1781 | case 6: /* BLEZ, BLEZL */ |
7113a196 | 1782 | if (regcache_raw_get_signed (regcache, itype_rs (inst)) <= 0) |
c5aa993b JM |
1783 | pc += mips32_relative_offset (inst) + 4; |
1784 | else | |
1785 | pc += 8; | |
1786 | break; | |
1787 | case 7: | |
e135b889 DJ |
1788 | default: |
1789 | greater_branch: /* BGTZ, BGTZL */ | |
7113a196 | 1790 | if (regcache_raw_get_signed (regcache, itype_rs (inst)) > 0) |
c5aa993b JM |
1791 | pc += mips32_relative_offset (inst) + 4; |
1792 | else | |
1793 | pc += 8; | |
1794 | break; | |
c5aa993b JM |
1795 | } /* switch */ |
1796 | } /* else */ | |
1797 | return pc; | |
1798 | } /* mips32_next_pc */ | |
c906108c | 1799 | |
4cc0665f MR |
1800 | /* Extract the 7-bit signed immediate offset from the microMIPS instruction |
1801 | INSN. */ | |
1802 | ||
1803 | static LONGEST | |
1804 | micromips_relative_offset7 (ULONGEST insn) | |
1805 | { | |
1806 | return ((b0s7_imm (insn) ^ 0x40) - 0x40) << 1; | |
1807 | } | |
1808 | ||
1809 | /* Extract the 10-bit signed immediate offset from the microMIPS instruction | |
1810 | INSN. */ | |
1811 | ||
1812 | static LONGEST | |
1813 | micromips_relative_offset10 (ULONGEST insn) | |
1814 | { | |
1815 | return ((b0s10_imm (insn) ^ 0x200) - 0x200) << 1; | |
1816 | } | |
1817 | ||
1818 | /* Extract the 16-bit signed immediate offset from the microMIPS instruction | |
1819 | INSN. */ | |
1820 | ||
1821 | static LONGEST | |
1822 | micromips_relative_offset16 (ULONGEST insn) | |
1823 | { | |
1824 | return ((b0s16_imm (insn) ^ 0x8000) - 0x8000) << 1; | |
1825 | } | |
1826 | ||
1827 | /* Return the size in bytes of the microMIPS instruction at the address PC. */ | |
1828 | ||
1829 | static int | |
1830 | micromips_pc_insn_size (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1831 | { | |
1832 | ULONGEST insn; | |
1833 | ||
1834 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
1835 | return mips_insn_size (ISA_MICROMIPS, insn); | |
1836 | } | |
1837 | ||
1838 | /* Calculate the address of the next microMIPS instruction to execute | |
1839 | after the INSN coprocessor 1 conditional branch instruction at the | |
1840 | address PC. COUNT denotes the number of coprocessor condition bits | |
1841 | examined by the branch. */ | |
1842 | ||
1843 | static CORE_ADDR | |
7113a196 | 1844 | micromips_bc1_pc (struct gdbarch *gdbarch, struct regcache *regcache, |
4cc0665f MR |
1845 | ULONGEST insn, CORE_ADDR pc, int count) |
1846 | { | |
1847 | int fcsr = mips_regnum (gdbarch)->fp_control_status; | |
1848 | int cnum = b2s3_cc (insn >> 16) & (count - 1); | |
1849 | int tf = b5s5_op (insn >> 16) & 1; | |
1850 | int mask = (1 << count) - 1; | |
1851 | ULONGEST fcs; | |
1852 | int cond; | |
1853 | ||
1854 | if (fcsr == -1) | |
1855 | /* No way to handle; it'll most likely trap anyway. */ | |
1856 | return pc; | |
1857 | ||
7113a196 | 1858 | fcs = regcache_raw_get_unsigned (regcache, fcsr); |
4cc0665f MR |
1859 | cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); |
1860 | ||
1861 | if (((cond >> cnum) & mask) != mask * !tf) | |
1862 | pc += micromips_relative_offset16 (insn); | |
1863 | else | |
1864 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1865 | ||
1866 | return pc; | |
1867 | } | |
1868 | ||
1869 | /* Calculate the address of the next microMIPS instruction to execute | |
1870 | after the instruction at the address PC. */ | |
1871 | ||
1872 | static CORE_ADDR | |
7113a196 | 1873 | micromips_next_pc (struct regcache *regcache, CORE_ADDR pc) |
4cc0665f | 1874 | { |
7113a196 | 1875 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
4cc0665f MR |
1876 | ULONGEST insn; |
1877 | ||
1878 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
1879 | pc += MIPS_INSN16_SIZE; | |
1880 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
1881 | { | |
4cc0665f MR |
1882 | /* 32-bit instructions. */ |
1883 | case 2 * MIPS_INSN16_SIZE: | |
1884 | insn <<= 16; | |
1885 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
1886 | pc += MIPS_INSN16_SIZE; | |
1887 | switch (micromips_op (insn >> 16)) | |
1888 | { | |
1889 | case 0x00: /* POOL32A: bits 000000 */ | |
1890 | if (b0s6_op (insn) == 0x3c | |
1891 | /* POOL32Axf: bits 000000 ... 111100 */ | |
1892 | && (b6s10_ext (insn) & 0x2bf) == 0x3c) | |
1893 | /* JALR, JALR.HB: 000000 000x111100 111100 */ | |
1894 | /* JALRS, JALRS.HB: 000000 010x111100 111100 */ | |
7113a196 | 1895 | pc = regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16)); |
4cc0665f MR |
1896 | break; |
1897 | ||
1898 | case 0x10: /* POOL32I: bits 010000 */ | |
1899 | switch (b5s5_op (insn >> 16)) | |
1900 | { | |
1901 | case 0x00: /* BLTZ: bits 010000 00000 */ | |
1902 | case 0x01: /* BLTZAL: bits 010000 00001 */ | |
1903 | case 0x11: /* BLTZALS: bits 010000 10001 */ | |
7113a196 YQ |
1904 | if (regcache_raw_get_signed (regcache, |
1905 | b0s5_reg (insn >> 16)) < 0) | |
4cc0665f MR |
1906 | pc += micromips_relative_offset16 (insn); |
1907 | else | |
1908 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1909 | break; | |
1910 | ||
1911 | case 0x02: /* BGEZ: bits 010000 00010 */ | |
1912 | case 0x03: /* BGEZAL: bits 010000 00011 */ | |
1913 | case 0x13: /* BGEZALS: bits 010000 10011 */ | |
7113a196 YQ |
1914 | if (regcache_raw_get_signed (regcache, |
1915 | b0s5_reg (insn >> 16)) >= 0) | |
4cc0665f MR |
1916 | pc += micromips_relative_offset16 (insn); |
1917 | else | |
1918 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1919 | break; | |
1920 | ||
1921 | case 0x04: /* BLEZ: bits 010000 00100 */ | |
7113a196 YQ |
1922 | if (regcache_raw_get_signed (regcache, |
1923 | b0s5_reg (insn >> 16)) <= 0) | |
4cc0665f MR |
1924 | pc += micromips_relative_offset16 (insn); |
1925 | else | |
1926 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1927 | break; | |
1928 | ||
1929 | case 0x05: /* BNEZC: bits 010000 00101 */ | |
7113a196 YQ |
1930 | if (regcache_raw_get_signed (regcache, |
1931 | b0s5_reg (insn >> 16)) != 0) | |
4cc0665f MR |
1932 | pc += micromips_relative_offset16 (insn); |
1933 | break; | |
1934 | ||
1935 | case 0x06: /* BGTZ: bits 010000 00110 */ | |
7113a196 YQ |
1936 | if (regcache_raw_get_signed (regcache, |
1937 | b0s5_reg (insn >> 16)) > 0) | |
4cc0665f MR |
1938 | pc += micromips_relative_offset16 (insn); |
1939 | else | |
1940 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1941 | break; | |
1942 | ||
1943 | case 0x07: /* BEQZC: bits 010000 00111 */ | |
7113a196 YQ |
1944 | if (regcache_raw_get_signed (regcache, |
1945 | b0s5_reg (insn >> 16)) == 0) | |
4cc0665f MR |
1946 | pc += micromips_relative_offset16 (insn); |
1947 | break; | |
1948 | ||
1949 | case 0x14: /* BC2F: bits 010000 10100 xxx00 */ | |
1950 | case 0x15: /* BC2T: bits 010000 10101 xxx00 */ | |
1951 | if (((insn >> 16) & 0x3) == 0x0) | |
1952 | /* BC2F, BC2T: don't know how to handle these. */ | |
1953 | break; | |
1954 | break; | |
1955 | ||
1956 | case 0x1a: /* BPOSGE64: bits 010000 11010 */ | |
1957 | case 0x1b: /* BPOSGE32: bits 010000 11011 */ | |
1958 | { | |
1959 | unsigned int pos = (b5s5_op (insn >> 16) & 1) ? 32 : 64; | |
1960 | int dspctl = mips_regnum (gdbarch)->dspctl; | |
1961 | ||
1962 | if (dspctl == -1) | |
1963 | /* No way to handle; it'll most likely trap anyway. */ | |
1964 | break; | |
1965 | ||
7113a196 YQ |
1966 | if ((regcache_raw_get_unsigned (regcache, |
1967 | dspctl) & 0x7f) >= pos) | |
4cc0665f MR |
1968 | pc += micromips_relative_offset16 (insn); |
1969 | else | |
1970 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1971 | } | |
1972 | break; | |
1973 | ||
1974 | case 0x1c: /* BC1F: bits 010000 11100 xxx00 */ | |
1975 | /* BC1ANY2F: bits 010000 11100 xxx01 */ | |
1976 | case 0x1d: /* BC1T: bits 010000 11101 xxx00 */ | |
1977 | /* BC1ANY2T: bits 010000 11101 xxx01 */ | |
1978 | if (((insn >> 16) & 0x2) == 0x0) | |
7113a196 | 1979 | pc = micromips_bc1_pc (gdbarch, regcache, insn, pc, |
4cc0665f MR |
1980 | ((insn >> 16) & 0x1) + 1); |
1981 | break; | |
1982 | ||
1983 | case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */ | |
1984 | case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */ | |
1985 | if (((insn >> 16) & 0x3) == 0x1) | |
7113a196 | 1986 | pc = micromips_bc1_pc (gdbarch, regcache, insn, pc, 4); |
4cc0665f MR |
1987 | break; |
1988 | } | |
1989 | break; | |
1990 | ||
1991 | case 0x1d: /* JALS: bits 011101 */ | |
1992 | case 0x35: /* J: bits 110101 */ | |
1993 | case 0x3d: /* JAL: bits 111101 */ | |
1994 | pc = ((pc | 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn) << 1); | |
1995 | break; | |
1996 | ||
1997 | case 0x25: /* BEQ: bits 100101 */ | |
7113a196 YQ |
1998 | if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16)) |
1999 | == regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16))) | |
4cc0665f MR |
2000 | pc += micromips_relative_offset16 (insn); |
2001 | else | |
2002 | pc += micromips_pc_insn_size (gdbarch, pc); | |
2003 | break; | |
2004 | ||
2005 | case 0x2d: /* BNE: bits 101101 */ | |
7113a196 YQ |
2006 | if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16)) |
2007 | != regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16))) | |
4cc0665f MR |
2008 | pc += micromips_relative_offset16 (insn); |
2009 | else | |
2010 | pc += micromips_pc_insn_size (gdbarch, pc); | |
2011 | break; | |
2012 | ||
2013 | case 0x3c: /* JALX: bits 111100 */ | |
2014 | pc = ((pc | 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn) << 2); | |
2015 | break; | |
2016 | } | |
2017 | break; | |
2018 | ||
2019 | /* 16-bit instructions. */ | |
2020 | case MIPS_INSN16_SIZE: | |
2021 | switch (micromips_op (insn)) | |
2022 | { | |
2023 | case 0x11: /* POOL16C: bits 010001 */ | |
2024 | if ((b5s5_op (insn) & 0x1c) == 0xc) | |
2025 | /* JR16, JRC, JALR16, JALRS16: 010001 011xx */ | |
7113a196 | 2026 | pc = regcache_raw_get_signed (regcache, b0s5_reg (insn)); |
4cc0665f MR |
2027 | else if (b5s5_op (insn) == 0x18) |
2028 | /* JRADDIUSP: bits 010001 11000 */ | |
7113a196 | 2029 | pc = regcache_raw_get_signed (regcache, MIPS_RA_REGNUM); |
4cc0665f MR |
2030 | break; |
2031 | ||
2032 | case 0x23: /* BEQZ16: bits 100011 */ | |
2033 | { | |
2034 | int rs = mips_reg3_to_reg[b7s3_reg (insn)]; | |
2035 | ||
7113a196 | 2036 | if (regcache_raw_get_signed (regcache, rs) == 0) |
4cc0665f MR |
2037 | pc += micromips_relative_offset7 (insn); |
2038 | else | |
2039 | pc += micromips_pc_insn_size (gdbarch, pc); | |
2040 | } | |
2041 | break; | |
2042 | ||
2043 | case 0x2b: /* BNEZ16: bits 101011 */ | |
2044 | { | |
2045 | int rs = mips_reg3_to_reg[b7s3_reg (insn)]; | |
2046 | ||
7113a196 | 2047 | if (regcache_raw_get_signed (regcache, rs) != 0) |
4cc0665f MR |
2048 | pc += micromips_relative_offset7 (insn); |
2049 | else | |
2050 | pc += micromips_pc_insn_size (gdbarch, pc); | |
2051 | } | |
2052 | break; | |
2053 | ||
2054 | case 0x33: /* B16: bits 110011 */ | |
2055 | pc += micromips_relative_offset10 (insn); | |
2056 | break; | |
2057 | } | |
2058 | break; | |
2059 | } | |
2060 | ||
2061 | return pc; | |
2062 | } | |
2063 | ||
c906108c | 2064 | /* Decoding the next place to set a breakpoint is irregular for the |
025bb325 MS |
2065 | mips 16 variant, but fortunately, there fewer instructions. We have |
2066 | to cope ith extensions for 16 bit instructions and a pair of actual | |
2067 | 32 bit instructions. We dont want to set a single step instruction | |
2068 | on the extend instruction either. */ | |
c906108c SS |
2069 | |
2070 | /* Lots of mips16 instruction formats */ | |
2071 | /* Predicting jumps requires itype,ritype,i8type | |
025bb325 | 2072 | and their extensions extItype,extritype,extI8type. */ |
c906108c SS |
2073 | enum mips16_inst_fmts |
2074 | { | |
c5aa993b JM |
2075 | itype, /* 0 immediate 5,10 */ |
2076 | ritype, /* 1 5,3,8 */ | |
2077 | rrtype, /* 2 5,3,3,5 */ | |
2078 | rritype, /* 3 5,3,3,5 */ | |
2079 | rrrtype, /* 4 5,3,3,3,2 */ | |
2080 | rriatype, /* 5 5,3,3,1,4 */ | |
2081 | shifttype, /* 6 5,3,3,3,2 */ | |
2082 | i8type, /* 7 5,3,8 */ | |
2083 | i8movtype, /* 8 5,3,3,5 */ | |
2084 | i8mov32rtype, /* 9 5,3,5,3 */ | |
2085 | i64type, /* 10 5,3,8 */ | |
2086 | ri64type, /* 11 5,3,3,5 */ | |
2087 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
2088 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
2089 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
2090 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
2091 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
2092 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
2093 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
2094 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
2095 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
2096 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
2097 | }; | |
12f02c2a | 2098 | /* I am heaping all the fields of the formats into one structure and |
025bb325 | 2099 | then, only the fields which are involved in instruction extension. */ |
c906108c | 2100 | struct upk_mips16 |
6d82d43b AC |
2101 | { |
2102 | CORE_ADDR offset; | |
025bb325 | 2103 | unsigned int regx; /* Function in i8 type. */ |
6d82d43b AC |
2104 | unsigned int regy; |
2105 | }; | |
c906108c SS |
2106 | |
2107 | ||
12f02c2a | 2108 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
c68cf8ad | 2109 | for the bits which make up the immediate extension. */ |
c906108c | 2110 | |
12f02c2a AC |
2111 | static CORE_ADDR |
2112 | extended_offset (unsigned int extension) | |
c906108c | 2113 | { |
12f02c2a | 2114 | CORE_ADDR value; |
130854df | 2115 | |
4c2051c6 | 2116 | value = (extension >> 16) & 0x1f; /* Extract 15:11. */ |
c5aa993b | 2117 | value = value << 6; |
4c2051c6 | 2118 | value |= (extension >> 21) & 0x3f; /* Extract 10:5. */ |
c5aa993b | 2119 | value = value << 5; |
130854df MR |
2120 | value |= extension & 0x1f; /* Extract 4:0. */ |
2121 | ||
c5aa993b | 2122 | return value; |
c906108c SS |
2123 | } |
2124 | ||
2125 | /* Only call this function if you know that this is an extendable | |
bcf1ea1e MR |
2126 | instruction. It won't malfunction, but why make excess remote memory |
2127 | references? If the immediate operands get sign extended or something, | |
2128 | do it after the extension is performed. */ | |
c906108c | 2129 | /* FIXME: Every one of these cases needs to worry about sign extension |
bcf1ea1e | 2130 | when the offset is to be used in relative addressing. */ |
c906108c | 2131 | |
12f02c2a | 2132 | static unsigned int |
e17a4113 | 2133 | fetch_mips_16 (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 2134 | { |
e17a4113 | 2135 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 2136 | gdb_byte buf[8]; |
a2fb2cee MR |
2137 | |
2138 | pc = unmake_compact_addr (pc); /* Clear the low order bit. */ | |
c5aa993b | 2139 | target_read_memory (pc, buf, 2); |
e17a4113 | 2140 | return extract_unsigned_integer (buf, 2, byte_order); |
c906108c SS |
2141 | } |
2142 | ||
2143 | static void | |
e17a4113 | 2144 | unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc, |
12f02c2a AC |
2145 | unsigned int extension, |
2146 | unsigned int inst, | |
6d82d43b | 2147 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 2148 | { |
12f02c2a AC |
2149 | CORE_ADDR offset; |
2150 | int regx; | |
2151 | int regy; | |
2152 | switch (insn_format) | |
c906108c | 2153 | { |
c5aa993b | 2154 | case itype: |
c906108c | 2155 | { |
12f02c2a AC |
2156 | CORE_ADDR value; |
2157 | if (extension) | |
c5aa993b | 2158 | { |
4c2051c6 MR |
2159 | value = extended_offset ((extension << 16) | inst); |
2160 | value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ | |
c906108c SS |
2161 | } |
2162 | else | |
c5aa993b | 2163 | { |
12f02c2a | 2164 | value = inst & 0x7ff; |
4c2051c6 | 2165 | value = (value ^ 0x400) - 0x400; /* Sign-extend. */ |
c906108c | 2166 | } |
12f02c2a AC |
2167 | offset = value; |
2168 | regx = -1; | |
2169 | regy = -1; | |
c906108c | 2170 | } |
c5aa993b JM |
2171 | break; |
2172 | case ritype: | |
2173 | case i8type: | |
025bb325 | 2174 | { /* A register identifier and an offset. */ |
c906108c | 2175 | /* Most of the fields are the same as I type but the |
025bb325 | 2176 | immediate value is of a different length. */ |
12f02c2a AC |
2177 | CORE_ADDR value; |
2178 | if (extension) | |
c906108c | 2179 | { |
4c2051c6 MR |
2180 | value = extended_offset ((extension << 16) | inst); |
2181 | value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ | |
c906108c | 2182 | } |
c5aa993b JM |
2183 | else |
2184 | { | |
4c2051c6 MR |
2185 | value = inst & 0xff; /* 8 bits */ |
2186 | value = (value ^ 0x80) - 0x80; /* Sign-extend. */ | |
c5aa993b | 2187 | } |
12f02c2a | 2188 | offset = value; |
4c2051c6 | 2189 | regx = (inst >> 8) & 0x07; /* i8 funct */ |
12f02c2a | 2190 | regy = -1; |
c5aa993b | 2191 | break; |
c906108c | 2192 | } |
c5aa993b | 2193 | case jalxtype: |
c906108c | 2194 | { |
c5aa993b | 2195 | unsigned long value; |
12f02c2a AC |
2196 | unsigned int nexthalf; |
2197 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b | 2198 | value = value << 16; |
4cc0665f MR |
2199 | nexthalf = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc + 2, NULL); |
2200 | /* Low bit still set. */ | |
c5aa993b | 2201 | value |= nexthalf; |
12f02c2a AC |
2202 | offset = value; |
2203 | regx = -1; | |
2204 | regy = -1; | |
c5aa993b | 2205 | break; |
c906108c SS |
2206 | } |
2207 | default: | |
e2e0b3e5 | 2208 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c | 2209 | } |
12f02c2a AC |
2210 | upk->offset = offset; |
2211 | upk->regx = regx; | |
2212 | upk->regy = regy; | |
c906108c SS |
2213 | } |
2214 | ||
2215 | ||
484933d1 MR |
2216 | /* Calculate the destination of a branch whose 16-bit opcode word is at PC, |
2217 | and having a signed 16-bit OFFSET. */ | |
2218 | ||
c5aa993b JM |
2219 | static CORE_ADDR |
2220 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 2221 | { |
484933d1 | 2222 | return pc + (offset << 1) + 2; |
c906108c SS |
2223 | } |
2224 | ||
12f02c2a | 2225 | static CORE_ADDR |
7113a196 | 2226 | extended_mips16_next_pc (regcache *regcache, CORE_ADDR pc, |
6d82d43b | 2227 | unsigned int extension, unsigned int insn) |
c906108c | 2228 | { |
7113a196 | 2229 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
12f02c2a AC |
2230 | int op = (insn >> 11); |
2231 | switch (op) | |
c906108c | 2232 | { |
6d82d43b | 2233 | case 2: /* Branch */ |
12f02c2a | 2234 | { |
12f02c2a | 2235 | struct upk_mips16 upk; |
e17a4113 | 2236 | unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk); |
484933d1 | 2237 | pc = add_offset_16 (pc, upk.offset); |
12f02c2a AC |
2238 | break; |
2239 | } | |
025bb325 MS |
2240 | case 3: /* JAL , JALX - Watch out, these are 32 bit |
2241 | instructions. */ | |
12f02c2a AC |
2242 | { |
2243 | struct upk_mips16 upk; | |
e17a4113 | 2244 | unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk); |
484933d1 | 2245 | pc = ((pc + 2) & (~(CORE_ADDR) 0x0fffffff)) | (upk.offset << 2); |
12f02c2a | 2246 | if ((insn >> 10) & 0x01) /* Exchange mode */ |
025bb325 | 2247 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode. */ |
12f02c2a AC |
2248 | else |
2249 | pc |= 0x01; | |
2250 | break; | |
2251 | } | |
6d82d43b | 2252 | case 4: /* beqz */ |
12f02c2a AC |
2253 | { |
2254 | struct upk_mips16 upk; | |
2255 | int reg; | |
e17a4113 | 2256 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
7113a196 | 2257 | reg = regcache_raw_get_signed (regcache, mips_reg3_to_reg[upk.regx]); |
12f02c2a | 2258 | if (reg == 0) |
484933d1 | 2259 | pc = add_offset_16 (pc, upk.offset); |
12f02c2a AC |
2260 | else |
2261 | pc += 2; | |
2262 | break; | |
2263 | } | |
6d82d43b | 2264 | case 5: /* bnez */ |
12f02c2a AC |
2265 | { |
2266 | struct upk_mips16 upk; | |
2267 | int reg; | |
e17a4113 | 2268 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
7113a196 | 2269 | reg = regcache_raw_get_signed (regcache, mips_reg3_to_reg[upk.regx]); |
12f02c2a | 2270 | if (reg != 0) |
484933d1 | 2271 | pc = add_offset_16 (pc, upk.offset); |
12f02c2a AC |
2272 | else |
2273 | pc += 2; | |
2274 | break; | |
2275 | } | |
6d82d43b | 2276 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
2277 | { |
2278 | struct upk_mips16 upk; | |
2279 | int reg; | |
e17a4113 | 2280 | unpack_mips16 (gdbarch, pc, extension, insn, i8type, &upk); |
12f02c2a | 2281 | /* upk.regx contains the opcode */ |
7113a196 YQ |
2282 | /* Test register is 24 */ |
2283 | reg = regcache_raw_get_signed (regcache, 24); | |
12f02c2a AC |
2284 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ |
2285 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
484933d1 | 2286 | pc = add_offset_16 (pc, upk.offset); |
12f02c2a AC |
2287 | else |
2288 | pc += 2; | |
2289 | break; | |
2290 | } | |
6d82d43b | 2291 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
2292 | { |
2293 | struct upk_mips16 upk; | |
2294 | /* upk.fmt = rrtype; */ | |
2295 | op = insn & 0x1f; | |
2296 | if (op == 0) | |
c5aa993b | 2297 | { |
12f02c2a AC |
2298 | int reg; |
2299 | upk.regx = (insn >> 8) & 0x07; | |
2300 | upk.regy = (insn >> 5) & 0x07; | |
4c2051c6 | 2301 | if ((upk.regy & 1) == 0) |
4cc0665f | 2302 | reg = mips_reg3_to_reg[upk.regx]; |
4c2051c6 MR |
2303 | else |
2304 | reg = 31; /* Function return instruction. */ | |
7113a196 | 2305 | pc = regcache_raw_get_signed (regcache, reg); |
c906108c | 2306 | } |
12f02c2a | 2307 | else |
c5aa993b | 2308 | pc += 2; |
12f02c2a AC |
2309 | break; |
2310 | } | |
2311 | case 30: | |
2312 | /* This is an instruction extension. Fetch the real instruction | |
2313 | (which follows the extension) and decode things based on | |
025bb325 | 2314 | that. */ |
12f02c2a AC |
2315 | { |
2316 | pc += 2; | |
7113a196 | 2317 | pc = extended_mips16_next_pc (regcache, pc, insn, |
e17a4113 | 2318 | fetch_mips_16 (gdbarch, pc)); |
12f02c2a AC |
2319 | break; |
2320 | } | |
2321 | default: | |
2322 | { | |
2323 | pc += 2; | |
2324 | break; | |
2325 | } | |
c906108c | 2326 | } |
c5aa993b | 2327 | return pc; |
12f02c2a | 2328 | } |
c906108c | 2329 | |
5a89d8aa | 2330 | static CORE_ADDR |
7113a196 | 2331 | mips16_next_pc (struct regcache *regcache, CORE_ADDR pc) |
12f02c2a | 2332 | { |
7113a196 | 2333 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
e17a4113 | 2334 | unsigned int insn = fetch_mips_16 (gdbarch, pc); |
7113a196 | 2335 | return extended_mips16_next_pc (regcache, pc, 0, insn); |
12f02c2a AC |
2336 | } |
2337 | ||
2338 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 2339 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a | 2340 | It works by decoding the current instruction and predicting where a |
1aee363c | 2341 | branch will go. This isn't hard because all the data is available. |
4cc0665f | 2342 | The MIPS32, MIPS16 and microMIPS variants are quite different. */ |
ad527d2e | 2343 | static CORE_ADDR |
7113a196 | 2344 | mips_next_pc (struct regcache *regcache, CORE_ADDR pc) |
c906108c | 2345 | { |
7113a196 | 2346 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
4cc0665f MR |
2347 | |
2348 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
7113a196 | 2349 | return mips16_next_pc (regcache, pc); |
4cc0665f | 2350 | else if (mips_pc_is_micromips (gdbarch, pc)) |
7113a196 | 2351 | return micromips_next_pc (regcache, pc); |
c5aa993b | 2352 | else |
7113a196 | 2353 | return mips32_next_pc (regcache, pc); |
12f02c2a | 2354 | } |
c906108c | 2355 | |
ab50adb6 MR |
2356 | /* Return non-zero if the MIPS16 instruction INSN is a compact branch |
2357 | or jump. */ | |
2358 | ||
2359 | static int | |
2360 | mips16_instruction_is_compact_branch (unsigned short insn) | |
2361 | { | |
2362 | switch (insn & 0xf800) | |
2363 | { | |
2364 | case 0xe800: | |
2365 | return (insn & 0x009f) == 0x80; /* JALRC/JRC */ | |
2366 | case 0x6000: | |
2367 | return (insn & 0x0600) == 0; /* BTNEZ/BTEQZ */ | |
2368 | case 0x2800: /* BNEZ */ | |
2369 | case 0x2000: /* BEQZ */ | |
2370 | case 0x1000: /* B */ | |
2371 | return 1; | |
2372 | default: | |
2373 | return 0; | |
2374 | } | |
2375 | } | |
2376 | ||
2377 | /* Return non-zero if the microMIPS instruction INSN is a compact branch | |
2378 | or jump. */ | |
2379 | ||
2380 | static int | |
2381 | micromips_instruction_is_compact_branch (unsigned short insn) | |
2382 | { | |
2383 | switch (micromips_op (insn)) | |
2384 | { | |
2385 | case 0x11: /* POOL16C: bits 010001 */ | |
2386 | return (b5s5_op (insn) == 0x18 | |
2387 | /* JRADDIUSP: bits 010001 11000 */ | |
2388 | || b5s5_op (insn) == 0xd); | |
2389 | /* JRC: bits 010011 01101 */ | |
2390 | case 0x10: /* POOL32I: bits 010000 */ | |
2391 | return (b5s5_op (insn) & 0x1d) == 0x5; | |
2392 | /* BEQZC/BNEZC: bits 010000 001x1 */ | |
2393 | default: | |
2394 | return 0; | |
2395 | } | |
2396 | } | |
2397 | ||
edfae063 AC |
2398 | struct mips_frame_cache |
2399 | { | |
2400 | CORE_ADDR base; | |
2401 | struct trad_frame_saved_reg *saved_regs; | |
2402 | }; | |
2403 | ||
29639122 JB |
2404 | /* Set a register's saved stack address in temp_saved_regs. If an |
2405 | address has already been set for this register, do nothing; this | |
2406 | way we will only recognize the first save of a given register in a | |
2407 | function prologue. | |
eec63939 | 2408 | |
f57d151a UW |
2409 | For simplicity, save the address in both [0 .. gdbarch_num_regs) and |
2410 | [gdbarch_num_regs .. 2*gdbarch_num_regs). | |
2411 | Strictly speaking, only the second range is used as it is only second | |
2412 | range (the ABI instead of ISA registers) that comes into play when finding | |
2413 | saved registers in a frame. */ | |
eec63939 AC |
2414 | |
2415 | static void | |
74ed0bb4 MD |
2416 | set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache, |
2417 | int regnum, CORE_ADDR offset) | |
eec63939 | 2418 | { |
29639122 JB |
2419 | if (this_cache != NULL |
2420 | && this_cache->saved_regs[regnum].addr == -1) | |
2421 | { | |
74ed0bb4 MD |
2422 | this_cache->saved_regs[regnum + 0 * gdbarch_num_regs (gdbarch)].addr |
2423 | = offset; | |
2424 | this_cache->saved_regs[regnum + 1 * gdbarch_num_regs (gdbarch)].addr | |
2425 | = offset; | |
29639122 | 2426 | } |
eec63939 AC |
2427 | } |
2428 | ||
eec63939 | 2429 | |
29639122 JB |
2430 | /* Fetch the immediate value from a MIPS16 instruction. |
2431 | If the previous instruction was an EXTEND, use it to extend | |
2432 | the upper bits of the immediate value. This is a helper function | |
2433 | for mips16_scan_prologue. */ | |
eec63939 | 2434 | |
29639122 JB |
2435 | static int |
2436 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ | |
2437 | unsigned short inst, /* current instruction */ | |
2438 | int nbits, /* number of bits in imm field */ | |
2439 | int scale, /* scale factor to be applied to imm */ | |
025bb325 | 2440 | int is_signed) /* is the imm field signed? */ |
eec63939 | 2441 | { |
29639122 | 2442 | int offset; |
eec63939 | 2443 | |
29639122 JB |
2444 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
2445 | { | |
2446 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
2447 | if (offset & 0x8000) /* check for negative extend */ | |
2448 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
2449 | return offset | (inst & 0x1f); | |
2450 | } | |
eec63939 | 2451 | else |
29639122 JB |
2452 | { |
2453 | int max_imm = 1 << nbits; | |
2454 | int mask = max_imm - 1; | |
2455 | int sign_bit = max_imm >> 1; | |
45c9dd44 | 2456 | |
29639122 JB |
2457 | offset = inst & mask; |
2458 | if (is_signed && (offset & sign_bit)) | |
2459 | offset = 0 - (max_imm - offset); | |
2460 | return offset * scale; | |
2461 | } | |
2462 | } | |
eec63939 | 2463 | |
65596487 | 2464 | |
29639122 JB |
2465 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
2466 | the associated FRAME_CACHE if not null. | |
2467 | Return the address of the first instruction past the prologue. */ | |
eec63939 | 2468 | |
29639122 | 2469 | static CORE_ADDR |
e17a4113 UW |
2470 | mips16_scan_prologue (struct gdbarch *gdbarch, |
2471 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 2472 | struct frame_info *this_frame, |
29639122 JB |
2473 | struct mips_frame_cache *this_cache) |
2474 | { | |
ab50adb6 MR |
2475 | int prev_non_prologue_insn = 0; |
2476 | int this_non_prologue_insn; | |
2477 | int non_prologue_insns = 0; | |
2478 | CORE_ADDR prev_pc; | |
29639122 | 2479 | CORE_ADDR cur_pc; |
025bb325 | 2480 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer. */ |
29639122 JB |
2481 | CORE_ADDR sp; |
2482 | long frame_offset = 0; /* Size of stack frame. */ | |
2483 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
2484 | int frame_reg = MIPS_SP_REGNUM; | |
025bb325 | 2485 | unsigned short prev_inst = 0; /* saved copy of previous instruction. */ |
29639122 JB |
2486 | unsigned inst = 0; /* current instruction */ |
2487 | unsigned entry_inst = 0; /* the entry instruction */ | |
2207132d | 2488 | unsigned save_inst = 0; /* the save instruction */ |
ab50adb6 MR |
2489 | int prev_delay_slot = 0; |
2490 | int in_delay_slot; | |
29639122 | 2491 | int reg, offset; |
a343eb3c | 2492 | |
29639122 | 2493 | int extend_bytes = 0; |
ab50adb6 MR |
2494 | int prev_extend_bytes = 0; |
2495 | CORE_ADDR end_prologue_addr; | |
a343eb3c | 2496 | |
29639122 | 2497 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
2498 | THIS_FRAME. */ |
2499 | if (this_frame != NULL) | |
2500 | sp = get_frame_register_signed (this_frame, | |
2501 | gdbarch_num_regs (gdbarch) | |
2502 | + MIPS_SP_REGNUM); | |
29639122 JB |
2503 | else |
2504 | sp = 0; | |
eec63939 | 2505 | |
29639122 JB |
2506 | if (limit_pc > start_pc + 200) |
2507 | limit_pc = start_pc + 200; | |
ab50adb6 | 2508 | prev_pc = start_pc; |
eec63939 | 2509 | |
ab50adb6 MR |
2510 | /* Permit at most one non-prologue non-control-transfer instruction |
2511 | in the middle which may have been reordered by the compiler for | |
2512 | optimisation. */ | |
95ac2dcf | 2513 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) |
29639122 | 2514 | { |
ab50adb6 MR |
2515 | this_non_prologue_insn = 0; |
2516 | in_delay_slot = 0; | |
2517 | ||
29639122 JB |
2518 | /* Save the previous instruction. If it's an EXTEND, we'll extract |
2519 | the immediate offset extension from it in mips16_get_imm. */ | |
2520 | prev_inst = inst; | |
eec63939 | 2521 | |
025bb325 | 2522 | /* Fetch and decode the instruction. */ |
4cc0665f MR |
2523 | inst = (unsigned short) mips_fetch_instruction (gdbarch, ISA_MIPS16, |
2524 | cur_pc, NULL); | |
eec63939 | 2525 | |
29639122 JB |
2526 | /* Normally we ignore extend instructions. However, if it is |
2527 | not followed by a valid prologue instruction, then this | |
2528 | instruction is not part of the prologue either. We must | |
2529 | remember in this case to adjust the end_prologue_addr back | |
2530 | over the extend. */ | |
2531 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
2532 | { | |
95ac2dcf | 2533 | extend_bytes = MIPS_INSN16_SIZE; |
29639122 JB |
2534 | continue; |
2535 | } | |
eec63939 | 2536 | |
29639122 JB |
2537 | prev_extend_bytes = extend_bytes; |
2538 | extend_bytes = 0; | |
eec63939 | 2539 | |
29639122 JB |
2540 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
2541 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2542 | { | |
2543 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
025bb325 | 2544 | if (offset < 0) /* Negative stack adjustment? */ |
29639122 JB |
2545 | frame_offset -= offset; |
2546 | else | |
2547 | /* Exit loop if a positive stack adjustment is found, which | |
2548 | usually means that the stack cleanup code in the function | |
2549 | epilogue is reached. */ | |
2550 | break; | |
2551 | } | |
2552 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
2553 | { | |
2554 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
4cc0665f | 2555 | reg = mips_reg3_to_reg[(inst & 0x700) >> 8]; |
74ed0bb4 | 2556 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
2557 | } |
2558 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
2559 | { | |
2560 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
4cc0665f | 2561 | reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
74ed0bb4 | 2562 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
2563 | } |
2564 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
2565 | { | |
2566 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
74ed0bb4 | 2567 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
2568 | } |
2569 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
2570 | { | |
2571 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
74ed0bb4 | 2572 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
2573 | } |
2574 | else if (inst == 0x673d) /* move $s1, $sp */ | |
2575 | { | |
2576 | frame_addr = sp; | |
2577 | frame_reg = 17; | |
2578 | } | |
2579 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
2580 | { | |
2581 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2582 | frame_addr = sp + offset; | |
2583 | frame_reg = 17; | |
2584 | frame_adjust = offset; | |
2585 | } | |
2586 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
2587 | { | |
2588 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
4cc0665f | 2589 | reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
74ed0bb4 | 2590 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
2591 | } |
2592 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
2593 | { | |
2594 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
4cc0665f | 2595 | reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
74ed0bb4 | 2596 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
2597 | } |
2598 | else if ((inst & 0xf81f) == 0xe809 | |
2599 | && (inst & 0x700) != 0x700) /* entry */ | |
025bb325 | 2600 | entry_inst = inst; /* Save for later processing. */ |
2207132d MR |
2601 | else if ((inst & 0xff80) == 0x6480) /* save */ |
2602 | { | |
025bb325 | 2603 | save_inst = inst; /* Save for later processing. */ |
2207132d MR |
2604 | if (prev_extend_bytes) /* extend */ |
2605 | save_inst |= prev_inst << 16; | |
2606 | } | |
29639122 JB |
2607 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
2608 | { | |
2609 | /* This instruction is part of the prologue, but we don't | |
2610 | need to do anything special to handle it. */ | |
2611 | } | |
ab50adb6 MR |
2612 | else if (mips16_instruction_has_delay_slot (inst, 0)) |
2613 | /* JAL/JALR/JALX/JR */ | |
2614 | { | |
2615 | /* The instruction in the delay slot can be a part | |
2616 | of the prologue, so move forward once more. */ | |
2617 | in_delay_slot = 1; | |
2618 | if (mips16_instruction_has_delay_slot (inst, 1)) | |
2619 | /* JAL/JALX */ | |
2620 | { | |
2621 | prev_extend_bytes = MIPS_INSN16_SIZE; | |
2622 | cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ | |
2623 | } | |
2624 | } | |
29639122 JB |
2625 | else |
2626 | { | |
ab50adb6 | 2627 | this_non_prologue_insn = 1; |
29639122 | 2628 | } |
ab50adb6 MR |
2629 | |
2630 | non_prologue_insns += this_non_prologue_insn; | |
2631 | ||
2632 | /* A jump or branch, or enough non-prologue insns seen? If so, | |
2633 | then we must have reached the end of the prologue by now. */ | |
2634 | if (prev_delay_slot || non_prologue_insns > 1 | |
2635 | || mips16_instruction_is_compact_branch (inst)) | |
2636 | break; | |
2637 | ||
2638 | prev_non_prologue_insn = this_non_prologue_insn; | |
2639 | prev_delay_slot = in_delay_slot; | |
2640 | prev_pc = cur_pc - prev_extend_bytes; | |
29639122 | 2641 | } |
eec63939 | 2642 | |
29639122 JB |
2643 | /* The entry instruction is typically the first instruction in a function, |
2644 | and it stores registers at offsets relative to the value of the old SP | |
2645 | (before the prologue). But the value of the sp parameter to this | |
2646 | function is the new SP (after the prologue has been executed). So we | |
2647 | can't calculate those offsets until we've seen the entire prologue, | |
025bb325 | 2648 | and can calculate what the old SP must have been. */ |
29639122 JB |
2649 | if (entry_inst != 0) |
2650 | { | |
2651 | int areg_count = (entry_inst >> 8) & 7; | |
2652 | int sreg_count = (entry_inst >> 6) & 3; | |
eec63939 | 2653 | |
29639122 JB |
2654 | /* The entry instruction always subtracts 32 from the SP. */ |
2655 | frame_offset += 32; | |
2656 | ||
2657 | /* Now we can calculate what the SP must have been at the | |
2658 | start of the function prologue. */ | |
2659 | sp += frame_offset; | |
2660 | ||
2661 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
2662 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
2663 | { | |
74ed0bb4 | 2664 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 2665 | offset += mips_abi_regsize (gdbarch); |
29639122 JB |
2666 | } |
2667 | ||
2668 | /* Check if the ra register was pushed on the stack. */ | |
2669 | offset = -4; | |
2670 | if (entry_inst & 0x20) | |
2671 | { | |
74ed0bb4 | 2672 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
72a155b4 | 2673 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
2674 | } |
2675 | ||
2676 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
2677 | for (reg = 16; reg < sreg_count + 16; reg++) | |
2678 | { | |
74ed0bb4 | 2679 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 2680 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
2681 | } |
2682 | } | |
2683 | ||
2207132d MR |
2684 | /* The SAVE instruction is similar to ENTRY, except that defined by the |
2685 | MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the | |
2686 | size of the frame is specified as an immediate field of instruction | |
2687 | and an extended variation exists which lets additional registers and | |
2688 | frame space to be specified. The instruction always treats registers | |
2689 | as 32-bit so its usefulness for 64-bit ABIs is questionable. */ | |
2690 | if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4) | |
2691 | { | |
2692 | static int args_table[16] = { | |
2693 | 0, 0, 0, 0, 1, 1, 1, 1, | |
2694 | 2, 2, 2, 0, 3, 3, 4, -1, | |
2695 | }; | |
2696 | static int astatic_table[16] = { | |
2697 | 0, 1, 2, 3, 0, 1, 2, 3, | |
2698 | 0, 1, 2, 4, 0, 1, 0, -1, | |
2699 | }; | |
2700 | int aregs = (save_inst >> 16) & 0xf; | |
2701 | int xsregs = (save_inst >> 24) & 0x7; | |
2702 | int args = args_table[aregs]; | |
2703 | int astatic = astatic_table[aregs]; | |
2704 | long frame_size; | |
2705 | ||
2706 | if (args < 0) | |
2707 | { | |
2708 | warning (_("Invalid number of argument registers encoded in SAVE.")); | |
2709 | args = 0; | |
2710 | } | |
2711 | if (astatic < 0) | |
2712 | { | |
2713 | warning (_("Invalid number of static registers encoded in SAVE.")); | |
2714 | astatic = 0; | |
2715 | } | |
2716 | ||
2717 | /* For standard SAVE the frame size of 0 means 128. */ | |
2718 | frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf); | |
2719 | if (frame_size == 0 && (save_inst >> 16) == 0) | |
2720 | frame_size = 16; | |
2721 | frame_size *= 8; | |
2722 | frame_offset += frame_size; | |
2723 | ||
2724 | /* Now we can calculate what the SP must have been at the | |
2725 | start of the function prologue. */ | |
2726 | sp += frame_offset; | |
2727 | ||
2728 | /* Check if A0-A3 were saved in the caller's argument save area. */ | |
2729 | for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++) | |
2730 | { | |
74ed0bb4 | 2731 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
2732 | offset += mips_abi_regsize (gdbarch); |
2733 | } | |
2734 | ||
2735 | offset = -4; | |
2736 | ||
2737 | /* Check if the RA register was pushed on the stack. */ | |
2738 | if (save_inst & 0x40) | |
2739 | { | |
74ed0bb4 | 2740 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
2207132d MR |
2741 | offset -= mips_abi_regsize (gdbarch); |
2742 | } | |
2743 | ||
2744 | /* Check if the S8 register was pushed on the stack. */ | |
2745 | if (xsregs > 6) | |
2746 | { | |
74ed0bb4 | 2747 | set_reg_offset (gdbarch, this_cache, 30, sp + offset); |
2207132d MR |
2748 | offset -= mips_abi_regsize (gdbarch); |
2749 | xsregs--; | |
2750 | } | |
2751 | /* Check if S2-S7 were pushed on the stack. */ | |
2752 | for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--) | |
2753 | { | |
74ed0bb4 | 2754 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
2755 | offset -= mips_abi_regsize (gdbarch); |
2756 | } | |
2757 | ||
2758 | /* Check if the S1 register was pushed on the stack. */ | |
2759 | if (save_inst & 0x10) | |
2760 | { | |
74ed0bb4 | 2761 | set_reg_offset (gdbarch, this_cache, 17, sp + offset); |
2207132d MR |
2762 | offset -= mips_abi_regsize (gdbarch); |
2763 | } | |
2764 | /* Check if the S0 register was pushed on the stack. */ | |
2765 | if (save_inst & 0x20) | |
2766 | { | |
74ed0bb4 | 2767 | set_reg_offset (gdbarch, this_cache, 16, sp + offset); |
2207132d MR |
2768 | offset -= mips_abi_regsize (gdbarch); |
2769 | } | |
2770 | ||
4cc0665f MR |
2771 | /* Check if A0-A3 were pushed on the stack. */ |
2772 | for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--) | |
2773 | { | |
2774 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); | |
2775 | offset -= mips_abi_regsize (gdbarch); | |
2776 | } | |
2777 | } | |
2778 | ||
2779 | if (this_cache != NULL) | |
2780 | { | |
2781 | this_cache->base = | |
2782 | (get_frame_register_signed (this_frame, | |
2783 | gdbarch_num_regs (gdbarch) + frame_reg) | |
2784 | + frame_offset - frame_adjust); | |
2785 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should | |
2786 | be able to get rid of the assignment below, evetually. But it's | |
2787 | still needed for now. */ | |
2788 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) | |
2789 | + mips_regnum (gdbarch)->pc] | |
2790 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; | |
2791 | } | |
2792 | ||
ab50adb6 MR |
2793 | /* Set end_prologue_addr to the address of the instruction immediately |
2794 | after the last one we scanned. Unless the last one looked like a | |
2795 | non-prologue instruction (and we looked ahead), in which case use | |
2796 | its address instead. */ | |
2797 | end_prologue_addr = (prev_non_prologue_insn || prev_delay_slot | |
2798 | ? prev_pc : cur_pc - prev_extend_bytes); | |
4cc0665f MR |
2799 | |
2800 | return end_prologue_addr; | |
2801 | } | |
2802 | ||
2803 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). | |
2804 | Procedures that use the 32-bit instruction set are handled by the | |
2805 | mips_insn32 unwinder. */ | |
2806 | ||
2807 | static struct mips_frame_cache * | |
2808 | mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache) | |
2809 | { | |
2810 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2811 | struct mips_frame_cache *cache; | |
2812 | ||
2813 | if ((*this_cache) != NULL) | |
19ba03f4 | 2814 | return (struct mips_frame_cache *) (*this_cache); |
4cc0665f MR |
2815 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
2816 | (*this_cache) = cache; | |
2817 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
2818 | ||
2819 | /* Analyze the function prologue. */ | |
2820 | { | |
2821 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); | |
2822 | CORE_ADDR start_addr; | |
2823 | ||
2824 | find_pc_partial_function (pc, NULL, &start_addr, NULL); | |
2825 | if (start_addr == 0) | |
2826 | start_addr = heuristic_proc_start (gdbarch, pc); | |
2827 | /* We can't analyze the prologue if we couldn't find the begining | |
2828 | of the function. */ | |
2829 | if (start_addr == 0) | |
2830 | return cache; | |
2831 | ||
19ba03f4 SM |
2832 | mips16_scan_prologue (gdbarch, start_addr, pc, this_frame, |
2833 | (struct mips_frame_cache *) *this_cache); | |
4cc0665f MR |
2834 | } |
2835 | ||
2836 | /* gdbarch_sp_regnum contains the value and not the address. */ | |
2837 | trad_frame_set_value (cache->saved_regs, | |
2838 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, | |
2839 | cache->base); | |
2840 | ||
19ba03f4 | 2841 | return (struct mips_frame_cache *) (*this_cache); |
4cc0665f MR |
2842 | } |
2843 | ||
2844 | static void | |
2845 | mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache, | |
2846 | struct frame_id *this_id) | |
2847 | { | |
2848 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, | |
2849 | this_cache); | |
2850 | /* This marks the outermost frame. */ | |
2851 | if (info->base == 0) | |
2852 | return; | |
2853 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); | |
2854 | } | |
2855 | ||
2856 | static struct value * | |
2857 | mips_insn16_frame_prev_register (struct frame_info *this_frame, | |
2858 | void **this_cache, int regnum) | |
2859 | { | |
2860 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, | |
2861 | this_cache); | |
2862 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); | |
2863 | } | |
2864 | ||
2865 | static int | |
2866 | mips_insn16_frame_sniffer (const struct frame_unwind *self, | |
2867 | struct frame_info *this_frame, void **this_cache) | |
2868 | { | |
2869 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2870 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2871 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
2872 | return 1; | |
2873 | return 0; | |
2874 | } | |
2875 | ||
2876 | static const struct frame_unwind mips_insn16_frame_unwind = | |
2877 | { | |
2878 | NORMAL_FRAME, | |
2879 | default_frame_unwind_stop_reason, | |
2880 | mips_insn16_frame_this_id, | |
2881 | mips_insn16_frame_prev_register, | |
2882 | NULL, | |
2883 | mips_insn16_frame_sniffer | |
2884 | }; | |
2885 | ||
2886 | static CORE_ADDR | |
2887 | mips_insn16_frame_base_address (struct frame_info *this_frame, | |
2888 | void **this_cache) | |
2889 | { | |
2890 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, | |
2891 | this_cache); | |
2892 | return info->base; | |
2893 | } | |
2894 | ||
2895 | static const struct frame_base mips_insn16_frame_base = | |
2896 | { | |
2897 | &mips_insn16_frame_unwind, | |
2898 | mips_insn16_frame_base_address, | |
2899 | mips_insn16_frame_base_address, | |
2900 | mips_insn16_frame_base_address | |
2901 | }; | |
2902 | ||
2903 | static const struct frame_base * | |
2904 | mips_insn16_frame_base_sniffer (struct frame_info *this_frame) | |
2905 | { | |
2906 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2907 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2908 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
2909 | return &mips_insn16_frame_base; | |
2910 | else | |
2911 | return NULL; | |
2912 | } | |
2913 | ||
2914 | /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped | |
2915 | to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are | |
2916 | interpreted directly, and then multiplied by 4. */ | |
2917 | ||
2918 | static int | |
2919 | micromips_decode_imm9 (int imm) | |
2920 | { | |
2921 | imm = (imm ^ 0x100) - 0x100; | |
2922 | if (imm > -3 && imm < 2) | |
2923 | imm ^= 0x100; | |
2924 | return imm << 2; | |
2925 | } | |
2926 | ||
2927 | /* Analyze the function prologue from START_PC to LIMIT_PC. Return | |
2928 | the address of the first instruction past the prologue. */ | |
2929 | ||
2930 | static CORE_ADDR | |
2931 | micromips_scan_prologue (struct gdbarch *gdbarch, | |
2932 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
2933 | struct frame_info *this_frame, | |
2934 | struct mips_frame_cache *this_cache) | |
2935 | { | |
ab50adb6 | 2936 | CORE_ADDR end_prologue_addr; |
4cc0665f MR |
2937 | int prev_non_prologue_insn = 0; |
2938 | int frame_reg = MIPS_SP_REGNUM; | |
2939 | int this_non_prologue_insn; | |
2940 | int non_prologue_insns = 0; | |
2941 | long frame_offset = 0; /* Size of stack frame. */ | |
2942 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
ab50adb6 MR |
2943 | int prev_delay_slot = 0; |
2944 | int in_delay_slot; | |
4cc0665f MR |
2945 | CORE_ADDR prev_pc; |
2946 | CORE_ADDR cur_pc; | |
2947 | ULONGEST insn; /* current instruction */ | |
2948 | CORE_ADDR sp; | |
2949 | long offset; | |
2950 | long sp_adj; | |
2951 | long v1_off = 0; /* The assumption is LUI will replace it. */ | |
2952 | int reglist; | |
2953 | int breg; | |
2954 | int dreg; | |
2955 | int sreg; | |
2956 | int treg; | |
2957 | int loc; | |
2958 | int op; | |
2959 | int s; | |
2960 | int i; | |
2961 | ||
2962 | /* Can be called when there's no process, and hence when there's no | |
2963 | THIS_FRAME. */ | |
2964 | if (this_frame != NULL) | |
2965 | sp = get_frame_register_signed (this_frame, | |
2966 | gdbarch_num_regs (gdbarch) | |
2967 | + MIPS_SP_REGNUM); | |
2968 | else | |
2969 | sp = 0; | |
2970 | ||
2971 | if (limit_pc > start_pc + 200) | |
2972 | limit_pc = start_pc + 200; | |
2973 | prev_pc = start_pc; | |
2974 | ||
2975 | /* Permit at most one non-prologue non-control-transfer instruction | |
2976 | in the middle which may have been reordered by the compiler for | |
2977 | optimisation. */ | |
2978 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += loc) | |
2979 | { | |
2980 | this_non_prologue_insn = 0; | |
ab50adb6 | 2981 | in_delay_slot = 0; |
4cc0665f MR |
2982 | sp_adj = 0; |
2983 | loc = 0; | |
2984 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, cur_pc, NULL); | |
2985 | loc += MIPS_INSN16_SIZE; | |
2986 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
2987 | { | |
4cc0665f MR |
2988 | /* 32-bit instructions. */ |
2989 | case 2 * MIPS_INSN16_SIZE: | |
2990 | insn <<= 16; | |
2991 | insn |= mips_fetch_instruction (gdbarch, | |
2992 | ISA_MICROMIPS, cur_pc + loc, NULL); | |
2993 | loc += MIPS_INSN16_SIZE; | |
2994 | switch (micromips_op (insn >> 16)) | |
2995 | { | |
2996 | /* Record $sp/$fp adjustment. */ | |
2997 | /* Discard (D)ADDU $gp,$jp used for PIC code. */ | |
2998 | case 0x0: /* POOL32A: bits 000000 */ | |
2999 | case 0x16: /* POOL32S: bits 010110 */ | |
3000 | op = b0s11_op (insn); | |
3001 | sreg = b0s5_reg (insn >> 16); | |
3002 | treg = b5s5_reg (insn >> 16); | |
3003 | dreg = b11s5_reg (insn); | |
3004 | if (op == 0x1d0 | |
3005 | /* SUBU: bits 000000 00111010000 */ | |
3006 | /* DSUBU: bits 010110 00111010000 */ | |
3007 | && dreg == MIPS_SP_REGNUM && sreg == MIPS_SP_REGNUM | |
3008 | && treg == 3) | |
3009 | /* (D)SUBU $sp, $v1 */ | |
3010 | sp_adj = v1_off; | |
3011 | else if (op != 0x150 | |
3012 | /* ADDU: bits 000000 00101010000 */ | |
3013 | /* DADDU: bits 010110 00101010000 */ | |
3014 | || dreg != 28 || sreg != 28 || treg != MIPS_T9_REGNUM) | |
3015 | this_non_prologue_insn = 1; | |
3016 | break; | |
3017 | ||
3018 | case 0x8: /* POOL32B: bits 001000 */ | |
3019 | op = b12s4_op (insn); | |
3020 | breg = b0s5_reg (insn >> 16); | |
3021 | reglist = sreg = b5s5_reg (insn >> 16); | |
3022 | offset = (b0s12_imm (insn) ^ 0x800) - 0x800; | |
3023 | if ((op == 0x9 || op == 0xc) | |
3024 | /* SWP: bits 001000 1001 */ | |
3025 | /* SDP: bits 001000 1100 */ | |
3026 | && breg == MIPS_SP_REGNUM && sreg < MIPS_RA_REGNUM) | |
3027 | /* S[DW]P reg,offset($sp) */ | |
3028 | { | |
3029 | s = 4 << ((b12s4_op (insn) & 0x4) == 0x4); | |
3030 | set_reg_offset (gdbarch, this_cache, | |
3031 | sreg, sp + offset); | |
3032 | set_reg_offset (gdbarch, this_cache, | |
3033 | sreg + 1, sp + offset + s); | |
3034 | } | |
3035 | else if ((op == 0xd || op == 0xf) | |
3036 | /* SWM: bits 001000 1101 */ | |
3037 | /* SDM: bits 001000 1111 */ | |
3038 | && breg == MIPS_SP_REGNUM | |
3039 | /* SWM reglist,offset($sp) */ | |
3040 | && ((reglist >= 1 && reglist <= 9) | |
3041 | || (reglist >= 16 && reglist <= 25))) | |
3042 | { | |
325fac50 | 3043 | int sreglist = std::min(reglist & 0xf, 8); |
4cc0665f MR |
3044 | |
3045 | s = 4 << ((b12s4_op (insn) & 0x2) == 0x2); | |
3046 | for (i = 0; i < sreglist; i++) | |
3047 | set_reg_offset (gdbarch, this_cache, 16 + i, sp + s * i); | |
3048 | if ((reglist & 0xf) > 8) | |
3049 | set_reg_offset (gdbarch, this_cache, 30, sp + s * i++); | |
3050 | if ((reglist & 0x10) == 0x10) | |
3051 | set_reg_offset (gdbarch, this_cache, | |
3052 | MIPS_RA_REGNUM, sp + s * i++); | |
3053 | } | |
3054 | else | |
3055 | this_non_prologue_insn = 1; | |
3056 | break; | |
3057 | ||
3058 | /* Record $sp/$fp adjustment. */ | |
3059 | /* Discard (D)ADDIU $gp used for PIC code. */ | |
3060 | case 0xc: /* ADDIU: bits 001100 */ | |
3061 | case 0x17: /* DADDIU: bits 010111 */ | |
3062 | sreg = b0s5_reg (insn >> 16); | |
3063 | dreg = b5s5_reg (insn >> 16); | |
3064 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
3065 | if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM) | |
3066 | /* (D)ADDIU $sp, imm */ | |
3067 | sp_adj = offset; | |
3068 | else if (sreg == MIPS_SP_REGNUM && dreg == 30) | |
3069 | /* (D)ADDIU $fp, $sp, imm */ | |
3070 | { | |
4cc0665f MR |
3071 | frame_adjust = offset; |
3072 | frame_reg = 30; | |
3073 | } | |
3074 | else if (sreg != 28 || dreg != 28) | |
3075 | /* (D)ADDIU $gp, imm */ | |
3076 | this_non_prologue_insn = 1; | |
3077 | break; | |
3078 | ||
3079 | /* LUI $v1 is used for larger $sp adjustments. */ | |
3356937a | 3080 | /* Discard LUI $gp used for PIC code. */ |
4cc0665f MR |
3081 | case 0x10: /* POOL32I: bits 010000 */ |
3082 | if (b5s5_op (insn >> 16) == 0xd | |
3083 | /* LUI: bits 010000 001101 */ | |
3084 | && b0s5_reg (insn >> 16) == 3) | |
3085 | /* LUI $v1, imm */ | |
3086 | v1_off = ((b0s16_imm (insn) << 16) ^ 0x80000000) - 0x80000000; | |
3087 | else if (b5s5_op (insn >> 16) != 0xd | |
3088 | /* LUI: bits 010000 001101 */ | |
3089 | || b0s5_reg (insn >> 16) != 28) | |
3090 | /* LUI $gp, imm */ | |
3091 | this_non_prologue_insn = 1; | |
3092 | break; | |
3093 | ||
3094 | /* ORI $v1 is used for larger $sp adjustments. */ | |
3095 | case 0x14: /* ORI: bits 010100 */ | |
3096 | sreg = b0s5_reg (insn >> 16); | |
3097 | dreg = b5s5_reg (insn >> 16); | |
3098 | if (sreg == 3 && dreg == 3) | |
3099 | /* ORI $v1, imm */ | |
3100 | v1_off |= b0s16_imm (insn); | |
3101 | else | |
3102 | this_non_prologue_insn = 1; | |
3103 | break; | |
3104 | ||
3105 | case 0x26: /* SWC1: bits 100110 */ | |
3106 | case 0x2e: /* SDC1: bits 101110 */ | |
3107 | breg = b0s5_reg (insn >> 16); | |
3108 | if (breg != MIPS_SP_REGNUM) | |
3109 | /* S[DW]C1 reg,offset($sp) */ | |
3110 | this_non_prologue_insn = 1; | |
3111 | break; | |
3112 | ||
3113 | case 0x36: /* SD: bits 110110 */ | |
3114 | case 0x3e: /* SW: bits 111110 */ | |
3115 | breg = b0s5_reg (insn >> 16); | |
3116 | sreg = b5s5_reg (insn >> 16); | |
3117 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
3118 | if (breg == MIPS_SP_REGNUM) | |
3119 | /* S[DW] reg,offset($sp) */ | |
3120 | set_reg_offset (gdbarch, this_cache, sreg, sp + offset); | |
3121 | else | |
3122 | this_non_prologue_insn = 1; | |
3123 | break; | |
3124 | ||
3125 | default: | |
ab50adb6 MR |
3126 | /* The instruction in the delay slot can be a part |
3127 | of the prologue, so move forward once more. */ | |
3128 | if (micromips_instruction_has_delay_slot (insn, 0)) | |
3129 | in_delay_slot = 1; | |
3130 | else | |
3131 | this_non_prologue_insn = 1; | |
4cc0665f MR |
3132 | break; |
3133 | } | |
ab50adb6 | 3134 | insn >>= 16; |
4cc0665f MR |
3135 | break; |
3136 | ||
3137 | /* 16-bit instructions. */ | |
3138 | case MIPS_INSN16_SIZE: | |
3139 | switch (micromips_op (insn)) | |
3140 | { | |
3141 | case 0x3: /* MOVE: bits 000011 */ | |
3142 | sreg = b0s5_reg (insn); | |
3143 | dreg = b5s5_reg (insn); | |
3144 | if (sreg == MIPS_SP_REGNUM && dreg == 30) | |
3145 | /* MOVE $fp, $sp */ | |
78cc6c2d | 3146 | frame_reg = 30; |
4cc0665f MR |
3147 | else if ((sreg & 0x1c) != 0x4) |
3148 | /* MOVE reg, $a0-$a3 */ | |
3149 | this_non_prologue_insn = 1; | |
3150 | break; | |
3151 | ||
3152 | case 0x11: /* POOL16C: bits 010001 */ | |
3153 | if (b6s4_op (insn) == 0x5) | |
3154 | /* SWM: bits 010001 0101 */ | |
3155 | { | |
3156 | offset = ((b0s4_imm (insn) << 2) ^ 0x20) - 0x20; | |
3157 | reglist = b4s2_regl (insn); | |
3158 | for (i = 0; i <= reglist; i++) | |
3159 | set_reg_offset (gdbarch, this_cache, 16 + i, sp + 4 * i); | |
3160 | set_reg_offset (gdbarch, this_cache, | |
3161 | MIPS_RA_REGNUM, sp + 4 * i++); | |
3162 | } | |
3163 | else | |
3164 | this_non_prologue_insn = 1; | |
3165 | break; | |
3166 | ||
3167 | case 0x13: /* POOL16D: bits 010011 */ | |
3168 | if ((insn & 0x1) == 0x1) | |
3169 | /* ADDIUSP: bits 010011 1 */ | |
3170 | sp_adj = micromips_decode_imm9 (b1s9_imm (insn)); | |
3171 | else if (b5s5_reg (insn) == MIPS_SP_REGNUM) | |
3172 | /* ADDIUS5: bits 010011 0 */ | |
3173 | /* ADDIUS5 $sp, imm */ | |
3174 | sp_adj = (b1s4_imm (insn) ^ 8) - 8; | |
3175 | else | |
3176 | this_non_prologue_insn = 1; | |
3177 | break; | |
3178 | ||
3179 | case 0x32: /* SWSP: bits 110010 */ | |
3180 | offset = b0s5_imm (insn) << 2; | |
3181 | sreg = b5s5_reg (insn); | |
3182 | set_reg_offset (gdbarch, this_cache, sreg, sp + offset); | |
3183 | break; | |
3184 | ||
3185 | default: | |
ab50adb6 MR |
3186 | /* The instruction in the delay slot can be a part |
3187 | of the prologue, so move forward once more. */ | |
3188 | if (micromips_instruction_has_delay_slot (insn << 16, 0)) | |
3189 | in_delay_slot = 1; | |
3190 | else | |
3191 | this_non_prologue_insn = 1; | |
4cc0665f MR |
3192 | break; |
3193 | } | |
3194 | break; | |
3195 | } | |
3196 | if (sp_adj < 0) | |
3197 | frame_offset -= sp_adj; | |
3198 | ||
3199 | non_prologue_insns += this_non_prologue_insn; | |
ab50adb6 MR |
3200 | |
3201 | /* A jump or branch, enough non-prologue insns seen or positive | |
3202 | stack adjustment? If so, then we must have reached the end | |
3203 | of the prologue by now. */ | |
3204 | if (prev_delay_slot || non_prologue_insns > 1 || sp_adj > 0 | |
3205 | || micromips_instruction_is_compact_branch (insn)) | |
3206 | break; | |
3207 | ||
4cc0665f | 3208 | prev_non_prologue_insn = this_non_prologue_insn; |
ab50adb6 | 3209 | prev_delay_slot = in_delay_slot; |
4cc0665f | 3210 | prev_pc = cur_pc; |
2207132d MR |
3211 | } |
3212 | ||
29639122 JB |
3213 | if (this_cache != NULL) |
3214 | { | |
3215 | this_cache->base = | |
4cc0665f | 3216 | (get_frame_register_signed (this_frame, |
b8a22b94 | 3217 | gdbarch_num_regs (gdbarch) + frame_reg) |
4cc0665f | 3218 | + frame_offset - frame_adjust); |
29639122 | 3219 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should |
4cc0665f MR |
3220 | be able to get rid of the assignment below, evetually. But it's |
3221 | still needed for now. */ | |
72a155b4 UW |
3222 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
3223 | + mips_regnum (gdbarch)->pc] | |
4cc0665f | 3224 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; |
29639122 JB |
3225 | } |
3226 | ||
ab50adb6 MR |
3227 | /* Set end_prologue_addr to the address of the instruction immediately |
3228 | after the last one we scanned. Unless the last one looked like a | |
3229 | non-prologue instruction (and we looked ahead), in which case use | |
3230 | its address instead. */ | |
3231 | end_prologue_addr | |
3232 | = prev_non_prologue_insn || prev_delay_slot ? prev_pc : cur_pc; | |
29639122 JB |
3233 | |
3234 | return end_prologue_addr; | |
eec63939 AC |
3235 | } |
3236 | ||
4cc0665f | 3237 | /* Heuristic unwinder for procedures using microMIPS instructions. |
29639122 | 3238 | Procedures that use the 32-bit instruction set are handled by the |
4cc0665f | 3239 | mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */ |
29639122 JB |
3240 | |
3241 | static struct mips_frame_cache * | |
4cc0665f | 3242 | mips_micro_frame_cache (struct frame_info *this_frame, void **this_cache) |
eec63939 | 3243 | { |
e17a4113 | 3244 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 3245 | struct mips_frame_cache *cache; |
eec63939 AC |
3246 | |
3247 | if ((*this_cache) != NULL) | |
19ba03f4 | 3248 | return (struct mips_frame_cache *) (*this_cache); |
4cc0665f | 3249 | |
29639122 JB |
3250 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
3251 | (*this_cache) = cache; | |
b8a22b94 | 3252 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
eec63939 | 3253 | |
29639122 JB |
3254 | /* Analyze the function prologue. */ |
3255 | { | |
b8a22b94 | 3256 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 3257 | CORE_ADDR start_addr; |
eec63939 | 3258 | |
29639122 JB |
3259 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
3260 | if (start_addr == 0) | |
4cc0665f | 3261 | start_addr = heuristic_proc_start (get_frame_arch (this_frame), pc); |
29639122 JB |
3262 | /* We can't analyze the prologue if we couldn't find the begining |
3263 | of the function. */ | |
3264 | if (start_addr == 0) | |
3265 | return cache; | |
eec63939 | 3266 | |
19ba03f4 SM |
3267 | micromips_scan_prologue (gdbarch, start_addr, pc, this_frame, |
3268 | (struct mips_frame_cache *) *this_cache); | |
29639122 | 3269 | } |
4cc0665f | 3270 | |
3e8c568d | 3271 | /* gdbarch_sp_regnum contains the value and not the address. */ |
72a155b4 | 3272 | trad_frame_set_value (cache->saved_regs, |
e17a4113 | 3273 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
72a155b4 | 3274 | cache->base); |
eec63939 | 3275 | |
19ba03f4 | 3276 | return (struct mips_frame_cache *) (*this_cache); |
eec63939 AC |
3277 | } |
3278 | ||
3279 | static void | |
4cc0665f MR |
3280 | mips_micro_frame_this_id (struct frame_info *this_frame, void **this_cache, |
3281 | struct frame_id *this_id) | |
eec63939 | 3282 | { |
4cc0665f MR |
3283 | struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
3284 | this_cache); | |
21327321 DJ |
3285 | /* This marks the outermost frame. */ |
3286 | if (info->base == 0) | |
3287 | return; | |
b8a22b94 | 3288 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
eec63939 AC |
3289 | } |
3290 | ||
b8a22b94 | 3291 | static struct value * |
4cc0665f MR |
3292 | mips_micro_frame_prev_register (struct frame_info *this_frame, |
3293 | void **this_cache, int regnum) | |
eec63939 | 3294 | { |
4cc0665f MR |
3295 | struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
3296 | this_cache); | |
b8a22b94 DJ |
3297 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
3298 | } | |
3299 | ||
3300 | static int | |
4cc0665f MR |
3301 | mips_micro_frame_sniffer (const struct frame_unwind *self, |
3302 | struct frame_info *this_frame, void **this_cache) | |
b8a22b94 | 3303 | { |
4cc0665f | 3304 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
b8a22b94 | 3305 | CORE_ADDR pc = get_frame_pc (this_frame); |
4cc0665f MR |
3306 | |
3307 | if (mips_pc_is_micromips (gdbarch, pc)) | |
b8a22b94 DJ |
3308 | return 1; |
3309 | return 0; | |
eec63939 AC |
3310 | } |
3311 | ||
4cc0665f | 3312 | static const struct frame_unwind mips_micro_frame_unwind = |
eec63939 AC |
3313 | { |
3314 | NORMAL_FRAME, | |
8fbca658 | 3315 | default_frame_unwind_stop_reason, |
4cc0665f MR |
3316 | mips_micro_frame_this_id, |
3317 | mips_micro_frame_prev_register, | |
b8a22b94 | 3318 | NULL, |
4cc0665f | 3319 | mips_micro_frame_sniffer |
eec63939 AC |
3320 | }; |
3321 | ||
eec63939 | 3322 | static CORE_ADDR |
4cc0665f MR |
3323 | mips_micro_frame_base_address (struct frame_info *this_frame, |
3324 | void **this_cache) | |
eec63939 | 3325 | { |
4cc0665f MR |
3326 | struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
3327 | this_cache); | |
29639122 | 3328 | return info->base; |
eec63939 AC |
3329 | } |
3330 | ||
4cc0665f | 3331 | static const struct frame_base mips_micro_frame_base = |
eec63939 | 3332 | { |
4cc0665f MR |
3333 | &mips_micro_frame_unwind, |
3334 | mips_micro_frame_base_address, | |
3335 | mips_micro_frame_base_address, | |
3336 | mips_micro_frame_base_address | |
eec63939 AC |
3337 | }; |
3338 | ||
3339 | static const struct frame_base * | |
4cc0665f | 3340 | mips_micro_frame_base_sniffer (struct frame_info *this_frame) |
eec63939 | 3341 | { |
4cc0665f | 3342 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
b8a22b94 | 3343 | CORE_ADDR pc = get_frame_pc (this_frame); |
4cc0665f MR |
3344 | |
3345 | if (mips_pc_is_micromips (gdbarch, pc)) | |
3346 | return &mips_micro_frame_base; | |
eec63939 AC |
3347 | else |
3348 | return NULL; | |
edfae063 AC |
3349 | } |
3350 | ||
29639122 JB |
3351 | /* Mark all the registers as unset in the saved_regs array |
3352 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
3353 | ||
74ed0bb4 MD |
3354 | static void |
3355 | reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache) | |
c906108c | 3356 | { |
29639122 JB |
3357 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
3358 | return; | |
3359 | ||
3360 | { | |
74ed0bb4 | 3361 | const int num_regs = gdbarch_num_regs (gdbarch); |
29639122 | 3362 | int i; |
64159455 | 3363 | |
29639122 JB |
3364 | for (i = 0; i < num_regs; i++) |
3365 | { | |
3366 | this_cache->saved_regs[i].addr = -1; | |
3367 | } | |
3368 | } | |
c906108c SS |
3369 | } |
3370 | ||
025bb325 | 3371 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
29639122 JB |
3372 | the associated FRAME_CACHE if not null. |
3373 | Return the address of the first instruction past the prologue. */ | |
c906108c | 3374 | |
875e1767 | 3375 | static CORE_ADDR |
e17a4113 UW |
3376 | mips32_scan_prologue (struct gdbarch *gdbarch, |
3377 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 3378 | struct frame_info *this_frame, |
29639122 | 3379 | struct mips_frame_cache *this_cache) |
c906108c | 3380 | { |
ab50adb6 MR |
3381 | int prev_non_prologue_insn; |
3382 | int this_non_prologue_insn; | |
3383 | int non_prologue_insns; | |
025bb325 MS |
3384 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for |
3385 | frame-pointer. */ | |
ab50adb6 MR |
3386 | int prev_delay_slot; |
3387 | CORE_ADDR prev_pc; | |
3388 | CORE_ADDR cur_pc; | |
29639122 JB |
3389 | CORE_ADDR sp; |
3390 | long frame_offset; | |
3391 | int frame_reg = MIPS_SP_REGNUM; | |
8fa9cfa1 | 3392 | |
ab50adb6 | 3393 | CORE_ADDR end_prologue_addr; |
29639122 JB |
3394 | int seen_sp_adjust = 0; |
3395 | int load_immediate_bytes = 0; | |
ab50adb6 | 3396 | int in_delay_slot; |
7d1e6fb8 | 3397 | int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8); |
8fa9cfa1 | 3398 | |
29639122 | 3399 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
3400 | THIS_FRAME. */ |
3401 | if (this_frame != NULL) | |
3402 | sp = get_frame_register_signed (this_frame, | |
3403 | gdbarch_num_regs (gdbarch) | |
3404 | + MIPS_SP_REGNUM); | |
8fa9cfa1 | 3405 | else |
29639122 | 3406 | sp = 0; |
9022177c | 3407 | |
29639122 JB |
3408 | if (limit_pc > start_pc + 200) |
3409 | limit_pc = start_pc + 200; | |
9022177c | 3410 | |
29639122 | 3411 | restart: |
ab50adb6 MR |
3412 | prev_non_prologue_insn = 0; |
3413 | non_prologue_insns = 0; | |
3414 | prev_delay_slot = 0; | |
3415 | prev_pc = start_pc; | |
9022177c | 3416 | |
ab50adb6 MR |
3417 | /* Permit at most one non-prologue non-control-transfer instruction |
3418 | in the middle which may have been reordered by the compiler for | |
3419 | optimisation. */ | |
29639122 | 3420 | frame_offset = 0; |
95ac2dcf | 3421 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) |
9022177c | 3422 | { |
eaa6a9a4 MR |
3423 | unsigned long inst, high_word; |
3424 | long offset; | |
29639122 | 3425 | int reg; |
9022177c | 3426 | |
ab50adb6 MR |
3427 | this_non_prologue_insn = 0; |
3428 | in_delay_slot = 0; | |
3429 | ||
025bb325 | 3430 | /* Fetch the instruction. */ |
4cc0665f MR |
3431 | inst = (unsigned long) mips_fetch_instruction (gdbarch, ISA_MIPS, |
3432 | cur_pc, NULL); | |
9022177c | 3433 | |
29639122 JB |
3434 | /* Save some code by pre-extracting some useful fields. */ |
3435 | high_word = (inst >> 16) & 0xffff; | |
eaa6a9a4 | 3436 | offset = ((inst & 0xffff) ^ 0x8000) - 0x8000; |
29639122 | 3437 | reg = high_word & 0x1f; |
fe29b929 | 3438 | |
025bb325 | 3439 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
29639122 JB |
3440 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
3441 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
3442 | { | |
eaa6a9a4 MR |
3443 | if (offset < 0) /* Negative stack adjustment? */ |
3444 | frame_offset -= offset; | |
29639122 JB |
3445 | else |
3446 | /* Exit loop if a positive stack adjustment is found, which | |
3447 | usually means that the stack cleanup code in the function | |
3448 | epilogue is reached. */ | |
3449 | break; | |
3450 | seen_sp_adjust = 1; | |
3451 | } | |
7d1e6fb8 KB |
3452 | else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ |
3453 | && !regsize_is_64_bits) | |
29639122 | 3454 | { |
eaa6a9a4 | 3455 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 | 3456 | } |
7d1e6fb8 KB |
3457 | else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ |
3458 | && regsize_is_64_bits) | |
29639122 JB |
3459 | { |
3460 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ | |
eaa6a9a4 | 3461 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
3462 | } |
3463 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
3464 | { | |
3465 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
eaa6a9a4 MR |
3466 | if (offset != frame_offset) |
3467 | frame_addr = sp + offset; | |
b8a22b94 | 3468 | else if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
3469 | { |
3470 | unsigned alloca_adjust; | |
a4b8ebc8 | 3471 | |
29639122 | 3472 | frame_reg = 30; |
b8a22b94 DJ |
3473 | frame_addr = get_frame_register_signed |
3474 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
ca9c94ef | 3475 | frame_offset = 0; |
d2ca4222 | 3476 | |
eaa6a9a4 | 3477 | alloca_adjust = (unsigned) (frame_addr - (sp + offset)); |
29639122 JB |
3478 | if (alloca_adjust > 0) |
3479 | { | |
025bb325 | 3480 | /* FP > SP + frame_size. This may be because of |
29639122 JB |
3481 | an alloca or somethings similar. Fix sp to |
3482 | "pre-alloca" value, and try again. */ | |
3483 | sp += alloca_adjust; | |
3484 | /* Need to reset the status of all registers. Otherwise, | |
3485 | we will hit a guard that prevents the new address | |
3486 | for each register to be recomputed during the second | |
3487 | pass. */ | |
74ed0bb4 | 3488 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
3489 | goto restart; |
3490 | } | |
3491 | } | |
3492 | } | |
3493 | /* move $30,$sp. With different versions of gas this will be either | |
3494 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
3495 | Accept any one of these. */ | |
3496 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
3497 | { | |
3498 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
b8a22b94 | 3499 | if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
3500 | { |
3501 | unsigned alloca_adjust; | |
c906108c | 3502 | |
29639122 | 3503 | frame_reg = 30; |
b8a22b94 DJ |
3504 | frame_addr = get_frame_register_signed |
3505 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 3506 | |
29639122 JB |
3507 | alloca_adjust = (unsigned) (frame_addr - sp); |
3508 | if (alloca_adjust > 0) | |
3509 | { | |
025bb325 | 3510 | /* FP > SP + frame_size. This may be because of |
29639122 JB |
3511 | an alloca or somethings similar. Fix sp to |
3512 | "pre-alloca" value, and try again. */ | |
3513 | sp = frame_addr; | |
3514 | /* Need to reset the status of all registers. Otherwise, | |
3515 | we will hit a guard that prevents the new address | |
3516 | for each register to be recomputed during the second | |
3517 | pass. */ | |
74ed0bb4 | 3518 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
3519 | goto restart; |
3520 | } | |
3521 | } | |
3522 | } | |
7d1e6fb8 KB |
3523 | else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */ |
3524 | && !regsize_is_64_bits) | |
29639122 | 3525 | { |
eaa6a9a4 | 3526 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
3527 | } |
3528 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | |
3529 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ | |
3530 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | |
3531 | || high_word == 0x3c1c /* lui $gp,n */ | |
3532 | || high_word == 0x279c /* addiu $gp,$gp,n */ | |
3533 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
3534 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | |
3535 | ) | |
19080931 MR |
3536 | { |
3537 | /* These instructions are part of the prologue, but we don't | |
3538 | need to do anything special to handle them. */ | |
3539 | } | |
29639122 JB |
3540 | /* The instructions below load $at or $t0 with an immediate |
3541 | value in preparation for a stack adjustment via | |
025bb325 | 3542 | subu $sp,$sp,[$at,$t0]. These instructions could also |
29639122 JB |
3543 | initialize a local variable, so we accept them only before |
3544 | a stack adjustment instruction was seen. */ | |
3545 | else if (!seen_sp_adjust | |
ab50adb6 | 3546 | && !prev_delay_slot |
19080931 MR |
3547 | && (high_word == 0x3c01 /* lui $at,n */ |
3548 | || high_word == 0x3c08 /* lui $t0,n */ | |
3549 | || high_word == 0x3421 /* ori $at,$at,n */ | |
3550 | || high_word == 0x3508 /* ori $t0,$t0,n */ | |
3551 | || high_word == 0x3401 /* ori $at,$zero,n */ | |
3552 | || high_word == 0x3408 /* ori $t0,$zero,n */ | |
3553 | )) | |
3554 | { | |
ab50adb6 | 3555 | load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ |
19080931 | 3556 | } |
ab50adb6 MR |
3557 | /* Check for branches and jumps. The instruction in the delay |
3558 | slot can be a part of the prologue, so move forward once more. */ | |
3559 | else if (mips32_instruction_has_delay_slot (gdbarch, inst)) | |
3560 | { | |
3561 | in_delay_slot = 1; | |
3562 | } | |
3563 | /* This instruction is not an instruction typically found | |
3564 | in a prologue, so we must have reached the end of the | |
3565 | prologue. */ | |
29639122 | 3566 | else |
19080931 | 3567 | { |
ab50adb6 | 3568 | this_non_prologue_insn = 1; |
19080931 | 3569 | } |
db5f024e | 3570 | |
ab50adb6 MR |
3571 | non_prologue_insns += this_non_prologue_insn; |
3572 | ||
3573 | /* A jump or branch, or enough non-prologue insns seen? If so, | |
3574 | then we must have reached the end of the prologue by now. */ | |
3575 | if (prev_delay_slot || non_prologue_insns > 1) | |
db5f024e | 3576 | break; |
ab50adb6 MR |
3577 | |
3578 | prev_non_prologue_insn = this_non_prologue_insn; | |
3579 | prev_delay_slot = in_delay_slot; | |
3580 | prev_pc = cur_pc; | |
a4b8ebc8 | 3581 | } |
c906108c | 3582 | |
29639122 JB |
3583 | if (this_cache != NULL) |
3584 | { | |
3585 | this_cache->base = | |
b8a22b94 DJ |
3586 | (get_frame_register_signed (this_frame, |
3587 | gdbarch_num_regs (gdbarch) + frame_reg) | |
29639122 JB |
3588 | + frame_offset); |
3589 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of | |
3590 | this assignment below, eventually. But it's still needed | |
3591 | for now. */ | |
72a155b4 UW |
3592 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
3593 | + mips_regnum (gdbarch)->pc] | |
3594 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) | |
f57d151a | 3595 | + MIPS_RA_REGNUM]; |
29639122 | 3596 | } |
c906108c | 3597 | |
ab50adb6 MR |
3598 | /* Set end_prologue_addr to the address of the instruction immediately |
3599 | after the last one we scanned. Unless the last one looked like a | |
3600 | non-prologue instruction (and we looked ahead), in which case use | |
3601 | its address instead. */ | |
3602 | end_prologue_addr | |
3603 | = prev_non_prologue_insn || prev_delay_slot ? prev_pc : cur_pc; | |
29639122 JB |
3604 | |
3605 | /* In a frameless function, we might have incorrectly | |
025bb325 | 3606 | skipped some load immediate instructions. Undo the skipping |
29639122 JB |
3607 | if the load immediate was not followed by a stack adjustment. */ |
3608 | if (load_immediate_bytes && !seen_sp_adjust) | |
3609 | end_prologue_addr -= load_immediate_bytes; | |
c906108c | 3610 | |
29639122 | 3611 | return end_prologue_addr; |
c906108c SS |
3612 | } |
3613 | ||
29639122 JB |
3614 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
3615 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
3616 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
4cc0665f | 3617 | unwinder. Likewise microMIPS and the mips_micro unwinder. */ |
c906108c | 3618 | |
29639122 | 3619 | static struct mips_frame_cache * |
b8a22b94 | 3620 | mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache) |
c906108c | 3621 | { |
e17a4113 | 3622 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 3623 | struct mips_frame_cache *cache; |
c906108c | 3624 | |
29639122 | 3625 | if ((*this_cache) != NULL) |
19ba03f4 | 3626 | return (struct mips_frame_cache *) (*this_cache); |
c5aa993b | 3627 | |
29639122 JB |
3628 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
3629 | (*this_cache) = cache; | |
b8a22b94 | 3630 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
c5aa993b | 3631 | |
29639122 JB |
3632 | /* Analyze the function prologue. */ |
3633 | { | |
b8a22b94 | 3634 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 3635 | CORE_ADDR start_addr; |
c906108c | 3636 | |
29639122 JB |
3637 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
3638 | if (start_addr == 0) | |
e17a4113 | 3639 | start_addr = heuristic_proc_start (gdbarch, pc); |
29639122 JB |
3640 | /* We can't analyze the prologue if we couldn't find the begining |
3641 | of the function. */ | |
3642 | if (start_addr == 0) | |
3643 | return cache; | |
c5aa993b | 3644 | |
19ba03f4 SM |
3645 | mips32_scan_prologue (gdbarch, start_addr, pc, this_frame, |
3646 | (struct mips_frame_cache *) *this_cache); | |
29639122 JB |
3647 | } |
3648 | ||
3e8c568d | 3649 | /* gdbarch_sp_regnum contains the value and not the address. */ |
f57d151a | 3650 | trad_frame_set_value (cache->saved_regs, |
e17a4113 | 3651 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
f57d151a | 3652 | cache->base); |
c5aa993b | 3653 | |
19ba03f4 | 3654 | return (struct mips_frame_cache *) (*this_cache); |
c906108c SS |
3655 | } |
3656 | ||
29639122 | 3657 | static void |
b8a22b94 | 3658 | mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 | 3659 | struct frame_id *this_id) |
c906108c | 3660 | { |
b8a22b94 | 3661 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 3662 | this_cache); |
21327321 DJ |
3663 | /* This marks the outermost frame. */ |
3664 | if (info->base == 0) | |
3665 | return; | |
b8a22b94 | 3666 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
29639122 | 3667 | } |
c906108c | 3668 | |
b8a22b94 DJ |
3669 | static struct value * |
3670 | mips_insn32_frame_prev_register (struct frame_info *this_frame, | |
3671 | void **this_cache, int regnum) | |
29639122 | 3672 | { |
b8a22b94 | 3673 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 3674 | this_cache); |
b8a22b94 DJ |
3675 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
3676 | } | |
3677 | ||
3678 | static int | |
3679 | mips_insn32_frame_sniffer (const struct frame_unwind *self, | |
3680 | struct frame_info *this_frame, void **this_cache) | |
3681 | { | |
3682 | CORE_ADDR pc = get_frame_pc (this_frame); | |
4cc0665f | 3683 | if (mips_pc_is_mips (pc)) |
b8a22b94 DJ |
3684 | return 1; |
3685 | return 0; | |
c906108c SS |
3686 | } |
3687 | ||
29639122 JB |
3688 | static const struct frame_unwind mips_insn32_frame_unwind = |
3689 | { | |
3690 | NORMAL_FRAME, | |
8fbca658 | 3691 | default_frame_unwind_stop_reason, |
29639122 | 3692 | mips_insn32_frame_this_id, |
b8a22b94 DJ |
3693 | mips_insn32_frame_prev_register, |
3694 | NULL, | |
3695 | mips_insn32_frame_sniffer | |
29639122 | 3696 | }; |
c906108c | 3697 | |
1c645fec | 3698 | static CORE_ADDR |
b8a22b94 | 3699 | mips_insn32_frame_base_address (struct frame_info *this_frame, |
29639122 | 3700 | void **this_cache) |
c906108c | 3701 | { |
b8a22b94 | 3702 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 JB |
3703 | this_cache); |
3704 | return info->base; | |
3705 | } | |
c906108c | 3706 | |
29639122 JB |
3707 | static const struct frame_base mips_insn32_frame_base = |
3708 | { | |
3709 | &mips_insn32_frame_unwind, | |
3710 | mips_insn32_frame_base_address, | |
3711 | mips_insn32_frame_base_address, | |
3712 | mips_insn32_frame_base_address | |
3713 | }; | |
1c645fec | 3714 | |
29639122 | 3715 | static const struct frame_base * |
b8a22b94 | 3716 | mips_insn32_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 3717 | { |
b8a22b94 | 3718 | CORE_ADDR pc = get_frame_pc (this_frame); |
4cc0665f | 3719 | if (mips_pc_is_mips (pc)) |
29639122 | 3720 | return &mips_insn32_frame_base; |
a65bbe44 | 3721 | else |
29639122 JB |
3722 | return NULL; |
3723 | } | |
a65bbe44 | 3724 | |
29639122 | 3725 | static struct trad_frame_cache * |
b8a22b94 | 3726 | mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache) |
29639122 JB |
3727 | { |
3728 | CORE_ADDR pc; | |
3729 | CORE_ADDR start_addr; | |
3730 | CORE_ADDR stack_addr; | |
3731 | struct trad_frame_cache *this_trad_cache; | |
b8a22b94 DJ |
3732 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
3733 | int num_regs = gdbarch_num_regs (gdbarch); | |
c906108c | 3734 | |
29639122 | 3735 | if ((*this_cache) != NULL) |
19ba03f4 | 3736 | return (struct trad_frame_cache *) (*this_cache); |
b8a22b94 | 3737 | this_trad_cache = trad_frame_cache_zalloc (this_frame); |
29639122 | 3738 | (*this_cache) = this_trad_cache; |
1c645fec | 3739 | |
29639122 | 3740 | /* The return address is in the link register. */ |
3e8c568d | 3741 | trad_frame_set_reg_realreg (this_trad_cache, |
72a155b4 | 3742 | gdbarch_pc_regnum (gdbarch), |
b8a22b94 | 3743 | num_regs + MIPS_RA_REGNUM); |
1c645fec | 3744 | |
29639122 JB |
3745 | /* Frame ID, since it's a frameless / stackless function, no stack |
3746 | space is allocated and SP on entry is the current SP. */ | |
b8a22b94 | 3747 | pc = get_frame_pc (this_frame); |
29639122 | 3748 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
b8a22b94 DJ |
3749 | stack_addr = get_frame_register_signed (this_frame, |
3750 | num_regs + MIPS_SP_REGNUM); | |
aa6c981f | 3751 | trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr)); |
1c645fec | 3752 | |
29639122 JB |
3753 | /* Assume that the frame's base is the same as the |
3754 | stack-pointer. */ | |
3755 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
c906108c | 3756 | |
29639122 JB |
3757 | return this_trad_cache; |
3758 | } | |
c906108c | 3759 | |
29639122 | 3760 | static void |
b8a22b94 | 3761 | mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 JB |
3762 | struct frame_id *this_id) |
3763 | { | |
3764 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 3765 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
3766 | trad_frame_get_id (this_trad_cache, this_id); |
3767 | } | |
c906108c | 3768 | |
b8a22b94 DJ |
3769 | static struct value * |
3770 | mips_stub_frame_prev_register (struct frame_info *this_frame, | |
3771 | void **this_cache, int regnum) | |
29639122 JB |
3772 | { |
3773 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 DJ |
3774 | = mips_stub_frame_cache (this_frame, this_cache); |
3775 | return trad_frame_get_register (this_trad_cache, this_frame, regnum); | |
29639122 | 3776 | } |
c906108c | 3777 | |
b8a22b94 DJ |
3778 | static int |
3779 | mips_stub_frame_sniffer (const struct frame_unwind *self, | |
3780 | struct frame_info *this_frame, void **this_cache) | |
29639122 | 3781 | { |
aa6c981f | 3782 | gdb_byte dummy[4]; |
979b38e0 | 3783 | struct obj_section *s; |
b8a22b94 | 3784 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
7cbd4a93 | 3785 | struct bound_minimal_symbol msym; |
979b38e0 | 3786 | |
aa6c981f | 3787 | /* Use the stub unwinder for unreadable code. */ |
b8a22b94 DJ |
3788 | if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) |
3789 | return 1; | |
aa6c981f | 3790 | |
3e5d3a5a | 3791 | if (in_plt_section (pc) || in_mips_stubs_section (pc)) |
b8a22b94 | 3792 | return 1; |
979b38e0 | 3793 | |
db5f024e DJ |
3794 | /* Calling a PIC function from a non-PIC function passes through a |
3795 | stub. The stub for foo is named ".pic.foo". */ | |
3796 | msym = lookup_minimal_symbol_by_pc (pc); | |
7cbd4a93 | 3797 | if (msym.minsym != NULL |
efd66ac6 | 3798 | && MSYMBOL_LINKAGE_NAME (msym.minsym) != NULL |
61012eef | 3799 | && startswith (MSYMBOL_LINKAGE_NAME (msym.minsym), ".pic.")) |
db5f024e DJ |
3800 | return 1; |
3801 | ||
b8a22b94 | 3802 | return 0; |
29639122 | 3803 | } |
c906108c | 3804 | |
b8a22b94 DJ |
3805 | static const struct frame_unwind mips_stub_frame_unwind = |
3806 | { | |
3807 | NORMAL_FRAME, | |
8fbca658 | 3808 | default_frame_unwind_stop_reason, |
b8a22b94 DJ |
3809 | mips_stub_frame_this_id, |
3810 | mips_stub_frame_prev_register, | |
3811 | NULL, | |
3812 | mips_stub_frame_sniffer | |
3813 | }; | |
3814 | ||
29639122 | 3815 | static CORE_ADDR |
b8a22b94 | 3816 | mips_stub_frame_base_address (struct frame_info *this_frame, |
29639122 JB |
3817 | void **this_cache) |
3818 | { | |
3819 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 3820 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
3821 | return trad_frame_get_this_base (this_trad_cache); |
3822 | } | |
0fce0821 | 3823 | |
29639122 JB |
3824 | static const struct frame_base mips_stub_frame_base = |
3825 | { | |
3826 | &mips_stub_frame_unwind, | |
3827 | mips_stub_frame_base_address, | |
3828 | mips_stub_frame_base_address, | |
3829 | mips_stub_frame_base_address | |
3830 | }; | |
3831 | ||
3832 | static const struct frame_base * | |
b8a22b94 | 3833 | mips_stub_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 3834 | { |
b8a22b94 | 3835 | if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL)) |
29639122 JB |
3836 | return &mips_stub_frame_base; |
3837 | else | |
3838 | return NULL; | |
3839 | } | |
3840 | ||
29639122 | 3841 | /* mips_addr_bits_remove - remove useless address bits */ |
65596487 | 3842 | |
29639122 | 3843 | static CORE_ADDR |
24568a2c | 3844 | mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) |
65596487 | 3845 | { |
24568a2c | 3846 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
930bd0e0 | 3847 | |
29639122 JB |
3848 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) |
3849 | /* This hack is a work-around for existing boards using PMON, the | |
3850 | simulator, and any other 64-bit targets that doesn't have true | |
3851 | 64-bit addressing. On these targets, the upper 32 bits of | |
3852 | addresses are ignored by the hardware. Thus, the PC or SP are | |
3853 | likely to have been sign extended to all 1s by instruction | |
3854 | sequences that load 32-bit addresses. For example, a typical | |
3855 | piece of code that loads an address is this: | |
65596487 | 3856 | |
29639122 JB |
3857 | lui $r2, <upper 16 bits> |
3858 | ori $r2, <lower 16 bits> | |
65596487 | 3859 | |
29639122 JB |
3860 | But the lui sign-extends the value such that the upper 32 bits |
3861 | may be all 1s. The workaround is simply to mask off these | |
3862 | bits. In the future, gcc may be changed to support true 64-bit | |
3863 | addressing, and this masking will have to be disabled. */ | |
3864 | return addr &= 0xffffffffUL; | |
3865 | else | |
3866 | return addr; | |
65596487 JB |
3867 | } |
3868 | ||
3d5f6d12 DJ |
3869 | |
3870 | /* Checks for an atomic sequence of instructions beginning with a LL/LLD | |
3871 | instruction and ending with a SC/SCD instruction. If such a sequence | |
3872 | is found, attempt to step through it. A breakpoint is placed at the end of | |
3873 | the sequence. */ | |
3874 | ||
4cc0665f MR |
3875 | /* Instructions used during single-stepping of atomic sequences, standard |
3876 | ISA version. */ | |
3877 | #define LL_OPCODE 0x30 | |
3878 | #define LLD_OPCODE 0x34 | |
3879 | #define SC_OPCODE 0x38 | |
3880 | #define SCD_OPCODE 0x3c | |
3881 | ||
93f9a11f YQ |
3882 | static VEC (CORE_ADDR) * |
3883 | mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) | |
3d5f6d12 DJ |
3884 | { |
3885 | CORE_ADDR breaks[2] = {-1, -1}; | |
3886 | CORE_ADDR loc = pc; | |
3887 | CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ | |
4cc0665f | 3888 | ULONGEST insn; |
3d5f6d12 DJ |
3889 | int insn_count; |
3890 | int index; | |
3891 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
3892 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
93f9a11f | 3893 | VEC (CORE_ADDR) *next_pcs = NULL; |
3d5f6d12 | 3894 | |
4cc0665f | 3895 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); |
3d5f6d12 DJ |
3896 | /* Assume all atomic sequences start with a ll/lld instruction. */ |
3897 | if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE) | |
93f9a11f | 3898 | return NULL; |
3d5f6d12 DJ |
3899 | |
3900 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" | |
3901 | instructions. */ | |
3902 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
3903 | { | |
3904 | int is_branch = 0; | |
3905 | loc += MIPS_INSN32_SIZE; | |
4cc0665f | 3906 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); |
3d5f6d12 DJ |
3907 | |
3908 | /* Assume that there is at most one branch in the atomic | |
3909 | sequence. If a branch is found, put a breakpoint in its | |
3910 | destination address. */ | |
3911 | switch (itype_op (insn)) | |
3912 | { | |
3913 | case 0: /* SPECIAL */ | |
3914 | if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */ | |
025bb325 | 3915 | return 0; /* fallback to the standard single-step code. */ |
3d5f6d12 DJ |
3916 | break; |
3917 | case 1: /* REGIMM */ | |
a385295e MR |
3918 | is_branch = ((itype_rt (insn) & 0xc) == 0 /* B{LT,GE}Z* */ |
3919 | || ((itype_rt (insn) & 0x1e) == 0 | |
3920 | && itype_rs (insn) == 0)); /* BPOSGE* */ | |
3d5f6d12 DJ |
3921 | break; |
3922 | case 2: /* J */ | |
3923 | case 3: /* JAL */ | |
025bb325 | 3924 | return 0; /* fallback to the standard single-step code. */ |
3d5f6d12 DJ |
3925 | case 4: /* BEQ */ |
3926 | case 5: /* BNE */ | |
3927 | case 6: /* BLEZ */ | |
3928 | case 7: /* BGTZ */ | |
3929 | case 20: /* BEQL */ | |
3930 | case 21: /* BNEL */ | |
3931 | case 22: /* BLEZL */ | |
3932 | case 23: /* BGTTL */ | |
3933 | is_branch = 1; | |
3934 | break; | |
3935 | case 17: /* COP1 */ | |
a385295e MR |
3936 | is_branch = ((itype_rs (insn) == 9 || itype_rs (insn) == 10) |
3937 | && (itype_rt (insn) & 0x2) == 0); | |
3938 | if (is_branch) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */ | |
3939 | break; | |
3940 | /* Fall through. */ | |
3d5f6d12 DJ |
3941 | case 18: /* COP2 */ |
3942 | case 19: /* COP3 */ | |
3943 | is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */ | |
3944 | break; | |
3945 | } | |
3946 | if (is_branch) | |
3947 | { | |
3948 | branch_bp = loc + mips32_relative_offset (insn) + 4; | |
3949 | if (last_breakpoint >= 1) | |
3950 | return 0; /* More than one branch found, fallback to the | |
3951 | standard single-step code. */ | |
3952 | breaks[1] = branch_bp; | |
3953 | last_breakpoint++; | |
3954 | } | |
3955 | ||
3956 | if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE) | |
3957 | break; | |
3958 | } | |
3959 | ||
3960 | /* Assume that the atomic sequence ends with a sc/scd instruction. */ | |
3961 | if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE) | |
93f9a11f | 3962 | return NULL; |
3d5f6d12 DJ |
3963 | |
3964 | loc += MIPS_INSN32_SIZE; | |
3965 | ||
3966 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
3967 | breaks[0] = loc; | |
3968 | ||
3969 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
025bb325 | 3970 | placed (branch instruction's destination) in the atomic sequence. */ |
3d5f6d12 DJ |
3971 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) |
3972 | last_breakpoint = 0; | |
3973 | ||
3974 | /* Effectively inserts the breakpoints. */ | |
3975 | for (index = 0; index <= last_breakpoint; index++) | |
93f9a11f | 3976 | VEC_safe_push (CORE_ADDR, next_pcs, breaks[index]); |
3d5f6d12 | 3977 | |
93f9a11f | 3978 | return next_pcs; |
3d5f6d12 DJ |
3979 | } |
3980 | ||
93f9a11f | 3981 | static VEC (CORE_ADDR) * |
4cc0665f | 3982 | micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch, |
4cc0665f MR |
3983 | CORE_ADDR pc) |
3984 | { | |
3985 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
3986 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
3987 | CORE_ADDR breaks[2] = {-1, -1}; | |
4b844a38 AT |
3988 | CORE_ADDR branch_bp = 0; /* Breakpoint at branch instruction's |
3989 | destination. */ | |
4cc0665f MR |
3990 | CORE_ADDR loc = pc; |
3991 | int sc_found = 0; | |
3992 | ULONGEST insn; | |
3993 | int insn_count; | |
3994 | int index; | |
93f9a11f | 3995 | VEC (CORE_ADDR) *next_pcs = NULL; |
4cc0665f MR |
3996 | |
3997 | /* Assume all atomic sequences start with a ll/lld instruction. */ | |
3998 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); | |
3999 | if (micromips_op (insn) != 0x18) /* POOL32C: bits 011000 */ | |
93f9a11f | 4000 | return NULL; |
4cc0665f MR |
4001 | loc += MIPS_INSN16_SIZE; |
4002 | insn <<= 16; | |
4003 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); | |
4004 | if ((b12s4_op (insn) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */ | |
93f9a11f | 4005 | return NULL; |
4cc0665f MR |
4006 | loc += MIPS_INSN16_SIZE; |
4007 | ||
4008 | /* Assume all atomic sequences end with an sc/scd instruction. Assume | |
4009 | that no atomic sequence is longer than "atomic_sequence_length" | |
4010 | instructions. */ | |
4011 | for (insn_count = 0; | |
4012 | !sc_found && insn_count < atomic_sequence_length; | |
4013 | ++insn_count) | |
4014 | { | |
4015 | int is_branch = 0; | |
4016 | ||
4017 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); | |
4018 | loc += MIPS_INSN16_SIZE; | |
4019 | ||
4020 | /* Assume that there is at most one conditional branch in the | |
4021 | atomic sequence. If a branch is found, put a breakpoint in | |
4022 | its destination address. */ | |
4023 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
4024 | { | |
4cc0665f MR |
4025 | /* 32-bit instructions. */ |
4026 | case 2 * MIPS_INSN16_SIZE: | |
4027 | switch (micromips_op (insn)) | |
4028 | { | |
4029 | case 0x10: /* POOL32I: bits 010000 */ | |
4030 | if ((b5s5_op (insn) & 0x18) != 0x0 | |
4031 | /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */ | |
4032 | /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */ | |
4033 | && (b5s5_op (insn) & 0x1d) != 0x11 | |
4034 | /* BLTZALS, BGEZALS: bits 010000 100x1 */ | |
4035 | && ((b5s5_op (insn) & 0x1e) != 0x14 | |
4036 | || (insn & 0x3) != 0x0) | |
4037 | /* BC2F, BC2T: bits 010000 1010x xxx00 */ | |
4038 | && (b5s5_op (insn) & 0x1e) != 0x1a | |
4039 | /* BPOSGE64, BPOSGE32: bits 010000 1101x */ | |
4040 | && ((b5s5_op (insn) & 0x1e) != 0x1c | |
4041 | || (insn & 0x3) != 0x0) | |
4042 | /* BC1F, BC1T: bits 010000 1110x xxx00 */ | |
4043 | && ((b5s5_op (insn) & 0x1c) != 0x1c | |
4044 | || (insn & 0x3) != 0x1)) | |
4045 | /* BC1ANY*: bits 010000 111xx xxx01 */ | |
4046 | break; | |
4047 | /* Fall through. */ | |
4048 | ||
4049 | case 0x25: /* BEQ: bits 100101 */ | |
4050 | case 0x2d: /* BNE: bits 101101 */ | |
4051 | insn <<= 16; | |
4052 | insn |= mips_fetch_instruction (gdbarch, | |
4053 | ISA_MICROMIPS, loc, NULL); | |
4054 | branch_bp = (loc + MIPS_INSN16_SIZE | |
4055 | + micromips_relative_offset16 (insn)); | |
4056 | is_branch = 1; | |
4057 | break; | |
4058 | ||
4059 | case 0x00: /* POOL32A: bits 000000 */ | |
4060 | insn <<= 16; | |
4061 | insn |= mips_fetch_instruction (gdbarch, | |
4062 | ISA_MICROMIPS, loc, NULL); | |
4063 | if (b0s6_op (insn) != 0x3c | |
4064 | /* POOL32Axf: bits 000000 ... 111100 */ | |
4065 | || (b6s10_ext (insn) & 0x2bf) != 0x3c) | |
4066 | /* JALR, JALR.HB: 000000 000x111100 111100 */ | |
4067 | /* JALRS, JALRS.HB: 000000 010x111100 111100 */ | |
4068 | break; | |
4069 | /* Fall through. */ | |
4070 | ||
4071 | case 0x1d: /* JALS: bits 011101 */ | |
4072 | case 0x35: /* J: bits 110101 */ | |
4073 | case 0x3d: /* JAL: bits 111101 */ | |
4074 | case 0x3c: /* JALX: bits 111100 */ | |
4075 | return 0; /* Fall back to the standard single-step code. */ | |
4076 | ||
4077 | case 0x18: /* POOL32C: bits 011000 */ | |
4078 | if ((b12s4_op (insn) & 0xb) == 0xb) | |
4079 | /* SC, SCD: bits 011000 1x11 */ | |
4080 | sc_found = 1; | |
4081 | break; | |
4082 | } | |
4083 | loc += MIPS_INSN16_SIZE; | |
4084 | break; | |
4085 | ||
4086 | /* 16-bit instructions. */ | |
4087 | case MIPS_INSN16_SIZE: | |
4088 | switch (micromips_op (insn)) | |
4089 | { | |
4090 | case 0x23: /* BEQZ16: bits 100011 */ | |
4091 | case 0x2b: /* BNEZ16: bits 101011 */ | |
4092 | branch_bp = loc + micromips_relative_offset7 (insn); | |
4093 | is_branch = 1; | |
4094 | break; | |
4095 | ||
4096 | case 0x11: /* POOL16C: bits 010001 */ | |
4097 | if ((b5s5_op (insn) & 0x1c) != 0xc | |
4098 | /* JR16, JRC, JALR16, JALRS16: 010001 011xx */ | |
4099 | && b5s5_op (insn) != 0x18) | |
4100 | /* JRADDIUSP: bits 010001 11000 */ | |
4101 | break; | |
93f9a11f | 4102 | return NULL; /* Fall back to the standard single-step code. */ |
4cc0665f MR |
4103 | |
4104 | case 0x33: /* B16: bits 110011 */ | |
93f9a11f | 4105 | return NULL; /* Fall back to the standard single-step code. */ |
4cc0665f MR |
4106 | } |
4107 | break; | |
4108 | } | |
4109 | if (is_branch) | |
4110 | { | |
4111 | if (last_breakpoint >= 1) | |
93f9a11f | 4112 | return NULL; /* More than one branch found, fallback to the |
4cc0665f MR |
4113 | standard single-step code. */ |
4114 | breaks[1] = branch_bp; | |
4115 | last_breakpoint++; | |
4116 | } | |
4117 | } | |
4118 | if (!sc_found) | |
93f9a11f | 4119 | return NULL; |
4cc0665f MR |
4120 | |
4121 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
4122 | breaks[0] = loc; | |
4123 | ||
4124 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
4125 | placed (branch instruction's destination) in the atomic sequence */ | |
4126 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) | |
4127 | last_breakpoint = 0; | |
4128 | ||
4129 | /* Effectively inserts the breakpoints. */ | |
4130 | for (index = 0; index <= last_breakpoint; index++) | |
93f9a11f | 4131 | VEC_safe_push (CORE_ADDR, next_pcs, breaks[index]); |
4cc0665f | 4132 | |
93f9a11f | 4133 | return next_pcs; |
4cc0665f MR |
4134 | } |
4135 | ||
93f9a11f YQ |
4136 | static VEC (CORE_ADDR) * |
4137 | deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) | |
4cc0665f MR |
4138 | { |
4139 | if (mips_pc_is_mips (pc)) | |
93f9a11f | 4140 | return mips_deal_with_atomic_sequence (gdbarch, pc); |
4cc0665f | 4141 | else if (mips_pc_is_micromips (gdbarch, pc)) |
93f9a11f | 4142 | return micromips_deal_with_atomic_sequence (gdbarch, pc); |
4cc0665f | 4143 | else |
93f9a11f | 4144 | return NULL; |
4cc0665f MR |
4145 | } |
4146 | ||
29639122 JB |
4147 | /* mips_software_single_step() is called just before we want to resume |
4148 | the inferior, if we want to single-step it but there is no hardware | |
4149 | or kernel single-step support (MIPS on GNU/Linux for example). We find | |
e0cd558a | 4150 | the target of the coming instruction and breakpoint it. */ |
29639122 | 4151 | |
93f9a11f | 4152 | VEC (CORE_ADDR) * |
f5ea389a | 4153 | mips_software_single_step (struct regcache *regcache) |
c906108c | 4154 | { |
7113a196 | 4155 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
8181d85f | 4156 | CORE_ADDR pc, next_pc; |
93f9a11f | 4157 | VEC (CORE_ADDR) *next_pcs; |
65596487 | 4158 | |
7113a196 | 4159 | pc = regcache_read_pc (regcache); |
93f9a11f YQ |
4160 | next_pcs = deal_with_atomic_sequence (gdbarch, pc); |
4161 | if (next_pcs != NULL) | |
4162 | return next_pcs; | |
3d5f6d12 | 4163 | |
7113a196 | 4164 | next_pc = mips_next_pc (regcache, pc); |
e6590a1b | 4165 | |
93f9a11f YQ |
4166 | VEC_safe_push (CORE_ADDR, next_pcs, next_pc); |
4167 | return next_pcs; | |
29639122 | 4168 | } |
a65bbe44 | 4169 | |
29639122 | 4170 | /* Test whether the PC points to the return instruction at the |
025bb325 | 4171 | end of a function. */ |
65596487 | 4172 | |
29639122 | 4173 | static int |
e17a4113 | 4174 | mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 | 4175 | { |
6321c22a MR |
4176 | ULONGEST insn; |
4177 | ULONGEST hint; | |
4178 | ||
4179 | /* This used to check for MIPS16, but this piece of code is never | |
4cc0665f MR |
4180 | called for MIPS16 functions. And likewise microMIPS ones. */ |
4181 | gdb_assert (mips_pc_is_mips (pc)); | |
6321c22a | 4182 | |
4cc0665f | 4183 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
6321c22a MR |
4184 | hint = 0x7c0; |
4185 | return (insn & ~hint) == 0x3e00008; /* jr(.hb) $ra */ | |
29639122 | 4186 | } |
c906108c | 4187 | |
c906108c | 4188 | |
29639122 JB |
4189 | /* This fencepost looks highly suspicious to me. Removing it also |
4190 | seems suspicious as it could affect remote debugging across serial | |
4191 | lines. */ | |
c906108c | 4192 | |
29639122 | 4193 | static CORE_ADDR |
74ed0bb4 | 4194 | heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 JB |
4195 | { |
4196 | CORE_ADDR start_pc; | |
4197 | CORE_ADDR fence; | |
4198 | int instlen; | |
4199 | int seen_adjsp = 0; | |
d6b48e9c | 4200 | struct inferior *inf; |
65596487 | 4201 | |
74ed0bb4 | 4202 | pc = gdbarch_addr_bits_remove (gdbarch, pc); |
29639122 JB |
4203 | start_pc = pc; |
4204 | fence = start_pc - heuristic_fence_post; | |
4205 | if (start_pc == 0) | |
4206 | return 0; | |
65596487 | 4207 | |
44096aee | 4208 | if (heuristic_fence_post == -1 || fence < VM_MIN_ADDRESS) |
29639122 | 4209 | fence = VM_MIN_ADDRESS; |
65596487 | 4210 | |
4cc0665f | 4211 | instlen = mips_pc_is_mips (pc) ? MIPS_INSN32_SIZE : MIPS_INSN16_SIZE; |
98b4dd94 | 4212 | |
d6b48e9c PA |
4213 | inf = current_inferior (); |
4214 | ||
025bb325 | 4215 | /* Search back for previous return. */ |
29639122 JB |
4216 | for (start_pc -= instlen;; start_pc -= instlen) |
4217 | if (start_pc < fence) | |
4218 | { | |
4219 | /* It's not clear to me why we reach this point when | |
4220 | stop_soon, but with this test, at least we | |
4221 | don't print out warnings for every child forked (eg, on | |
4222 | decstation). 22apr93 rich@cygnus.com. */ | |
16c381f0 | 4223 | if (inf->control.stop_soon == NO_STOP_QUIETLY) |
29639122 JB |
4224 | { |
4225 | static int blurb_printed = 0; | |
98b4dd94 | 4226 | |
5af949e3 UW |
4227 | warning (_("GDB can't find the start of the function at %s."), |
4228 | paddress (gdbarch, pc)); | |
29639122 JB |
4229 | |
4230 | if (!blurb_printed) | |
4231 | { | |
4232 | /* This actually happens frequently in embedded | |
4233 | development, when you first connect to a board | |
4234 | and your stack pointer and pc are nowhere in | |
4235 | particular. This message needs to give people | |
4236 | in that situation enough information to | |
4237 | determine that it's no big deal. */ | |
4238 | printf_filtered ("\n\ | |
5af949e3 | 4239 | GDB is unable to find the start of the function at %s\n\ |
29639122 JB |
4240 | and thus can't determine the size of that function's stack frame.\n\ |
4241 | This means that GDB may be unable to access that stack frame, or\n\ | |
4242 | the frames below it.\n\ | |
4243 | This problem is most likely caused by an invalid program counter or\n\ | |
4244 | stack pointer.\n\ | |
4245 | However, if you think GDB should simply search farther back\n\ | |
5af949e3 | 4246 | from %s for code which looks like the beginning of a\n\ |
29639122 | 4247 | function, you can increase the range of the search using the `set\n\ |
5af949e3 UW |
4248 | heuristic-fence-post' command.\n", |
4249 | paddress (gdbarch, pc), paddress (gdbarch, pc)); | |
29639122 JB |
4250 | blurb_printed = 1; |
4251 | } | |
4252 | } | |
4253 | ||
4254 | return 0; | |
4255 | } | |
4cc0665f | 4256 | else if (mips_pc_is_mips16 (gdbarch, start_pc)) |
29639122 JB |
4257 | { |
4258 | unsigned short inst; | |
4259 | ||
4260 | /* On MIPS16, any one of the following is likely to be the | |
4261 | start of a function: | |
193774b3 MR |
4262 | extend save |
4263 | save | |
29639122 JB |
4264 | entry |
4265 | addiu sp,-n | |
4266 | daddiu sp,-n | |
025bb325 | 4267 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */ |
4cc0665f | 4268 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, start_pc, NULL); |
193774b3 MR |
4269 | if ((inst & 0xff80) == 0x6480) /* save */ |
4270 | { | |
4271 | if (start_pc - instlen >= fence) | |
4272 | { | |
4cc0665f MR |
4273 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, |
4274 | start_pc - instlen, NULL); | |
193774b3 MR |
4275 | if ((inst & 0xf800) == 0xf000) /* extend */ |
4276 | start_pc -= instlen; | |
4277 | } | |
4278 | break; | |
4279 | } | |
4280 | else if (((inst & 0xf81f) == 0xe809 | |
4281 | && (inst & 0x700) != 0x700) /* entry */ | |
4282 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
4283 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
4284 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
29639122 JB |
4285 | break; |
4286 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
4287 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
4288 | seen_adjsp = 1; | |
4289 | else | |
4290 | seen_adjsp = 0; | |
4291 | } | |
4cc0665f MR |
4292 | else if (mips_pc_is_micromips (gdbarch, start_pc)) |
4293 | { | |
4294 | ULONGEST insn; | |
4295 | int stop = 0; | |
4296 | long offset; | |
4297 | int dreg; | |
4298 | int sreg; | |
4299 | ||
4300 | /* On microMIPS, any one of the following is likely to be the | |
4301 | start of a function: | |
4302 | ADDIUSP -imm | |
4303 | (D)ADDIU $sp, -imm | |
4304 | LUI $gp, imm */ | |
4305 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
4306 | switch (micromips_op (insn)) | |
4307 | { | |
4308 | case 0xc: /* ADDIU: bits 001100 */ | |
4309 | case 0x17: /* DADDIU: bits 010111 */ | |
4310 | sreg = b0s5_reg (insn); | |
4311 | dreg = b5s5_reg (insn); | |
4312 | insn <<= 16; | |
4313 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, | |
4314 | pc + MIPS_INSN16_SIZE, NULL); | |
4315 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
4316 | if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM | |
4317 | /* (D)ADDIU $sp, imm */ | |
4318 | && offset < 0) | |
4319 | stop = 1; | |
4320 | break; | |
4321 | ||
4322 | case 0x10: /* POOL32I: bits 010000 */ | |
4323 | if (b5s5_op (insn) == 0xd | |
4324 | /* LUI: bits 010000 001101 */ | |
4325 | && b0s5_reg (insn >> 16) == 28) | |
4326 | /* LUI $gp, imm */ | |
4327 | stop = 1; | |
4328 | break; | |
4329 | ||
4330 | case 0x13: /* POOL16D: bits 010011 */ | |
4331 | if ((insn & 0x1) == 0x1) | |
4332 | /* ADDIUSP: bits 010011 1 */ | |
4333 | { | |
4334 | offset = micromips_decode_imm9 (b1s9_imm (insn)); | |
4335 | if (offset < 0) | |
4336 | /* ADDIUSP -imm */ | |
4337 | stop = 1; | |
4338 | } | |
4339 | else | |
4340 | /* ADDIUS5: bits 010011 0 */ | |
4341 | { | |
4342 | dreg = b5s5_reg (insn); | |
4343 | offset = (b1s4_imm (insn) ^ 8) - 8; | |
4344 | if (dreg == MIPS_SP_REGNUM && offset < 0) | |
4345 | /* ADDIUS5 $sp, -imm */ | |
4346 | stop = 1; | |
4347 | } | |
4348 | break; | |
4349 | } | |
4350 | if (stop) | |
4351 | break; | |
4352 | } | |
e17a4113 | 4353 | else if (mips_about_to_return (gdbarch, start_pc)) |
29639122 | 4354 | { |
4c7d22cb | 4355 | /* Skip return and its delay slot. */ |
95ac2dcf | 4356 | start_pc += 2 * MIPS_INSN32_SIZE; |
29639122 JB |
4357 | break; |
4358 | } | |
4359 | ||
4360 | return start_pc; | |
c906108c SS |
4361 | } |
4362 | ||
6c0d6680 DJ |
4363 | struct mips_objfile_private |
4364 | { | |
4365 | bfd_size_type size; | |
4366 | char *contents; | |
4367 | }; | |
4368 | ||
f09ded24 AC |
4369 | /* According to the current ABI, should the type be passed in a |
4370 | floating-point register (assuming that there is space)? When there | |
a1f5b845 | 4371 | is no FPU, FP are not even considered as possible candidates for |
f09ded24 | 4372 | FP registers and, consequently this returns false - forces FP |
025bb325 | 4373 | arguments into integer registers. */ |
f09ded24 AC |
4374 | |
4375 | static int | |
74ed0bb4 MD |
4376 | fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode, |
4377 | struct type *arg_type) | |
f09ded24 AC |
4378 | { |
4379 | return ((typecode == TYPE_CODE_FLT | |
74ed0bb4 | 4380 | || (MIPS_EABI (gdbarch) |
6d82d43b AC |
4381 | && (typecode == TYPE_CODE_STRUCT |
4382 | || typecode == TYPE_CODE_UNION) | |
f09ded24 | 4383 | && TYPE_NFIELDS (arg_type) == 1 |
b2d6f210 MS |
4384 | && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0))) |
4385 | == TYPE_CODE_FLT)) | |
74ed0bb4 | 4386 | && MIPS_FPU_TYPE(gdbarch) != MIPS_FPU_NONE); |
f09ded24 AC |
4387 | } |
4388 | ||
49e790b0 | 4389 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
025bb325 | 4390 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ |
49e790b0 DJ |
4391 | |
4392 | static int | |
4393 | mips_type_needs_double_align (struct type *type) | |
4394 | { | |
4395 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 4396 | |
49e790b0 DJ |
4397 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
4398 | return 1; | |
4399 | else if (typecode == TYPE_CODE_STRUCT) | |
4400 | { | |
4401 | if (TYPE_NFIELDS (type) < 1) | |
4402 | return 0; | |
4403 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
4404 | } | |
4405 | else if (typecode == TYPE_CODE_UNION) | |
4406 | { | |
361d1df0 | 4407 | int i, n; |
49e790b0 DJ |
4408 | |
4409 | n = TYPE_NFIELDS (type); | |
4410 | for (i = 0; i < n; i++) | |
4411 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
4412 | return 1; | |
4413 | return 0; | |
4414 | } | |
4415 | return 0; | |
4416 | } | |
4417 | ||
dc604539 AC |
4418 | /* Adjust the address downward (direction of stack growth) so that it |
4419 | is correctly aligned for a new stack frame. */ | |
4420 | static CORE_ADDR | |
4421 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
4422 | { | |
5b03f266 | 4423 | return align_down (addr, 16); |
dc604539 AC |
4424 | } |
4425 | ||
8ae38c14 | 4426 | /* Implement the "push_dummy_code" gdbarch method. */ |
2c76a0c7 JB |
4427 | |
4428 | static CORE_ADDR | |
4429 | mips_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
4430 | CORE_ADDR funaddr, struct value **args, | |
4431 | int nargs, struct type *value_type, | |
4432 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, | |
4433 | struct regcache *regcache) | |
4434 | { | |
2c76a0c7 | 4435 | static gdb_byte nop_insn[] = { 0, 0, 0, 0 }; |
2e81047f MR |
4436 | CORE_ADDR nop_addr; |
4437 | CORE_ADDR bp_slot; | |
2c76a0c7 JB |
4438 | |
4439 | /* Reserve enough room on the stack for our breakpoint instruction. */ | |
2e81047f MR |
4440 | bp_slot = sp - sizeof (nop_insn); |
4441 | ||
4442 | /* Return to microMIPS mode if calling microMIPS code to avoid | |
4443 | triggering an address error exception on processors that only | |
4444 | support microMIPS execution. */ | |
4445 | *bp_addr = (mips_pc_is_micromips (gdbarch, funaddr) | |
4446 | ? make_compact_addr (bp_slot) : bp_slot); | |
2c76a0c7 JB |
4447 | |
4448 | /* The breakpoint layer automatically adjusts the address of | |
4449 | breakpoints inserted in a branch delay slot. With enough | |
4450 | bad luck, the 4 bytes located just before our breakpoint | |
4451 | instruction could look like a branch instruction, and thus | |
4452 | trigger the adjustement, and break the function call entirely. | |
4453 | So, we reserve those 4 bytes and write a nop instruction | |
4454 | to prevent that from happening. */ | |
2e81047f | 4455 | nop_addr = bp_slot - sizeof (nop_insn); |
2c76a0c7 JB |
4456 | write_memory (nop_addr, nop_insn, sizeof (nop_insn)); |
4457 | sp = mips_frame_align (gdbarch, nop_addr); | |
4458 | ||
4459 | /* Inferior resumes at the function entry point. */ | |
4460 | *real_pc = funaddr; | |
4461 | ||
4462 | return sp; | |
4463 | } | |
4464 | ||
f7ab6ec6 | 4465 | static CORE_ADDR |
7d9b040b | 4466 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4467 | struct regcache *regcache, CORE_ADDR bp_addr, |
4468 | int nargs, struct value **args, CORE_ADDR sp, | |
4469 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
4470 | { |
4471 | int argreg; | |
4472 | int float_argreg; | |
4473 | int argnum; | |
4474 | int len = 0; | |
4475 | int stack_offset = 0; | |
e17a4113 | 4476 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 4477 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
1a69e1e4 | 4478 | int regsize = mips_abi_regsize (gdbarch); |
c906108c | 4479 | |
25ab4790 AC |
4480 | /* For shared libraries, "t9" needs to point at the function |
4481 | address. */ | |
4c7d22cb | 4482 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
4483 | |
4484 | /* Set the return address register to point to the entry point of | |
4485 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 4486 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 4487 | |
c906108c | 4488 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
4489 | are properly aligned. The stack has to be at least 64-bit |
4490 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4491 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4492 | aligned, so we round to this widest known alignment. */ | |
4493 | ||
5b03f266 AC |
4494 | sp = align_down (sp, 16); |
4495 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 4496 | |
46e0f506 | 4497 | /* Now make space on the stack for the args. We allocate more |
c906108c | 4498 | than necessary for EABI, because the first few arguments are |
46e0f506 | 4499 | passed in registers, but that's OK. */ |
c906108c | 4500 | for (argnum = 0; argnum < nargs; argnum++) |
1a69e1e4 | 4501 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize); |
5b03f266 | 4502 | sp -= align_up (len, 16); |
c906108c | 4503 | |
9ace0497 | 4504 | if (mips_debug) |
6d82d43b | 4505 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
4506 | "mips_eabi_push_dummy_call: sp=%s allocated %ld\n", |
4507 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
9ace0497 | 4508 | |
c906108c | 4509 | /* Initialize the integer and float register pointers. */ |
4c7d22cb | 4510 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 4511 | float_argreg = mips_fpa0_regnum (gdbarch); |
c906108c | 4512 | |
46e0f506 | 4513 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 4514 | if (struct_return) |
9ace0497 AC |
4515 | { |
4516 | if (mips_debug) | |
4517 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
4518 | "mips_eabi_push_dummy_call: " |
4519 | "struct_return reg=%d %s\n", | |
5af949e3 | 4520 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 4521 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
9ace0497 | 4522 | } |
c906108c SS |
4523 | |
4524 | /* Now load as many as possible of the first arguments into | |
4525 | registers, and push the rest onto the stack. Loop thru args | |
4526 | from first to last. */ | |
4527 | for (argnum = 0; argnum < nargs; argnum++) | |
4528 | { | |
47a35522 MK |
4529 | const gdb_byte *val; |
4530 | gdb_byte valbuf[MAX_REGISTER_SIZE]; | |
ea7c478f | 4531 | struct value *arg = args[argnum]; |
4991999e | 4532 | struct type *arg_type = check_typedef (value_type (arg)); |
c906108c SS |
4533 | int len = TYPE_LENGTH (arg_type); |
4534 | enum type_code typecode = TYPE_CODE (arg_type); | |
4535 | ||
9ace0497 AC |
4536 | if (mips_debug) |
4537 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4538 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 4539 | argnum + 1, len, (int) typecode); |
9ace0497 | 4540 | |
c906108c | 4541 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 4542 | reference. */ |
3e29f34a | 4543 | if (len > regsize |
9ace0497 | 4544 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 4545 | { |
e17a4113 UW |
4546 | store_unsigned_integer (valbuf, regsize, byte_order, |
4547 | value_address (arg)); | |
c906108c | 4548 | typecode = TYPE_CODE_PTR; |
1a69e1e4 | 4549 | len = regsize; |
c906108c | 4550 | val = valbuf; |
9ace0497 AC |
4551 | if (mips_debug) |
4552 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
4553 | } |
4554 | else | |
47a35522 | 4555 | val = value_contents (arg); |
c906108c SS |
4556 | |
4557 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
4558 | even-numbered floating point register. Round the FP register |
4559 | up before the check to see if there are any FP registers | |
46e0f506 MS |
4560 | left. Non MIPS_EABI targets also pass the FP in the integer |
4561 | registers so also round up normal registers. */ | |
74ed0bb4 | 4562 | if (regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type)) |
acdb74a0 AC |
4563 | { |
4564 | if ((float_argreg & 1)) | |
4565 | float_argreg++; | |
4566 | } | |
c906108c SS |
4567 | |
4568 | /* Floating point arguments passed in registers have to be | |
4569 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
4570 | are passed in register pairs; the even register gets |
4571 | the low word, and the odd register gets the high word. | |
4572 | On non-EABI processors, the first two floating point arguments are | |
4573 | also copied to general registers, because MIPS16 functions | |
4574 | don't use float registers for arguments. This duplication of | |
4575 | arguments in general registers can't hurt non-MIPS16 functions | |
4576 | because those registers are normally skipped. */ | |
1012bd0e EZ |
4577 | /* MIPS_EABI squeezes a struct that contains a single floating |
4578 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 4579 | stack. */ |
74ed0bb4 MD |
4580 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
4581 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
c906108c | 4582 | { |
6da397e0 KB |
4583 | /* EABI32 will pass doubles in consecutive registers, even on |
4584 | 64-bit cores. At one time, we used to check the size of | |
4585 | `float_argreg' to determine whether or not to pass doubles | |
4586 | in consecutive registers, but this is not sufficient for | |
4587 | making the ABI determination. */ | |
4588 | if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) | |
c906108c | 4589 | { |
72a155b4 | 4590 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 4591 | == BFD_ENDIAN_BIG ? 4 : 0; |
a8852dc5 | 4592 | long regval; |
c906108c SS |
4593 | |
4594 | /* Write the low word of the double to the even register(s). */ | |
a8852dc5 KB |
4595 | regval = extract_signed_integer (val + low_offset, |
4596 | 4, byte_order); | |
9ace0497 | 4597 | if (mips_debug) |
acdb74a0 | 4598 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 4599 | float_argreg, phex (regval, 4)); |
a8852dc5 | 4600 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
4601 | |
4602 | /* Write the high word of the double to the odd register(s). */ | |
a8852dc5 KB |
4603 | regval = extract_signed_integer (val + 4 - low_offset, |
4604 | 4, byte_order); | |
9ace0497 | 4605 | if (mips_debug) |
acdb74a0 | 4606 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 4607 | float_argreg, phex (regval, 4)); |
a8852dc5 | 4608 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
4609 | } |
4610 | else | |
4611 | { | |
4612 | /* This is a floating point value that fits entirely | |
4613 | in a single register. */ | |
53a5351d | 4614 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 4615 | above to ensure that it is even register aligned. */ |
a8852dc5 | 4616 | LONGEST regval = extract_signed_integer (val, len, byte_order); |
9ace0497 | 4617 | if (mips_debug) |
acdb74a0 | 4618 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 4619 | float_argreg, phex (regval, len)); |
a8852dc5 | 4620 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
4621 | } |
4622 | } | |
4623 | else | |
4624 | { | |
4625 | /* Copy the argument to general registers or the stack in | |
4626 | register-sized pieces. Large arguments are split between | |
4627 | registers and stack. */ | |
1a69e1e4 DJ |
4628 | /* Note: structs whose size is not a multiple of regsize |
4629 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
4630 | them in registers where gcc sometimes puts them on the |
4631 | stack. For maximum compatibility, we will put them in | |
4632 | both places. */ | |
1a69e1e4 | 4633 | int odd_sized_struct = (len > regsize && len % regsize != 0); |
46e0f506 | 4634 | |
f09ded24 | 4635 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 4636 | register are only written to memory. */ |
c906108c SS |
4637 | while (len > 0) |
4638 | { | |
ebafbe83 | 4639 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 4640 | int stack_used_p = 0; |
1a69e1e4 | 4641 | int partial_len = (len < regsize ? len : regsize); |
c906108c | 4642 | |
acdb74a0 AC |
4643 | if (mips_debug) |
4644 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4645 | partial_len); | |
4646 | ||
566f0f7a | 4647 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 4648 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
f09ded24 | 4649 | || odd_sized_struct |
74ed0bb4 | 4650 | || fp_register_arg_p (gdbarch, typecode, arg_type)) |
c906108c | 4651 | { |
c906108c | 4652 | /* Should shorter than int integer values be |
025bb325 | 4653 | promoted to int before being stored? */ |
c906108c | 4654 | int longword_offset = 0; |
9ace0497 | 4655 | CORE_ADDR addr; |
566f0f7a | 4656 | stack_used_p = 1; |
72a155b4 | 4657 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
7a292a7a | 4658 | { |
1a69e1e4 | 4659 | if (regsize == 8 |
480d3dd2 AC |
4660 | && (typecode == TYPE_CODE_INT |
4661 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 4662 | || typecode == TYPE_CODE_FLT) && len <= 4) |
1a69e1e4 | 4663 | longword_offset = regsize - len; |
480d3dd2 AC |
4664 | else if ((typecode == TYPE_CODE_STRUCT |
4665 | || typecode == TYPE_CODE_UNION) | |
1a69e1e4 DJ |
4666 | && TYPE_LENGTH (arg_type) < regsize) |
4667 | longword_offset = regsize - len; | |
7a292a7a | 4668 | } |
c5aa993b | 4669 | |
9ace0497 AC |
4670 | if (mips_debug) |
4671 | { | |
5af949e3 UW |
4672 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
4673 | paddress (gdbarch, stack_offset)); | |
4674 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
4675 | paddress (gdbarch, longword_offset)); | |
9ace0497 | 4676 | } |
361d1df0 | 4677 | |
9ace0497 AC |
4678 | addr = sp + stack_offset + longword_offset; |
4679 | ||
4680 | if (mips_debug) | |
4681 | { | |
4682 | int i; | |
5af949e3 UW |
4683 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
4684 | paddress (gdbarch, addr)); | |
9ace0497 AC |
4685 | for (i = 0; i < partial_len; i++) |
4686 | { | |
6d82d43b | 4687 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 4688 | val[i] & 0xff); |
9ace0497 AC |
4689 | } |
4690 | } | |
4691 | write_memory (addr, val, partial_len); | |
c906108c SS |
4692 | } |
4693 | ||
f09ded24 AC |
4694 | /* Note!!! This is NOT an else clause. Odd sized |
4695 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 4696 | arguments will not. */ |
566f0f7a | 4697 | /* Write this portion of the argument to a general |
6d82d43b | 4698 | purpose register. */ |
74ed0bb4 MD |
4699 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch) |
4700 | && !fp_register_arg_p (gdbarch, typecode, arg_type)) | |
c906108c | 4701 | { |
6d82d43b | 4702 | LONGEST regval = |
a8852dc5 | 4703 | extract_signed_integer (val, partial_len, byte_order); |
c906108c | 4704 | |
9ace0497 | 4705 | if (mips_debug) |
acdb74a0 | 4706 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 4707 | argreg, |
1a69e1e4 | 4708 | phex (regval, regsize)); |
a8852dc5 | 4709 | regcache_cooked_write_signed (regcache, argreg, regval); |
c906108c | 4710 | argreg++; |
c906108c | 4711 | } |
c5aa993b | 4712 | |
c906108c SS |
4713 | len -= partial_len; |
4714 | val += partial_len; | |
4715 | ||
b021a221 MS |
4716 | /* Compute the offset into the stack at which we will |
4717 | copy the next parameter. | |
566f0f7a | 4718 | |
566f0f7a | 4719 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 4720 | only needs to be adjusted when it has been used. */ |
c906108c | 4721 | |
46e0f506 | 4722 | if (stack_used_p) |
1a69e1e4 | 4723 | stack_offset += align_up (partial_len, regsize); |
c906108c SS |
4724 | } |
4725 | } | |
9ace0497 AC |
4726 | if (mips_debug) |
4727 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
4728 | } |
4729 | ||
f10683bb | 4730 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4731 | |
0f71a2f6 JM |
4732 | /* Return adjusted stack pointer. */ |
4733 | return sp; | |
4734 | } | |
4735 | ||
a1f5b845 | 4736 | /* Determine the return value convention being used. */ |
6d82d43b | 4737 | |
9c8fdbfa | 4738 | static enum return_value_convention |
6a3a010b | 4739 | mips_eabi_return_value (struct gdbarch *gdbarch, struct value *function, |
9c8fdbfa | 4740 | struct type *type, struct regcache *regcache, |
47a35522 | 4741 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 4742 | { |
609ba780 JM |
4743 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4744 | int fp_return_type = 0; | |
4745 | int offset, regnum, xfer; | |
4746 | ||
9c8fdbfa AC |
4747 | if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
4748 | return RETURN_VALUE_STRUCT_CONVENTION; | |
609ba780 JM |
4749 | |
4750 | /* Floating point type? */ | |
4751 | if (tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4752 | { | |
4753 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
4754 | fp_return_type = 1; | |
4755 | /* Structs with a single field of float type | |
4756 | are returned in a floating point register. */ | |
4757 | if ((TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4758 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4759 | && TYPE_NFIELDS (type) == 1) | |
4760 | { | |
4761 | struct type *fieldtype = TYPE_FIELD_TYPE (type, 0); | |
4762 | ||
4763 | if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT) | |
4764 | fp_return_type = 1; | |
4765 | } | |
4766 | } | |
4767 | ||
4768 | if (fp_return_type) | |
4769 | { | |
4770 | /* A floating-point value belongs in the least significant part | |
4771 | of FP0/FP1. */ | |
4772 | if (mips_debug) | |
4773 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
4774 | regnum = mips_regnum (gdbarch)->fp0; | |
4775 | } | |
4776 | else | |
4777 | { | |
4778 | /* An integer value goes in V0/V1. */ | |
4779 | if (mips_debug) | |
4780 | fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n"); | |
4781 | regnum = MIPS_V0_REGNUM; | |
4782 | } | |
4783 | for (offset = 0; | |
4784 | offset < TYPE_LENGTH (type); | |
4785 | offset += mips_abi_regsize (gdbarch), regnum++) | |
4786 | { | |
4787 | xfer = mips_abi_regsize (gdbarch); | |
4788 | if (offset + xfer > TYPE_LENGTH (type)) | |
4789 | xfer = TYPE_LENGTH (type) - offset; | |
4790 | mips_xfer_register (gdbarch, regcache, | |
4791 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
4792 | gdbarch_byte_order (gdbarch), readbuf, writebuf, | |
4793 | offset); | |
4794 | } | |
4795 | ||
9c8fdbfa | 4796 | return RETURN_VALUE_REGISTER_CONVENTION; |
6d82d43b AC |
4797 | } |
4798 | ||
6d82d43b AC |
4799 | |
4800 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 4801 | |
8d26208a DJ |
4802 | /* Search for a naturally aligned double at OFFSET inside a struct |
4803 | ARG_TYPE. The N32 / N64 ABIs pass these in floating point | |
4804 | registers. */ | |
4805 | ||
4806 | static int | |
74ed0bb4 MD |
4807 | mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type, |
4808 | int offset) | |
8d26208a DJ |
4809 | { |
4810 | int i; | |
4811 | ||
4812 | if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT) | |
4813 | return 0; | |
4814 | ||
74ed0bb4 | 4815 | if (MIPS_FPU_TYPE (gdbarch) != MIPS_FPU_DOUBLE) |
8d26208a DJ |
4816 | return 0; |
4817 | ||
4818 | if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE) | |
4819 | return 0; | |
4820 | ||
4821 | for (i = 0; i < TYPE_NFIELDS (arg_type); i++) | |
4822 | { | |
4823 | int pos; | |
4824 | struct type *field_type; | |
4825 | ||
4826 | /* We're only looking at normal fields. */ | |
5bc60cfb | 4827 | if (field_is_static (&TYPE_FIELD (arg_type, i)) |
8d26208a DJ |
4828 | || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0) |
4829 | continue; | |
4830 | ||
4831 | /* If we have gone past the offset, there is no double to pass. */ | |
4832 | pos = TYPE_FIELD_BITPOS (arg_type, i) / 8; | |
4833 | if (pos > offset) | |
4834 | return 0; | |
4835 | ||
4836 | field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i)); | |
4837 | ||
4838 | /* If this field is entirely before the requested offset, go | |
4839 | on to the next one. */ | |
4840 | if (pos + TYPE_LENGTH (field_type) <= offset) | |
4841 | continue; | |
4842 | ||
4843 | /* If this is our special aligned double, we can stop. */ | |
4844 | if (TYPE_CODE (field_type) == TYPE_CODE_FLT | |
4845 | && TYPE_LENGTH (field_type) == MIPS64_REGSIZE) | |
4846 | return 1; | |
4847 | ||
4848 | /* This field starts at or before the requested offset, and | |
4849 | overlaps it. If it is a structure, recurse inwards. */ | |
74ed0bb4 | 4850 | return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos); |
8d26208a DJ |
4851 | } |
4852 | ||
4853 | return 0; | |
4854 | } | |
4855 | ||
f7ab6ec6 | 4856 | static CORE_ADDR |
7d9b040b | 4857 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4858 | struct regcache *regcache, CORE_ADDR bp_addr, |
4859 | int nargs, struct value **args, CORE_ADDR sp, | |
4860 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
4861 | { |
4862 | int argreg; | |
4863 | int float_argreg; | |
4864 | int argnum; | |
4865 | int len = 0; | |
4866 | int stack_offset = 0; | |
e17a4113 | 4867 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 4868 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 4869 | |
25ab4790 AC |
4870 | /* For shared libraries, "t9" needs to point at the function |
4871 | address. */ | |
4c7d22cb | 4872 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
4873 | |
4874 | /* Set the return address register to point to the entry point of | |
4875 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 4876 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 4877 | |
cb3d25d1 MS |
4878 | /* First ensure that the stack and structure return address (if any) |
4879 | are properly aligned. The stack has to be at least 64-bit | |
4880 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4881 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4882 | aligned, so we round to this widest known alignment. */ | |
4883 | ||
5b03f266 AC |
4884 | sp = align_down (sp, 16); |
4885 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
4886 | |
4887 | /* Now make space on the stack for the args. */ | |
4888 | for (argnum = 0; argnum < nargs; argnum++) | |
1a69e1e4 | 4889 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE); |
5b03f266 | 4890 | sp -= align_up (len, 16); |
cb3d25d1 MS |
4891 | |
4892 | if (mips_debug) | |
6d82d43b | 4893 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
4894 | "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n", |
4895 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
4896 | |
4897 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 4898 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 4899 | float_argreg = mips_fpa0_regnum (gdbarch); |
cb3d25d1 | 4900 | |
46e0f506 | 4901 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
4902 | if (struct_return) |
4903 | { | |
4904 | if (mips_debug) | |
4905 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
4906 | "mips_n32n64_push_dummy_call: " |
4907 | "struct_return reg=%d %s\n", | |
5af949e3 | 4908 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 4909 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
cb3d25d1 MS |
4910 | } |
4911 | ||
4912 | /* Now load as many as possible of the first arguments into | |
4913 | registers, and push the rest onto the stack. Loop thru args | |
4914 | from first to last. */ | |
4915 | for (argnum = 0; argnum < nargs; argnum++) | |
4916 | { | |
47a35522 | 4917 | const gdb_byte *val; |
cb3d25d1 | 4918 | struct value *arg = args[argnum]; |
4991999e | 4919 | struct type *arg_type = check_typedef (value_type (arg)); |
cb3d25d1 MS |
4920 | int len = TYPE_LENGTH (arg_type); |
4921 | enum type_code typecode = TYPE_CODE (arg_type); | |
4922 | ||
4923 | if (mips_debug) | |
4924 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4925 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
4926 | argnum + 1, len, (int) typecode); |
4927 | ||
47a35522 | 4928 | val = value_contents (arg); |
cb3d25d1 | 4929 | |
5b68030f JM |
4930 | /* A 128-bit long double value requires an even-odd pair of |
4931 | floating-point registers. */ | |
4932 | if (len == 16 | |
4933 | && fp_register_arg_p (gdbarch, typecode, arg_type) | |
4934 | && (float_argreg & 1)) | |
4935 | { | |
4936 | float_argreg++; | |
4937 | argreg++; | |
4938 | } | |
4939 | ||
74ed0bb4 MD |
4940 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
4941 | && argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) | |
cb3d25d1 MS |
4942 | { |
4943 | /* This is a floating point value that fits entirely | |
5b68030f JM |
4944 | in a single register or a pair of registers. */ |
4945 | int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE); | |
e17a4113 | 4946 | LONGEST regval = extract_unsigned_integer (val, reglen, byte_order); |
cb3d25d1 MS |
4947 | if (mips_debug) |
4948 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5b68030f | 4949 | float_argreg, phex (regval, reglen)); |
8d26208a | 4950 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); |
cb3d25d1 MS |
4951 | |
4952 | if (mips_debug) | |
4953 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5b68030f | 4954 | argreg, phex (regval, reglen)); |
9c9acae0 | 4955 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a DJ |
4956 | float_argreg++; |
4957 | argreg++; | |
5b68030f JM |
4958 | if (len == 16) |
4959 | { | |
e17a4113 UW |
4960 | regval = extract_unsigned_integer (val + reglen, |
4961 | reglen, byte_order); | |
5b68030f JM |
4962 | if (mips_debug) |
4963 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4964 | float_argreg, phex (regval, reglen)); | |
4965 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); | |
4966 | ||
4967 | if (mips_debug) | |
4968 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4969 | argreg, phex (regval, reglen)); | |
4970 | regcache_cooked_write_unsigned (regcache, argreg, regval); | |
4971 | float_argreg++; | |
4972 | argreg++; | |
4973 | } | |
cb3d25d1 MS |
4974 | } |
4975 | else | |
4976 | { | |
4977 | /* Copy the argument to general registers or the stack in | |
4978 | register-sized pieces. Large arguments are split between | |
4979 | registers and stack. */ | |
ab2e1992 MR |
4980 | /* For N32/N64, structs, unions, or other composite types are |
4981 | treated as a sequence of doublewords, and are passed in integer | |
4982 | or floating point registers as though they were simple scalar | |
4983 | parameters to the extent that they fit, with any excess on the | |
4984 | stack packed according to the normal memory layout of the | |
4985 | object. | |
4986 | The caller does not reserve space for the register arguments; | |
4987 | the callee is responsible for reserving it if required. */ | |
cb3d25d1 | 4988 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 4989 | register are only written to memory. */ |
cb3d25d1 MS |
4990 | while (len > 0) |
4991 | { | |
ad018eee | 4992 | /* Remember if the argument was written to the stack. */ |
cb3d25d1 | 4993 | int stack_used_p = 0; |
1a69e1e4 | 4994 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
cb3d25d1 MS |
4995 | |
4996 | if (mips_debug) | |
4997 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4998 | partial_len); | |
4999 | ||
74ed0bb4 MD |
5000 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
5001 | gdb_assert (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)); | |
8d26208a | 5002 | |
cb3d25d1 | 5003 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 5004 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 MS |
5005 | { |
5006 | /* Should shorter than int integer values be | |
025bb325 | 5007 | promoted to int before being stored? */ |
cb3d25d1 MS |
5008 | int longword_offset = 0; |
5009 | CORE_ADDR addr; | |
5010 | stack_used_p = 1; | |
72a155b4 | 5011 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
cb3d25d1 | 5012 | { |
1a69e1e4 | 5013 | if ((typecode == TYPE_CODE_INT |
5b68030f | 5014 | || typecode == TYPE_CODE_PTR) |
1a69e1e4 DJ |
5015 | && len <= 4) |
5016 | longword_offset = MIPS64_REGSIZE - len; | |
cb3d25d1 MS |
5017 | } |
5018 | ||
5019 | if (mips_debug) | |
5020 | { | |
5af949e3 UW |
5021 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
5022 | paddress (gdbarch, stack_offset)); | |
5023 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
5024 | paddress (gdbarch, longword_offset)); | |
cb3d25d1 MS |
5025 | } |
5026 | ||
5027 | addr = sp + stack_offset + longword_offset; | |
5028 | ||
5029 | if (mips_debug) | |
5030 | { | |
5031 | int i; | |
5af949e3 UW |
5032 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
5033 | paddress (gdbarch, addr)); | |
cb3d25d1 MS |
5034 | for (i = 0; i < partial_len; i++) |
5035 | { | |
6d82d43b | 5036 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
5037 | val[i] & 0xff); |
5038 | } | |
5039 | } | |
5040 | write_memory (addr, val, partial_len); | |
5041 | } | |
5042 | ||
5043 | /* Note!!! This is NOT an else clause. Odd sized | |
8d26208a | 5044 | structs may go thru BOTH paths. */ |
cb3d25d1 | 5045 | /* Write this portion of the argument to a general |
6d82d43b | 5046 | purpose register. */ |
74ed0bb4 | 5047 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 | 5048 | { |
5863b5d5 MR |
5049 | LONGEST regval; |
5050 | ||
5051 | /* Sign extend pointers, 32-bit integers and signed | |
5052 | 16-bit and 8-bit integers; everything else is taken | |
5053 | as is. */ | |
5054 | ||
5055 | if ((partial_len == 4 | |
5056 | && (typecode == TYPE_CODE_PTR | |
5057 | || typecode == TYPE_CODE_INT)) | |
5058 | || (partial_len < 4 | |
5059 | && typecode == TYPE_CODE_INT | |
5060 | && !TYPE_UNSIGNED (arg_type))) | |
e17a4113 UW |
5061 | regval = extract_signed_integer (val, partial_len, |
5062 | byte_order); | |
5863b5d5 | 5063 | else |
e17a4113 UW |
5064 | regval = extract_unsigned_integer (val, partial_len, |
5065 | byte_order); | |
cb3d25d1 MS |
5066 | |
5067 | /* A non-floating-point argument being passed in a | |
5068 | general register. If a struct or union, and if | |
5069 | the remaining length is smaller than the register | |
5070 | size, we have to adjust the register value on | |
5071 | big endian targets. | |
5072 | ||
5073 | It does not seem to be necessary to do the | |
1a69e1e4 | 5074 | same for integral types. */ |
cb3d25d1 | 5075 | |
72a155b4 | 5076 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 5077 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
5078 | && (typecode == TYPE_CODE_STRUCT |
5079 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 5080 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 5081 | * TARGET_CHAR_BIT); |
cb3d25d1 MS |
5082 | |
5083 | if (mips_debug) | |
5084 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
5085 | argreg, | |
1a69e1e4 | 5086 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 5087 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a | 5088 | |
74ed0bb4 | 5089 | if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type, |
8d26208a DJ |
5090 | TYPE_LENGTH (arg_type) - len)) |
5091 | { | |
5092 | if (mips_debug) | |
5093 | fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s", | |
5094 | float_argreg, | |
5095 | phex (regval, MIPS64_REGSIZE)); | |
5096 | regcache_cooked_write_unsigned (regcache, float_argreg, | |
5097 | regval); | |
5098 | } | |
5099 | ||
5100 | float_argreg++; | |
cb3d25d1 MS |
5101 | argreg++; |
5102 | } | |
5103 | ||
5104 | len -= partial_len; | |
5105 | val += partial_len; | |
5106 | ||
b021a221 MS |
5107 | /* Compute the offset into the stack at which we will |
5108 | copy the next parameter. | |
cb3d25d1 MS |
5109 | |
5110 | In N32 (N64?), the stack_offset only needs to be | |
5111 | adjusted when it has been used. */ | |
5112 | ||
5113 | if (stack_used_p) | |
1a69e1e4 | 5114 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
cb3d25d1 MS |
5115 | } |
5116 | } | |
5117 | if (mips_debug) | |
5118 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
5119 | } | |
5120 | ||
f10683bb | 5121 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 5122 | |
cb3d25d1 MS |
5123 | /* Return adjusted stack pointer. */ |
5124 | return sp; | |
5125 | } | |
5126 | ||
6d82d43b | 5127 | static enum return_value_convention |
6a3a010b | 5128 | mips_n32n64_return_value (struct gdbarch *gdbarch, struct value *function, |
6d82d43b | 5129 | struct type *type, struct regcache *regcache, |
47a35522 | 5130 | gdb_byte *readbuf, const gdb_byte *writebuf) |
ebafbe83 | 5131 | { |
72a155b4 | 5132 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
b18bb924 MR |
5133 | |
5134 | /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004 | |
5135 | ||
5136 | Function results are returned in $2 (and $3 if needed), or $f0 (and $f2 | |
5137 | if needed), as appropriate for the type. Composite results (struct, | |
5138 | union, or array) are returned in $2/$f0 and $3/$f2 according to the | |
5139 | following rules: | |
5140 | ||
5141 | * A struct with only one or two floating point fields is returned in $f0 | |
5142 | (and $f2 if necessary). This is a generalization of the Fortran COMPLEX | |
5143 | case. | |
5144 | ||
f08877ba | 5145 | * Any other composite results of at most 128 bits are returned in |
b18bb924 MR |
5146 | $2 (first 64 bits) and $3 (remainder, if necessary). |
5147 | ||
5148 | * Larger composite results are handled by converting the function to a | |
5149 | procedure with an implicit first parameter, which is a pointer to an area | |
5150 | reserved by the caller to receive the result. [The o32-bit ABI requires | |
5151 | that all composite results be handled by conversion to implicit first | |
5152 | parameters. The MIPS/SGI Fortran implementation has always made a | |
5153 | specific exception to return COMPLEX results in the floating point | |
5154 | registers.] */ | |
5155 | ||
f08877ba | 5156 | if (TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE) |
6d82d43b | 5157 | return RETURN_VALUE_STRUCT_CONVENTION; |
d05f6826 DJ |
5158 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
5159 | && TYPE_LENGTH (type) == 16 | |
5160 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5161 | { | |
5162 | /* A 128-bit floating-point value fills both $f0 and $f2. The | |
5163 | two registers are used in the same as memory order, so the | |
5164 | eight bytes with the lower memory address are in $f0. */ | |
5165 | if (mips_debug) | |
5166 | fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n"); | |
ba32f989 | 5167 | mips_xfer_register (gdbarch, regcache, |
dca9aa3a MR |
5168 | (gdbarch_num_regs (gdbarch) |
5169 | + mips_regnum (gdbarch)->fp0), | |
72a155b4 | 5170 | 8, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5171 | readbuf, writebuf, 0); |
ba32f989 | 5172 | mips_xfer_register (gdbarch, regcache, |
dca9aa3a MR |
5173 | (gdbarch_num_regs (gdbarch) |
5174 | + mips_regnum (gdbarch)->fp0 + 2), | |
72a155b4 | 5175 | 8, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5176 | readbuf ? readbuf + 8 : readbuf, |
d05f6826 DJ |
5177 | writebuf ? writebuf + 8 : writebuf, 0); |
5178 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5179 | } | |
6d82d43b AC |
5180 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
5181 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5182 | { | |
59aa1faa | 5183 | /* A single or double floating-point value that fits in FP0. */ |
6d82d43b AC |
5184 | if (mips_debug) |
5185 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 5186 | mips_xfer_register (gdbarch, regcache, |
dca9aa3a MR |
5187 | (gdbarch_num_regs (gdbarch) |
5188 | + mips_regnum (gdbarch)->fp0), | |
6d82d43b | 5189 | TYPE_LENGTH (type), |
72a155b4 | 5190 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 5191 | readbuf, writebuf, 0); |
6d82d43b AC |
5192 | return RETURN_VALUE_REGISTER_CONVENTION; |
5193 | } | |
5194 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
5195 | && TYPE_NFIELDS (type) <= 2 | |
5196 | && TYPE_NFIELDS (type) >= 1 | |
5197 | && ((TYPE_NFIELDS (type) == 1 | |
b18bb924 | 5198 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b AC |
5199 | == TYPE_CODE_FLT)) |
5200 | || (TYPE_NFIELDS (type) == 2 | |
b18bb924 | 5201 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b | 5202 | == TYPE_CODE_FLT) |
b18bb924 | 5203 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1))) |
5b68030f | 5204 | == TYPE_CODE_FLT)))) |
6d82d43b AC |
5205 | { |
5206 | /* A struct that contains one or two floats. Each value is part | |
5207 | in the least significant part of their floating point | |
5b68030f | 5208 | register (or GPR, for soft float). */ |
6d82d43b AC |
5209 | int regnum; |
5210 | int field; | |
5b68030f JM |
5211 | for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE |
5212 | ? mips_regnum (gdbarch)->fp0 | |
5213 | : MIPS_V0_REGNUM); | |
6d82d43b AC |
5214 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
5215 | { | |
5216 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
5217 | / TARGET_CHAR_BIT); | |
5218 | if (mips_debug) | |
5219 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
5220 | offset); | |
5b68030f JM |
5221 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)) == 16) |
5222 | { | |
5223 | /* A 16-byte long double field goes in two consecutive | |
5224 | registers. */ | |
5225 | mips_xfer_register (gdbarch, regcache, | |
5226 | gdbarch_num_regs (gdbarch) + regnum, | |
5227 | 8, | |
5228 | gdbarch_byte_order (gdbarch), | |
5229 | readbuf, writebuf, offset); | |
5230 | mips_xfer_register (gdbarch, regcache, | |
5231 | gdbarch_num_regs (gdbarch) + regnum + 1, | |
5232 | 8, | |
5233 | gdbarch_byte_order (gdbarch), | |
5234 | readbuf, writebuf, offset + 8); | |
5235 | } | |
5236 | else | |
5237 | mips_xfer_register (gdbarch, regcache, | |
5238 | gdbarch_num_regs (gdbarch) + regnum, | |
5239 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
5240 | gdbarch_byte_order (gdbarch), | |
5241 | readbuf, writebuf, offset); | |
6d82d43b AC |
5242 | } |
5243 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5244 | } | |
5245 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
f08877ba JB |
5246 | || TYPE_CODE (type) == TYPE_CODE_UNION |
5247 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
6d82d43b | 5248 | { |
f08877ba | 5249 | /* A composite type. Extract the left justified value, |
6d82d43b AC |
5250 | regardless of the byte order. I.e. DO NOT USE |
5251 | mips_xfer_lower. */ | |
5252 | int offset; | |
5253 | int regnum; | |
4c7d22cb | 5254 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 5255 | offset < TYPE_LENGTH (type); |
72a155b4 | 5256 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 5257 | { |
72a155b4 | 5258 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
5259 | if (offset + xfer > TYPE_LENGTH (type)) |
5260 | xfer = TYPE_LENGTH (type) - offset; | |
5261 | if (mips_debug) | |
5262 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
5263 | offset, xfer, regnum); | |
ba32f989 DJ |
5264 | mips_xfer_register (gdbarch, regcache, |
5265 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 UW |
5266 | xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf, |
5267 | offset); | |
6d82d43b AC |
5268 | } |
5269 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5270 | } | |
5271 | else | |
5272 | { | |
5273 | /* A scalar extract each part but least-significant-byte | |
5274 | justified. */ | |
5275 | int offset; | |
5276 | int regnum; | |
4c7d22cb | 5277 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 5278 | offset < TYPE_LENGTH (type); |
72a155b4 | 5279 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 5280 | { |
72a155b4 | 5281 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
5282 | if (offset + xfer > TYPE_LENGTH (type)) |
5283 | xfer = TYPE_LENGTH (type) - offset; | |
5284 | if (mips_debug) | |
5285 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
5286 | offset, xfer, regnum); | |
ba32f989 DJ |
5287 | mips_xfer_register (gdbarch, regcache, |
5288 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 5289 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5290 | readbuf, writebuf, offset); |
6d82d43b AC |
5291 | } |
5292 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5293 | } | |
5294 | } | |
5295 | ||
6a3a010b MR |
5296 | /* Which registers to use for passing floating-point values between |
5297 | function calls, one of floating-point, general and both kinds of | |
5298 | registers. O32 and O64 use different register kinds for standard | |
5299 | MIPS and MIPS16 code; to make the handling of cases where we may | |
5300 | not know what kind of code is being used (e.g. no debug information) | |
5301 | easier we sometimes use both kinds. */ | |
5302 | ||
5303 | enum mips_fval_reg | |
5304 | { | |
5305 | mips_fval_fpr, | |
5306 | mips_fval_gpr, | |
5307 | mips_fval_both | |
5308 | }; | |
5309 | ||
6d82d43b AC |
5310 | /* O32 ABI stuff. */ |
5311 | ||
5312 | static CORE_ADDR | |
7d9b040b | 5313 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
5314 | struct regcache *regcache, CORE_ADDR bp_addr, |
5315 | int nargs, struct value **args, CORE_ADDR sp, | |
5316 | int struct_return, CORE_ADDR struct_addr) | |
5317 | { | |
5318 | int argreg; | |
5319 | int float_argreg; | |
5320 | int argnum; | |
5321 | int len = 0; | |
5322 | int stack_offset = 0; | |
e17a4113 | 5323 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 5324 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
5325 | |
5326 | /* For shared libraries, "t9" needs to point at the function | |
5327 | address. */ | |
4c7d22cb | 5328 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
6d82d43b AC |
5329 | |
5330 | /* Set the return address register to point to the entry point of | |
5331 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 5332 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
6d82d43b AC |
5333 | |
5334 | /* First ensure that the stack and structure return address (if any) | |
5335 | are properly aligned. The stack has to be at least 64-bit | |
5336 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
5337 | aligned. For n32 and n64, stack frames need to be 128-bit |
5338 | aligned, so we round to this widest known alignment. */ | |
5339 | ||
5b03f266 AC |
5340 | sp = align_down (sp, 16); |
5341 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
5342 | |
5343 | /* Now make space on the stack for the args. */ | |
5344 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
5345 | { |
5346 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
968b5391 MR |
5347 | |
5348 | /* Align to double-word if necessary. */ | |
2afd3f0a | 5349 | if (mips_type_needs_double_align (arg_type)) |
1a69e1e4 | 5350 | len = align_up (len, MIPS32_REGSIZE * 2); |
968b5391 | 5351 | /* Allocate space on the stack. */ |
354ecfd5 | 5352 | len += align_up (TYPE_LENGTH (arg_type), MIPS32_REGSIZE); |
968b5391 | 5353 | } |
5b03f266 | 5354 | sp -= align_up (len, 16); |
ebafbe83 MS |
5355 | |
5356 | if (mips_debug) | |
6d82d43b | 5357 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
5358 | "mips_o32_push_dummy_call: sp=%s allocated %ld\n", |
5359 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
5360 | |
5361 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 5362 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 5363 | float_argreg = mips_fpa0_regnum (gdbarch); |
ebafbe83 | 5364 | |
bcb0cc15 | 5365 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
5366 | if (struct_return) |
5367 | { | |
5368 | if (mips_debug) | |
5369 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
5370 | "mips_o32_push_dummy_call: " |
5371 | "struct_return reg=%d %s\n", | |
5af949e3 | 5372 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 5373 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 5374 | stack_offset += MIPS32_REGSIZE; |
ebafbe83 MS |
5375 | } |
5376 | ||
5377 | /* Now load as many as possible of the first arguments into | |
5378 | registers, and push the rest onto the stack. Loop thru args | |
5379 | from first to last. */ | |
5380 | for (argnum = 0; argnum < nargs; argnum++) | |
5381 | { | |
47a35522 | 5382 | const gdb_byte *val; |
ebafbe83 | 5383 | struct value *arg = args[argnum]; |
4991999e | 5384 | struct type *arg_type = check_typedef (value_type (arg)); |
ebafbe83 MS |
5385 | int len = TYPE_LENGTH (arg_type); |
5386 | enum type_code typecode = TYPE_CODE (arg_type); | |
5387 | ||
5388 | if (mips_debug) | |
5389 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 5390 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
5391 | argnum + 1, len, (int) typecode); |
5392 | ||
47a35522 | 5393 | val = value_contents (arg); |
46cac009 AC |
5394 | |
5395 | /* 32-bit ABIs always start floating point arguments in an | |
5396 | even-numbered floating point register. Round the FP register | |
5397 | up before the check to see if there are any FP registers | |
6a3a010b MR |
5398 | left. O32 targets also pass the FP in the integer registers |
5399 | so also round up normal registers. */ | |
74ed0bb4 | 5400 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
46cac009 AC |
5401 | { |
5402 | if ((float_argreg & 1)) | |
5403 | float_argreg++; | |
5404 | } | |
5405 | ||
5406 | /* Floating point arguments passed in registers have to be | |
6a3a010b MR |
5407 | treated specially. On 32-bit architectures, doubles are |
5408 | passed in register pairs; the even FP register gets the | |
5409 | low word, and the odd FP register gets the high word. | |
5410 | On O32, the first two floating point arguments are also | |
5411 | copied to general registers, following their memory order, | |
5412 | because MIPS16 functions don't use float registers for | |
5413 | arguments. This duplication of arguments in general | |
5414 | registers can't hurt non-MIPS16 functions, because those | |
5415 | registers are normally skipped. */ | |
46cac009 | 5416 | |
74ed0bb4 MD |
5417 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
5418 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
46cac009 | 5419 | { |
8b07f6d8 | 5420 | if (register_size (gdbarch, float_argreg) < 8 && len == 8) |
46cac009 | 5421 | { |
6a3a010b MR |
5422 | int freg_offset = gdbarch_byte_order (gdbarch) |
5423 | == BFD_ENDIAN_BIG ? 1 : 0; | |
46cac009 AC |
5424 | unsigned long regval; |
5425 | ||
6a3a010b MR |
5426 | /* First word. */ |
5427 | regval = extract_unsigned_integer (val, 4, byte_order); | |
46cac009 AC |
5428 | if (mips_debug) |
5429 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
6a3a010b MR |
5430 | float_argreg + freg_offset, |
5431 | phex (regval, 4)); | |
025bb325 | 5432 | regcache_cooked_write_unsigned (regcache, |
6a3a010b MR |
5433 | float_argreg++ + freg_offset, |
5434 | regval); | |
46cac009 AC |
5435 | if (mips_debug) |
5436 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5437 | argreg, phex (regval, 4)); | |
9c9acae0 | 5438 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 | 5439 | |
6a3a010b MR |
5440 | /* Second word. */ |
5441 | regval = extract_unsigned_integer (val + 4, 4, byte_order); | |
46cac009 AC |
5442 | if (mips_debug) |
5443 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
6a3a010b MR |
5444 | float_argreg - freg_offset, |
5445 | phex (regval, 4)); | |
025bb325 | 5446 | regcache_cooked_write_unsigned (regcache, |
6a3a010b MR |
5447 | float_argreg++ - freg_offset, |
5448 | regval); | |
46cac009 AC |
5449 | if (mips_debug) |
5450 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5451 | argreg, phex (regval, 4)); | |
9c9acae0 | 5452 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
5453 | } |
5454 | else | |
5455 | { | |
5456 | /* This is a floating point value that fits entirely | |
5457 | in a single register. */ | |
5458 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 5459 | above to ensure that it is even register aligned. */ |
e17a4113 | 5460 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
46cac009 AC |
5461 | if (mips_debug) |
5462 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5463 | float_argreg, phex (regval, len)); | |
025bb325 MS |
5464 | regcache_cooked_write_unsigned (regcache, |
5465 | float_argreg++, regval); | |
5b68030f JM |
5466 | /* Although two FP registers are reserved for each |
5467 | argument, only one corresponding integer register is | |
5468 | reserved. */ | |
46cac009 AC |
5469 | if (mips_debug) |
5470 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5471 | argreg, phex (regval, len)); | |
5b68030f | 5472 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
5473 | } |
5474 | /* Reserve space for the FP register. */ | |
1a69e1e4 | 5475 | stack_offset += align_up (len, MIPS32_REGSIZE); |
46cac009 AC |
5476 | } |
5477 | else | |
5478 | { | |
5479 | /* Copy the argument to general registers or the stack in | |
5480 | register-sized pieces. Large arguments are split between | |
5481 | registers and stack. */ | |
1a69e1e4 DJ |
5482 | /* Note: structs whose size is not a multiple of MIPS32_REGSIZE |
5483 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
5484 | them in registers where gcc sometimes puts them on the |
5485 | stack. For maximum compatibility, we will put them in | |
5486 | both places. */ | |
1a69e1e4 DJ |
5487 | int odd_sized_struct = (len > MIPS32_REGSIZE |
5488 | && len % MIPS32_REGSIZE != 0); | |
46cac009 AC |
5489 | /* Structures should be aligned to eight bytes (even arg registers) |
5490 | on MIPS_ABI_O32, if their first member has double precision. */ | |
2afd3f0a | 5491 | if (mips_type_needs_double_align (arg_type)) |
46cac009 AC |
5492 | { |
5493 | if ((argreg & 1)) | |
968b5391 MR |
5494 | { |
5495 | argreg++; | |
1a69e1e4 | 5496 | stack_offset += MIPS32_REGSIZE; |
968b5391 | 5497 | } |
46cac009 | 5498 | } |
46cac009 AC |
5499 | while (len > 0) |
5500 | { | |
1a69e1e4 | 5501 | int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); |
46cac009 AC |
5502 | |
5503 | if (mips_debug) | |
5504 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
5505 | partial_len); | |
5506 | ||
5507 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 5508 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 5509 | || odd_sized_struct) |
46cac009 AC |
5510 | { |
5511 | /* Should shorter than int integer values be | |
025bb325 | 5512 | promoted to int before being stored? */ |
46cac009 AC |
5513 | int longword_offset = 0; |
5514 | CORE_ADDR addr; | |
46cac009 AC |
5515 | |
5516 | if (mips_debug) | |
5517 | { | |
5af949e3 UW |
5518 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
5519 | paddress (gdbarch, stack_offset)); | |
5520 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
5521 | paddress (gdbarch, longword_offset)); | |
46cac009 AC |
5522 | } |
5523 | ||
5524 | addr = sp + stack_offset + longword_offset; | |
5525 | ||
5526 | if (mips_debug) | |
5527 | { | |
5528 | int i; | |
5af949e3 UW |
5529 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
5530 | paddress (gdbarch, addr)); | |
46cac009 AC |
5531 | for (i = 0; i < partial_len; i++) |
5532 | { | |
6d82d43b | 5533 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
5534 | val[i] & 0xff); |
5535 | } | |
5536 | } | |
5537 | write_memory (addr, val, partial_len); | |
5538 | } | |
5539 | ||
5540 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 5541 | structs may go thru BOTH paths. */ |
46cac009 | 5542 | /* Write this portion of the argument to a general |
6d82d43b | 5543 | purpose register. */ |
74ed0bb4 | 5544 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
46cac009 | 5545 | { |
e17a4113 UW |
5546 | LONGEST regval = extract_signed_integer (val, partial_len, |
5547 | byte_order); | |
4246e332 | 5548 | /* Value may need to be sign extended, because |
1b13c4f6 | 5549 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
5550 | |
5551 | /* A non-floating-point argument being passed in a | |
5552 | general register. If a struct or union, and if | |
5553 | the remaining length is smaller than the register | |
5554 | size, we have to adjust the register value on | |
5555 | big endian targets. | |
5556 | ||
5557 | It does not seem to be necessary to do the | |
5558 | same for integral types. | |
5559 | ||
5560 | Also don't do this adjustment on O64 binaries. | |
5561 | ||
5562 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
5563 | outputting LE O32 with sizeof (struct) < | |
e914cb17 MR |
5564 | mips_abi_regsize(), generates a left shift |
5565 | as part of storing the argument in a register | |
5566 | (the left shift isn't generated when | |
1b13c4f6 | 5567 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
5568 | it is quite possible that this is GCC |
5569 | contradicting the LE/O32 ABI, GDB has not been | |
5570 | adjusted to accommodate this. Either someone | |
5571 | needs to demonstrate that the LE/O32 ABI | |
5572 | specifies such a left shift OR this new ABI gets | |
5573 | identified as such and GDB gets tweaked | |
5574 | accordingly. */ | |
5575 | ||
72a155b4 | 5576 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 5577 | && partial_len < MIPS32_REGSIZE |
06f9a1af MR |
5578 | && (typecode == TYPE_CODE_STRUCT |
5579 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 5580 | regval <<= ((MIPS32_REGSIZE - partial_len) |
9ecf7166 | 5581 | * TARGET_CHAR_BIT); |
46cac009 AC |
5582 | |
5583 | if (mips_debug) | |
5584 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
5585 | argreg, | |
1a69e1e4 | 5586 | phex (regval, MIPS32_REGSIZE)); |
9c9acae0 | 5587 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
46cac009 AC |
5588 | argreg++; |
5589 | ||
5590 | /* Prevent subsequent floating point arguments from | |
5591 | being passed in floating point registers. */ | |
74ed0bb4 | 5592 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
46cac009 AC |
5593 | } |
5594 | ||
5595 | len -= partial_len; | |
5596 | val += partial_len; | |
5597 | ||
b021a221 MS |
5598 | /* Compute the offset into the stack at which we will |
5599 | copy the next parameter. | |
46cac009 | 5600 | |
6d82d43b AC |
5601 | In older ABIs, the caller reserved space for |
5602 | registers that contained arguments. This was loosely | |
5603 | refered to as their "home". Consequently, space is | |
5604 | always allocated. */ | |
46cac009 | 5605 | |
1a69e1e4 | 5606 | stack_offset += align_up (partial_len, MIPS32_REGSIZE); |
46cac009 AC |
5607 | } |
5608 | } | |
5609 | if (mips_debug) | |
5610 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
5611 | } | |
5612 | ||
f10683bb | 5613 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 5614 | |
46cac009 AC |
5615 | /* Return adjusted stack pointer. */ |
5616 | return sp; | |
5617 | } | |
5618 | ||
6d82d43b | 5619 | static enum return_value_convention |
6a3a010b | 5620 | mips_o32_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 | 5621 | struct type *type, struct regcache *regcache, |
47a35522 | 5622 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 5623 | { |
6a3a010b | 5624 | CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0; |
4cc0665f | 5625 | int mips16 = mips_pc_is_mips16 (gdbarch, func_addr); |
72a155b4 | 5626 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
6a3a010b | 5627 | enum mips_fval_reg fval_reg; |
6d82d43b | 5628 | |
6a3a010b | 5629 | fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both; |
6d82d43b AC |
5630 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
5631 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
5632 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
5633 | return RETURN_VALUE_STRUCT_CONVENTION; | |
5634 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
5635 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5636 | { | |
6a3a010b MR |
5637 | /* A single-precision floating-point value. If reading in or copying, |
5638 | then we get it from/put it to FP0 for standard MIPS code or GPR2 | |
5639 | for MIPS16 code. If writing out only, then we put it to both FP0 | |
5640 | and GPR2. We do not support reading in with no function known, if | |
5641 | this safety check ever triggers, then we'll have to try harder. */ | |
5642 | gdb_assert (function || !readbuf); | |
6d82d43b | 5643 | if (mips_debug) |
6a3a010b MR |
5644 | switch (fval_reg) |
5645 | { | |
5646 | case mips_fval_fpr: | |
5647 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
5648 | break; | |
5649 | case mips_fval_gpr: | |
5650 | fprintf_unfiltered (gdb_stderr, "Return float in $2\n"); | |
5651 | break; | |
5652 | case mips_fval_both: | |
5653 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n"); | |
5654 | break; | |
5655 | } | |
5656 | if (fval_reg != mips_fval_gpr) | |
5657 | mips_xfer_register (gdbarch, regcache, | |
5658 | (gdbarch_num_regs (gdbarch) | |
5659 | + mips_regnum (gdbarch)->fp0), | |
5660 | TYPE_LENGTH (type), | |
5661 | gdbarch_byte_order (gdbarch), | |
5662 | readbuf, writebuf, 0); | |
5663 | if (fval_reg != mips_fval_fpr) | |
5664 | mips_xfer_register (gdbarch, regcache, | |
5665 | gdbarch_num_regs (gdbarch) + 2, | |
5666 | TYPE_LENGTH (type), | |
5667 | gdbarch_byte_order (gdbarch), | |
5668 | readbuf, writebuf, 0); | |
6d82d43b AC |
5669 | return RETURN_VALUE_REGISTER_CONVENTION; |
5670 | } | |
5671 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
5672 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5673 | { | |
6a3a010b MR |
5674 | /* A double-precision floating-point value. If reading in or copying, |
5675 | then we get it from/put it to FP1 and FP0 for standard MIPS code or | |
5676 | GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it | |
5677 | to both FP1/FP0 and GPR2/GPR3. We do not support reading in with | |
5678 | no function known, if this safety check ever triggers, then we'll | |
5679 | have to try harder. */ | |
5680 | gdb_assert (function || !readbuf); | |
6d82d43b | 5681 | if (mips_debug) |
6a3a010b MR |
5682 | switch (fval_reg) |
5683 | { | |
5684 | case mips_fval_fpr: | |
5685 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
5686 | break; | |
5687 | case mips_fval_gpr: | |
5688 | fprintf_unfiltered (gdb_stderr, "Return float in $2/$3\n"); | |
5689 | break; | |
5690 | case mips_fval_both: | |
5691 | fprintf_unfiltered (gdb_stderr, | |
5692 | "Return float in $fp1/$fp0 and $2/$3\n"); | |
5693 | break; | |
5694 | } | |
5695 | if (fval_reg != mips_fval_gpr) | |
6d82d43b | 5696 | { |
6a3a010b MR |
5697 | /* The most significant part goes in FP1, and the least significant |
5698 | in FP0. */ | |
5699 | switch (gdbarch_byte_order (gdbarch)) | |
5700 | { | |
5701 | case BFD_ENDIAN_LITTLE: | |
5702 | mips_xfer_register (gdbarch, regcache, | |
5703 | (gdbarch_num_regs (gdbarch) | |
5704 | + mips_regnum (gdbarch)->fp0 + 0), | |
5705 | 4, gdbarch_byte_order (gdbarch), | |
5706 | readbuf, writebuf, 0); | |
5707 | mips_xfer_register (gdbarch, regcache, | |
5708 | (gdbarch_num_regs (gdbarch) | |
5709 | + mips_regnum (gdbarch)->fp0 + 1), | |
5710 | 4, gdbarch_byte_order (gdbarch), | |
5711 | readbuf, writebuf, 4); | |
5712 | break; | |
5713 | case BFD_ENDIAN_BIG: | |
5714 | mips_xfer_register (gdbarch, regcache, | |
5715 | (gdbarch_num_regs (gdbarch) | |
5716 | + mips_regnum (gdbarch)->fp0 + 1), | |
5717 | 4, gdbarch_byte_order (gdbarch), | |
5718 | readbuf, writebuf, 0); | |
5719 | mips_xfer_register (gdbarch, regcache, | |
5720 | (gdbarch_num_regs (gdbarch) | |
5721 | + mips_regnum (gdbarch)->fp0 + 0), | |
5722 | 4, gdbarch_byte_order (gdbarch), | |
5723 | readbuf, writebuf, 4); | |
5724 | break; | |
5725 | default: | |
5726 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
5727 | } | |
5728 | } | |
5729 | if (fval_reg != mips_fval_fpr) | |
5730 | { | |
5731 | /* The two 32-bit parts are always placed in GPR2 and GPR3 | |
5732 | following these registers' memory order. */ | |
ba32f989 | 5733 | mips_xfer_register (gdbarch, regcache, |
6a3a010b | 5734 | gdbarch_num_regs (gdbarch) + 2, |
72a155b4 | 5735 | 4, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5736 | readbuf, writebuf, 0); |
ba32f989 | 5737 | mips_xfer_register (gdbarch, regcache, |
6a3a010b | 5738 | gdbarch_num_regs (gdbarch) + 3, |
72a155b4 | 5739 | 4, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5740 | readbuf, writebuf, 4); |
6d82d43b AC |
5741 | } |
5742 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5743 | } | |
5744 | #if 0 | |
5745 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
5746 | && TYPE_NFIELDS (type) <= 2 | |
5747 | && TYPE_NFIELDS (type) >= 1 | |
5748 | && ((TYPE_NFIELDS (type) == 1 | |
5749 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
5750 | == TYPE_CODE_FLT)) | |
5751 | || (TYPE_NFIELDS (type) == 2 | |
5752 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
5753 | == TYPE_CODE_FLT) | |
5754 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
5755 | == TYPE_CODE_FLT))) | |
5756 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5757 | { | |
5758 | /* A struct that contains one or two floats. Each value is part | |
5759 | in the least significant part of their floating point | |
5760 | register.. */ | |
870cd05e | 5761 | gdb_byte reg[MAX_REGISTER_SIZE]; |
6d82d43b AC |
5762 | int regnum; |
5763 | int field; | |
72a155b4 | 5764 | for (field = 0, regnum = mips_regnum (gdbarch)->fp0; |
6d82d43b AC |
5765 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
5766 | { | |
5767 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
5768 | / TARGET_CHAR_BIT); | |
5769 | if (mips_debug) | |
5770 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
5771 | offset); | |
ba32f989 DJ |
5772 | mips_xfer_register (gdbarch, regcache, |
5773 | gdbarch_num_regs (gdbarch) + regnum, | |
6d82d43b | 5774 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
72a155b4 | 5775 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 5776 | readbuf, writebuf, offset); |
6d82d43b AC |
5777 | } |
5778 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5779 | } | |
5780 | #endif | |
5781 | #if 0 | |
5782 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
5783 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
5784 | { | |
5785 | /* A structure or union. Extract the left justified value, | |
5786 | regardless of the byte order. I.e. DO NOT USE | |
5787 | mips_xfer_lower. */ | |
5788 | int offset; | |
5789 | int regnum; | |
4c7d22cb | 5790 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 5791 | offset < TYPE_LENGTH (type); |
72a155b4 | 5792 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 5793 | { |
72a155b4 | 5794 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
5795 | if (offset + xfer > TYPE_LENGTH (type)) |
5796 | xfer = TYPE_LENGTH (type) - offset; | |
5797 | if (mips_debug) | |
5798 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
5799 | offset, xfer, regnum); | |
ba32f989 DJ |
5800 | mips_xfer_register (gdbarch, regcache, |
5801 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
6d82d43b AC |
5802 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
5803 | } | |
5804 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5805 | } | |
5806 | #endif | |
5807 | else | |
5808 | { | |
5809 | /* A scalar extract each part but least-significant-byte | |
5810 | justified. o32 thinks registers are 4 byte, regardless of | |
1a69e1e4 | 5811 | the ISA. */ |
6d82d43b AC |
5812 | int offset; |
5813 | int regnum; | |
4c7d22cb | 5814 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 5815 | offset < TYPE_LENGTH (type); |
1a69e1e4 | 5816 | offset += MIPS32_REGSIZE, regnum++) |
6d82d43b | 5817 | { |
1a69e1e4 | 5818 | int xfer = MIPS32_REGSIZE; |
6d82d43b AC |
5819 | if (offset + xfer > TYPE_LENGTH (type)) |
5820 | xfer = TYPE_LENGTH (type) - offset; | |
5821 | if (mips_debug) | |
5822 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
5823 | offset, xfer, regnum); | |
ba32f989 DJ |
5824 | mips_xfer_register (gdbarch, regcache, |
5825 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
72a155b4 | 5826 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 5827 | readbuf, writebuf, offset); |
6d82d43b AC |
5828 | } |
5829 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5830 | } | |
5831 | } | |
5832 | ||
5833 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
5834 | ABI. */ | |
46cac009 AC |
5835 | |
5836 | static CORE_ADDR | |
7d9b040b | 5837 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
5838 | struct regcache *regcache, CORE_ADDR bp_addr, |
5839 | int nargs, | |
5840 | struct value **args, CORE_ADDR sp, | |
5841 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
5842 | { |
5843 | int argreg; | |
5844 | int float_argreg; | |
5845 | int argnum; | |
5846 | int len = 0; | |
5847 | int stack_offset = 0; | |
e17a4113 | 5848 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 5849 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 5850 | |
25ab4790 AC |
5851 | /* For shared libraries, "t9" needs to point at the function |
5852 | address. */ | |
4c7d22cb | 5853 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
5854 | |
5855 | /* Set the return address register to point to the entry point of | |
5856 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 5857 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 5858 | |
46cac009 AC |
5859 | /* First ensure that the stack and structure return address (if any) |
5860 | are properly aligned. The stack has to be at least 64-bit | |
5861 | aligned even on 32-bit machines, because doubles must be 64-bit | |
5862 | aligned. For n32 and n64, stack frames need to be 128-bit | |
5863 | aligned, so we round to this widest known alignment. */ | |
5864 | ||
5b03f266 AC |
5865 | sp = align_down (sp, 16); |
5866 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
5867 | |
5868 | /* Now make space on the stack for the args. */ | |
5869 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
5870 | { |
5871 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
968b5391 | 5872 | |
968b5391 | 5873 | /* Allocate space on the stack. */ |
354ecfd5 | 5874 | len += align_up (TYPE_LENGTH (arg_type), MIPS64_REGSIZE); |
968b5391 | 5875 | } |
5b03f266 | 5876 | sp -= align_up (len, 16); |
46cac009 AC |
5877 | |
5878 | if (mips_debug) | |
6d82d43b | 5879 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
5880 | "mips_o64_push_dummy_call: sp=%s allocated %ld\n", |
5881 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
46cac009 AC |
5882 | |
5883 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 5884 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 5885 | float_argreg = mips_fpa0_regnum (gdbarch); |
46cac009 AC |
5886 | |
5887 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
5888 | if (struct_return) | |
5889 | { | |
5890 | if (mips_debug) | |
5891 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
5892 | "mips_o64_push_dummy_call: " |
5893 | "struct_return reg=%d %s\n", | |
5af949e3 | 5894 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 5895 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 5896 | stack_offset += MIPS64_REGSIZE; |
46cac009 AC |
5897 | } |
5898 | ||
5899 | /* Now load as many as possible of the first arguments into | |
5900 | registers, and push the rest onto the stack. Loop thru args | |
5901 | from first to last. */ | |
5902 | for (argnum = 0; argnum < nargs; argnum++) | |
5903 | { | |
47a35522 | 5904 | const gdb_byte *val; |
46cac009 | 5905 | struct value *arg = args[argnum]; |
4991999e | 5906 | struct type *arg_type = check_typedef (value_type (arg)); |
46cac009 AC |
5907 | int len = TYPE_LENGTH (arg_type); |
5908 | enum type_code typecode = TYPE_CODE (arg_type); | |
5909 | ||
5910 | if (mips_debug) | |
5911 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 5912 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
5913 | argnum + 1, len, (int) typecode); |
5914 | ||
47a35522 | 5915 | val = value_contents (arg); |
ebafbe83 | 5916 | |
ebafbe83 | 5917 | /* Floating point arguments passed in registers have to be |
6a3a010b MR |
5918 | treated specially. On 32-bit architectures, doubles are |
5919 | passed in register pairs; the even FP register gets the | |
5920 | low word, and the odd FP register gets the high word. | |
5921 | On O64, the first two floating point arguments are also | |
5922 | copied to general registers, because MIPS16 functions | |
5923 | don't use float registers for arguments. This duplication | |
5924 | of arguments in general registers can't hurt non-MIPS16 | |
5925 | functions because those registers are normally skipped. */ | |
ebafbe83 | 5926 | |
74ed0bb4 MD |
5927 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
5928 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
ebafbe83 | 5929 | { |
e17a4113 | 5930 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
2afd3f0a MR |
5931 | if (mips_debug) |
5932 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5933 | float_argreg, phex (regval, len)); | |
9c9acae0 | 5934 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
2afd3f0a MR |
5935 | if (mips_debug) |
5936 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5937 | argreg, phex (regval, len)); | |
9c9acae0 | 5938 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
2afd3f0a | 5939 | argreg++; |
ebafbe83 | 5940 | /* Reserve space for the FP register. */ |
1a69e1e4 | 5941 | stack_offset += align_up (len, MIPS64_REGSIZE); |
ebafbe83 MS |
5942 | } |
5943 | else | |
5944 | { | |
5945 | /* Copy the argument to general registers or the stack in | |
5946 | register-sized pieces. Large arguments are split between | |
5947 | registers and stack. */ | |
1a69e1e4 | 5948 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
5949 | are treated specially: Irix cc passes them in registers |
5950 | where gcc sometimes puts them on the stack. For maximum | |
5951 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
5952 | int odd_sized_struct = (len > MIPS64_REGSIZE |
5953 | && len % MIPS64_REGSIZE != 0); | |
ebafbe83 MS |
5954 | while (len > 0) |
5955 | { | |
1a69e1e4 | 5956 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
ebafbe83 MS |
5957 | |
5958 | if (mips_debug) | |
5959 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
5960 | partial_len); | |
5961 | ||
5962 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 5963 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 5964 | || odd_sized_struct) |
ebafbe83 MS |
5965 | { |
5966 | /* Should shorter than int integer values be | |
025bb325 | 5967 | promoted to int before being stored? */ |
ebafbe83 MS |
5968 | int longword_offset = 0; |
5969 | CORE_ADDR addr; | |
72a155b4 | 5970 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ebafbe83 | 5971 | { |
1a69e1e4 DJ |
5972 | if ((typecode == TYPE_CODE_INT |
5973 | || typecode == TYPE_CODE_PTR | |
5974 | || typecode == TYPE_CODE_FLT) | |
5975 | && len <= 4) | |
5976 | longword_offset = MIPS64_REGSIZE - len; | |
ebafbe83 MS |
5977 | } |
5978 | ||
5979 | if (mips_debug) | |
5980 | { | |
5af949e3 UW |
5981 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
5982 | paddress (gdbarch, stack_offset)); | |
5983 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
5984 | paddress (gdbarch, longword_offset)); | |
ebafbe83 MS |
5985 | } |
5986 | ||
5987 | addr = sp + stack_offset + longword_offset; | |
5988 | ||
5989 | if (mips_debug) | |
5990 | { | |
5991 | int i; | |
5af949e3 UW |
5992 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
5993 | paddress (gdbarch, addr)); | |
ebafbe83 MS |
5994 | for (i = 0; i < partial_len; i++) |
5995 | { | |
6d82d43b | 5996 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
5997 | val[i] & 0xff); |
5998 | } | |
5999 | } | |
6000 | write_memory (addr, val, partial_len); | |
6001 | } | |
6002 | ||
6003 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 6004 | structs may go thru BOTH paths. */ |
ebafbe83 | 6005 | /* Write this portion of the argument to a general |
6d82d43b | 6006 | purpose register. */ |
74ed0bb4 | 6007 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
ebafbe83 | 6008 | { |
e17a4113 UW |
6009 | LONGEST regval = extract_signed_integer (val, partial_len, |
6010 | byte_order); | |
4246e332 | 6011 | /* Value may need to be sign extended, because |
1b13c4f6 | 6012 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
6013 | |
6014 | /* A non-floating-point argument being passed in a | |
6015 | general register. If a struct or union, and if | |
6016 | the remaining length is smaller than the register | |
6017 | size, we have to adjust the register value on | |
6018 | big endian targets. | |
6019 | ||
6020 | It does not seem to be necessary to do the | |
025bb325 | 6021 | same for integral types. */ |
480d3dd2 | 6022 | |
72a155b4 | 6023 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 6024 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
6025 | && (typecode == TYPE_CODE_STRUCT |
6026 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 6027 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 6028 | * TARGET_CHAR_BIT); |
ebafbe83 MS |
6029 | |
6030 | if (mips_debug) | |
6031 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
6032 | argreg, | |
1a69e1e4 | 6033 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 6034 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
ebafbe83 MS |
6035 | argreg++; |
6036 | ||
6037 | /* Prevent subsequent floating point arguments from | |
6038 | being passed in floating point registers. */ | |
74ed0bb4 | 6039 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
ebafbe83 MS |
6040 | } |
6041 | ||
6042 | len -= partial_len; | |
6043 | val += partial_len; | |
6044 | ||
b021a221 MS |
6045 | /* Compute the offset into the stack at which we will |
6046 | copy the next parameter. | |
ebafbe83 | 6047 | |
6d82d43b AC |
6048 | In older ABIs, the caller reserved space for |
6049 | registers that contained arguments. This was loosely | |
6050 | refered to as their "home". Consequently, space is | |
6051 | always allocated. */ | |
ebafbe83 | 6052 | |
1a69e1e4 | 6053 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
ebafbe83 MS |
6054 | } |
6055 | } | |
6056 | if (mips_debug) | |
6057 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
6058 | } | |
6059 | ||
f10683bb | 6060 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 6061 | |
ebafbe83 MS |
6062 | /* Return adjusted stack pointer. */ |
6063 | return sp; | |
6064 | } | |
6065 | ||
9c8fdbfa | 6066 | static enum return_value_convention |
6a3a010b | 6067 | mips_o64_return_value (struct gdbarch *gdbarch, struct value *function, |
9c8fdbfa | 6068 | struct type *type, struct regcache *regcache, |
47a35522 | 6069 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 6070 | { |
6a3a010b | 6071 | CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0; |
4cc0665f | 6072 | int mips16 = mips_pc_is_mips16 (gdbarch, func_addr); |
72a155b4 | 6073 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
6a3a010b | 6074 | enum mips_fval_reg fval_reg; |
7a076fd2 | 6075 | |
6a3a010b | 6076 | fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both; |
7a076fd2 FF |
6077 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
6078 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
6079 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
6080 | return RETURN_VALUE_STRUCT_CONVENTION; | |
74ed0bb4 | 6081 | else if (fp_register_arg_p (gdbarch, TYPE_CODE (type), type)) |
7a076fd2 | 6082 | { |
6a3a010b MR |
6083 | /* A floating-point value. If reading in or copying, then we get it |
6084 | from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code. | |
6085 | If writing out only, then we put it to both FP0 and GPR2. We do | |
6086 | not support reading in with no function known, if this safety | |
6087 | check ever triggers, then we'll have to try harder. */ | |
6088 | gdb_assert (function || !readbuf); | |
7a076fd2 | 6089 | if (mips_debug) |
6a3a010b MR |
6090 | switch (fval_reg) |
6091 | { | |
6092 | case mips_fval_fpr: | |
6093 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
6094 | break; | |
6095 | case mips_fval_gpr: | |
6096 | fprintf_unfiltered (gdb_stderr, "Return float in $2\n"); | |
6097 | break; | |
6098 | case mips_fval_both: | |
6099 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n"); | |
6100 | break; | |
6101 | } | |
6102 | if (fval_reg != mips_fval_gpr) | |
6103 | mips_xfer_register (gdbarch, regcache, | |
6104 | (gdbarch_num_regs (gdbarch) | |
6105 | + mips_regnum (gdbarch)->fp0), | |
6106 | TYPE_LENGTH (type), | |
6107 | gdbarch_byte_order (gdbarch), | |
6108 | readbuf, writebuf, 0); | |
6109 | if (fval_reg != mips_fval_fpr) | |
6110 | mips_xfer_register (gdbarch, regcache, | |
6111 | gdbarch_num_regs (gdbarch) + 2, | |
6112 | TYPE_LENGTH (type), | |
6113 | gdbarch_byte_order (gdbarch), | |
6114 | readbuf, writebuf, 0); | |
7a076fd2 FF |
6115 | return RETURN_VALUE_REGISTER_CONVENTION; |
6116 | } | |
6117 | else | |
6118 | { | |
6119 | /* A scalar extract each part but least-significant-byte | |
025bb325 | 6120 | justified. */ |
7a076fd2 FF |
6121 | int offset; |
6122 | int regnum; | |
6123 | for (offset = 0, regnum = MIPS_V0_REGNUM; | |
6124 | offset < TYPE_LENGTH (type); | |
1a69e1e4 | 6125 | offset += MIPS64_REGSIZE, regnum++) |
7a076fd2 | 6126 | { |
1a69e1e4 | 6127 | int xfer = MIPS64_REGSIZE; |
7a076fd2 FF |
6128 | if (offset + xfer > TYPE_LENGTH (type)) |
6129 | xfer = TYPE_LENGTH (type) - offset; | |
6130 | if (mips_debug) | |
6131 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
6132 | offset, xfer, regnum); | |
ba32f989 DJ |
6133 | mips_xfer_register (gdbarch, regcache, |
6134 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 6135 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 6136 | readbuf, writebuf, offset); |
7a076fd2 FF |
6137 | } |
6138 | return RETURN_VALUE_REGISTER_CONVENTION; | |
6139 | } | |
6d82d43b AC |
6140 | } |
6141 | ||
dd824b04 DJ |
6142 | /* Floating point register management. |
6143 | ||
6144 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
6145 | 64bit operations, these early MIPS cpus treat fp register pairs | |
6146 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
6147 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
6148 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
6149 | double precision floats into two 32-bit chunks and store them in | |
6150 | consecutive fp regs. To display 64-bit floats stored in this | |
6151 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
6152 | Throw in user-configurable endianness and you have a real mess. | |
6153 | ||
6154 | The way this works is: | |
6155 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
6156 | double-precision value will be split across two logical registers. | |
6157 | The lower-numbered logical register will hold the low-order bits, | |
6158 | regardless of the processor's endianness. | |
6159 | - If we are on a 64-bit processor, and we are looking for a | |
6160 | single-precision value, it will be in the low ordered bits | |
6161 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
6162 | save slot in memory. | |
6163 | - If we are in 64-bit mode, everything is straightforward. | |
6164 | ||
6165 | Note that this code only deals with "live" registers at the top of the | |
6166 | stack. We will attempt to deal with saved registers later, when | |
025bb325 | 6167 | the raw/cooked register interface is in place. (We need a general |
dd824b04 DJ |
6168 | interface that can deal with dynamic saved register sizes -- fp |
6169 | regs could be 32 bits wide in one frame and 64 on the frame above | |
6170 | and below). */ | |
6171 | ||
6172 | /* Copy a 32-bit single-precision value from the current frame | |
6173 | into rare_buffer. */ | |
6174 | ||
6175 | static void | |
e11c53d2 | 6176 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
47a35522 | 6177 | gdb_byte *rare_buffer) |
dd824b04 | 6178 | { |
72a155b4 UW |
6179 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6180 | int raw_size = register_size (gdbarch, regno); | |
224c3ddb | 6181 | gdb_byte *raw_buffer = (gdb_byte *) alloca (raw_size); |
dd824b04 | 6182 | |
ca9d61b9 | 6183 | if (!deprecated_frame_register_read (frame, regno, raw_buffer)) |
c9f4d572 | 6184 | error (_("can't read register %d (%s)"), |
72a155b4 | 6185 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
6186 | if (raw_size == 8) |
6187 | { | |
6188 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 6189 | 32 bits. */ |
dd824b04 DJ |
6190 | int offset; |
6191 | ||
72a155b4 | 6192 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 DJ |
6193 | offset = 4; |
6194 | else | |
6195 | offset = 0; | |
6196 | ||
6197 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
6198 | } | |
6199 | else | |
6200 | { | |
6201 | memcpy (rare_buffer, raw_buffer, 4); | |
6202 | } | |
6203 | } | |
6204 | ||
6205 | /* Copy a 64-bit double-precision value from the current frame into | |
6206 | rare_buffer. This may include getting half of it from the next | |
6207 | register. */ | |
6208 | ||
6209 | static void | |
e11c53d2 | 6210 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
47a35522 | 6211 | gdb_byte *rare_buffer) |
dd824b04 | 6212 | { |
72a155b4 UW |
6213 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6214 | int raw_size = register_size (gdbarch, regno); | |
dd824b04 | 6215 | |
9c9acae0 | 6216 | if (raw_size == 8 && !mips2_fp_compat (frame)) |
dd824b04 DJ |
6217 | { |
6218 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 6219 | all 64 bits. */ |
ca9d61b9 | 6220 | if (!deprecated_frame_register_read (frame, regno, rare_buffer)) |
c9f4d572 | 6221 | error (_("can't read register %d (%s)"), |
72a155b4 | 6222 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
6223 | } |
6224 | else | |
6225 | { | |
72a155b4 | 6226 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
82e91389 | 6227 | |
72a155b4 | 6228 | if ((rawnum - mips_regnum (gdbarch)->fp0) & 1) |
dd824b04 | 6229 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
6230 | _("mips_read_fp_register_double: bad access to " |
6231 | "odd-numbered FP register")); | |
dd824b04 DJ |
6232 | |
6233 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 6234 | each register. */ |
72a155b4 | 6235 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 | 6236 | { |
e11c53d2 AC |
6237 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
6238 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 6239 | } |
361d1df0 | 6240 | else |
dd824b04 | 6241 | { |
e11c53d2 AC |
6242 | mips_read_fp_register_single (frame, regno, rare_buffer); |
6243 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
6244 | } |
6245 | } | |
6246 | } | |
6247 | ||
c906108c | 6248 | static void |
e11c53d2 AC |
6249 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
6250 | int regnum) | |
025bb325 | 6251 | { /* Do values for FP (float) regs. */ |
72a155b4 | 6252 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 6253 | gdb_byte *raw_buffer; |
025bb325 | 6254 | double doub, flt1; /* Doubles extracted from raw hex data. */ |
3903d437 | 6255 | int inv1, inv2; |
c5aa993b | 6256 | |
224c3ddb SM |
6257 | raw_buffer |
6258 | = ((gdb_byte *) | |
6259 | alloca (2 * register_size (gdbarch, mips_regnum (gdbarch)->fp0))); | |
c906108c | 6260 | |
72a155b4 | 6261 | fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum)); |
c9f4d572 | 6262 | fprintf_filtered (file, "%*s", |
72a155b4 | 6263 | 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)), |
e11c53d2 | 6264 | ""); |
f0ef6b29 | 6265 | |
72a155b4 | 6266 | if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame)) |
c906108c | 6267 | { |
79a45b7d TT |
6268 | struct value_print_options opts; |
6269 | ||
f0ef6b29 KB |
6270 | /* 4-byte registers: Print hex and floating. Also print even |
6271 | numbered registers as doubles. */ | |
e11c53d2 | 6272 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
025bb325 MS |
6273 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, |
6274 | raw_buffer, &inv1); | |
c5aa993b | 6275 | |
79a45b7d | 6276 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
6277 | print_scalar_formatted (raw_buffer, |
6278 | builtin_type (gdbarch)->builtin_uint32, | |
6279 | &opts, 'w', file); | |
dd824b04 | 6280 | |
e11c53d2 | 6281 | fprintf_filtered (file, " flt: "); |
1adad886 | 6282 | if (inv1) |
e11c53d2 | 6283 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 6284 | else |
e11c53d2 | 6285 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 6286 | |
72a155b4 | 6287 | if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0) |
f0ef6b29 | 6288 | { |
e11c53d2 | 6289 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
27067745 UW |
6290 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
6291 | raw_buffer, &inv2); | |
1adad886 | 6292 | |
e11c53d2 | 6293 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 6294 | if (inv2) |
e11c53d2 | 6295 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 6296 | else |
e11c53d2 | 6297 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 6298 | } |
c906108c SS |
6299 | } |
6300 | else | |
dd824b04 | 6301 | { |
79a45b7d TT |
6302 | struct value_print_options opts; |
6303 | ||
f0ef6b29 | 6304 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 6305 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
27067745 UW |
6306 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, |
6307 | raw_buffer, &inv1); | |
c906108c | 6308 | |
e11c53d2 | 6309 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
27067745 UW |
6310 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
6311 | raw_buffer, &inv2); | |
f0ef6b29 | 6312 | |
79a45b7d | 6313 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
6314 | print_scalar_formatted (raw_buffer, |
6315 | builtin_type (gdbarch)->builtin_uint64, | |
6316 | &opts, 'g', file); | |
f0ef6b29 | 6317 | |
e11c53d2 | 6318 | fprintf_filtered (file, " flt: "); |
1adad886 | 6319 | if (inv1) |
e11c53d2 | 6320 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 6321 | else |
e11c53d2 | 6322 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 6323 | |
e11c53d2 | 6324 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 6325 | if (inv2) |
e11c53d2 | 6326 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 6327 | else |
e11c53d2 | 6328 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
6329 | } |
6330 | } | |
6331 | ||
6332 | static void | |
e11c53d2 | 6333 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
0cc93a06 | 6334 | int regnum) |
f0ef6b29 | 6335 | { |
a4b8ebc8 | 6336 | struct gdbarch *gdbarch = get_frame_arch (frame); |
79a45b7d | 6337 | struct value_print_options opts; |
de15c4ab | 6338 | struct value *val; |
1adad886 | 6339 | |
004159a2 | 6340 | if (mips_float_register_p (gdbarch, regnum)) |
f0ef6b29 | 6341 | { |
e11c53d2 | 6342 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
6343 | return; |
6344 | } | |
6345 | ||
de15c4ab | 6346 | val = get_frame_register_value (frame, regnum); |
f0ef6b29 | 6347 | |
72a155b4 | 6348 | fputs_filtered (gdbarch_register_name (gdbarch, regnum), file); |
f0ef6b29 KB |
6349 | |
6350 | /* The problem with printing numeric register names (r26, etc.) is that | |
6351 | the user can't use them on input. Probably the best solution is to | |
6352 | fix it so that either the numeric or the funky (a2, etc.) names | |
6353 | are accepted on input. */ | |
6354 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 6355 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 6356 | else |
e11c53d2 | 6357 | fprintf_filtered (file, ": "); |
f0ef6b29 | 6358 | |
79a45b7d | 6359 | get_formatted_print_options (&opts, 'x'); |
de15c4ab | 6360 | val_print_scalar_formatted (value_type (val), |
de15c4ab PA |
6361 | value_embedded_offset (val), |
6362 | val, | |
6363 | &opts, 0, file); | |
c906108c SS |
6364 | } |
6365 | ||
1bab7383 YQ |
6366 | /* Print IEEE exception condition bits in FLAGS. */ |
6367 | ||
6368 | static void | |
6369 | print_fpu_flags (struct ui_file *file, int flags) | |
6370 | { | |
6371 | if (flags & (1 << 0)) | |
6372 | fputs_filtered (" inexact", file); | |
6373 | if (flags & (1 << 1)) | |
6374 | fputs_filtered (" uflow", file); | |
6375 | if (flags & (1 << 2)) | |
6376 | fputs_filtered (" oflow", file); | |
6377 | if (flags & (1 << 3)) | |
6378 | fputs_filtered (" div0", file); | |
6379 | if (flags & (1 << 4)) | |
6380 | fputs_filtered (" inval", file); | |
6381 | if (flags & (1 << 5)) | |
6382 | fputs_filtered (" unimp", file); | |
6383 | fputc_filtered ('\n', file); | |
6384 | } | |
6385 | ||
6386 | /* Print interesting information about the floating point processor | |
6387 | (if present) or emulator. */ | |
6388 | ||
6389 | static void | |
6390 | mips_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, | |
6391 | struct frame_info *frame, const char *args) | |
6392 | { | |
6393 | int fcsr = mips_regnum (gdbarch)->fp_control_status; | |
6394 | enum mips_fpu_type type = MIPS_FPU_TYPE (gdbarch); | |
6395 | ULONGEST fcs = 0; | |
6396 | int i; | |
6397 | ||
6398 | if (fcsr == -1 || !read_frame_register_unsigned (frame, fcsr, &fcs)) | |
6399 | type = MIPS_FPU_NONE; | |
6400 | ||
6401 | fprintf_filtered (file, "fpu type: %s\n", | |
6402 | type == MIPS_FPU_DOUBLE ? "double-precision" | |
6403 | : type == MIPS_FPU_SINGLE ? "single-precision" | |
6404 | : "none / unused"); | |
6405 | ||
6406 | if (type == MIPS_FPU_NONE) | |
6407 | return; | |
6408 | ||
6409 | fprintf_filtered (file, "reg size: %d bits\n", | |
6410 | register_size (gdbarch, mips_regnum (gdbarch)->fp0) * 8); | |
6411 | ||
6412 | fputs_filtered ("cond :", file); | |
6413 | if (fcs & (1 << 23)) | |
6414 | fputs_filtered (" 0", file); | |
6415 | for (i = 1; i <= 7; i++) | |
6416 | if (fcs & (1 << (24 + i))) | |
6417 | fprintf_filtered (file, " %d", i); | |
6418 | fputc_filtered ('\n', file); | |
6419 | ||
6420 | fputs_filtered ("cause :", file); | |
6421 | print_fpu_flags (file, (fcs >> 12) & 0x3f); | |
6422 | fputs ("mask :", stdout); | |
6423 | print_fpu_flags (file, (fcs >> 7) & 0x1f); | |
6424 | fputs ("flags :", stdout); | |
6425 | print_fpu_flags (file, (fcs >> 2) & 0x1f); | |
6426 | ||
6427 | fputs_filtered ("rounding: ", file); | |
6428 | switch (fcs & 3) | |
6429 | { | |
6430 | case 0: fputs_filtered ("nearest\n", file); break; | |
6431 | case 1: fputs_filtered ("zero\n", file); break; | |
6432 | case 2: fputs_filtered ("+inf\n", file); break; | |
6433 | case 3: fputs_filtered ("-inf\n", file); break; | |
6434 | } | |
6435 | ||
6436 | fputs_filtered ("flush :", file); | |
6437 | if (fcs & (1 << 21)) | |
6438 | fputs_filtered (" nearest", file); | |
6439 | if (fcs & (1 << 22)) | |
6440 | fputs_filtered (" override", file); | |
6441 | if (fcs & (1 << 24)) | |
6442 | fputs_filtered (" zero", file); | |
6443 | if ((fcs & (0xb << 21)) == 0) | |
6444 | fputs_filtered (" no", file); | |
6445 | fputc_filtered ('\n', file); | |
6446 | ||
6447 | fprintf_filtered (file, "nan2008 : %s\n", fcs & (1 << 18) ? "yes" : "no"); | |
6448 | fprintf_filtered (file, "abs2008 : %s\n", fcs & (1 << 19) ? "yes" : "no"); | |
6449 | fputc_filtered ('\n', file); | |
6450 | ||
6451 | default_print_float_info (gdbarch, file, frame, args); | |
6452 | } | |
6453 | ||
f0ef6b29 KB |
6454 | /* Replacement for generic do_registers_info. |
6455 | Print regs in pretty columns. */ | |
6456 | ||
6457 | static int | |
e11c53d2 AC |
6458 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
6459 | int regnum) | |
f0ef6b29 | 6460 | { |
e11c53d2 AC |
6461 | fprintf_filtered (file, " "); |
6462 | mips_print_fp_register (file, frame, regnum); | |
6463 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
6464 | return regnum + 1; |
6465 | } | |
6466 | ||
6467 | ||
025bb325 | 6468 | /* Print a row's worth of GP (int) registers, with name labels above. */ |
c906108c SS |
6469 | |
6470 | static int | |
e11c53d2 | 6471 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 6472 | int start_regnum) |
c906108c | 6473 | { |
a4b8ebc8 | 6474 | struct gdbarch *gdbarch = get_frame_arch (frame); |
025bb325 | 6475 | /* Do values for GP (int) regs. */ |
47a35522 | 6476 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
025bb325 MS |
6477 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols |
6478 | per row. */ | |
c906108c | 6479 | int col, byte; |
a4b8ebc8 | 6480 | int regnum; |
c906108c | 6481 | |
025bb325 | 6482 | /* For GP registers, we print a separate row of names above the vals. */ |
a4b8ebc8 | 6483 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
6484 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
6485 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 6486 | regnum++) |
c906108c | 6487 | { |
72a155b4 | 6488 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 6489 | continue; /* unused register */ |
004159a2 | 6490 | if (mips_float_register_p (gdbarch, regnum)) |
025bb325 | 6491 | break; /* End the row: reached FP register. */ |
0cc93a06 | 6492 | /* Large registers are handled separately. */ |
72a155b4 | 6493 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
6494 | { |
6495 | if (col > 0) | |
6496 | break; /* End the row before this register. */ | |
6497 | ||
6498 | /* Print this register on a row by itself. */ | |
6499 | mips_print_register (file, frame, regnum); | |
6500 | fprintf_filtered (file, "\n"); | |
6501 | return regnum + 1; | |
6502 | } | |
d05f6826 DJ |
6503 | if (col == 0) |
6504 | fprintf_filtered (file, " "); | |
6d82d43b | 6505 | fprintf_filtered (file, |
72a155b4 UW |
6506 | mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s", |
6507 | gdbarch_register_name (gdbarch, regnum)); | |
c906108c SS |
6508 | col++; |
6509 | } | |
d05f6826 DJ |
6510 | |
6511 | if (col == 0) | |
6512 | return regnum; | |
6513 | ||
025bb325 | 6514 | /* Print the R0 to R31 names. */ |
72a155b4 | 6515 | if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS) |
f57d151a | 6516 | fprintf_filtered (file, "\n R%-4d", |
72a155b4 | 6517 | start_regnum % gdbarch_num_regs (gdbarch)); |
20e6603c AC |
6518 | else |
6519 | fprintf_filtered (file, "\n "); | |
c906108c | 6520 | |
025bb325 | 6521 | /* Now print the values in hex, 4 or 8 to the row. */ |
a4b8ebc8 | 6522 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
6523 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
6524 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 6525 | regnum++) |
c906108c | 6526 | { |
72a155b4 | 6527 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 6528 | continue; /* unused register */ |
004159a2 | 6529 | if (mips_float_register_p (gdbarch, regnum)) |
025bb325 | 6530 | break; /* End row: reached FP register. */ |
72a155b4 | 6531 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
6532 | break; /* End row: large register. */ |
6533 | ||
c906108c | 6534 | /* OK: get the data in raw format. */ |
ca9d61b9 | 6535 | if (!deprecated_frame_register_read (frame, regnum, raw_buffer)) |
c9f4d572 | 6536 | error (_("can't read register %d (%s)"), |
72a155b4 | 6537 | regnum, gdbarch_register_name (gdbarch, regnum)); |
c906108c | 6538 | /* pad small registers */ |
4246e332 | 6539 | for (byte = 0; |
72a155b4 UW |
6540 | byte < (mips_abi_regsize (gdbarch) |
6541 | - register_size (gdbarch, regnum)); byte++) | |
c906108c | 6542 | printf_filtered (" "); |
025bb325 | 6543 | /* Now print the register value in hex, endian order. */ |
72a155b4 | 6544 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b | 6545 | for (byte = |
72a155b4 UW |
6546 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
6547 | byte < register_size (gdbarch, regnum); byte++) | |
47a35522 | 6548 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
c906108c | 6549 | else |
72a155b4 | 6550 | for (byte = register_size (gdbarch, regnum) - 1; |
6d82d43b | 6551 | byte >= 0; byte--) |
47a35522 | 6552 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
e11c53d2 | 6553 | fprintf_filtered (file, " "); |
c906108c SS |
6554 | col++; |
6555 | } | |
025bb325 | 6556 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 6557 | fprintf_filtered (file, "\n"); |
c906108c SS |
6558 | |
6559 | return regnum; | |
6560 | } | |
6561 | ||
025bb325 | 6562 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */ |
c906108c | 6563 | |
bf1f5b4c | 6564 | static void |
e11c53d2 AC |
6565 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
6566 | struct frame_info *frame, int regnum, int all) | |
c906108c | 6567 | { |
025bb325 | 6568 | if (regnum != -1) /* Do one specified register. */ |
c906108c | 6569 | { |
72a155b4 UW |
6570 | gdb_assert (regnum >= gdbarch_num_regs (gdbarch)); |
6571 | if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
8a3fe4f8 | 6572 | error (_("Not a valid register for the current processor type")); |
c906108c | 6573 | |
0cc93a06 | 6574 | mips_print_register (file, frame, regnum); |
e11c53d2 | 6575 | fprintf_filtered (file, "\n"); |
c906108c | 6576 | } |
c5aa993b | 6577 | else |
025bb325 | 6578 | /* Do all (or most) registers. */ |
c906108c | 6579 | { |
72a155b4 UW |
6580 | regnum = gdbarch_num_regs (gdbarch); |
6581 | while (regnum < gdbarch_num_regs (gdbarch) | |
6582 | + gdbarch_num_pseudo_regs (gdbarch)) | |
c906108c | 6583 | { |
004159a2 | 6584 | if (mips_float_register_p (gdbarch, regnum)) |
e11c53d2 | 6585 | { |
025bb325 | 6586 | if (all) /* True for "INFO ALL-REGISTERS" command. */ |
e11c53d2 AC |
6587 | regnum = print_fp_register_row (file, frame, regnum); |
6588 | else | |
025bb325 | 6589 | regnum += MIPS_NUMREGS; /* Skip floating point regs. */ |
e11c53d2 | 6590 | } |
c906108c | 6591 | else |
e11c53d2 | 6592 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
6593 | } |
6594 | } | |
6595 | } | |
6596 | ||
63807e1d | 6597 | static int |
3352ef37 AC |
6598 | mips_single_step_through_delay (struct gdbarch *gdbarch, |
6599 | struct frame_info *frame) | |
c906108c | 6600 | { |
e17a4113 | 6601 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
3352ef37 | 6602 | CORE_ADDR pc = get_frame_pc (frame); |
4cc0665f MR |
6603 | struct address_space *aspace; |
6604 | enum mips_isa isa; | |
6605 | ULONGEST insn; | |
6606 | int status; | |
6607 | int size; | |
6608 | ||
6609 | if ((mips_pc_is_mips (pc) | |
ab50adb6 | 6610 | && !mips32_insn_at_pc_has_delay_slot (gdbarch, pc)) |
4cc0665f | 6611 | || (mips_pc_is_micromips (gdbarch, pc) |
ab50adb6 | 6612 | && !micromips_insn_at_pc_has_delay_slot (gdbarch, pc, 0)) |
4cc0665f | 6613 | || (mips_pc_is_mips16 (gdbarch, pc) |
ab50adb6 | 6614 | && !mips16_insn_at_pc_has_delay_slot (gdbarch, pc, 0))) |
06648491 MK |
6615 | return 0; |
6616 | ||
4cc0665f MR |
6617 | isa = mips_pc_isa (gdbarch, pc); |
6618 | /* _has_delay_slot above will have validated the read. */ | |
6619 | insn = mips_fetch_instruction (gdbarch, isa, pc, NULL); | |
6620 | size = mips_insn_size (isa, insn); | |
6621 | aspace = get_frame_address_space (frame); | |
6622 | return breakpoint_here_p (aspace, pc + size) != no_breakpoint_here; | |
c906108c SS |
6623 | } |
6624 | ||
6d82d43b AC |
6625 | /* To skip prologues, I use this predicate. Returns either PC itself |
6626 | if the code at PC does not look like a function prologue; otherwise | |
6627 | returns an address that (if we're lucky) follows the prologue. If | |
6628 | LENIENT, then we must skip everything which is involved in setting | |
6629 | up the frame (it's OK to skip more, just so long as we don't skip | |
6630 | anything which might clobber the registers which are being saved. | |
6631 | We must skip more in the case where part of the prologue is in the | |
6632 | delay slot of a non-prologue instruction). */ | |
6633 | ||
6634 | static CORE_ADDR | |
6093d2eb | 6635 | mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
6d82d43b | 6636 | { |
8b622e6a AC |
6637 | CORE_ADDR limit_pc; |
6638 | CORE_ADDR func_addr; | |
6639 | ||
6d82d43b AC |
6640 | /* See if we can determine the end of the prologue via the symbol table. |
6641 | If so, then return either PC, or the PC after the prologue, whichever | |
6642 | is greater. */ | |
8b622e6a AC |
6643 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
6644 | { | |
d80b854b UW |
6645 | CORE_ADDR post_prologue_pc |
6646 | = skip_prologue_using_sal (gdbarch, func_addr); | |
8b622e6a | 6647 | if (post_prologue_pc != 0) |
325fac50 | 6648 | return std::max (pc, post_prologue_pc); |
8b622e6a | 6649 | } |
6d82d43b AC |
6650 | |
6651 | /* Can't determine prologue from the symbol table, need to examine | |
6652 | instructions. */ | |
6653 | ||
98b4dd94 JB |
6654 | /* Find an upper limit on the function prologue using the debug |
6655 | information. If the debug information could not be used to provide | |
6656 | that bound, then use an arbitrary large number as the upper bound. */ | |
d80b854b | 6657 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
98b4dd94 JB |
6658 | if (limit_pc == 0) |
6659 | limit_pc = pc + 100; /* Magic. */ | |
6660 | ||
4cc0665f | 6661 | if (mips_pc_is_mips16 (gdbarch, pc)) |
e17a4113 | 6662 | return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
4cc0665f MR |
6663 | else if (mips_pc_is_micromips (gdbarch, pc)) |
6664 | return micromips_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); | |
6d82d43b | 6665 | else |
e17a4113 | 6666 | return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
88658117 AC |
6667 | } |
6668 | ||
c9cf6e20 MG |
6669 | /* Implement the stack_frame_destroyed_p gdbarch method (32-bit version). |
6670 | This is a helper function for mips_stack_frame_destroyed_p. */ | |
6671 | ||
97ab0fdd | 6672 | static int |
c9cf6e20 | 6673 | mips32_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
6674 | { |
6675 | CORE_ADDR func_addr = 0, func_end = 0; | |
6676 | ||
6677 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
6678 | { | |
6679 | /* The MIPS epilogue is max. 12 bytes long. */ | |
6680 | CORE_ADDR addr = func_end - 12; | |
6681 | ||
6682 | if (addr < func_addr + 4) | |
6683 | addr = func_addr + 4; | |
6684 | if (pc < addr) | |
6685 | return 0; | |
6686 | ||
6687 | for (; pc < func_end; pc += MIPS_INSN32_SIZE) | |
6688 | { | |
6689 | unsigned long high_word; | |
6690 | unsigned long inst; | |
6691 | ||
4cc0665f | 6692 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
97ab0fdd MR |
6693 | high_word = (inst >> 16) & 0xffff; |
6694 | ||
6695 | if (high_word != 0x27bd /* addiu $sp,$sp,offset */ | |
6696 | && high_word != 0x67bd /* daddiu $sp,$sp,offset */ | |
6697 | && inst != 0x03e00008 /* jr $ra */ | |
6698 | && inst != 0x00000000) /* nop */ | |
6699 | return 0; | |
6700 | } | |
6701 | ||
6702 | return 1; | |
6703 | } | |
6704 | ||
6705 | return 0; | |
6706 | } | |
6707 | ||
c9cf6e20 MG |
6708 | /* Implement the stack_frame_destroyed_p gdbarch method (microMIPS version). |
6709 | This is a helper function for mips_stack_frame_destroyed_p. */ | |
4cc0665f MR |
6710 | |
6711 | static int | |
c9cf6e20 | 6712 | micromips_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
4cc0665f MR |
6713 | { |
6714 | CORE_ADDR func_addr = 0; | |
6715 | CORE_ADDR func_end = 0; | |
6716 | CORE_ADDR addr; | |
6717 | ULONGEST insn; | |
6718 | long offset; | |
6719 | int dreg; | |
6720 | int sreg; | |
6721 | int loc; | |
6722 | ||
6723 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
6724 | return 0; | |
6725 | ||
6726 | /* The microMIPS epilogue is max. 12 bytes long. */ | |
6727 | addr = func_end - 12; | |
6728 | ||
6729 | if (addr < func_addr + 2) | |
6730 | addr = func_addr + 2; | |
6731 | if (pc < addr) | |
6732 | return 0; | |
6733 | ||
6734 | for (; pc < func_end; pc += loc) | |
6735 | { | |
6736 | loc = 0; | |
6737 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
6738 | loc += MIPS_INSN16_SIZE; | |
6739 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
6740 | { | |
4cc0665f MR |
6741 | /* 32-bit instructions. */ |
6742 | case 2 * MIPS_INSN16_SIZE: | |
6743 | insn <<= 16; | |
6744 | insn |= mips_fetch_instruction (gdbarch, | |
6745 | ISA_MICROMIPS, pc + loc, NULL); | |
6746 | loc += MIPS_INSN16_SIZE; | |
6747 | switch (micromips_op (insn >> 16)) | |
6748 | { | |
6749 | case 0xc: /* ADDIU: bits 001100 */ | |
6750 | case 0x17: /* DADDIU: bits 010111 */ | |
6751 | sreg = b0s5_reg (insn >> 16); | |
6752 | dreg = b5s5_reg (insn >> 16); | |
6753 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
6754 | if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM | |
6755 | /* (D)ADDIU $sp, imm */ | |
6756 | && offset >= 0) | |
6757 | break; | |
6758 | return 0; | |
6759 | ||
6760 | default: | |
6761 | return 0; | |
6762 | } | |
6763 | break; | |
6764 | ||
6765 | /* 16-bit instructions. */ | |
6766 | case MIPS_INSN16_SIZE: | |
6767 | switch (micromips_op (insn)) | |
6768 | { | |
6769 | case 0x3: /* MOVE: bits 000011 */ | |
6770 | sreg = b0s5_reg (insn); | |
6771 | dreg = b5s5_reg (insn); | |
6772 | if (sreg == 0 && dreg == 0) | |
6773 | /* MOVE $zero, $zero aka NOP */ | |
6774 | break; | |
6775 | return 0; | |
6776 | ||
6777 | case 0x11: /* POOL16C: bits 010001 */ | |
6778 | if (b5s5_op (insn) == 0x18 | |
6779 | /* JRADDIUSP: bits 010011 11000 */ | |
6780 | || (b5s5_op (insn) == 0xd | |
6781 | /* JRC: bits 010011 01101 */ | |
6782 | && b0s5_reg (insn) == MIPS_RA_REGNUM)) | |
6783 | /* JRC $ra */ | |
6784 | break; | |
6785 | return 0; | |
6786 | ||
6787 | case 0x13: /* POOL16D: bits 010011 */ | |
6788 | offset = micromips_decode_imm9 (b1s9_imm (insn)); | |
6789 | if ((insn & 0x1) == 0x1 | |
6790 | /* ADDIUSP: bits 010011 1 */ | |
6791 | && offset > 0) | |
6792 | break; | |
6793 | return 0; | |
6794 | ||
6795 | default: | |
6796 | return 0; | |
6797 | } | |
6798 | } | |
6799 | } | |
6800 | ||
6801 | return 1; | |
6802 | } | |
6803 | ||
c9cf6e20 MG |
6804 | /* Implement the stack_frame_destroyed_p gdbarch method (16-bit version). |
6805 | This is a helper function for mips_stack_frame_destroyed_p. */ | |
6806 | ||
97ab0fdd | 6807 | static int |
c9cf6e20 | 6808 | mips16_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
6809 | { |
6810 | CORE_ADDR func_addr = 0, func_end = 0; | |
6811 | ||
6812 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
6813 | { | |
6814 | /* The MIPS epilogue is max. 12 bytes long. */ | |
6815 | CORE_ADDR addr = func_end - 12; | |
6816 | ||
6817 | if (addr < func_addr + 4) | |
6818 | addr = func_addr + 4; | |
6819 | if (pc < addr) | |
6820 | return 0; | |
6821 | ||
6822 | for (; pc < func_end; pc += MIPS_INSN16_SIZE) | |
6823 | { | |
6824 | unsigned short inst; | |
6825 | ||
4cc0665f | 6826 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc, NULL); |
97ab0fdd MR |
6827 | |
6828 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
6829 | continue; | |
6830 | ||
6831 | if (inst != 0x6300 /* addiu $sp,offset */ | |
6832 | && inst != 0xfb00 /* daddiu $sp,$sp,offset */ | |
6833 | && inst != 0xe820 /* jr $ra */ | |
6834 | && inst != 0xe8a0 /* jrc $ra */ | |
6835 | && inst != 0x6500) /* nop */ | |
6836 | return 0; | |
6837 | } | |
6838 | ||
6839 | return 1; | |
6840 | } | |
6841 | ||
6842 | return 0; | |
6843 | } | |
6844 | ||
c9cf6e20 MG |
6845 | /* Implement the stack_frame_destroyed_p gdbarch method. |
6846 | ||
6847 | The epilogue is defined here as the area at the end of a function, | |
97ab0fdd | 6848 | after an instruction which destroys the function's stack frame. */ |
c9cf6e20 | 6849 | |
97ab0fdd | 6850 | static int |
c9cf6e20 | 6851 | mips_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd | 6852 | { |
4cc0665f | 6853 | if (mips_pc_is_mips16 (gdbarch, pc)) |
c9cf6e20 | 6854 | return mips16_stack_frame_destroyed_p (gdbarch, pc); |
4cc0665f | 6855 | else if (mips_pc_is_micromips (gdbarch, pc)) |
c9cf6e20 | 6856 | return micromips_stack_frame_destroyed_p (gdbarch, pc); |
97ab0fdd | 6857 | else |
c9cf6e20 | 6858 | return mips32_stack_frame_destroyed_p (gdbarch, pc); |
97ab0fdd MR |
6859 | } |
6860 | ||
025bb325 | 6861 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
a5ea2558 AC |
6862 | used for all MIPS-specific commands. */ |
6863 | ||
a5ea2558 | 6864 | static void |
acdb74a0 | 6865 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
6866 | { |
6867 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
6868 | } | |
6869 | ||
a5ea2558 | 6870 | static void |
acdb74a0 | 6871 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 6872 | { |
6d82d43b AC |
6873 | printf_unfiltered |
6874 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
6875 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
6876 | } | |
6877 | ||
c906108c SS |
6878 | /* Commands to show/set the MIPS FPU type. */ |
6879 | ||
c906108c | 6880 | static void |
acdb74a0 | 6881 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 6882 | { |
c906108c | 6883 | char *fpu; |
6ca0852e | 6884 | |
f5656ead | 6885 | if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips) |
6ca0852e UW |
6886 | { |
6887 | printf_unfiltered | |
6888 | ("The MIPS floating-point coprocessor is unknown " | |
6889 | "because the current architecture is not MIPS.\n"); | |
6890 | return; | |
6891 | } | |
6892 | ||
f5656ead | 6893 | switch (MIPS_FPU_TYPE (target_gdbarch ())) |
c906108c SS |
6894 | { |
6895 | case MIPS_FPU_SINGLE: | |
6896 | fpu = "single-precision"; | |
6897 | break; | |
6898 | case MIPS_FPU_DOUBLE: | |
6899 | fpu = "double-precision"; | |
6900 | break; | |
6901 | case MIPS_FPU_NONE: | |
6902 | fpu = "absent (none)"; | |
6903 | break; | |
93d56215 | 6904 | default: |
e2e0b3e5 | 6905 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c SS |
6906 | } |
6907 | if (mips_fpu_type_auto) | |
025bb325 MS |
6908 | printf_unfiltered ("The MIPS floating-point coprocessor " |
6909 | "is set automatically (currently %s)\n", | |
6910 | fpu); | |
c906108c | 6911 | else |
6d82d43b AC |
6912 | printf_unfiltered |
6913 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
6914 | } |
6915 | ||
6916 | ||
c906108c | 6917 | static void |
acdb74a0 | 6918 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 6919 | { |
025bb325 MS |
6920 | printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", " |
6921 | "\"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
6922 | show_mipsfpu_command (args, from_tty); |
6923 | } | |
6924 | ||
c906108c | 6925 | static void |
acdb74a0 | 6926 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 6927 | { |
8d5838b5 AC |
6928 | struct gdbarch_info info; |
6929 | gdbarch_info_init (&info); | |
c906108c SS |
6930 | mips_fpu_type = MIPS_FPU_SINGLE; |
6931 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
6932 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
6933 | instead of relying on globals. Doing that would let generic code | |
6934 | handle the search for this specific architecture. */ | |
6935 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 6936 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
6937 | } |
6938 | ||
c906108c | 6939 | static void |
acdb74a0 | 6940 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 6941 | { |
8d5838b5 AC |
6942 | struct gdbarch_info info; |
6943 | gdbarch_info_init (&info); | |
c906108c SS |
6944 | mips_fpu_type = MIPS_FPU_DOUBLE; |
6945 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
6946 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
6947 | instead of relying on globals. Doing that would let generic code | |
6948 | handle the search for this specific architecture. */ | |
6949 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 6950 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
6951 | } |
6952 | ||
c906108c | 6953 | static void |
acdb74a0 | 6954 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 6955 | { |
8d5838b5 AC |
6956 | struct gdbarch_info info; |
6957 | gdbarch_info_init (&info); | |
c906108c SS |
6958 | mips_fpu_type = MIPS_FPU_NONE; |
6959 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
6960 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
6961 | instead of relying on globals. Doing that would let generic code | |
6962 | handle the search for this specific architecture. */ | |
6963 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 6964 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
6965 | } |
6966 | ||
c906108c | 6967 | static void |
acdb74a0 | 6968 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
6969 | { |
6970 | mips_fpu_type_auto = 1; | |
6971 | } | |
6972 | ||
c906108c SS |
6973 | /* Just like reinit_frame_cache, but with the right arguments to be |
6974 | callable as an sfunc. */ | |
6975 | ||
6976 | static void | |
acdb74a0 AC |
6977 | reinit_frame_cache_sfunc (char *args, int from_tty, |
6978 | struct cmd_list_element *c) | |
c906108c SS |
6979 | { |
6980 | reinit_frame_cache (); | |
6981 | } | |
6982 | ||
a89aa300 AC |
6983 | static int |
6984 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 6985 | { |
e47ad6c0 YQ |
6986 | gdb_disassembler *di |
6987 | = static_cast<gdb_disassembler *>(info->application_data); | |
6988 | struct gdbarch *gdbarch = di->arch (); | |
4cc0665f | 6989 | |
d31431ed AC |
6990 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
6991 | disassembler needs to be able to locally determine the ISA, and | |
6992 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
6993 | work. */ | |
4cc0665f | 6994 | if (mips_pc_is_mips16 (gdbarch, memaddr)) |
ec4045ea | 6995 | info->mach = bfd_mach_mips16; |
4cc0665f MR |
6996 | else if (mips_pc_is_micromips (gdbarch, memaddr)) |
6997 | info->mach = bfd_mach_mips_micromips; | |
c906108c SS |
6998 | |
6999 | /* Round down the instruction address to the appropriate boundary. */ | |
4cc0665f MR |
7000 | memaddr &= (info->mach == bfd_mach_mips16 |
7001 | || info->mach == bfd_mach_mips_micromips) ? ~1 : ~3; | |
c5aa993b | 7002 | |
e5ab0dce | 7003 | /* Set the disassembler options. */ |
9dae60cc | 7004 | if (!info->disassembler_options) |
e5ab0dce AC |
7005 | /* This string is not recognized explicitly by the disassembler, |
7006 | but it tells the disassembler to not try to guess the ABI from | |
7007 | the bfd elf headers, such that, if the user overrides the ABI | |
7008 | of a program linked as NewABI, the disassembly will follow the | |
7009 | register naming conventions specified by the user. */ | |
7010 | info->disassembler_options = "gpr-names=32"; | |
7011 | ||
c906108c | 7012 | /* Call the appropriate disassembler based on the target endian-ness. */ |
40887e1a | 7013 | if (info->endian == BFD_ENDIAN_BIG) |
c906108c SS |
7014 | return print_insn_big_mips (memaddr, info); |
7015 | else | |
7016 | return print_insn_little_mips (memaddr, info); | |
7017 | } | |
7018 | ||
9dae60cc UW |
7019 | static int |
7020 | gdb_print_insn_mips_n32 (bfd_vma memaddr, struct disassemble_info *info) | |
7021 | { | |
7022 | /* Set up the disassembler info, so that we get the right | |
7023 | register names from libopcodes. */ | |
7024 | info->disassembler_options = "gpr-names=n32"; | |
7025 | info->flavour = bfd_target_elf_flavour; | |
7026 | ||
7027 | return gdb_print_insn_mips (memaddr, info); | |
7028 | } | |
7029 | ||
7030 | static int | |
7031 | gdb_print_insn_mips_n64 (bfd_vma memaddr, struct disassemble_info *info) | |
7032 | { | |
7033 | /* Set up the disassembler info, so that we get the right | |
7034 | register names from libopcodes. */ | |
7035 | info->disassembler_options = "gpr-names=64"; | |
7036 | info->flavour = bfd_target_elf_flavour; | |
7037 | ||
7038 | return gdb_print_insn_mips (memaddr, info); | |
7039 | } | |
7040 | ||
cd6c3b4f YQ |
7041 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ |
7042 | ||
d19280ad YQ |
7043 | static int |
7044 | mips_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
c906108c | 7045 | { |
4cc0665f MR |
7046 | CORE_ADDR pc = *pcptr; |
7047 | ||
d19280ad | 7048 | if (mips_pc_is_mips16 (gdbarch, pc)) |
c906108c | 7049 | { |
d19280ad YQ |
7050 | *pcptr = unmake_compact_addr (pc); |
7051 | return MIPS_BP_KIND_MIPS16; | |
7052 | } | |
7053 | else if (mips_pc_is_micromips (gdbarch, pc)) | |
7054 | { | |
7055 | ULONGEST insn; | |
7056 | int status; | |
c906108c | 7057 | |
d19280ad YQ |
7058 | *pcptr = unmake_compact_addr (pc); |
7059 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status); | |
7060 | if (status || (mips_insn_size (ISA_MICROMIPS, insn) == 2)) | |
7061 | return MIPS_BP_KIND_MICROMIPS16; | |
7062 | else | |
7063 | return MIPS_BP_KIND_MICROMIPS32; | |
c906108c SS |
7064 | } |
7065 | else | |
d19280ad YQ |
7066 | return MIPS_BP_KIND_MIPS32; |
7067 | } | |
7068 | ||
cd6c3b4f YQ |
7069 | /* Implement the sw_breakpoint_from_kind gdbarch method. */ |
7070 | ||
d19280ad YQ |
7071 | static const gdb_byte * |
7072 | mips_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) | |
7073 | { | |
7074 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
7075 | ||
7076 | switch (kind) | |
c906108c | 7077 | { |
d19280ad YQ |
7078 | case MIPS_BP_KIND_MIPS16: |
7079 | { | |
7080 | static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; | |
7081 | static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; | |
7082 | ||
7083 | *size = 2; | |
7084 | if (byte_order_for_code == BFD_ENDIAN_BIG) | |
7085 | return mips16_big_breakpoint; | |
7086 | else | |
c906108c | 7087 | return mips16_little_breakpoint; |
d19280ad YQ |
7088 | } |
7089 | case MIPS_BP_KIND_MICROMIPS16: | |
7090 | { | |
7091 | static gdb_byte micromips16_big_breakpoint[] = { 0x46, 0x85 }; | |
7092 | static gdb_byte micromips16_little_breakpoint[] = { 0x85, 0x46 }; | |
7093 | ||
7094 | *size = 2; | |
7095 | ||
7096 | if (byte_order_for_code == BFD_ENDIAN_BIG) | |
7097 | return micromips16_big_breakpoint; | |
7098 | else | |
7099 | return micromips16_little_breakpoint; | |
7100 | } | |
7101 | case MIPS_BP_KIND_MICROMIPS32: | |
7102 | { | |
7103 | static gdb_byte micromips32_big_breakpoint[] = { 0, 0x5, 0, 0x7 }; | |
7104 | static gdb_byte micromips32_little_breakpoint[] = { 0x5, 0, 0x7, 0 }; | |
7105 | ||
7106 | *size = 4; | |
7107 | if (byte_order_for_code == BFD_ENDIAN_BIG) | |
7108 | return micromips32_big_breakpoint; | |
7109 | else | |
7110 | return micromips32_little_breakpoint; | |
7111 | } | |
7112 | case MIPS_BP_KIND_MIPS32: | |
7113 | { | |
7114 | static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; | |
7115 | static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; | |
c906108c | 7116 | |
d19280ad YQ |
7117 | *size = 4; |
7118 | if (byte_order_for_code == BFD_ENDIAN_BIG) | |
7119 | return big_breakpoint; | |
7120 | else | |
7e3d947d | 7121 | return little_breakpoint; |
d19280ad YQ |
7122 | } |
7123 | default: | |
7124 | gdb_assert_not_reached ("unexpected mips breakpoint kind"); | |
7125 | }; | |
c906108c SS |
7126 | } |
7127 | ||
ab50adb6 MR |
7128 | /* Return non-zero if the standard MIPS instruction INST has a branch |
7129 | delay slot (i.e. it is a jump or branch instruction). This function | |
7130 | is based on mips32_next_pc. */ | |
c8cef75f MR |
7131 | |
7132 | static int | |
ab50adb6 | 7133 | mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, ULONGEST inst) |
c8cef75f | 7134 | { |
c8cef75f | 7135 | int op; |
a385295e MR |
7136 | int rs; |
7137 | int rt; | |
c8cef75f | 7138 | |
c8cef75f MR |
7139 | op = itype_op (inst); |
7140 | if ((inst & 0xe0000000) != 0) | |
a385295e MR |
7141 | { |
7142 | rs = itype_rs (inst); | |
7143 | rt = itype_rt (inst); | |
f94363d7 AP |
7144 | return (is_octeon_bbit_op (op, gdbarch) |
7145 | || op >> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ | |
a385295e MR |
7146 | || op == 29 /* JALX: bits 011101 */ |
7147 | || (op == 17 | |
7148 | && (rs == 8 | |
c8cef75f | 7149 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
a385295e MR |
7150 | || (rs == 9 && (rt & 0x2) == 0) |
7151 | /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */ | |
7152 | || (rs == 10 && (rt & 0x2) == 0)))); | |
7153 | /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */ | |
7154 | } | |
c8cef75f MR |
7155 | else |
7156 | switch (op & 0x07) /* extract bits 28,27,26 */ | |
7157 | { | |
7158 | case 0: /* SPECIAL */ | |
7159 | op = rtype_funct (inst); | |
7160 | return (op == 8 /* JR */ | |
7161 | || op == 9); /* JALR */ | |
7162 | break; /* end SPECIAL */ | |
7163 | case 1: /* REGIMM */ | |
a385295e MR |
7164 | rs = itype_rs (inst); |
7165 | rt = itype_rt (inst); /* branch condition */ | |
7166 | return ((rt & 0xc) == 0 | |
c8cef75f MR |
7167 | /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */ |
7168 | /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */ | |
a385295e MR |
7169 | || ((rt & 0x1e) == 0x1c && rs == 0)); |
7170 | /* BPOSGE32, BPOSGE64: bits 1110x */ | |
c8cef75f MR |
7171 | break; /* end REGIMM */ |
7172 | default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */ | |
7173 | return 1; | |
7174 | break; | |
7175 | } | |
7176 | } | |
7177 | ||
ab50adb6 MR |
7178 | /* Return non-zero if a standard MIPS instruction at ADDR has a branch |
7179 | delay slot (i.e. it is a jump or branch instruction). */ | |
c8cef75f | 7180 | |
4cc0665f | 7181 | static int |
ab50adb6 | 7182 | mips32_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr) |
4cc0665f MR |
7183 | { |
7184 | ULONGEST insn; | |
7185 | int status; | |
7186 | ||
ab50adb6 | 7187 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, addr, &status); |
4cc0665f MR |
7188 | if (status) |
7189 | return 0; | |
7190 | ||
ab50adb6 MR |
7191 | return mips32_instruction_has_delay_slot (gdbarch, insn); |
7192 | } | |
4cc0665f | 7193 | |
ab50adb6 MR |
7194 | /* Return non-zero if the microMIPS instruction INSN, comprising the |
7195 | 16-bit major opcode word in the high 16 bits and any second word | |
7196 | in the low 16 bits, has a branch delay slot (i.e. it is a non-compact | |
7197 | jump or branch instruction). The instruction must be 32-bit if | |
7198 | MUSTBE32 is set or can be any instruction otherwise. */ | |
7199 | ||
7200 | static int | |
7201 | micromips_instruction_has_delay_slot (ULONGEST insn, int mustbe32) | |
7202 | { | |
7203 | ULONGEST major = insn >> 16; | |
4cc0665f | 7204 | |
ab50adb6 MR |
7205 | switch (micromips_op (major)) |
7206 | { | |
7207 | /* 16-bit instructions. */ | |
7208 | case 0x33: /* B16: bits 110011 */ | |
7209 | case 0x2b: /* BNEZ16: bits 101011 */ | |
7210 | case 0x23: /* BEQZ16: bits 100011 */ | |
7211 | return !mustbe32; | |
7212 | case 0x11: /* POOL16C: bits 010001 */ | |
7213 | return (!mustbe32 | |
7214 | && ((b5s5_op (major) == 0xc | |
7215 | /* JR16: bits 010001 01100 */ | |
7216 | || (b5s5_op (major) & 0x1e) == 0xe))); | |
7217 | /* JALR16, JALRS16: bits 010001 0111x */ | |
7218 | /* 32-bit instructions. */ | |
7219 | case 0x3d: /* JAL: bits 111101 */ | |
7220 | case 0x3c: /* JALX: bits 111100 */ | |
7221 | case 0x35: /* J: bits 110101 */ | |
7222 | case 0x2d: /* BNE: bits 101101 */ | |
7223 | case 0x25: /* BEQ: bits 100101 */ | |
7224 | case 0x1d: /* JALS: bits 011101 */ | |
7225 | return 1; | |
7226 | case 0x10: /* POOL32I: bits 010000 */ | |
7227 | return ((b5s5_op (major) & 0x1c) == 0x0 | |
4cc0665f | 7228 | /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */ |
ab50adb6 | 7229 | || (b5s5_op (major) & 0x1d) == 0x4 |
4cc0665f | 7230 | /* BLEZ, BGTZ: bits 010000 001x0 */ |
ab50adb6 | 7231 | || (b5s5_op (major) & 0x1d) == 0x11 |
4cc0665f | 7232 | /* BLTZALS, BGEZALS: bits 010000 100x1 */ |
ab50adb6 MR |
7233 | || ((b5s5_op (major) & 0x1e) == 0x14 |
7234 | && (major & 0x3) == 0x0) | |
4cc0665f | 7235 | /* BC2F, BC2T: bits 010000 1010x xxx00 */ |
ab50adb6 | 7236 | || (b5s5_op (major) & 0x1e) == 0x1a |
4cc0665f | 7237 | /* BPOSGE64, BPOSGE32: bits 010000 1101x */ |
ab50adb6 MR |
7238 | || ((b5s5_op (major) & 0x1e) == 0x1c |
7239 | && (major & 0x3) == 0x0) | |
4cc0665f | 7240 | /* BC1F, BC1T: bits 010000 1110x xxx00 */ |
ab50adb6 MR |
7241 | || ((b5s5_op (major) & 0x1c) == 0x1c |
7242 | && (major & 0x3) == 0x1)); | |
4cc0665f | 7243 | /* BC1ANY*: bits 010000 111xx xxx01 */ |
ab50adb6 MR |
7244 | case 0x0: /* POOL32A: bits 000000 */ |
7245 | return (b0s6_op (insn) == 0x3c | |
7246 | /* POOL32Axf: bits 000000 ... 111100 */ | |
7247 | && (b6s10_ext (insn) & 0x2bf) == 0x3c); | |
7248 | /* JALR, JALR.HB: 000000 000x111100 111100 */ | |
7249 | /* JALRS, JALRS.HB: 000000 010x111100 111100 */ | |
7250 | default: | |
7251 | return 0; | |
7252 | } | |
4cc0665f MR |
7253 | } |
7254 | ||
ab50adb6 | 7255 | /* Return non-zero if a microMIPS instruction at ADDR has a branch delay |
ae790652 MR |
7256 | slot (i.e. it is a non-compact jump instruction). The instruction |
7257 | must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */ | |
7258 | ||
c8cef75f | 7259 | static int |
ab50adb6 MR |
7260 | micromips_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, |
7261 | CORE_ADDR addr, int mustbe32) | |
c8cef75f | 7262 | { |
ab50adb6 | 7263 | ULONGEST insn; |
c8cef75f | 7264 | int status; |
3f7f3650 | 7265 | int size; |
c8cef75f | 7266 | |
ab50adb6 | 7267 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status); |
c8cef75f MR |
7268 | if (status) |
7269 | return 0; | |
3f7f3650 | 7270 | size = mips_insn_size (ISA_MICROMIPS, insn); |
ab50adb6 | 7271 | insn <<= 16; |
3f7f3650 | 7272 | if (size == 2 * MIPS_INSN16_SIZE) |
ab50adb6 MR |
7273 | { |
7274 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status); | |
7275 | if (status) | |
7276 | return 0; | |
7277 | } | |
7278 | ||
7279 | return micromips_instruction_has_delay_slot (insn, mustbe32); | |
7280 | } | |
c8cef75f | 7281 | |
ab50adb6 MR |
7282 | /* Return non-zero if the MIPS16 instruction INST, which must be |
7283 | a 32-bit instruction if MUSTBE32 is set or can be any instruction | |
7284 | otherwise, has a branch delay slot (i.e. it is a non-compact jump | |
7285 | instruction). This function is based on mips16_next_pc. */ | |
7286 | ||
7287 | static int | |
7288 | mips16_instruction_has_delay_slot (unsigned short inst, int mustbe32) | |
7289 | { | |
ae790652 MR |
7290 | if ((inst & 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */ |
7291 | return !mustbe32; | |
c8cef75f MR |
7292 | return (inst & 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */ |
7293 | } | |
7294 | ||
ab50adb6 MR |
7295 | /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay |
7296 | slot (i.e. it is a non-compact jump instruction). The instruction | |
7297 | must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */ | |
7298 | ||
7299 | static int | |
7300 | mips16_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, | |
7301 | CORE_ADDR addr, int mustbe32) | |
7302 | { | |
7303 | unsigned short insn; | |
7304 | int status; | |
7305 | ||
7306 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS16, addr, &status); | |
7307 | if (status) | |
7308 | return 0; | |
7309 | ||
7310 | return mips16_instruction_has_delay_slot (insn, mustbe32); | |
7311 | } | |
7312 | ||
c8cef75f MR |
7313 | /* Calculate the starting address of the MIPS memory segment BPADDR is in. |
7314 | This assumes KSSEG exists. */ | |
7315 | ||
7316 | static CORE_ADDR | |
7317 | mips_segment_boundary (CORE_ADDR bpaddr) | |
7318 | { | |
7319 | CORE_ADDR mask = CORE_ADDR_MAX; | |
7320 | int segsize; | |
7321 | ||
7322 | if (sizeof (CORE_ADDR) == 8) | |
7323 | /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid | |
7324 | a compiler warning produced where CORE_ADDR is a 32-bit type even | |
7325 | though in that case this is dead code). */ | |
7326 | switch (bpaddr >> ((sizeof (CORE_ADDR) << 3) - 2) & 3) | |
7327 | { | |
7328 | case 3: | |
7329 | if (bpaddr == (bfd_signed_vma) (int32_t) bpaddr) | |
7330 | segsize = 29; /* 32-bit compatibility segment */ | |
7331 | else | |
7332 | segsize = 62; /* xkseg */ | |
7333 | break; | |
7334 | case 2: /* xkphys */ | |
7335 | segsize = 59; | |
7336 | break; | |
7337 | default: /* xksseg (1), xkuseg/kuseg (0) */ | |
7338 | segsize = 62; | |
7339 | break; | |
7340 | } | |
7341 | else if (bpaddr & 0x80000000) /* kernel segment */ | |
7342 | segsize = 29; | |
7343 | else | |
7344 | segsize = 31; /* user segment */ | |
7345 | mask <<= segsize; | |
7346 | return bpaddr & mask; | |
7347 | } | |
7348 | ||
7349 | /* Move the breakpoint at BPADDR out of any branch delay slot by shifting | |
7350 | it backwards if necessary. Return the address of the new location. */ | |
7351 | ||
7352 | static CORE_ADDR | |
7353 | mips_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) | |
7354 | { | |
22e048c9 | 7355 | CORE_ADDR prev_addr; |
c8cef75f MR |
7356 | CORE_ADDR boundary; |
7357 | CORE_ADDR func_addr; | |
7358 | ||
7359 | /* If a breakpoint is set on the instruction in a branch delay slot, | |
7360 | GDB gets confused. When the breakpoint is hit, the PC isn't on | |
7361 | the instruction in the branch delay slot, the PC will point to | |
7362 | the branch instruction. Since the PC doesn't match any known | |
7363 | breakpoints, GDB reports a trap exception. | |
7364 | ||
7365 | There are two possible fixes for this problem. | |
7366 | ||
7367 | 1) When the breakpoint gets hit, see if the BD bit is set in the | |
7368 | Cause register (which indicates the last exception occurred in a | |
7369 | branch delay slot). If the BD bit is set, fix the PC to point to | |
7370 | the instruction in the branch delay slot. | |
7371 | ||
7372 | 2) When the user sets the breakpoint, don't allow him to set the | |
7373 | breakpoint on the instruction in the branch delay slot. Instead | |
7374 | move the breakpoint to the branch instruction (which will have | |
7375 | the same result). | |
7376 | ||
7377 | The problem with the first solution is that if the user then | |
7378 | single-steps the processor, the branch instruction will get | |
7379 | skipped (since GDB thinks the PC is on the instruction in the | |
7380 | branch delay slot). | |
7381 | ||
7382 | So, we'll use the second solution. To do this we need to know if | |
7383 | the instruction we're trying to set the breakpoint on is in the | |
7384 | branch delay slot. */ | |
7385 | ||
7386 | boundary = mips_segment_boundary (bpaddr); | |
7387 | ||
7388 | /* Make sure we don't scan back before the beginning of the current | |
7389 | function, since we may fetch constant data or insns that look like | |
7390 | a jump. Of course we might do that anyway if the compiler has | |
7391 | moved constants inline. :-( */ | |
7392 | if (find_pc_partial_function (bpaddr, NULL, &func_addr, NULL) | |
7393 | && func_addr > boundary && func_addr <= bpaddr) | |
7394 | boundary = func_addr; | |
7395 | ||
4cc0665f | 7396 | if (mips_pc_is_mips (bpaddr)) |
c8cef75f MR |
7397 | { |
7398 | if (bpaddr == boundary) | |
7399 | return bpaddr; | |
7400 | ||
7401 | /* If the previous instruction has a branch delay slot, we have | |
7402 | to move the breakpoint to the branch instruction. */ | |
7403 | prev_addr = bpaddr - 4; | |
ab50adb6 | 7404 | if (mips32_insn_at_pc_has_delay_slot (gdbarch, prev_addr)) |
c8cef75f MR |
7405 | bpaddr = prev_addr; |
7406 | } | |
7407 | else | |
7408 | { | |
ab50adb6 | 7409 | int (*insn_at_pc_has_delay_slot) (struct gdbarch *, CORE_ADDR, int); |
c8cef75f MR |
7410 | CORE_ADDR addr, jmpaddr; |
7411 | int i; | |
7412 | ||
4cc0665f | 7413 | boundary = unmake_compact_addr (boundary); |
c8cef75f MR |
7414 | |
7415 | /* The only MIPS16 instructions with delay slots are JAL, JALX, | |
7416 | JALR and JR. An absolute JAL/JALX is always 4 bytes long, | |
7417 | so try for that first, then try the 2 byte JALR/JR. | |
4cc0665f MR |
7418 | The microMIPS ASE has a whole range of jumps and branches |
7419 | with delay slots, some of which take 4 bytes and some take | |
7420 | 2 bytes, so the idea is the same. | |
c8cef75f MR |
7421 | FIXME: We have to assume that bpaddr is not the second half |
7422 | of an extended instruction. */ | |
ab50adb6 MR |
7423 | insn_at_pc_has_delay_slot = (mips_pc_is_micromips (gdbarch, bpaddr) |
7424 | ? micromips_insn_at_pc_has_delay_slot | |
7425 | : mips16_insn_at_pc_has_delay_slot); | |
c8cef75f MR |
7426 | |
7427 | jmpaddr = 0; | |
7428 | addr = bpaddr; | |
7429 | for (i = 1; i < 4; i++) | |
7430 | { | |
4cc0665f | 7431 | if (unmake_compact_addr (addr) == boundary) |
c8cef75f | 7432 | break; |
4cc0665f | 7433 | addr -= MIPS_INSN16_SIZE; |
ab50adb6 | 7434 | if (i == 1 && insn_at_pc_has_delay_slot (gdbarch, addr, 0)) |
c8cef75f MR |
7435 | /* Looks like a JR/JALR at [target-1], but it could be |
7436 | the second word of a previous JAL/JALX, so record it | |
7437 | and check back one more. */ | |
7438 | jmpaddr = addr; | |
ab50adb6 | 7439 | else if (i > 1 && insn_at_pc_has_delay_slot (gdbarch, addr, 1)) |
c8cef75f MR |
7440 | { |
7441 | if (i == 2) | |
7442 | /* Looks like a JAL/JALX at [target-2], but it could also | |
7443 | be the second word of a previous JAL/JALX, record it, | |
7444 | and check back one more. */ | |
7445 | jmpaddr = addr; | |
7446 | else | |
7447 | /* Looks like a JAL/JALX at [target-3], so any previously | |
7448 | recorded JAL/JALX or JR/JALR must be wrong, because: | |
7449 | ||
7450 | >-3: JAL | |
7451 | -2: JAL-ext (can't be JAL/JALX) | |
7452 | -1: bdslot (can't be JR/JALR) | |
7453 | 0: target insn | |
7454 | ||
7455 | Of course it could be another JAL-ext which looks | |
7456 | like a JAL, but in that case we'd have broken out | |
7457 | of this loop at [target-2]: | |
7458 | ||
7459 | -4: JAL | |
7460 | >-3: JAL-ext | |
7461 | -2: bdslot (can't be jmp) | |
7462 | -1: JR/JALR | |
7463 | 0: target insn */ | |
7464 | jmpaddr = 0; | |
7465 | } | |
7466 | else | |
7467 | { | |
7468 | /* Not a jump instruction: if we're at [target-1] this | |
7469 | could be the second word of a JAL/JALX, so continue; | |
7470 | otherwise we're done. */ | |
7471 | if (i > 1) | |
7472 | break; | |
7473 | } | |
7474 | } | |
7475 | ||
7476 | if (jmpaddr) | |
7477 | bpaddr = jmpaddr; | |
7478 | } | |
7479 | ||
7480 | return bpaddr; | |
7481 | } | |
7482 | ||
14132e89 MR |
7483 | /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16 |
7484 | call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */ | |
7485 | ||
7486 | static int | |
7487 | mips_is_stub_suffix (const char *suffix, int zero) | |
7488 | { | |
7489 | switch (suffix[0]) | |
7490 | { | |
7491 | case '0': | |
7492 | return zero && suffix[1] == '\0'; | |
7493 | case '1': | |
7494 | return suffix[1] == '\0' || (suffix[1] == '0' && suffix[2] == '\0'); | |
7495 | case '2': | |
7496 | case '5': | |
7497 | case '6': | |
7498 | case '9': | |
7499 | return suffix[1] == '\0'; | |
7500 | default: | |
7501 | return 0; | |
7502 | } | |
7503 | } | |
7504 | ||
7505 | /* Return non-zero if MODE is one of the mode infixes used for MIPS16 | |
7506 | call stubs, one of sf, df, sc, or dc. */ | |
7507 | ||
7508 | static int | |
7509 | mips_is_stub_mode (const char *mode) | |
7510 | { | |
7511 | return ((mode[0] == 's' || mode[0] == 'd') | |
7512 | && (mode[1] == 'f' || mode[1] == 'c')); | |
7513 | } | |
7514 | ||
7515 | /* Code at PC is a compiler-generated stub. Such a stub for a function | |
7516 | bar might have a name like __fn_stub_bar, and might look like this: | |
7517 | ||
7518 | mfc1 $4, $f13 | |
7519 | mfc1 $5, $f12 | |
7520 | mfc1 $6, $f15 | |
7521 | mfc1 $7, $f14 | |
7522 | ||
7523 | followed by (or interspersed with): | |
7524 | ||
7525 | j bar | |
7526 | ||
7527 | or: | |
7528 | ||
7529 | lui $25, %hi(bar) | |
7530 | addiu $25, $25, %lo(bar) | |
7531 | jr $25 | |
7532 | ||
7533 | ($1 may be used in old code; for robustness we accept any register) | |
7534 | or, in PIC code: | |
7535 | ||
7536 | lui $28, %hi(_gp_disp) | |
7537 | addiu $28, $28, %lo(_gp_disp) | |
7538 | addu $28, $28, $25 | |
7539 | lw $25, %got(bar) | |
7540 | addiu $25, $25, %lo(bar) | |
7541 | jr $25 | |
7542 | ||
7543 | In the case of a __call_stub_bar stub, the sequence to set up | |
7544 | arguments might look like this: | |
7545 | ||
7546 | mtc1 $4, $f13 | |
7547 | mtc1 $5, $f12 | |
7548 | mtc1 $6, $f15 | |
7549 | mtc1 $7, $f14 | |
7550 | ||
7551 | followed by (or interspersed with) one of the jump sequences above. | |
7552 | ||
7553 | In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead | |
7554 | of J or JR, respectively, followed by: | |
7555 | ||
7556 | mfc1 $2, $f0 | |
7557 | mfc1 $3, $f1 | |
7558 | jr $18 | |
7559 | ||
7560 | We are at the beginning of the stub here, and scan down and extract | |
7561 | the target address from the jump immediate instruction or, if a jump | |
7562 | register instruction is used, from the register referred. Return | |
7563 | the value of PC calculated or 0 if inconclusive. | |
7564 | ||
7565 | The limit on the search is arbitrarily set to 20 instructions. FIXME. */ | |
7566 | ||
7567 | static CORE_ADDR | |
7568 | mips_get_mips16_fn_stub_pc (struct frame_info *frame, CORE_ADDR pc) | |
7569 | { | |
7570 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
7571 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
7572 | int addrreg = MIPS_ZERO_REGNUM; | |
7573 | CORE_ADDR start_pc = pc; | |
7574 | CORE_ADDR target_pc = 0; | |
7575 | CORE_ADDR addr = 0; | |
7576 | CORE_ADDR gp = 0; | |
7577 | int status = 0; | |
7578 | int i; | |
7579 | ||
7580 | for (i = 0; | |
7581 | status == 0 && target_pc == 0 && i < 20; | |
7582 | i++, pc += MIPS_INSN32_SIZE) | |
7583 | { | |
4cc0665f | 7584 | ULONGEST inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
14132e89 MR |
7585 | CORE_ADDR imm; |
7586 | int rt; | |
7587 | int rs; | |
7588 | int rd; | |
7589 | ||
7590 | switch (itype_op (inst)) | |
7591 | { | |
7592 | case 0: /* SPECIAL */ | |
7593 | switch (rtype_funct (inst)) | |
7594 | { | |
7595 | case 8: /* JR */ | |
7596 | case 9: /* JALR */ | |
7597 | rs = rtype_rs (inst); | |
7598 | if (rs == MIPS_GP_REGNUM) | |
7599 | target_pc = gp; /* Hmm... */ | |
7600 | else if (rs == addrreg) | |
7601 | target_pc = addr; | |
7602 | break; | |
7603 | ||
7604 | case 0x21: /* ADDU */ | |
7605 | rt = rtype_rt (inst); | |
7606 | rs = rtype_rs (inst); | |
7607 | rd = rtype_rd (inst); | |
7608 | if (rd == MIPS_GP_REGNUM | |
7609 | && ((rs == MIPS_GP_REGNUM && rt == MIPS_T9_REGNUM) | |
7610 | || (rs == MIPS_T9_REGNUM && rt == MIPS_GP_REGNUM))) | |
7611 | gp += start_pc; | |
7612 | break; | |
7613 | } | |
7614 | break; | |
7615 | ||
7616 | case 2: /* J */ | |
7617 | case 3: /* JAL */ | |
7618 | target_pc = jtype_target (inst) << 2; | |
7619 | target_pc += ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); | |
7620 | break; | |
7621 | ||
7622 | case 9: /* ADDIU */ | |
7623 | rt = itype_rt (inst); | |
7624 | rs = itype_rs (inst); | |
7625 | if (rt == rs) | |
7626 | { | |
7627 | imm = (itype_immediate (inst) ^ 0x8000) - 0x8000; | |
7628 | if (rt == MIPS_GP_REGNUM) | |
7629 | gp += imm; | |
7630 | else if (rt == addrreg) | |
7631 | addr += imm; | |
7632 | } | |
7633 | break; | |
7634 | ||
7635 | case 0xf: /* LUI */ | |
7636 | rt = itype_rt (inst); | |
7637 | imm = ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 16; | |
7638 | if (rt == MIPS_GP_REGNUM) | |
7639 | gp = imm; | |
7640 | else if (rt != MIPS_ZERO_REGNUM) | |
7641 | { | |
7642 | addrreg = rt; | |
7643 | addr = imm; | |
7644 | } | |
7645 | break; | |
7646 | ||
7647 | case 0x23: /* LW */ | |
7648 | rt = itype_rt (inst); | |
7649 | rs = itype_rs (inst); | |
7650 | imm = (itype_immediate (inst) ^ 0x8000) - 0x8000; | |
7651 | if (gp != 0 && rs == MIPS_GP_REGNUM) | |
7652 | { | |
7653 | gdb_byte buf[4]; | |
7654 | ||
7655 | memset (buf, 0, sizeof (buf)); | |
7656 | status = target_read_memory (gp + imm, buf, sizeof (buf)); | |
7657 | addrreg = rt; | |
7658 | addr = extract_signed_integer (buf, sizeof (buf), byte_order); | |
7659 | } | |
7660 | break; | |
7661 | } | |
7662 | } | |
7663 | ||
7664 | return target_pc; | |
7665 | } | |
7666 | ||
7667 | /* If PC is in a MIPS16 call or return stub, return the address of the | |
7668 | target PC, which is either the callee or the caller. There are several | |
c906108c SS |
7669 | cases which must be handled: |
7670 | ||
14132e89 MR |
7671 | * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub |
7672 | and the target PC is in $31 ($ra). | |
c906108c | 7673 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
14132e89 MR |
7674 | and the target PC is in $2. |
7675 | * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10}, | |
7676 | i.e. before the JALR instruction, this is effectively a call stub | |
7677 | and the target PC is in $2. Otherwise this is effectively | |
7678 | a return stub and the target PC is in $18. | |
7679 | * If the PC is at the start of __call_stub_fp_*, i.e. before the | |
7680 | JAL or JALR instruction, this is effectively a call stub and the | |
7681 | target PC is buried in the instruction stream. Otherwise this | |
7682 | is effectively a return stub and the target PC is in $18. | |
7683 | * If the PC is in __call_stub_* or in __fn_stub_*, this is a call | |
7684 | stub and the target PC is buried in the instruction stream. | |
7685 | ||
7686 | See the source code for the stubs in gcc/config/mips/mips16.S, or the | |
7687 | stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the | |
e7d6a6d2 | 7688 | gory details. */ |
c906108c | 7689 | |
757a7cc6 | 7690 | static CORE_ADDR |
db5f024e | 7691 | mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 7692 | { |
e17a4113 | 7693 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 7694 | CORE_ADDR start_addr; |
14132e89 MR |
7695 | const char *name; |
7696 | size_t prefixlen; | |
c906108c SS |
7697 | |
7698 | /* Find the starting address and name of the function containing the PC. */ | |
7699 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
7700 | return 0; | |
7701 | ||
14132e89 MR |
7702 | /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub |
7703 | and the target PC is in $31 ($ra). */ | |
7704 | prefixlen = strlen (mips_str_mips16_ret_stub); | |
7705 | if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0 | |
7706 | && mips_is_stub_mode (name + prefixlen) | |
7707 | && name[prefixlen + 2] == '\0') | |
7708 | return get_frame_register_signed | |
7709 | (frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM); | |
7710 | ||
7711 | /* If the PC is in __mips16_call_stub_*, this is one of the call | |
7712 | call/return stubs. */ | |
7713 | prefixlen = strlen (mips_str_mips16_call_stub); | |
7714 | if (strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0) | |
c906108c SS |
7715 | { |
7716 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
7717 | and the target PC is in $2. */ | |
14132e89 MR |
7718 | if (mips_is_stub_suffix (name + prefixlen, 0)) |
7719 | return get_frame_register_signed | |
7720 | (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); | |
c906108c | 7721 | |
14132e89 MR |
7722 | /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10}, |
7723 | i.e. before the JALR instruction, this is effectively a call stub | |
b021a221 | 7724 | and the target PC is in $2. Otherwise this is effectively |
c5aa993b | 7725 | a return stub and the target PC is in $18. */ |
14132e89 MR |
7726 | else if (mips_is_stub_mode (name + prefixlen) |
7727 | && name[prefixlen + 2] == '_' | |
7728 | && mips_is_stub_suffix (name + prefixlen + 3, 0)) | |
c906108c SS |
7729 | { |
7730 | if (pc == start_addr) | |
14132e89 MR |
7731 | /* This is the 'call' part of a call stub. The return |
7732 | address is in $2. */ | |
7733 | return get_frame_register_signed | |
7734 | (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); | |
c906108c SS |
7735 | else |
7736 | /* This is the 'return' part of a call stub. The return | |
14132e89 MR |
7737 | address is in $18. */ |
7738 | return get_frame_register_signed | |
7739 | (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); | |
c906108c | 7740 | } |
14132e89 MR |
7741 | else |
7742 | return 0; /* Not a stub. */ | |
7743 | } | |
7744 | ||
7745 | /* If the PC is in __call_stub_* or __fn_stub*, this is one of the | |
7746 | compiler-generated call or call/return stubs. */ | |
61012eef GB |
7747 | if (startswith (name, mips_str_fn_stub) |
7748 | || startswith (name, mips_str_call_stub)) | |
14132e89 MR |
7749 | { |
7750 | if (pc == start_addr) | |
7751 | /* This is the 'call' part of a call stub. Call this helper | |
7752 | to scan through this code for interesting instructions | |
7753 | and determine the final PC. */ | |
7754 | return mips_get_mips16_fn_stub_pc (frame, pc); | |
7755 | else | |
7756 | /* This is the 'return' part of a call stub. The return address | |
7757 | is in $18. */ | |
7758 | return get_frame_register_signed | |
7759 | (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); | |
c906108c | 7760 | } |
14132e89 MR |
7761 | |
7762 | return 0; /* Not a stub. */ | |
7763 | } | |
7764 | ||
7765 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
7766 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
7767 | ||
7768 | static int | |
7769 | mips_in_return_stub (struct gdbarch *gdbarch, CORE_ADDR pc, const char *name) | |
7770 | { | |
7771 | CORE_ADDR start_addr; | |
7772 | size_t prefixlen; | |
7773 | ||
7774 | /* Find the starting address of the function containing the PC. */ | |
7775 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
7776 | return 0; | |
7777 | ||
7778 | /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at | |
7779 | the start, i.e. after the JALR instruction, this is effectively | |
7780 | a return stub. */ | |
7781 | prefixlen = strlen (mips_str_mips16_call_stub); | |
7782 | if (pc != start_addr | |
7783 | && strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0 | |
7784 | && mips_is_stub_mode (name + prefixlen) | |
7785 | && name[prefixlen + 2] == '_' | |
7786 | && mips_is_stub_suffix (name + prefixlen + 3, 1)) | |
7787 | return 1; | |
7788 | ||
7789 | /* If the PC is in __call_stub_fp_* but not at the start, i.e. after | |
7790 | the JAL or JALR instruction, this is effectively a return stub. */ | |
7791 | prefixlen = strlen (mips_str_call_fp_stub); | |
7792 | if (pc != start_addr | |
7793 | && strncmp (name, mips_str_call_fp_stub, prefixlen) == 0) | |
7794 | return 1; | |
7795 | ||
7796 | /* Consume the .pic. prefix of any PIC stub, this function must return | |
7797 | true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub | |
7798 | or the call stub path will trigger in handle_inferior_event causing | |
7799 | it to go astray. */ | |
7800 | prefixlen = strlen (mips_str_pic); | |
7801 | if (strncmp (name, mips_str_pic, prefixlen) == 0) | |
7802 | name += prefixlen; | |
7803 | ||
7804 | /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */ | |
7805 | prefixlen = strlen (mips_str_mips16_ret_stub); | |
7806 | if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0 | |
7807 | && mips_is_stub_mode (name + prefixlen) | |
7808 | && name[prefixlen + 2] == '\0') | |
7809 | return 1; | |
7810 | ||
7811 | return 0; /* Not a stub. */ | |
c906108c SS |
7812 | } |
7813 | ||
db5f024e DJ |
7814 | /* If the current PC is the start of a non-PIC-to-PIC stub, return the |
7815 | PC of the stub target. The stub just loads $t9 and jumps to it, | |
7816 | so that $t9 has the correct value at function entry. */ | |
7817 | ||
7818 | static CORE_ADDR | |
7819 | mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
7820 | { | |
e17a4113 UW |
7821 | struct gdbarch *gdbarch = get_frame_arch (frame); |
7822 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
7cbd4a93 | 7823 | struct bound_minimal_symbol msym; |
db5f024e DJ |
7824 | int i; |
7825 | gdb_byte stub_code[16]; | |
7826 | int32_t stub_words[4]; | |
7827 | ||
7828 | /* The stub for foo is named ".pic.foo", and is either two | |
7829 | instructions inserted before foo or a three instruction sequence | |
7830 | which jumps to foo. */ | |
7831 | msym = lookup_minimal_symbol_by_pc (pc); | |
7cbd4a93 | 7832 | if (msym.minsym == NULL |
77e371c0 | 7833 | || BMSYMBOL_VALUE_ADDRESS (msym) != pc |
efd66ac6 | 7834 | || MSYMBOL_LINKAGE_NAME (msym.minsym) == NULL |
61012eef | 7835 | || !startswith (MSYMBOL_LINKAGE_NAME (msym.minsym), ".pic.")) |
db5f024e DJ |
7836 | return 0; |
7837 | ||
7838 | /* A two-instruction header. */ | |
7cbd4a93 | 7839 | if (MSYMBOL_SIZE (msym.minsym) == 8) |
db5f024e DJ |
7840 | return pc + 8; |
7841 | ||
7842 | /* A three-instruction (plus delay slot) trampoline. */ | |
7cbd4a93 | 7843 | if (MSYMBOL_SIZE (msym.minsym) == 16) |
db5f024e DJ |
7844 | { |
7845 | if (target_read_memory (pc, stub_code, 16) != 0) | |
7846 | return 0; | |
7847 | for (i = 0; i < 4; i++) | |
e17a4113 UW |
7848 | stub_words[i] = extract_unsigned_integer (stub_code + i * 4, |
7849 | 4, byte_order); | |
db5f024e DJ |
7850 | |
7851 | /* A stub contains these instructions: | |
7852 | lui t9, %hi(target) | |
7853 | j target | |
7854 | addiu t9, t9, %lo(target) | |
7855 | nop | |
7856 | ||
7857 | This works even for N64, since stubs are only generated with | |
7858 | -msym32. */ | |
7859 | if ((stub_words[0] & 0xffff0000U) == 0x3c190000 | |
7860 | && (stub_words[1] & 0xfc000000U) == 0x08000000 | |
7861 | && (stub_words[2] & 0xffff0000U) == 0x27390000 | |
7862 | && stub_words[3] == 0x00000000) | |
34b192ce MR |
7863 | return ((((stub_words[0] & 0x0000ffff) << 16) |
7864 | + (stub_words[2] & 0x0000ffff)) ^ 0x8000) - 0x8000; | |
db5f024e DJ |
7865 | } |
7866 | ||
7867 | /* Not a recognized stub. */ | |
7868 | return 0; | |
7869 | } | |
7870 | ||
7871 | static CORE_ADDR | |
7872 | mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
7873 | { | |
14132e89 | 7874 | CORE_ADDR requested_pc = pc; |
db5f024e | 7875 | CORE_ADDR target_pc; |
14132e89 MR |
7876 | CORE_ADDR new_pc; |
7877 | ||
7878 | do | |
7879 | { | |
7880 | target_pc = pc; | |
db5f024e | 7881 | |
14132e89 MR |
7882 | new_pc = mips_skip_mips16_trampoline_code (frame, pc); |
7883 | if (new_pc) | |
3e29f34a | 7884 | pc = new_pc; |
db5f024e | 7885 | |
14132e89 MR |
7886 | new_pc = find_solib_trampoline_target (frame, pc); |
7887 | if (new_pc) | |
3e29f34a | 7888 | pc = new_pc; |
db5f024e | 7889 | |
14132e89 MR |
7890 | new_pc = mips_skip_pic_trampoline_code (frame, pc); |
7891 | if (new_pc) | |
3e29f34a | 7892 | pc = new_pc; |
14132e89 MR |
7893 | } |
7894 | while (pc != target_pc); | |
db5f024e | 7895 | |
14132e89 | 7896 | return pc != requested_pc ? pc : 0; |
db5f024e DJ |
7897 | } |
7898 | ||
a4b8ebc8 | 7899 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
f57d151a | 7900 | [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
7901 | |
7902 | static int | |
d3f73121 | 7903 | mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 7904 | { |
a4b8ebc8 | 7905 | int regnum; |
2f38ef89 | 7906 | if (num >= 0 && num < 32) |
a4b8ebc8 | 7907 | regnum = num; |
2f38ef89 | 7908 | else if (num >= 38 && num < 70) |
d3f73121 | 7909 | regnum = num + mips_regnum (gdbarch)->fp0 - 38; |
040b99fd | 7910 | else if (num == 70) |
d3f73121 | 7911 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 7912 | else if (num == 71) |
d3f73121 | 7913 | regnum = mips_regnum (gdbarch)->lo; |
1faeff08 MR |
7914 | else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 72 && num < 78) |
7915 | regnum = num + mips_regnum (gdbarch)->dspacc - 72; | |
2f38ef89 | 7916 | else |
0fde2c53 | 7917 | return -1; |
d3f73121 | 7918 | return gdbarch_num_regs (gdbarch) + regnum; |
88c72b7d AC |
7919 | } |
7920 | ||
2f38ef89 | 7921 | |
a4b8ebc8 | 7922 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
f57d151a | 7923 | gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
7924 | |
7925 | static int | |
d3f73121 | 7926 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 7927 | { |
a4b8ebc8 | 7928 | int regnum; |
2f38ef89 | 7929 | if (num >= 0 && num < 32) |
a4b8ebc8 | 7930 | regnum = num; |
2f38ef89 | 7931 | else if (num >= 32 && num < 64) |
d3f73121 | 7932 | regnum = num + mips_regnum (gdbarch)->fp0 - 32; |
040b99fd | 7933 | else if (num == 64) |
d3f73121 | 7934 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 7935 | else if (num == 65) |
d3f73121 | 7936 | regnum = mips_regnum (gdbarch)->lo; |
1faeff08 MR |
7937 | else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 66 && num < 72) |
7938 | regnum = num + mips_regnum (gdbarch)->dspacc - 66; | |
2f38ef89 | 7939 | else |
0fde2c53 | 7940 | return -1; |
d3f73121 | 7941 | return gdbarch_num_regs (gdbarch) + regnum; |
a4b8ebc8 AC |
7942 | } |
7943 | ||
7944 | static int | |
e7faf938 | 7945 | mips_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
a4b8ebc8 AC |
7946 | { |
7947 | /* Only makes sense to supply raw registers. */ | |
e7faf938 | 7948 | gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)); |
a4b8ebc8 AC |
7949 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to |
7950 | decide if it is valid. Should instead define a standard sim/gdb | |
7951 | register numbering scheme. */ | |
e7faf938 MD |
7952 | if (gdbarch_register_name (gdbarch, |
7953 | gdbarch_num_regs (gdbarch) + regnum) != NULL | |
7954 | && gdbarch_register_name (gdbarch, | |
025bb325 MS |
7955 | gdbarch_num_regs (gdbarch) |
7956 | + regnum)[0] != '\0') | |
a4b8ebc8 AC |
7957 | return regnum; |
7958 | else | |
6d82d43b | 7959 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
7960 | } |
7961 | ||
2f38ef89 | 7962 | |
4844f454 CV |
7963 | /* Convert an integer into an address. Extracting the value signed |
7964 | guarantees a correctly sign extended address. */ | |
fc0c74b1 AC |
7965 | |
7966 | static CORE_ADDR | |
79dd2d24 | 7967 | mips_integer_to_address (struct gdbarch *gdbarch, |
870cd05e | 7968 | struct type *type, const gdb_byte *buf) |
fc0c74b1 | 7969 | { |
e17a4113 UW |
7970 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7971 | return extract_signed_integer (buf, TYPE_LENGTH (type), byte_order); | |
fc0c74b1 AC |
7972 | } |
7973 | ||
82e91389 DJ |
7974 | /* Dummy virtual frame pointer method. This is no more or less accurate |
7975 | than most other architectures; we just need to be explicit about it, | |
7976 | because the pseudo-register gdbarch_sp_regnum will otherwise lead to | |
7977 | an assertion failure. */ | |
7978 | ||
7979 | static void | |
a54fba4c MD |
7980 | mips_virtual_frame_pointer (struct gdbarch *gdbarch, |
7981 | CORE_ADDR pc, int *reg, LONGEST *offset) | |
82e91389 DJ |
7982 | { |
7983 | *reg = MIPS_SP_REGNUM; | |
7984 | *offset = 0; | |
7985 | } | |
7986 | ||
caaa3122 DJ |
7987 | static void |
7988 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
7989 | { | |
7990 | enum mips_abi *abip = (enum mips_abi *) obj; | |
7991 | const char *name = bfd_get_section_name (abfd, sect); | |
7992 | ||
7993 | if (*abip != MIPS_ABI_UNKNOWN) | |
7994 | return; | |
7995 | ||
61012eef | 7996 | if (!startswith (name, ".mdebug.")) |
caaa3122 DJ |
7997 | return; |
7998 | ||
7999 | if (strcmp (name, ".mdebug.abi32") == 0) | |
8000 | *abip = MIPS_ABI_O32; | |
8001 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
8002 | *abip = MIPS_ABI_N32; | |
62a49b2c | 8003 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 8004 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
8005 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
8006 | *abip = MIPS_ABI_O64; | |
8007 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
8008 | *abip = MIPS_ABI_EABI32; | |
8009 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
8010 | *abip = MIPS_ABI_EABI64; | |
8011 | else | |
8a3fe4f8 | 8012 | warning (_("unsupported ABI %s."), name + 8); |
caaa3122 DJ |
8013 | } |
8014 | ||
22e47e37 FF |
8015 | static void |
8016 | mips_find_long_section (bfd *abfd, asection *sect, void *obj) | |
8017 | { | |
8018 | int *lbp = (int *) obj; | |
8019 | const char *name = bfd_get_section_name (abfd, sect); | |
8020 | ||
61012eef | 8021 | if (startswith (name, ".gcc_compiled_long32")) |
22e47e37 | 8022 | *lbp = 32; |
61012eef | 8023 | else if (startswith (name, ".gcc_compiled_long64")) |
22e47e37 | 8024 | *lbp = 64; |
61012eef | 8025 | else if (startswith (name, ".gcc_compiled_long")) |
22e47e37 FF |
8026 | warning (_("unrecognized .gcc_compiled_longXX")); |
8027 | } | |
8028 | ||
2e4ebe70 DJ |
8029 | static enum mips_abi |
8030 | global_mips_abi (void) | |
8031 | { | |
8032 | int i; | |
8033 | ||
8034 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
8035 | if (mips_abi_strings[i] == mips_abi_string) | |
8036 | return (enum mips_abi) i; | |
8037 | ||
e2e0b3e5 | 8038 | internal_error (__FILE__, __LINE__, _("unknown ABI string")); |
2e4ebe70 DJ |
8039 | } |
8040 | ||
4cc0665f MR |
8041 | /* Return the default compressed instruction set, either of MIPS16 |
8042 | or microMIPS, selected when none could have been determined from | |
8043 | the ELF header of the binary being executed (or no binary has been | |
8044 | selected. */ | |
8045 | ||
8046 | static enum mips_isa | |
8047 | global_mips_compression (void) | |
8048 | { | |
8049 | int i; | |
8050 | ||
8051 | for (i = 0; mips_compression_strings[i] != NULL; i++) | |
8052 | if (mips_compression_strings[i] == mips_compression_string) | |
8053 | return (enum mips_isa) i; | |
8054 | ||
8055 | internal_error (__FILE__, __LINE__, _("unknown compressed ISA string")); | |
8056 | } | |
8057 | ||
29709017 DJ |
8058 | static void |
8059 | mips_register_g_packet_guesses (struct gdbarch *gdbarch) | |
8060 | { | |
29709017 DJ |
8061 | /* If the size matches the set of 32-bit or 64-bit integer registers, |
8062 | assume that's what we've got. */ | |
4eb0ad19 DJ |
8063 | register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32); |
8064 | register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64); | |
29709017 DJ |
8065 | |
8066 | /* If the size matches the full set of registers GDB traditionally | |
8067 | knows about, including floating point, for either 32-bit or | |
8068 | 64-bit, assume that's what we've got. */ | |
4eb0ad19 DJ |
8069 | register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32); |
8070 | register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64); | |
29709017 DJ |
8071 | |
8072 | /* Otherwise we don't have a useful guess. */ | |
8073 | } | |
8074 | ||
f8b73d13 DJ |
8075 | static struct value * |
8076 | value_of_mips_user_reg (struct frame_info *frame, const void *baton) | |
8077 | { | |
19ba03f4 | 8078 | const int *reg_p = (const int *) baton; |
f8b73d13 DJ |
8079 | return value_of_register (*reg_p, frame); |
8080 | } | |
8081 | ||
c2d11a7d | 8082 | static struct gdbarch * |
6d82d43b | 8083 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 8084 | { |
c2d11a7d JM |
8085 | struct gdbarch *gdbarch; |
8086 | struct gdbarch_tdep *tdep; | |
8087 | int elf_flags; | |
2e4ebe70 | 8088 | enum mips_abi mips_abi, found_abi, wanted_abi; |
f8b73d13 | 8089 | int i, num_regs; |
8d5838b5 | 8090 | enum mips_fpu_type fpu_type; |
f8b73d13 | 8091 | struct tdesc_arch_data *tdesc_data = NULL; |
d929bc19 | 8092 | int elf_fpu_type = Val_GNU_MIPS_ABI_FP_ANY; |
1faeff08 MR |
8093 | const char **reg_names; |
8094 | struct mips_regnum mips_regnum, *regnum; | |
4cc0665f | 8095 | enum mips_isa mips_isa; |
1faeff08 MR |
8096 | int dspacc; |
8097 | int dspctl; | |
8098 | ||
8099 | /* Fill in the OS dependent register numbers and names. */ | |
de4bfa86 | 8100 | if (info.osabi == GDB_OSABI_LINUX) |
1faeff08 MR |
8101 | { |
8102 | mips_regnum.fp0 = 38; | |
8103 | mips_regnum.pc = 37; | |
8104 | mips_regnum.cause = 36; | |
8105 | mips_regnum.badvaddr = 35; | |
8106 | mips_regnum.hi = 34; | |
8107 | mips_regnum.lo = 33; | |
8108 | mips_regnum.fp_control_status = 70; | |
8109 | mips_regnum.fp_implementation_revision = 71; | |
8110 | mips_regnum.dspacc = -1; | |
8111 | mips_regnum.dspctl = -1; | |
8112 | dspacc = 72; | |
8113 | dspctl = 78; | |
3877922e | 8114 | num_regs = 90; |
1faeff08 MR |
8115 | reg_names = mips_linux_reg_names; |
8116 | } | |
8117 | else | |
8118 | { | |
8119 | mips_regnum.lo = MIPS_EMBED_LO_REGNUM; | |
8120 | mips_regnum.hi = MIPS_EMBED_HI_REGNUM; | |
8121 | mips_regnum.badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
8122 | mips_regnum.cause = MIPS_EMBED_CAUSE_REGNUM; | |
8123 | mips_regnum.pc = MIPS_EMBED_PC_REGNUM; | |
8124 | mips_regnum.fp0 = MIPS_EMBED_FP0_REGNUM; | |
8125 | mips_regnum.fp_control_status = 70; | |
8126 | mips_regnum.fp_implementation_revision = 71; | |
8127 | mips_regnum.dspacc = dspacc = -1; | |
8128 | mips_regnum.dspctl = dspctl = -1; | |
8129 | num_regs = MIPS_LAST_EMBED_REGNUM + 1; | |
8130 | if (info.bfd_arch_info != NULL | |
8131 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
8132 | reg_names = mips_tx39_reg_names; | |
8133 | else | |
8134 | reg_names = mips_generic_reg_names; | |
8135 | } | |
f8b73d13 DJ |
8136 | |
8137 | /* Check any target description for validity. */ | |
8138 | if (tdesc_has_registers (info.target_desc)) | |
8139 | { | |
8140 | static const char *const mips_gprs[] = { | |
8141 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
8142 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
8143 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
8144 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
8145 | }; | |
8146 | static const char *const mips_fprs[] = { | |
8147 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
8148 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
8149 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
8150 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
8151 | }; | |
8152 | ||
8153 | const struct tdesc_feature *feature; | |
8154 | int valid_p; | |
8155 | ||
8156 | feature = tdesc_find_feature (info.target_desc, | |
8157 | "org.gnu.gdb.mips.cpu"); | |
8158 | if (feature == NULL) | |
8159 | return NULL; | |
8160 | ||
8161 | tdesc_data = tdesc_data_alloc (); | |
8162 | ||
8163 | valid_p = 1; | |
8164 | for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) | |
8165 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
8166 | mips_gprs[i]); | |
8167 | ||
8168 | ||
8169 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 8170 | mips_regnum.lo, "lo"); |
f8b73d13 | 8171 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
1faeff08 | 8172 | mips_regnum.hi, "hi"); |
f8b73d13 | 8173 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
1faeff08 | 8174 | mips_regnum.pc, "pc"); |
f8b73d13 DJ |
8175 | |
8176 | if (!valid_p) | |
8177 | { | |
8178 | tdesc_data_cleanup (tdesc_data); | |
8179 | return NULL; | |
8180 | } | |
8181 | ||
8182 | feature = tdesc_find_feature (info.target_desc, | |
8183 | "org.gnu.gdb.mips.cp0"); | |
8184 | if (feature == NULL) | |
8185 | { | |
8186 | tdesc_data_cleanup (tdesc_data); | |
8187 | return NULL; | |
8188 | } | |
8189 | ||
8190 | valid_p = 1; | |
8191 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 8192 | mips_regnum.badvaddr, "badvaddr"); |
f8b73d13 DJ |
8193 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
8194 | MIPS_PS_REGNUM, "status"); | |
8195 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 8196 | mips_regnum.cause, "cause"); |
f8b73d13 DJ |
8197 | |
8198 | if (!valid_p) | |
8199 | { | |
8200 | tdesc_data_cleanup (tdesc_data); | |
8201 | return NULL; | |
8202 | } | |
8203 | ||
8204 | /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS | |
8205 | backend is not prepared for that, though. */ | |
8206 | feature = tdesc_find_feature (info.target_desc, | |
8207 | "org.gnu.gdb.mips.fpu"); | |
8208 | if (feature == NULL) | |
8209 | { | |
8210 | tdesc_data_cleanup (tdesc_data); | |
8211 | return NULL; | |
8212 | } | |
8213 | ||
8214 | valid_p = 1; | |
8215 | for (i = 0; i < 32; i++) | |
8216 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 8217 | i + mips_regnum.fp0, mips_fprs[i]); |
f8b73d13 DJ |
8218 | |
8219 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 MR |
8220 | mips_regnum.fp_control_status, |
8221 | "fcsr"); | |
8222 | valid_p | |
8223 | &= tdesc_numbered_register (feature, tdesc_data, | |
8224 | mips_regnum.fp_implementation_revision, | |
8225 | "fir"); | |
f8b73d13 DJ |
8226 | |
8227 | if (!valid_p) | |
8228 | { | |
8229 | tdesc_data_cleanup (tdesc_data); | |
8230 | return NULL; | |
8231 | } | |
8232 | ||
3877922e MR |
8233 | num_regs = mips_regnum.fp_implementation_revision + 1; |
8234 | ||
1faeff08 MR |
8235 | if (dspacc >= 0) |
8236 | { | |
8237 | feature = tdesc_find_feature (info.target_desc, | |
8238 | "org.gnu.gdb.mips.dsp"); | |
8239 | /* The DSP registers are optional; it's OK if they are absent. */ | |
8240 | if (feature != NULL) | |
8241 | { | |
8242 | i = 0; | |
8243 | valid_p = 1; | |
8244 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8245 | dspacc + i++, "hi1"); | |
8246 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8247 | dspacc + i++, "lo1"); | |
8248 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8249 | dspacc + i++, "hi2"); | |
8250 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8251 | dspacc + i++, "lo2"); | |
8252 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8253 | dspacc + i++, "hi3"); | |
8254 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8255 | dspacc + i++, "lo3"); | |
8256 | ||
8257 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8258 | dspctl, "dspctl"); | |
8259 | ||
8260 | if (!valid_p) | |
8261 | { | |
8262 | tdesc_data_cleanup (tdesc_data); | |
8263 | return NULL; | |
8264 | } | |
8265 | ||
8266 | mips_regnum.dspacc = dspacc; | |
8267 | mips_regnum.dspctl = dspctl; | |
3877922e MR |
8268 | |
8269 | num_regs = mips_regnum.dspctl + 1; | |
1faeff08 MR |
8270 | } |
8271 | } | |
8272 | ||
f8b73d13 DJ |
8273 | /* It would be nice to detect an attempt to use a 64-bit ABI |
8274 | when only 32-bit registers are provided. */ | |
1faeff08 | 8275 | reg_names = NULL; |
f8b73d13 | 8276 | } |
c2d11a7d | 8277 | |
ec03c1ac AC |
8278 | /* First of all, extract the elf_flags, if available. */ |
8279 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
8280 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
8281 | else if (arches != NULL) |
8282 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
8283 | else |
8284 | elf_flags = 0; | |
8285 | if (gdbarch_debug) | |
8286 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 8287 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 8288 | |
102182a9 | 8289 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
8290 | switch ((elf_flags & EF_MIPS_ABI)) |
8291 | { | |
8292 | case E_MIPS_ABI_O32: | |
ec03c1ac | 8293 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
8294 | break; |
8295 | case E_MIPS_ABI_O64: | |
ec03c1ac | 8296 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
8297 | break; |
8298 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 8299 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
8300 | break; |
8301 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 8302 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
8303 | break; |
8304 | default: | |
acdb74a0 | 8305 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 8306 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 8307 | else |
ec03c1ac | 8308 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
8309 | break; |
8310 | } | |
acdb74a0 | 8311 | |
caaa3122 | 8312 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
8313 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
8314 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 8315 | |
dc305454 | 8316 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
8317 | MIPS architecture (if there is one). */ |
8318 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
8319 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 8320 | |
32a6503c | 8321 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 8322 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
8323 | && info.bfd_arch_info != NULL |
8324 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
8325 | { | |
8326 | switch (info.bfd_arch_info->mach) | |
8327 | { | |
8328 | case bfd_mach_mips3900: | |
ec03c1ac | 8329 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
8330 | break; |
8331 | case bfd_mach_mips4100: | |
8332 | case bfd_mach_mips5000: | |
ec03c1ac | 8333 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 8334 | break; |
1d06468c EZ |
8335 | case bfd_mach_mips8000: |
8336 | case bfd_mach_mips10000: | |
32a6503c KB |
8337 | /* On Irix, ELF64 executables use the N64 ABI. The |
8338 | pseudo-sections which describe the ABI aren't present | |
8339 | on IRIX. (Even for executables created by gcc.) */ | |
e6c2f47b PA |
8340 | if (info.abfd != NULL |
8341 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
28d169de | 8342 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) |
ec03c1ac | 8343 | found_abi = MIPS_ABI_N64; |
28d169de | 8344 | else |
ec03c1ac | 8345 | found_abi = MIPS_ABI_N32; |
1d06468c | 8346 | break; |
bf64bfd6 AC |
8347 | } |
8348 | } | |
2e4ebe70 | 8349 | |
26c53e50 DJ |
8350 | /* Default 64-bit objects to N64 instead of O32. */ |
8351 | if (found_abi == MIPS_ABI_UNKNOWN | |
8352 | && info.abfd != NULL | |
8353 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
8354 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
8355 | found_abi = MIPS_ABI_N64; | |
8356 | ||
ec03c1ac AC |
8357 | if (gdbarch_debug) |
8358 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
8359 | found_abi); | |
8360 | ||
8361 | /* What has the user specified from the command line? */ | |
8362 | wanted_abi = global_mips_abi (); | |
8363 | if (gdbarch_debug) | |
8364 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
8365 | wanted_abi); | |
2e4ebe70 DJ |
8366 | |
8367 | /* Now that we have found what the ABI for this binary would be, | |
8368 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
8369 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
8370 | mips_abi = wanted_abi; | |
ec03c1ac AC |
8371 | else if (found_abi != MIPS_ABI_UNKNOWN) |
8372 | mips_abi = found_abi; | |
8373 | else | |
8374 | mips_abi = MIPS_ABI_O32; | |
8375 | if (gdbarch_debug) | |
8376 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
8377 | mips_abi); | |
2e4ebe70 | 8378 | |
4cc0665f MR |
8379 | /* Determine the default compressed ISA. */ |
8380 | if ((elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0 | |
8381 | && (elf_flags & EF_MIPS_ARCH_ASE_M16) == 0) | |
8382 | mips_isa = ISA_MICROMIPS; | |
8383 | else if ((elf_flags & EF_MIPS_ARCH_ASE_M16) != 0 | |
8384 | && (elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) == 0) | |
8385 | mips_isa = ISA_MIPS16; | |
8386 | else | |
8387 | mips_isa = global_mips_compression (); | |
8388 | mips_compression_string = mips_compression_strings[mips_isa]; | |
8389 | ||
ec03c1ac | 8390 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 8391 | if (gdbarch_debug) |
ec03c1ac | 8392 | fprintf_unfiltered (gdb_stdlog, |
025bb325 MS |
8393 | "mips_gdbarch_init: " |
8394 | "mips64_transfers_32bit_regs_p = %d\n", | |
ec03c1ac | 8395 | mips64_transfers_32bit_regs_p); |
0dadbba0 | 8396 | |
8d5838b5 | 8397 | /* Determine the MIPS FPU type. */ |
609ca2b9 DJ |
8398 | #ifdef HAVE_ELF |
8399 | if (info.abfd | |
8400 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
8401 | elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
8402 | Tag_GNU_MIPS_ABI_FP); | |
8403 | #endif /* HAVE_ELF */ | |
8404 | ||
8d5838b5 AC |
8405 | if (!mips_fpu_type_auto) |
8406 | fpu_type = mips_fpu_type; | |
d929bc19 | 8407 | else if (elf_fpu_type != Val_GNU_MIPS_ABI_FP_ANY) |
609ca2b9 DJ |
8408 | { |
8409 | switch (elf_fpu_type) | |
8410 | { | |
d929bc19 | 8411 | case Val_GNU_MIPS_ABI_FP_DOUBLE: |
609ca2b9 DJ |
8412 | fpu_type = MIPS_FPU_DOUBLE; |
8413 | break; | |
d929bc19 | 8414 | case Val_GNU_MIPS_ABI_FP_SINGLE: |
609ca2b9 DJ |
8415 | fpu_type = MIPS_FPU_SINGLE; |
8416 | break; | |
d929bc19 | 8417 | case Val_GNU_MIPS_ABI_FP_SOFT: |
609ca2b9 DJ |
8418 | default: |
8419 | /* Soft float or unknown. */ | |
8420 | fpu_type = MIPS_FPU_NONE; | |
8421 | break; | |
8422 | } | |
8423 | } | |
8d5838b5 AC |
8424 | else if (info.bfd_arch_info != NULL |
8425 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
8426 | switch (info.bfd_arch_info->mach) | |
8427 | { | |
8428 | case bfd_mach_mips3900: | |
8429 | case bfd_mach_mips4100: | |
8430 | case bfd_mach_mips4111: | |
a9d61c86 | 8431 | case bfd_mach_mips4120: |
8d5838b5 AC |
8432 | fpu_type = MIPS_FPU_NONE; |
8433 | break; | |
8434 | case bfd_mach_mips4650: | |
8435 | fpu_type = MIPS_FPU_SINGLE; | |
8436 | break; | |
8437 | default: | |
8438 | fpu_type = MIPS_FPU_DOUBLE; | |
8439 | break; | |
8440 | } | |
8441 | else if (arches != NULL) | |
8442 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
8443 | else | |
8444 | fpu_type = MIPS_FPU_DOUBLE; | |
8445 | if (gdbarch_debug) | |
8446 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 8447 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 8448 | |
29709017 DJ |
8449 | /* Check for blatant incompatibilities. */ |
8450 | ||
8451 | /* If we have only 32-bit registers, then we can't debug a 64-bit | |
8452 | ABI. */ | |
8453 | if (info.target_desc | |
8454 | && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL | |
8455 | && mips_abi != MIPS_ABI_EABI32 | |
8456 | && mips_abi != MIPS_ABI_O32) | |
f8b73d13 DJ |
8457 | { |
8458 | if (tdesc_data != NULL) | |
8459 | tdesc_data_cleanup (tdesc_data); | |
8460 | return NULL; | |
8461 | } | |
29709017 | 8462 | |
025bb325 | 8463 | /* Try to find a pre-existing architecture. */ |
c2d11a7d JM |
8464 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
8465 | arches != NULL; | |
8466 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
8467 | { | |
d54398a7 MR |
8468 | /* MIPS needs to be pedantic about which ABI and the compressed |
8469 | ISA variation the object is using. */ | |
9103eae0 | 8470 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 8471 | continue; |
9103eae0 | 8472 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 8473 | continue; |
d54398a7 MR |
8474 | if (gdbarch_tdep (arches->gdbarch)->mips_isa != mips_isa) |
8475 | continue; | |
719ec221 AC |
8476 | /* Need to be pedantic about which register virtual size is |
8477 | used. */ | |
8478 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
8479 | != mips64_transfers_32bit_regs_p) | |
8480 | continue; | |
8d5838b5 AC |
8481 | /* Be pedantic about which FPU is selected. */ |
8482 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
8483 | continue; | |
f8b73d13 DJ |
8484 | |
8485 | if (tdesc_data != NULL) | |
8486 | tdesc_data_cleanup (tdesc_data); | |
4be87837 | 8487 | return arches->gdbarch; |
c2d11a7d JM |
8488 | } |
8489 | ||
102182a9 | 8490 | /* Need a new architecture. Fill in a target specific vector. */ |
8d749320 | 8491 | tdep = XNEW (struct gdbarch_tdep); |
c2d11a7d JM |
8492 | gdbarch = gdbarch_alloc (&info, tdep); |
8493 | tdep->elf_flags = elf_flags; | |
719ec221 | 8494 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
8495 | tdep->found_abi = found_abi; |
8496 | tdep->mips_abi = mips_abi; | |
4cc0665f | 8497 | tdep->mips_isa = mips_isa; |
8d5838b5 | 8498 | tdep->mips_fpu_type = fpu_type; |
29709017 DJ |
8499 | tdep->register_size_valid_p = 0; |
8500 | tdep->register_size = 0; | |
8501 | ||
8502 | if (info.target_desc) | |
8503 | { | |
8504 | /* Some useful properties can be inferred from the target. */ | |
8505 | if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) | |
8506 | { | |
8507 | tdep->register_size_valid_p = 1; | |
8508 | tdep->register_size = 4; | |
8509 | } | |
8510 | else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) | |
8511 | { | |
8512 | tdep->register_size_valid_p = 1; | |
8513 | tdep->register_size = 8; | |
8514 | } | |
8515 | } | |
c2d11a7d | 8516 | |
102182a9 | 8517 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
8518 | set_gdbarch_short_bit (gdbarch, 16); |
8519 | set_gdbarch_int_bit (gdbarch, 32); | |
8520 | set_gdbarch_float_bit (gdbarch, 32); | |
8521 | set_gdbarch_double_bit (gdbarch, 64); | |
8522 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
8523 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
8524 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
8525 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 8526 | |
175ff332 HZ |
8527 | set_gdbarch_ax_pseudo_register_collect (gdbarch, |
8528 | mips_ax_pseudo_register_collect); | |
8529 | set_gdbarch_ax_pseudo_register_push_stack | |
8530 | (gdbarch, mips_ax_pseudo_register_push_stack); | |
8531 | ||
6d82d43b | 8532 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 | 8533 | mips_elf_make_msymbol_special); |
3e29f34a MR |
8534 | set_gdbarch_make_symbol_special (gdbarch, mips_make_symbol_special); |
8535 | set_gdbarch_adjust_dwarf2_addr (gdbarch, mips_adjust_dwarf2_addr); | |
8536 | set_gdbarch_adjust_dwarf2_line (gdbarch, mips_adjust_dwarf2_line); | |
f7ab6ec6 | 8537 | |
1faeff08 MR |
8538 | regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, struct mips_regnum); |
8539 | *regnum = mips_regnum; | |
1faeff08 MR |
8540 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
8541 | set_gdbarch_num_regs (gdbarch, num_regs); | |
8542 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
8543 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
8544 | set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer); | |
8545 | tdep->mips_processor_reg_names = reg_names; | |
8546 | tdep->regnum = regnum; | |
fe29b929 | 8547 | |
0dadbba0 | 8548 | switch (mips_abi) |
c2d11a7d | 8549 | { |
0dadbba0 | 8550 | case MIPS_ABI_O32: |
25ab4790 | 8551 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 8552 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
4c7d22cb | 8553 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 8554 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 8555 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8556 | set_gdbarch_long_bit (gdbarch, 32); |
8557 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8558 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8559 | break; | |
0dadbba0 | 8560 | case MIPS_ABI_O64: |
25ab4790 | 8561 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
9c8fdbfa | 8562 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
4c7d22cb | 8563 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 8564 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 8565 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8566 | set_gdbarch_long_bit (gdbarch, 32); |
8567 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8568 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8569 | break; | |
0dadbba0 | 8570 | case MIPS_ABI_EABI32: |
25ab4790 | 8571 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 8572 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 8573 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8574 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 8575 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8576 | set_gdbarch_long_bit (gdbarch, 32); |
8577 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8578 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8579 | break; | |
0dadbba0 | 8580 | case MIPS_ABI_EABI64: |
25ab4790 | 8581 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 8582 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 8583 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8584 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 8585 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8586 | set_gdbarch_long_bit (gdbarch, 64); |
8587 | set_gdbarch_ptr_bit (gdbarch, 64); | |
8588 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8589 | break; | |
0dadbba0 | 8590 | case MIPS_ABI_N32: |
25ab4790 | 8591 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 8592 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 8593 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8594 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 8595 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
8596 | set_gdbarch_long_bit (gdbarch, 32); |
8597 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8598 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 8599 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 8600 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
28d169de KB |
8601 | break; |
8602 | case MIPS_ABI_N64: | |
25ab4790 | 8603 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 8604 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 8605 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8606 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
8607 | tdep->default_mask_address_p = 0; |
8608 | set_gdbarch_long_bit (gdbarch, 64); | |
8609 | set_gdbarch_ptr_bit (gdbarch, 64); | |
8610 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 8611 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 8612 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
0dadbba0 | 8613 | break; |
c2d11a7d | 8614 | default: |
e2e0b3e5 | 8615 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); |
c2d11a7d JM |
8616 | } |
8617 | ||
22e47e37 FF |
8618 | /* GCC creates a pseudo-section whose name specifies the size of |
8619 | longs, since -mlong32 or -mlong64 may be used independent of | |
8620 | other options. How those options affect pointer sizes is ABI and | |
8621 | architecture dependent, so use them to override the default sizes | |
8622 | set by the ABI. This table shows the relationship between ABI, | |
8623 | -mlongXX, and size of pointers: | |
8624 | ||
8625 | ABI -mlongXX ptr bits | |
8626 | --- -------- -------- | |
8627 | o32 32 32 | |
8628 | o32 64 32 | |
8629 | n32 32 32 | |
8630 | n32 64 64 | |
8631 | o64 32 32 | |
8632 | o64 64 64 | |
8633 | n64 32 32 | |
8634 | n64 64 64 | |
8635 | eabi32 32 32 | |
8636 | eabi32 64 32 | |
8637 | eabi64 32 32 | |
8638 | eabi64 64 64 | |
8639 | ||
8640 | Note that for o32 and eabi32, pointers are always 32 bits | |
8641 | regardless of any -mlongXX option. For all others, pointers and | |
025bb325 | 8642 | longs are the same, as set by -mlongXX or set by defaults. */ |
22e47e37 FF |
8643 | |
8644 | if (info.abfd != NULL) | |
8645 | { | |
8646 | int long_bit = 0; | |
8647 | ||
8648 | bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); | |
8649 | if (long_bit) | |
8650 | { | |
8651 | set_gdbarch_long_bit (gdbarch, long_bit); | |
8652 | switch (mips_abi) | |
8653 | { | |
8654 | case MIPS_ABI_O32: | |
8655 | case MIPS_ABI_EABI32: | |
8656 | break; | |
8657 | case MIPS_ABI_N32: | |
8658 | case MIPS_ABI_O64: | |
8659 | case MIPS_ABI_N64: | |
8660 | case MIPS_ABI_EABI64: | |
8661 | set_gdbarch_ptr_bit (gdbarch, long_bit); | |
8662 | break; | |
8663 | default: | |
8664 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); | |
8665 | } | |
8666 | } | |
8667 | } | |
8668 | ||
a5ea2558 AC |
8669 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
8670 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
8671 | comment: | |
8672 | ||
8673 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
8674 | flag in object files because to do so would make it impossible to | |
102182a9 | 8675 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 8676 | unnecessarily restrictive. |
361d1df0 | 8677 | |
a5ea2558 AC |
8678 | We could solve this problem by adding "-gp32" multilibs to gcc, |
8679 | but to set this flag before gcc is built with such multilibs will | |
8680 | break too many systems.'' | |
8681 | ||
8682 | But even more unhelpfully, the default linker output target for | |
8683 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
8684 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 8685 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
8686 | this flag to detect 32-bit mode would do the wrong thing given |
8687 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 8688 | as 32-bit programs by default. */ |
a5ea2558 | 8689 | |
6c997a34 | 8690 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 8691 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
c2d11a7d | 8692 | |
102182a9 MS |
8693 | /* Add/remove bits from an address. The MIPS needs be careful to |
8694 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
8695 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
8696 | ||
58dfe9ff AC |
8697 | /* Unwind the frame. */ |
8698 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
30244cd8 | 8699 | set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); |
b8a22b94 | 8700 | set_gdbarch_dummy_id (gdbarch, mips_dummy_id); |
10312cc4 | 8701 | |
102182a9 | 8702 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 8703 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
8704 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
8705 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
6d82d43b AC |
8706 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, |
8707 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 8708 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 8709 | |
025bb325 | 8710 | /* MIPS version of CALL_DUMMY. */ |
c2d11a7d | 8711 | |
2c76a0c7 JB |
8712 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
8713 | set_gdbarch_push_dummy_code (gdbarch, mips_push_dummy_code); | |
dc604539 | 8714 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 8715 | |
1bab7383 YQ |
8716 | set_gdbarch_print_float_info (gdbarch, mips_print_float_info); |
8717 | ||
87783b8b AC |
8718 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
8719 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
8720 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
8721 | ||
f7b9e9fc | 8722 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
04180708 YQ |
8723 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, mips_breakpoint_kind_from_pc); |
8724 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, mips_sw_breakpoint_from_kind); | |
c8cef75f MR |
8725 | set_gdbarch_adjust_breakpoint_address (gdbarch, |
8726 | mips_adjust_breakpoint_address); | |
f7b9e9fc AC |
8727 | |
8728 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 8729 | |
c9cf6e20 | 8730 | set_gdbarch_stack_frame_destroyed_p (gdbarch, mips_stack_frame_destroyed_p); |
97ab0fdd | 8731 | |
fc0c74b1 AC |
8732 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
8733 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
8734 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 8735 | |
a4b8ebc8 | 8736 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 8737 | |
e11c53d2 | 8738 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 8739 | |
9dae60cc UW |
8740 | if (mips_abi == MIPS_ABI_N32) |
8741 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n32); | |
8742 | else if (mips_abi == MIPS_ABI_N64) | |
8743 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n64); | |
8744 | else | |
8745 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); | |
e5ab0dce | 8746 | |
d92524f1 PM |
8747 | /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint, |
8748 | HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint | |
3a3bc038 | 8749 | need to all be folded into the target vector. Since they are |
d92524f1 PM |
8750 | being used as guards for target_stopped_by_watchpoint, why not have |
8751 | target_stopped_by_watchpoint return the type of watchpoint that the code | |
3a3bc038 AC |
8752 | is sitting on? */ |
8753 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
8754 | ||
e7d6a6d2 | 8755 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
757a7cc6 | 8756 | |
14132e89 MR |
8757 | /* NOTE drow/2012-04-25: We overload the core solib trampoline code |
8758 | to support MIPS16. This is a bad thing. Make sure not to do it | |
8759 | if we have an OS ABI that actually supports shared libraries, since | |
8760 | shared library support is more important. If we have an OS someday | |
8761 | that supports both shared libraries and MIPS16, we'll have to find | |
8762 | a better place for these. | |
8763 | macro/2012-04-25: But that applies to return trampolines only and | |
8764 | currently no MIPS OS ABI uses shared libraries that have them. */ | |
8765 | set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); | |
8766 | ||
025bb325 MS |
8767 | set_gdbarch_single_step_through_delay (gdbarch, |
8768 | mips_single_step_through_delay); | |
3352ef37 | 8769 | |
0d5de010 DJ |
8770 | /* Virtual tables. */ |
8771 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
8772 | ||
29709017 DJ |
8773 | mips_register_g_packet_guesses (gdbarch); |
8774 | ||
6de918a6 | 8775 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
ede5f151 | 8776 | info.tdep_info = tdesc_data; |
6de918a6 | 8777 | gdbarch_init_osabi (info, gdbarch); |
757a7cc6 | 8778 | |
9aac7884 MR |
8779 | /* The hook may have adjusted num_regs, fetch the final value and |
8780 | set pc_regnum and sp_regnum now that it has been fixed. */ | |
9aac7884 MR |
8781 | num_regs = gdbarch_num_regs (gdbarch); |
8782 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); | |
8783 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
8784 | ||
5792a79b | 8785 | /* Unwind the frame. */ |
b8a22b94 DJ |
8786 | dwarf2_append_unwinders (gdbarch); |
8787 | frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind); | |
8788 | frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind); | |
4cc0665f | 8789 | frame_unwind_append_unwinder (gdbarch, &mips_micro_frame_unwind); |
b8a22b94 | 8790 | frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind); |
2bd0c3d7 | 8791 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
eec63939 | 8792 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
45c9dd44 | 8793 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
4cc0665f | 8794 | frame_base_append_sniffer (gdbarch, mips_micro_frame_base_sniffer); |
45c9dd44 | 8795 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); |
5792a79b | 8796 | |
f8b73d13 DJ |
8797 | if (tdesc_data) |
8798 | { | |
8799 | set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); | |
7cc46491 | 8800 | tdesc_use_registers (gdbarch, info.target_desc, tdesc_data); |
f8b73d13 DJ |
8801 | |
8802 | /* Override the normal target description methods to handle our | |
8803 | dual real and pseudo registers. */ | |
8804 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
025bb325 MS |
8805 | set_gdbarch_register_reggroup_p (gdbarch, |
8806 | mips_tdesc_register_reggroup_p); | |
f8b73d13 DJ |
8807 | |
8808 | num_regs = gdbarch_num_regs (gdbarch); | |
8809 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
8810 | set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs); | |
8811 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
8812 | } | |
8813 | ||
8814 | /* Add ABI-specific aliases for the registers. */ | |
8815 | if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) | |
8816 | for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++) | |
8817 | user_reg_add (gdbarch, mips_n32_n64_aliases[i].name, | |
8818 | value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); | |
8819 | else | |
8820 | for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) | |
8821 | user_reg_add (gdbarch, mips_o32_aliases[i].name, | |
8822 | value_of_mips_user_reg, &mips_o32_aliases[i].regnum); | |
8823 | ||
8824 | /* Add some other standard aliases. */ | |
8825 | for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) | |
8826 | user_reg_add (gdbarch, mips_register_aliases[i].name, | |
8827 | value_of_mips_user_reg, &mips_register_aliases[i].regnum); | |
8828 | ||
865093a3 AR |
8829 | for (i = 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++) |
8830 | user_reg_add (gdbarch, mips_numeric_register_aliases[i].name, | |
8831 | value_of_mips_user_reg, | |
8832 | &mips_numeric_register_aliases[i].regnum); | |
8833 | ||
4b9b3959 AC |
8834 | return gdbarch; |
8835 | } | |
8836 | ||
2e4ebe70 | 8837 | static void |
6d82d43b | 8838 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
8839 | { |
8840 | struct gdbarch_info info; | |
8841 | ||
8842 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
8843 | mips_gdbarch_init will take care of the rest. */ | |
8844 | gdbarch_info_init (&info); | |
8845 | gdbarch_update_p (info); | |
8846 | } | |
8847 | ||
ad188201 KB |
8848 | /* Print out which MIPS ABI is in use. */ |
8849 | ||
8850 | static void | |
1f8ca57c JB |
8851 | show_mips_abi (struct ui_file *file, |
8852 | int from_tty, | |
8853 | struct cmd_list_element *ignored_cmd, | |
8854 | const char *ignored_value) | |
ad188201 | 8855 | { |
f5656ead | 8856 | if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips) |
1f8ca57c JB |
8857 | fprintf_filtered |
8858 | (file, | |
8859 | "The MIPS ABI is unknown because the current architecture " | |
8860 | "is not MIPS.\n"); | |
ad188201 KB |
8861 | else |
8862 | { | |
8863 | enum mips_abi global_abi = global_mips_abi (); | |
f5656ead | 8864 | enum mips_abi actual_abi = mips_abi (target_gdbarch ()); |
ad188201 KB |
8865 | const char *actual_abi_str = mips_abi_strings[actual_abi]; |
8866 | ||
8867 | if (global_abi == MIPS_ABI_UNKNOWN) | |
1f8ca57c JB |
8868 | fprintf_filtered |
8869 | (file, | |
8870 | "The MIPS ABI is set automatically (currently \"%s\").\n", | |
6d82d43b | 8871 | actual_abi_str); |
ad188201 | 8872 | else if (global_abi == actual_abi) |
1f8ca57c JB |
8873 | fprintf_filtered |
8874 | (file, | |
8875 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6d82d43b | 8876 | actual_abi_str); |
ad188201 KB |
8877 | else |
8878 | { | |
8879 | /* Probably shouldn't happen... */ | |
025bb325 MS |
8880 | fprintf_filtered (file, |
8881 | "The (auto detected) MIPS ABI \"%s\" is in use " | |
8882 | "even though the user setting was \"%s\".\n", | |
6d82d43b | 8883 | actual_abi_str, mips_abi_strings[global_abi]); |
ad188201 KB |
8884 | } |
8885 | } | |
8886 | } | |
8887 | ||
4cc0665f MR |
8888 | /* Print out which MIPS compressed ISA encoding is used. */ |
8889 | ||
8890 | static void | |
8891 | show_mips_compression (struct ui_file *file, int from_tty, | |
8892 | struct cmd_list_element *c, const char *value) | |
8893 | { | |
8894 | fprintf_filtered (file, _("The compressed ISA encoding used is %s.\n"), | |
8895 | value); | |
8896 | } | |
8897 | ||
4b9b3959 | 8898 | static void |
72a155b4 | 8899 | mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
4b9b3959 | 8900 | { |
72a155b4 | 8901 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4b9b3959 | 8902 | if (tdep != NULL) |
c2d11a7d | 8903 | { |
acdb74a0 AC |
8904 | int ef_mips_arch; |
8905 | int ef_mips_32bitmode; | |
f49e4e6d | 8906 | /* Determine the ISA. */ |
acdb74a0 AC |
8907 | switch (tdep->elf_flags & EF_MIPS_ARCH) |
8908 | { | |
8909 | case E_MIPS_ARCH_1: | |
8910 | ef_mips_arch = 1; | |
8911 | break; | |
8912 | case E_MIPS_ARCH_2: | |
8913 | ef_mips_arch = 2; | |
8914 | break; | |
8915 | case E_MIPS_ARCH_3: | |
8916 | ef_mips_arch = 3; | |
8917 | break; | |
8918 | case E_MIPS_ARCH_4: | |
93d56215 | 8919 | ef_mips_arch = 4; |
acdb74a0 AC |
8920 | break; |
8921 | default: | |
93d56215 | 8922 | ef_mips_arch = 0; |
acdb74a0 AC |
8923 | break; |
8924 | } | |
f49e4e6d | 8925 | /* Determine the size of a pointer. */ |
acdb74a0 | 8926 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); |
4b9b3959 AC |
8927 | fprintf_unfiltered (file, |
8928 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 8929 | tdep->elf_flags); |
4b9b3959 | 8930 | fprintf_unfiltered (file, |
acdb74a0 AC |
8931 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
8932 | ef_mips_32bitmode); | |
8933 | fprintf_unfiltered (file, | |
8934 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
8935 | ef_mips_arch); | |
8936 | fprintf_unfiltered (file, | |
8937 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 8938 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b | 8939 | fprintf_unfiltered (file, |
025bb325 MS |
8940 | "mips_dump_tdep: " |
8941 | "mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 8942 | mips_mask_address_p (tdep), |
4014092b | 8943 | tdep->default_mask_address_p); |
c2d11a7d | 8944 | } |
4b9b3959 AC |
8945 | fprintf_unfiltered (file, |
8946 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
8947 | MIPS_DEFAULT_FPU_TYPE, | |
8948 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
8949 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
8950 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
8951 | : "???")); | |
74ed0bb4 MD |
8952 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", |
8953 | MIPS_EABI (gdbarch)); | |
4b9b3959 AC |
8954 | fprintf_unfiltered (file, |
8955 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
74ed0bb4 MD |
8956 | MIPS_FPU_TYPE (gdbarch), |
8957 | (MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_NONE ? "none" | |
8958 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_SINGLE ? "single" | |
8959 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_DOUBLE ? "double" | |
4b9b3959 | 8960 | : "???")); |
c2d11a7d JM |
8961 | } |
8962 | ||
025bb325 | 8963 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 8964 | |
c906108c | 8965 | void |
acdb74a0 | 8966 | _initialize_mips_tdep (void) |
c906108c SS |
8967 | { |
8968 | static struct cmd_list_element *mipsfpulist = NULL; | |
8969 | struct cmd_list_element *c; | |
8970 | ||
6d82d43b | 8971 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
8972 | if (MIPS_ABI_LAST + 1 |
8973 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
e2e0b3e5 | 8974 | internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync")); |
2e4ebe70 | 8975 | |
4b9b3959 | 8976 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 8977 | |
8d5f9dcb DJ |
8978 | mips_pdr_data = register_objfile_data (); |
8979 | ||
4eb0ad19 DJ |
8980 | /* Create feature sets with the appropriate properties. The values |
8981 | are not important. */ | |
8982 | mips_tdesc_gp32 = allocate_target_description (); | |
8983 | set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, ""); | |
8984 | ||
8985 | mips_tdesc_gp64 = allocate_target_description (); | |
8986 | set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, ""); | |
8987 | ||
025bb325 | 8988 | /* Add root prefix command for all "set mips"/"show mips" commands. */ |
a5ea2558 | 8989 | add_prefix_cmd ("mips", no_class, set_mips_command, |
1bedd215 | 8990 | _("Various MIPS specific commands."), |
a5ea2558 AC |
8991 | &setmipscmdlist, "set mips ", 0, &setlist); |
8992 | ||
8993 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
1bedd215 | 8994 | _("Various MIPS specific commands."), |
a5ea2558 AC |
8995 | &showmipscmdlist, "show mips ", 0, &showlist); |
8996 | ||
025bb325 | 8997 | /* Allow the user to override the ABI. */ |
7ab04401 AC |
8998 | add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, |
8999 | &mips_abi_string, _("\ | |
9000 | Set the MIPS ABI used by this program."), _("\ | |
9001 | Show the MIPS ABI used by this program."), _("\ | |
9002 | This option can be set to one of:\n\ | |
9003 | auto - the default ABI associated with the current binary\n\ | |
9004 | o32\n\ | |
9005 | o64\n\ | |
9006 | n32\n\ | |
9007 | n64\n\ | |
9008 | eabi32\n\ | |
9009 | eabi64"), | |
9010 | mips_abi_update, | |
9011 | show_mips_abi, | |
9012 | &setmipscmdlist, &showmipscmdlist); | |
2e4ebe70 | 9013 | |
4cc0665f MR |
9014 | /* Allow the user to set the ISA to assume for compressed code if ELF |
9015 | file flags don't tell or there is no program file selected. This | |
9016 | setting is updated whenever unambiguous ELF file flags are interpreted, | |
9017 | and carried over to subsequent sessions. */ | |
9018 | add_setshow_enum_cmd ("compression", class_obscure, mips_compression_strings, | |
9019 | &mips_compression_string, _("\ | |
9020 | Set the compressed ISA encoding used by MIPS code."), _("\ | |
9021 | Show the compressed ISA encoding used by MIPS code."), _("\ | |
9022 | Select the compressed ISA encoding used in functions that have no symbol\n\ | |
9023 | information available. The encoding can be set to either of:\n\ | |
9024 | mips16\n\ | |
9025 | micromips\n\ | |
9026 | and is updated automatically from ELF file flags if available."), | |
9027 | mips_abi_update, | |
9028 | show_mips_compression, | |
9029 | &setmipscmdlist, &showmipscmdlist); | |
9030 | ||
c906108c SS |
9031 | /* Let the user turn off floating point and set the fence post for |
9032 | heuristic_proc_start. */ | |
9033 | ||
9034 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
1bedd215 | 9035 | _("Set use of MIPS floating-point coprocessor."), |
c906108c SS |
9036 | &mipsfpulist, "set mipsfpu ", 0, &setlist); |
9037 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
1a966eab | 9038 | _("Select single-precision MIPS floating-point coprocessor."), |
c906108c SS |
9039 | &mipsfpulist); |
9040 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
1a966eab | 9041 | _("Select double-precision MIPS floating-point coprocessor."), |
c906108c SS |
9042 | &mipsfpulist); |
9043 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
9044 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
9045 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
9046 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
1a966eab | 9047 | _("Select no MIPS floating-point coprocessor."), &mipsfpulist); |
c906108c SS |
9048 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
9049 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
9050 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
9051 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
1a966eab | 9052 | _("Select MIPS floating-point coprocessor automatically."), |
c906108c SS |
9053 | &mipsfpulist); |
9054 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
1a966eab | 9055 | _("Show current use of MIPS floating-point coprocessor target."), |
c906108c SS |
9056 | &showlist); |
9057 | ||
c906108c SS |
9058 | /* We really would like to have both "0" and "unlimited" work, but |
9059 | command.c doesn't deal with that. So make it a var_zinteger | |
9060 | because the user can always use "999999" or some such for unlimited. */ | |
6bcadd06 | 9061 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
7915a72c AC |
9062 | &heuristic_fence_post, _("\ |
9063 | Set the distance searched for the start of a function."), _("\ | |
9064 | Show the distance searched for the start of a function."), _("\ | |
c906108c SS |
9065 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
9066 | program for the start of a function. This command sets the distance of the\n\ | |
7915a72c | 9067 | search. The only need to set it is when debugging a stripped executable."), |
2c5b56ce | 9068 | reinit_frame_cache_sfunc, |
025bb325 MS |
9069 | NULL, /* FIXME: i18n: The distance searched for |
9070 | the start of a function is %s. */ | |
6bcadd06 | 9071 | &setlist, &showlist); |
c906108c SS |
9072 | |
9073 | /* Allow the user to control whether the upper bits of 64-bit | |
9074 | addresses should be zeroed. */ | |
7915a72c AC |
9075 | add_setshow_auto_boolean_cmd ("mask-address", no_class, |
9076 | &mask_address_var, _("\ | |
9077 | Set zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
9078 | Show zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
cce7e648 | 9079 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\ |
7915a72c | 9080 | allow GDB to determine the correct value."), |
08546159 AC |
9081 | NULL, show_mask_address, |
9082 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
9083 | |
9084 | /* Allow the user to control the size of 32 bit registers within the | |
9085 | raw remote packet. */ | |
b3f42336 | 9086 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
7915a72c AC |
9087 | &mips64_transfers_32bit_regs_p, _("\ |
9088 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
9089 | _("\ | |
9090 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
9091 | _("\ | |
719ec221 AC |
9092 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
9093 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
7915a72c | 9094 | 64 bits for others. Use \"off\" to disable compatibility mode"), |
2c5b56ce | 9095 | set_mips64_transfers_32bit_regs, |
025bb325 MS |
9096 | NULL, /* FIXME: i18n: Compatibility with 64-bit |
9097 | MIPS target that transfers 32-bit | |
9098 | quantities is %s. */ | |
7915a72c | 9099 | &setlist, &showlist); |
9ace0497 | 9100 | |
025bb325 | 9101 | /* Debug this files internals. */ |
ccce17b0 YQ |
9102 | add_setshow_zuinteger_cmd ("mips", class_maintenance, |
9103 | &mips_debug, _("\ | |
7915a72c AC |
9104 | Set mips debugging."), _("\ |
9105 | Show mips debugging."), _("\ | |
9106 | When non-zero, mips specific debugging is enabled."), | |
ccce17b0 YQ |
9107 | NULL, |
9108 | NULL, /* FIXME: i18n: Mips debugging is | |
9109 | currently %s. */ | |
9110 | &setdebuglist, &showdebuglist); | |
c906108c | 9111 | } |