Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
6aba47ca | 3 | Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
4c38e0a4 | 4 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, |
7b6bb8da | 5 | 2010, 2011 Free Software Foundation, Inc. |
bf64bfd6 | 6 | |
c906108c SS |
7 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
8 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
9 | ||
c5aa993b | 10 | This file is part of GDB. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is free software; you can redistribute it and/or modify |
13 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 14 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 15 | (at your option) any later version. |
c906108c | 16 | |
c5aa993b JM |
17 | This program is distributed in the hope that it will be useful, |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
c906108c | 21 | |
c5aa993b | 22 | You should have received a copy of the GNU General Public License |
a9762ec7 | 23 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
24 | |
25 | #include "defs.h" | |
26 | #include "gdb_string.h" | |
5e2e9765 | 27 | #include "gdb_assert.h" |
c906108c SS |
28 | #include "frame.h" |
29 | #include "inferior.h" | |
30 | #include "symtab.h" | |
31 | #include "value.h" | |
32 | #include "gdbcmd.h" | |
33 | #include "language.h" | |
34 | #include "gdbcore.h" | |
35 | #include "symfile.h" | |
36 | #include "objfiles.h" | |
37 | #include "gdbtypes.h" | |
38 | #include "target.h" | |
28d069e6 | 39 | #include "arch-utils.h" |
4e052eda | 40 | #include "regcache.h" |
70f80edf | 41 | #include "osabi.h" |
d1973055 | 42 | #include "mips-tdep.h" |
fe898f56 | 43 | #include "block.h" |
a4b8ebc8 | 44 | #include "reggroups.h" |
c906108c | 45 | #include "opcode/mips.h" |
c2d11a7d JM |
46 | #include "elf/mips.h" |
47 | #include "elf-bfd.h" | |
2475bac3 | 48 | #include "symcat.h" |
a4b8ebc8 | 49 | #include "sim-regno.h" |
a89aa300 | 50 | #include "dis-asm.h" |
edfae063 AC |
51 | #include "frame-unwind.h" |
52 | #include "frame-base.h" | |
53 | #include "trad-frame.h" | |
7d9b040b | 54 | #include "infcall.h" |
fed7ba43 | 55 | #include "floatformat.h" |
29709017 DJ |
56 | #include "remote.h" |
57 | #include "target-descriptions.h" | |
2bd0c3d7 | 58 | #include "dwarf2-frame.h" |
f8b73d13 | 59 | #include "user-regs.h" |
79a45b7d | 60 | #include "valprint.h" |
175ff332 | 61 | #include "ax.h" |
c906108c | 62 | |
8d5f9dcb DJ |
63 | static const struct objfile_data *mips_pdr_data; |
64 | ||
5bbcb741 | 65 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 66 | |
24e05951 | 67 | /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ |
dd824b04 DJ |
68 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ |
69 | #define ST0_FR (1 << 26) | |
70 | ||
b0069a17 AC |
71 | /* The sizes of floating point registers. */ |
72 | ||
73 | enum | |
74 | { | |
75 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
76 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
77 | }; | |
78 | ||
1a69e1e4 DJ |
79 | enum |
80 | { | |
81 | MIPS32_REGSIZE = 4, | |
82 | MIPS64_REGSIZE = 8 | |
83 | }; | |
0dadbba0 | 84 | |
2e4ebe70 DJ |
85 | static const char *mips_abi_string; |
86 | ||
87 | static const char *mips_abi_strings[] = { | |
88 | "auto", | |
89 | "n32", | |
90 | "o32", | |
28d169de | 91 | "n64", |
2e4ebe70 DJ |
92 | "o64", |
93 | "eabi32", | |
94 | "eabi64", | |
95 | NULL | |
96 | }; | |
97 | ||
f8b73d13 DJ |
98 | /* The standard register names, and all the valid aliases for them. */ |
99 | struct register_alias | |
100 | { | |
101 | const char *name; | |
102 | int regnum; | |
103 | }; | |
104 | ||
105 | /* Aliases for o32 and most other ABIs. */ | |
106 | const struct register_alias mips_o32_aliases[] = { | |
107 | { "ta0", 12 }, | |
108 | { "ta1", 13 }, | |
109 | { "ta2", 14 }, | |
110 | { "ta3", 15 } | |
111 | }; | |
112 | ||
113 | /* Aliases for n32 and n64. */ | |
114 | const struct register_alias mips_n32_n64_aliases[] = { | |
115 | { "ta0", 8 }, | |
116 | { "ta1", 9 }, | |
117 | { "ta2", 10 }, | |
118 | { "ta3", 11 } | |
119 | }; | |
120 | ||
121 | /* Aliases for ABI-independent registers. */ | |
122 | const struct register_alias mips_register_aliases[] = { | |
123 | /* The architecture manuals specify these ABI-independent names for | |
124 | the GPRs. */ | |
125 | #define R(n) { "r" #n, n } | |
126 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
127 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
128 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
129 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
130 | #undef R | |
131 | ||
132 | /* k0 and k1 are sometimes called these instead (for "kernel | |
133 | temp"). */ | |
134 | { "kt0", 26 }, | |
135 | { "kt1", 27 }, | |
136 | ||
137 | /* This is the traditional GDB name for the CP0 status register. */ | |
138 | { "sr", MIPS_PS_REGNUM }, | |
139 | ||
140 | /* This is the traditional GDB name for the CP0 BadVAddr register. */ | |
141 | { "bad", MIPS_EMBED_BADVADDR_REGNUM }, | |
142 | ||
143 | /* This is the traditional GDB name for the FCSR. */ | |
144 | { "fsr", MIPS_EMBED_FP0_REGNUM + 32 } | |
145 | }; | |
146 | ||
865093a3 AR |
147 | const struct register_alias mips_numeric_register_aliases[] = { |
148 | #define R(n) { #n, n } | |
149 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
150 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
151 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
152 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
153 | #undef R | |
154 | }; | |
155 | ||
c906108c SS |
156 | #ifndef MIPS_DEFAULT_FPU_TYPE |
157 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
158 | #endif | |
159 | static int mips_fpu_type_auto = 1; | |
160 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 161 | |
9ace0497 | 162 | static int mips_debug = 0; |
7a292a7a | 163 | |
29709017 DJ |
164 | /* Properties (for struct target_desc) describing the g/G packet |
165 | layout. */ | |
166 | #define PROPERTY_GP32 "internal: transfers-32bit-registers" | |
167 | #define PROPERTY_GP64 "internal: transfers-64bit-registers" | |
168 | ||
4eb0ad19 DJ |
169 | struct target_desc *mips_tdesc_gp32; |
170 | struct target_desc *mips_tdesc_gp64; | |
171 | ||
56cea623 AC |
172 | const struct mips_regnum * |
173 | mips_regnum (struct gdbarch *gdbarch) | |
174 | { | |
175 | return gdbarch_tdep (gdbarch)->regnum; | |
176 | } | |
177 | ||
178 | static int | |
179 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
180 | { | |
181 | return mips_regnum (gdbarch)->fp0 + 12; | |
182 | } | |
183 | ||
74ed0bb4 MD |
184 | #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \ |
185 | == MIPS_ABI_EABI32 \ | |
186 | || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64) | |
c2d11a7d | 187 | |
025bb325 MS |
188 | #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \ |
189 | (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum) | |
c2d11a7d | 190 | |
025bb325 MS |
191 | #define MIPS_LAST_ARG_REGNUM(gdbarch) \ |
192 | (gdbarch_tdep (gdbarch)->mips_last_arg_regnum) | |
c2d11a7d | 193 | |
74ed0bb4 | 194 | #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type) |
c2d11a7d | 195 | |
95404a3e AC |
196 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
197 | functions to test, set, or clear bit 0 of addresses. */ | |
198 | ||
199 | static CORE_ADDR | |
200 | is_mips16_addr (CORE_ADDR addr) | |
201 | { | |
202 | return ((addr) & 1); | |
203 | } | |
204 | ||
95404a3e AC |
205 | static CORE_ADDR |
206 | unmake_mips16_addr (CORE_ADDR addr) | |
207 | { | |
5b652102 | 208 | return ((addr) & ~(CORE_ADDR) 1); |
95404a3e AC |
209 | } |
210 | ||
930bd0e0 KB |
211 | static CORE_ADDR |
212 | make_mips16_addr (CORE_ADDR addr) | |
213 | { | |
214 | return ((addr) | (CORE_ADDR) 1); | |
215 | } | |
216 | ||
d1973055 KB |
217 | /* Return the MIPS ABI associated with GDBARCH. */ |
218 | enum mips_abi | |
219 | mips_abi (struct gdbarch *gdbarch) | |
220 | { | |
221 | return gdbarch_tdep (gdbarch)->mips_abi; | |
222 | } | |
223 | ||
4246e332 | 224 | int |
1b13c4f6 | 225 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 | 226 | { |
29709017 DJ |
227 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
228 | ||
229 | /* If we know how big the registers are, use that size. */ | |
230 | if (tdep->register_size_valid_p) | |
231 | return tdep->register_size; | |
232 | ||
233 | /* Fall back to the previous behavior. */ | |
4246e332 AC |
234 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word |
235 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
236 | } | |
237 | ||
025bb325 | 238 | /* Return the currently configured (or set) saved register size. */ |
480d3dd2 | 239 | |
e6bc2e8a | 240 | unsigned int |
13326b4e | 241 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 242 | { |
1a69e1e4 DJ |
243 | switch (mips_abi (gdbarch)) |
244 | { | |
245 | case MIPS_ABI_EABI32: | |
246 | case MIPS_ABI_O32: | |
247 | return 4; | |
248 | case MIPS_ABI_N32: | |
249 | case MIPS_ABI_N64: | |
250 | case MIPS_ABI_O64: | |
251 | case MIPS_ABI_EABI64: | |
252 | return 8; | |
253 | case MIPS_ABI_UNKNOWN: | |
254 | case MIPS_ABI_LAST: | |
255 | default: | |
256 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
257 | } | |
d929b26f AC |
258 | } |
259 | ||
71b8ef93 | 260 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 261 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 262 | "info" field is used for this purpose. |
5a89d8aa | 263 | |
95f1da47 | 264 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special", |
5a89d8aa MS |
265 | i.e. refers to a 16-bit function, and sets a "special" bit in a |
266 | minimal symbol to mark it as a 16-bit function | |
267 | ||
f594e5e9 | 268 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 269 | |
5a89d8aa | 270 | static void |
6d82d43b AC |
271 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
272 | { | |
273 | if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16) | |
274 | { | |
b887350f | 275 | MSYMBOL_TARGET_FLAG_1 (msym) = 1; |
6d82d43b | 276 | } |
5a89d8aa MS |
277 | } |
278 | ||
71b8ef93 MS |
279 | static int |
280 | msymbol_is_special (struct minimal_symbol *msym) | |
281 | { | |
b887350f | 282 | return MSYMBOL_TARGET_FLAG_1 (msym); |
71b8ef93 MS |
283 | } |
284 | ||
88658117 AC |
285 | /* XFER a value from the big/little/left end of the register. |
286 | Depending on the size of the value it might occupy the entire | |
287 | register or just part of it. Make an allowance for this, aligning | |
288 | things accordingly. */ | |
289 | ||
290 | static void | |
ba32f989 DJ |
291 | mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache, |
292 | int reg_num, int length, | |
870cd05e MK |
293 | enum bfd_endian endian, gdb_byte *in, |
294 | const gdb_byte *out, int buf_offset) | |
88658117 | 295 | { |
88658117 | 296 | int reg_offset = 0; |
72a155b4 UW |
297 | |
298 | gdb_assert (reg_num >= gdbarch_num_regs (gdbarch)); | |
cb1d2653 AC |
299 | /* Need to transfer the left or right part of the register, based on |
300 | the targets byte order. */ | |
88658117 AC |
301 | switch (endian) |
302 | { | |
303 | case BFD_ENDIAN_BIG: | |
72a155b4 | 304 | reg_offset = register_size (gdbarch, reg_num) - length; |
88658117 AC |
305 | break; |
306 | case BFD_ENDIAN_LITTLE: | |
307 | reg_offset = 0; | |
308 | break; | |
6d82d43b | 309 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
310 | reg_offset = 0; |
311 | break; | |
312 | default: | |
e2e0b3e5 | 313 | internal_error (__FILE__, __LINE__, _("bad switch")); |
88658117 AC |
314 | } |
315 | if (mips_debug) | |
cb1d2653 AC |
316 | fprintf_unfiltered (gdb_stderr, |
317 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
318 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
319 | if (mips_debug && out != NULL) |
320 | { | |
321 | int i; | |
cb1d2653 | 322 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 323 | for (i = 0; i < length; i++) |
cb1d2653 | 324 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
325 | } |
326 | if (in != NULL) | |
6d82d43b AC |
327 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
328 | in + buf_offset); | |
88658117 | 329 | if (out != NULL) |
6d82d43b AC |
330 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
331 | out + buf_offset); | |
88658117 AC |
332 | if (mips_debug && in != NULL) |
333 | { | |
334 | int i; | |
cb1d2653 | 335 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 336 | for (i = 0; i < length; i++) |
cb1d2653 | 337 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
338 | } |
339 | if (mips_debug) | |
340 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
341 | } | |
342 | ||
dd824b04 DJ |
343 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
344 | compatiblity mode. A return value of 1 means that we have | |
345 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
346 | ||
347 | static int | |
9c9acae0 | 348 | mips2_fp_compat (struct frame_info *frame) |
dd824b04 | 349 | { |
72a155b4 | 350 | struct gdbarch *gdbarch = get_frame_arch (frame); |
dd824b04 DJ |
351 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not |
352 | meaningful. */ | |
72a155b4 | 353 | if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4) |
dd824b04 DJ |
354 | return 0; |
355 | ||
356 | #if 0 | |
357 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
358 | in all the places we deal with FP registers. PR gdb/413. */ | |
359 | /* Otherwise check the FR bit in the status register - it controls | |
360 | the FP compatiblity mode. If it is clear we are in compatibility | |
361 | mode. */ | |
9c9acae0 | 362 | if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0) |
dd824b04 DJ |
363 | return 1; |
364 | #endif | |
361d1df0 | 365 | |
dd824b04 DJ |
366 | return 0; |
367 | } | |
368 | ||
7a292a7a | 369 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 370 | |
74ed0bb4 | 371 | static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR); |
c906108c | 372 | |
a14ed312 | 373 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 374 | |
025bb325 | 375 | /* The list of available "set mips " and "show mips " commands. */ |
acdb74a0 AC |
376 | |
377 | static struct cmd_list_element *setmipscmdlist = NULL; | |
378 | static struct cmd_list_element *showmipscmdlist = NULL; | |
379 | ||
5e2e9765 KB |
380 | /* Integer registers 0 thru 31 are handled explicitly by |
381 | mips_register_name(). Processor specific registers 32 and above | |
8a9fc081 | 382 | are listed in the following tables. */ |
691c0433 | 383 | |
6d82d43b AC |
384 | enum |
385 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
386 | |
387 | /* Generic MIPS. */ | |
388 | ||
389 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
390 | "sr", "lo", "hi", "bad", "cause", "pc", |
391 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
392 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
393 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
394 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
395 | "fsr", "fir", "" /*"fp" */ , "", | |
396 | "", "", "", "", "", "", "", "", | |
397 | "", "", "", "", "", "", "", "", | |
691c0433 AC |
398 | }; |
399 | ||
400 | /* Names of IDT R3041 registers. */ | |
401 | ||
402 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
403 | "sr", "lo", "hi", "bad", "cause", "pc", |
404 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
405 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
406 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
407 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
408 | "fsr", "fir", "", /*"fp" */ "", | |
409 | "", "", "bus", "ccfg", "", "", "", "", | |
410 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
411 | }; |
412 | ||
413 | /* Names of tx39 registers. */ | |
414 | ||
415 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
416 | "sr", "lo", "hi", "bad", "cause", "pc", |
417 | "", "", "", "", "", "", "", "", | |
418 | "", "", "", "", "", "", "", "", | |
419 | "", "", "", "", "", "", "", "", | |
420 | "", "", "", "", "", "", "", "", | |
421 | "", "", "", "", | |
422 | "", "", "", "", "", "", "", "", | |
423 | "", "", "config", "cache", "debug", "depc", "epc", "" | |
691c0433 AC |
424 | }; |
425 | ||
426 | /* Names of IRIX registers. */ | |
427 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
428 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
429 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
430 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
431 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
432 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
433 | }; |
434 | ||
cce74817 | 435 | |
5e2e9765 | 436 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 437 | static const char * |
d93859e2 | 438 | mips_register_name (struct gdbarch *gdbarch, int regno) |
cce74817 | 439 | { |
d93859e2 | 440 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
5e2e9765 KB |
441 | /* GPR names for all ABIs other than n32/n64. */ |
442 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
443 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
444 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
445 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
446 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
447 | }; |
448 | ||
449 | /* GPR names for n32 and n64 ABIs. */ | |
450 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
451 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
452 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
453 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
454 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
455 | }; |
456 | ||
d93859e2 | 457 | enum mips_abi abi = mips_abi (gdbarch); |
5e2e9765 | 458 | |
f57d151a | 459 | /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, |
6229fbea HZ |
460 | but then don't make the raw register names visible. This (upper) |
461 | range of user visible register numbers are the pseudo-registers. | |
462 | ||
463 | This approach was adopted accommodate the following scenario: | |
464 | It is possible to debug a 64-bit device using a 32-bit | |
465 | programming model. In such instances, the raw registers are | |
466 | configured to be 64-bits wide, while the pseudo registers are | |
467 | configured to be 32-bits wide. The registers that the user | |
468 | sees - the pseudo registers - match the users expectations | |
469 | given the programming model being used. */ | |
d93859e2 UW |
470 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
471 | if (regno < gdbarch_num_regs (gdbarch)) | |
a4b8ebc8 AC |
472 | return ""; |
473 | ||
5e2e9765 KB |
474 | /* The MIPS integer registers are always mapped from 0 to 31. The |
475 | names of the registers (which reflects the conventions regarding | |
476 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 477 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
478 | { |
479 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 480 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 481 | else |
a4b8ebc8 | 482 | return mips_gpr_names[rawnum]; |
5e2e9765 | 483 | } |
d93859e2 UW |
484 | else if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
485 | return tdesc_register_name (gdbarch, rawnum); | |
486 | else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch)) | |
691c0433 AC |
487 | { |
488 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
489 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
490 | } | |
5e2e9765 KB |
491 | else |
492 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 493 | _("mips_register_name: bad register number %d"), rawnum); |
cce74817 | 494 | } |
5e2e9765 | 495 | |
a4b8ebc8 | 496 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 497 | |
a4b8ebc8 AC |
498 | static int |
499 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
500 | struct reggroup *reggroup) | |
501 | { | |
502 | int vector_p; | |
503 | int float_p; | |
504 | int raw_p; | |
72a155b4 UW |
505 | int rawnum = regnum % gdbarch_num_regs (gdbarch); |
506 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
a4b8ebc8 AC |
507 | if (reggroup == all_reggroup) |
508 | return pseudo; | |
509 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
510 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
511 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
512 | (gdbarch), as not all architectures are multi-arch. */ | |
72a155b4 UW |
513 | raw_p = rawnum < gdbarch_num_regs (gdbarch); |
514 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
515 | || gdbarch_register_name (gdbarch, regnum)[0] == '\0') | |
a4b8ebc8 AC |
516 | return 0; |
517 | if (reggroup == float_reggroup) | |
518 | return float_p && pseudo; | |
519 | if (reggroup == vector_reggroup) | |
520 | return vector_p && pseudo; | |
521 | if (reggroup == general_reggroup) | |
522 | return (!vector_p && !float_p) && pseudo; | |
523 | /* Save the pseudo registers. Need to make certain that any code | |
524 | extracting register values from a saved register cache also uses | |
525 | pseudo registers. */ | |
526 | if (reggroup == save_reggroup) | |
527 | return raw_p && pseudo; | |
528 | /* Restore the same pseudo register. */ | |
529 | if (reggroup == restore_reggroup) | |
530 | return raw_p && pseudo; | |
6d82d43b | 531 | return 0; |
a4b8ebc8 AC |
532 | } |
533 | ||
f8b73d13 DJ |
534 | /* Return the groups that a MIPS register can be categorised into. |
535 | This version is only used if we have a target description which | |
536 | describes real registers (and their groups). */ | |
537 | ||
538 | static int | |
539 | mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
540 | struct reggroup *reggroup) | |
541 | { | |
542 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
543 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
544 | int ret; | |
545 | ||
546 | /* Only save, restore, and display the pseudo registers. Need to | |
547 | make certain that any code extracting register values from a | |
548 | saved register cache also uses pseudo registers. | |
549 | ||
550 | Note: saving and restoring the pseudo registers is slightly | |
551 | strange; if we have 64 bits, we should save and restore all | |
552 | 64 bits. But this is hard and has little benefit. */ | |
553 | if (!pseudo) | |
554 | return 0; | |
555 | ||
556 | ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup); | |
557 | if (ret != -1) | |
558 | return ret; | |
559 | ||
560 | return mips_register_reggroup_p (gdbarch, regnum, reggroup); | |
561 | } | |
562 | ||
a4b8ebc8 | 563 | /* Map the symbol table registers which live in the range [1 * |
f57d151a | 564 | gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw |
47ebcfbe | 565 | registers. Take care of alignment and size problems. */ |
c5aa993b | 566 | |
05d1431c | 567 | static enum register_status |
a4b8ebc8 | 568 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
47a35522 | 569 | int cookednum, gdb_byte *buf) |
a4b8ebc8 | 570 | { |
72a155b4 UW |
571 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
572 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
573 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 574 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
05d1431c | 575 | return regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
576 | else if (register_size (gdbarch, rawnum) > |
577 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 578 | { |
8bdf35dc | 579 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
05d1431c | 580 | return regcache_raw_read_part (regcache, rawnum, 0, 4, buf); |
47ebcfbe | 581 | else |
8bdf35dc KB |
582 | { |
583 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
584 | LONGEST regval; | |
05d1431c PA |
585 | enum register_status status; |
586 | ||
587 | status = regcache_raw_read_signed (regcache, rawnum, ®val); | |
588 | if (status == REG_VALID) | |
589 | store_signed_integer (buf, 4, byte_order, regval); | |
590 | return status; | |
8bdf35dc | 591 | } |
47ebcfbe AC |
592 | } |
593 | else | |
e2e0b3e5 | 594 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 AC |
595 | } |
596 | ||
597 | static void | |
6d82d43b AC |
598 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
599 | struct regcache *regcache, int cookednum, | |
47a35522 | 600 | const gdb_byte *buf) |
a4b8ebc8 | 601 | { |
72a155b4 UW |
602 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
603 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
604 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 605 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 606 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
607 | else if (register_size (gdbarch, rawnum) > |
608 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 609 | { |
8bdf35dc | 610 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
47ebcfbe AC |
611 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); |
612 | else | |
8bdf35dc KB |
613 | { |
614 | /* Sign extend the shortened version of the register prior | |
615 | to placing it in the raw register. This is required for | |
616 | some mips64 parts in order to avoid unpredictable behavior. */ | |
617 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
618 | LONGEST regval = extract_signed_integer (buf, 4, byte_order); | |
619 | regcache_raw_write_signed (regcache, rawnum, regval); | |
620 | } | |
47ebcfbe AC |
621 | } |
622 | else | |
e2e0b3e5 | 623 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 | 624 | } |
c5aa993b | 625 | |
175ff332 HZ |
626 | static int |
627 | mips_ax_pseudo_register_collect (struct gdbarch *gdbarch, | |
628 | struct agent_expr *ax, int reg) | |
629 | { | |
630 | int rawnum = reg % gdbarch_num_regs (gdbarch); | |
631 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) | |
632 | && reg < 2 * gdbarch_num_regs (gdbarch)); | |
633 | ||
634 | ax_reg_mask (ax, rawnum); | |
635 | ||
636 | return 0; | |
637 | } | |
638 | ||
639 | static int | |
640 | mips_ax_pseudo_register_push_stack (struct gdbarch *gdbarch, | |
641 | struct agent_expr *ax, int reg) | |
642 | { | |
643 | int rawnum = reg % gdbarch_num_regs (gdbarch); | |
644 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) | |
645 | && reg < 2 * gdbarch_num_regs (gdbarch)); | |
646 | if (register_size (gdbarch, rawnum) >= register_size (gdbarch, reg)) | |
647 | { | |
648 | ax_reg (ax, rawnum); | |
649 | ||
650 | if (register_size (gdbarch, rawnum) > register_size (gdbarch, reg)) | |
651 | { | |
652 | if (!gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
653 | || gdbarch_byte_order (gdbarch) != BFD_ENDIAN_BIG) | |
654 | { | |
655 | ax_const_l (ax, 32); | |
656 | ax_simple (ax, aop_lsh); | |
657 | } | |
658 | ax_const_l (ax, 32); | |
659 | ax_simple (ax, aop_rsh_signed); | |
660 | } | |
661 | } | |
662 | else | |
663 | internal_error (__FILE__, __LINE__, _("bad register size")); | |
664 | ||
665 | return 0; | |
666 | } | |
667 | ||
c906108c | 668 | /* Table to translate MIPS16 register field to actual register number. */ |
6d82d43b | 669 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
670 | |
671 | /* Heuristic_proc_start may hunt through the text section for a long | |
672 | time across a 2400 baud serial line. Allows the user to limit this | |
673 | search. */ | |
674 | ||
675 | static unsigned int heuristic_fence_post = 0; | |
676 | ||
46cd78fb | 677 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
678 | register N. NOTE: This defines the pseudo register type so need to |
679 | rebuild the architecture vector. */ | |
43e526b9 JM |
680 | |
681 | static int mips64_transfers_32bit_regs_p = 0; | |
682 | ||
719ec221 AC |
683 | static void |
684 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
685 | struct cmd_list_element *c) | |
43e526b9 | 686 | { |
719ec221 AC |
687 | struct gdbarch_info info; |
688 | gdbarch_info_init (&info); | |
689 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
690 | instead of relying on globals. Doing that would let generic code | |
691 | handle the search for this specific architecture. */ | |
692 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 693 | { |
719ec221 | 694 | mips64_transfers_32bit_regs_p = 0; |
8a3fe4f8 | 695 | error (_("32-bit compatibility mode not supported")); |
a4b8ebc8 | 696 | } |
a4b8ebc8 AC |
697 | } |
698 | ||
47ebcfbe | 699 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 700 | |
ee51a8c7 KB |
701 | /* This predicate tests for the case of an 8 byte floating point |
702 | value that is being transferred to or from a pair of floating point | |
703 | registers each of which are (or are considered to be) only 4 bytes | |
704 | wide. */ | |
ff2e87ac | 705 | static int |
ee51a8c7 KB |
706 | mips_convert_register_float_case_p (struct gdbarch *gdbarch, int regnum, |
707 | struct type *type) | |
ff2e87ac | 708 | { |
0abe36f5 MD |
709 | return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
710 | && register_size (gdbarch, regnum) == 4 | |
711 | && (regnum % gdbarch_num_regs (gdbarch)) | |
712 | >= mips_regnum (gdbarch)->fp0 | |
713 | && (regnum % gdbarch_num_regs (gdbarch)) | |
714 | < mips_regnum (gdbarch)->fp0 + 32 | |
6d82d43b | 715 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
716 | } |
717 | ||
ee51a8c7 KB |
718 | /* This predicate tests for the case of a value of less than 8 |
719 | bytes in width that is being transfered to or from an 8 byte | |
720 | general purpose register. */ | |
721 | static int | |
722 | mips_convert_register_gpreg_case_p (struct gdbarch *gdbarch, int regnum, | |
723 | struct type *type) | |
724 | { | |
725 | int num_regs = gdbarch_num_regs (gdbarch); | |
726 | ||
727 | return (register_size (gdbarch, regnum) == 8 | |
728 | && regnum % num_regs > 0 && regnum % num_regs < 32 | |
729 | && TYPE_LENGTH (type) < 8); | |
730 | } | |
731 | ||
732 | static int | |
025bb325 MS |
733 | mips_convert_register_p (struct gdbarch *gdbarch, |
734 | int regnum, struct type *type) | |
ee51a8c7 KB |
735 | { |
736 | return mips_convert_register_float_case_p (gdbarch, regnum, type) | |
737 | || mips_convert_register_gpreg_case_p (gdbarch, regnum, type); | |
738 | } | |
739 | ||
8dccd430 | 740 | static int |
ff2e87ac | 741 | mips_register_to_value (struct frame_info *frame, int regnum, |
8dccd430 PA |
742 | struct type *type, gdb_byte *to, |
743 | int *optimizedp, int *unavailablep) | |
102182a9 | 744 | { |
ee51a8c7 KB |
745 | struct gdbarch *gdbarch = get_frame_arch (frame); |
746 | ||
747 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
748 | { | |
749 | get_frame_register (frame, regnum + 0, to + 4); | |
750 | get_frame_register (frame, regnum + 1, to + 0); | |
8dccd430 PA |
751 | |
752 | if (!get_frame_register_bytes (frame, regnum + 0, 0, 4, to + 4, | |
753 | optimizedp, unavailablep)) | |
754 | return 0; | |
755 | ||
756 | if (!get_frame_register_bytes (frame, regnum + 1, 0, 4, to + 0, | |
757 | optimizedp, unavailablep)) | |
758 | return 0; | |
759 | *optimizedp = *unavailablep = 0; | |
760 | return 1; | |
ee51a8c7 KB |
761 | } |
762 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
763 | { | |
764 | int len = TYPE_LENGTH (type); | |
8dccd430 PA |
765 | CORE_ADDR offset; |
766 | ||
767 | offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 8 - len : 0; | |
768 | if (!get_frame_register_bytes (frame, regnum, offset, len, to, | |
769 | optimizedp, unavailablep)) | |
770 | return 0; | |
771 | ||
772 | *optimizedp = *unavailablep = 0; | |
773 | return 1; | |
ee51a8c7 KB |
774 | } |
775 | else | |
776 | { | |
777 | internal_error (__FILE__, __LINE__, | |
778 | _("mips_register_to_value: unrecognized case")); | |
779 | } | |
102182a9 MS |
780 | } |
781 | ||
42c466d7 | 782 | static void |
ff2e87ac | 783 | mips_value_to_register (struct frame_info *frame, int regnum, |
47a35522 | 784 | struct type *type, const gdb_byte *from) |
102182a9 | 785 | { |
ee51a8c7 KB |
786 | struct gdbarch *gdbarch = get_frame_arch (frame); |
787 | ||
788 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
789 | { | |
790 | put_frame_register (frame, regnum + 0, from + 4); | |
791 | put_frame_register (frame, regnum + 1, from + 0); | |
792 | } | |
793 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
794 | { | |
795 | gdb_byte fill[8]; | |
796 | int len = TYPE_LENGTH (type); | |
797 | ||
798 | /* Sign extend values, irrespective of type, that are stored to | |
799 | a 64-bit general purpose register. (32-bit unsigned values | |
800 | are stored as signed quantities within a 64-bit register. | |
801 | When performing an operation, in compiled code, that combines | |
802 | a 32-bit unsigned value with a signed 64-bit value, a type | |
803 | conversion is first performed that zeroes out the high 32 bits.) */ | |
804 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
805 | { | |
806 | if (from[0] & 0x80) | |
807 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, -1); | |
808 | else | |
809 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, 0); | |
810 | put_frame_register_bytes (frame, regnum, 0, 8 - len, fill); | |
811 | put_frame_register_bytes (frame, regnum, 8 - len, len, from); | |
812 | } | |
813 | else | |
814 | { | |
815 | if (from[len-1] & 0x80) | |
816 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, -1); | |
817 | else | |
818 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, 0); | |
819 | put_frame_register_bytes (frame, regnum, 0, len, from); | |
820 | put_frame_register_bytes (frame, regnum, len, 8 - len, fill); | |
821 | } | |
822 | } | |
823 | else | |
824 | { | |
825 | internal_error (__FILE__, __LINE__, | |
826 | _("mips_value_to_register: unrecognized case")); | |
827 | } | |
102182a9 MS |
828 | } |
829 | ||
a4b8ebc8 AC |
830 | /* Return the GDB type object for the "standard" data type of data in |
831 | register REG. */ | |
78fde5f8 KB |
832 | |
833 | static struct type * | |
a4b8ebc8 AC |
834 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
835 | { | |
72a155b4 UW |
836 | gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch)); |
837 | if ((regnum % gdbarch_num_regs (gdbarch)) >= mips_regnum (gdbarch)->fp0 | |
838 | && (regnum % gdbarch_num_regs (gdbarch)) | |
839 | < mips_regnum (gdbarch)->fp0 + 32) | |
a6425924 | 840 | { |
5ef80fb0 | 841 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 842 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
8da61cc4 | 843 | if (mips_isa_regsize (gdbarch) == 4) |
27067745 | 844 | return builtin_type (gdbarch)->builtin_float; |
8da61cc4 | 845 | else |
27067745 | 846 | return builtin_type (gdbarch)->builtin_double; |
a6425924 | 847 | } |
72a155b4 | 848 | else if (regnum < gdbarch_num_regs (gdbarch)) |
d5ac5a39 AC |
849 | { |
850 | /* The raw or ISA registers. These are all sized according to | |
851 | the ISA regsize. */ | |
852 | if (mips_isa_regsize (gdbarch) == 4) | |
df4df182 | 853 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 | 854 | else |
df4df182 | 855 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 856 | } |
78fde5f8 | 857 | else |
d5ac5a39 AC |
858 | { |
859 | /* The cooked or ABI registers. These are sized according to | |
860 | the ABI (with a few complications). */ | |
72a155b4 UW |
861 | if (regnum >= (gdbarch_num_regs (gdbarch) |
862 | + mips_regnum (gdbarch)->fp_control_status) | |
863 | && regnum <= gdbarch_num_regs (gdbarch) + MIPS_LAST_EMBED_REGNUM) | |
d5ac5a39 AC |
864 | /* The pseudo/cooked view of the embedded registers is always |
865 | 32-bit. The raw view is handled below. */ | |
df4df182 | 866 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
867 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
868 | /* The target, while possibly using a 64-bit register buffer, | |
869 | is only transfering 32-bits of each integer register. | |
870 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
df4df182 | 871 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
872 | else if (mips_abi_regsize (gdbarch) == 4) |
873 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
874 | 32- or 64-bit). */ | |
df4df182 | 875 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
876 | else |
877 | /* 64-bit ABI. */ | |
df4df182 | 878 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 879 | } |
78fde5f8 KB |
880 | } |
881 | ||
f8b73d13 DJ |
882 | /* Return the GDB type for the pseudo register REGNUM, which is the |
883 | ABI-level view. This function is only called if there is a target | |
884 | description which includes registers, so we know precisely the | |
885 | types of hardware registers. */ | |
886 | ||
887 | static struct type * | |
888 | mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
889 | { | |
890 | const int num_regs = gdbarch_num_regs (gdbarch); | |
891 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
892 | int rawnum = regnum % num_regs; | |
893 | struct type *rawtype; | |
894 | ||
895 | gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); | |
896 | ||
897 | /* Absent registers are still absent. */ | |
898 | rawtype = gdbarch_register_type (gdbarch, rawnum); | |
899 | if (TYPE_LENGTH (rawtype) == 0) | |
900 | return rawtype; | |
901 | ||
902 | if (rawnum >= MIPS_EMBED_FP0_REGNUM && rawnum < MIPS_EMBED_FP0_REGNUM + 32) | |
903 | /* Present the floating point registers however the hardware did; | |
904 | do not try to convert between FPU layouts. */ | |
905 | return rawtype; | |
906 | ||
907 | if (rawnum >= MIPS_EMBED_FP0_REGNUM + 32 && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
908 | { | |
909 | /* The pseudo/cooked view of embedded registers is always | |
910 | 32-bit, even if the target transfers 64-bit values for them. | |
911 | New targets relying on XML descriptions should only transfer | |
912 | the necessary 32 bits, but older versions of GDB expected 64, | |
913 | so allow the target to provide 64 bits without interfering | |
914 | with the displayed type. */ | |
df4df182 | 915 | return builtin_type (gdbarch)->builtin_int32; |
f8b73d13 DJ |
916 | } |
917 | ||
918 | /* Use pointer types for registers if we can. For n32 we can not, | |
919 | since we do not have a 64-bit pointer type. */ | |
0dfff4cb UW |
920 | if (mips_abi_regsize (gdbarch) |
921 | == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr)) | |
f8b73d13 DJ |
922 | { |
923 | if (rawnum == MIPS_SP_REGNUM || rawnum == MIPS_EMBED_BADVADDR_REGNUM) | |
0dfff4cb | 924 | return builtin_type (gdbarch)->builtin_data_ptr; |
f8b73d13 | 925 | else if (rawnum == MIPS_EMBED_PC_REGNUM) |
0dfff4cb | 926 | return builtin_type (gdbarch)->builtin_func_ptr; |
f8b73d13 DJ |
927 | } |
928 | ||
929 | if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8 | |
930 | && rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_EMBED_PC_REGNUM) | |
df4df182 | 931 | return builtin_type (gdbarch)->builtin_int32; |
f8b73d13 DJ |
932 | |
933 | /* For all other registers, pass through the hardware type. */ | |
934 | return rawtype; | |
935 | } | |
bcb0cc15 | 936 | |
025bb325 | 937 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 938 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
939 | |
940 | static int | |
480d3dd2 | 941 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
942 | { |
943 | switch (mask_address_var) | |
944 | { | |
7f19b9a2 | 945 | case AUTO_BOOLEAN_TRUE: |
4014092b | 946 | return 1; |
7f19b9a2 | 947 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
948 | return 0; |
949 | break; | |
7f19b9a2 | 950 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 951 | return tdep->default_mask_address_p; |
4014092b | 952 | default: |
025bb325 MS |
953 | internal_error (__FILE__, __LINE__, |
954 | _("mips_mask_address_p: bad switch")); | |
4014092b | 955 | return -1; |
361d1df0 | 956 | } |
4014092b AC |
957 | } |
958 | ||
959 | static void | |
08546159 AC |
960 | show_mask_address (struct ui_file *file, int from_tty, |
961 | struct cmd_list_element *c, const char *value) | |
4014092b | 962 | { |
1cf3db46 | 963 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
08546159 AC |
964 | |
965 | deprecated_show_value_hack (file, from_tty, c, value); | |
4014092b AC |
966 | switch (mask_address_var) |
967 | { | |
7f19b9a2 | 968 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
969 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
970 | break; | |
7f19b9a2 | 971 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
972 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
973 | break; | |
7f19b9a2 | 974 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
975 | printf_filtered |
976 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
977 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
978 | break; |
979 | default: | |
e2e0b3e5 | 980 | internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); |
4014092b | 981 | break; |
361d1df0 | 982 | } |
4014092b | 983 | } |
c906108c | 984 | |
c906108c SS |
985 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
986 | ||
0fe7e7c8 AC |
987 | int |
988 | mips_pc_is_mips16 (CORE_ADDR memaddr) | |
c906108c SS |
989 | { |
990 | struct minimal_symbol *sym; | |
991 | ||
025bb325 | 992 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ |
95404a3e | 993 | if (is_mips16_addr (memaddr)) |
c906108c SS |
994 | return 1; |
995 | ||
996 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
997 | the high bit of the info field. Use this to decide if the function is | |
998 | MIPS16 or normal MIPS. */ | |
999 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
1000 | if (sym) | |
71b8ef93 | 1001 | return msymbol_is_special (sym); |
c906108c SS |
1002 | else |
1003 | return 0; | |
1004 | } | |
1005 | ||
b2fa5097 | 1006 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
025bb325 | 1007 | all registers should be sign extended for simplicity? */ |
6c997a34 AC |
1008 | |
1009 | static CORE_ADDR | |
61a1198a | 1010 | mips_read_pc (struct regcache *regcache) |
6c997a34 | 1011 | { |
61a1198a UW |
1012 | ULONGEST pc; |
1013 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; | |
1014 | regcache_cooked_read_signed (regcache, regnum, &pc); | |
930bd0e0 KB |
1015 | if (is_mips16_addr (pc)) |
1016 | pc = unmake_mips16_addr (pc); | |
61a1198a | 1017 | return pc; |
b6cb9035 AC |
1018 | } |
1019 | ||
58dfe9ff AC |
1020 | static CORE_ADDR |
1021 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1022 | { | |
930bd0e0 KB |
1023 | ULONGEST pc; |
1024 | ||
1025 | pc = frame_unwind_register_signed | |
1026 | (next_frame, gdbarch_num_regs (gdbarch) + mips_regnum (gdbarch)->pc); | |
1027 | if (is_mips16_addr (pc)) | |
1028 | pc = unmake_mips16_addr (pc); | |
1029 | return pc; | |
edfae063 AC |
1030 | } |
1031 | ||
30244cd8 UW |
1032 | static CORE_ADDR |
1033 | mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1034 | { | |
72a155b4 UW |
1035 | return frame_unwind_register_signed |
1036 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM); | |
30244cd8 UW |
1037 | } |
1038 | ||
b8a22b94 | 1039 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that |
edfae063 AC |
1040 | dummy frame. The frame ID's base needs to match the TOS value |
1041 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
1042 | breakpoint. */ | |
1043 | ||
1044 | static struct frame_id | |
b8a22b94 | 1045 | mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
edfae063 | 1046 | { |
f57d151a | 1047 | return frame_id_build |
b8a22b94 DJ |
1048 | (get_frame_register_signed (this_frame, |
1049 | gdbarch_num_regs (gdbarch) | |
1050 | + MIPS_SP_REGNUM), | |
1051 | get_frame_pc (this_frame)); | |
58dfe9ff AC |
1052 | } |
1053 | ||
b6cb9035 | 1054 | static void |
61a1198a | 1055 | mips_write_pc (struct regcache *regcache, CORE_ADDR pc) |
b6cb9035 | 1056 | { |
61a1198a | 1057 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; |
930bd0e0 KB |
1058 | if (mips_pc_is_mips16 (pc)) |
1059 | regcache_cooked_write_unsigned (regcache, regnum, make_mips16_addr (pc)); | |
1060 | else | |
1061 | regcache_cooked_write_unsigned (regcache, regnum, pc); | |
6c997a34 | 1062 | } |
c906108c | 1063 | |
c906108c SS |
1064 | /* Fetch and return instruction from the specified location. If the PC |
1065 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
1066 | ||
d37cca3d | 1067 | static ULONGEST |
e17a4113 | 1068 | mips_fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR addr) |
c906108c | 1069 | { |
e17a4113 | 1070 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 1071 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
1072 | int instlen; |
1073 | int status; | |
1074 | ||
0fe7e7c8 | 1075 | if (mips_pc_is_mips16 (addr)) |
c906108c | 1076 | { |
95ac2dcf | 1077 | instlen = MIPS_INSN16_SIZE; |
95404a3e | 1078 | addr = unmake_mips16_addr (addr); |
c906108c SS |
1079 | } |
1080 | else | |
95ac2dcf | 1081 | instlen = MIPS_INSN32_SIZE; |
8defab1a | 1082 | status = target_read_memory (addr, buf, instlen); |
c906108c SS |
1083 | if (status) |
1084 | memory_error (status, addr); | |
e17a4113 | 1085 | return extract_unsigned_integer (buf, instlen, byte_order); |
c906108c SS |
1086 | } |
1087 | ||
025bb325 | 1088 | /* These are the fields of 32 bit mips instructions. */ |
e135b889 DJ |
1089 | #define mips32_op(x) (x >> 26) |
1090 | #define itype_op(x) (x >> 26) | |
1091 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 1092 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 1093 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 1094 | |
e135b889 DJ |
1095 | #define jtype_op(x) (x >> 26) |
1096 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 1097 | |
e135b889 DJ |
1098 | #define rtype_op(x) (x >> 26) |
1099 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
1100 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
1101 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
1102 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
1103 | #define rtype_funct(x) (x & 0x3f) | |
c906108c | 1104 | |
06987e64 MK |
1105 | static LONGEST |
1106 | mips32_relative_offset (ULONGEST inst) | |
c5aa993b | 1107 | { |
06987e64 | 1108 | return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; |
c906108c SS |
1109 | } |
1110 | ||
f49e4e6d MS |
1111 | /* Determine where to set a single step breakpoint while considering |
1112 | branch prediction. */ | |
5a89d8aa | 1113 | static CORE_ADDR |
0b1b3e42 | 1114 | mips32_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c5aa993b | 1115 | { |
e17a4113 | 1116 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c5aa993b JM |
1117 | unsigned long inst; |
1118 | int op; | |
e17a4113 | 1119 | inst = mips_fetch_instruction (gdbarch, pc); |
025bb325 MS |
1120 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch |
1121 | instruction. */ | |
c5aa993b | 1122 | { |
e135b889 | 1123 | if (itype_op (inst) >> 2 == 5) |
6d82d43b | 1124 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 1125 | { |
e135b889 | 1126 | op = (itype_op (inst) & 0x03); |
c906108c SS |
1127 | switch (op) |
1128 | { | |
e135b889 DJ |
1129 | case 0: /* BEQL */ |
1130 | goto equal_branch; | |
1131 | case 1: /* BNEL */ | |
1132 | goto neq_branch; | |
1133 | case 2: /* BLEZL */ | |
1134 | goto less_branch; | |
313628cc | 1135 | case 3: /* BGTZL */ |
e135b889 | 1136 | goto greater_branch; |
c5aa993b JM |
1137 | default: |
1138 | pc += 4; | |
c906108c SS |
1139 | } |
1140 | } | |
e135b889 | 1141 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
6d82d43b | 1142 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
e135b889 DJ |
1143 | { |
1144 | int tf = itype_rt (inst) & 0x01; | |
1145 | int cnum = itype_rt (inst) >> 2; | |
6d82d43b | 1146 | int fcrcs = |
72a155b4 UW |
1147 | get_frame_register_signed (frame, |
1148 | mips_regnum (get_frame_arch (frame))-> | |
0b1b3e42 | 1149 | fp_control_status); |
e135b889 DJ |
1150 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); |
1151 | ||
1152 | if (((cond >> cnum) & 0x01) == tf) | |
1153 | pc += mips32_relative_offset (inst) + 4; | |
1154 | else | |
1155 | pc += 8; | |
1156 | } | |
c5aa993b | 1157 | else |
025bb325 | 1158 | pc += 4; /* Not a branch, next instruction is easy. */ |
c906108c SS |
1159 | } |
1160 | else | |
025bb325 | 1161 | { /* This gets way messy. */ |
c5aa993b | 1162 | |
025bb325 MS |
1163 | /* Further subdivide into SPECIAL, REGIMM and other. */ |
1164 | switch (op = itype_op (inst) & 0x07) /* Extract bits 28,27,26. */ | |
c906108c | 1165 | { |
c5aa993b JM |
1166 | case 0: /* SPECIAL */ |
1167 | op = rtype_funct (inst); | |
1168 | switch (op) | |
1169 | { | |
1170 | case 8: /* JR */ | |
1171 | case 9: /* JALR */ | |
025bb325 | 1172 | /* Set PC to that address. */ |
0b1b3e42 | 1173 | pc = get_frame_register_signed (frame, rtype_rs (inst)); |
c5aa993b | 1174 | break; |
e38d4e1a DJ |
1175 | case 12: /* SYSCALL */ |
1176 | { | |
1177 | struct gdbarch_tdep *tdep; | |
1178 | ||
1179 | tdep = gdbarch_tdep (get_frame_arch (frame)); | |
1180 | if (tdep->syscall_next_pc != NULL) | |
1181 | pc = tdep->syscall_next_pc (frame); | |
1182 | else | |
1183 | pc += 4; | |
1184 | } | |
1185 | break; | |
c5aa993b JM |
1186 | default: |
1187 | pc += 4; | |
1188 | } | |
1189 | ||
6d82d43b | 1190 | break; /* end SPECIAL */ |
025bb325 | 1191 | case 1: /* REGIMM */ |
c906108c | 1192 | { |
e135b889 DJ |
1193 | op = itype_rt (inst); /* branch condition */ |
1194 | switch (op) | |
c906108c | 1195 | { |
c5aa993b | 1196 | case 0: /* BLTZ */ |
e135b889 DJ |
1197 | case 2: /* BLTZL */ |
1198 | case 16: /* BLTZAL */ | |
c5aa993b | 1199 | case 18: /* BLTZALL */ |
c906108c | 1200 | less_branch: |
0b1b3e42 | 1201 | if (get_frame_register_signed (frame, itype_rs (inst)) < 0) |
c5aa993b JM |
1202 | pc += mips32_relative_offset (inst) + 4; |
1203 | else | |
1204 | pc += 8; /* after the delay slot */ | |
1205 | break; | |
e135b889 | 1206 | case 1: /* BGEZ */ |
c5aa993b JM |
1207 | case 3: /* BGEZL */ |
1208 | case 17: /* BGEZAL */ | |
1209 | case 19: /* BGEZALL */ | |
0b1b3e42 | 1210 | if (get_frame_register_signed (frame, itype_rs (inst)) >= 0) |
c5aa993b JM |
1211 | pc += mips32_relative_offset (inst) + 4; |
1212 | else | |
1213 | pc += 8; /* after the delay slot */ | |
1214 | break; | |
e135b889 | 1215 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1216 | default: |
1217 | pc += 4; | |
c906108c SS |
1218 | } |
1219 | } | |
6d82d43b | 1220 | break; /* end REGIMM */ |
c5aa993b JM |
1221 | case 2: /* J */ |
1222 | case 3: /* JAL */ | |
1223 | { | |
1224 | unsigned long reg; | |
1225 | reg = jtype_target (inst) << 2; | |
025bb325 | 1226 | /* Upper four bits get never changed... */ |
5b652102 | 1227 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
c906108c | 1228 | } |
c5aa993b JM |
1229 | break; |
1230 | /* FIXME case JALX : */ | |
1231 | { | |
1232 | unsigned long reg; | |
1233 | reg = jtype_target (inst) << 2; | |
025bb325 | 1234 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + 1; /* yes, +1 */ |
c906108c SS |
1235 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1236 | } | |
c5aa993b | 1237 | break; /* The new PC will be alternate mode */ |
e135b889 | 1238 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1239 | equal_branch: |
0b1b3e42 UW |
1240 | if (get_frame_register_signed (frame, itype_rs (inst)) == |
1241 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1242 | pc += mips32_relative_offset (inst) + 4; |
1243 | else | |
1244 | pc += 8; | |
1245 | break; | |
e135b889 | 1246 | case 5: /* BNE, BNEL */ |
c5aa993b | 1247 | neq_branch: |
0b1b3e42 UW |
1248 | if (get_frame_register_signed (frame, itype_rs (inst)) != |
1249 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1250 | pc += mips32_relative_offset (inst) + 4; |
1251 | else | |
1252 | pc += 8; | |
1253 | break; | |
e135b889 | 1254 | case 6: /* BLEZ, BLEZL */ |
0b1b3e42 | 1255 | if (get_frame_register_signed (frame, itype_rs (inst)) <= 0) |
c5aa993b JM |
1256 | pc += mips32_relative_offset (inst) + 4; |
1257 | else | |
1258 | pc += 8; | |
1259 | break; | |
1260 | case 7: | |
e135b889 DJ |
1261 | default: |
1262 | greater_branch: /* BGTZ, BGTZL */ | |
0b1b3e42 | 1263 | if (get_frame_register_signed (frame, itype_rs (inst)) > 0) |
c5aa993b JM |
1264 | pc += mips32_relative_offset (inst) + 4; |
1265 | else | |
1266 | pc += 8; | |
1267 | break; | |
c5aa993b JM |
1268 | } /* switch */ |
1269 | } /* else */ | |
1270 | return pc; | |
1271 | } /* mips32_next_pc */ | |
c906108c SS |
1272 | |
1273 | /* Decoding the next place to set a breakpoint is irregular for the | |
025bb325 MS |
1274 | mips 16 variant, but fortunately, there fewer instructions. We have |
1275 | to cope ith extensions for 16 bit instructions and a pair of actual | |
1276 | 32 bit instructions. We dont want to set a single step instruction | |
1277 | on the extend instruction either. */ | |
c906108c SS |
1278 | |
1279 | /* Lots of mips16 instruction formats */ | |
1280 | /* Predicting jumps requires itype,ritype,i8type | |
025bb325 | 1281 | and their extensions extItype,extritype,extI8type. */ |
c906108c SS |
1282 | enum mips16_inst_fmts |
1283 | { | |
c5aa993b JM |
1284 | itype, /* 0 immediate 5,10 */ |
1285 | ritype, /* 1 5,3,8 */ | |
1286 | rrtype, /* 2 5,3,3,5 */ | |
1287 | rritype, /* 3 5,3,3,5 */ | |
1288 | rrrtype, /* 4 5,3,3,3,2 */ | |
1289 | rriatype, /* 5 5,3,3,1,4 */ | |
1290 | shifttype, /* 6 5,3,3,3,2 */ | |
1291 | i8type, /* 7 5,3,8 */ | |
1292 | i8movtype, /* 8 5,3,3,5 */ | |
1293 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1294 | i64type, /* 10 5,3,8 */ | |
1295 | ri64type, /* 11 5,3,3,5 */ | |
1296 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1297 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1298 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1299 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1300 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1301 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1302 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1303 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1304 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1305 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1306 | }; | |
12f02c2a | 1307 | /* I am heaping all the fields of the formats into one structure and |
025bb325 | 1308 | then, only the fields which are involved in instruction extension. */ |
c906108c | 1309 | struct upk_mips16 |
6d82d43b AC |
1310 | { |
1311 | CORE_ADDR offset; | |
025bb325 | 1312 | unsigned int regx; /* Function in i8 type. */ |
6d82d43b AC |
1313 | unsigned int regy; |
1314 | }; | |
c906108c SS |
1315 | |
1316 | ||
12f02c2a | 1317 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
c68cf8ad | 1318 | for the bits which make up the immediate extension. */ |
c906108c | 1319 | |
12f02c2a AC |
1320 | static CORE_ADDR |
1321 | extended_offset (unsigned int extension) | |
c906108c | 1322 | { |
12f02c2a | 1323 | CORE_ADDR value; |
c5aa993b JM |
1324 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1325 | value = value << 6; | |
025bb325 | 1326 | value |= (extension >> 16) & 0x1f; /* extract 10:5 */ |
c5aa993b JM |
1327 | value = value << 5; |
1328 | value |= extension & 0x01f; /* extract 4:0 */ | |
1329 | return value; | |
c906108c SS |
1330 | } |
1331 | ||
1332 | /* Only call this function if you know that this is an extendable | |
bcf1ea1e MR |
1333 | instruction. It won't malfunction, but why make excess remote memory |
1334 | references? If the immediate operands get sign extended or something, | |
1335 | do it after the extension is performed. */ | |
c906108c | 1336 | /* FIXME: Every one of these cases needs to worry about sign extension |
bcf1ea1e | 1337 | when the offset is to be used in relative addressing. */ |
c906108c | 1338 | |
12f02c2a | 1339 | static unsigned int |
e17a4113 | 1340 | fetch_mips_16 (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 1341 | { |
e17a4113 | 1342 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 1343 | gdb_byte buf[8]; |
025bb325 | 1344 | pc &= 0xfffffffe; /* Clear the low order bit. */ |
c5aa993b | 1345 | target_read_memory (pc, buf, 2); |
e17a4113 | 1346 | return extract_unsigned_integer (buf, 2, byte_order); |
c906108c SS |
1347 | } |
1348 | ||
1349 | static void | |
e17a4113 | 1350 | unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc, |
12f02c2a AC |
1351 | unsigned int extension, |
1352 | unsigned int inst, | |
6d82d43b | 1353 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 1354 | { |
12f02c2a AC |
1355 | CORE_ADDR offset; |
1356 | int regx; | |
1357 | int regy; | |
1358 | switch (insn_format) | |
c906108c | 1359 | { |
c5aa993b | 1360 | case itype: |
c906108c | 1361 | { |
12f02c2a AC |
1362 | CORE_ADDR value; |
1363 | if (extension) | |
c5aa993b JM |
1364 | { |
1365 | value = extended_offset (extension); | |
1366 | value = value << 11; /* rom for the original value */ | |
6d82d43b | 1367 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1368 | } |
1369 | else | |
c5aa993b | 1370 | { |
12f02c2a | 1371 | value = inst & 0x7ff; |
025bb325 | 1372 | /* FIXME : Consider sign extension. */ |
c906108c | 1373 | } |
12f02c2a AC |
1374 | offset = value; |
1375 | regx = -1; | |
1376 | regy = -1; | |
c906108c | 1377 | } |
c5aa993b JM |
1378 | break; |
1379 | case ritype: | |
1380 | case i8type: | |
025bb325 | 1381 | { /* A register identifier and an offset. */ |
c906108c | 1382 | /* Most of the fields are the same as I type but the |
025bb325 | 1383 | immediate value is of a different length. */ |
12f02c2a AC |
1384 | CORE_ADDR value; |
1385 | if (extension) | |
c906108c | 1386 | { |
c5aa993b | 1387 | value = extended_offset (extension); |
025bb325 | 1388 | value = value << 8; /* from the original instruction */ |
12f02c2a AC |
1389 | value |= inst & 0xff; /* eleven bits from instruction */ |
1390 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
025bb325 | 1391 | if (value & 0x4000) /* Test the sign bit, bit 26. */ |
c5aa993b | 1392 | { |
025bb325 | 1393 | value &= ~0x3fff; /* Remove the sign bit. */ |
c5aa993b | 1394 | value = -value; |
c906108c SS |
1395 | } |
1396 | } | |
c5aa993b JM |
1397 | else |
1398 | { | |
12f02c2a AC |
1399 | value = inst & 0xff; /* 8 bits */ |
1400 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
025bb325 MS |
1401 | /* FIXME: Do sign extension, this format needs it. */ |
1402 | if (value & 0x80) /* THIS CONFUSES ME. */ | |
c5aa993b | 1403 | { |
025bb325 | 1404 | value &= 0xef; /* Remove the sign bit. */ |
c5aa993b JM |
1405 | value = -value; |
1406 | } | |
c5aa993b | 1407 | } |
12f02c2a AC |
1408 | offset = value; |
1409 | regy = -1; | |
c5aa993b | 1410 | break; |
c906108c | 1411 | } |
c5aa993b | 1412 | case jalxtype: |
c906108c | 1413 | { |
c5aa993b | 1414 | unsigned long value; |
12f02c2a AC |
1415 | unsigned int nexthalf; |
1416 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b | 1417 | value = value << 16; |
025bb325 MS |
1418 | nexthalf = mips_fetch_instruction (gdbarch, pc + 2); /* low bit |
1419 | still set. */ | |
c5aa993b | 1420 | value |= nexthalf; |
12f02c2a AC |
1421 | offset = value; |
1422 | regx = -1; | |
1423 | regy = -1; | |
c5aa993b | 1424 | break; |
c906108c SS |
1425 | } |
1426 | default: | |
e2e0b3e5 | 1427 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c | 1428 | } |
12f02c2a AC |
1429 | upk->offset = offset; |
1430 | upk->regx = regx; | |
1431 | upk->regy = regy; | |
c906108c SS |
1432 | } |
1433 | ||
1434 | ||
c5aa993b JM |
1435 | static CORE_ADDR |
1436 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1437 | { |
5b652102 | 1438 | return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff))); |
c906108c SS |
1439 | } |
1440 | ||
12f02c2a | 1441 | static CORE_ADDR |
0b1b3e42 | 1442 | extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc, |
6d82d43b | 1443 | unsigned int extension, unsigned int insn) |
c906108c | 1444 | { |
e17a4113 | 1445 | struct gdbarch *gdbarch = get_frame_arch (frame); |
12f02c2a AC |
1446 | int op = (insn >> 11); |
1447 | switch (op) | |
c906108c | 1448 | { |
6d82d43b | 1449 | case 2: /* Branch */ |
12f02c2a AC |
1450 | { |
1451 | CORE_ADDR offset; | |
1452 | struct upk_mips16 upk; | |
e17a4113 | 1453 | unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk); |
12f02c2a AC |
1454 | offset = upk.offset; |
1455 | if (offset & 0x800) | |
1456 | { | |
1457 | offset &= 0xeff; | |
1458 | offset = -offset; | |
1459 | } | |
1460 | pc += (offset << 1) + 2; | |
1461 | break; | |
1462 | } | |
025bb325 MS |
1463 | case 3: /* JAL , JALX - Watch out, these are 32 bit |
1464 | instructions. */ | |
12f02c2a AC |
1465 | { |
1466 | struct upk_mips16 upk; | |
e17a4113 | 1467 | unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk); |
12f02c2a AC |
1468 | pc = add_offset_16 (pc, upk.offset); |
1469 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
025bb325 | 1470 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode. */ |
12f02c2a AC |
1471 | else |
1472 | pc |= 0x01; | |
1473 | break; | |
1474 | } | |
6d82d43b | 1475 | case 4: /* beqz */ |
12f02c2a AC |
1476 | { |
1477 | struct upk_mips16 upk; | |
1478 | int reg; | |
e17a4113 | 1479 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
0b1b3e42 | 1480 | reg = get_frame_register_signed (frame, upk.regx); |
12f02c2a AC |
1481 | if (reg == 0) |
1482 | pc += (upk.offset << 1) + 2; | |
1483 | else | |
1484 | pc += 2; | |
1485 | break; | |
1486 | } | |
6d82d43b | 1487 | case 5: /* bnez */ |
12f02c2a AC |
1488 | { |
1489 | struct upk_mips16 upk; | |
1490 | int reg; | |
e17a4113 | 1491 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
0b1b3e42 | 1492 | reg = get_frame_register_signed (frame, upk.regx); |
12f02c2a AC |
1493 | if (reg != 0) |
1494 | pc += (upk.offset << 1) + 2; | |
1495 | else | |
1496 | pc += 2; | |
1497 | break; | |
1498 | } | |
6d82d43b | 1499 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
1500 | { |
1501 | struct upk_mips16 upk; | |
1502 | int reg; | |
e17a4113 | 1503 | unpack_mips16 (gdbarch, pc, extension, insn, i8type, &upk); |
12f02c2a | 1504 | /* upk.regx contains the opcode */ |
0b1b3e42 | 1505 | reg = get_frame_register_signed (frame, 24); /* Test register is 24 */ |
12f02c2a AC |
1506 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ |
1507 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1508 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1509 | pc += (upk.offset << 1) + 2; | |
1510 | else | |
1511 | pc += 2; | |
1512 | break; | |
1513 | } | |
6d82d43b | 1514 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
1515 | { |
1516 | struct upk_mips16 upk; | |
1517 | /* upk.fmt = rrtype; */ | |
1518 | op = insn & 0x1f; | |
1519 | if (op == 0) | |
c5aa993b | 1520 | { |
12f02c2a AC |
1521 | int reg; |
1522 | upk.regx = (insn >> 8) & 0x07; | |
1523 | upk.regy = (insn >> 5) & 0x07; | |
1524 | switch (upk.regy) | |
c5aa993b | 1525 | { |
12f02c2a AC |
1526 | case 0: |
1527 | reg = upk.regx; | |
1528 | break; | |
1529 | case 1: | |
1530 | reg = 31; | |
025bb325 | 1531 | break; /* Function return instruction. */ |
12f02c2a AC |
1532 | case 2: |
1533 | reg = upk.regx; | |
1534 | break; | |
1535 | default: | |
1536 | reg = 31; | |
6d82d43b | 1537 | break; /* BOGUS Guess */ |
c906108c | 1538 | } |
0b1b3e42 | 1539 | pc = get_frame_register_signed (frame, reg); |
c906108c | 1540 | } |
12f02c2a | 1541 | else |
c5aa993b | 1542 | pc += 2; |
12f02c2a AC |
1543 | break; |
1544 | } | |
1545 | case 30: | |
1546 | /* This is an instruction extension. Fetch the real instruction | |
1547 | (which follows the extension) and decode things based on | |
025bb325 | 1548 | that. */ |
12f02c2a AC |
1549 | { |
1550 | pc += 2; | |
e17a4113 UW |
1551 | pc = extended_mips16_next_pc (frame, pc, insn, |
1552 | fetch_mips_16 (gdbarch, pc)); | |
12f02c2a AC |
1553 | break; |
1554 | } | |
1555 | default: | |
1556 | { | |
1557 | pc += 2; | |
1558 | break; | |
1559 | } | |
c906108c | 1560 | } |
c5aa993b | 1561 | return pc; |
12f02c2a | 1562 | } |
c906108c | 1563 | |
5a89d8aa | 1564 | static CORE_ADDR |
0b1b3e42 | 1565 | mips16_next_pc (struct frame_info *frame, CORE_ADDR pc) |
12f02c2a | 1566 | { |
e17a4113 UW |
1567 | struct gdbarch *gdbarch = get_frame_arch (frame); |
1568 | unsigned int insn = fetch_mips_16 (gdbarch, pc); | |
0b1b3e42 | 1569 | return extended_mips16_next_pc (frame, pc, 0, insn); |
12f02c2a AC |
1570 | } |
1571 | ||
1572 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1573 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a | 1574 | It works by decoding the current instruction and predicting where a |
025bb325 | 1575 | branch will go. This isnt hard because all the data is available. |
ce1f96de | 1576 | The MIPS32 and MIPS16 variants are quite different. */ |
ad527d2e | 1577 | static CORE_ADDR |
0b1b3e42 | 1578 | mips_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 1579 | { |
ce1f96de | 1580 | if (is_mips16_addr (pc)) |
0b1b3e42 | 1581 | return mips16_next_pc (frame, pc); |
c5aa993b | 1582 | else |
0b1b3e42 | 1583 | return mips32_next_pc (frame, pc); |
12f02c2a | 1584 | } |
c906108c | 1585 | |
edfae063 AC |
1586 | struct mips_frame_cache |
1587 | { | |
1588 | CORE_ADDR base; | |
1589 | struct trad_frame_saved_reg *saved_regs; | |
1590 | }; | |
1591 | ||
29639122 JB |
1592 | /* Set a register's saved stack address in temp_saved_regs. If an |
1593 | address has already been set for this register, do nothing; this | |
1594 | way we will only recognize the first save of a given register in a | |
1595 | function prologue. | |
eec63939 | 1596 | |
f57d151a UW |
1597 | For simplicity, save the address in both [0 .. gdbarch_num_regs) and |
1598 | [gdbarch_num_regs .. 2*gdbarch_num_regs). | |
1599 | Strictly speaking, only the second range is used as it is only second | |
1600 | range (the ABI instead of ISA registers) that comes into play when finding | |
1601 | saved registers in a frame. */ | |
eec63939 AC |
1602 | |
1603 | static void | |
74ed0bb4 MD |
1604 | set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache, |
1605 | int regnum, CORE_ADDR offset) | |
eec63939 | 1606 | { |
29639122 JB |
1607 | if (this_cache != NULL |
1608 | && this_cache->saved_regs[regnum].addr == -1) | |
1609 | { | |
74ed0bb4 MD |
1610 | this_cache->saved_regs[regnum + 0 * gdbarch_num_regs (gdbarch)].addr |
1611 | = offset; | |
1612 | this_cache->saved_regs[regnum + 1 * gdbarch_num_regs (gdbarch)].addr | |
1613 | = offset; | |
29639122 | 1614 | } |
eec63939 AC |
1615 | } |
1616 | ||
eec63939 | 1617 | |
29639122 JB |
1618 | /* Fetch the immediate value from a MIPS16 instruction. |
1619 | If the previous instruction was an EXTEND, use it to extend | |
1620 | the upper bits of the immediate value. This is a helper function | |
1621 | for mips16_scan_prologue. */ | |
eec63939 | 1622 | |
29639122 JB |
1623 | static int |
1624 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ | |
1625 | unsigned short inst, /* current instruction */ | |
1626 | int nbits, /* number of bits in imm field */ | |
1627 | int scale, /* scale factor to be applied to imm */ | |
025bb325 | 1628 | int is_signed) /* is the imm field signed? */ |
eec63939 | 1629 | { |
29639122 | 1630 | int offset; |
eec63939 | 1631 | |
29639122 JB |
1632 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
1633 | { | |
1634 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
1635 | if (offset & 0x8000) /* check for negative extend */ | |
1636 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
1637 | return offset | (inst & 0x1f); | |
1638 | } | |
eec63939 | 1639 | else |
29639122 JB |
1640 | { |
1641 | int max_imm = 1 << nbits; | |
1642 | int mask = max_imm - 1; | |
1643 | int sign_bit = max_imm >> 1; | |
45c9dd44 | 1644 | |
29639122 JB |
1645 | offset = inst & mask; |
1646 | if (is_signed && (offset & sign_bit)) | |
1647 | offset = 0 - (max_imm - offset); | |
1648 | return offset * scale; | |
1649 | } | |
1650 | } | |
eec63939 | 1651 | |
65596487 | 1652 | |
29639122 JB |
1653 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1654 | the associated FRAME_CACHE if not null. | |
1655 | Return the address of the first instruction past the prologue. */ | |
eec63939 | 1656 | |
29639122 | 1657 | static CORE_ADDR |
e17a4113 UW |
1658 | mips16_scan_prologue (struct gdbarch *gdbarch, |
1659 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 1660 | struct frame_info *this_frame, |
29639122 JB |
1661 | struct mips_frame_cache *this_cache) |
1662 | { | |
1663 | CORE_ADDR cur_pc; | |
025bb325 | 1664 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer. */ |
29639122 JB |
1665 | CORE_ADDR sp; |
1666 | long frame_offset = 0; /* Size of stack frame. */ | |
1667 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
1668 | int frame_reg = MIPS_SP_REGNUM; | |
025bb325 | 1669 | unsigned short prev_inst = 0; /* saved copy of previous instruction. */ |
29639122 JB |
1670 | unsigned inst = 0; /* current instruction */ |
1671 | unsigned entry_inst = 0; /* the entry instruction */ | |
2207132d | 1672 | unsigned save_inst = 0; /* the save instruction */ |
29639122 | 1673 | int reg, offset; |
a343eb3c | 1674 | |
29639122 JB |
1675 | int extend_bytes = 0; |
1676 | int prev_extend_bytes; | |
1677 | CORE_ADDR end_prologue_addr = 0; | |
a343eb3c | 1678 | |
29639122 | 1679 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
1680 | THIS_FRAME. */ |
1681 | if (this_frame != NULL) | |
1682 | sp = get_frame_register_signed (this_frame, | |
1683 | gdbarch_num_regs (gdbarch) | |
1684 | + MIPS_SP_REGNUM); | |
29639122 JB |
1685 | else |
1686 | sp = 0; | |
eec63939 | 1687 | |
29639122 JB |
1688 | if (limit_pc > start_pc + 200) |
1689 | limit_pc = start_pc + 200; | |
eec63939 | 1690 | |
95ac2dcf | 1691 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) |
29639122 JB |
1692 | { |
1693 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1694 | the immediate offset extension from it in mips16_get_imm. */ | |
1695 | prev_inst = inst; | |
eec63939 | 1696 | |
025bb325 | 1697 | /* Fetch and decode the instruction. */ |
e17a4113 | 1698 | inst = (unsigned short) mips_fetch_instruction (gdbarch, cur_pc); |
eec63939 | 1699 | |
29639122 JB |
1700 | /* Normally we ignore extend instructions. However, if it is |
1701 | not followed by a valid prologue instruction, then this | |
1702 | instruction is not part of the prologue either. We must | |
1703 | remember in this case to adjust the end_prologue_addr back | |
1704 | over the extend. */ | |
1705 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
1706 | { | |
95ac2dcf | 1707 | extend_bytes = MIPS_INSN16_SIZE; |
29639122 JB |
1708 | continue; |
1709 | } | |
eec63939 | 1710 | |
29639122 JB |
1711 | prev_extend_bytes = extend_bytes; |
1712 | extend_bytes = 0; | |
eec63939 | 1713 | |
29639122 JB |
1714 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
1715 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1716 | { | |
1717 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
025bb325 | 1718 | if (offset < 0) /* Negative stack adjustment? */ |
29639122 JB |
1719 | frame_offset -= offset; |
1720 | else | |
1721 | /* Exit loop if a positive stack adjustment is found, which | |
1722 | usually means that the stack cleanup code in the function | |
1723 | epilogue is reached. */ | |
1724 | break; | |
1725 | } | |
1726 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
1727 | { | |
1728 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1729 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
74ed0bb4 | 1730 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
1731 | } |
1732 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
1733 | { | |
1734 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1735 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1736 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
1737 | } |
1738 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
1739 | { | |
1740 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
74ed0bb4 | 1741 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1742 | } |
1743 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
1744 | { | |
1745 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
74ed0bb4 | 1746 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1747 | } |
1748 | else if (inst == 0x673d) /* move $s1, $sp */ | |
1749 | { | |
1750 | frame_addr = sp; | |
1751 | frame_reg = 17; | |
1752 | } | |
1753 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
1754 | { | |
1755 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1756 | frame_addr = sp + offset; | |
1757 | frame_reg = 17; | |
1758 | frame_adjust = offset; | |
1759 | } | |
1760 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
1761 | { | |
1762 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
1763 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1764 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
1765 | } |
1766 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
1767 | { | |
1768 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1769 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1770 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
1771 | } |
1772 | else if ((inst & 0xf81f) == 0xe809 | |
1773 | && (inst & 0x700) != 0x700) /* entry */ | |
025bb325 | 1774 | entry_inst = inst; /* Save for later processing. */ |
2207132d MR |
1775 | else if ((inst & 0xff80) == 0x6480) /* save */ |
1776 | { | |
025bb325 | 1777 | save_inst = inst; /* Save for later processing. */ |
2207132d MR |
1778 | if (prev_extend_bytes) /* extend */ |
1779 | save_inst |= prev_inst << 16; | |
1780 | } | |
29639122 | 1781 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
95ac2dcf | 1782 | cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ |
29639122 JB |
1783 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
1784 | { | |
1785 | /* This instruction is part of the prologue, but we don't | |
1786 | need to do anything special to handle it. */ | |
1787 | } | |
1788 | else | |
1789 | { | |
1790 | /* This instruction is not an instruction typically found | |
1791 | in a prologue, so we must have reached the end of the | |
1792 | prologue. */ | |
1793 | if (end_prologue_addr == 0) | |
1794 | end_prologue_addr = cur_pc - prev_extend_bytes; | |
1795 | } | |
1796 | } | |
eec63939 | 1797 | |
29639122 JB |
1798 | /* The entry instruction is typically the first instruction in a function, |
1799 | and it stores registers at offsets relative to the value of the old SP | |
1800 | (before the prologue). But the value of the sp parameter to this | |
1801 | function is the new SP (after the prologue has been executed). So we | |
1802 | can't calculate those offsets until we've seen the entire prologue, | |
025bb325 | 1803 | and can calculate what the old SP must have been. */ |
29639122 JB |
1804 | if (entry_inst != 0) |
1805 | { | |
1806 | int areg_count = (entry_inst >> 8) & 7; | |
1807 | int sreg_count = (entry_inst >> 6) & 3; | |
eec63939 | 1808 | |
29639122 JB |
1809 | /* The entry instruction always subtracts 32 from the SP. */ |
1810 | frame_offset += 32; | |
1811 | ||
1812 | /* Now we can calculate what the SP must have been at the | |
1813 | start of the function prologue. */ | |
1814 | sp += frame_offset; | |
1815 | ||
1816 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
1817 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
1818 | { | |
74ed0bb4 | 1819 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 1820 | offset += mips_abi_regsize (gdbarch); |
29639122 JB |
1821 | } |
1822 | ||
1823 | /* Check if the ra register was pushed on the stack. */ | |
1824 | offset = -4; | |
1825 | if (entry_inst & 0x20) | |
1826 | { | |
74ed0bb4 | 1827 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
72a155b4 | 1828 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
1829 | } |
1830 | ||
1831 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
1832 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1833 | { | |
74ed0bb4 | 1834 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 1835 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
1836 | } |
1837 | } | |
1838 | ||
2207132d MR |
1839 | /* The SAVE instruction is similar to ENTRY, except that defined by the |
1840 | MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the | |
1841 | size of the frame is specified as an immediate field of instruction | |
1842 | and an extended variation exists which lets additional registers and | |
1843 | frame space to be specified. The instruction always treats registers | |
1844 | as 32-bit so its usefulness for 64-bit ABIs is questionable. */ | |
1845 | if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4) | |
1846 | { | |
1847 | static int args_table[16] = { | |
1848 | 0, 0, 0, 0, 1, 1, 1, 1, | |
1849 | 2, 2, 2, 0, 3, 3, 4, -1, | |
1850 | }; | |
1851 | static int astatic_table[16] = { | |
1852 | 0, 1, 2, 3, 0, 1, 2, 3, | |
1853 | 0, 1, 2, 4, 0, 1, 0, -1, | |
1854 | }; | |
1855 | int aregs = (save_inst >> 16) & 0xf; | |
1856 | int xsregs = (save_inst >> 24) & 0x7; | |
1857 | int args = args_table[aregs]; | |
1858 | int astatic = astatic_table[aregs]; | |
1859 | long frame_size; | |
1860 | ||
1861 | if (args < 0) | |
1862 | { | |
1863 | warning (_("Invalid number of argument registers encoded in SAVE.")); | |
1864 | args = 0; | |
1865 | } | |
1866 | if (astatic < 0) | |
1867 | { | |
1868 | warning (_("Invalid number of static registers encoded in SAVE.")); | |
1869 | astatic = 0; | |
1870 | } | |
1871 | ||
1872 | /* For standard SAVE the frame size of 0 means 128. */ | |
1873 | frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf); | |
1874 | if (frame_size == 0 && (save_inst >> 16) == 0) | |
1875 | frame_size = 16; | |
1876 | frame_size *= 8; | |
1877 | frame_offset += frame_size; | |
1878 | ||
1879 | /* Now we can calculate what the SP must have been at the | |
1880 | start of the function prologue. */ | |
1881 | sp += frame_offset; | |
1882 | ||
1883 | /* Check if A0-A3 were saved in the caller's argument save area. */ | |
1884 | for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++) | |
1885 | { | |
74ed0bb4 | 1886 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1887 | offset += mips_abi_regsize (gdbarch); |
1888 | } | |
1889 | ||
1890 | offset = -4; | |
1891 | ||
1892 | /* Check if the RA register was pushed on the stack. */ | |
1893 | if (save_inst & 0x40) | |
1894 | { | |
74ed0bb4 | 1895 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
2207132d MR |
1896 | offset -= mips_abi_regsize (gdbarch); |
1897 | } | |
1898 | ||
1899 | /* Check if the S8 register was pushed on the stack. */ | |
1900 | if (xsregs > 6) | |
1901 | { | |
74ed0bb4 | 1902 | set_reg_offset (gdbarch, this_cache, 30, sp + offset); |
2207132d MR |
1903 | offset -= mips_abi_regsize (gdbarch); |
1904 | xsregs--; | |
1905 | } | |
1906 | /* Check if S2-S7 were pushed on the stack. */ | |
1907 | for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--) | |
1908 | { | |
74ed0bb4 | 1909 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1910 | offset -= mips_abi_regsize (gdbarch); |
1911 | } | |
1912 | ||
1913 | /* Check if the S1 register was pushed on the stack. */ | |
1914 | if (save_inst & 0x10) | |
1915 | { | |
74ed0bb4 | 1916 | set_reg_offset (gdbarch, this_cache, 17, sp + offset); |
2207132d MR |
1917 | offset -= mips_abi_regsize (gdbarch); |
1918 | } | |
1919 | /* Check if the S0 register was pushed on the stack. */ | |
1920 | if (save_inst & 0x20) | |
1921 | { | |
74ed0bb4 | 1922 | set_reg_offset (gdbarch, this_cache, 16, sp + offset); |
2207132d MR |
1923 | offset -= mips_abi_regsize (gdbarch); |
1924 | } | |
1925 | ||
1926 | /* Check if A0-A3 were pushed on the stack. */ | |
1927 | for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--) | |
1928 | { | |
74ed0bb4 | 1929 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1930 | offset -= mips_abi_regsize (gdbarch); |
1931 | } | |
1932 | } | |
1933 | ||
29639122 JB |
1934 | if (this_cache != NULL) |
1935 | { | |
1936 | this_cache->base = | |
b8a22b94 DJ |
1937 | (get_frame_register_signed (this_frame, |
1938 | gdbarch_num_regs (gdbarch) + frame_reg) | |
29639122 JB |
1939 | + frame_offset - frame_adjust); |
1940 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should | |
025bb325 | 1941 | be able to get rid of the assignment below, evetually. But it's |
29639122 | 1942 | still needed for now. */ |
72a155b4 UW |
1943 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
1944 | + mips_regnum (gdbarch)->pc] | |
1945 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; | |
29639122 JB |
1946 | } |
1947 | ||
1948 | /* If we didn't reach the end of the prologue when scanning the function | |
1949 | instructions, then set end_prologue_addr to the address of the | |
1950 | instruction immediately after the last one we scanned. */ | |
1951 | if (end_prologue_addr == 0) | |
1952 | end_prologue_addr = cur_pc; | |
1953 | ||
1954 | return end_prologue_addr; | |
eec63939 AC |
1955 | } |
1956 | ||
29639122 JB |
1957 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). |
1958 | Procedures that use the 32-bit instruction set are handled by the | |
1959 | mips_insn32 unwinder. */ | |
1960 | ||
1961 | static struct mips_frame_cache * | |
b8a22b94 | 1962 | mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache) |
eec63939 | 1963 | { |
e17a4113 | 1964 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 1965 | struct mips_frame_cache *cache; |
eec63939 AC |
1966 | |
1967 | if ((*this_cache) != NULL) | |
1968 | return (*this_cache); | |
29639122 JB |
1969 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
1970 | (*this_cache) = cache; | |
b8a22b94 | 1971 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
eec63939 | 1972 | |
29639122 JB |
1973 | /* Analyze the function prologue. */ |
1974 | { | |
b8a22b94 | 1975 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 1976 | CORE_ADDR start_addr; |
eec63939 | 1977 | |
29639122 JB |
1978 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
1979 | if (start_addr == 0) | |
e17a4113 | 1980 | start_addr = heuristic_proc_start (gdbarch, pc); |
29639122 JB |
1981 | /* We can't analyze the prologue if we couldn't find the begining |
1982 | of the function. */ | |
1983 | if (start_addr == 0) | |
1984 | return cache; | |
eec63939 | 1985 | |
e17a4113 | 1986 | mips16_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); |
29639122 JB |
1987 | } |
1988 | ||
3e8c568d | 1989 | /* gdbarch_sp_regnum contains the value and not the address. */ |
72a155b4 | 1990 | trad_frame_set_value (cache->saved_regs, |
e17a4113 | 1991 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
72a155b4 | 1992 | cache->base); |
eec63939 | 1993 | |
29639122 | 1994 | return (*this_cache); |
eec63939 AC |
1995 | } |
1996 | ||
1997 | static void | |
b8a22b94 | 1998 | mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 | 1999 | struct frame_id *this_id) |
eec63939 | 2000 | { |
b8a22b94 | 2001 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 | 2002 | this_cache); |
21327321 DJ |
2003 | /* This marks the outermost frame. */ |
2004 | if (info->base == 0) | |
2005 | return; | |
b8a22b94 | 2006 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
eec63939 AC |
2007 | } |
2008 | ||
b8a22b94 DJ |
2009 | static struct value * |
2010 | mips_insn16_frame_prev_register (struct frame_info *this_frame, | |
2011 | void **this_cache, int regnum) | |
eec63939 | 2012 | { |
b8a22b94 | 2013 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 | 2014 | this_cache); |
b8a22b94 DJ |
2015 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
2016 | } | |
2017 | ||
2018 | static int | |
2019 | mips_insn16_frame_sniffer (const struct frame_unwind *self, | |
2020 | struct frame_info *this_frame, void **this_cache) | |
2021 | { | |
2022 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2023 | if (mips_pc_is_mips16 (pc)) | |
2024 | return 1; | |
2025 | return 0; | |
eec63939 AC |
2026 | } |
2027 | ||
29639122 | 2028 | static const struct frame_unwind mips_insn16_frame_unwind = |
eec63939 AC |
2029 | { |
2030 | NORMAL_FRAME, | |
8fbca658 | 2031 | default_frame_unwind_stop_reason, |
29639122 | 2032 | mips_insn16_frame_this_id, |
b8a22b94 DJ |
2033 | mips_insn16_frame_prev_register, |
2034 | NULL, | |
2035 | mips_insn16_frame_sniffer | |
eec63939 AC |
2036 | }; |
2037 | ||
eec63939 | 2038 | static CORE_ADDR |
b8a22b94 | 2039 | mips_insn16_frame_base_address (struct frame_info *this_frame, |
29639122 | 2040 | void **this_cache) |
eec63939 | 2041 | { |
b8a22b94 | 2042 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 JB |
2043 | this_cache); |
2044 | return info->base; | |
eec63939 AC |
2045 | } |
2046 | ||
29639122 | 2047 | static const struct frame_base mips_insn16_frame_base = |
eec63939 | 2048 | { |
29639122 JB |
2049 | &mips_insn16_frame_unwind, |
2050 | mips_insn16_frame_base_address, | |
2051 | mips_insn16_frame_base_address, | |
2052 | mips_insn16_frame_base_address | |
eec63939 AC |
2053 | }; |
2054 | ||
2055 | static const struct frame_base * | |
b8a22b94 | 2056 | mips_insn16_frame_base_sniffer (struct frame_info *this_frame) |
eec63939 | 2057 | { |
b8a22b94 DJ |
2058 | CORE_ADDR pc = get_frame_pc (this_frame); |
2059 | if (mips_pc_is_mips16 (pc)) | |
29639122 | 2060 | return &mips_insn16_frame_base; |
eec63939 AC |
2061 | else |
2062 | return NULL; | |
edfae063 AC |
2063 | } |
2064 | ||
29639122 JB |
2065 | /* Mark all the registers as unset in the saved_regs array |
2066 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
2067 | ||
74ed0bb4 MD |
2068 | static void |
2069 | reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache) | |
c906108c | 2070 | { |
29639122 JB |
2071 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
2072 | return; | |
2073 | ||
2074 | { | |
74ed0bb4 | 2075 | const int num_regs = gdbarch_num_regs (gdbarch); |
29639122 | 2076 | int i; |
64159455 | 2077 | |
29639122 JB |
2078 | for (i = 0; i < num_regs; i++) |
2079 | { | |
2080 | this_cache->saved_regs[i].addr = -1; | |
2081 | } | |
2082 | } | |
c906108c SS |
2083 | } |
2084 | ||
025bb325 | 2085 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
29639122 JB |
2086 | the associated FRAME_CACHE if not null. |
2087 | Return the address of the first instruction past the prologue. */ | |
c906108c | 2088 | |
875e1767 | 2089 | static CORE_ADDR |
e17a4113 UW |
2090 | mips32_scan_prologue (struct gdbarch *gdbarch, |
2091 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 2092 | struct frame_info *this_frame, |
29639122 | 2093 | struct mips_frame_cache *this_cache) |
c906108c | 2094 | { |
29639122 | 2095 | CORE_ADDR cur_pc; |
025bb325 MS |
2096 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for |
2097 | frame-pointer. */ | |
29639122 JB |
2098 | CORE_ADDR sp; |
2099 | long frame_offset; | |
2100 | int frame_reg = MIPS_SP_REGNUM; | |
8fa9cfa1 | 2101 | |
29639122 JB |
2102 | CORE_ADDR end_prologue_addr = 0; |
2103 | int seen_sp_adjust = 0; | |
2104 | int load_immediate_bytes = 0; | |
db5f024e | 2105 | int in_delay_slot = 0; |
7d1e6fb8 | 2106 | int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8); |
8fa9cfa1 | 2107 | |
29639122 | 2108 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
2109 | THIS_FRAME. */ |
2110 | if (this_frame != NULL) | |
2111 | sp = get_frame_register_signed (this_frame, | |
2112 | gdbarch_num_regs (gdbarch) | |
2113 | + MIPS_SP_REGNUM); | |
8fa9cfa1 | 2114 | else |
29639122 | 2115 | sp = 0; |
9022177c | 2116 | |
29639122 JB |
2117 | if (limit_pc > start_pc + 200) |
2118 | limit_pc = start_pc + 200; | |
9022177c | 2119 | |
29639122 | 2120 | restart: |
9022177c | 2121 | |
29639122 | 2122 | frame_offset = 0; |
95ac2dcf | 2123 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) |
9022177c | 2124 | { |
29639122 JB |
2125 | unsigned long inst, high_word, low_word; |
2126 | int reg; | |
9022177c | 2127 | |
025bb325 | 2128 | /* Fetch the instruction. */ |
e17a4113 | 2129 | inst = (unsigned long) mips_fetch_instruction (gdbarch, cur_pc); |
9022177c | 2130 | |
29639122 JB |
2131 | /* Save some code by pre-extracting some useful fields. */ |
2132 | high_word = (inst >> 16) & 0xffff; | |
2133 | low_word = inst & 0xffff; | |
2134 | reg = high_word & 0x1f; | |
fe29b929 | 2135 | |
025bb325 | 2136 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
29639122 JB |
2137 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
2138 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
2139 | { | |
025bb325 | 2140 | if (low_word & 0x8000) /* Negative stack adjustment? */ |
29639122 JB |
2141 | frame_offset += 0x10000 - low_word; |
2142 | else | |
2143 | /* Exit loop if a positive stack adjustment is found, which | |
2144 | usually means that the stack cleanup code in the function | |
2145 | epilogue is reached. */ | |
2146 | break; | |
2147 | seen_sp_adjust = 1; | |
2148 | } | |
7d1e6fb8 KB |
2149 | else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ |
2150 | && !regsize_is_64_bits) | |
29639122 | 2151 | { |
74ed0bb4 | 2152 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
29639122 | 2153 | } |
7d1e6fb8 KB |
2154 | else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ |
2155 | && regsize_is_64_bits) | |
29639122 JB |
2156 | { |
2157 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ | |
74ed0bb4 | 2158 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
29639122 JB |
2159 | } |
2160 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
2161 | { | |
2162 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
2163 | if ((long) low_word != frame_offset) | |
2164 | frame_addr = sp + low_word; | |
b8a22b94 | 2165 | else if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
2166 | { |
2167 | unsigned alloca_adjust; | |
a4b8ebc8 | 2168 | |
29639122 | 2169 | frame_reg = 30; |
b8a22b94 DJ |
2170 | frame_addr = get_frame_register_signed |
2171 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 2172 | |
29639122 JB |
2173 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
2174 | if (alloca_adjust > 0) | |
2175 | { | |
025bb325 | 2176 | /* FP > SP + frame_size. This may be because of |
29639122 JB |
2177 | an alloca or somethings similar. Fix sp to |
2178 | "pre-alloca" value, and try again. */ | |
2179 | sp += alloca_adjust; | |
2180 | /* Need to reset the status of all registers. Otherwise, | |
2181 | we will hit a guard that prevents the new address | |
2182 | for each register to be recomputed during the second | |
2183 | pass. */ | |
74ed0bb4 | 2184 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
2185 | goto restart; |
2186 | } | |
2187 | } | |
2188 | } | |
2189 | /* move $30,$sp. With different versions of gas this will be either | |
2190 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
2191 | Accept any one of these. */ | |
2192 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
2193 | { | |
2194 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
b8a22b94 | 2195 | if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
2196 | { |
2197 | unsigned alloca_adjust; | |
c906108c | 2198 | |
29639122 | 2199 | frame_reg = 30; |
b8a22b94 DJ |
2200 | frame_addr = get_frame_register_signed |
2201 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 2202 | |
29639122 JB |
2203 | alloca_adjust = (unsigned) (frame_addr - sp); |
2204 | if (alloca_adjust > 0) | |
2205 | { | |
025bb325 | 2206 | /* FP > SP + frame_size. This may be because of |
29639122 JB |
2207 | an alloca or somethings similar. Fix sp to |
2208 | "pre-alloca" value, and try again. */ | |
2209 | sp = frame_addr; | |
2210 | /* Need to reset the status of all registers. Otherwise, | |
2211 | we will hit a guard that prevents the new address | |
2212 | for each register to be recomputed during the second | |
2213 | pass. */ | |
74ed0bb4 | 2214 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
2215 | goto restart; |
2216 | } | |
2217 | } | |
2218 | } | |
7d1e6fb8 KB |
2219 | else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */ |
2220 | && !regsize_is_64_bits) | |
29639122 | 2221 | { |
74ed0bb4 | 2222 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + low_word); |
29639122 JB |
2223 | } |
2224 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | |
2225 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ | |
2226 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | |
2227 | || high_word == 0x3c1c /* lui $gp,n */ | |
2228 | || high_word == 0x279c /* addiu $gp,$gp,n */ | |
2229 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
2230 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | |
2231 | ) | |
2232 | { | |
2233 | /* These instructions are part of the prologue, but we don't | |
2234 | need to do anything special to handle them. */ | |
2235 | } | |
2236 | /* The instructions below load $at or $t0 with an immediate | |
2237 | value in preparation for a stack adjustment via | |
025bb325 | 2238 | subu $sp,$sp,[$at,$t0]. These instructions could also |
29639122 JB |
2239 | initialize a local variable, so we accept them only before |
2240 | a stack adjustment instruction was seen. */ | |
2241 | else if (!seen_sp_adjust | |
2242 | && (high_word == 0x3c01 /* lui $at,n */ | |
2243 | || high_word == 0x3c08 /* lui $t0,n */ | |
2244 | || high_word == 0x3421 /* ori $at,$at,n */ | |
2245 | || high_word == 0x3508 /* ori $t0,$t0,n */ | |
2246 | || high_word == 0x3401 /* ori $at,$zero,n */ | |
2247 | || high_word == 0x3408 /* ori $t0,$zero,n */ | |
2248 | )) | |
2249 | { | |
95ac2dcf | 2250 | load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ |
29639122 JB |
2251 | } |
2252 | else | |
2253 | { | |
2254 | /* This instruction is not an instruction typically found | |
2255 | in a prologue, so we must have reached the end of the | |
2256 | prologue. */ | |
2257 | /* FIXME: brobecker/2004-10-10: Can't we just break out of this | |
2258 | loop now? Why would we need to continue scanning the function | |
2259 | instructions? */ | |
2260 | if (end_prologue_addr == 0) | |
2261 | end_prologue_addr = cur_pc; | |
db5f024e DJ |
2262 | |
2263 | /* Check for branches and jumps. For now, only jump to | |
2264 | register are caught (i.e. returns). */ | |
2265 | if ((itype_op (inst) & 0x07) == 0 && rtype_funct (inst) == 8) | |
2266 | in_delay_slot = 1; | |
29639122 | 2267 | } |
db5f024e DJ |
2268 | |
2269 | /* If the previous instruction was a jump, we must have reached | |
2270 | the end of the prologue by now. Stop scanning so that we do | |
2271 | not go past the function return. */ | |
2272 | if (in_delay_slot) | |
2273 | break; | |
a4b8ebc8 | 2274 | } |
c906108c | 2275 | |
29639122 JB |
2276 | if (this_cache != NULL) |
2277 | { | |
2278 | this_cache->base = | |
b8a22b94 DJ |
2279 | (get_frame_register_signed (this_frame, |
2280 | gdbarch_num_regs (gdbarch) + frame_reg) | |
29639122 JB |
2281 | + frame_offset); |
2282 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of | |
2283 | this assignment below, eventually. But it's still needed | |
2284 | for now. */ | |
72a155b4 UW |
2285 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
2286 | + mips_regnum (gdbarch)->pc] | |
2287 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) | |
f57d151a | 2288 | + MIPS_RA_REGNUM]; |
29639122 | 2289 | } |
c906108c | 2290 | |
29639122 JB |
2291 | /* If we didn't reach the end of the prologue when scanning the function |
2292 | instructions, then set end_prologue_addr to the address of the | |
2293 | instruction immediately after the last one we scanned. */ | |
2294 | /* brobecker/2004-10-10: I don't think this would ever happen, but | |
2295 | we may as well be careful and do our best if we have a null | |
2296 | end_prologue_addr. */ | |
2297 | if (end_prologue_addr == 0) | |
2298 | end_prologue_addr = cur_pc; | |
2299 | ||
2300 | /* In a frameless function, we might have incorrectly | |
025bb325 | 2301 | skipped some load immediate instructions. Undo the skipping |
29639122 JB |
2302 | if the load immediate was not followed by a stack adjustment. */ |
2303 | if (load_immediate_bytes && !seen_sp_adjust) | |
2304 | end_prologue_addr -= load_immediate_bytes; | |
c906108c | 2305 | |
29639122 | 2306 | return end_prologue_addr; |
c906108c SS |
2307 | } |
2308 | ||
29639122 JB |
2309 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
2310 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
2311 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
2312 | unwinder. */ | |
c906108c | 2313 | |
29639122 | 2314 | static struct mips_frame_cache * |
b8a22b94 | 2315 | mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache) |
c906108c | 2316 | { |
e17a4113 | 2317 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 2318 | struct mips_frame_cache *cache; |
c906108c | 2319 | |
29639122 JB |
2320 | if ((*this_cache) != NULL) |
2321 | return (*this_cache); | |
c5aa993b | 2322 | |
29639122 JB |
2323 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
2324 | (*this_cache) = cache; | |
b8a22b94 | 2325 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
c5aa993b | 2326 | |
29639122 JB |
2327 | /* Analyze the function prologue. */ |
2328 | { | |
b8a22b94 | 2329 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 2330 | CORE_ADDR start_addr; |
c906108c | 2331 | |
29639122 JB |
2332 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
2333 | if (start_addr == 0) | |
e17a4113 | 2334 | start_addr = heuristic_proc_start (gdbarch, pc); |
29639122 JB |
2335 | /* We can't analyze the prologue if we couldn't find the begining |
2336 | of the function. */ | |
2337 | if (start_addr == 0) | |
2338 | return cache; | |
c5aa993b | 2339 | |
e17a4113 | 2340 | mips32_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); |
29639122 JB |
2341 | } |
2342 | ||
3e8c568d | 2343 | /* gdbarch_sp_regnum contains the value and not the address. */ |
f57d151a | 2344 | trad_frame_set_value (cache->saved_regs, |
e17a4113 | 2345 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
f57d151a | 2346 | cache->base); |
c5aa993b | 2347 | |
29639122 | 2348 | return (*this_cache); |
c906108c SS |
2349 | } |
2350 | ||
29639122 | 2351 | static void |
b8a22b94 | 2352 | mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 | 2353 | struct frame_id *this_id) |
c906108c | 2354 | { |
b8a22b94 | 2355 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 2356 | this_cache); |
21327321 DJ |
2357 | /* This marks the outermost frame. */ |
2358 | if (info->base == 0) | |
2359 | return; | |
b8a22b94 | 2360 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
29639122 | 2361 | } |
c906108c | 2362 | |
b8a22b94 DJ |
2363 | static struct value * |
2364 | mips_insn32_frame_prev_register (struct frame_info *this_frame, | |
2365 | void **this_cache, int regnum) | |
29639122 | 2366 | { |
b8a22b94 | 2367 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 2368 | this_cache); |
b8a22b94 DJ |
2369 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
2370 | } | |
2371 | ||
2372 | static int | |
2373 | mips_insn32_frame_sniffer (const struct frame_unwind *self, | |
2374 | struct frame_info *this_frame, void **this_cache) | |
2375 | { | |
2376 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2377 | if (! mips_pc_is_mips16 (pc)) | |
2378 | return 1; | |
2379 | return 0; | |
c906108c SS |
2380 | } |
2381 | ||
29639122 JB |
2382 | static const struct frame_unwind mips_insn32_frame_unwind = |
2383 | { | |
2384 | NORMAL_FRAME, | |
8fbca658 | 2385 | default_frame_unwind_stop_reason, |
29639122 | 2386 | mips_insn32_frame_this_id, |
b8a22b94 DJ |
2387 | mips_insn32_frame_prev_register, |
2388 | NULL, | |
2389 | mips_insn32_frame_sniffer | |
29639122 | 2390 | }; |
c906108c | 2391 | |
1c645fec | 2392 | static CORE_ADDR |
b8a22b94 | 2393 | mips_insn32_frame_base_address (struct frame_info *this_frame, |
29639122 | 2394 | void **this_cache) |
c906108c | 2395 | { |
b8a22b94 | 2396 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 JB |
2397 | this_cache); |
2398 | return info->base; | |
2399 | } | |
c906108c | 2400 | |
29639122 JB |
2401 | static const struct frame_base mips_insn32_frame_base = |
2402 | { | |
2403 | &mips_insn32_frame_unwind, | |
2404 | mips_insn32_frame_base_address, | |
2405 | mips_insn32_frame_base_address, | |
2406 | mips_insn32_frame_base_address | |
2407 | }; | |
1c645fec | 2408 | |
29639122 | 2409 | static const struct frame_base * |
b8a22b94 | 2410 | mips_insn32_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 2411 | { |
b8a22b94 DJ |
2412 | CORE_ADDR pc = get_frame_pc (this_frame); |
2413 | if (! mips_pc_is_mips16 (pc)) | |
29639122 | 2414 | return &mips_insn32_frame_base; |
a65bbe44 | 2415 | else |
29639122 JB |
2416 | return NULL; |
2417 | } | |
a65bbe44 | 2418 | |
29639122 | 2419 | static struct trad_frame_cache * |
b8a22b94 | 2420 | mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache) |
29639122 JB |
2421 | { |
2422 | CORE_ADDR pc; | |
2423 | CORE_ADDR start_addr; | |
2424 | CORE_ADDR stack_addr; | |
2425 | struct trad_frame_cache *this_trad_cache; | |
b8a22b94 DJ |
2426 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2427 | int num_regs = gdbarch_num_regs (gdbarch); | |
c906108c | 2428 | |
29639122 JB |
2429 | if ((*this_cache) != NULL) |
2430 | return (*this_cache); | |
b8a22b94 | 2431 | this_trad_cache = trad_frame_cache_zalloc (this_frame); |
29639122 | 2432 | (*this_cache) = this_trad_cache; |
1c645fec | 2433 | |
29639122 | 2434 | /* The return address is in the link register. */ |
3e8c568d | 2435 | trad_frame_set_reg_realreg (this_trad_cache, |
72a155b4 | 2436 | gdbarch_pc_regnum (gdbarch), |
b8a22b94 | 2437 | num_regs + MIPS_RA_REGNUM); |
1c645fec | 2438 | |
29639122 JB |
2439 | /* Frame ID, since it's a frameless / stackless function, no stack |
2440 | space is allocated and SP on entry is the current SP. */ | |
b8a22b94 | 2441 | pc = get_frame_pc (this_frame); |
29639122 | 2442 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
b8a22b94 DJ |
2443 | stack_addr = get_frame_register_signed (this_frame, |
2444 | num_regs + MIPS_SP_REGNUM); | |
aa6c981f | 2445 | trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr)); |
1c645fec | 2446 | |
29639122 JB |
2447 | /* Assume that the frame's base is the same as the |
2448 | stack-pointer. */ | |
2449 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
c906108c | 2450 | |
29639122 JB |
2451 | return this_trad_cache; |
2452 | } | |
c906108c | 2453 | |
29639122 | 2454 | static void |
b8a22b94 | 2455 | mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 JB |
2456 | struct frame_id *this_id) |
2457 | { | |
2458 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 2459 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
2460 | trad_frame_get_id (this_trad_cache, this_id); |
2461 | } | |
c906108c | 2462 | |
b8a22b94 DJ |
2463 | static struct value * |
2464 | mips_stub_frame_prev_register (struct frame_info *this_frame, | |
2465 | void **this_cache, int regnum) | |
29639122 JB |
2466 | { |
2467 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 DJ |
2468 | = mips_stub_frame_cache (this_frame, this_cache); |
2469 | return trad_frame_get_register (this_trad_cache, this_frame, regnum); | |
29639122 | 2470 | } |
c906108c | 2471 | |
b8a22b94 DJ |
2472 | static int |
2473 | mips_stub_frame_sniffer (const struct frame_unwind *self, | |
2474 | struct frame_info *this_frame, void **this_cache) | |
29639122 | 2475 | { |
aa6c981f | 2476 | gdb_byte dummy[4]; |
979b38e0 | 2477 | struct obj_section *s; |
b8a22b94 | 2478 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
db5f024e | 2479 | struct minimal_symbol *msym; |
979b38e0 | 2480 | |
aa6c981f | 2481 | /* Use the stub unwinder for unreadable code. */ |
b8a22b94 DJ |
2482 | if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) |
2483 | return 1; | |
aa6c981f | 2484 | |
29639122 | 2485 | if (in_plt_section (pc, NULL)) |
b8a22b94 | 2486 | return 1; |
979b38e0 DJ |
2487 | |
2488 | /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */ | |
2489 | s = find_pc_section (pc); | |
2490 | ||
2491 | if (s != NULL | |
2492 | && strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section), | |
2493 | ".MIPS.stubs") == 0) | |
b8a22b94 | 2494 | return 1; |
979b38e0 | 2495 | |
db5f024e DJ |
2496 | /* Calling a PIC function from a non-PIC function passes through a |
2497 | stub. The stub for foo is named ".pic.foo". */ | |
2498 | msym = lookup_minimal_symbol_by_pc (pc); | |
2499 | if (msym != NULL | |
2500 | && SYMBOL_LINKAGE_NAME (msym) != NULL | |
2501 | && strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) == 0) | |
2502 | return 1; | |
2503 | ||
b8a22b94 | 2504 | return 0; |
29639122 | 2505 | } |
c906108c | 2506 | |
b8a22b94 DJ |
2507 | static const struct frame_unwind mips_stub_frame_unwind = |
2508 | { | |
2509 | NORMAL_FRAME, | |
8fbca658 | 2510 | default_frame_unwind_stop_reason, |
b8a22b94 DJ |
2511 | mips_stub_frame_this_id, |
2512 | mips_stub_frame_prev_register, | |
2513 | NULL, | |
2514 | mips_stub_frame_sniffer | |
2515 | }; | |
2516 | ||
29639122 | 2517 | static CORE_ADDR |
b8a22b94 | 2518 | mips_stub_frame_base_address (struct frame_info *this_frame, |
29639122 JB |
2519 | void **this_cache) |
2520 | { | |
2521 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 2522 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
2523 | return trad_frame_get_this_base (this_trad_cache); |
2524 | } | |
0fce0821 | 2525 | |
29639122 JB |
2526 | static const struct frame_base mips_stub_frame_base = |
2527 | { | |
2528 | &mips_stub_frame_unwind, | |
2529 | mips_stub_frame_base_address, | |
2530 | mips_stub_frame_base_address, | |
2531 | mips_stub_frame_base_address | |
2532 | }; | |
2533 | ||
2534 | static const struct frame_base * | |
b8a22b94 | 2535 | mips_stub_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 2536 | { |
b8a22b94 | 2537 | if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL)) |
29639122 JB |
2538 | return &mips_stub_frame_base; |
2539 | else | |
2540 | return NULL; | |
2541 | } | |
2542 | ||
29639122 | 2543 | /* mips_addr_bits_remove - remove useless address bits */ |
65596487 | 2544 | |
29639122 | 2545 | static CORE_ADDR |
24568a2c | 2546 | mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) |
65596487 | 2547 | { |
24568a2c | 2548 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
930bd0e0 KB |
2549 | |
2550 | if (is_mips16_addr (addr)) | |
2551 | addr = unmake_mips16_addr (addr); | |
2552 | ||
29639122 JB |
2553 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) |
2554 | /* This hack is a work-around for existing boards using PMON, the | |
2555 | simulator, and any other 64-bit targets that doesn't have true | |
2556 | 64-bit addressing. On these targets, the upper 32 bits of | |
2557 | addresses are ignored by the hardware. Thus, the PC or SP are | |
2558 | likely to have been sign extended to all 1s by instruction | |
2559 | sequences that load 32-bit addresses. For example, a typical | |
2560 | piece of code that loads an address is this: | |
65596487 | 2561 | |
29639122 JB |
2562 | lui $r2, <upper 16 bits> |
2563 | ori $r2, <lower 16 bits> | |
65596487 | 2564 | |
29639122 JB |
2565 | But the lui sign-extends the value such that the upper 32 bits |
2566 | may be all 1s. The workaround is simply to mask off these | |
2567 | bits. In the future, gcc may be changed to support true 64-bit | |
2568 | addressing, and this masking will have to be disabled. */ | |
2569 | return addr &= 0xffffffffUL; | |
2570 | else | |
2571 | return addr; | |
65596487 JB |
2572 | } |
2573 | ||
3d5f6d12 DJ |
2574 | /* Instructions used during single-stepping of atomic sequences. */ |
2575 | #define LL_OPCODE 0x30 | |
2576 | #define LLD_OPCODE 0x34 | |
2577 | #define SC_OPCODE 0x38 | |
2578 | #define SCD_OPCODE 0x3c | |
2579 | ||
2580 | /* Checks for an atomic sequence of instructions beginning with a LL/LLD | |
2581 | instruction and ending with a SC/SCD instruction. If such a sequence | |
2582 | is found, attempt to step through it. A breakpoint is placed at the end of | |
2583 | the sequence. */ | |
2584 | ||
2585 | static int | |
6c95b8df PA |
2586 | deal_with_atomic_sequence (struct gdbarch *gdbarch, |
2587 | struct address_space *aspace, CORE_ADDR pc) | |
3d5f6d12 DJ |
2588 | { |
2589 | CORE_ADDR breaks[2] = {-1, -1}; | |
2590 | CORE_ADDR loc = pc; | |
2591 | CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ | |
2592 | unsigned long insn; | |
2593 | int insn_count; | |
2594 | int index; | |
2595 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
2596 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
2597 | ||
2598 | if (pc & 0x01) | |
2599 | return 0; | |
2600 | ||
e17a4113 | 2601 | insn = mips_fetch_instruction (gdbarch, loc); |
3d5f6d12 DJ |
2602 | /* Assume all atomic sequences start with a ll/lld instruction. */ |
2603 | if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE) | |
2604 | return 0; | |
2605 | ||
2606 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" | |
2607 | instructions. */ | |
2608 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
2609 | { | |
2610 | int is_branch = 0; | |
2611 | loc += MIPS_INSN32_SIZE; | |
e17a4113 | 2612 | insn = mips_fetch_instruction (gdbarch, loc); |
3d5f6d12 DJ |
2613 | |
2614 | /* Assume that there is at most one branch in the atomic | |
2615 | sequence. If a branch is found, put a breakpoint in its | |
2616 | destination address. */ | |
2617 | switch (itype_op (insn)) | |
2618 | { | |
2619 | case 0: /* SPECIAL */ | |
2620 | if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */ | |
025bb325 | 2621 | return 0; /* fallback to the standard single-step code. */ |
3d5f6d12 DJ |
2622 | break; |
2623 | case 1: /* REGIMM */ | |
2624 | is_branch = ((itype_rt (insn) & 0xc0) == 0); /* B{LT,GE}Z* */ | |
2625 | break; | |
2626 | case 2: /* J */ | |
2627 | case 3: /* JAL */ | |
025bb325 | 2628 | return 0; /* fallback to the standard single-step code. */ |
3d5f6d12 DJ |
2629 | case 4: /* BEQ */ |
2630 | case 5: /* BNE */ | |
2631 | case 6: /* BLEZ */ | |
2632 | case 7: /* BGTZ */ | |
2633 | case 20: /* BEQL */ | |
2634 | case 21: /* BNEL */ | |
2635 | case 22: /* BLEZL */ | |
2636 | case 23: /* BGTTL */ | |
2637 | is_branch = 1; | |
2638 | break; | |
2639 | case 17: /* COP1 */ | |
2640 | case 18: /* COP2 */ | |
2641 | case 19: /* COP3 */ | |
2642 | is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */ | |
2643 | break; | |
2644 | } | |
2645 | if (is_branch) | |
2646 | { | |
2647 | branch_bp = loc + mips32_relative_offset (insn) + 4; | |
2648 | if (last_breakpoint >= 1) | |
2649 | return 0; /* More than one branch found, fallback to the | |
2650 | standard single-step code. */ | |
2651 | breaks[1] = branch_bp; | |
2652 | last_breakpoint++; | |
2653 | } | |
2654 | ||
2655 | if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE) | |
2656 | break; | |
2657 | } | |
2658 | ||
2659 | /* Assume that the atomic sequence ends with a sc/scd instruction. */ | |
2660 | if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE) | |
2661 | return 0; | |
2662 | ||
2663 | loc += MIPS_INSN32_SIZE; | |
2664 | ||
2665 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
2666 | breaks[0] = loc; | |
2667 | ||
2668 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
025bb325 | 2669 | placed (branch instruction's destination) in the atomic sequence. */ |
3d5f6d12 DJ |
2670 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) |
2671 | last_breakpoint = 0; | |
2672 | ||
2673 | /* Effectively inserts the breakpoints. */ | |
2674 | for (index = 0; index <= last_breakpoint; index++) | |
6c95b8df | 2675 | insert_single_step_breakpoint (gdbarch, aspace, breaks[index]); |
3d5f6d12 DJ |
2676 | |
2677 | return 1; | |
2678 | } | |
2679 | ||
29639122 JB |
2680 | /* mips_software_single_step() is called just before we want to resume |
2681 | the inferior, if we want to single-step it but there is no hardware | |
2682 | or kernel single-step support (MIPS on GNU/Linux for example). We find | |
e0cd558a | 2683 | the target of the coming instruction and breakpoint it. */ |
29639122 | 2684 | |
e6590a1b | 2685 | int |
0b1b3e42 | 2686 | mips_software_single_step (struct frame_info *frame) |
c906108c | 2687 | { |
a6d9a66e | 2688 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6c95b8df | 2689 | struct address_space *aspace = get_frame_address_space (frame); |
8181d85f | 2690 | CORE_ADDR pc, next_pc; |
65596487 | 2691 | |
0b1b3e42 | 2692 | pc = get_frame_pc (frame); |
6c95b8df | 2693 | if (deal_with_atomic_sequence (gdbarch, aspace, pc)) |
3d5f6d12 DJ |
2694 | return 1; |
2695 | ||
0b1b3e42 | 2696 | next_pc = mips_next_pc (frame, pc); |
e6590a1b | 2697 | |
6c95b8df | 2698 | insert_single_step_breakpoint (gdbarch, aspace, next_pc); |
e6590a1b | 2699 | return 1; |
29639122 | 2700 | } |
a65bbe44 | 2701 | |
29639122 | 2702 | /* Test whether the PC points to the return instruction at the |
025bb325 | 2703 | end of a function. */ |
65596487 | 2704 | |
29639122 | 2705 | static int |
e17a4113 | 2706 | mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 | 2707 | { |
0fe7e7c8 | 2708 | if (mips_pc_is_mips16 (pc)) |
29639122 JB |
2709 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler |
2710 | generates a "jr $ra"; other times it generates code to load | |
2711 | the return address from the stack to an accessible register (such | |
2712 | as $a3), then a "jr" using that register. This second case | |
2713 | is almost impossible to distinguish from an indirect jump | |
2714 | used for switch statements, so we don't even try. */ | |
e17a4113 | 2715 | return mips_fetch_instruction (gdbarch, pc) == 0xe820; /* jr $ra */ |
29639122 | 2716 | else |
e17a4113 | 2717 | return mips_fetch_instruction (gdbarch, pc) == 0x3e00008; /* jr $ra */ |
29639122 | 2718 | } |
c906108c | 2719 | |
c906108c | 2720 | |
29639122 JB |
2721 | /* This fencepost looks highly suspicious to me. Removing it also |
2722 | seems suspicious as it could affect remote debugging across serial | |
2723 | lines. */ | |
c906108c | 2724 | |
29639122 | 2725 | static CORE_ADDR |
74ed0bb4 | 2726 | heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 JB |
2727 | { |
2728 | CORE_ADDR start_pc; | |
2729 | CORE_ADDR fence; | |
2730 | int instlen; | |
2731 | int seen_adjsp = 0; | |
d6b48e9c | 2732 | struct inferior *inf; |
65596487 | 2733 | |
74ed0bb4 | 2734 | pc = gdbarch_addr_bits_remove (gdbarch, pc); |
29639122 JB |
2735 | start_pc = pc; |
2736 | fence = start_pc - heuristic_fence_post; | |
2737 | if (start_pc == 0) | |
2738 | return 0; | |
65596487 | 2739 | |
29639122 JB |
2740 | if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
2741 | fence = VM_MIN_ADDRESS; | |
65596487 | 2742 | |
95ac2dcf | 2743 | instlen = mips_pc_is_mips16 (pc) ? MIPS_INSN16_SIZE : MIPS_INSN32_SIZE; |
98b4dd94 | 2744 | |
d6b48e9c PA |
2745 | inf = current_inferior (); |
2746 | ||
025bb325 | 2747 | /* Search back for previous return. */ |
29639122 JB |
2748 | for (start_pc -= instlen;; start_pc -= instlen) |
2749 | if (start_pc < fence) | |
2750 | { | |
2751 | /* It's not clear to me why we reach this point when | |
2752 | stop_soon, but with this test, at least we | |
2753 | don't print out warnings for every child forked (eg, on | |
2754 | decstation). 22apr93 rich@cygnus.com. */ | |
16c381f0 | 2755 | if (inf->control.stop_soon == NO_STOP_QUIETLY) |
29639122 JB |
2756 | { |
2757 | static int blurb_printed = 0; | |
98b4dd94 | 2758 | |
5af949e3 UW |
2759 | warning (_("GDB can't find the start of the function at %s."), |
2760 | paddress (gdbarch, pc)); | |
29639122 JB |
2761 | |
2762 | if (!blurb_printed) | |
2763 | { | |
2764 | /* This actually happens frequently in embedded | |
2765 | development, when you first connect to a board | |
2766 | and your stack pointer and pc are nowhere in | |
2767 | particular. This message needs to give people | |
2768 | in that situation enough information to | |
2769 | determine that it's no big deal. */ | |
2770 | printf_filtered ("\n\ | |
5af949e3 | 2771 | GDB is unable to find the start of the function at %s\n\ |
29639122 JB |
2772 | and thus can't determine the size of that function's stack frame.\n\ |
2773 | This means that GDB may be unable to access that stack frame, or\n\ | |
2774 | the frames below it.\n\ | |
2775 | This problem is most likely caused by an invalid program counter or\n\ | |
2776 | stack pointer.\n\ | |
2777 | However, if you think GDB should simply search farther back\n\ | |
5af949e3 | 2778 | from %s for code which looks like the beginning of a\n\ |
29639122 | 2779 | function, you can increase the range of the search using the `set\n\ |
5af949e3 UW |
2780 | heuristic-fence-post' command.\n", |
2781 | paddress (gdbarch, pc), paddress (gdbarch, pc)); | |
29639122 JB |
2782 | blurb_printed = 1; |
2783 | } | |
2784 | } | |
2785 | ||
2786 | return 0; | |
2787 | } | |
0fe7e7c8 | 2788 | else if (mips_pc_is_mips16 (start_pc)) |
29639122 JB |
2789 | { |
2790 | unsigned short inst; | |
2791 | ||
2792 | /* On MIPS16, any one of the following is likely to be the | |
2793 | start of a function: | |
193774b3 MR |
2794 | extend save |
2795 | save | |
29639122 JB |
2796 | entry |
2797 | addiu sp,-n | |
2798 | daddiu sp,-n | |
025bb325 | 2799 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */ |
e17a4113 | 2800 | inst = mips_fetch_instruction (gdbarch, start_pc); |
193774b3 MR |
2801 | if ((inst & 0xff80) == 0x6480) /* save */ |
2802 | { | |
2803 | if (start_pc - instlen >= fence) | |
2804 | { | |
e17a4113 | 2805 | inst = mips_fetch_instruction (gdbarch, start_pc - instlen); |
193774b3 MR |
2806 | if ((inst & 0xf800) == 0xf000) /* extend */ |
2807 | start_pc -= instlen; | |
2808 | } | |
2809 | break; | |
2810 | } | |
2811 | else if (((inst & 0xf81f) == 0xe809 | |
2812 | && (inst & 0x700) != 0x700) /* entry */ | |
2813 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
2814 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
2815 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
29639122 JB |
2816 | break; |
2817 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
2818 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2819 | seen_adjsp = 1; | |
2820 | else | |
2821 | seen_adjsp = 0; | |
2822 | } | |
e17a4113 | 2823 | else if (mips_about_to_return (gdbarch, start_pc)) |
29639122 | 2824 | { |
4c7d22cb | 2825 | /* Skip return and its delay slot. */ |
95ac2dcf | 2826 | start_pc += 2 * MIPS_INSN32_SIZE; |
29639122 JB |
2827 | break; |
2828 | } | |
2829 | ||
2830 | return start_pc; | |
c906108c SS |
2831 | } |
2832 | ||
6c0d6680 DJ |
2833 | struct mips_objfile_private |
2834 | { | |
2835 | bfd_size_type size; | |
2836 | char *contents; | |
2837 | }; | |
2838 | ||
f09ded24 AC |
2839 | /* According to the current ABI, should the type be passed in a |
2840 | floating-point register (assuming that there is space)? When there | |
a1f5b845 | 2841 | is no FPU, FP are not even considered as possible candidates for |
f09ded24 | 2842 | FP registers and, consequently this returns false - forces FP |
025bb325 | 2843 | arguments into integer registers. */ |
f09ded24 AC |
2844 | |
2845 | static int | |
74ed0bb4 MD |
2846 | fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode, |
2847 | struct type *arg_type) | |
f09ded24 AC |
2848 | { |
2849 | return ((typecode == TYPE_CODE_FLT | |
74ed0bb4 | 2850 | || (MIPS_EABI (gdbarch) |
6d82d43b AC |
2851 | && (typecode == TYPE_CODE_STRUCT |
2852 | || typecode == TYPE_CODE_UNION) | |
f09ded24 | 2853 | && TYPE_NFIELDS (arg_type) == 1 |
b2d6f210 MS |
2854 | && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0))) |
2855 | == TYPE_CODE_FLT)) | |
74ed0bb4 | 2856 | && MIPS_FPU_TYPE(gdbarch) != MIPS_FPU_NONE); |
f09ded24 AC |
2857 | } |
2858 | ||
49e790b0 | 2859 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
025bb325 | 2860 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ |
49e790b0 DJ |
2861 | |
2862 | static int | |
2863 | mips_type_needs_double_align (struct type *type) | |
2864 | { | |
2865 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2866 | |
49e790b0 DJ |
2867 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2868 | return 1; | |
2869 | else if (typecode == TYPE_CODE_STRUCT) | |
2870 | { | |
2871 | if (TYPE_NFIELDS (type) < 1) | |
2872 | return 0; | |
2873 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2874 | } | |
2875 | else if (typecode == TYPE_CODE_UNION) | |
2876 | { | |
361d1df0 | 2877 | int i, n; |
49e790b0 DJ |
2878 | |
2879 | n = TYPE_NFIELDS (type); | |
2880 | for (i = 0; i < n; i++) | |
2881 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2882 | return 1; | |
2883 | return 0; | |
2884 | } | |
2885 | return 0; | |
2886 | } | |
2887 | ||
dc604539 AC |
2888 | /* Adjust the address downward (direction of stack growth) so that it |
2889 | is correctly aligned for a new stack frame. */ | |
2890 | static CORE_ADDR | |
2891 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2892 | { | |
5b03f266 | 2893 | return align_down (addr, 16); |
dc604539 AC |
2894 | } |
2895 | ||
f7ab6ec6 | 2896 | static CORE_ADDR |
7d9b040b | 2897 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
2898 | struct regcache *regcache, CORE_ADDR bp_addr, |
2899 | int nargs, struct value **args, CORE_ADDR sp, | |
2900 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
2901 | { |
2902 | int argreg; | |
2903 | int float_argreg; | |
2904 | int argnum; | |
2905 | int len = 0; | |
2906 | int stack_offset = 0; | |
480d3dd2 | 2907 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 2908 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 2909 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
1a69e1e4 | 2910 | int regsize = mips_abi_regsize (gdbarch); |
c906108c | 2911 | |
25ab4790 AC |
2912 | /* For shared libraries, "t9" needs to point at the function |
2913 | address. */ | |
4c7d22cb | 2914 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
2915 | |
2916 | /* Set the return address register to point to the entry point of | |
2917 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 2918 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 2919 | |
c906108c | 2920 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2921 | are properly aligned. The stack has to be at least 64-bit |
2922 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2923 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2924 | aligned, so we round to this widest known alignment. */ | |
2925 | ||
5b03f266 AC |
2926 | sp = align_down (sp, 16); |
2927 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 2928 | |
46e0f506 | 2929 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2930 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2931 | passed in registers, but that's OK. */ |
c906108c | 2932 | for (argnum = 0; argnum < nargs; argnum++) |
1a69e1e4 | 2933 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize); |
5b03f266 | 2934 | sp -= align_up (len, 16); |
c906108c | 2935 | |
9ace0497 | 2936 | if (mips_debug) |
6d82d43b | 2937 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
2938 | "mips_eabi_push_dummy_call: sp=%s allocated %ld\n", |
2939 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
9ace0497 | 2940 | |
c906108c | 2941 | /* Initialize the integer and float register pointers. */ |
4c7d22cb | 2942 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 2943 | float_argreg = mips_fpa0_regnum (gdbarch); |
c906108c | 2944 | |
46e0f506 | 2945 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2946 | if (struct_return) |
9ace0497 AC |
2947 | { |
2948 | if (mips_debug) | |
2949 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
2950 | "mips_eabi_push_dummy_call: " |
2951 | "struct_return reg=%d %s\n", | |
5af949e3 | 2952 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 2953 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
9ace0497 | 2954 | } |
c906108c SS |
2955 | |
2956 | /* Now load as many as possible of the first arguments into | |
2957 | registers, and push the rest onto the stack. Loop thru args | |
2958 | from first to last. */ | |
2959 | for (argnum = 0; argnum < nargs; argnum++) | |
2960 | { | |
47a35522 MK |
2961 | const gdb_byte *val; |
2962 | gdb_byte valbuf[MAX_REGISTER_SIZE]; | |
ea7c478f | 2963 | struct value *arg = args[argnum]; |
4991999e | 2964 | struct type *arg_type = check_typedef (value_type (arg)); |
c906108c SS |
2965 | int len = TYPE_LENGTH (arg_type); |
2966 | enum type_code typecode = TYPE_CODE (arg_type); | |
2967 | ||
9ace0497 AC |
2968 | if (mips_debug) |
2969 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2970 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 2971 | argnum + 1, len, (int) typecode); |
9ace0497 | 2972 | |
930bd0e0 KB |
2973 | /* Function pointer arguments to mips16 code need to be made into |
2974 | mips16 pointers. */ | |
2975 | if (typecode == TYPE_CODE_PTR | |
2976 | && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC) | |
2977 | { | |
2978 | CORE_ADDR addr = extract_signed_integer (value_contents (arg), | |
2979 | len, byte_order); | |
2980 | if (mips_pc_is_mips16 (addr)) | |
2981 | { | |
2982 | store_signed_integer (valbuf, len, byte_order, | |
2983 | make_mips16_addr (addr)); | |
2984 | val = valbuf; | |
2985 | } | |
2986 | else | |
2987 | val = value_contents (arg); | |
2988 | } | |
c906108c | 2989 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 2990 | reference. */ |
930bd0e0 | 2991 | else if (len > regsize |
9ace0497 | 2992 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 2993 | { |
e17a4113 UW |
2994 | store_unsigned_integer (valbuf, regsize, byte_order, |
2995 | value_address (arg)); | |
c906108c | 2996 | typecode = TYPE_CODE_PTR; |
1a69e1e4 | 2997 | len = regsize; |
c906108c | 2998 | val = valbuf; |
9ace0497 AC |
2999 | if (mips_debug) |
3000 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
3001 | } |
3002 | else | |
47a35522 | 3003 | val = value_contents (arg); |
c906108c SS |
3004 | |
3005 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
3006 | even-numbered floating point register. Round the FP register |
3007 | up before the check to see if there are any FP registers | |
46e0f506 MS |
3008 | left. Non MIPS_EABI targets also pass the FP in the integer |
3009 | registers so also round up normal registers. */ | |
74ed0bb4 | 3010 | if (regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type)) |
acdb74a0 AC |
3011 | { |
3012 | if ((float_argreg & 1)) | |
3013 | float_argreg++; | |
3014 | } | |
c906108c SS |
3015 | |
3016 | /* Floating point arguments passed in registers have to be | |
3017 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
3018 | are passed in register pairs; the even register gets |
3019 | the low word, and the odd register gets the high word. | |
3020 | On non-EABI processors, the first two floating point arguments are | |
3021 | also copied to general registers, because MIPS16 functions | |
3022 | don't use float registers for arguments. This duplication of | |
3023 | arguments in general registers can't hurt non-MIPS16 functions | |
3024 | because those registers are normally skipped. */ | |
1012bd0e EZ |
3025 | /* MIPS_EABI squeezes a struct that contains a single floating |
3026 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 3027 | stack. */ |
74ed0bb4 MD |
3028 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
3029 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
c906108c | 3030 | { |
6da397e0 KB |
3031 | /* EABI32 will pass doubles in consecutive registers, even on |
3032 | 64-bit cores. At one time, we used to check the size of | |
3033 | `float_argreg' to determine whether or not to pass doubles | |
3034 | in consecutive registers, but this is not sufficient for | |
3035 | making the ABI determination. */ | |
3036 | if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) | |
c906108c | 3037 | { |
72a155b4 | 3038 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 3039 | == BFD_ENDIAN_BIG ? 4 : 0; |
a8852dc5 | 3040 | long regval; |
c906108c SS |
3041 | |
3042 | /* Write the low word of the double to the even register(s). */ | |
a8852dc5 KB |
3043 | regval = extract_signed_integer (val + low_offset, |
3044 | 4, byte_order); | |
9ace0497 | 3045 | if (mips_debug) |
acdb74a0 | 3046 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 3047 | float_argreg, phex (regval, 4)); |
a8852dc5 | 3048 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
3049 | |
3050 | /* Write the high word of the double to the odd register(s). */ | |
a8852dc5 KB |
3051 | regval = extract_signed_integer (val + 4 - low_offset, |
3052 | 4, byte_order); | |
9ace0497 | 3053 | if (mips_debug) |
acdb74a0 | 3054 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 3055 | float_argreg, phex (regval, 4)); |
a8852dc5 | 3056 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
3057 | } |
3058 | else | |
3059 | { | |
3060 | /* This is a floating point value that fits entirely | |
3061 | in a single register. */ | |
53a5351d | 3062 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 3063 | above to ensure that it is even register aligned. */ |
a8852dc5 | 3064 | LONGEST regval = extract_signed_integer (val, len, byte_order); |
9ace0497 | 3065 | if (mips_debug) |
acdb74a0 | 3066 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 3067 | float_argreg, phex (regval, len)); |
a8852dc5 | 3068 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
3069 | } |
3070 | } | |
3071 | else | |
3072 | { | |
3073 | /* Copy the argument to general registers or the stack in | |
3074 | register-sized pieces. Large arguments are split between | |
3075 | registers and stack. */ | |
1a69e1e4 DJ |
3076 | /* Note: structs whose size is not a multiple of regsize |
3077 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
3078 | them in registers where gcc sometimes puts them on the |
3079 | stack. For maximum compatibility, we will put them in | |
3080 | both places. */ | |
1a69e1e4 | 3081 | int odd_sized_struct = (len > regsize && len % regsize != 0); |
46e0f506 | 3082 | |
f09ded24 | 3083 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3084 | register are only written to memory. */ |
c906108c SS |
3085 | while (len > 0) |
3086 | { | |
ebafbe83 | 3087 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 3088 | int stack_used_p = 0; |
1a69e1e4 | 3089 | int partial_len = (len < regsize ? len : regsize); |
c906108c | 3090 | |
acdb74a0 AC |
3091 | if (mips_debug) |
3092 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3093 | partial_len); | |
3094 | ||
566f0f7a | 3095 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 3096 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
f09ded24 | 3097 | || odd_sized_struct |
74ed0bb4 | 3098 | || fp_register_arg_p (gdbarch, typecode, arg_type)) |
c906108c | 3099 | { |
c906108c | 3100 | /* Should shorter than int integer values be |
025bb325 | 3101 | promoted to int before being stored? */ |
c906108c | 3102 | int longword_offset = 0; |
9ace0497 | 3103 | CORE_ADDR addr; |
566f0f7a | 3104 | stack_used_p = 1; |
72a155b4 | 3105 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
7a292a7a | 3106 | { |
1a69e1e4 | 3107 | if (regsize == 8 |
480d3dd2 AC |
3108 | && (typecode == TYPE_CODE_INT |
3109 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 3110 | || typecode == TYPE_CODE_FLT) && len <= 4) |
1a69e1e4 | 3111 | longword_offset = regsize - len; |
480d3dd2 AC |
3112 | else if ((typecode == TYPE_CODE_STRUCT |
3113 | || typecode == TYPE_CODE_UNION) | |
1a69e1e4 DJ |
3114 | && TYPE_LENGTH (arg_type) < regsize) |
3115 | longword_offset = regsize - len; | |
7a292a7a | 3116 | } |
c5aa993b | 3117 | |
9ace0497 AC |
3118 | if (mips_debug) |
3119 | { | |
5af949e3 UW |
3120 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
3121 | paddress (gdbarch, stack_offset)); | |
3122 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
3123 | paddress (gdbarch, longword_offset)); | |
9ace0497 | 3124 | } |
361d1df0 | 3125 | |
9ace0497 AC |
3126 | addr = sp + stack_offset + longword_offset; |
3127 | ||
3128 | if (mips_debug) | |
3129 | { | |
3130 | int i; | |
5af949e3 UW |
3131 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
3132 | paddress (gdbarch, addr)); | |
9ace0497 AC |
3133 | for (i = 0; i < partial_len; i++) |
3134 | { | |
6d82d43b | 3135 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 3136 | val[i] & 0xff); |
9ace0497 AC |
3137 | } |
3138 | } | |
3139 | write_memory (addr, val, partial_len); | |
c906108c SS |
3140 | } |
3141 | ||
f09ded24 AC |
3142 | /* Note!!! This is NOT an else clause. Odd sized |
3143 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 3144 | arguments will not. */ |
566f0f7a | 3145 | /* Write this portion of the argument to a general |
6d82d43b | 3146 | purpose register. */ |
74ed0bb4 MD |
3147 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch) |
3148 | && !fp_register_arg_p (gdbarch, typecode, arg_type)) | |
c906108c | 3149 | { |
6d82d43b | 3150 | LONGEST regval = |
a8852dc5 | 3151 | extract_signed_integer (val, partial_len, byte_order); |
c906108c | 3152 | |
9ace0497 | 3153 | if (mips_debug) |
acdb74a0 | 3154 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 3155 | argreg, |
1a69e1e4 | 3156 | phex (regval, regsize)); |
a8852dc5 | 3157 | regcache_cooked_write_signed (regcache, argreg, regval); |
c906108c | 3158 | argreg++; |
c906108c | 3159 | } |
c5aa993b | 3160 | |
c906108c SS |
3161 | len -= partial_len; |
3162 | val += partial_len; | |
3163 | ||
b021a221 MS |
3164 | /* Compute the offset into the stack at which we will |
3165 | copy the next parameter. | |
566f0f7a | 3166 | |
566f0f7a | 3167 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 3168 | only needs to be adjusted when it has been used. */ |
c906108c | 3169 | |
46e0f506 | 3170 | if (stack_used_p) |
1a69e1e4 | 3171 | stack_offset += align_up (partial_len, regsize); |
c906108c SS |
3172 | } |
3173 | } | |
9ace0497 AC |
3174 | if (mips_debug) |
3175 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
3176 | } |
3177 | ||
f10683bb | 3178 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3179 | |
0f71a2f6 JM |
3180 | /* Return adjusted stack pointer. */ |
3181 | return sp; | |
3182 | } | |
3183 | ||
a1f5b845 | 3184 | /* Determine the return value convention being used. */ |
6d82d43b | 3185 | |
9c8fdbfa | 3186 | static enum return_value_convention |
c055b101 | 3187 | mips_eabi_return_value (struct gdbarch *gdbarch, struct type *func_type, |
9c8fdbfa | 3188 | struct type *type, struct regcache *regcache, |
47a35522 | 3189 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 3190 | { |
609ba780 JM |
3191 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3192 | int fp_return_type = 0; | |
3193 | int offset, regnum, xfer; | |
3194 | ||
9c8fdbfa AC |
3195 | if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
3196 | return RETURN_VALUE_STRUCT_CONVENTION; | |
609ba780 JM |
3197 | |
3198 | /* Floating point type? */ | |
3199 | if (tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3200 | { | |
3201 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
3202 | fp_return_type = 1; | |
3203 | /* Structs with a single field of float type | |
3204 | are returned in a floating point register. */ | |
3205 | if ((TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3206 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3207 | && TYPE_NFIELDS (type) == 1) | |
3208 | { | |
3209 | struct type *fieldtype = TYPE_FIELD_TYPE (type, 0); | |
3210 | ||
3211 | if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT) | |
3212 | fp_return_type = 1; | |
3213 | } | |
3214 | } | |
3215 | ||
3216 | if (fp_return_type) | |
3217 | { | |
3218 | /* A floating-point value belongs in the least significant part | |
3219 | of FP0/FP1. */ | |
3220 | if (mips_debug) | |
3221 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3222 | regnum = mips_regnum (gdbarch)->fp0; | |
3223 | } | |
3224 | else | |
3225 | { | |
3226 | /* An integer value goes in V0/V1. */ | |
3227 | if (mips_debug) | |
3228 | fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n"); | |
3229 | regnum = MIPS_V0_REGNUM; | |
3230 | } | |
3231 | for (offset = 0; | |
3232 | offset < TYPE_LENGTH (type); | |
3233 | offset += mips_abi_regsize (gdbarch), regnum++) | |
3234 | { | |
3235 | xfer = mips_abi_regsize (gdbarch); | |
3236 | if (offset + xfer > TYPE_LENGTH (type)) | |
3237 | xfer = TYPE_LENGTH (type) - offset; | |
3238 | mips_xfer_register (gdbarch, regcache, | |
3239 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
3240 | gdbarch_byte_order (gdbarch), readbuf, writebuf, | |
3241 | offset); | |
3242 | } | |
3243 | ||
9c8fdbfa | 3244 | return RETURN_VALUE_REGISTER_CONVENTION; |
6d82d43b AC |
3245 | } |
3246 | ||
6d82d43b AC |
3247 | |
3248 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 3249 | |
8d26208a DJ |
3250 | /* Search for a naturally aligned double at OFFSET inside a struct |
3251 | ARG_TYPE. The N32 / N64 ABIs pass these in floating point | |
3252 | registers. */ | |
3253 | ||
3254 | static int | |
74ed0bb4 MD |
3255 | mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type, |
3256 | int offset) | |
8d26208a DJ |
3257 | { |
3258 | int i; | |
3259 | ||
3260 | if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT) | |
3261 | return 0; | |
3262 | ||
74ed0bb4 | 3263 | if (MIPS_FPU_TYPE (gdbarch) != MIPS_FPU_DOUBLE) |
8d26208a DJ |
3264 | return 0; |
3265 | ||
3266 | if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE) | |
3267 | return 0; | |
3268 | ||
3269 | for (i = 0; i < TYPE_NFIELDS (arg_type); i++) | |
3270 | { | |
3271 | int pos; | |
3272 | struct type *field_type; | |
3273 | ||
3274 | /* We're only looking at normal fields. */ | |
5bc60cfb | 3275 | if (field_is_static (&TYPE_FIELD (arg_type, i)) |
8d26208a DJ |
3276 | || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0) |
3277 | continue; | |
3278 | ||
3279 | /* If we have gone past the offset, there is no double to pass. */ | |
3280 | pos = TYPE_FIELD_BITPOS (arg_type, i) / 8; | |
3281 | if (pos > offset) | |
3282 | return 0; | |
3283 | ||
3284 | field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i)); | |
3285 | ||
3286 | /* If this field is entirely before the requested offset, go | |
3287 | on to the next one. */ | |
3288 | if (pos + TYPE_LENGTH (field_type) <= offset) | |
3289 | continue; | |
3290 | ||
3291 | /* If this is our special aligned double, we can stop. */ | |
3292 | if (TYPE_CODE (field_type) == TYPE_CODE_FLT | |
3293 | && TYPE_LENGTH (field_type) == MIPS64_REGSIZE) | |
3294 | return 1; | |
3295 | ||
3296 | /* This field starts at or before the requested offset, and | |
3297 | overlaps it. If it is a structure, recurse inwards. */ | |
74ed0bb4 | 3298 | return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos); |
8d26208a DJ |
3299 | } |
3300 | ||
3301 | return 0; | |
3302 | } | |
3303 | ||
f7ab6ec6 | 3304 | static CORE_ADDR |
7d9b040b | 3305 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3306 | struct regcache *regcache, CORE_ADDR bp_addr, |
3307 | int nargs, struct value **args, CORE_ADDR sp, | |
3308 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
3309 | { |
3310 | int argreg; | |
3311 | int float_argreg; | |
3312 | int argnum; | |
3313 | int len = 0; | |
3314 | int stack_offset = 0; | |
480d3dd2 | 3315 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 3316 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 3317 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 3318 | |
25ab4790 AC |
3319 | /* For shared libraries, "t9" needs to point at the function |
3320 | address. */ | |
4c7d22cb | 3321 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
3322 | |
3323 | /* Set the return address register to point to the entry point of | |
3324 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3325 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 3326 | |
cb3d25d1 MS |
3327 | /* First ensure that the stack and structure return address (if any) |
3328 | are properly aligned. The stack has to be at least 64-bit | |
3329 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3330 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3331 | aligned, so we round to this widest known alignment. */ | |
3332 | ||
5b03f266 AC |
3333 | sp = align_down (sp, 16); |
3334 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
3335 | |
3336 | /* Now make space on the stack for the args. */ | |
3337 | for (argnum = 0; argnum < nargs; argnum++) | |
1a69e1e4 | 3338 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE); |
5b03f266 | 3339 | sp -= align_up (len, 16); |
cb3d25d1 MS |
3340 | |
3341 | if (mips_debug) | |
6d82d43b | 3342 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
3343 | "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n", |
3344 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
3345 | |
3346 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3347 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 3348 | float_argreg = mips_fpa0_regnum (gdbarch); |
cb3d25d1 | 3349 | |
46e0f506 | 3350 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
3351 | if (struct_return) |
3352 | { | |
3353 | if (mips_debug) | |
3354 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
3355 | "mips_n32n64_push_dummy_call: " |
3356 | "struct_return reg=%d %s\n", | |
5af949e3 | 3357 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 3358 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
cb3d25d1 MS |
3359 | } |
3360 | ||
3361 | /* Now load as many as possible of the first arguments into | |
3362 | registers, and push the rest onto the stack. Loop thru args | |
3363 | from first to last. */ | |
3364 | for (argnum = 0; argnum < nargs; argnum++) | |
3365 | { | |
47a35522 | 3366 | const gdb_byte *val; |
cb3d25d1 | 3367 | struct value *arg = args[argnum]; |
4991999e | 3368 | struct type *arg_type = check_typedef (value_type (arg)); |
cb3d25d1 MS |
3369 | int len = TYPE_LENGTH (arg_type); |
3370 | enum type_code typecode = TYPE_CODE (arg_type); | |
3371 | ||
3372 | if (mips_debug) | |
3373 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3374 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
3375 | argnum + 1, len, (int) typecode); |
3376 | ||
47a35522 | 3377 | val = value_contents (arg); |
cb3d25d1 | 3378 | |
5b68030f JM |
3379 | /* A 128-bit long double value requires an even-odd pair of |
3380 | floating-point registers. */ | |
3381 | if (len == 16 | |
3382 | && fp_register_arg_p (gdbarch, typecode, arg_type) | |
3383 | && (float_argreg & 1)) | |
3384 | { | |
3385 | float_argreg++; | |
3386 | argreg++; | |
3387 | } | |
3388 | ||
74ed0bb4 MD |
3389 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
3390 | && argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) | |
cb3d25d1 MS |
3391 | { |
3392 | /* This is a floating point value that fits entirely | |
5b68030f JM |
3393 | in a single register or a pair of registers. */ |
3394 | int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE); | |
e17a4113 | 3395 | LONGEST regval = extract_unsigned_integer (val, reglen, byte_order); |
cb3d25d1 MS |
3396 | if (mips_debug) |
3397 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5b68030f | 3398 | float_argreg, phex (regval, reglen)); |
8d26208a | 3399 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); |
cb3d25d1 MS |
3400 | |
3401 | if (mips_debug) | |
3402 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5b68030f | 3403 | argreg, phex (regval, reglen)); |
9c9acae0 | 3404 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a DJ |
3405 | float_argreg++; |
3406 | argreg++; | |
5b68030f JM |
3407 | if (len == 16) |
3408 | { | |
e17a4113 UW |
3409 | regval = extract_unsigned_integer (val + reglen, |
3410 | reglen, byte_order); | |
5b68030f JM |
3411 | if (mips_debug) |
3412 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3413 | float_argreg, phex (regval, reglen)); | |
3414 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); | |
3415 | ||
3416 | if (mips_debug) | |
3417 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3418 | argreg, phex (regval, reglen)); | |
3419 | regcache_cooked_write_unsigned (regcache, argreg, regval); | |
3420 | float_argreg++; | |
3421 | argreg++; | |
3422 | } | |
cb3d25d1 MS |
3423 | } |
3424 | else | |
3425 | { | |
3426 | /* Copy the argument to general registers or the stack in | |
3427 | register-sized pieces. Large arguments are split between | |
3428 | registers and stack. */ | |
ab2e1992 MR |
3429 | /* For N32/N64, structs, unions, or other composite types are |
3430 | treated as a sequence of doublewords, and are passed in integer | |
3431 | or floating point registers as though they were simple scalar | |
3432 | parameters to the extent that they fit, with any excess on the | |
3433 | stack packed according to the normal memory layout of the | |
3434 | object. | |
3435 | The caller does not reserve space for the register arguments; | |
3436 | the callee is responsible for reserving it if required. */ | |
cb3d25d1 | 3437 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3438 | register are only written to memory. */ |
cb3d25d1 MS |
3439 | while (len > 0) |
3440 | { | |
ad018eee | 3441 | /* Remember if the argument was written to the stack. */ |
cb3d25d1 | 3442 | int stack_used_p = 0; |
1a69e1e4 | 3443 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
cb3d25d1 MS |
3444 | |
3445 | if (mips_debug) | |
3446 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3447 | partial_len); | |
3448 | ||
74ed0bb4 MD |
3449 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
3450 | gdb_assert (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)); | |
8d26208a | 3451 | |
cb3d25d1 | 3452 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 3453 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 MS |
3454 | { |
3455 | /* Should shorter than int integer values be | |
025bb325 | 3456 | promoted to int before being stored? */ |
cb3d25d1 MS |
3457 | int longword_offset = 0; |
3458 | CORE_ADDR addr; | |
3459 | stack_used_p = 1; | |
72a155b4 | 3460 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
cb3d25d1 | 3461 | { |
1a69e1e4 | 3462 | if ((typecode == TYPE_CODE_INT |
5b68030f | 3463 | || typecode == TYPE_CODE_PTR) |
1a69e1e4 DJ |
3464 | && len <= 4) |
3465 | longword_offset = MIPS64_REGSIZE - len; | |
cb3d25d1 MS |
3466 | } |
3467 | ||
3468 | if (mips_debug) | |
3469 | { | |
5af949e3 UW |
3470 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
3471 | paddress (gdbarch, stack_offset)); | |
3472 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
3473 | paddress (gdbarch, longword_offset)); | |
cb3d25d1 MS |
3474 | } |
3475 | ||
3476 | addr = sp + stack_offset + longword_offset; | |
3477 | ||
3478 | if (mips_debug) | |
3479 | { | |
3480 | int i; | |
5af949e3 UW |
3481 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
3482 | paddress (gdbarch, addr)); | |
cb3d25d1 MS |
3483 | for (i = 0; i < partial_len; i++) |
3484 | { | |
6d82d43b | 3485 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
3486 | val[i] & 0xff); |
3487 | } | |
3488 | } | |
3489 | write_memory (addr, val, partial_len); | |
3490 | } | |
3491 | ||
3492 | /* Note!!! This is NOT an else clause. Odd sized | |
8d26208a | 3493 | structs may go thru BOTH paths. */ |
cb3d25d1 | 3494 | /* Write this portion of the argument to a general |
6d82d43b | 3495 | purpose register. */ |
74ed0bb4 | 3496 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 | 3497 | { |
5863b5d5 MR |
3498 | LONGEST regval; |
3499 | ||
3500 | /* Sign extend pointers, 32-bit integers and signed | |
3501 | 16-bit and 8-bit integers; everything else is taken | |
3502 | as is. */ | |
3503 | ||
3504 | if ((partial_len == 4 | |
3505 | && (typecode == TYPE_CODE_PTR | |
3506 | || typecode == TYPE_CODE_INT)) | |
3507 | || (partial_len < 4 | |
3508 | && typecode == TYPE_CODE_INT | |
3509 | && !TYPE_UNSIGNED (arg_type))) | |
e17a4113 UW |
3510 | regval = extract_signed_integer (val, partial_len, |
3511 | byte_order); | |
5863b5d5 | 3512 | else |
e17a4113 UW |
3513 | regval = extract_unsigned_integer (val, partial_len, |
3514 | byte_order); | |
cb3d25d1 MS |
3515 | |
3516 | /* A non-floating-point argument being passed in a | |
3517 | general register. If a struct or union, and if | |
3518 | the remaining length is smaller than the register | |
3519 | size, we have to adjust the register value on | |
3520 | big endian targets. | |
3521 | ||
3522 | It does not seem to be necessary to do the | |
1a69e1e4 | 3523 | same for integral types. */ |
cb3d25d1 | 3524 | |
72a155b4 | 3525 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3526 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
3527 | && (typecode == TYPE_CODE_STRUCT |
3528 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3529 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 3530 | * TARGET_CHAR_BIT); |
cb3d25d1 MS |
3531 | |
3532 | if (mips_debug) | |
3533 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3534 | argreg, | |
1a69e1e4 | 3535 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 3536 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a | 3537 | |
74ed0bb4 | 3538 | if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type, |
8d26208a DJ |
3539 | TYPE_LENGTH (arg_type) - len)) |
3540 | { | |
3541 | if (mips_debug) | |
3542 | fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s", | |
3543 | float_argreg, | |
3544 | phex (regval, MIPS64_REGSIZE)); | |
3545 | regcache_cooked_write_unsigned (regcache, float_argreg, | |
3546 | regval); | |
3547 | } | |
3548 | ||
3549 | float_argreg++; | |
cb3d25d1 MS |
3550 | argreg++; |
3551 | } | |
3552 | ||
3553 | len -= partial_len; | |
3554 | val += partial_len; | |
3555 | ||
b021a221 MS |
3556 | /* Compute the offset into the stack at which we will |
3557 | copy the next parameter. | |
cb3d25d1 MS |
3558 | |
3559 | In N32 (N64?), the stack_offset only needs to be | |
3560 | adjusted when it has been used. */ | |
3561 | ||
3562 | if (stack_used_p) | |
1a69e1e4 | 3563 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
cb3d25d1 MS |
3564 | } |
3565 | } | |
3566 | if (mips_debug) | |
3567 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3568 | } | |
3569 | ||
f10683bb | 3570 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3571 | |
cb3d25d1 MS |
3572 | /* Return adjusted stack pointer. */ |
3573 | return sp; | |
3574 | } | |
3575 | ||
6d82d43b | 3576 | static enum return_value_convention |
c055b101 | 3577 | mips_n32n64_return_value (struct gdbarch *gdbarch, struct type *func_type, |
6d82d43b | 3578 | struct type *type, struct regcache *regcache, |
47a35522 | 3579 | gdb_byte *readbuf, const gdb_byte *writebuf) |
ebafbe83 | 3580 | { |
72a155b4 | 3581 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
b18bb924 MR |
3582 | |
3583 | /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004 | |
3584 | ||
3585 | Function results are returned in $2 (and $3 if needed), or $f0 (and $f2 | |
3586 | if needed), as appropriate for the type. Composite results (struct, | |
3587 | union, or array) are returned in $2/$f0 and $3/$f2 according to the | |
3588 | following rules: | |
3589 | ||
3590 | * A struct with only one or two floating point fields is returned in $f0 | |
3591 | (and $f2 if necessary). This is a generalization of the Fortran COMPLEX | |
3592 | case. | |
3593 | ||
f08877ba | 3594 | * Any other composite results of at most 128 bits are returned in |
b18bb924 MR |
3595 | $2 (first 64 bits) and $3 (remainder, if necessary). |
3596 | ||
3597 | * Larger composite results are handled by converting the function to a | |
3598 | procedure with an implicit first parameter, which is a pointer to an area | |
3599 | reserved by the caller to receive the result. [The o32-bit ABI requires | |
3600 | that all composite results be handled by conversion to implicit first | |
3601 | parameters. The MIPS/SGI Fortran implementation has always made a | |
3602 | specific exception to return COMPLEX results in the floating point | |
3603 | registers.] */ | |
3604 | ||
f08877ba | 3605 | if (TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE) |
6d82d43b | 3606 | return RETURN_VALUE_STRUCT_CONVENTION; |
d05f6826 DJ |
3607 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3608 | && TYPE_LENGTH (type) == 16 | |
3609 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3610 | { | |
3611 | /* A 128-bit floating-point value fills both $f0 and $f2. The | |
3612 | two registers are used in the same as memory order, so the | |
3613 | eight bytes with the lower memory address are in $f0. */ | |
3614 | if (mips_debug) | |
3615 | fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n"); | |
ba32f989 | 3616 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3617 | gdbarch_num_regs (gdbarch) |
3618 | + mips_regnum (gdbarch)->fp0, | |
3619 | 8, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3620 | readbuf, writebuf, 0); |
ba32f989 | 3621 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3622 | gdbarch_num_regs (gdbarch) |
3623 | + mips_regnum (gdbarch)->fp0 + 2, | |
3624 | 8, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3625 | readbuf ? readbuf + 8 : readbuf, |
d05f6826 DJ |
3626 | writebuf ? writebuf + 8 : writebuf, 0); |
3627 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3628 | } | |
6d82d43b AC |
3629 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3630 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3631 | { | |
59aa1faa | 3632 | /* A single or double floating-point value that fits in FP0. */ |
6d82d43b AC |
3633 | if (mips_debug) |
3634 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 3635 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3636 | gdbarch_num_regs (gdbarch) |
3637 | + mips_regnum (gdbarch)->fp0, | |
6d82d43b | 3638 | TYPE_LENGTH (type), |
72a155b4 | 3639 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3640 | readbuf, writebuf, 0); |
6d82d43b AC |
3641 | return RETURN_VALUE_REGISTER_CONVENTION; |
3642 | } | |
3643 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3644 | && TYPE_NFIELDS (type) <= 2 | |
3645 | && TYPE_NFIELDS (type) >= 1 | |
3646 | && ((TYPE_NFIELDS (type) == 1 | |
b18bb924 | 3647 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b AC |
3648 | == TYPE_CODE_FLT)) |
3649 | || (TYPE_NFIELDS (type) == 2 | |
b18bb924 | 3650 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b | 3651 | == TYPE_CODE_FLT) |
b18bb924 | 3652 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1))) |
5b68030f | 3653 | == TYPE_CODE_FLT)))) |
6d82d43b AC |
3654 | { |
3655 | /* A struct that contains one or two floats. Each value is part | |
3656 | in the least significant part of their floating point | |
5b68030f | 3657 | register (or GPR, for soft float). */ |
6d82d43b AC |
3658 | int regnum; |
3659 | int field; | |
5b68030f JM |
3660 | for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE |
3661 | ? mips_regnum (gdbarch)->fp0 | |
3662 | : MIPS_V0_REGNUM); | |
6d82d43b AC |
3663 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
3664 | { | |
3665 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3666 | / TARGET_CHAR_BIT); | |
3667 | if (mips_debug) | |
3668 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3669 | offset); | |
5b68030f JM |
3670 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)) == 16) |
3671 | { | |
3672 | /* A 16-byte long double field goes in two consecutive | |
3673 | registers. */ | |
3674 | mips_xfer_register (gdbarch, regcache, | |
3675 | gdbarch_num_regs (gdbarch) + regnum, | |
3676 | 8, | |
3677 | gdbarch_byte_order (gdbarch), | |
3678 | readbuf, writebuf, offset); | |
3679 | mips_xfer_register (gdbarch, regcache, | |
3680 | gdbarch_num_regs (gdbarch) + regnum + 1, | |
3681 | 8, | |
3682 | gdbarch_byte_order (gdbarch), | |
3683 | readbuf, writebuf, offset + 8); | |
3684 | } | |
3685 | else | |
3686 | mips_xfer_register (gdbarch, regcache, | |
3687 | gdbarch_num_regs (gdbarch) + regnum, | |
3688 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
3689 | gdbarch_byte_order (gdbarch), | |
3690 | readbuf, writebuf, offset); | |
6d82d43b AC |
3691 | } |
3692 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3693 | } | |
3694 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
f08877ba JB |
3695 | || TYPE_CODE (type) == TYPE_CODE_UNION |
3696 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
6d82d43b | 3697 | { |
f08877ba | 3698 | /* A composite type. Extract the left justified value, |
6d82d43b AC |
3699 | regardless of the byte order. I.e. DO NOT USE |
3700 | mips_xfer_lower. */ | |
3701 | int offset; | |
3702 | int regnum; | |
4c7d22cb | 3703 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3704 | offset < TYPE_LENGTH (type); |
72a155b4 | 3705 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3706 | { |
72a155b4 | 3707 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3708 | if (offset + xfer > TYPE_LENGTH (type)) |
3709 | xfer = TYPE_LENGTH (type) - offset; | |
3710 | if (mips_debug) | |
3711 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3712 | offset, xfer, regnum); | |
ba32f989 DJ |
3713 | mips_xfer_register (gdbarch, regcache, |
3714 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 UW |
3715 | xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf, |
3716 | offset); | |
6d82d43b AC |
3717 | } |
3718 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3719 | } | |
3720 | else | |
3721 | { | |
3722 | /* A scalar extract each part but least-significant-byte | |
3723 | justified. */ | |
3724 | int offset; | |
3725 | int regnum; | |
4c7d22cb | 3726 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3727 | offset < TYPE_LENGTH (type); |
72a155b4 | 3728 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3729 | { |
72a155b4 | 3730 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3731 | if (offset + xfer > TYPE_LENGTH (type)) |
3732 | xfer = TYPE_LENGTH (type) - offset; | |
3733 | if (mips_debug) | |
3734 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3735 | offset, xfer, regnum); | |
ba32f989 DJ |
3736 | mips_xfer_register (gdbarch, regcache, |
3737 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 3738 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 3739 | readbuf, writebuf, offset); |
6d82d43b AC |
3740 | } |
3741 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3742 | } | |
3743 | } | |
3744 | ||
3745 | /* O32 ABI stuff. */ | |
3746 | ||
3747 | static CORE_ADDR | |
7d9b040b | 3748 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3749 | struct regcache *regcache, CORE_ADDR bp_addr, |
3750 | int nargs, struct value **args, CORE_ADDR sp, | |
3751 | int struct_return, CORE_ADDR struct_addr) | |
3752 | { | |
3753 | int argreg; | |
3754 | int float_argreg; | |
3755 | int argnum; | |
3756 | int len = 0; | |
3757 | int stack_offset = 0; | |
3758 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
e17a4113 | 3759 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 3760 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
3761 | |
3762 | /* For shared libraries, "t9" needs to point at the function | |
3763 | address. */ | |
4c7d22cb | 3764 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
6d82d43b AC |
3765 | |
3766 | /* Set the return address register to point to the entry point of | |
3767 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3768 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
6d82d43b AC |
3769 | |
3770 | /* First ensure that the stack and structure return address (if any) | |
3771 | are properly aligned. The stack has to be at least 64-bit | |
3772 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
3773 | aligned. For n32 and n64, stack frames need to be 128-bit |
3774 | aligned, so we round to this widest known alignment. */ | |
3775 | ||
5b03f266 AC |
3776 | sp = align_down (sp, 16); |
3777 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
3778 | |
3779 | /* Now make space on the stack for the args. */ | |
3780 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
3781 | { |
3782 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
3783 | int arglen = TYPE_LENGTH (arg_type); | |
3784 | ||
3785 | /* Align to double-word if necessary. */ | |
2afd3f0a | 3786 | if (mips_type_needs_double_align (arg_type)) |
1a69e1e4 | 3787 | len = align_up (len, MIPS32_REGSIZE * 2); |
968b5391 | 3788 | /* Allocate space on the stack. */ |
1a69e1e4 | 3789 | len += align_up (arglen, MIPS32_REGSIZE); |
968b5391 | 3790 | } |
5b03f266 | 3791 | sp -= align_up (len, 16); |
ebafbe83 MS |
3792 | |
3793 | if (mips_debug) | |
6d82d43b | 3794 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
3795 | "mips_o32_push_dummy_call: sp=%s allocated %ld\n", |
3796 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
3797 | |
3798 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3799 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 3800 | float_argreg = mips_fpa0_regnum (gdbarch); |
ebafbe83 | 3801 | |
bcb0cc15 | 3802 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3803 | if (struct_return) |
3804 | { | |
3805 | if (mips_debug) | |
3806 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
3807 | "mips_o32_push_dummy_call: " |
3808 | "struct_return reg=%d %s\n", | |
5af949e3 | 3809 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 3810 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 3811 | stack_offset += MIPS32_REGSIZE; |
ebafbe83 MS |
3812 | } |
3813 | ||
3814 | /* Now load as many as possible of the first arguments into | |
3815 | registers, and push the rest onto the stack. Loop thru args | |
3816 | from first to last. */ | |
3817 | for (argnum = 0; argnum < nargs; argnum++) | |
3818 | { | |
47a35522 | 3819 | const gdb_byte *val; |
ebafbe83 | 3820 | struct value *arg = args[argnum]; |
4991999e | 3821 | struct type *arg_type = check_typedef (value_type (arg)); |
ebafbe83 MS |
3822 | int len = TYPE_LENGTH (arg_type); |
3823 | enum type_code typecode = TYPE_CODE (arg_type); | |
3824 | ||
3825 | if (mips_debug) | |
3826 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3827 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3828 | argnum + 1, len, (int) typecode); |
3829 | ||
47a35522 | 3830 | val = value_contents (arg); |
46cac009 AC |
3831 | |
3832 | /* 32-bit ABIs always start floating point arguments in an | |
3833 | even-numbered floating point register. Round the FP register | |
3834 | up before the check to see if there are any FP registers | |
3835 | left. O32/O64 targets also pass the FP in the integer | |
3836 | registers so also round up normal registers. */ | |
74ed0bb4 | 3837 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
46cac009 AC |
3838 | { |
3839 | if ((float_argreg & 1)) | |
3840 | float_argreg++; | |
3841 | } | |
3842 | ||
3843 | /* Floating point arguments passed in registers have to be | |
3844 | treated specially. On 32-bit architectures, doubles | |
3845 | are passed in register pairs; the even register gets | |
3846 | the low word, and the odd register gets the high word. | |
3847 | On O32/O64, the first two floating point arguments are | |
3848 | also copied to general registers, because MIPS16 functions | |
3849 | don't use float registers for arguments. This duplication of | |
3850 | arguments in general registers can't hurt non-MIPS16 functions | |
3851 | because those registers are normally skipped. */ | |
3852 | ||
74ed0bb4 MD |
3853 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
3854 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
46cac009 | 3855 | { |
8b07f6d8 | 3856 | if (register_size (gdbarch, float_argreg) < 8 && len == 8) |
46cac009 | 3857 | { |
72a155b4 | 3858 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 3859 | == BFD_ENDIAN_BIG ? 4 : 0; |
46cac009 AC |
3860 | unsigned long regval; |
3861 | ||
3862 | /* Write the low word of the double to the even register(s). */ | |
e17a4113 UW |
3863 | regval = extract_unsigned_integer (val + low_offset, |
3864 | 4, byte_order); | |
46cac009 AC |
3865 | if (mips_debug) |
3866 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3867 | float_argreg, phex (regval, 4)); | |
025bb325 MS |
3868 | regcache_cooked_write_unsigned (regcache, |
3869 | float_argreg++, regval); | |
46cac009 AC |
3870 | if (mips_debug) |
3871 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3872 | argreg, phex (regval, 4)); | |
9c9acae0 | 3873 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3874 | |
3875 | /* Write the high word of the double to the odd register(s). */ | |
e17a4113 UW |
3876 | regval = extract_unsigned_integer (val + 4 - low_offset, |
3877 | 4, byte_order); | |
46cac009 AC |
3878 | if (mips_debug) |
3879 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3880 | float_argreg, phex (regval, 4)); | |
025bb325 MS |
3881 | regcache_cooked_write_unsigned (regcache, |
3882 | float_argreg++, regval); | |
46cac009 AC |
3883 | |
3884 | if (mips_debug) | |
3885 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3886 | argreg, phex (regval, 4)); | |
9c9acae0 | 3887 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3888 | } |
3889 | else | |
3890 | { | |
3891 | /* This is a floating point value that fits entirely | |
3892 | in a single register. */ | |
3893 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 3894 | above to ensure that it is even register aligned. */ |
e17a4113 | 3895 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
46cac009 AC |
3896 | if (mips_debug) |
3897 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3898 | float_argreg, phex (regval, len)); | |
025bb325 MS |
3899 | regcache_cooked_write_unsigned (regcache, |
3900 | float_argreg++, regval); | |
5b68030f JM |
3901 | /* Although two FP registers are reserved for each |
3902 | argument, only one corresponding integer register is | |
3903 | reserved. */ | |
46cac009 AC |
3904 | if (mips_debug) |
3905 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3906 | argreg, phex (regval, len)); | |
5b68030f | 3907 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3908 | } |
3909 | /* Reserve space for the FP register. */ | |
1a69e1e4 | 3910 | stack_offset += align_up (len, MIPS32_REGSIZE); |
46cac009 AC |
3911 | } |
3912 | else | |
3913 | { | |
3914 | /* Copy the argument to general registers or the stack in | |
3915 | register-sized pieces. Large arguments are split between | |
3916 | registers and stack. */ | |
1a69e1e4 DJ |
3917 | /* Note: structs whose size is not a multiple of MIPS32_REGSIZE |
3918 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
3919 | them in registers where gcc sometimes puts them on the |
3920 | stack. For maximum compatibility, we will put them in | |
3921 | both places. */ | |
1a69e1e4 DJ |
3922 | int odd_sized_struct = (len > MIPS32_REGSIZE |
3923 | && len % MIPS32_REGSIZE != 0); | |
46cac009 AC |
3924 | /* Structures should be aligned to eight bytes (even arg registers) |
3925 | on MIPS_ABI_O32, if their first member has double precision. */ | |
2afd3f0a | 3926 | if (mips_type_needs_double_align (arg_type)) |
46cac009 AC |
3927 | { |
3928 | if ((argreg & 1)) | |
968b5391 MR |
3929 | { |
3930 | argreg++; | |
1a69e1e4 | 3931 | stack_offset += MIPS32_REGSIZE; |
968b5391 | 3932 | } |
46cac009 | 3933 | } |
46cac009 AC |
3934 | while (len > 0) |
3935 | { | |
3936 | /* Remember if the argument was written to the stack. */ | |
3937 | int stack_used_p = 0; | |
1a69e1e4 | 3938 | int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); |
46cac009 AC |
3939 | |
3940 | if (mips_debug) | |
3941 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3942 | partial_len); | |
3943 | ||
3944 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 3945 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 3946 | || odd_sized_struct) |
46cac009 AC |
3947 | { |
3948 | /* Should shorter than int integer values be | |
025bb325 | 3949 | promoted to int before being stored? */ |
46cac009 AC |
3950 | int longword_offset = 0; |
3951 | CORE_ADDR addr; | |
3952 | stack_used_p = 1; | |
46cac009 AC |
3953 | |
3954 | if (mips_debug) | |
3955 | { | |
5af949e3 UW |
3956 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
3957 | paddress (gdbarch, stack_offset)); | |
3958 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
3959 | paddress (gdbarch, longword_offset)); | |
46cac009 AC |
3960 | } |
3961 | ||
3962 | addr = sp + stack_offset + longword_offset; | |
3963 | ||
3964 | if (mips_debug) | |
3965 | { | |
3966 | int i; | |
5af949e3 UW |
3967 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
3968 | paddress (gdbarch, addr)); | |
46cac009 AC |
3969 | for (i = 0; i < partial_len; i++) |
3970 | { | |
6d82d43b | 3971 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
3972 | val[i] & 0xff); |
3973 | } | |
3974 | } | |
3975 | write_memory (addr, val, partial_len); | |
3976 | } | |
3977 | ||
3978 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 3979 | structs may go thru BOTH paths. */ |
46cac009 | 3980 | /* Write this portion of the argument to a general |
6d82d43b | 3981 | purpose register. */ |
74ed0bb4 | 3982 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
46cac009 | 3983 | { |
e17a4113 UW |
3984 | LONGEST regval = extract_signed_integer (val, partial_len, |
3985 | byte_order); | |
4246e332 | 3986 | /* Value may need to be sign extended, because |
1b13c4f6 | 3987 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
3988 | |
3989 | /* A non-floating-point argument being passed in a | |
3990 | general register. If a struct or union, and if | |
3991 | the remaining length is smaller than the register | |
3992 | size, we have to adjust the register value on | |
3993 | big endian targets. | |
3994 | ||
3995 | It does not seem to be necessary to do the | |
3996 | same for integral types. | |
3997 | ||
3998 | Also don't do this adjustment on O64 binaries. | |
3999 | ||
4000 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
4001 | outputting LE O32 with sizeof (struct) < | |
e914cb17 MR |
4002 | mips_abi_regsize(), generates a left shift |
4003 | as part of storing the argument in a register | |
4004 | (the left shift isn't generated when | |
1b13c4f6 | 4005 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
4006 | it is quite possible that this is GCC |
4007 | contradicting the LE/O32 ABI, GDB has not been | |
4008 | adjusted to accommodate this. Either someone | |
4009 | needs to demonstrate that the LE/O32 ABI | |
4010 | specifies such a left shift OR this new ABI gets | |
4011 | identified as such and GDB gets tweaked | |
4012 | accordingly. */ | |
4013 | ||
72a155b4 | 4014 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 4015 | && partial_len < MIPS32_REGSIZE |
06f9a1af MR |
4016 | && (typecode == TYPE_CODE_STRUCT |
4017 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 4018 | regval <<= ((MIPS32_REGSIZE - partial_len) |
9ecf7166 | 4019 | * TARGET_CHAR_BIT); |
46cac009 AC |
4020 | |
4021 | if (mips_debug) | |
4022 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
4023 | argreg, | |
1a69e1e4 | 4024 | phex (regval, MIPS32_REGSIZE)); |
9c9acae0 | 4025 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
46cac009 AC |
4026 | argreg++; |
4027 | ||
4028 | /* Prevent subsequent floating point arguments from | |
4029 | being passed in floating point registers. */ | |
74ed0bb4 | 4030 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
46cac009 AC |
4031 | } |
4032 | ||
4033 | len -= partial_len; | |
4034 | val += partial_len; | |
4035 | ||
b021a221 MS |
4036 | /* Compute the offset into the stack at which we will |
4037 | copy the next parameter. | |
46cac009 | 4038 | |
6d82d43b AC |
4039 | In older ABIs, the caller reserved space for |
4040 | registers that contained arguments. This was loosely | |
4041 | refered to as their "home". Consequently, space is | |
4042 | always allocated. */ | |
46cac009 | 4043 | |
1a69e1e4 | 4044 | stack_offset += align_up (partial_len, MIPS32_REGSIZE); |
46cac009 AC |
4045 | } |
4046 | } | |
4047 | if (mips_debug) | |
4048 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
4049 | } | |
4050 | ||
f10683bb | 4051 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4052 | |
46cac009 AC |
4053 | /* Return adjusted stack pointer. */ |
4054 | return sp; | |
4055 | } | |
4056 | ||
6d82d43b | 4057 | static enum return_value_convention |
c055b101 CV |
4058 | mips_o32_return_value (struct gdbarch *gdbarch, struct type *func_type, |
4059 | struct type *type, struct regcache *regcache, | |
47a35522 | 4060 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 4061 | { |
72a155b4 | 4062 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
6d82d43b AC |
4063 | |
4064 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4065 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
4066 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
4067 | return RETURN_VALUE_STRUCT_CONVENTION; | |
4068 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4069 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4070 | { | |
4071 | /* A single-precision floating-point value. It fits in the | |
4072 | least significant part of FP0. */ | |
4073 | if (mips_debug) | |
4074 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 4075 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4076 | gdbarch_num_regs (gdbarch) |
4077 | + mips_regnum (gdbarch)->fp0, | |
6d82d43b | 4078 | TYPE_LENGTH (type), |
72a155b4 | 4079 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4080 | readbuf, writebuf, 0); |
6d82d43b AC |
4081 | return RETURN_VALUE_REGISTER_CONVENTION; |
4082 | } | |
4083 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4084 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4085 | { | |
4086 | /* A double-precision floating-point value. The most | |
4087 | significant part goes in FP1, and the least significant in | |
4088 | FP0. */ | |
4089 | if (mips_debug) | |
4090 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
72a155b4 | 4091 | switch (gdbarch_byte_order (gdbarch)) |
6d82d43b AC |
4092 | { |
4093 | case BFD_ENDIAN_LITTLE: | |
ba32f989 | 4094 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4095 | gdbarch_num_regs (gdbarch) |
4096 | + mips_regnum (gdbarch)->fp0 + | |
4097 | 0, 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 4098 | readbuf, writebuf, 0); |
ba32f989 | 4099 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4100 | gdbarch_num_regs (gdbarch) |
4101 | + mips_regnum (gdbarch)->fp0 + 1, | |
4102 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 4103 | readbuf, writebuf, 4); |
6d82d43b AC |
4104 | break; |
4105 | case BFD_ENDIAN_BIG: | |
ba32f989 | 4106 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4107 | gdbarch_num_regs (gdbarch) |
4108 | + mips_regnum (gdbarch)->fp0 + 1, | |
4109 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 4110 | readbuf, writebuf, 0); |
ba32f989 | 4111 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4112 | gdbarch_num_regs (gdbarch) |
4113 | + mips_regnum (gdbarch)->fp0 + 0, | |
4114 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 4115 | readbuf, writebuf, 4); |
6d82d43b AC |
4116 | break; |
4117 | default: | |
e2e0b3e5 | 4118 | internal_error (__FILE__, __LINE__, _("bad switch")); |
6d82d43b AC |
4119 | } |
4120 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4121 | } | |
4122 | #if 0 | |
4123 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4124 | && TYPE_NFIELDS (type) <= 2 | |
4125 | && TYPE_NFIELDS (type) >= 1 | |
4126 | && ((TYPE_NFIELDS (type) == 1 | |
4127 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4128 | == TYPE_CODE_FLT)) | |
4129 | || (TYPE_NFIELDS (type) == 2 | |
4130 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4131 | == TYPE_CODE_FLT) | |
4132 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
4133 | == TYPE_CODE_FLT))) | |
4134 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4135 | { | |
4136 | /* A struct that contains one or two floats. Each value is part | |
4137 | in the least significant part of their floating point | |
4138 | register.. */ | |
870cd05e | 4139 | gdb_byte reg[MAX_REGISTER_SIZE]; |
6d82d43b AC |
4140 | int regnum; |
4141 | int field; | |
72a155b4 | 4142 | for (field = 0, regnum = mips_regnum (gdbarch)->fp0; |
6d82d43b AC |
4143 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
4144 | { | |
4145 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
4146 | / TARGET_CHAR_BIT); | |
4147 | if (mips_debug) | |
4148 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
4149 | offset); | |
ba32f989 DJ |
4150 | mips_xfer_register (gdbarch, regcache, |
4151 | gdbarch_num_regs (gdbarch) + regnum, | |
6d82d43b | 4152 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
72a155b4 | 4153 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4154 | readbuf, writebuf, offset); |
6d82d43b AC |
4155 | } |
4156 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4157 | } | |
4158 | #endif | |
4159 | #if 0 | |
4160 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4161 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4162 | { | |
4163 | /* A structure or union. Extract the left justified value, | |
4164 | regardless of the byte order. I.e. DO NOT USE | |
4165 | mips_xfer_lower. */ | |
4166 | int offset; | |
4167 | int regnum; | |
4c7d22cb | 4168 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 4169 | offset < TYPE_LENGTH (type); |
72a155b4 | 4170 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 4171 | { |
72a155b4 | 4172 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
4173 | if (offset + xfer > TYPE_LENGTH (type)) |
4174 | xfer = TYPE_LENGTH (type) - offset; | |
4175 | if (mips_debug) | |
4176 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
4177 | offset, xfer, regnum); | |
ba32f989 DJ |
4178 | mips_xfer_register (gdbarch, regcache, |
4179 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
6d82d43b AC |
4180 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
4181 | } | |
4182 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4183 | } | |
4184 | #endif | |
4185 | else | |
4186 | { | |
4187 | /* A scalar extract each part but least-significant-byte | |
4188 | justified. o32 thinks registers are 4 byte, regardless of | |
1a69e1e4 | 4189 | the ISA. */ |
6d82d43b AC |
4190 | int offset; |
4191 | int regnum; | |
4c7d22cb | 4192 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 4193 | offset < TYPE_LENGTH (type); |
1a69e1e4 | 4194 | offset += MIPS32_REGSIZE, regnum++) |
6d82d43b | 4195 | { |
1a69e1e4 | 4196 | int xfer = MIPS32_REGSIZE; |
6d82d43b AC |
4197 | if (offset + xfer > TYPE_LENGTH (type)) |
4198 | xfer = TYPE_LENGTH (type) - offset; | |
4199 | if (mips_debug) | |
4200 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4201 | offset, xfer, regnum); | |
ba32f989 DJ |
4202 | mips_xfer_register (gdbarch, regcache, |
4203 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
72a155b4 | 4204 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4205 | readbuf, writebuf, offset); |
6d82d43b AC |
4206 | } |
4207 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4208 | } | |
4209 | } | |
4210 | ||
4211 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
4212 | ABI. */ | |
46cac009 AC |
4213 | |
4214 | static CORE_ADDR | |
7d9b040b | 4215 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4216 | struct regcache *regcache, CORE_ADDR bp_addr, |
4217 | int nargs, | |
4218 | struct value **args, CORE_ADDR sp, | |
4219 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
4220 | { |
4221 | int argreg; | |
4222 | int float_argreg; | |
4223 | int argnum; | |
4224 | int len = 0; | |
4225 | int stack_offset = 0; | |
480d3dd2 | 4226 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 4227 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 4228 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 4229 | |
25ab4790 AC |
4230 | /* For shared libraries, "t9" needs to point at the function |
4231 | address. */ | |
4c7d22cb | 4232 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
4233 | |
4234 | /* Set the return address register to point to the entry point of | |
4235 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 4236 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 4237 | |
46cac009 AC |
4238 | /* First ensure that the stack and structure return address (if any) |
4239 | are properly aligned. The stack has to be at least 64-bit | |
4240 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4241 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4242 | aligned, so we round to this widest known alignment. */ | |
4243 | ||
5b03f266 AC |
4244 | sp = align_down (sp, 16); |
4245 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
4246 | |
4247 | /* Now make space on the stack for the args. */ | |
4248 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
4249 | { |
4250 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
4251 | int arglen = TYPE_LENGTH (arg_type); | |
4252 | ||
968b5391 | 4253 | /* Allocate space on the stack. */ |
1a69e1e4 | 4254 | len += align_up (arglen, MIPS64_REGSIZE); |
968b5391 | 4255 | } |
5b03f266 | 4256 | sp -= align_up (len, 16); |
46cac009 AC |
4257 | |
4258 | if (mips_debug) | |
6d82d43b | 4259 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
4260 | "mips_o64_push_dummy_call: sp=%s allocated %ld\n", |
4261 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
46cac009 AC |
4262 | |
4263 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 4264 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 4265 | float_argreg = mips_fpa0_regnum (gdbarch); |
46cac009 AC |
4266 | |
4267 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
4268 | if (struct_return) | |
4269 | { | |
4270 | if (mips_debug) | |
4271 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
4272 | "mips_o64_push_dummy_call: " |
4273 | "struct_return reg=%d %s\n", | |
5af949e3 | 4274 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 4275 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 4276 | stack_offset += MIPS64_REGSIZE; |
46cac009 AC |
4277 | } |
4278 | ||
4279 | /* Now load as many as possible of the first arguments into | |
4280 | registers, and push the rest onto the stack. Loop thru args | |
4281 | from first to last. */ | |
4282 | for (argnum = 0; argnum < nargs; argnum++) | |
4283 | { | |
47a35522 | 4284 | const gdb_byte *val; |
930bd0e0 | 4285 | gdb_byte valbuf[MAX_REGISTER_SIZE]; |
46cac009 | 4286 | struct value *arg = args[argnum]; |
4991999e | 4287 | struct type *arg_type = check_typedef (value_type (arg)); |
46cac009 AC |
4288 | int len = TYPE_LENGTH (arg_type); |
4289 | enum type_code typecode = TYPE_CODE (arg_type); | |
4290 | ||
4291 | if (mips_debug) | |
4292 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4293 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
4294 | argnum + 1, len, (int) typecode); |
4295 | ||
47a35522 | 4296 | val = value_contents (arg); |
ebafbe83 | 4297 | |
930bd0e0 KB |
4298 | /* Function pointer arguments to mips16 code need to be made into |
4299 | mips16 pointers. */ | |
4300 | if (typecode == TYPE_CODE_PTR | |
4301 | && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC) | |
4302 | { | |
4303 | CORE_ADDR addr = extract_signed_integer (value_contents (arg), | |
4304 | len, byte_order); | |
4305 | if (mips_pc_is_mips16 (addr)) | |
4306 | { | |
4307 | store_signed_integer (valbuf, len, byte_order, | |
4308 | make_mips16_addr (addr)); | |
4309 | val = valbuf; | |
4310 | } | |
4311 | } | |
4312 | ||
ebafbe83 MS |
4313 | /* Floating point arguments passed in registers have to be |
4314 | treated specially. On 32-bit architectures, doubles | |
4315 | are passed in register pairs; the even register gets | |
4316 | the low word, and the odd register gets the high word. | |
4317 | On O32/O64, the first two floating point arguments are | |
4318 | also copied to general registers, because MIPS16 functions | |
4319 | don't use float registers for arguments. This duplication of | |
4320 | arguments in general registers can't hurt non-MIPS16 functions | |
4321 | because those registers are normally skipped. */ | |
4322 | ||
74ed0bb4 MD |
4323 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
4324 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
ebafbe83 | 4325 | { |
e17a4113 | 4326 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
2afd3f0a MR |
4327 | if (mips_debug) |
4328 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4329 | float_argreg, phex (regval, len)); | |
9c9acae0 | 4330 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
2afd3f0a MR |
4331 | if (mips_debug) |
4332 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4333 | argreg, phex (regval, len)); | |
9c9acae0 | 4334 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
2afd3f0a | 4335 | argreg++; |
ebafbe83 | 4336 | /* Reserve space for the FP register. */ |
1a69e1e4 | 4337 | stack_offset += align_up (len, MIPS64_REGSIZE); |
ebafbe83 MS |
4338 | } |
4339 | else | |
4340 | { | |
4341 | /* Copy the argument to general registers or the stack in | |
4342 | register-sized pieces. Large arguments are split between | |
4343 | registers and stack. */ | |
1a69e1e4 | 4344 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
4345 | are treated specially: Irix cc passes them in registers |
4346 | where gcc sometimes puts them on the stack. For maximum | |
4347 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
4348 | int odd_sized_struct = (len > MIPS64_REGSIZE |
4349 | && len % MIPS64_REGSIZE != 0); | |
ebafbe83 MS |
4350 | while (len > 0) |
4351 | { | |
4352 | /* Remember if the argument was written to the stack. */ | |
4353 | int stack_used_p = 0; | |
1a69e1e4 | 4354 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
ebafbe83 MS |
4355 | |
4356 | if (mips_debug) | |
4357 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4358 | partial_len); | |
4359 | ||
4360 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 4361 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 4362 | || odd_sized_struct) |
ebafbe83 MS |
4363 | { |
4364 | /* Should shorter than int integer values be | |
025bb325 | 4365 | promoted to int before being stored? */ |
ebafbe83 MS |
4366 | int longword_offset = 0; |
4367 | CORE_ADDR addr; | |
4368 | stack_used_p = 1; | |
72a155b4 | 4369 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ebafbe83 | 4370 | { |
1a69e1e4 DJ |
4371 | if ((typecode == TYPE_CODE_INT |
4372 | || typecode == TYPE_CODE_PTR | |
4373 | || typecode == TYPE_CODE_FLT) | |
4374 | && len <= 4) | |
4375 | longword_offset = MIPS64_REGSIZE - len; | |
ebafbe83 MS |
4376 | } |
4377 | ||
4378 | if (mips_debug) | |
4379 | { | |
5af949e3 UW |
4380 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
4381 | paddress (gdbarch, stack_offset)); | |
4382 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
4383 | paddress (gdbarch, longword_offset)); | |
ebafbe83 MS |
4384 | } |
4385 | ||
4386 | addr = sp + stack_offset + longword_offset; | |
4387 | ||
4388 | if (mips_debug) | |
4389 | { | |
4390 | int i; | |
5af949e3 UW |
4391 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
4392 | paddress (gdbarch, addr)); | |
ebafbe83 MS |
4393 | for (i = 0; i < partial_len; i++) |
4394 | { | |
6d82d43b | 4395 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
4396 | val[i] & 0xff); |
4397 | } | |
4398 | } | |
4399 | write_memory (addr, val, partial_len); | |
4400 | } | |
4401 | ||
4402 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 4403 | structs may go thru BOTH paths. */ |
ebafbe83 | 4404 | /* Write this portion of the argument to a general |
6d82d43b | 4405 | purpose register. */ |
74ed0bb4 | 4406 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
ebafbe83 | 4407 | { |
e17a4113 UW |
4408 | LONGEST regval = extract_signed_integer (val, partial_len, |
4409 | byte_order); | |
4246e332 | 4410 | /* Value may need to be sign extended, because |
1b13c4f6 | 4411 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
4412 | |
4413 | /* A non-floating-point argument being passed in a | |
4414 | general register. If a struct or union, and if | |
4415 | the remaining length is smaller than the register | |
4416 | size, we have to adjust the register value on | |
4417 | big endian targets. | |
4418 | ||
4419 | It does not seem to be necessary to do the | |
025bb325 | 4420 | same for integral types. */ |
480d3dd2 | 4421 | |
72a155b4 | 4422 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 4423 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
4424 | && (typecode == TYPE_CODE_STRUCT |
4425 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 4426 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 4427 | * TARGET_CHAR_BIT); |
ebafbe83 MS |
4428 | |
4429 | if (mips_debug) | |
4430 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
4431 | argreg, | |
1a69e1e4 | 4432 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 4433 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
ebafbe83 MS |
4434 | argreg++; |
4435 | ||
4436 | /* Prevent subsequent floating point arguments from | |
4437 | being passed in floating point registers. */ | |
74ed0bb4 | 4438 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
ebafbe83 MS |
4439 | } |
4440 | ||
4441 | len -= partial_len; | |
4442 | val += partial_len; | |
4443 | ||
b021a221 MS |
4444 | /* Compute the offset into the stack at which we will |
4445 | copy the next parameter. | |
ebafbe83 | 4446 | |
6d82d43b AC |
4447 | In older ABIs, the caller reserved space for |
4448 | registers that contained arguments. This was loosely | |
4449 | refered to as their "home". Consequently, space is | |
4450 | always allocated. */ | |
ebafbe83 | 4451 | |
1a69e1e4 | 4452 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
ebafbe83 MS |
4453 | } |
4454 | } | |
4455 | if (mips_debug) | |
4456 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
4457 | } | |
4458 | ||
f10683bb | 4459 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4460 | |
ebafbe83 MS |
4461 | /* Return adjusted stack pointer. */ |
4462 | return sp; | |
4463 | } | |
4464 | ||
9c8fdbfa | 4465 | static enum return_value_convention |
c055b101 | 4466 | mips_o64_return_value (struct gdbarch *gdbarch, struct type *func_type, |
9c8fdbfa | 4467 | struct type *type, struct regcache *regcache, |
47a35522 | 4468 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 4469 | { |
72a155b4 | 4470 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7a076fd2 FF |
4471 | |
4472 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4473 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
4474 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
4475 | return RETURN_VALUE_STRUCT_CONVENTION; | |
74ed0bb4 | 4476 | else if (fp_register_arg_p (gdbarch, TYPE_CODE (type), type)) |
7a076fd2 FF |
4477 | { |
4478 | /* A floating-point value. It fits in the least significant | |
4479 | part of FP0. */ | |
4480 | if (mips_debug) | |
4481 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 4482 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4483 | gdbarch_num_regs (gdbarch) |
4484 | + mips_regnum (gdbarch)->fp0, | |
7a076fd2 | 4485 | TYPE_LENGTH (type), |
72a155b4 | 4486 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4487 | readbuf, writebuf, 0); |
7a076fd2 FF |
4488 | return RETURN_VALUE_REGISTER_CONVENTION; |
4489 | } | |
4490 | else | |
4491 | { | |
4492 | /* A scalar extract each part but least-significant-byte | |
025bb325 | 4493 | justified. */ |
7a076fd2 FF |
4494 | int offset; |
4495 | int regnum; | |
4496 | for (offset = 0, regnum = MIPS_V0_REGNUM; | |
4497 | offset < TYPE_LENGTH (type); | |
1a69e1e4 | 4498 | offset += MIPS64_REGSIZE, regnum++) |
7a076fd2 | 4499 | { |
1a69e1e4 | 4500 | int xfer = MIPS64_REGSIZE; |
7a076fd2 FF |
4501 | if (offset + xfer > TYPE_LENGTH (type)) |
4502 | xfer = TYPE_LENGTH (type) - offset; | |
4503 | if (mips_debug) | |
4504 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4505 | offset, xfer, regnum); | |
ba32f989 DJ |
4506 | mips_xfer_register (gdbarch, regcache, |
4507 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 4508 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 4509 | readbuf, writebuf, offset); |
7a076fd2 FF |
4510 | } |
4511 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4512 | } | |
6d82d43b AC |
4513 | } |
4514 | ||
dd824b04 DJ |
4515 | /* Floating point register management. |
4516 | ||
4517 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
4518 | 64bit operations, these early MIPS cpus treat fp register pairs | |
4519 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
4520 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
4521 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
4522 | double precision floats into two 32-bit chunks and store them in | |
4523 | consecutive fp regs. To display 64-bit floats stored in this | |
4524 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
4525 | Throw in user-configurable endianness and you have a real mess. | |
4526 | ||
4527 | The way this works is: | |
4528 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
4529 | double-precision value will be split across two logical registers. | |
4530 | The lower-numbered logical register will hold the low-order bits, | |
4531 | regardless of the processor's endianness. | |
4532 | - If we are on a 64-bit processor, and we are looking for a | |
4533 | single-precision value, it will be in the low ordered bits | |
4534 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
4535 | save slot in memory. | |
4536 | - If we are in 64-bit mode, everything is straightforward. | |
4537 | ||
4538 | Note that this code only deals with "live" registers at the top of the | |
4539 | stack. We will attempt to deal with saved registers later, when | |
025bb325 | 4540 | the raw/cooked register interface is in place. (We need a general |
dd824b04 DJ |
4541 | interface that can deal with dynamic saved register sizes -- fp |
4542 | regs could be 32 bits wide in one frame and 64 on the frame above | |
4543 | and below). */ | |
4544 | ||
4545 | /* Copy a 32-bit single-precision value from the current frame | |
4546 | into rare_buffer. */ | |
4547 | ||
4548 | static void | |
e11c53d2 | 4549 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
47a35522 | 4550 | gdb_byte *rare_buffer) |
dd824b04 | 4551 | { |
72a155b4 UW |
4552 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4553 | int raw_size = register_size (gdbarch, regno); | |
47a35522 | 4554 | gdb_byte *raw_buffer = alloca (raw_size); |
dd824b04 | 4555 | |
e11c53d2 | 4556 | if (!frame_register_read (frame, regno, raw_buffer)) |
c9f4d572 | 4557 | error (_("can't read register %d (%s)"), |
72a155b4 | 4558 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
4559 | if (raw_size == 8) |
4560 | { | |
4561 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 4562 | 32 bits. */ |
dd824b04 DJ |
4563 | int offset; |
4564 | ||
72a155b4 | 4565 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 DJ |
4566 | offset = 4; |
4567 | else | |
4568 | offset = 0; | |
4569 | ||
4570 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
4571 | } | |
4572 | else | |
4573 | { | |
4574 | memcpy (rare_buffer, raw_buffer, 4); | |
4575 | } | |
4576 | } | |
4577 | ||
4578 | /* Copy a 64-bit double-precision value from the current frame into | |
4579 | rare_buffer. This may include getting half of it from the next | |
4580 | register. */ | |
4581 | ||
4582 | static void | |
e11c53d2 | 4583 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
47a35522 | 4584 | gdb_byte *rare_buffer) |
dd824b04 | 4585 | { |
72a155b4 UW |
4586 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4587 | int raw_size = register_size (gdbarch, regno); | |
dd824b04 | 4588 | |
9c9acae0 | 4589 | if (raw_size == 8 && !mips2_fp_compat (frame)) |
dd824b04 DJ |
4590 | { |
4591 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 4592 | all 64 bits. */ |
e11c53d2 | 4593 | if (!frame_register_read (frame, regno, rare_buffer)) |
c9f4d572 | 4594 | error (_("can't read register %d (%s)"), |
72a155b4 | 4595 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
4596 | } |
4597 | else | |
4598 | { | |
72a155b4 | 4599 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
82e91389 | 4600 | |
72a155b4 | 4601 | if ((rawnum - mips_regnum (gdbarch)->fp0) & 1) |
dd824b04 | 4602 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
4603 | _("mips_read_fp_register_double: bad access to " |
4604 | "odd-numbered FP register")); | |
dd824b04 DJ |
4605 | |
4606 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 4607 | each register. */ |
72a155b4 | 4608 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 | 4609 | { |
e11c53d2 AC |
4610 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
4611 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 4612 | } |
361d1df0 | 4613 | else |
dd824b04 | 4614 | { |
e11c53d2 AC |
4615 | mips_read_fp_register_single (frame, regno, rare_buffer); |
4616 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
4617 | } |
4618 | } | |
4619 | } | |
4620 | ||
c906108c | 4621 | static void |
e11c53d2 AC |
4622 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
4623 | int regnum) | |
025bb325 | 4624 | { /* Do values for FP (float) regs. */ |
72a155b4 | 4625 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 4626 | gdb_byte *raw_buffer; |
025bb325 | 4627 | double doub, flt1; /* Doubles extracted from raw hex data. */ |
3903d437 | 4628 | int inv1, inv2; |
c5aa993b | 4629 | |
025bb325 MS |
4630 | raw_buffer = alloca (2 * register_size (gdbarch, |
4631 | mips_regnum (gdbarch)->fp0)); | |
c906108c | 4632 | |
72a155b4 | 4633 | fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum)); |
c9f4d572 | 4634 | fprintf_filtered (file, "%*s", |
72a155b4 | 4635 | 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)), |
e11c53d2 | 4636 | ""); |
f0ef6b29 | 4637 | |
72a155b4 | 4638 | if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame)) |
c906108c | 4639 | { |
79a45b7d TT |
4640 | struct value_print_options opts; |
4641 | ||
f0ef6b29 KB |
4642 | /* 4-byte registers: Print hex and floating. Also print even |
4643 | numbered registers as doubles. */ | |
e11c53d2 | 4644 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
025bb325 MS |
4645 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, |
4646 | raw_buffer, &inv1); | |
c5aa993b | 4647 | |
79a45b7d | 4648 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
4649 | print_scalar_formatted (raw_buffer, |
4650 | builtin_type (gdbarch)->builtin_uint32, | |
4651 | &opts, 'w', file); | |
dd824b04 | 4652 | |
e11c53d2 | 4653 | fprintf_filtered (file, " flt: "); |
1adad886 | 4654 | if (inv1) |
e11c53d2 | 4655 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4656 | else |
e11c53d2 | 4657 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4658 | |
72a155b4 | 4659 | if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0) |
f0ef6b29 | 4660 | { |
e11c53d2 | 4661 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
27067745 UW |
4662 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
4663 | raw_buffer, &inv2); | |
1adad886 | 4664 | |
e11c53d2 | 4665 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4666 | if (inv2) |
e11c53d2 | 4667 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 4668 | else |
e11c53d2 | 4669 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 4670 | } |
c906108c SS |
4671 | } |
4672 | else | |
dd824b04 | 4673 | { |
79a45b7d TT |
4674 | struct value_print_options opts; |
4675 | ||
f0ef6b29 | 4676 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 4677 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
27067745 UW |
4678 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, |
4679 | raw_buffer, &inv1); | |
c906108c | 4680 | |
e11c53d2 | 4681 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
27067745 UW |
4682 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
4683 | raw_buffer, &inv2); | |
f0ef6b29 | 4684 | |
79a45b7d | 4685 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
4686 | print_scalar_formatted (raw_buffer, |
4687 | builtin_type (gdbarch)->builtin_uint64, | |
4688 | &opts, 'g', file); | |
f0ef6b29 | 4689 | |
e11c53d2 | 4690 | fprintf_filtered (file, " flt: "); |
1adad886 | 4691 | if (inv1) |
e11c53d2 | 4692 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 4693 | else |
e11c53d2 | 4694 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4695 | |
e11c53d2 | 4696 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4697 | if (inv2) |
e11c53d2 | 4698 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 4699 | else |
e11c53d2 | 4700 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
4701 | } |
4702 | } | |
4703 | ||
4704 | static void | |
e11c53d2 | 4705 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
0cc93a06 | 4706 | int regnum) |
f0ef6b29 | 4707 | { |
a4b8ebc8 | 4708 | struct gdbarch *gdbarch = get_frame_arch (frame); |
f0ef6b29 | 4709 | int offset; |
79a45b7d | 4710 | struct value_print_options opts; |
de15c4ab | 4711 | struct value *val; |
1adad886 | 4712 | |
7b9ee6a8 | 4713 | if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 4714 | { |
e11c53d2 | 4715 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4716 | return; |
4717 | } | |
4718 | ||
de15c4ab PA |
4719 | val = get_frame_register_value (frame, regnum); |
4720 | if (value_optimized_out (val)) | |
f0ef6b29 | 4721 | { |
c9f4d572 | 4722 | fprintf_filtered (file, "%s: [Invalid]", |
72a155b4 | 4723 | gdbarch_register_name (gdbarch, regnum)); |
f0ef6b29 | 4724 | return; |
c906108c | 4725 | } |
f0ef6b29 | 4726 | |
72a155b4 | 4727 | fputs_filtered (gdbarch_register_name (gdbarch, regnum), file); |
f0ef6b29 KB |
4728 | |
4729 | /* The problem with printing numeric register names (r26, etc.) is that | |
4730 | the user can't use them on input. Probably the best solution is to | |
4731 | fix it so that either the numeric or the funky (a2, etc.) names | |
4732 | are accepted on input. */ | |
4733 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 4734 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 4735 | else |
e11c53d2 | 4736 | fprintf_filtered (file, ": "); |
f0ef6b29 | 4737 | |
79a45b7d | 4738 | get_formatted_print_options (&opts, 'x'); |
de15c4ab PA |
4739 | val_print_scalar_formatted (value_type (val), |
4740 | value_contents_for_printing (val), | |
4741 | value_embedded_offset (val), | |
4742 | val, | |
4743 | &opts, 0, file); | |
c906108c SS |
4744 | } |
4745 | ||
f0ef6b29 KB |
4746 | /* Replacement for generic do_registers_info. |
4747 | Print regs in pretty columns. */ | |
4748 | ||
4749 | static int | |
e11c53d2 AC |
4750 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
4751 | int regnum) | |
f0ef6b29 | 4752 | { |
e11c53d2 AC |
4753 | fprintf_filtered (file, " "); |
4754 | mips_print_fp_register (file, frame, regnum); | |
4755 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
4756 | return regnum + 1; |
4757 | } | |
4758 | ||
4759 | ||
025bb325 | 4760 | /* Print a row's worth of GP (int) registers, with name labels above. */ |
c906108c SS |
4761 | |
4762 | static int | |
e11c53d2 | 4763 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 4764 | int start_regnum) |
c906108c | 4765 | { |
a4b8ebc8 | 4766 | struct gdbarch *gdbarch = get_frame_arch (frame); |
025bb325 | 4767 | /* Do values for GP (int) regs. */ |
47a35522 | 4768 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
025bb325 MS |
4769 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols |
4770 | per row. */ | |
c906108c | 4771 | int col, byte; |
a4b8ebc8 | 4772 | int regnum; |
c906108c | 4773 | |
025bb325 | 4774 | /* For GP registers, we print a separate row of names above the vals. */ |
a4b8ebc8 | 4775 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
4776 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
4777 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 4778 | regnum++) |
c906108c | 4779 | { |
72a155b4 | 4780 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 4781 | continue; /* unused register */ |
7b9ee6a8 | 4782 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4783 | TYPE_CODE_FLT) |
025bb325 | 4784 | break; /* End the row: reached FP register. */ |
0cc93a06 | 4785 | /* Large registers are handled separately. */ |
72a155b4 | 4786 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
4787 | { |
4788 | if (col > 0) | |
4789 | break; /* End the row before this register. */ | |
4790 | ||
4791 | /* Print this register on a row by itself. */ | |
4792 | mips_print_register (file, frame, regnum); | |
4793 | fprintf_filtered (file, "\n"); | |
4794 | return regnum + 1; | |
4795 | } | |
d05f6826 DJ |
4796 | if (col == 0) |
4797 | fprintf_filtered (file, " "); | |
6d82d43b | 4798 | fprintf_filtered (file, |
72a155b4 UW |
4799 | mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s", |
4800 | gdbarch_register_name (gdbarch, regnum)); | |
c906108c SS |
4801 | col++; |
4802 | } | |
d05f6826 DJ |
4803 | |
4804 | if (col == 0) | |
4805 | return regnum; | |
4806 | ||
025bb325 | 4807 | /* Print the R0 to R31 names. */ |
72a155b4 | 4808 | if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS) |
f57d151a | 4809 | fprintf_filtered (file, "\n R%-4d", |
72a155b4 | 4810 | start_regnum % gdbarch_num_regs (gdbarch)); |
20e6603c AC |
4811 | else |
4812 | fprintf_filtered (file, "\n "); | |
c906108c | 4813 | |
025bb325 | 4814 | /* Now print the values in hex, 4 or 8 to the row. */ |
a4b8ebc8 | 4815 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
4816 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
4817 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 4818 | regnum++) |
c906108c | 4819 | { |
72a155b4 | 4820 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 4821 | continue; /* unused register */ |
7b9ee6a8 | 4822 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4823 | TYPE_CODE_FLT) |
025bb325 | 4824 | break; /* End row: reached FP register. */ |
72a155b4 | 4825 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
4826 | break; /* End row: large register. */ |
4827 | ||
c906108c | 4828 | /* OK: get the data in raw format. */ |
e11c53d2 | 4829 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c9f4d572 | 4830 | error (_("can't read register %d (%s)"), |
72a155b4 | 4831 | regnum, gdbarch_register_name (gdbarch, regnum)); |
c906108c | 4832 | /* pad small registers */ |
4246e332 | 4833 | for (byte = 0; |
72a155b4 UW |
4834 | byte < (mips_abi_regsize (gdbarch) |
4835 | - register_size (gdbarch, regnum)); byte++) | |
c906108c | 4836 | printf_filtered (" "); |
025bb325 | 4837 | /* Now print the register value in hex, endian order. */ |
72a155b4 | 4838 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b | 4839 | for (byte = |
72a155b4 UW |
4840 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
4841 | byte < register_size (gdbarch, regnum); byte++) | |
47a35522 | 4842 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
c906108c | 4843 | else |
72a155b4 | 4844 | for (byte = register_size (gdbarch, regnum) - 1; |
6d82d43b | 4845 | byte >= 0; byte--) |
47a35522 | 4846 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
e11c53d2 | 4847 | fprintf_filtered (file, " "); |
c906108c SS |
4848 | col++; |
4849 | } | |
025bb325 | 4850 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 4851 | fprintf_filtered (file, "\n"); |
c906108c SS |
4852 | |
4853 | return regnum; | |
4854 | } | |
4855 | ||
025bb325 | 4856 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */ |
c906108c | 4857 | |
bf1f5b4c | 4858 | static void |
e11c53d2 AC |
4859 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4860 | struct frame_info *frame, int regnum, int all) | |
c906108c | 4861 | { |
025bb325 | 4862 | if (regnum != -1) /* Do one specified register. */ |
c906108c | 4863 | { |
72a155b4 UW |
4864 | gdb_assert (regnum >= gdbarch_num_regs (gdbarch)); |
4865 | if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
8a3fe4f8 | 4866 | error (_("Not a valid register for the current processor type")); |
c906108c | 4867 | |
0cc93a06 | 4868 | mips_print_register (file, frame, regnum); |
e11c53d2 | 4869 | fprintf_filtered (file, "\n"); |
c906108c | 4870 | } |
c5aa993b | 4871 | else |
025bb325 | 4872 | /* Do all (or most) registers. */ |
c906108c | 4873 | { |
72a155b4 UW |
4874 | regnum = gdbarch_num_regs (gdbarch); |
4875 | while (regnum < gdbarch_num_regs (gdbarch) | |
4876 | + gdbarch_num_pseudo_regs (gdbarch)) | |
c906108c | 4877 | { |
7b9ee6a8 | 4878 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4879 | TYPE_CODE_FLT) |
e11c53d2 | 4880 | { |
025bb325 | 4881 | if (all) /* True for "INFO ALL-REGISTERS" command. */ |
e11c53d2 AC |
4882 | regnum = print_fp_register_row (file, frame, regnum); |
4883 | else | |
025bb325 | 4884 | regnum += MIPS_NUMREGS; /* Skip floating point regs. */ |
e11c53d2 | 4885 | } |
c906108c | 4886 | else |
e11c53d2 | 4887 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
4888 | } |
4889 | } | |
4890 | } | |
4891 | ||
c906108c SS |
4892 | /* Is this a branch with a delay slot? */ |
4893 | ||
c906108c | 4894 | static int |
acdb74a0 | 4895 | is_delayed (unsigned long insn) |
c906108c SS |
4896 | { |
4897 | int i; | |
4898 | for (i = 0; i < NUMOPCODES; ++i) | |
4899 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4900 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4901 | break; | |
4902 | return (i < NUMOPCODES | |
4903 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4904 | | INSN_COND_BRANCH_DELAY | |
4905 | | INSN_COND_BRANCH_LIKELY))); | |
4906 | } | |
4907 | ||
63807e1d | 4908 | static int |
3352ef37 AC |
4909 | mips_single_step_through_delay (struct gdbarch *gdbarch, |
4910 | struct frame_info *frame) | |
c906108c | 4911 | { |
e17a4113 | 4912 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
3352ef37 | 4913 | CORE_ADDR pc = get_frame_pc (frame); |
47a35522 | 4914 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
4915 | |
4916 | /* There is no branch delay slot on MIPS16. */ | |
0fe7e7c8 | 4917 | if (mips_pc_is_mips16 (pc)) |
c906108c SS |
4918 | return 0; |
4919 | ||
6c95b8df | 4920 | if (!breakpoint_here_p (get_frame_address_space (frame), pc + 4)) |
06648491 MK |
4921 | return 0; |
4922 | ||
3352ef37 AC |
4923 | if (!safe_frame_unwind_memory (frame, pc, buf, sizeof buf)) |
4924 | /* If error reading memory, guess that it is not a delayed | |
4925 | branch. */ | |
c906108c | 4926 | return 0; |
e17a4113 | 4927 | return is_delayed (extract_unsigned_integer (buf, sizeof buf, byte_order)); |
c906108c SS |
4928 | } |
4929 | ||
6d82d43b AC |
4930 | /* To skip prologues, I use this predicate. Returns either PC itself |
4931 | if the code at PC does not look like a function prologue; otherwise | |
4932 | returns an address that (if we're lucky) follows the prologue. If | |
4933 | LENIENT, then we must skip everything which is involved in setting | |
4934 | up the frame (it's OK to skip more, just so long as we don't skip | |
4935 | anything which might clobber the registers which are being saved. | |
4936 | We must skip more in the case where part of the prologue is in the | |
4937 | delay slot of a non-prologue instruction). */ | |
4938 | ||
4939 | static CORE_ADDR | |
6093d2eb | 4940 | mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
6d82d43b | 4941 | { |
8b622e6a AC |
4942 | CORE_ADDR limit_pc; |
4943 | CORE_ADDR func_addr; | |
4944 | ||
6d82d43b AC |
4945 | /* See if we can determine the end of the prologue via the symbol table. |
4946 | If so, then return either PC, or the PC after the prologue, whichever | |
4947 | is greater. */ | |
8b622e6a AC |
4948 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
4949 | { | |
d80b854b UW |
4950 | CORE_ADDR post_prologue_pc |
4951 | = skip_prologue_using_sal (gdbarch, func_addr); | |
8b622e6a AC |
4952 | if (post_prologue_pc != 0) |
4953 | return max (pc, post_prologue_pc); | |
4954 | } | |
6d82d43b AC |
4955 | |
4956 | /* Can't determine prologue from the symbol table, need to examine | |
4957 | instructions. */ | |
4958 | ||
98b4dd94 JB |
4959 | /* Find an upper limit on the function prologue using the debug |
4960 | information. If the debug information could not be used to provide | |
4961 | that bound, then use an arbitrary large number as the upper bound. */ | |
d80b854b | 4962 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
98b4dd94 JB |
4963 | if (limit_pc == 0) |
4964 | limit_pc = pc + 100; /* Magic. */ | |
4965 | ||
0fe7e7c8 | 4966 | if (mips_pc_is_mips16 (pc)) |
e17a4113 | 4967 | return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
6d82d43b | 4968 | else |
e17a4113 | 4969 | return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
88658117 AC |
4970 | } |
4971 | ||
97ab0fdd MR |
4972 | /* Check whether the PC is in a function epilogue (32-bit version). |
4973 | This is a helper function for mips_in_function_epilogue_p. */ | |
4974 | static int | |
e17a4113 | 4975 | mips32_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
4976 | { |
4977 | CORE_ADDR func_addr = 0, func_end = 0; | |
4978 | ||
4979 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
4980 | { | |
4981 | /* The MIPS epilogue is max. 12 bytes long. */ | |
4982 | CORE_ADDR addr = func_end - 12; | |
4983 | ||
4984 | if (addr < func_addr + 4) | |
4985 | addr = func_addr + 4; | |
4986 | if (pc < addr) | |
4987 | return 0; | |
4988 | ||
4989 | for (; pc < func_end; pc += MIPS_INSN32_SIZE) | |
4990 | { | |
4991 | unsigned long high_word; | |
4992 | unsigned long inst; | |
4993 | ||
e17a4113 | 4994 | inst = mips_fetch_instruction (gdbarch, pc); |
97ab0fdd MR |
4995 | high_word = (inst >> 16) & 0xffff; |
4996 | ||
4997 | if (high_word != 0x27bd /* addiu $sp,$sp,offset */ | |
4998 | && high_word != 0x67bd /* daddiu $sp,$sp,offset */ | |
4999 | && inst != 0x03e00008 /* jr $ra */ | |
5000 | && inst != 0x00000000) /* nop */ | |
5001 | return 0; | |
5002 | } | |
5003 | ||
5004 | return 1; | |
5005 | } | |
5006 | ||
5007 | return 0; | |
5008 | } | |
5009 | ||
5010 | /* Check whether the PC is in a function epilogue (16-bit version). | |
5011 | This is a helper function for mips_in_function_epilogue_p. */ | |
5012 | static int | |
e17a4113 | 5013 | mips16_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
5014 | { |
5015 | CORE_ADDR func_addr = 0, func_end = 0; | |
5016 | ||
5017 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
5018 | { | |
5019 | /* The MIPS epilogue is max. 12 bytes long. */ | |
5020 | CORE_ADDR addr = func_end - 12; | |
5021 | ||
5022 | if (addr < func_addr + 4) | |
5023 | addr = func_addr + 4; | |
5024 | if (pc < addr) | |
5025 | return 0; | |
5026 | ||
5027 | for (; pc < func_end; pc += MIPS_INSN16_SIZE) | |
5028 | { | |
5029 | unsigned short inst; | |
5030 | ||
e17a4113 | 5031 | inst = mips_fetch_instruction (gdbarch, pc); |
97ab0fdd MR |
5032 | |
5033 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
5034 | continue; | |
5035 | ||
5036 | if (inst != 0x6300 /* addiu $sp,offset */ | |
5037 | && inst != 0xfb00 /* daddiu $sp,$sp,offset */ | |
5038 | && inst != 0xe820 /* jr $ra */ | |
5039 | && inst != 0xe8a0 /* jrc $ra */ | |
5040 | && inst != 0x6500) /* nop */ | |
5041 | return 0; | |
5042 | } | |
5043 | ||
5044 | return 1; | |
5045 | } | |
5046 | ||
5047 | return 0; | |
5048 | } | |
5049 | ||
5050 | /* The epilogue is defined here as the area at the end of a function, | |
5051 | after an instruction which destroys the function's stack frame. */ | |
5052 | static int | |
5053 | mips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
5054 | { | |
5055 | if (mips_pc_is_mips16 (pc)) | |
e17a4113 | 5056 | return mips16_in_function_epilogue_p (gdbarch, pc); |
97ab0fdd | 5057 | else |
e17a4113 | 5058 | return mips32_in_function_epilogue_p (gdbarch, pc); |
97ab0fdd MR |
5059 | } |
5060 | ||
025bb325 | 5061 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
a5ea2558 AC |
5062 | used for all MIPS-specific commands. */ |
5063 | ||
a5ea2558 | 5064 | static void |
acdb74a0 | 5065 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
5066 | { |
5067 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
5068 | } | |
5069 | ||
a5ea2558 | 5070 | static void |
acdb74a0 | 5071 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 5072 | { |
6d82d43b AC |
5073 | printf_unfiltered |
5074 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
5075 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
5076 | } | |
5077 | ||
c906108c SS |
5078 | /* Commands to show/set the MIPS FPU type. */ |
5079 | ||
c906108c | 5080 | static void |
acdb74a0 | 5081 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 5082 | { |
c906108c | 5083 | char *fpu; |
6ca0852e | 5084 | |
1cf3db46 | 5085 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips) |
6ca0852e UW |
5086 | { |
5087 | printf_unfiltered | |
5088 | ("The MIPS floating-point coprocessor is unknown " | |
5089 | "because the current architecture is not MIPS.\n"); | |
5090 | return; | |
5091 | } | |
5092 | ||
1cf3db46 | 5093 | switch (MIPS_FPU_TYPE (target_gdbarch)) |
c906108c SS |
5094 | { |
5095 | case MIPS_FPU_SINGLE: | |
5096 | fpu = "single-precision"; | |
5097 | break; | |
5098 | case MIPS_FPU_DOUBLE: | |
5099 | fpu = "double-precision"; | |
5100 | break; | |
5101 | case MIPS_FPU_NONE: | |
5102 | fpu = "absent (none)"; | |
5103 | break; | |
93d56215 | 5104 | default: |
e2e0b3e5 | 5105 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c SS |
5106 | } |
5107 | if (mips_fpu_type_auto) | |
025bb325 MS |
5108 | printf_unfiltered ("The MIPS floating-point coprocessor " |
5109 | "is set automatically (currently %s)\n", | |
5110 | fpu); | |
c906108c | 5111 | else |
6d82d43b AC |
5112 | printf_unfiltered |
5113 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
5114 | } |
5115 | ||
5116 | ||
c906108c | 5117 | static void |
acdb74a0 | 5118 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 5119 | { |
025bb325 MS |
5120 | printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", " |
5121 | "\"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
5122 | show_mipsfpu_command (args, from_tty); |
5123 | } | |
5124 | ||
c906108c | 5125 | static void |
acdb74a0 | 5126 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 5127 | { |
8d5838b5 AC |
5128 | struct gdbarch_info info; |
5129 | gdbarch_info_init (&info); | |
c906108c SS |
5130 | mips_fpu_type = MIPS_FPU_SINGLE; |
5131 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5132 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5133 | instead of relying on globals. Doing that would let generic code | |
5134 | handle the search for this specific architecture. */ | |
5135 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 5136 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
5137 | } |
5138 | ||
c906108c | 5139 | static void |
acdb74a0 | 5140 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 5141 | { |
8d5838b5 AC |
5142 | struct gdbarch_info info; |
5143 | gdbarch_info_init (&info); | |
c906108c SS |
5144 | mips_fpu_type = MIPS_FPU_DOUBLE; |
5145 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5146 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5147 | instead of relying on globals. Doing that would let generic code | |
5148 | handle the search for this specific architecture. */ | |
5149 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 5150 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
5151 | } |
5152 | ||
c906108c | 5153 | static void |
acdb74a0 | 5154 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 5155 | { |
8d5838b5 AC |
5156 | struct gdbarch_info info; |
5157 | gdbarch_info_init (&info); | |
c906108c SS |
5158 | mips_fpu_type = MIPS_FPU_NONE; |
5159 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5160 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5161 | instead of relying on globals. Doing that would let generic code | |
5162 | handle the search for this specific architecture. */ | |
5163 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 5164 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
5165 | } |
5166 | ||
c906108c | 5167 | static void |
acdb74a0 | 5168 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
5169 | { |
5170 | mips_fpu_type_auto = 1; | |
5171 | } | |
5172 | ||
c906108c | 5173 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
5174 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
5175 | the relevant processor still exists (it dates back to '94) and | |
5176 | secondly this is not the way to do this. The processor type should | |
5177 | be set by forcing an architecture change. */ | |
c906108c | 5178 | |
691c0433 AC |
5179 | void |
5180 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 5181 | { |
bb486190 UW |
5182 | struct regcache *regcache = get_current_regcache (); |
5183 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
5184 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
a9614958 | 5185 | ULONGEST prid; |
c906108c | 5186 | |
bb486190 | 5187 | regcache_cooked_read_unsigned (regcache, MIPS_PRID_REGNUM, &prid); |
c906108c | 5188 | if ((prid & ~0xf) == 0x700) |
691c0433 | 5189 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
5190 | } |
5191 | ||
5192 | /* Just like reinit_frame_cache, but with the right arguments to be | |
5193 | callable as an sfunc. */ | |
5194 | ||
5195 | static void | |
acdb74a0 AC |
5196 | reinit_frame_cache_sfunc (char *args, int from_tty, |
5197 | struct cmd_list_element *c) | |
c906108c SS |
5198 | { |
5199 | reinit_frame_cache (); | |
5200 | } | |
5201 | ||
a89aa300 AC |
5202 | static int |
5203 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 5204 | { |
d31431ed AC |
5205 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
5206 | disassembler needs to be able to locally determine the ISA, and | |
5207 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
5208 | work. */ | |
ec4045ea AC |
5209 | if (mips_pc_is_mips16 (memaddr)) |
5210 | info->mach = bfd_mach_mips16; | |
c906108c SS |
5211 | |
5212 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 5213 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 5214 | |
e5ab0dce | 5215 | /* Set the disassembler options. */ |
9dae60cc | 5216 | if (!info->disassembler_options) |
e5ab0dce AC |
5217 | /* This string is not recognized explicitly by the disassembler, |
5218 | but it tells the disassembler to not try to guess the ABI from | |
5219 | the bfd elf headers, such that, if the user overrides the ABI | |
5220 | of a program linked as NewABI, the disassembly will follow the | |
5221 | register naming conventions specified by the user. */ | |
5222 | info->disassembler_options = "gpr-names=32"; | |
5223 | ||
c906108c | 5224 | /* Call the appropriate disassembler based on the target endian-ness. */ |
40887e1a | 5225 | if (info->endian == BFD_ENDIAN_BIG) |
c906108c SS |
5226 | return print_insn_big_mips (memaddr, info); |
5227 | else | |
5228 | return print_insn_little_mips (memaddr, info); | |
5229 | } | |
5230 | ||
9dae60cc UW |
5231 | static int |
5232 | gdb_print_insn_mips_n32 (bfd_vma memaddr, struct disassemble_info *info) | |
5233 | { | |
5234 | /* Set up the disassembler info, so that we get the right | |
5235 | register names from libopcodes. */ | |
5236 | info->disassembler_options = "gpr-names=n32"; | |
5237 | info->flavour = bfd_target_elf_flavour; | |
5238 | ||
5239 | return gdb_print_insn_mips (memaddr, info); | |
5240 | } | |
5241 | ||
5242 | static int | |
5243 | gdb_print_insn_mips_n64 (bfd_vma memaddr, struct disassemble_info *info) | |
5244 | { | |
5245 | /* Set up the disassembler info, so that we get the right | |
5246 | register names from libopcodes. */ | |
5247 | info->disassembler_options = "gpr-names=64"; | |
5248 | info->flavour = bfd_target_elf_flavour; | |
5249 | ||
5250 | return gdb_print_insn_mips (memaddr, info); | |
5251 | } | |
5252 | ||
025bb325 MS |
5253 | /* This function implements gdbarch_breakpoint_from_pc. It uses the |
5254 | program counter value to determine whether a 16- or 32-bit breakpoint | |
5255 | should be used. It returns a pointer to a string of bytes that encode a | |
5256 | breakpoint instruction, stores the length of the string to *lenptr, and | |
5257 | adjusts pc (if necessary) to point to the actual memory location where | |
5258 | the breakpoint should be inserted. */ | |
c906108c | 5259 | |
47a35522 | 5260 | static const gdb_byte * |
025bb325 MS |
5261 | mips_breakpoint_from_pc (struct gdbarch *gdbarch, |
5262 | CORE_ADDR *pcptr, int *lenptr) | |
c906108c | 5263 | { |
67d57894 | 5264 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
c906108c | 5265 | { |
0fe7e7c8 | 5266 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 5267 | { |
47a35522 | 5268 | static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
95404a3e | 5269 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5270 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
5271 | return mips16_big_breakpoint; |
5272 | } | |
5273 | else | |
5274 | { | |
aaab4dba AC |
5275 | /* The IDT board uses an unusual breakpoint value, and |
5276 | sometimes gets confused when it sees the usual MIPS | |
5277 | breakpoint instruction. */ | |
47a35522 MK |
5278 | static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
5279 | static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
5280 | static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
f2ec0ecf | 5281 | /* Likewise, IRIX appears to expect a different breakpoint, |
025bb325 | 5282 | although this is not apparent until you try to use pthreads. */ |
f2ec0ecf | 5283 | static gdb_byte irix_big_breakpoint[] = { 0, 0, 0, 0xd }; |
c906108c | 5284 | |
c5aa993b | 5285 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
5286 | |
5287 | if (strcmp (target_shortname, "mips") == 0) | |
5288 | return idt_big_breakpoint; | |
5289 | else if (strcmp (target_shortname, "ddb") == 0 | |
5290 | || strcmp (target_shortname, "pmon") == 0 | |
5291 | || strcmp (target_shortname, "lsi") == 0) | |
5292 | return pmon_big_breakpoint; | |
f2ec0ecf JB |
5293 | else if (gdbarch_osabi (gdbarch) == GDB_OSABI_IRIX) |
5294 | return irix_big_breakpoint; | |
c906108c SS |
5295 | else |
5296 | return big_breakpoint; | |
5297 | } | |
5298 | } | |
5299 | else | |
5300 | { | |
0fe7e7c8 | 5301 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 5302 | { |
47a35522 | 5303 | static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
95404a3e | 5304 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5305 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
5306 | return mips16_little_breakpoint; |
5307 | } | |
5308 | else | |
5309 | { | |
47a35522 MK |
5310 | static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
5311 | static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
5312 | static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 5313 | |
c5aa993b | 5314 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
5315 | |
5316 | if (strcmp (target_shortname, "mips") == 0) | |
5317 | return idt_little_breakpoint; | |
5318 | else if (strcmp (target_shortname, "ddb") == 0 | |
5319 | || strcmp (target_shortname, "pmon") == 0 | |
5320 | || strcmp (target_shortname, "lsi") == 0) | |
5321 | return pmon_little_breakpoint; | |
5322 | else | |
5323 | return little_breakpoint; | |
5324 | } | |
5325 | } | |
5326 | } | |
5327 | ||
5328 | /* If PC is in a mips16 call or return stub, return the address of the target | |
5329 | PC, which is either the callee or the caller. There are several | |
5330 | cases which must be handled: | |
5331 | ||
5332 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 5333 | target PC is in $31 ($ra). |
c906108c | 5334 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 5335 | and the target PC is in $2. |
c906108c | 5336 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b | 5337 | before the jal instruction, this is effectively a call stub |
b021a221 | 5338 | and the target PC is in $2. Otherwise this is effectively |
c5aa993b | 5339 | a return stub and the target PC is in $18. |
c906108c SS |
5340 | |
5341 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
e7d6a6d2 | 5342 | gory details. */ |
c906108c | 5343 | |
757a7cc6 | 5344 | static CORE_ADDR |
db5f024e | 5345 | mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 5346 | { |
e17a4113 | 5347 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c SS |
5348 | char *name; |
5349 | CORE_ADDR start_addr; | |
5350 | ||
5351 | /* Find the starting address and name of the function containing the PC. */ | |
5352 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
5353 | return 0; | |
5354 | ||
5355 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
5356 | target PC is in $31 ($ra). */ | |
5357 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5358 | || strcmp (name, "__mips16_ret_df") == 0) | |
52f729a7 | 5359 | return get_frame_register_signed (frame, MIPS_RA_REGNUM); |
c906108c SS |
5360 | |
5361 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5362 | { | |
5363 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
5364 | and the target PC is in $2. */ | |
5365 | if (name[19] >= '0' && name[19] <= '9') | |
52f729a7 | 5366 | return get_frame_register_signed (frame, 2); |
c906108c SS |
5367 | |
5368 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b | 5369 | before the jal instruction, this is effectively a call stub |
b021a221 | 5370 | and the target PC is in $2. Otherwise this is effectively |
c5aa993b | 5371 | a return stub and the target PC is in $18. */ |
c906108c SS |
5372 | else if (name[19] == 's' || name[19] == 'd') |
5373 | { | |
5374 | if (pc == start_addr) | |
5375 | { | |
5376 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
5377 | stub. Such a stub for a function bar might have a name |
5378 | like __fn_stub_bar, and might look like this: | |
5379 | mfc1 $4,$f13 | |
5380 | mfc1 $5,$f12 | |
5381 | mfc1 $6,$f15 | |
5382 | mfc1 $7,$f14 | |
5383 | la $1,bar (becomes a lui/addiu pair) | |
5384 | jr $1 | |
5385 | So scan down to the lui/addi and extract the target | |
5386 | address from those two instructions. */ | |
c906108c | 5387 | |
52f729a7 | 5388 | CORE_ADDR target_pc = get_frame_register_signed (frame, 2); |
d37cca3d | 5389 | ULONGEST inst; |
c906108c SS |
5390 | int i; |
5391 | ||
5392 | /* See if the name of the target function is __fn_stub_*. */ | |
6d82d43b AC |
5393 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == |
5394 | 0) | |
c906108c SS |
5395 | return target_pc; |
5396 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
5397 | && strcmp (name, "etext") != 0 | |
5398 | && strcmp (name, "_etext") != 0) | |
5399 | return target_pc; | |
5400 | ||
5401 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
5402 | The limit on the search is arbitrarily set to 20 |
5403 | instructions. FIXME. */ | |
95ac2dcf | 5404 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSN32_SIZE) |
c906108c | 5405 | { |
e17a4113 | 5406 | inst = mips_fetch_instruction (gdbarch, target_pc); |
c5aa993b | 5407 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ |
025bb325 | 5408 | pc = (inst << 16) & 0xffff0000; /* high word */ |
c5aa993b | 5409 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ |
025bb325 | 5410 | return pc | (inst & 0xffff); /* low word */ |
c906108c SS |
5411 | } |
5412 | ||
5413 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
5414 | return target_pc; | |
5415 | } | |
5416 | else | |
5417 | /* This is the 'return' part of a call stub. The return | |
5418 | address is in $r18. */ | |
52f729a7 | 5419 | return get_frame_register_signed (frame, 18); |
c906108c SS |
5420 | } |
5421 | } | |
c5aa993b | 5422 | return 0; /* not a stub */ |
c906108c SS |
5423 | } |
5424 | ||
db5f024e DJ |
5425 | /* If the current PC is the start of a non-PIC-to-PIC stub, return the |
5426 | PC of the stub target. The stub just loads $t9 and jumps to it, | |
5427 | so that $t9 has the correct value at function entry. */ | |
5428 | ||
5429 | static CORE_ADDR | |
5430 | mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
5431 | { | |
e17a4113 UW |
5432 | struct gdbarch *gdbarch = get_frame_arch (frame); |
5433 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
db5f024e DJ |
5434 | struct minimal_symbol *msym; |
5435 | int i; | |
5436 | gdb_byte stub_code[16]; | |
5437 | int32_t stub_words[4]; | |
5438 | ||
5439 | /* The stub for foo is named ".pic.foo", and is either two | |
5440 | instructions inserted before foo or a three instruction sequence | |
5441 | which jumps to foo. */ | |
5442 | msym = lookup_minimal_symbol_by_pc (pc); | |
5443 | if (msym == NULL | |
5444 | || SYMBOL_VALUE_ADDRESS (msym) != pc | |
5445 | || SYMBOL_LINKAGE_NAME (msym) == NULL | |
5446 | || strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) != 0) | |
5447 | return 0; | |
5448 | ||
5449 | /* A two-instruction header. */ | |
5450 | if (MSYMBOL_SIZE (msym) == 8) | |
5451 | return pc + 8; | |
5452 | ||
5453 | /* A three-instruction (plus delay slot) trampoline. */ | |
5454 | if (MSYMBOL_SIZE (msym) == 16) | |
5455 | { | |
5456 | if (target_read_memory (pc, stub_code, 16) != 0) | |
5457 | return 0; | |
5458 | for (i = 0; i < 4; i++) | |
e17a4113 UW |
5459 | stub_words[i] = extract_unsigned_integer (stub_code + i * 4, |
5460 | 4, byte_order); | |
db5f024e DJ |
5461 | |
5462 | /* A stub contains these instructions: | |
5463 | lui t9, %hi(target) | |
5464 | j target | |
5465 | addiu t9, t9, %lo(target) | |
5466 | nop | |
5467 | ||
5468 | This works even for N64, since stubs are only generated with | |
5469 | -msym32. */ | |
5470 | if ((stub_words[0] & 0xffff0000U) == 0x3c190000 | |
5471 | && (stub_words[1] & 0xfc000000U) == 0x08000000 | |
5472 | && (stub_words[2] & 0xffff0000U) == 0x27390000 | |
5473 | && stub_words[3] == 0x00000000) | |
5474 | return (((stub_words[0] & 0x0000ffff) << 16) | |
5475 | + (stub_words[2] & 0x0000ffff)); | |
5476 | } | |
5477 | ||
5478 | /* Not a recognized stub. */ | |
5479 | return 0; | |
5480 | } | |
5481 | ||
5482 | static CORE_ADDR | |
5483 | mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
5484 | { | |
5485 | CORE_ADDR target_pc; | |
5486 | ||
5487 | target_pc = mips_skip_mips16_trampoline_code (frame, pc); | |
5488 | if (target_pc) | |
5489 | return target_pc; | |
5490 | ||
5491 | target_pc = find_solib_trampoline_target (frame, pc); | |
5492 | if (target_pc) | |
5493 | return target_pc; | |
5494 | ||
5495 | target_pc = mips_skip_pic_trampoline_code (frame, pc); | |
5496 | if (target_pc) | |
5497 | return target_pc; | |
5498 | ||
5499 | return 0; | |
5500 | } | |
5501 | ||
a4b8ebc8 | 5502 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
f57d151a | 5503 | [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
5504 | |
5505 | static int | |
d3f73121 | 5506 | mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 5507 | { |
a4b8ebc8 | 5508 | int regnum; |
2f38ef89 | 5509 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5510 | regnum = num; |
2f38ef89 | 5511 | else if (num >= 38 && num < 70) |
d3f73121 | 5512 | regnum = num + mips_regnum (gdbarch)->fp0 - 38; |
040b99fd | 5513 | else if (num == 70) |
d3f73121 | 5514 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 5515 | else if (num == 71) |
d3f73121 | 5516 | regnum = mips_regnum (gdbarch)->lo; |
2f38ef89 | 5517 | else |
a4b8ebc8 AC |
5518 | /* This will hopefully (eventually) provoke a warning. Should |
5519 | we be calling complaint() here? */ | |
d3f73121 MD |
5520 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
5521 | return gdbarch_num_regs (gdbarch) + regnum; | |
88c72b7d AC |
5522 | } |
5523 | ||
2f38ef89 | 5524 | |
a4b8ebc8 | 5525 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
f57d151a | 5526 | gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
5527 | |
5528 | static int | |
d3f73121 | 5529 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 5530 | { |
a4b8ebc8 | 5531 | int regnum; |
2f38ef89 | 5532 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5533 | regnum = num; |
2f38ef89 | 5534 | else if (num >= 32 && num < 64) |
d3f73121 | 5535 | regnum = num + mips_regnum (gdbarch)->fp0 - 32; |
040b99fd | 5536 | else if (num == 64) |
d3f73121 | 5537 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 5538 | else if (num == 65) |
d3f73121 | 5539 | regnum = mips_regnum (gdbarch)->lo; |
2f38ef89 | 5540 | else |
a4b8ebc8 AC |
5541 | /* This will hopefully (eventually) provoke a warning. Should we |
5542 | be calling complaint() here? */ | |
d3f73121 MD |
5543 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
5544 | return gdbarch_num_regs (gdbarch) + regnum; | |
a4b8ebc8 AC |
5545 | } |
5546 | ||
5547 | static int | |
e7faf938 | 5548 | mips_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
a4b8ebc8 AC |
5549 | { |
5550 | /* Only makes sense to supply raw registers. */ | |
e7faf938 | 5551 | gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)); |
a4b8ebc8 AC |
5552 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to |
5553 | decide if it is valid. Should instead define a standard sim/gdb | |
5554 | register numbering scheme. */ | |
e7faf938 MD |
5555 | if (gdbarch_register_name (gdbarch, |
5556 | gdbarch_num_regs (gdbarch) + regnum) != NULL | |
5557 | && gdbarch_register_name (gdbarch, | |
025bb325 MS |
5558 | gdbarch_num_regs (gdbarch) |
5559 | + regnum)[0] != '\0') | |
a4b8ebc8 AC |
5560 | return regnum; |
5561 | else | |
6d82d43b | 5562 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
5563 | } |
5564 | ||
2f38ef89 | 5565 | |
4844f454 CV |
5566 | /* Convert an integer into an address. Extracting the value signed |
5567 | guarantees a correctly sign extended address. */ | |
fc0c74b1 AC |
5568 | |
5569 | static CORE_ADDR | |
79dd2d24 | 5570 | mips_integer_to_address (struct gdbarch *gdbarch, |
870cd05e | 5571 | struct type *type, const gdb_byte *buf) |
fc0c74b1 | 5572 | { |
e17a4113 UW |
5573 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
5574 | return extract_signed_integer (buf, TYPE_LENGTH (type), byte_order); | |
fc0c74b1 AC |
5575 | } |
5576 | ||
82e91389 DJ |
5577 | /* Dummy virtual frame pointer method. This is no more or less accurate |
5578 | than most other architectures; we just need to be explicit about it, | |
5579 | because the pseudo-register gdbarch_sp_regnum will otherwise lead to | |
5580 | an assertion failure. */ | |
5581 | ||
5582 | static void | |
a54fba4c MD |
5583 | mips_virtual_frame_pointer (struct gdbarch *gdbarch, |
5584 | CORE_ADDR pc, int *reg, LONGEST *offset) | |
82e91389 DJ |
5585 | { |
5586 | *reg = MIPS_SP_REGNUM; | |
5587 | *offset = 0; | |
5588 | } | |
5589 | ||
caaa3122 DJ |
5590 | static void |
5591 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
5592 | { | |
5593 | enum mips_abi *abip = (enum mips_abi *) obj; | |
5594 | const char *name = bfd_get_section_name (abfd, sect); | |
5595 | ||
5596 | if (*abip != MIPS_ABI_UNKNOWN) | |
5597 | return; | |
5598 | ||
5599 | if (strncmp (name, ".mdebug.", 8) != 0) | |
5600 | return; | |
5601 | ||
5602 | if (strcmp (name, ".mdebug.abi32") == 0) | |
5603 | *abip = MIPS_ABI_O32; | |
5604 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
5605 | *abip = MIPS_ABI_N32; | |
62a49b2c | 5606 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 5607 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
5608 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
5609 | *abip = MIPS_ABI_O64; | |
5610 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
5611 | *abip = MIPS_ABI_EABI32; | |
5612 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
5613 | *abip = MIPS_ABI_EABI64; | |
5614 | else | |
8a3fe4f8 | 5615 | warning (_("unsupported ABI %s."), name + 8); |
caaa3122 DJ |
5616 | } |
5617 | ||
22e47e37 FF |
5618 | static void |
5619 | mips_find_long_section (bfd *abfd, asection *sect, void *obj) | |
5620 | { | |
5621 | int *lbp = (int *) obj; | |
5622 | const char *name = bfd_get_section_name (abfd, sect); | |
5623 | ||
5624 | if (strncmp (name, ".gcc_compiled_long32", 20) == 0) | |
5625 | *lbp = 32; | |
5626 | else if (strncmp (name, ".gcc_compiled_long64", 20) == 0) | |
5627 | *lbp = 64; | |
5628 | else if (strncmp (name, ".gcc_compiled_long", 18) == 0) | |
5629 | warning (_("unrecognized .gcc_compiled_longXX")); | |
5630 | } | |
5631 | ||
2e4ebe70 DJ |
5632 | static enum mips_abi |
5633 | global_mips_abi (void) | |
5634 | { | |
5635 | int i; | |
5636 | ||
5637 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
5638 | if (mips_abi_strings[i] == mips_abi_string) | |
5639 | return (enum mips_abi) i; | |
5640 | ||
e2e0b3e5 | 5641 | internal_error (__FILE__, __LINE__, _("unknown ABI string")); |
2e4ebe70 DJ |
5642 | } |
5643 | ||
29709017 DJ |
5644 | static void |
5645 | mips_register_g_packet_guesses (struct gdbarch *gdbarch) | |
5646 | { | |
29709017 DJ |
5647 | /* If the size matches the set of 32-bit or 64-bit integer registers, |
5648 | assume that's what we've got. */ | |
4eb0ad19 DJ |
5649 | register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32); |
5650 | register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64); | |
29709017 DJ |
5651 | |
5652 | /* If the size matches the full set of registers GDB traditionally | |
5653 | knows about, including floating point, for either 32-bit or | |
5654 | 64-bit, assume that's what we've got. */ | |
4eb0ad19 DJ |
5655 | register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32); |
5656 | register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64); | |
29709017 DJ |
5657 | |
5658 | /* Otherwise we don't have a useful guess. */ | |
5659 | } | |
5660 | ||
f8b73d13 DJ |
5661 | static struct value * |
5662 | value_of_mips_user_reg (struct frame_info *frame, const void *baton) | |
5663 | { | |
5664 | const int *reg_p = baton; | |
5665 | return value_of_register (*reg_p, frame); | |
5666 | } | |
5667 | ||
c2d11a7d | 5668 | static struct gdbarch * |
6d82d43b | 5669 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 5670 | { |
c2d11a7d JM |
5671 | struct gdbarch *gdbarch; |
5672 | struct gdbarch_tdep *tdep; | |
5673 | int elf_flags; | |
2e4ebe70 | 5674 | enum mips_abi mips_abi, found_abi, wanted_abi; |
f8b73d13 | 5675 | int i, num_regs; |
8d5838b5 | 5676 | enum mips_fpu_type fpu_type; |
f8b73d13 | 5677 | struct tdesc_arch_data *tdesc_data = NULL; |
609ca2b9 | 5678 | int elf_fpu_type = 0; |
f8b73d13 DJ |
5679 | |
5680 | /* Check any target description for validity. */ | |
5681 | if (tdesc_has_registers (info.target_desc)) | |
5682 | { | |
5683 | static const char *const mips_gprs[] = { | |
5684 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
5685 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
5686 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
5687 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
5688 | }; | |
5689 | static const char *const mips_fprs[] = { | |
5690 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
5691 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
5692 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
5693 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
5694 | }; | |
5695 | ||
5696 | const struct tdesc_feature *feature; | |
5697 | int valid_p; | |
5698 | ||
5699 | feature = tdesc_find_feature (info.target_desc, | |
5700 | "org.gnu.gdb.mips.cpu"); | |
5701 | if (feature == NULL) | |
5702 | return NULL; | |
5703 | ||
5704 | tdesc_data = tdesc_data_alloc (); | |
5705 | ||
5706 | valid_p = 1; | |
5707 | for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) | |
5708 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
5709 | mips_gprs[i]); | |
5710 | ||
5711 | ||
5712 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5713 | MIPS_EMBED_LO_REGNUM, "lo"); | |
5714 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5715 | MIPS_EMBED_HI_REGNUM, "hi"); | |
5716 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5717 | MIPS_EMBED_PC_REGNUM, "pc"); | |
5718 | ||
5719 | if (!valid_p) | |
5720 | { | |
5721 | tdesc_data_cleanup (tdesc_data); | |
5722 | return NULL; | |
5723 | } | |
5724 | ||
5725 | feature = tdesc_find_feature (info.target_desc, | |
5726 | "org.gnu.gdb.mips.cp0"); | |
5727 | if (feature == NULL) | |
5728 | { | |
5729 | tdesc_data_cleanup (tdesc_data); | |
5730 | return NULL; | |
5731 | } | |
5732 | ||
5733 | valid_p = 1; | |
5734 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5735 | MIPS_EMBED_BADVADDR_REGNUM, | |
5736 | "badvaddr"); | |
5737 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5738 | MIPS_PS_REGNUM, "status"); | |
5739 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5740 | MIPS_EMBED_CAUSE_REGNUM, "cause"); | |
5741 | ||
5742 | if (!valid_p) | |
5743 | { | |
5744 | tdesc_data_cleanup (tdesc_data); | |
5745 | return NULL; | |
5746 | } | |
5747 | ||
5748 | /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS | |
5749 | backend is not prepared for that, though. */ | |
5750 | feature = tdesc_find_feature (info.target_desc, | |
5751 | "org.gnu.gdb.mips.fpu"); | |
5752 | if (feature == NULL) | |
5753 | { | |
5754 | tdesc_data_cleanup (tdesc_data); | |
5755 | return NULL; | |
5756 | } | |
5757 | ||
5758 | valid_p = 1; | |
5759 | for (i = 0; i < 32; i++) | |
5760 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5761 | i + MIPS_EMBED_FP0_REGNUM, | |
5762 | mips_fprs[i]); | |
5763 | ||
5764 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5765 | MIPS_EMBED_FP0_REGNUM + 32, "fcsr"); | |
5766 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5767 | MIPS_EMBED_FP0_REGNUM + 33, "fir"); | |
5768 | ||
5769 | if (!valid_p) | |
5770 | { | |
5771 | tdesc_data_cleanup (tdesc_data); | |
5772 | return NULL; | |
5773 | } | |
5774 | ||
5775 | /* It would be nice to detect an attempt to use a 64-bit ABI | |
5776 | when only 32-bit registers are provided. */ | |
5777 | } | |
c2d11a7d | 5778 | |
ec03c1ac AC |
5779 | /* First of all, extract the elf_flags, if available. */ |
5780 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5781 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
5782 | else if (arches != NULL) |
5783 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
5784 | else |
5785 | elf_flags = 0; | |
5786 | if (gdbarch_debug) | |
5787 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5788 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 5789 | |
102182a9 | 5790 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
5791 | switch ((elf_flags & EF_MIPS_ABI)) |
5792 | { | |
5793 | case E_MIPS_ABI_O32: | |
ec03c1ac | 5794 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
5795 | break; |
5796 | case E_MIPS_ABI_O64: | |
ec03c1ac | 5797 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
5798 | break; |
5799 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 5800 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
5801 | break; |
5802 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 5803 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
5804 | break; |
5805 | default: | |
acdb74a0 | 5806 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 5807 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 5808 | else |
ec03c1ac | 5809 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
5810 | break; |
5811 | } | |
acdb74a0 | 5812 | |
caaa3122 | 5813 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
5814 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
5815 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 5816 | |
dc305454 | 5817 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
5818 | MIPS architecture (if there is one). */ |
5819 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
5820 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 5821 | |
32a6503c | 5822 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 5823 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
5824 | && info.bfd_arch_info != NULL |
5825 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5826 | { | |
5827 | switch (info.bfd_arch_info->mach) | |
5828 | { | |
5829 | case bfd_mach_mips3900: | |
ec03c1ac | 5830 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
5831 | break; |
5832 | case bfd_mach_mips4100: | |
5833 | case bfd_mach_mips5000: | |
ec03c1ac | 5834 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 5835 | break; |
1d06468c EZ |
5836 | case bfd_mach_mips8000: |
5837 | case bfd_mach_mips10000: | |
32a6503c KB |
5838 | /* On Irix, ELF64 executables use the N64 ABI. The |
5839 | pseudo-sections which describe the ABI aren't present | |
5840 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
5841 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
5842 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 5843 | found_abi = MIPS_ABI_N64; |
28d169de | 5844 | else |
ec03c1ac | 5845 | found_abi = MIPS_ABI_N32; |
1d06468c | 5846 | break; |
bf64bfd6 AC |
5847 | } |
5848 | } | |
2e4ebe70 | 5849 | |
26c53e50 DJ |
5850 | /* Default 64-bit objects to N64 instead of O32. */ |
5851 | if (found_abi == MIPS_ABI_UNKNOWN | |
5852 | && info.abfd != NULL | |
5853 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
5854 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
5855 | found_abi = MIPS_ABI_N64; | |
5856 | ||
ec03c1ac AC |
5857 | if (gdbarch_debug) |
5858 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
5859 | found_abi); | |
5860 | ||
5861 | /* What has the user specified from the command line? */ | |
5862 | wanted_abi = global_mips_abi (); | |
5863 | if (gdbarch_debug) | |
5864 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
5865 | wanted_abi); | |
2e4ebe70 DJ |
5866 | |
5867 | /* Now that we have found what the ABI for this binary would be, | |
5868 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
5869 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
5870 | mips_abi = wanted_abi; | |
ec03c1ac AC |
5871 | else if (found_abi != MIPS_ABI_UNKNOWN) |
5872 | mips_abi = found_abi; | |
5873 | else | |
5874 | mips_abi = MIPS_ABI_O32; | |
5875 | if (gdbarch_debug) | |
5876 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
5877 | mips_abi); | |
2e4ebe70 | 5878 | |
ec03c1ac | 5879 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 5880 | if (gdbarch_debug) |
ec03c1ac | 5881 | fprintf_unfiltered (gdb_stdlog, |
025bb325 MS |
5882 | "mips_gdbarch_init: " |
5883 | "mips64_transfers_32bit_regs_p = %d\n", | |
ec03c1ac | 5884 | mips64_transfers_32bit_regs_p); |
0dadbba0 | 5885 | |
8d5838b5 | 5886 | /* Determine the MIPS FPU type. */ |
609ca2b9 DJ |
5887 | #ifdef HAVE_ELF |
5888 | if (info.abfd | |
5889 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5890 | elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
5891 | Tag_GNU_MIPS_ABI_FP); | |
5892 | #endif /* HAVE_ELF */ | |
5893 | ||
8d5838b5 AC |
5894 | if (!mips_fpu_type_auto) |
5895 | fpu_type = mips_fpu_type; | |
609ca2b9 DJ |
5896 | else if (elf_fpu_type != 0) |
5897 | { | |
5898 | switch (elf_fpu_type) | |
5899 | { | |
5900 | case 1: | |
5901 | fpu_type = MIPS_FPU_DOUBLE; | |
5902 | break; | |
5903 | case 2: | |
5904 | fpu_type = MIPS_FPU_SINGLE; | |
5905 | break; | |
5906 | case 3: | |
5907 | default: | |
5908 | /* Soft float or unknown. */ | |
5909 | fpu_type = MIPS_FPU_NONE; | |
5910 | break; | |
5911 | } | |
5912 | } | |
8d5838b5 AC |
5913 | else if (info.bfd_arch_info != NULL |
5914 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5915 | switch (info.bfd_arch_info->mach) | |
5916 | { | |
5917 | case bfd_mach_mips3900: | |
5918 | case bfd_mach_mips4100: | |
5919 | case bfd_mach_mips4111: | |
a9d61c86 | 5920 | case bfd_mach_mips4120: |
8d5838b5 AC |
5921 | fpu_type = MIPS_FPU_NONE; |
5922 | break; | |
5923 | case bfd_mach_mips4650: | |
5924 | fpu_type = MIPS_FPU_SINGLE; | |
5925 | break; | |
5926 | default: | |
5927 | fpu_type = MIPS_FPU_DOUBLE; | |
5928 | break; | |
5929 | } | |
5930 | else if (arches != NULL) | |
5931 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
5932 | else | |
5933 | fpu_type = MIPS_FPU_DOUBLE; | |
5934 | if (gdbarch_debug) | |
5935 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5936 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 5937 | |
29709017 DJ |
5938 | /* Check for blatant incompatibilities. */ |
5939 | ||
5940 | /* If we have only 32-bit registers, then we can't debug a 64-bit | |
5941 | ABI. */ | |
5942 | if (info.target_desc | |
5943 | && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL | |
5944 | && mips_abi != MIPS_ABI_EABI32 | |
5945 | && mips_abi != MIPS_ABI_O32) | |
f8b73d13 DJ |
5946 | { |
5947 | if (tdesc_data != NULL) | |
5948 | tdesc_data_cleanup (tdesc_data); | |
5949 | return NULL; | |
5950 | } | |
29709017 | 5951 | |
025bb325 | 5952 | /* Try to find a pre-existing architecture. */ |
c2d11a7d JM |
5953 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
5954 | arches != NULL; | |
5955 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
5956 | { | |
5957 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 5958 | using. */ |
9103eae0 | 5959 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 5960 | continue; |
9103eae0 | 5961 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 5962 | continue; |
719ec221 AC |
5963 | /* Need to be pedantic about which register virtual size is |
5964 | used. */ | |
5965 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
5966 | != mips64_transfers_32bit_regs_p) | |
5967 | continue; | |
8d5838b5 AC |
5968 | /* Be pedantic about which FPU is selected. */ |
5969 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
5970 | continue; | |
f8b73d13 DJ |
5971 | |
5972 | if (tdesc_data != NULL) | |
5973 | tdesc_data_cleanup (tdesc_data); | |
4be87837 | 5974 | return arches->gdbarch; |
c2d11a7d JM |
5975 | } |
5976 | ||
102182a9 | 5977 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
5978 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
5979 | gdbarch = gdbarch_alloc (&info, tdep); | |
5980 | tdep->elf_flags = elf_flags; | |
719ec221 | 5981 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
5982 | tdep->found_abi = found_abi; |
5983 | tdep->mips_abi = mips_abi; | |
8d5838b5 | 5984 | tdep->mips_fpu_type = fpu_type; |
29709017 DJ |
5985 | tdep->register_size_valid_p = 0; |
5986 | tdep->register_size = 0; | |
50e8a0d5 HZ |
5987 | tdep->gregset = NULL; |
5988 | tdep->gregset64 = NULL; | |
5989 | tdep->fpregset = NULL; | |
5990 | tdep->fpregset64 = NULL; | |
29709017 DJ |
5991 | |
5992 | if (info.target_desc) | |
5993 | { | |
5994 | /* Some useful properties can be inferred from the target. */ | |
5995 | if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) | |
5996 | { | |
5997 | tdep->register_size_valid_p = 1; | |
5998 | tdep->register_size = 4; | |
5999 | } | |
6000 | else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) | |
6001 | { | |
6002 | tdep->register_size_valid_p = 1; | |
6003 | tdep->register_size = 8; | |
6004 | } | |
6005 | } | |
c2d11a7d | 6006 | |
102182a9 | 6007 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
6008 | set_gdbarch_short_bit (gdbarch, 16); |
6009 | set_gdbarch_int_bit (gdbarch, 32); | |
6010 | set_gdbarch_float_bit (gdbarch, 32); | |
6011 | set_gdbarch_double_bit (gdbarch, 64); | |
6012 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
6013 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
6014 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
6015 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 6016 | |
175ff332 HZ |
6017 | set_gdbarch_ax_pseudo_register_collect (gdbarch, |
6018 | mips_ax_pseudo_register_collect); | |
6019 | set_gdbarch_ax_pseudo_register_push_stack | |
6020 | (gdbarch, mips_ax_pseudo_register_push_stack); | |
6021 | ||
6d82d43b | 6022 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
6023 | mips_elf_make_msymbol_special); |
6024 | ||
16e109ca | 6025 | /* Fill in the OS dependant register numbers and names. */ |
56cea623 | 6026 | { |
16e109ca | 6027 | const char **reg_names; |
56cea623 AC |
6028 | struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, |
6029 | struct mips_regnum); | |
f8b73d13 DJ |
6030 | if (tdesc_has_registers (info.target_desc)) |
6031 | { | |
6032 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
6033 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
6034 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
6035 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
6036 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
6037 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
6038 | regnum->fp_control_status = 70; | |
6039 | regnum->fp_implementation_revision = 71; | |
6040 | num_regs = MIPS_LAST_EMBED_REGNUM + 1; | |
6041 | reg_names = NULL; | |
6042 | } | |
6043 | else if (info.osabi == GDB_OSABI_IRIX) | |
56cea623 AC |
6044 | { |
6045 | regnum->fp0 = 32; | |
6046 | regnum->pc = 64; | |
6047 | regnum->cause = 65; | |
6048 | regnum->badvaddr = 66; | |
6049 | regnum->hi = 67; | |
6050 | regnum->lo = 68; | |
6051 | regnum->fp_control_status = 69; | |
6052 | regnum->fp_implementation_revision = 70; | |
6053 | num_regs = 71; | |
16e109ca | 6054 | reg_names = mips_irix_reg_names; |
56cea623 AC |
6055 | } |
6056 | else | |
6057 | { | |
6058 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
6059 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
6060 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
6061 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
6062 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
6063 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
6064 | regnum->fp_control_status = 70; | |
6065 | regnum->fp_implementation_revision = 71; | |
6066 | num_regs = 90; | |
16e109ca AC |
6067 | if (info.bfd_arch_info != NULL |
6068 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
6069 | reg_names = mips_tx39_reg_names; | |
6070 | else | |
6071 | reg_names = mips_generic_reg_names; | |
56cea623 | 6072 | } |
3e8c568d | 6073 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been |
fb14de7b | 6074 | replaced by gdbarch_read_pc? */ |
f10683bb MH |
6075 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); |
6076 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
56cea623 AC |
6077 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
6078 | set_gdbarch_num_regs (gdbarch, num_regs); | |
6079 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
16e109ca | 6080 | set_gdbarch_register_name (gdbarch, mips_register_name); |
82e91389 | 6081 | set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer); |
16e109ca AC |
6082 | tdep->mips_processor_reg_names = reg_names; |
6083 | tdep->regnum = regnum; | |
56cea623 | 6084 | } |
fe29b929 | 6085 | |
0dadbba0 | 6086 | switch (mips_abi) |
c2d11a7d | 6087 | { |
0dadbba0 | 6088 | case MIPS_ABI_O32: |
25ab4790 | 6089 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 6090 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
4c7d22cb | 6091 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 6092 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 6093 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6094 | set_gdbarch_long_bit (gdbarch, 32); |
6095 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6096 | set_gdbarch_long_long_bit (gdbarch, 64); | |
6097 | break; | |
0dadbba0 | 6098 | case MIPS_ABI_O64: |
25ab4790 | 6099 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
9c8fdbfa | 6100 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
4c7d22cb | 6101 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 6102 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 6103 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6104 | set_gdbarch_long_bit (gdbarch, 32); |
6105 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6106 | set_gdbarch_long_long_bit (gdbarch, 64); | |
6107 | break; | |
0dadbba0 | 6108 | case MIPS_ABI_EABI32: |
25ab4790 | 6109 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 6110 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 6111 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 6112 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 6113 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6114 | set_gdbarch_long_bit (gdbarch, 32); |
6115 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6116 | set_gdbarch_long_long_bit (gdbarch, 64); | |
6117 | break; | |
0dadbba0 | 6118 | case MIPS_ABI_EABI64: |
25ab4790 | 6119 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 6120 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 6121 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 6122 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 6123 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6124 | set_gdbarch_long_bit (gdbarch, 64); |
6125 | set_gdbarch_ptr_bit (gdbarch, 64); | |
6126 | set_gdbarch_long_long_bit (gdbarch, 64); | |
6127 | break; | |
0dadbba0 | 6128 | case MIPS_ABI_N32: |
25ab4790 | 6129 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 6130 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 6131 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 6132 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 6133 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
6134 | set_gdbarch_long_bit (gdbarch, 32); |
6135 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6136 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 6137 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 6138 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
28d169de KB |
6139 | break; |
6140 | case MIPS_ABI_N64: | |
25ab4790 | 6141 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 6142 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 6143 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 6144 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
6145 | tdep->default_mask_address_p = 0; |
6146 | set_gdbarch_long_bit (gdbarch, 64); | |
6147 | set_gdbarch_ptr_bit (gdbarch, 64); | |
6148 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 6149 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 6150 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
0dadbba0 | 6151 | break; |
c2d11a7d | 6152 | default: |
e2e0b3e5 | 6153 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); |
c2d11a7d JM |
6154 | } |
6155 | ||
22e47e37 FF |
6156 | /* GCC creates a pseudo-section whose name specifies the size of |
6157 | longs, since -mlong32 or -mlong64 may be used independent of | |
6158 | other options. How those options affect pointer sizes is ABI and | |
6159 | architecture dependent, so use them to override the default sizes | |
6160 | set by the ABI. This table shows the relationship between ABI, | |
6161 | -mlongXX, and size of pointers: | |
6162 | ||
6163 | ABI -mlongXX ptr bits | |
6164 | --- -------- -------- | |
6165 | o32 32 32 | |
6166 | o32 64 32 | |
6167 | n32 32 32 | |
6168 | n32 64 64 | |
6169 | o64 32 32 | |
6170 | o64 64 64 | |
6171 | n64 32 32 | |
6172 | n64 64 64 | |
6173 | eabi32 32 32 | |
6174 | eabi32 64 32 | |
6175 | eabi64 32 32 | |
6176 | eabi64 64 64 | |
6177 | ||
6178 | Note that for o32 and eabi32, pointers are always 32 bits | |
6179 | regardless of any -mlongXX option. For all others, pointers and | |
025bb325 | 6180 | longs are the same, as set by -mlongXX or set by defaults. */ |
22e47e37 FF |
6181 | |
6182 | if (info.abfd != NULL) | |
6183 | { | |
6184 | int long_bit = 0; | |
6185 | ||
6186 | bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); | |
6187 | if (long_bit) | |
6188 | { | |
6189 | set_gdbarch_long_bit (gdbarch, long_bit); | |
6190 | switch (mips_abi) | |
6191 | { | |
6192 | case MIPS_ABI_O32: | |
6193 | case MIPS_ABI_EABI32: | |
6194 | break; | |
6195 | case MIPS_ABI_N32: | |
6196 | case MIPS_ABI_O64: | |
6197 | case MIPS_ABI_N64: | |
6198 | case MIPS_ABI_EABI64: | |
6199 | set_gdbarch_ptr_bit (gdbarch, long_bit); | |
6200 | break; | |
6201 | default: | |
6202 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); | |
6203 | } | |
6204 | } | |
6205 | } | |
6206 | ||
a5ea2558 AC |
6207 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
6208 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
6209 | comment: | |
6210 | ||
6211 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
6212 | flag in object files because to do so would make it impossible to | |
102182a9 | 6213 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 6214 | unnecessarily restrictive. |
361d1df0 | 6215 | |
a5ea2558 AC |
6216 | We could solve this problem by adding "-gp32" multilibs to gcc, |
6217 | but to set this flag before gcc is built with such multilibs will | |
6218 | break too many systems.'' | |
6219 | ||
6220 | But even more unhelpfully, the default linker output target for | |
6221 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
6222 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 6223 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
6224 | this flag to detect 32-bit mode would do the wrong thing given |
6225 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 6226 | as 32-bit programs by default. */ |
a5ea2558 | 6227 | |
6c997a34 | 6228 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 6229 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
c2d11a7d | 6230 | |
102182a9 MS |
6231 | /* Add/remove bits from an address. The MIPS needs be careful to |
6232 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
6233 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
6234 | ||
58dfe9ff AC |
6235 | /* Unwind the frame. */ |
6236 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
30244cd8 | 6237 | set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); |
b8a22b94 | 6238 | set_gdbarch_dummy_id (gdbarch, mips_dummy_id); |
10312cc4 | 6239 | |
102182a9 | 6240 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 6241 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
6242 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
6243 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
6d82d43b AC |
6244 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, |
6245 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 6246 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 6247 | |
025bb325 | 6248 | /* MIPS version of CALL_DUMMY. */ |
c2d11a7d | 6249 | |
9710e734 AC |
6250 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
6251 | replaced by a command, and all targets will default to on stack | |
6252 | (regardless of the stack's execute status). */ | |
6253 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
dc604539 | 6254 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 6255 | |
87783b8b AC |
6256 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
6257 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
6258 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
6259 | ||
f7b9e9fc AC |
6260 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
6261 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
f7b9e9fc AC |
6262 | |
6263 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 6264 | |
97ab0fdd MR |
6265 | set_gdbarch_in_function_epilogue_p (gdbarch, mips_in_function_epilogue_p); |
6266 | ||
fc0c74b1 AC |
6267 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
6268 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
6269 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 6270 | |
a4b8ebc8 | 6271 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 6272 | |
e11c53d2 | 6273 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 6274 | |
9dae60cc UW |
6275 | if (mips_abi == MIPS_ABI_N32) |
6276 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n32); | |
6277 | else if (mips_abi == MIPS_ABI_N64) | |
6278 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n64); | |
6279 | else | |
6280 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); | |
e5ab0dce | 6281 | |
d92524f1 PM |
6282 | /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint, |
6283 | HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint | |
3a3bc038 | 6284 | need to all be folded into the target vector. Since they are |
d92524f1 PM |
6285 | being used as guards for target_stopped_by_watchpoint, why not have |
6286 | target_stopped_by_watchpoint return the type of watchpoint that the code | |
3a3bc038 AC |
6287 | is sitting on? */ |
6288 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
6289 | ||
e7d6a6d2 | 6290 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
757a7cc6 | 6291 | |
025bb325 MS |
6292 | set_gdbarch_single_step_through_delay (gdbarch, |
6293 | mips_single_step_through_delay); | |
3352ef37 | 6294 | |
0d5de010 DJ |
6295 | /* Virtual tables. */ |
6296 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
6297 | ||
29709017 DJ |
6298 | mips_register_g_packet_guesses (gdbarch); |
6299 | ||
6de918a6 | 6300 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
822b6570 | 6301 | info.tdep_info = (void *) tdesc_data; |
6de918a6 | 6302 | gdbarch_init_osabi (info, gdbarch); |
757a7cc6 | 6303 | |
5792a79b | 6304 | /* Unwind the frame. */ |
b8a22b94 DJ |
6305 | dwarf2_append_unwinders (gdbarch); |
6306 | frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind); | |
6307 | frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind); | |
6308 | frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind); | |
2bd0c3d7 | 6309 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
eec63939 | 6310 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
45c9dd44 AC |
6311 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
6312 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); | |
5792a79b | 6313 | |
f8b73d13 DJ |
6314 | if (tdesc_data) |
6315 | { | |
6316 | set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); | |
7cc46491 | 6317 | tdesc_use_registers (gdbarch, info.target_desc, tdesc_data); |
f8b73d13 DJ |
6318 | |
6319 | /* Override the normal target description methods to handle our | |
6320 | dual real and pseudo registers. */ | |
6321 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
025bb325 MS |
6322 | set_gdbarch_register_reggroup_p (gdbarch, |
6323 | mips_tdesc_register_reggroup_p); | |
f8b73d13 DJ |
6324 | |
6325 | num_regs = gdbarch_num_regs (gdbarch); | |
6326 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
6327 | set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs); | |
6328 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
6329 | } | |
6330 | ||
6331 | /* Add ABI-specific aliases for the registers. */ | |
6332 | if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) | |
6333 | for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++) | |
6334 | user_reg_add (gdbarch, mips_n32_n64_aliases[i].name, | |
6335 | value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); | |
6336 | else | |
6337 | for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) | |
6338 | user_reg_add (gdbarch, mips_o32_aliases[i].name, | |
6339 | value_of_mips_user_reg, &mips_o32_aliases[i].regnum); | |
6340 | ||
6341 | /* Add some other standard aliases. */ | |
6342 | for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) | |
6343 | user_reg_add (gdbarch, mips_register_aliases[i].name, | |
6344 | value_of_mips_user_reg, &mips_register_aliases[i].regnum); | |
6345 | ||
865093a3 AR |
6346 | for (i = 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++) |
6347 | user_reg_add (gdbarch, mips_numeric_register_aliases[i].name, | |
6348 | value_of_mips_user_reg, | |
6349 | &mips_numeric_register_aliases[i].regnum); | |
6350 | ||
4b9b3959 AC |
6351 | return gdbarch; |
6352 | } | |
6353 | ||
2e4ebe70 | 6354 | static void |
6d82d43b | 6355 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
6356 | { |
6357 | struct gdbarch_info info; | |
6358 | ||
6359 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
6360 | mips_gdbarch_init will take care of the rest. */ | |
6361 | gdbarch_info_init (&info); | |
6362 | gdbarch_update_p (info); | |
6363 | } | |
6364 | ||
ad188201 KB |
6365 | /* Print out which MIPS ABI is in use. */ |
6366 | ||
6367 | static void | |
1f8ca57c JB |
6368 | show_mips_abi (struct ui_file *file, |
6369 | int from_tty, | |
6370 | struct cmd_list_element *ignored_cmd, | |
6371 | const char *ignored_value) | |
ad188201 | 6372 | { |
1cf3db46 | 6373 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips) |
1f8ca57c JB |
6374 | fprintf_filtered |
6375 | (file, | |
6376 | "The MIPS ABI is unknown because the current architecture " | |
6377 | "is not MIPS.\n"); | |
ad188201 KB |
6378 | else |
6379 | { | |
6380 | enum mips_abi global_abi = global_mips_abi (); | |
1cf3db46 | 6381 | enum mips_abi actual_abi = mips_abi (target_gdbarch); |
ad188201 KB |
6382 | const char *actual_abi_str = mips_abi_strings[actual_abi]; |
6383 | ||
6384 | if (global_abi == MIPS_ABI_UNKNOWN) | |
1f8ca57c JB |
6385 | fprintf_filtered |
6386 | (file, | |
6387 | "The MIPS ABI is set automatically (currently \"%s\").\n", | |
6d82d43b | 6388 | actual_abi_str); |
ad188201 | 6389 | else if (global_abi == actual_abi) |
1f8ca57c JB |
6390 | fprintf_filtered |
6391 | (file, | |
6392 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6d82d43b | 6393 | actual_abi_str); |
ad188201 KB |
6394 | else |
6395 | { | |
6396 | /* Probably shouldn't happen... */ | |
025bb325 MS |
6397 | fprintf_filtered (file, |
6398 | "The (auto detected) MIPS ABI \"%s\" is in use " | |
6399 | "even though the user setting was \"%s\".\n", | |
6d82d43b | 6400 | actual_abi_str, mips_abi_strings[global_abi]); |
ad188201 KB |
6401 | } |
6402 | } | |
6403 | } | |
6404 | ||
4b9b3959 | 6405 | static void |
72a155b4 | 6406 | mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
4b9b3959 | 6407 | { |
72a155b4 | 6408 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4b9b3959 | 6409 | if (tdep != NULL) |
c2d11a7d | 6410 | { |
acdb74a0 AC |
6411 | int ef_mips_arch; |
6412 | int ef_mips_32bitmode; | |
f49e4e6d | 6413 | /* Determine the ISA. */ |
acdb74a0 AC |
6414 | switch (tdep->elf_flags & EF_MIPS_ARCH) |
6415 | { | |
6416 | case E_MIPS_ARCH_1: | |
6417 | ef_mips_arch = 1; | |
6418 | break; | |
6419 | case E_MIPS_ARCH_2: | |
6420 | ef_mips_arch = 2; | |
6421 | break; | |
6422 | case E_MIPS_ARCH_3: | |
6423 | ef_mips_arch = 3; | |
6424 | break; | |
6425 | case E_MIPS_ARCH_4: | |
93d56215 | 6426 | ef_mips_arch = 4; |
acdb74a0 AC |
6427 | break; |
6428 | default: | |
93d56215 | 6429 | ef_mips_arch = 0; |
acdb74a0 AC |
6430 | break; |
6431 | } | |
f49e4e6d | 6432 | /* Determine the size of a pointer. */ |
acdb74a0 | 6433 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); |
4b9b3959 AC |
6434 | fprintf_unfiltered (file, |
6435 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 6436 | tdep->elf_flags); |
4b9b3959 | 6437 | fprintf_unfiltered (file, |
acdb74a0 AC |
6438 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
6439 | ef_mips_32bitmode); | |
6440 | fprintf_unfiltered (file, | |
6441 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
6442 | ef_mips_arch); | |
6443 | fprintf_unfiltered (file, | |
6444 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 6445 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b | 6446 | fprintf_unfiltered (file, |
025bb325 MS |
6447 | "mips_dump_tdep: " |
6448 | "mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 6449 | mips_mask_address_p (tdep), |
4014092b | 6450 | tdep->default_mask_address_p); |
c2d11a7d | 6451 | } |
4b9b3959 AC |
6452 | fprintf_unfiltered (file, |
6453 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
6454 | MIPS_DEFAULT_FPU_TYPE, | |
6455 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6456 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6457 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6458 | : "???")); | |
74ed0bb4 MD |
6459 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", |
6460 | MIPS_EABI (gdbarch)); | |
4b9b3959 AC |
6461 | fprintf_unfiltered (file, |
6462 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
74ed0bb4 MD |
6463 | MIPS_FPU_TYPE (gdbarch), |
6464 | (MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_NONE ? "none" | |
6465 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_SINGLE ? "single" | |
6466 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_DOUBLE ? "double" | |
4b9b3959 | 6467 | : "???")); |
c2d11a7d JM |
6468 | } |
6469 | ||
025bb325 | 6470 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 6471 | |
c906108c | 6472 | void |
acdb74a0 | 6473 | _initialize_mips_tdep (void) |
c906108c SS |
6474 | { |
6475 | static struct cmd_list_element *mipsfpulist = NULL; | |
6476 | struct cmd_list_element *c; | |
6477 | ||
6d82d43b | 6478 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
6479 | if (MIPS_ABI_LAST + 1 |
6480 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
e2e0b3e5 | 6481 | internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync")); |
2e4ebe70 | 6482 | |
4b9b3959 | 6483 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 6484 | |
8d5f9dcb DJ |
6485 | mips_pdr_data = register_objfile_data (); |
6486 | ||
4eb0ad19 DJ |
6487 | /* Create feature sets with the appropriate properties. The values |
6488 | are not important. */ | |
6489 | mips_tdesc_gp32 = allocate_target_description (); | |
6490 | set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, ""); | |
6491 | ||
6492 | mips_tdesc_gp64 = allocate_target_description (); | |
6493 | set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, ""); | |
6494 | ||
025bb325 | 6495 | /* Add root prefix command for all "set mips"/"show mips" commands. */ |
a5ea2558 | 6496 | add_prefix_cmd ("mips", no_class, set_mips_command, |
1bedd215 | 6497 | _("Various MIPS specific commands."), |
a5ea2558 AC |
6498 | &setmipscmdlist, "set mips ", 0, &setlist); |
6499 | ||
6500 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
1bedd215 | 6501 | _("Various MIPS specific commands."), |
a5ea2558 AC |
6502 | &showmipscmdlist, "show mips ", 0, &showlist); |
6503 | ||
025bb325 | 6504 | /* Allow the user to override the ABI. */ |
7ab04401 AC |
6505 | add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, |
6506 | &mips_abi_string, _("\ | |
6507 | Set the MIPS ABI used by this program."), _("\ | |
6508 | Show the MIPS ABI used by this program."), _("\ | |
6509 | This option can be set to one of:\n\ | |
6510 | auto - the default ABI associated with the current binary\n\ | |
6511 | o32\n\ | |
6512 | o64\n\ | |
6513 | n32\n\ | |
6514 | n64\n\ | |
6515 | eabi32\n\ | |
6516 | eabi64"), | |
6517 | mips_abi_update, | |
6518 | show_mips_abi, | |
6519 | &setmipscmdlist, &showmipscmdlist); | |
2e4ebe70 | 6520 | |
c906108c SS |
6521 | /* Let the user turn off floating point and set the fence post for |
6522 | heuristic_proc_start. */ | |
6523 | ||
6524 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
1bedd215 | 6525 | _("Set use of MIPS floating-point coprocessor."), |
c906108c SS |
6526 | &mipsfpulist, "set mipsfpu ", 0, &setlist); |
6527 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
1a966eab | 6528 | _("Select single-precision MIPS floating-point coprocessor."), |
c906108c SS |
6529 | &mipsfpulist); |
6530 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
1a966eab | 6531 | _("Select double-precision MIPS floating-point coprocessor."), |
c906108c SS |
6532 | &mipsfpulist); |
6533 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
6534 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
6535 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
6536 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
1a966eab | 6537 | _("Select no MIPS floating-point coprocessor."), &mipsfpulist); |
c906108c SS |
6538 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
6539 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
6540 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
6541 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
1a966eab | 6542 | _("Select MIPS floating-point coprocessor automatically."), |
c906108c SS |
6543 | &mipsfpulist); |
6544 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
1a966eab | 6545 | _("Show current use of MIPS floating-point coprocessor target."), |
c906108c SS |
6546 | &showlist); |
6547 | ||
c906108c SS |
6548 | /* We really would like to have both "0" and "unlimited" work, but |
6549 | command.c doesn't deal with that. So make it a var_zinteger | |
6550 | because the user can always use "999999" or some such for unlimited. */ | |
6bcadd06 | 6551 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
7915a72c AC |
6552 | &heuristic_fence_post, _("\ |
6553 | Set the distance searched for the start of a function."), _("\ | |
6554 | Show the distance searched for the start of a function."), _("\ | |
c906108c SS |
6555 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
6556 | program for the start of a function. This command sets the distance of the\n\ | |
7915a72c | 6557 | search. The only need to set it is when debugging a stripped executable."), |
2c5b56ce | 6558 | reinit_frame_cache_sfunc, |
025bb325 MS |
6559 | NULL, /* FIXME: i18n: The distance searched for |
6560 | the start of a function is %s. */ | |
6bcadd06 | 6561 | &setlist, &showlist); |
c906108c SS |
6562 | |
6563 | /* Allow the user to control whether the upper bits of 64-bit | |
6564 | addresses should be zeroed. */ | |
7915a72c AC |
6565 | add_setshow_auto_boolean_cmd ("mask-address", no_class, |
6566 | &mask_address_var, _("\ | |
6567 | Set zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
6568 | Show zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
cce7e648 | 6569 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\ |
7915a72c | 6570 | allow GDB to determine the correct value."), |
08546159 AC |
6571 | NULL, show_mask_address, |
6572 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
6573 | |
6574 | /* Allow the user to control the size of 32 bit registers within the | |
6575 | raw remote packet. */ | |
b3f42336 | 6576 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
7915a72c AC |
6577 | &mips64_transfers_32bit_regs_p, _("\ |
6578 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
6579 | _("\ | |
6580 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
6581 | _("\ | |
719ec221 AC |
6582 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
6583 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
7915a72c | 6584 | 64 bits for others. Use \"off\" to disable compatibility mode"), |
2c5b56ce | 6585 | set_mips64_transfers_32bit_regs, |
025bb325 MS |
6586 | NULL, /* FIXME: i18n: Compatibility with 64-bit |
6587 | MIPS target that transfers 32-bit | |
6588 | quantities is %s. */ | |
7915a72c | 6589 | &setlist, &showlist); |
9ace0497 | 6590 | |
025bb325 | 6591 | /* Debug this files internals. */ |
6bcadd06 | 6592 | add_setshow_zinteger_cmd ("mips", class_maintenance, |
7915a72c AC |
6593 | &mips_debug, _("\ |
6594 | Set mips debugging."), _("\ | |
6595 | Show mips debugging."), _("\ | |
6596 | When non-zero, mips specific debugging is enabled."), | |
2c5b56ce | 6597 | NULL, |
025bb325 MS |
6598 | NULL, /* FIXME: i18n: Mips debugging is |
6599 | currently %s. */ | |
6bcadd06 | 6600 | &setdebuglist, &showdebuglist); |
c906108c | 6601 | } |