Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
cda5a58a | 3 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, |
1e698235 | 4 | 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. |
bf64bfd6 | 5 | |
c906108c SS |
6 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
7 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
8 | ||
c5aa993b | 9 | This file is part of GDB. |
c906108c | 10 | |
c5aa993b JM |
11 | This program is free software; you can redistribute it and/or modify |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2 of the License, or | |
14 | (at your option) any later version. | |
c906108c | 15 | |
c5aa993b JM |
16 | This program is distributed in the hope that it will be useful, |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
c906108c | 20 | |
c5aa993b JM |
21 | You should have received a copy of the GNU General Public License |
22 | along with this program; if not, write to the Free Software | |
23 | Foundation, Inc., 59 Temple Place - Suite 330, | |
24 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
25 | |
26 | #include "defs.h" | |
27 | #include "gdb_string.h" | |
5e2e9765 | 28 | #include "gdb_assert.h" |
c906108c SS |
29 | #include "frame.h" |
30 | #include "inferior.h" | |
31 | #include "symtab.h" | |
32 | #include "value.h" | |
33 | #include "gdbcmd.h" | |
34 | #include "language.h" | |
35 | #include "gdbcore.h" | |
36 | #include "symfile.h" | |
37 | #include "objfiles.h" | |
38 | #include "gdbtypes.h" | |
39 | #include "target.h" | |
28d069e6 | 40 | #include "arch-utils.h" |
4e052eda | 41 | #include "regcache.h" |
70f80edf | 42 | #include "osabi.h" |
d1973055 | 43 | #include "mips-tdep.h" |
fe898f56 | 44 | #include "block.h" |
c906108c SS |
45 | |
46 | #include "opcode/mips.h" | |
c2d11a7d JM |
47 | #include "elf/mips.h" |
48 | #include "elf-bfd.h" | |
2475bac3 | 49 | #include "symcat.h" |
c906108c | 50 | |
e0f7ec59 AC |
51 | static void set_reg_offset (CORE_ADDR *saved_regs, int regnum, CORE_ADDR off); |
52 | ||
dd824b04 DJ |
53 | /* A useful bit in the CP0 status register (PS_REGNUM). */ |
54 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ | |
55 | #define ST0_FR (1 << 26) | |
56 | ||
b0069a17 AC |
57 | /* The sizes of floating point registers. */ |
58 | ||
59 | enum | |
60 | { | |
61 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
62 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
63 | }; | |
64 | ||
0dadbba0 | 65 | |
2e4ebe70 DJ |
66 | static const char *mips_abi_string; |
67 | ||
68 | static const char *mips_abi_strings[] = { | |
69 | "auto", | |
70 | "n32", | |
71 | "o32", | |
28d169de | 72 | "n64", |
2e4ebe70 DJ |
73 | "o64", |
74 | "eabi32", | |
75 | "eabi64", | |
76 | NULL | |
77 | }; | |
78 | ||
cce74817 | 79 | struct frame_extra_info |
c5aa993b JM |
80 | { |
81 | mips_extra_func_info_t proc_desc; | |
82 | int num_args; | |
83 | }; | |
cce74817 | 84 | |
d929b26f AC |
85 | /* Various MIPS ISA options (related to stack analysis) can be |
86 | overridden dynamically. Establish an enum/array for managing | |
87 | them. */ | |
88 | ||
53904c9e AC |
89 | static const char size_auto[] = "auto"; |
90 | static const char size_32[] = "32"; | |
91 | static const char size_64[] = "64"; | |
d929b26f | 92 | |
53904c9e | 93 | static const char *size_enums[] = { |
d929b26f AC |
94 | size_auto, |
95 | size_32, | |
96 | size_64, | |
a5ea2558 AC |
97 | 0 |
98 | }; | |
99 | ||
7a292a7a SS |
100 | /* Some MIPS boards don't support floating point while others only |
101 | support single-precision floating-point operations. See also | |
102 | FP_REGISTER_DOUBLE. */ | |
c906108c SS |
103 | |
104 | enum mips_fpu_type | |
c5aa993b JM |
105 | { |
106 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
107 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
108 | MIPS_FPU_NONE /* No floating point. */ | |
109 | }; | |
c906108c SS |
110 | |
111 | #ifndef MIPS_DEFAULT_FPU_TYPE | |
112 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
113 | #endif | |
114 | static int mips_fpu_type_auto = 1; | |
115 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 116 | |
9ace0497 | 117 | static int mips_debug = 0; |
7a292a7a | 118 | |
c2d11a7d JM |
119 | /* MIPS specific per-architecture information */ |
120 | struct gdbarch_tdep | |
121 | { | |
122 | /* from the elf header */ | |
123 | int elf_flags; | |
70f80edf | 124 | |
c2d11a7d | 125 | /* mips options */ |
0dadbba0 | 126 | enum mips_abi mips_abi; |
2e4ebe70 | 127 | enum mips_abi found_abi; |
c2d11a7d JM |
128 | enum mips_fpu_type mips_fpu_type; |
129 | int mips_last_arg_regnum; | |
130 | int mips_last_fp_arg_regnum; | |
a5ea2558 | 131 | int mips_default_saved_regsize; |
c2d11a7d | 132 | int mips_fp_register_double; |
d929b26f | 133 | int mips_default_stack_argsize; |
5213ab06 | 134 | int gdb_target_is_mips64; |
4014092b | 135 | int default_mask_address_p; |
c2d11a7d JM |
136 | }; |
137 | ||
0dadbba0 | 138 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \ |
216a600b | 139 | || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64) |
c2d11a7d | 140 | |
c2d11a7d | 141 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 142 | |
c2d11a7d | 143 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 144 | |
c2d11a7d | 145 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) |
c2d11a7d | 146 | |
d929b26f AC |
147 | /* Return the currently configured (or set) saved register size. */ |
148 | ||
a5ea2558 | 149 | #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize) |
c2d11a7d | 150 | |
53904c9e | 151 | static const char *mips_saved_regsize_string = size_auto; |
d929b26f AC |
152 | |
153 | #define MIPS_SAVED_REGSIZE (mips_saved_regsize()) | |
154 | ||
95404a3e AC |
155 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
156 | functions to test, set, or clear bit 0 of addresses. */ | |
157 | ||
158 | static CORE_ADDR | |
159 | is_mips16_addr (CORE_ADDR addr) | |
160 | { | |
161 | return ((addr) & 1); | |
162 | } | |
163 | ||
164 | static CORE_ADDR | |
165 | make_mips16_addr (CORE_ADDR addr) | |
166 | { | |
167 | return ((addr) | 1); | |
168 | } | |
169 | ||
170 | static CORE_ADDR | |
171 | unmake_mips16_addr (CORE_ADDR addr) | |
172 | { | |
173 | return ((addr) & ~1); | |
174 | } | |
175 | ||
22540ece AC |
176 | /* Return the contents of register REGNUM as a signed integer. */ |
177 | ||
178 | static LONGEST | |
179 | read_signed_register (int regnum) | |
180 | { | |
181 | void *buf = alloca (REGISTER_RAW_SIZE (regnum)); | |
182 | deprecated_read_register_gen (regnum, buf); | |
183 | return (extract_signed_integer (buf, REGISTER_RAW_SIZE (regnum))); | |
184 | } | |
185 | ||
186 | static LONGEST | |
187 | read_signed_register_pid (int regnum, ptid_t ptid) | |
188 | { | |
189 | ptid_t save_ptid; | |
190 | LONGEST retval; | |
191 | ||
192 | if (ptid_equal (ptid, inferior_ptid)) | |
193 | return read_signed_register (regnum); | |
194 | ||
195 | save_ptid = inferior_ptid; | |
196 | ||
197 | inferior_ptid = ptid; | |
198 | ||
199 | retval = read_signed_register (regnum); | |
200 | ||
201 | inferior_ptid = save_ptid; | |
202 | ||
203 | return retval; | |
204 | } | |
205 | ||
d1973055 KB |
206 | /* Return the MIPS ABI associated with GDBARCH. */ |
207 | enum mips_abi | |
208 | mips_abi (struct gdbarch *gdbarch) | |
209 | { | |
210 | return gdbarch_tdep (gdbarch)->mips_abi; | |
211 | } | |
212 | ||
d929b26f | 213 | static unsigned int |
acdb74a0 | 214 | mips_saved_regsize (void) |
d929b26f AC |
215 | { |
216 | if (mips_saved_regsize_string == size_auto) | |
217 | return MIPS_DEFAULT_SAVED_REGSIZE; | |
218 | else if (mips_saved_regsize_string == size_64) | |
219 | return 8; | |
220 | else /* if (mips_saved_regsize_string == size_32) */ | |
221 | return 4; | |
222 | } | |
223 | ||
71b8ef93 | 224 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa MS |
225 | marks it as 16-bit function. The MSB of the minimal symbol's |
226 | "info" field is used for this purpose. This field is already | |
227 | being used to store the symbol size, so the assumption is | |
228 | that the symbol size cannot exceed 2^31. | |
229 | ||
230 | ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special", | |
231 | i.e. refers to a 16-bit function, and sets a "special" bit in a | |
232 | minimal symbol to mark it as a 16-bit function | |
233 | ||
234 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol | |
235 | MSYMBOL_SIZE returns the size of the minimal symbol, i.e. | |
236 | the "info" field with the "special" bit masked out */ | |
237 | ||
5a89d8aa MS |
238 | static void |
239 | mips_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym) | |
240 | { | |
241 | if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_MIPS16) | |
242 | { | |
243 | MSYMBOL_INFO (msym) = (char *) | |
244 | (((long) MSYMBOL_INFO (msym)) | 0x80000000); | |
245 | SYMBOL_VALUE_ADDRESS (msym) |= 1; | |
246 | } | |
247 | } | |
248 | ||
71b8ef93 MS |
249 | static int |
250 | msymbol_is_special (struct minimal_symbol *msym) | |
251 | { | |
252 | return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0); | |
253 | } | |
254 | ||
255 | static long | |
256 | msymbol_size (struct minimal_symbol *msym) | |
257 | { | |
258 | return ((long) MSYMBOL_INFO (msym) & 0x7fffffff); | |
259 | } | |
260 | ||
88658117 AC |
261 | /* XFER a value from the big/little/left end of the register. |
262 | Depending on the size of the value it might occupy the entire | |
263 | register or just part of it. Make an allowance for this, aligning | |
264 | things accordingly. */ | |
265 | ||
266 | static void | |
267 | mips_xfer_register (struct regcache *regcache, int reg_num, int length, | |
268 | enum bfd_endian endian, bfd_byte *in, const bfd_byte *out, | |
269 | int buf_offset) | |
270 | { | |
d9d9c31f | 271 | bfd_byte reg[MAX_REGISTER_SIZE]; |
88658117 | 272 | int reg_offset = 0; |
cb1d2653 AC |
273 | /* Need to transfer the left or right part of the register, based on |
274 | the targets byte order. */ | |
88658117 AC |
275 | switch (endian) |
276 | { | |
277 | case BFD_ENDIAN_BIG: | |
278 | reg_offset = REGISTER_RAW_SIZE (reg_num) - length; | |
279 | break; | |
280 | case BFD_ENDIAN_LITTLE: | |
281 | reg_offset = 0; | |
282 | break; | |
283 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ | |
284 | reg_offset = 0; | |
285 | break; | |
286 | default: | |
287 | internal_error (__FILE__, __LINE__, "bad switch"); | |
288 | } | |
289 | if (mips_debug) | |
cb1d2653 AC |
290 | fprintf_unfiltered (gdb_stderr, |
291 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
292 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
293 | if (mips_debug && out != NULL) |
294 | { | |
295 | int i; | |
cb1d2653 | 296 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 297 | for (i = 0; i < length; i++) |
cb1d2653 | 298 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
299 | } |
300 | if (in != NULL) | |
301 | regcache_raw_read_part (regcache, reg_num, reg_offset, length, in + buf_offset); | |
302 | if (out != NULL) | |
303 | regcache_raw_write_part (regcache, reg_num, reg_offset, length, out + buf_offset); | |
304 | if (mips_debug && in != NULL) | |
305 | { | |
306 | int i; | |
cb1d2653 | 307 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 308 | for (i = 0; i < length; i++) |
cb1d2653 | 309 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
310 | } |
311 | if (mips_debug) | |
312 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
313 | } | |
314 | ||
dd824b04 DJ |
315 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
316 | compatiblity mode. A return value of 1 means that we have | |
317 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
318 | ||
319 | static int | |
320 | mips2_fp_compat (void) | |
321 | { | |
322 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not | |
323 | meaningful. */ | |
324 | if (REGISTER_RAW_SIZE (FP0_REGNUM) == 4) | |
325 | return 0; | |
326 | ||
327 | #if 0 | |
328 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
329 | in all the places we deal with FP registers. PR gdb/413. */ | |
330 | /* Otherwise check the FR bit in the status register - it controls | |
331 | the FP compatiblity mode. If it is clear we are in compatibility | |
332 | mode. */ | |
333 | if ((read_register (PS_REGNUM) & ST0_FR) == 0) | |
334 | return 1; | |
335 | #endif | |
361d1df0 | 336 | |
dd824b04 DJ |
337 | return 0; |
338 | } | |
339 | ||
c2d11a7d JM |
340 | /* Indicate that the ABI makes use of double-precision registers |
341 | provided by the FPU (rather than combining pairs of registers to | |
342 | form double-precision values). Do not use "TARGET_IS_MIPS64" to | |
343 | determine if the ABI is using double-precision registers. See also | |
344 | MIPS_FPU_TYPE. */ | |
c2d11a7d | 345 | #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double) |
c2d11a7d | 346 | |
d929b26f AC |
347 | /* The amount of space reserved on the stack for registers. This is |
348 | different to MIPS_SAVED_REGSIZE as it determines the alignment of | |
349 | data allocated after the registers have run out. */ | |
350 | ||
0dadbba0 | 351 | #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize) |
d929b26f AC |
352 | |
353 | #define MIPS_STACK_ARGSIZE (mips_stack_argsize ()) | |
354 | ||
53904c9e | 355 | static const char *mips_stack_argsize_string = size_auto; |
d929b26f AC |
356 | |
357 | static unsigned int | |
358 | mips_stack_argsize (void) | |
359 | { | |
360 | if (mips_stack_argsize_string == size_auto) | |
361 | return MIPS_DEFAULT_STACK_ARGSIZE; | |
362 | else if (mips_stack_argsize_string == size_64) | |
363 | return 8; | |
364 | else /* if (mips_stack_argsize_string == size_32) */ | |
365 | return 4; | |
366 | } | |
367 | ||
5213ab06 | 368 | #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0) |
c2d11a7d | 369 | |
92e1c15c | 370 | #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p) |
92e1c15c | 371 | |
7a292a7a | 372 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 373 | |
a14ed312 | 374 | int gdb_print_insn_mips (bfd_vma, disassemble_info *); |
c906108c | 375 | |
570b8f7c AC |
376 | static mips_extra_func_info_t heuristic_proc_desc (CORE_ADDR, CORE_ADDR, |
377 | struct frame_info *, int); | |
c906108c | 378 | |
a14ed312 | 379 | static CORE_ADDR heuristic_proc_start (CORE_ADDR); |
c906108c | 380 | |
a14ed312 | 381 | static CORE_ADDR read_next_frame_reg (struct frame_info *, int); |
c906108c | 382 | |
5a89d8aa | 383 | static int mips_set_processor_type (char *); |
c906108c | 384 | |
a14ed312 | 385 | static void mips_show_processor_type_command (char *, int); |
c906108c | 386 | |
a14ed312 | 387 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 388 | |
570b8f7c AC |
389 | static mips_extra_func_info_t find_proc_desc (CORE_ADDR pc, |
390 | struct frame_info *next_frame, | |
391 | int cur_frame); | |
c906108c | 392 | |
a14ed312 KB |
393 | static CORE_ADDR after_prologue (CORE_ADDR pc, |
394 | mips_extra_func_info_t proc_desc); | |
c906108c | 395 | |
67b2c998 DJ |
396 | static struct type *mips_float_register_type (void); |
397 | static struct type *mips_double_register_type (void); | |
398 | ||
c906108c SS |
399 | /* This value is the model of MIPS in use. It is derived from the value |
400 | of the PrID register. */ | |
401 | ||
402 | char *mips_processor_type; | |
403 | ||
404 | char *tmp_mips_processor_type; | |
405 | ||
acdb74a0 AC |
406 | /* The list of available "set mips " and "show mips " commands */ |
407 | ||
408 | static struct cmd_list_element *setmipscmdlist = NULL; | |
409 | static struct cmd_list_element *showmipscmdlist = NULL; | |
410 | ||
c906108c SS |
411 | /* A set of original names, to be used when restoring back to generic |
412 | registers from a specific set. */ | |
5e2e9765 | 413 | static char *mips_generic_reg_names[] = MIPS_REGISTER_NAMES; |
c906108c | 414 | |
5e2e9765 KB |
415 | /* Integer registers 0 thru 31 are handled explicitly by |
416 | mips_register_name(). Processor specific registers 32 and above | |
417 | are listed in the sets of register names assigned to | |
418 | mips_processor_reg_names. */ | |
419 | static char **mips_processor_reg_names = mips_generic_reg_names; | |
cce74817 | 420 | |
5e2e9765 | 421 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 422 | static const char * |
5e2e9765 | 423 | mips_register_name (int regno) |
cce74817 | 424 | { |
5e2e9765 KB |
425 | /* GPR names for all ABIs other than n32/n64. */ |
426 | static char *mips_gpr_names[] = { | |
427 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
428 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
429 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
430 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
431 | }; | |
432 | ||
433 | /* GPR names for n32 and n64 ABIs. */ | |
434 | static char *mips_n32_n64_gpr_names[] = { | |
435 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
436 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
437 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
438 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
439 | }; | |
440 | ||
441 | enum mips_abi abi = mips_abi (current_gdbarch); | |
442 | ||
443 | /* The MIPS integer registers are always mapped from 0 to 31. The | |
444 | names of the registers (which reflects the conventions regarding | |
445 | register use) vary depending on the ABI. */ | |
446 | if (0 <= regno && regno < 32) | |
447 | { | |
448 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
449 | return mips_n32_n64_gpr_names[regno]; | |
450 | else | |
451 | return mips_gpr_names[regno]; | |
452 | } | |
b006a9e9 | 453 | else if (32 <= regno && regno < NUM_REGS) |
5e2e9765 KB |
454 | return mips_processor_reg_names[regno - 32]; |
455 | else | |
456 | internal_error (__FILE__, __LINE__, | |
457 | "mips_register_name: bad register number %d", regno); | |
cce74817 | 458 | } |
5e2e9765 | 459 | |
9846de1b | 460 | /* *INDENT-OFF* */ |
c906108c SS |
461 | /* Names of IDT R3041 registers. */ |
462 | ||
463 | char *mips_r3041_reg_names[] = { | |
c906108c SS |
464 | "sr", "lo", "hi", "bad", "cause","pc", |
465 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
466 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
467 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
468 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
a094c6fb | 469 | "fsr", "fir", "",/*"fp"*/ "", |
c906108c SS |
470 | "", "", "bus", "ccfg", "", "", "", "", |
471 | "", "", "port", "cmp", "", "", "epc", "prid", | |
472 | }; | |
473 | ||
474 | /* Names of IDT R3051 registers. */ | |
475 | ||
476 | char *mips_r3051_reg_names[] = { | |
c906108c SS |
477 | "sr", "lo", "hi", "bad", "cause","pc", |
478 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
479 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
480 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
481 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
a094c6fb | 482 | "fsr", "fir", ""/*"fp"*/, "", |
c906108c SS |
483 | "inx", "rand", "elo", "", "ctxt", "", "", "", |
484 | "", "", "ehi", "", "", "", "epc", "prid", | |
485 | }; | |
486 | ||
487 | /* Names of IDT R3081 registers. */ | |
488 | ||
489 | char *mips_r3081_reg_names[] = { | |
c906108c SS |
490 | "sr", "lo", "hi", "bad", "cause","pc", |
491 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
492 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
493 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
494 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
a094c6fb | 495 | "fsr", "fir", ""/*"fp"*/, "", |
c906108c SS |
496 | "inx", "rand", "elo", "cfg", "ctxt", "", "", "", |
497 | "", "", "ehi", "", "", "", "epc", "prid", | |
498 | }; | |
499 | ||
500 | /* Names of LSI 33k registers. */ | |
501 | ||
502 | char *mips_lsi33k_reg_names[] = { | |
c906108c SS |
503 | "epc", "hi", "lo", "sr", "cause","badvaddr", |
504 | "dcic", "bpc", "bda", "", "", "", "", "", | |
505 | "", "", "", "", "", "", "", "", | |
506 | "", "", "", "", "", "", "", "", | |
507 | "", "", "", "", "", "", "", "", | |
508 | "", "", "", "", | |
509 | "", "", "", "", "", "", "", "", | |
510 | "", "", "", "", "", "", "", "", | |
511 | }; | |
512 | ||
513 | struct { | |
514 | char *name; | |
515 | char **regnames; | |
516 | } mips_processor_type_table[] = { | |
517 | { "generic", mips_generic_reg_names }, | |
518 | { "r3041", mips_r3041_reg_names }, | |
519 | { "r3051", mips_r3051_reg_names }, | |
520 | { "r3071", mips_r3081_reg_names }, | |
521 | { "r3081", mips_r3081_reg_names }, | |
522 | { "lsi33k", mips_lsi33k_reg_names }, | |
523 | { NULL, NULL } | |
524 | }; | |
9846de1b | 525 | /* *INDENT-ON* */ |
c906108c | 526 | |
c5aa993b JM |
527 | |
528 | ||
529 | ||
c906108c | 530 | /* Table to translate MIPS16 register field to actual register number. */ |
c5aa993b JM |
531 | static int mips16_to_32_reg[8] = |
532 | {16, 17, 2, 3, 4, 5, 6, 7}; | |
c906108c SS |
533 | |
534 | /* Heuristic_proc_start may hunt through the text section for a long | |
535 | time across a 2400 baud serial line. Allows the user to limit this | |
536 | search. */ | |
537 | ||
538 | static unsigned int heuristic_fence_post = 0; | |
539 | ||
c5aa993b JM |
540 | #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ |
541 | #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */ | |
c906108c SS |
542 | #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) |
543 | #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) | |
544 | #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust) | |
545 | #define PROC_REG_MASK(proc) ((proc)->pdr.regmask) | |
546 | #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) | |
547 | #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) | |
548 | #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) | |
549 | #define PROC_PC_REG(proc) ((proc)->pdr.pcreg) | |
6c0d6680 DJ |
550 | /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long, |
551 | this will corrupt pdr.iline. Fortunately we don't use it. */ | |
c906108c SS |
552 | #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) |
553 | #define _PROC_MAGIC_ 0x0F0F0F0F | |
554 | #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_) | |
555 | #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_) | |
556 | ||
557 | struct linked_proc_info | |
c5aa993b JM |
558 | { |
559 | struct mips_extra_func_info info; | |
560 | struct linked_proc_info *next; | |
561 | } | |
562 | *linked_proc_desc_table = NULL; | |
c906108c | 563 | |
cce74817 | 564 | void |
acdb74a0 | 565 | mips_print_extra_frame_info (struct frame_info *fi) |
cce74817 JM |
566 | { |
567 | if (fi | |
da50a4b7 AC |
568 | && get_frame_extra_info (fi) |
569 | && get_frame_extra_info (fi)->proc_desc | |
570 | && get_frame_extra_info (fi)->proc_desc->pdr.framereg < NUM_REGS) | |
d4f3574e | 571 | printf_filtered (" frame pointer is at %s+%s\n", |
da50a4b7 AC |
572 | REGISTER_NAME (get_frame_extra_info (fi)->proc_desc->pdr.framereg), |
573 | paddr_d (get_frame_extra_info (fi)->proc_desc->pdr.frameoffset)); | |
cce74817 | 574 | } |
c906108c | 575 | |
46cd78fb AC |
576 | /* Number of bytes of storage in the actual machine representation for |
577 | register N. NOTE: This indirectly defines the register size | |
578 | transfered by the GDB protocol. */ | |
43e526b9 JM |
579 | |
580 | static int mips64_transfers_32bit_regs_p = 0; | |
581 | ||
f7ab6ec6 | 582 | static int |
acdb74a0 | 583 | mips_register_raw_size (int reg_nr) |
43e526b9 JM |
584 | { |
585 | if (mips64_transfers_32bit_regs_p) | |
586 | return REGISTER_VIRTUAL_SIZE (reg_nr); | |
d02ee681 AC |
587 | else if (reg_nr >= FP0_REGNUM && reg_nr < FP0_REGNUM + 32 |
588 | && FP_REGISTER_DOUBLE) | |
589 | /* For MIPS_ABI_N32 (for example) we need 8 byte floating point | |
590 | registers. */ | |
591 | return 8; | |
43e526b9 JM |
592 | else |
593 | return MIPS_REGSIZE; | |
594 | } | |
595 | ||
46cd78fb AC |
596 | /* Convert between RAW and VIRTUAL registers. The RAW register size |
597 | defines the remote-gdb packet. */ | |
598 | ||
d05285fa | 599 | static int |
acdb74a0 | 600 | mips_register_convertible (int reg_nr) |
43e526b9 JM |
601 | { |
602 | if (mips64_transfers_32bit_regs_p) | |
603 | return 0; | |
604 | else | |
605 | return (REGISTER_RAW_SIZE (reg_nr) > REGISTER_VIRTUAL_SIZE (reg_nr)); | |
606 | } | |
607 | ||
d05285fa | 608 | static void |
acdb74a0 AC |
609 | mips_register_convert_to_virtual (int n, struct type *virtual_type, |
610 | char *raw_buf, char *virt_buf) | |
43e526b9 | 611 | { |
d7449b42 | 612 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
43e526b9 JM |
613 | memcpy (virt_buf, |
614 | raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)), | |
615 | TYPE_LENGTH (virtual_type)); | |
616 | else | |
617 | memcpy (virt_buf, | |
618 | raw_buf, | |
619 | TYPE_LENGTH (virtual_type)); | |
620 | } | |
621 | ||
d05285fa | 622 | static void |
acdb74a0 | 623 | mips_register_convert_to_raw (struct type *virtual_type, int n, |
781a750d | 624 | const char *virt_buf, char *raw_buf) |
43e526b9 JM |
625 | { |
626 | memset (raw_buf, 0, REGISTER_RAW_SIZE (n)); | |
d7449b42 | 627 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
43e526b9 JM |
628 | memcpy (raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)), |
629 | virt_buf, | |
630 | TYPE_LENGTH (virtual_type)); | |
631 | else | |
632 | memcpy (raw_buf, | |
633 | virt_buf, | |
634 | TYPE_LENGTH (virtual_type)); | |
635 | } | |
636 | ||
ff2e87ac AC |
637 | static int |
638 | mips_convert_register_p (int regnum, struct type *type) | |
639 | { | |
640 | return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
641 | && REGISTER_RAW_SIZE (regnum) == 4 | |
642 | && (regnum) >= FP0_REGNUM && (regnum) < FP0_REGNUM + 32 | |
643 | && TYPE_CODE(type) == TYPE_CODE_FLT | |
644 | && TYPE_LENGTH(type) == 8); | |
645 | } | |
646 | ||
42c466d7 | 647 | static void |
ff2e87ac AC |
648 | mips_register_to_value (struct frame_info *frame, int regnum, |
649 | struct type *type, void *to) | |
102182a9 | 650 | { |
ff2e87ac AC |
651 | frame_read_register (frame, regnum + 0, (char *) to + 4); |
652 | frame_read_register (frame, regnum + 1, (char *) to + 0); | |
102182a9 MS |
653 | } |
654 | ||
42c466d7 | 655 | static void |
ff2e87ac AC |
656 | mips_value_to_register (struct frame_info *frame, int regnum, |
657 | struct type *type, const void *from) | |
102182a9 | 658 | { |
ff2e87ac AC |
659 | put_frame_register (frame, regnum + 0, (const char *) from + 4); |
660 | put_frame_register (frame, regnum + 1, (const char *) from + 0); | |
102182a9 MS |
661 | } |
662 | ||
78fde5f8 KB |
663 | /* Return the GDB type object for the "standard" data type |
664 | of data in register REG. | |
665 | ||
666 | Note: kevinb/2002-08-01: The definition below should faithfully | |
667 | reproduce the behavior of each of the REGISTER_VIRTUAL_TYPE | |
0ba6dca9 AC |
668 | definitions found in config/mips/tm-*.h. I'm concerned about the |
669 | ``FCRCS_REGNUM <= reg && reg <= LAST_EMBED_REGNUM'' clause though. | |
670 | In some cases DEPRECATED_FP_REGNUM is in this range, and I doubt | |
78fde5f8 KB |
671 | that this code is correct for the 64-bit case. */ |
672 | ||
673 | static struct type * | |
674 | mips_register_virtual_type (int reg) | |
675 | { | |
676 | if (FP0_REGNUM <= reg && reg < FP0_REGNUM + 32) | |
a6425924 KB |
677 | { |
678 | /* Floating point registers... */ | |
679 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
680 | return builtin_type_ieee_double_big; | |
681 | else | |
682 | return builtin_type_ieee_double_little; | |
683 | } | |
78fde5f8 KB |
684 | else if (reg == PS_REGNUM /* CR */) |
685 | return builtin_type_uint32; | |
686 | else if (FCRCS_REGNUM <= reg && reg <= LAST_EMBED_REGNUM) | |
687 | return builtin_type_uint32; | |
688 | else | |
689 | { | |
a6425924 KB |
690 | /* Everything else... |
691 | Return type appropriate for width of register. */ | |
692 | if (MIPS_REGSIZE == TYPE_LENGTH (builtin_type_uint64)) | |
693 | return builtin_type_uint64; | |
78fde5f8 | 694 | else |
a6425924 | 695 | return builtin_type_uint32; |
78fde5f8 KB |
696 | } |
697 | } | |
698 | ||
bcb0cc15 MS |
699 | /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */ |
700 | ||
701 | static CORE_ADDR | |
702 | mips_read_sp (void) | |
703 | { | |
e227b13c | 704 | return read_signed_register (SP_REGNUM); |
bcb0cc15 MS |
705 | } |
706 | ||
c906108c | 707 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 708 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
709 | |
710 | static int | |
711 | mips_mask_address_p (void) | |
712 | { | |
713 | switch (mask_address_var) | |
714 | { | |
7f19b9a2 | 715 | case AUTO_BOOLEAN_TRUE: |
4014092b | 716 | return 1; |
7f19b9a2 | 717 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
718 | return 0; |
719 | break; | |
7f19b9a2 | 720 | case AUTO_BOOLEAN_AUTO: |
92e1c15c | 721 | return MIPS_DEFAULT_MASK_ADDRESS_P; |
4014092b | 722 | default: |
8e65ff28 AC |
723 | internal_error (__FILE__, __LINE__, |
724 | "mips_mask_address_p: bad switch"); | |
4014092b | 725 | return -1; |
361d1df0 | 726 | } |
4014092b AC |
727 | } |
728 | ||
729 | static void | |
e9e68a56 | 730 | show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c) |
4014092b AC |
731 | { |
732 | switch (mask_address_var) | |
733 | { | |
7f19b9a2 | 734 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
735 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
736 | break; | |
7f19b9a2 | 737 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
738 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
739 | break; | |
7f19b9a2 | 740 | case AUTO_BOOLEAN_AUTO: |
4014092b AC |
741 | printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n", |
742 | mips_mask_address_p () ? "enabled" : "disabled"); | |
743 | break; | |
744 | default: | |
8e65ff28 AC |
745 | internal_error (__FILE__, __LINE__, |
746 | "show_mask_address: bad switch"); | |
4014092b | 747 | break; |
361d1df0 | 748 | } |
4014092b | 749 | } |
c906108c SS |
750 | |
751 | /* Should call_function allocate stack space for a struct return? */ | |
cb811fe7 | 752 | |
f7ab6ec6 | 753 | static int |
cb811fe7 | 754 | mips_eabi_use_struct_convention (int gcc_p, struct type *type) |
c906108c | 755 | { |
cb811fe7 MS |
756 | return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE); |
757 | } | |
758 | ||
f7ab6ec6 | 759 | static int |
cb811fe7 MS |
760 | mips_n32n64_use_struct_convention (int gcc_p, struct type *type) |
761 | { | |
b78bcb18 | 762 | return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE); |
cb811fe7 MS |
763 | } |
764 | ||
8b389c40 MS |
765 | /* Should call_function pass struct by reference? |
766 | For each architecture, structs are passed either by | |
767 | value or by reference, depending on their size. */ | |
768 | ||
769 | static int | |
770 | mips_eabi_reg_struct_has_addr (int gcc_p, struct type *type) | |
771 | { | |
772 | enum type_code typecode = TYPE_CODE (check_typedef (type)); | |
773 | int len = TYPE_LENGTH (check_typedef (type)); | |
774 | ||
775 | if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
776 | return (len > MIPS_SAVED_REGSIZE); | |
777 | ||
778 | return 0; | |
779 | } | |
780 | ||
781 | static int | |
782 | mips_n32n64_reg_struct_has_addr (int gcc_p, struct type *type) | |
783 | { | |
784 | return 0; /* Assumption: N32/N64 never passes struct by ref. */ | |
785 | } | |
786 | ||
f7ab6ec6 | 787 | static int |
8b389c40 MS |
788 | mips_o32_reg_struct_has_addr (int gcc_p, struct type *type) |
789 | { | |
790 | return 0; /* Assumption: O32/O64 never passes struct by ref. */ | |
791 | } | |
792 | ||
c906108c SS |
793 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
794 | ||
795 | static int | |
796 | pc_is_mips16 (bfd_vma memaddr) | |
797 | { | |
798 | struct minimal_symbol *sym; | |
799 | ||
800 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
95404a3e | 801 | if (is_mips16_addr (memaddr)) |
c906108c SS |
802 | return 1; |
803 | ||
804 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
805 | the high bit of the info field. Use this to decide if the function is | |
806 | MIPS16 or normal MIPS. */ | |
807 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
808 | if (sym) | |
71b8ef93 | 809 | return msymbol_is_special (sym); |
c906108c SS |
810 | else |
811 | return 0; | |
812 | } | |
813 | ||
6c997a34 AC |
814 | /* MIPS believes that the PC has a sign extended value. Perhaphs the |
815 | all registers should be sign extended for simplicity? */ | |
816 | ||
817 | static CORE_ADDR | |
39f77062 | 818 | mips_read_pc (ptid_t ptid) |
6c997a34 | 819 | { |
39f77062 | 820 | return read_signed_register_pid (PC_REGNUM, ptid); |
6c997a34 | 821 | } |
c906108c SS |
822 | |
823 | /* This returns the PC of the first inst after the prologue. If we can't | |
824 | find the prologue, then return 0. */ | |
825 | ||
826 | static CORE_ADDR | |
acdb74a0 AC |
827 | after_prologue (CORE_ADDR pc, |
828 | mips_extra_func_info_t proc_desc) | |
c906108c SS |
829 | { |
830 | struct symtab_and_line sal; | |
831 | CORE_ADDR func_addr, func_end; | |
832 | ||
479412cd DJ |
833 | /* Pass cur_frame == 0 to find_proc_desc. We should not attempt |
834 | to read the stack pointer from the current machine state, because | |
835 | the current machine state has nothing to do with the information | |
836 | we need from the proc_desc; and the process may or may not exist | |
837 | right now. */ | |
c906108c | 838 | if (!proc_desc) |
479412cd | 839 | proc_desc = find_proc_desc (pc, NULL, 0); |
c906108c SS |
840 | |
841 | if (proc_desc) | |
842 | { | |
843 | /* If function is frameless, then we need to do it the hard way. I | |
c5aa993b | 844 | strongly suspect that frameless always means prologueless... */ |
c906108c SS |
845 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM |
846 | && PROC_FRAME_OFFSET (proc_desc) == 0) | |
847 | return 0; | |
848 | } | |
849 | ||
850 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
851 | return 0; /* Unknown */ | |
852 | ||
853 | sal = find_pc_line (func_addr, 0); | |
854 | ||
855 | if (sal.end < func_end) | |
856 | return sal.end; | |
857 | ||
858 | /* The line after the prologue is after the end of the function. In this | |
859 | case, tell the caller to find the prologue the hard way. */ | |
860 | ||
861 | return 0; | |
862 | } | |
863 | ||
864 | /* Decode a MIPS32 instruction that saves a register in the stack, and | |
865 | set the appropriate bit in the general register mask or float register mask | |
866 | to indicate which register is saved. This is a helper function | |
867 | for mips_find_saved_regs. */ | |
868 | ||
869 | static void | |
acdb74a0 AC |
870 | mips32_decode_reg_save (t_inst inst, unsigned long *gen_mask, |
871 | unsigned long *float_mask) | |
c906108c SS |
872 | { |
873 | int reg; | |
874 | ||
875 | if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */ | |
876 | || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */ | |
877 | || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */ | |
878 | { | |
879 | /* It might be possible to use the instruction to | |
c5aa993b JM |
880 | find the offset, rather than the code below which |
881 | is based on things being in a certain order in the | |
882 | frame, but figuring out what the instruction's offset | |
883 | is relative to might be a little tricky. */ | |
c906108c SS |
884 | reg = (inst & 0x001f0000) >> 16; |
885 | *gen_mask |= (1 << reg); | |
886 | } | |
887 | else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */ | |
c5aa993b JM |
888 | || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */ |
889 | || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */ | |
c906108c SS |
890 | |
891 | { | |
892 | reg = ((inst & 0x001f0000) >> 16); | |
893 | *float_mask |= (1 << reg); | |
894 | } | |
895 | } | |
896 | ||
897 | /* Decode a MIPS16 instruction that saves a register in the stack, and | |
898 | set the appropriate bit in the general register or float register mask | |
899 | to indicate which register is saved. This is a helper function | |
900 | for mips_find_saved_regs. */ | |
901 | ||
902 | static void | |
acdb74a0 | 903 | mips16_decode_reg_save (t_inst inst, unsigned long *gen_mask) |
c906108c | 904 | { |
c5aa993b | 905 | if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ |
c906108c SS |
906 | { |
907 | int reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
908 | *gen_mask |= (1 << reg); | |
909 | } | |
c5aa993b | 910 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ |
c906108c SS |
911 | { |
912 | int reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
913 | *gen_mask |= (1 << reg); | |
914 | } | |
c5aa993b | 915 | else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */ |
c906108c SS |
916 | || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ |
917 | *gen_mask |= (1 << RA_REGNUM); | |
918 | } | |
919 | ||
920 | ||
921 | /* Fetch and return instruction from the specified location. If the PC | |
922 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
923 | ||
924 | static t_inst | |
acdb74a0 | 925 | mips_fetch_instruction (CORE_ADDR addr) |
c906108c SS |
926 | { |
927 | char buf[MIPS_INSTLEN]; | |
928 | int instlen; | |
929 | int status; | |
930 | ||
931 | if (pc_is_mips16 (addr)) | |
932 | { | |
933 | instlen = MIPS16_INSTLEN; | |
95404a3e | 934 | addr = unmake_mips16_addr (addr); |
c906108c SS |
935 | } |
936 | else | |
c5aa993b | 937 | instlen = MIPS_INSTLEN; |
c906108c SS |
938 | status = read_memory_nobpt (addr, buf, instlen); |
939 | if (status) | |
940 | memory_error (status, addr); | |
941 | return extract_unsigned_integer (buf, instlen); | |
942 | } | |
943 | ||
944 | ||
945 | /* These the fields of 32 bit mips instructions */ | |
e135b889 DJ |
946 | #define mips32_op(x) (x >> 26) |
947 | #define itype_op(x) (x >> 26) | |
948 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 949 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 950 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 951 | |
e135b889 DJ |
952 | #define jtype_op(x) (x >> 26) |
953 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 954 | |
e135b889 DJ |
955 | #define rtype_op(x) (x >> 26) |
956 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
957 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
958 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
959 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
960 | #define rtype_funct(x) (x & 0x3f) | |
c906108c SS |
961 | |
962 | static CORE_ADDR | |
c5aa993b JM |
963 | mips32_relative_offset (unsigned long inst) |
964 | { | |
965 | long x; | |
966 | x = itype_immediate (inst); | |
967 | if (x & 0x8000) /* sign bit set */ | |
c906108c | 968 | { |
c5aa993b | 969 | x |= 0xffff0000; /* sign extension */ |
c906108c | 970 | } |
c5aa993b JM |
971 | x = x << 2; |
972 | return x; | |
c906108c SS |
973 | } |
974 | ||
975 | /* Determine whate to set a single step breakpoint while considering | |
976 | branch prediction */ | |
5a89d8aa | 977 | static CORE_ADDR |
c5aa993b JM |
978 | mips32_next_pc (CORE_ADDR pc) |
979 | { | |
980 | unsigned long inst; | |
981 | int op; | |
982 | inst = mips_fetch_instruction (pc); | |
e135b889 | 983 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 984 | { |
e135b889 DJ |
985 | if (itype_op (inst) >> 2 == 5) |
986 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ | |
c5aa993b | 987 | { |
e135b889 | 988 | op = (itype_op (inst) & 0x03); |
c906108c SS |
989 | switch (op) |
990 | { | |
e135b889 DJ |
991 | case 0: /* BEQL */ |
992 | goto equal_branch; | |
993 | case 1: /* BNEL */ | |
994 | goto neq_branch; | |
995 | case 2: /* BLEZL */ | |
996 | goto less_branch; | |
997 | case 3: /* BGTZ */ | |
998 | goto greater_branch; | |
c5aa993b JM |
999 | default: |
1000 | pc += 4; | |
c906108c SS |
1001 | } |
1002 | } | |
e135b889 DJ |
1003 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
1004 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ | |
1005 | { | |
1006 | int tf = itype_rt (inst) & 0x01; | |
1007 | int cnum = itype_rt (inst) >> 2; | |
1008 | int fcrcs = read_signed_register (FCRCS_REGNUM); | |
1009 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); | |
1010 | ||
1011 | if (((cond >> cnum) & 0x01) == tf) | |
1012 | pc += mips32_relative_offset (inst) + 4; | |
1013 | else | |
1014 | pc += 8; | |
1015 | } | |
c5aa993b JM |
1016 | else |
1017 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
1018 | } |
1019 | else | |
c5aa993b JM |
1020 | { /* This gets way messy */ |
1021 | ||
c906108c | 1022 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 1023 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 1024 | { |
c5aa993b JM |
1025 | case 0: /* SPECIAL */ |
1026 | op = rtype_funct (inst); | |
1027 | switch (op) | |
1028 | { | |
1029 | case 8: /* JR */ | |
1030 | case 9: /* JALR */ | |
6c997a34 AC |
1031 | /* Set PC to that address */ |
1032 | pc = read_signed_register (rtype_rs (inst)); | |
c5aa993b JM |
1033 | break; |
1034 | default: | |
1035 | pc += 4; | |
1036 | } | |
1037 | ||
e135b889 | 1038 | break; /* end SPECIAL */ |
c5aa993b | 1039 | case 1: /* REGIMM */ |
c906108c | 1040 | { |
e135b889 DJ |
1041 | op = itype_rt (inst); /* branch condition */ |
1042 | switch (op) | |
c906108c | 1043 | { |
c5aa993b | 1044 | case 0: /* BLTZ */ |
e135b889 DJ |
1045 | case 2: /* BLTZL */ |
1046 | case 16: /* BLTZAL */ | |
c5aa993b | 1047 | case 18: /* BLTZALL */ |
c906108c | 1048 | less_branch: |
6c997a34 | 1049 | if (read_signed_register (itype_rs (inst)) < 0) |
c5aa993b JM |
1050 | pc += mips32_relative_offset (inst) + 4; |
1051 | else | |
1052 | pc += 8; /* after the delay slot */ | |
1053 | break; | |
e135b889 | 1054 | case 1: /* BGEZ */ |
c5aa993b JM |
1055 | case 3: /* BGEZL */ |
1056 | case 17: /* BGEZAL */ | |
1057 | case 19: /* BGEZALL */ | |
c906108c | 1058 | greater_equal_branch: |
6c997a34 | 1059 | if (read_signed_register (itype_rs (inst)) >= 0) |
c5aa993b JM |
1060 | pc += mips32_relative_offset (inst) + 4; |
1061 | else | |
1062 | pc += 8; /* after the delay slot */ | |
1063 | break; | |
e135b889 | 1064 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1065 | default: |
1066 | pc += 4; | |
c906108c SS |
1067 | } |
1068 | } | |
e135b889 | 1069 | break; /* end REGIMM */ |
c5aa993b JM |
1070 | case 2: /* J */ |
1071 | case 3: /* JAL */ | |
1072 | { | |
1073 | unsigned long reg; | |
1074 | reg = jtype_target (inst) << 2; | |
e135b889 | 1075 | /* Upper four bits get never changed... */ |
c5aa993b | 1076 | pc = reg + ((pc + 4) & 0xf0000000); |
c906108c | 1077 | } |
c5aa993b JM |
1078 | break; |
1079 | /* FIXME case JALX : */ | |
1080 | { | |
1081 | unsigned long reg; | |
1082 | reg = jtype_target (inst) << 2; | |
1083 | pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */ | |
c906108c SS |
1084 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1085 | } | |
c5aa993b | 1086 | break; /* The new PC will be alternate mode */ |
e135b889 | 1087 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1088 | equal_branch: |
6c997a34 AC |
1089 | if (read_signed_register (itype_rs (inst)) == |
1090 | read_signed_register (itype_rt (inst))) | |
c5aa993b JM |
1091 | pc += mips32_relative_offset (inst) + 4; |
1092 | else | |
1093 | pc += 8; | |
1094 | break; | |
e135b889 | 1095 | case 5: /* BNE, BNEL */ |
c5aa993b | 1096 | neq_branch: |
6c997a34 | 1097 | if (read_signed_register (itype_rs (inst)) != |
e135b889 | 1098 | read_signed_register (itype_rt (inst))) |
c5aa993b JM |
1099 | pc += mips32_relative_offset (inst) + 4; |
1100 | else | |
1101 | pc += 8; | |
1102 | break; | |
e135b889 | 1103 | case 6: /* BLEZ, BLEZL */ |
c906108c | 1104 | less_zero_branch: |
6c997a34 | 1105 | if (read_signed_register (itype_rs (inst) <= 0)) |
c5aa993b JM |
1106 | pc += mips32_relative_offset (inst) + 4; |
1107 | else | |
1108 | pc += 8; | |
1109 | break; | |
1110 | case 7: | |
e135b889 DJ |
1111 | default: |
1112 | greater_branch: /* BGTZ, BGTZL */ | |
6c997a34 | 1113 | if (read_signed_register (itype_rs (inst) > 0)) |
c5aa993b JM |
1114 | pc += mips32_relative_offset (inst) + 4; |
1115 | else | |
1116 | pc += 8; | |
1117 | break; | |
c5aa993b JM |
1118 | } /* switch */ |
1119 | } /* else */ | |
1120 | return pc; | |
1121 | } /* mips32_next_pc */ | |
c906108c SS |
1122 | |
1123 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 1124 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
1125 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
1126 | We dont want to set a single step instruction on the extend instruction | |
1127 | either. | |
c5aa993b | 1128 | */ |
c906108c SS |
1129 | |
1130 | /* Lots of mips16 instruction formats */ | |
1131 | /* Predicting jumps requires itype,ritype,i8type | |
1132 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 1133 | */ |
c906108c SS |
1134 | enum mips16_inst_fmts |
1135 | { | |
c5aa993b JM |
1136 | itype, /* 0 immediate 5,10 */ |
1137 | ritype, /* 1 5,3,8 */ | |
1138 | rrtype, /* 2 5,3,3,5 */ | |
1139 | rritype, /* 3 5,3,3,5 */ | |
1140 | rrrtype, /* 4 5,3,3,3,2 */ | |
1141 | rriatype, /* 5 5,3,3,1,4 */ | |
1142 | shifttype, /* 6 5,3,3,3,2 */ | |
1143 | i8type, /* 7 5,3,8 */ | |
1144 | i8movtype, /* 8 5,3,3,5 */ | |
1145 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1146 | i64type, /* 10 5,3,8 */ | |
1147 | ri64type, /* 11 5,3,3,5 */ | |
1148 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1149 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1150 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1151 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1152 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1153 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1154 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1155 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1156 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1157 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1158 | }; | |
12f02c2a AC |
1159 | /* I am heaping all the fields of the formats into one structure and |
1160 | then, only the fields which are involved in instruction extension */ | |
c906108c | 1161 | struct upk_mips16 |
c5aa993b | 1162 | { |
12f02c2a | 1163 | CORE_ADDR offset; |
c5aa993b JM |
1164 | unsigned int regx; /* Function in i8 type */ |
1165 | unsigned int regy; | |
1166 | }; | |
c906108c SS |
1167 | |
1168 | ||
12f02c2a AC |
1169 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
1170 | for the bits which make up the immediatate extension. */ | |
c906108c | 1171 | |
12f02c2a AC |
1172 | static CORE_ADDR |
1173 | extended_offset (unsigned int extension) | |
c906108c | 1174 | { |
12f02c2a | 1175 | CORE_ADDR value; |
c5aa993b JM |
1176 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1177 | value = value << 6; | |
1178 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
1179 | value = value << 5; | |
1180 | value |= extension & 0x01f; /* extract 4:0 */ | |
1181 | return value; | |
c906108c SS |
1182 | } |
1183 | ||
1184 | /* Only call this function if you know that this is an extendable | |
1185 | instruction, It wont malfunction, but why make excess remote memory references? | |
1186 | If the immediate operands get sign extended or somthing, do it after | |
1187 | the extension is performed. | |
c5aa993b | 1188 | */ |
c906108c SS |
1189 | /* FIXME: Every one of these cases needs to worry about sign extension |
1190 | when the offset is to be used in relative addressing */ | |
1191 | ||
1192 | ||
12f02c2a | 1193 | static unsigned int |
c5aa993b | 1194 | fetch_mips_16 (CORE_ADDR pc) |
c906108c | 1195 | { |
c5aa993b JM |
1196 | char buf[8]; |
1197 | pc &= 0xfffffffe; /* clear the low order bit */ | |
1198 | target_read_memory (pc, buf, 2); | |
1199 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
1200 | } |
1201 | ||
1202 | static void | |
c5aa993b | 1203 | unpack_mips16 (CORE_ADDR pc, |
12f02c2a AC |
1204 | unsigned int extension, |
1205 | unsigned int inst, | |
1206 | enum mips16_inst_fmts insn_format, | |
c5aa993b | 1207 | struct upk_mips16 *upk) |
c906108c | 1208 | { |
12f02c2a AC |
1209 | CORE_ADDR offset; |
1210 | int regx; | |
1211 | int regy; | |
1212 | switch (insn_format) | |
c906108c | 1213 | { |
c5aa993b | 1214 | case itype: |
c906108c | 1215 | { |
12f02c2a AC |
1216 | CORE_ADDR value; |
1217 | if (extension) | |
c5aa993b JM |
1218 | { |
1219 | value = extended_offset (extension); | |
1220 | value = value << 11; /* rom for the original value */ | |
12f02c2a | 1221 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1222 | } |
1223 | else | |
c5aa993b | 1224 | { |
12f02c2a | 1225 | value = inst & 0x7ff; |
c5aa993b | 1226 | /* FIXME : Consider sign extension */ |
c906108c | 1227 | } |
12f02c2a AC |
1228 | offset = value; |
1229 | regx = -1; | |
1230 | regy = -1; | |
c906108c | 1231 | } |
c5aa993b JM |
1232 | break; |
1233 | case ritype: | |
1234 | case i8type: | |
1235 | { /* A register identifier and an offset */ | |
c906108c SS |
1236 | /* Most of the fields are the same as I type but the |
1237 | immediate value is of a different length */ | |
12f02c2a AC |
1238 | CORE_ADDR value; |
1239 | if (extension) | |
c906108c | 1240 | { |
c5aa993b JM |
1241 | value = extended_offset (extension); |
1242 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1243 | value |= inst & 0xff; /* eleven bits from instruction */ |
1244 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1245 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1246 | { | |
1247 | value &= ~0x3fff; /* remove the sign bit */ | |
1248 | value = -value; | |
c906108c SS |
1249 | } |
1250 | } | |
c5aa993b JM |
1251 | else |
1252 | { | |
12f02c2a AC |
1253 | value = inst & 0xff; /* 8 bits */ |
1254 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1255 | /* FIXME: Do sign extension , this format needs it */ |
1256 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1257 | { | |
1258 | value &= 0xef; /* remove the sign bit */ | |
1259 | value = -value; | |
1260 | } | |
c5aa993b | 1261 | } |
12f02c2a AC |
1262 | offset = value; |
1263 | regy = -1; | |
c5aa993b | 1264 | break; |
c906108c | 1265 | } |
c5aa993b | 1266 | case jalxtype: |
c906108c | 1267 | { |
c5aa993b | 1268 | unsigned long value; |
12f02c2a AC |
1269 | unsigned int nexthalf; |
1270 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b JM |
1271 | value = value << 16; |
1272 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
1273 | value |= nexthalf; | |
12f02c2a AC |
1274 | offset = value; |
1275 | regx = -1; | |
1276 | regy = -1; | |
c5aa993b | 1277 | break; |
c906108c SS |
1278 | } |
1279 | default: | |
8e65ff28 AC |
1280 | internal_error (__FILE__, __LINE__, |
1281 | "bad switch"); | |
c906108c | 1282 | } |
12f02c2a AC |
1283 | upk->offset = offset; |
1284 | upk->regx = regx; | |
1285 | upk->regy = regy; | |
c906108c SS |
1286 | } |
1287 | ||
1288 | ||
c5aa993b JM |
1289 | static CORE_ADDR |
1290 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1291 | { |
c5aa993b | 1292 | return ((offset << 2) | ((pc + 2) & (0xf0000000))); |
c906108c SS |
1293 | } |
1294 | ||
12f02c2a AC |
1295 | static CORE_ADDR |
1296 | extended_mips16_next_pc (CORE_ADDR pc, | |
1297 | unsigned int extension, | |
1298 | unsigned int insn) | |
c906108c | 1299 | { |
12f02c2a AC |
1300 | int op = (insn >> 11); |
1301 | switch (op) | |
c906108c | 1302 | { |
12f02c2a AC |
1303 | case 2: /* Branch */ |
1304 | { | |
1305 | CORE_ADDR offset; | |
1306 | struct upk_mips16 upk; | |
1307 | unpack_mips16 (pc, extension, insn, itype, &upk); | |
1308 | offset = upk.offset; | |
1309 | if (offset & 0x800) | |
1310 | { | |
1311 | offset &= 0xeff; | |
1312 | offset = -offset; | |
1313 | } | |
1314 | pc += (offset << 1) + 2; | |
1315 | break; | |
1316 | } | |
1317 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ | |
1318 | { | |
1319 | struct upk_mips16 upk; | |
1320 | unpack_mips16 (pc, extension, insn, jalxtype, &upk); | |
1321 | pc = add_offset_16 (pc, upk.offset); | |
1322 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1323 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1324 | else | |
1325 | pc |= 0x01; | |
1326 | break; | |
1327 | } | |
1328 | case 4: /* beqz */ | |
1329 | { | |
1330 | struct upk_mips16 upk; | |
1331 | int reg; | |
1332 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1333 | reg = read_signed_register (upk.regx); | |
1334 | if (reg == 0) | |
1335 | pc += (upk.offset << 1) + 2; | |
1336 | else | |
1337 | pc += 2; | |
1338 | break; | |
1339 | } | |
1340 | case 5: /* bnez */ | |
1341 | { | |
1342 | struct upk_mips16 upk; | |
1343 | int reg; | |
1344 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1345 | reg = read_signed_register (upk.regx); | |
1346 | if (reg != 0) | |
1347 | pc += (upk.offset << 1) + 2; | |
1348 | else | |
1349 | pc += 2; | |
1350 | break; | |
1351 | } | |
1352 | case 12: /* I8 Formats btez btnez */ | |
1353 | { | |
1354 | struct upk_mips16 upk; | |
1355 | int reg; | |
1356 | unpack_mips16 (pc, extension, insn, i8type, &upk); | |
1357 | /* upk.regx contains the opcode */ | |
1358 | reg = read_signed_register (24); /* Test register is 24 */ | |
1359 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ | |
1360 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1361 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1362 | pc += (upk.offset << 1) + 2; | |
1363 | else | |
1364 | pc += 2; | |
1365 | break; | |
1366 | } | |
1367 | case 29: /* RR Formats JR, JALR, JALR-RA */ | |
1368 | { | |
1369 | struct upk_mips16 upk; | |
1370 | /* upk.fmt = rrtype; */ | |
1371 | op = insn & 0x1f; | |
1372 | if (op == 0) | |
c5aa993b | 1373 | { |
12f02c2a AC |
1374 | int reg; |
1375 | upk.regx = (insn >> 8) & 0x07; | |
1376 | upk.regy = (insn >> 5) & 0x07; | |
1377 | switch (upk.regy) | |
c5aa993b | 1378 | { |
12f02c2a AC |
1379 | case 0: |
1380 | reg = upk.regx; | |
1381 | break; | |
1382 | case 1: | |
1383 | reg = 31; | |
1384 | break; /* Function return instruction */ | |
1385 | case 2: | |
1386 | reg = upk.regx; | |
1387 | break; | |
1388 | default: | |
1389 | reg = 31; | |
1390 | break; /* BOGUS Guess */ | |
c906108c | 1391 | } |
12f02c2a | 1392 | pc = read_signed_register (reg); |
c906108c | 1393 | } |
12f02c2a | 1394 | else |
c5aa993b | 1395 | pc += 2; |
12f02c2a AC |
1396 | break; |
1397 | } | |
1398 | case 30: | |
1399 | /* This is an instruction extension. Fetch the real instruction | |
1400 | (which follows the extension) and decode things based on | |
1401 | that. */ | |
1402 | { | |
1403 | pc += 2; | |
1404 | pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc)); | |
1405 | break; | |
1406 | } | |
1407 | default: | |
1408 | { | |
1409 | pc += 2; | |
1410 | break; | |
1411 | } | |
c906108c | 1412 | } |
c5aa993b | 1413 | return pc; |
12f02c2a | 1414 | } |
c906108c | 1415 | |
5a89d8aa | 1416 | static CORE_ADDR |
12f02c2a AC |
1417 | mips16_next_pc (CORE_ADDR pc) |
1418 | { | |
1419 | unsigned int insn = fetch_mips_16 (pc); | |
1420 | return extended_mips16_next_pc (pc, 0, insn); | |
1421 | } | |
1422 | ||
1423 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1424 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1425 | It works by decoding the current instruction and predicting where a |
1426 | branch will go. This isnt hard because all the data is available. | |
1427 | The MIPS32 and MIPS16 variants are quite different */ | |
c5aa993b JM |
1428 | CORE_ADDR |
1429 | mips_next_pc (CORE_ADDR pc) | |
c906108c | 1430 | { |
c5aa993b JM |
1431 | if (pc & 0x01) |
1432 | return mips16_next_pc (pc); | |
1433 | else | |
1434 | return mips32_next_pc (pc); | |
12f02c2a | 1435 | } |
c906108c | 1436 | |
e0f7ec59 AC |
1437 | /* Set up the 'saved_regs' array. This is a data structure containing |
1438 | the addresses on the stack where each register has been saved, for | |
1439 | each stack frame. Registers that have not been saved will have | |
1440 | zero here. The stack pointer register is special: rather than the | |
1441 | address where the stack register has been saved, | |
1442 | saved_regs[SP_REGNUM] will have the actual value of the previous | |
1443 | frame's stack register. */ | |
c906108c | 1444 | |
d28e01f4 | 1445 | static void |
acdb74a0 | 1446 | mips_find_saved_regs (struct frame_info *fci) |
c906108c SS |
1447 | { |
1448 | int ireg; | |
c906108c SS |
1449 | /* r0 bit means kernel trap */ |
1450 | int kernel_trap; | |
1451 | /* What registers have been saved? Bitmasks. */ | |
1452 | unsigned long gen_mask, float_mask; | |
1453 | mips_extra_func_info_t proc_desc; | |
1454 | t_inst inst; | |
e0f7ec59 | 1455 | CORE_ADDR *saved_regs; |
c906108c | 1456 | |
e0f7ec59 AC |
1457 | if (get_frame_saved_regs (fci) != NULL) |
1458 | return; | |
1459 | saved_regs = frame_saved_regs_zalloc (fci); | |
c906108c SS |
1460 | |
1461 | /* If it is the frame for sigtramp, the saved registers are located | |
e0f7ec59 AC |
1462 | in a sigcontext structure somewhere on the stack. If the stack |
1463 | layout for sigtramp changes we might have to change these | |
1464 | constants and the companion fixup_sigtramp in mdebugread.c */ | |
c906108c | 1465 | #ifndef SIGFRAME_BASE |
e0f7ec59 AC |
1466 | /* To satisfy alignment restrictions, sigcontext is located 4 bytes |
1467 | above the sigtramp frame. */ | |
c906108c SS |
1468 | #define SIGFRAME_BASE MIPS_REGSIZE |
1469 | /* FIXME! Are these correct?? */ | |
1470 | #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE) | |
1471 | #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE) | |
1472 | #define SIGFRAME_FPREGSAVE_OFF \ | |
1473 | (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE) | |
1474 | #endif | |
1475 | #ifndef SIGFRAME_REG_SIZE | |
e0f7ec59 | 1476 | /* FIXME! Is this correct?? */ |
c906108c SS |
1477 | #define SIGFRAME_REG_SIZE MIPS_REGSIZE |
1478 | #endif | |
5a203e44 | 1479 | if ((get_frame_type (fci) == SIGTRAMP_FRAME)) |
c906108c SS |
1480 | { |
1481 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) | |
1482 | { | |
e0f7ec59 AC |
1483 | CORE_ADDR reg_position = (get_frame_base (fci) + SIGFRAME_REGSAVE_OFF |
1484 | + ireg * SIGFRAME_REG_SIZE); | |
1485 | set_reg_offset (saved_regs, ireg, reg_position); | |
c906108c SS |
1486 | } |
1487 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) | |
1488 | { | |
e0f7ec59 AC |
1489 | CORE_ADDR reg_position = (get_frame_base (fci) |
1490 | + SIGFRAME_FPREGSAVE_OFF | |
1491 | + ireg * SIGFRAME_REG_SIZE); | |
1492 | set_reg_offset (saved_regs, FP0_REGNUM + ireg, reg_position); | |
c906108c | 1493 | } |
e0f7ec59 AC |
1494 | |
1495 | set_reg_offset (saved_regs, PC_REGNUM, get_frame_base (fci) + SIGFRAME_PC_OFF); | |
1496 | /* SP_REGNUM, contains the value and not the address. */ | |
1497 | set_reg_offset (saved_regs, SP_REGNUM, get_frame_base (fci)); | |
c906108c SS |
1498 | return; |
1499 | } | |
1500 | ||
da50a4b7 | 1501 | proc_desc = get_frame_extra_info (fci)->proc_desc; |
c906108c | 1502 | if (proc_desc == NULL) |
e0f7ec59 AC |
1503 | /* I'm not sure how/whether this can happen. Normally when we |
1504 | can't find a proc_desc, we "synthesize" one using | |
1505 | heuristic_proc_desc and set the saved_regs right away. */ | |
c906108c SS |
1506 | return; |
1507 | ||
c5aa993b JM |
1508 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; |
1509 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc); | |
1510 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc); | |
c906108c | 1511 | |
e0f7ec59 AC |
1512 | if (/* In any frame other than the innermost or a frame interrupted |
1513 | by a signal, we assume that all registers have been saved. | |
1514 | This assumes that all register saves in a function happen | |
1515 | before the first function call. */ | |
11c02a10 AC |
1516 | (get_next_frame (fci) == NULL |
1517 | || (get_frame_type (get_next_frame (fci)) == SIGTRAMP_FRAME)) | |
c906108c | 1518 | |
e0f7ec59 | 1519 | /* In a dummy frame we know exactly where things are saved. */ |
c5aa993b | 1520 | && !PROC_DESC_IS_DUMMY (proc_desc) |
c906108c | 1521 | |
e0f7ec59 AC |
1522 | /* Don't bother unless we are inside a function prologue. |
1523 | Outside the prologue, we know where everything is. */ | |
c906108c | 1524 | |
50abf9e5 | 1525 | && in_prologue (get_frame_pc (fci), PROC_LOW_ADDR (proc_desc)) |
c906108c | 1526 | |
e0f7ec59 AC |
1527 | /* Not sure exactly what kernel_trap means, but if it means the |
1528 | kernel saves the registers without a prologue doing it, we | |
1529 | better not examine the prologue to see whether registers | |
1530 | have been saved yet. */ | |
c5aa993b | 1531 | && !kernel_trap) |
c906108c | 1532 | { |
e0f7ec59 AC |
1533 | /* We need to figure out whether the registers that the |
1534 | proc_desc claims are saved have been saved yet. */ | |
c906108c SS |
1535 | |
1536 | CORE_ADDR addr; | |
1537 | ||
1538 | /* Bitmasks; set if we have found a save for the register. */ | |
1539 | unsigned long gen_save_found = 0; | |
1540 | unsigned long float_save_found = 0; | |
1541 | int instlen; | |
1542 | ||
1543 | /* If the address is odd, assume this is MIPS16 code. */ | |
1544 | addr = PROC_LOW_ADDR (proc_desc); | |
1545 | instlen = pc_is_mips16 (addr) ? MIPS16_INSTLEN : MIPS_INSTLEN; | |
1546 | ||
e0f7ec59 AC |
1547 | /* Scan through this function's instructions preceding the |
1548 | current PC, and look for those that save registers. */ | |
50abf9e5 | 1549 | while (addr < get_frame_pc (fci)) |
c906108c SS |
1550 | { |
1551 | inst = mips_fetch_instruction (addr); | |
1552 | if (pc_is_mips16 (addr)) | |
1553 | mips16_decode_reg_save (inst, &gen_save_found); | |
1554 | else | |
1555 | mips32_decode_reg_save (inst, &gen_save_found, &float_save_found); | |
1556 | addr += instlen; | |
1557 | } | |
1558 | gen_mask = gen_save_found; | |
1559 | float_mask = float_save_found; | |
1560 | } | |
1561 | ||
e0f7ec59 AC |
1562 | /* Fill in the offsets for the registers which gen_mask says were |
1563 | saved. */ | |
1564 | { | |
1565 | CORE_ADDR reg_position = (get_frame_base (fci) | |
1566 | + PROC_REG_OFFSET (proc_desc)); | |
1567 | for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1) | |
1568 | if (gen_mask & 0x80000000) | |
1569 | { | |
1570 | set_reg_offset (saved_regs, ireg, reg_position); | |
1571 | reg_position -= MIPS_SAVED_REGSIZE; | |
1572 | } | |
1573 | } | |
c906108c | 1574 | |
e0f7ec59 AC |
1575 | /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse |
1576 | order of that normally used by gcc. Therefore, we have to fetch | |
1577 | the first instruction of the function, and if it's an entry | |
1578 | instruction that saves $s0 or $s1, correct their saved addresses. */ | |
c906108c SS |
1579 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) |
1580 | { | |
1581 | inst = mips_fetch_instruction (PROC_LOW_ADDR (proc_desc)); | |
e0f7ec59 AC |
1582 | if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) |
1583 | /* entry */ | |
c906108c SS |
1584 | { |
1585 | int reg; | |
1586 | int sreg_count = (inst >> 6) & 3; | |
c5aa993b | 1587 | |
c906108c | 1588 | /* Check if the ra register was pushed on the stack. */ |
e0f7ec59 AC |
1589 | CORE_ADDR reg_position = (get_frame_base (fci) |
1590 | + PROC_REG_OFFSET (proc_desc)); | |
c906108c | 1591 | if (inst & 0x20) |
7a292a7a | 1592 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c | 1593 | |
e0f7ec59 AC |
1594 | /* Check if the s0 and s1 registers were pushed on the |
1595 | stack. */ | |
c5aa993b | 1596 | for (reg = 16; reg < sreg_count + 16; reg++) |
c906108c | 1597 | { |
e0f7ec59 | 1598 | set_reg_offset (saved_regs, reg, reg_position); |
7a292a7a | 1599 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1600 | } |
1601 | } | |
1602 | } | |
1603 | ||
e0f7ec59 AC |
1604 | /* Fill in the offsets for the registers which float_mask says were |
1605 | saved. */ | |
1606 | { | |
1607 | CORE_ADDR reg_position = (get_frame_base (fci) | |
1608 | + PROC_FREG_OFFSET (proc_desc)); | |
6acdf5c7 | 1609 | |
e0f7ec59 AC |
1610 | /* Apparently, the freg_offset gives the offset to the first 64 |
1611 | bit saved. | |
6acdf5c7 | 1612 | |
e0f7ec59 AC |
1613 | When the ABI specifies 64 bit saved registers, the FREG_OFFSET |
1614 | designates the first saved 64 bit register. | |
6acdf5c7 | 1615 | |
e0f7ec59 AC |
1616 | When the ABI specifies 32 bit saved registers, the ``64 bit |
1617 | saved DOUBLE'' consists of two adjacent 32 bit registers, Hence | |
1618 | FREG_OFFSET, designates the address of the lower register of | |
1619 | the register pair. Adjust the offset so that it designates the | |
1620 | upper register of the pair -- i.e., the address of the first | |
1621 | saved 32 bit register. */ | |
c906108c | 1622 | |
e0f7ec59 AC |
1623 | if (MIPS_SAVED_REGSIZE == 4) |
1624 | reg_position += MIPS_SAVED_REGSIZE; | |
c906108c | 1625 | |
e0f7ec59 AC |
1626 | /* Fill in the offsets for the float registers which float_mask |
1627 | says were saved. */ | |
1628 | for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1) | |
1629 | if (float_mask & 0x80000000) | |
1630 | { | |
1631 | set_reg_offset (saved_regs, FP0_REGNUM + ireg, reg_position); | |
1632 | reg_position -= MIPS_SAVED_REGSIZE; | |
1633 | } | |
c906108c | 1634 | |
e0f7ec59 AC |
1635 | set_reg_offset (saved_regs, PC_REGNUM, saved_regs[RA_REGNUM]); |
1636 | } | |
d28e01f4 | 1637 | |
e0f7ec59 AC |
1638 | /* SP_REGNUM, contains the value and not the address. */ |
1639 | set_reg_offset (saved_regs, SP_REGNUM, get_frame_base (fci)); | |
d28e01f4 KB |
1640 | } |
1641 | ||
c906108c | 1642 | static CORE_ADDR |
acdb74a0 | 1643 | read_next_frame_reg (struct frame_info *fi, int regno) |
c906108c | 1644 | { |
64159455 AC |
1645 | int optimized; |
1646 | CORE_ADDR addr; | |
1647 | int realnum; | |
1648 | enum lval_type lval; | |
d9d9c31f | 1649 | char raw_buffer[MAX_REGISTER_SIZE]; |
f796e4be KB |
1650 | |
1651 | if (fi == NULL) | |
c906108c | 1652 | { |
f796e4be KB |
1653 | regcache_cooked_read (current_regcache, regno, raw_buffer); |
1654 | } | |
1655 | else | |
1656 | { | |
1657 | frame_register_unwind (fi, regno, &optimized, &lval, &addr, &realnum, | |
1658 | raw_buffer); | |
1659 | /* FIXME: cagney/2002-09-13: This is just soooo bad. The MIPS | |
1660 | should have a pseudo register range that correspons to the ABI's, | |
1661 | rather than the ISA's, view of registers. These registers would | |
1662 | then implicitly describe their size and hence could be used | |
1663 | without the below munging. */ | |
1664 | if (lval == lval_memory) | |
c906108c | 1665 | { |
f796e4be KB |
1666 | if (regno < 32) |
1667 | { | |
1668 | /* Only MIPS_SAVED_REGSIZE bytes of GP registers are | |
1669 | saved. */ | |
1670 | return read_memory_integer (addr, MIPS_SAVED_REGSIZE); | |
1671 | } | |
c906108c SS |
1672 | } |
1673 | } | |
64159455 AC |
1674 | |
1675 | return extract_signed_integer (raw_buffer, REGISTER_VIRTUAL_SIZE (regno)); | |
c906108c SS |
1676 | } |
1677 | ||
1678 | /* mips_addr_bits_remove - remove useless address bits */ | |
1679 | ||
875e1767 | 1680 | static CORE_ADDR |
acdb74a0 | 1681 | mips_addr_bits_remove (CORE_ADDR addr) |
c906108c | 1682 | { |
5213ab06 AC |
1683 | if (GDB_TARGET_IS_MIPS64) |
1684 | { | |
4014092b | 1685 | if (mips_mask_address_p () && (addr >> 32 == (CORE_ADDR) 0xffffffff)) |
5213ab06 AC |
1686 | { |
1687 | /* This hack is a work-around for existing boards using | |
1688 | PMON, the simulator, and any other 64-bit targets that | |
1689 | doesn't have true 64-bit addressing. On these targets, | |
1690 | the upper 32 bits of addresses are ignored by the | |
1691 | hardware. Thus, the PC or SP are likely to have been | |
1692 | sign extended to all 1s by instruction sequences that | |
1693 | load 32-bit addresses. For example, a typical piece of | |
4014092b AC |
1694 | code that loads an address is this: |
1695 | lui $r2, <upper 16 bits> | |
1696 | ori $r2, <lower 16 bits> | |
1697 | But the lui sign-extends the value such that the upper 32 | |
1698 | bits may be all 1s. The workaround is simply to mask off | |
1699 | these bits. In the future, gcc may be changed to support | |
1700 | true 64-bit addressing, and this masking will have to be | |
1701 | disabled. */ | |
5213ab06 AC |
1702 | addr &= (CORE_ADDR) 0xffffffff; |
1703 | } | |
1704 | } | |
4014092b | 1705 | else if (mips_mask_address_p ()) |
5213ab06 | 1706 | { |
4014092b AC |
1707 | /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be |
1708 | masking off bits, instead, the actual target should be asking | |
1709 | for the address to be converted to a valid pointer. */ | |
5213ab06 AC |
1710 | /* Even when GDB is configured for some 32-bit targets |
1711 | (e.g. mips-elf), BFD is configured to handle 64-bit targets, | |
1712 | so CORE_ADDR is 64 bits. So we still have to mask off | |
1713 | useless bits from addresses. */ | |
c5aa993b | 1714 | addr &= (CORE_ADDR) 0xffffffff; |
c906108c | 1715 | } |
c906108c SS |
1716 | return addr; |
1717 | } | |
1718 | ||
9022177c DJ |
1719 | /* mips_software_single_step() is called just before we want to resume |
1720 | the inferior, if we want to single-step it but there is no hardware | |
75c9abc6 | 1721 | or kernel single-step support (MIPS on GNU/Linux for example). We find |
9022177c DJ |
1722 | the target of the coming instruction and breakpoint it. |
1723 | ||
1724 | single_step is also called just after the inferior stops. If we had | |
1725 | set up a simulated single-step, we undo our damage. */ | |
1726 | ||
1727 | void | |
1728 | mips_software_single_step (enum target_signal sig, int insert_breakpoints_p) | |
1729 | { | |
1730 | static CORE_ADDR next_pc; | |
1731 | typedef char binsn_quantum[BREAKPOINT_MAX]; | |
1732 | static binsn_quantum break_mem; | |
1733 | CORE_ADDR pc; | |
1734 | ||
1735 | if (insert_breakpoints_p) | |
1736 | { | |
1737 | pc = read_register (PC_REGNUM); | |
1738 | next_pc = mips_next_pc (pc); | |
1739 | ||
1740 | target_insert_breakpoint (next_pc, break_mem); | |
1741 | } | |
1742 | else | |
1743 | target_remove_breakpoint (next_pc, break_mem); | |
1744 | } | |
1745 | ||
97f46953 | 1746 | static CORE_ADDR |
acdb74a0 | 1747 | mips_init_frame_pc_first (int fromleaf, struct frame_info *prev) |
c906108c SS |
1748 | { |
1749 | CORE_ADDR pc, tmp; | |
1750 | ||
11c02a10 | 1751 | pc = ((fromleaf) |
6913c89a | 1752 | ? DEPRECATED_SAVED_PC_AFTER_CALL (get_next_frame (prev)) |
11c02a10 | 1753 | : get_next_frame (prev) |
8bedc050 | 1754 | ? DEPRECATED_FRAME_SAVED_PC (get_next_frame (prev)) |
11c02a10 | 1755 | : read_pc ()); |
5a89d8aa | 1756 | tmp = SKIP_TRAMPOLINE_CODE (pc); |
97f46953 | 1757 | return tmp ? tmp : pc; |
c906108c SS |
1758 | } |
1759 | ||
1760 | ||
f7ab6ec6 | 1761 | static CORE_ADDR |
acdb74a0 | 1762 | mips_frame_saved_pc (struct frame_info *frame) |
c906108c SS |
1763 | { |
1764 | CORE_ADDR saved_pc; | |
da50a4b7 | 1765 | mips_extra_func_info_t proc_desc = get_frame_extra_info (frame)->proc_desc; |
c906108c SS |
1766 | /* We have to get the saved pc from the sigcontext |
1767 | if it is a signal handler frame. */ | |
5a203e44 | 1768 | int pcreg = (get_frame_type (frame) == SIGTRAMP_FRAME) ? PC_REGNUM |
c5aa993b | 1769 | : (proc_desc ? PROC_PC_REG (proc_desc) : RA_REGNUM); |
c906108c | 1770 | |
50abf9e5 | 1771 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0)) |
cedea778 AC |
1772 | { |
1773 | LONGEST tmp; | |
1774 | frame_unwind_signed_register (frame, PC_REGNUM, &tmp); | |
1775 | saved_pc = tmp; | |
1776 | } | |
1777 | else if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) | |
1e2330ba | 1778 | saved_pc = read_memory_integer (get_frame_base (frame) - MIPS_SAVED_REGSIZE, MIPS_SAVED_REGSIZE); |
c906108c | 1779 | else |
7a292a7a | 1780 | saved_pc = read_next_frame_reg (frame, pcreg); |
c906108c SS |
1781 | |
1782 | return ADDR_BITS_REMOVE (saved_pc); | |
1783 | } | |
1784 | ||
1785 | static struct mips_extra_func_info temp_proc_desc; | |
fe29b929 KB |
1786 | |
1787 | /* This hack will go away once the get_prev_frame() code has been | |
1788 | modified to set the frame's type first. That is BEFORE init extra | |
1789 | frame info et.al. is called. This is because it will become | |
1790 | possible to skip the init extra info call for sigtramp and dummy | |
1791 | frames. */ | |
1792 | static CORE_ADDR *temp_saved_regs; | |
c906108c | 1793 | |
e0f7ec59 AC |
1794 | /* Set a register's saved stack address in temp_saved_regs. If an |
1795 | address has already been set for this register, do nothing; this | |
1796 | way we will only recognize the first save of a given register in a | |
1797 | function prologue. */ | |
c906108c SS |
1798 | |
1799 | static void | |
e0f7ec59 | 1800 | set_reg_offset (CORE_ADDR *saved_regs, int regno, CORE_ADDR offset) |
c906108c | 1801 | { |
e0f7ec59 AC |
1802 | if (saved_regs[regno] == 0) |
1803 | saved_regs[regno] = offset; | |
c906108c SS |
1804 | } |
1805 | ||
1806 | ||
1807 | /* Test whether the PC points to the return instruction at the | |
1808 | end of a function. */ | |
1809 | ||
c5aa993b | 1810 | static int |
acdb74a0 | 1811 | mips_about_to_return (CORE_ADDR pc) |
c906108c SS |
1812 | { |
1813 | if (pc_is_mips16 (pc)) | |
1814 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler | |
1815 | generates a "jr $ra"; other times it generates code to load | |
1816 | the return address from the stack to an accessible register (such | |
1817 | as $a3), then a "jr" using that register. This second case | |
1818 | is almost impossible to distinguish from an indirect jump | |
1819 | used for switch statements, so we don't even try. */ | |
1820 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
1821 | else | |
1822 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
1823 | } | |
1824 | ||
1825 | ||
1826 | /* This fencepost looks highly suspicious to me. Removing it also | |
1827 | seems suspicious as it could affect remote debugging across serial | |
1828 | lines. */ | |
1829 | ||
1830 | static CORE_ADDR | |
acdb74a0 | 1831 | heuristic_proc_start (CORE_ADDR pc) |
c906108c | 1832 | { |
c5aa993b JM |
1833 | CORE_ADDR start_pc; |
1834 | CORE_ADDR fence; | |
1835 | int instlen; | |
1836 | int seen_adjsp = 0; | |
c906108c | 1837 | |
c5aa993b JM |
1838 | pc = ADDR_BITS_REMOVE (pc); |
1839 | start_pc = pc; | |
1840 | fence = start_pc - heuristic_fence_post; | |
1841 | if (start_pc == 0) | |
1842 | return 0; | |
c906108c | 1843 | |
c5aa993b JM |
1844 | if (heuristic_fence_post == UINT_MAX |
1845 | || fence < VM_MIN_ADDRESS) | |
1846 | fence = VM_MIN_ADDRESS; | |
c906108c | 1847 | |
c5aa993b | 1848 | instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN; |
c906108c | 1849 | |
c5aa993b JM |
1850 | /* search back for previous return */ |
1851 | for (start_pc -= instlen;; start_pc -= instlen) | |
1852 | if (start_pc < fence) | |
1853 | { | |
1854 | /* It's not clear to me why we reach this point when | |
c0236d92 | 1855 | stop_soon, but with this test, at least we |
c5aa993b JM |
1856 | don't print out warnings for every child forked (eg, on |
1857 | decstation). 22apr93 rich@cygnus.com. */ | |
c0236d92 | 1858 | if (stop_soon == NO_STOP_QUIETLY) |
c906108c | 1859 | { |
c5aa993b JM |
1860 | static int blurb_printed = 0; |
1861 | ||
1862 | warning ("Warning: GDB can't find the start of the function at 0x%s.", | |
1863 | paddr_nz (pc)); | |
1864 | ||
1865 | if (!blurb_printed) | |
c906108c | 1866 | { |
c5aa993b JM |
1867 | /* This actually happens frequently in embedded |
1868 | development, when you first connect to a board | |
1869 | and your stack pointer and pc are nowhere in | |
1870 | particular. This message needs to give people | |
1871 | in that situation enough information to | |
1872 | determine that it's no big deal. */ | |
1873 | printf_filtered ("\n\ | |
cd0fc7c3 SS |
1874 | GDB is unable to find the start of the function at 0x%s\n\ |
1875 | and thus can't determine the size of that function's stack frame.\n\ | |
1876 | This means that GDB may be unable to access that stack frame, or\n\ | |
1877 | the frames below it.\n\ | |
1878 | This problem is most likely caused by an invalid program counter or\n\ | |
1879 | stack pointer.\n\ | |
1880 | However, if you think GDB should simply search farther back\n\ | |
1881 | from 0x%s for code which looks like the beginning of a\n\ | |
1882 | function, you can increase the range of the search using the `set\n\ | |
1883 | heuristic-fence-post' command.\n", | |
c5aa993b JM |
1884 | paddr_nz (pc), paddr_nz (pc)); |
1885 | blurb_printed = 1; | |
c906108c | 1886 | } |
c906108c SS |
1887 | } |
1888 | ||
c5aa993b JM |
1889 | return 0; |
1890 | } | |
1891 | else if (pc_is_mips16 (start_pc)) | |
1892 | { | |
1893 | unsigned short inst; | |
1894 | ||
1895 | /* On MIPS16, any one of the following is likely to be the | |
1896 | start of a function: | |
1897 | entry | |
1898 | addiu sp,-n | |
1899 | daddiu sp,-n | |
1900 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
1901 | inst = mips_fetch_instruction (start_pc); | |
1902 | if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
1903 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
1904 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
1905 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
1906 | break; | |
1907 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
1908 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1909 | seen_adjsp = 1; | |
1910 | else | |
1911 | seen_adjsp = 0; | |
1912 | } | |
1913 | else if (mips_about_to_return (start_pc)) | |
1914 | { | |
1915 | start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */ | |
1916 | break; | |
1917 | } | |
1918 | ||
c5aa993b | 1919 | return start_pc; |
c906108c SS |
1920 | } |
1921 | ||
1922 | /* Fetch the immediate value from a MIPS16 instruction. | |
1923 | If the previous instruction was an EXTEND, use it to extend | |
1924 | the upper bits of the immediate value. This is a helper function | |
1925 | for mips16_heuristic_proc_desc. */ | |
1926 | ||
1927 | static int | |
acdb74a0 AC |
1928 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ |
1929 | unsigned short inst, /* current instruction */ | |
1930 | int nbits, /* number of bits in imm field */ | |
1931 | int scale, /* scale factor to be applied to imm */ | |
1932 | int is_signed) /* is the imm field signed? */ | |
c906108c SS |
1933 | { |
1934 | int offset; | |
1935 | ||
1936 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ | |
1937 | { | |
1938 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
c5aa993b | 1939 | if (offset & 0x8000) /* check for negative extend */ |
c906108c SS |
1940 | offset = 0 - (0x10000 - (offset & 0xffff)); |
1941 | return offset | (inst & 0x1f); | |
1942 | } | |
1943 | else | |
1944 | { | |
1945 | int max_imm = 1 << nbits; | |
1946 | int mask = max_imm - 1; | |
1947 | int sign_bit = max_imm >> 1; | |
1948 | ||
1949 | offset = inst & mask; | |
1950 | if (is_signed && (offset & sign_bit)) | |
1951 | offset = 0 - (max_imm - offset); | |
1952 | return offset * scale; | |
1953 | } | |
1954 | } | |
1955 | ||
1956 | ||
1957 | /* Fill in values in temp_proc_desc based on the MIPS16 instruction | |
1958 | stream from start_pc to limit_pc. */ | |
1959 | ||
1960 | static void | |
acdb74a0 AC |
1961 | mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
1962 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
1963 | { |
1964 | CORE_ADDR cur_pc; | |
1965 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
1966 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
1967 | unsigned inst = 0; /* current instruction */ | |
1968 | unsigned entry_inst = 0; /* the entry instruction */ | |
1969 | int reg, offset; | |
1970 | ||
c5aa993b JM |
1971 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */ |
1972 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ | |
c906108c SS |
1973 | |
1974 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN) | |
1975 | { | |
1976 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1977 | the immediate offset extension from it in mips16_get_imm. */ | |
1978 | prev_inst = inst; | |
1979 | ||
1980 | /* Fetch and decode the instruction. */ | |
1981 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
c5aa993b | 1982 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
c906108c SS |
1983 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ |
1984 | { | |
1985 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
c5aa993b JM |
1986 | if (offset < 0) /* negative stack adjustment? */ |
1987 | PROC_FRAME_OFFSET (&temp_proc_desc) -= offset; | |
c906108c SS |
1988 | else |
1989 | /* Exit loop if a positive stack adjustment is found, which | |
1990 | usually means that the stack cleanup code in the function | |
1991 | epilogue is reached. */ | |
1992 | break; | |
1993 | } | |
1994 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
1995 | { | |
1996 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1997 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
c5aa993b | 1998 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
e0f7ec59 | 1999 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c906108c SS |
2000 | } |
2001 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
2002 | { | |
2003 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
2004 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2005 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
e0f7ec59 | 2006 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c906108c SS |
2007 | } |
2008 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
2009 | { | |
2010 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
c5aa993b | 2011 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
e0f7ec59 | 2012 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
c906108c SS |
2013 | } |
2014 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
2015 | { | |
2016 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
c5aa993b | 2017 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
e0f7ec59 | 2018 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
c906108c | 2019 | } |
c5aa993b | 2020 | else if (inst == 0x673d) /* move $s1, $sp */ |
c906108c SS |
2021 | { |
2022 | frame_addr = sp; | |
2023 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
2024 | } | |
2025 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
2026 | { | |
2027 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2028 | frame_addr = sp + offset; | |
2029 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
2030 | PROC_FRAME_ADJUST (&temp_proc_desc) = offset; | |
2031 | } | |
2032 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
2033 | { | |
2034 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
2035 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2036 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2037 | set_reg_offset (temp_saved_regs, reg, frame_addr + offset); |
c906108c SS |
2038 | } |
2039 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
2040 | { | |
2041 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
2042 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2043 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2044 | set_reg_offset (temp_saved_regs, reg, frame_addr + offset); |
c906108c | 2045 | } |
c5aa993b JM |
2046 | else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
2047 | entry_inst = inst; /* save for later processing */ | |
c906108c | 2048 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
c5aa993b | 2049 | cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */ |
c906108c SS |
2050 | } |
2051 | ||
c5aa993b JM |
2052 | /* The entry instruction is typically the first instruction in a function, |
2053 | and it stores registers at offsets relative to the value of the old SP | |
2054 | (before the prologue). But the value of the sp parameter to this | |
2055 | function is the new SP (after the prologue has been executed). So we | |
2056 | can't calculate those offsets until we've seen the entire prologue, | |
2057 | and can calculate what the old SP must have been. */ | |
2058 | if (entry_inst != 0) | |
2059 | { | |
2060 | int areg_count = (entry_inst >> 8) & 7; | |
2061 | int sreg_count = (entry_inst >> 6) & 3; | |
c906108c | 2062 | |
c5aa993b JM |
2063 | /* The entry instruction always subtracts 32 from the SP. */ |
2064 | PROC_FRAME_OFFSET (&temp_proc_desc) += 32; | |
c906108c | 2065 | |
c5aa993b JM |
2066 | /* Now we can calculate what the SP must have been at the |
2067 | start of the function prologue. */ | |
2068 | sp += PROC_FRAME_OFFSET (&temp_proc_desc); | |
c906108c | 2069 | |
c5aa993b JM |
2070 | /* Check if a0-a3 were saved in the caller's argument save area. */ |
2071 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
2072 | { | |
2073 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
e0f7ec59 | 2074 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c5aa993b JM |
2075 | offset += MIPS_SAVED_REGSIZE; |
2076 | } | |
c906108c | 2077 | |
c5aa993b JM |
2078 | /* Check if the ra register was pushed on the stack. */ |
2079 | offset = -4; | |
2080 | if (entry_inst & 0x20) | |
2081 | { | |
2082 | PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM; | |
e0f7ec59 | 2083 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
c5aa993b JM |
2084 | offset -= MIPS_SAVED_REGSIZE; |
2085 | } | |
c906108c | 2086 | |
c5aa993b JM |
2087 | /* Check if the s0 and s1 registers were pushed on the stack. */ |
2088 | for (reg = 16; reg < sreg_count + 16; reg++) | |
2089 | { | |
2090 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
e0f7ec59 | 2091 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c5aa993b JM |
2092 | offset -= MIPS_SAVED_REGSIZE; |
2093 | } | |
2094 | } | |
c906108c SS |
2095 | } |
2096 | ||
2097 | static void | |
fba45db2 KB |
2098 | mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
2099 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
2100 | { |
2101 | CORE_ADDR cur_pc; | |
c5aa993b | 2102 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ |
c906108c | 2103 | restart: |
fe29b929 | 2104 | temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); |
cce74817 | 2105 | memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c5aa993b | 2106 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; |
c906108c SS |
2107 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ |
2108 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN) | |
2109 | { | |
2110 | unsigned long inst, high_word, low_word; | |
2111 | int reg; | |
2112 | ||
2113 | /* Fetch the instruction. */ | |
2114 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
2115 | ||
2116 | /* Save some code by pre-extracting some useful fields. */ | |
2117 | high_word = (inst >> 16) & 0xffff; | |
2118 | low_word = inst & 0xffff; | |
2119 | reg = high_word & 0x1f; | |
2120 | ||
c5aa993b | 2121 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
c906108c SS |
2122 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
2123 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
2124 | { | |
2125 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
c5aa993b | 2126 | PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word; |
c906108c SS |
2127 | else |
2128 | /* Exit loop if a positive stack adjustment is found, which | |
2129 | usually means that the stack cleanup code in the function | |
2130 | epilogue is reached. */ | |
2131 | break; | |
2132 | } | |
2133 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
2134 | { | |
c5aa993b | 2135 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2136 | set_reg_offset (temp_saved_regs, reg, sp + low_word); |
c906108c SS |
2137 | } |
2138 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
2139 | { | |
2140 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra, | |
2141 | but the register size used is only 32 bits. Make the address | |
2142 | for the saved register point to the lower 32 bits. */ | |
c5aa993b | 2143 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2144 | set_reg_offset (temp_saved_regs, reg, sp + low_word + 8 - MIPS_REGSIZE); |
c906108c | 2145 | } |
c5aa993b | 2146 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ |
c906108c SS |
2147 | { |
2148 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
c5aa993b JM |
2149 | if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc)) |
2150 | frame_addr = sp + low_word; | |
c906108c SS |
2151 | else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) |
2152 | { | |
2153 | unsigned alloca_adjust; | |
2154 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
c5aa993b JM |
2155 | frame_addr = read_next_frame_reg (next_frame, 30); |
2156 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); | |
c906108c SS |
2157 | if (alloca_adjust > 0) |
2158 | { | |
2159 | /* FP > SP + frame_size. This may be because | |
2160 | * of an alloca or somethings similar. | |
2161 | * Fix sp to "pre-alloca" value, and try again. | |
2162 | */ | |
2163 | sp += alloca_adjust; | |
2164 | goto restart; | |
2165 | } | |
2166 | } | |
2167 | } | |
c5aa993b JM |
2168 | /* move $30,$sp. With different versions of gas this will be either |
2169 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
2170 | Accept any one of these. */ | |
c906108c SS |
2171 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) |
2172 | { | |
2173 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
2174 | if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) | |
2175 | { | |
2176 | unsigned alloca_adjust; | |
2177 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
c5aa993b JM |
2178 | frame_addr = read_next_frame_reg (next_frame, 30); |
2179 | alloca_adjust = (unsigned) (frame_addr - sp); | |
c906108c SS |
2180 | if (alloca_adjust > 0) |
2181 | { | |
2182 | /* FP > SP + frame_size. This may be because | |
2183 | * of an alloca or somethings similar. | |
2184 | * Fix sp to "pre-alloca" value, and try again. | |
2185 | */ | |
2186 | sp += alloca_adjust; | |
2187 | goto restart; | |
2188 | } | |
2189 | } | |
2190 | } | |
c5aa993b | 2191 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ |
c906108c | 2192 | { |
c5aa993b | 2193 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2194 | set_reg_offset (temp_saved_regs, reg, frame_addr + low_word); |
c906108c SS |
2195 | } |
2196 | } | |
2197 | } | |
2198 | ||
2199 | static mips_extra_func_info_t | |
acdb74a0 | 2200 | heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
479412cd | 2201 | struct frame_info *next_frame, int cur_frame) |
c906108c | 2202 | { |
479412cd DJ |
2203 | CORE_ADDR sp; |
2204 | ||
2205 | if (cur_frame) | |
2206 | sp = read_next_frame_reg (next_frame, SP_REGNUM); | |
2207 | else | |
2208 | sp = 0; | |
c906108c | 2209 | |
c5aa993b JM |
2210 | if (start_pc == 0) |
2211 | return NULL; | |
2212 | memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc)); | |
fe29b929 | 2213 | temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); |
3758ac48 | 2214 | memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
2215 | PROC_LOW_ADDR (&temp_proc_desc) = start_pc; |
2216 | PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM; | |
2217 | PROC_PC_REG (&temp_proc_desc) = RA_REGNUM; | |
2218 | ||
2219 | if (start_pc + 200 < limit_pc) | |
2220 | limit_pc = start_pc + 200; | |
2221 | if (pc_is_mips16 (start_pc)) | |
2222 | mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
2223 | else | |
2224 | mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
2225 | return &temp_proc_desc; | |
2226 | } | |
2227 | ||
6c0d6680 DJ |
2228 | struct mips_objfile_private |
2229 | { | |
2230 | bfd_size_type size; | |
2231 | char *contents; | |
2232 | }; | |
2233 | ||
2234 | /* Global used to communicate between non_heuristic_proc_desc and | |
2235 | compare_pdr_entries within qsort (). */ | |
2236 | static bfd *the_bfd; | |
2237 | ||
2238 | static int | |
2239 | compare_pdr_entries (const void *a, const void *b) | |
2240 | { | |
2241 | CORE_ADDR lhs = bfd_get_32 (the_bfd, (bfd_byte *) a); | |
2242 | CORE_ADDR rhs = bfd_get_32 (the_bfd, (bfd_byte *) b); | |
2243 | ||
2244 | if (lhs < rhs) | |
2245 | return -1; | |
2246 | else if (lhs == rhs) | |
2247 | return 0; | |
2248 | else | |
2249 | return 1; | |
2250 | } | |
2251 | ||
c906108c | 2252 | static mips_extra_func_info_t |
acdb74a0 | 2253 | non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr) |
c906108c SS |
2254 | { |
2255 | CORE_ADDR startaddr; | |
2256 | mips_extra_func_info_t proc_desc; | |
c5aa993b | 2257 | struct block *b = block_for_pc (pc); |
c906108c | 2258 | struct symbol *sym; |
6c0d6680 DJ |
2259 | struct obj_section *sec; |
2260 | struct mips_objfile_private *priv; | |
2261 | ||
ae45cd16 | 2262 | if (DEPRECATED_PC_IN_CALL_DUMMY (pc, 0, 0)) |
6c0d6680 | 2263 | return NULL; |
c906108c SS |
2264 | |
2265 | find_pc_partial_function (pc, NULL, &startaddr, NULL); | |
2266 | if (addrptr) | |
2267 | *addrptr = startaddr; | |
6c0d6680 DJ |
2268 | |
2269 | priv = NULL; | |
2270 | ||
2271 | sec = find_pc_section (pc); | |
2272 | if (sec != NULL) | |
c906108c | 2273 | { |
6c0d6680 DJ |
2274 | priv = (struct mips_objfile_private *) sec->objfile->obj_private; |
2275 | ||
2276 | /* Search the ".pdr" section generated by GAS. This includes most of | |
2277 | the information normally found in ECOFF PDRs. */ | |
2278 | ||
2279 | the_bfd = sec->objfile->obfd; | |
2280 | if (priv == NULL | |
2281 | && (the_bfd->format == bfd_object | |
2282 | && bfd_get_flavour (the_bfd) == bfd_target_elf_flavour | |
2283 | && elf_elfheader (the_bfd)->e_ident[EI_CLASS] == ELFCLASS64)) | |
2284 | { | |
2285 | /* Right now GAS only outputs the address as a four-byte sequence. | |
2286 | This means that we should not bother with this method on 64-bit | |
2287 | targets (until that is fixed). */ | |
2288 | ||
2289 | priv = obstack_alloc (& sec->objfile->psymbol_obstack, | |
2290 | sizeof (struct mips_objfile_private)); | |
2291 | priv->size = 0; | |
2292 | sec->objfile->obj_private = priv; | |
2293 | } | |
2294 | else if (priv == NULL) | |
2295 | { | |
2296 | asection *bfdsec; | |
2297 | ||
2298 | priv = obstack_alloc (& sec->objfile->psymbol_obstack, | |
2299 | sizeof (struct mips_objfile_private)); | |
2300 | ||
2301 | bfdsec = bfd_get_section_by_name (sec->objfile->obfd, ".pdr"); | |
2302 | if (bfdsec != NULL) | |
2303 | { | |
2304 | priv->size = bfd_section_size (sec->objfile->obfd, bfdsec); | |
2305 | priv->contents = obstack_alloc (& sec->objfile->psymbol_obstack, | |
2306 | priv->size); | |
2307 | bfd_get_section_contents (sec->objfile->obfd, bfdsec, | |
2308 | priv->contents, 0, priv->size); | |
2309 | ||
2310 | /* In general, the .pdr section is sorted. However, in the | |
2311 | presence of multiple code sections (and other corner cases) | |
2312 | it can become unsorted. Sort it so that we can use a faster | |
2313 | binary search. */ | |
2314 | qsort (priv->contents, priv->size / 32, 32, compare_pdr_entries); | |
2315 | } | |
2316 | else | |
2317 | priv->size = 0; | |
2318 | ||
2319 | sec->objfile->obj_private = priv; | |
2320 | } | |
2321 | the_bfd = NULL; | |
2322 | ||
2323 | if (priv->size != 0) | |
2324 | { | |
2325 | int low, mid, high; | |
2326 | char *ptr; | |
2327 | ||
2328 | low = 0; | |
2329 | high = priv->size / 32; | |
2330 | ||
2331 | do | |
2332 | { | |
2333 | CORE_ADDR pdr_pc; | |
2334 | ||
2335 | mid = (low + high) / 2; | |
2336 | ||
2337 | ptr = priv->contents + mid * 32; | |
2338 | pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr); | |
2339 | pdr_pc += ANOFFSET (sec->objfile->section_offsets, | |
2340 | SECT_OFF_TEXT (sec->objfile)); | |
2341 | if (pdr_pc == startaddr) | |
2342 | break; | |
2343 | if (pdr_pc > startaddr) | |
2344 | high = mid; | |
2345 | else | |
2346 | low = mid + 1; | |
2347 | } | |
2348 | while (low != high); | |
2349 | ||
2350 | if (low != high) | |
2351 | { | |
2352 | struct symbol *sym = find_pc_function (pc); | |
2353 | ||
2354 | /* Fill in what we need of the proc_desc. */ | |
2355 | proc_desc = (mips_extra_func_info_t) | |
2356 | obstack_alloc (&sec->objfile->psymbol_obstack, | |
2357 | sizeof (struct mips_extra_func_info)); | |
2358 | PROC_LOW_ADDR (proc_desc) = startaddr; | |
2359 | ||
2360 | /* Only used for dummy frames. */ | |
2361 | PROC_HIGH_ADDR (proc_desc) = 0; | |
2362 | ||
2363 | PROC_FRAME_OFFSET (proc_desc) | |
2364 | = bfd_get_32 (sec->objfile->obfd, ptr + 20); | |
2365 | PROC_FRAME_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2366 | ptr + 24); | |
2367 | PROC_FRAME_ADJUST (proc_desc) = 0; | |
2368 | PROC_REG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2369 | ptr + 4); | |
2370 | PROC_FREG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2371 | ptr + 12); | |
2372 | PROC_REG_OFFSET (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2373 | ptr + 8); | |
2374 | PROC_FREG_OFFSET (proc_desc) | |
2375 | = bfd_get_32 (sec->objfile->obfd, ptr + 16); | |
2376 | PROC_PC_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2377 | ptr + 28); | |
2378 | proc_desc->pdr.isym = (long) sym; | |
2379 | ||
2380 | return proc_desc; | |
2381 | } | |
2382 | } | |
c906108c SS |
2383 | } |
2384 | ||
6c0d6680 DJ |
2385 | if (b == NULL) |
2386 | return NULL; | |
2387 | ||
2388 | if (startaddr > BLOCK_START (b)) | |
2389 | { | |
2390 | /* This is the "pathological" case referred to in a comment in | |
2391 | print_frame_info. It might be better to move this check into | |
2392 | symbol reading. */ | |
2393 | return NULL; | |
2394 | } | |
2395 | ||
176620f1 | 2396 | sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_DOMAIN, 0, NULL); |
6c0d6680 | 2397 | |
c906108c SS |
2398 | /* If we never found a PDR for this function in symbol reading, then |
2399 | examine prologues to find the information. */ | |
2400 | if (sym) | |
2401 | { | |
2402 | proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); | |
2403 | if (PROC_FRAME_REG (proc_desc) == -1) | |
2404 | return NULL; | |
2405 | else | |
2406 | return proc_desc; | |
2407 | } | |
2408 | else | |
2409 | return NULL; | |
2410 | } | |
2411 | ||
2412 | ||
2413 | static mips_extra_func_info_t | |
479412cd | 2414 | find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame) |
c906108c SS |
2415 | { |
2416 | mips_extra_func_info_t proc_desc; | |
4e0df2df | 2417 | CORE_ADDR startaddr = 0; |
c906108c SS |
2418 | |
2419 | proc_desc = non_heuristic_proc_desc (pc, &startaddr); | |
2420 | ||
2421 | if (proc_desc) | |
2422 | { | |
2423 | /* IF this is the topmost frame AND | |
2424 | * (this proc does not have debugging information OR | |
2425 | * the PC is in the procedure prologue) | |
2426 | * THEN create a "heuristic" proc_desc (by analyzing | |
2427 | * the actual code) to replace the "official" proc_desc. | |
2428 | */ | |
2429 | if (next_frame == NULL) | |
2430 | { | |
2431 | struct symtab_and_line val; | |
2432 | struct symbol *proc_symbol = | |
c86b5b38 | 2433 | PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc); |
c906108c SS |
2434 | |
2435 | if (proc_symbol) | |
2436 | { | |
2437 | val = find_pc_line (BLOCK_START | |
c5aa993b | 2438 | (SYMBOL_BLOCK_VALUE (proc_symbol)), |
c906108c SS |
2439 | 0); |
2440 | val.pc = val.end ? val.end : pc; | |
2441 | } | |
2442 | if (!proc_symbol || pc < val.pc) | |
2443 | { | |
2444 | mips_extra_func_info_t found_heuristic = | |
c86b5b38 MS |
2445 | heuristic_proc_desc (PROC_LOW_ADDR (proc_desc), |
2446 | pc, next_frame, cur_frame); | |
c906108c SS |
2447 | if (found_heuristic) |
2448 | proc_desc = found_heuristic; | |
2449 | } | |
2450 | } | |
2451 | } | |
2452 | else | |
2453 | { | |
2454 | /* Is linked_proc_desc_table really necessary? It only seems to be used | |
c5aa993b JM |
2455 | by procedure call dummys. However, the procedures being called ought |
2456 | to have their own proc_descs, and even if they don't, | |
2457 | heuristic_proc_desc knows how to create them! */ | |
c906108c SS |
2458 | |
2459 | register struct linked_proc_info *link; | |
2460 | ||
2461 | for (link = linked_proc_desc_table; link; link = link->next) | |
c5aa993b JM |
2462 | if (PROC_LOW_ADDR (&link->info) <= pc |
2463 | && PROC_HIGH_ADDR (&link->info) > pc) | |
c906108c SS |
2464 | return &link->info; |
2465 | ||
2466 | if (startaddr == 0) | |
2467 | startaddr = heuristic_proc_start (pc); | |
2468 | ||
2469 | proc_desc = | |
479412cd | 2470 | heuristic_proc_desc (startaddr, pc, next_frame, cur_frame); |
c906108c SS |
2471 | } |
2472 | return proc_desc; | |
2473 | } | |
2474 | ||
2475 | static CORE_ADDR | |
acdb74a0 AC |
2476 | get_frame_pointer (struct frame_info *frame, |
2477 | mips_extra_func_info_t proc_desc) | |
c906108c | 2478 | { |
e227b13c AC |
2479 | return (read_next_frame_reg (frame, PROC_FRAME_REG (proc_desc)) |
2480 | + PROC_FRAME_OFFSET (proc_desc) | |
2481 | - PROC_FRAME_ADJUST (proc_desc)); | |
c906108c SS |
2482 | } |
2483 | ||
5a89d8aa | 2484 | static mips_extra_func_info_t cached_proc_desc; |
c906108c | 2485 | |
f7ab6ec6 | 2486 | static CORE_ADDR |
acdb74a0 | 2487 | mips_frame_chain (struct frame_info *frame) |
c906108c SS |
2488 | { |
2489 | mips_extra_func_info_t proc_desc; | |
2490 | CORE_ADDR tmp; | |
8bedc050 | 2491 | CORE_ADDR saved_pc = DEPRECATED_FRAME_SAVED_PC (frame); |
c906108c SS |
2492 | |
2493 | if (saved_pc == 0 || inside_entry_file (saved_pc)) | |
2494 | return 0; | |
2495 | ||
2496 | /* Check if the PC is inside a call stub. If it is, fetch the | |
2497 | PC of the caller of that stub. */ | |
5a89d8aa | 2498 | if ((tmp = SKIP_TRAMPOLINE_CODE (saved_pc)) != 0) |
c906108c SS |
2499 | saved_pc = tmp; |
2500 | ||
ae45cd16 | 2501 | if (DEPRECATED_PC_IN_CALL_DUMMY (saved_pc, 0, 0)) |
cedea778 AC |
2502 | { |
2503 | /* A dummy frame, uses SP not FP. Get the old SP value. If all | |
2504 | is well, frame->frame the bottom of the current frame will | |
2505 | contain that value. */ | |
1e2330ba | 2506 | return get_frame_base (frame); |
cedea778 AC |
2507 | } |
2508 | ||
c906108c | 2509 | /* Look up the procedure descriptor for this PC. */ |
479412cd | 2510 | proc_desc = find_proc_desc (saved_pc, frame, 1); |
c906108c SS |
2511 | if (!proc_desc) |
2512 | return 0; | |
2513 | ||
2514 | cached_proc_desc = proc_desc; | |
2515 | ||
2516 | /* If no frame pointer and frame size is zero, we must be at end | |
2517 | of stack (or otherwise hosed). If we don't check frame size, | |
2518 | we loop forever if we see a zero size frame. */ | |
2519 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM | |
2520 | && PROC_FRAME_OFFSET (proc_desc) == 0 | |
7807aa61 MS |
2521 | /* The previous frame from a sigtramp frame might be frameless |
2522 | and have frame size zero. */ | |
5a203e44 | 2523 | && !(get_frame_type (frame) == SIGTRAMP_FRAME) |
cedea778 AC |
2524 | /* For a generic dummy frame, let get_frame_pointer() unwind a |
2525 | register value saved as part of the dummy frame call. */ | |
50abf9e5 | 2526 | && !(DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0))) |
c906108c SS |
2527 | return 0; |
2528 | else | |
2529 | return get_frame_pointer (frame, proc_desc); | |
2530 | } | |
2531 | ||
f7ab6ec6 | 2532 | static void |
acdb74a0 | 2533 | mips_init_extra_frame_info (int fromleaf, struct frame_info *fci) |
c906108c SS |
2534 | { |
2535 | int regnum; | |
f2c16bd6 KB |
2536 | mips_extra_func_info_t proc_desc; |
2537 | ||
2538 | if (get_frame_type (fci) == DUMMY_FRAME) | |
2539 | return; | |
c906108c | 2540 | |
f796e4be KB |
2541 | /* Use proc_desc calculated in frame_chain. When there is no |
2542 | next frame, i.e, get_next_frame (fci) == NULL, we call | |
2543 | find_proc_desc () to calculate it, passing an explicit | |
2544 | NULL as the frame parameter. */ | |
f2c16bd6 | 2545 | proc_desc = |
11c02a10 AC |
2546 | get_next_frame (fci) |
2547 | ? cached_proc_desc | |
f796e4be KB |
2548 | : find_proc_desc (get_frame_pc (fci), |
2549 | NULL /* i.e, get_next_frame (fci) */, | |
2550 | 1); | |
c906108c | 2551 | |
a00a19e9 | 2552 | frame_extra_info_zalloc (fci, sizeof (struct frame_extra_info)); |
cce74817 | 2553 | |
7b5849cc | 2554 | deprecated_set_frame_saved_regs_hack (fci, NULL); |
da50a4b7 | 2555 | get_frame_extra_info (fci)->proc_desc = |
c906108c SS |
2556 | proc_desc == &temp_proc_desc ? 0 : proc_desc; |
2557 | if (proc_desc) | |
2558 | { | |
2559 | /* Fixup frame-pointer - only needed for top frame */ | |
2560 | /* This may not be quite right, if proc has a real frame register. | |
c5aa993b JM |
2561 | Get the value of the frame relative sp, procedure might have been |
2562 | interrupted by a signal at it's very start. */ | |
50abf9e5 | 2563 | if (get_frame_pc (fci) == PROC_LOW_ADDR (proc_desc) |
c906108c | 2564 | && !PROC_DESC_IS_DUMMY (proc_desc)) |
11c02a10 | 2565 | deprecated_update_frame_base_hack (fci, read_next_frame_reg (get_next_frame (fci), SP_REGNUM)); |
50abf9e5 | 2566 | else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fci), 0, 0)) |
cedea778 AC |
2567 | /* Do not ``fix'' fci->frame. It will have the value of the |
2568 | generic dummy frame's top-of-stack (since the draft | |
2569 | fci->frame is obtained by returning the unwound stack | |
2570 | pointer) and that is what we want. That way the fci->frame | |
2571 | value will match the top-of-stack value that was saved as | |
2572 | part of the dummy frames data. */ | |
2573 | /* Do nothing. */; | |
c906108c | 2574 | else |
11c02a10 | 2575 | deprecated_update_frame_base_hack (fci, get_frame_pointer (get_next_frame (fci), proc_desc)); |
c906108c SS |
2576 | |
2577 | if (proc_desc == &temp_proc_desc) | |
2578 | { | |
2579 | char *name; | |
2580 | ||
2581 | /* Do not set the saved registers for a sigtramp frame, | |
5a203e44 AC |
2582 | mips_find_saved_registers will do that for us. We can't |
2583 | use (get_frame_type (fci) == SIGTRAMP_FRAME), it is not | |
2584 | yet set. */ | |
2585 | /* FIXME: cagney/2002-11-18: This problem will go away once | |
2586 | frame.c:get_prev_frame() is modified to set the frame's | |
2587 | type before calling functions like this. */ | |
50abf9e5 | 2588 | find_pc_partial_function (get_frame_pc (fci), &name, |
c5aa993b | 2589 | (CORE_ADDR *) NULL, (CORE_ADDR *) NULL); |
50abf9e5 | 2590 | if (!PC_IN_SIGTRAMP (get_frame_pc (fci), name)) |
c906108c | 2591 | { |
c5aa993b | 2592 | frame_saved_regs_zalloc (fci); |
e0f7ec59 AC |
2593 | /* Set value of previous frame's stack pointer. |
2594 | Remember that saved_regs[SP_REGNUM] is special in | |
2595 | that it contains the value of the stack pointer | |
2596 | register. The other saved_regs values are addresses | |
2597 | (in the inferior) at which a given register's value | |
2598 | may be found. */ | |
2599 | set_reg_offset (temp_saved_regs, SP_REGNUM, | |
2600 | get_frame_base (fci)); | |
2601 | set_reg_offset (temp_saved_regs, PC_REGNUM, | |
2602 | temp_saved_regs[RA_REGNUM]); | |
2603 | memcpy (get_frame_saved_regs (fci), temp_saved_regs, | |
2604 | SIZEOF_FRAME_SAVED_REGS); | |
c906108c SS |
2605 | } |
2606 | } | |
2607 | ||
2608 | /* hack: if argument regs are saved, guess these contain args */ | |
cce74817 | 2609 | /* assume we can't tell how many args for now */ |
da50a4b7 | 2610 | get_frame_extra_info (fci)->num_args = -1; |
c906108c SS |
2611 | for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--) |
2612 | { | |
c5aa993b | 2613 | if (PROC_REG_MASK (proc_desc) & (1 << regnum)) |
c906108c | 2614 | { |
da50a4b7 | 2615 | get_frame_extra_info (fci)->num_args = regnum - A0_REGNUM + 1; |
c906108c SS |
2616 | break; |
2617 | } | |
c5aa993b | 2618 | } |
c906108c SS |
2619 | } |
2620 | } | |
2621 | ||
2622 | /* MIPS stack frames are almost impenetrable. When execution stops, | |
2623 | we basically have to look at symbol information for the function | |
2624 | that we stopped in, which tells us *which* register (if any) is | |
2625 | the base of the frame pointer, and what offset from that register | |
361d1df0 | 2626 | the frame itself is at. |
c906108c SS |
2627 | |
2628 | This presents a problem when trying to examine a stack in memory | |
2629 | (that isn't executing at the moment), using the "frame" command. We | |
2630 | don't have a PC, nor do we have any registers except SP. | |
2631 | ||
2632 | This routine takes two arguments, SP and PC, and tries to make the | |
2633 | cached frames look as if these two arguments defined a frame on the | |
2634 | cache. This allows the rest of info frame to extract the important | |
2635 | arguments without difficulty. */ | |
2636 | ||
2637 | struct frame_info * | |
acdb74a0 | 2638 | setup_arbitrary_frame (int argc, CORE_ADDR *argv) |
c906108c SS |
2639 | { |
2640 | if (argc != 2) | |
2641 | error ("MIPS frame specifications require two arguments: sp and pc"); | |
2642 | ||
2643 | return create_new_frame (argv[0], argv[1]); | |
2644 | } | |
2645 | ||
f09ded24 AC |
2646 | /* According to the current ABI, should the type be passed in a |
2647 | floating-point register (assuming that there is space)? When there | |
2648 | is no FPU, FP are not even considered as possibile candidates for | |
2649 | FP registers and, consequently this returns false - forces FP | |
2650 | arguments into integer registers. */ | |
2651 | ||
2652 | static int | |
2653 | fp_register_arg_p (enum type_code typecode, struct type *arg_type) | |
2654 | { | |
2655 | return ((typecode == TYPE_CODE_FLT | |
2656 | || (MIPS_EABI | |
2657 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
2658 | && TYPE_NFIELDS (arg_type) == 1 | |
2659 | && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT)) | |
c86b5b38 | 2660 | && MIPS_FPU_TYPE != MIPS_FPU_NONE); |
f09ded24 AC |
2661 | } |
2662 | ||
49e790b0 DJ |
2663 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
2664 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
2665 | ||
2666 | static int | |
2667 | mips_type_needs_double_align (struct type *type) | |
2668 | { | |
2669 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2670 | |
49e790b0 DJ |
2671 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2672 | return 1; | |
2673 | else if (typecode == TYPE_CODE_STRUCT) | |
2674 | { | |
2675 | if (TYPE_NFIELDS (type) < 1) | |
2676 | return 0; | |
2677 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2678 | } | |
2679 | else if (typecode == TYPE_CODE_UNION) | |
2680 | { | |
361d1df0 | 2681 | int i, n; |
49e790b0 DJ |
2682 | |
2683 | n = TYPE_NFIELDS (type); | |
2684 | for (i = 0; i < n; i++) | |
2685 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2686 | return 1; | |
2687 | return 0; | |
2688 | } | |
2689 | return 0; | |
2690 | } | |
2691 | ||
cb3d25d1 MS |
2692 | /* Macros to round N up or down to the next A boundary; |
2693 | A must be a power of two. */ | |
2694 | ||
2695 | #define ROUND_DOWN(n,a) ((n) & ~((a)-1)) | |
2696 | #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1)) | |
2697 | ||
dc604539 AC |
2698 | /* Adjust the address downward (direction of stack growth) so that it |
2699 | is correctly aligned for a new stack frame. */ | |
2700 | static CORE_ADDR | |
2701 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2702 | { | |
2703 | return ROUND_DOWN (addr, 16); | |
2704 | } | |
2705 | ||
f7ab6ec6 | 2706 | static CORE_ADDR |
25ab4790 AC |
2707 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
2708 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
2709 | struct value **args, CORE_ADDR sp, int struct_return, | |
2710 | CORE_ADDR struct_addr) | |
c906108c SS |
2711 | { |
2712 | int argreg; | |
2713 | int float_argreg; | |
2714 | int argnum; | |
2715 | int len = 0; | |
2716 | int stack_offset = 0; | |
2717 | ||
25ab4790 AC |
2718 | /* For shared libraries, "t9" needs to point at the function |
2719 | address. */ | |
2720 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
2721 | ||
2722 | /* Set the return address register to point to the entry point of | |
2723 | the program, where a breakpoint lies in wait. */ | |
2724 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
2725 | ||
c906108c | 2726 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2727 | are properly aligned. The stack has to be at least 64-bit |
2728 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2729 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2730 | aligned, so we round to this widest known alignment. */ | |
2731 | ||
c906108c | 2732 | sp = ROUND_DOWN (sp, 16); |
cce41527 | 2733 | struct_addr = ROUND_DOWN (struct_addr, 16); |
c5aa993b | 2734 | |
46e0f506 | 2735 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2736 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2737 | passed in registers, but that's OK. */ |
c906108c | 2738 | for (argnum = 0; argnum < nargs; argnum++) |
46e0f506 MS |
2739 | len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
2740 | MIPS_STACK_ARGSIZE); | |
c906108c SS |
2741 | sp -= ROUND_UP (len, 16); |
2742 | ||
9ace0497 | 2743 | if (mips_debug) |
46e0f506 | 2744 | fprintf_unfiltered (gdb_stdlog, |
25ab4790 | 2745 | "mips_eabi_push_dummy_call: sp=0x%s allocated %d\n", |
cb3d25d1 | 2746 | paddr_nz (sp), ROUND_UP (len, 16)); |
9ace0497 | 2747 | |
c906108c SS |
2748 | /* Initialize the integer and float register pointers. */ |
2749 | argreg = A0_REGNUM; | |
2750 | float_argreg = FPA0_REGNUM; | |
2751 | ||
46e0f506 | 2752 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2753 | if (struct_return) |
9ace0497 AC |
2754 | { |
2755 | if (mips_debug) | |
2756 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2757 | "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 2758 | argreg, paddr_nz (struct_addr)); |
9ace0497 AC |
2759 | write_register (argreg++, struct_addr); |
2760 | } | |
c906108c SS |
2761 | |
2762 | /* Now load as many as possible of the first arguments into | |
2763 | registers, and push the rest onto the stack. Loop thru args | |
2764 | from first to last. */ | |
2765 | for (argnum = 0; argnum < nargs; argnum++) | |
2766 | { | |
2767 | char *val; | |
d9d9c31f | 2768 | char valbuf[MAX_REGISTER_SIZE]; |
ea7c478f | 2769 | struct value *arg = args[argnum]; |
c906108c SS |
2770 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); |
2771 | int len = TYPE_LENGTH (arg_type); | |
2772 | enum type_code typecode = TYPE_CODE (arg_type); | |
2773 | ||
9ace0497 AC |
2774 | if (mips_debug) |
2775 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2776 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 2777 | argnum + 1, len, (int) typecode); |
9ace0497 | 2778 | |
c906108c | 2779 | /* The EABI passes structures that do not fit in a register by |
46e0f506 MS |
2780 | reference. */ |
2781 | if (len > MIPS_SAVED_REGSIZE | |
9ace0497 | 2782 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 2783 | { |
fbd9dcd3 | 2784 | store_unsigned_integer (valbuf, MIPS_SAVED_REGSIZE, VALUE_ADDRESS (arg)); |
c906108c | 2785 | typecode = TYPE_CODE_PTR; |
7a292a7a | 2786 | len = MIPS_SAVED_REGSIZE; |
c906108c | 2787 | val = valbuf; |
9ace0497 AC |
2788 | if (mips_debug) |
2789 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
2790 | } |
2791 | else | |
c5aa993b | 2792 | val = (char *) VALUE_CONTENTS (arg); |
c906108c SS |
2793 | |
2794 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
2795 | even-numbered floating point register. Round the FP register |
2796 | up before the check to see if there are any FP registers | |
46e0f506 MS |
2797 | left. Non MIPS_EABI targets also pass the FP in the integer |
2798 | registers so also round up normal registers. */ | |
acdb74a0 AC |
2799 | if (!FP_REGISTER_DOUBLE |
2800 | && fp_register_arg_p (typecode, arg_type)) | |
2801 | { | |
2802 | if ((float_argreg & 1)) | |
2803 | float_argreg++; | |
2804 | } | |
c906108c SS |
2805 | |
2806 | /* Floating point arguments passed in registers have to be | |
2807 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2808 | are passed in register pairs; the even register gets |
2809 | the low word, and the odd register gets the high word. | |
2810 | On non-EABI processors, the first two floating point arguments are | |
2811 | also copied to general registers, because MIPS16 functions | |
2812 | don't use float registers for arguments. This duplication of | |
2813 | arguments in general registers can't hurt non-MIPS16 functions | |
2814 | because those registers are normally skipped. */ | |
1012bd0e EZ |
2815 | /* MIPS_EABI squeezes a struct that contains a single floating |
2816 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 2817 | stack. */ |
f09ded24 AC |
2818 | if (fp_register_arg_p (typecode, arg_type) |
2819 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
c906108c SS |
2820 | { |
2821 | if (!FP_REGISTER_DOUBLE && len == 8) | |
2822 | { | |
d7449b42 | 2823 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
c906108c SS |
2824 | unsigned long regval; |
2825 | ||
2826 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 2827 | regval = extract_unsigned_integer (val + low_offset, 4); |
9ace0497 | 2828 | if (mips_debug) |
acdb74a0 | 2829 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2830 | float_argreg, phex (regval, 4)); |
c906108c | 2831 | write_register (float_argreg++, regval); |
c906108c SS |
2832 | |
2833 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 2834 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
9ace0497 | 2835 | if (mips_debug) |
acdb74a0 | 2836 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2837 | float_argreg, phex (regval, 4)); |
c906108c | 2838 | write_register (float_argreg++, regval); |
c906108c SS |
2839 | } |
2840 | else | |
2841 | { | |
2842 | /* This is a floating point value that fits entirely | |
2843 | in a single register. */ | |
53a5351d | 2844 | /* On 32 bit ABI's the float_argreg is further adjusted |
46e0f506 | 2845 | above to ensure that it is even register aligned. */ |
9ace0497 AC |
2846 | LONGEST regval = extract_unsigned_integer (val, len); |
2847 | if (mips_debug) | |
acdb74a0 | 2848 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2849 | float_argreg, phex (regval, len)); |
c906108c | 2850 | write_register (float_argreg++, regval); |
c906108c SS |
2851 | } |
2852 | } | |
2853 | else | |
2854 | { | |
2855 | /* Copy the argument to general registers or the stack in | |
2856 | register-sized pieces. Large arguments are split between | |
2857 | registers and stack. */ | |
2858 | /* Note: structs whose size is not a multiple of MIPS_REGSIZE | |
2859 | are treated specially: Irix cc passes them in registers | |
2860 | where gcc sometimes puts them on the stack. For maximum | |
2861 | compatibility, we will put them in both places. */ | |
c5aa993b | 2862 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && |
7a292a7a | 2863 | (len % MIPS_SAVED_REGSIZE != 0)); |
46e0f506 | 2864 | |
f09ded24 | 2865 | /* Note: Floating-point values that didn't fit into an FP |
46e0f506 | 2866 | register are only written to memory. */ |
c906108c SS |
2867 | while (len > 0) |
2868 | { | |
ebafbe83 | 2869 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 2870 | int stack_used_p = 0; |
46e0f506 MS |
2871 | int partial_len = |
2872 | len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE; | |
c906108c | 2873 | |
acdb74a0 AC |
2874 | if (mips_debug) |
2875 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2876 | partial_len); | |
2877 | ||
566f0f7a | 2878 | /* Write this portion of the argument to the stack. */ |
f09ded24 AC |
2879 | if (argreg > MIPS_LAST_ARG_REGNUM |
2880 | || odd_sized_struct | |
2881 | || fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2882 | { |
c906108c SS |
2883 | /* Should shorter than int integer values be |
2884 | promoted to int before being stored? */ | |
c906108c | 2885 | int longword_offset = 0; |
9ace0497 | 2886 | CORE_ADDR addr; |
566f0f7a | 2887 | stack_used_p = 1; |
d7449b42 | 2888 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
7a292a7a | 2889 | { |
d929b26f | 2890 | if (MIPS_STACK_ARGSIZE == 8 && |
7a292a7a SS |
2891 | (typecode == TYPE_CODE_INT || |
2892 | typecode == TYPE_CODE_PTR || | |
2893 | typecode == TYPE_CODE_FLT) && len <= 4) | |
d929b26f | 2894 | longword_offset = MIPS_STACK_ARGSIZE - len; |
7a292a7a SS |
2895 | else if ((typecode == TYPE_CODE_STRUCT || |
2896 | typecode == TYPE_CODE_UNION) && | |
d929b26f AC |
2897 | TYPE_LENGTH (arg_type) < MIPS_STACK_ARGSIZE) |
2898 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
7a292a7a | 2899 | } |
c5aa993b | 2900 | |
9ace0497 AC |
2901 | if (mips_debug) |
2902 | { | |
cb3d25d1 MS |
2903 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", |
2904 | paddr_nz (stack_offset)); | |
2905 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
2906 | paddr_nz (longword_offset)); | |
9ace0497 | 2907 | } |
361d1df0 | 2908 | |
9ace0497 AC |
2909 | addr = sp + stack_offset + longword_offset; |
2910 | ||
2911 | if (mips_debug) | |
2912 | { | |
2913 | int i; | |
cb3d25d1 MS |
2914 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
2915 | paddr_nz (addr)); | |
9ace0497 AC |
2916 | for (i = 0; i < partial_len; i++) |
2917 | { | |
cb3d25d1 MS |
2918 | fprintf_unfiltered (gdb_stdlog, "%02x", |
2919 | val[i] & 0xff); | |
9ace0497 AC |
2920 | } |
2921 | } | |
2922 | write_memory (addr, val, partial_len); | |
c906108c SS |
2923 | } |
2924 | ||
f09ded24 AC |
2925 | /* Note!!! This is NOT an else clause. Odd sized |
2926 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 2927 | arguments will not. */ |
566f0f7a | 2928 | /* Write this portion of the argument to a general |
46e0f506 | 2929 | purpose register. */ |
f09ded24 AC |
2930 | if (argreg <= MIPS_LAST_ARG_REGNUM |
2931 | && !fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2932 | { |
9ace0497 | 2933 | LONGEST regval = extract_unsigned_integer (val, partial_len); |
c906108c | 2934 | |
9ace0497 | 2935 | if (mips_debug) |
acdb74a0 | 2936 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 AC |
2937 | argreg, |
2938 | phex (regval, MIPS_SAVED_REGSIZE)); | |
c906108c SS |
2939 | write_register (argreg, regval); |
2940 | argreg++; | |
c906108c | 2941 | } |
c5aa993b | 2942 | |
c906108c SS |
2943 | len -= partial_len; |
2944 | val += partial_len; | |
2945 | ||
566f0f7a AC |
2946 | /* Compute the the offset into the stack at which we |
2947 | will copy the next parameter. | |
2948 | ||
566f0f7a | 2949 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 2950 | only needs to be adjusted when it has been used. */ |
c906108c | 2951 | |
46e0f506 | 2952 | if (stack_used_p) |
d929b26f | 2953 | stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE); |
c906108c SS |
2954 | } |
2955 | } | |
9ace0497 AC |
2956 | if (mips_debug) |
2957 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
2958 | } |
2959 | ||
310e9b6a AC |
2960 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
2961 | ||
0f71a2f6 JM |
2962 | /* Return adjusted stack pointer. */ |
2963 | return sp; | |
2964 | } | |
2965 | ||
25ab4790 | 2966 | /* N32/N64 version of push_dummy_call. */ |
ebafbe83 | 2967 | |
f7ab6ec6 | 2968 | static CORE_ADDR |
25ab4790 AC |
2969 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
2970 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
2971 | struct value **args, CORE_ADDR sp, int struct_return, | |
2972 | CORE_ADDR struct_addr) | |
cb3d25d1 MS |
2973 | { |
2974 | int argreg; | |
2975 | int float_argreg; | |
2976 | int argnum; | |
2977 | int len = 0; | |
2978 | int stack_offset = 0; | |
2979 | ||
25ab4790 AC |
2980 | /* For shared libraries, "t9" needs to point at the function |
2981 | address. */ | |
2982 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
2983 | ||
2984 | /* Set the return address register to point to the entry point of | |
2985 | the program, where a breakpoint lies in wait. */ | |
2986 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
2987 | ||
cb3d25d1 MS |
2988 | /* First ensure that the stack and structure return address (if any) |
2989 | are properly aligned. The stack has to be at least 64-bit | |
2990 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2991 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2992 | aligned, so we round to this widest known alignment. */ | |
2993 | ||
2994 | sp = ROUND_DOWN (sp, 16); | |
2995 | struct_addr = ROUND_DOWN (struct_addr, 16); | |
2996 | ||
2997 | /* Now make space on the stack for the args. */ | |
2998 | for (argnum = 0; argnum < nargs; argnum++) | |
2999 | len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])), | |
3000 | MIPS_STACK_ARGSIZE); | |
3001 | sp -= ROUND_UP (len, 16); | |
3002 | ||
3003 | if (mips_debug) | |
3004 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3005 | "mips_n32n64_push_dummy_call: sp=0x%s allocated %d\n", |
cb3d25d1 MS |
3006 | paddr_nz (sp), ROUND_UP (len, 16)); |
3007 | ||
3008 | /* Initialize the integer and float register pointers. */ | |
3009 | argreg = A0_REGNUM; | |
3010 | float_argreg = FPA0_REGNUM; | |
3011 | ||
46e0f506 | 3012 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
3013 | if (struct_return) |
3014 | { | |
3015 | if (mips_debug) | |
3016 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3017 | "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 MS |
3018 | argreg, paddr_nz (struct_addr)); |
3019 | write_register (argreg++, struct_addr); | |
3020 | } | |
3021 | ||
3022 | /* Now load as many as possible of the first arguments into | |
3023 | registers, and push the rest onto the stack. Loop thru args | |
3024 | from first to last. */ | |
3025 | for (argnum = 0; argnum < nargs; argnum++) | |
3026 | { | |
3027 | char *val; | |
d9d9c31f | 3028 | char valbuf[MAX_REGISTER_SIZE]; |
cb3d25d1 MS |
3029 | struct value *arg = args[argnum]; |
3030 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3031 | int len = TYPE_LENGTH (arg_type); | |
3032 | enum type_code typecode = TYPE_CODE (arg_type); | |
3033 | ||
3034 | if (mips_debug) | |
3035 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3036 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
3037 | argnum + 1, len, (int) typecode); |
3038 | ||
3039 | val = (char *) VALUE_CONTENTS (arg); | |
3040 | ||
3041 | if (fp_register_arg_p (typecode, arg_type) | |
3042 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3043 | { | |
3044 | /* This is a floating point value that fits entirely | |
3045 | in a single register. */ | |
3046 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3047 | above to ensure that it is even register aligned. */ | |
3048 | LONGEST regval = extract_unsigned_integer (val, len); | |
3049 | if (mips_debug) | |
3050 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3051 | float_argreg, phex (regval, len)); | |
3052 | write_register (float_argreg++, regval); | |
3053 | ||
3054 | if (mips_debug) | |
3055 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3056 | argreg, phex (regval, len)); | |
3057 | write_register (argreg, regval); | |
3058 | argreg += 1; | |
3059 | } | |
3060 | else | |
3061 | { | |
3062 | /* Copy the argument to general registers or the stack in | |
3063 | register-sized pieces. Large arguments are split between | |
3064 | registers and stack. */ | |
3065 | /* Note: structs whose size is not a multiple of MIPS_REGSIZE | |
3066 | are treated specially: Irix cc passes them in registers | |
3067 | where gcc sometimes puts them on the stack. For maximum | |
3068 | compatibility, we will put them in both places. */ | |
3069 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && | |
3070 | (len % MIPS_SAVED_REGSIZE != 0)); | |
3071 | /* Note: Floating-point values that didn't fit into an FP | |
3072 | register are only written to memory. */ | |
3073 | while (len > 0) | |
3074 | { | |
3075 | /* Rememer if the argument was written to the stack. */ | |
3076 | int stack_used_p = 0; | |
3077 | int partial_len = len < MIPS_SAVED_REGSIZE ? | |
3078 | len : MIPS_SAVED_REGSIZE; | |
3079 | ||
3080 | if (mips_debug) | |
3081 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3082 | partial_len); | |
3083 | ||
3084 | /* Write this portion of the argument to the stack. */ | |
3085 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3086 | || odd_sized_struct | |
3087 | || fp_register_arg_p (typecode, arg_type)) | |
3088 | { | |
3089 | /* Should shorter than int integer values be | |
3090 | promoted to int before being stored? */ | |
3091 | int longword_offset = 0; | |
3092 | CORE_ADDR addr; | |
3093 | stack_used_p = 1; | |
3094 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3095 | { | |
3096 | if (MIPS_STACK_ARGSIZE == 8 && | |
3097 | (typecode == TYPE_CODE_INT || | |
3098 | typecode == TYPE_CODE_PTR || | |
3099 | typecode == TYPE_CODE_FLT) && len <= 4) | |
3100 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
cb3d25d1 MS |
3101 | } |
3102 | ||
3103 | if (mips_debug) | |
3104 | { | |
3105 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3106 | paddr_nz (stack_offset)); | |
3107 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3108 | paddr_nz (longword_offset)); | |
3109 | } | |
3110 | ||
3111 | addr = sp + stack_offset + longword_offset; | |
3112 | ||
3113 | if (mips_debug) | |
3114 | { | |
3115 | int i; | |
3116 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", | |
3117 | paddr_nz (addr)); | |
3118 | for (i = 0; i < partial_len; i++) | |
3119 | { | |
3120 | fprintf_unfiltered (gdb_stdlog, "%02x", | |
3121 | val[i] & 0xff); | |
3122 | } | |
3123 | } | |
3124 | write_memory (addr, val, partial_len); | |
3125 | } | |
3126 | ||
3127 | /* Note!!! This is NOT an else clause. Odd sized | |
3128 | structs may go thru BOTH paths. Floating point | |
3129 | arguments will not. */ | |
3130 | /* Write this portion of the argument to a general | |
3131 | purpose register. */ | |
3132 | if (argreg <= MIPS_LAST_ARG_REGNUM | |
3133 | && !fp_register_arg_p (typecode, arg_type)) | |
3134 | { | |
3135 | LONGEST regval = extract_unsigned_integer (val, partial_len); | |
3136 | ||
3137 | /* A non-floating-point argument being passed in a | |
3138 | general register. If a struct or union, and if | |
3139 | the remaining length is smaller than the register | |
3140 | size, we have to adjust the register value on | |
3141 | big endian targets. | |
3142 | ||
3143 | It does not seem to be necessary to do the | |
3144 | same for integral types. | |
3145 | ||
3146 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3147 | outputting LE O32 with sizeof (struct) < | |
3148 | MIPS_SAVED_REGSIZE, generates a left shift as | |
3149 | part of storing the argument in a register a | |
3150 | register (the left shift isn't generated when | |
3151 | sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it | |
3152 | is quite possible that this is GCC contradicting | |
3153 | the LE/O32 ABI, GDB has not been adjusted to | |
3154 | accommodate this. Either someone needs to | |
3155 | demonstrate that the LE/O32 ABI specifies such a | |
3156 | left shift OR this new ABI gets identified as | |
3157 | such and GDB gets tweaked accordingly. */ | |
3158 | ||
3159 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3160 | && partial_len < MIPS_SAVED_REGSIZE | |
3161 | && (typecode == TYPE_CODE_STRUCT || | |
3162 | typecode == TYPE_CODE_UNION)) | |
3163 | regval <<= ((MIPS_SAVED_REGSIZE - partial_len) * | |
3164 | TARGET_CHAR_BIT); | |
3165 | ||
3166 | if (mips_debug) | |
3167 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3168 | argreg, | |
3169 | phex (regval, MIPS_SAVED_REGSIZE)); | |
3170 | write_register (argreg, regval); | |
3171 | argreg++; | |
3172 | } | |
3173 | ||
3174 | len -= partial_len; | |
3175 | val += partial_len; | |
3176 | ||
3177 | /* Compute the the offset into the stack at which we | |
3178 | will copy the next parameter. | |
3179 | ||
3180 | In N32 (N64?), the stack_offset only needs to be | |
3181 | adjusted when it has been used. */ | |
3182 | ||
3183 | if (stack_used_p) | |
3184 | stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE); | |
3185 | } | |
3186 | } | |
3187 | if (mips_debug) | |
3188 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3189 | } | |
3190 | ||
310e9b6a AC |
3191 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
3192 | ||
cb3d25d1 MS |
3193 | /* Return adjusted stack pointer. */ |
3194 | return sp; | |
3195 | } | |
3196 | ||
25ab4790 | 3197 | /* O32 version of push_dummy_call. */ |
ebafbe83 | 3198 | |
46cac009 | 3199 | static CORE_ADDR |
25ab4790 AC |
3200 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
3201 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
3202 | struct value **args, CORE_ADDR sp, int struct_return, | |
3203 | CORE_ADDR struct_addr) | |
ebafbe83 MS |
3204 | { |
3205 | int argreg; | |
3206 | int float_argreg; | |
3207 | int argnum; | |
3208 | int len = 0; | |
3209 | int stack_offset = 0; | |
ebafbe83 | 3210 | |
25ab4790 AC |
3211 | /* For shared libraries, "t9" needs to point at the function |
3212 | address. */ | |
3213 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3214 | ||
3215 | /* Set the return address register to point to the entry point of | |
3216 | the program, where a breakpoint lies in wait. */ | |
3217 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3218 | ||
ebafbe83 MS |
3219 | /* First ensure that the stack and structure return address (if any) |
3220 | are properly aligned. The stack has to be at least 64-bit | |
3221 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3222 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3223 | aligned, so we round to this widest known alignment. */ | |
3224 | ||
3225 | sp = ROUND_DOWN (sp, 16); | |
3226 | struct_addr = ROUND_DOWN (struct_addr, 16); | |
3227 | ||
3228 | /* Now make space on the stack for the args. */ | |
3229 | for (argnum = 0; argnum < nargs; argnum++) | |
3230 | len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])), | |
3231 | MIPS_STACK_ARGSIZE); | |
3232 | sp -= ROUND_UP (len, 16); | |
3233 | ||
3234 | if (mips_debug) | |
3235 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3236 | "mips_o32_push_dummy_call: sp=0x%s allocated %d\n", |
ebafbe83 MS |
3237 | paddr_nz (sp), ROUND_UP (len, 16)); |
3238 | ||
3239 | /* Initialize the integer and float register pointers. */ | |
3240 | argreg = A0_REGNUM; | |
3241 | float_argreg = FPA0_REGNUM; | |
3242 | ||
bcb0cc15 | 3243 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3244 | if (struct_return) |
3245 | { | |
3246 | if (mips_debug) | |
3247 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3248 | "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n", |
ebafbe83 MS |
3249 | argreg, paddr_nz (struct_addr)); |
3250 | write_register (argreg++, struct_addr); | |
3251 | stack_offset += MIPS_STACK_ARGSIZE; | |
3252 | } | |
3253 | ||
3254 | /* Now load as many as possible of the first arguments into | |
3255 | registers, and push the rest onto the stack. Loop thru args | |
3256 | from first to last. */ | |
3257 | for (argnum = 0; argnum < nargs; argnum++) | |
3258 | { | |
3259 | char *val; | |
d9d9c31f | 3260 | char valbuf[MAX_REGISTER_SIZE]; |
ebafbe83 MS |
3261 | struct value *arg = args[argnum]; |
3262 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3263 | int len = TYPE_LENGTH (arg_type); | |
3264 | enum type_code typecode = TYPE_CODE (arg_type); | |
3265 | ||
3266 | if (mips_debug) | |
3267 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3268 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3269 | argnum + 1, len, (int) typecode); |
3270 | ||
3271 | val = (char *) VALUE_CONTENTS (arg); | |
3272 | ||
3273 | /* 32-bit ABIs always start floating point arguments in an | |
3274 | even-numbered floating point register. Round the FP register | |
3275 | up before the check to see if there are any FP registers | |
3276 | left. O32/O64 targets also pass the FP in the integer | |
3277 | registers so also round up normal registers. */ | |
3278 | if (!FP_REGISTER_DOUBLE | |
3279 | && fp_register_arg_p (typecode, arg_type)) | |
3280 | { | |
3281 | if ((float_argreg & 1)) | |
3282 | float_argreg++; | |
3283 | } | |
3284 | ||
3285 | /* Floating point arguments passed in registers have to be | |
3286 | treated specially. On 32-bit architectures, doubles | |
3287 | are passed in register pairs; the even register gets | |
3288 | the low word, and the odd register gets the high word. | |
3289 | On O32/O64, the first two floating point arguments are | |
3290 | also copied to general registers, because MIPS16 functions | |
3291 | don't use float registers for arguments. This duplication of | |
3292 | arguments in general registers can't hurt non-MIPS16 functions | |
3293 | because those registers are normally skipped. */ | |
3294 | ||
3295 | if (fp_register_arg_p (typecode, arg_type) | |
3296 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3297 | { | |
3298 | if (!FP_REGISTER_DOUBLE && len == 8) | |
3299 | { | |
3300 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
3301 | unsigned long regval; | |
3302 | ||
3303 | /* Write the low word of the double to the even register(s). */ | |
3304 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3305 | if (mips_debug) | |
3306 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3307 | float_argreg, phex (regval, 4)); | |
3308 | write_register (float_argreg++, regval); | |
3309 | if (mips_debug) | |
3310 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3311 | argreg, phex (regval, 4)); | |
3312 | write_register (argreg++, regval); | |
3313 | ||
3314 | /* Write the high word of the double to the odd register(s). */ | |
3315 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3316 | if (mips_debug) | |
3317 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3318 | float_argreg, phex (regval, 4)); | |
3319 | write_register (float_argreg++, regval); | |
3320 | ||
3321 | if (mips_debug) | |
3322 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3323 | argreg, phex (regval, 4)); | |
3324 | write_register (argreg++, regval); | |
3325 | } | |
3326 | else | |
3327 | { | |
3328 | /* This is a floating point value that fits entirely | |
3329 | in a single register. */ | |
3330 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3331 | above to ensure that it is even register aligned. */ | |
3332 | LONGEST regval = extract_unsigned_integer (val, len); | |
3333 | if (mips_debug) | |
3334 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3335 | float_argreg, phex (regval, len)); | |
3336 | write_register (float_argreg++, regval); | |
3337 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
3338 | registers for each argument. The below is (my | |
3339 | guess) to ensure that the corresponding integer | |
3340 | register has reserved the same space. */ | |
3341 | if (mips_debug) | |
3342 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3343 | argreg, phex (regval, len)); | |
3344 | write_register (argreg, regval); | |
3345 | argreg += FP_REGISTER_DOUBLE ? 1 : 2; | |
3346 | } | |
3347 | /* Reserve space for the FP register. */ | |
3348 | stack_offset += ROUND_UP (len, MIPS_STACK_ARGSIZE); | |
3349 | } | |
3350 | else | |
3351 | { | |
3352 | /* Copy the argument to general registers or the stack in | |
3353 | register-sized pieces. Large arguments are split between | |
3354 | registers and stack. */ | |
3355 | /* Note: structs whose size is not a multiple of MIPS_REGSIZE | |
3356 | are treated specially: Irix cc passes them in registers | |
3357 | where gcc sometimes puts them on the stack. For maximum | |
3358 | compatibility, we will put them in both places. */ | |
3359 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && | |
3360 | (len % MIPS_SAVED_REGSIZE != 0)); | |
3361 | /* Structures should be aligned to eight bytes (even arg registers) | |
3362 | on MIPS_ABI_O32, if their first member has double precision. */ | |
3363 | if (MIPS_SAVED_REGSIZE < 8 | |
3364 | && mips_type_needs_double_align (arg_type)) | |
3365 | { | |
3366 | if ((argreg & 1)) | |
3367 | argreg++; | |
3368 | } | |
3369 | /* Note: Floating-point values that didn't fit into an FP | |
3370 | register are only written to memory. */ | |
3371 | while (len > 0) | |
3372 | { | |
3373 | /* Remember if the argument was written to the stack. */ | |
3374 | int stack_used_p = 0; | |
3375 | int partial_len = | |
3376 | len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE; | |
3377 | ||
3378 | if (mips_debug) | |
3379 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3380 | partial_len); | |
3381 | ||
3382 | /* Write this portion of the argument to the stack. */ | |
3383 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3384 | || odd_sized_struct | |
3385 | || fp_register_arg_p (typecode, arg_type)) | |
3386 | { | |
3387 | /* Should shorter than int integer values be | |
3388 | promoted to int before being stored? */ | |
3389 | int longword_offset = 0; | |
3390 | CORE_ADDR addr; | |
3391 | stack_used_p = 1; | |
3392 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3393 | { | |
3394 | if (MIPS_STACK_ARGSIZE == 8 && | |
3395 | (typecode == TYPE_CODE_INT || | |
3396 | typecode == TYPE_CODE_PTR || | |
3397 | typecode == TYPE_CODE_FLT) && len <= 4) | |
3398 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
3399 | } | |
3400 | ||
3401 | if (mips_debug) | |
3402 | { | |
3403 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3404 | paddr_nz (stack_offset)); | |
3405 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3406 | paddr_nz (longword_offset)); | |
3407 | } | |
3408 | ||
3409 | addr = sp + stack_offset + longword_offset; | |
3410 | ||
3411 | if (mips_debug) | |
3412 | { | |
3413 | int i; | |
3414 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", | |
3415 | paddr_nz (addr)); | |
3416 | for (i = 0; i < partial_len; i++) | |
3417 | { | |
3418 | fprintf_unfiltered (gdb_stdlog, "%02x", | |
3419 | val[i] & 0xff); | |
3420 | } | |
3421 | } | |
3422 | write_memory (addr, val, partial_len); | |
3423 | } | |
3424 | ||
3425 | /* Note!!! This is NOT an else clause. Odd sized | |
3426 | structs may go thru BOTH paths. Floating point | |
3427 | arguments will not. */ | |
3428 | /* Write this portion of the argument to a general | |
3429 | purpose register. */ | |
3430 | if (argreg <= MIPS_LAST_ARG_REGNUM | |
3431 | && !fp_register_arg_p (typecode, arg_type)) | |
3432 | { | |
3433 | LONGEST regval = extract_signed_integer (val, partial_len); | |
3434 | /* Value may need to be sign extended, because | |
3435 | MIPS_REGSIZE != MIPS_SAVED_REGSIZE. */ | |
3436 | ||
3437 | /* A non-floating-point argument being passed in a | |
3438 | general register. If a struct or union, and if | |
3439 | the remaining length is smaller than the register | |
3440 | size, we have to adjust the register value on | |
3441 | big endian targets. | |
3442 | ||
3443 | It does not seem to be necessary to do the | |
3444 | same for integral types. | |
3445 | ||
3446 | Also don't do this adjustment on O64 binaries. | |
3447 | ||
3448 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3449 | outputting LE O32 with sizeof (struct) < | |
3450 | MIPS_SAVED_REGSIZE, generates a left shift as | |
3451 | part of storing the argument in a register a | |
3452 | register (the left shift isn't generated when | |
3453 | sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it | |
3454 | is quite possible that this is GCC contradicting | |
3455 | the LE/O32 ABI, GDB has not been adjusted to | |
3456 | accommodate this. Either someone needs to | |
3457 | demonstrate that the LE/O32 ABI specifies such a | |
3458 | left shift OR this new ABI gets identified as | |
3459 | such and GDB gets tweaked accordingly. */ | |
3460 | ||
3461 | if (MIPS_SAVED_REGSIZE < 8 | |
3462 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3463 | && partial_len < MIPS_SAVED_REGSIZE | |
3464 | && (typecode == TYPE_CODE_STRUCT || | |
3465 | typecode == TYPE_CODE_UNION)) | |
3466 | regval <<= ((MIPS_SAVED_REGSIZE - partial_len) * | |
3467 | TARGET_CHAR_BIT); | |
3468 | ||
3469 | if (mips_debug) | |
3470 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3471 | argreg, | |
3472 | phex (regval, MIPS_SAVED_REGSIZE)); | |
3473 | write_register (argreg, regval); | |
3474 | argreg++; | |
3475 | ||
3476 | /* Prevent subsequent floating point arguments from | |
3477 | being passed in floating point registers. */ | |
3478 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3479 | } | |
3480 | ||
3481 | len -= partial_len; | |
3482 | val += partial_len; | |
3483 | ||
3484 | /* Compute the the offset into the stack at which we | |
3485 | will copy the next parameter. | |
3486 | ||
3487 | In older ABIs, the caller reserved space for | |
3488 | registers that contained arguments. This was loosely | |
3489 | refered to as their "home". Consequently, space is | |
3490 | always allocated. */ | |
3491 | ||
3492 | stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE); | |
3493 | } | |
3494 | } | |
3495 | if (mips_debug) | |
3496 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3497 | } | |
3498 | ||
310e9b6a AC |
3499 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
3500 | ||
46cac009 AC |
3501 | /* Return adjusted stack pointer. */ |
3502 | return sp; | |
3503 | } | |
3504 | ||
25ab4790 | 3505 | /* O64 version of push_dummy_call. */ |
46cac009 AC |
3506 | |
3507 | static CORE_ADDR | |
25ab4790 AC |
3508 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
3509 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
3510 | struct value **args, CORE_ADDR sp, int struct_return, | |
3511 | CORE_ADDR struct_addr) | |
46cac009 AC |
3512 | { |
3513 | int argreg; | |
3514 | int float_argreg; | |
3515 | int argnum; | |
3516 | int len = 0; | |
3517 | int stack_offset = 0; | |
3518 | ||
25ab4790 AC |
3519 | /* For shared libraries, "t9" needs to point at the function |
3520 | address. */ | |
3521 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3522 | ||
3523 | /* Set the return address register to point to the entry point of | |
3524 | the program, where a breakpoint lies in wait. */ | |
3525 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3526 | ||
46cac009 AC |
3527 | /* First ensure that the stack and structure return address (if any) |
3528 | are properly aligned. The stack has to be at least 64-bit | |
3529 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3530 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3531 | aligned, so we round to this widest known alignment. */ | |
3532 | ||
3533 | sp = ROUND_DOWN (sp, 16); | |
3534 | struct_addr = ROUND_DOWN (struct_addr, 16); | |
3535 | ||
3536 | /* Now make space on the stack for the args. */ | |
3537 | for (argnum = 0; argnum < nargs; argnum++) | |
3538 | len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])), | |
3539 | MIPS_STACK_ARGSIZE); | |
3540 | sp -= ROUND_UP (len, 16); | |
3541 | ||
3542 | if (mips_debug) | |
3543 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3544 | "mips_o64_push_dummy_call: sp=0x%s allocated %d\n", |
46cac009 AC |
3545 | paddr_nz (sp), ROUND_UP (len, 16)); |
3546 | ||
3547 | /* Initialize the integer and float register pointers. */ | |
3548 | argreg = A0_REGNUM; | |
3549 | float_argreg = FPA0_REGNUM; | |
3550 | ||
3551 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
3552 | if (struct_return) | |
3553 | { | |
3554 | if (mips_debug) | |
3555 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3556 | "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n", |
46cac009 AC |
3557 | argreg, paddr_nz (struct_addr)); |
3558 | write_register (argreg++, struct_addr); | |
3559 | stack_offset += MIPS_STACK_ARGSIZE; | |
3560 | } | |
3561 | ||
3562 | /* Now load as many as possible of the first arguments into | |
3563 | registers, and push the rest onto the stack. Loop thru args | |
3564 | from first to last. */ | |
3565 | for (argnum = 0; argnum < nargs; argnum++) | |
3566 | { | |
3567 | char *val; | |
d9d9c31f | 3568 | char valbuf[MAX_REGISTER_SIZE]; |
46cac009 AC |
3569 | struct value *arg = args[argnum]; |
3570 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3571 | int len = TYPE_LENGTH (arg_type); | |
3572 | enum type_code typecode = TYPE_CODE (arg_type); | |
3573 | ||
3574 | if (mips_debug) | |
3575 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3576 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
3577 | argnum + 1, len, (int) typecode); |
3578 | ||
3579 | val = (char *) VALUE_CONTENTS (arg); | |
3580 | ||
3581 | /* 32-bit ABIs always start floating point arguments in an | |
3582 | even-numbered floating point register. Round the FP register | |
3583 | up before the check to see if there are any FP registers | |
3584 | left. O32/O64 targets also pass the FP in the integer | |
3585 | registers so also round up normal registers. */ | |
3586 | if (!FP_REGISTER_DOUBLE | |
3587 | && fp_register_arg_p (typecode, arg_type)) | |
3588 | { | |
3589 | if ((float_argreg & 1)) | |
3590 | float_argreg++; | |
3591 | } | |
3592 | ||
3593 | /* Floating point arguments passed in registers have to be | |
3594 | treated specially. On 32-bit architectures, doubles | |
3595 | are passed in register pairs; the even register gets | |
3596 | the low word, and the odd register gets the high word. | |
3597 | On O32/O64, the first two floating point arguments are | |
3598 | also copied to general registers, because MIPS16 functions | |
3599 | don't use float registers for arguments. This duplication of | |
3600 | arguments in general registers can't hurt non-MIPS16 functions | |
3601 | because those registers are normally skipped. */ | |
3602 | ||
3603 | if (fp_register_arg_p (typecode, arg_type) | |
3604 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3605 | { | |
3606 | if (!FP_REGISTER_DOUBLE && len == 8) | |
3607 | { | |
3608 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
3609 | unsigned long regval; | |
3610 | ||
3611 | /* Write the low word of the double to the even register(s). */ | |
3612 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3613 | if (mips_debug) | |
3614 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3615 | float_argreg, phex (regval, 4)); | |
3616 | write_register (float_argreg++, regval); | |
3617 | if (mips_debug) | |
3618 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3619 | argreg, phex (regval, 4)); | |
3620 | write_register (argreg++, regval); | |
3621 | ||
3622 | /* Write the high word of the double to the odd register(s). */ | |
3623 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3624 | if (mips_debug) | |
3625 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3626 | float_argreg, phex (regval, 4)); | |
3627 | write_register (float_argreg++, regval); | |
3628 | ||
3629 | if (mips_debug) | |
3630 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3631 | argreg, phex (regval, 4)); | |
3632 | write_register (argreg++, regval); | |
3633 | } | |
3634 | else | |
3635 | { | |
3636 | /* This is a floating point value that fits entirely | |
3637 | in a single register. */ | |
3638 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3639 | above to ensure that it is even register aligned. */ | |
3640 | LONGEST regval = extract_unsigned_integer (val, len); | |
3641 | if (mips_debug) | |
3642 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3643 | float_argreg, phex (regval, len)); | |
3644 | write_register (float_argreg++, regval); | |
3645 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
3646 | registers for each argument. The below is (my | |
3647 | guess) to ensure that the corresponding integer | |
3648 | register has reserved the same space. */ | |
3649 | if (mips_debug) | |
3650 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3651 | argreg, phex (regval, len)); | |
3652 | write_register (argreg, regval); | |
3653 | argreg += FP_REGISTER_DOUBLE ? 1 : 2; | |
3654 | } | |
3655 | /* Reserve space for the FP register. */ | |
3656 | stack_offset += ROUND_UP (len, MIPS_STACK_ARGSIZE); | |
3657 | } | |
3658 | else | |
3659 | { | |
3660 | /* Copy the argument to general registers or the stack in | |
3661 | register-sized pieces. Large arguments are split between | |
3662 | registers and stack. */ | |
3663 | /* Note: structs whose size is not a multiple of MIPS_REGSIZE | |
3664 | are treated specially: Irix cc passes them in registers | |
3665 | where gcc sometimes puts them on the stack. For maximum | |
3666 | compatibility, we will put them in both places. */ | |
3667 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && | |
3668 | (len % MIPS_SAVED_REGSIZE != 0)); | |
3669 | /* Structures should be aligned to eight bytes (even arg registers) | |
3670 | on MIPS_ABI_O32, if their first member has double precision. */ | |
3671 | if (MIPS_SAVED_REGSIZE < 8 | |
3672 | && mips_type_needs_double_align (arg_type)) | |
3673 | { | |
3674 | if ((argreg & 1)) | |
3675 | argreg++; | |
3676 | } | |
3677 | /* Note: Floating-point values that didn't fit into an FP | |
3678 | register are only written to memory. */ | |
3679 | while (len > 0) | |
3680 | { | |
3681 | /* Remember if the argument was written to the stack. */ | |
3682 | int stack_used_p = 0; | |
3683 | int partial_len = | |
3684 | len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE; | |
3685 | ||
3686 | if (mips_debug) | |
3687 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3688 | partial_len); | |
3689 | ||
3690 | /* Write this portion of the argument to the stack. */ | |
3691 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3692 | || odd_sized_struct | |
3693 | || fp_register_arg_p (typecode, arg_type)) | |
3694 | { | |
3695 | /* Should shorter than int integer values be | |
3696 | promoted to int before being stored? */ | |
3697 | int longword_offset = 0; | |
3698 | CORE_ADDR addr; | |
3699 | stack_used_p = 1; | |
3700 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3701 | { | |
3702 | if (MIPS_STACK_ARGSIZE == 8 && | |
3703 | (typecode == TYPE_CODE_INT || | |
3704 | typecode == TYPE_CODE_PTR || | |
3705 | typecode == TYPE_CODE_FLT) && len <= 4) | |
3706 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
3707 | } | |
3708 | ||
3709 | if (mips_debug) | |
3710 | { | |
3711 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3712 | paddr_nz (stack_offset)); | |
3713 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3714 | paddr_nz (longword_offset)); | |
3715 | } | |
3716 | ||
3717 | addr = sp + stack_offset + longword_offset; | |
3718 | ||
3719 | if (mips_debug) | |
3720 | { | |
3721 | int i; | |
3722 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", | |
3723 | paddr_nz (addr)); | |
3724 | for (i = 0; i < partial_len; i++) | |
3725 | { | |
3726 | fprintf_unfiltered (gdb_stdlog, "%02x", | |
3727 | val[i] & 0xff); | |
3728 | } | |
3729 | } | |
3730 | write_memory (addr, val, partial_len); | |
3731 | } | |
3732 | ||
3733 | /* Note!!! This is NOT an else clause. Odd sized | |
3734 | structs may go thru BOTH paths. Floating point | |
3735 | arguments will not. */ | |
3736 | /* Write this portion of the argument to a general | |
3737 | purpose register. */ | |
3738 | if (argreg <= MIPS_LAST_ARG_REGNUM | |
3739 | && !fp_register_arg_p (typecode, arg_type)) | |
3740 | { | |
3741 | LONGEST regval = extract_signed_integer (val, partial_len); | |
3742 | /* Value may need to be sign extended, because | |
3743 | MIPS_REGSIZE != MIPS_SAVED_REGSIZE. */ | |
3744 | ||
3745 | /* A non-floating-point argument being passed in a | |
3746 | general register. If a struct or union, and if | |
3747 | the remaining length is smaller than the register | |
3748 | size, we have to adjust the register value on | |
3749 | big endian targets. | |
3750 | ||
3751 | It does not seem to be necessary to do the | |
3752 | same for integral types. | |
3753 | ||
3754 | Also don't do this adjustment on O64 binaries. | |
3755 | ||
3756 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3757 | outputting LE O32 with sizeof (struct) < | |
3758 | MIPS_SAVED_REGSIZE, generates a left shift as | |
3759 | part of storing the argument in a register a | |
3760 | register (the left shift isn't generated when | |
3761 | sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it | |
3762 | is quite possible that this is GCC contradicting | |
3763 | the LE/O32 ABI, GDB has not been adjusted to | |
3764 | accommodate this. Either someone needs to | |
3765 | demonstrate that the LE/O32 ABI specifies such a | |
3766 | left shift OR this new ABI gets identified as | |
3767 | such and GDB gets tweaked accordingly. */ | |
3768 | ||
3769 | if (MIPS_SAVED_REGSIZE < 8 | |
3770 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3771 | && partial_len < MIPS_SAVED_REGSIZE | |
3772 | && (typecode == TYPE_CODE_STRUCT || | |
3773 | typecode == TYPE_CODE_UNION)) | |
3774 | regval <<= ((MIPS_SAVED_REGSIZE - partial_len) * | |
3775 | TARGET_CHAR_BIT); | |
3776 | ||
3777 | if (mips_debug) | |
3778 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3779 | argreg, | |
3780 | phex (regval, MIPS_SAVED_REGSIZE)); | |
3781 | write_register (argreg, regval); | |
3782 | argreg++; | |
3783 | ||
3784 | /* Prevent subsequent floating point arguments from | |
3785 | being passed in floating point registers. */ | |
3786 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3787 | } | |
3788 | ||
3789 | len -= partial_len; | |
3790 | val += partial_len; | |
3791 | ||
3792 | /* Compute the the offset into the stack at which we | |
3793 | will copy the next parameter. | |
3794 | ||
3795 | In older ABIs, the caller reserved space for | |
3796 | registers that contained arguments. This was loosely | |
3797 | refered to as their "home". Consequently, space is | |
3798 | always allocated. */ | |
3799 | ||
3800 | stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE); | |
3801 | } | |
3802 | } | |
3803 | if (mips_debug) | |
3804 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3805 | } | |
3806 | ||
310e9b6a AC |
3807 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
3808 | ||
ebafbe83 MS |
3809 | /* Return adjusted stack pointer. */ |
3810 | return sp; | |
3811 | } | |
3812 | ||
f7ab6ec6 | 3813 | static void |
acdb74a0 | 3814 | mips_pop_frame (void) |
c906108c SS |
3815 | { |
3816 | register int regnum; | |
3817 | struct frame_info *frame = get_current_frame (); | |
c193f6ac | 3818 | CORE_ADDR new_sp = get_frame_base (frame); |
e227b13c | 3819 | mips_extra_func_info_t proc_desc; |
c906108c | 3820 | |
50abf9e5 | 3821 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0)) |
cedea778 AC |
3822 | { |
3823 | generic_pop_dummy_frame (); | |
3824 | flush_cached_frames (); | |
3825 | return; | |
3826 | } | |
3827 | ||
e227b13c | 3828 | proc_desc = get_frame_extra_info (frame)->proc_desc; |
8bedc050 | 3829 | write_register (PC_REGNUM, DEPRECATED_FRAME_SAVED_PC (frame)); |
e0f7ec59 | 3830 | mips_find_saved_regs (frame); |
c906108c | 3831 | for (regnum = 0; regnum < NUM_REGS; regnum++) |
21f87145 | 3832 | if (regnum != SP_REGNUM && regnum != PC_REGNUM |
b2fb4676 | 3833 | && get_frame_saved_regs (frame)[regnum]) |
21f87145 MS |
3834 | { |
3835 | /* Floating point registers must not be sign extended, | |
3836 | in case MIPS_SAVED_REGSIZE = 4 but sizeof (FP0_REGNUM) == 8. */ | |
3837 | ||
3838 | if (FP0_REGNUM <= regnum && regnum < FP0_REGNUM + 32) | |
3839 | write_register (regnum, | |
b2fb4676 | 3840 | read_memory_unsigned_integer (get_frame_saved_regs (frame)[regnum], |
21f87145 MS |
3841 | MIPS_SAVED_REGSIZE)); |
3842 | else | |
3843 | write_register (regnum, | |
b2fb4676 | 3844 | read_memory_integer (get_frame_saved_regs (frame)[regnum], |
21f87145 MS |
3845 | MIPS_SAVED_REGSIZE)); |
3846 | } | |
757a7cc6 | 3847 | |
c906108c SS |
3848 | write_register (SP_REGNUM, new_sp); |
3849 | flush_cached_frames (); | |
3850 | ||
c5aa993b | 3851 | if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) |
c906108c SS |
3852 | { |
3853 | struct linked_proc_info *pi_ptr, *prev_ptr; | |
3854 | ||
3855 | for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL; | |
3856 | pi_ptr != NULL; | |
3857 | prev_ptr = pi_ptr, pi_ptr = pi_ptr->next) | |
3858 | { | |
3859 | if (&pi_ptr->info == proc_desc) | |
3860 | break; | |
3861 | } | |
3862 | ||
3863 | if (pi_ptr == NULL) | |
3864 | error ("Can't locate dummy extra frame info\n"); | |
3865 | ||
3866 | if (prev_ptr != NULL) | |
3867 | prev_ptr->next = pi_ptr->next; | |
3868 | else | |
3869 | linked_proc_desc_table = pi_ptr->next; | |
3870 | ||
b8c9b27d | 3871 | xfree (pi_ptr); |
c906108c SS |
3872 | |
3873 | write_register (HI_REGNUM, | |
c5aa993b | 3874 | read_memory_integer (new_sp - 2 * MIPS_SAVED_REGSIZE, |
7a292a7a | 3875 | MIPS_SAVED_REGSIZE)); |
c906108c | 3876 | write_register (LO_REGNUM, |
c5aa993b | 3877 | read_memory_integer (new_sp - 3 * MIPS_SAVED_REGSIZE, |
7a292a7a | 3878 | MIPS_SAVED_REGSIZE)); |
c906108c SS |
3879 | if (MIPS_FPU_TYPE != MIPS_FPU_NONE) |
3880 | write_register (FCRCS_REGNUM, | |
c5aa993b | 3881 | read_memory_integer (new_sp - 4 * MIPS_SAVED_REGSIZE, |
7a292a7a | 3882 | MIPS_SAVED_REGSIZE)); |
c906108c SS |
3883 | } |
3884 | } | |
3885 | ||
dd824b04 DJ |
3886 | /* Floating point register management. |
3887 | ||
3888 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
3889 | 64bit operations, these early MIPS cpus treat fp register pairs | |
3890 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
3891 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
3892 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
3893 | double precision floats into two 32-bit chunks and store them in | |
3894 | consecutive fp regs. To display 64-bit floats stored in this | |
3895 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
3896 | Throw in user-configurable endianness and you have a real mess. | |
3897 | ||
3898 | The way this works is: | |
3899 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
3900 | double-precision value will be split across two logical registers. | |
3901 | The lower-numbered logical register will hold the low-order bits, | |
3902 | regardless of the processor's endianness. | |
3903 | - If we are on a 64-bit processor, and we are looking for a | |
3904 | single-precision value, it will be in the low ordered bits | |
3905 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
3906 | save slot in memory. | |
3907 | - If we are in 64-bit mode, everything is straightforward. | |
3908 | ||
3909 | Note that this code only deals with "live" registers at the top of the | |
3910 | stack. We will attempt to deal with saved registers later, when | |
3911 | the raw/cooked register interface is in place. (We need a general | |
3912 | interface that can deal with dynamic saved register sizes -- fp | |
3913 | regs could be 32 bits wide in one frame and 64 on the frame above | |
3914 | and below). */ | |
3915 | ||
67b2c998 DJ |
3916 | static struct type * |
3917 | mips_float_register_type (void) | |
3918 | { | |
361d1df0 | 3919 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
3920 | return builtin_type_ieee_single_big; |
3921 | else | |
3922 | return builtin_type_ieee_single_little; | |
3923 | } | |
3924 | ||
3925 | static struct type * | |
3926 | mips_double_register_type (void) | |
3927 | { | |
361d1df0 | 3928 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
3929 | return builtin_type_ieee_double_big; |
3930 | else | |
3931 | return builtin_type_ieee_double_little; | |
3932 | } | |
3933 | ||
dd824b04 DJ |
3934 | /* Copy a 32-bit single-precision value from the current frame |
3935 | into rare_buffer. */ | |
3936 | ||
3937 | static void | |
e11c53d2 AC |
3938 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
3939 | char *rare_buffer) | |
dd824b04 DJ |
3940 | { |
3941 | int raw_size = REGISTER_RAW_SIZE (regno); | |
3942 | char *raw_buffer = alloca (raw_size); | |
3943 | ||
e11c53d2 | 3944 | if (!frame_register_read (frame, regno, raw_buffer)) |
dd824b04 DJ |
3945 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
3946 | if (raw_size == 8) | |
3947 | { | |
3948 | /* We have a 64-bit value for this register. Find the low-order | |
3949 | 32 bits. */ | |
3950 | int offset; | |
3951 | ||
3952 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3953 | offset = 4; | |
3954 | else | |
3955 | offset = 0; | |
3956 | ||
3957 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
3958 | } | |
3959 | else | |
3960 | { | |
3961 | memcpy (rare_buffer, raw_buffer, 4); | |
3962 | } | |
3963 | } | |
3964 | ||
3965 | /* Copy a 64-bit double-precision value from the current frame into | |
3966 | rare_buffer. This may include getting half of it from the next | |
3967 | register. */ | |
3968 | ||
3969 | static void | |
e11c53d2 AC |
3970 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
3971 | char *rare_buffer) | |
dd824b04 DJ |
3972 | { |
3973 | int raw_size = REGISTER_RAW_SIZE (regno); | |
3974 | ||
3975 | if (raw_size == 8 && !mips2_fp_compat ()) | |
3976 | { | |
3977 | /* We have a 64-bit value for this register, and we should use | |
3978 | all 64 bits. */ | |
e11c53d2 | 3979 | if (!frame_register_read (frame, regno, rare_buffer)) |
dd824b04 DJ |
3980 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
3981 | } | |
3982 | else | |
3983 | { | |
3984 | if ((regno - FP0_REGNUM) & 1) | |
3985 | internal_error (__FILE__, __LINE__, | |
3986 | "mips_read_fp_register_double: bad access to " | |
3987 | "odd-numbered FP register"); | |
3988 | ||
3989 | /* mips_read_fp_register_single will find the correct 32 bits from | |
3990 | each register. */ | |
3991 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3992 | { | |
e11c53d2 AC |
3993 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
3994 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 3995 | } |
361d1df0 | 3996 | else |
dd824b04 | 3997 | { |
e11c53d2 AC |
3998 | mips_read_fp_register_single (frame, regno, rare_buffer); |
3999 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
4000 | } |
4001 | } | |
4002 | } | |
4003 | ||
c906108c | 4004 | static void |
e11c53d2 AC |
4005 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
4006 | int regnum) | |
c5aa993b | 4007 | { /* do values for FP (float) regs */ |
dd824b04 | 4008 | char *raw_buffer; |
c906108c | 4009 | double doub, flt1, flt2; /* doubles extracted from raw hex data */ |
f0ef6b29 | 4010 | int inv1, inv2, namelen; |
c5aa993b | 4011 | |
dd824b04 | 4012 | raw_buffer = (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM)); |
c906108c | 4013 | |
e11c53d2 AC |
4014 | fprintf_filtered (file, "%s:", REGISTER_NAME (regnum)); |
4015 | fprintf_filtered (file, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum)), | |
4016 | ""); | |
f0ef6b29 | 4017 | |
dd824b04 | 4018 | if (REGISTER_RAW_SIZE (regnum) == 4 || mips2_fp_compat ()) |
c906108c | 4019 | { |
f0ef6b29 KB |
4020 | /* 4-byte registers: Print hex and floating. Also print even |
4021 | numbered registers as doubles. */ | |
e11c53d2 | 4022 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
67b2c998 | 4023 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c5aa993b | 4024 | |
e11c53d2 | 4025 | print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w', file); |
dd824b04 | 4026 | |
e11c53d2 | 4027 | fprintf_filtered (file, " flt: "); |
1adad886 | 4028 | if (inv1) |
e11c53d2 | 4029 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4030 | else |
e11c53d2 | 4031 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4032 | |
f0ef6b29 KB |
4033 | if (regnum % 2 == 0) |
4034 | { | |
e11c53d2 | 4035 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
4036 | doub = unpack_double (mips_double_register_type (), raw_buffer, |
4037 | &inv2); | |
1adad886 | 4038 | |
e11c53d2 | 4039 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4040 | if (inv2) |
e11c53d2 | 4041 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 4042 | else |
e11c53d2 | 4043 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 4044 | } |
c906108c SS |
4045 | } |
4046 | else | |
dd824b04 | 4047 | { |
f0ef6b29 | 4048 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 4049 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
2f38ef89 | 4050 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c906108c | 4051 | |
e11c53d2 | 4052 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
4053 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2); |
4054 | ||
361d1df0 | 4055 | |
e11c53d2 | 4056 | print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g', file); |
f0ef6b29 | 4057 | |
e11c53d2 | 4058 | fprintf_filtered (file, " flt: "); |
1adad886 | 4059 | if (inv1) |
e11c53d2 | 4060 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 4061 | else |
e11c53d2 | 4062 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4063 | |
e11c53d2 | 4064 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4065 | if (inv2) |
e11c53d2 | 4066 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 4067 | else |
e11c53d2 | 4068 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
4069 | } |
4070 | } | |
4071 | ||
4072 | static void | |
e11c53d2 AC |
4073 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
4074 | int regnum, int all) | |
f0ef6b29 | 4075 | { |
d9d9c31f | 4076 | char raw_buffer[MAX_REGISTER_SIZE]; |
f0ef6b29 | 4077 | int offset; |
1adad886 | 4078 | |
f0ef6b29 KB |
4079 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
4080 | { | |
e11c53d2 | 4081 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4082 | return; |
4083 | } | |
4084 | ||
4085 | /* Get the data in raw format. */ | |
e11c53d2 | 4086 | if (!frame_register_read (frame, regnum, raw_buffer)) |
f0ef6b29 | 4087 | { |
e11c53d2 | 4088 | fprintf_filtered (file, "%s: [Invalid]", REGISTER_NAME (regnum)); |
f0ef6b29 | 4089 | return; |
c906108c | 4090 | } |
f0ef6b29 | 4091 | |
e11c53d2 | 4092 | fputs_filtered (REGISTER_NAME (regnum), file); |
f0ef6b29 KB |
4093 | |
4094 | /* The problem with printing numeric register names (r26, etc.) is that | |
4095 | the user can't use them on input. Probably the best solution is to | |
4096 | fix it so that either the numeric or the funky (a2, etc.) names | |
4097 | are accepted on input. */ | |
4098 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 4099 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 4100 | else |
e11c53d2 | 4101 | fprintf_filtered (file, ": "); |
f0ef6b29 KB |
4102 | |
4103 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
4104 | offset = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum); | |
4105 | else | |
4106 | offset = 0; | |
4107 | ||
4108 | print_scalar_formatted (raw_buffer + offset, | |
4109 | REGISTER_VIRTUAL_TYPE (regnum), | |
e11c53d2 | 4110 | 'x', 0, file); |
c906108c SS |
4111 | } |
4112 | ||
f0ef6b29 KB |
4113 | /* Replacement for generic do_registers_info. |
4114 | Print regs in pretty columns. */ | |
4115 | ||
4116 | static int | |
e11c53d2 AC |
4117 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
4118 | int regnum) | |
f0ef6b29 | 4119 | { |
e11c53d2 AC |
4120 | fprintf_filtered (file, " "); |
4121 | mips_print_fp_register (file, frame, regnum); | |
4122 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
4123 | return regnum + 1; |
4124 | } | |
4125 | ||
4126 | ||
c906108c SS |
4127 | /* Print a row's worth of GP (int) registers, with name labels above */ |
4128 | ||
4129 | static int | |
e11c53d2 AC |
4130 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
4131 | int regnum) | |
c906108c SS |
4132 | { |
4133 | /* do values for GP (int) regs */ | |
d9d9c31f | 4134 | char raw_buffer[MAX_REGISTER_SIZE]; |
c906108c SS |
4135 | int ncols = (MIPS_REGSIZE == 8 ? 4 : 8); /* display cols per row */ |
4136 | int col, byte; | |
4137 | int start_regnum = regnum; | |
4138 | int numregs = NUM_REGS; | |
4139 | ||
4140 | ||
4141 | /* For GP registers, we print a separate row of names above the vals */ | |
e11c53d2 | 4142 | fprintf_filtered (file, " "); |
c906108c SS |
4143 | for (col = 0; col < ncols && regnum < numregs; regnum++) |
4144 | { | |
4145 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 4146 | continue; /* unused register */ |
c906108c | 4147 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
c5aa993b | 4148 | break; /* end the row: reached FP register */ |
e11c53d2 AC |
4149 | fprintf_filtered (file, MIPS_REGSIZE == 8 ? "%17s" : "%9s", |
4150 | REGISTER_NAME (regnum)); | |
c906108c SS |
4151 | col++; |
4152 | } | |
e11c53d2 AC |
4153 | fprintf_filtered (file, |
4154 | start_regnum < MIPS_NUMREGS ? "\n R%-4d" : "\n ", | |
4155 | start_regnum); /* print the R0 to R31 names */ | |
c906108c SS |
4156 | |
4157 | regnum = start_regnum; /* go back to start of row */ | |
4158 | /* now print the values in hex, 4 or 8 to the row */ | |
4159 | for (col = 0; col < ncols && regnum < numregs; regnum++) | |
4160 | { | |
4161 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 4162 | continue; /* unused register */ |
c906108c | 4163 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
c5aa993b | 4164 | break; /* end row: reached FP register */ |
c906108c | 4165 | /* OK: get the data in raw format. */ |
e11c53d2 | 4166 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c906108c SS |
4167 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); |
4168 | /* pad small registers */ | |
43e526b9 | 4169 | for (byte = 0; byte < (MIPS_REGSIZE - REGISTER_VIRTUAL_SIZE (regnum)); byte++) |
c906108c SS |
4170 | printf_filtered (" "); |
4171 | /* Now print the register value in hex, endian order. */ | |
d7449b42 | 4172 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
43e526b9 JM |
4173 | for (byte = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum); |
4174 | byte < REGISTER_RAW_SIZE (regnum); | |
4175 | byte++) | |
e11c53d2 | 4176 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); |
c906108c | 4177 | else |
43e526b9 JM |
4178 | for (byte = REGISTER_VIRTUAL_SIZE (regnum) - 1; |
4179 | byte >= 0; | |
4180 | byte--) | |
e11c53d2 AC |
4181 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); |
4182 | fprintf_filtered (file, " "); | |
c906108c SS |
4183 | col++; |
4184 | } | |
c5aa993b | 4185 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 4186 | fprintf_filtered (file, "\n"); |
c906108c SS |
4187 | |
4188 | return regnum; | |
4189 | } | |
4190 | ||
4191 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
4192 | ||
bf1f5b4c | 4193 | static void |
e11c53d2 AC |
4194 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4195 | struct frame_info *frame, int regnum, int all) | |
c906108c | 4196 | { |
c5aa993b | 4197 | if (regnum != -1) /* do one specified register */ |
c906108c SS |
4198 | { |
4199 | if (*(REGISTER_NAME (regnum)) == '\0') | |
4200 | error ("Not a valid register for the current processor type"); | |
4201 | ||
e11c53d2 AC |
4202 | mips_print_register (file, frame, regnum, 0); |
4203 | fprintf_filtered (file, "\n"); | |
c906108c | 4204 | } |
c5aa993b JM |
4205 | else |
4206 | /* do all (or most) registers */ | |
c906108c SS |
4207 | { |
4208 | regnum = 0; | |
4209 | while (regnum < NUM_REGS) | |
4210 | { | |
c5aa993b | 4211 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
e11c53d2 AC |
4212 | { |
4213 | if (all) /* true for "INFO ALL-REGISTERS" command */ | |
4214 | regnum = print_fp_register_row (file, frame, regnum); | |
4215 | else | |
4216 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
4217 | } | |
c906108c | 4218 | else |
e11c53d2 | 4219 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
4220 | } |
4221 | } | |
4222 | } | |
4223 | ||
c906108c SS |
4224 | /* Is this a branch with a delay slot? */ |
4225 | ||
a14ed312 | 4226 | static int is_delayed (unsigned long); |
c906108c SS |
4227 | |
4228 | static int | |
acdb74a0 | 4229 | is_delayed (unsigned long insn) |
c906108c SS |
4230 | { |
4231 | int i; | |
4232 | for (i = 0; i < NUMOPCODES; ++i) | |
4233 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4234 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4235 | break; | |
4236 | return (i < NUMOPCODES | |
4237 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4238 | | INSN_COND_BRANCH_DELAY | |
4239 | | INSN_COND_BRANCH_LIKELY))); | |
4240 | } | |
4241 | ||
4242 | int | |
acdb74a0 | 4243 | mips_step_skips_delay (CORE_ADDR pc) |
c906108c SS |
4244 | { |
4245 | char buf[MIPS_INSTLEN]; | |
4246 | ||
4247 | /* There is no branch delay slot on MIPS16. */ | |
4248 | if (pc_is_mips16 (pc)) | |
4249 | return 0; | |
4250 | ||
4251 | if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0) | |
4252 | /* If error reading memory, guess that it is not a delayed branch. */ | |
4253 | return 0; | |
c5aa993b | 4254 | return is_delayed ((unsigned long) extract_unsigned_integer (buf, MIPS_INSTLEN)); |
c906108c SS |
4255 | } |
4256 | ||
4257 | ||
4258 | /* Skip the PC past function prologue instructions (32-bit version). | |
4259 | This is a helper function for mips_skip_prologue. */ | |
4260 | ||
4261 | static CORE_ADDR | |
f7b9e9fc | 4262 | mips32_skip_prologue (CORE_ADDR pc) |
c906108c | 4263 | { |
c5aa993b JM |
4264 | t_inst inst; |
4265 | CORE_ADDR end_pc; | |
4266 | int seen_sp_adjust = 0; | |
4267 | int load_immediate_bytes = 0; | |
4268 | ||
4269 | /* Skip the typical prologue instructions. These are the stack adjustment | |
4270 | instruction and the instructions that save registers on the stack | |
4271 | or in the gcc frame. */ | |
4272 | for (end_pc = pc + 100; pc < end_pc; pc += MIPS_INSTLEN) | |
4273 | { | |
4274 | unsigned long high_word; | |
c906108c | 4275 | |
c5aa993b JM |
4276 | inst = mips_fetch_instruction (pc); |
4277 | high_word = (inst >> 16) & 0xffff; | |
c906108c | 4278 | |
c5aa993b JM |
4279 | if (high_word == 0x27bd /* addiu $sp,$sp,offset */ |
4280 | || high_word == 0x67bd) /* daddiu $sp,$sp,offset */ | |
4281 | seen_sp_adjust = 1; | |
4282 | else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */ | |
4283 | inst == 0x03a8e823) /* subu $sp,$sp,$t0 */ | |
4284 | seen_sp_adjust = 1; | |
4285 | else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */ | |
4286 | || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */ | |
4287 | && (inst & 0x001F0000)) /* reg != $zero */ | |
4288 | continue; | |
4289 | ||
4290 | else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */ | |
4291 | continue; | |
4292 | else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000)) | |
4293 | /* sx reg,n($s8) */ | |
4294 | continue; /* reg != $zero */ | |
4295 | ||
4296 | /* move $s8,$sp. With different versions of gas this will be either | |
4297 | `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'. | |
4298 | Accept any one of these. */ | |
4299 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
4300 | continue; | |
4301 | ||
4302 | else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */ | |
4303 | continue; | |
4304 | else if (high_word == 0x3c1c) /* lui $gp,n */ | |
4305 | continue; | |
4306 | else if (high_word == 0x279c) /* addiu $gp,$gp,n */ | |
4307 | continue; | |
4308 | else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
4309 | || inst == 0x033ce021) /* addu $gp,$t9,$gp */ | |
4310 | continue; | |
4311 | /* The following instructions load $at or $t0 with an immediate | |
4312 | value in preparation for a stack adjustment via | |
4313 | subu $sp,$sp,[$at,$t0]. These instructions could also initialize | |
4314 | a local variable, so we accept them only before a stack adjustment | |
4315 | instruction was seen. */ | |
4316 | else if (!seen_sp_adjust) | |
4317 | { | |
4318 | if (high_word == 0x3c01 || /* lui $at,n */ | |
4319 | high_word == 0x3c08) /* lui $t0,n */ | |
4320 | { | |
4321 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
4322 | continue; | |
4323 | } | |
4324 | else if (high_word == 0x3421 || /* ori $at,$at,n */ | |
4325 | high_word == 0x3508 || /* ori $t0,$t0,n */ | |
4326 | high_word == 0x3401 || /* ori $at,$zero,n */ | |
4327 | high_word == 0x3408) /* ori $t0,$zero,n */ | |
4328 | { | |
4329 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
4330 | continue; | |
4331 | } | |
4332 | else | |
4333 | break; | |
4334 | } | |
4335 | else | |
4336 | break; | |
c906108c SS |
4337 | } |
4338 | ||
c5aa993b JM |
4339 | /* In a frameless function, we might have incorrectly |
4340 | skipped some load immediate instructions. Undo the skipping | |
4341 | if the load immediate was not followed by a stack adjustment. */ | |
4342 | if (load_immediate_bytes && !seen_sp_adjust) | |
4343 | pc -= load_immediate_bytes; | |
4344 | return pc; | |
c906108c SS |
4345 | } |
4346 | ||
4347 | /* Skip the PC past function prologue instructions (16-bit version). | |
4348 | This is a helper function for mips_skip_prologue. */ | |
4349 | ||
4350 | static CORE_ADDR | |
f7b9e9fc | 4351 | mips16_skip_prologue (CORE_ADDR pc) |
c906108c | 4352 | { |
c5aa993b JM |
4353 | CORE_ADDR end_pc; |
4354 | int extend_bytes = 0; | |
4355 | int prev_extend_bytes; | |
c906108c | 4356 | |
c5aa993b JM |
4357 | /* Table of instructions likely to be found in a function prologue. */ |
4358 | static struct | |
c906108c SS |
4359 | { |
4360 | unsigned short inst; | |
4361 | unsigned short mask; | |
c5aa993b JM |
4362 | } |
4363 | table[] = | |
4364 | { | |
c906108c | 4365 | { |
c5aa993b JM |
4366 | 0x6300, 0xff00 |
4367 | } | |
4368 | , /* addiu $sp,offset */ | |
4369 | { | |
4370 | 0xfb00, 0xff00 | |
4371 | } | |
4372 | , /* daddiu $sp,offset */ | |
4373 | { | |
4374 | 0xd000, 0xf800 | |
4375 | } | |
4376 | , /* sw reg,n($sp) */ | |
4377 | { | |
4378 | 0xf900, 0xff00 | |
4379 | } | |
4380 | , /* sd reg,n($sp) */ | |
4381 | { | |
4382 | 0x6200, 0xff00 | |
4383 | } | |
4384 | , /* sw $ra,n($sp) */ | |
4385 | { | |
4386 | 0xfa00, 0xff00 | |
4387 | } | |
4388 | , /* sd $ra,n($sp) */ | |
4389 | { | |
4390 | 0x673d, 0xffff | |
4391 | } | |
4392 | , /* move $s1,sp */ | |
4393 | { | |
4394 | 0xd980, 0xff80 | |
4395 | } | |
4396 | , /* sw $a0-$a3,n($s1) */ | |
4397 | { | |
4398 | 0x6704, 0xff1c | |
4399 | } | |
4400 | , /* move reg,$a0-$a3 */ | |
4401 | { | |
4402 | 0xe809, 0xf81f | |
4403 | } | |
4404 | , /* entry pseudo-op */ | |
4405 | { | |
4406 | 0x0100, 0xff00 | |
4407 | } | |
4408 | , /* addiu $s1,$sp,n */ | |
4409 | { | |
4410 | 0, 0 | |
4411 | } /* end of table marker */ | |
4412 | }; | |
4413 | ||
4414 | /* Skip the typical prologue instructions. These are the stack adjustment | |
4415 | instruction and the instructions that save registers on the stack | |
4416 | or in the gcc frame. */ | |
4417 | for (end_pc = pc + 100; pc < end_pc; pc += MIPS16_INSTLEN) | |
4418 | { | |
4419 | unsigned short inst; | |
4420 | int i; | |
c906108c | 4421 | |
c5aa993b | 4422 | inst = mips_fetch_instruction (pc); |
c906108c | 4423 | |
c5aa993b JM |
4424 | /* Normally we ignore an extend instruction. However, if it is |
4425 | not followed by a valid prologue instruction, we must adjust | |
4426 | the pc back over the extend so that it won't be considered | |
4427 | part of the prologue. */ | |
4428 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
4429 | { | |
4430 | extend_bytes = MIPS16_INSTLEN; | |
4431 | continue; | |
4432 | } | |
4433 | prev_extend_bytes = extend_bytes; | |
4434 | extend_bytes = 0; | |
c906108c | 4435 | |
c5aa993b JM |
4436 | /* Check for other valid prologue instructions besides extend. */ |
4437 | for (i = 0; table[i].mask != 0; i++) | |
4438 | if ((inst & table[i].mask) == table[i].inst) /* found, get out */ | |
4439 | break; | |
4440 | if (table[i].mask != 0) /* it was in table? */ | |
4441 | continue; /* ignore it */ | |
4442 | else | |
4443 | /* non-prologue */ | |
4444 | { | |
4445 | /* Return the current pc, adjusted backwards by 2 if | |
4446 | the previous instruction was an extend. */ | |
4447 | return pc - prev_extend_bytes; | |
4448 | } | |
c906108c SS |
4449 | } |
4450 | return pc; | |
4451 | } | |
4452 | ||
4453 | /* To skip prologues, I use this predicate. Returns either PC itself | |
4454 | if the code at PC does not look like a function prologue; otherwise | |
4455 | returns an address that (if we're lucky) follows the prologue. If | |
4456 | LENIENT, then we must skip everything which is involved in setting | |
4457 | up the frame (it's OK to skip more, just so long as we don't skip | |
4458 | anything which might clobber the registers which are being saved. | |
4459 | We must skip more in the case where part of the prologue is in the | |
4460 | delay slot of a non-prologue instruction). */ | |
4461 | ||
f7ab6ec6 | 4462 | static CORE_ADDR |
f7b9e9fc | 4463 | mips_skip_prologue (CORE_ADDR pc) |
c906108c SS |
4464 | { |
4465 | /* See if we can determine the end of the prologue via the symbol table. | |
4466 | If so, then return either PC, or the PC after the prologue, whichever | |
4467 | is greater. */ | |
4468 | ||
4469 | CORE_ADDR post_prologue_pc = after_prologue (pc, NULL); | |
4470 | ||
4471 | if (post_prologue_pc != 0) | |
4472 | return max (pc, post_prologue_pc); | |
4473 | ||
4474 | /* Can't determine prologue from the symbol table, need to examine | |
4475 | instructions. */ | |
4476 | ||
4477 | if (pc_is_mips16 (pc)) | |
f7b9e9fc | 4478 | return mips16_skip_prologue (pc); |
c906108c | 4479 | else |
f7b9e9fc | 4480 | return mips32_skip_prologue (pc); |
c906108c | 4481 | } |
c906108c | 4482 | |
7a292a7a SS |
4483 | /* Determine how a return value is stored within the MIPS register |
4484 | file, given the return type `valtype'. */ | |
4485 | ||
4486 | struct return_value_word | |
4487 | { | |
4488 | int len; | |
4489 | int reg; | |
4490 | int reg_offset; | |
4491 | int buf_offset; | |
4492 | }; | |
4493 | ||
7a292a7a | 4494 | static void |
acdb74a0 AC |
4495 | return_value_location (struct type *valtype, |
4496 | struct return_value_word *hi, | |
4497 | struct return_value_word *lo) | |
7a292a7a SS |
4498 | { |
4499 | int len = TYPE_LENGTH (valtype); | |
c5aa993b | 4500 | |
7a292a7a SS |
4501 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT |
4502 | && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8)) | |
4503 | || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4))) | |
4504 | { | |
4505 | if (!FP_REGISTER_DOUBLE && len == 8) | |
4506 | { | |
4507 | /* We need to break a 64bit float in two 32 bit halves and | |
c5aa993b | 4508 | spread them across a floating-point register pair. */ |
d7449b42 AC |
4509 | lo->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
4510 | hi->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 0 : 4; | |
4511 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
7a292a7a SS |
4512 | && REGISTER_RAW_SIZE (FP0_REGNUM) == 8) |
4513 | ? 4 : 0); | |
4514 | hi->reg_offset = lo->reg_offset; | |
4515 | lo->reg = FP0_REGNUM + 0; | |
4516 | hi->reg = FP0_REGNUM + 1; | |
4517 | lo->len = 4; | |
4518 | hi->len = 4; | |
4519 | } | |
4520 | else | |
4521 | { | |
4522 | /* The floating point value fits in a single floating-point | |
c5aa993b | 4523 | register. */ |
d7449b42 | 4524 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
4525 | && REGISTER_RAW_SIZE (FP0_REGNUM) == 8 |
4526 | && len == 4) | |
4527 | ? 4 : 0); | |
4528 | lo->reg = FP0_REGNUM; | |
4529 | lo->len = len; | |
4530 | lo->buf_offset = 0; | |
4531 | hi->len = 0; | |
4532 | hi->reg_offset = 0; | |
4533 | hi->buf_offset = 0; | |
4534 | hi->reg = 0; | |
4535 | } | |
4536 | } | |
4537 | else | |
4538 | { | |
4539 | /* Locate a result possibly spread across two registers. */ | |
4540 | int regnum = 2; | |
4541 | lo->reg = regnum + 0; | |
4542 | hi->reg = regnum + 1; | |
d7449b42 | 4543 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
4544 | && len < MIPS_SAVED_REGSIZE) |
4545 | { | |
bf1f5b4c MS |
4546 | /* "un-left-justify" the value in the low register */ |
4547 | lo->reg_offset = MIPS_SAVED_REGSIZE - len; | |
bcb0cc15 | 4548 | lo->len = len; |
bf1f5b4c | 4549 | hi->reg_offset = 0; |
7a292a7a SS |
4550 | hi->len = 0; |
4551 | } | |
d7449b42 | 4552 | else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
4553 | && len > MIPS_SAVED_REGSIZE /* odd-size structs */ |
4554 | && len < MIPS_SAVED_REGSIZE * 2 | |
4555 | && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || | |
4556 | TYPE_CODE (valtype) == TYPE_CODE_UNION)) | |
4557 | { | |
4558 | /* "un-left-justify" the value spread across two registers. */ | |
4559 | lo->reg_offset = 2 * MIPS_SAVED_REGSIZE - len; | |
4560 | lo->len = MIPS_SAVED_REGSIZE - lo->reg_offset; | |
4561 | hi->reg_offset = 0; | |
4562 | hi->len = len - lo->len; | |
4563 | } | |
4564 | else | |
4565 | { | |
4566 | /* Only perform a partial copy of the second register. */ | |
4567 | lo->reg_offset = 0; | |
4568 | hi->reg_offset = 0; | |
4569 | if (len > MIPS_SAVED_REGSIZE) | |
4570 | { | |
4571 | lo->len = MIPS_SAVED_REGSIZE; | |
4572 | hi->len = len - MIPS_SAVED_REGSIZE; | |
4573 | } | |
4574 | else | |
4575 | { | |
4576 | lo->len = len; | |
4577 | hi->len = 0; | |
4578 | } | |
4579 | } | |
d7449b42 | 4580 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
4581 | && REGISTER_RAW_SIZE (regnum) == 8 |
4582 | && MIPS_SAVED_REGSIZE == 4) | |
4583 | { | |
4584 | /* Account for the fact that only the least-signficant part | |
c5aa993b | 4585 | of the register is being used */ |
7a292a7a SS |
4586 | lo->reg_offset += 4; |
4587 | hi->reg_offset += 4; | |
4588 | } | |
4589 | lo->buf_offset = 0; | |
4590 | hi->buf_offset = lo->len; | |
4591 | } | |
4592 | } | |
4593 | ||
4594 | /* Given a return value in `regbuf' with a type `valtype', extract and | |
4595 | copy its value into `valbuf'. */ | |
4596 | ||
46cac009 AC |
4597 | static void |
4598 | mips_eabi_extract_return_value (struct type *valtype, | |
b8b527c5 | 4599 | char regbuf[], |
46cac009 AC |
4600 | char *valbuf) |
4601 | { | |
4602 | struct return_value_word lo; | |
4603 | struct return_value_word hi; | |
4604 | return_value_location (valtype, &hi, &lo); | |
4605 | ||
4606 | memcpy (valbuf + lo.buf_offset, | |
4607 | regbuf + REGISTER_BYTE (lo.reg) + lo.reg_offset, | |
4608 | lo.len); | |
4609 | ||
4610 | if (hi.len > 0) | |
4611 | memcpy (valbuf + hi.buf_offset, | |
4612 | regbuf + REGISTER_BYTE (hi.reg) + hi.reg_offset, | |
4613 | hi.len); | |
4614 | } | |
4615 | ||
46cac009 AC |
4616 | static void |
4617 | mips_o64_extract_return_value (struct type *valtype, | |
b8b527c5 | 4618 | char regbuf[], |
46cac009 AC |
4619 | char *valbuf) |
4620 | { | |
4621 | struct return_value_word lo; | |
4622 | struct return_value_word hi; | |
4623 | return_value_location (valtype, &hi, &lo); | |
4624 | ||
4625 | memcpy (valbuf + lo.buf_offset, | |
4626 | regbuf + REGISTER_BYTE (lo.reg) + lo.reg_offset, | |
4627 | lo.len); | |
4628 | ||
4629 | if (hi.len > 0) | |
4630 | memcpy (valbuf + hi.buf_offset, | |
4631 | regbuf + REGISTER_BYTE (hi.reg) + hi.reg_offset, | |
4632 | hi.len); | |
4633 | } | |
4634 | ||
7a292a7a SS |
4635 | /* Given a return value in `valbuf' with a type `valtype', write it's |
4636 | value into the appropriate register. */ | |
4637 | ||
46cac009 AC |
4638 | static void |
4639 | mips_eabi_store_return_value (struct type *valtype, char *valbuf) | |
4640 | { | |
d9d9c31f | 4641 | char raw_buffer[MAX_REGISTER_SIZE]; |
46cac009 AC |
4642 | struct return_value_word lo; |
4643 | struct return_value_word hi; | |
4644 | return_value_location (valtype, &hi, &lo); | |
4645 | ||
4646 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4647 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
73937e03 AC |
4648 | deprecated_write_register_bytes (REGISTER_BYTE (lo.reg), raw_buffer, |
4649 | REGISTER_RAW_SIZE (lo.reg)); | |
46cac009 AC |
4650 | |
4651 | if (hi.len > 0) | |
4652 | { | |
4653 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4654 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
73937e03 AC |
4655 | deprecated_write_register_bytes (REGISTER_BYTE (hi.reg), raw_buffer, |
4656 | REGISTER_RAW_SIZE (hi.reg)); | |
46cac009 AC |
4657 | } |
4658 | } | |
4659 | ||
4660 | static void | |
cb1d2653 | 4661 | mips_o64_store_return_value (struct type *valtype, char *valbuf) |
46cac009 | 4662 | { |
d9d9c31f | 4663 | char raw_buffer[MAX_REGISTER_SIZE]; |
46cac009 AC |
4664 | struct return_value_word lo; |
4665 | struct return_value_word hi; | |
4666 | return_value_location (valtype, &hi, &lo); | |
4667 | ||
4668 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4669 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
73937e03 AC |
4670 | deprecated_write_register_bytes (REGISTER_BYTE (lo.reg), raw_buffer, |
4671 | REGISTER_RAW_SIZE (lo.reg)); | |
46cac009 AC |
4672 | |
4673 | if (hi.len > 0) | |
4674 | { | |
4675 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4676 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
73937e03 AC |
4677 | deprecated_write_register_bytes (REGISTER_BYTE (hi.reg), raw_buffer, |
4678 | REGISTER_RAW_SIZE (hi.reg)); | |
46cac009 AC |
4679 | } |
4680 | } | |
4681 | ||
cb1d2653 AC |
4682 | /* O32 ABI stuff. */ |
4683 | ||
46cac009 | 4684 | static void |
cb1d2653 AC |
4685 | mips_o32_xfer_return_value (struct type *type, |
4686 | struct regcache *regcache, | |
4687 | bfd_byte *in, const bfd_byte *out) | |
46cac009 | 4688 | { |
cb1d2653 AC |
4689 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
4690 | if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4691 | && TYPE_LENGTH (type) == 4 | |
4692 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
46cac009 | 4693 | { |
cb1d2653 AC |
4694 | /* A single-precision floating-point value. It fits in the |
4695 | least significant part of FP0. */ | |
4696 | if (mips_debug) | |
4697 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
4698 | mips_xfer_register (regcache, FP0_REGNUM, TYPE_LENGTH (type), | |
4699 | TARGET_BYTE_ORDER, in, out, 0); | |
4700 | } | |
4701 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4702 | && TYPE_LENGTH (type) == 8 | |
4703 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4704 | { | |
4705 | /* A double-precision floating-point value. It fits in the | |
4706 | least significant part of FP0/FP1 but with byte ordering | |
4707 | based on the target (???). */ | |
4708 | if (mips_debug) | |
4709 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0/$fp1\n"); | |
4710 | switch (TARGET_BYTE_ORDER) | |
4711 | { | |
4712 | case BFD_ENDIAN_LITTLE: | |
4713 | mips_xfer_register (regcache, FP0_REGNUM + 0, 4, | |
4714 | TARGET_BYTE_ORDER, in, out, 0); | |
4715 | mips_xfer_register (regcache, FP0_REGNUM + 1, 4, | |
4716 | TARGET_BYTE_ORDER, in, out, 4); | |
4717 | break; | |
4718 | case BFD_ENDIAN_BIG: | |
4719 | mips_xfer_register (regcache, FP0_REGNUM + 1, 4, | |
4720 | TARGET_BYTE_ORDER, in, out, 0); | |
4721 | mips_xfer_register (regcache, FP0_REGNUM + 0, 4, | |
4722 | TARGET_BYTE_ORDER, in, out, 4); | |
4723 | break; | |
4724 | default: | |
4725 | internal_error (__FILE__, __LINE__, "bad switch"); | |
4726 | } | |
4727 | } | |
4728 | #if 0 | |
4729 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4730 | && TYPE_NFIELDS (type) <= 2 | |
4731 | && TYPE_NFIELDS (type) >= 1 | |
4732 | && ((TYPE_NFIELDS (type) == 1 | |
4733 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4734 | == TYPE_CODE_FLT)) | |
4735 | || (TYPE_NFIELDS (type) == 2 | |
4736 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4737 | == TYPE_CODE_FLT) | |
4738 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
4739 | == TYPE_CODE_FLT))) | |
4740 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4741 | { | |
4742 | /* A struct that contains one or two floats. Each value is part | |
4743 | in the least significant part of their floating point | |
4744 | register.. */ | |
d9d9c31f | 4745 | bfd_byte reg[MAX_REGISTER_SIZE]; |
cb1d2653 AC |
4746 | int regnum; |
4747 | int field; | |
4748 | for (field = 0, regnum = FP0_REGNUM; | |
4749 | field < TYPE_NFIELDS (type); | |
4750 | field++, regnum += 2) | |
4751 | { | |
4752 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
4753 | / TARGET_CHAR_BIT); | |
4754 | if (mips_debug) | |
4755 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", offset); | |
4756 | mips_xfer_register (regcache, regnum, TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
4757 | TARGET_BYTE_ORDER, in, out, offset); | |
4758 | } | |
4759 | } | |
4760 | #endif | |
4761 | #if 0 | |
4762 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4763 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4764 | { | |
4765 | /* A structure or union. Extract the left justified value, | |
4766 | regardless of the byte order. I.e. DO NOT USE | |
4767 | mips_xfer_lower. */ | |
4768 | int offset; | |
4769 | int regnum; | |
4770 | for (offset = 0, regnum = V0_REGNUM; | |
4771 | offset < TYPE_LENGTH (type); | |
4772 | offset += REGISTER_RAW_SIZE (regnum), regnum++) | |
4773 | { | |
4774 | int xfer = REGISTER_RAW_SIZE (regnum); | |
4775 | if (offset + xfer > TYPE_LENGTH (type)) | |
4776 | xfer = TYPE_LENGTH (type) - offset; | |
4777 | if (mips_debug) | |
4778 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
4779 | offset, xfer, regnum); | |
4780 | mips_xfer_register (regcache, regnum, xfer, BFD_ENDIAN_UNKNOWN, | |
4781 | in, out, offset); | |
4782 | } | |
4783 | } | |
4784 | #endif | |
4785 | else | |
4786 | { | |
4787 | /* A scalar extract each part but least-significant-byte | |
4788 | justified. o32 thinks registers are 4 byte, regardless of | |
4789 | the ISA. mips_stack_argsize controls this. */ | |
4790 | int offset; | |
4791 | int regnum; | |
4792 | for (offset = 0, regnum = V0_REGNUM; | |
4793 | offset < TYPE_LENGTH (type); | |
4794 | offset += mips_stack_argsize (), regnum++) | |
4795 | { | |
4796 | int xfer = mips_stack_argsize (); | |
4797 | int pos = 0; | |
4798 | if (offset + xfer > TYPE_LENGTH (type)) | |
4799 | xfer = TYPE_LENGTH (type) - offset; | |
4800 | if (mips_debug) | |
4801 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4802 | offset, xfer, regnum); | |
4803 | mips_xfer_register (regcache, regnum, xfer, TARGET_BYTE_ORDER, | |
4804 | in, out, offset); | |
4805 | } | |
46cac009 AC |
4806 | } |
4807 | } | |
4808 | ||
cb1d2653 AC |
4809 | static void |
4810 | mips_o32_extract_return_value (struct type *type, | |
4811 | struct regcache *regcache, | |
ebba8386 | 4812 | void *valbuf) |
cb1d2653 AC |
4813 | { |
4814 | mips_o32_xfer_return_value (type, regcache, valbuf, NULL); | |
4815 | } | |
4816 | ||
4817 | static void | |
4818 | mips_o32_store_return_value (struct type *type, char *valbuf) | |
4819 | { | |
4820 | mips_o32_xfer_return_value (type, current_regcache, NULL, valbuf); | |
4821 | } | |
4822 | ||
4823 | /* N32/N44 ABI stuff. */ | |
4824 | ||
46cac009 | 4825 | static void |
88658117 AC |
4826 | mips_n32n64_xfer_return_value (struct type *type, |
4827 | struct regcache *regcache, | |
4828 | bfd_byte *in, const bfd_byte *out) | |
c906108c | 4829 | { |
88658117 AC |
4830 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
4831 | if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4832 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
7a292a7a | 4833 | { |
88658117 AC |
4834 | /* A floating-point value belongs in the least significant part |
4835 | of FP0. */ | |
4836 | if (mips_debug) | |
4837 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
4838 | mips_xfer_register (regcache, FP0_REGNUM, TYPE_LENGTH (type), | |
4839 | TARGET_BYTE_ORDER, in, out, 0); | |
4840 | } | |
4841 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4842 | && TYPE_NFIELDS (type) <= 2 | |
4843 | && TYPE_NFIELDS (type) >= 1 | |
4844 | && ((TYPE_NFIELDS (type) == 1 | |
4845 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4846 | == TYPE_CODE_FLT)) | |
4847 | || (TYPE_NFIELDS (type) == 2 | |
4848 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4849 | == TYPE_CODE_FLT) | |
4850 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
4851 | == TYPE_CODE_FLT))) | |
4852 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4853 | { | |
4854 | /* A struct that contains one or two floats. Each value is part | |
4855 | in the least significant part of their floating point | |
4856 | register.. */ | |
d9d9c31f | 4857 | bfd_byte reg[MAX_REGISTER_SIZE]; |
88658117 AC |
4858 | int regnum; |
4859 | int field; | |
4860 | for (field = 0, regnum = FP0_REGNUM; | |
4861 | field < TYPE_NFIELDS (type); | |
4862 | field++, regnum += 2) | |
4863 | { | |
4864 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
4865 | / TARGET_CHAR_BIT); | |
4866 | if (mips_debug) | |
4867 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", offset); | |
4868 | mips_xfer_register (regcache, regnum, TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
4869 | TARGET_BYTE_ORDER, in, out, offset); | |
4870 | } | |
7a292a7a | 4871 | } |
88658117 AC |
4872 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
4873 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4874 | { | |
4875 | /* A structure or union. Extract the left justified value, | |
4876 | regardless of the byte order. I.e. DO NOT USE | |
4877 | mips_xfer_lower. */ | |
4878 | int offset; | |
4879 | int regnum; | |
4880 | for (offset = 0, regnum = V0_REGNUM; | |
4881 | offset < TYPE_LENGTH (type); | |
4882 | offset += REGISTER_RAW_SIZE (regnum), regnum++) | |
4883 | { | |
4884 | int xfer = REGISTER_RAW_SIZE (regnum); | |
4885 | if (offset + xfer > TYPE_LENGTH (type)) | |
4886 | xfer = TYPE_LENGTH (type) - offset; | |
4887 | if (mips_debug) | |
4888 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
4889 | offset, xfer, regnum); | |
4890 | mips_xfer_register (regcache, regnum, xfer, BFD_ENDIAN_UNKNOWN, | |
4891 | in, out, offset); | |
4892 | } | |
4893 | } | |
4894 | else | |
4895 | { | |
4896 | /* A scalar extract each part but least-significant-byte | |
4897 | justified. */ | |
4898 | int offset; | |
4899 | int regnum; | |
4900 | for (offset = 0, regnum = V0_REGNUM; | |
4901 | offset < TYPE_LENGTH (type); | |
4902 | offset += REGISTER_RAW_SIZE (regnum), regnum++) | |
4903 | { | |
4904 | int xfer = REGISTER_RAW_SIZE (regnum); | |
4905 | int pos = 0; | |
4906 | if (offset + xfer > TYPE_LENGTH (type)) | |
4907 | xfer = TYPE_LENGTH (type) - offset; | |
4908 | if (mips_debug) | |
4909 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4910 | offset, xfer, regnum); | |
4911 | mips_xfer_register (regcache, regnum, xfer, TARGET_BYTE_ORDER, | |
4912 | in, out, offset); | |
4913 | } | |
4914 | } | |
4915 | } | |
4916 | ||
4917 | static void | |
4918 | mips_n32n64_extract_return_value (struct type *type, | |
4919 | struct regcache *regcache, | |
ebba8386 | 4920 | void *valbuf) |
88658117 AC |
4921 | { |
4922 | mips_n32n64_xfer_return_value (type, regcache, valbuf, NULL); | |
4923 | } | |
4924 | ||
4925 | static void | |
4926 | mips_n32n64_store_return_value (struct type *type, char *valbuf) | |
4927 | { | |
4928 | mips_n32n64_xfer_return_value (type, current_regcache, NULL, valbuf); | |
c906108c SS |
4929 | } |
4930 | ||
2f1488ce | 4931 | static CORE_ADDR |
6672060b | 4932 | mips_extract_struct_value_address (struct regcache *regcache) |
2f1488ce MS |
4933 | { |
4934 | /* FIXME: This will only work at random. The caller passes the | |
4935 | struct_return address in V0, but it is not preserved. It may | |
4936 | still be there, or this may be a random value. */ | |
77d8f2b4 MS |
4937 | LONGEST val; |
4938 | ||
4939 | regcache_cooked_read_signed (regcache, V0_REGNUM, &val); | |
6672060b | 4940 | return val; |
2f1488ce MS |
4941 | } |
4942 | ||
c906108c SS |
4943 | /* Exported procedure: Is PC in the signal trampoline code */ |
4944 | ||
102182a9 MS |
4945 | static int |
4946 | mips_pc_in_sigtramp (CORE_ADDR pc, char *ignore) | |
c906108c SS |
4947 | { |
4948 | if (sigtramp_address == 0) | |
4949 | fixup_sigtramp (); | |
4950 | return (pc >= sigtramp_address && pc < sigtramp_end); | |
4951 | } | |
4952 | ||
a5ea2558 AC |
4953 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
4954 | used for all MIPS-specific commands. */ | |
4955 | ||
a5ea2558 | 4956 | static void |
acdb74a0 | 4957 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
4958 | { |
4959 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
4960 | } | |
4961 | ||
a5ea2558 | 4962 | static void |
acdb74a0 | 4963 | set_mips_command (char *args, int from_tty) |
a5ea2558 AC |
4964 | { |
4965 | printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
4966 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); | |
4967 | } | |
4968 | ||
c906108c SS |
4969 | /* Commands to show/set the MIPS FPU type. */ |
4970 | ||
c906108c | 4971 | static void |
acdb74a0 | 4972 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 4973 | { |
c906108c SS |
4974 | char *fpu; |
4975 | switch (MIPS_FPU_TYPE) | |
4976 | { | |
4977 | case MIPS_FPU_SINGLE: | |
4978 | fpu = "single-precision"; | |
4979 | break; | |
4980 | case MIPS_FPU_DOUBLE: | |
4981 | fpu = "double-precision"; | |
4982 | break; | |
4983 | case MIPS_FPU_NONE: | |
4984 | fpu = "absent (none)"; | |
4985 | break; | |
93d56215 AC |
4986 | default: |
4987 | internal_error (__FILE__, __LINE__, "bad switch"); | |
c906108c SS |
4988 | } |
4989 | if (mips_fpu_type_auto) | |
4990 | printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
4991 | fpu); | |
4992 | else | |
4993 | printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n", | |
4994 | fpu); | |
4995 | } | |
4996 | ||
4997 | ||
c906108c | 4998 | static void |
acdb74a0 | 4999 | set_mipsfpu_command (char *args, int from_tty) |
c906108c SS |
5000 | { |
5001 | printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
5002 | show_mipsfpu_command (args, from_tty); | |
5003 | } | |
5004 | ||
c906108c | 5005 | static void |
acdb74a0 | 5006 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c SS |
5007 | { |
5008 | mips_fpu_type = MIPS_FPU_SINGLE; | |
5009 | mips_fpu_type_auto = 0; | |
9e364162 | 5010 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_SINGLE; |
c906108c SS |
5011 | } |
5012 | ||
c906108c | 5013 | static void |
acdb74a0 | 5014 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c SS |
5015 | { |
5016 | mips_fpu_type = MIPS_FPU_DOUBLE; | |
5017 | mips_fpu_type_auto = 0; | |
9e364162 | 5018 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_DOUBLE; |
c906108c SS |
5019 | } |
5020 | ||
c906108c | 5021 | static void |
acdb74a0 | 5022 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c SS |
5023 | { |
5024 | mips_fpu_type = MIPS_FPU_NONE; | |
5025 | mips_fpu_type_auto = 0; | |
9e364162 | 5026 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_NONE; |
c906108c SS |
5027 | } |
5028 | ||
c906108c | 5029 | static void |
acdb74a0 | 5030 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
5031 | { |
5032 | mips_fpu_type_auto = 1; | |
5033 | } | |
5034 | ||
5035 | /* Command to set the processor type. */ | |
5036 | ||
5037 | void | |
acdb74a0 | 5038 | mips_set_processor_type_command (char *args, int from_tty) |
c906108c SS |
5039 | { |
5040 | int i; | |
5041 | ||
5042 | if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0') | |
5043 | { | |
5044 | printf_unfiltered ("The known MIPS processor types are as follows:\n\n"); | |
5045 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
5046 | printf_unfiltered ("%s\n", mips_processor_type_table[i].name); | |
5047 | ||
5048 | /* Restore the value. */ | |
4fcf66da | 5049 | tmp_mips_processor_type = xstrdup (mips_processor_type); |
c906108c SS |
5050 | |
5051 | return; | |
5052 | } | |
c5aa993b | 5053 | |
c906108c SS |
5054 | if (!mips_set_processor_type (tmp_mips_processor_type)) |
5055 | { | |
5056 | error ("Unknown processor type `%s'.", tmp_mips_processor_type); | |
5057 | /* Restore its value. */ | |
4fcf66da | 5058 | tmp_mips_processor_type = xstrdup (mips_processor_type); |
c906108c SS |
5059 | } |
5060 | } | |
5061 | ||
5062 | static void | |
acdb74a0 | 5063 | mips_show_processor_type_command (char *args, int from_tty) |
c906108c SS |
5064 | { |
5065 | } | |
5066 | ||
5067 | /* Modify the actual processor type. */ | |
5068 | ||
5a89d8aa | 5069 | static int |
acdb74a0 | 5070 | mips_set_processor_type (char *str) |
c906108c | 5071 | { |
1012bd0e | 5072 | int i; |
c906108c SS |
5073 | |
5074 | if (str == NULL) | |
5075 | return 0; | |
5076 | ||
5077 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
5078 | { | |
5079 | if (strcasecmp (str, mips_processor_type_table[i].name) == 0) | |
5080 | { | |
5081 | mips_processor_type = str; | |
cce74817 | 5082 | mips_processor_reg_names = mips_processor_type_table[i].regnames; |
c906108c | 5083 | return 1; |
c906108c SS |
5084 | /* FIXME tweak fpu flag too */ |
5085 | } | |
5086 | } | |
5087 | ||
5088 | return 0; | |
5089 | } | |
5090 | ||
5091 | /* Attempt to identify the particular processor model by reading the | |
5092 | processor id. */ | |
5093 | ||
5094 | char * | |
acdb74a0 | 5095 | mips_read_processor_type (void) |
c906108c SS |
5096 | { |
5097 | CORE_ADDR prid; | |
5098 | ||
5099 | prid = read_register (PRID_REGNUM); | |
5100 | ||
5101 | if ((prid & ~0xf) == 0x700) | |
c5aa993b | 5102 | return savestring ("r3041", strlen ("r3041")); |
c906108c SS |
5103 | |
5104 | return NULL; | |
5105 | } | |
5106 | ||
5107 | /* Just like reinit_frame_cache, but with the right arguments to be | |
5108 | callable as an sfunc. */ | |
5109 | ||
5110 | static void | |
acdb74a0 AC |
5111 | reinit_frame_cache_sfunc (char *args, int from_tty, |
5112 | struct cmd_list_element *c) | |
c906108c SS |
5113 | { |
5114 | reinit_frame_cache (); | |
5115 | } | |
5116 | ||
5117 | int | |
acdb74a0 | 5118 | gdb_print_insn_mips (bfd_vma memaddr, disassemble_info *info) |
c906108c SS |
5119 | { |
5120 | mips_extra_func_info_t proc_desc; | |
5121 | ||
5122 | /* Search for the function containing this address. Set the low bit | |
5123 | of the address when searching, in case we were given an even address | |
5124 | that is the start of a 16-bit function. If we didn't do this, | |
5125 | the search would fail because the symbol table says the function | |
5126 | starts at an odd address, i.e. 1 byte past the given address. */ | |
5127 | memaddr = ADDR_BITS_REMOVE (memaddr); | |
95404a3e | 5128 | proc_desc = non_heuristic_proc_desc (make_mips16_addr (memaddr), NULL); |
c906108c SS |
5129 | |
5130 | /* Make an attempt to determine if this is a 16-bit function. If | |
5131 | the procedure descriptor exists and the address therein is odd, | |
5132 | it's definitely a 16-bit function. Otherwise, we have to just | |
5133 | guess that if the address passed in is odd, it's 16-bits. */ | |
5134 | if (proc_desc) | |
361d1df0 | 5135 | info->mach = pc_is_mips16 (PROC_LOW_ADDR (proc_desc)) ? |
95404a3e | 5136 | bfd_mach_mips16 : 0; |
c906108c | 5137 | else |
361d1df0 | 5138 | info->mach = pc_is_mips16 (memaddr) ? |
95404a3e | 5139 | bfd_mach_mips16 : 0; |
c906108c SS |
5140 | |
5141 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 5142 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 5143 | |
c906108c | 5144 | /* Call the appropriate disassembler based on the target endian-ness. */ |
d7449b42 | 5145 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
5146 | return print_insn_big_mips (memaddr, info); |
5147 | else | |
5148 | return print_insn_little_mips (memaddr, info); | |
5149 | } | |
5150 | ||
c906108c SS |
5151 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program |
5152 | counter value to determine whether a 16- or 32-bit breakpoint should be | |
5153 | used. It returns a pointer to a string of bytes that encode a breakpoint | |
5154 | instruction, stores the length of the string to *lenptr, and adjusts pc | |
5155 | (if necessary) to point to the actual memory location where the | |
5156 | breakpoint should be inserted. */ | |
5157 | ||
f7ab6ec6 | 5158 | static const unsigned char * |
acdb74a0 | 5159 | mips_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr) |
c906108c | 5160 | { |
d7449b42 | 5161 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
5162 | { |
5163 | if (pc_is_mips16 (*pcptr)) | |
5164 | { | |
aaab4dba | 5165 | static unsigned char mips16_big_breakpoint[] = {0xe8, 0xa5}; |
95404a3e | 5166 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5167 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
5168 | return mips16_big_breakpoint; |
5169 | } | |
5170 | else | |
5171 | { | |
aaab4dba AC |
5172 | /* The IDT board uses an unusual breakpoint value, and |
5173 | sometimes gets confused when it sees the usual MIPS | |
5174 | breakpoint instruction. */ | |
5175 | static unsigned char big_breakpoint[] = {0, 0x5, 0, 0xd}; | |
5176 | static unsigned char pmon_big_breakpoint[] = {0, 0, 0, 0xd}; | |
5177 | static unsigned char idt_big_breakpoint[] = {0, 0, 0x0a, 0xd}; | |
c906108c | 5178 | |
c5aa993b | 5179 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
5180 | |
5181 | if (strcmp (target_shortname, "mips") == 0) | |
5182 | return idt_big_breakpoint; | |
5183 | else if (strcmp (target_shortname, "ddb") == 0 | |
5184 | || strcmp (target_shortname, "pmon") == 0 | |
5185 | || strcmp (target_shortname, "lsi") == 0) | |
5186 | return pmon_big_breakpoint; | |
5187 | else | |
5188 | return big_breakpoint; | |
5189 | } | |
5190 | } | |
5191 | else | |
5192 | { | |
5193 | if (pc_is_mips16 (*pcptr)) | |
5194 | { | |
aaab4dba | 5195 | static unsigned char mips16_little_breakpoint[] = {0xa5, 0xe8}; |
95404a3e | 5196 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5197 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
5198 | return mips16_little_breakpoint; |
5199 | } | |
5200 | else | |
5201 | { | |
aaab4dba AC |
5202 | static unsigned char little_breakpoint[] = {0xd, 0, 0x5, 0}; |
5203 | static unsigned char pmon_little_breakpoint[] = {0xd, 0, 0, 0}; | |
5204 | static unsigned char idt_little_breakpoint[] = {0xd, 0x0a, 0, 0}; | |
c906108c | 5205 | |
c5aa993b | 5206 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
5207 | |
5208 | if (strcmp (target_shortname, "mips") == 0) | |
5209 | return idt_little_breakpoint; | |
5210 | else if (strcmp (target_shortname, "ddb") == 0 | |
5211 | || strcmp (target_shortname, "pmon") == 0 | |
5212 | || strcmp (target_shortname, "lsi") == 0) | |
5213 | return pmon_little_breakpoint; | |
5214 | else | |
5215 | return little_breakpoint; | |
5216 | } | |
5217 | } | |
5218 | } | |
5219 | ||
5220 | /* If PC is in a mips16 call or return stub, return the address of the target | |
5221 | PC, which is either the callee or the caller. There are several | |
5222 | cases which must be handled: | |
5223 | ||
5224 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 5225 | target PC is in $31 ($ra). |
c906108c | 5226 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 5227 | and the target PC is in $2. |
c906108c | 5228 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
5229 | before the jal instruction, this is effectively a call stub |
5230 | and the the target PC is in $2. Otherwise this is effectively | |
5231 | a return stub and the target PC is in $18. | |
c906108c SS |
5232 | |
5233 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
5234 | gory details. | |
5235 | ||
5236 | This function implements the SKIP_TRAMPOLINE_CODE macro. | |
c5aa993b | 5237 | */ |
c906108c | 5238 | |
757a7cc6 | 5239 | static CORE_ADDR |
acdb74a0 | 5240 | mips_skip_stub (CORE_ADDR pc) |
c906108c SS |
5241 | { |
5242 | char *name; | |
5243 | CORE_ADDR start_addr; | |
5244 | ||
5245 | /* Find the starting address and name of the function containing the PC. */ | |
5246 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
5247 | return 0; | |
5248 | ||
5249 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
5250 | target PC is in $31 ($ra). */ | |
5251 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5252 | || strcmp (name, "__mips16_ret_df") == 0) | |
6c997a34 | 5253 | return read_signed_register (RA_REGNUM); |
c906108c SS |
5254 | |
5255 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5256 | { | |
5257 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
5258 | and the target PC is in $2. */ | |
5259 | if (name[19] >= '0' && name[19] <= '9') | |
6c997a34 | 5260 | return read_signed_register (2); |
c906108c SS |
5261 | |
5262 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
5263 | before the jal instruction, this is effectively a call stub |
5264 | and the the target PC is in $2. Otherwise this is effectively | |
5265 | a return stub and the target PC is in $18. */ | |
c906108c SS |
5266 | else if (name[19] == 's' || name[19] == 'd') |
5267 | { | |
5268 | if (pc == start_addr) | |
5269 | { | |
5270 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
5271 | stub. Such a stub for a function bar might have a name |
5272 | like __fn_stub_bar, and might look like this: | |
5273 | mfc1 $4,$f13 | |
5274 | mfc1 $5,$f12 | |
5275 | mfc1 $6,$f15 | |
5276 | mfc1 $7,$f14 | |
5277 | la $1,bar (becomes a lui/addiu pair) | |
5278 | jr $1 | |
5279 | So scan down to the lui/addi and extract the target | |
5280 | address from those two instructions. */ | |
c906108c | 5281 | |
6c997a34 | 5282 | CORE_ADDR target_pc = read_signed_register (2); |
c906108c SS |
5283 | t_inst inst; |
5284 | int i; | |
5285 | ||
5286 | /* See if the name of the target function is __fn_stub_*. */ | |
5287 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == 0) | |
5288 | return target_pc; | |
5289 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
5290 | && strcmp (name, "etext") != 0 | |
5291 | && strcmp (name, "_etext") != 0) | |
5292 | return target_pc; | |
5293 | ||
5294 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
5295 | The limit on the search is arbitrarily set to 20 |
5296 | instructions. FIXME. */ | |
c906108c SS |
5297 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN) |
5298 | { | |
c5aa993b JM |
5299 | inst = mips_fetch_instruction (target_pc); |
5300 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
5301 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
5302 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
5303 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
5304 | } |
5305 | ||
5306 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
5307 | return target_pc; | |
5308 | } | |
5309 | else | |
5310 | /* This is the 'return' part of a call stub. The return | |
5311 | address is in $r18. */ | |
6c997a34 | 5312 | return read_signed_register (18); |
c906108c SS |
5313 | } |
5314 | } | |
c5aa993b | 5315 | return 0; /* not a stub */ |
c906108c SS |
5316 | } |
5317 | ||
5318 | ||
5319 | /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline). | |
5320 | This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */ | |
5321 | ||
757a7cc6 | 5322 | static int |
acdb74a0 | 5323 | mips_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
5324 | { |
5325 | CORE_ADDR start_addr; | |
5326 | ||
5327 | /* Find the starting address of the function containing the PC. If the | |
5328 | caller didn't give us a name, look it up at the same time. */ | |
5329 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0) | |
5330 | return 0; | |
5331 | ||
5332 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5333 | { | |
5334 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */ | |
5335 | if (name[19] >= '0' && name[19] <= '9') | |
5336 | return 1; | |
5337 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b | 5338 | before the jal instruction, this is effectively a call stub. */ |
c906108c SS |
5339 | else if (name[19] == 's' || name[19] == 'd') |
5340 | return pc == start_addr; | |
5341 | } | |
5342 | ||
c5aa993b | 5343 | return 0; /* not a stub */ |
c906108c SS |
5344 | } |
5345 | ||
5346 | ||
5347 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
5348 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
5349 | ||
e41b17f0 | 5350 | static int |
acdb74a0 | 5351 | mips_in_return_stub (CORE_ADDR pc, char *name) |
c906108c SS |
5352 | { |
5353 | CORE_ADDR start_addr; | |
5354 | ||
5355 | /* Find the starting address of the function containing the PC. */ | |
5356 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
5357 | return 0; | |
5358 | ||
5359 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */ | |
5360 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5361 | || strcmp (name, "__mips16_ret_df") == 0) | |
5362 | return 1; | |
5363 | ||
5364 | /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start, | |
c5aa993b | 5365 | i.e. after the jal instruction, this is effectively a return stub. */ |
c906108c SS |
5366 | if (strncmp (name, "__mips16_call_stub_", 19) == 0 |
5367 | && (name[19] == 's' || name[19] == 'd') | |
5368 | && pc != start_addr) | |
5369 | return 1; | |
5370 | ||
c5aa993b | 5371 | return 0; /* not a stub */ |
c906108c SS |
5372 | } |
5373 | ||
5374 | ||
5375 | /* Return non-zero if the PC is in a library helper function that should | |
5376 | be ignored. This implements the IGNORE_HELPER_CALL macro. */ | |
5377 | ||
5378 | int | |
acdb74a0 | 5379 | mips_ignore_helper (CORE_ADDR pc) |
c906108c SS |
5380 | { |
5381 | char *name; | |
5382 | ||
5383 | /* Find the starting address and name of the function containing the PC. */ | |
5384 | if (find_pc_partial_function (pc, &name, NULL, NULL) == 0) | |
5385 | return 0; | |
5386 | ||
5387 | /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function | |
5388 | that we want to ignore. */ | |
5389 | return (strcmp (name, "__mips16_ret_sf") == 0 | |
5390 | || strcmp (name, "__mips16_ret_df") == 0); | |
5391 | } | |
5392 | ||
5393 | ||
5394 | /* Return a location where we can set a breakpoint that will be hit | |
5395 | when an inferior function call returns. This is normally the | |
5396 | program's entry point. Executables that don't have an entry | |
5397 | point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS | |
5398 | whose address is the location where the breakpoint should be placed. */ | |
5399 | ||
f7ab6ec6 | 5400 | static CORE_ADDR |
acdb74a0 | 5401 | mips_call_dummy_address (void) |
c906108c SS |
5402 | { |
5403 | struct minimal_symbol *sym; | |
5404 | ||
5405 | sym = lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL, NULL); | |
5406 | if (sym) | |
5407 | return SYMBOL_VALUE_ADDRESS (sym); | |
5408 | else | |
5409 | return entry_point_address (); | |
5410 | } | |
5411 | ||
5412 | ||
47a8d4ba AC |
5413 | /* When debugging a 64 MIPS target running a 32 bit ABI, the size of |
5414 | the register stored on the stack (32) is different to its real raw | |
5415 | size (64). The below ensures that registers are fetched from the | |
5416 | stack using their ABI size and then stored into the RAW_BUFFER | |
5417 | using their raw size. | |
5418 | ||
5419 | The alternative to adding this function would be to add an ABI | |
5420 | macro - REGISTER_STACK_SIZE(). */ | |
5421 | ||
5422 | static void | |
acdb74a0 | 5423 | mips_get_saved_register (char *raw_buffer, |
795e1e11 | 5424 | int *optimizedp, |
acdb74a0 AC |
5425 | CORE_ADDR *addrp, |
5426 | struct frame_info *frame, | |
5427 | int regnum, | |
795e1e11 | 5428 | enum lval_type *lvalp) |
47a8d4ba | 5429 | { |
795e1e11 AC |
5430 | CORE_ADDR addrx; |
5431 | enum lval_type lvalx; | |
5432 | int optimizedx; | |
47a8d4ba AC |
5433 | |
5434 | if (!target_has_registers) | |
5435 | error ("No registers."); | |
5436 | ||
795e1e11 AC |
5437 | /* Make certain that all needed parameters are present. */ |
5438 | if (addrp == NULL) | |
5439 | addrp = &addrx; | |
5440 | if (lvalp == NULL) | |
5441 | lvalp = &lvalx; | |
5442 | if (optimizedp == NULL) | |
5443 | optimizedp = &optimizedx; | |
248de703 AC |
5444 | deprecated_unwind_get_saved_register (raw_buffer, optimizedp, addrp, frame, |
5445 | regnum, lvalp); | |
795e1e11 AC |
5446 | /* FIXME: cagney/2002-09-13: This is just so bad. The MIPS should |
5447 | have a pseudo register range that correspons to the ABI's, rather | |
5448 | than the ISA's, view of registers. These registers would then | |
5449 | implicitly describe their size and hence could be used without | |
5450 | the below munging. */ | |
5451 | if ((*lvalp) == lval_memory) | |
47a8d4ba | 5452 | { |
47a8d4ba AC |
5453 | if (raw_buffer != NULL) |
5454 | { | |
47a8d4ba | 5455 | if (regnum < 32) |
795e1e11 AC |
5456 | { |
5457 | /* Only MIPS_SAVED_REGSIZE bytes of GP registers are | |
5458 | saved. */ | |
5459 | LONGEST val = read_memory_integer ((*addrp), MIPS_SAVED_REGSIZE); | |
fbd9dcd3 | 5460 | store_unsigned_integer (raw_buffer, REGISTER_RAW_SIZE (regnum), val); |
795e1e11 | 5461 | } |
47a8d4ba AC |
5462 | } |
5463 | } | |
47a8d4ba | 5464 | } |
2acceee2 | 5465 | |
f7b9e9fc AC |
5466 | /* Immediately after a function call, return the saved pc. |
5467 | Can't always go through the frames for this because on some machines | |
5468 | the new frame is not set up until the new function executes | |
5469 | some instructions. */ | |
5470 | ||
5471 | static CORE_ADDR | |
5472 | mips_saved_pc_after_call (struct frame_info *frame) | |
5473 | { | |
6c997a34 | 5474 | return read_signed_register (RA_REGNUM); |
f7b9e9fc AC |
5475 | } |
5476 | ||
5477 | ||
88c72b7d AC |
5478 | /* Convert a dbx stab register number (from `r' declaration) to a gdb |
5479 | REGNUM */ | |
5480 | ||
5481 | static int | |
5482 | mips_stab_reg_to_regnum (int num) | |
5483 | { | |
2f38ef89 | 5484 | if (num >= 0 && num < 32) |
88c72b7d | 5485 | return num; |
2f38ef89 | 5486 | else if (num >= 38 && num < 70) |
88c72b7d | 5487 | return num + FP0_REGNUM - 38; |
040b99fd KB |
5488 | else if (num == 70) |
5489 | return HI_REGNUM; | |
5490 | else if (num == 71) | |
5491 | return LO_REGNUM; | |
2f38ef89 KB |
5492 | else |
5493 | { | |
5494 | /* This will hopefully (eventually) provoke a warning. Should | |
5495 | we be calling complaint() here? */ | |
5496 | return NUM_REGS + NUM_PSEUDO_REGS; | |
5497 | } | |
88c72b7d AC |
5498 | } |
5499 | ||
2f38ef89 KB |
5500 | |
5501 | /* Convert a dwarf, dwarf2, or ecoff register number to a gdb REGNUM */ | |
88c72b7d AC |
5502 | |
5503 | static int | |
2f38ef89 | 5504 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num) |
88c72b7d | 5505 | { |
2f38ef89 | 5506 | if (num >= 0 && num < 32) |
88c72b7d | 5507 | return num; |
2f38ef89 | 5508 | else if (num >= 32 && num < 64) |
88c72b7d | 5509 | return num + FP0_REGNUM - 32; |
040b99fd KB |
5510 | else if (num == 64) |
5511 | return HI_REGNUM; | |
5512 | else if (num == 65) | |
5513 | return LO_REGNUM; | |
2f38ef89 KB |
5514 | else |
5515 | { | |
5516 | /* This will hopefully (eventually) provoke a warning. Should | |
5517 | we be calling complaint() here? */ | |
5518 | return NUM_REGS + NUM_PSEUDO_REGS; | |
5519 | } | |
88c72b7d AC |
5520 | } |
5521 | ||
2f38ef89 | 5522 | |
fc0c74b1 AC |
5523 | /* Convert an integer into an address. By first converting the value |
5524 | into a pointer and then extracting it signed, the address is | |
5525 | guarenteed to be correctly sign extended. */ | |
5526 | ||
5527 | static CORE_ADDR | |
5528 | mips_integer_to_address (struct type *type, void *buf) | |
5529 | { | |
5530 | char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5531 | LONGEST val = unpack_long (type, buf); | |
5532 | store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val); | |
5533 | return extract_signed_integer (tmp, | |
5534 | TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5535 | } | |
5536 | ||
caaa3122 DJ |
5537 | static void |
5538 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
5539 | { | |
5540 | enum mips_abi *abip = (enum mips_abi *) obj; | |
5541 | const char *name = bfd_get_section_name (abfd, sect); | |
5542 | ||
5543 | if (*abip != MIPS_ABI_UNKNOWN) | |
5544 | return; | |
5545 | ||
5546 | if (strncmp (name, ".mdebug.", 8) != 0) | |
5547 | return; | |
5548 | ||
5549 | if (strcmp (name, ".mdebug.abi32") == 0) | |
5550 | *abip = MIPS_ABI_O32; | |
5551 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
5552 | *abip = MIPS_ABI_N32; | |
62a49b2c | 5553 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 5554 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
5555 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
5556 | *abip = MIPS_ABI_O64; | |
5557 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
5558 | *abip = MIPS_ABI_EABI32; | |
5559 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
5560 | *abip = MIPS_ABI_EABI64; | |
5561 | else | |
5562 | warning ("unsupported ABI %s.", name + 8); | |
5563 | } | |
5564 | ||
2e4ebe70 DJ |
5565 | static enum mips_abi |
5566 | global_mips_abi (void) | |
5567 | { | |
5568 | int i; | |
5569 | ||
5570 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
5571 | if (mips_abi_strings[i] == mips_abi_string) | |
5572 | return (enum mips_abi) i; | |
5573 | ||
5574 | internal_error (__FILE__, __LINE__, | |
5575 | "unknown ABI string"); | |
5576 | } | |
5577 | ||
c2d11a7d | 5578 | static struct gdbarch * |
acdb74a0 AC |
5579 | mips_gdbarch_init (struct gdbarch_info info, |
5580 | struct gdbarch_list *arches) | |
c2d11a7d | 5581 | { |
c2d11a7d JM |
5582 | struct gdbarch *gdbarch; |
5583 | struct gdbarch_tdep *tdep; | |
5584 | int elf_flags; | |
2e4ebe70 | 5585 | enum mips_abi mips_abi, found_abi, wanted_abi; |
c2d11a7d | 5586 | |
1d06468c EZ |
5587 | /* Reset the disassembly info, in case it was set to something |
5588 | non-default. */ | |
810ecf9f AC |
5589 | deprecated_tm_print_insn_info.flavour = bfd_target_unknown_flavour; |
5590 | deprecated_tm_print_insn_info.arch = bfd_arch_unknown; | |
5591 | deprecated_tm_print_insn_info.mach = 0; | |
1d06468c | 5592 | |
70f80edf JT |
5593 | elf_flags = 0; |
5594 | ||
5595 | if (info.abfd) | |
5596 | { | |
5597 | /* First of all, extract the elf_flags, if available. */ | |
5598 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5599 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
70f80edf | 5600 | } |
c2d11a7d | 5601 | |
102182a9 | 5602 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
5603 | switch ((elf_flags & EF_MIPS_ABI)) |
5604 | { | |
5605 | case E_MIPS_ABI_O32: | |
5606 | mips_abi = MIPS_ABI_O32; | |
5607 | break; | |
5608 | case E_MIPS_ABI_O64: | |
5609 | mips_abi = MIPS_ABI_O64; | |
5610 | break; | |
5611 | case E_MIPS_ABI_EABI32: | |
5612 | mips_abi = MIPS_ABI_EABI32; | |
5613 | break; | |
5614 | case E_MIPS_ABI_EABI64: | |
4a7f7ba8 | 5615 | mips_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
5616 | break; |
5617 | default: | |
acdb74a0 AC |
5618 | if ((elf_flags & EF_MIPS_ABI2)) |
5619 | mips_abi = MIPS_ABI_N32; | |
5620 | else | |
5621 | mips_abi = MIPS_ABI_UNKNOWN; | |
0dadbba0 AC |
5622 | break; |
5623 | } | |
acdb74a0 | 5624 | |
caaa3122 DJ |
5625 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
5626 | if (mips_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) | |
5627 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &mips_abi); | |
5628 | ||
2e4ebe70 DJ |
5629 | /* If we have no bfd, then mips_abi will still be MIPS_ABI_UNKNOWN. |
5630 | Use the ABI from the last architecture if there is one. */ | |
5631 | if (info.abfd == NULL && arches != NULL) | |
5632 | mips_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
5633 | ||
32a6503c | 5634 | /* Try the architecture for any hint of the correct ABI. */ |
bf64bfd6 AC |
5635 | if (mips_abi == MIPS_ABI_UNKNOWN |
5636 | && info.bfd_arch_info != NULL | |
5637 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5638 | { | |
5639 | switch (info.bfd_arch_info->mach) | |
5640 | { | |
5641 | case bfd_mach_mips3900: | |
5642 | mips_abi = MIPS_ABI_EABI32; | |
5643 | break; | |
5644 | case bfd_mach_mips4100: | |
5645 | case bfd_mach_mips5000: | |
5646 | mips_abi = MIPS_ABI_EABI64; | |
5647 | break; | |
1d06468c EZ |
5648 | case bfd_mach_mips8000: |
5649 | case bfd_mach_mips10000: | |
32a6503c KB |
5650 | /* On Irix, ELF64 executables use the N64 ABI. The |
5651 | pseudo-sections which describe the ABI aren't present | |
5652 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
5653 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
5654 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
5655 | mips_abi = MIPS_ABI_N64; | |
5656 | else | |
5657 | mips_abi = MIPS_ABI_N32; | |
1d06468c | 5658 | break; |
bf64bfd6 AC |
5659 | } |
5660 | } | |
2e4ebe70 | 5661 | |
2e4ebe70 DJ |
5662 | if (mips_abi == MIPS_ABI_UNKNOWN) |
5663 | mips_abi = MIPS_ABI_O32; | |
5664 | ||
5665 | /* Now that we have found what the ABI for this binary would be, | |
5666 | check whether the user is overriding it. */ | |
5667 | found_abi = mips_abi; | |
5668 | wanted_abi = global_mips_abi (); | |
5669 | if (wanted_abi != MIPS_ABI_UNKNOWN) | |
5670 | mips_abi = wanted_abi; | |
5671 | ||
810ecf9f | 5672 | /* We have to set deprecated_tm_print_insn_info before looking for a |
2252e863 AO |
5673 | pre-existing architecture, otherwise we may return before we get |
5674 | a chance to set it up. */ | |
5675 | if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) | |
5676 | { | |
5677 | /* Set up the disassembler info, so that we get the right | |
5678 | register names from libopcodes. */ | |
5679 | if (mips_abi == MIPS_ABI_N32) | |
810ecf9f | 5680 | deprecated_tm_print_insn_info.disassembler_options = "gpr-names=n32"; |
2252e863 | 5681 | else |
810ecf9f AC |
5682 | deprecated_tm_print_insn_info.disassembler_options = "gpr-names=64"; |
5683 | deprecated_tm_print_insn_info.flavour = bfd_target_elf_flavour; | |
5684 | deprecated_tm_print_insn_info.arch = bfd_arch_mips; | |
2252e863 AO |
5685 | if (info.bfd_arch_info != NULL |
5686 | && info.bfd_arch_info->arch == bfd_arch_mips | |
5687 | && info.bfd_arch_info->mach) | |
810ecf9f | 5688 | deprecated_tm_print_insn_info.mach = info.bfd_arch_info->mach; |
2252e863 | 5689 | else |
810ecf9f | 5690 | deprecated_tm_print_insn_info.mach = bfd_mach_mips8000; |
2252e863 AO |
5691 | } |
5692 | else | |
5693 | /* This string is not recognized explicitly by the disassembler, | |
5694 | but it tells the disassembler to not try to guess the ABI from | |
5695 | the bfd elf headers, such that, if the user overrides the ABI | |
5696 | of a program linked as NewABI, the disassembly will follow the | |
5697 | register naming conventions specified by the user. */ | |
810ecf9f | 5698 | deprecated_tm_print_insn_info.disassembler_options = "gpr-names=32"; |
2252e863 | 5699 | |
4b9b3959 AC |
5700 | if (gdbarch_debug) |
5701 | { | |
5702 | fprintf_unfiltered (gdb_stdlog, | |
9ace0497 | 5703 | "mips_gdbarch_init: elf_flags = 0x%08x\n", |
4b9b3959 | 5704 | elf_flags); |
4b9b3959 AC |
5705 | fprintf_unfiltered (gdb_stdlog, |
5706 | "mips_gdbarch_init: mips_abi = %d\n", | |
5707 | mips_abi); | |
2e4ebe70 DJ |
5708 | fprintf_unfiltered (gdb_stdlog, |
5709 | "mips_gdbarch_init: found_mips_abi = %d\n", | |
5710 | found_abi); | |
4b9b3959 | 5711 | } |
0dadbba0 | 5712 | |
c2d11a7d JM |
5713 | /* try to find a pre-existing architecture */ |
5714 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
5715 | arches != NULL; | |
5716 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
5717 | { | |
5718 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 5719 | using. */ |
9103eae0 | 5720 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 5721 | continue; |
9103eae0 | 5722 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 5723 | continue; |
4be87837 | 5724 | return arches->gdbarch; |
c2d11a7d JM |
5725 | } |
5726 | ||
102182a9 | 5727 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
5728 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
5729 | gdbarch = gdbarch_alloc (&info, tdep); | |
5730 | tdep->elf_flags = elf_flags; | |
5731 | ||
102182a9 | 5732 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
5733 | set_gdbarch_short_bit (gdbarch, 16); |
5734 | set_gdbarch_int_bit (gdbarch, 32); | |
5735 | set_gdbarch_float_bit (gdbarch, 32); | |
5736 | set_gdbarch_double_bit (gdbarch, 64); | |
5737 | set_gdbarch_long_double_bit (gdbarch, 64); | |
9c04cab7 | 5738 | set_gdbarch_deprecated_register_raw_size (gdbarch, mips_register_raw_size); |
2e4ebe70 | 5739 | tdep->found_abi = found_abi; |
0dadbba0 | 5740 | tdep->mips_abi = mips_abi; |
1d06468c | 5741 | |
f7ab6ec6 MS |
5742 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
5743 | mips_elf_make_msymbol_special); | |
5744 | ||
4be87837 | 5745 | if (info.osabi == GDB_OSABI_IRIX) |
fe29b929 KB |
5746 | set_gdbarch_num_regs (gdbarch, 71); |
5747 | else | |
5748 | set_gdbarch_num_regs (gdbarch, 90); | |
5749 | ||
0dadbba0 | 5750 | switch (mips_abi) |
c2d11a7d | 5751 | { |
0dadbba0 | 5752 | case MIPS_ABI_O32: |
25ab4790 | 5753 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
ebba8386 | 5754 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_o32_store_return_value); |
cb1d2653 | 5755 | set_gdbarch_extract_return_value (gdbarch, mips_o32_extract_return_value); |
a5ea2558 | 5756 | tdep->mips_default_saved_regsize = 4; |
0dadbba0 | 5757 | tdep->mips_default_stack_argsize = 4; |
c2d11a7d | 5758 | tdep->mips_fp_register_double = 0; |
acdb74a0 AC |
5759 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
5760 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1; | |
5213ab06 | 5761 | tdep->gdb_target_is_mips64 = 0; |
4014092b | 5762 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5763 | set_gdbarch_long_bit (gdbarch, 32); |
5764 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5765 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8b389c40 MS |
5766 | set_gdbarch_reg_struct_has_addr (gdbarch, |
5767 | mips_o32_reg_struct_has_addr); | |
cb811fe7 | 5768 | set_gdbarch_use_struct_convention (gdbarch, |
1fd35568 | 5769 | always_use_struct_convention); |
c2d11a7d | 5770 | break; |
0dadbba0 | 5771 | case MIPS_ABI_O64: |
25ab4790 | 5772 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
ebba8386 | 5773 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_o64_store_return_value); |
46cac009 | 5774 | set_gdbarch_deprecated_extract_return_value (gdbarch, mips_o64_extract_return_value); |
a5ea2558 | 5775 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 | 5776 | tdep->mips_default_stack_argsize = 8; |
c2d11a7d | 5777 | tdep->mips_fp_register_double = 1; |
acdb74a0 AC |
5778 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
5779 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1; | |
5213ab06 | 5780 | tdep->gdb_target_is_mips64 = 1; |
361d1df0 | 5781 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5782 | set_gdbarch_long_bit (gdbarch, 32); |
5783 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5784 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8b389c40 MS |
5785 | set_gdbarch_reg_struct_has_addr (gdbarch, |
5786 | mips_o32_reg_struct_has_addr); | |
b060cbea | 5787 | set_gdbarch_use_struct_convention (gdbarch, always_use_struct_convention); |
c2d11a7d | 5788 | break; |
0dadbba0 | 5789 | case MIPS_ABI_EABI32: |
25ab4790 | 5790 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
ebba8386 | 5791 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_eabi_store_return_value); |
46cac009 | 5792 | set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value); |
a5ea2558 | 5793 | tdep->mips_default_saved_regsize = 4; |
0dadbba0 | 5794 | tdep->mips_default_stack_argsize = 4; |
c2d11a7d | 5795 | tdep->mips_fp_register_double = 0; |
acdb74a0 AC |
5796 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
5797 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1; | |
5213ab06 | 5798 | tdep->gdb_target_is_mips64 = 0; |
4014092b | 5799 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5800 | set_gdbarch_long_bit (gdbarch, 32); |
5801 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5802 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8b389c40 MS |
5803 | set_gdbarch_reg_struct_has_addr (gdbarch, |
5804 | mips_eabi_reg_struct_has_addr); | |
cb811fe7 MS |
5805 | set_gdbarch_use_struct_convention (gdbarch, |
5806 | mips_eabi_use_struct_convention); | |
c2d11a7d | 5807 | break; |
0dadbba0 | 5808 | case MIPS_ABI_EABI64: |
25ab4790 | 5809 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
ebba8386 | 5810 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_eabi_store_return_value); |
46cac009 | 5811 | set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value); |
a5ea2558 | 5812 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 | 5813 | tdep->mips_default_stack_argsize = 8; |
c2d11a7d | 5814 | tdep->mips_fp_register_double = 1; |
acdb74a0 AC |
5815 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
5816 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1; | |
5213ab06 | 5817 | tdep->gdb_target_is_mips64 = 1; |
4014092b | 5818 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5819 | set_gdbarch_long_bit (gdbarch, 64); |
5820 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5821 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8b389c40 MS |
5822 | set_gdbarch_reg_struct_has_addr (gdbarch, |
5823 | mips_eabi_reg_struct_has_addr); | |
cb811fe7 MS |
5824 | set_gdbarch_use_struct_convention (gdbarch, |
5825 | mips_eabi_use_struct_convention); | |
c2d11a7d | 5826 | break; |
0dadbba0 | 5827 | case MIPS_ABI_N32: |
25ab4790 | 5828 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
ebba8386 | 5829 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_n32n64_store_return_value); |
88658117 | 5830 | set_gdbarch_extract_return_value (gdbarch, mips_n32n64_extract_return_value); |
63db5580 | 5831 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 AC |
5832 | tdep->mips_default_stack_argsize = 8; |
5833 | tdep->mips_fp_register_double = 1; | |
acdb74a0 AC |
5834 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
5835 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1; | |
6acdf5c7 | 5836 | tdep->gdb_target_is_mips64 = 1; |
4014092b | 5837 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
5838 | set_gdbarch_long_bit (gdbarch, 32); |
5839 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5840 | set_gdbarch_long_long_bit (gdbarch, 64); | |
cb811fe7 MS |
5841 | set_gdbarch_use_struct_convention (gdbarch, |
5842 | mips_n32n64_use_struct_convention); | |
8b389c40 MS |
5843 | set_gdbarch_reg_struct_has_addr (gdbarch, |
5844 | mips_n32n64_reg_struct_has_addr); | |
28d169de KB |
5845 | break; |
5846 | case MIPS_ABI_N64: | |
25ab4790 | 5847 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
ebba8386 | 5848 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_n32n64_store_return_value); |
88658117 | 5849 | set_gdbarch_extract_return_value (gdbarch, mips_n32n64_extract_return_value); |
28d169de KB |
5850 | tdep->mips_default_saved_regsize = 8; |
5851 | tdep->mips_default_stack_argsize = 8; | |
5852 | tdep->mips_fp_register_double = 1; | |
5853 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; | |
5854 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1; | |
28d169de KB |
5855 | tdep->gdb_target_is_mips64 = 1; |
5856 | tdep->default_mask_address_p = 0; | |
5857 | set_gdbarch_long_bit (gdbarch, 64); | |
5858 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5859 | set_gdbarch_long_long_bit (gdbarch, 64); | |
cb811fe7 MS |
5860 | set_gdbarch_use_struct_convention (gdbarch, |
5861 | mips_n32n64_use_struct_convention); | |
8b389c40 MS |
5862 | set_gdbarch_reg_struct_has_addr (gdbarch, |
5863 | mips_n32n64_reg_struct_has_addr); | |
0dadbba0 | 5864 | break; |
c2d11a7d | 5865 | default: |
2e4ebe70 DJ |
5866 | internal_error (__FILE__, __LINE__, |
5867 | "unknown ABI in switch"); | |
c2d11a7d JM |
5868 | } |
5869 | ||
a5ea2558 AC |
5870 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
5871 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
5872 | comment: | |
5873 | ||
5874 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
5875 | flag in object files because to do so would make it impossible to | |
102182a9 | 5876 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 5877 | unnecessarily restrictive. |
361d1df0 | 5878 | |
a5ea2558 AC |
5879 | We could solve this problem by adding "-gp32" multilibs to gcc, |
5880 | but to set this flag before gcc is built with such multilibs will | |
5881 | break too many systems.'' | |
5882 | ||
5883 | But even more unhelpfully, the default linker output target for | |
5884 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
5885 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 5886 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
5887 | this flag to detect 32-bit mode would do the wrong thing given |
5888 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 5889 | as 32-bit programs by default. */ |
a5ea2558 | 5890 | |
c2d11a7d JM |
5891 | /* enable/disable the MIPS FPU */ |
5892 | if (!mips_fpu_type_auto) | |
5893 | tdep->mips_fpu_type = mips_fpu_type; | |
5894 | else if (info.bfd_arch_info != NULL | |
5895 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5896 | switch (info.bfd_arch_info->mach) | |
5897 | { | |
b0069a17 | 5898 | case bfd_mach_mips3900: |
c2d11a7d | 5899 | case bfd_mach_mips4100: |
ed9a39eb | 5900 | case bfd_mach_mips4111: |
c2d11a7d JM |
5901 | tdep->mips_fpu_type = MIPS_FPU_NONE; |
5902 | break; | |
bf64bfd6 AC |
5903 | case bfd_mach_mips4650: |
5904 | tdep->mips_fpu_type = MIPS_FPU_SINGLE; | |
5905 | break; | |
c2d11a7d JM |
5906 | default: |
5907 | tdep->mips_fpu_type = MIPS_FPU_DOUBLE; | |
5908 | break; | |
5909 | } | |
5910 | else | |
5911 | tdep->mips_fpu_type = MIPS_FPU_DOUBLE; | |
5912 | ||
5913 | /* MIPS version of register names. NOTE: At present the MIPS | |
5914 | register name management is part way between the old - | |
5915 | #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr). | |
102182a9 | 5916 | Further work on it is required. */ |
18f81521 MS |
5917 | /* NOTE: many targets (esp. embedded) do not go thru the |
5918 | gdbarch_register_name vector at all, instead bypassing it | |
5919 | by defining REGISTER_NAMES. */ | |
c2d11a7d | 5920 | set_gdbarch_register_name (gdbarch, mips_register_name); |
6c997a34 | 5921 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
c2d11a7d | 5922 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); |
0ba6dca9 | 5923 | set_gdbarch_deprecated_target_read_fp (gdbarch, mips_read_sp); /* Draft FRAME base. */ |
bcb0cc15 | 5924 | set_gdbarch_read_sp (gdbarch, mips_read_sp); |
c2d11a7d | 5925 | |
102182a9 MS |
5926 | /* Add/remove bits from an address. The MIPS needs be careful to |
5927 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
5928 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
5929 | ||
10312cc4 | 5930 | /* There's a mess in stack frame creation. See comments in |
2ca6c561 AC |
5931 | blockframe.c near reference to DEPRECATED_INIT_FRAME_PC_FIRST. */ |
5932 | set_gdbarch_deprecated_init_frame_pc_first (gdbarch, mips_init_frame_pc_first); | |
a5afb99f | 5933 | set_gdbarch_deprecated_init_frame_pc (gdbarch, init_frame_pc_noop); |
10312cc4 | 5934 | |
102182a9 | 5935 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 5936 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
2f38ef89 KB |
5937 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum); |
5938 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
5939 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
88c72b7d | 5940 | |
c2d11a7d | 5941 | /* Initialize a frame */ |
e0f7ec59 | 5942 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, mips_find_saved_regs); |
e9582e71 | 5943 | set_gdbarch_deprecated_init_extra_frame_info (gdbarch, mips_init_extra_frame_info); |
c2d11a7d JM |
5944 | |
5945 | /* MIPS version of CALL_DUMMY */ | |
5946 | ||
c2d11a7d | 5947 | set_gdbarch_call_dummy_address (gdbarch, mips_call_dummy_address); |
749b82f6 | 5948 | set_gdbarch_deprecated_pop_frame (gdbarch, mips_pop_frame); |
dc604539 | 5949 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
a59fe496 | 5950 | set_gdbarch_deprecated_save_dummy_frame_tos (gdbarch, generic_save_dummy_frame_tos); |
781a750d AC |
5951 | set_gdbarch_deprecated_register_convertible (gdbarch, mips_register_convertible); |
5952 | set_gdbarch_deprecated_register_convert_to_virtual (gdbarch, mips_register_convert_to_virtual); | |
5953 | set_gdbarch_deprecated_register_convert_to_raw (gdbarch, mips_register_convert_to_raw); | |
d05285fa | 5954 | |
618ce49f | 5955 | set_gdbarch_deprecated_frame_chain (gdbarch, mips_frame_chain); |
b5d1566e MS |
5956 | set_gdbarch_frameless_function_invocation (gdbarch, |
5957 | generic_frameless_function_invocation_not); | |
8bedc050 | 5958 | set_gdbarch_deprecated_frame_saved_pc (gdbarch, mips_frame_saved_pc); |
b5d1566e MS |
5959 | set_gdbarch_frame_args_skip (gdbarch, 0); |
5960 | ||
129c1cd6 | 5961 | set_gdbarch_deprecated_get_saved_register (gdbarch, mips_get_saved_register); |
c2d11a7d | 5962 | |
f7b9e9fc AC |
5963 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
5964 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
5965 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
f7b9e9fc AC |
5966 | |
5967 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
6913c89a | 5968 | set_gdbarch_deprecated_saved_pc_after_call (gdbarch, mips_saved_pc_after_call); |
f7b9e9fc | 5969 | |
fc0c74b1 AC |
5970 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
5971 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
5972 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 5973 | |
102182a9 MS |
5974 | set_gdbarch_function_start_offset (gdbarch, 0); |
5975 | ||
32a6503c KB |
5976 | /* There are MIPS targets which do not yet use this since they still |
5977 | define REGISTER_VIRTUAL_TYPE. */ | |
9c04cab7 | 5978 | set_gdbarch_deprecated_register_virtual_type (gdbarch, mips_register_virtual_type); |
78fde5f8 | 5979 | |
e11c53d2 | 5980 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
102182a9 | 5981 | set_gdbarch_pc_in_sigtramp (gdbarch, mips_pc_in_sigtramp); |
bf1f5b4c | 5982 | |
70f80edf | 5983 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
4be87837 | 5984 | gdbarch_init_osabi (info, gdbarch); |
70f80edf | 5985 | |
2f1488ce MS |
5986 | set_gdbarch_extract_struct_value_address (gdbarch, |
5987 | mips_extract_struct_value_address); | |
757a7cc6 MS |
5988 | |
5989 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_stub); | |
5990 | ||
5991 | set_gdbarch_in_solib_call_trampoline (gdbarch, mips_in_call_stub); | |
e41b17f0 | 5992 | set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); |
757a7cc6 | 5993 | |
4b9b3959 AC |
5994 | return gdbarch; |
5995 | } | |
5996 | ||
2e4ebe70 DJ |
5997 | static void |
5998 | mips_abi_update (char *ignore_args, int from_tty, | |
5999 | struct cmd_list_element *c) | |
6000 | { | |
6001 | struct gdbarch_info info; | |
6002 | ||
6003 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
6004 | mips_gdbarch_init will take care of the rest. */ | |
6005 | gdbarch_info_init (&info); | |
6006 | gdbarch_update_p (info); | |
6007 | } | |
6008 | ||
ad188201 KB |
6009 | /* Print out which MIPS ABI is in use. */ |
6010 | ||
6011 | static void | |
6012 | show_mips_abi (char *ignore_args, int from_tty) | |
6013 | { | |
6014 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips) | |
6015 | printf_filtered ( | |
6016 | "The MIPS ABI is unknown because the current architecture is not MIPS.\n"); | |
6017 | else | |
6018 | { | |
6019 | enum mips_abi global_abi = global_mips_abi (); | |
6020 | enum mips_abi actual_abi = mips_abi (current_gdbarch); | |
6021 | const char *actual_abi_str = mips_abi_strings[actual_abi]; | |
6022 | ||
6023 | if (global_abi == MIPS_ABI_UNKNOWN) | |
6024 | printf_filtered ("The MIPS ABI is set automatically (currently \"%s\").\n", | |
6025 | actual_abi_str); | |
6026 | else if (global_abi == actual_abi) | |
6027 | printf_filtered ( | |
6028 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6029 | actual_abi_str); | |
6030 | else | |
6031 | { | |
6032 | /* Probably shouldn't happen... */ | |
6033 | printf_filtered ( | |
6034 | "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n", | |
6035 | actual_abi_str, | |
6036 | mips_abi_strings[global_abi]); | |
6037 | } | |
6038 | } | |
6039 | } | |
6040 | ||
4b9b3959 AC |
6041 | static void |
6042 | mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
6043 | { | |
6044 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
6045 | if (tdep != NULL) | |
c2d11a7d | 6046 | { |
acdb74a0 AC |
6047 | int ef_mips_arch; |
6048 | int ef_mips_32bitmode; | |
6049 | /* determine the ISA */ | |
6050 | switch (tdep->elf_flags & EF_MIPS_ARCH) | |
6051 | { | |
6052 | case E_MIPS_ARCH_1: | |
6053 | ef_mips_arch = 1; | |
6054 | break; | |
6055 | case E_MIPS_ARCH_2: | |
6056 | ef_mips_arch = 2; | |
6057 | break; | |
6058 | case E_MIPS_ARCH_3: | |
6059 | ef_mips_arch = 3; | |
6060 | break; | |
6061 | case E_MIPS_ARCH_4: | |
93d56215 | 6062 | ef_mips_arch = 4; |
acdb74a0 AC |
6063 | break; |
6064 | default: | |
93d56215 | 6065 | ef_mips_arch = 0; |
acdb74a0 AC |
6066 | break; |
6067 | } | |
6068 | /* determine the size of a pointer */ | |
6069 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); | |
4b9b3959 AC |
6070 | fprintf_unfiltered (file, |
6071 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 6072 | tdep->elf_flags); |
4b9b3959 | 6073 | fprintf_unfiltered (file, |
acdb74a0 AC |
6074 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
6075 | ef_mips_32bitmode); | |
6076 | fprintf_unfiltered (file, | |
6077 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
6078 | ef_mips_arch); | |
6079 | fprintf_unfiltered (file, | |
6080 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6081 | tdep->mips_abi, | |
2e4ebe70 | 6082 | mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
6083 | fprintf_unfiltered (file, |
6084 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
6085 | mips_mask_address_p (), | |
6086 | tdep->default_mask_address_p); | |
c2d11a7d | 6087 | } |
4b9b3959 AC |
6088 | fprintf_unfiltered (file, |
6089 | "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n", | |
6090 | FP_REGISTER_DOUBLE); | |
6091 | fprintf_unfiltered (file, | |
6092 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
6093 | MIPS_DEFAULT_FPU_TYPE, | |
6094 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6095 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6096 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6097 | : "???")); | |
6098 | fprintf_unfiltered (file, | |
6099 | "mips_dump_tdep: MIPS_EABI = %d\n", | |
6100 | MIPS_EABI); | |
6101 | fprintf_unfiltered (file, | |
acdb74a0 AC |
6102 | "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n", |
6103 | MIPS_LAST_FP_ARG_REGNUM, | |
6104 | MIPS_LAST_FP_ARG_REGNUM - FPA0_REGNUM + 1); | |
4b9b3959 AC |
6105 | fprintf_unfiltered (file, |
6106 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
6107 | MIPS_FPU_TYPE, | |
6108 | (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6109 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6110 | : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6111 | : "???")); | |
6112 | fprintf_unfiltered (file, | |
6113 | "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n", | |
6114 | MIPS_DEFAULT_SAVED_REGSIZE); | |
4b9b3959 AC |
6115 | fprintf_unfiltered (file, |
6116 | "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n", | |
6117 | FP_REGISTER_DOUBLE); | |
4b9b3959 AC |
6118 | fprintf_unfiltered (file, |
6119 | "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n", | |
6120 | MIPS_DEFAULT_STACK_ARGSIZE); | |
6121 | fprintf_unfiltered (file, | |
6122 | "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n", | |
6123 | MIPS_STACK_ARGSIZE); | |
6124 | fprintf_unfiltered (file, | |
6125 | "mips_dump_tdep: MIPS_REGSIZE = %d\n", | |
6126 | MIPS_REGSIZE); | |
2475bac3 AC |
6127 | fprintf_unfiltered (file, |
6128 | "mips_dump_tdep: A0_REGNUM = %d\n", | |
6129 | A0_REGNUM); | |
6130 | fprintf_unfiltered (file, | |
6131 | "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n", | |
6132 | XSTRING (ADDR_BITS_REMOVE(ADDR))); | |
6133 | fprintf_unfiltered (file, | |
6134 | "mips_dump_tdep: ATTACH_DETACH # %s\n", | |
6135 | XSTRING (ATTACH_DETACH)); | |
6136 | fprintf_unfiltered (file, | |
6137 | "mips_dump_tdep: BADVADDR_REGNUM = %d\n", | |
6138 | BADVADDR_REGNUM); | |
2475bac3 AC |
6139 | fprintf_unfiltered (file, |
6140 | "mips_dump_tdep: CAUSE_REGNUM = %d\n", | |
6141 | CAUSE_REGNUM); | |
2475bac3 AC |
6142 | fprintf_unfiltered (file, |
6143 | "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n", | |
6144 | XSTRING (DWARF_REG_TO_REGNUM (REGNUM))); | |
6145 | fprintf_unfiltered (file, | |
6146 | "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n", | |
6147 | XSTRING (ECOFF_REG_TO_REGNUM (REGNUM))); | |
2475bac3 AC |
6148 | fprintf_unfiltered (file, |
6149 | "mips_dump_tdep: FCRCS_REGNUM = %d\n", | |
6150 | FCRCS_REGNUM); | |
6151 | fprintf_unfiltered (file, | |
6152 | "mips_dump_tdep: FCRIR_REGNUM = %d\n", | |
6153 | FCRIR_REGNUM); | |
6154 | fprintf_unfiltered (file, | |
6155 | "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n", | |
6156 | FIRST_EMBED_REGNUM); | |
6157 | fprintf_unfiltered (file, | |
6158 | "mips_dump_tdep: FPA0_REGNUM = %d\n", | |
6159 | FPA0_REGNUM); | |
6160 | fprintf_unfiltered (file, | |
6161 | "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n", | |
6162 | GDB_TARGET_IS_MIPS64); | |
2475bac3 AC |
6163 | fprintf_unfiltered (file, |
6164 | "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n", | |
6165 | XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT)); | |
6166 | fprintf_unfiltered (file, | |
6167 | "mips_dump_tdep: HI_REGNUM = %d\n", | |
6168 | HI_REGNUM); | |
2475bac3 AC |
6169 | fprintf_unfiltered (file, |
6170 | "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n", | |
6171 | XSTRING (IGNORE_HELPER_CALL (PC))); | |
2475bac3 AC |
6172 | fprintf_unfiltered (file, |
6173 | "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n", | |
6174 | XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME))); | |
6175 | fprintf_unfiltered (file, | |
6176 | "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n", | |
6177 | XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME))); | |
2475bac3 AC |
6178 | fprintf_unfiltered (file, |
6179 | "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n", | |
6180 | LAST_EMBED_REGNUM); | |
2475bac3 AC |
6181 | fprintf_unfiltered (file, |
6182 | "mips_dump_tdep: LO_REGNUM = %d\n", | |
6183 | LO_REGNUM); | |
6184 | #ifdef MACHINE_CPROC_FP_OFFSET | |
6185 | fprintf_unfiltered (file, | |
6186 | "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n", | |
6187 | MACHINE_CPROC_FP_OFFSET); | |
6188 | #endif | |
6189 | #ifdef MACHINE_CPROC_PC_OFFSET | |
6190 | fprintf_unfiltered (file, | |
6191 | "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n", | |
6192 | MACHINE_CPROC_PC_OFFSET); | |
6193 | #endif | |
6194 | #ifdef MACHINE_CPROC_SP_OFFSET | |
6195 | fprintf_unfiltered (file, | |
6196 | "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n", | |
6197 | MACHINE_CPROC_SP_OFFSET); | |
6198 | #endif | |
2475bac3 AC |
6199 | fprintf_unfiltered (file, |
6200 | "mips_dump_tdep: MIPS16_INSTLEN = %d\n", | |
6201 | MIPS16_INSTLEN); | |
2475bac3 AC |
6202 | fprintf_unfiltered (file, |
6203 | "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n"); | |
6204 | fprintf_unfiltered (file, | |
6205 | "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n"); | |
6206 | fprintf_unfiltered (file, | |
6207 | "mips_dump_tdep: MIPS_INSTLEN = %d\n", | |
6208 | MIPS_INSTLEN); | |
6209 | fprintf_unfiltered (file, | |
acdb74a0 AC |
6210 | "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n", |
6211 | MIPS_LAST_ARG_REGNUM, | |
6212 | MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1); | |
2475bac3 AC |
6213 | fprintf_unfiltered (file, |
6214 | "mips_dump_tdep: MIPS_NUMREGS = %d\n", | |
6215 | MIPS_NUMREGS); | |
6216 | fprintf_unfiltered (file, | |
6217 | "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n"); | |
6218 | fprintf_unfiltered (file, | |
6219 | "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n", | |
6220 | MIPS_SAVED_REGSIZE); | |
2475bac3 AC |
6221 | fprintf_unfiltered (file, |
6222 | "mips_dump_tdep: OP_LDFPR = used?\n"); | |
6223 | fprintf_unfiltered (file, | |
6224 | "mips_dump_tdep: OP_LDGPR = used?\n"); | |
2475bac3 AC |
6225 | fprintf_unfiltered (file, |
6226 | "mips_dump_tdep: PRID_REGNUM = %d\n", | |
6227 | PRID_REGNUM); | |
6228 | fprintf_unfiltered (file, | |
6229 | "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n", | |
6230 | XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME))); | |
6231 | fprintf_unfiltered (file, | |
6232 | "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n"); | |
6233 | fprintf_unfiltered (file, | |
6234 | "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n"); | |
6235 | fprintf_unfiltered (file, | |
6236 | "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n"); | |
6237 | fprintf_unfiltered (file, | |
6238 | "mips_dump_tdep: PROC_FRAME_REG = function?\n"); | |
6239 | fprintf_unfiltered (file, | |
6240 | "mips_dump_tdep: PROC_FREG_MASK = function?\n"); | |
6241 | fprintf_unfiltered (file, | |
6242 | "mips_dump_tdep: PROC_FREG_OFFSET = function?\n"); | |
6243 | fprintf_unfiltered (file, | |
6244 | "mips_dump_tdep: PROC_HIGH_ADDR = function?\n"); | |
6245 | fprintf_unfiltered (file, | |
6246 | "mips_dump_tdep: PROC_LOW_ADDR = function?\n"); | |
6247 | fprintf_unfiltered (file, | |
6248 | "mips_dump_tdep: PROC_PC_REG = function?\n"); | |
6249 | fprintf_unfiltered (file, | |
6250 | "mips_dump_tdep: PROC_REG_MASK = function?\n"); | |
6251 | fprintf_unfiltered (file, | |
6252 | "mips_dump_tdep: PROC_REG_OFFSET = function?\n"); | |
6253 | fprintf_unfiltered (file, | |
6254 | "mips_dump_tdep: PROC_SYMBOL = function?\n"); | |
6255 | fprintf_unfiltered (file, | |
6256 | "mips_dump_tdep: PS_REGNUM = %d\n", | |
6257 | PS_REGNUM); | |
2475bac3 AC |
6258 | fprintf_unfiltered (file, |
6259 | "mips_dump_tdep: RA_REGNUM = %d\n", | |
6260 | RA_REGNUM); | |
6261 | fprintf_unfiltered (file, | |
6262 | "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n", | |
6263 | XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM, VALTYPE, RAW_BUFFER))); | |
6264 | fprintf_unfiltered (file, | |
6265 | "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n", | |
6266 | XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM, VALTYPE, RAW_BUFFER))); | |
6267 | fprintf_unfiltered (file, | |
6268 | "mips_dump_tdep: REGISTER_NAMES = delete?\n"); | |
6269 | fprintf_unfiltered (file, | |
6270 | "mips_dump_tdep: ROUND_DOWN = function?\n"); | |
6271 | fprintf_unfiltered (file, | |
6272 | "mips_dump_tdep: ROUND_UP = function?\n"); | |
6273 | #ifdef SAVED_BYTES | |
6274 | fprintf_unfiltered (file, | |
6275 | "mips_dump_tdep: SAVED_BYTES = %d\n", | |
6276 | SAVED_BYTES); | |
6277 | #endif | |
6278 | #ifdef SAVED_FP | |
6279 | fprintf_unfiltered (file, | |
6280 | "mips_dump_tdep: SAVED_FP = %d\n", | |
6281 | SAVED_FP); | |
6282 | #endif | |
6283 | #ifdef SAVED_PC | |
6284 | fprintf_unfiltered (file, | |
6285 | "mips_dump_tdep: SAVED_PC = %d\n", | |
6286 | SAVED_PC); | |
6287 | #endif | |
6288 | fprintf_unfiltered (file, | |
6289 | "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n", | |
6290 | XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS))); | |
6291 | fprintf_unfiltered (file, | |
6292 | "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n"); | |
6293 | fprintf_unfiltered (file, | |
6294 | "mips_dump_tdep: SIGFRAME_BASE = %d\n", | |
6295 | SIGFRAME_BASE); | |
6296 | fprintf_unfiltered (file, | |
6297 | "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n", | |
6298 | SIGFRAME_FPREGSAVE_OFF); | |
6299 | fprintf_unfiltered (file, | |
6300 | "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n", | |
6301 | SIGFRAME_PC_OFF); | |
6302 | fprintf_unfiltered (file, | |
6303 | "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n", | |
6304 | SIGFRAME_REGSAVE_OFF); | |
6305 | fprintf_unfiltered (file, | |
6306 | "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n", | |
6307 | SIGFRAME_REG_SIZE); | |
6308 | fprintf_unfiltered (file, | |
6309 | "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n", | |
6310 | XSTRING (SKIP_TRAMPOLINE_CODE (PC))); | |
6311 | fprintf_unfiltered (file, | |
6312 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n", | |
6313 | XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P))); | |
6314 | fprintf_unfiltered (file, | |
b0ed3589 AC |
6315 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n", |
6316 | SOFTWARE_SINGLE_STEP_P ()); | |
2475bac3 AC |
6317 | fprintf_unfiltered (file, |
6318 | "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n", | |
6319 | XSTRING (STAB_REG_TO_REGNUM (REGNUM))); | |
6320 | #ifdef STACK_END_ADDR | |
6321 | fprintf_unfiltered (file, | |
6322 | "mips_dump_tdep: STACK_END_ADDR = %d\n", | |
6323 | STACK_END_ADDR); | |
6324 | #endif | |
6325 | fprintf_unfiltered (file, | |
6326 | "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n", | |
6327 | XSTRING (STEP_SKIPS_DELAY (PC))); | |
6328 | fprintf_unfiltered (file, | |
6329 | "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n", | |
6330 | STEP_SKIPS_DELAY_P); | |
6331 | fprintf_unfiltered (file, | |
6332 | "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n", | |
6333 | XSTRING (STOPPED_BY_WATCHPOINT (WS))); | |
6334 | fprintf_unfiltered (file, | |
6335 | "mips_dump_tdep: T9_REGNUM = %d\n", | |
6336 | T9_REGNUM); | |
6337 | fprintf_unfiltered (file, | |
6338 | "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n"); | |
6339 | fprintf_unfiltered (file, | |
6340 | "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n", | |
6341 | XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE,CNT,OTHERTYPE))); | |
6342 | fprintf_unfiltered (file, | |
6343 | "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n", | |
6344 | XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS)); | |
2475bac3 AC |
6345 | #ifdef TRACE_CLEAR |
6346 | fprintf_unfiltered (file, | |
6347 | "mips_dump_tdep: TRACE_CLEAR # %s\n", | |
6348 | XSTRING (TRACE_CLEAR (THREAD, STATE))); | |
6349 | #endif | |
6350 | #ifdef TRACE_FLAVOR | |
6351 | fprintf_unfiltered (file, | |
6352 | "mips_dump_tdep: TRACE_FLAVOR = %d\n", | |
6353 | TRACE_FLAVOR); | |
6354 | #endif | |
6355 | #ifdef TRACE_FLAVOR_SIZE | |
6356 | fprintf_unfiltered (file, | |
6357 | "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n", | |
6358 | TRACE_FLAVOR_SIZE); | |
6359 | #endif | |
6360 | #ifdef TRACE_SET | |
6361 | fprintf_unfiltered (file, | |
6362 | "mips_dump_tdep: TRACE_SET # %s\n", | |
6363 | XSTRING (TRACE_SET (X,STATE))); | |
6364 | #endif | |
2475bac3 AC |
6365 | #ifdef UNUSED_REGNUM |
6366 | fprintf_unfiltered (file, | |
6367 | "mips_dump_tdep: UNUSED_REGNUM = %d\n", | |
6368 | UNUSED_REGNUM); | |
6369 | #endif | |
6370 | fprintf_unfiltered (file, | |
6371 | "mips_dump_tdep: V0_REGNUM = %d\n", | |
6372 | V0_REGNUM); | |
6373 | fprintf_unfiltered (file, | |
6374 | "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n", | |
6375 | (long) VM_MIN_ADDRESS); | |
6376 | #ifdef VX_NUM_REGS | |
6377 | fprintf_unfiltered (file, | |
6378 | "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n", | |
6379 | VX_NUM_REGS); | |
6380 | #endif | |
6381 | fprintf_unfiltered (file, | |
6382 | "mips_dump_tdep: ZERO_REGNUM = %d\n", | |
6383 | ZERO_REGNUM); | |
6384 | fprintf_unfiltered (file, | |
6385 | "mips_dump_tdep: _PROC_MAGIC_ = %d\n", | |
6386 | _PROC_MAGIC_); | |
c2d11a7d JM |
6387 | } |
6388 | ||
a78f21af AC |
6389 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
6390 | ||
c906108c | 6391 | void |
acdb74a0 | 6392 | _initialize_mips_tdep (void) |
c906108c SS |
6393 | { |
6394 | static struct cmd_list_element *mipsfpulist = NULL; | |
6395 | struct cmd_list_element *c; | |
6396 | ||
2e4ebe70 DJ |
6397 | mips_abi_string = mips_abi_strings [MIPS_ABI_UNKNOWN]; |
6398 | if (MIPS_ABI_LAST + 1 | |
6399 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
6400 | internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync"); | |
6401 | ||
4b9b3959 | 6402 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
d7a27068 AC |
6403 | if (!deprecated_tm_print_insn) /* Someone may have already set it */ |
6404 | deprecated_tm_print_insn = gdb_print_insn_mips; | |
c906108c | 6405 | |
a5ea2558 AC |
6406 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
6407 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
6408 | "Various MIPS specific commands.", | |
6409 | &setmipscmdlist, "set mips ", 0, &setlist); | |
6410 | ||
6411 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
6412 | "Various MIPS specific commands.", | |
6413 | &showmipscmdlist, "show mips ", 0, &showlist); | |
6414 | ||
6415 | /* Allow the user to override the saved register size. */ | |
6416 | add_show_from_set (add_set_enum_cmd ("saved-gpreg-size", | |
1ed2a135 AC |
6417 | class_obscure, |
6418 | size_enums, | |
6419 | &mips_saved_regsize_string, "\ | |
a5ea2558 AC |
6420 | Set size of general purpose registers saved on the stack.\n\ |
6421 | This option can be set to one of:\n\ | |
6422 | 32 - Force GDB to treat saved GP registers as 32-bit\n\ | |
6423 | 64 - Force GDB to treat saved GP registers as 64-bit\n\ | |
6424 | auto - Allow GDB to use the target's default setting or autodetect the\n\ | |
6425 | saved GP register size from information contained in the executable.\n\ | |
6426 | (default: auto)", | |
1ed2a135 | 6427 | &setmipscmdlist), |
a5ea2558 AC |
6428 | &showmipscmdlist); |
6429 | ||
d929b26f AC |
6430 | /* Allow the user to override the argument stack size. */ |
6431 | add_show_from_set (add_set_enum_cmd ("stack-arg-size", | |
6432 | class_obscure, | |
6433 | size_enums, | |
1ed2a135 | 6434 | &mips_stack_argsize_string, "\ |
d929b26f AC |
6435 | Set the amount of stack space reserved for each argument.\n\ |
6436 | This option can be set to one of:\n\ | |
6437 | 32 - Force GDB to allocate 32-bit chunks per argument\n\ | |
6438 | 64 - Force GDB to allocate 64-bit chunks per argument\n\ | |
6439 | auto - Allow GDB to determine the correct setting from the current\n\ | |
6440 | target and executable (default)", | |
6441 | &setmipscmdlist), | |
6442 | &showmipscmdlist); | |
6443 | ||
2e4ebe70 DJ |
6444 | /* Allow the user to override the ABI. */ |
6445 | c = add_set_enum_cmd | |
6446 | ("abi", class_obscure, mips_abi_strings, &mips_abi_string, | |
6447 | "Set the ABI used by this program.\n" | |
6448 | "This option can be set to one of:\n" | |
6449 | " auto - the default ABI associated with the current binary\n" | |
6450 | " o32\n" | |
6451 | " o64\n" | |
6452 | " n32\n" | |
f3a7b3a5 | 6453 | " n64\n" |
2e4ebe70 DJ |
6454 | " eabi32\n" |
6455 | " eabi64", | |
6456 | &setmipscmdlist); | |
2e4ebe70 | 6457 | set_cmd_sfunc (c, mips_abi_update); |
ad188201 KB |
6458 | add_cmd ("abi", class_obscure, show_mips_abi, |
6459 | "Show ABI in use by MIPS target", &showmipscmdlist); | |
2e4ebe70 | 6460 | |
c906108c SS |
6461 | /* Let the user turn off floating point and set the fence post for |
6462 | heuristic_proc_start. */ | |
6463 | ||
6464 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
6465 | "Set use of MIPS floating-point coprocessor.", | |
6466 | &mipsfpulist, "set mipsfpu ", 0, &setlist); | |
6467 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
6468 | "Select single-precision MIPS floating-point coprocessor.", | |
6469 | &mipsfpulist); | |
6470 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
8e1a459b | 6471 | "Select double-precision MIPS floating-point coprocessor.", |
c906108c SS |
6472 | &mipsfpulist); |
6473 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
6474 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
6475 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
6476 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
6477 | "Select no MIPS floating-point coprocessor.", | |
6478 | &mipsfpulist); | |
6479 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); | |
6480 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
6481 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
6482 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
6483 | "Select MIPS floating-point coprocessor automatically.", | |
6484 | &mipsfpulist); | |
6485 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
6486 | "Show current use of MIPS floating-point coprocessor target.", | |
6487 | &showlist); | |
6488 | ||
c906108c SS |
6489 | /* We really would like to have both "0" and "unlimited" work, but |
6490 | command.c doesn't deal with that. So make it a var_zinteger | |
6491 | because the user can always use "999999" or some such for unlimited. */ | |
6492 | c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger, | |
6493 | (char *) &heuristic_fence_post, | |
6494 | "\ | |
6495 | Set the distance searched for the start of a function.\n\ | |
6496 | If you are debugging a stripped executable, GDB needs to search through the\n\ | |
6497 | program for the start of a function. This command sets the distance of the\n\ | |
6498 | search. The only need to set it is when debugging a stripped executable.", | |
6499 | &setlist); | |
6500 | /* We need to throw away the frame cache when we set this, since it | |
6501 | might change our ability to get backtraces. */ | |
9f60d481 | 6502 | set_cmd_sfunc (c, reinit_frame_cache_sfunc); |
c906108c SS |
6503 | add_show_from_set (c, &showlist); |
6504 | ||
6505 | /* Allow the user to control whether the upper bits of 64-bit | |
6506 | addresses should be zeroed. */ | |
e9e68a56 AC |
6507 | add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, "\ |
6508 | Set zeroing of upper 32 bits of 64-bit addresses.\n\ | |
6509 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ | |
6510 | allow GDB to determine the correct value.\n", "\ | |
6511 | Show zeroing of upper 32 bits of 64-bit addresses.", | |
6512 | NULL, show_mask_address, | |
6513 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
6514 | |
6515 | /* Allow the user to control the size of 32 bit registers within the | |
6516 | raw remote packet. */ | |
6517 | add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs", | |
6518 | class_obscure, | |
6519 | var_boolean, | |
6520 | (char *)&mips64_transfers_32bit_regs_p, "\ | |
6521 | Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\ | |
6522 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ | |
6523 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
6524 | 64 bits for others. Use \"off\" to disable compatibility mode", | |
6525 | &setlist), | |
6526 | &showlist); | |
9ace0497 AC |
6527 | |
6528 | /* Debug this files internals. */ | |
6529 | add_show_from_set (add_set_cmd ("mips", class_maintenance, var_zinteger, | |
6530 | &mips_debug, "Set mips debugging.\n\ | |
6531 | When non-zero, mips specific debugging is enabled.", &setdebuglist), | |
6532 | &showdebuglist); | |
c906108c | 6533 | } |