Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
cda5a58a | 3 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, |
16e109ca AC |
4 | 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software |
5 | Foundation, Inc. | |
bf64bfd6 | 6 | |
c906108c SS |
7 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
8 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
9 | ||
c5aa993b | 10 | This file is part of GDB. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is free software; you can redistribute it and/or modify |
13 | it under the terms of the GNU General Public License as published by | |
14 | the Free Software Foundation; either version 2 of the License, or | |
15 | (at your option) any later version. | |
c906108c | 16 | |
c5aa993b JM |
17 | This program is distributed in the hope that it will be useful, |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
c906108c | 21 | |
c5aa993b JM |
22 | You should have received a copy of the GNU General Public License |
23 | along with this program; if not, write to the Free Software | |
24 | Foundation, Inc., 59 Temple Place - Suite 330, | |
25 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
26 | |
27 | #include "defs.h" | |
28 | #include "gdb_string.h" | |
5e2e9765 | 29 | #include "gdb_assert.h" |
c906108c SS |
30 | #include "frame.h" |
31 | #include "inferior.h" | |
32 | #include "symtab.h" | |
33 | #include "value.h" | |
34 | #include "gdbcmd.h" | |
35 | #include "language.h" | |
36 | #include "gdbcore.h" | |
37 | #include "symfile.h" | |
38 | #include "objfiles.h" | |
39 | #include "gdbtypes.h" | |
40 | #include "target.h" | |
28d069e6 | 41 | #include "arch-utils.h" |
4e052eda | 42 | #include "regcache.h" |
70f80edf | 43 | #include "osabi.h" |
d1973055 | 44 | #include "mips-tdep.h" |
fe898f56 | 45 | #include "block.h" |
a4b8ebc8 | 46 | #include "reggroups.h" |
c906108c | 47 | #include "opcode/mips.h" |
c2d11a7d JM |
48 | #include "elf/mips.h" |
49 | #include "elf-bfd.h" | |
2475bac3 | 50 | #include "symcat.h" |
a4b8ebc8 | 51 | #include "sim-regno.h" |
a89aa300 | 52 | #include "dis-asm.h" |
edfae063 AC |
53 | #include "frame-unwind.h" |
54 | #include "frame-base.h" | |
55 | #include "trad-frame.h" | |
c906108c | 56 | |
8d5f9dcb DJ |
57 | static const struct objfile_data *mips_pdr_data; |
58 | ||
e0f7ec59 | 59 | static void set_reg_offset (CORE_ADDR *saved_regs, int regnum, CORE_ADDR off); |
5bbcb741 | 60 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 61 | |
dd824b04 DJ |
62 | /* A useful bit in the CP0 status register (PS_REGNUM). */ |
63 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ | |
64 | #define ST0_FR (1 << 26) | |
65 | ||
b0069a17 AC |
66 | /* The sizes of floating point registers. */ |
67 | ||
68 | enum | |
69 | { | |
70 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
71 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
72 | }; | |
73 | ||
0dadbba0 | 74 | |
2e4ebe70 DJ |
75 | static const char *mips_abi_string; |
76 | ||
77 | static const char *mips_abi_strings[] = { | |
78 | "auto", | |
79 | "n32", | |
80 | "o32", | |
28d169de | 81 | "n64", |
2e4ebe70 DJ |
82 | "o64", |
83 | "eabi32", | |
84 | "eabi64", | |
85 | NULL | |
86 | }; | |
87 | ||
cce74817 | 88 | struct frame_extra_info |
6d82d43b AC |
89 | { |
90 | mips_extra_func_info_t proc_desc; | |
91 | int num_args; | |
92 | }; | |
cce74817 | 93 | |
d929b26f AC |
94 | /* Various MIPS ISA options (related to stack analysis) can be |
95 | overridden dynamically. Establish an enum/array for managing | |
96 | them. */ | |
97 | ||
53904c9e AC |
98 | static const char size_auto[] = "auto"; |
99 | static const char size_32[] = "32"; | |
100 | static const char size_64[] = "64"; | |
d929b26f | 101 | |
53904c9e | 102 | static const char *size_enums[] = { |
d929b26f AC |
103 | size_auto, |
104 | size_32, | |
105 | size_64, | |
a5ea2558 AC |
106 | 0 |
107 | }; | |
108 | ||
7a292a7a | 109 | /* Some MIPS boards don't support floating point while others only |
ceae6e75 | 110 | support single-precision floating-point operations. */ |
c906108c SS |
111 | |
112 | enum mips_fpu_type | |
6d82d43b AC |
113 | { |
114 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
115 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
116 | MIPS_FPU_NONE /* No floating point. */ | |
117 | }; | |
c906108c SS |
118 | |
119 | #ifndef MIPS_DEFAULT_FPU_TYPE | |
120 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
121 | #endif | |
122 | static int mips_fpu_type_auto = 1; | |
123 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 124 | |
9ace0497 | 125 | static int mips_debug = 0; |
7a292a7a | 126 | |
c2d11a7d JM |
127 | /* MIPS specific per-architecture information */ |
128 | struct gdbarch_tdep | |
6d82d43b AC |
129 | { |
130 | /* from the elf header */ | |
131 | int elf_flags; | |
132 | ||
133 | /* mips options */ | |
134 | enum mips_abi mips_abi; | |
135 | enum mips_abi found_abi; | |
136 | enum mips_fpu_type mips_fpu_type; | |
137 | int mips_last_arg_regnum; | |
138 | int mips_last_fp_arg_regnum; | |
6d82d43b AC |
139 | int default_mask_address_p; |
140 | /* Is the target using 64-bit raw integer registers but only | |
141 | storing a left-aligned 32-bit value in each? */ | |
142 | int mips64_transfers_32bit_regs_p; | |
143 | /* Indexes for various registers. IRIX and embedded have | |
144 | different values. This contains the "public" fields. Don't | |
145 | add any that do not need to be public. */ | |
146 | const struct mips_regnum *regnum; | |
147 | /* Register names table for the current register set. */ | |
148 | const char **mips_processor_reg_names; | |
149 | }; | |
c2d11a7d | 150 | |
56cea623 AC |
151 | const struct mips_regnum * |
152 | mips_regnum (struct gdbarch *gdbarch) | |
153 | { | |
154 | return gdbarch_tdep (gdbarch)->regnum; | |
155 | } | |
156 | ||
157 | static int | |
158 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
159 | { | |
160 | return mips_regnum (gdbarch)->fp0 + 12; | |
161 | } | |
162 | ||
0dadbba0 | 163 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \ |
216a600b | 164 | || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64) |
c2d11a7d | 165 | |
c2d11a7d | 166 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 167 | |
c2d11a7d | 168 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 169 | |
c2d11a7d | 170 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) |
c2d11a7d | 171 | |
95404a3e AC |
172 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
173 | functions to test, set, or clear bit 0 of addresses. */ | |
174 | ||
175 | static CORE_ADDR | |
176 | is_mips16_addr (CORE_ADDR addr) | |
177 | { | |
178 | return ((addr) & 1); | |
179 | } | |
180 | ||
181 | static CORE_ADDR | |
182 | make_mips16_addr (CORE_ADDR addr) | |
183 | { | |
184 | return ((addr) | 1); | |
185 | } | |
186 | ||
187 | static CORE_ADDR | |
188 | unmake_mips16_addr (CORE_ADDR addr) | |
189 | { | |
190 | return ((addr) & ~1); | |
191 | } | |
192 | ||
22540ece AC |
193 | /* Return the contents of register REGNUM as a signed integer. */ |
194 | ||
195 | static LONGEST | |
196 | read_signed_register (int regnum) | |
197 | { | |
719ec221 | 198 | void *buf = alloca (register_size (current_gdbarch, regnum)); |
22540ece | 199 | deprecated_read_register_gen (regnum, buf); |
6d82d43b AC |
200 | return (extract_signed_integer |
201 | (buf, register_size (current_gdbarch, regnum))); | |
22540ece AC |
202 | } |
203 | ||
204 | static LONGEST | |
205 | read_signed_register_pid (int regnum, ptid_t ptid) | |
206 | { | |
207 | ptid_t save_ptid; | |
208 | LONGEST retval; | |
209 | ||
210 | if (ptid_equal (ptid, inferior_ptid)) | |
211 | return read_signed_register (regnum); | |
212 | ||
213 | save_ptid = inferior_ptid; | |
214 | ||
215 | inferior_ptid = ptid; | |
216 | ||
217 | retval = read_signed_register (regnum); | |
218 | ||
219 | inferior_ptid = save_ptid; | |
220 | ||
221 | return retval; | |
222 | } | |
223 | ||
d1973055 KB |
224 | /* Return the MIPS ABI associated with GDBARCH. */ |
225 | enum mips_abi | |
226 | mips_abi (struct gdbarch *gdbarch) | |
227 | { | |
228 | return gdbarch_tdep (gdbarch)->mips_abi; | |
229 | } | |
230 | ||
4246e332 | 231 | int |
1b13c4f6 | 232 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 AC |
233 | { |
234 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word | |
235 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
236 | } | |
237 | ||
480d3dd2 AC |
238 | /* Return the currently configured (or set) saved register size. */ |
239 | ||
1b13c4f6 | 240 | static const char *mips_abi_regsize_string = size_auto; |
480d3dd2 | 241 | |
d929b26f | 242 | static unsigned int |
13326b4e | 243 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 244 | { |
1b13c4f6 | 245 | if (mips_abi_regsize_string == size_auto) |
13326b4e AC |
246 | switch (mips_abi (gdbarch)) |
247 | { | |
248 | case MIPS_ABI_EABI32: | |
249 | case MIPS_ABI_O32: | |
250 | return 4; | |
251 | case MIPS_ABI_N32: | |
252 | case MIPS_ABI_N64: | |
253 | case MIPS_ABI_O64: | |
254 | case MIPS_ABI_EABI64: | |
255 | return 8; | |
256 | case MIPS_ABI_UNKNOWN: | |
257 | case MIPS_ABI_LAST: | |
258 | default: | |
259 | internal_error (__FILE__, __LINE__, "bad switch"); | |
260 | } | |
1b13c4f6 | 261 | else if (mips_abi_regsize_string == size_64) |
d929b26f | 262 | return 8; |
1b13c4f6 | 263 | else /* if (mips_abi_regsize_string == size_32) */ |
d929b26f AC |
264 | return 4; |
265 | } | |
266 | ||
71b8ef93 | 267 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 268 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 269 | "info" field is used for this purpose. |
5a89d8aa MS |
270 | |
271 | ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special", | |
272 | i.e. refers to a 16-bit function, and sets a "special" bit in a | |
273 | minimal symbol to mark it as a 16-bit function | |
274 | ||
f594e5e9 | 275 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 276 | |
5a89d8aa | 277 | static void |
6d82d43b AC |
278 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
279 | { | |
280 | if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16) | |
281 | { | |
282 | MSYMBOL_INFO (msym) = (char *) | |
283 | (((long) MSYMBOL_INFO (msym)) | 0x80000000); | |
284 | SYMBOL_VALUE_ADDRESS (msym) |= 1; | |
285 | } | |
5a89d8aa MS |
286 | } |
287 | ||
71b8ef93 MS |
288 | static int |
289 | msymbol_is_special (struct minimal_symbol *msym) | |
290 | { | |
291 | return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0); | |
292 | } | |
293 | ||
88658117 AC |
294 | /* XFER a value from the big/little/left end of the register. |
295 | Depending on the size of the value it might occupy the entire | |
296 | register or just part of it. Make an allowance for this, aligning | |
297 | things accordingly. */ | |
298 | ||
299 | static void | |
300 | mips_xfer_register (struct regcache *regcache, int reg_num, int length, | |
6d82d43b AC |
301 | enum bfd_endian endian, bfd_byte * in, |
302 | const bfd_byte * out, int buf_offset) | |
88658117 | 303 | { |
88658117 | 304 | int reg_offset = 0; |
a4b8ebc8 | 305 | gdb_assert (reg_num >= NUM_REGS); |
cb1d2653 AC |
306 | /* Need to transfer the left or right part of the register, based on |
307 | the targets byte order. */ | |
88658117 AC |
308 | switch (endian) |
309 | { | |
310 | case BFD_ENDIAN_BIG: | |
719ec221 | 311 | reg_offset = register_size (current_gdbarch, reg_num) - length; |
88658117 AC |
312 | break; |
313 | case BFD_ENDIAN_LITTLE: | |
314 | reg_offset = 0; | |
315 | break; | |
6d82d43b | 316 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
317 | reg_offset = 0; |
318 | break; | |
319 | default: | |
320 | internal_error (__FILE__, __LINE__, "bad switch"); | |
321 | } | |
322 | if (mips_debug) | |
cb1d2653 AC |
323 | fprintf_unfiltered (gdb_stderr, |
324 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
325 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
326 | if (mips_debug && out != NULL) |
327 | { | |
328 | int i; | |
cb1d2653 | 329 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 330 | for (i = 0; i < length; i++) |
cb1d2653 | 331 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
332 | } |
333 | if (in != NULL) | |
6d82d43b AC |
334 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
335 | in + buf_offset); | |
88658117 | 336 | if (out != NULL) |
6d82d43b AC |
337 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
338 | out + buf_offset); | |
88658117 AC |
339 | if (mips_debug && in != NULL) |
340 | { | |
341 | int i; | |
cb1d2653 | 342 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 343 | for (i = 0; i < length; i++) |
cb1d2653 | 344 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
345 | } |
346 | if (mips_debug) | |
347 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
348 | } | |
349 | ||
dd824b04 DJ |
350 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
351 | compatiblity mode. A return value of 1 means that we have | |
352 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
353 | ||
354 | static int | |
355 | mips2_fp_compat (void) | |
356 | { | |
357 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not | |
358 | meaningful. */ | |
6d82d43b AC |
359 | if (register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) == |
360 | 4) | |
dd824b04 DJ |
361 | return 0; |
362 | ||
363 | #if 0 | |
364 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
365 | in all the places we deal with FP registers. PR gdb/413. */ | |
366 | /* Otherwise check the FR bit in the status register - it controls | |
367 | the FP compatiblity mode. If it is clear we are in compatibility | |
368 | mode. */ | |
369 | if ((read_register (PS_REGNUM) & ST0_FR) == 0) | |
370 | return 1; | |
371 | #endif | |
361d1df0 | 372 | |
dd824b04 DJ |
373 | return 0; |
374 | } | |
375 | ||
d929b26f | 376 | /* The amount of space reserved on the stack for registers. This is |
1b13c4f6 | 377 | different to MIPS_ABI_REGSIZE as it determines the alignment of |
d929b26f AC |
378 | data allocated after the registers have run out. */ |
379 | ||
53904c9e | 380 | static const char *mips_stack_argsize_string = size_auto; |
d929b26f AC |
381 | |
382 | static unsigned int | |
13326b4e | 383 | mips_stack_argsize (struct gdbarch *gdbarch) |
d929b26f AC |
384 | { |
385 | if (mips_stack_argsize_string == size_auto) | |
13326b4e | 386 | return mips_abi_regsize (gdbarch); |
d929b26f AC |
387 | else if (mips_stack_argsize_string == size_64) |
388 | return 8; | |
6d82d43b | 389 | else /* if (mips_stack_argsize_string == size_32) */ |
d929b26f AC |
390 | return 4; |
391 | } | |
392 | ||
7a292a7a | 393 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 394 | |
570b8f7c AC |
395 | static mips_extra_func_info_t heuristic_proc_desc (CORE_ADDR, CORE_ADDR, |
396 | struct frame_info *, int); | |
c906108c | 397 | |
a14ed312 | 398 | static CORE_ADDR heuristic_proc_start (CORE_ADDR); |
c906108c | 399 | |
a14ed312 | 400 | static CORE_ADDR read_next_frame_reg (struct frame_info *, int); |
c906108c | 401 | |
a14ed312 | 402 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 403 | |
570b8f7c AC |
404 | static mips_extra_func_info_t find_proc_desc (CORE_ADDR pc, |
405 | struct frame_info *next_frame, | |
406 | int cur_frame); | |
c906108c | 407 | |
a14ed312 KB |
408 | static CORE_ADDR after_prologue (CORE_ADDR pc, |
409 | mips_extra_func_info_t proc_desc); | |
c906108c | 410 | |
67b2c998 DJ |
411 | static struct type *mips_float_register_type (void); |
412 | static struct type *mips_double_register_type (void); | |
413 | ||
acdb74a0 AC |
414 | /* The list of available "set mips " and "show mips " commands */ |
415 | ||
416 | static struct cmd_list_element *setmipscmdlist = NULL; | |
417 | static struct cmd_list_element *showmipscmdlist = NULL; | |
418 | ||
5e2e9765 KB |
419 | /* Integer registers 0 thru 31 are handled explicitly by |
420 | mips_register_name(). Processor specific registers 32 and above | |
691c0433 AC |
421 | are listed in the followign tables. */ |
422 | ||
6d82d43b AC |
423 | enum |
424 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
425 | |
426 | /* Generic MIPS. */ | |
427 | ||
428 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
429 | "sr", "lo", "hi", "bad", "cause", "pc", |
430 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
431 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
432 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
433 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
434 | "fsr", "fir", "" /*"fp" */ , "", | |
435 | "", "", "", "", "", "", "", "", | |
436 | "", "", "", "", "", "", "", "", | |
691c0433 AC |
437 | }; |
438 | ||
439 | /* Names of IDT R3041 registers. */ | |
440 | ||
441 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
442 | "sr", "lo", "hi", "bad", "cause", "pc", |
443 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
444 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
445 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
446 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
447 | "fsr", "fir", "", /*"fp" */ "", | |
448 | "", "", "bus", "ccfg", "", "", "", "", | |
449 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
450 | }; |
451 | ||
452 | /* Names of tx39 registers. */ | |
453 | ||
454 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
455 | "sr", "lo", "hi", "bad", "cause", "pc", |
456 | "", "", "", "", "", "", "", "", | |
457 | "", "", "", "", "", "", "", "", | |
458 | "", "", "", "", "", "", "", "", | |
459 | "", "", "", "", "", "", "", "", | |
460 | "", "", "", "", | |
461 | "", "", "", "", "", "", "", "", | |
462 | "", "", "config", "cache", "debug", "depc", "epc", "" | |
691c0433 AC |
463 | }; |
464 | ||
465 | /* Names of IRIX registers. */ | |
466 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
467 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
468 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
469 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
470 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
471 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
472 | }; |
473 | ||
cce74817 | 474 | |
5e2e9765 | 475 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 476 | static const char * |
5e2e9765 | 477 | mips_register_name (int regno) |
cce74817 | 478 | { |
691c0433 | 479 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
5e2e9765 KB |
480 | /* GPR names for all ABIs other than n32/n64. */ |
481 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
482 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
483 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
484 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
485 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
486 | }; |
487 | ||
488 | /* GPR names for n32 and n64 ABIs. */ | |
489 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
490 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
491 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
492 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
493 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
494 | }; |
495 | ||
496 | enum mips_abi abi = mips_abi (current_gdbarch); | |
497 | ||
a4b8ebc8 AC |
498 | /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then |
499 | don't make the raw register names visible. */ | |
500 | int rawnum = regno % NUM_REGS; | |
501 | if (regno < NUM_REGS) | |
502 | return ""; | |
503 | ||
5e2e9765 KB |
504 | /* The MIPS integer registers are always mapped from 0 to 31. The |
505 | names of the registers (which reflects the conventions regarding | |
506 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 507 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
508 | { |
509 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 510 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 511 | else |
a4b8ebc8 | 512 | return mips_gpr_names[rawnum]; |
5e2e9765 | 513 | } |
a4b8ebc8 | 514 | else if (32 <= rawnum && rawnum < NUM_REGS) |
691c0433 AC |
515 | { |
516 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
517 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
518 | } | |
5e2e9765 KB |
519 | else |
520 | internal_error (__FILE__, __LINE__, | |
a4b8ebc8 | 521 | "mips_register_name: bad register number %d", rawnum); |
cce74817 | 522 | } |
5e2e9765 | 523 | |
a4b8ebc8 | 524 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 525 | |
a4b8ebc8 AC |
526 | static int |
527 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
528 | struct reggroup *reggroup) | |
529 | { | |
530 | int vector_p; | |
531 | int float_p; | |
532 | int raw_p; | |
533 | int rawnum = regnum % NUM_REGS; | |
534 | int pseudo = regnum / NUM_REGS; | |
535 | if (reggroup == all_reggroup) | |
536 | return pseudo; | |
537 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
538 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
539 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
540 | (gdbarch), as not all architectures are multi-arch. */ | |
541 | raw_p = rawnum < NUM_REGS; | |
6d82d43b | 542 | if (REGISTER_NAME (regnum) == NULL || REGISTER_NAME (regnum)[0] == '\0') |
a4b8ebc8 AC |
543 | return 0; |
544 | if (reggroup == float_reggroup) | |
545 | return float_p && pseudo; | |
546 | if (reggroup == vector_reggroup) | |
547 | return vector_p && pseudo; | |
548 | if (reggroup == general_reggroup) | |
549 | return (!vector_p && !float_p) && pseudo; | |
550 | /* Save the pseudo registers. Need to make certain that any code | |
551 | extracting register values from a saved register cache also uses | |
552 | pseudo registers. */ | |
553 | if (reggroup == save_reggroup) | |
554 | return raw_p && pseudo; | |
555 | /* Restore the same pseudo register. */ | |
556 | if (reggroup == restore_reggroup) | |
557 | return raw_p && pseudo; | |
6d82d43b | 558 | return 0; |
a4b8ebc8 AC |
559 | } |
560 | ||
561 | /* Map the symbol table registers which live in the range [1 * | |
562 | NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw | |
47ebcfbe | 563 | registers. Take care of alignment and size problems. */ |
c5aa993b | 564 | |
a4b8ebc8 AC |
565 | static void |
566 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
567 | int cookednum, void *buf) | |
568 | { | |
47ebcfbe | 569 | int rawnum = cookednum % NUM_REGS; |
a4b8ebc8 | 570 | gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); |
47ebcfbe | 571 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 572 | regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
573 | else if (register_size (gdbarch, rawnum) > |
574 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
575 | { |
576 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
577 | || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
578 | regcache_raw_read_part (regcache, rawnum, 0, 4, buf); | |
579 | else | |
580 | regcache_raw_read_part (regcache, rawnum, 4, 4, buf); | |
581 | } | |
582 | else | |
583 | internal_error (__FILE__, __LINE__, "bad register size"); | |
a4b8ebc8 AC |
584 | } |
585 | ||
586 | static void | |
6d82d43b AC |
587 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
588 | struct regcache *regcache, int cookednum, | |
589 | const void *buf) | |
a4b8ebc8 | 590 | { |
47ebcfbe | 591 | int rawnum = cookednum % NUM_REGS; |
a4b8ebc8 | 592 | gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); |
47ebcfbe | 593 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 594 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
595 | else if (register_size (gdbarch, rawnum) > |
596 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
597 | { |
598 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
599 | || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
600 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); | |
601 | else | |
602 | regcache_raw_write_part (regcache, rawnum, 4, 4, buf); | |
603 | } | |
604 | else | |
605 | internal_error (__FILE__, __LINE__, "bad register size"); | |
a4b8ebc8 | 606 | } |
c5aa993b | 607 | |
c906108c | 608 | /* Table to translate MIPS16 register field to actual register number. */ |
6d82d43b | 609 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
610 | |
611 | /* Heuristic_proc_start may hunt through the text section for a long | |
612 | time across a 2400 baud serial line. Allows the user to limit this | |
613 | search. */ | |
614 | ||
615 | static unsigned int heuristic_fence_post = 0; | |
616 | ||
c5aa993b JM |
617 | #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ |
618 | #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */ | |
c906108c SS |
619 | #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) |
620 | #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) | |
621 | #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust) | |
622 | #define PROC_REG_MASK(proc) ((proc)->pdr.regmask) | |
623 | #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) | |
624 | #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) | |
625 | #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) | |
626 | #define PROC_PC_REG(proc) ((proc)->pdr.pcreg) | |
6c0d6680 DJ |
627 | /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long, |
628 | this will corrupt pdr.iline. Fortunately we don't use it. */ | |
c906108c SS |
629 | #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) |
630 | #define _PROC_MAGIC_ 0x0F0F0F0F | |
631 | #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_) | |
632 | #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_) | |
633 | ||
634 | struct linked_proc_info | |
6d82d43b AC |
635 | { |
636 | struct mips_extra_func_info info; | |
637 | struct linked_proc_info *next; | |
638 | } | |
c5aa993b | 639 | *linked_proc_desc_table = NULL; |
c906108c | 640 | |
46cd78fb | 641 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
642 | register N. NOTE: This defines the pseudo register type so need to |
643 | rebuild the architecture vector. */ | |
43e526b9 JM |
644 | |
645 | static int mips64_transfers_32bit_regs_p = 0; | |
646 | ||
719ec221 AC |
647 | static void |
648 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
649 | struct cmd_list_element *c) | |
43e526b9 | 650 | { |
719ec221 AC |
651 | struct gdbarch_info info; |
652 | gdbarch_info_init (&info); | |
653 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
654 | instead of relying on globals. Doing that would let generic code | |
655 | handle the search for this specific architecture. */ | |
656 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 657 | { |
719ec221 AC |
658 | mips64_transfers_32bit_regs_p = 0; |
659 | error ("32-bit compatibility mode not supported"); | |
a4b8ebc8 | 660 | } |
a4b8ebc8 AC |
661 | } |
662 | ||
47ebcfbe | 663 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 664 | |
ff2e87ac AC |
665 | static int |
666 | mips_convert_register_p (int regnum, struct type *type) | |
667 | { | |
668 | return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
719ec221 | 669 | && register_size (current_gdbarch, regnum) == 4 |
87783b8b AC |
670 | && (regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0 |
671 | && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32 | |
6d82d43b | 672 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
673 | } |
674 | ||
42c466d7 | 675 | static void |
ff2e87ac AC |
676 | mips_register_to_value (struct frame_info *frame, int regnum, |
677 | struct type *type, void *to) | |
102182a9 | 678 | { |
7f5f525d AC |
679 | get_frame_register (frame, regnum + 0, (char *) to + 4); |
680 | get_frame_register (frame, regnum + 1, (char *) to + 0); | |
102182a9 MS |
681 | } |
682 | ||
42c466d7 | 683 | static void |
ff2e87ac AC |
684 | mips_value_to_register (struct frame_info *frame, int regnum, |
685 | struct type *type, const void *from) | |
102182a9 | 686 | { |
ff2e87ac AC |
687 | put_frame_register (frame, regnum + 0, (const char *) from + 4); |
688 | put_frame_register (frame, regnum + 1, (const char *) from + 0); | |
102182a9 MS |
689 | } |
690 | ||
a4b8ebc8 AC |
691 | /* Return the GDB type object for the "standard" data type of data in |
692 | register REG. */ | |
78fde5f8 KB |
693 | |
694 | static struct type * | |
a4b8ebc8 AC |
695 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
696 | { | |
5ef80fb0 | 697 | gdb_assert (regnum >= 0 && regnum < 2 * NUM_REGS); |
56cea623 AC |
698 | if ((regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0 |
699 | && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32) | |
a6425924 | 700 | { |
5ef80fb0 | 701 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 702 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
5ef80fb0 AC |
703 | switch (gdbarch_byte_order (gdbarch)) |
704 | { | |
705 | case BFD_ENDIAN_BIG: | |
1b13c4f6 | 706 | if (mips_isa_regsize (gdbarch) == 4) |
5ef80fb0 AC |
707 | return builtin_type_ieee_single_big; |
708 | else | |
709 | return builtin_type_ieee_double_big; | |
710 | case BFD_ENDIAN_LITTLE: | |
1b13c4f6 | 711 | if (mips_isa_regsize (gdbarch) == 4) |
5ef80fb0 AC |
712 | return builtin_type_ieee_single_little; |
713 | else | |
714 | return builtin_type_ieee_double_little; | |
715 | case BFD_ENDIAN_UNKNOWN: | |
716 | default: | |
717 | internal_error (__FILE__, __LINE__, "bad switch"); | |
718 | } | |
a6425924 | 719 | } |
d5ac5a39 AC |
720 | else if (regnum < NUM_REGS) |
721 | { | |
722 | /* The raw or ISA registers. These are all sized according to | |
723 | the ISA regsize. */ | |
724 | if (mips_isa_regsize (gdbarch) == 4) | |
725 | return builtin_type_int32; | |
726 | else | |
727 | return builtin_type_int64; | |
728 | } | |
78fde5f8 | 729 | else |
d5ac5a39 AC |
730 | { |
731 | /* The cooked or ABI registers. These are sized according to | |
732 | the ABI (with a few complications). */ | |
733 | if (regnum >= (NUM_REGS | |
734 | + mips_regnum (current_gdbarch)->fp_control_status) | |
735 | && regnum <= NUM_REGS + LAST_EMBED_REGNUM) | |
736 | /* The pseudo/cooked view of the embedded registers is always | |
737 | 32-bit. The raw view is handled below. */ | |
738 | return builtin_type_int32; | |
739 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) | |
740 | /* The target, while possibly using a 64-bit register buffer, | |
741 | is only transfering 32-bits of each integer register. | |
742 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
743 | return builtin_type_int32; | |
744 | else if (mips_abi_regsize (gdbarch) == 4) | |
745 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
746 | 32- or 64-bit). */ | |
747 | return builtin_type_int32; | |
748 | else | |
749 | /* 64-bit ABI. */ | |
750 | return builtin_type_int64; | |
751 | } | |
78fde5f8 KB |
752 | } |
753 | ||
bcb0cc15 MS |
754 | /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */ |
755 | ||
756 | static CORE_ADDR | |
757 | mips_read_sp (void) | |
758 | { | |
e227b13c | 759 | return read_signed_register (SP_REGNUM); |
bcb0cc15 MS |
760 | } |
761 | ||
c906108c | 762 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 763 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
764 | |
765 | static int | |
480d3dd2 | 766 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
767 | { |
768 | switch (mask_address_var) | |
769 | { | |
7f19b9a2 | 770 | case AUTO_BOOLEAN_TRUE: |
4014092b | 771 | return 1; |
7f19b9a2 | 772 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
773 | return 0; |
774 | break; | |
7f19b9a2 | 775 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 776 | return tdep->default_mask_address_p; |
4014092b | 777 | default: |
6d82d43b | 778 | internal_error (__FILE__, __LINE__, "mips_mask_address_p: bad switch"); |
4014092b | 779 | return -1; |
361d1df0 | 780 | } |
4014092b AC |
781 | } |
782 | ||
783 | static void | |
e9e68a56 | 784 | show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c) |
4014092b | 785 | { |
480d3dd2 | 786 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
4014092b AC |
787 | switch (mask_address_var) |
788 | { | |
7f19b9a2 | 789 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
790 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
791 | break; | |
7f19b9a2 | 792 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
793 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
794 | break; | |
7f19b9a2 | 795 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
796 | printf_filtered |
797 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
798 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
799 | break; |
800 | default: | |
6d82d43b | 801 | internal_error (__FILE__, __LINE__, "show_mask_address: bad switch"); |
4014092b | 802 | break; |
361d1df0 | 803 | } |
4014092b | 804 | } |
c906108c | 805 | |
c906108c SS |
806 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
807 | ||
808 | static int | |
809 | pc_is_mips16 (bfd_vma memaddr) | |
810 | { | |
811 | struct minimal_symbol *sym; | |
812 | ||
813 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
95404a3e | 814 | if (is_mips16_addr (memaddr)) |
c906108c SS |
815 | return 1; |
816 | ||
817 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
818 | the high bit of the info field. Use this to decide if the function is | |
819 | MIPS16 or normal MIPS. */ | |
820 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
821 | if (sym) | |
71b8ef93 | 822 | return msymbol_is_special (sym); |
c906108c SS |
823 | else |
824 | return 0; | |
825 | } | |
826 | ||
6c997a34 AC |
827 | /* MIPS believes that the PC has a sign extended value. Perhaphs the |
828 | all registers should be sign extended for simplicity? */ | |
829 | ||
830 | static CORE_ADDR | |
39f77062 | 831 | mips_read_pc (ptid_t ptid) |
6c997a34 | 832 | { |
b6cb9035 AC |
833 | return read_signed_register_pid (mips_regnum (current_gdbarch)->pc, ptid); |
834 | } | |
835 | ||
58dfe9ff AC |
836 | static CORE_ADDR |
837 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
838 | { | |
edfae063 AC |
839 | return frame_unwind_register_signed (next_frame, |
840 | NUM_REGS + mips_regnum (gdbarch)->pc); | |
841 | } | |
842 | ||
843 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that | |
844 | dummy frame. The frame ID's base needs to match the TOS value | |
845 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
846 | breakpoint. */ | |
847 | ||
848 | static struct frame_id | |
849 | mips_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
850 | { | |
851 | return frame_id_build (frame_unwind_register_signed (next_frame, NUM_REGS + SP_REGNUM), | |
852 | frame_pc_unwind (next_frame)); | |
58dfe9ff AC |
853 | } |
854 | ||
b6cb9035 AC |
855 | static void |
856 | mips_write_pc (CORE_ADDR pc, ptid_t ptid) | |
857 | { | |
858 | write_register_pid (mips_regnum (current_gdbarch)->pc, pc, ptid); | |
6c997a34 | 859 | } |
c906108c SS |
860 | |
861 | /* This returns the PC of the first inst after the prologue. If we can't | |
862 | find the prologue, then return 0. */ | |
863 | ||
864 | static CORE_ADDR | |
6d82d43b | 865 | after_prologue (CORE_ADDR pc, mips_extra_func_info_t proc_desc) |
c906108c SS |
866 | { |
867 | struct symtab_and_line sal; | |
868 | CORE_ADDR func_addr, func_end; | |
869 | ||
479412cd DJ |
870 | /* Pass cur_frame == 0 to find_proc_desc. We should not attempt |
871 | to read the stack pointer from the current machine state, because | |
872 | the current machine state has nothing to do with the information | |
873 | we need from the proc_desc; and the process may or may not exist | |
874 | right now. */ | |
c906108c | 875 | if (!proc_desc) |
479412cd | 876 | proc_desc = find_proc_desc (pc, NULL, 0); |
c906108c SS |
877 | |
878 | if (proc_desc) | |
879 | { | |
880 | /* If function is frameless, then we need to do it the hard way. I | |
c5aa993b | 881 | strongly suspect that frameless always means prologueless... */ |
c906108c SS |
882 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM |
883 | && PROC_FRAME_OFFSET (proc_desc) == 0) | |
884 | return 0; | |
885 | } | |
886 | ||
887 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
888 | return 0; /* Unknown */ | |
889 | ||
890 | sal = find_pc_line (func_addr, 0); | |
891 | ||
892 | if (sal.end < func_end) | |
893 | return sal.end; | |
894 | ||
895 | /* The line after the prologue is after the end of the function. In this | |
896 | case, tell the caller to find the prologue the hard way. */ | |
897 | ||
898 | return 0; | |
899 | } | |
900 | ||
901 | /* Decode a MIPS32 instruction that saves a register in the stack, and | |
902 | set the appropriate bit in the general register mask or float register mask | |
903 | to indicate which register is saved. This is a helper function | |
904 | for mips_find_saved_regs. */ | |
905 | ||
906 | static void | |
acdb74a0 AC |
907 | mips32_decode_reg_save (t_inst inst, unsigned long *gen_mask, |
908 | unsigned long *float_mask) | |
c906108c SS |
909 | { |
910 | int reg; | |
911 | ||
6d82d43b | 912 | if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */ |
c906108c SS |
913 | || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */ |
914 | || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */ | |
915 | { | |
916 | /* It might be possible to use the instruction to | |
c5aa993b JM |
917 | find the offset, rather than the code below which |
918 | is based on things being in a certain order in the | |
919 | frame, but figuring out what the instruction's offset | |
920 | is relative to might be a little tricky. */ | |
c906108c SS |
921 | reg = (inst & 0x001f0000) >> 16; |
922 | *gen_mask |= (1 << reg); | |
923 | } | |
924 | else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */ | |
6d82d43b | 925 | || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */ |
c5aa993b | 926 | || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */ |
c906108c SS |
927 | |
928 | { | |
929 | reg = ((inst & 0x001f0000) >> 16); | |
930 | *float_mask |= (1 << reg); | |
931 | } | |
932 | } | |
933 | ||
934 | /* Decode a MIPS16 instruction that saves a register in the stack, and | |
935 | set the appropriate bit in the general register or float register mask | |
936 | to indicate which register is saved. This is a helper function | |
937 | for mips_find_saved_regs. */ | |
938 | ||
939 | static void | |
acdb74a0 | 940 | mips16_decode_reg_save (t_inst inst, unsigned long *gen_mask) |
c906108c | 941 | { |
c5aa993b | 942 | if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ |
c906108c SS |
943 | { |
944 | int reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
945 | *gen_mask |= (1 << reg); | |
946 | } | |
c5aa993b | 947 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ |
c906108c SS |
948 | { |
949 | int reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
950 | *gen_mask |= (1 << reg); | |
951 | } | |
c5aa993b | 952 | else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */ |
c906108c SS |
953 | || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ |
954 | *gen_mask |= (1 << RA_REGNUM); | |
955 | } | |
956 | ||
957 | ||
958 | /* Fetch and return instruction from the specified location. If the PC | |
959 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
960 | ||
961 | static t_inst | |
acdb74a0 | 962 | mips_fetch_instruction (CORE_ADDR addr) |
c906108c SS |
963 | { |
964 | char buf[MIPS_INSTLEN]; | |
965 | int instlen; | |
966 | int status; | |
967 | ||
968 | if (pc_is_mips16 (addr)) | |
969 | { | |
970 | instlen = MIPS16_INSTLEN; | |
95404a3e | 971 | addr = unmake_mips16_addr (addr); |
c906108c SS |
972 | } |
973 | else | |
c5aa993b | 974 | instlen = MIPS_INSTLEN; |
c906108c SS |
975 | status = read_memory_nobpt (addr, buf, instlen); |
976 | if (status) | |
977 | memory_error (status, addr); | |
978 | return extract_unsigned_integer (buf, instlen); | |
979 | } | |
980 | ||
edfae063 AC |
981 | static ULONGEST |
982 | mips16_fetch_instruction (CORE_ADDR addr) | |
983 | { | |
984 | char buf[MIPS_INSTLEN]; | |
985 | int instlen; | |
986 | int status; | |
987 | ||
988 | instlen = MIPS16_INSTLEN; | |
989 | addr = unmake_mips16_addr (addr); | |
990 | status = read_memory_nobpt (addr, buf, instlen); | |
991 | if (status) | |
992 | memory_error (status, addr); | |
993 | return extract_unsigned_integer (buf, instlen); | |
994 | } | |
995 | ||
996 | static ULONGEST | |
997 | mips32_fetch_instruction (CORE_ADDR addr) | |
998 | { | |
999 | char buf[MIPS_INSTLEN]; | |
1000 | int instlen; | |
1001 | int status; | |
1002 | instlen = MIPS_INSTLEN; | |
1003 | status = read_memory_nobpt (addr, buf, instlen); | |
1004 | if (status) | |
1005 | memory_error (status, addr); | |
1006 | return extract_unsigned_integer (buf, instlen); | |
1007 | } | |
1008 | ||
c906108c SS |
1009 | |
1010 | /* These the fields of 32 bit mips instructions */ | |
e135b889 DJ |
1011 | #define mips32_op(x) (x >> 26) |
1012 | #define itype_op(x) (x >> 26) | |
1013 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 1014 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 1015 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 1016 | |
e135b889 DJ |
1017 | #define jtype_op(x) (x >> 26) |
1018 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 1019 | |
e135b889 DJ |
1020 | #define rtype_op(x) (x >> 26) |
1021 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
1022 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
1023 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
1024 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
1025 | #define rtype_funct(x) (x & 0x3f) | |
c906108c SS |
1026 | |
1027 | static CORE_ADDR | |
c5aa993b JM |
1028 | mips32_relative_offset (unsigned long inst) |
1029 | { | |
1030 | long x; | |
1031 | x = itype_immediate (inst); | |
1032 | if (x & 0x8000) /* sign bit set */ | |
c906108c | 1033 | { |
c5aa993b | 1034 | x |= 0xffff0000; /* sign extension */ |
c906108c | 1035 | } |
c5aa993b JM |
1036 | x = x << 2; |
1037 | return x; | |
c906108c SS |
1038 | } |
1039 | ||
1040 | /* Determine whate to set a single step breakpoint while considering | |
1041 | branch prediction */ | |
5a89d8aa | 1042 | static CORE_ADDR |
c5aa993b JM |
1043 | mips32_next_pc (CORE_ADDR pc) |
1044 | { | |
1045 | unsigned long inst; | |
1046 | int op; | |
1047 | inst = mips_fetch_instruction (pc); | |
e135b889 | 1048 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 1049 | { |
e135b889 | 1050 | if (itype_op (inst) >> 2 == 5) |
6d82d43b | 1051 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 1052 | { |
e135b889 | 1053 | op = (itype_op (inst) & 0x03); |
c906108c SS |
1054 | switch (op) |
1055 | { | |
e135b889 DJ |
1056 | case 0: /* BEQL */ |
1057 | goto equal_branch; | |
1058 | case 1: /* BNEL */ | |
1059 | goto neq_branch; | |
1060 | case 2: /* BLEZL */ | |
1061 | goto less_branch; | |
1062 | case 3: /* BGTZ */ | |
1063 | goto greater_branch; | |
c5aa993b JM |
1064 | default: |
1065 | pc += 4; | |
c906108c SS |
1066 | } |
1067 | } | |
e135b889 | 1068 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
6d82d43b | 1069 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
e135b889 DJ |
1070 | { |
1071 | int tf = itype_rt (inst) & 0x01; | |
1072 | int cnum = itype_rt (inst) >> 2; | |
6d82d43b AC |
1073 | int fcrcs = |
1074 | read_signed_register (mips_regnum (current_gdbarch)-> | |
1075 | fp_control_status); | |
e135b889 DJ |
1076 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); |
1077 | ||
1078 | if (((cond >> cnum) & 0x01) == tf) | |
1079 | pc += mips32_relative_offset (inst) + 4; | |
1080 | else | |
1081 | pc += 8; | |
1082 | } | |
c5aa993b JM |
1083 | else |
1084 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
1085 | } |
1086 | else | |
c5aa993b JM |
1087 | { /* This gets way messy */ |
1088 | ||
c906108c | 1089 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 1090 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 1091 | { |
c5aa993b JM |
1092 | case 0: /* SPECIAL */ |
1093 | op = rtype_funct (inst); | |
1094 | switch (op) | |
1095 | { | |
1096 | case 8: /* JR */ | |
1097 | case 9: /* JALR */ | |
6c997a34 AC |
1098 | /* Set PC to that address */ |
1099 | pc = read_signed_register (rtype_rs (inst)); | |
c5aa993b JM |
1100 | break; |
1101 | default: | |
1102 | pc += 4; | |
1103 | } | |
1104 | ||
6d82d43b | 1105 | break; /* end SPECIAL */ |
c5aa993b | 1106 | case 1: /* REGIMM */ |
c906108c | 1107 | { |
e135b889 DJ |
1108 | op = itype_rt (inst); /* branch condition */ |
1109 | switch (op) | |
c906108c | 1110 | { |
c5aa993b | 1111 | case 0: /* BLTZ */ |
e135b889 DJ |
1112 | case 2: /* BLTZL */ |
1113 | case 16: /* BLTZAL */ | |
c5aa993b | 1114 | case 18: /* BLTZALL */ |
c906108c | 1115 | less_branch: |
6c997a34 | 1116 | if (read_signed_register (itype_rs (inst)) < 0) |
c5aa993b JM |
1117 | pc += mips32_relative_offset (inst) + 4; |
1118 | else | |
1119 | pc += 8; /* after the delay slot */ | |
1120 | break; | |
e135b889 | 1121 | case 1: /* BGEZ */ |
c5aa993b JM |
1122 | case 3: /* BGEZL */ |
1123 | case 17: /* BGEZAL */ | |
1124 | case 19: /* BGEZALL */ | |
6c997a34 | 1125 | if (read_signed_register (itype_rs (inst)) >= 0) |
c5aa993b JM |
1126 | pc += mips32_relative_offset (inst) + 4; |
1127 | else | |
1128 | pc += 8; /* after the delay slot */ | |
1129 | break; | |
e135b889 | 1130 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1131 | default: |
1132 | pc += 4; | |
c906108c SS |
1133 | } |
1134 | } | |
6d82d43b | 1135 | break; /* end REGIMM */ |
c5aa993b JM |
1136 | case 2: /* J */ |
1137 | case 3: /* JAL */ | |
1138 | { | |
1139 | unsigned long reg; | |
1140 | reg = jtype_target (inst) << 2; | |
e135b889 | 1141 | /* Upper four bits get never changed... */ |
c5aa993b | 1142 | pc = reg + ((pc + 4) & 0xf0000000); |
c906108c | 1143 | } |
c5aa993b JM |
1144 | break; |
1145 | /* FIXME case JALX : */ | |
1146 | { | |
1147 | unsigned long reg; | |
1148 | reg = jtype_target (inst) << 2; | |
1149 | pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */ | |
c906108c SS |
1150 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1151 | } | |
c5aa993b | 1152 | break; /* The new PC will be alternate mode */ |
e135b889 | 1153 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1154 | equal_branch: |
6c997a34 AC |
1155 | if (read_signed_register (itype_rs (inst)) == |
1156 | read_signed_register (itype_rt (inst))) | |
c5aa993b JM |
1157 | pc += mips32_relative_offset (inst) + 4; |
1158 | else | |
1159 | pc += 8; | |
1160 | break; | |
e135b889 | 1161 | case 5: /* BNE, BNEL */ |
c5aa993b | 1162 | neq_branch: |
6c997a34 | 1163 | if (read_signed_register (itype_rs (inst)) != |
e135b889 | 1164 | read_signed_register (itype_rt (inst))) |
c5aa993b JM |
1165 | pc += mips32_relative_offset (inst) + 4; |
1166 | else | |
1167 | pc += 8; | |
1168 | break; | |
e135b889 | 1169 | case 6: /* BLEZ, BLEZL */ |
6c997a34 | 1170 | if (read_signed_register (itype_rs (inst) <= 0)) |
c5aa993b JM |
1171 | pc += mips32_relative_offset (inst) + 4; |
1172 | else | |
1173 | pc += 8; | |
1174 | break; | |
1175 | case 7: | |
e135b889 DJ |
1176 | default: |
1177 | greater_branch: /* BGTZ, BGTZL */ | |
6c997a34 | 1178 | if (read_signed_register (itype_rs (inst) > 0)) |
c5aa993b JM |
1179 | pc += mips32_relative_offset (inst) + 4; |
1180 | else | |
1181 | pc += 8; | |
1182 | break; | |
c5aa993b JM |
1183 | } /* switch */ |
1184 | } /* else */ | |
1185 | return pc; | |
1186 | } /* mips32_next_pc */ | |
c906108c SS |
1187 | |
1188 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 1189 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
1190 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
1191 | We dont want to set a single step instruction on the extend instruction | |
1192 | either. | |
c5aa993b | 1193 | */ |
c906108c SS |
1194 | |
1195 | /* Lots of mips16 instruction formats */ | |
1196 | /* Predicting jumps requires itype,ritype,i8type | |
1197 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 1198 | */ |
c906108c SS |
1199 | enum mips16_inst_fmts |
1200 | { | |
c5aa993b JM |
1201 | itype, /* 0 immediate 5,10 */ |
1202 | ritype, /* 1 5,3,8 */ | |
1203 | rrtype, /* 2 5,3,3,5 */ | |
1204 | rritype, /* 3 5,3,3,5 */ | |
1205 | rrrtype, /* 4 5,3,3,3,2 */ | |
1206 | rriatype, /* 5 5,3,3,1,4 */ | |
1207 | shifttype, /* 6 5,3,3,3,2 */ | |
1208 | i8type, /* 7 5,3,8 */ | |
1209 | i8movtype, /* 8 5,3,3,5 */ | |
1210 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1211 | i64type, /* 10 5,3,8 */ | |
1212 | ri64type, /* 11 5,3,3,5 */ | |
1213 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1214 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1215 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1216 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1217 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1218 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1219 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1220 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1221 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1222 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1223 | }; | |
12f02c2a AC |
1224 | /* I am heaping all the fields of the formats into one structure and |
1225 | then, only the fields which are involved in instruction extension */ | |
c906108c | 1226 | struct upk_mips16 |
6d82d43b AC |
1227 | { |
1228 | CORE_ADDR offset; | |
1229 | unsigned int regx; /* Function in i8 type */ | |
1230 | unsigned int regy; | |
1231 | }; | |
c906108c SS |
1232 | |
1233 | ||
12f02c2a AC |
1234 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
1235 | for the bits which make up the immediatate extension. */ | |
c906108c | 1236 | |
12f02c2a AC |
1237 | static CORE_ADDR |
1238 | extended_offset (unsigned int extension) | |
c906108c | 1239 | { |
12f02c2a | 1240 | CORE_ADDR value; |
c5aa993b JM |
1241 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1242 | value = value << 6; | |
1243 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
1244 | value = value << 5; | |
1245 | value |= extension & 0x01f; /* extract 4:0 */ | |
1246 | return value; | |
c906108c SS |
1247 | } |
1248 | ||
1249 | /* Only call this function if you know that this is an extendable | |
1250 | instruction, It wont malfunction, but why make excess remote memory references? | |
1251 | If the immediate operands get sign extended or somthing, do it after | |
1252 | the extension is performed. | |
c5aa993b | 1253 | */ |
c906108c SS |
1254 | /* FIXME: Every one of these cases needs to worry about sign extension |
1255 | when the offset is to be used in relative addressing */ | |
1256 | ||
1257 | ||
12f02c2a | 1258 | static unsigned int |
c5aa993b | 1259 | fetch_mips_16 (CORE_ADDR pc) |
c906108c | 1260 | { |
c5aa993b JM |
1261 | char buf[8]; |
1262 | pc &= 0xfffffffe; /* clear the low order bit */ | |
1263 | target_read_memory (pc, buf, 2); | |
1264 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
1265 | } |
1266 | ||
1267 | static void | |
c5aa993b | 1268 | unpack_mips16 (CORE_ADDR pc, |
12f02c2a AC |
1269 | unsigned int extension, |
1270 | unsigned int inst, | |
6d82d43b | 1271 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 1272 | { |
12f02c2a AC |
1273 | CORE_ADDR offset; |
1274 | int regx; | |
1275 | int regy; | |
1276 | switch (insn_format) | |
c906108c | 1277 | { |
c5aa993b | 1278 | case itype: |
c906108c | 1279 | { |
12f02c2a AC |
1280 | CORE_ADDR value; |
1281 | if (extension) | |
c5aa993b JM |
1282 | { |
1283 | value = extended_offset (extension); | |
1284 | value = value << 11; /* rom for the original value */ | |
6d82d43b | 1285 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1286 | } |
1287 | else | |
c5aa993b | 1288 | { |
12f02c2a | 1289 | value = inst & 0x7ff; |
c5aa993b | 1290 | /* FIXME : Consider sign extension */ |
c906108c | 1291 | } |
12f02c2a AC |
1292 | offset = value; |
1293 | regx = -1; | |
1294 | regy = -1; | |
c906108c | 1295 | } |
c5aa993b JM |
1296 | break; |
1297 | case ritype: | |
1298 | case i8type: | |
1299 | { /* A register identifier and an offset */ | |
c906108c SS |
1300 | /* Most of the fields are the same as I type but the |
1301 | immediate value is of a different length */ | |
12f02c2a AC |
1302 | CORE_ADDR value; |
1303 | if (extension) | |
c906108c | 1304 | { |
c5aa993b JM |
1305 | value = extended_offset (extension); |
1306 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1307 | value |= inst & 0xff; /* eleven bits from instruction */ |
1308 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1309 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1310 | { | |
1311 | value &= ~0x3fff; /* remove the sign bit */ | |
1312 | value = -value; | |
c906108c SS |
1313 | } |
1314 | } | |
c5aa993b JM |
1315 | else |
1316 | { | |
12f02c2a AC |
1317 | value = inst & 0xff; /* 8 bits */ |
1318 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1319 | /* FIXME: Do sign extension , this format needs it */ |
1320 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1321 | { | |
1322 | value &= 0xef; /* remove the sign bit */ | |
1323 | value = -value; | |
1324 | } | |
c5aa993b | 1325 | } |
12f02c2a AC |
1326 | offset = value; |
1327 | regy = -1; | |
c5aa993b | 1328 | break; |
c906108c | 1329 | } |
c5aa993b | 1330 | case jalxtype: |
c906108c | 1331 | { |
c5aa993b | 1332 | unsigned long value; |
12f02c2a AC |
1333 | unsigned int nexthalf; |
1334 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b JM |
1335 | value = value << 16; |
1336 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
1337 | value |= nexthalf; | |
12f02c2a AC |
1338 | offset = value; |
1339 | regx = -1; | |
1340 | regy = -1; | |
c5aa993b | 1341 | break; |
c906108c SS |
1342 | } |
1343 | default: | |
6d82d43b | 1344 | internal_error (__FILE__, __LINE__, "bad switch"); |
c906108c | 1345 | } |
12f02c2a AC |
1346 | upk->offset = offset; |
1347 | upk->regx = regx; | |
1348 | upk->regy = regy; | |
c906108c SS |
1349 | } |
1350 | ||
1351 | ||
c5aa993b JM |
1352 | static CORE_ADDR |
1353 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1354 | { |
c5aa993b | 1355 | return ((offset << 2) | ((pc + 2) & (0xf0000000))); |
c906108c SS |
1356 | } |
1357 | ||
12f02c2a AC |
1358 | static CORE_ADDR |
1359 | extended_mips16_next_pc (CORE_ADDR pc, | |
6d82d43b | 1360 | unsigned int extension, unsigned int insn) |
c906108c | 1361 | { |
12f02c2a AC |
1362 | int op = (insn >> 11); |
1363 | switch (op) | |
c906108c | 1364 | { |
6d82d43b | 1365 | case 2: /* Branch */ |
12f02c2a AC |
1366 | { |
1367 | CORE_ADDR offset; | |
1368 | struct upk_mips16 upk; | |
1369 | unpack_mips16 (pc, extension, insn, itype, &upk); | |
1370 | offset = upk.offset; | |
1371 | if (offset & 0x800) | |
1372 | { | |
1373 | offset &= 0xeff; | |
1374 | offset = -offset; | |
1375 | } | |
1376 | pc += (offset << 1) + 2; | |
1377 | break; | |
1378 | } | |
6d82d43b | 1379 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ |
12f02c2a AC |
1380 | { |
1381 | struct upk_mips16 upk; | |
1382 | unpack_mips16 (pc, extension, insn, jalxtype, &upk); | |
1383 | pc = add_offset_16 (pc, upk.offset); | |
1384 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1385 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1386 | else | |
1387 | pc |= 0x01; | |
1388 | break; | |
1389 | } | |
6d82d43b | 1390 | case 4: /* beqz */ |
12f02c2a AC |
1391 | { |
1392 | struct upk_mips16 upk; | |
1393 | int reg; | |
1394 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1395 | reg = read_signed_register (upk.regx); | |
1396 | if (reg == 0) | |
1397 | pc += (upk.offset << 1) + 2; | |
1398 | else | |
1399 | pc += 2; | |
1400 | break; | |
1401 | } | |
6d82d43b | 1402 | case 5: /* bnez */ |
12f02c2a AC |
1403 | { |
1404 | struct upk_mips16 upk; | |
1405 | int reg; | |
1406 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1407 | reg = read_signed_register (upk.regx); | |
1408 | if (reg != 0) | |
1409 | pc += (upk.offset << 1) + 2; | |
1410 | else | |
1411 | pc += 2; | |
1412 | break; | |
1413 | } | |
6d82d43b | 1414 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
1415 | { |
1416 | struct upk_mips16 upk; | |
1417 | int reg; | |
1418 | unpack_mips16 (pc, extension, insn, i8type, &upk); | |
1419 | /* upk.regx contains the opcode */ | |
1420 | reg = read_signed_register (24); /* Test register is 24 */ | |
1421 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ | |
1422 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1423 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1424 | pc += (upk.offset << 1) + 2; | |
1425 | else | |
1426 | pc += 2; | |
1427 | break; | |
1428 | } | |
6d82d43b | 1429 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
1430 | { |
1431 | struct upk_mips16 upk; | |
1432 | /* upk.fmt = rrtype; */ | |
1433 | op = insn & 0x1f; | |
1434 | if (op == 0) | |
c5aa993b | 1435 | { |
12f02c2a AC |
1436 | int reg; |
1437 | upk.regx = (insn >> 8) & 0x07; | |
1438 | upk.regy = (insn >> 5) & 0x07; | |
1439 | switch (upk.regy) | |
c5aa993b | 1440 | { |
12f02c2a AC |
1441 | case 0: |
1442 | reg = upk.regx; | |
1443 | break; | |
1444 | case 1: | |
1445 | reg = 31; | |
6d82d43b | 1446 | break; /* Function return instruction */ |
12f02c2a AC |
1447 | case 2: |
1448 | reg = upk.regx; | |
1449 | break; | |
1450 | default: | |
1451 | reg = 31; | |
6d82d43b | 1452 | break; /* BOGUS Guess */ |
c906108c | 1453 | } |
12f02c2a | 1454 | pc = read_signed_register (reg); |
c906108c | 1455 | } |
12f02c2a | 1456 | else |
c5aa993b | 1457 | pc += 2; |
12f02c2a AC |
1458 | break; |
1459 | } | |
1460 | case 30: | |
1461 | /* This is an instruction extension. Fetch the real instruction | |
1462 | (which follows the extension) and decode things based on | |
1463 | that. */ | |
1464 | { | |
1465 | pc += 2; | |
1466 | pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc)); | |
1467 | break; | |
1468 | } | |
1469 | default: | |
1470 | { | |
1471 | pc += 2; | |
1472 | break; | |
1473 | } | |
c906108c | 1474 | } |
c5aa993b | 1475 | return pc; |
12f02c2a | 1476 | } |
c906108c | 1477 | |
5a89d8aa | 1478 | static CORE_ADDR |
12f02c2a AC |
1479 | mips16_next_pc (CORE_ADDR pc) |
1480 | { | |
1481 | unsigned int insn = fetch_mips_16 (pc); | |
1482 | return extended_mips16_next_pc (pc, 0, insn); | |
1483 | } | |
1484 | ||
1485 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1486 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1487 | It works by decoding the current instruction and predicting where a |
1488 | branch will go. This isnt hard because all the data is available. | |
1489 | The MIPS32 and MIPS16 variants are quite different */ | |
c5aa993b JM |
1490 | CORE_ADDR |
1491 | mips_next_pc (CORE_ADDR pc) | |
c906108c | 1492 | { |
c5aa993b JM |
1493 | if (pc & 0x01) |
1494 | return mips16_next_pc (pc); | |
1495 | else | |
1496 | return mips32_next_pc (pc); | |
12f02c2a | 1497 | } |
c906108c | 1498 | |
edfae063 AC |
1499 | struct mips_frame_cache |
1500 | { | |
1501 | CORE_ADDR base; | |
1502 | struct trad_frame_saved_reg *saved_regs; | |
1503 | }; | |
1504 | ||
1505 | ||
1506 | static struct mips_frame_cache * | |
1507 | mips_mdebug_frame_cache (struct frame_info *next_frame, void **this_cache) | |
1508 | { | |
1509 | mips_extra_func_info_t proc_desc; | |
1510 | struct mips_frame_cache *cache; | |
1511 | struct gdbarch *gdbarch = get_frame_arch (next_frame); | |
1512 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1513 | /* r0 bit means kernel trap */ | |
1514 | int kernel_trap; | |
1515 | /* What registers have been saved? Bitmasks. */ | |
1516 | unsigned long gen_mask, float_mask; | |
1517 | ||
1518 | if ((*this_cache) != NULL) | |
1519 | return (*this_cache); | |
1520 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); | |
1521 | (*this_cache) = cache; | |
1522 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
1523 | ||
1524 | /* Get the mdebug proc descriptor. */ | |
1525 | proc_desc = find_proc_desc (frame_pc_unwind (next_frame), next_frame, 1); | |
1526 | if (proc_desc == NULL) | |
1527 | /* I'm not sure how/whether this can happen. Normally when we | |
1528 | can't find a proc_desc, we "synthesize" one using | |
1529 | heuristic_proc_desc and set the saved_regs right away. */ | |
1530 | return cache; | |
1531 | ||
1532 | /* Extract the frame's base. */ | |
1533 | cache->base = (frame_unwind_register_signed (next_frame, NUM_REGS + PROC_FRAME_REG (proc_desc)) | |
1534 | + PROC_FRAME_OFFSET (proc_desc) - PROC_FRAME_ADJUST (proc_desc)); | |
1535 | ||
1536 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; | |
1537 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc); | |
1538 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc); | |
1539 | ||
1540 | /* In any frame other than the innermost or a frame interrupted by a | |
1541 | signal, we assume that all registers have been saved. This | |
1542 | assumes that all register saves in a function happen before the | |
1543 | first function call. */ | |
1544 | if (in_prologue (frame_pc_unwind (next_frame), PROC_LOW_ADDR (proc_desc)) | |
1545 | /* Not sure exactly what kernel_trap means, but if it means the | |
1546 | kernel saves the registers without a prologue doing it, we | |
1547 | better not examine the prologue to see whether registers | |
1548 | have been saved yet. */ | |
1549 | && !kernel_trap) | |
1550 | { | |
1551 | /* We need to figure out whether the registers that the | |
1552 | proc_desc claims are saved have been saved yet. */ | |
1553 | ||
1554 | CORE_ADDR addr; | |
1555 | ||
1556 | /* Bitmasks; set if we have found a save for the register. */ | |
1557 | unsigned long gen_save_found = 0; | |
1558 | unsigned long float_save_found = 0; | |
1559 | int mips16; | |
1560 | ||
1561 | /* If the address is odd, assume this is MIPS16 code. */ | |
1562 | addr = PROC_LOW_ADDR (proc_desc); | |
1563 | mips16 = pc_is_mips16 (addr); | |
1564 | ||
1565 | /* Scan through this function's instructions preceding the | |
1566 | current PC, and look for those that save registers. */ | |
1567 | while (addr < frame_pc_unwind (next_frame)) | |
1568 | { | |
1569 | if (mips16) | |
1570 | { | |
1571 | mips16_decode_reg_save (mips16_fetch_instruction (addr), | |
1572 | &gen_save_found); | |
1573 | addr += MIPS16_INSTLEN; | |
1574 | } | |
1575 | else | |
1576 | { | |
1577 | mips32_decode_reg_save (mips32_fetch_instruction (addr), | |
1578 | &gen_save_found, &float_save_found); | |
1579 | addr += MIPS_INSTLEN; | |
1580 | } | |
1581 | } | |
1582 | gen_mask = gen_save_found; | |
1583 | float_mask = float_save_found; | |
1584 | } | |
1585 | ||
1586 | /* Fill in the offsets for the registers which gen_mask says were | |
1587 | saved. */ | |
1588 | { | |
1589 | CORE_ADDR reg_position = (cache->base | |
1590 | + PROC_REG_OFFSET (proc_desc)); | |
1591 | int ireg; | |
1592 | for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1) | |
1593 | if (gen_mask & 0x80000000) | |
1594 | { | |
1595 | cache->saved_regs[NUM_REGS + ireg].addr = reg_position; | |
13326b4e | 1596 | reg_position -= mips_abi_regsize (gdbarch); |
edfae063 AC |
1597 | } |
1598 | } | |
1599 | ||
1600 | /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse | |
1601 | order of that normally used by gcc. Therefore, we have to fetch | |
1602 | the first instruction of the function, and if it's an entry | |
1603 | instruction that saves $s0 or $s1, correct their saved addresses. */ | |
1604 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) | |
1605 | { | |
1606 | ULONGEST inst = mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc)); | |
1607 | if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) | |
1608 | /* entry */ | |
1609 | { | |
1610 | int reg; | |
1611 | int sreg_count = (inst >> 6) & 3; | |
1612 | ||
1613 | /* Check if the ra register was pushed on the stack. */ | |
1614 | CORE_ADDR reg_position = (cache->base | |
1615 | + PROC_REG_OFFSET (proc_desc)); | |
1616 | if (inst & 0x20) | |
13326b4e | 1617 | reg_position -= mips_abi_regsize (gdbarch); |
edfae063 AC |
1618 | |
1619 | /* Check if the s0 and s1 registers were pushed on the | |
1620 | stack. */ | |
1621 | /* NOTE: cagney/2004-02-08: Huh? This is doing no such | |
1622 | check. */ | |
1623 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1624 | { | |
1625 | cache->saved_regs[NUM_REGS + reg].addr = reg_position; | |
13326b4e | 1626 | reg_position -= mips_abi_regsize (gdbarch); |
edfae063 AC |
1627 | } |
1628 | } | |
1629 | } | |
1630 | ||
1631 | /* Fill in the offsets for the registers which float_mask says were | |
1632 | saved. */ | |
1633 | { | |
1634 | CORE_ADDR reg_position = (cache->base | |
1635 | + PROC_FREG_OFFSET (proc_desc)); | |
1636 | int ireg; | |
1637 | /* Fill in the offsets for the float registers which float_mask | |
1638 | says were saved. */ | |
1639 | for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1) | |
1640 | if (float_mask & 0x80000000) | |
1641 | { | |
13326b4e | 1642 | if (mips_abi_regsize (gdbarch) == 4 |
edfae063 AC |
1643 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
1644 | { | |
1645 | /* On a big endian 32 bit ABI, floating point registers | |
1646 | are paired to form doubles such that the most | |
1647 | significant part is in $f[N+1] and the least | |
1648 | significant in $f[N] vis: $f[N+1] ||| $f[N]. The | |
1649 | registers are also spilled as a pair and stored as a | |
1650 | double. | |
1651 | ||
1652 | When little-endian the least significant part is | |
1653 | stored first leading to the memory order $f[N] and | |
1654 | then $f[N+1]. | |
1655 | ||
1656 | Unfortunately, when big-endian the most significant | |
1657 | part of the double is stored first, and the least | |
1658 | significant is stored second. This leads to the | |
1659 | registers being ordered in memory as firt $f[N+1] and | |
1660 | then $f[N]. | |
1661 | ||
1662 | For the big-endian case make certain that the | |
1663 | addresses point at the correct (swapped) locations | |
1664 | $f[N] and $f[N+1] pair (keep in mind that | |
1665 | reg_position is decremented each time through the | |
1666 | loop). */ | |
1667 | if ((ireg & 1)) | |
1668 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg] | |
13326b4e | 1669 | .addr = reg_position - mips_abi_regsize (gdbarch); |
edfae063 AC |
1670 | else |
1671 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg] | |
13326b4e | 1672 | .addr = reg_position + mips_abi_regsize (gdbarch); |
edfae063 AC |
1673 | } |
1674 | else | |
1675 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg] | |
1676 | .addr = reg_position; | |
13326b4e | 1677 | reg_position -= mips_abi_regsize (gdbarch); |
edfae063 AC |
1678 | } |
1679 | ||
1680 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc] | |
1681 | = cache->saved_regs[NUM_REGS + RA_REGNUM]; | |
1682 | } | |
1683 | ||
1684 | /* SP_REGNUM, contains the value and not the address. */ | |
1685 | trad_frame_set_value (cache->saved_regs, NUM_REGS + SP_REGNUM, cache->base); | |
1686 | ||
1687 | return (*this_cache); | |
1688 | } | |
1689 | ||
1690 | static void | |
1691 | mips_mdebug_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
1692 | struct frame_id *this_id) | |
1693 | { | |
1694 | struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame, | |
1695 | this_cache); | |
1696 | (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame)); | |
1697 | } | |
1698 | ||
1699 | static void | |
1700 | mips_mdebug_frame_prev_register (struct frame_info *next_frame, | |
1701 | void **this_cache, | |
1702 | int regnum, int *optimizedp, | |
1703 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1704 | int *realnump, void *valuep) | |
1705 | { | |
1706 | struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame, | |
1707 | this_cache); | |
1708 | trad_frame_prev_register (next_frame, info->saved_regs, regnum, | |
1709 | optimizedp, lvalp, addrp, realnump, valuep); | |
1710 | } | |
1711 | ||
1712 | static const struct frame_unwind mips_mdebug_frame_unwind = | |
1713 | { | |
1714 | NORMAL_FRAME, | |
1715 | mips_mdebug_frame_this_id, | |
1716 | mips_mdebug_frame_prev_register | |
1717 | }; | |
1718 | ||
1719 | static const struct frame_unwind * | |
1720 | mips_mdebug_frame_sniffer (struct frame_info *next_frame) | |
1721 | { | |
1722 | return &mips_mdebug_frame_unwind; | |
1723 | } | |
1724 | ||
1725 | static CORE_ADDR | |
1726 | mips_mdebug_frame_base_address (struct frame_info *next_frame, | |
1727 | void **this_cache) | |
1728 | { | |
1729 | struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame, | |
1730 | this_cache); | |
1731 | return info->base; | |
1732 | } | |
1733 | ||
1734 | static const struct frame_base mips_mdebug_frame_base = { | |
1735 | &mips_mdebug_frame_unwind, | |
1736 | mips_mdebug_frame_base_address, | |
1737 | mips_mdebug_frame_base_address, | |
1738 | mips_mdebug_frame_base_address | |
1739 | }; | |
1740 | ||
1741 | static const struct frame_base * | |
1742 | mips_mdebug_frame_base_sniffer (struct frame_info *next_frame) | |
1743 | { | |
1744 | return &mips_mdebug_frame_base; | |
1745 | } | |
1746 | ||
c906108c | 1747 | static CORE_ADDR |
acdb74a0 | 1748 | read_next_frame_reg (struct frame_info *fi, int regno) |
c906108c | 1749 | { |
a4b8ebc8 AC |
1750 | /* Always a pseudo. */ |
1751 | gdb_assert (regno >= NUM_REGS); | |
f796e4be | 1752 | if (fi == NULL) |
c906108c | 1753 | { |
a4b8ebc8 AC |
1754 | LONGEST val; |
1755 | regcache_cooked_read_signed (current_regcache, regno, &val); | |
1756 | return val; | |
f796e4be | 1757 | } |
a4b8ebc8 AC |
1758 | else if ((regno % NUM_REGS) == SP_REGNUM) |
1759 | /* The SP_REGNUM is special, its value is stored in saved_regs. | |
1760 | In fact, it is so special that it can even only be fetched | |
1761 | using a raw register number! Once this code as been converted | |
1762 | to frame-unwind the problem goes away. */ | |
1763 | return frame_unwind_register_signed (fi, regno % NUM_REGS); | |
f796e4be | 1764 | else |
a4b8ebc8 | 1765 | return frame_unwind_register_signed (fi, regno); |
64159455 | 1766 | |
c906108c SS |
1767 | } |
1768 | ||
1769 | /* mips_addr_bits_remove - remove useless address bits */ | |
1770 | ||
875e1767 | 1771 | static CORE_ADDR |
acdb74a0 | 1772 | mips_addr_bits_remove (CORE_ADDR addr) |
c906108c | 1773 | { |
480d3dd2 | 1774 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
6d82d43b | 1775 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) |
8fa9cfa1 AC |
1776 | /* This hack is a work-around for existing boards using PMON, the |
1777 | simulator, and any other 64-bit targets that doesn't have true | |
1778 | 64-bit addressing. On these targets, the upper 32 bits of | |
1779 | addresses are ignored by the hardware. Thus, the PC or SP are | |
1780 | likely to have been sign extended to all 1s by instruction | |
1781 | sequences that load 32-bit addresses. For example, a typical | |
1782 | piece of code that loads an address is this: | |
1783 | ||
1784 | lui $r2, <upper 16 bits> | |
1785 | ori $r2, <lower 16 bits> | |
1786 | ||
1787 | But the lui sign-extends the value such that the upper 32 bits | |
1788 | may be all 1s. The workaround is simply to mask off these | |
1789 | bits. In the future, gcc may be changed to support true 64-bit | |
1790 | addressing, and this masking will have to be disabled. */ | |
1791 | return addr &= 0xffffffffUL; | |
1792 | else | |
1793 | return addr; | |
c906108c SS |
1794 | } |
1795 | ||
9022177c DJ |
1796 | /* mips_software_single_step() is called just before we want to resume |
1797 | the inferior, if we want to single-step it but there is no hardware | |
75c9abc6 | 1798 | or kernel single-step support (MIPS on GNU/Linux for example). We find |
9022177c DJ |
1799 | the target of the coming instruction and breakpoint it. |
1800 | ||
1801 | single_step is also called just after the inferior stops. If we had | |
1802 | set up a simulated single-step, we undo our damage. */ | |
1803 | ||
1804 | void | |
1805 | mips_software_single_step (enum target_signal sig, int insert_breakpoints_p) | |
1806 | { | |
1807 | static CORE_ADDR next_pc; | |
1808 | typedef char binsn_quantum[BREAKPOINT_MAX]; | |
1809 | static binsn_quantum break_mem; | |
1810 | CORE_ADDR pc; | |
1811 | ||
1812 | if (insert_breakpoints_p) | |
1813 | { | |
b6cb9035 | 1814 | pc = read_register (mips_regnum (current_gdbarch)->pc); |
9022177c DJ |
1815 | next_pc = mips_next_pc (pc); |
1816 | ||
1817 | target_insert_breakpoint (next_pc, break_mem); | |
1818 | } | |
1819 | else | |
1820 | target_remove_breakpoint (next_pc, break_mem); | |
1821 | } | |
1822 | ||
c906108c | 1823 | static struct mips_extra_func_info temp_proc_desc; |
fe29b929 KB |
1824 | |
1825 | /* This hack will go away once the get_prev_frame() code has been | |
1826 | modified to set the frame's type first. That is BEFORE init extra | |
1827 | frame info et.al. is called. This is because it will become | |
1828 | possible to skip the init extra info call for sigtramp and dummy | |
1829 | frames. */ | |
1830 | static CORE_ADDR *temp_saved_regs; | |
c906108c | 1831 | |
e0f7ec59 AC |
1832 | /* Set a register's saved stack address in temp_saved_regs. If an |
1833 | address has already been set for this register, do nothing; this | |
1834 | way we will only recognize the first save of a given register in a | |
a4b8ebc8 AC |
1835 | function prologue. |
1836 | ||
1837 | For simplicity, save the address in both [0 .. NUM_REGS) and | |
1838 | [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range | |
1839 | is used as it is only second range (the ABI instead of ISA | |
1840 | registers) that comes into play when finding saved registers in a | |
1841 | frame. */ | |
c906108c SS |
1842 | |
1843 | static void | |
e0f7ec59 | 1844 | set_reg_offset (CORE_ADDR *saved_regs, int regno, CORE_ADDR offset) |
c906108c | 1845 | { |
e0f7ec59 | 1846 | if (saved_regs[regno] == 0) |
a4b8ebc8 AC |
1847 | { |
1848 | saved_regs[regno + 0 * NUM_REGS] = offset; | |
1849 | saved_regs[regno + 1 * NUM_REGS] = offset; | |
1850 | } | |
c906108c SS |
1851 | } |
1852 | ||
1853 | ||
1854 | /* Test whether the PC points to the return instruction at the | |
1855 | end of a function. */ | |
1856 | ||
c5aa993b | 1857 | static int |
acdb74a0 | 1858 | mips_about_to_return (CORE_ADDR pc) |
c906108c SS |
1859 | { |
1860 | if (pc_is_mips16 (pc)) | |
1861 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler | |
1862 | generates a "jr $ra"; other times it generates code to load | |
1863 | the return address from the stack to an accessible register (such | |
1864 | as $a3), then a "jr" using that register. This second case | |
1865 | is almost impossible to distinguish from an indirect jump | |
1866 | used for switch statements, so we don't even try. */ | |
1867 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
1868 | else | |
1869 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
1870 | } | |
1871 | ||
1872 | ||
1873 | /* This fencepost looks highly suspicious to me. Removing it also | |
1874 | seems suspicious as it could affect remote debugging across serial | |
1875 | lines. */ | |
1876 | ||
1877 | static CORE_ADDR | |
acdb74a0 | 1878 | heuristic_proc_start (CORE_ADDR pc) |
c906108c | 1879 | { |
c5aa993b JM |
1880 | CORE_ADDR start_pc; |
1881 | CORE_ADDR fence; | |
1882 | int instlen; | |
1883 | int seen_adjsp = 0; | |
c906108c | 1884 | |
c5aa993b JM |
1885 | pc = ADDR_BITS_REMOVE (pc); |
1886 | start_pc = pc; | |
1887 | fence = start_pc - heuristic_fence_post; | |
1888 | if (start_pc == 0) | |
1889 | return 0; | |
c906108c | 1890 | |
6d82d43b | 1891 | if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
c5aa993b | 1892 | fence = VM_MIN_ADDRESS; |
c906108c | 1893 | |
c5aa993b | 1894 | instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN; |
c906108c | 1895 | |
c5aa993b JM |
1896 | /* search back for previous return */ |
1897 | for (start_pc -= instlen;; start_pc -= instlen) | |
1898 | if (start_pc < fence) | |
1899 | { | |
1900 | /* It's not clear to me why we reach this point when | |
c0236d92 | 1901 | stop_soon, but with this test, at least we |
c5aa993b JM |
1902 | don't print out warnings for every child forked (eg, on |
1903 | decstation). 22apr93 rich@cygnus.com. */ | |
c0236d92 | 1904 | if (stop_soon == NO_STOP_QUIETLY) |
c906108c | 1905 | { |
c5aa993b JM |
1906 | static int blurb_printed = 0; |
1907 | ||
dc305454 MS |
1908 | warning ("GDB can't find the start of the function at 0x%s.", |
1909 | paddr_nz (pc)); | |
c5aa993b JM |
1910 | |
1911 | if (!blurb_printed) | |
c906108c | 1912 | { |
c5aa993b JM |
1913 | /* This actually happens frequently in embedded |
1914 | development, when you first connect to a board | |
1915 | and your stack pointer and pc are nowhere in | |
1916 | particular. This message needs to give people | |
1917 | in that situation enough information to | |
1918 | determine that it's no big deal. */ | |
1919 | printf_filtered ("\n\ | |
cd0fc7c3 SS |
1920 | GDB is unable to find the start of the function at 0x%s\n\ |
1921 | and thus can't determine the size of that function's stack frame.\n\ | |
1922 | This means that GDB may be unable to access that stack frame, or\n\ | |
1923 | the frames below it.\n\ | |
1924 | This problem is most likely caused by an invalid program counter or\n\ | |
1925 | stack pointer.\n\ | |
1926 | However, if you think GDB should simply search farther back\n\ | |
1927 | from 0x%s for code which looks like the beginning of a\n\ | |
1928 | function, you can increase the range of the search using the `set\n\ | |
6d82d43b | 1929 | heuristic-fence-post' command.\n", paddr_nz (pc), paddr_nz (pc)); |
c5aa993b | 1930 | blurb_printed = 1; |
c906108c | 1931 | } |
c906108c SS |
1932 | } |
1933 | ||
c5aa993b JM |
1934 | return 0; |
1935 | } | |
1936 | else if (pc_is_mips16 (start_pc)) | |
1937 | { | |
1938 | unsigned short inst; | |
1939 | ||
1940 | /* On MIPS16, any one of the following is likely to be the | |
1941 | start of a function: | |
1942 | entry | |
1943 | addiu sp,-n | |
1944 | daddiu sp,-n | |
1945 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
1946 | inst = mips_fetch_instruction (start_pc); | |
1947 | if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
1948 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
1949 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
1950 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
1951 | break; | |
1952 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
1953 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1954 | seen_adjsp = 1; | |
1955 | else | |
1956 | seen_adjsp = 0; | |
1957 | } | |
1958 | else if (mips_about_to_return (start_pc)) | |
1959 | { | |
1960 | start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */ | |
1961 | break; | |
1962 | } | |
1963 | ||
c5aa993b | 1964 | return start_pc; |
c906108c SS |
1965 | } |
1966 | ||
1967 | /* Fetch the immediate value from a MIPS16 instruction. | |
1968 | If the previous instruction was an EXTEND, use it to extend | |
1969 | the upper bits of the immediate value. This is a helper function | |
1970 | for mips16_heuristic_proc_desc. */ | |
1971 | ||
1972 | static int | |
acdb74a0 AC |
1973 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ |
1974 | unsigned short inst, /* current instruction */ | |
6d82d43b AC |
1975 | int nbits, /* number of bits in imm field */ |
1976 | int scale, /* scale factor to be applied to imm */ | |
1977 | int is_signed) /* is the imm field signed? */ | |
c906108c SS |
1978 | { |
1979 | int offset; | |
1980 | ||
1981 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ | |
1982 | { | |
1983 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
c5aa993b | 1984 | if (offset & 0x8000) /* check for negative extend */ |
c906108c SS |
1985 | offset = 0 - (0x10000 - (offset & 0xffff)); |
1986 | return offset | (inst & 0x1f); | |
1987 | } | |
1988 | else | |
1989 | { | |
1990 | int max_imm = 1 << nbits; | |
1991 | int mask = max_imm - 1; | |
1992 | int sign_bit = max_imm >> 1; | |
1993 | ||
1994 | offset = inst & mask; | |
1995 | if (is_signed && (offset & sign_bit)) | |
1996 | offset = 0 - (max_imm - offset); | |
1997 | return offset * scale; | |
1998 | } | |
1999 | } | |
2000 | ||
2001 | ||
2002 | /* Fill in values in temp_proc_desc based on the MIPS16 instruction | |
2003 | stream from start_pc to limit_pc. */ | |
2004 | ||
2005 | static void | |
acdb74a0 AC |
2006 | mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
2007 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
2008 | { |
2009 | CORE_ADDR cur_pc; | |
2010 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
2011 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
2012 | unsigned inst = 0; /* current instruction */ | |
2013 | unsigned entry_inst = 0; /* the entry instruction */ | |
2014 | int reg, offset; | |
480d3dd2 | 2015 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c | 2016 | |
c5aa993b JM |
2017 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */ |
2018 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ | |
c906108c SS |
2019 | |
2020 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN) | |
2021 | { | |
2022 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
2023 | the immediate offset extension from it in mips16_get_imm. */ | |
2024 | prev_inst = inst; | |
2025 | ||
2026 | /* Fetch and decode the instruction. */ | |
2027 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
c5aa993b | 2028 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
6d82d43b | 2029 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ |
c906108c SS |
2030 | { |
2031 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
c5aa993b JM |
2032 | if (offset < 0) /* negative stack adjustment? */ |
2033 | PROC_FRAME_OFFSET (&temp_proc_desc) -= offset; | |
c906108c SS |
2034 | else |
2035 | /* Exit loop if a positive stack adjustment is found, which | |
2036 | usually means that the stack cleanup code in the function | |
2037 | epilogue is reached. */ | |
2038 | break; | |
2039 | } | |
2040 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
2041 | { | |
2042 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2043 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
c5aa993b | 2044 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
e0f7ec59 | 2045 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c906108c SS |
2046 | } |
2047 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
2048 | { | |
2049 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
2050 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2051 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
e0f7ec59 | 2052 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c906108c SS |
2053 | } |
2054 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
2055 | { | |
2056 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
c5aa993b | 2057 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
e0f7ec59 | 2058 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
c906108c SS |
2059 | } |
2060 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
2061 | { | |
2062 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
c5aa993b | 2063 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
e0f7ec59 | 2064 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
c906108c | 2065 | } |
c5aa993b | 2066 | else if (inst == 0x673d) /* move $s1, $sp */ |
c906108c SS |
2067 | { |
2068 | frame_addr = sp; | |
2069 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
2070 | } | |
2071 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
2072 | { | |
2073 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2074 | frame_addr = sp + offset; | |
2075 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
2076 | PROC_FRAME_ADJUST (&temp_proc_desc) = offset; | |
2077 | } | |
2078 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
2079 | { | |
2080 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
2081 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2082 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2083 | set_reg_offset (temp_saved_regs, reg, frame_addr + offset); |
c906108c SS |
2084 | } |
2085 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
2086 | { | |
2087 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
2088 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2089 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2090 | set_reg_offset (temp_saved_regs, reg, frame_addr + offset); |
c906108c | 2091 | } |
c5aa993b JM |
2092 | else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
2093 | entry_inst = inst; /* save for later processing */ | |
c906108c | 2094 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
c5aa993b | 2095 | cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */ |
c906108c SS |
2096 | } |
2097 | ||
c5aa993b JM |
2098 | /* The entry instruction is typically the first instruction in a function, |
2099 | and it stores registers at offsets relative to the value of the old SP | |
2100 | (before the prologue). But the value of the sp parameter to this | |
2101 | function is the new SP (after the prologue has been executed). So we | |
2102 | can't calculate those offsets until we've seen the entire prologue, | |
2103 | and can calculate what the old SP must have been. */ | |
2104 | if (entry_inst != 0) | |
2105 | { | |
2106 | int areg_count = (entry_inst >> 8) & 7; | |
2107 | int sreg_count = (entry_inst >> 6) & 3; | |
c906108c | 2108 | |
c5aa993b JM |
2109 | /* The entry instruction always subtracts 32 from the SP. */ |
2110 | PROC_FRAME_OFFSET (&temp_proc_desc) += 32; | |
c906108c | 2111 | |
c5aa993b JM |
2112 | /* Now we can calculate what the SP must have been at the |
2113 | start of the function prologue. */ | |
2114 | sp += PROC_FRAME_OFFSET (&temp_proc_desc); | |
c906108c | 2115 | |
c5aa993b JM |
2116 | /* Check if a0-a3 were saved in the caller's argument save area. */ |
2117 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
2118 | { | |
2119 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
e0f7ec59 | 2120 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
13326b4e | 2121 | offset += mips_abi_regsize (current_gdbarch); |
c5aa993b | 2122 | } |
c906108c | 2123 | |
c5aa993b JM |
2124 | /* Check if the ra register was pushed on the stack. */ |
2125 | offset = -4; | |
2126 | if (entry_inst & 0x20) | |
2127 | { | |
2128 | PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM; | |
e0f7ec59 | 2129 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
13326b4e | 2130 | offset -= mips_abi_regsize (current_gdbarch); |
c5aa993b | 2131 | } |
c906108c | 2132 | |
c5aa993b JM |
2133 | /* Check if the s0 and s1 registers were pushed on the stack. */ |
2134 | for (reg = 16; reg < sreg_count + 16; reg++) | |
2135 | { | |
2136 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
e0f7ec59 | 2137 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
13326b4e | 2138 | offset -= mips_abi_regsize (current_gdbarch); |
c5aa993b JM |
2139 | } |
2140 | } | |
c906108c SS |
2141 | } |
2142 | ||
2143 | static void | |
fba45db2 KB |
2144 | mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
2145 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
2146 | { |
2147 | CORE_ADDR cur_pc; | |
c5aa993b | 2148 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ |
c906108c | 2149 | restart: |
fe29b929 | 2150 | temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); |
cce74817 | 2151 | memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c5aa993b | 2152 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; |
c906108c SS |
2153 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ |
2154 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN) | |
2155 | { | |
2156 | unsigned long inst, high_word, low_word; | |
2157 | int reg; | |
2158 | ||
2159 | /* Fetch the instruction. */ | |
2160 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
2161 | ||
2162 | /* Save some code by pre-extracting some useful fields. */ | |
2163 | high_word = (inst >> 16) & 0xffff; | |
2164 | low_word = inst & 0xffff; | |
2165 | reg = high_word & 0x1f; | |
2166 | ||
c5aa993b | 2167 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
c906108c SS |
2168 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
2169 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
2170 | { | |
2171 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
c5aa993b | 2172 | PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word; |
c906108c SS |
2173 | else |
2174 | /* Exit loop if a positive stack adjustment is found, which | |
2175 | usually means that the stack cleanup code in the function | |
2176 | epilogue is reached. */ | |
2177 | break; | |
2178 | } | |
2179 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
2180 | { | |
c5aa993b | 2181 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2182 | set_reg_offset (temp_saved_regs, reg, sp + low_word); |
c906108c SS |
2183 | } |
2184 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
2185 | { | |
d5ac5a39 AC |
2186 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and |
2187 | $ra. */ | |
c5aa993b | 2188 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
d5ac5a39 | 2189 | set_reg_offset (temp_saved_regs, reg, sp + low_word); |
c906108c | 2190 | } |
c5aa993b | 2191 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ |
c906108c SS |
2192 | { |
2193 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
c5aa993b JM |
2194 | if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc)) |
2195 | frame_addr = sp + low_word; | |
c906108c SS |
2196 | else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) |
2197 | { | |
2198 | unsigned alloca_adjust; | |
2199 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
a4b8ebc8 | 2200 | frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); |
c5aa993b | 2201 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
c906108c SS |
2202 | if (alloca_adjust > 0) |
2203 | { | |
2204 | /* FP > SP + frame_size. This may be because | |
2205 | * of an alloca or somethings similar. | |
2206 | * Fix sp to "pre-alloca" value, and try again. | |
2207 | */ | |
2208 | sp += alloca_adjust; | |
2209 | goto restart; | |
2210 | } | |
2211 | } | |
2212 | } | |
c5aa993b JM |
2213 | /* move $30,$sp. With different versions of gas this will be either |
2214 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
2215 | Accept any one of these. */ | |
c906108c SS |
2216 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) |
2217 | { | |
2218 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
2219 | if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) | |
2220 | { | |
2221 | unsigned alloca_adjust; | |
2222 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
a4b8ebc8 | 2223 | frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); |
c5aa993b | 2224 | alloca_adjust = (unsigned) (frame_addr - sp); |
c906108c SS |
2225 | if (alloca_adjust > 0) |
2226 | { | |
2227 | /* FP > SP + frame_size. This may be because | |
2228 | * of an alloca or somethings similar. | |
2229 | * Fix sp to "pre-alloca" value, and try again. | |
2230 | */ | |
2231 | sp += alloca_adjust; | |
2232 | goto restart; | |
2233 | } | |
2234 | } | |
2235 | } | |
c5aa993b | 2236 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ |
c906108c | 2237 | { |
c5aa993b | 2238 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2239 | set_reg_offset (temp_saved_regs, reg, frame_addr + low_word); |
c906108c SS |
2240 | } |
2241 | } | |
2242 | } | |
2243 | ||
2244 | static mips_extra_func_info_t | |
acdb74a0 | 2245 | heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
479412cd | 2246 | struct frame_info *next_frame, int cur_frame) |
c906108c | 2247 | { |
479412cd DJ |
2248 | CORE_ADDR sp; |
2249 | ||
2250 | if (cur_frame) | |
a4b8ebc8 | 2251 | sp = read_next_frame_reg (next_frame, NUM_REGS + SP_REGNUM); |
479412cd DJ |
2252 | else |
2253 | sp = 0; | |
c906108c | 2254 | |
c5aa993b JM |
2255 | if (start_pc == 0) |
2256 | return NULL; | |
2257 | memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc)); | |
fe29b929 | 2258 | temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); |
3758ac48 | 2259 | memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
2260 | PROC_LOW_ADDR (&temp_proc_desc) = start_pc; |
2261 | PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM; | |
2262 | PROC_PC_REG (&temp_proc_desc) = RA_REGNUM; | |
2263 | ||
2264 | if (start_pc + 200 < limit_pc) | |
2265 | limit_pc = start_pc + 200; | |
2266 | if (pc_is_mips16 (start_pc)) | |
2267 | mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
2268 | else | |
2269 | mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
2270 | return &temp_proc_desc; | |
2271 | } | |
2272 | ||
6c0d6680 DJ |
2273 | struct mips_objfile_private |
2274 | { | |
2275 | bfd_size_type size; | |
2276 | char *contents; | |
2277 | }; | |
2278 | ||
2279 | /* Global used to communicate between non_heuristic_proc_desc and | |
2280 | compare_pdr_entries within qsort (). */ | |
2281 | static bfd *the_bfd; | |
2282 | ||
2283 | static int | |
2284 | compare_pdr_entries (const void *a, const void *b) | |
2285 | { | |
2286 | CORE_ADDR lhs = bfd_get_32 (the_bfd, (bfd_byte *) a); | |
2287 | CORE_ADDR rhs = bfd_get_32 (the_bfd, (bfd_byte *) b); | |
2288 | ||
2289 | if (lhs < rhs) | |
2290 | return -1; | |
2291 | else if (lhs == rhs) | |
2292 | return 0; | |
2293 | else | |
2294 | return 1; | |
2295 | } | |
2296 | ||
c906108c | 2297 | static mips_extra_func_info_t |
acdb74a0 | 2298 | non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr) |
c906108c SS |
2299 | { |
2300 | CORE_ADDR startaddr; | |
2301 | mips_extra_func_info_t proc_desc; | |
c5aa993b | 2302 | struct block *b = block_for_pc (pc); |
c906108c | 2303 | struct symbol *sym; |
6c0d6680 DJ |
2304 | struct obj_section *sec; |
2305 | struct mips_objfile_private *priv; | |
2306 | ||
ae45cd16 | 2307 | if (DEPRECATED_PC_IN_CALL_DUMMY (pc, 0, 0)) |
6c0d6680 | 2308 | return NULL; |
c906108c SS |
2309 | |
2310 | find_pc_partial_function (pc, NULL, &startaddr, NULL); | |
2311 | if (addrptr) | |
2312 | *addrptr = startaddr; | |
6c0d6680 DJ |
2313 | |
2314 | priv = NULL; | |
2315 | ||
2316 | sec = find_pc_section (pc); | |
2317 | if (sec != NULL) | |
c906108c | 2318 | { |
8d5f9dcb | 2319 | priv = (struct mips_objfile_private *) objfile_data (sec->objfile, mips_pdr_data); |
6c0d6680 DJ |
2320 | |
2321 | /* Search the ".pdr" section generated by GAS. This includes most of | |
6d82d43b | 2322 | the information normally found in ECOFF PDRs. */ |
6c0d6680 DJ |
2323 | |
2324 | the_bfd = sec->objfile->obfd; | |
2325 | if (priv == NULL | |
2326 | && (the_bfd->format == bfd_object | |
2327 | && bfd_get_flavour (the_bfd) == bfd_target_elf_flavour | |
2328 | && elf_elfheader (the_bfd)->e_ident[EI_CLASS] == ELFCLASS64)) | |
2329 | { | |
2330 | /* Right now GAS only outputs the address as a four-byte sequence. | |
2331 | This means that we should not bother with this method on 64-bit | |
2332 | targets (until that is fixed). */ | |
2333 | ||
8b92e4d5 | 2334 | priv = obstack_alloc (&sec->objfile->objfile_obstack, |
6c0d6680 DJ |
2335 | sizeof (struct mips_objfile_private)); |
2336 | priv->size = 0; | |
8d5f9dcb | 2337 | set_objfile_data (sec->objfile, mips_pdr_data, priv); |
6c0d6680 DJ |
2338 | } |
2339 | else if (priv == NULL) | |
2340 | { | |
2341 | asection *bfdsec; | |
2342 | ||
8b92e4d5 | 2343 | priv = obstack_alloc (&sec->objfile->objfile_obstack, |
6c0d6680 DJ |
2344 | sizeof (struct mips_objfile_private)); |
2345 | ||
2346 | bfdsec = bfd_get_section_by_name (sec->objfile->obfd, ".pdr"); | |
2347 | if (bfdsec != NULL) | |
2348 | { | |
2349 | priv->size = bfd_section_size (sec->objfile->obfd, bfdsec); | |
8b92e4d5 | 2350 | priv->contents = obstack_alloc (&sec->objfile->objfile_obstack, |
6c0d6680 DJ |
2351 | priv->size); |
2352 | bfd_get_section_contents (sec->objfile->obfd, bfdsec, | |
2353 | priv->contents, 0, priv->size); | |
2354 | ||
2355 | /* In general, the .pdr section is sorted. However, in the | |
6d82d43b AC |
2356 | presence of multiple code sections (and other corner cases) |
2357 | it can become unsorted. Sort it so that we can use a faster | |
2358 | binary search. */ | |
2359 | qsort (priv->contents, priv->size / 32, 32, | |
2360 | compare_pdr_entries); | |
6c0d6680 DJ |
2361 | } |
2362 | else | |
2363 | priv->size = 0; | |
2364 | ||
8d5f9dcb | 2365 | set_objfile_data (sec->objfile, mips_pdr_data, priv); |
6c0d6680 DJ |
2366 | } |
2367 | the_bfd = NULL; | |
2368 | ||
2369 | if (priv->size != 0) | |
2370 | { | |
2371 | int low, mid, high; | |
2372 | char *ptr; | |
34fcf120 | 2373 | CORE_ADDR pdr_pc; |
6c0d6680 DJ |
2374 | |
2375 | low = 0; | |
2376 | high = priv->size / 32; | |
2377 | ||
34fcf120 DJ |
2378 | /* We've found a .pdr section describing this objfile. We want to |
2379 | find the entry which describes this code address. The .pdr | |
2380 | information is not very descriptive; we have only a function | |
2381 | start address. We have to look for the closest entry, because | |
2382 | the local symbol at the beginning of this function may have | |
2383 | been stripped - so if we ask the symbol table for the start | |
2384 | address we may get a preceding global function. */ | |
2385 | ||
2386 | /* First, find the last .pdr entry starting at or before PC. */ | |
6c0d6680 DJ |
2387 | do |
2388 | { | |
6c0d6680 DJ |
2389 | mid = (low + high) / 2; |
2390 | ||
2391 | ptr = priv->contents + mid * 32; | |
2392 | pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr); | |
2393 | pdr_pc += ANOFFSET (sec->objfile->section_offsets, | |
2394 | SECT_OFF_TEXT (sec->objfile)); | |
34fcf120 DJ |
2395 | |
2396 | if (pdr_pc > pc) | |
6c0d6680 DJ |
2397 | high = mid; |
2398 | else | |
2399 | low = mid + 1; | |
2400 | } | |
2401 | while (low != high); | |
2402 | ||
34fcf120 DJ |
2403 | /* Both low and high point one past the PDR of interest. If |
2404 | both are zero, that means this PC is before any region | |
2405 | covered by a PDR, i.e. pdr_pc for the first PDR entry is | |
2406 | greater than PC. */ | |
2407 | if (low > 0) | |
2408 | { | |
2409 | ptr = priv->contents + (low - 1) * 32; | |
2410 | pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr); | |
2411 | pdr_pc += ANOFFSET (sec->objfile->section_offsets, | |
2412 | SECT_OFF_TEXT (sec->objfile)); | |
2413 | } | |
2414 | ||
2415 | /* We don't have a range, so we have no way to know for sure | |
2416 | whether we're in the correct PDR or a PDR for a preceding | |
2417 | function and the current function was a stripped local | |
2418 | symbol. But if the PDR's PC is at least as great as the | |
2419 | best guess from the symbol table, assume that it does cover | |
2420 | the right area; if a .pdr section is present at all then | |
2421 | nearly every function will have an entry. The biggest exception | |
2422 | will be the dynamic linker stubs; conveniently these are | |
2423 | placed before .text instead of after. */ | |
2424 | ||
2425 | if (pc >= pdr_pc && pdr_pc >= startaddr) | |
6c0d6680 DJ |
2426 | { |
2427 | struct symbol *sym = find_pc_function (pc); | |
2428 | ||
34fcf120 DJ |
2429 | if (addrptr) |
2430 | *addrptr = pdr_pc; | |
2431 | ||
6c0d6680 DJ |
2432 | /* Fill in what we need of the proc_desc. */ |
2433 | proc_desc = (mips_extra_func_info_t) | |
8b92e4d5 | 2434 | obstack_alloc (&sec->objfile->objfile_obstack, |
6c0d6680 | 2435 | sizeof (struct mips_extra_func_info)); |
34fcf120 | 2436 | PROC_LOW_ADDR (proc_desc) = pdr_pc; |
6c0d6680 DJ |
2437 | |
2438 | /* Only used for dummy frames. */ | |
2439 | PROC_HIGH_ADDR (proc_desc) = 0; | |
2440 | ||
2441 | PROC_FRAME_OFFSET (proc_desc) | |
2442 | = bfd_get_32 (sec->objfile->obfd, ptr + 20); | |
2443 | PROC_FRAME_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2444 | ptr + 24); | |
2445 | PROC_FRAME_ADJUST (proc_desc) = 0; | |
2446 | PROC_REG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2447 | ptr + 4); | |
2448 | PROC_FREG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2449 | ptr + 12); | |
2450 | PROC_REG_OFFSET (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2451 | ptr + 8); | |
2452 | PROC_FREG_OFFSET (proc_desc) | |
2453 | = bfd_get_32 (sec->objfile->obfd, ptr + 16); | |
2454 | PROC_PC_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2455 | ptr + 28); | |
2456 | proc_desc->pdr.isym = (long) sym; | |
2457 | ||
2458 | return proc_desc; | |
2459 | } | |
2460 | } | |
c906108c SS |
2461 | } |
2462 | ||
6c0d6680 DJ |
2463 | if (b == NULL) |
2464 | return NULL; | |
2465 | ||
2466 | if (startaddr > BLOCK_START (b)) | |
2467 | { | |
2468 | /* This is the "pathological" case referred to in a comment in | |
6d82d43b AC |
2469 | print_frame_info. It might be better to move this check into |
2470 | symbol reading. */ | |
6c0d6680 DJ |
2471 | return NULL; |
2472 | } | |
2473 | ||
176620f1 | 2474 | sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_DOMAIN, 0, NULL); |
6c0d6680 | 2475 | |
c906108c SS |
2476 | /* If we never found a PDR for this function in symbol reading, then |
2477 | examine prologues to find the information. */ | |
2478 | if (sym) | |
2479 | { | |
2480 | proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); | |
2481 | if (PROC_FRAME_REG (proc_desc) == -1) | |
2482 | return NULL; | |
2483 | else | |
2484 | return proc_desc; | |
2485 | } | |
2486 | else | |
2487 | return NULL; | |
2488 | } | |
2489 | ||
2490 | ||
2491 | static mips_extra_func_info_t | |
479412cd | 2492 | find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame) |
c906108c SS |
2493 | { |
2494 | mips_extra_func_info_t proc_desc; | |
4e0df2df | 2495 | CORE_ADDR startaddr = 0; |
c906108c SS |
2496 | |
2497 | proc_desc = non_heuristic_proc_desc (pc, &startaddr); | |
2498 | ||
2499 | if (proc_desc) | |
2500 | { | |
2501 | /* IF this is the topmost frame AND | |
2502 | * (this proc does not have debugging information OR | |
2503 | * the PC is in the procedure prologue) | |
2504 | * THEN create a "heuristic" proc_desc (by analyzing | |
2505 | * the actual code) to replace the "official" proc_desc. | |
2506 | */ | |
2507 | if (next_frame == NULL) | |
2508 | { | |
2509 | struct symtab_and_line val; | |
2510 | struct symbol *proc_symbol = | |
c86b5b38 | 2511 | PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc); |
c906108c SS |
2512 | |
2513 | if (proc_symbol) | |
2514 | { | |
2515 | val = find_pc_line (BLOCK_START | |
6d82d43b | 2516 | (SYMBOL_BLOCK_VALUE (proc_symbol)), 0); |
c906108c SS |
2517 | val.pc = val.end ? val.end : pc; |
2518 | } | |
2519 | if (!proc_symbol || pc < val.pc) | |
2520 | { | |
2521 | mips_extra_func_info_t found_heuristic = | |
c86b5b38 MS |
2522 | heuristic_proc_desc (PROC_LOW_ADDR (proc_desc), |
2523 | pc, next_frame, cur_frame); | |
c906108c SS |
2524 | if (found_heuristic) |
2525 | proc_desc = found_heuristic; | |
2526 | } | |
2527 | } | |
2528 | } | |
2529 | else | |
2530 | { | |
2531 | /* Is linked_proc_desc_table really necessary? It only seems to be used | |
c5aa993b JM |
2532 | by procedure call dummys. However, the procedures being called ought |
2533 | to have their own proc_descs, and even if they don't, | |
2534 | heuristic_proc_desc knows how to create them! */ | |
c906108c | 2535 | |
aa1ee363 | 2536 | struct linked_proc_info *link; |
c906108c SS |
2537 | |
2538 | for (link = linked_proc_desc_table; link; link = link->next) | |
c5aa993b JM |
2539 | if (PROC_LOW_ADDR (&link->info) <= pc |
2540 | && PROC_HIGH_ADDR (&link->info) > pc) | |
c906108c SS |
2541 | return &link->info; |
2542 | ||
2543 | if (startaddr == 0) | |
2544 | startaddr = heuristic_proc_start (pc); | |
2545 | ||
6d82d43b | 2546 | proc_desc = heuristic_proc_desc (startaddr, pc, next_frame, cur_frame); |
c906108c SS |
2547 | } |
2548 | return proc_desc; | |
2549 | } | |
2550 | ||
c906108c SS |
2551 | /* MIPS stack frames are almost impenetrable. When execution stops, |
2552 | we basically have to look at symbol information for the function | |
2553 | that we stopped in, which tells us *which* register (if any) is | |
2554 | the base of the frame pointer, and what offset from that register | |
361d1df0 | 2555 | the frame itself is at. |
c906108c SS |
2556 | |
2557 | This presents a problem when trying to examine a stack in memory | |
2558 | (that isn't executing at the moment), using the "frame" command. We | |
2559 | don't have a PC, nor do we have any registers except SP. | |
2560 | ||
2561 | This routine takes two arguments, SP and PC, and tries to make the | |
2562 | cached frames look as if these two arguments defined a frame on the | |
2563 | cache. This allows the rest of info frame to extract the important | |
2564 | arguments without difficulty. */ | |
2565 | ||
2566 | struct frame_info * | |
acdb74a0 | 2567 | setup_arbitrary_frame (int argc, CORE_ADDR *argv) |
c906108c SS |
2568 | { |
2569 | if (argc != 2) | |
2570 | error ("MIPS frame specifications require two arguments: sp and pc"); | |
2571 | ||
2572 | return create_new_frame (argv[0], argv[1]); | |
2573 | } | |
2574 | ||
f09ded24 AC |
2575 | /* According to the current ABI, should the type be passed in a |
2576 | floating-point register (assuming that there is space)? When there | |
2577 | is no FPU, FP are not even considered as possibile candidates for | |
2578 | FP registers and, consequently this returns false - forces FP | |
2579 | arguments into integer registers. */ | |
2580 | ||
2581 | static int | |
2582 | fp_register_arg_p (enum type_code typecode, struct type *arg_type) | |
2583 | { | |
2584 | return ((typecode == TYPE_CODE_FLT | |
2585 | || (MIPS_EABI | |
6d82d43b AC |
2586 | && (typecode == TYPE_CODE_STRUCT |
2587 | || typecode == TYPE_CODE_UNION) | |
f09ded24 AC |
2588 | && TYPE_NFIELDS (arg_type) == 1 |
2589 | && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT)) | |
c86b5b38 | 2590 | && MIPS_FPU_TYPE != MIPS_FPU_NONE); |
f09ded24 AC |
2591 | } |
2592 | ||
49e790b0 DJ |
2593 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
2594 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
2595 | ||
2596 | static int | |
2597 | mips_type_needs_double_align (struct type *type) | |
2598 | { | |
2599 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2600 | |
49e790b0 DJ |
2601 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2602 | return 1; | |
2603 | else if (typecode == TYPE_CODE_STRUCT) | |
2604 | { | |
2605 | if (TYPE_NFIELDS (type) < 1) | |
2606 | return 0; | |
2607 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2608 | } | |
2609 | else if (typecode == TYPE_CODE_UNION) | |
2610 | { | |
361d1df0 | 2611 | int i, n; |
49e790b0 DJ |
2612 | |
2613 | n = TYPE_NFIELDS (type); | |
2614 | for (i = 0; i < n; i++) | |
2615 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2616 | return 1; | |
2617 | return 0; | |
2618 | } | |
2619 | return 0; | |
2620 | } | |
2621 | ||
dc604539 AC |
2622 | /* Adjust the address downward (direction of stack growth) so that it |
2623 | is correctly aligned for a new stack frame. */ | |
2624 | static CORE_ADDR | |
2625 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2626 | { | |
5b03f266 | 2627 | return align_down (addr, 16); |
dc604539 AC |
2628 | } |
2629 | ||
6d82d43b AC |
2630 | /* Determine how a return value is stored within the MIPS register |
2631 | file, given the return type `valtype'. */ | |
2632 | ||
2633 | struct return_value_word | |
2634 | { | |
2635 | int len; | |
2636 | int reg; | |
2637 | int reg_offset; | |
2638 | int buf_offset; | |
2639 | }; | |
2640 | ||
2641 | static void | |
2642 | return_value_location (struct type *valtype, | |
2643 | struct return_value_word *hi, | |
2644 | struct return_value_word *lo) | |
2645 | { | |
2646 | int len = TYPE_LENGTH (valtype); | |
2647 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2648 | ||
2649 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT | |
2650 | && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8)) | |
2651 | || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4))) | |
2652 | { | |
ceae6e75 | 2653 | if (mips_abi_regsize (current_gdbarch) < 8 && len == 8) |
6d82d43b AC |
2654 | { |
2655 | /* We need to break a 64bit float in two 32 bit halves and | |
ceae6e75 | 2656 | spread them across a floating-point register pair. */ |
6d82d43b AC |
2657 | lo->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
2658 | hi->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 0 : 4; | |
2659 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
2660 | && register_size (current_gdbarch, | |
2661 | mips_regnum (current_gdbarch)-> | |
2662 | fp0) == 8) ? 4 : 0); | |
2663 | hi->reg_offset = lo->reg_offset; | |
2664 | lo->reg = mips_regnum (current_gdbarch)->fp0 + 0; | |
2665 | hi->reg = mips_regnum (current_gdbarch)->fp0 + 1; | |
2666 | lo->len = 4; | |
2667 | hi->len = 4; | |
2668 | } | |
2669 | else | |
2670 | { | |
2671 | /* The floating point value fits in a single floating-point | |
2672 | register. */ | |
2673 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
2674 | && register_size (current_gdbarch, | |
2675 | mips_regnum (current_gdbarch)-> | |
2676 | fp0) == 8 | |
2677 | && len == 4) ? 4 : 0); | |
2678 | lo->reg = mips_regnum (current_gdbarch)->fp0; | |
2679 | lo->len = len; | |
2680 | lo->buf_offset = 0; | |
2681 | hi->len = 0; | |
2682 | hi->reg_offset = 0; | |
2683 | hi->buf_offset = 0; | |
2684 | hi->reg = 0; | |
2685 | } | |
2686 | } | |
2687 | else | |
2688 | { | |
2689 | /* Locate a result possibly spread across two registers. */ | |
2690 | int regnum = 2; | |
2691 | lo->reg = regnum + 0; | |
2692 | hi->reg = regnum + 1; | |
2693 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
13326b4e | 2694 | && len < mips_abi_regsize (current_gdbarch)) |
6d82d43b AC |
2695 | { |
2696 | /* "un-left-justify" the value in the low register */ | |
13326b4e | 2697 | lo->reg_offset = mips_abi_regsize (current_gdbarch) - len; |
6d82d43b AC |
2698 | lo->len = len; |
2699 | hi->reg_offset = 0; | |
2700 | hi->len = 0; | |
2701 | } | |
13326b4e AC |
2702 | else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG && len > mips_abi_regsize (current_gdbarch) /* odd-size structs */ |
2703 | && len < mips_abi_regsize (current_gdbarch) * 2 | |
6d82d43b AC |
2704 | && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || |
2705 | TYPE_CODE (valtype) == TYPE_CODE_UNION)) | |
2706 | { | |
2707 | /* "un-left-justify" the value spread across two registers. */ | |
13326b4e AC |
2708 | lo->reg_offset = 2 * mips_abi_regsize (current_gdbarch) - len; |
2709 | lo->len = mips_abi_regsize (current_gdbarch) - lo->reg_offset; | |
6d82d43b AC |
2710 | hi->reg_offset = 0; |
2711 | hi->len = len - lo->len; | |
2712 | } | |
2713 | else | |
2714 | { | |
2715 | /* Only perform a partial copy of the second register. */ | |
2716 | lo->reg_offset = 0; | |
2717 | hi->reg_offset = 0; | |
13326b4e | 2718 | if (len > mips_abi_regsize (current_gdbarch)) |
6d82d43b | 2719 | { |
13326b4e AC |
2720 | lo->len = mips_abi_regsize (current_gdbarch); |
2721 | hi->len = len - mips_abi_regsize (current_gdbarch); | |
6d82d43b AC |
2722 | } |
2723 | else | |
2724 | { | |
2725 | lo->len = len; | |
2726 | hi->len = 0; | |
2727 | } | |
2728 | } | |
2729 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
2730 | && register_size (current_gdbarch, regnum) == 8 | |
13326b4e | 2731 | && mips_abi_regsize (current_gdbarch) == 4) |
6d82d43b AC |
2732 | { |
2733 | /* Account for the fact that only the least-signficant part | |
2734 | of the register is being used */ | |
2735 | lo->reg_offset += 4; | |
2736 | hi->reg_offset += 4; | |
2737 | } | |
2738 | lo->buf_offset = 0; | |
2739 | hi->buf_offset = lo->len; | |
2740 | } | |
2741 | } | |
2742 | ||
2743 | /* Should call_function allocate stack space for a struct return? */ | |
2744 | ||
2745 | static int | |
2746 | mips_eabi_use_struct_convention (int gcc_p, struct type *type) | |
2747 | { | |
2748 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
13326b4e | 2749 | return (TYPE_LENGTH (type) > 2 * mips_abi_regsize (current_gdbarch)); |
6d82d43b AC |
2750 | } |
2751 | ||
2752 | /* Should call_function pass struct by reference? | |
2753 | For each architecture, structs are passed either by | |
2754 | value or by reference, depending on their size. */ | |
2755 | ||
2756 | static int | |
2757 | mips_eabi_reg_struct_has_addr (int gcc_p, struct type *type) | |
2758 | { | |
2759 | enum type_code typecode = TYPE_CODE (check_typedef (type)); | |
2760 | int len = TYPE_LENGTH (check_typedef (type)); | |
2761 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2762 | ||
2763 | if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
13326b4e | 2764 | return (len > mips_abi_regsize (current_gdbarch)); |
6d82d43b AC |
2765 | |
2766 | return 0; | |
2767 | } | |
2768 | ||
f7ab6ec6 | 2769 | static CORE_ADDR |
25ab4790 | 2770 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
6d82d43b AC |
2771 | struct regcache *regcache, CORE_ADDR bp_addr, |
2772 | int nargs, struct value **args, CORE_ADDR sp, | |
2773 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
2774 | { |
2775 | int argreg; | |
2776 | int float_argreg; | |
2777 | int argnum; | |
2778 | int len = 0; | |
2779 | int stack_offset = 0; | |
480d3dd2 | 2780 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
c906108c | 2781 | |
25ab4790 AC |
2782 | /* For shared libraries, "t9" needs to point at the function |
2783 | address. */ | |
2784 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
2785 | ||
2786 | /* Set the return address register to point to the entry point of | |
2787 | the program, where a breakpoint lies in wait. */ | |
2788 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
2789 | ||
c906108c | 2790 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2791 | are properly aligned. The stack has to be at least 64-bit |
2792 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2793 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2794 | aligned, so we round to this widest known alignment. */ | |
2795 | ||
5b03f266 AC |
2796 | sp = align_down (sp, 16); |
2797 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 2798 | |
46e0f506 | 2799 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2800 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2801 | passed in registers, but that's OK. */ |
c906108c | 2802 | for (argnum = 0; argnum < nargs; argnum++) |
6d82d43b | 2803 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
13326b4e | 2804 | mips_stack_argsize (gdbarch)); |
5b03f266 | 2805 | sp -= align_up (len, 16); |
c906108c | 2806 | |
9ace0497 | 2807 | if (mips_debug) |
6d82d43b | 2808 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
2809 | "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n", |
2810 | paddr_nz (sp), (long) align_up (len, 16)); | |
9ace0497 | 2811 | |
c906108c SS |
2812 | /* Initialize the integer and float register pointers. */ |
2813 | argreg = A0_REGNUM; | |
56cea623 | 2814 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
c906108c | 2815 | |
46e0f506 | 2816 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2817 | if (struct_return) |
9ace0497 AC |
2818 | { |
2819 | if (mips_debug) | |
2820 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2821 | "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 2822 | argreg, paddr_nz (struct_addr)); |
9ace0497 AC |
2823 | write_register (argreg++, struct_addr); |
2824 | } | |
c906108c SS |
2825 | |
2826 | /* Now load as many as possible of the first arguments into | |
2827 | registers, and push the rest onto the stack. Loop thru args | |
2828 | from first to last. */ | |
2829 | for (argnum = 0; argnum < nargs; argnum++) | |
2830 | { | |
2831 | char *val; | |
d9d9c31f | 2832 | char valbuf[MAX_REGISTER_SIZE]; |
ea7c478f | 2833 | struct value *arg = args[argnum]; |
c906108c SS |
2834 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); |
2835 | int len = TYPE_LENGTH (arg_type); | |
2836 | enum type_code typecode = TYPE_CODE (arg_type); | |
2837 | ||
9ace0497 AC |
2838 | if (mips_debug) |
2839 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2840 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 2841 | argnum + 1, len, (int) typecode); |
9ace0497 | 2842 | |
c906108c | 2843 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 2844 | reference. */ |
13326b4e | 2845 | if (len > mips_abi_regsize (gdbarch) |
9ace0497 | 2846 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 2847 | { |
13326b4e | 2848 | store_unsigned_integer (valbuf, mips_abi_regsize (gdbarch), |
480d3dd2 | 2849 | VALUE_ADDRESS (arg)); |
c906108c | 2850 | typecode = TYPE_CODE_PTR; |
13326b4e | 2851 | len = mips_abi_regsize (gdbarch); |
c906108c | 2852 | val = valbuf; |
9ace0497 AC |
2853 | if (mips_debug) |
2854 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
2855 | } |
2856 | else | |
c5aa993b | 2857 | val = (char *) VALUE_CONTENTS (arg); |
c906108c SS |
2858 | |
2859 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
2860 | even-numbered floating point register. Round the FP register |
2861 | up before the check to see if there are any FP registers | |
46e0f506 MS |
2862 | left. Non MIPS_EABI targets also pass the FP in the integer |
2863 | registers so also round up normal registers. */ | |
ceae6e75 AC |
2864 | if (mips_abi_regsize (gdbarch) < 8 |
2865 | && fp_register_arg_p (typecode, arg_type)) | |
acdb74a0 AC |
2866 | { |
2867 | if ((float_argreg & 1)) | |
2868 | float_argreg++; | |
2869 | } | |
c906108c SS |
2870 | |
2871 | /* Floating point arguments passed in registers have to be | |
2872 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2873 | are passed in register pairs; the even register gets |
2874 | the low word, and the odd register gets the high word. | |
2875 | On non-EABI processors, the first two floating point arguments are | |
2876 | also copied to general registers, because MIPS16 functions | |
2877 | don't use float registers for arguments. This duplication of | |
2878 | arguments in general registers can't hurt non-MIPS16 functions | |
2879 | because those registers are normally skipped. */ | |
1012bd0e EZ |
2880 | /* MIPS_EABI squeezes a struct that contains a single floating |
2881 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 2882 | stack. */ |
f09ded24 AC |
2883 | if (fp_register_arg_p (typecode, arg_type) |
2884 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
c906108c | 2885 | { |
ceae6e75 | 2886 | if (mips_abi_regsize (gdbarch) < 8 && len == 8) |
c906108c | 2887 | { |
d7449b42 | 2888 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
c906108c SS |
2889 | unsigned long regval; |
2890 | ||
2891 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 2892 | regval = extract_unsigned_integer (val + low_offset, 4); |
9ace0497 | 2893 | if (mips_debug) |
acdb74a0 | 2894 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2895 | float_argreg, phex (regval, 4)); |
c906108c | 2896 | write_register (float_argreg++, regval); |
c906108c SS |
2897 | |
2898 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 2899 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
9ace0497 | 2900 | if (mips_debug) |
acdb74a0 | 2901 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2902 | float_argreg, phex (regval, 4)); |
c906108c | 2903 | write_register (float_argreg++, regval); |
c906108c SS |
2904 | } |
2905 | else | |
2906 | { | |
2907 | /* This is a floating point value that fits entirely | |
2908 | in a single register. */ | |
53a5351d | 2909 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 2910 | above to ensure that it is even register aligned. */ |
9ace0497 AC |
2911 | LONGEST regval = extract_unsigned_integer (val, len); |
2912 | if (mips_debug) | |
acdb74a0 | 2913 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2914 | float_argreg, phex (regval, len)); |
c906108c | 2915 | write_register (float_argreg++, regval); |
c906108c SS |
2916 | } |
2917 | } | |
2918 | else | |
2919 | { | |
2920 | /* Copy the argument to general registers or the stack in | |
2921 | register-sized pieces. Large arguments are split between | |
2922 | registers and stack. */ | |
4246e332 | 2923 | /* Note: structs whose size is not a multiple of |
d5ac5a39 AC |
2924 | mips_abi_regsize() are treated specially: Irix cc passes |
2925 | them in registers where gcc sometimes puts them on the | |
2926 | stack. For maximum compatibility, we will put them in | |
2927 | both places. */ | |
13326b4e AC |
2928 | int odd_sized_struct = ((len > mips_abi_regsize (gdbarch)) |
2929 | && (len % mips_abi_regsize (gdbarch) != 0)); | |
46e0f506 | 2930 | |
f09ded24 | 2931 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 2932 | register are only written to memory. */ |
c906108c SS |
2933 | while (len > 0) |
2934 | { | |
ebafbe83 | 2935 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 2936 | int stack_used_p = 0; |
13326b4e AC |
2937 | int partial_len = (len < mips_abi_regsize (gdbarch) |
2938 | ? len : mips_abi_regsize (gdbarch)); | |
c906108c | 2939 | |
acdb74a0 AC |
2940 | if (mips_debug) |
2941 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2942 | partial_len); | |
2943 | ||
566f0f7a | 2944 | /* Write this portion of the argument to the stack. */ |
f09ded24 AC |
2945 | if (argreg > MIPS_LAST_ARG_REGNUM |
2946 | || odd_sized_struct | |
2947 | || fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2948 | { |
c906108c SS |
2949 | /* Should shorter than int integer values be |
2950 | promoted to int before being stored? */ | |
c906108c | 2951 | int longword_offset = 0; |
9ace0497 | 2952 | CORE_ADDR addr; |
566f0f7a | 2953 | stack_used_p = 1; |
d7449b42 | 2954 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
7a292a7a | 2955 | { |
13326b4e | 2956 | if (mips_stack_argsize (gdbarch) == 8 |
480d3dd2 AC |
2957 | && (typecode == TYPE_CODE_INT |
2958 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 2959 | || typecode == TYPE_CODE_FLT) && len <= 4) |
13326b4e | 2960 | longword_offset = mips_stack_argsize (gdbarch) - len; |
480d3dd2 AC |
2961 | else if ((typecode == TYPE_CODE_STRUCT |
2962 | || typecode == TYPE_CODE_UNION) | |
2963 | && (TYPE_LENGTH (arg_type) | |
13326b4e AC |
2964 | < mips_stack_argsize (gdbarch))) |
2965 | longword_offset = mips_stack_argsize (gdbarch) - len; | |
7a292a7a | 2966 | } |
c5aa993b | 2967 | |
9ace0497 AC |
2968 | if (mips_debug) |
2969 | { | |
cb3d25d1 MS |
2970 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", |
2971 | paddr_nz (stack_offset)); | |
2972 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
2973 | paddr_nz (longword_offset)); | |
9ace0497 | 2974 | } |
361d1df0 | 2975 | |
9ace0497 AC |
2976 | addr = sp + stack_offset + longword_offset; |
2977 | ||
2978 | if (mips_debug) | |
2979 | { | |
2980 | int i; | |
6d82d43b | 2981 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 | 2982 | paddr_nz (addr)); |
9ace0497 AC |
2983 | for (i = 0; i < partial_len; i++) |
2984 | { | |
6d82d43b | 2985 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 2986 | val[i] & 0xff); |
9ace0497 AC |
2987 | } |
2988 | } | |
2989 | write_memory (addr, val, partial_len); | |
c906108c SS |
2990 | } |
2991 | ||
f09ded24 AC |
2992 | /* Note!!! This is NOT an else clause. Odd sized |
2993 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 2994 | arguments will not. */ |
566f0f7a | 2995 | /* Write this portion of the argument to a general |
6d82d43b | 2996 | purpose register. */ |
f09ded24 AC |
2997 | if (argreg <= MIPS_LAST_ARG_REGNUM |
2998 | && !fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2999 | { |
6d82d43b AC |
3000 | LONGEST regval = |
3001 | extract_unsigned_integer (val, partial_len); | |
c906108c | 3002 | |
9ace0497 | 3003 | if (mips_debug) |
acdb74a0 | 3004 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 3005 | argreg, |
6d82d43b | 3006 | phex (regval, |
13326b4e | 3007 | mips_abi_regsize (gdbarch))); |
c906108c SS |
3008 | write_register (argreg, regval); |
3009 | argreg++; | |
c906108c | 3010 | } |
c5aa993b | 3011 | |
c906108c SS |
3012 | len -= partial_len; |
3013 | val += partial_len; | |
3014 | ||
566f0f7a | 3015 | /* Compute the the offset into the stack at which we |
6d82d43b | 3016 | will copy the next parameter. |
566f0f7a | 3017 | |
566f0f7a | 3018 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 3019 | only needs to be adjusted when it has been used. */ |
c906108c | 3020 | |
46e0f506 | 3021 | if (stack_used_p) |
480d3dd2 | 3022 | stack_offset += align_up (partial_len, |
13326b4e | 3023 | mips_stack_argsize (gdbarch)); |
c906108c SS |
3024 | } |
3025 | } | |
9ace0497 AC |
3026 | if (mips_debug) |
3027 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
3028 | } |
3029 | ||
310e9b6a AC |
3030 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
3031 | ||
0f71a2f6 JM |
3032 | /* Return adjusted stack pointer. */ |
3033 | return sp; | |
3034 | } | |
3035 | ||
6d82d43b AC |
3036 | /* Given a return value in `regbuf' with a type `valtype', extract and |
3037 | copy its value into `valbuf'. */ | |
3038 | ||
3039 | static void | |
3040 | mips_eabi_extract_return_value (struct type *valtype, | |
3041 | char regbuf[], char *valbuf) | |
3042 | { | |
3043 | struct return_value_word lo; | |
3044 | struct return_value_word hi; | |
3045 | return_value_location (valtype, &hi, &lo); | |
3046 | ||
3047 | memcpy (valbuf + lo.buf_offset, | |
3048 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + lo.reg) + | |
3049 | lo.reg_offset, lo.len); | |
3050 | ||
3051 | if (hi.len > 0) | |
3052 | memcpy (valbuf + hi.buf_offset, | |
3053 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + hi.reg) + | |
3054 | hi.reg_offset, hi.len); | |
3055 | } | |
3056 | ||
3057 | /* Given a return value in `valbuf' with a type `valtype', write it's | |
3058 | value into the appropriate register. */ | |
3059 | ||
3060 | static void | |
3061 | mips_eabi_store_return_value (struct type *valtype, char *valbuf) | |
3062 | { | |
3063 | char raw_buffer[MAX_REGISTER_SIZE]; | |
3064 | struct return_value_word lo; | |
3065 | struct return_value_word hi; | |
3066 | return_value_location (valtype, &hi, &lo); | |
3067 | ||
3068 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
3069 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
3070 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg), | |
3071 | raw_buffer, register_size (current_gdbarch, | |
3072 | lo.reg)); | |
3073 | ||
3074 | if (hi.len > 0) | |
3075 | { | |
3076 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
3077 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
3078 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg), | |
3079 | raw_buffer, | |
3080 | register_size (current_gdbarch, | |
3081 | hi.reg)); | |
3082 | } | |
3083 | } | |
3084 | ||
3085 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 3086 | |
f7ab6ec6 | 3087 | static CORE_ADDR |
25ab4790 | 3088 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
6d82d43b AC |
3089 | struct regcache *regcache, CORE_ADDR bp_addr, |
3090 | int nargs, struct value **args, CORE_ADDR sp, | |
3091 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
3092 | { |
3093 | int argreg; | |
3094 | int float_argreg; | |
3095 | int argnum; | |
3096 | int len = 0; | |
3097 | int stack_offset = 0; | |
480d3dd2 | 3098 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
cb3d25d1 | 3099 | |
25ab4790 AC |
3100 | /* For shared libraries, "t9" needs to point at the function |
3101 | address. */ | |
3102 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3103 | ||
3104 | /* Set the return address register to point to the entry point of | |
3105 | the program, where a breakpoint lies in wait. */ | |
3106 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3107 | ||
cb3d25d1 MS |
3108 | /* First ensure that the stack and structure return address (if any) |
3109 | are properly aligned. The stack has to be at least 64-bit | |
3110 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3111 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3112 | aligned, so we round to this widest known alignment. */ | |
3113 | ||
5b03f266 AC |
3114 | sp = align_down (sp, 16); |
3115 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
3116 | |
3117 | /* Now make space on the stack for the args. */ | |
3118 | for (argnum = 0; argnum < nargs; argnum++) | |
6d82d43b | 3119 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
13326b4e | 3120 | mips_stack_argsize (gdbarch)); |
5b03f266 | 3121 | sp -= align_up (len, 16); |
cb3d25d1 MS |
3122 | |
3123 | if (mips_debug) | |
6d82d43b | 3124 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3125 | "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n", |
3126 | paddr_nz (sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
3127 | |
3128 | /* Initialize the integer and float register pointers. */ | |
3129 | argreg = A0_REGNUM; | |
56cea623 | 3130 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
cb3d25d1 | 3131 | |
46e0f506 | 3132 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
3133 | if (struct_return) |
3134 | { | |
3135 | if (mips_debug) | |
3136 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3137 | "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 MS |
3138 | argreg, paddr_nz (struct_addr)); |
3139 | write_register (argreg++, struct_addr); | |
3140 | } | |
3141 | ||
3142 | /* Now load as many as possible of the first arguments into | |
3143 | registers, and push the rest onto the stack. Loop thru args | |
3144 | from first to last. */ | |
3145 | for (argnum = 0; argnum < nargs; argnum++) | |
3146 | { | |
3147 | char *val; | |
cb3d25d1 MS |
3148 | struct value *arg = args[argnum]; |
3149 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3150 | int len = TYPE_LENGTH (arg_type); | |
3151 | enum type_code typecode = TYPE_CODE (arg_type); | |
3152 | ||
3153 | if (mips_debug) | |
3154 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3155 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
3156 | argnum + 1, len, (int) typecode); |
3157 | ||
3158 | val = (char *) VALUE_CONTENTS (arg); | |
3159 | ||
3160 | if (fp_register_arg_p (typecode, arg_type) | |
3161 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3162 | { | |
3163 | /* This is a floating point value that fits entirely | |
3164 | in a single register. */ | |
3165 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3166 | above to ensure that it is even register aligned. */ | |
3167 | LONGEST regval = extract_unsigned_integer (val, len); | |
3168 | if (mips_debug) | |
3169 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3170 | float_argreg, phex (regval, len)); | |
3171 | write_register (float_argreg++, regval); | |
3172 | ||
3173 | if (mips_debug) | |
3174 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3175 | argreg, phex (regval, len)); | |
3176 | write_register (argreg, regval); | |
3177 | argreg += 1; | |
3178 | } | |
3179 | else | |
3180 | { | |
3181 | /* Copy the argument to general registers or the stack in | |
3182 | register-sized pieces. Large arguments are split between | |
3183 | registers and stack. */ | |
4246e332 | 3184 | /* Note: structs whose size is not a multiple of |
d5ac5a39 AC |
3185 | mips_abi_regsize() are treated specially: Irix cc passes |
3186 | them in registers where gcc sometimes puts them on the | |
3187 | stack. For maximum compatibility, we will put them in | |
3188 | both places. */ | |
13326b4e AC |
3189 | int odd_sized_struct = ((len > mips_abi_regsize (gdbarch)) |
3190 | && (len % mips_abi_regsize (gdbarch) != 0)); | |
cb3d25d1 | 3191 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3192 | register are only written to memory. */ |
cb3d25d1 MS |
3193 | while (len > 0) |
3194 | { | |
3195 | /* Rememer if the argument was written to the stack. */ | |
3196 | int stack_used_p = 0; | |
13326b4e AC |
3197 | int partial_len = (len < mips_abi_regsize (gdbarch) |
3198 | ? len : mips_abi_regsize (gdbarch)); | |
cb3d25d1 MS |
3199 | |
3200 | if (mips_debug) | |
3201 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3202 | partial_len); | |
3203 | ||
3204 | /* Write this portion of the argument to the stack. */ | |
3205 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3206 | || odd_sized_struct | |
3207 | || fp_register_arg_p (typecode, arg_type)) | |
3208 | { | |
3209 | /* Should shorter than int integer values be | |
3210 | promoted to int before being stored? */ | |
3211 | int longword_offset = 0; | |
3212 | CORE_ADDR addr; | |
3213 | stack_used_p = 1; | |
3214 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3215 | { | |
13326b4e | 3216 | if (mips_stack_argsize (gdbarch) == 8 |
480d3dd2 AC |
3217 | && (typecode == TYPE_CODE_INT |
3218 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 3219 | || typecode == TYPE_CODE_FLT) && len <= 4) |
13326b4e | 3220 | longword_offset = mips_stack_argsize (gdbarch) - len; |
cb3d25d1 MS |
3221 | } |
3222 | ||
3223 | if (mips_debug) | |
3224 | { | |
3225 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3226 | paddr_nz (stack_offset)); | |
3227 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3228 | paddr_nz (longword_offset)); | |
3229 | } | |
3230 | ||
3231 | addr = sp + stack_offset + longword_offset; | |
3232 | ||
3233 | if (mips_debug) | |
3234 | { | |
3235 | int i; | |
6d82d43b | 3236 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 MS |
3237 | paddr_nz (addr)); |
3238 | for (i = 0; i < partial_len; i++) | |
3239 | { | |
6d82d43b | 3240 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
3241 | val[i] & 0xff); |
3242 | } | |
3243 | } | |
3244 | write_memory (addr, val, partial_len); | |
3245 | } | |
3246 | ||
3247 | /* Note!!! This is NOT an else clause. Odd sized | |
3248 | structs may go thru BOTH paths. Floating point | |
3249 | arguments will not. */ | |
3250 | /* Write this portion of the argument to a general | |
6d82d43b | 3251 | purpose register. */ |
cb3d25d1 MS |
3252 | if (argreg <= MIPS_LAST_ARG_REGNUM |
3253 | && !fp_register_arg_p (typecode, arg_type)) | |
3254 | { | |
6d82d43b AC |
3255 | LONGEST regval = |
3256 | extract_unsigned_integer (val, partial_len); | |
cb3d25d1 MS |
3257 | |
3258 | /* A non-floating-point argument being passed in a | |
3259 | general register. If a struct or union, and if | |
3260 | the remaining length is smaller than the register | |
3261 | size, we have to adjust the register value on | |
3262 | big endian targets. | |
3263 | ||
3264 | It does not seem to be necessary to do the | |
3265 | same for integral types. | |
3266 | ||
3267 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3268 | outputting LE O32 with sizeof (struct) < | |
1b13c4f6 | 3269 | mips_abi_regsize(), generates a left shift as |
cb3d25d1 MS |
3270 | part of storing the argument in a register a |
3271 | register (the left shift isn't generated when | |
1b13c4f6 | 3272 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
3273 | it is quite possible that this is GCC |
3274 | contradicting the LE/O32 ABI, GDB has not been | |
3275 | adjusted to accommodate this. Either someone | |
3276 | needs to demonstrate that the LE/O32 ABI | |
3277 | specifies such a left shift OR this new ABI gets | |
3278 | identified as such and GDB gets tweaked | |
3279 | accordingly. */ | |
cb3d25d1 MS |
3280 | |
3281 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
13326b4e | 3282 | && partial_len < mips_abi_regsize (gdbarch) |
cb3d25d1 MS |
3283 | && (typecode == TYPE_CODE_STRUCT || |
3284 | typecode == TYPE_CODE_UNION)) | |
13326b4e | 3285 | regval <<= ((mips_abi_regsize (gdbarch) - partial_len) * |
cb3d25d1 MS |
3286 | TARGET_CHAR_BIT); |
3287 | ||
3288 | if (mips_debug) | |
3289 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3290 | argreg, | |
6d82d43b | 3291 | phex (regval, |
13326b4e | 3292 | mips_abi_regsize (gdbarch))); |
cb3d25d1 MS |
3293 | write_register (argreg, regval); |
3294 | argreg++; | |
3295 | } | |
3296 | ||
3297 | len -= partial_len; | |
3298 | val += partial_len; | |
3299 | ||
3300 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3301 | will copy the next parameter. |
cb3d25d1 MS |
3302 | |
3303 | In N32 (N64?), the stack_offset only needs to be | |
3304 | adjusted when it has been used. */ | |
3305 | ||
3306 | if (stack_used_p) | |
480d3dd2 | 3307 | stack_offset += align_up (partial_len, |
13326b4e | 3308 | mips_stack_argsize (gdbarch)); |
cb3d25d1 MS |
3309 | } |
3310 | } | |
3311 | if (mips_debug) | |
3312 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3313 | } | |
3314 | ||
310e9b6a AC |
3315 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
3316 | ||
cb3d25d1 MS |
3317 | /* Return adjusted stack pointer. */ |
3318 | return sp; | |
3319 | } | |
3320 | ||
6d82d43b AC |
3321 | static enum return_value_convention |
3322 | mips_n32n64_return_value (struct gdbarch *gdbarch, | |
3323 | struct type *type, struct regcache *regcache, | |
3324 | void *readbuf, const void *writebuf) | |
ebafbe83 | 3325 | { |
6d82d43b AC |
3326 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
3327 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3328 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3329 | || TYPE_CODE (type) == TYPE_CODE_ARRAY | |
13326b4e | 3330 | || TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
6d82d43b AC |
3331 | return RETURN_VALUE_STRUCT_CONVENTION; |
3332 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3333 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3334 | { | |
3335 | /* A floating-point value belongs in the least significant part | |
3336 | of FP0. */ | |
3337 | if (mips_debug) | |
3338 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3339 | mips_xfer_register (regcache, | |
3340 | NUM_REGS + mips_regnum (current_gdbarch)->fp0, | |
3341 | TYPE_LENGTH (type), | |
3342 | TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
3343 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3344 | } | |
3345 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3346 | && TYPE_NFIELDS (type) <= 2 | |
3347 | && TYPE_NFIELDS (type) >= 1 | |
3348 | && ((TYPE_NFIELDS (type) == 1 | |
3349 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3350 | == TYPE_CODE_FLT)) | |
3351 | || (TYPE_NFIELDS (type) == 2 | |
3352 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3353 | == TYPE_CODE_FLT) | |
3354 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
3355 | == TYPE_CODE_FLT))) | |
3356 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3357 | { | |
3358 | /* A struct that contains one or two floats. Each value is part | |
3359 | in the least significant part of their floating point | |
3360 | register.. */ | |
6d82d43b AC |
3361 | int regnum; |
3362 | int field; | |
3363 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; | |
3364 | field < TYPE_NFIELDS (type); field++, regnum += 2) | |
3365 | { | |
3366 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3367 | / TARGET_CHAR_BIT); | |
3368 | if (mips_debug) | |
3369 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3370 | offset); | |
3371 | mips_xfer_register (regcache, NUM_REGS + regnum, | |
3372 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
3373 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
3374 | } | |
3375 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3376 | } | |
3377 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3378 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3379 | { | |
3380 | /* A structure or union. Extract the left justified value, | |
3381 | regardless of the byte order. I.e. DO NOT USE | |
3382 | mips_xfer_lower. */ | |
3383 | int offset; | |
3384 | int regnum; | |
3385 | for (offset = 0, regnum = V0_REGNUM; | |
3386 | offset < TYPE_LENGTH (type); | |
3387 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3388 | { | |
3389 | int xfer = register_size (current_gdbarch, regnum); | |
3390 | if (offset + xfer > TYPE_LENGTH (type)) | |
3391 | xfer = TYPE_LENGTH (type) - offset; | |
3392 | if (mips_debug) | |
3393 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3394 | offset, xfer, regnum); | |
3395 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
3396 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); | |
3397 | } | |
3398 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3399 | } | |
3400 | else | |
3401 | { | |
3402 | /* A scalar extract each part but least-significant-byte | |
3403 | justified. */ | |
3404 | int offset; | |
3405 | int regnum; | |
3406 | for (offset = 0, regnum = V0_REGNUM; | |
3407 | offset < TYPE_LENGTH (type); | |
3408 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3409 | { | |
3410 | int xfer = register_size (current_gdbarch, regnum); | |
6d82d43b AC |
3411 | if (offset + xfer > TYPE_LENGTH (type)) |
3412 | xfer = TYPE_LENGTH (type) - offset; | |
3413 | if (mips_debug) | |
3414 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3415 | offset, xfer, regnum); | |
3416 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
3417 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
3418 | } | |
3419 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3420 | } | |
3421 | } | |
3422 | ||
3423 | /* O32 ABI stuff. */ | |
3424 | ||
3425 | static CORE_ADDR | |
3426 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, | |
3427 | struct regcache *regcache, CORE_ADDR bp_addr, | |
3428 | int nargs, struct value **args, CORE_ADDR sp, | |
3429 | int struct_return, CORE_ADDR struct_addr) | |
3430 | { | |
3431 | int argreg; | |
3432 | int float_argreg; | |
3433 | int argnum; | |
3434 | int len = 0; | |
3435 | int stack_offset = 0; | |
3436 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3437 | ||
3438 | /* For shared libraries, "t9" needs to point at the function | |
3439 | address. */ | |
3440 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3441 | ||
3442 | /* Set the return address register to point to the entry point of | |
3443 | the program, where a breakpoint lies in wait. */ | |
3444 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3445 | ||
3446 | /* First ensure that the stack and structure return address (if any) | |
3447 | are properly aligned. The stack has to be at least 64-bit | |
3448 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
3449 | aligned. For n32 and n64, stack frames need to be 128-bit |
3450 | aligned, so we round to this widest known alignment. */ | |
3451 | ||
5b03f266 AC |
3452 | sp = align_down (sp, 16); |
3453 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
3454 | |
3455 | /* Now make space on the stack for the args. */ | |
3456 | for (argnum = 0; argnum < nargs; argnum++) | |
6d82d43b | 3457 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
13326b4e | 3458 | mips_stack_argsize (gdbarch)); |
5b03f266 | 3459 | sp -= align_up (len, 16); |
ebafbe83 MS |
3460 | |
3461 | if (mips_debug) | |
6d82d43b | 3462 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3463 | "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n", |
3464 | paddr_nz (sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
3465 | |
3466 | /* Initialize the integer and float register pointers. */ | |
3467 | argreg = A0_REGNUM; | |
56cea623 | 3468 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
ebafbe83 | 3469 | |
bcb0cc15 | 3470 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3471 | if (struct_return) |
3472 | { | |
3473 | if (mips_debug) | |
3474 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3475 | "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n", |
ebafbe83 MS |
3476 | argreg, paddr_nz (struct_addr)); |
3477 | write_register (argreg++, struct_addr); | |
13326b4e | 3478 | stack_offset += mips_stack_argsize (gdbarch); |
ebafbe83 MS |
3479 | } |
3480 | ||
3481 | /* Now load as many as possible of the first arguments into | |
3482 | registers, and push the rest onto the stack. Loop thru args | |
3483 | from first to last. */ | |
3484 | for (argnum = 0; argnum < nargs; argnum++) | |
3485 | { | |
3486 | char *val; | |
ebafbe83 MS |
3487 | struct value *arg = args[argnum]; |
3488 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3489 | int len = TYPE_LENGTH (arg_type); | |
3490 | enum type_code typecode = TYPE_CODE (arg_type); | |
3491 | ||
3492 | if (mips_debug) | |
3493 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3494 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3495 | argnum + 1, len, (int) typecode); |
3496 | ||
3497 | val = (char *) VALUE_CONTENTS (arg); | |
3498 | ||
3499 | /* 32-bit ABIs always start floating point arguments in an | |
3500 | even-numbered floating point register. Round the FP register | |
3501 | up before the check to see if there are any FP registers | |
3502 | left. O32/O64 targets also pass the FP in the integer | |
3503 | registers so also round up normal registers. */ | |
ceae6e75 AC |
3504 | if (mips_abi_regsize (gdbarch) < 8 |
3505 | && fp_register_arg_p (typecode, arg_type)) | |
46cac009 AC |
3506 | { |
3507 | if ((float_argreg & 1)) | |
3508 | float_argreg++; | |
3509 | } | |
3510 | ||
3511 | /* Floating point arguments passed in registers have to be | |
3512 | treated specially. On 32-bit architectures, doubles | |
3513 | are passed in register pairs; the even register gets | |
3514 | the low word, and the odd register gets the high word. | |
3515 | On O32/O64, the first two floating point arguments are | |
3516 | also copied to general registers, because MIPS16 functions | |
3517 | don't use float registers for arguments. This duplication of | |
3518 | arguments in general registers can't hurt non-MIPS16 functions | |
3519 | because those registers are normally skipped. */ | |
3520 | ||
3521 | if (fp_register_arg_p (typecode, arg_type) | |
3522 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3523 | { | |
ceae6e75 | 3524 | if (mips_abi_regsize (gdbarch) < 8 && len == 8) |
46cac009 AC |
3525 | { |
3526 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
3527 | unsigned long regval; | |
3528 | ||
3529 | /* Write the low word of the double to the even register(s). */ | |
3530 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3531 | if (mips_debug) | |
3532 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3533 | float_argreg, phex (regval, 4)); | |
3534 | write_register (float_argreg++, regval); | |
3535 | if (mips_debug) | |
3536 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3537 | argreg, phex (regval, 4)); | |
3538 | write_register (argreg++, regval); | |
3539 | ||
3540 | /* Write the high word of the double to the odd register(s). */ | |
3541 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3542 | if (mips_debug) | |
3543 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3544 | float_argreg, phex (regval, 4)); | |
3545 | write_register (float_argreg++, regval); | |
3546 | ||
3547 | if (mips_debug) | |
3548 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3549 | argreg, phex (regval, 4)); | |
3550 | write_register (argreg++, regval); | |
3551 | } | |
3552 | else | |
3553 | { | |
3554 | /* This is a floating point value that fits entirely | |
3555 | in a single register. */ | |
3556 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 3557 | above to ensure that it is even register aligned. */ |
46cac009 AC |
3558 | LONGEST regval = extract_unsigned_integer (val, len); |
3559 | if (mips_debug) | |
3560 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3561 | float_argreg, phex (regval, len)); | |
3562 | write_register (float_argreg++, regval); | |
3563 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
6d82d43b AC |
3564 | registers for each argument. The below is (my |
3565 | guess) to ensure that the corresponding integer | |
3566 | register has reserved the same space. */ | |
46cac009 AC |
3567 | if (mips_debug) |
3568 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3569 | argreg, phex (regval, len)); | |
3570 | write_register (argreg, regval); | |
ceae6e75 | 3571 | argreg += (mips_abi_regsize (gdbarch) == 8) ? 1 : 2; |
46cac009 AC |
3572 | } |
3573 | /* Reserve space for the FP register. */ | |
13326b4e | 3574 | stack_offset += align_up (len, mips_stack_argsize (gdbarch)); |
46cac009 AC |
3575 | } |
3576 | else | |
3577 | { | |
3578 | /* Copy the argument to general registers or the stack in | |
3579 | register-sized pieces. Large arguments are split between | |
3580 | registers and stack. */ | |
4246e332 | 3581 | /* Note: structs whose size is not a multiple of |
d5ac5a39 AC |
3582 | mips_abi_regsize() are treated specially: Irix cc passes |
3583 | them in registers where gcc sometimes puts them on the | |
3584 | stack. For maximum compatibility, we will put them in | |
3585 | both places. */ | |
13326b4e AC |
3586 | int odd_sized_struct = ((len > mips_abi_regsize (gdbarch)) |
3587 | && (len % mips_abi_regsize (gdbarch) != 0)); | |
46cac009 AC |
3588 | /* Structures should be aligned to eight bytes (even arg registers) |
3589 | on MIPS_ABI_O32, if their first member has double precision. */ | |
13326b4e | 3590 | if (mips_abi_regsize (gdbarch) < 8 |
46cac009 AC |
3591 | && mips_type_needs_double_align (arg_type)) |
3592 | { | |
3593 | if ((argreg & 1)) | |
6d82d43b | 3594 | argreg++; |
46cac009 AC |
3595 | } |
3596 | /* Note: Floating-point values that didn't fit into an FP | |
6d82d43b | 3597 | register are only written to memory. */ |
46cac009 AC |
3598 | while (len > 0) |
3599 | { | |
3600 | /* Remember if the argument was written to the stack. */ | |
3601 | int stack_used_p = 0; | |
13326b4e AC |
3602 | int partial_len = (len < mips_abi_regsize (gdbarch) |
3603 | ? len : mips_abi_regsize (gdbarch)); | |
46cac009 AC |
3604 | |
3605 | if (mips_debug) | |
3606 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3607 | partial_len); | |
3608 | ||
3609 | /* Write this portion of the argument to the stack. */ | |
3610 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3611 | || odd_sized_struct | |
3612 | || fp_register_arg_p (typecode, arg_type)) | |
3613 | { | |
3614 | /* Should shorter than int integer values be | |
3615 | promoted to int before being stored? */ | |
3616 | int longword_offset = 0; | |
3617 | CORE_ADDR addr; | |
3618 | stack_used_p = 1; | |
3619 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3620 | { | |
13326b4e | 3621 | if (mips_stack_argsize (gdbarch) == 8 |
480d3dd2 AC |
3622 | && (typecode == TYPE_CODE_INT |
3623 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 3624 | || typecode == TYPE_CODE_FLT) && len <= 4) |
13326b4e | 3625 | longword_offset = mips_stack_argsize (gdbarch) - len; |
46cac009 AC |
3626 | } |
3627 | ||
3628 | if (mips_debug) | |
3629 | { | |
3630 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3631 | paddr_nz (stack_offset)); | |
3632 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3633 | paddr_nz (longword_offset)); | |
3634 | } | |
3635 | ||
3636 | addr = sp + stack_offset + longword_offset; | |
3637 | ||
3638 | if (mips_debug) | |
3639 | { | |
3640 | int i; | |
6d82d43b | 3641 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
46cac009 AC |
3642 | paddr_nz (addr)); |
3643 | for (i = 0; i < partial_len; i++) | |
3644 | { | |
6d82d43b | 3645 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
3646 | val[i] & 0xff); |
3647 | } | |
3648 | } | |
3649 | write_memory (addr, val, partial_len); | |
3650 | } | |
3651 | ||
3652 | /* Note!!! This is NOT an else clause. Odd sized | |
3653 | structs may go thru BOTH paths. Floating point | |
3654 | arguments will not. */ | |
3655 | /* Write this portion of the argument to a general | |
6d82d43b | 3656 | purpose register. */ |
46cac009 AC |
3657 | if (argreg <= MIPS_LAST_ARG_REGNUM |
3658 | && !fp_register_arg_p (typecode, arg_type)) | |
3659 | { | |
3660 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 3661 | /* Value may need to be sign extended, because |
1b13c4f6 | 3662 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
3663 | |
3664 | /* A non-floating-point argument being passed in a | |
3665 | general register. If a struct or union, and if | |
3666 | the remaining length is smaller than the register | |
3667 | size, we have to adjust the register value on | |
3668 | big endian targets. | |
3669 | ||
3670 | It does not seem to be necessary to do the | |
3671 | same for integral types. | |
3672 | ||
3673 | Also don't do this adjustment on O64 binaries. | |
3674 | ||
3675 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3676 | outputting LE O32 with sizeof (struct) < | |
1b13c4f6 | 3677 | mips_abi_regsize(), generates a left shift as |
46cac009 AC |
3678 | part of storing the argument in a register a |
3679 | register (the left shift isn't generated when | |
1b13c4f6 | 3680 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
3681 | it is quite possible that this is GCC |
3682 | contradicting the LE/O32 ABI, GDB has not been | |
3683 | adjusted to accommodate this. Either someone | |
3684 | needs to demonstrate that the LE/O32 ABI | |
3685 | specifies such a left shift OR this new ABI gets | |
3686 | identified as such and GDB gets tweaked | |
3687 | accordingly. */ | |
3688 | ||
13326b4e | 3689 | if (mips_abi_regsize (gdbarch) < 8 |
46cac009 | 3690 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
13326b4e | 3691 | && partial_len < mips_abi_regsize (gdbarch) |
46cac009 AC |
3692 | && (typecode == TYPE_CODE_STRUCT || |
3693 | typecode == TYPE_CODE_UNION)) | |
13326b4e | 3694 | regval <<= ((mips_abi_regsize (gdbarch) - partial_len) * |
46cac009 AC |
3695 | TARGET_CHAR_BIT); |
3696 | ||
3697 | if (mips_debug) | |
3698 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3699 | argreg, | |
6d82d43b | 3700 | phex (regval, |
13326b4e | 3701 | mips_abi_regsize (gdbarch))); |
46cac009 AC |
3702 | write_register (argreg, regval); |
3703 | argreg++; | |
3704 | ||
3705 | /* Prevent subsequent floating point arguments from | |
3706 | being passed in floating point registers. */ | |
3707 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3708 | } | |
3709 | ||
3710 | len -= partial_len; | |
3711 | val += partial_len; | |
3712 | ||
3713 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3714 | will copy the next parameter. |
46cac009 | 3715 | |
6d82d43b AC |
3716 | In older ABIs, the caller reserved space for |
3717 | registers that contained arguments. This was loosely | |
3718 | refered to as their "home". Consequently, space is | |
3719 | always allocated. */ | |
46cac009 | 3720 | |
480d3dd2 | 3721 | stack_offset += align_up (partial_len, |
13326b4e | 3722 | mips_stack_argsize (gdbarch)); |
46cac009 AC |
3723 | } |
3724 | } | |
3725 | if (mips_debug) | |
3726 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3727 | } | |
3728 | ||
310e9b6a AC |
3729 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
3730 | ||
46cac009 AC |
3731 | /* Return adjusted stack pointer. */ |
3732 | return sp; | |
3733 | } | |
3734 | ||
6d82d43b AC |
3735 | static enum return_value_convention |
3736 | mips_o32_return_value (struct gdbarch *gdbarch, struct type *type, | |
3737 | struct regcache *regcache, | |
3738 | void *readbuf, const void *writebuf) | |
3739 | { | |
3740 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3741 | ||
3742 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3743 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3744 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
3745 | return RETURN_VALUE_STRUCT_CONVENTION; | |
3746 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3747 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3748 | { | |
3749 | /* A single-precision floating-point value. It fits in the | |
3750 | least significant part of FP0. */ | |
3751 | if (mips_debug) | |
3752 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3753 | mips_xfer_register (regcache, | |
3754 | NUM_REGS + mips_regnum (current_gdbarch)->fp0, | |
3755 | TYPE_LENGTH (type), | |
3756 | TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
3757 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3758 | } | |
3759 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3760 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3761 | { | |
3762 | /* A double-precision floating-point value. The most | |
3763 | significant part goes in FP1, and the least significant in | |
3764 | FP0. */ | |
3765 | if (mips_debug) | |
3766 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
3767 | switch (TARGET_BYTE_ORDER) | |
3768 | { | |
3769 | case BFD_ENDIAN_LITTLE: | |
3770 | mips_xfer_register (regcache, | |
3771 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
3772 | 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
3773 | mips_xfer_register (regcache, | |
3774 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
3775 | 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4); | |
3776 | break; | |
3777 | case BFD_ENDIAN_BIG: | |
3778 | mips_xfer_register (regcache, | |
3779 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
3780 | 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
3781 | mips_xfer_register (regcache, | |
3782 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
3783 | 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4); | |
3784 | break; | |
3785 | default: | |
3786 | internal_error (__FILE__, __LINE__, "bad switch"); | |
3787 | } | |
3788 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3789 | } | |
3790 | #if 0 | |
3791 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3792 | && TYPE_NFIELDS (type) <= 2 | |
3793 | && TYPE_NFIELDS (type) >= 1 | |
3794 | && ((TYPE_NFIELDS (type) == 1 | |
3795 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3796 | == TYPE_CODE_FLT)) | |
3797 | || (TYPE_NFIELDS (type) == 2 | |
3798 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3799 | == TYPE_CODE_FLT) | |
3800 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
3801 | == TYPE_CODE_FLT))) | |
3802 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3803 | { | |
3804 | /* A struct that contains one or two floats. Each value is part | |
3805 | in the least significant part of their floating point | |
3806 | register.. */ | |
3807 | bfd_byte reg[MAX_REGISTER_SIZE]; | |
3808 | int regnum; | |
3809 | int field; | |
3810 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; | |
3811 | field < TYPE_NFIELDS (type); field++, regnum += 2) | |
3812 | { | |
3813 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3814 | / TARGET_CHAR_BIT); | |
3815 | if (mips_debug) | |
3816 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3817 | offset); | |
3818 | mips_xfer_register (regcache, NUM_REGS + regnum, | |
3819 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
3820 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
3821 | } | |
3822 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3823 | } | |
3824 | #endif | |
3825 | #if 0 | |
3826 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3827 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3828 | { | |
3829 | /* A structure or union. Extract the left justified value, | |
3830 | regardless of the byte order. I.e. DO NOT USE | |
3831 | mips_xfer_lower. */ | |
3832 | int offset; | |
3833 | int regnum; | |
3834 | for (offset = 0, regnum = V0_REGNUM; | |
3835 | offset < TYPE_LENGTH (type); | |
3836 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3837 | { | |
3838 | int xfer = register_size (current_gdbarch, regnum); | |
3839 | if (offset + xfer > TYPE_LENGTH (type)) | |
3840 | xfer = TYPE_LENGTH (type) - offset; | |
3841 | if (mips_debug) | |
3842 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3843 | offset, xfer, regnum); | |
3844 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
3845 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); | |
3846 | } | |
3847 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3848 | } | |
3849 | #endif | |
3850 | else | |
3851 | { | |
3852 | /* A scalar extract each part but least-significant-byte | |
3853 | justified. o32 thinks registers are 4 byte, regardless of | |
3854 | the ISA. mips_stack_argsize controls this. */ | |
3855 | int offset; | |
3856 | int regnum; | |
3857 | for (offset = 0, regnum = V0_REGNUM; | |
3858 | offset < TYPE_LENGTH (type); | |
13326b4e | 3859 | offset += mips_stack_argsize (gdbarch), regnum++) |
6d82d43b | 3860 | { |
13326b4e | 3861 | int xfer = mips_stack_argsize (gdbarch); |
6d82d43b AC |
3862 | if (offset + xfer > TYPE_LENGTH (type)) |
3863 | xfer = TYPE_LENGTH (type) - offset; | |
3864 | if (mips_debug) | |
3865 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3866 | offset, xfer, regnum); | |
3867 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
3868 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
3869 | } | |
3870 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3871 | } | |
3872 | } | |
3873 | ||
3874 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
3875 | ABI. */ | |
46cac009 AC |
3876 | |
3877 | static CORE_ADDR | |
25ab4790 | 3878 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
6d82d43b AC |
3879 | struct regcache *regcache, CORE_ADDR bp_addr, |
3880 | int nargs, | |
3881 | struct value **args, CORE_ADDR sp, | |
3882 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
3883 | { |
3884 | int argreg; | |
3885 | int float_argreg; | |
3886 | int argnum; | |
3887 | int len = 0; | |
3888 | int stack_offset = 0; | |
480d3dd2 | 3889 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
46cac009 | 3890 | |
25ab4790 AC |
3891 | /* For shared libraries, "t9" needs to point at the function |
3892 | address. */ | |
3893 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3894 | ||
3895 | /* Set the return address register to point to the entry point of | |
3896 | the program, where a breakpoint lies in wait. */ | |
3897 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3898 | ||
46cac009 AC |
3899 | /* First ensure that the stack and structure return address (if any) |
3900 | are properly aligned. The stack has to be at least 64-bit | |
3901 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3902 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3903 | aligned, so we round to this widest known alignment. */ | |
3904 | ||
5b03f266 AC |
3905 | sp = align_down (sp, 16); |
3906 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
3907 | |
3908 | /* Now make space on the stack for the args. */ | |
3909 | for (argnum = 0; argnum < nargs; argnum++) | |
6d82d43b | 3910 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
13326b4e | 3911 | mips_stack_argsize (gdbarch)); |
5b03f266 | 3912 | sp -= align_up (len, 16); |
46cac009 AC |
3913 | |
3914 | if (mips_debug) | |
6d82d43b | 3915 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3916 | "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n", |
3917 | paddr_nz (sp), (long) align_up (len, 16)); | |
46cac009 AC |
3918 | |
3919 | /* Initialize the integer and float register pointers. */ | |
3920 | argreg = A0_REGNUM; | |
56cea623 | 3921 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
46cac009 AC |
3922 | |
3923 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
3924 | if (struct_return) | |
3925 | { | |
3926 | if (mips_debug) | |
3927 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3928 | "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n", |
46cac009 AC |
3929 | argreg, paddr_nz (struct_addr)); |
3930 | write_register (argreg++, struct_addr); | |
13326b4e | 3931 | stack_offset += mips_stack_argsize (gdbarch); |
46cac009 AC |
3932 | } |
3933 | ||
3934 | /* Now load as many as possible of the first arguments into | |
3935 | registers, and push the rest onto the stack. Loop thru args | |
3936 | from first to last. */ | |
3937 | for (argnum = 0; argnum < nargs; argnum++) | |
3938 | { | |
3939 | char *val; | |
46cac009 AC |
3940 | struct value *arg = args[argnum]; |
3941 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3942 | int len = TYPE_LENGTH (arg_type); | |
3943 | enum type_code typecode = TYPE_CODE (arg_type); | |
3944 | ||
3945 | if (mips_debug) | |
3946 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3947 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
3948 | argnum + 1, len, (int) typecode); |
3949 | ||
3950 | val = (char *) VALUE_CONTENTS (arg); | |
3951 | ||
3952 | /* 32-bit ABIs always start floating point arguments in an | |
3953 | even-numbered floating point register. Round the FP register | |
3954 | up before the check to see if there are any FP registers | |
3955 | left. O32/O64 targets also pass the FP in the integer | |
3956 | registers so also round up normal registers. */ | |
ceae6e75 AC |
3957 | if (mips_abi_regsize (gdbarch) < 8 |
3958 | && fp_register_arg_p (typecode, arg_type)) | |
ebafbe83 MS |
3959 | { |
3960 | if ((float_argreg & 1)) | |
3961 | float_argreg++; | |
3962 | } | |
3963 | ||
3964 | /* Floating point arguments passed in registers have to be | |
3965 | treated specially. On 32-bit architectures, doubles | |
3966 | are passed in register pairs; the even register gets | |
3967 | the low word, and the odd register gets the high word. | |
3968 | On O32/O64, the first two floating point arguments are | |
3969 | also copied to general registers, because MIPS16 functions | |
3970 | don't use float registers for arguments. This duplication of | |
3971 | arguments in general registers can't hurt non-MIPS16 functions | |
3972 | because those registers are normally skipped. */ | |
3973 | ||
3974 | if (fp_register_arg_p (typecode, arg_type) | |
3975 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3976 | { | |
ceae6e75 | 3977 | if (mips_abi_regsize (gdbarch) < 8 && len == 8) |
ebafbe83 MS |
3978 | { |
3979 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
3980 | unsigned long regval; | |
3981 | ||
3982 | /* Write the low word of the double to the even register(s). */ | |
3983 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3984 | if (mips_debug) | |
3985 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3986 | float_argreg, phex (regval, 4)); | |
3987 | write_register (float_argreg++, regval); | |
3988 | if (mips_debug) | |
3989 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3990 | argreg, phex (regval, 4)); | |
3991 | write_register (argreg++, regval); | |
3992 | ||
3993 | /* Write the high word of the double to the odd register(s). */ | |
3994 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3995 | if (mips_debug) | |
3996 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3997 | float_argreg, phex (regval, 4)); | |
3998 | write_register (float_argreg++, regval); | |
3999 | ||
4000 | if (mips_debug) | |
4001 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4002 | argreg, phex (regval, 4)); | |
4003 | write_register (argreg++, regval); | |
4004 | } | |
4005 | else | |
4006 | { | |
4007 | /* This is a floating point value that fits entirely | |
4008 | in a single register. */ | |
4009 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 4010 | above to ensure that it is even register aligned. */ |
ebafbe83 MS |
4011 | LONGEST regval = extract_unsigned_integer (val, len); |
4012 | if (mips_debug) | |
4013 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4014 | float_argreg, phex (regval, len)); | |
4015 | write_register (float_argreg++, regval); | |
4016 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
6d82d43b AC |
4017 | registers for each argument. The below is (my |
4018 | guess) to ensure that the corresponding integer | |
4019 | register has reserved the same space. */ | |
ebafbe83 MS |
4020 | if (mips_debug) |
4021 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4022 | argreg, phex (regval, len)); | |
4023 | write_register (argreg, regval); | |
ceae6e75 | 4024 | argreg += (mips_abi_regsize (gdbarch) == 8) ? 1 : 2; |
ebafbe83 MS |
4025 | } |
4026 | /* Reserve space for the FP register. */ | |
13326b4e | 4027 | stack_offset += align_up (len, mips_stack_argsize (gdbarch)); |
ebafbe83 MS |
4028 | } |
4029 | else | |
4030 | { | |
4031 | /* Copy the argument to general registers or the stack in | |
4032 | register-sized pieces. Large arguments are split between | |
4033 | registers and stack. */ | |
4246e332 | 4034 | /* Note: structs whose size is not a multiple of |
d5ac5a39 AC |
4035 | mips_abi_regsize() are treated specially: Irix cc passes |
4036 | them in registers where gcc sometimes puts them on the | |
4037 | stack. For maximum compatibility, we will put them in | |
4038 | both places. */ | |
13326b4e AC |
4039 | int odd_sized_struct = ((len > mips_abi_regsize (gdbarch)) |
4040 | && (len % mips_abi_regsize (gdbarch) != 0)); | |
ebafbe83 MS |
4041 | /* Structures should be aligned to eight bytes (even arg registers) |
4042 | on MIPS_ABI_O32, if their first member has double precision. */ | |
13326b4e | 4043 | if (mips_abi_regsize (gdbarch) < 8 |
ebafbe83 MS |
4044 | && mips_type_needs_double_align (arg_type)) |
4045 | { | |
4046 | if ((argreg & 1)) | |
6d82d43b | 4047 | argreg++; |
ebafbe83 MS |
4048 | } |
4049 | /* Note: Floating-point values that didn't fit into an FP | |
6d82d43b | 4050 | register are only written to memory. */ |
ebafbe83 MS |
4051 | while (len > 0) |
4052 | { | |
4053 | /* Remember if the argument was written to the stack. */ | |
4054 | int stack_used_p = 0; | |
13326b4e AC |
4055 | int partial_len = (len < mips_abi_regsize (gdbarch) |
4056 | ? len : mips_abi_regsize (gdbarch)); | |
ebafbe83 MS |
4057 | |
4058 | if (mips_debug) | |
4059 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4060 | partial_len); | |
4061 | ||
4062 | /* Write this portion of the argument to the stack. */ | |
4063 | if (argreg > MIPS_LAST_ARG_REGNUM | |
4064 | || odd_sized_struct | |
4065 | || fp_register_arg_p (typecode, arg_type)) | |
4066 | { | |
4067 | /* Should shorter than int integer values be | |
4068 | promoted to int before being stored? */ | |
4069 | int longword_offset = 0; | |
4070 | CORE_ADDR addr; | |
4071 | stack_used_p = 1; | |
4072 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
4073 | { | |
13326b4e | 4074 | if (mips_stack_argsize (gdbarch) == 8 |
480d3dd2 AC |
4075 | && (typecode == TYPE_CODE_INT |
4076 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 4077 | || typecode == TYPE_CODE_FLT) && len <= 4) |
13326b4e | 4078 | longword_offset = mips_stack_argsize (gdbarch) - len; |
ebafbe83 MS |
4079 | } |
4080 | ||
4081 | if (mips_debug) | |
4082 | { | |
4083 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
4084 | paddr_nz (stack_offset)); | |
4085 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
4086 | paddr_nz (longword_offset)); | |
4087 | } | |
4088 | ||
4089 | addr = sp + stack_offset + longword_offset; | |
4090 | ||
4091 | if (mips_debug) | |
4092 | { | |
4093 | int i; | |
6d82d43b | 4094 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
ebafbe83 MS |
4095 | paddr_nz (addr)); |
4096 | for (i = 0; i < partial_len; i++) | |
4097 | { | |
6d82d43b | 4098 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
4099 | val[i] & 0xff); |
4100 | } | |
4101 | } | |
4102 | write_memory (addr, val, partial_len); | |
4103 | } | |
4104 | ||
4105 | /* Note!!! This is NOT an else clause. Odd sized | |
4106 | structs may go thru BOTH paths. Floating point | |
4107 | arguments will not. */ | |
4108 | /* Write this portion of the argument to a general | |
6d82d43b | 4109 | purpose register. */ |
ebafbe83 MS |
4110 | if (argreg <= MIPS_LAST_ARG_REGNUM |
4111 | && !fp_register_arg_p (typecode, arg_type)) | |
4112 | { | |
4113 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 4114 | /* Value may need to be sign extended, because |
1b13c4f6 | 4115 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
4116 | |
4117 | /* A non-floating-point argument being passed in a | |
4118 | general register. If a struct or union, and if | |
4119 | the remaining length is smaller than the register | |
4120 | size, we have to adjust the register value on | |
4121 | big endian targets. | |
4122 | ||
4123 | It does not seem to be necessary to do the | |
4124 | same for integral types. | |
4125 | ||
4126 | Also don't do this adjustment on O64 binaries. | |
4127 | ||
4128 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
4129 | outputting LE O32 with sizeof (struct) < | |
1b13c4f6 | 4130 | mips_abi_regsize(), generates a left shift as |
ebafbe83 MS |
4131 | part of storing the argument in a register a |
4132 | register (the left shift isn't generated when | |
1b13c4f6 | 4133 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
4134 | it is quite possible that this is GCC |
4135 | contradicting the LE/O32 ABI, GDB has not been | |
4136 | adjusted to accommodate this. Either someone | |
4137 | needs to demonstrate that the LE/O32 ABI | |
4138 | specifies such a left shift OR this new ABI gets | |
4139 | identified as such and GDB gets tweaked | |
4140 | accordingly. */ | |
4141 | ||
13326b4e | 4142 | if (mips_abi_regsize (gdbarch) < 8 |
ebafbe83 | 4143 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
13326b4e | 4144 | && partial_len < mips_abi_regsize (gdbarch) |
ebafbe83 MS |
4145 | && (typecode == TYPE_CODE_STRUCT || |
4146 | typecode == TYPE_CODE_UNION)) | |
13326b4e | 4147 | regval <<= ((mips_abi_regsize (gdbarch) - partial_len) * |
ebafbe83 MS |
4148 | TARGET_CHAR_BIT); |
4149 | ||
4150 | if (mips_debug) | |
4151 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
4152 | argreg, | |
6d82d43b | 4153 | phex (regval, |
13326b4e | 4154 | mips_abi_regsize (gdbarch))); |
ebafbe83 MS |
4155 | write_register (argreg, regval); |
4156 | argreg++; | |
4157 | ||
4158 | /* Prevent subsequent floating point arguments from | |
4159 | being passed in floating point registers. */ | |
4160 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
4161 | } | |
4162 | ||
4163 | len -= partial_len; | |
4164 | val += partial_len; | |
4165 | ||
4166 | /* Compute the the offset into the stack at which we | |
6d82d43b | 4167 | will copy the next parameter. |
ebafbe83 | 4168 | |
6d82d43b AC |
4169 | In older ABIs, the caller reserved space for |
4170 | registers that contained arguments. This was loosely | |
4171 | refered to as their "home". Consequently, space is | |
4172 | always allocated. */ | |
ebafbe83 | 4173 | |
480d3dd2 | 4174 | stack_offset += align_up (partial_len, |
13326b4e | 4175 | mips_stack_argsize (gdbarch)); |
ebafbe83 MS |
4176 | } |
4177 | } | |
4178 | if (mips_debug) | |
4179 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
4180 | } | |
4181 | ||
310e9b6a AC |
4182 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
4183 | ||
ebafbe83 MS |
4184 | /* Return adjusted stack pointer. */ |
4185 | return sp; | |
4186 | } | |
4187 | ||
f7ab6ec6 | 4188 | static void |
6d82d43b AC |
4189 | mips_o64_extract_return_value (struct type *valtype, |
4190 | char regbuf[], char *valbuf) | |
c906108c | 4191 | { |
6d82d43b AC |
4192 | struct return_value_word lo; |
4193 | struct return_value_word hi; | |
4194 | return_value_location (valtype, &hi, &lo); | |
c906108c | 4195 | |
6d82d43b AC |
4196 | memcpy (valbuf + lo.buf_offset, |
4197 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + lo.reg) + | |
4198 | lo.reg_offset, lo.len); | |
4199 | ||
4200 | if (hi.len > 0) | |
4201 | memcpy (valbuf + hi.buf_offset, | |
4202 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + hi.reg) + | |
4203 | hi.reg_offset, hi.len); | |
4204 | } | |
4205 | ||
4206 | static void | |
4207 | mips_o64_store_return_value (struct type *valtype, char *valbuf) | |
4208 | { | |
4209 | char raw_buffer[MAX_REGISTER_SIZE]; | |
4210 | struct return_value_word lo; | |
4211 | struct return_value_word hi; | |
4212 | return_value_location (valtype, &hi, &lo); | |
4213 | ||
4214 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4215 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
4216 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg), | |
4217 | raw_buffer, register_size (current_gdbarch, | |
4218 | lo.reg)); | |
4219 | ||
4220 | if (hi.len > 0) | |
4221 | { | |
4222 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4223 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
4224 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg), | |
4225 | raw_buffer, | |
4226 | register_size (current_gdbarch, | |
4227 | hi.reg)); | |
4228 | } | |
4229 | } | |
4230 | ||
dd824b04 DJ |
4231 | /* Floating point register management. |
4232 | ||
4233 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
4234 | 64bit operations, these early MIPS cpus treat fp register pairs | |
4235 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
4236 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
4237 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
4238 | double precision floats into two 32-bit chunks and store them in | |
4239 | consecutive fp regs. To display 64-bit floats stored in this | |
4240 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
4241 | Throw in user-configurable endianness and you have a real mess. | |
4242 | ||
4243 | The way this works is: | |
4244 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
4245 | double-precision value will be split across two logical registers. | |
4246 | The lower-numbered logical register will hold the low-order bits, | |
4247 | regardless of the processor's endianness. | |
4248 | - If we are on a 64-bit processor, and we are looking for a | |
4249 | single-precision value, it will be in the low ordered bits | |
4250 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
4251 | save slot in memory. | |
4252 | - If we are in 64-bit mode, everything is straightforward. | |
4253 | ||
4254 | Note that this code only deals with "live" registers at the top of the | |
4255 | stack. We will attempt to deal with saved registers later, when | |
4256 | the raw/cooked register interface is in place. (We need a general | |
4257 | interface that can deal with dynamic saved register sizes -- fp | |
4258 | regs could be 32 bits wide in one frame and 64 on the frame above | |
4259 | and below). */ | |
4260 | ||
67b2c998 DJ |
4261 | static struct type * |
4262 | mips_float_register_type (void) | |
4263 | { | |
361d1df0 | 4264 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
4265 | return builtin_type_ieee_single_big; |
4266 | else | |
4267 | return builtin_type_ieee_single_little; | |
4268 | } | |
4269 | ||
4270 | static struct type * | |
4271 | mips_double_register_type (void) | |
4272 | { | |
361d1df0 | 4273 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
4274 | return builtin_type_ieee_double_big; |
4275 | else | |
4276 | return builtin_type_ieee_double_little; | |
4277 | } | |
4278 | ||
dd824b04 DJ |
4279 | /* Copy a 32-bit single-precision value from the current frame |
4280 | into rare_buffer. */ | |
4281 | ||
4282 | static void | |
e11c53d2 AC |
4283 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
4284 | char *rare_buffer) | |
dd824b04 | 4285 | { |
719ec221 | 4286 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 DJ |
4287 | char *raw_buffer = alloca (raw_size); |
4288 | ||
e11c53d2 | 4289 | if (!frame_register_read (frame, regno, raw_buffer)) |
dd824b04 DJ |
4290 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
4291 | if (raw_size == 8) | |
4292 | { | |
4293 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 4294 | 32 bits. */ |
dd824b04 DJ |
4295 | int offset; |
4296 | ||
4297 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
4298 | offset = 4; | |
4299 | else | |
4300 | offset = 0; | |
4301 | ||
4302 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
4303 | } | |
4304 | else | |
4305 | { | |
4306 | memcpy (rare_buffer, raw_buffer, 4); | |
4307 | } | |
4308 | } | |
4309 | ||
4310 | /* Copy a 64-bit double-precision value from the current frame into | |
4311 | rare_buffer. This may include getting half of it from the next | |
4312 | register. */ | |
4313 | ||
4314 | static void | |
e11c53d2 AC |
4315 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
4316 | char *rare_buffer) | |
dd824b04 | 4317 | { |
719ec221 | 4318 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 DJ |
4319 | |
4320 | if (raw_size == 8 && !mips2_fp_compat ()) | |
4321 | { | |
4322 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 4323 | all 64 bits. */ |
e11c53d2 | 4324 | if (!frame_register_read (frame, regno, rare_buffer)) |
dd824b04 DJ |
4325 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
4326 | } | |
4327 | else | |
4328 | { | |
56cea623 | 4329 | if ((regno - mips_regnum (current_gdbarch)->fp0) & 1) |
dd824b04 DJ |
4330 | internal_error (__FILE__, __LINE__, |
4331 | "mips_read_fp_register_double: bad access to " | |
4332 | "odd-numbered FP register"); | |
4333 | ||
4334 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 4335 | each register. */ |
dd824b04 DJ |
4336 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
4337 | { | |
e11c53d2 AC |
4338 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
4339 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 4340 | } |
361d1df0 | 4341 | else |
dd824b04 | 4342 | { |
e11c53d2 AC |
4343 | mips_read_fp_register_single (frame, regno, rare_buffer); |
4344 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
4345 | } |
4346 | } | |
4347 | } | |
4348 | ||
c906108c | 4349 | static void |
e11c53d2 AC |
4350 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
4351 | int regnum) | |
c5aa993b | 4352 | { /* do values for FP (float) regs */ |
dd824b04 | 4353 | char *raw_buffer; |
3903d437 AC |
4354 | double doub, flt1; /* doubles extracted from raw hex data */ |
4355 | int inv1, inv2; | |
c5aa993b | 4356 | |
6d82d43b AC |
4357 | raw_buffer = |
4358 | (char *) alloca (2 * | |
4359 | register_size (current_gdbarch, | |
4360 | mips_regnum (current_gdbarch)->fp0)); | |
c906108c | 4361 | |
e11c53d2 AC |
4362 | fprintf_filtered (file, "%s:", REGISTER_NAME (regnum)); |
4363 | fprintf_filtered (file, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum)), | |
4364 | ""); | |
f0ef6b29 | 4365 | |
719ec221 | 4366 | if (register_size (current_gdbarch, regnum) == 4 || mips2_fp_compat ()) |
c906108c | 4367 | { |
f0ef6b29 KB |
4368 | /* 4-byte registers: Print hex and floating. Also print even |
4369 | numbered registers as doubles. */ | |
e11c53d2 | 4370 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
67b2c998 | 4371 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c5aa993b | 4372 | |
6d82d43b AC |
4373 | print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w', |
4374 | file); | |
dd824b04 | 4375 | |
e11c53d2 | 4376 | fprintf_filtered (file, " flt: "); |
1adad886 | 4377 | if (inv1) |
e11c53d2 | 4378 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4379 | else |
e11c53d2 | 4380 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4381 | |
f0ef6b29 KB |
4382 | if (regnum % 2 == 0) |
4383 | { | |
e11c53d2 | 4384 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 | 4385 | doub = unpack_double (mips_double_register_type (), raw_buffer, |
6d82d43b | 4386 | &inv2); |
1adad886 | 4387 | |
e11c53d2 | 4388 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4389 | if (inv2) |
e11c53d2 | 4390 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 4391 | else |
e11c53d2 | 4392 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 4393 | } |
c906108c SS |
4394 | } |
4395 | else | |
dd824b04 | 4396 | { |
f0ef6b29 | 4397 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 4398 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
2f38ef89 | 4399 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c906108c | 4400 | |
e11c53d2 | 4401 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
4402 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2); |
4403 | ||
361d1df0 | 4404 | |
6d82d43b AC |
4405 | print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g', |
4406 | file); | |
f0ef6b29 | 4407 | |
e11c53d2 | 4408 | fprintf_filtered (file, " flt: "); |
1adad886 | 4409 | if (inv1) |
e11c53d2 | 4410 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 4411 | else |
e11c53d2 | 4412 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4413 | |
e11c53d2 | 4414 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4415 | if (inv2) |
e11c53d2 | 4416 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 4417 | else |
e11c53d2 | 4418 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
4419 | } |
4420 | } | |
4421 | ||
4422 | static void | |
e11c53d2 AC |
4423 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
4424 | int regnum, int all) | |
f0ef6b29 | 4425 | { |
a4b8ebc8 | 4426 | struct gdbarch *gdbarch = get_frame_arch (frame); |
d9d9c31f | 4427 | char raw_buffer[MAX_REGISTER_SIZE]; |
f0ef6b29 | 4428 | int offset; |
1adad886 | 4429 | |
a4b8ebc8 | 4430 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 4431 | { |
e11c53d2 | 4432 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4433 | return; |
4434 | } | |
4435 | ||
4436 | /* Get the data in raw format. */ | |
e11c53d2 | 4437 | if (!frame_register_read (frame, regnum, raw_buffer)) |
f0ef6b29 | 4438 | { |
e11c53d2 | 4439 | fprintf_filtered (file, "%s: [Invalid]", REGISTER_NAME (regnum)); |
f0ef6b29 | 4440 | return; |
c906108c | 4441 | } |
f0ef6b29 | 4442 | |
e11c53d2 | 4443 | fputs_filtered (REGISTER_NAME (regnum), file); |
f0ef6b29 KB |
4444 | |
4445 | /* The problem with printing numeric register names (r26, etc.) is that | |
4446 | the user can't use them on input. Probably the best solution is to | |
4447 | fix it so that either the numeric or the funky (a2, etc.) names | |
4448 | are accepted on input. */ | |
4449 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 4450 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 4451 | else |
e11c53d2 | 4452 | fprintf_filtered (file, ": "); |
f0ef6b29 KB |
4453 | |
4454 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
6d82d43b AC |
4455 | offset = |
4456 | register_size (current_gdbarch, | |
4457 | regnum) - register_size (current_gdbarch, regnum); | |
f0ef6b29 KB |
4458 | else |
4459 | offset = 0; | |
4460 | ||
6d82d43b AC |
4461 | print_scalar_formatted (raw_buffer + offset, |
4462 | gdbarch_register_type (gdbarch, regnum), 'x', 0, | |
4463 | file); | |
c906108c SS |
4464 | } |
4465 | ||
f0ef6b29 KB |
4466 | /* Replacement for generic do_registers_info. |
4467 | Print regs in pretty columns. */ | |
4468 | ||
4469 | static int | |
e11c53d2 AC |
4470 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
4471 | int regnum) | |
f0ef6b29 | 4472 | { |
e11c53d2 AC |
4473 | fprintf_filtered (file, " "); |
4474 | mips_print_fp_register (file, frame, regnum); | |
4475 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
4476 | return regnum + 1; |
4477 | } | |
4478 | ||
4479 | ||
c906108c SS |
4480 | /* Print a row's worth of GP (int) registers, with name labels above */ |
4481 | ||
4482 | static int | |
e11c53d2 | 4483 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 4484 | int start_regnum) |
c906108c | 4485 | { |
a4b8ebc8 | 4486 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 4487 | /* do values for GP (int) regs */ |
d9d9c31f | 4488 | char raw_buffer[MAX_REGISTER_SIZE]; |
d5ac5a39 | 4489 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */ |
c906108c | 4490 | int col, byte; |
a4b8ebc8 | 4491 | int regnum; |
c906108c SS |
4492 | |
4493 | /* For GP registers, we print a separate row of names above the vals */ | |
e11c53d2 | 4494 | fprintf_filtered (file, " "); |
a4b8ebc8 | 4495 | for (col = 0, regnum = start_regnum; |
6d82d43b | 4496 | col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++) |
c906108c SS |
4497 | { |
4498 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 4499 | continue; /* unused register */ |
6d82d43b AC |
4500 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
4501 | TYPE_CODE_FLT) | |
c5aa993b | 4502 | break; /* end the row: reached FP register */ |
6d82d43b | 4503 | fprintf_filtered (file, |
d5ac5a39 | 4504 | mips_abi_regsize (current_gdbarch) == 8 ? "%17s" : "%9s", |
e11c53d2 | 4505 | REGISTER_NAME (regnum)); |
c906108c SS |
4506 | col++; |
4507 | } | |
a4b8ebc8 | 4508 | /* print the R0 to R31 names */ |
20e6603c AC |
4509 | if ((start_regnum % NUM_REGS) < MIPS_NUMREGS) |
4510 | fprintf_filtered (file, "\n R%-4d", start_regnum % NUM_REGS); | |
4511 | else | |
4512 | fprintf_filtered (file, "\n "); | |
c906108c | 4513 | |
c906108c | 4514 | /* now print the values in hex, 4 or 8 to the row */ |
a4b8ebc8 | 4515 | for (col = 0, regnum = start_regnum; |
6d82d43b | 4516 | col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++) |
c906108c SS |
4517 | { |
4518 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 4519 | continue; /* unused register */ |
6d82d43b AC |
4520 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
4521 | TYPE_CODE_FLT) | |
c5aa993b | 4522 | break; /* end row: reached FP register */ |
c906108c | 4523 | /* OK: get the data in raw format. */ |
e11c53d2 | 4524 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c906108c SS |
4525 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); |
4526 | /* pad small registers */ | |
4246e332 | 4527 | for (byte = 0; |
d5ac5a39 | 4528 | byte < (mips_abi_regsize (current_gdbarch) |
6d82d43b | 4529 | - register_size (current_gdbarch, regnum)); byte++) |
c906108c SS |
4530 | printf_filtered (" "); |
4531 | /* Now print the register value in hex, endian order. */ | |
d7449b42 | 4532 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
6d82d43b AC |
4533 | for (byte = |
4534 | register_size (current_gdbarch, | |
4535 | regnum) - register_size (current_gdbarch, regnum); | |
4536 | byte < register_size (current_gdbarch, regnum); byte++) | |
e11c53d2 | 4537 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); |
c906108c | 4538 | else |
c73e8f27 | 4539 | for (byte = register_size (current_gdbarch, regnum) - 1; |
6d82d43b | 4540 | byte >= 0; byte--) |
e11c53d2 AC |
4541 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); |
4542 | fprintf_filtered (file, " "); | |
c906108c SS |
4543 | col++; |
4544 | } | |
c5aa993b | 4545 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 4546 | fprintf_filtered (file, "\n"); |
c906108c SS |
4547 | |
4548 | return regnum; | |
4549 | } | |
4550 | ||
4551 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
4552 | ||
bf1f5b4c | 4553 | static void |
e11c53d2 AC |
4554 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4555 | struct frame_info *frame, int regnum, int all) | |
c906108c | 4556 | { |
c5aa993b | 4557 | if (regnum != -1) /* do one specified register */ |
c906108c | 4558 | { |
a4b8ebc8 | 4559 | gdb_assert (regnum >= NUM_REGS); |
c906108c SS |
4560 | if (*(REGISTER_NAME (regnum)) == '\0') |
4561 | error ("Not a valid register for the current processor type"); | |
4562 | ||
e11c53d2 AC |
4563 | mips_print_register (file, frame, regnum, 0); |
4564 | fprintf_filtered (file, "\n"); | |
c906108c | 4565 | } |
c5aa993b JM |
4566 | else |
4567 | /* do all (or most) registers */ | |
c906108c | 4568 | { |
a4b8ebc8 AC |
4569 | regnum = NUM_REGS; |
4570 | while (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
c906108c | 4571 | { |
6d82d43b AC |
4572 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
4573 | TYPE_CODE_FLT) | |
e11c53d2 AC |
4574 | { |
4575 | if (all) /* true for "INFO ALL-REGISTERS" command */ | |
4576 | regnum = print_fp_register_row (file, frame, regnum); | |
4577 | else | |
4578 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
4579 | } | |
c906108c | 4580 | else |
e11c53d2 | 4581 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
4582 | } |
4583 | } | |
4584 | } | |
4585 | ||
c906108c SS |
4586 | /* Is this a branch with a delay slot? */ |
4587 | ||
a14ed312 | 4588 | static int is_delayed (unsigned long); |
c906108c SS |
4589 | |
4590 | static int | |
acdb74a0 | 4591 | is_delayed (unsigned long insn) |
c906108c SS |
4592 | { |
4593 | int i; | |
4594 | for (i = 0; i < NUMOPCODES; ++i) | |
4595 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4596 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4597 | break; | |
4598 | return (i < NUMOPCODES | |
4599 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4600 | | INSN_COND_BRANCH_DELAY | |
4601 | | INSN_COND_BRANCH_LIKELY))); | |
4602 | } | |
4603 | ||
4604 | int | |
acdb74a0 | 4605 | mips_step_skips_delay (CORE_ADDR pc) |
c906108c SS |
4606 | { |
4607 | char buf[MIPS_INSTLEN]; | |
4608 | ||
4609 | /* There is no branch delay slot on MIPS16. */ | |
4610 | if (pc_is_mips16 (pc)) | |
4611 | return 0; | |
4612 | ||
4613 | if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0) | |
4614 | /* If error reading memory, guess that it is not a delayed branch. */ | |
4615 | return 0; | |
6d82d43b AC |
4616 | return is_delayed ((unsigned long) |
4617 | extract_unsigned_integer (buf, MIPS_INSTLEN)); | |
c906108c SS |
4618 | } |
4619 | ||
c906108c SS |
4620 | /* Skip the PC past function prologue instructions (32-bit version). |
4621 | This is a helper function for mips_skip_prologue. */ | |
4622 | ||
4623 | static CORE_ADDR | |
f7b9e9fc | 4624 | mips32_skip_prologue (CORE_ADDR pc) |
c906108c | 4625 | { |
c5aa993b JM |
4626 | t_inst inst; |
4627 | CORE_ADDR end_pc; | |
4628 | int seen_sp_adjust = 0; | |
4629 | int load_immediate_bytes = 0; | |
4630 | ||
74da7425 AC |
4631 | /* Find an upper bound on the prologue. */ |
4632 | end_pc = skip_prologue_using_sal (pc); | |
4633 | if (end_pc == 0) | |
6d82d43b | 4634 | end_pc = pc + 100; /* Magic. */ |
74da7425 | 4635 | |
c5aa993b JM |
4636 | /* Skip the typical prologue instructions. These are the stack adjustment |
4637 | instruction and the instructions that save registers on the stack | |
4638 | or in the gcc frame. */ | |
74da7425 | 4639 | for (; pc < end_pc; pc += MIPS_INSTLEN) |
c5aa993b JM |
4640 | { |
4641 | unsigned long high_word; | |
c906108c | 4642 | |
c5aa993b JM |
4643 | inst = mips_fetch_instruction (pc); |
4644 | high_word = (inst >> 16) & 0xffff; | |
c906108c | 4645 | |
c5aa993b JM |
4646 | if (high_word == 0x27bd /* addiu $sp,$sp,offset */ |
4647 | || high_word == 0x67bd) /* daddiu $sp,$sp,offset */ | |
4648 | seen_sp_adjust = 1; | |
4649 | else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */ | |
4650 | inst == 0x03a8e823) /* subu $sp,$sp,$t0 */ | |
4651 | seen_sp_adjust = 1; | |
4652 | else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */ | |
4653 | || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */ | |
4654 | && (inst & 0x001F0000)) /* reg != $zero */ | |
4655 | continue; | |
4656 | ||
4657 | else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */ | |
4658 | continue; | |
4659 | else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000)) | |
4660 | /* sx reg,n($s8) */ | |
4661 | continue; /* reg != $zero */ | |
4662 | ||
4663 | /* move $s8,$sp. With different versions of gas this will be either | |
4664 | `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'. | |
4665 | Accept any one of these. */ | |
4666 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
4667 | continue; | |
4668 | ||
4669 | else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */ | |
4670 | continue; | |
6d82d43b AC |
4671 | else if (high_word == 0x3c1c) /* lui $gp,n */ |
4672 | continue; | |
4673 | else if (high_word == 0x279c) /* addiu $gp,$gp,n */ | |
4674 | continue; | |
4675 | else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
4676 | || inst == 0x033ce021) /* addu $gp,$t9,$gp */ | |
4677 | continue; | |
4678 | /* The following instructions load $at or $t0 with an immediate | |
4679 | value in preparation for a stack adjustment via | |
4680 | subu $sp,$sp,[$at,$t0]. These instructions could also initialize | |
4681 | a local variable, so we accept them only before a stack adjustment | |
4682 | instruction was seen. */ | |
4683 | else if (!seen_sp_adjust) | |
cb1d2653 | 4684 | { |
6d82d43b AC |
4685 | if (high_word == 0x3c01 || /* lui $at,n */ |
4686 | high_word == 0x3c08) /* lui $t0,n */ | |
4687 | { | |
4688 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
4689 | continue; | |
4690 | } | |
4691 | else if (high_word == 0x3421 || /* ori $at,$at,n */ | |
4692 | high_word == 0x3508 || /* ori $t0,$t0,n */ | |
4693 | high_word == 0x3401 || /* ori $at,$zero,n */ | |
4694 | high_word == 0x3408) /* ori $t0,$zero,n */ | |
4695 | { | |
4696 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
4697 | continue; | |
4698 | } | |
4699 | else | |
4700 | break; | |
cb1d2653 | 4701 | } |
6d82d43b AC |
4702 | else |
4703 | break; | |
46cac009 | 4704 | } |
6d82d43b AC |
4705 | |
4706 | /* In a frameless function, we might have incorrectly | |
4707 | skipped some load immediate instructions. Undo the skipping | |
4708 | if the load immediate was not followed by a stack adjustment. */ | |
4709 | if (load_immediate_bytes && !seen_sp_adjust) | |
4710 | pc -= load_immediate_bytes; | |
4711 | return pc; | |
46cac009 AC |
4712 | } |
4713 | ||
6d82d43b AC |
4714 | /* Skip the PC past function prologue instructions (16-bit version). |
4715 | This is a helper function for mips_skip_prologue. */ | |
cb1d2653 | 4716 | |
6d82d43b AC |
4717 | static CORE_ADDR |
4718 | mips16_skip_prologue (CORE_ADDR pc) | |
c906108c | 4719 | { |
6d82d43b AC |
4720 | CORE_ADDR end_pc; |
4721 | int extend_bytes = 0; | |
4722 | int prev_extend_bytes; | |
4723 | ||
4724 | /* Table of instructions likely to be found in a function prologue. */ | |
4725 | static struct | |
4726 | { | |
4727 | unsigned short inst; | |
4728 | unsigned short mask; | |
4729 | } | |
4730 | table[] = | |
4731 | { | |
7a292a7a | 4732 | { |
6d82d43b AC |
4733 | 0x6300, 0xff00} |
4734 | , /* addiu $sp,offset */ | |
88658117 | 4735 | { |
6d82d43b AC |
4736 | 0xfb00, 0xff00} |
4737 | , /* daddiu $sp,offset */ | |
88658117 | 4738 | { |
6d82d43b AC |
4739 | 0xd000, 0xf800} |
4740 | , /* sw reg,n($sp) */ | |
4741 | { | |
4742 | 0xf900, 0xff00} | |
4743 | , /* sd reg,n($sp) */ | |
4744 | { | |
4745 | 0x6200, 0xff00} | |
4746 | , /* sw $ra,n($sp) */ | |
4747 | { | |
4748 | 0xfa00, 0xff00} | |
4749 | , /* sd $ra,n($sp) */ | |
4750 | { | |
4751 | 0x673d, 0xffff} | |
4752 | , /* move $s1,sp */ | |
4753 | { | |
4754 | 0xd980, 0xff80} | |
4755 | , /* sw $a0-$a3,n($s1) */ | |
4756 | { | |
4757 | 0x6704, 0xff1c} | |
4758 | , /* move reg,$a0-$a3 */ | |
4759 | { | |
4760 | 0xe809, 0xf81f} | |
4761 | , /* entry pseudo-op */ | |
4762 | { | |
4763 | 0x0100, 0xff00} | |
4764 | , /* addiu $s1,$sp,n */ | |
4765 | { | |
4766 | 0, 0} /* end of table marker */ | |
4767 | }; | |
4768 | ||
4769 | /* Find an upper bound on the prologue. */ | |
4770 | end_pc = skip_prologue_using_sal (pc); | |
4771 | if (end_pc == 0) | |
4772 | end_pc = pc + 100; /* Magic. */ | |
4773 | ||
4774 | /* Skip the typical prologue instructions. These are the stack adjustment | |
4775 | instruction and the instructions that save registers on the stack | |
4776 | or in the gcc frame. */ | |
4777 | for (; pc < end_pc; pc += MIPS16_INSTLEN) | |
4778 | { | |
4779 | unsigned short inst; | |
4780 | int i; | |
4781 | ||
4782 | inst = mips_fetch_instruction (pc); | |
4783 | ||
4784 | /* Normally we ignore an extend instruction. However, if it is | |
4785 | not followed by a valid prologue instruction, we must adjust | |
4786 | the pc back over the extend so that it won't be considered | |
4787 | part of the prologue. */ | |
4788 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
88658117 | 4789 | { |
6d82d43b AC |
4790 | extend_bytes = MIPS16_INSTLEN; |
4791 | continue; | |
88658117 | 4792 | } |
6d82d43b AC |
4793 | prev_extend_bytes = extend_bytes; |
4794 | extend_bytes = 0; | |
4795 | ||
4796 | /* Check for other valid prologue instructions besides extend. */ | |
4797 | for (i = 0; table[i].mask != 0; i++) | |
4798 | if ((inst & table[i].mask) == table[i].inst) /* found, get out */ | |
4799 | break; | |
4800 | if (table[i].mask != 0) /* it was in table? */ | |
4801 | continue; /* ignore it */ | |
4802 | else | |
4803 | /* non-prologue */ | |
88658117 | 4804 | { |
6d82d43b AC |
4805 | /* Return the current pc, adjusted backwards by 2 if |
4806 | the previous instruction was an extend. */ | |
4807 | return pc - prev_extend_bytes; | |
88658117 AC |
4808 | } |
4809 | } | |
6d82d43b AC |
4810 | return pc; |
4811 | } | |
4812 | ||
4813 | /* To skip prologues, I use this predicate. Returns either PC itself | |
4814 | if the code at PC does not look like a function prologue; otherwise | |
4815 | returns an address that (if we're lucky) follows the prologue. If | |
4816 | LENIENT, then we must skip everything which is involved in setting | |
4817 | up the frame (it's OK to skip more, just so long as we don't skip | |
4818 | anything which might clobber the registers which are being saved. | |
4819 | We must skip more in the case where part of the prologue is in the | |
4820 | delay slot of a non-prologue instruction). */ | |
4821 | ||
4822 | static CORE_ADDR | |
4823 | mips_skip_prologue (CORE_ADDR pc) | |
4824 | { | |
4825 | /* See if we can determine the end of the prologue via the symbol table. | |
4826 | If so, then return either PC, or the PC after the prologue, whichever | |
4827 | is greater. */ | |
4828 | ||
4829 | CORE_ADDR post_prologue_pc = after_prologue (pc, NULL); | |
4830 | ||
4831 | if (post_prologue_pc != 0) | |
4832 | return max (pc, post_prologue_pc); | |
4833 | ||
4834 | /* Can't determine prologue from the symbol table, need to examine | |
4835 | instructions. */ | |
4836 | ||
4837 | if (pc_is_mips16 (pc)) | |
4838 | return mips16_skip_prologue (pc); | |
4839 | else | |
4840 | return mips32_skip_prologue (pc); | |
88658117 AC |
4841 | } |
4842 | ||
a5ea2558 AC |
4843 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
4844 | used for all MIPS-specific commands. */ | |
4845 | ||
a5ea2558 | 4846 | static void |
acdb74a0 | 4847 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
4848 | { |
4849 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
4850 | } | |
4851 | ||
a5ea2558 | 4852 | static void |
acdb74a0 | 4853 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 4854 | { |
6d82d43b AC |
4855 | printf_unfiltered |
4856 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
4857 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
4858 | } | |
4859 | ||
c906108c SS |
4860 | /* Commands to show/set the MIPS FPU type. */ |
4861 | ||
c906108c | 4862 | static void |
acdb74a0 | 4863 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 4864 | { |
c906108c SS |
4865 | char *fpu; |
4866 | switch (MIPS_FPU_TYPE) | |
4867 | { | |
4868 | case MIPS_FPU_SINGLE: | |
4869 | fpu = "single-precision"; | |
4870 | break; | |
4871 | case MIPS_FPU_DOUBLE: | |
4872 | fpu = "double-precision"; | |
4873 | break; | |
4874 | case MIPS_FPU_NONE: | |
4875 | fpu = "absent (none)"; | |
4876 | break; | |
93d56215 AC |
4877 | default: |
4878 | internal_error (__FILE__, __LINE__, "bad switch"); | |
c906108c SS |
4879 | } |
4880 | if (mips_fpu_type_auto) | |
6d82d43b AC |
4881 | printf_unfiltered |
4882 | ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
4883 | fpu); | |
c906108c | 4884 | else |
6d82d43b AC |
4885 | printf_unfiltered |
4886 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
4887 | } |
4888 | ||
4889 | ||
c906108c | 4890 | static void |
acdb74a0 | 4891 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 4892 | { |
6d82d43b AC |
4893 | printf_unfiltered |
4894 | ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
4895 | show_mipsfpu_command (args, from_tty); |
4896 | } | |
4897 | ||
c906108c | 4898 | static void |
acdb74a0 | 4899 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 4900 | { |
8d5838b5 AC |
4901 | struct gdbarch_info info; |
4902 | gdbarch_info_init (&info); | |
c906108c SS |
4903 | mips_fpu_type = MIPS_FPU_SINGLE; |
4904 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4905 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4906 | instead of relying on globals. Doing that would let generic code | |
4907 | handle the search for this specific architecture. */ | |
4908 | if (!gdbarch_update_p (info)) | |
4909 | internal_error (__FILE__, __LINE__, "set mipsfpu failed"); | |
c906108c SS |
4910 | } |
4911 | ||
c906108c | 4912 | static void |
acdb74a0 | 4913 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 4914 | { |
8d5838b5 AC |
4915 | struct gdbarch_info info; |
4916 | gdbarch_info_init (&info); | |
c906108c SS |
4917 | mips_fpu_type = MIPS_FPU_DOUBLE; |
4918 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4919 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4920 | instead of relying on globals. Doing that would let generic code | |
4921 | handle the search for this specific architecture. */ | |
4922 | if (!gdbarch_update_p (info)) | |
4923 | internal_error (__FILE__, __LINE__, "set mipsfpu failed"); | |
c906108c SS |
4924 | } |
4925 | ||
c906108c | 4926 | static void |
acdb74a0 | 4927 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 4928 | { |
8d5838b5 AC |
4929 | struct gdbarch_info info; |
4930 | gdbarch_info_init (&info); | |
c906108c SS |
4931 | mips_fpu_type = MIPS_FPU_NONE; |
4932 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4933 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4934 | instead of relying on globals. Doing that would let generic code | |
4935 | handle the search for this specific architecture. */ | |
4936 | if (!gdbarch_update_p (info)) | |
4937 | internal_error (__FILE__, __LINE__, "set mipsfpu failed"); | |
c906108c SS |
4938 | } |
4939 | ||
c906108c | 4940 | static void |
acdb74a0 | 4941 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
4942 | { |
4943 | mips_fpu_type_auto = 1; | |
4944 | } | |
4945 | ||
c906108c | 4946 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
4947 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
4948 | the relevant processor still exists (it dates back to '94) and | |
4949 | secondly this is not the way to do this. The processor type should | |
4950 | be set by forcing an architecture change. */ | |
c906108c | 4951 | |
691c0433 AC |
4952 | void |
4953 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 4954 | { |
691c0433 | 4955 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
4956 | CORE_ADDR prid; |
4957 | ||
4958 | prid = read_register (PRID_REGNUM); | |
4959 | ||
4960 | if ((prid & ~0xf) == 0x700) | |
691c0433 | 4961 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
4962 | } |
4963 | ||
4964 | /* Just like reinit_frame_cache, but with the right arguments to be | |
4965 | callable as an sfunc. */ | |
4966 | ||
4967 | static void | |
acdb74a0 AC |
4968 | reinit_frame_cache_sfunc (char *args, int from_tty, |
4969 | struct cmd_list_element *c) | |
c906108c SS |
4970 | { |
4971 | reinit_frame_cache (); | |
4972 | } | |
4973 | ||
a89aa300 AC |
4974 | static int |
4975 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 4976 | { |
e5ab0dce | 4977 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
4978 | mips_extra_func_info_t proc_desc; |
4979 | ||
4980 | /* Search for the function containing this address. Set the low bit | |
4981 | of the address when searching, in case we were given an even address | |
4982 | that is the start of a 16-bit function. If we didn't do this, | |
4983 | the search would fail because the symbol table says the function | |
4984 | starts at an odd address, i.e. 1 byte past the given address. */ | |
4985 | memaddr = ADDR_BITS_REMOVE (memaddr); | |
95404a3e | 4986 | proc_desc = non_heuristic_proc_desc (make_mips16_addr (memaddr), NULL); |
c906108c SS |
4987 | |
4988 | /* Make an attempt to determine if this is a 16-bit function. If | |
4989 | the procedure descriptor exists and the address therein is odd, | |
4990 | it's definitely a 16-bit function. Otherwise, we have to just | |
4991 | guess that if the address passed in is odd, it's 16-bits. */ | |
d31431ed AC |
4992 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
4993 | disassembler needs to be able to locally determine the ISA, and | |
4994 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
4995 | work. */ | |
c906108c | 4996 | if (proc_desc) |
d31431ed AC |
4997 | { |
4998 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) | |
6d82d43b | 4999 | info->mach = bfd_mach_mips16; |
d31431ed | 5000 | } |
c906108c | 5001 | else |
d31431ed AC |
5002 | { |
5003 | if (pc_is_mips16 (memaddr)) | |
6d82d43b AC |
5004 | info->mach = bfd_mach_mips16; |
5005 | } | |
c906108c SS |
5006 | |
5007 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 5008 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 5009 | |
e5ab0dce | 5010 | /* Set the disassembler options. */ |
6d82d43b | 5011 | if (tdep->mips_abi == MIPS_ABI_N32 || tdep->mips_abi == MIPS_ABI_N64) |
e5ab0dce AC |
5012 | { |
5013 | /* Set up the disassembler info, so that we get the right | |
6d82d43b | 5014 | register names from libopcodes. */ |
e5ab0dce AC |
5015 | if (tdep->mips_abi == MIPS_ABI_N32) |
5016 | info->disassembler_options = "gpr-names=n32"; | |
5017 | else | |
5018 | info->disassembler_options = "gpr-names=64"; | |
5019 | info->flavour = bfd_target_elf_flavour; | |
5020 | } | |
5021 | else | |
5022 | /* This string is not recognized explicitly by the disassembler, | |
5023 | but it tells the disassembler to not try to guess the ABI from | |
5024 | the bfd elf headers, such that, if the user overrides the ABI | |
5025 | of a program linked as NewABI, the disassembly will follow the | |
5026 | register naming conventions specified by the user. */ | |
5027 | info->disassembler_options = "gpr-names=32"; | |
5028 | ||
c906108c | 5029 | /* Call the appropriate disassembler based on the target endian-ness. */ |
d7449b42 | 5030 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
5031 | return print_insn_big_mips (memaddr, info); |
5032 | else | |
5033 | return print_insn_little_mips (memaddr, info); | |
5034 | } | |
5035 | ||
c906108c SS |
5036 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program |
5037 | counter value to determine whether a 16- or 32-bit breakpoint should be | |
5038 | used. It returns a pointer to a string of bytes that encode a breakpoint | |
5039 | instruction, stores the length of the string to *lenptr, and adjusts pc | |
5040 | (if necessary) to point to the actual memory location where the | |
5041 | breakpoint should be inserted. */ | |
5042 | ||
f7ab6ec6 | 5043 | static const unsigned char * |
6d82d43b | 5044 | mips_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c | 5045 | { |
d7449b42 | 5046 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
5047 | { |
5048 | if (pc_is_mips16 (*pcptr)) | |
5049 | { | |
6d82d43b | 5050 | static unsigned char mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
95404a3e | 5051 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5052 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
5053 | return mips16_big_breakpoint; |
5054 | } | |
5055 | else | |
5056 | { | |
aaab4dba AC |
5057 | /* The IDT board uses an unusual breakpoint value, and |
5058 | sometimes gets confused when it sees the usual MIPS | |
5059 | breakpoint instruction. */ | |
6d82d43b AC |
5060 | static unsigned char big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
5061 | static unsigned char pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
5062 | static unsigned char idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
c906108c | 5063 | |
c5aa993b | 5064 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
5065 | |
5066 | if (strcmp (target_shortname, "mips") == 0) | |
5067 | return idt_big_breakpoint; | |
5068 | else if (strcmp (target_shortname, "ddb") == 0 | |
5069 | || strcmp (target_shortname, "pmon") == 0 | |
5070 | || strcmp (target_shortname, "lsi") == 0) | |
5071 | return pmon_big_breakpoint; | |
5072 | else | |
5073 | return big_breakpoint; | |
5074 | } | |
5075 | } | |
5076 | else | |
5077 | { | |
5078 | if (pc_is_mips16 (*pcptr)) | |
5079 | { | |
6d82d43b | 5080 | static unsigned char mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
95404a3e | 5081 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5082 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
5083 | return mips16_little_breakpoint; |
5084 | } | |
5085 | else | |
5086 | { | |
6d82d43b AC |
5087 | static unsigned char little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
5088 | static unsigned char pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
5089 | static unsigned char idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 5090 | |
c5aa993b | 5091 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
5092 | |
5093 | if (strcmp (target_shortname, "mips") == 0) | |
5094 | return idt_little_breakpoint; | |
5095 | else if (strcmp (target_shortname, "ddb") == 0 | |
5096 | || strcmp (target_shortname, "pmon") == 0 | |
5097 | || strcmp (target_shortname, "lsi") == 0) | |
5098 | return pmon_little_breakpoint; | |
5099 | else | |
5100 | return little_breakpoint; | |
5101 | } | |
5102 | } | |
5103 | } | |
5104 | ||
5105 | /* If PC is in a mips16 call or return stub, return the address of the target | |
5106 | PC, which is either the callee or the caller. There are several | |
5107 | cases which must be handled: | |
5108 | ||
5109 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 5110 | target PC is in $31 ($ra). |
c906108c | 5111 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 5112 | and the target PC is in $2. |
c906108c | 5113 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
5114 | before the jal instruction, this is effectively a call stub |
5115 | and the the target PC is in $2. Otherwise this is effectively | |
5116 | a return stub and the target PC is in $18. | |
c906108c SS |
5117 | |
5118 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
5119 | gory details. | |
5120 | ||
5121 | This function implements the SKIP_TRAMPOLINE_CODE macro. | |
c5aa993b | 5122 | */ |
c906108c | 5123 | |
757a7cc6 | 5124 | static CORE_ADDR |
acdb74a0 | 5125 | mips_skip_stub (CORE_ADDR pc) |
c906108c SS |
5126 | { |
5127 | char *name; | |
5128 | CORE_ADDR start_addr; | |
5129 | ||
5130 | /* Find the starting address and name of the function containing the PC. */ | |
5131 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
5132 | return 0; | |
5133 | ||
5134 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
5135 | target PC is in $31 ($ra). */ | |
5136 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5137 | || strcmp (name, "__mips16_ret_df") == 0) | |
6c997a34 | 5138 | return read_signed_register (RA_REGNUM); |
c906108c SS |
5139 | |
5140 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5141 | { | |
5142 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
5143 | and the target PC is in $2. */ | |
5144 | if (name[19] >= '0' && name[19] <= '9') | |
6c997a34 | 5145 | return read_signed_register (2); |
c906108c SS |
5146 | |
5147 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
5148 | before the jal instruction, this is effectively a call stub |
5149 | and the the target PC is in $2. Otherwise this is effectively | |
5150 | a return stub and the target PC is in $18. */ | |
c906108c SS |
5151 | else if (name[19] == 's' || name[19] == 'd') |
5152 | { | |
5153 | if (pc == start_addr) | |
5154 | { | |
5155 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
5156 | stub. Such a stub for a function bar might have a name |
5157 | like __fn_stub_bar, and might look like this: | |
5158 | mfc1 $4,$f13 | |
5159 | mfc1 $5,$f12 | |
5160 | mfc1 $6,$f15 | |
5161 | mfc1 $7,$f14 | |
5162 | la $1,bar (becomes a lui/addiu pair) | |
5163 | jr $1 | |
5164 | So scan down to the lui/addi and extract the target | |
5165 | address from those two instructions. */ | |
c906108c | 5166 | |
6c997a34 | 5167 | CORE_ADDR target_pc = read_signed_register (2); |
c906108c SS |
5168 | t_inst inst; |
5169 | int i; | |
5170 | ||
5171 | /* See if the name of the target function is __fn_stub_*. */ | |
6d82d43b AC |
5172 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == |
5173 | 0) | |
c906108c SS |
5174 | return target_pc; |
5175 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
5176 | && strcmp (name, "etext") != 0 | |
5177 | && strcmp (name, "_etext") != 0) | |
5178 | return target_pc; | |
5179 | ||
5180 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
5181 | The limit on the search is arbitrarily set to 20 |
5182 | instructions. FIXME. */ | |
c906108c SS |
5183 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN) |
5184 | { | |
c5aa993b JM |
5185 | inst = mips_fetch_instruction (target_pc); |
5186 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
5187 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
5188 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
5189 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
5190 | } |
5191 | ||
5192 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
5193 | return target_pc; | |
5194 | } | |
5195 | else | |
5196 | /* This is the 'return' part of a call stub. The return | |
5197 | address is in $r18. */ | |
6c997a34 | 5198 | return read_signed_register (18); |
c906108c SS |
5199 | } |
5200 | } | |
c5aa993b | 5201 | return 0; /* not a stub */ |
c906108c SS |
5202 | } |
5203 | ||
5204 | ||
5205 | /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline). | |
5206 | This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */ | |
5207 | ||
757a7cc6 | 5208 | static int |
acdb74a0 | 5209 | mips_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
5210 | { |
5211 | CORE_ADDR start_addr; | |
5212 | ||
5213 | /* Find the starting address of the function containing the PC. If the | |
5214 | caller didn't give us a name, look it up at the same time. */ | |
6d82d43b AC |
5215 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == |
5216 | 0) | |
c906108c SS |
5217 | return 0; |
5218 | ||
5219 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5220 | { | |
5221 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */ | |
5222 | if (name[19] >= '0' && name[19] <= '9') | |
5223 | return 1; | |
5224 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b | 5225 | before the jal instruction, this is effectively a call stub. */ |
c906108c SS |
5226 | else if (name[19] == 's' || name[19] == 'd') |
5227 | return pc == start_addr; | |
5228 | } | |
5229 | ||
c5aa993b | 5230 | return 0; /* not a stub */ |
c906108c SS |
5231 | } |
5232 | ||
5233 | ||
5234 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
5235 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
5236 | ||
e41b17f0 | 5237 | static int |
acdb74a0 | 5238 | mips_in_return_stub (CORE_ADDR pc, char *name) |
c906108c SS |
5239 | { |
5240 | CORE_ADDR start_addr; | |
5241 | ||
5242 | /* Find the starting address of the function containing the PC. */ | |
5243 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
5244 | return 0; | |
5245 | ||
5246 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */ | |
5247 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5248 | || strcmp (name, "__mips16_ret_df") == 0) | |
5249 | return 1; | |
5250 | ||
5251 | /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start, | |
c5aa993b | 5252 | i.e. after the jal instruction, this is effectively a return stub. */ |
c906108c | 5253 | if (strncmp (name, "__mips16_call_stub_", 19) == 0 |
6d82d43b | 5254 | && (name[19] == 's' || name[19] == 'd') && pc != start_addr) |
c906108c SS |
5255 | return 1; |
5256 | ||
c5aa993b | 5257 | return 0; /* not a stub */ |
c906108c SS |
5258 | } |
5259 | ||
5260 | ||
5261 | /* Return non-zero if the PC is in a library helper function that should | |
5262 | be ignored. This implements the IGNORE_HELPER_CALL macro. */ | |
5263 | ||
5264 | int | |
acdb74a0 | 5265 | mips_ignore_helper (CORE_ADDR pc) |
c906108c SS |
5266 | { |
5267 | char *name; | |
5268 | ||
5269 | /* Find the starting address and name of the function containing the PC. */ | |
5270 | if (find_pc_partial_function (pc, &name, NULL, NULL) == 0) | |
5271 | return 0; | |
5272 | ||
5273 | /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function | |
5274 | that we want to ignore. */ | |
5275 | return (strcmp (name, "__mips16_ret_sf") == 0 | |
5276 | || strcmp (name, "__mips16_ret_df") == 0); | |
5277 | } | |
5278 | ||
5279 | ||
a4b8ebc8 AC |
5280 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
5281 | [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */ | |
88c72b7d AC |
5282 | |
5283 | static int | |
5284 | mips_stab_reg_to_regnum (int num) | |
5285 | { | |
a4b8ebc8 | 5286 | int regnum; |
2f38ef89 | 5287 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5288 | regnum = num; |
2f38ef89 | 5289 | else if (num >= 38 && num < 70) |
56cea623 | 5290 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 38; |
040b99fd | 5291 | else if (num == 70) |
56cea623 | 5292 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 5293 | else if (num == 71) |
56cea623 | 5294 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 5295 | else |
a4b8ebc8 AC |
5296 | /* This will hopefully (eventually) provoke a warning. Should |
5297 | we be calling complaint() here? */ | |
5298 | return NUM_REGS + NUM_PSEUDO_REGS; | |
5299 | return NUM_REGS + regnum; | |
88c72b7d AC |
5300 | } |
5301 | ||
2f38ef89 | 5302 | |
a4b8ebc8 AC |
5303 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
5304 | NUM_REGS .. 2 * NUM_REGS) REGNUM. */ | |
88c72b7d AC |
5305 | |
5306 | static int | |
2f38ef89 | 5307 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num) |
88c72b7d | 5308 | { |
a4b8ebc8 | 5309 | int regnum; |
2f38ef89 | 5310 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5311 | regnum = num; |
2f38ef89 | 5312 | else if (num >= 32 && num < 64) |
56cea623 | 5313 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 32; |
040b99fd | 5314 | else if (num == 64) |
56cea623 | 5315 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 5316 | else if (num == 65) |
56cea623 | 5317 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 5318 | else |
a4b8ebc8 AC |
5319 | /* This will hopefully (eventually) provoke a warning. Should we |
5320 | be calling complaint() here? */ | |
5321 | return NUM_REGS + NUM_PSEUDO_REGS; | |
5322 | return NUM_REGS + regnum; | |
5323 | } | |
5324 | ||
5325 | static int | |
5326 | mips_register_sim_regno (int regnum) | |
5327 | { | |
5328 | /* Only makes sense to supply raw registers. */ | |
5329 | gdb_assert (regnum >= 0 && regnum < NUM_REGS); | |
5330 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to | |
5331 | decide if it is valid. Should instead define a standard sim/gdb | |
5332 | register numbering scheme. */ | |
5333 | if (REGISTER_NAME (NUM_REGS + regnum) != NULL | |
5334 | && REGISTER_NAME (NUM_REGS + regnum)[0] != '\0') | |
5335 | return regnum; | |
5336 | else | |
6d82d43b | 5337 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
5338 | } |
5339 | ||
2f38ef89 | 5340 | |
fc0c74b1 AC |
5341 | /* Convert an integer into an address. By first converting the value |
5342 | into a pointer and then extracting it signed, the address is | |
5343 | guarenteed to be correctly sign extended. */ | |
5344 | ||
5345 | static CORE_ADDR | |
5346 | mips_integer_to_address (struct type *type, void *buf) | |
5347 | { | |
5348 | char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5349 | LONGEST val = unpack_long (type, buf); | |
5350 | store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val); | |
5351 | return extract_signed_integer (tmp, | |
5352 | TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5353 | } | |
5354 | ||
caaa3122 DJ |
5355 | static void |
5356 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
5357 | { | |
5358 | enum mips_abi *abip = (enum mips_abi *) obj; | |
5359 | const char *name = bfd_get_section_name (abfd, sect); | |
5360 | ||
5361 | if (*abip != MIPS_ABI_UNKNOWN) | |
5362 | return; | |
5363 | ||
5364 | if (strncmp (name, ".mdebug.", 8) != 0) | |
5365 | return; | |
5366 | ||
5367 | if (strcmp (name, ".mdebug.abi32") == 0) | |
5368 | *abip = MIPS_ABI_O32; | |
5369 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
5370 | *abip = MIPS_ABI_N32; | |
62a49b2c | 5371 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 5372 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
5373 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
5374 | *abip = MIPS_ABI_O64; | |
5375 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
5376 | *abip = MIPS_ABI_EABI32; | |
5377 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
5378 | *abip = MIPS_ABI_EABI64; | |
5379 | else | |
5380 | warning ("unsupported ABI %s.", name + 8); | |
5381 | } | |
5382 | ||
2e4ebe70 DJ |
5383 | static enum mips_abi |
5384 | global_mips_abi (void) | |
5385 | { | |
5386 | int i; | |
5387 | ||
5388 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
5389 | if (mips_abi_strings[i] == mips_abi_string) | |
5390 | return (enum mips_abi) i; | |
5391 | ||
6d82d43b | 5392 | internal_error (__FILE__, __LINE__, "unknown ABI string"); |
2e4ebe70 DJ |
5393 | } |
5394 | ||
c2d11a7d | 5395 | static struct gdbarch * |
6d82d43b | 5396 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 5397 | { |
c2d11a7d JM |
5398 | struct gdbarch *gdbarch; |
5399 | struct gdbarch_tdep *tdep; | |
5400 | int elf_flags; | |
2e4ebe70 | 5401 | enum mips_abi mips_abi, found_abi, wanted_abi; |
a4b8ebc8 | 5402 | int num_regs; |
8d5838b5 | 5403 | enum mips_fpu_type fpu_type; |
c2d11a7d | 5404 | |
ec03c1ac AC |
5405 | /* First of all, extract the elf_flags, if available. */ |
5406 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5407 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
5408 | else if (arches != NULL) |
5409 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
5410 | else |
5411 | elf_flags = 0; | |
5412 | if (gdbarch_debug) | |
5413 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5414 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 5415 | |
102182a9 | 5416 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
5417 | switch ((elf_flags & EF_MIPS_ABI)) |
5418 | { | |
5419 | case E_MIPS_ABI_O32: | |
ec03c1ac | 5420 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
5421 | break; |
5422 | case E_MIPS_ABI_O64: | |
ec03c1ac | 5423 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
5424 | break; |
5425 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 5426 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
5427 | break; |
5428 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 5429 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
5430 | break; |
5431 | default: | |
acdb74a0 | 5432 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 5433 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 5434 | else |
ec03c1ac | 5435 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
5436 | break; |
5437 | } | |
acdb74a0 | 5438 | |
caaa3122 | 5439 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
5440 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
5441 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 5442 | |
dc305454 | 5443 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
5444 | MIPS architecture (if there is one). */ |
5445 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
5446 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 5447 | |
32a6503c | 5448 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 5449 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
5450 | && info.bfd_arch_info != NULL |
5451 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5452 | { | |
5453 | switch (info.bfd_arch_info->mach) | |
5454 | { | |
5455 | case bfd_mach_mips3900: | |
ec03c1ac | 5456 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
5457 | break; |
5458 | case bfd_mach_mips4100: | |
5459 | case bfd_mach_mips5000: | |
ec03c1ac | 5460 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 5461 | break; |
1d06468c EZ |
5462 | case bfd_mach_mips8000: |
5463 | case bfd_mach_mips10000: | |
32a6503c KB |
5464 | /* On Irix, ELF64 executables use the N64 ABI. The |
5465 | pseudo-sections which describe the ABI aren't present | |
5466 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
5467 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
5468 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 5469 | found_abi = MIPS_ABI_N64; |
28d169de | 5470 | else |
ec03c1ac | 5471 | found_abi = MIPS_ABI_N32; |
1d06468c | 5472 | break; |
bf64bfd6 AC |
5473 | } |
5474 | } | |
2e4ebe70 | 5475 | |
ec03c1ac AC |
5476 | if (gdbarch_debug) |
5477 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
5478 | found_abi); | |
5479 | ||
5480 | /* What has the user specified from the command line? */ | |
5481 | wanted_abi = global_mips_abi (); | |
5482 | if (gdbarch_debug) | |
5483 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
5484 | wanted_abi); | |
2e4ebe70 DJ |
5485 | |
5486 | /* Now that we have found what the ABI for this binary would be, | |
5487 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
5488 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
5489 | mips_abi = wanted_abi; | |
ec03c1ac AC |
5490 | else if (found_abi != MIPS_ABI_UNKNOWN) |
5491 | mips_abi = found_abi; | |
5492 | else | |
5493 | mips_abi = MIPS_ABI_O32; | |
5494 | if (gdbarch_debug) | |
5495 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
5496 | mips_abi); | |
2e4ebe70 | 5497 | |
ec03c1ac | 5498 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 5499 | if (gdbarch_debug) |
ec03c1ac AC |
5500 | fprintf_unfiltered (gdb_stdlog, |
5501 | "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n", | |
5502 | mips64_transfers_32bit_regs_p); | |
0dadbba0 | 5503 | |
8d5838b5 AC |
5504 | /* Determine the MIPS FPU type. */ |
5505 | if (!mips_fpu_type_auto) | |
5506 | fpu_type = mips_fpu_type; | |
5507 | else if (info.bfd_arch_info != NULL | |
5508 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5509 | switch (info.bfd_arch_info->mach) | |
5510 | { | |
5511 | case bfd_mach_mips3900: | |
5512 | case bfd_mach_mips4100: | |
5513 | case bfd_mach_mips4111: | |
5514 | fpu_type = MIPS_FPU_NONE; | |
5515 | break; | |
5516 | case bfd_mach_mips4650: | |
5517 | fpu_type = MIPS_FPU_SINGLE; | |
5518 | break; | |
5519 | default: | |
5520 | fpu_type = MIPS_FPU_DOUBLE; | |
5521 | break; | |
5522 | } | |
5523 | else if (arches != NULL) | |
5524 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
5525 | else | |
5526 | fpu_type = MIPS_FPU_DOUBLE; | |
5527 | if (gdbarch_debug) | |
5528 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5529 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 5530 | |
c2d11a7d JM |
5531 | /* try to find a pre-existing architecture */ |
5532 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
5533 | arches != NULL; | |
5534 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
5535 | { | |
5536 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 5537 | using. */ |
9103eae0 | 5538 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 5539 | continue; |
9103eae0 | 5540 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 5541 | continue; |
719ec221 AC |
5542 | /* Need to be pedantic about which register virtual size is |
5543 | used. */ | |
5544 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
5545 | != mips64_transfers_32bit_regs_p) | |
5546 | continue; | |
8d5838b5 AC |
5547 | /* Be pedantic about which FPU is selected. */ |
5548 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
5549 | continue; | |
4be87837 | 5550 | return arches->gdbarch; |
c2d11a7d JM |
5551 | } |
5552 | ||
102182a9 | 5553 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
5554 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
5555 | gdbarch = gdbarch_alloc (&info, tdep); | |
5556 | tdep->elf_flags = elf_flags; | |
719ec221 | 5557 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
5558 | tdep->found_abi = found_abi; |
5559 | tdep->mips_abi = mips_abi; | |
8d5838b5 | 5560 | tdep->mips_fpu_type = fpu_type; |
c2d11a7d | 5561 | |
102182a9 | 5562 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
5563 | set_gdbarch_short_bit (gdbarch, 16); |
5564 | set_gdbarch_int_bit (gdbarch, 32); | |
5565 | set_gdbarch_float_bit (gdbarch, 32); | |
5566 | set_gdbarch_double_bit (gdbarch, 64); | |
5567 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
5568 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
5569 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
5570 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 5571 | |
6d82d43b | 5572 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
5573 | mips_elf_make_msymbol_special); |
5574 | ||
16e109ca | 5575 | /* Fill in the OS dependant register numbers and names. */ |
56cea623 | 5576 | { |
16e109ca | 5577 | const char **reg_names; |
56cea623 AC |
5578 | struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, |
5579 | struct mips_regnum); | |
56cea623 AC |
5580 | if (info.osabi == GDB_OSABI_IRIX) |
5581 | { | |
5582 | regnum->fp0 = 32; | |
5583 | regnum->pc = 64; | |
5584 | regnum->cause = 65; | |
5585 | regnum->badvaddr = 66; | |
5586 | regnum->hi = 67; | |
5587 | regnum->lo = 68; | |
5588 | regnum->fp_control_status = 69; | |
5589 | regnum->fp_implementation_revision = 70; | |
5590 | num_regs = 71; | |
16e109ca | 5591 | reg_names = mips_irix_reg_names; |
56cea623 AC |
5592 | } |
5593 | else | |
5594 | { | |
5595 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5596 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5597 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5598 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5599 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5600 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5601 | regnum->fp_control_status = 70; | |
5602 | regnum->fp_implementation_revision = 71; | |
5603 | num_regs = 90; | |
16e109ca AC |
5604 | if (info.bfd_arch_info != NULL |
5605 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
5606 | reg_names = mips_tx39_reg_names; | |
5607 | else | |
5608 | reg_names = mips_generic_reg_names; | |
56cea623 AC |
5609 | } |
5610 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been | |
5611 | replaced by read_pc? */ | |
5612 | set_gdbarch_pc_regnum (gdbarch, regnum->pc); | |
5613 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); | |
5614 | set_gdbarch_num_regs (gdbarch, num_regs); | |
5615 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
16e109ca AC |
5616 | set_gdbarch_register_name (gdbarch, mips_register_name); |
5617 | tdep->mips_processor_reg_names = reg_names; | |
5618 | tdep->regnum = regnum; | |
56cea623 | 5619 | } |
fe29b929 | 5620 | |
0dadbba0 | 5621 | switch (mips_abi) |
c2d11a7d | 5622 | { |
0dadbba0 | 5623 | case MIPS_ABI_O32: |
25ab4790 | 5624 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 5625 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
acdb74a0 | 5626 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
56cea623 | 5627 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 5628 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5629 | set_gdbarch_long_bit (gdbarch, 32); |
5630 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5631 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5632 | break; | |
0dadbba0 | 5633 | case MIPS_ABI_O64: |
25ab4790 | 5634 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
6d82d43b AC |
5635 | set_gdbarch_deprecated_store_return_value (gdbarch, |
5636 | mips_o64_store_return_value); | |
5637 | set_gdbarch_deprecated_extract_return_value (gdbarch, | |
5638 | mips_o64_extract_return_value); | |
acdb74a0 | 5639 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
56cea623 | 5640 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 5641 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5642 | set_gdbarch_long_bit (gdbarch, 32); |
5643 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5644 | set_gdbarch_long_long_bit (gdbarch, 64); | |
6d82d43b AC |
5645 | set_gdbarch_use_struct_convention (gdbarch, |
5646 | always_use_struct_convention); | |
c2d11a7d | 5647 | break; |
0dadbba0 | 5648 | case MIPS_ABI_EABI32: |
25ab4790 | 5649 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
6d82d43b AC |
5650 | set_gdbarch_deprecated_store_return_value (gdbarch, |
5651 | mips_eabi_store_return_value); | |
5652 | set_gdbarch_deprecated_extract_return_value (gdbarch, | |
5653 | mips_eabi_extract_return_value); | |
acdb74a0 | 5654 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 5655 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5656 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5657 | set_gdbarch_long_bit (gdbarch, 32); |
5658 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5659 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
5660 | set_gdbarch_deprecated_reg_struct_has_addr |
5661 | (gdbarch, mips_eabi_reg_struct_has_addr); | |
6d82d43b | 5662 | set_gdbarch_use_struct_convention (gdbarch, |
cb811fe7 | 5663 | mips_eabi_use_struct_convention); |
c2d11a7d | 5664 | break; |
0dadbba0 | 5665 | case MIPS_ABI_EABI64: |
25ab4790 | 5666 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
6d82d43b AC |
5667 | set_gdbarch_deprecated_store_return_value (gdbarch, |
5668 | mips_eabi_store_return_value); | |
5669 | set_gdbarch_deprecated_extract_return_value (gdbarch, | |
5670 | mips_eabi_extract_return_value); | |
acdb74a0 | 5671 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 5672 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5673 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5674 | set_gdbarch_long_bit (gdbarch, 64); |
5675 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5676 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
5677 | set_gdbarch_deprecated_reg_struct_has_addr |
5678 | (gdbarch, mips_eabi_reg_struct_has_addr); | |
6d82d43b | 5679 | set_gdbarch_use_struct_convention (gdbarch, |
cb811fe7 | 5680 | mips_eabi_use_struct_convention); |
c2d11a7d | 5681 | break; |
0dadbba0 | 5682 | case MIPS_ABI_N32: |
25ab4790 | 5683 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5684 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
acdb74a0 | 5685 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 5686 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5687 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
5688 | set_gdbarch_long_bit (gdbarch, 32); |
5689 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5690 | set_gdbarch_long_long_bit (gdbarch, 64); | |
28d169de KB |
5691 | break; |
5692 | case MIPS_ABI_N64: | |
25ab4790 | 5693 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5694 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
28d169de | 5695 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 5696 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
5697 | tdep->default_mask_address_p = 0; |
5698 | set_gdbarch_long_bit (gdbarch, 64); | |
5699 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5700 | set_gdbarch_long_long_bit (gdbarch, 64); | |
0dadbba0 | 5701 | break; |
c2d11a7d | 5702 | default: |
6d82d43b | 5703 | internal_error (__FILE__, __LINE__, "unknown ABI in switch"); |
c2d11a7d JM |
5704 | } |
5705 | ||
a5ea2558 AC |
5706 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
5707 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
5708 | comment: | |
5709 | ||
5710 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
5711 | flag in object files because to do so would make it impossible to | |
102182a9 | 5712 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 5713 | unnecessarily restrictive. |
361d1df0 | 5714 | |
a5ea2558 AC |
5715 | We could solve this problem by adding "-gp32" multilibs to gcc, |
5716 | but to set this flag before gcc is built with such multilibs will | |
5717 | break too many systems.'' | |
5718 | ||
5719 | But even more unhelpfully, the default linker output target for | |
5720 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
5721 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 5722 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
5723 | this flag to detect 32-bit mode would do the wrong thing given |
5724 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 5725 | as 32-bit programs by default. */ |
a5ea2558 | 5726 | |
6c997a34 | 5727 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 5728 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
bcb0cc15 | 5729 | set_gdbarch_read_sp (gdbarch, mips_read_sp); |
c2d11a7d | 5730 | |
102182a9 MS |
5731 | /* Add/remove bits from an address. The MIPS needs be careful to |
5732 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
5733 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
5734 | ||
58dfe9ff AC |
5735 | /* Unwind the frame. */ |
5736 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
edfae063 | 5737 | set_gdbarch_unwind_dummy_id (gdbarch, mips_unwind_dummy_id); |
10312cc4 | 5738 | |
102182a9 | 5739 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 5740 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
5741 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
5742 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
5743 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, | |
5744 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
5745 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, | |
5746 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 5747 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 5748 | |
c2d11a7d JM |
5749 | /* MIPS version of CALL_DUMMY */ |
5750 | ||
9710e734 AC |
5751 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
5752 | replaced by a command, and all targets will default to on stack | |
5753 | (regardless of the stack's execute status). */ | |
5754 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
dc604539 | 5755 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 5756 | |
87783b8b AC |
5757 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
5758 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
5759 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
5760 | ||
f7b9e9fc AC |
5761 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
5762 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
f7b9e9fc AC |
5763 | |
5764 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 5765 | |
fc0c74b1 AC |
5766 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
5767 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
5768 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 5769 | |
a4b8ebc8 | 5770 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 5771 | |
e11c53d2 | 5772 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 5773 | |
e5ab0dce AC |
5774 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); |
5775 | ||
3a3bc038 AC |
5776 | /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT, |
5777 | HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT | |
5778 | need to all be folded into the target vector. Since they are | |
5779 | being used as guards for STOPPED_BY_WATCHPOINT, why not have | |
5780 | STOPPED_BY_WATCHPOINT return the type of watchpoint that the code | |
5781 | is sitting on? */ | |
5782 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
5783 | ||
757a7cc6 MS |
5784 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_stub); |
5785 | ||
6de918a6 DJ |
5786 | /* NOTE drow/2004-02-11: We overload the core solib trampoline code |
5787 | to support MIPS16. This is a bad thing. Make sure not to do it | |
5788 | if we have an OS ABI that actually supports shared libraries, since | |
5789 | shared library support is more important. If we have an OS someday | |
5790 | that supports both shared libraries and MIPS16, we'll have to find | |
5791 | a better place for these. */ | |
5792 | if (info.osabi == GDB_OSABI_UNKNOWN) | |
5793 | { | |
5794 | set_gdbarch_in_solib_call_trampoline (gdbarch, mips_in_call_stub); | |
5795 | set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); | |
5796 | } | |
5797 | ||
5798 | /* Hook in OS ABI-specific overrides, if they have been registered. */ | |
5799 | gdbarch_init_osabi (info, gdbarch); | |
757a7cc6 | 5800 | |
5792a79b DJ |
5801 | /* Unwind the frame. */ |
5802 | frame_unwind_append_sniffer (gdbarch, mips_mdebug_frame_sniffer); | |
5803 | frame_base_append_sniffer (gdbarch, mips_mdebug_frame_base_sniffer); | |
5804 | ||
4b9b3959 AC |
5805 | return gdbarch; |
5806 | } | |
5807 | ||
2e4ebe70 | 5808 | static void |
6d82d43b | 5809 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
5810 | { |
5811 | struct gdbarch_info info; | |
5812 | ||
5813 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
5814 | mips_gdbarch_init will take care of the rest. */ | |
5815 | gdbarch_info_init (&info); | |
5816 | gdbarch_update_p (info); | |
5817 | } | |
5818 | ||
ad188201 KB |
5819 | /* Print out which MIPS ABI is in use. */ |
5820 | ||
5821 | static void | |
5822 | show_mips_abi (char *ignore_args, int from_tty) | |
5823 | { | |
5824 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips) | |
6d82d43b AC |
5825 | printf_filtered |
5826 | ("The MIPS ABI is unknown because the current architecture is not MIPS.\n"); | |
ad188201 KB |
5827 | else |
5828 | { | |
5829 | enum mips_abi global_abi = global_mips_abi (); | |
5830 | enum mips_abi actual_abi = mips_abi (current_gdbarch); | |
5831 | const char *actual_abi_str = mips_abi_strings[actual_abi]; | |
5832 | ||
5833 | if (global_abi == MIPS_ABI_UNKNOWN) | |
6d82d43b AC |
5834 | printf_filtered |
5835 | ("The MIPS ABI is set automatically (currently \"%s\").\n", | |
5836 | actual_abi_str); | |
ad188201 | 5837 | else if (global_abi == actual_abi) |
6d82d43b AC |
5838 | printf_filtered |
5839 | ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
5840 | actual_abi_str); | |
ad188201 KB |
5841 | else |
5842 | { | |
5843 | /* Probably shouldn't happen... */ | |
6d82d43b AC |
5844 | printf_filtered |
5845 | ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n", | |
5846 | actual_abi_str, mips_abi_strings[global_abi]); | |
ad188201 KB |
5847 | } |
5848 | } | |
5849 | } | |
5850 | ||
4b9b3959 AC |
5851 | static void |
5852 | mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
5853 | { | |
5854 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
5855 | if (tdep != NULL) | |
c2d11a7d | 5856 | { |
acdb74a0 AC |
5857 | int ef_mips_arch; |
5858 | int ef_mips_32bitmode; | |
5859 | /* determine the ISA */ | |
5860 | switch (tdep->elf_flags & EF_MIPS_ARCH) | |
5861 | { | |
5862 | case E_MIPS_ARCH_1: | |
5863 | ef_mips_arch = 1; | |
5864 | break; | |
5865 | case E_MIPS_ARCH_2: | |
5866 | ef_mips_arch = 2; | |
5867 | break; | |
5868 | case E_MIPS_ARCH_3: | |
5869 | ef_mips_arch = 3; | |
5870 | break; | |
5871 | case E_MIPS_ARCH_4: | |
93d56215 | 5872 | ef_mips_arch = 4; |
acdb74a0 AC |
5873 | break; |
5874 | default: | |
93d56215 | 5875 | ef_mips_arch = 0; |
acdb74a0 AC |
5876 | break; |
5877 | } | |
5878 | /* determine the size of a pointer */ | |
5879 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); | |
4b9b3959 AC |
5880 | fprintf_unfiltered (file, |
5881 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 5882 | tdep->elf_flags); |
4b9b3959 | 5883 | fprintf_unfiltered (file, |
acdb74a0 AC |
5884 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
5885 | ef_mips_32bitmode); | |
5886 | fprintf_unfiltered (file, | |
5887 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
5888 | ef_mips_arch); | |
5889 | fprintf_unfiltered (file, | |
5890 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 5891 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
5892 | fprintf_unfiltered (file, |
5893 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 5894 | mips_mask_address_p (tdep), |
4014092b | 5895 | tdep->default_mask_address_p); |
c2d11a7d | 5896 | } |
4b9b3959 AC |
5897 | fprintf_unfiltered (file, |
5898 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
5899 | MIPS_DEFAULT_FPU_TYPE, | |
5900 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
5901 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
5902 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
5903 | : "???")); | |
6d82d43b | 5904 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI); |
4b9b3959 AC |
5905 | fprintf_unfiltered (file, |
5906 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
5907 | MIPS_FPU_TYPE, | |
5908 | (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
5909 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
5910 | : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
5911 | : "???")); | |
4b9b3959 | 5912 | fprintf_unfiltered (file, |
480d3dd2 | 5913 | "mips_dump_tdep: mips_stack_argsize() = %d\n", |
13326b4e | 5914 | mips_stack_argsize (current_gdbarch)); |
6d82d43b | 5915 | fprintf_unfiltered (file, "mips_dump_tdep: A0_REGNUM = %d\n", A0_REGNUM); |
2475bac3 AC |
5916 | fprintf_unfiltered (file, |
5917 | "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n", | |
6d82d43b | 5918 | XSTRING (ADDR_BITS_REMOVE (ADDR))); |
2475bac3 AC |
5919 | fprintf_unfiltered (file, |
5920 | "mips_dump_tdep: ATTACH_DETACH # %s\n", | |
5921 | XSTRING (ATTACH_DETACH)); | |
2475bac3 AC |
5922 | fprintf_unfiltered (file, |
5923 | "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n", | |
5924 | XSTRING (DWARF_REG_TO_REGNUM (REGNUM))); | |
5925 | fprintf_unfiltered (file, | |
5926 | "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n", | |
5927 | XSTRING (ECOFF_REG_TO_REGNUM (REGNUM))); | |
2475bac3 AC |
5928 | fprintf_unfiltered (file, |
5929 | "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n", | |
5930 | FIRST_EMBED_REGNUM); | |
2475bac3 AC |
5931 | fprintf_unfiltered (file, |
5932 | "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n", | |
5933 | XSTRING (IGNORE_HELPER_CALL (PC))); | |
2475bac3 AC |
5934 | fprintf_unfiltered (file, |
5935 | "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n", | |
5936 | XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME))); | |
5937 | fprintf_unfiltered (file, | |
5938 | "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n", | |
5939 | XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME))); | |
2475bac3 AC |
5940 | fprintf_unfiltered (file, |
5941 | "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n", | |
5942 | LAST_EMBED_REGNUM); | |
2475bac3 AC |
5943 | #ifdef MACHINE_CPROC_FP_OFFSET |
5944 | fprintf_unfiltered (file, | |
5945 | "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n", | |
5946 | MACHINE_CPROC_FP_OFFSET); | |
5947 | #endif | |
5948 | #ifdef MACHINE_CPROC_PC_OFFSET | |
5949 | fprintf_unfiltered (file, | |
5950 | "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n", | |
5951 | MACHINE_CPROC_PC_OFFSET); | |
5952 | #endif | |
5953 | #ifdef MACHINE_CPROC_SP_OFFSET | |
5954 | fprintf_unfiltered (file, | |
5955 | "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n", | |
5956 | MACHINE_CPROC_SP_OFFSET); | |
5957 | #endif | |
2475bac3 AC |
5958 | fprintf_unfiltered (file, |
5959 | "mips_dump_tdep: MIPS16_INSTLEN = %d\n", | |
5960 | MIPS16_INSTLEN); | |
6d82d43b | 5961 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n"); |
2475bac3 AC |
5962 | fprintf_unfiltered (file, |
5963 | "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n"); | |
5964 | fprintf_unfiltered (file, | |
6d82d43b | 5965 | "mips_dump_tdep: MIPS_INSTLEN = %d\n", MIPS_INSTLEN); |
2475bac3 | 5966 | fprintf_unfiltered (file, |
acdb74a0 AC |
5967 | "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n", |
5968 | MIPS_LAST_ARG_REGNUM, | |
5969 | MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1); | |
2475bac3 | 5970 | fprintf_unfiltered (file, |
6d82d43b | 5971 | "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS); |
2475bac3 | 5972 | fprintf_unfiltered (file, |
1b13c4f6 | 5973 | "mips_dump_tdep: mips_abi_regsize() = %d\n", |
13326b4e | 5974 | mips_abi_regsize (current_gdbarch)); |
2475bac3 | 5975 | fprintf_unfiltered (file, |
6d82d43b | 5976 | "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM); |
2475bac3 AC |
5977 | fprintf_unfiltered (file, |
5978 | "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n"); | |
5979 | fprintf_unfiltered (file, | |
5980 | "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n"); | |
5981 | fprintf_unfiltered (file, | |
5982 | "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n"); | |
6d82d43b AC |
5983 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_FRAME_REG = function?\n"); |
5984 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_FREG_MASK = function?\n"); | |
5985 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n"); | |
5986 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n"); | |
5987 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_LOW_ADDR = function?\n"); | |
5988 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_PC_REG = function?\n"); | |
5989 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_REG_MASK = function?\n"); | |
5990 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_REG_OFFSET = function?\n"); | |
5991 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_SYMBOL = function?\n"); | |
5992 | fprintf_unfiltered (file, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM); | |
5993 | fprintf_unfiltered (file, "mips_dump_tdep: RA_REGNUM = %d\n", RA_REGNUM); | |
2475bac3 AC |
5994 | #ifdef SAVED_BYTES |
5995 | fprintf_unfiltered (file, | |
6d82d43b | 5996 | "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES); |
2475bac3 AC |
5997 | #endif |
5998 | #ifdef SAVED_FP | |
6d82d43b | 5999 | fprintf_unfiltered (file, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP); |
2475bac3 AC |
6000 | #endif |
6001 | #ifdef SAVED_PC | |
6d82d43b | 6002 | fprintf_unfiltered (file, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC); |
2475bac3 AC |
6003 | #endif |
6004 | fprintf_unfiltered (file, | |
6005 | "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n", | |
6006 | XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS))); | |
6007 | fprintf_unfiltered (file, | |
6008 | "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n"); | |
2475bac3 AC |
6009 | fprintf_unfiltered (file, |
6010 | "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n", | |
6011 | XSTRING (SKIP_TRAMPOLINE_CODE (PC))); | |
6012 | fprintf_unfiltered (file, | |
6013 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n", | |
6014 | XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P))); | |
6015 | fprintf_unfiltered (file, | |
b0ed3589 AC |
6016 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n", |
6017 | SOFTWARE_SINGLE_STEP_P ()); | |
2475bac3 AC |
6018 | fprintf_unfiltered (file, |
6019 | "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n", | |
6020 | XSTRING (STAB_REG_TO_REGNUM (REGNUM))); | |
6021 | #ifdef STACK_END_ADDR | |
6022 | fprintf_unfiltered (file, | |
6023 | "mips_dump_tdep: STACK_END_ADDR = %d\n", | |
6024 | STACK_END_ADDR); | |
6025 | #endif | |
6026 | fprintf_unfiltered (file, | |
6027 | "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n", | |
6028 | XSTRING (STEP_SKIPS_DELAY (PC))); | |
6029 | fprintf_unfiltered (file, | |
6030 | "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n", | |
6031 | STEP_SKIPS_DELAY_P); | |
6032 | fprintf_unfiltered (file, | |
6033 | "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n", | |
6034 | XSTRING (STOPPED_BY_WATCHPOINT (WS))); | |
6d82d43b | 6035 | fprintf_unfiltered (file, "mips_dump_tdep: T9_REGNUM = %d\n", T9_REGNUM); |
2475bac3 AC |
6036 | fprintf_unfiltered (file, |
6037 | "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n"); | |
6038 | fprintf_unfiltered (file, | |
6039 | "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n", | |
6d82d43b AC |
6040 | XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT |
6041 | (TYPE, CNT, OTHERTYPE))); | |
2475bac3 AC |
6042 | fprintf_unfiltered (file, |
6043 | "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n", | |
6044 | XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS)); | |
2475bac3 AC |
6045 | #ifdef TRACE_CLEAR |
6046 | fprintf_unfiltered (file, | |
6047 | "mips_dump_tdep: TRACE_CLEAR # %s\n", | |
6048 | XSTRING (TRACE_CLEAR (THREAD, STATE))); | |
6049 | #endif | |
6050 | #ifdef TRACE_FLAVOR | |
6051 | fprintf_unfiltered (file, | |
6d82d43b | 6052 | "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR); |
2475bac3 AC |
6053 | #endif |
6054 | #ifdef TRACE_FLAVOR_SIZE | |
6055 | fprintf_unfiltered (file, | |
6056 | "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n", | |
6057 | TRACE_FLAVOR_SIZE); | |
6058 | #endif | |
6059 | #ifdef TRACE_SET | |
6060 | fprintf_unfiltered (file, | |
6061 | "mips_dump_tdep: TRACE_SET # %s\n", | |
6d82d43b | 6062 | XSTRING (TRACE_SET (X, STATE))); |
2475bac3 | 6063 | #endif |
2475bac3 AC |
6064 | #ifdef UNUSED_REGNUM |
6065 | fprintf_unfiltered (file, | |
6d82d43b | 6066 | "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM); |
2475bac3 | 6067 | #endif |
6d82d43b | 6068 | fprintf_unfiltered (file, "mips_dump_tdep: V0_REGNUM = %d\n", V0_REGNUM); |
2475bac3 AC |
6069 | fprintf_unfiltered (file, |
6070 | "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n", | |
6071 | (long) VM_MIN_ADDRESS); | |
2475bac3 | 6072 | fprintf_unfiltered (file, |
6d82d43b | 6073 | "mips_dump_tdep: ZERO_REGNUM = %d\n", ZERO_REGNUM); |
2475bac3 | 6074 | fprintf_unfiltered (file, |
6d82d43b | 6075 | "mips_dump_tdep: _PROC_MAGIC_ = %d\n", _PROC_MAGIC_); |
c2d11a7d JM |
6076 | } |
6077 | ||
6d82d43b | 6078 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 6079 | |
c906108c | 6080 | void |
acdb74a0 | 6081 | _initialize_mips_tdep (void) |
c906108c SS |
6082 | { |
6083 | static struct cmd_list_element *mipsfpulist = NULL; | |
6084 | struct cmd_list_element *c; | |
6085 | ||
6d82d43b | 6086 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
6087 | if (MIPS_ABI_LAST + 1 |
6088 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
6089 | internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync"); | |
6090 | ||
4b9b3959 | 6091 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 6092 | |
8d5f9dcb DJ |
6093 | mips_pdr_data = register_objfile_data (); |
6094 | ||
a5ea2558 AC |
6095 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
6096 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
6097 | "Various MIPS specific commands.", | |
6098 | &setmipscmdlist, "set mips ", 0, &setlist); | |
6099 | ||
6100 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
6101 | "Various MIPS specific commands.", | |
6102 | &showmipscmdlist, "show mips ", 0, &showlist); | |
6103 | ||
6104 | /* Allow the user to override the saved register size. */ | |
6105 | add_show_from_set (add_set_enum_cmd ("saved-gpreg-size", | |
1ed2a135 AC |
6106 | class_obscure, |
6107 | size_enums, | |
1b13c4f6 | 6108 | &mips_abi_regsize_string, "\ |
a5ea2558 AC |
6109 | Set size of general purpose registers saved on the stack.\n\ |
6110 | This option can be set to one of:\n\ | |
6111 | 32 - Force GDB to treat saved GP registers as 32-bit\n\ | |
6112 | 64 - Force GDB to treat saved GP registers as 64-bit\n\ | |
6113 | auto - Allow GDB to use the target's default setting or autodetect the\n\ | |
6114 | saved GP register size from information contained in the executable.\n\ | |
6d82d43b | 6115 | (default: auto)", &setmipscmdlist), &showmipscmdlist); |
a5ea2558 | 6116 | |
d929b26f AC |
6117 | /* Allow the user to override the argument stack size. */ |
6118 | add_show_from_set (add_set_enum_cmd ("stack-arg-size", | |
6119 | class_obscure, | |
6120 | size_enums, | |
1ed2a135 | 6121 | &mips_stack_argsize_string, "\ |
d929b26f AC |
6122 | Set the amount of stack space reserved for each argument.\n\ |
6123 | This option can be set to one of:\n\ | |
6124 | 32 - Force GDB to allocate 32-bit chunks per argument\n\ | |
6125 | 64 - Force GDB to allocate 64-bit chunks per argument\n\ | |
6126 | auto - Allow GDB to determine the correct setting from the current\n\ | |
6d82d43b | 6127 | target and executable (default)", &setmipscmdlist), &showmipscmdlist); |
d929b26f | 6128 | |
2e4ebe70 DJ |
6129 | /* Allow the user to override the ABI. */ |
6130 | c = add_set_enum_cmd | |
6131 | ("abi", class_obscure, mips_abi_strings, &mips_abi_string, | |
6132 | "Set the ABI used by this program.\n" | |
6133 | "This option can be set to one of:\n" | |
6134 | " auto - the default ABI associated with the current binary\n" | |
6135 | " o32\n" | |
6d82d43b | 6136 | " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist); |
2e4ebe70 | 6137 | set_cmd_sfunc (c, mips_abi_update); |
ad188201 | 6138 | add_cmd ("abi", class_obscure, show_mips_abi, |
6d82d43b | 6139 | "Show ABI in use by MIPS target", &showmipscmdlist); |
2e4ebe70 | 6140 | |
c906108c SS |
6141 | /* Let the user turn off floating point and set the fence post for |
6142 | heuristic_proc_start. */ | |
6143 | ||
6144 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
6145 | "Set use of MIPS floating-point coprocessor.", | |
6146 | &mipsfpulist, "set mipsfpu ", 0, &setlist); | |
6147 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
6148 | "Select single-precision MIPS floating-point coprocessor.", | |
6149 | &mipsfpulist); | |
6150 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
8e1a459b | 6151 | "Select double-precision MIPS floating-point coprocessor.", |
c906108c SS |
6152 | &mipsfpulist); |
6153 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
6154 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
6155 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
6156 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
6d82d43b | 6157 | "Select no MIPS floating-point coprocessor.", &mipsfpulist); |
c906108c SS |
6158 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
6159 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
6160 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
6161 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
6162 | "Select MIPS floating-point coprocessor automatically.", | |
6163 | &mipsfpulist); | |
6164 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
6165 | "Show current use of MIPS floating-point coprocessor target.", | |
6166 | &showlist); | |
6167 | ||
c906108c SS |
6168 | /* We really would like to have both "0" and "unlimited" work, but |
6169 | command.c doesn't deal with that. So make it a var_zinteger | |
6170 | because the user can always use "999999" or some such for unlimited. */ | |
6171 | c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger, | |
6d82d43b | 6172 | (char *) &heuristic_fence_post, "\ |
c906108c SS |
6173 | Set the distance searched for the start of a function.\n\ |
6174 | If you are debugging a stripped executable, GDB needs to search through the\n\ | |
6175 | program for the start of a function. This command sets the distance of the\n\ | |
6d82d43b | 6176 | search. The only need to set it is when debugging a stripped executable.", &setlist); |
c906108c SS |
6177 | /* We need to throw away the frame cache when we set this, since it |
6178 | might change our ability to get backtraces. */ | |
9f60d481 | 6179 | set_cmd_sfunc (c, reinit_frame_cache_sfunc); |
c906108c SS |
6180 | add_show_from_set (c, &showlist); |
6181 | ||
6182 | /* Allow the user to control whether the upper bits of 64-bit | |
6183 | addresses should be zeroed. */ | |
e9e68a56 AC |
6184 | add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, "\ |
6185 | Set zeroing of upper 32 bits of 64-bit addresses.\n\ | |
6186 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ | |
6187 | allow GDB to determine the correct value.\n", "\ | |
6188 | Show zeroing of upper 32 bits of 64-bit addresses.", | |
6d82d43b | 6189 | NULL, show_mask_address, &setmipscmdlist, &showmipscmdlist); |
43e526b9 JM |
6190 | |
6191 | /* Allow the user to control the size of 32 bit registers within the | |
6192 | raw remote packet. */ | |
719ec221 AC |
6193 | add_setshow_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
6194 | var_boolean, &mips64_transfers_32bit_regs_p, "\ | |
6195 | Set compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\ | |
6196 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ | |
6197 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
6d82d43b | 6198 | 64 bits for others. Use \"off\" to disable compatibility mode", "\ |
719ec221 | 6199 | Show compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\ |
43e526b9 JM |
6200 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
6201 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
6d82d43b | 6202 | 64 bits for others. Use \"off\" to disable compatibility mode", set_mips64_transfers_32bit_regs, NULL, &setlist, &showlist); |
9ace0497 AC |
6203 | |
6204 | /* Debug this files internals. */ | |
6205 | add_show_from_set (add_set_cmd ("mips", class_maintenance, var_zinteger, | |
6206 | &mips_debug, "Set mips debugging.\n\ | |
6d82d43b | 6207 | When non-zero, mips specific debugging is enabled.", &setdebuglist), &showdebuglist); |
c906108c | 6208 | } |