Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
cda5a58a AC |
3 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, |
4 | 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. | |
bf64bfd6 | 5 | |
c906108c SS |
6 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
7 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
8 | ||
c5aa993b | 9 | This file is part of GDB. |
c906108c | 10 | |
c5aa993b JM |
11 | This program is free software; you can redistribute it and/or modify |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2 of the License, or | |
14 | (at your option) any later version. | |
c906108c | 15 | |
c5aa993b JM |
16 | This program is distributed in the hope that it will be useful, |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
c906108c | 20 | |
c5aa993b JM |
21 | You should have received a copy of the GNU General Public License |
22 | along with this program; if not, write to the Free Software | |
23 | Foundation, Inc., 59 Temple Place - Suite 330, | |
24 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
25 | |
26 | #include "defs.h" | |
27 | #include "gdb_string.h" | |
28 | #include "frame.h" | |
29 | #include "inferior.h" | |
30 | #include "symtab.h" | |
31 | #include "value.h" | |
32 | #include "gdbcmd.h" | |
33 | #include "language.h" | |
34 | #include "gdbcore.h" | |
35 | #include "symfile.h" | |
36 | #include "objfiles.h" | |
37 | #include "gdbtypes.h" | |
38 | #include "target.h" | |
28d069e6 | 39 | #include "arch-utils.h" |
4e052eda | 40 | #include "regcache.h" |
70f80edf | 41 | #include "osabi.h" |
c906108c SS |
42 | |
43 | #include "opcode/mips.h" | |
c2d11a7d JM |
44 | #include "elf/mips.h" |
45 | #include "elf-bfd.h" | |
2475bac3 | 46 | #include "symcat.h" |
c906108c | 47 | |
dd824b04 DJ |
48 | /* A useful bit in the CP0 status register (PS_REGNUM). */ |
49 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ | |
50 | #define ST0_FR (1 << 26) | |
51 | ||
b0069a17 AC |
52 | /* The sizes of floating point registers. */ |
53 | ||
54 | enum | |
55 | { | |
56 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
57 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
58 | }; | |
59 | ||
0dadbba0 AC |
60 | /* All the possible MIPS ABIs. */ |
61 | ||
62 | enum mips_abi | |
63 | { | |
2e4ebe70 | 64 | MIPS_ABI_UNKNOWN = 0, |
0dadbba0 AC |
65 | MIPS_ABI_N32, |
66 | MIPS_ABI_O32, | |
28d169de | 67 | MIPS_ABI_N64, |
0dadbba0 AC |
68 | MIPS_ABI_O64, |
69 | MIPS_ABI_EABI32, | |
2e4ebe70 DJ |
70 | MIPS_ABI_EABI64, |
71 | MIPS_ABI_LAST | |
0dadbba0 AC |
72 | }; |
73 | ||
2e4ebe70 DJ |
74 | static const char *mips_abi_string; |
75 | ||
76 | static const char *mips_abi_strings[] = { | |
77 | "auto", | |
78 | "n32", | |
79 | "o32", | |
28d169de | 80 | "n64", |
2e4ebe70 DJ |
81 | "o64", |
82 | "eabi32", | |
83 | "eabi64", | |
84 | NULL | |
85 | }; | |
86 | ||
cce74817 | 87 | struct frame_extra_info |
c5aa993b JM |
88 | { |
89 | mips_extra_func_info_t proc_desc; | |
90 | int num_args; | |
91 | }; | |
cce74817 | 92 | |
d929b26f AC |
93 | /* Various MIPS ISA options (related to stack analysis) can be |
94 | overridden dynamically. Establish an enum/array for managing | |
95 | them. */ | |
96 | ||
53904c9e AC |
97 | static const char size_auto[] = "auto"; |
98 | static const char size_32[] = "32"; | |
99 | static const char size_64[] = "64"; | |
d929b26f | 100 | |
53904c9e | 101 | static const char *size_enums[] = { |
d929b26f AC |
102 | size_auto, |
103 | size_32, | |
104 | size_64, | |
a5ea2558 AC |
105 | 0 |
106 | }; | |
107 | ||
7a292a7a SS |
108 | /* Some MIPS boards don't support floating point while others only |
109 | support single-precision floating-point operations. See also | |
110 | FP_REGISTER_DOUBLE. */ | |
c906108c SS |
111 | |
112 | enum mips_fpu_type | |
c5aa993b JM |
113 | { |
114 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
115 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
116 | MIPS_FPU_NONE /* No floating point. */ | |
117 | }; | |
c906108c SS |
118 | |
119 | #ifndef MIPS_DEFAULT_FPU_TYPE | |
120 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
121 | #endif | |
122 | static int mips_fpu_type_auto = 1; | |
123 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 124 | |
9ace0497 | 125 | static int mips_debug = 0; |
7a292a7a | 126 | |
c2d11a7d JM |
127 | /* MIPS specific per-architecture information */ |
128 | struct gdbarch_tdep | |
129 | { | |
130 | /* from the elf header */ | |
131 | int elf_flags; | |
70f80edf | 132 | |
c2d11a7d | 133 | /* mips options */ |
0dadbba0 | 134 | enum mips_abi mips_abi; |
2e4ebe70 | 135 | enum mips_abi found_abi; |
c2d11a7d JM |
136 | enum mips_fpu_type mips_fpu_type; |
137 | int mips_last_arg_regnum; | |
138 | int mips_last_fp_arg_regnum; | |
a5ea2558 | 139 | int mips_default_saved_regsize; |
c2d11a7d | 140 | int mips_fp_register_double; |
d929b26f | 141 | int mips_default_stack_argsize; |
5213ab06 | 142 | int gdb_target_is_mips64; |
4014092b | 143 | int default_mask_address_p; |
70f80edf JT |
144 | |
145 | enum gdb_osabi osabi; | |
c2d11a7d JM |
146 | }; |
147 | ||
0dadbba0 | 148 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \ |
216a600b | 149 | || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64) |
c2d11a7d | 150 | |
c2d11a7d | 151 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 152 | |
c2d11a7d | 153 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 154 | |
c2d11a7d | 155 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) |
c2d11a7d | 156 | |
d929b26f AC |
157 | /* Return the currently configured (or set) saved register size. */ |
158 | ||
a5ea2558 | 159 | #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize) |
c2d11a7d | 160 | |
53904c9e | 161 | static const char *mips_saved_regsize_string = size_auto; |
d929b26f AC |
162 | |
163 | #define MIPS_SAVED_REGSIZE (mips_saved_regsize()) | |
164 | ||
165 | static unsigned int | |
acdb74a0 | 166 | mips_saved_regsize (void) |
d929b26f AC |
167 | { |
168 | if (mips_saved_regsize_string == size_auto) | |
169 | return MIPS_DEFAULT_SAVED_REGSIZE; | |
170 | else if (mips_saved_regsize_string == size_64) | |
171 | return 8; | |
172 | else /* if (mips_saved_regsize_string == size_32) */ | |
173 | return 4; | |
174 | } | |
175 | ||
71b8ef93 | 176 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa MS |
177 | marks it as 16-bit function. The MSB of the minimal symbol's |
178 | "info" field is used for this purpose. This field is already | |
179 | being used to store the symbol size, so the assumption is | |
180 | that the symbol size cannot exceed 2^31. | |
181 | ||
182 | ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special", | |
183 | i.e. refers to a 16-bit function, and sets a "special" bit in a | |
184 | minimal symbol to mark it as a 16-bit function | |
185 | ||
186 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol | |
187 | MSYMBOL_SIZE returns the size of the minimal symbol, i.e. | |
188 | the "info" field with the "special" bit masked out */ | |
189 | ||
5a89d8aa MS |
190 | static void |
191 | mips_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym) | |
192 | { | |
193 | if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_MIPS16) | |
194 | { | |
195 | MSYMBOL_INFO (msym) = (char *) | |
196 | (((long) MSYMBOL_INFO (msym)) | 0x80000000); | |
197 | SYMBOL_VALUE_ADDRESS (msym) |= 1; | |
198 | } | |
199 | } | |
200 | ||
71b8ef93 MS |
201 | static int |
202 | msymbol_is_special (struct minimal_symbol *msym) | |
203 | { | |
204 | return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0); | |
205 | } | |
206 | ||
207 | static long | |
208 | msymbol_size (struct minimal_symbol *msym) | |
209 | { | |
210 | return ((long) MSYMBOL_INFO (msym) & 0x7fffffff); | |
211 | } | |
212 | ||
88658117 AC |
213 | /* XFER a value from the big/little/left end of the register. |
214 | Depending on the size of the value it might occupy the entire | |
215 | register or just part of it. Make an allowance for this, aligning | |
216 | things accordingly. */ | |
217 | ||
218 | static void | |
219 | mips_xfer_register (struct regcache *regcache, int reg_num, int length, | |
220 | enum bfd_endian endian, bfd_byte *in, const bfd_byte *out, | |
221 | int buf_offset) | |
222 | { | |
223 | bfd_byte *reg = alloca (MAX_REGISTER_RAW_SIZE); | |
224 | int reg_offset = 0; | |
cb1d2653 AC |
225 | /* Need to transfer the left or right part of the register, based on |
226 | the targets byte order. */ | |
88658117 AC |
227 | switch (endian) |
228 | { | |
229 | case BFD_ENDIAN_BIG: | |
230 | reg_offset = REGISTER_RAW_SIZE (reg_num) - length; | |
231 | break; | |
232 | case BFD_ENDIAN_LITTLE: | |
233 | reg_offset = 0; | |
234 | break; | |
235 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ | |
236 | reg_offset = 0; | |
237 | break; | |
238 | default: | |
239 | internal_error (__FILE__, __LINE__, "bad switch"); | |
240 | } | |
241 | if (mips_debug) | |
cb1d2653 AC |
242 | fprintf_unfiltered (gdb_stderr, |
243 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
244 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
245 | if (mips_debug && out != NULL) |
246 | { | |
247 | int i; | |
cb1d2653 | 248 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 249 | for (i = 0; i < length; i++) |
cb1d2653 | 250 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
251 | } |
252 | if (in != NULL) | |
253 | regcache_raw_read_part (regcache, reg_num, reg_offset, length, in + buf_offset); | |
254 | if (out != NULL) | |
255 | regcache_raw_write_part (regcache, reg_num, reg_offset, length, out + buf_offset); | |
256 | if (mips_debug && in != NULL) | |
257 | { | |
258 | int i; | |
cb1d2653 | 259 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 260 | for (i = 0; i < length; i++) |
cb1d2653 | 261 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
262 | } |
263 | if (mips_debug) | |
264 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
265 | } | |
266 | ||
dd824b04 DJ |
267 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
268 | compatiblity mode. A return value of 1 means that we have | |
269 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
270 | ||
271 | static int | |
272 | mips2_fp_compat (void) | |
273 | { | |
274 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not | |
275 | meaningful. */ | |
276 | if (REGISTER_RAW_SIZE (FP0_REGNUM) == 4) | |
277 | return 0; | |
278 | ||
279 | #if 0 | |
280 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
281 | in all the places we deal with FP registers. PR gdb/413. */ | |
282 | /* Otherwise check the FR bit in the status register - it controls | |
283 | the FP compatiblity mode. If it is clear we are in compatibility | |
284 | mode. */ | |
285 | if ((read_register (PS_REGNUM) & ST0_FR) == 0) | |
286 | return 1; | |
287 | #endif | |
361d1df0 | 288 | |
dd824b04 DJ |
289 | return 0; |
290 | } | |
291 | ||
c2d11a7d JM |
292 | /* Indicate that the ABI makes use of double-precision registers |
293 | provided by the FPU (rather than combining pairs of registers to | |
294 | form double-precision values). Do not use "TARGET_IS_MIPS64" to | |
295 | determine if the ABI is using double-precision registers. See also | |
296 | MIPS_FPU_TYPE. */ | |
c2d11a7d | 297 | #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double) |
c2d11a7d | 298 | |
d929b26f AC |
299 | /* The amount of space reserved on the stack for registers. This is |
300 | different to MIPS_SAVED_REGSIZE as it determines the alignment of | |
301 | data allocated after the registers have run out. */ | |
302 | ||
0dadbba0 | 303 | #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize) |
d929b26f AC |
304 | |
305 | #define MIPS_STACK_ARGSIZE (mips_stack_argsize ()) | |
306 | ||
53904c9e | 307 | static const char *mips_stack_argsize_string = size_auto; |
d929b26f AC |
308 | |
309 | static unsigned int | |
310 | mips_stack_argsize (void) | |
311 | { | |
312 | if (mips_stack_argsize_string == size_auto) | |
313 | return MIPS_DEFAULT_STACK_ARGSIZE; | |
314 | else if (mips_stack_argsize_string == size_64) | |
315 | return 8; | |
316 | else /* if (mips_stack_argsize_string == size_32) */ | |
317 | return 4; | |
318 | } | |
319 | ||
5213ab06 | 320 | #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0) |
c2d11a7d | 321 | |
92e1c15c | 322 | #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p) |
92e1c15c | 323 | |
7a292a7a | 324 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 325 | |
a14ed312 | 326 | int gdb_print_insn_mips (bfd_vma, disassemble_info *); |
c906108c | 327 | |
a14ed312 | 328 | static void mips_print_register (int, int); |
c906108c SS |
329 | |
330 | static mips_extra_func_info_t | |
479412cd | 331 | heuristic_proc_desc (CORE_ADDR, CORE_ADDR, struct frame_info *, int); |
c906108c | 332 | |
a14ed312 | 333 | static CORE_ADDR heuristic_proc_start (CORE_ADDR); |
c906108c | 334 | |
a14ed312 | 335 | static CORE_ADDR read_next_frame_reg (struct frame_info *, int); |
c906108c | 336 | |
5a89d8aa | 337 | static int mips_set_processor_type (char *); |
c906108c | 338 | |
a14ed312 | 339 | static void mips_show_processor_type_command (char *, int); |
c906108c | 340 | |
a14ed312 | 341 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c SS |
342 | |
343 | static mips_extra_func_info_t | |
479412cd | 344 | find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame); |
c906108c | 345 | |
a14ed312 KB |
346 | static CORE_ADDR after_prologue (CORE_ADDR pc, |
347 | mips_extra_func_info_t proc_desc); | |
c906108c | 348 | |
dd824b04 DJ |
349 | static void mips_read_fp_register_single (int regno, char *rare_buffer); |
350 | static void mips_read_fp_register_double (int regno, char *rare_buffer); | |
351 | ||
67b2c998 DJ |
352 | static struct type *mips_float_register_type (void); |
353 | static struct type *mips_double_register_type (void); | |
354 | ||
c906108c SS |
355 | /* This value is the model of MIPS in use. It is derived from the value |
356 | of the PrID register. */ | |
357 | ||
358 | char *mips_processor_type; | |
359 | ||
360 | char *tmp_mips_processor_type; | |
361 | ||
acdb74a0 AC |
362 | /* The list of available "set mips " and "show mips " commands */ |
363 | ||
364 | static struct cmd_list_element *setmipscmdlist = NULL; | |
365 | static struct cmd_list_element *showmipscmdlist = NULL; | |
366 | ||
c906108c SS |
367 | /* A set of original names, to be used when restoring back to generic |
368 | registers from a specific set. */ | |
369 | ||
cce74817 JM |
370 | char *mips_generic_reg_names[] = MIPS_REGISTER_NAMES; |
371 | char **mips_processor_reg_names = mips_generic_reg_names; | |
372 | ||
5a89d8aa | 373 | static const char * |
fba45db2 | 374 | mips_register_name (int i) |
cce74817 JM |
375 | { |
376 | return mips_processor_reg_names[i]; | |
377 | } | |
9846de1b | 378 | /* *INDENT-OFF* */ |
c906108c SS |
379 | /* Names of IDT R3041 registers. */ |
380 | ||
381 | char *mips_r3041_reg_names[] = { | |
382 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
383 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
384 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
385 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
386 | "sr", "lo", "hi", "bad", "cause","pc", | |
387 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
388 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
389 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
390 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
391 | "fsr", "fir", "fp", "", | |
392 | "", "", "bus", "ccfg", "", "", "", "", | |
393 | "", "", "port", "cmp", "", "", "epc", "prid", | |
394 | }; | |
395 | ||
396 | /* Names of IDT R3051 registers. */ | |
397 | ||
398 | char *mips_r3051_reg_names[] = { | |
399 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
400 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
401 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
402 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
403 | "sr", "lo", "hi", "bad", "cause","pc", | |
404 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
405 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
406 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
407 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
408 | "fsr", "fir", "fp", "", | |
409 | "inx", "rand", "elo", "", "ctxt", "", "", "", | |
410 | "", "", "ehi", "", "", "", "epc", "prid", | |
411 | }; | |
412 | ||
413 | /* Names of IDT R3081 registers. */ | |
414 | ||
415 | char *mips_r3081_reg_names[] = { | |
416 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
417 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
418 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
419 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
420 | "sr", "lo", "hi", "bad", "cause","pc", | |
421 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
422 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
423 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
424 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
425 | "fsr", "fir", "fp", "", | |
426 | "inx", "rand", "elo", "cfg", "ctxt", "", "", "", | |
427 | "", "", "ehi", "", "", "", "epc", "prid", | |
428 | }; | |
429 | ||
430 | /* Names of LSI 33k registers. */ | |
431 | ||
432 | char *mips_lsi33k_reg_names[] = { | |
433 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
434 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
435 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
436 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
437 | "epc", "hi", "lo", "sr", "cause","badvaddr", | |
438 | "dcic", "bpc", "bda", "", "", "", "", "", | |
439 | "", "", "", "", "", "", "", "", | |
440 | "", "", "", "", "", "", "", "", | |
441 | "", "", "", "", "", "", "", "", | |
442 | "", "", "", "", | |
443 | "", "", "", "", "", "", "", "", | |
444 | "", "", "", "", "", "", "", "", | |
445 | }; | |
446 | ||
447 | struct { | |
448 | char *name; | |
449 | char **regnames; | |
450 | } mips_processor_type_table[] = { | |
451 | { "generic", mips_generic_reg_names }, | |
452 | { "r3041", mips_r3041_reg_names }, | |
453 | { "r3051", mips_r3051_reg_names }, | |
454 | { "r3071", mips_r3081_reg_names }, | |
455 | { "r3081", mips_r3081_reg_names }, | |
456 | { "lsi33k", mips_lsi33k_reg_names }, | |
457 | { NULL, NULL } | |
458 | }; | |
9846de1b | 459 | /* *INDENT-ON* */ |
c906108c | 460 | |
c5aa993b JM |
461 | |
462 | ||
463 | ||
c906108c | 464 | /* Table to translate MIPS16 register field to actual register number. */ |
c5aa993b JM |
465 | static int mips16_to_32_reg[8] = |
466 | {16, 17, 2, 3, 4, 5, 6, 7}; | |
c906108c SS |
467 | |
468 | /* Heuristic_proc_start may hunt through the text section for a long | |
469 | time across a 2400 baud serial line. Allows the user to limit this | |
470 | search. */ | |
471 | ||
472 | static unsigned int heuristic_fence_post = 0; | |
473 | ||
c5aa993b JM |
474 | #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ |
475 | #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */ | |
c906108c SS |
476 | #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) |
477 | #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) | |
478 | #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust) | |
479 | #define PROC_REG_MASK(proc) ((proc)->pdr.regmask) | |
480 | #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) | |
481 | #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) | |
482 | #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) | |
483 | #define PROC_PC_REG(proc) ((proc)->pdr.pcreg) | |
6c0d6680 DJ |
484 | /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long, |
485 | this will corrupt pdr.iline. Fortunately we don't use it. */ | |
c906108c SS |
486 | #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) |
487 | #define _PROC_MAGIC_ 0x0F0F0F0F | |
488 | #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_) | |
489 | #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_) | |
490 | ||
491 | struct linked_proc_info | |
c5aa993b JM |
492 | { |
493 | struct mips_extra_func_info info; | |
494 | struct linked_proc_info *next; | |
495 | } | |
496 | *linked_proc_desc_table = NULL; | |
c906108c | 497 | |
cce74817 | 498 | void |
acdb74a0 | 499 | mips_print_extra_frame_info (struct frame_info *fi) |
cce74817 JM |
500 | { |
501 | if (fi | |
502 | && fi->extra_info | |
503 | && fi->extra_info->proc_desc | |
504 | && fi->extra_info->proc_desc->pdr.framereg < NUM_REGS) | |
d4f3574e | 505 | printf_filtered (" frame pointer is at %s+%s\n", |
cce74817 | 506 | REGISTER_NAME (fi->extra_info->proc_desc->pdr.framereg), |
d4f3574e | 507 | paddr_d (fi->extra_info->proc_desc->pdr.frameoffset)); |
cce74817 | 508 | } |
c906108c | 509 | |
46cd78fb AC |
510 | /* Number of bytes of storage in the actual machine representation for |
511 | register N. NOTE: This indirectly defines the register size | |
512 | transfered by the GDB protocol. */ | |
43e526b9 JM |
513 | |
514 | static int mips64_transfers_32bit_regs_p = 0; | |
515 | ||
f7ab6ec6 | 516 | static int |
acdb74a0 | 517 | mips_register_raw_size (int reg_nr) |
43e526b9 JM |
518 | { |
519 | if (mips64_transfers_32bit_regs_p) | |
520 | return REGISTER_VIRTUAL_SIZE (reg_nr); | |
d02ee681 AC |
521 | else if (reg_nr >= FP0_REGNUM && reg_nr < FP0_REGNUM + 32 |
522 | && FP_REGISTER_DOUBLE) | |
523 | /* For MIPS_ABI_N32 (for example) we need 8 byte floating point | |
524 | registers. */ | |
525 | return 8; | |
43e526b9 JM |
526 | else |
527 | return MIPS_REGSIZE; | |
528 | } | |
529 | ||
46cd78fb AC |
530 | /* Convert between RAW and VIRTUAL registers. The RAW register size |
531 | defines the remote-gdb packet. */ | |
532 | ||
d05285fa | 533 | static int |
acdb74a0 | 534 | mips_register_convertible (int reg_nr) |
43e526b9 JM |
535 | { |
536 | if (mips64_transfers_32bit_regs_p) | |
537 | return 0; | |
538 | else | |
539 | return (REGISTER_RAW_SIZE (reg_nr) > REGISTER_VIRTUAL_SIZE (reg_nr)); | |
540 | } | |
541 | ||
d05285fa | 542 | static void |
acdb74a0 AC |
543 | mips_register_convert_to_virtual (int n, struct type *virtual_type, |
544 | char *raw_buf, char *virt_buf) | |
43e526b9 | 545 | { |
d7449b42 | 546 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
43e526b9 JM |
547 | memcpy (virt_buf, |
548 | raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)), | |
549 | TYPE_LENGTH (virtual_type)); | |
550 | else | |
551 | memcpy (virt_buf, | |
552 | raw_buf, | |
553 | TYPE_LENGTH (virtual_type)); | |
554 | } | |
555 | ||
d05285fa | 556 | static void |
acdb74a0 AC |
557 | mips_register_convert_to_raw (struct type *virtual_type, int n, |
558 | char *virt_buf, char *raw_buf) | |
43e526b9 JM |
559 | { |
560 | memset (raw_buf, 0, REGISTER_RAW_SIZE (n)); | |
d7449b42 | 561 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
43e526b9 JM |
562 | memcpy (raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)), |
563 | virt_buf, | |
564 | TYPE_LENGTH (virtual_type)); | |
565 | else | |
566 | memcpy (raw_buf, | |
567 | virt_buf, | |
568 | TYPE_LENGTH (virtual_type)); | |
569 | } | |
570 | ||
102182a9 MS |
571 | void |
572 | mips_register_convert_to_type (int regnum, struct type *type, char *buffer) | |
573 | { | |
574 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
575 | && REGISTER_RAW_SIZE (regnum) == 4 | |
576 | && (regnum) >= FP0_REGNUM && (regnum) < FP0_REGNUM + 32 | |
577 | && TYPE_CODE(type) == TYPE_CODE_FLT | |
578 | && TYPE_LENGTH(type) == 8) | |
579 | { | |
580 | char temp[4]; | |
581 | memcpy (temp, ((char *)(buffer))+4, 4); | |
582 | memcpy (((char *)(buffer))+4, (buffer), 4); | |
583 | memcpy (((char *)(buffer)), temp, 4); | |
584 | } | |
585 | } | |
586 | ||
587 | void | |
588 | mips_register_convert_from_type (int regnum, struct type *type, char *buffer) | |
589 | { | |
590 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
591 | && REGISTER_RAW_SIZE (regnum) == 4 | |
592 | && (regnum) >= FP0_REGNUM && (regnum) < FP0_REGNUM + 32 | |
593 | && TYPE_CODE(type) == TYPE_CODE_FLT | |
594 | && TYPE_LENGTH(type) == 8) | |
595 | { | |
596 | char temp[4]; | |
597 | memcpy (temp, ((char *)(buffer))+4, 4); | |
598 | memcpy (((char *)(buffer))+4, (buffer), 4); | |
599 | memcpy (((char *)(buffer)), temp, 4); | |
600 | } | |
601 | } | |
602 | ||
78fde5f8 KB |
603 | /* Return the GDB type object for the "standard" data type |
604 | of data in register REG. | |
605 | ||
606 | Note: kevinb/2002-08-01: The definition below should faithfully | |
607 | reproduce the behavior of each of the REGISTER_VIRTUAL_TYPE | |
608 | definitions found in config/mips/tm-*.h. I'm concerned about | |
609 | the ``FCRCS_REGNUM <= reg && reg <= LAST_EMBED_REGNUM'' clause | |
610 | though. In some cases FP_REGNUM is in this range, and I doubt | |
611 | that this code is correct for the 64-bit case. */ | |
612 | ||
613 | static struct type * | |
614 | mips_register_virtual_type (int reg) | |
615 | { | |
616 | if (FP0_REGNUM <= reg && reg < FP0_REGNUM + 32) | |
a6425924 KB |
617 | { |
618 | /* Floating point registers... */ | |
619 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
620 | return builtin_type_ieee_double_big; | |
621 | else | |
622 | return builtin_type_ieee_double_little; | |
623 | } | |
78fde5f8 KB |
624 | else if (reg == PS_REGNUM /* CR */) |
625 | return builtin_type_uint32; | |
626 | else if (FCRCS_REGNUM <= reg && reg <= LAST_EMBED_REGNUM) | |
627 | return builtin_type_uint32; | |
628 | else | |
629 | { | |
a6425924 KB |
630 | /* Everything else... |
631 | Return type appropriate for width of register. */ | |
632 | if (MIPS_REGSIZE == TYPE_LENGTH (builtin_type_uint64)) | |
633 | return builtin_type_uint64; | |
78fde5f8 | 634 | else |
a6425924 | 635 | return builtin_type_uint32; |
78fde5f8 KB |
636 | } |
637 | } | |
638 | ||
bcb0cc15 MS |
639 | /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */ |
640 | ||
641 | static CORE_ADDR | |
642 | mips_read_sp (void) | |
643 | { | |
644 | return ADDR_BITS_REMOVE (read_register (SP_REGNUM)); | |
645 | } | |
646 | ||
c906108c | 647 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 648 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
649 | |
650 | static int | |
651 | mips_mask_address_p (void) | |
652 | { | |
653 | switch (mask_address_var) | |
654 | { | |
7f19b9a2 | 655 | case AUTO_BOOLEAN_TRUE: |
4014092b | 656 | return 1; |
7f19b9a2 | 657 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
658 | return 0; |
659 | break; | |
7f19b9a2 | 660 | case AUTO_BOOLEAN_AUTO: |
92e1c15c | 661 | return MIPS_DEFAULT_MASK_ADDRESS_P; |
4014092b | 662 | default: |
8e65ff28 AC |
663 | internal_error (__FILE__, __LINE__, |
664 | "mips_mask_address_p: bad switch"); | |
4014092b | 665 | return -1; |
361d1df0 | 666 | } |
4014092b AC |
667 | } |
668 | ||
669 | static void | |
e9e68a56 | 670 | show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c) |
4014092b AC |
671 | { |
672 | switch (mask_address_var) | |
673 | { | |
7f19b9a2 | 674 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
675 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
676 | break; | |
7f19b9a2 | 677 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
678 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
679 | break; | |
7f19b9a2 | 680 | case AUTO_BOOLEAN_AUTO: |
4014092b AC |
681 | printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n", |
682 | mips_mask_address_p () ? "enabled" : "disabled"); | |
683 | break; | |
684 | default: | |
8e65ff28 AC |
685 | internal_error (__FILE__, __LINE__, |
686 | "show_mask_address: bad switch"); | |
4014092b | 687 | break; |
361d1df0 | 688 | } |
4014092b | 689 | } |
c906108c SS |
690 | |
691 | /* Should call_function allocate stack space for a struct return? */ | |
cb811fe7 | 692 | |
f7ab6ec6 | 693 | static int |
cb811fe7 | 694 | mips_eabi_use_struct_convention (int gcc_p, struct type *type) |
c906108c | 695 | { |
cb811fe7 MS |
696 | return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE); |
697 | } | |
698 | ||
f7ab6ec6 | 699 | static int |
cb811fe7 MS |
700 | mips_n32n64_use_struct_convention (int gcc_p, struct type *type) |
701 | { | |
b78bcb18 | 702 | return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE); |
cb811fe7 MS |
703 | } |
704 | ||
f7ab6ec6 | 705 | static int |
cb811fe7 MS |
706 | mips_o32_use_struct_convention (int gcc_p, struct type *type) |
707 | { | |
708 | return 1; /* Structures are returned by ref in extra arg0. */ | |
c906108c SS |
709 | } |
710 | ||
8b389c40 MS |
711 | /* Should call_function pass struct by reference? |
712 | For each architecture, structs are passed either by | |
713 | value or by reference, depending on their size. */ | |
714 | ||
715 | static int | |
716 | mips_eabi_reg_struct_has_addr (int gcc_p, struct type *type) | |
717 | { | |
718 | enum type_code typecode = TYPE_CODE (check_typedef (type)); | |
719 | int len = TYPE_LENGTH (check_typedef (type)); | |
720 | ||
721 | if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
722 | return (len > MIPS_SAVED_REGSIZE); | |
723 | ||
724 | return 0; | |
725 | } | |
726 | ||
727 | static int | |
728 | mips_n32n64_reg_struct_has_addr (int gcc_p, struct type *type) | |
729 | { | |
730 | return 0; /* Assumption: N32/N64 never passes struct by ref. */ | |
731 | } | |
732 | ||
f7ab6ec6 | 733 | static int |
8b389c40 MS |
734 | mips_o32_reg_struct_has_addr (int gcc_p, struct type *type) |
735 | { | |
736 | return 0; /* Assumption: O32/O64 never passes struct by ref. */ | |
737 | } | |
738 | ||
c906108c SS |
739 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
740 | ||
741 | static int | |
742 | pc_is_mips16 (bfd_vma memaddr) | |
743 | { | |
744 | struct minimal_symbol *sym; | |
745 | ||
746 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
747 | if (IS_MIPS16_ADDR (memaddr)) | |
748 | return 1; | |
749 | ||
750 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
751 | the high bit of the info field. Use this to decide if the function is | |
752 | MIPS16 or normal MIPS. */ | |
753 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
754 | if (sym) | |
71b8ef93 | 755 | return msymbol_is_special (sym); |
c906108c SS |
756 | else |
757 | return 0; | |
758 | } | |
759 | ||
6c997a34 AC |
760 | /* MIPS believes that the PC has a sign extended value. Perhaphs the |
761 | all registers should be sign extended for simplicity? */ | |
762 | ||
763 | static CORE_ADDR | |
39f77062 | 764 | mips_read_pc (ptid_t ptid) |
6c997a34 | 765 | { |
39f77062 | 766 | return read_signed_register_pid (PC_REGNUM, ptid); |
6c997a34 | 767 | } |
c906108c SS |
768 | |
769 | /* This returns the PC of the first inst after the prologue. If we can't | |
770 | find the prologue, then return 0. */ | |
771 | ||
772 | static CORE_ADDR | |
acdb74a0 AC |
773 | after_prologue (CORE_ADDR pc, |
774 | mips_extra_func_info_t proc_desc) | |
c906108c SS |
775 | { |
776 | struct symtab_and_line sal; | |
777 | CORE_ADDR func_addr, func_end; | |
778 | ||
479412cd DJ |
779 | /* Pass cur_frame == 0 to find_proc_desc. We should not attempt |
780 | to read the stack pointer from the current machine state, because | |
781 | the current machine state has nothing to do with the information | |
782 | we need from the proc_desc; and the process may or may not exist | |
783 | right now. */ | |
c906108c | 784 | if (!proc_desc) |
479412cd | 785 | proc_desc = find_proc_desc (pc, NULL, 0); |
c906108c SS |
786 | |
787 | if (proc_desc) | |
788 | { | |
789 | /* If function is frameless, then we need to do it the hard way. I | |
c5aa993b | 790 | strongly suspect that frameless always means prologueless... */ |
c906108c SS |
791 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM |
792 | && PROC_FRAME_OFFSET (proc_desc) == 0) | |
793 | return 0; | |
794 | } | |
795 | ||
796 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
797 | return 0; /* Unknown */ | |
798 | ||
799 | sal = find_pc_line (func_addr, 0); | |
800 | ||
801 | if (sal.end < func_end) | |
802 | return sal.end; | |
803 | ||
804 | /* The line after the prologue is after the end of the function. In this | |
805 | case, tell the caller to find the prologue the hard way. */ | |
806 | ||
807 | return 0; | |
808 | } | |
809 | ||
810 | /* Decode a MIPS32 instruction that saves a register in the stack, and | |
811 | set the appropriate bit in the general register mask or float register mask | |
812 | to indicate which register is saved. This is a helper function | |
813 | for mips_find_saved_regs. */ | |
814 | ||
815 | static void | |
acdb74a0 AC |
816 | mips32_decode_reg_save (t_inst inst, unsigned long *gen_mask, |
817 | unsigned long *float_mask) | |
c906108c SS |
818 | { |
819 | int reg; | |
820 | ||
821 | if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */ | |
822 | || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */ | |
823 | || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */ | |
824 | { | |
825 | /* It might be possible to use the instruction to | |
c5aa993b JM |
826 | find the offset, rather than the code below which |
827 | is based on things being in a certain order in the | |
828 | frame, but figuring out what the instruction's offset | |
829 | is relative to might be a little tricky. */ | |
c906108c SS |
830 | reg = (inst & 0x001f0000) >> 16; |
831 | *gen_mask |= (1 << reg); | |
832 | } | |
833 | else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */ | |
c5aa993b JM |
834 | || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */ |
835 | || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */ | |
c906108c SS |
836 | |
837 | { | |
838 | reg = ((inst & 0x001f0000) >> 16); | |
839 | *float_mask |= (1 << reg); | |
840 | } | |
841 | } | |
842 | ||
843 | /* Decode a MIPS16 instruction that saves a register in the stack, and | |
844 | set the appropriate bit in the general register or float register mask | |
845 | to indicate which register is saved. This is a helper function | |
846 | for mips_find_saved_regs. */ | |
847 | ||
848 | static void | |
acdb74a0 | 849 | mips16_decode_reg_save (t_inst inst, unsigned long *gen_mask) |
c906108c | 850 | { |
c5aa993b | 851 | if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ |
c906108c SS |
852 | { |
853 | int reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
854 | *gen_mask |= (1 << reg); | |
855 | } | |
c5aa993b | 856 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ |
c906108c SS |
857 | { |
858 | int reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
859 | *gen_mask |= (1 << reg); | |
860 | } | |
c5aa993b | 861 | else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */ |
c906108c SS |
862 | || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ |
863 | *gen_mask |= (1 << RA_REGNUM); | |
864 | } | |
865 | ||
866 | ||
867 | /* Fetch and return instruction from the specified location. If the PC | |
868 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
869 | ||
870 | static t_inst | |
acdb74a0 | 871 | mips_fetch_instruction (CORE_ADDR addr) |
c906108c SS |
872 | { |
873 | char buf[MIPS_INSTLEN]; | |
874 | int instlen; | |
875 | int status; | |
876 | ||
877 | if (pc_is_mips16 (addr)) | |
878 | { | |
879 | instlen = MIPS16_INSTLEN; | |
880 | addr = UNMAKE_MIPS16_ADDR (addr); | |
881 | } | |
882 | else | |
c5aa993b | 883 | instlen = MIPS_INSTLEN; |
c906108c SS |
884 | status = read_memory_nobpt (addr, buf, instlen); |
885 | if (status) | |
886 | memory_error (status, addr); | |
887 | return extract_unsigned_integer (buf, instlen); | |
888 | } | |
889 | ||
890 | ||
891 | /* These the fields of 32 bit mips instructions */ | |
e135b889 DJ |
892 | #define mips32_op(x) (x >> 26) |
893 | #define itype_op(x) (x >> 26) | |
894 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 895 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 896 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 897 | |
e135b889 DJ |
898 | #define jtype_op(x) (x >> 26) |
899 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 900 | |
e135b889 DJ |
901 | #define rtype_op(x) (x >> 26) |
902 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
903 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
904 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
905 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
906 | #define rtype_funct(x) (x & 0x3f) | |
c906108c SS |
907 | |
908 | static CORE_ADDR | |
c5aa993b JM |
909 | mips32_relative_offset (unsigned long inst) |
910 | { | |
911 | long x; | |
912 | x = itype_immediate (inst); | |
913 | if (x & 0x8000) /* sign bit set */ | |
c906108c | 914 | { |
c5aa993b | 915 | x |= 0xffff0000; /* sign extension */ |
c906108c | 916 | } |
c5aa993b JM |
917 | x = x << 2; |
918 | return x; | |
c906108c SS |
919 | } |
920 | ||
921 | /* Determine whate to set a single step breakpoint while considering | |
922 | branch prediction */ | |
5a89d8aa | 923 | static CORE_ADDR |
c5aa993b JM |
924 | mips32_next_pc (CORE_ADDR pc) |
925 | { | |
926 | unsigned long inst; | |
927 | int op; | |
928 | inst = mips_fetch_instruction (pc); | |
e135b889 | 929 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 930 | { |
e135b889 DJ |
931 | if (itype_op (inst) >> 2 == 5) |
932 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ | |
c5aa993b | 933 | { |
e135b889 | 934 | op = (itype_op (inst) & 0x03); |
c906108c SS |
935 | switch (op) |
936 | { | |
e135b889 DJ |
937 | case 0: /* BEQL */ |
938 | goto equal_branch; | |
939 | case 1: /* BNEL */ | |
940 | goto neq_branch; | |
941 | case 2: /* BLEZL */ | |
942 | goto less_branch; | |
943 | case 3: /* BGTZ */ | |
944 | goto greater_branch; | |
c5aa993b JM |
945 | default: |
946 | pc += 4; | |
c906108c SS |
947 | } |
948 | } | |
e135b889 DJ |
949 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
950 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ | |
951 | { | |
952 | int tf = itype_rt (inst) & 0x01; | |
953 | int cnum = itype_rt (inst) >> 2; | |
954 | int fcrcs = read_signed_register (FCRCS_REGNUM); | |
955 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); | |
956 | ||
957 | if (((cond >> cnum) & 0x01) == tf) | |
958 | pc += mips32_relative_offset (inst) + 4; | |
959 | else | |
960 | pc += 8; | |
961 | } | |
c5aa993b JM |
962 | else |
963 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
964 | } |
965 | else | |
c5aa993b JM |
966 | { /* This gets way messy */ |
967 | ||
c906108c | 968 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 969 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 970 | { |
c5aa993b JM |
971 | case 0: /* SPECIAL */ |
972 | op = rtype_funct (inst); | |
973 | switch (op) | |
974 | { | |
975 | case 8: /* JR */ | |
976 | case 9: /* JALR */ | |
6c997a34 AC |
977 | /* Set PC to that address */ |
978 | pc = read_signed_register (rtype_rs (inst)); | |
c5aa993b JM |
979 | break; |
980 | default: | |
981 | pc += 4; | |
982 | } | |
983 | ||
e135b889 | 984 | break; /* end SPECIAL */ |
c5aa993b | 985 | case 1: /* REGIMM */ |
c906108c | 986 | { |
e135b889 DJ |
987 | op = itype_rt (inst); /* branch condition */ |
988 | switch (op) | |
c906108c | 989 | { |
c5aa993b | 990 | case 0: /* BLTZ */ |
e135b889 DJ |
991 | case 2: /* BLTZL */ |
992 | case 16: /* BLTZAL */ | |
c5aa993b | 993 | case 18: /* BLTZALL */ |
c906108c | 994 | less_branch: |
6c997a34 | 995 | if (read_signed_register (itype_rs (inst)) < 0) |
c5aa993b JM |
996 | pc += mips32_relative_offset (inst) + 4; |
997 | else | |
998 | pc += 8; /* after the delay slot */ | |
999 | break; | |
e135b889 | 1000 | case 1: /* BGEZ */ |
c5aa993b JM |
1001 | case 3: /* BGEZL */ |
1002 | case 17: /* BGEZAL */ | |
1003 | case 19: /* BGEZALL */ | |
c906108c | 1004 | greater_equal_branch: |
6c997a34 | 1005 | if (read_signed_register (itype_rs (inst)) >= 0) |
c5aa993b JM |
1006 | pc += mips32_relative_offset (inst) + 4; |
1007 | else | |
1008 | pc += 8; /* after the delay slot */ | |
1009 | break; | |
e135b889 | 1010 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1011 | default: |
1012 | pc += 4; | |
c906108c SS |
1013 | } |
1014 | } | |
e135b889 | 1015 | break; /* end REGIMM */ |
c5aa993b JM |
1016 | case 2: /* J */ |
1017 | case 3: /* JAL */ | |
1018 | { | |
1019 | unsigned long reg; | |
1020 | reg = jtype_target (inst) << 2; | |
e135b889 | 1021 | /* Upper four bits get never changed... */ |
c5aa993b | 1022 | pc = reg + ((pc + 4) & 0xf0000000); |
c906108c | 1023 | } |
c5aa993b JM |
1024 | break; |
1025 | /* FIXME case JALX : */ | |
1026 | { | |
1027 | unsigned long reg; | |
1028 | reg = jtype_target (inst) << 2; | |
1029 | pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */ | |
c906108c SS |
1030 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1031 | } | |
c5aa993b | 1032 | break; /* The new PC will be alternate mode */ |
e135b889 | 1033 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1034 | equal_branch: |
6c997a34 AC |
1035 | if (read_signed_register (itype_rs (inst)) == |
1036 | read_signed_register (itype_rt (inst))) | |
c5aa993b JM |
1037 | pc += mips32_relative_offset (inst) + 4; |
1038 | else | |
1039 | pc += 8; | |
1040 | break; | |
e135b889 | 1041 | case 5: /* BNE, BNEL */ |
c5aa993b | 1042 | neq_branch: |
6c997a34 | 1043 | if (read_signed_register (itype_rs (inst)) != |
e135b889 | 1044 | read_signed_register (itype_rt (inst))) |
c5aa993b JM |
1045 | pc += mips32_relative_offset (inst) + 4; |
1046 | else | |
1047 | pc += 8; | |
1048 | break; | |
e135b889 | 1049 | case 6: /* BLEZ, BLEZL */ |
c906108c | 1050 | less_zero_branch: |
6c997a34 | 1051 | if (read_signed_register (itype_rs (inst) <= 0)) |
c5aa993b JM |
1052 | pc += mips32_relative_offset (inst) + 4; |
1053 | else | |
1054 | pc += 8; | |
1055 | break; | |
1056 | case 7: | |
e135b889 DJ |
1057 | default: |
1058 | greater_branch: /* BGTZ, BGTZL */ | |
6c997a34 | 1059 | if (read_signed_register (itype_rs (inst) > 0)) |
c5aa993b JM |
1060 | pc += mips32_relative_offset (inst) + 4; |
1061 | else | |
1062 | pc += 8; | |
1063 | break; | |
c5aa993b JM |
1064 | } /* switch */ |
1065 | } /* else */ | |
1066 | return pc; | |
1067 | } /* mips32_next_pc */ | |
c906108c SS |
1068 | |
1069 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 1070 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
1071 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
1072 | We dont want to set a single step instruction on the extend instruction | |
1073 | either. | |
c5aa993b | 1074 | */ |
c906108c SS |
1075 | |
1076 | /* Lots of mips16 instruction formats */ | |
1077 | /* Predicting jumps requires itype,ritype,i8type | |
1078 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 1079 | */ |
c906108c SS |
1080 | enum mips16_inst_fmts |
1081 | { | |
c5aa993b JM |
1082 | itype, /* 0 immediate 5,10 */ |
1083 | ritype, /* 1 5,3,8 */ | |
1084 | rrtype, /* 2 5,3,3,5 */ | |
1085 | rritype, /* 3 5,3,3,5 */ | |
1086 | rrrtype, /* 4 5,3,3,3,2 */ | |
1087 | rriatype, /* 5 5,3,3,1,4 */ | |
1088 | shifttype, /* 6 5,3,3,3,2 */ | |
1089 | i8type, /* 7 5,3,8 */ | |
1090 | i8movtype, /* 8 5,3,3,5 */ | |
1091 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1092 | i64type, /* 10 5,3,8 */ | |
1093 | ri64type, /* 11 5,3,3,5 */ | |
1094 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1095 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1096 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1097 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1098 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1099 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1100 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1101 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1102 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1103 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1104 | }; | |
12f02c2a AC |
1105 | /* I am heaping all the fields of the formats into one structure and |
1106 | then, only the fields which are involved in instruction extension */ | |
c906108c | 1107 | struct upk_mips16 |
c5aa993b | 1108 | { |
12f02c2a | 1109 | CORE_ADDR offset; |
c5aa993b JM |
1110 | unsigned int regx; /* Function in i8 type */ |
1111 | unsigned int regy; | |
1112 | }; | |
c906108c SS |
1113 | |
1114 | ||
12f02c2a AC |
1115 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
1116 | for the bits which make up the immediatate extension. */ | |
c906108c | 1117 | |
12f02c2a AC |
1118 | static CORE_ADDR |
1119 | extended_offset (unsigned int extension) | |
c906108c | 1120 | { |
12f02c2a | 1121 | CORE_ADDR value; |
c5aa993b JM |
1122 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1123 | value = value << 6; | |
1124 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
1125 | value = value << 5; | |
1126 | value |= extension & 0x01f; /* extract 4:0 */ | |
1127 | return value; | |
c906108c SS |
1128 | } |
1129 | ||
1130 | /* Only call this function if you know that this is an extendable | |
1131 | instruction, It wont malfunction, but why make excess remote memory references? | |
1132 | If the immediate operands get sign extended or somthing, do it after | |
1133 | the extension is performed. | |
c5aa993b | 1134 | */ |
c906108c SS |
1135 | /* FIXME: Every one of these cases needs to worry about sign extension |
1136 | when the offset is to be used in relative addressing */ | |
1137 | ||
1138 | ||
12f02c2a | 1139 | static unsigned int |
c5aa993b | 1140 | fetch_mips_16 (CORE_ADDR pc) |
c906108c | 1141 | { |
c5aa993b JM |
1142 | char buf[8]; |
1143 | pc &= 0xfffffffe; /* clear the low order bit */ | |
1144 | target_read_memory (pc, buf, 2); | |
1145 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
1146 | } |
1147 | ||
1148 | static void | |
c5aa993b | 1149 | unpack_mips16 (CORE_ADDR pc, |
12f02c2a AC |
1150 | unsigned int extension, |
1151 | unsigned int inst, | |
1152 | enum mips16_inst_fmts insn_format, | |
c5aa993b | 1153 | struct upk_mips16 *upk) |
c906108c | 1154 | { |
12f02c2a AC |
1155 | CORE_ADDR offset; |
1156 | int regx; | |
1157 | int regy; | |
1158 | switch (insn_format) | |
c906108c | 1159 | { |
c5aa993b | 1160 | case itype: |
c906108c | 1161 | { |
12f02c2a AC |
1162 | CORE_ADDR value; |
1163 | if (extension) | |
c5aa993b JM |
1164 | { |
1165 | value = extended_offset (extension); | |
1166 | value = value << 11; /* rom for the original value */ | |
12f02c2a | 1167 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1168 | } |
1169 | else | |
c5aa993b | 1170 | { |
12f02c2a | 1171 | value = inst & 0x7ff; |
c5aa993b | 1172 | /* FIXME : Consider sign extension */ |
c906108c | 1173 | } |
12f02c2a AC |
1174 | offset = value; |
1175 | regx = -1; | |
1176 | regy = -1; | |
c906108c | 1177 | } |
c5aa993b JM |
1178 | break; |
1179 | case ritype: | |
1180 | case i8type: | |
1181 | { /* A register identifier and an offset */ | |
c906108c SS |
1182 | /* Most of the fields are the same as I type but the |
1183 | immediate value is of a different length */ | |
12f02c2a AC |
1184 | CORE_ADDR value; |
1185 | if (extension) | |
c906108c | 1186 | { |
c5aa993b JM |
1187 | value = extended_offset (extension); |
1188 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1189 | value |= inst & 0xff; /* eleven bits from instruction */ |
1190 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1191 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1192 | { | |
1193 | value &= ~0x3fff; /* remove the sign bit */ | |
1194 | value = -value; | |
c906108c SS |
1195 | } |
1196 | } | |
c5aa993b JM |
1197 | else |
1198 | { | |
12f02c2a AC |
1199 | value = inst & 0xff; /* 8 bits */ |
1200 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1201 | /* FIXME: Do sign extension , this format needs it */ |
1202 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1203 | { | |
1204 | value &= 0xef; /* remove the sign bit */ | |
1205 | value = -value; | |
1206 | } | |
c5aa993b | 1207 | } |
12f02c2a AC |
1208 | offset = value; |
1209 | regy = -1; | |
c5aa993b | 1210 | break; |
c906108c | 1211 | } |
c5aa993b | 1212 | case jalxtype: |
c906108c | 1213 | { |
c5aa993b | 1214 | unsigned long value; |
12f02c2a AC |
1215 | unsigned int nexthalf; |
1216 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b JM |
1217 | value = value << 16; |
1218 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
1219 | value |= nexthalf; | |
12f02c2a AC |
1220 | offset = value; |
1221 | regx = -1; | |
1222 | regy = -1; | |
c5aa993b | 1223 | break; |
c906108c SS |
1224 | } |
1225 | default: | |
8e65ff28 AC |
1226 | internal_error (__FILE__, __LINE__, |
1227 | "bad switch"); | |
c906108c | 1228 | } |
12f02c2a AC |
1229 | upk->offset = offset; |
1230 | upk->regx = regx; | |
1231 | upk->regy = regy; | |
c906108c SS |
1232 | } |
1233 | ||
1234 | ||
c5aa993b JM |
1235 | static CORE_ADDR |
1236 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1237 | { |
c5aa993b | 1238 | return ((offset << 2) | ((pc + 2) & (0xf0000000))); |
c906108c SS |
1239 | } |
1240 | ||
12f02c2a AC |
1241 | static CORE_ADDR |
1242 | extended_mips16_next_pc (CORE_ADDR pc, | |
1243 | unsigned int extension, | |
1244 | unsigned int insn) | |
c906108c | 1245 | { |
12f02c2a AC |
1246 | int op = (insn >> 11); |
1247 | switch (op) | |
c906108c | 1248 | { |
12f02c2a AC |
1249 | case 2: /* Branch */ |
1250 | { | |
1251 | CORE_ADDR offset; | |
1252 | struct upk_mips16 upk; | |
1253 | unpack_mips16 (pc, extension, insn, itype, &upk); | |
1254 | offset = upk.offset; | |
1255 | if (offset & 0x800) | |
1256 | { | |
1257 | offset &= 0xeff; | |
1258 | offset = -offset; | |
1259 | } | |
1260 | pc += (offset << 1) + 2; | |
1261 | break; | |
1262 | } | |
1263 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ | |
1264 | { | |
1265 | struct upk_mips16 upk; | |
1266 | unpack_mips16 (pc, extension, insn, jalxtype, &upk); | |
1267 | pc = add_offset_16 (pc, upk.offset); | |
1268 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1269 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1270 | else | |
1271 | pc |= 0x01; | |
1272 | break; | |
1273 | } | |
1274 | case 4: /* beqz */ | |
1275 | { | |
1276 | struct upk_mips16 upk; | |
1277 | int reg; | |
1278 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1279 | reg = read_signed_register (upk.regx); | |
1280 | if (reg == 0) | |
1281 | pc += (upk.offset << 1) + 2; | |
1282 | else | |
1283 | pc += 2; | |
1284 | break; | |
1285 | } | |
1286 | case 5: /* bnez */ | |
1287 | { | |
1288 | struct upk_mips16 upk; | |
1289 | int reg; | |
1290 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1291 | reg = read_signed_register (upk.regx); | |
1292 | if (reg != 0) | |
1293 | pc += (upk.offset << 1) + 2; | |
1294 | else | |
1295 | pc += 2; | |
1296 | break; | |
1297 | } | |
1298 | case 12: /* I8 Formats btez btnez */ | |
1299 | { | |
1300 | struct upk_mips16 upk; | |
1301 | int reg; | |
1302 | unpack_mips16 (pc, extension, insn, i8type, &upk); | |
1303 | /* upk.regx contains the opcode */ | |
1304 | reg = read_signed_register (24); /* Test register is 24 */ | |
1305 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ | |
1306 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1307 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1308 | pc += (upk.offset << 1) + 2; | |
1309 | else | |
1310 | pc += 2; | |
1311 | break; | |
1312 | } | |
1313 | case 29: /* RR Formats JR, JALR, JALR-RA */ | |
1314 | { | |
1315 | struct upk_mips16 upk; | |
1316 | /* upk.fmt = rrtype; */ | |
1317 | op = insn & 0x1f; | |
1318 | if (op == 0) | |
c5aa993b | 1319 | { |
12f02c2a AC |
1320 | int reg; |
1321 | upk.regx = (insn >> 8) & 0x07; | |
1322 | upk.regy = (insn >> 5) & 0x07; | |
1323 | switch (upk.regy) | |
c5aa993b | 1324 | { |
12f02c2a AC |
1325 | case 0: |
1326 | reg = upk.regx; | |
1327 | break; | |
1328 | case 1: | |
1329 | reg = 31; | |
1330 | break; /* Function return instruction */ | |
1331 | case 2: | |
1332 | reg = upk.regx; | |
1333 | break; | |
1334 | default: | |
1335 | reg = 31; | |
1336 | break; /* BOGUS Guess */ | |
c906108c | 1337 | } |
12f02c2a | 1338 | pc = read_signed_register (reg); |
c906108c | 1339 | } |
12f02c2a | 1340 | else |
c5aa993b | 1341 | pc += 2; |
12f02c2a AC |
1342 | break; |
1343 | } | |
1344 | case 30: | |
1345 | /* This is an instruction extension. Fetch the real instruction | |
1346 | (which follows the extension) and decode things based on | |
1347 | that. */ | |
1348 | { | |
1349 | pc += 2; | |
1350 | pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc)); | |
1351 | break; | |
1352 | } | |
1353 | default: | |
1354 | { | |
1355 | pc += 2; | |
1356 | break; | |
1357 | } | |
c906108c | 1358 | } |
c5aa993b | 1359 | return pc; |
12f02c2a | 1360 | } |
c906108c | 1361 | |
5a89d8aa | 1362 | static CORE_ADDR |
12f02c2a AC |
1363 | mips16_next_pc (CORE_ADDR pc) |
1364 | { | |
1365 | unsigned int insn = fetch_mips_16 (pc); | |
1366 | return extended_mips16_next_pc (pc, 0, insn); | |
1367 | } | |
1368 | ||
1369 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1370 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1371 | It works by decoding the current instruction and predicting where a |
1372 | branch will go. This isnt hard because all the data is available. | |
1373 | The MIPS32 and MIPS16 variants are quite different */ | |
c5aa993b JM |
1374 | CORE_ADDR |
1375 | mips_next_pc (CORE_ADDR pc) | |
c906108c | 1376 | { |
c5aa993b JM |
1377 | if (pc & 0x01) |
1378 | return mips16_next_pc (pc); | |
1379 | else | |
1380 | return mips32_next_pc (pc); | |
12f02c2a | 1381 | } |
c906108c SS |
1382 | |
1383 | /* Guaranteed to set fci->saved_regs to some values (it never leaves it | |
ffabd70d KB |
1384 | NULL). |
1385 | ||
1386 | Note: kevinb/2002-08-09: The only caller of this function is (and | |
1387 | should remain) mips_frame_init_saved_regs(). In fact, | |
1388 | aside from calling mips_find_saved_regs(), mips_frame_init_saved_regs() | |
1389 | does nothing more than set frame->saved_regs[SP_REGNUM]. These two | |
1390 | functions should really be combined and now that there is only one | |
1391 | caller, it should be straightforward. (Watch out for multiple returns | |
c4ac3e63 | 1392 | though.) */ |
c906108c | 1393 | |
d28e01f4 | 1394 | static void |
acdb74a0 | 1395 | mips_find_saved_regs (struct frame_info *fci) |
c906108c SS |
1396 | { |
1397 | int ireg; | |
1398 | CORE_ADDR reg_position; | |
1399 | /* r0 bit means kernel trap */ | |
1400 | int kernel_trap; | |
1401 | /* What registers have been saved? Bitmasks. */ | |
1402 | unsigned long gen_mask, float_mask; | |
1403 | mips_extra_func_info_t proc_desc; | |
1404 | t_inst inst; | |
1405 | ||
1406 | frame_saved_regs_zalloc (fci); | |
1407 | ||
1408 | /* If it is the frame for sigtramp, the saved registers are located | |
1409 | in a sigcontext structure somewhere on the stack. | |
1410 | If the stack layout for sigtramp changes we might have to change these | |
1411 | constants and the companion fixup_sigtramp in mdebugread.c */ | |
1412 | #ifndef SIGFRAME_BASE | |
1413 | /* To satisfy alignment restrictions, sigcontext is located 4 bytes | |
1414 | above the sigtramp frame. */ | |
1415 | #define SIGFRAME_BASE MIPS_REGSIZE | |
1416 | /* FIXME! Are these correct?? */ | |
1417 | #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE) | |
1418 | #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE) | |
1419 | #define SIGFRAME_FPREGSAVE_OFF \ | |
1420 | (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE) | |
1421 | #endif | |
1422 | #ifndef SIGFRAME_REG_SIZE | |
1423 | /* FIXME! Is this correct?? */ | |
1424 | #define SIGFRAME_REG_SIZE MIPS_REGSIZE | |
1425 | #endif | |
1426 | if (fci->signal_handler_caller) | |
1427 | { | |
1428 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) | |
1429 | { | |
c5aa993b JM |
1430 | reg_position = fci->frame + SIGFRAME_REGSAVE_OFF |
1431 | + ireg * SIGFRAME_REG_SIZE; | |
1432 | fci->saved_regs[ireg] = reg_position; | |
c906108c SS |
1433 | } |
1434 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) | |
1435 | { | |
c5aa993b JM |
1436 | reg_position = fci->frame + SIGFRAME_FPREGSAVE_OFF |
1437 | + ireg * SIGFRAME_REG_SIZE; | |
1438 | fci->saved_regs[FP0_REGNUM + ireg] = reg_position; | |
c906108c SS |
1439 | } |
1440 | fci->saved_regs[PC_REGNUM] = fci->frame + SIGFRAME_PC_OFF; | |
1441 | return; | |
1442 | } | |
1443 | ||
cce74817 | 1444 | proc_desc = fci->extra_info->proc_desc; |
c906108c SS |
1445 | if (proc_desc == NULL) |
1446 | /* I'm not sure how/whether this can happen. Normally when we can't | |
1447 | find a proc_desc, we "synthesize" one using heuristic_proc_desc | |
1448 | and set the saved_regs right away. */ | |
1449 | return; | |
1450 | ||
c5aa993b JM |
1451 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; |
1452 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc); | |
1453 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc); | |
c906108c | 1454 | |
c5aa993b JM |
1455 | if ( /* In any frame other than the innermost or a frame interrupted by |
1456 | a signal, we assume that all registers have been saved. | |
1457 | This assumes that all register saves in a function happen before | |
1458 | the first function call. */ | |
1459 | (fci->next == NULL || fci->next->signal_handler_caller) | |
c906108c | 1460 | |
c5aa993b JM |
1461 | /* In a dummy frame we know exactly where things are saved. */ |
1462 | && !PROC_DESC_IS_DUMMY (proc_desc) | |
c906108c | 1463 | |
c5aa993b JM |
1464 | /* Don't bother unless we are inside a function prologue. Outside the |
1465 | prologue, we know where everything is. */ | |
c906108c | 1466 | |
c5aa993b | 1467 | && in_prologue (fci->pc, PROC_LOW_ADDR (proc_desc)) |
c906108c | 1468 | |
c5aa993b JM |
1469 | /* Not sure exactly what kernel_trap means, but if it means |
1470 | the kernel saves the registers without a prologue doing it, | |
1471 | we better not examine the prologue to see whether registers | |
1472 | have been saved yet. */ | |
1473 | && !kernel_trap) | |
c906108c SS |
1474 | { |
1475 | /* We need to figure out whether the registers that the proc_desc | |
c5aa993b | 1476 | claims are saved have been saved yet. */ |
c906108c SS |
1477 | |
1478 | CORE_ADDR addr; | |
1479 | ||
1480 | /* Bitmasks; set if we have found a save for the register. */ | |
1481 | unsigned long gen_save_found = 0; | |
1482 | unsigned long float_save_found = 0; | |
1483 | int instlen; | |
1484 | ||
1485 | /* If the address is odd, assume this is MIPS16 code. */ | |
1486 | addr = PROC_LOW_ADDR (proc_desc); | |
1487 | instlen = pc_is_mips16 (addr) ? MIPS16_INSTLEN : MIPS_INSTLEN; | |
1488 | ||
1489 | /* Scan through this function's instructions preceding the current | |
1490 | PC, and look for those that save registers. */ | |
1491 | while (addr < fci->pc) | |
1492 | { | |
1493 | inst = mips_fetch_instruction (addr); | |
1494 | if (pc_is_mips16 (addr)) | |
1495 | mips16_decode_reg_save (inst, &gen_save_found); | |
1496 | else | |
1497 | mips32_decode_reg_save (inst, &gen_save_found, &float_save_found); | |
1498 | addr += instlen; | |
1499 | } | |
1500 | gen_mask = gen_save_found; | |
1501 | float_mask = float_save_found; | |
1502 | } | |
1503 | ||
1504 | /* Fill in the offsets for the registers which gen_mask says | |
1505 | were saved. */ | |
1506 | reg_position = fci->frame + PROC_REG_OFFSET (proc_desc); | |
c5aa993b | 1507 | for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1) |
c906108c SS |
1508 | if (gen_mask & 0x80000000) |
1509 | { | |
1510 | fci->saved_regs[ireg] = reg_position; | |
7a292a7a | 1511 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1512 | } |
1513 | ||
1514 | /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order | |
1515 | of that normally used by gcc. Therefore, we have to fetch the first | |
1516 | instruction of the function, and if it's an entry instruction that | |
1517 | saves $s0 or $s1, correct their saved addresses. */ | |
1518 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) | |
1519 | { | |
1520 | inst = mips_fetch_instruction (PROC_LOW_ADDR (proc_desc)); | |
c5aa993b | 1521 | if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
c906108c SS |
1522 | { |
1523 | int reg; | |
1524 | int sreg_count = (inst >> 6) & 3; | |
c5aa993b | 1525 | |
c906108c SS |
1526 | /* Check if the ra register was pushed on the stack. */ |
1527 | reg_position = fci->frame + PROC_REG_OFFSET (proc_desc); | |
1528 | if (inst & 0x20) | |
7a292a7a | 1529 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1530 | |
1531 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
c5aa993b | 1532 | for (reg = 16; reg < sreg_count + 16; reg++) |
c906108c SS |
1533 | { |
1534 | fci->saved_regs[reg] = reg_position; | |
7a292a7a | 1535 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1536 | } |
1537 | } | |
1538 | } | |
1539 | ||
1540 | /* Fill in the offsets for the registers which float_mask says | |
1541 | were saved. */ | |
1542 | reg_position = fci->frame + PROC_FREG_OFFSET (proc_desc); | |
1543 | ||
6acdf5c7 MS |
1544 | /* Apparently, the freg_offset gives the offset to the first 64 bit |
1545 | saved. | |
1546 | ||
1547 | When the ABI specifies 64 bit saved registers, the FREG_OFFSET | |
1548 | designates the first saved 64 bit register. | |
1549 | ||
1550 | When the ABI specifies 32 bit saved registers, the ``64 bit saved | |
1551 | DOUBLE'' consists of two adjacent 32 bit registers, Hence | |
1552 | FREG_OFFSET, designates the address of the lower register of the | |
1553 | register pair. Adjust the offset so that it designates the upper | |
1554 | register of the pair -- i.e., the address of the first saved 32 | |
1555 | bit register. */ | |
1556 | ||
1557 | if (MIPS_SAVED_REGSIZE == 4) | |
7a292a7a | 1558 | reg_position += MIPS_SAVED_REGSIZE; |
c906108c SS |
1559 | |
1560 | /* Fill in the offsets for the float registers which float_mask says | |
1561 | were saved. */ | |
c5aa993b | 1562 | for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1) |
c906108c SS |
1563 | if (float_mask & 0x80000000) |
1564 | { | |
c5aa993b | 1565 | fci->saved_regs[FP0_REGNUM + ireg] = reg_position; |
7a292a7a | 1566 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1567 | } |
1568 | ||
1569 | fci->saved_regs[PC_REGNUM] = fci->saved_regs[RA_REGNUM]; | |
1570 | } | |
1571 | ||
d28e01f4 KB |
1572 | /* Set up the 'saved_regs' array. This is a data structure containing |
1573 | the addresses on the stack where each register has been saved, for | |
1574 | each stack frame. Registers that have not been saved will have | |
1575 | zero here. The stack pointer register is special: rather than the | |
1576 | address where the stack register has been saved, saved_regs[SP_REGNUM] | |
1577 | will have the actual value of the previous frame's stack register. */ | |
1578 | ||
1579 | static void | |
1580 | mips_frame_init_saved_regs (struct frame_info *frame) | |
1581 | { | |
1582 | if (frame->saved_regs == NULL) | |
1583 | { | |
1584 | mips_find_saved_regs (frame); | |
1585 | } | |
1586 | frame->saved_regs[SP_REGNUM] = frame->frame; | |
1587 | } | |
1588 | ||
c906108c | 1589 | static CORE_ADDR |
acdb74a0 | 1590 | read_next_frame_reg (struct frame_info *fi, int regno) |
c906108c SS |
1591 | { |
1592 | for (; fi; fi = fi->next) | |
1593 | { | |
1594 | /* We have to get the saved sp from the sigcontext | |
c5aa993b | 1595 | if it is a signal handler frame. */ |
c906108c SS |
1596 | if (regno == SP_REGNUM && !fi->signal_handler_caller) |
1597 | return fi->frame; | |
1598 | else | |
1599 | { | |
1600 | if (fi->saved_regs == NULL) | |
ffabd70d | 1601 | FRAME_INIT_SAVED_REGS (fi); |
c906108c | 1602 | if (fi->saved_regs[regno]) |
2acceee2 | 1603 | return read_memory_integer (ADDR_BITS_REMOVE (fi->saved_regs[regno]), MIPS_SAVED_REGSIZE); |
c906108c SS |
1604 | } |
1605 | } | |
6c997a34 | 1606 | return read_signed_register (regno); |
c906108c SS |
1607 | } |
1608 | ||
1609 | /* mips_addr_bits_remove - remove useless address bits */ | |
1610 | ||
875e1767 | 1611 | static CORE_ADDR |
acdb74a0 | 1612 | mips_addr_bits_remove (CORE_ADDR addr) |
c906108c | 1613 | { |
5213ab06 AC |
1614 | if (GDB_TARGET_IS_MIPS64) |
1615 | { | |
4014092b | 1616 | if (mips_mask_address_p () && (addr >> 32 == (CORE_ADDR) 0xffffffff)) |
5213ab06 AC |
1617 | { |
1618 | /* This hack is a work-around for existing boards using | |
1619 | PMON, the simulator, and any other 64-bit targets that | |
1620 | doesn't have true 64-bit addressing. On these targets, | |
1621 | the upper 32 bits of addresses are ignored by the | |
1622 | hardware. Thus, the PC or SP are likely to have been | |
1623 | sign extended to all 1s by instruction sequences that | |
1624 | load 32-bit addresses. For example, a typical piece of | |
4014092b AC |
1625 | code that loads an address is this: |
1626 | lui $r2, <upper 16 bits> | |
1627 | ori $r2, <lower 16 bits> | |
1628 | But the lui sign-extends the value such that the upper 32 | |
1629 | bits may be all 1s. The workaround is simply to mask off | |
1630 | these bits. In the future, gcc may be changed to support | |
1631 | true 64-bit addressing, and this masking will have to be | |
1632 | disabled. */ | |
5213ab06 AC |
1633 | addr &= (CORE_ADDR) 0xffffffff; |
1634 | } | |
1635 | } | |
4014092b | 1636 | else if (mips_mask_address_p ()) |
5213ab06 | 1637 | { |
4014092b AC |
1638 | /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be |
1639 | masking off bits, instead, the actual target should be asking | |
1640 | for the address to be converted to a valid pointer. */ | |
5213ab06 AC |
1641 | /* Even when GDB is configured for some 32-bit targets |
1642 | (e.g. mips-elf), BFD is configured to handle 64-bit targets, | |
1643 | so CORE_ADDR is 64 bits. So we still have to mask off | |
1644 | useless bits from addresses. */ | |
c5aa993b | 1645 | addr &= (CORE_ADDR) 0xffffffff; |
c906108c | 1646 | } |
c906108c SS |
1647 | return addr; |
1648 | } | |
1649 | ||
9022177c DJ |
1650 | /* mips_software_single_step() is called just before we want to resume |
1651 | the inferior, if we want to single-step it but there is no hardware | |
75c9abc6 | 1652 | or kernel single-step support (MIPS on GNU/Linux for example). We find |
9022177c DJ |
1653 | the target of the coming instruction and breakpoint it. |
1654 | ||
1655 | single_step is also called just after the inferior stops. If we had | |
1656 | set up a simulated single-step, we undo our damage. */ | |
1657 | ||
1658 | void | |
1659 | mips_software_single_step (enum target_signal sig, int insert_breakpoints_p) | |
1660 | { | |
1661 | static CORE_ADDR next_pc; | |
1662 | typedef char binsn_quantum[BREAKPOINT_MAX]; | |
1663 | static binsn_quantum break_mem; | |
1664 | CORE_ADDR pc; | |
1665 | ||
1666 | if (insert_breakpoints_p) | |
1667 | { | |
1668 | pc = read_register (PC_REGNUM); | |
1669 | next_pc = mips_next_pc (pc); | |
1670 | ||
1671 | target_insert_breakpoint (next_pc, break_mem); | |
1672 | } | |
1673 | else | |
1674 | target_remove_breakpoint (next_pc, break_mem); | |
1675 | } | |
1676 | ||
10312cc4 | 1677 | static void |
acdb74a0 | 1678 | mips_init_frame_pc_first (int fromleaf, struct frame_info *prev) |
c906108c SS |
1679 | { |
1680 | CORE_ADDR pc, tmp; | |
1681 | ||
1682 | pc = ((fromleaf) ? SAVED_PC_AFTER_CALL (prev->next) : | |
c5aa993b | 1683 | prev->next ? FRAME_SAVED_PC (prev->next) : read_pc ()); |
5a89d8aa | 1684 | tmp = SKIP_TRAMPOLINE_CODE (pc); |
c5aa993b | 1685 | prev->pc = tmp ? tmp : pc; |
c906108c SS |
1686 | } |
1687 | ||
1688 | ||
f7ab6ec6 | 1689 | static CORE_ADDR |
acdb74a0 | 1690 | mips_frame_saved_pc (struct frame_info *frame) |
c906108c SS |
1691 | { |
1692 | CORE_ADDR saved_pc; | |
cce74817 | 1693 | mips_extra_func_info_t proc_desc = frame->extra_info->proc_desc; |
c906108c SS |
1694 | /* We have to get the saved pc from the sigcontext |
1695 | if it is a signal handler frame. */ | |
1696 | int pcreg = frame->signal_handler_caller ? PC_REGNUM | |
c5aa993b | 1697 | : (proc_desc ? PROC_PC_REG (proc_desc) : RA_REGNUM); |
c906108c | 1698 | |
c5aa993b | 1699 | if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) |
7a292a7a | 1700 | saved_pc = read_memory_integer (frame->frame - MIPS_SAVED_REGSIZE, MIPS_SAVED_REGSIZE); |
c906108c | 1701 | else |
7a292a7a | 1702 | saved_pc = read_next_frame_reg (frame, pcreg); |
c906108c SS |
1703 | |
1704 | return ADDR_BITS_REMOVE (saved_pc); | |
1705 | } | |
1706 | ||
1707 | static struct mips_extra_func_info temp_proc_desc; | |
cce74817 | 1708 | static CORE_ADDR temp_saved_regs[NUM_REGS]; |
c906108c SS |
1709 | |
1710 | /* Set a register's saved stack address in temp_saved_regs. If an address | |
1711 | has already been set for this register, do nothing; this way we will | |
1712 | only recognize the first save of a given register in a function prologue. | |
1713 | This is a helper function for mips{16,32}_heuristic_proc_desc. */ | |
1714 | ||
1715 | static void | |
acdb74a0 | 1716 | set_reg_offset (int regno, CORE_ADDR offset) |
c906108c | 1717 | { |
cce74817 JM |
1718 | if (temp_saved_regs[regno] == 0) |
1719 | temp_saved_regs[regno] = offset; | |
c906108c SS |
1720 | } |
1721 | ||
1722 | ||
1723 | /* Test whether the PC points to the return instruction at the | |
1724 | end of a function. */ | |
1725 | ||
c5aa993b | 1726 | static int |
acdb74a0 | 1727 | mips_about_to_return (CORE_ADDR pc) |
c906108c SS |
1728 | { |
1729 | if (pc_is_mips16 (pc)) | |
1730 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler | |
1731 | generates a "jr $ra"; other times it generates code to load | |
1732 | the return address from the stack to an accessible register (such | |
1733 | as $a3), then a "jr" using that register. This second case | |
1734 | is almost impossible to distinguish from an indirect jump | |
1735 | used for switch statements, so we don't even try. */ | |
1736 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
1737 | else | |
1738 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
1739 | } | |
1740 | ||
1741 | ||
1742 | /* This fencepost looks highly suspicious to me. Removing it also | |
1743 | seems suspicious as it could affect remote debugging across serial | |
1744 | lines. */ | |
1745 | ||
1746 | static CORE_ADDR | |
acdb74a0 | 1747 | heuristic_proc_start (CORE_ADDR pc) |
c906108c | 1748 | { |
c5aa993b JM |
1749 | CORE_ADDR start_pc; |
1750 | CORE_ADDR fence; | |
1751 | int instlen; | |
1752 | int seen_adjsp = 0; | |
c906108c | 1753 | |
c5aa993b JM |
1754 | pc = ADDR_BITS_REMOVE (pc); |
1755 | start_pc = pc; | |
1756 | fence = start_pc - heuristic_fence_post; | |
1757 | if (start_pc == 0) | |
1758 | return 0; | |
c906108c | 1759 | |
c5aa993b JM |
1760 | if (heuristic_fence_post == UINT_MAX |
1761 | || fence < VM_MIN_ADDRESS) | |
1762 | fence = VM_MIN_ADDRESS; | |
c906108c | 1763 | |
c5aa993b | 1764 | instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN; |
c906108c | 1765 | |
c5aa993b JM |
1766 | /* search back for previous return */ |
1767 | for (start_pc -= instlen;; start_pc -= instlen) | |
1768 | if (start_pc < fence) | |
1769 | { | |
1770 | /* It's not clear to me why we reach this point when | |
1771 | stop_soon_quietly, but with this test, at least we | |
1772 | don't print out warnings for every child forked (eg, on | |
1773 | decstation). 22apr93 rich@cygnus.com. */ | |
1774 | if (!stop_soon_quietly) | |
c906108c | 1775 | { |
c5aa993b JM |
1776 | static int blurb_printed = 0; |
1777 | ||
1778 | warning ("Warning: GDB can't find the start of the function at 0x%s.", | |
1779 | paddr_nz (pc)); | |
1780 | ||
1781 | if (!blurb_printed) | |
c906108c | 1782 | { |
c5aa993b JM |
1783 | /* This actually happens frequently in embedded |
1784 | development, when you first connect to a board | |
1785 | and your stack pointer and pc are nowhere in | |
1786 | particular. This message needs to give people | |
1787 | in that situation enough information to | |
1788 | determine that it's no big deal. */ | |
1789 | printf_filtered ("\n\ | |
cd0fc7c3 SS |
1790 | GDB is unable to find the start of the function at 0x%s\n\ |
1791 | and thus can't determine the size of that function's stack frame.\n\ | |
1792 | This means that GDB may be unable to access that stack frame, or\n\ | |
1793 | the frames below it.\n\ | |
1794 | This problem is most likely caused by an invalid program counter or\n\ | |
1795 | stack pointer.\n\ | |
1796 | However, if you think GDB should simply search farther back\n\ | |
1797 | from 0x%s for code which looks like the beginning of a\n\ | |
1798 | function, you can increase the range of the search using the `set\n\ | |
1799 | heuristic-fence-post' command.\n", | |
c5aa993b JM |
1800 | paddr_nz (pc), paddr_nz (pc)); |
1801 | blurb_printed = 1; | |
c906108c | 1802 | } |
c906108c SS |
1803 | } |
1804 | ||
c5aa993b JM |
1805 | return 0; |
1806 | } | |
1807 | else if (pc_is_mips16 (start_pc)) | |
1808 | { | |
1809 | unsigned short inst; | |
1810 | ||
1811 | /* On MIPS16, any one of the following is likely to be the | |
1812 | start of a function: | |
1813 | entry | |
1814 | addiu sp,-n | |
1815 | daddiu sp,-n | |
1816 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
1817 | inst = mips_fetch_instruction (start_pc); | |
1818 | if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
1819 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
1820 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
1821 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
1822 | break; | |
1823 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
1824 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1825 | seen_adjsp = 1; | |
1826 | else | |
1827 | seen_adjsp = 0; | |
1828 | } | |
1829 | else if (mips_about_to_return (start_pc)) | |
1830 | { | |
1831 | start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */ | |
1832 | break; | |
1833 | } | |
1834 | ||
c5aa993b | 1835 | return start_pc; |
c906108c SS |
1836 | } |
1837 | ||
1838 | /* Fetch the immediate value from a MIPS16 instruction. | |
1839 | If the previous instruction was an EXTEND, use it to extend | |
1840 | the upper bits of the immediate value. This is a helper function | |
1841 | for mips16_heuristic_proc_desc. */ | |
1842 | ||
1843 | static int | |
acdb74a0 AC |
1844 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ |
1845 | unsigned short inst, /* current instruction */ | |
1846 | int nbits, /* number of bits in imm field */ | |
1847 | int scale, /* scale factor to be applied to imm */ | |
1848 | int is_signed) /* is the imm field signed? */ | |
c906108c SS |
1849 | { |
1850 | int offset; | |
1851 | ||
1852 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ | |
1853 | { | |
1854 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
c5aa993b | 1855 | if (offset & 0x8000) /* check for negative extend */ |
c906108c SS |
1856 | offset = 0 - (0x10000 - (offset & 0xffff)); |
1857 | return offset | (inst & 0x1f); | |
1858 | } | |
1859 | else | |
1860 | { | |
1861 | int max_imm = 1 << nbits; | |
1862 | int mask = max_imm - 1; | |
1863 | int sign_bit = max_imm >> 1; | |
1864 | ||
1865 | offset = inst & mask; | |
1866 | if (is_signed && (offset & sign_bit)) | |
1867 | offset = 0 - (max_imm - offset); | |
1868 | return offset * scale; | |
1869 | } | |
1870 | } | |
1871 | ||
1872 | ||
1873 | /* Fill in values in temp_proc_desc based on the MIPS16 instruction | |
1874 | stream from start_pc to limit_pc. */ | |
1875 | ||
1876 | static void | |
acdb74a0 AC |
1877 | mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
1878 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
1879 | { |
1880 | CORE_ADDR cur_pc; | |
1881 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
1882 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
1883 | unsigned inst = 0; /* current instruction */ | |
1884 | unsigned entry_inst = 0; /* the entry instruction */ | |
1885 | int reg, offset; | |
1886 | ||
c5aa993b JM |
1887 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */ |
1888 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ | |
c906108c SS |
1889 | |
1890 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN) | |
1891 | { | |
1892 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1893 | the immediate offset extension from it in mips16_get_imm. */ | |
1894 | prev_inst = inst; | |
1895 | ||
1896 | /* Fetch and decode the instruction. */ | |
1897 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
c5aa993b | 1898 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
c906108c SS |
1899 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ |
1900 | { | |
1901 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
c5aa993b JM |
1902 | if (offset < 0) /* negative stack adjustment? */ |
1903 | PROC_FRAME_OFFSET (&temp_proc_desc) -= offset; | |
c906108c SS |
1904 | else |
1905 | /* Exit loop if a positive stack adjustment is found, which | |
1906 | usually means that the stack cleanup code in the function | |
1907 | epilogue is reached. */ | |
1908 | break; | |
1909 | } | |
1910 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
1911 | { | |
1912 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1913 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
c5aa993b | 1914 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
c906108c SS |
1915 | set_reg_offset (reg, sp + offset); |
1916 | } | |
1917 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
1918 | { | |
1919 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1920 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 1921 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
c906108c SS |
1922 | set_reg_offset (reg, sp + offset); |
1923 | } | |
1924 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
1925 | { | |
1926 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
c5aa993b | 1927 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
c906108c SS |
1928 | set_reg_offset (RA_REGNUM, sp + offset); |
1929 | } | |
1930 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
1931 | { | |
1932 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
c5aa993b | 1933 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
c906108c SS |
1934 | set_reg_offset (RA_REGNUM, sp + offset); |
1935 | } | |
c5aa993b | 1936 | else if (inst == 0x673d) /* move $s1, $sp */ |
c906108c SS |
1937 | { |
1938 | frame_addr = sp; | |
1939 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
1940 | } | |
1941 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
1942 | { | |
1943 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1944 | frame_addr = sp + offset; | |
1945 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
1946 | PROC_FRAME_ADJUST (&temp_proc_desc) = offset; | |
1947 | } | |
1948 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
1949 | { | |
1950 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
1951 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 1952 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
1953 | set_reg_offset (reg, frame_addr + offset); |
1954 | } | |
1955 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
1956 | { | |
1957 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1958 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 1959 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
1960 | set_reg_offset (reg, frame_addr + offset); |
1961 | } | |
c5aa993b JM |
1962 | else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
1963 | entry_inst = inst; /* save for later processing */ | |
c906108c | 1964 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
c5aa993b | 1965 | cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */ |
c906108c SS |
1966 | } |
1967 | ||
c5aa993b JM |
1968 | /* The entry instruction is typically the first instruction in a function, |
1969 | and it stores registers at offsets relative to the value of the old SP | |
1970 | (before the prologue). But the value of the sp parameter to this | |
1971 | function is the new SP (after the prologue has been executed). So we | |
1972 | can't calculate those offsets until we've seen the entire prologue, | |
1973 | and can calculate what the old SP must have been. */ | |
1974 | if (entry_inst != 0) | |
1975 | { | |
1976 | int areg_count = (entry_inst >> 8) & 7; | |
1977 | int sreg_count = (entry_inst >> 6) & 3; | |
c906108c | 1978 | |
c5aa993b JM |
1979 | /* The entry instruction always subtracts 32 from the SP. */ |
1980 | PROC_FRAME_OFFSET (&temp_proc_desc) += 32; | |
c906108c | 1981 | |
c5aa993b JM |
1982 | /* Now we can calculate what the SP must have been at the |
1983 | start of the function prologue. */ | |
1984 | sp += PROC_FRAME_OFFSET (&temp_proc_desc); | |
c906108c | 1985 | |
c5aa993b JM |
1986 | /* Check if a0-a3 were saved in the caller's argument save area. */ |
1987 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
1988 | { | |
1989 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
1990 | set_reg_offset (reg, sp + offset); | |
1991 | offset += MIPS_SAVED_REGSIZE; | |
1992 | } | |
c906108c | 1993 | |
c5aa993b JM |
1994 | /* Check if the ra register was pushed on the stack. */ |
1995 | offset = -4; | |
1996 | if (entry_inst & 0x20) | |
1997 | { | |
1998 | PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM; | |
1999 | set_reg_offset (RA_REGNUM, sp + offset); | |
2000 | offset -= MIPS_SAVED_REGSIZE; | |
2001 | } | |
c906108c | 2002 | |
c5aa993b JM |
2003 | /* Check if the s0 and s1 registers were pushed on the stack. */ |
2004 | for (reg = 16; reg < sreg_count + 16; reg++) | |
2005 | { | |
2006 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
2007 | set_reg_offset (reg, sp + offset); | |
2008 | offset -= MIPS_SAVED_REGSIZE; | |
2009 | } | |
2010 | } | |
c906108c SS |
2011 | } |
2012 | ||
2013 | static void | |
fba45db2 KB |
2014 | mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
2015 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
2016 | { |
2017 | CORE_ADDR cur_pc; | |
c5aa993b | 2018 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ |
c906108c | 2019 | restart: |
cce74817 | 2020 | memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c5aa993b | 2021 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; |
c906108c SS |
2022 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ |
2023 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN) | |
2024 | { | |
2025 | unsigned long inst, high_word, low_word; | |
2026 | int reg; | |
2027 | ||
2028 | /* Fetch the instruction. */ | |
2029 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
2030 | ||
2031 | /* Save some code by pre-extracting some useful fields. */ | |
2032 | high_word = (inst >> 16) & 0xffff; | |
2033 | low_word = inst & 0xffff; | |
2034 | reg = high_word & 0x1f; | |
2035 | ||
c5aa993b | 2036 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
c906108c SS |
2037 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
2038 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
2039 | { | |
2040 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
c5aa993b | 2041 | PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word; |
c906108c SS |
2042 | else |
2043 | /* Exit loop if a positive stack adjustment is found, which | |
2044 | usually means that the stack cleanup code in the function | |
2045 | epilogue is reached. */ | |
2046 | break; | |
2047 | } | |
2048 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
2049 | { | |
c5aa993b | 2050 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
2051 | set_reg_offset (reg, sp + low_word); |
2052 | } | |
2053 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
2054 | { | |
2055 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra, | |
2056 | but the register size used is only 32 bits. Make the address | |
2057 | for the saved register point to the lower 32 bits. */ | |
c5aa993b | 2058 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
2059 | set_reg_offset (reg, sp + low_word + 8 - MIPS_REGSIZE); |
2060 | } | |
c5aa993b | 2061 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ |
c906108c SS |
2062 | { |
2063 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
c5aa993b JM |
2064 | if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc)) |
2065 | frame_addr = sp + low_word; | |
c906108c SS |
2066 | else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) |
2067 | { | |
2068 | unsigned alloca_adjust; | |
2069 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
c5aa993b JM |
2070 | frame_addr = read_next_frame_reg (next_frame, 30); |
2071 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); | |
c906108c SS |
2072 | if (alloca_adjust > 0) |
2073 | { | |
2074 | /* FP > SP + frame_size. This may be because | |
2075 | * of an alloca or somethings similar. | |
2076 | * Fix sp to "pre-alloca" value, and try again. | |
2077 | */ | |
2078 | sp += alloca_adjust; | |
2079 | goto restart; | |
2080 | } | |
2081 | } | |
2082 | } | |
c5aa993b JM |
2083 | /* move $30,$sp. With different versions of gas this will be either |
2084 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
2085 | Accept any one of these. */ | |
c906108c SS |
2086 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) |
2087 | { | |
2088 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
2089 | if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) | |
2090 | { | |
2091 | unsigned alloca_adjust; | |
2092 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
c5aa993b JM |
2093 | frame_addr = read_next_frame_reg (next_frame, 30); |
2094 | alloca_adjust = (unsigned) (frame_addr - sp); | |
c906108c SS |
2095 | if (alloca_adjust > 0) |
2096 | { | |
2097 | /* FP > SP + frame_size. This may be because | |
2098 | * of an alloca or somethings similar. | |
2099 | * Fix sp to "pre-alloca" value, and try again. | |
2100 | */ | |
2101 | sp += alloca_adjust; | |
2102 | goto restart; | |
2103 | } | |
2104 | } | |
2105 | } | |
c5aa993b | 2106 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ |
c906108c | 2107 | { |
c5aa993b | 2108 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
2109 | set_reg_offset (reg, frame_addr + low_word); |
2110 | } | |
2111 | } | |
2112 | } | |
2113 | ||
2114 | static mips_extra_func_info_t | |
acdb74a0 | 2115 | heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
479412cd | 2116 | struct frame_info *next_frame, int cur_frame) |
c906108c | 2117 | { |
479412cd DJ |
2118 | CORE_ADDR sp; |
2119 | ||
2120 | if (cur_frame) | |
2121 | sp = read_next_frame_reg (next_frame, SP_REGNUM); | |
2122 | else | |
2123 | sp = 0; | |
c906108c | 2124 | |
c5aa993b JM |
2125 | if (start_pc == 0) |
2126 | return NULL; | |
2127 | memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc)); | |
cce74817 | 2128 | memset (&temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
2129 | PROC_LOW_ADDR (&temp_proc_desc) = start_pc; |
2130 | PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM; | |
2131 | PROC_PC_REG (&temp_proc_desc) = RA_REGNUM; | |
2132 | ||
2133 | if (start_pc + 200 < limit_pc) | |
2134 | limit_pc = start_pc + 200; | |
2135 | if (pc_is_mips16 (start_pc)) | |
2136 | mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
2137 | else | |
2138 | mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
2139 | return &temp_proc_desc; | |
2140 | } | |
2141 | ||
6c0d6680 DJ |
2142 | struct mips_objfile_private |
2143 | { | |
2144 | bfd_size_type size; | |
2145 | char *contents; | |
2146 | }; | |
2147 | ||
2148 | /* Global used to communicate between non_heuristic_proc_desc and | |
2149 | compare_pdr_entries within qsort (). */ | |
2150 | static bfd *the_bfd; | |
2151 | ||
2152 | static int | |
2153 | compare_pdr_entries (const void *a, const void *b) | |
2154 | { | |
2155 | CORE_ADDR lhs = bfd_get_32 (the_bfd, (bfd_byte *) a); | |
2156 | CORE_ADDR rhs = bfd_get_32 (the_bfd, (bfd_byte *) b); | |
2157 | ||
2158 | if (lhs < rhs) | |
2159 | return -1; | |
2160 | else if (lhs == rhs) | |
2161 | return 0; | |
2162 | else | |
2163 | return 1; | |
2164 | } | |
2165 | ||
c906108c | 2166 | static mips_extra_func_info_t |
acdb74a0 | 2167 | non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr) |
c906108c SS |
2168 | { |
2169 | CORE_ADDR startaddr; | |
2170 | mips_extra_func_info_t proc_desc; | |
c5aa993b | 2171 | struct block *b = block_for_pc (pc); |
c906108c | 2172 | struct symbol *sym; |
6c0d6680 DJ |
2173 | struct obj_section *sec; |
2174 | struct mips_objfile_private *priv; | |
2175 | ||
2176 | if (PC_IN_CALL_DUMMY (pc, 0, 0)) | |
2177 | return NULL; | |
c906108c SS |
2178 | |
2179 | find_pc_partial_function (pc, NULL, &startaddr, NULL); | |
2180 | if (addrptr) | |
2181 | *addrptr = startaddr; | |
6c0d6680 DJ |
2182 | |
2183 | priv = NULL; | |
2184 | ||
2185 | sec = find_pc_section (pc); | |
2186 | if (sec != NULL) | |
c906108c | 2187 | { |
6c0d6680 DJ |
2188 | priv = (struct mips_objfile_private *) sec->objfile->obj_private; |
2189 | ||
2190 | /* Search the ".pdr" section generated by GAS. This includes most of | |
2191 | the information normally found in ECOFF PDRs. */ | |
2192 | ||
2193 | the_bfd = sec->objfile->obfd; | |
2194 | if (priv == NULL | |
2195 | && (the_bfd->format == bfd_object | |
2196 | && bfd_get_flavour (the_bfd) == bfd_target_elf_flavour | |
2197 | && elf_elfheader (the_bfd)->e_ident[EI_CLASS] == ELFCLASS64)) | |
2198 | { | |
2199 | /* Right now GAS only outputs the address as a four-byte sequence. | |
2200 | This means that we should not bother with this method on 64-bit | |
2201 | targets (until that is fixed). */ | |
2202 | ||
2203 | priv = obstack_alloc (& sec->objfile->psymbol_obstack, | |
2204 | sizeof (struct mips_objfile_private)); | |
2205 | priv->size = 0; | |
2206 | sec->objfile->obj_private = priv; | |
2207 | } | |
2208 | else if (priv == NULL) | |
2209 | { | |
2210 | asection *bfdsec; | |
2211 | ||
2212 | priv = obstack_alloc (& sec->objfile->psymbol_obstack, | |
2213 | sizeof (struct mips_objfile_private)); | |
2214 | ||
2215 | bfdsec = bfd_get_section_by_name (sec->objfile->obfd, ".pdr"); | |
2216 | if (bfdsec != NULL) | |
2217 | { | |
2218 | priv->size = bfd_section_size (sec->objfile->obfd, bfdsec); | |
2219 | priv->contents = obstack_alloc (& sec->objfile->psymbol_obstack, | |
2220 | priv->size); | |
2221 | bfd_get_section_contents (sec->objfile->obfd, bfdsec, | |
2222 | priv->contents, 0, priv->size); | |
2223 | ||
2224 | /* In general, the .pdr section is sorted. However, in the | |
2225 | presence of multiple code sections (and other corner cases) | |
2226 | it can become unsorted. Sort it so that we can use a faster | |
2227 | binary search. */ | |
2228 | qsort (priv->contents, priv->size / 32, 32, compare_pdr_entries); | |
2229 | } | |
2230 | else | |
2231 | priv->size = 0; | |
2232 | ||
2233 | sec->objfile->obj_private = priv; | |
2234 | } | |
2235 | the_bfd = NULL; | |
2236 | ||
2237 | if (priv->size != 0) | |
2238 | { | |
2239 | int low, mid, high; | |
2240 | char *ptr; | |
2241 | ||
2242 | low = 0; | |
2243 | high = priv->size / 32; | |
2244 | ||
2245 | do | |
2246 | { | |
2247 | CORE_ADDR pdr_pc; | |
2248 | ||
2249 | mid = (low + high) / 2; | |
2250 | ||
2251 | ptr = priv->contents + mid * 32; | |
2252 | pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr); | |
2253 | pdr_pc += ANOFFSET (sec->objfile->section_offsets, | |
2254 | SECT_OFF_TEXT (sec->objfile)); | |
2255 | if (pdr_pc == startaddr) | |
2256 | break; | |
2257 | if (pdr_pc > startaddr) | |
2258 | high = mid; | |
2259 | else | |
2260 | low = mid + 1; | |
2261 | } | |
2262 | while (low != high); | |
2263 | ||
2264 | if (low != high) | |
2265 | { | |
2266 | struct symbol *sym = find_pc_function (pc); | |
2267 | ||
2268 | /* Fill in what we need of the proc_desc. */ | |
2269 | proc_desc = (mips_extra_func_info_t) | |
2270 | obstack_alloc (&sec->objfile->psymbol_obstack, | |
2271 | sizeof (struct mips_extra_func_info)); | |
2272 | PROC_LOW_ADDR (proc_desc) = startaddr; | |
2273 | ||
2274 | /* Only used for dummy frames. */ | |
2275 | PROC_HIGH_ADDR (proc_desc) = 0; | |
2276 | ||
2277 | PROC_FRAME_OFFSET (proc_desc) | |
2278 | = bfd_get_32 (sec->objfile->obfd, ptr + 20); | |
2279 | PROC_FRAME_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2280 | ptr + 24); | |
2281 | PROC_FRAME_ADJUST (proc_desc) = 0; | |
2282 | PROC_REG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2283 | ptr + 4); | |
2284 | PROC_FREG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2285 | ptr + 12); | |
2286 | PROC_REG_OFFSET (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2287 | ptr + 8); | |
2288 | PROC_FREG_OFFSET (proc_desc) | |
2289 | = bfd_get_32 (sec->objfile->obfd, ptr + 16); | |
2290 | PROC_PC_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2291 | ptr + 28); | |
2292 | proc_desc->pdr.isym = (long) sym; | |
2293 | ||
2294 | return proc_desc; | |
2295 | } | |
2296 | } | |
c906108c SS |
2297 | } |
2298 | ||
6c0d6680 DJ |
2299 | if (b == NULL) |
2300 | return NULL; | |
2301 | ||
2302 | if (startaddr > BLOCK_START (b)) | |
2303 | { | |
2304 | /* This is the "pathological" case referred to in a comment in | |
2305 | print_frame_info. It might be better to move this check into | |
2306 | symbol reading. */ | |
2307 | return NULL; | |
2308 | } | |
2309 | ||
2310 | sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_NAMESPACE, 0, NULL); | |
2311 | ||
c906108c SS |
2312 | /* If we never found a PDR for this function in symbol reading, then |
2313 | examine prologues to find the information. */ | |
2314 | if (sym) | |
2315 | { | |
2316 | proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); | |
2317 | if (PROC_FRAME_REG (proc_desc) == -1) | |
2318 | return NULL; | |
2319 | else | |
2320 | return proc_desc; | |
2321 | } | |
2322 | else | |
2323 | return NULL; | |
2324 | } | |
2325 | ||
2326 | ||
2327 | static mips_extra_func_info_t | |
479412cd | 2328 | find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame) |
c906108c SS |
2329 | { |
2330 | mips_extra_func_info_t proc_desc; | |
2331 | CORE_ADDR startaddr; | |
2332 | ||
2333 | proc_desc = non_heuristic_proc_desc (pc, &startaddr); | |
2334 | ||
2335 | if (proc_desc) | |
2336 | { | |
2337 | /* IF this is the topmost frame AND | |
2338 | * (this proc does not have debugging information OR | |
2339 | * the PC is in the procedure prologue) | |
2340 | * THEN create a "heuristic" proc_desc (by analyzing | |
2341 | * the actual code) to replace the "official" proc_desc. | |
2342 | */ | |
2343 | if (next_frame == NULL) | |
2344 | { | |
2345 | struct symtab_and_line val; | |
2346 | struct symbol *proc_symbol = | |
c86b5b38 | 2347 | PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc); |
c906108c SS |
2348 | |
2349 | if (proc_symbol) | |
2350 | { | |
2351 | val = find_pc_line (BLOCK_START | |
c5aa993b | 2352 | (SYMBOL_BLOCK_VALUE (proc_symbol)), |
c906108c SS |
2353 | 0); |
2354 | val.pc = val.end ? val.end : pc; | |
2355 | } | |
2356 | if (!proc_symbol || pc < val.pc) | |
2357 | { | |
2358 | mips_extra_func_info_t found_heuristic = | |
c86b5b38 MS |
2359 | heuristic_proc_desc (PROC_LOW_ADDR (proc_desc), |
2360 | pc, next_frame, cur_frame); | |
c906108c SS |
2361 | if (found_heuristic) |
2362 | proc_desc = found_heuristic; | |
2363 | } | |
2364 | } | |
2365 | } | |
2366 | else | |
2367 | { | |
2368 | /* Is linked_proc_desc_table really necessary? It only seems to be used | |
c5aa993b JM |
2369 | by procedure call dummys. However, the procedures being called ought |
2370 | to have their own proc_descs, and even if they don't, | |
2371 | heuristic_proc_desc knows how to create them! */ | |
c906108c SS |
2372 | |
2373 | register struct linked_proc_info *link; | |
2374 | ||
2375 | for (link = linked_proc_desc_table; link; link = link->next) | |
c5aa993b JM |
2376 | if (PROC_LOW_ADDR (&link->info) <= pc |
2377 | && PROC_HIGH_ADDR (&link->info) > pc) | |
c906108c SS |
2378 | return &link->info; |
2379 | ||
2380 | if (startaddr == 0) | |
2381 | startaddr = heuristic_proc_start (pc); | |
2382 | ||
2383 | proc_desc = | |
479412cd | 2384 | heuristic_proc_desc (startaddr, pc, next_frame, cur_frame); |
c906108c SS |
2385 | } |
2386 | return proc_desc; | |
2387 | } | |
2388 | ||
2389 | static CORE_ADDR | |
acdb74a0 AC |
2390 | get_frame_pointer (struct frame_info *frame, |
2391 | mips_extra_func_info_t proc_desc) | |
c906108c | 2392 | { |
c86b5b38 MS |
2393 | return ADDR_BITS_REMOVE (read_next_frame_reg (frame, |
2394 | PROC_FRAME_REG (proc_desc)) + | |
2395 | PROC_FRAME_OFFSET (proc_desc) - | |
2396 | PROC_FRAME_ADJUST (proc_desc)); | |
c906108c SS |
2397 | } |
2398 | ||
5a89d8aa | 2399 | static mips_extra_func_info_t cached_proc_desc; |
c906108c | 2400 | |
f7ab6ec6 | 2401 | static CORE_ADDR |
acdb74a0 | 2402 | mips_frame_chain (struct frame_info *frame) |
c906108c SS |
2403 | { |
2404 | mips_extra_func_info_t proc_desc; | |
2405 | CORE_ADDR tmp; | |
c5aa993b | 2406 | CORE_ADDR saved_pc = FRAME_SAVED_PC (frame); |
c906108c SS |
2407 | |
2408 | if (saved_pc == 0 || inside_entry_file (saved_pc)) | |
2409 | return 0; | |
2410 | ||
2411 | /* Check if the PC is inside a call stub. If it is, fetch the | |
2412 | PC of the caller of that stub. */ | |
5a89d8aa | 2413 | if ((tmp = SKIP_TRAMPOLINE_CODE (saved_pc)) != 0) |
c906108c SS |
2414 | saved_pc = tmp; |
2415 | ||
2416 | /* Look up the procedure descriptor for this PC. */ | |
479412cd | 2417 | proc_desc = find_proc_desc (saved_pc, frame, 1); |
c906108c SS |
2418 | if (!proc_desc) |
2419 | return 0; | |
2420 | ||
2421 | cached_proc_desc = proc_desc; | |
2422 | ||
2423 | /* If no frame pointer and frame size is zero, we must be at end | |
2424 | of stack (or otherwise hosed). If we don't check frame size, | |
2425 | we loop forever if we see a zero size frame. */ | |
2426 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM | |
2427 | && PROC_FRAME_OFFSET (proc_desc) == 0 | |
7807aa61 MS |
2428 | /* The previous frame from a sigtramp frame might be frameless |
2429 | and have frame size zero. */ | |
2430 | && !frame->signal_handler_caller | |
2431 | /* Check if this is a call dummy frame. */ | |
f7ab6ec6 | 2432 | && frame->pc != CALL_DUMMY_ADDRESS ()) |
c906108c SS |
2433 | return 0; |
2434 | else | |
2435 | return get_frame_pointer (frame, proc_desc); | |
2436 | } | |
2437 | ||
f7ab6ec6 | 2438 | static void |
acdb74a0 | 2439 | mips_init_extra_frame_info (int fromleaf, struct frame_info *fci) |
c906108c SS |
2440 | { |
2441 | int regnum; | |
2442 | ||
2443 | /* Use proc_desc calculated in frame_chain */ | |
2444 | mips_extra_func_info_t proc_desc = | |
c86b5b38 | 2445 | fci->next ? cached_proc_desc : find_proc_desc (fci->pc, fci->next, 1); |
c906108c | 2446 | |
cce74817 JM |
2447 | fci->extra_info = (struct frame_extra_info *) |
2448 | frame_obstack_alloc (sizeof (struct frame_extra_info)); | |
2449 | ||
c906108c | 2450 | fci->saved_regs = NULL; |
cce74817 | 2451 | fci->extra_info->proc_desc = |
c906108c SS |
2452 | proc_desc == &temp_proc_desc ? 0 : proc_desc; |
2453 | if (proc_desc) | |
2454 | { | |
2455 | /* Fixup frame-pointer - only needed for top frame */ | |
2456 | /* This may not be quite right, if proc has a real frame register. | |
c5aa993b JM |
2457 | Get the value of the frame relative sp, procedure might have been |
2458 | interrupted by a signal at it's very start. */ | |
c906108c SS |
2459 | if (fci->pc == PROC_LOW_ADDR (proc_desc) |
2460 | && !PROC_DESC_IS_DUMMY (proc_desc)) | |
2461 | fci->frame = read_next_frame_reg (fci->next, SP_REGNUM); | |
2462 | else | |
2463 | fci->frame = get_frame_pointer (fci->next, proc_desc); | |
2464 | ||
2465 | if (proc_desc == &temp_proc_desc) | |
2466 | { | |
2467 | char *name; | |
2468 | ||
2469 | /* Do not set the saved registers for a sigtramp frame, | |
2470 | mips_find_saved_registers will do that for us. | |
2471 | We can't use fci->signal_handler_caller, it is not yet set. */ | |
2472 | find_pc_partial_function (fci->pc, &name, | |
c5aa993b | 2473 | (CORE_ADDR *) NULL, (CORE_ADDR *) NULL); |
d7bd68ca | 2474 | if (!PC_IN_SIGTRAMP (fci->pc, name)) |
c906108c | 2475 | { |
c5aa993b | 2476 | frame_saved_regs_zalloc (fci); |
cce74817 | 2477 | memcpy (fci->saved_regs, temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
2478 | fci->saved_regs[PC_REGNUM] |
2479 | = fci->saved_regs[RA_REGNUM]; | |
ffabd70d KB |
2480 | /* Set value of previous frame's stack pointer. Remember that |
2481 | saved_regs[SP_REGNUM] is special in that it contains the | |
2482 | value of the stack pointer register. The other saved_regs | |
2483 | values are addresses (in the inferior) at which a given | |
2484 | register's value may be found. */ | |
2485 | fci->saved_regs[SP_REGNUM] = fci->frame; | |
c906108c SS |
2486 | } |
2487 | } | |
2488 | ||
2489 | /* hack: if argument regs are saved, guess these contain args */ | |
cce74817 JM |
2490 | /* assume we can't tell how many args for now */ |
2491 | fci->extra_info->num_args = -1; | |
c906108c SS |
2492 | for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--) |
2493 | { | |
c5aa993b | 2494 | if (PROC_REG_MASK (proc_desc) & (1 << regnum)) |
c906108c | 2495 | { |
cce74817 | 2496 | fci->extra_info->num_args = regnum - A0_REGNUM + 1; |
c906108c SS |
2497 | break; |
2498 | } | |
c5aa993b | 2499 | } |
c906108c SS |
2500 | } |
2501 | } | |
2502 | ||
2503 | /* MIPS stack frames are almost impenetrable. When execution stops, | |
2504 | we basically have to look at symbol information for the function | |
2505 | that we stopped in, which tells us *which* register (if any) is | |
2506 | the base of the frame pointer, and what offset from that register | |
361d1df0 | 2507 | the frame itself is at. |
c906108c SS |
2508 | |
2509 | This presents a problem when trying to examine a stack in memory | |
2510 | (that isn't executing at the moment), using the "frame" command. We | |
2511 | don't have a PC, nor do we have any registers except SP. | |
2512 | ||
2513 | This routine takes two arguments, SP and PC, and tries to make the | |
2514 | cached frames look as if these two arguments defined a frame on the | |
2515 | cache. This allows the rest of info frame to extract the important | |
2516 | arguments without difficulty. */ | |
2517 | ||
2518 | struct frame_info * | |
acdb74a0 | 2519 | setup_arbitrary_frame (int argc, CORE_ADDR *argv) |
c906108c SS |
2520 | { |
2521 | if (argc != 2) | |
2522 | error ("MIPS frame specifications require two arguments: sp and pc"); | |
2523 | ||
2524 | return create_new_frame (argv[0], argv[1]); | |
2525 | } | |
2526 | ||
f09ded24 AC |
2527 | /* According to the current ABI, should the type be passed in a |
2528 | floating-point register (assuming that there is space)? When there | |
2529 | is no FPU, FP are not even considered as possibile candidates for | |
2530 | FP registers and, consequently this returns false - forces FP | |
2531 | arguments into integer registers. */ | |
2532 | ||
2533 | static int | |
2534 | fp_register_arg_p (enum type_code typecode, struct type *arg_type) | |
2535 | { | |
2536 | return ((typecode == TYPE_CODE_FLT | |
2537 | || (MIPS_EABI | |
2538 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
2539 | && TYPE_NFIELDS (arg_type) == 1 | |
2540 | && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT)) | |
c86b5b38 | 2541 | && MIPS_FPU_TYPE != MIPS_FPU_NONE); |
f09ded24 AC |
2542 | } |
2543 | ||
49e790b0 DJ |
2544 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
2545 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
2546 | ||
2547 | static int | |
2548 | mips_type_needs_double_align (struct type *type) | |
2549 | { | |
2550 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2551 | |
49e790b0 DJ |
2552 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2553 | return 1; | |
2554 | else if (typecode == TYPE_CODE_STRUCT) | |
2555 | { | |
2556 | if (TYPE_NFIELDS (type) < 1) | |
2557 | return 0; | |
2558 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2559 | } | |
2560 | else if (typecode == TYPE_CODE_UNION) | |
2561 | { | |
361d1df0 | 2562 | int i, n; |
49e790b0 DJ |
2563 | |
2564 | n = TYPE_NFIELDS (type); | |
2565 | for (i = 0; i < n; i++) | |
2566 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2567 | return 1; | |
2568 | return 0; | |
2569 | } | |
2570 | return 0; | |
2571 | } | |
2572 | ||
cb3d25d1 MS |
2573 | /* Macros to round N up or down to the next A boundary; |
2574 | A must be a power of two. */ | |
2575 | ||
2576 | #define ROUND_DOWN(n,a) ((n) & ~((a)-1)) | |
2577 | #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1)) | |
2578 | ||
f7ab6ec6 | 2579 | static CORE_ADDR |
46e0f506 MS |
2580 | mips_eabi_push_arguments (int nargs, |
2581 | struct value **args, | |
2582 | CORE_ADDR sp, | |
2583 | int struct_return, | |
2584 | CORE_ADDR struct_addr) | |
c906108c SS |
2585 | { |
2586 | int argreg; | |
2587 | int float_argreg; | |
2588 | int argnum; | |
2589 | int len = 0; | |
2590 | int stack_offset = 0; | |
2591 | ||
c906108c | 2592 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2593 | are properly aligned. The stack has to be at least 64-bit |
2594 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2595 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2596 | aligned, so we round to this widest known alignment. */ | |
2597 | ||
c906108c | 2598 | sp = ROUND_DOWN (sp, 16); |
cce41527 | 2599 | struct_addr = ROUND_DOWN (struct_addr, 16); |
c5aa993b | 2600 | |
46e0f506 | 2601 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2602 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2603 | passed in registers, but that's OK. */ |
c906108c | 2604 | for (argnum = 0; argnum < nargs; argnum++) |
46e0f506 MS |
2605 | len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
2606 | MIPS_STACK_ARGSIZE); | |
c906108c SS |
2607 | sp -= ROUND_UP (len, 16); |
2608 | ||
9ace0497 | 2609 | if (mips_debug) |
46e0f506 MS |
2610 | fprintf_unfiltered (gdb_stdlog, |
2611 | "mips_eabi_push_arguments: sp=0x%s allocated %d\n", | |
cb3d25d1 | 2612 | paddr_nz (sp), ROUND_UP (len, 16)); |
9ace0497 | 2613 | |
c906108c SS |
2614 | /* Initialize the integer and float register pointers. */ |
2615 | argreg = A0_REGNUM; | |
2616 | float_argreg = FPA0_REGNUM; | |
2617 | ||
46e0f506 | 2618 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2619 | if (struct_return) |
9ace0497 AC |
2620 | { |
2621 | if (mips_debug) | |
2622 | fprintf_unfiltered (gdb_stdlog, | |
46e0f506 | 2623 | "mips_eabi_push_arguments: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 2624 | argreg, paddr_nz (struct_addr)); |
9ace0497 AC |
2625 | write_register (argreg++, struct_addr); |
2626 | } | |
c906108c SS |
2627 | |
2628 | /* Now load as many as possible of the first arguments into | |
2629 | registers, and push the rest onto the stack. Loop thru args | |
2630 | from first to last. */ | |
2631 | for (argnum = 0; argnum < nargs; argnum++) | |
2632 | { | |
2633 | char *val; | |
cb3d25d1 | 2634 | char *valbuf = alloca (MAX_REGISTER_RAW_SIZE); |
ea7c478f | 2635 | struct value *arg = args[argnum]; |
c906108c SS |
2636 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); |
2637 | int len = TYPE_LENGTH (arg_type); | |
2638 | enum type_code typecode = TYPE_CODE (arg_type); | |
2639 | ||
9ace0497 AC |
2640 | if (mips_debug) |
2641 | fprintf_unfiltered (gdb_stdlog, | |
46e0f506 | 2642 | "mips_eabi_push_arguments: %d len=%d type=%d", |
acdb74a0 | 2643 | argnum + 1, len, (int) typecode); |
9ace0497 | 2644 | |
c906108c | 2645 | /* The EABI passes structures that do not fit in a register by |
46e0f506 MS |
2646 | reference. */ |
2647 | if (len > MIPS_SAVED_REGSIZE | |
9ace0497 | 2648 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 2649 | { |
7a292a7a | 2650 | store_address (valbuf, MIPS_SAVED_REGSIZE, VALUE_ADDRESS (arg)); |
c906108c | 2651 | typecode = TYPE_CODE_PTR; |
7a292a7a | 2652 | len = MIPS_SAVED_REGSIZE; |
c906108c | 2653 | val = valbuf; |
9ace0497 AC |
2654 | if (mips_debug) |
2655 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
2656 | } |
2657 | else | |
c5aa993b | 2658 | val = (char *) VALUE_CONTENTS (arg); |
c906108c SS |
2659 | |
2660 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
2661 | even-numbered floating point register. Round the FP register |
2662 | up before the check to see if there are any FP registers | |
46e0f506 MS |
2663 | left. Non MIPS_EABI targets also pass the FP in the integer |
2664 | registers so also round up normal registers. */ | |
acdb74a0 AC |
2665 | if (!FP_REGISTER_DOUBLE |
2666 | && fp_register_arg_p (typecode, arg_type)) | |
2667 | { | |
2668 | if ((float_argreg & 1)) | |
2669 | float_argreg++; | |
2670 | } | |
c906108c SS |
2671 | |
2672 | /* Floating point arguments passed in registers have to be | |
2673 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2674 | are passed in register pairs; the even register gets |
2675 | the low word, and the odd register gets the high word. | |
2676 | On non-EABI processors, the first two floating point arguments are | |
2677 | also copied to general registers, because MIPS16 functions | |
2678 | don't use float registers for arguments. This duplication of | |
2679 | arguments in general registers can't hurt non-MIPS16 functions | |
2680 | because those registers are normally skipped. */ | |
1012bd0e EZ |
2681 | /* MIPS_EABI squeezes a struct that contains a single floating |
2682 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 2683 | stack. */ |
f09ded24 AC |
2684 | if (fp_register_arg_p (typecode, arg_type) |
2685 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
c906108c SS |
2686 | { |
2687 | if (!FP_REGISTER_DOUBLE && len == 8) | |
2688 | { | |
d7449b42 | 2689 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
c906108c SS |
2690 | unsigned long regval; |
2691 | ||
2692 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 2693 | regval = extract_unsigned_integer (val + low_offset, 4); |
9ace0497 | 2694 | if (mips_debug) |
acdb74a0 | 2695 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2696 | float_argreg, phex (regval, 4)); |
c906108c | 2697 | write_register (float_argreg++, regval); |
c906108c SS |
2698 | |
2699 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 2700 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
9ace0497 | 2701 | if (mips_debug) |
acdb74a0 | 2702 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2703 | float_argreg, phex (regval, 4)); |
c906108c | 2704 | write_register (float_argreg++, regval); |
c906108c SS |
2705 | } |
2706 | else | |
2707 | { | |
2708 | /* This is a floating point value that fits entirely | |
2709 | in a single register. */ | |
53a5351d | 2710 | /* On 32 bit ABI's the float_argreg is further adjusted |
46e0f506 | 2711 | above to ensure that it is even register aligned. */ |
9ace0497 AC |
2712 | LONGEST regval = extract_unsigned_integer (val, len); |
2713 | if (mips_debug) | |
acdb74a0 | 2714 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2715 | float_argreg, phex (regval, len)); |
c906108c | 2716 | write_register (float_argreg++, regval); |
c906108c SS |
2717 | } |
2718 | } | |
2719 | else | |
2720 | { | |
2721 | /* Copy the argument to general registers or the stack in | |
2722 | register-sized pieces. Large arguments are split between | |
2723 | registers and stack. */ | |
2724 | /* Note: structs whose size is not a multiple of MIPS_REGSIZE | |
2725 | are treated specially: Irix cc passes them in registers | |
2726 | where gcc sometimes puts them on the stack. For maximum | |
2727 | compatibility, we will put them in both places. */ | |
c5aa993b | 2728 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && |
7a292a7a | 2729 | (len % MIPS_SAVED_REGSIZE != 0)); |
46e0f506 | 2730 | |
f09ded24 | 2731 | /* Note: Floating-point values that didn't fit into an FP |
46e0f506 | 2732 | register are only written to memory. */ |
c906108c SS |
2733 | while (len > 0) |
2734 | { | |
ebafbe83 | 2735 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 2736 | int stack_used_p = 0; |
46e0f506 MS |
2737 | int partial_len = |
2738 | len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE; | |
c906108c | 2739 | |
acdb74a0 AC |
2740 | if (mips_debug) |
2741 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2742 | partial_len); | |
2743 | ||
566f0f7a | 2744 | /* Write this portion of the argument to the stack. */ |
f09ded24 AC |
2745 | if (argreg > MIPS_LAST_ARG_REGNUM |
2746 | || odd_sized_struct | |
2747 | || fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2748 | { |
c906108c SS |
2749 | /* Should shorter than int integer values be |
2750 | promoted to int before being stored? */ | |
c906108c | 2751 | int longword_offset = 0; |
9ace0497 | 2752 | CORE_ADDR addr; |
566f0f7a | 2753 | stack_used_p = 1; |
d7449b42 | 2754 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
7a292a7a | 2755 | { |
d929b26f | 2756 | if (MIPS_STACK_ARGSIZE == 8 && |
7a292a7a SS |
2757 | (typecode == TYPE_CODE_INT || |
2758 | typecode == TYPE_CODE_PTR || | |
2759 | typecode == TYPE_CODE_FLT) && len <= 4) | |
d929b26f | 2760 | longword_offset = MIPS_STACK_ARGSIZE - len; |
7a292a7a SS |
2761 | else if ((typecode == TYPE_CODE_STRUCT || |
2762 | typecode == TYPE_CODE_UNION) && | |
d929b26f AC |
2763 | TYPE_LENGTH (arg_type) < MIPS_STACK_ARGSIZE) |
2764 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
7a292a7a | 2765 | } |
c5aa993b | 2766 | |
9ace0497 AC |
2767 | if (mips_debug) |
2768 | { | |
cb3d25d1 MS |
2769 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", |
2770 | paddr_nz (stack_offset)); | |
2771 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
2772 | paddr_nz (longword_offset)); | |
9ace0497 | 2773 | } |
361d1df0 | 2774 | |
9ace0497 AC |
2775 | addr = sp + stack_offset + longword_offset; |
2776 | ||
2777 | if (mips_debug) | |
2778 | { | |
2779 | int i; | |
cb3d25d1 MS |
2780 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
2781 | paddr_nz (addr)); | |
9ace0497 AC |
2782 | for (i = 0; i < partial_len; i++) |
2783 | { | |
cb3d25d1 MS |
2784 | fprintf_unfiltered (gdb_stdlog, "%02x", |
2785 | val[i] & 0xff); | |
9ace0497 AC |
2786 | } |
2787 | } | |
2788 | write_memory (addr, val, partial_len); | |
c906108c SS |
2789 | } |
2790 | ||
f09ded24 AC |
2791 | /* Note!!! This is NOT an else clause. Odd sized |
2792 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 2793 | arguments will not. */ |
566f0f7a | 2794 | /* Write this portion of the argument to a general |
46e0f506 | 2795 | purpose register. */ |
f09ded24 AC |
2796 | if (argreg <= MIPS_LAST_ARG_REGNUM |
2797 | && !fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2798 | { |
9ace0497 | 2799 | LONGEST regval = extract_unsigned_integer (val, partial_len); |
c906108c | 2800 | |
9ace0497 | 2801 | if (mips_debug) |
acdb74a0 | 2802 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 AC |
2803 | argreg, |
2804 | phex (regval, MIPS_SAVED_REGSIZE)); | |
c906108c SS |
2805 | write_register (argreg, regval); |
2806 | argreg++; | |
c906108c | 2807 | } |
c5aa993b | 2808 | |
c906108c SS |
2809 | len -= partial_len; |
2810 | val += partial_len; | |
2811 | ||
566f0f7a AC |
2812 | /* Compute the the offset into the stack at which we |
2813 | will copy the next parameter. | |
2814 | ||
566f0f7a | 2815 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 2816 | only needs to be adjusted when it has been used. */ |
c906108c | 2817 | |
46e0f506 | 2818 | if (stack_used_p) |
d929b26f | 2819 | stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE); |
c906108c SS |
2820 | } |
2821 | } | |
9ace0497 AC |
2822 | if (mips_debug) |
2823 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
2824 | } |
2825 | ||
0f71a2f6 JM |
2826 | /* Return adjusted stack pointer. */ |
2827 | return sp; | |
2828 | } | |
2829 | ||
ebafbe83 MS |
2830 | /* N32/N64 version of push_arguments. */ |
2831 | ||
f7ab6ec6 | 2832 | static CORE_ADDR |
cb3d25d1 MS |
2833 | mips_n32n64_push_arguments (int nargs, |
2834 | struct value **args, | |
2835 | CORE_ADDR sp, | |
2836 | int struct_return, | |
2837 | CORE_ADDR struct_addr) | |
2838 | { | |
2839 | int argreg; | |
2840 | int float_argreg; | |
2841 | int argnum; | |
2842 | int len = 0; | |
2843 | int stack_offset = 0; | |
2844 | ||
2845 | /* First ensure that the stack and structure return address (if any) | |
2846 | are properly aligned. The stack has to be at least 64-bit | |
2847 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2848 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2849 | aligned, so we round to this widest known alignment. */ | |
2850 | ||
2851 | sp = ROUND_DOWN (sp, 16); | |
2852 | struct_addr = ROUND_DOWN (struct_addr, 16); | |
2853 | ||
2854 | /* Now make space on the stack for the args. */ | |
2855 | for (argnum = 0; argnum < nargs; argnum++) | |
2856 | len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])), | |
2857 | MIPS_STACK_ARGSIZE); | |
2858 | sp -= ROUND_UP (len, 16); | |
2859 | ||
2860 | if (mips_debug) | |
2861 | fprintf_unfiltered (gdb_stdlog, | |
2862 | "mips_n32n64_push_arguments: sp=0x%s allocated %d\n", | |
2863 | paddr_nz (sp), ROUND_UP (len, 16)); | |
2864 | ||
2865 | /* Initialize the integer and float register pointers. */ | |
2866 | argreg = A0_REGNUM; | |
2867 | float_argreg = FPA0_REGNUM; | |
2868 | ||
46e0f506 | 2869 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
2870 | if (struct_return) |
2871 | { | |
2872 | if (mips_debug) | |
2873 | fprintf_unfiltered (gdb_stdlog, | |
2874 | "mips_n32n64_push_arguments: struct_return reg=%d 0x%s\n", | |
2875 | argreg, paddr_nz (struct_addr)); | |
2876 | write_register (argreg++, struct_addr); | |
2877 | } | |
2878 | ||
2879 | /* Now load as many as possible of the first arguments into | |
2880 | registers, and push the rest onto the stack. Loop thru args | |
2881 | from first to last. */ | |
2882 | for (argnum = 0; argnum < nargs; argnum++) | |
2883 | { | |
2884 | char *val; | |
2885 | char *valbuf = alloca (MAX_REGISTER_RAW_SIZE); | |
2886 | struct value *arg = args[argnum]; | |
2887 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
2888 | int len = TYPE_LENGTH (arg_type); | |
2889 | enum type_code typecode = TYPE_CODE (arg_type); | |
2890 | ||
2891 | if (mips_debug) | |
2892 | fprintf_unfiltered (gdb_stdlog, | |
2893 | "mips_n32n64_push_arguments: %d len=%d type=%d", | |
2894 | argnum + 1, len, (int) typecode); | |
2895 | ||
2896 | val = (char *) VALUE_CONTENTS (arg); | |
2897 | ||
2898 | if (fp_register_arg_p (typecode, arg_type) | |
2899 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
2900 | { | |
2901 | /* This is a floating point value that fits entirely | |
2902 | in a single register. */ | |
2903 | /* On 32 bit ABI's the float_argreg is further adjusted | |
2904 | above to ensure that it is even register aligned. */ | |
2905 | LONGEST regval = extract_unsigned_integer (val, len); | |
2906 | if (mips_debug) | |
2907 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
2908 | float_argreg, phex (regval, len)); | |
2909 | write_register (float_argreg++, regval); | |
2910 | ||
2911 | if (mips_debug) | |
2912 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
2913 | argreg, phex (regval, len)); | |
2914 | write_register (argreg, regval); | |
2915 | argreg += 1; | |
2916 | } | |
2917 | else | |
2918 | { | |
2919 | /* Copy the argument to general registers or the stack in | |
2920 | register-sized pieces. Large arguments are split between | |
2921 | registers and stack. */ | |
2922 | /* Note: structs whose size is not a multiple of MIPS_REGSIZE | |
2923 | are treated specially: Irix cc passes them in registers | |
2924 | where gcc sometimes puts them on the stack. For maximum | |
2925 | compatibility, we will put them in both places. */ | |
2926 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && | |
2927 | (len % MIPS_SAVED_REGSIZE != 0)); | |
2928 | /* Note: Floating-point values that didn't fit into an FP | |
2929 | register are only written to memory. */ | |
2930 | while (len > 0) | |
2931 | { | |
2932 | /* Rememer if the argument was written to the stack. */ | |
2933 | int stack_used_p = 0; | |
2934 | int partial_len = len < MIPS_SAVED_REGSIZE ? | |
2935 | len : MIPS_SAVED_REGSIZE; | |
2936 | ||
2937 | if (mips_debug) | |
2938 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2939 | partial_len); | |
2940 | ||
2941 | /* Write this portion of the argument to the stack. */ | |
2942 | if (argreg > MIPS_LAST_ARG_REGNUM | |
2943 | || odd_sized_struct | |
2944 | || fp_register_arg_p (typecode, arg_type)) | |
2945 | { | |
2946 | /* Should shorter than int integer values be | |
2947 | promoted to int before being stored? */ | |
2948 | int longword_offset = 0; | |
2949 | CORE_ADDR addr; | |
2950 | stack_used_p = 1; | |
2951 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
2952 | { | |
2953 | if (MIPS_STACK_ARGSIZE == 8 && | |
2954 | (typecode == TYPE_CODE_INT || | |
2955 | typecode == TYPE_CODE_PTR || | |
2956 | typecode == TYPE_CODE_FLT) && len <= 4) | |
2957 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
2958 | else if ((typecode == TYPE_CODE_STRUCT || | |
2959 | typecode == TYPE_CODE_UNION) && | |
2960 | TYPE_LENGTH (arg_type) < MIPS_STACK_ARGSIZE) | |
2961 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
2962 | } | |
2963 | ||
2964 | if (mips_debug) | |
2965 | { | |
2966 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
2967 | paddr_nz (stack_offset)); | |
2968 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
2969 | paddr_nz (longword_offset)); | |
2970 | } | |
2971 | ||
2972 | addr = sp + stack_offset + longword_offset; | |
2973 | ||
2974 | if (mips_debug) | |
2975 | { | |
2976 | int i; | |
2977 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", | |
2978 | paddr_nz (addr)); | |
2979 | for (i = 0; i < partial_len; i++) | |
2980 | { | |
2981 | fprintf_unfiltered (gdb_stdlog, "%02x", | |
2982 | val[i] & 0xff); | |
2983 | } | |
2984 | } | |
2985 | write_memory (addr, val, partial_len); | |
2986 | } | |
2987 | ||
2988 | /* Note!!! This is NOT an else clause. Odd sized | |
2989 | structs may go thru BOTH paths. Floating point | |
2990 | arguments will not. */ | |
2991 | /* Write this portion of the argument to a general | |
2992 | purpose register. */ | |
2993 | if (argreg <= MIPS_LAST_ARG_REGNUM | |
2994 | && !fp_register_arg_p (typecode, arg_type)) | |
2995 | { | |
2996 | LONGEST regval = extract_unsigned_integer (val, partial_len); | |
2997 | ||
2998 | /* A non-floating-point argument being passed in a | |
2999 | general register. If a struct or union, and if | |
3000 | the remaining length is smaller than the register | |
3001 | size, we have to adjust the register value on | |
3002 | big endian targets. | |
3003 | ||
3004 | It does not seem to be necessary to do the | |
3005 | same for integral types. | |
3006 | ||
3007 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3008 | outputting LE O32 with sizeof (struct) < | |
3009 | MIPS_SAVED_REGSIZE, generates a left shift as | |
3010 | part of storing the argument in a register a | |
3011 | register (the left shift isn't generated when | |
3012 | sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it | |
3013 | is quite possible that this is GCC contradicting | |
3014 | the LE/O32 ABI, GDB has not been adjusted to | |
3015 | accommodate this. Either someone needs to | |
3016 | demonstrate that the LE/O32 ABI specifies such a | |
3017 | left shift OR this new ABI gets identified as | |
3018 | such and GDB gets tweaked accordingly. */ | |
3019 | ||
3020 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3021 | && partial_len < MIPS_SAVED_REGSIZE | |
3022 | && (typecode == TYPE_CODE_STRUCT || | |
3023 | typecode == TYPE_CODE_UNION)) | |
3024 | regval <<= ((MIPS_SAVED_REGSIZE - partial_len) * | |
3025 | TARGET_CHAR_BIT); | |
3026 | ||
3027 | if (mips_debug) | |
3028 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3029 | argreg, | |
3030 | phex (regval, MIPS_SAVED_REGSIZE)); | |
3031 | write_register (argreg, regval); | |
3032 | argreg++; | |
3033 | } | |
3034 | ||
3035 | len -= partial_len; | |
3036 | val += partial_len; | |
3037 | ||
3038 | /* Compute the the offset into the stack at which we | |
3039 | will copy the next parameter. | |
3040 | ||
3041 | In N32 (N64?), the stack_offset only needs to be | |
3042 | adjusted when it has been used. */ | |
3043 | ||
3044 | if (stack_used_p) | |
3045 | stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE); | |
3046 | } | |
3047 | } | |
3048 | if (mips_debug) | |
3049 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3050 | } | |
3051 | ||
3052 | /* Return adjusted stack pointer. */ | |
3053 | return sp; | |
3054 | } | |
3055 | ||
46cac009 | 3056 | /* O32 version of push_arguments. */ |
ebafbe83 | 3057 | |
46cac009 AC |
3058 | static CORE_ADDR |
3059 | mips_o32_push_arguments (int nargs, | |
3060 | struct value **args, | |
3061 | CORE_ADDR sp, | |
3062 | int struct_return, | |
3063 | CORE_ADDR struct_addr) | |
ebafbe83 MS |
3064 | { |
3065 | int argreg; | |
3066 | int float_argreg; | |
3067 | int argnum; | |
3068 | int len = 0; | |
3069 | int stack_offset = 0; | |
ebafbe83 MS |
3070 | |
3071 | /* First ensure that the stack and structure return address (if any) | |
3072 | are properly aligned. The stack has to be at least 64-bit | |
3073 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3074 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3075 | aligned, so we round to this widest known alignment. */ | |
3076 | ||
3077 | sp = ROUND_DOWN (sp, 16); | |
3078 | struct_addr = ROUND_DOWN (struct_addr, 16); | |
3079 | ||
3080 | /* Now make space on the stack for the args. */ | |
3081 | for (argnum = 0; argnum < nargs; argnum++) | |
3082 | len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])), | |
3083 | MIPS_STACK_ARGSIZE); | |
3084 | sp -= ROUND_UP (len, 16); | |
3085 | ||
3086 | if (mips_debug) | |
3087 | fprintf_unfiltered (gdb_stdlog, | |
46cac009 | 3088 | "mips_o32_push_arguments: sp=0x%s allocated %d\n", |
ebafbe83 MS |
3089 | paddr_nz (sp), ROUND_UP (len, 16)); |
3090 | ||
3091 | /* Initialize the integer and float register pointers. */ | |
3092 | argreg = A0_REGNUM; | |
3093 | float_argreg = FPA0_REGNUM; | |
3094 | ||
bcb0cc15 | 3095 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3096 | if (struct_return) |
3097 | { | |
3098 | if (mips_debug) | |
3099 | fprintf_unfiltered (gdb_stdlog, | |
46cac009 | 3100 | "mips_o32_push_arguments: struct_return reg=%d 0x%s\n", |
ebafbe83 MS |
3101 | argreg, paddr_nz (struct_addr)); |
3102 | write_register (argreg++, struct_addr); | |
3103 | stack_offset += MIPS_STACK_ARGSIZE; | |
3104 | } | |
3105 | ||
3106 | /* Now load as many as possible of the first arguments into | |
3107 | registers, and push the rest onto the stack. Loop thru args | |
3108 | from first to last. */ | |
3109 | for (argnum = 0; argnum < nargs; argnum++) | |
3110 | { | |
3111 | char *val; | |
3112 | char *valbuf = alloca (MAX_REGISTER_RAW_SIZE); | |
3113 | struct value *arg = args[argnum]; | |
3114 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3115 | int len = TYPE_LENGTH (arg_type); | |
3116 | enum type_code typecode = TYPE_CODE (arg_type); | |
3117 | ||
3118 | if (mips_debug) | |
3119 | fprintf_unfiltered (gdb_stdlog, | |
46cac009 AC |
3120 | "mips_o32_push_arguments: %d len=%d type=%d", |
3121 | argnum + 1, len, (int) typecode); | |
3122 | ||
3123 | val = (char *) VALUE_CONTENTS (arg); | |
3124 | ||
3125 | /* 32-bit ABIs always start floating point arguments in an | |
3126 | even-numbered floating point register. Round the FP register | |
3127 | up before the check to see if there are any FP registers | |
3128 | left. O32/O64 targets also pass the FP in the integer | |
3129 | registers so also round up normal registers. */ | |
3130 | if (!FP_REGISTER_DOUBLE | |
3131 | && fp_register_arg_p (typecode, arg_type)) | |
3132 | { | |
3133 | if ((float_argreg & 1)) | |
3134 | float_argreg++; | |
3135 | } | |
3136 | ||
3137 | /* Floating point arguments passed in registers have to be | |
3138 | treated specially. On 32-bit architectures, doubles | |
3139 | are passed in register pairs; the even register gets | |
3140 | the low word, and the odd register gets the high word. | |
3141 | On O32/O64, the first two floating point arguments are | |
3142 | also copied to general registers, because MIPS16 functions | |
3143 | don't use float registers for arguments. This duplication of | |
3144 | arguments in general registers can't hurt non-MIPS16 functions | |
3145 | because those registers are normally skipped. */ | |
3146 | ||
3147 | if (fp_register_arg_p (typecode, arg_type) | |
3148 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3149 | { | |
3150 | if (!FP_REGISTER_DOUBLE && len == 8) | |
3151 | { | |
3152 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
3153 | unsigned long regval; | |
3154 | ||
3155 | /* Write the low word of the double to the even register(s). */ | |
3156 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3157 | if (mips_debug) | |
3158 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3159 | float_argreg, phex (regval, 4)); | |
3160 | write_register (float_argreg++, regval); | |
3161 | if (mips_debug) | |
3162 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3163 | argreg, phex (regval, 4)); | |
3164 | write_register (argreg++, regval); | |
3165 | ||
3166 | /* Write the high word of the double to the odd register(s). */ | |
3167 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3168 | if (mips_debug) | |
3169 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3170 | float_argreg, phex (regval, 4)); | |
3171 | write_register (float_argreg++, regval); | |
3172 | ||
3173 | if (mips_debug) | |
3174 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3175 | argreg, phex (regval, 4)); | |
3176 | write_register (argreg++, regval); | |
3177 | } | |
3178 | else | |
3179 | { | |
3180 | /* This is a floating point value that fits entirely | |
3181 | in a single register. */ | |
3182 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3183 | above to ensure that it is even register aligned. */ | |
3184 | LONGEST regval = extract_unsigned_integer (val, len); | |
3185 | if (mips_debug) | |
3186 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3187 | float_argreg, phex (regval, len)); | |
3188 | write_register (float_argreg++, regval); | |
3189 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
3190 | registers for each argument. The below is (my | |
3191 | guess) to ensure that the corresponding integer | |
3192 | register has reserved the same space. */ | |
3193 | if (mips_debug) | |
3194 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3195 | argreg, phex (regval, len)); | |
3196 | write_register (argreg, regval); | |
3197 | argreg += FP_REGISTER_DOUBLE ? 1 : 2; | |
3198 | } | |
3199 | /* Reserve space for the FP register. */ | |
3200 | stack_offset += ROUND_UP (len, MIPS_STACK_ARGSIZE); | |
3201 | } | |
3202 | else | |
3203 | { | |
3204 | /* Copy the argument to general registers or the stack in | |
3205 | register-sized pieces. Large arguments are split between | |
3206 | registers and stack. */ | |
3207 | /* Note: structs whose size is not a multiple of MIPS_REGSIZE | |
3208 | are treated specially: Irix cc passes them in registers | |
3209 | where gcc sometimes puts them on the stack. For maximum | |
3210 | compatibility, we will put them in both places. */ | |
3211 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && | |
3212 | (len % MIPS_SAVED_REGSIZE != 0)); | |
3213 | /* Structures should be aligned to eight bytes (even arg registers) | |
3214 | on MIPS_ABI_O32, if their first member has double precision. */ | |
3215 | if (MIPS_SAVED_REGSIZE < 8 | |
3216 | && mips_type_needs_double_align (arg_type)) | |
3217 | { | |
3218 | if ((argreg & 1)) | |
3219 | argreg++; | |
3220 | } | |
3221 | /* Note: Floating-point values that didn't fit into an FP | |
3222 | register are only written to memory. */ | |
3223 | while (len > 0) | |
3224 | { | |
3225 | /* Remember if the argument was written to the stack. */ | |
3226 | int stack_used_p = 0; | |
3227 | int partial_len = | |
3228 | len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE; | |
3229 | ||
3230 | if (mips_debug) | |
3231 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3232 | partial_len); | |
3233 | ||
3234 | /* Write this portion of the argument to the stack. */ | |
3235 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3236 | || odd_sized_struct | |
3237 | || fp_register_arg_p (typecode, arg_type)) | |
3238 | { | |
3239 | /* Should shorter than int integer values be | |
3240 | promoted to int before being stored? */ | |
3241 | int longword_offset = 0; | |
3242 | CORE_ADDR addr; | |
3243 | stack_used_p = 1; | |
3244 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3245 | { | |
3246 | if (MIPS_STACK_ARGSIZE == 8 && | |
3247 | (typecode == TYPE_CODE_INT || | |
3248 | typecode == TYPE_CODE_PTR || | |
3249 | typecode == TYPE_CODE_FLT) && len <= 4) | |
3250 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
3251 | } | |
3252 | ||
3253 | if (mips_debug) | |
3254 | { | |
3255 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3256 | paddr_nz (stack_offset)); | |
3257 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3258 | paddr_nz (longword_offset)); | |
3259 | } | |
3260 | ||
3261 | addr = sp + stack_offset + longword_offset; | |
3262 | ||
3263 | if (mips_debug) | |
3264 | { | |
3265 | int i; | |
3266 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", | |
3267 | paddr_nz (addr)); | |
3268 | for (i = 0; i < partial_len; i++) | |
3269 | { | |
3270 | fprintf_unfiltered (gdb_stdlog, "%02x", | |
3271 | val[i] & 0xff); | |
3272 | } | |
3273 | } | |
3274 | write_memory (addr, val, partial_len); | |
3275 | } | |
3276 | ||
3277 | /* Note!!! This is NOT an else clause. Odd sized | |
3278 | structs may go thru BOTH paths. Floating point | |
3279 | arguments will not. */ | |
3280 | /* Write this portion of the argument to a general | |
3281 | purpose register. */ | |
3282 | if (argreg <= MIPS_LAST_ARG_REGNUM | |
3283 | && !fp_register_arg_p (typecode, arg_type)) | |
3284 | { | |
3285 | LONGEST regval = extract_signed_integer (val, partial_len); | |
3286 | /* Value may need to be sign extended, because | |
3287 | MIPS_REGSIZE != MIPS_SAVED_REGSIZE. */ | |
3288 | ||
3289 | /* A non-floating-point argument being passed in a | |
3290 | general register. If a struct or union, and if | |
3291 | the remaining length is smaller than the register | |
3292 | size, we have to adjust the register value on | |
3293 | big endian targets. | |
3294 | ||
3295 | It does not seem to be necessary to do the | |
3296 | same for integral types. | |
3297 | ||
3298 | Also don't do this adjustment on O64 binaries. | |
3299 | ||
3300 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3301 | outputting LE O32 with sizeof (struct) < | |
3302 | MIPS_SAVED_REGSIZE, generates a left shift as | |
3303 | part of storing the argument in a register a | |
3304 | register (the left shift isn't generated when | |
3305 | sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it | |
3306 | is quite possible that this is GCC contradicting | |
3307 | the LE/O32 ABI, GDB has not been adjusted to | |
3308 | accommodate this. Either someone needs to | |
3309 | demonstrate that the LE/O32 ABI specifies such a | |
3310 | left shift OR this new ABI gets identified as | |
3311 | such and GDB gets tweaked accordingly. */ | |
3312 | ||
3313 | if (MIPS_SAVED_REGSIZE < 8 | |
3314 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3315 | && partial_len < MIPS_SAVED_REGSIZE | |
3316 | && (typecode == TYPE_CODE_STRUCT || | |
3317 | typecode == TYPE_CODE_UNION)) | |
3318 | regval <<= ((MIPS_SAVED_REGSIZE - partial_len) * | |
3319 | TARGET_CHAR_BIT); | |
3320 | ||
3321 | if (mips_debug) | |
3322 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3323 | argreg, | |
3324 | phex (regval, MIPS_SAVED_REGSIZE)); | |
3325 | write_register (argreg, regval); | |
3326 | argreg++; | |
3327 | ||
3328 | /* Prevent subsequent floating point arguments from | |
3329 | being passed in floating point registers. */ | |
3330 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3331 | } | |
3332 | ||
3333 | len -= partial_len; | |
3334 | val += partial_len; | |
3335 | ||
3336 | /* Compute the the offset into the stack at which we | |
3337 | will copy the next parameter. | |
3338 | ||
3339 | In older ABIs, the caller reserved space for | |
3340 | registers that contained arguments. This was loosely | |
3341 | refered to as their "home". Consequently, space is | |
3342 | always allocated. */ | |
3343 | ||
3344 | stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE); | |
3345 | } | |
3346 | } | |
3347 | if (mips_debug) | |
3348 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3349 | } | |
3350 | ||
3351 | /* Return adjusted stack pointer. */ | |
3352 | return sp; | |
3353 | } | |
3354 | ||
3355 | /* O64 version of push_arguments. */ | |
3356 | ||
3357 | static CORE_ADDR | |
3358 | mips_o64_push_arguments (int nargs, | |
3359 | struct value **args, | |
3360 | CORE_ADDR sp, | |
3361 | int struct_return, | |
3362 | CORE_ADDR struct_addr) | |
3363 | { | |
3364 | int argreg; | |
3365 | int float_argreg; | |
3366 | int argnum; | |
3367 | int len = 0; | |
3368 | int stack_offset = 0; | |
3369 | ||
3370 | /* First ensure that the stack and structure return address (if any) | |
3371 | are properly aligned. The stack has to be at least 64-bit | |
3372 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3373 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3374 | aligned, so we round to this widest known alignment. */ | |
3375 | ||
3376 | sp = ROUND_DOWN (sp, 16); | |
3377 | struct_addr = ROUND_DOWN (struct_addr, 16); | |
3378 | ||
3379 | /* Now make space on the stack for the args. */ | |
3380 | for (argnum = 0; argnum < nargs; argnum++) | |
3381 | len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])), | |
3382 | MIPS_STACK_ARGSIZE); | |
3383 | sp -= ROUND_UP (len, 16); | |
3384 | ||
3385 | if (mips_debug) | |
3386 | fprintf_unfiltered (gdb_stdlog, | |
3387 | "mips_o64_push_arguments: sp=0x%s allocated %d\n", | |
3388 | paddr_nz (sp), ROUND_UP (len, 16)); | |
3389 | ||
3390 | /* Initialize the integer and float register pointers. */ | |
3391 | argreg = A0_REGNUM; | |
3392 | float_argreg = FPA0_REGNUM; | |
3393 | ||
3394 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
3395 | if (struct_return) | |
3396 | { | |
3397 | if (mips_debug) | |
3398 | fprintf_unfiltered (gdb_stdlog, | |
3399 | "mips_o64_push_arguments: struct_return reg=%d 0x%s\n", | |
3400 | argreg, paddr_nz (struct_addr)); | |
3401 | write_register (argreg++, struct_addr); | |
3402 | stack_offset += MIPS_STACK_ARGSIZE; | |
3403 | } | |
3404 | ||
3405 | /* Now load as many as possible of the first arguments into | |
3406 | registers, and push the rest onto the stack. Loop thru args | |
3407 | from first to last. */ | |
3408 | for (argnum = 0; argnum < nargs; argnum++) | |
3409 | { | |
3410 | char *val; | |
3411 | char *valbuf = alloca (MAX_REGISTER_RAW_SIZE); | |
3412 | struct value *arg = args[argnum]; | |
3413 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3414 | int len = TYPE_LENGTH (arg_type); | |
3415 | enum type_code typecode = TYPE_CODE (arg_type); | |
3416 | ||
3417 | if (mips_debug) | |
3418 | fprintf_unfiltered (gdb_stdlog, | |
3419 | "mips_o64_push_arguments: %d len=%d type=%d", | |
ebafbe83 MS |
3420 | argnum + 1, len, (int) typecode); |
3421 | ||
3422 | val = (char *) VALUE_CONTENTS (arg); | |
3423 | ||
3424 | /* 32-bit ABIs always start floating point arguments in an | |
3425 | even-numbered floating point register. Round the FP register | |
3426 | up before the check to see if there are any FP registers | |
3427 | left. O32/O64 targets also pass the FP in the integer | |
3428 | registers so also round up normal registers. */ | |
3429 | if (!FP_REGISTER_DOUBLE | |
3430 | && fp_register_arg_p (typecode, arg_type)) | |
3431 | { | |
3432 | if ((float_argreg & 1)) | |
3433 | float_argreg++; | |
3434 | } | |
3435 | ||
3436 | /* Floating point arguments passed in registers have to be | |
3437 | treated specially. On 32-bit architectures, doubles | |
3438 | are passed in register pairs; the even register gets | |
3439 | the low word, and the odd register gets the high word. | |
3440 | On O32/O64, the first two floating point arguments are | |
3441 | also copied to general registers, because MIPS16 functions | |
3442 | don't use float registers for arguments. This duplication of | |
3443 | arguments in general registers can't hurt non-MIPS16 functions | |
3444 | because those registers are normally skipped. */ | |
3445 | ||
3446 | if (fp_register_arg_p (typecode, arg_type) | |
3447 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3448 | { | |
3449 | if (!FP_REGISTER_DOUBLE && len == 8) | |
3450 | { | |
3451 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
3452 | unsigned long regval; | |
3453 | ||
3454 | /* Write the low word of the double to the even register(s). */ | |
3455 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3456 | if (mips_debug) | |
3457 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3458 | float_argreg, phex (regval, 4)); | |
3459 | write_register (float_argreg++, regval); | |
3460 | if (mips_debug) | |
3461 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3462 | argreg, phex (regval, 4)); | |
3463 | write_register (argreg++, regval); | |
3464 | ||
3465 | /* Write the high word of the double to the odd register(s). */ | |
3466 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3467 | if (mips_debug) | |
3468 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3469 | float_argreg, phex (regval, 4)); | |
3470 | write_register (float_argreg++, regval); | |
3471 | ||
3472 | if (mips_debug) | |
3473 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3474 | argreg, phex (regval, 4)); | |
3475 | write_register (argreg++, regval); | |
3476 | } | |
3477 | else | |
3478 | { | |
3479 | /* This is a floating point value that fits entirely | |
3480 | in a single register. */ | |
3481 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3482 | above to ensure that it is even register aligned. */ | |
3483 | LONGEST regval = extract_unsigned_integer (val, len); | |
3484 | if (mips_debug) | |
3485 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3486 | float_argreg, phex (regval, len)); | |
3487 | write_register (float_argreg++, regval); | |
3488 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
3489 | registers for each argument. The below is (my | |
3490 | guess) to ensure that the corresponding integer | |
3491 | register has reserved the same space. */ | |
3492 | if (mips_debug) | |
3493 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3494 | argreg, phex (regval, len)); | |
3495 | write_register (argreg, regval); | |
3496 | argreg += FP_REGISTER_DOUBLE ? 1 : 2; | |
3497 | } | |
3498 | /* Reserve space for the FP register. */ | |
3499 | stack_offset += ROUND_UP (len, MIPS_STACK_ARGSIZE); | |
3500 | } | |
3501 | else | |
3502 | { | |
3503 | /* Copy the argument to general registers or the stack in | |
3504 | register-sized pieces. Large arguments are split between | |
3505 | registers and stack. */ | |
3506 | /* Note: structs whose size is not a multiple of MIPS_REGSIZE | |
3507 | are treated specially: Irix cc passes them in registers | |
3508 | where gcc sometimes puts them on the stack. For maximum | |
3509 | compatibility, we will put them in both places. */ | |
3510 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && | |
3511 | (len % MIPS_SAVED_REGSIZE != 0)); | |
3512 | /* Structures should be aligned to eight bytes (even arg registers) | |
3513 | on MIPS_ABI_O32, if their first member has double precision. */ | |
3514 | if (MIPS_SAVED_REGSIZE < 8 | |
3515 | && mips_type_needs_double_align (arg_type)) | |
3516 | { | |
3517 | if ((argreg & 1)) | |
3518 | argreg++; | |
3519 | } | |
3520 | /* Note: Floating-point values that didn't fit into an FP | |
3521 | register are only written to memory. */ | |
3522 | while (len > 0) | |
3523 | { | |
3524 | /* Remember if the argument was written to the stack. */ | |
3525 | int stack_used_p = 0; | |
3526 | int partial_len = | |
3527 | len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE; | |
3528 | ||
3529 | if (mips_debug) | |
3530 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3531 | partial_len); | |
3532 | ||
3533 | /* Write this portion of the argument to the stack. */ | |
3534 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3535 | || odd_sized_struct | |
3536 | || fp_register_arg_p (typecode, arg_type)) | |
3537 | { | |
3538 | /* Should shorter than int integer values be | |
3539 | promoted to int before being stored? */ | |
3540 | int longword_offset = 0; | |
3541 | CORE_ADDR addr; | |
3542 | stack_used_p = 1; | |
3543 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3544 | { | |
3545 | if (MIPS_STACK_ARGSIZE == 8 && | |
3546 | (typecode == TYPE_CODE_INT || | |
3547 | typecode == TYPE_CODE_PTR || | |
3548 | typecode == TYPE_CODE_FLT) && len <= 4) | |
3549 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
3550 | } | |
3551 | ||
3552 | if (mips_debug) | |
3553 | { | |
3554 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3555 | paddr_nz (stack_offset)); | |
3556 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3557 | paddr_nz (longword_offset)); | |
3558 | } | |
3559 | ||
3560 | addr = sp + stack_offset + longword_offset; | |
3561 | ||
3562 | if (mips_debug) | |
3563 | { | |
3564 | int i; | |
3565 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", | |
3566 | paddr_nz (addr)); | |
3567 | for (i = 0; i < partial_len; i++) | |
3568 | { | |
3569 | fprintf_unfiltered (gdb_stdlog, "%02x", | |
3570 | val[i] & 0xff); | |
3571 | } | |
3572 | } | |
3573 | write_memory (addr, val, partial_len); | |
3574 | } | |
3575 | ||
3576 | /* Note!!! This is NOT an else clause. Odd sized | |
3577 | structs may go thru BOTH paths. Floating point | |
3578 | arguments will not. */ | |
3579 | /* Write this portion of the argument to a general | |
3580 | purpose register. */ | |
3581 | if (argreg <= MIPS_LAST_ARG_REGNUM | |
3582 | && !fp_register_arg_p (typecode, arg_type)) | |
3583 | { | |
3584 | LONGEST regval = extract_signed_integer (val, partial_len); | |
3585 | /* Value may need to be sign extended, because | |
3586 | MIPS_REGSIZE != MIPS_SAVED_REGSIZE. */ | |
3587 | ||
3588 | /* A non-floating-point argument being passed in a | |
3589 | general register. If a struct or union, and if | |
3590 | the remaining length is smaller than the register | |
3591 | size, we have to adjust the register value on | |
3592 | big endian targets. | |
3593 | ||
3594 | It does not seem to be necessary to do the | |
3595 | same for integral types. | |
3596 | ||
3597 | Also don't do this adjustment on O64 binaries. | |
3598 | ||
3599 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3600 | outputting LE O32 with sizeof (struct) < | |
3601 | MIPS_SAVED_REGSIZE, generates a left shift as | |
3602 | part of storing the argument in a register a | |
3603 | register (the left shift isn't generated when | |
3604 | sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it | |
3605 | is quite possible that this is GCC contradicting | |
3606 | the LE/O32 ABI, GDB has not been adjusted to | |
3607 | accommodate this. Either someone needs to | |
3608 | demonstrate that the LE/O32 ABI specifies such a | |
3609 | left shift OR this new ABI gets identified as | |
3610 | such and GDB gets tweaked accordingly. */ | |
3611 | ||
3612 | if (MIPS_SAVED_REGSIZE < 8 | |
3613 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3614 | && partial_len < MIPS_SAVED_REGSIZE | |
3615 | && (typecode == TYPE_CODE_STRUCT || | |
3616 | typecode == TYPE_CODE_UNION)) | |
3617 | regval <<= ((MIPS_SAVED_REGSIZE - partial_len) * | |
3618 | TARGET_CHAR_BIT); | |
3619 | ||
3620 | if (mips_debug) | |
3621 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3622 | argreg, | |
3623 | phex (regval, MIPS_SAVED_REGSIZE)); | |
3624 | write_register (argreg, regval); | |
3625 | argreg++; | |
3626 | ||
3627 | /* Prevent subsequent floating point arguments from | |
3628 | being passed in floating point registers. */ | |
3629 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3630 | } | |
3631 | ||
3632 | len -= partial_len; | |
3633 | val += partial_len; | |
3634 | ||
3635 | /* Compute the the offset into the stack at which we | |
3636 | will copy the next parameter. | |
3637 | ||
3638 | In older ABIs, the caller reserved space for | |
3639 | registers that contained arguments. This was loosely | |
3640 | refered to as their "home". Consequently, space is | |
3641 | always allocated. */ | |
3642 | ||
3643 | stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE); | |
3644 | } | |
3645 | } | |
3646 | if (mips_debug) | |
3647 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3648 | } | |
3649 | ||
3650 | /* Return adjusted stack pointer. */ | |
3651 | return sp; | |
3652 | } | |
3653 | ||
f7ab6ec6 | 3654 | static CORE_ADDR |
acdb74a0 | 3655 | mips_push_return_address (CORE_ADDR pc, CORE_ADDR sp) |
0f71a2f6 | 3656 | { |
c906108c SS |
3657 | /* Set the return address register to point to the entry |
3658 | point of the program, where a breakpoint lies in wait. */ | |
c5aa993b | 3659 | write_register (RA_REGNUM, CALL_DUMMY_ADDRESS ()); |
c906108c SS |
3660 | return sp; |
3661 | } | |
3662 | ||
3663 | static void | |
c5aa993b | 3664 | mips_push_register (CORE_ADDR * sp, int regno) |
c906108c | 3665 | { |
cb3d25d1 | 3666 | char *buffer = alloca (MAX_REGISTER_RAW_SIZE); |
7a292a7a SS |
3667 | int regsize; |
3668 | int offset; | |
3669 | if (MIPS_SAVED_REGSIZE < REGISTER_RAW_SIZE (regno)) | |
3670 | { | |
3671 | regsize = MIPS_SAVED_REGSIZE; | |
d7449b42 | 3672 | offset = (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
3673 | ? REGISTER_RAW_SIZE (regno) - MIPS_SAVED_REGSIZE |
3674 | : 0); | |
3675 | } | |
3676 | else | |
3677 | { | |
3678 | regsize = REGISTER_RAW_SIZE (regno); | |
3679 | offset = 0; | |
3680 | } | |
c906108c SS |
3681 | *sp -= regsize; |
3682 | read_register_gen (regno, buffer); | |
7a292a7a | 3683 | write_memory (*sp, buffer + offset, regsize); |
c906108c SS |
3684 | } |
3685 | ||
3686 | /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */ | |
3687 | #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1)) | |
3688 | ||
f7ab6ec6 | 3689 | static void |
acdb74a0 | 3690 | mips_push_dummy_frame (void) |
c906108c SS |
3691 | { |
3692 | int ireg; | |
c5aa993b JM |
3693 | struct linked_proc_info *link = (struct linked_proc_info *) |
3694 | xmalloc (sizeof (struct linked_proc_info)); | |
c906108c | 3695 | mips_extra_func_info_t proc_desc = &link->info; |
6c997a34 | 3696 | CORE_ADDR sp = ADDR_BITS_REMOVE (read_signed_register (SP_REGNUM)); |
c906108c SS |
3697 | CORE_ADDR old_sp = sp; |
3698 | link->next = linked_proc_desc_table; | |
3699 | linked_proc_desc_table = link; | |
3700 | ||
3701 | /* FIXME! are these correct ? */ | |
c5aa993b | 3702 | #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */ |
c906108c SS |
3703 | #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1)) |
3704 | #define FLOAT_REG_SAVE_MASK MASK(0,19) | |
3705 | #define FLOAT_SINGLE_REG_SAVE_MASK \ | |
3706 | ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0)) | |
3707 | /* | |
3708 | * The registers we must save are all those not preserved across | |
3709 | * procedure calls. Dest_Reg (see tm-mips.h) must also be saved. | |
3710 | * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI | |
3711 | * and FP Control/Status registers. | |
361d1df0 | 3712 | * |
c906108c SS |
3713 | * |
3714 | * Dummy frame layout: | |
3715 | * (high memory) | |
c5aa993b JM |
3716 | * Saved PC |
3717 | * Saved MMHI, MMLO, FPC_CSR | |
3718 | * Saved R31 | |
3719 | * Saved R28 | |
3720 | * ... | |
3721 | * Saved R1 | |
c906108c SS |
3722 | * Saved D18 (i.e. F19, F18) |
3723 | * ... | |
3724 | * Saved D0 (i.e. F1, F0) | |
c5aa993b | 3725 | * Argument build area and stack arguments written via mips_push_arguments |
c906108c SS |
3726 | * (low memory) |
3727 | */ | |
3728 | ||
3729 | /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */ | |
c5aa993b JM |
3730 | PROC_FRAME_REG (proc_desc) = PUSH_FP_REGNUM; |
3731 | PROC_FRAME_OFFSET (proc_desc) = 0; | |
3732 | PROC_FRAME_ADJUST (proc_desc) = 0; | |
c906108c SS |
3733 | mips_push_register (&sp, PC_REGNUM); |
3734 | mips_push_register (&sp, HI_REGNUM); | |
3735 | mips_push_register (&sp, LO_REGNUM); | |
3736 | mips_push_register (&sp, MIPS_FPU_TYPE == MIPS_FPU_NONE ? 0 : FCRCS_REGNUM); | |
3737 | ||
3738 | /* Save general CPU registers */ | |
c5aa993b | 3739 | PROC_REG_MASK (proc_desc) = GEN_REG_SAVE_MASK; |
c906108c | 3740 | /* PROC_REG_OFFSET is the offset of the first saved register from FP. */ |
c5aa993b JM |
3741 | PROC_REG_OFFSET (proc_desc) = sp - old_sp - MIPS_SAVED_REGSIZE; |
3742 | for (ireg = 32; --ireg >= 0;) | |
3743 | if (PROC_REG_MASK (proc_desc) & (1 << ireg)) | |
c906108c SS |
3744 | mips_push_register (&sp, ireg); |
3745 | ||
3746 | /* Save floating point registers starting with high order word */ | |
c5aa993b | 3747 | PROC_FREG_MASK (proc_desc) = |
c906108c SS |
3748 | MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? FLOAT_REG_SAVE_MASK |
3749 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? FLOAT_SINGLE_REG_SAVE_MASK : 0; | |
3750 | /* PROC_FREG_OFFSET is the offset of the first saved *double* register | |
3751 | from FP. */ | |
c5aa993b JM |
3752 | PROC_FREG_OFFSET (proc_desc) = sp - old_sp - 8; |
3753 | for (ireg = 32; --ireg >= 0;) | |
3754 | if (PROC_FREG_MASK (proc_desc) & (1 << ireg)) | |
c906108c SS |
3755 | mips_push_register (&sp, ireg + FP0_REGNUM); |
3756 | ||
3757 | /* Update the frame pointer for the call dummy and the stack pointer. | |
3758 | Set the procedure's starting and ending addresses to point to the | |
3759 | call dummy address at the entry point. */ | |
3760 | write_register (PUSH_FP_REGNUM, old_sp); | |
3761 | write_register (SP_REGNUM, sp); | |
c5aa993b JM |
3762 | PROC_LOW_ADDR (proc_desc) = CALL_DUMMY_ADDRESS (); |
3763 | PROC_HIGH_ADDR (proc_desc) = CALL_DUMMY_ADDRESS () + 4; | |
3764 | SET_PROC_DESC_IS_DUMMY (proc_desc); | |
3765 | PROC_PC_REG (proc_desc) = RA_REGNUM; | |
c906108c SS |
3766 | } |
3767 | ||
f7ab6ec6 | 3768 | static void |
acdb74a0 | 3769 | mips_pop_frame (void) |
c906108c SS |
3770 | { |
3771 | register int regnum; | |
3772 | struct frame_info *frame = get_current_frame (); | |
3773 | CORE_ADDR new_sp = FRAME_FP (frame); | |
3774 | ||
cce74817 | 3775 | mips_extra_func_info_t proc_desc = frame->extra_info->proc_desc; |
c906108c | 3776 | |
c5aa993b | 3777 | write_register (PC_REGNUM, FRAME_SAVED_PC (frame)); |
c906108c | 3778 | if (frame->saved_regs == NULL) |
ffabd70d | 3779 | FRAME_INIT_SAVED_REGS (frame); |
c906108c | 3780 | for (regnum = 0; regnum < NUM_REGS; regnum++) |
e41b17f0 MS |
3781 | { |
3782 | if (regnum != SP_REGNUM && regnum != PC_REGNUM | |
3783 | && frame->saved_regs[regnum]) | |
3784 | write_register (regnum, | |
3785 | read_memory_integer (frame->saved_regs[regnum], | |
3786 | MIPS_SAVED_REGSIZE)); | |
3787 | } | |
757a7cc6 | 3788 | |
c906108c SS |
3789 | write_register (SP_REGNUM, new_sp); |
3790 | flush_cached_frames (); | |
3791 | ||
c5aa993b | 3792 | if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) |
c906108c SS |
3793 | { |
3794 | struct linked_proc_info *pi_ptr, *prev_ptr; | |
3795 | ||
3796 | for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL; | |
3797 | pi_ptr != NULL; | |
3798 | prev_ptr = pi_ptr, pi_ptr = pi_ptr->next) | |
3799 | { | |
3800 | if (&pi_ptr->info == proc_desc) | |
3801 | break; | |
3802 | } | |
3803 | ||
3804 | if (pi_ptr == NULL) | |
3805 | error ("Can't locate dummy extra frame info\n"); | |
3806 | ||
3807 | if (prev_ptr != NULL) | |
3808 | prev_ptr->next = pi_ptr->next; | |
3809 | else | |
3810 | linked_proc_desc_table = pi_ptr->next; | |
3811 | ||
b8c9b27d | 3812 | xfree (pi_ptr); |
c906108c SS |
3813 | |
3814 | write_register (HI_REGNUM, | |
c5aa993b | 3815 | read_memory_integer (new_sp - 2 * MIPS_SAVED_REGSIZE, |
7a292a7a | 3816 | MIPS_SAVED_REGSIZE)); |
c906108c | 3817 | write_register (LO_REGNUM, |
c5aa993b | 3818 | read_memory_integer (new_sp - 3 * MIPS_SAVED_REGSIZE, |
7a292a7a | 3819 | MIPS_SAVED_REGSIZE)); |
c906108c SS |
3820 | if (MIPS_FPU_TYPE != MIPS_FPU_NONE) |
3821 | write_register (FCRCS_REGNUM, | |
c5aa993b | 3822 | read_memory_integer (new_sp - 4 * MIPS_SAVED_REGSIZE, |
7a292a7a | 3823 | MIPS_SAVED_REGSIZE)); |
c906108c SS |
3824 | } |
3825 | } | |
3826 | ||
f7ab6ec6 MS |
3827 | static void |
3828 | mips_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs, | |
3829 | struct value **args, struct type *type, int gcc_p) | |
3830 | { | |
3831 | write_register(T9_REGNUM, fun); | |
3832 | } | |
3833 | ||
dd824b04 DJ |
3834 | /* Floating point register management. |
3835 | ||
3836 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
3837 | 64bit operations, these early MIPS cpus treat fp register pairs | |
3838 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
3839 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
3840 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
3841 | double precision floats into two 32-bit chunks and store them in | |
3842 | consecutive fp regs. To display 64-bit floats stored in this | |
3843 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
3844 | Throw in user-configurable endianness and you have a real mess. | |
3845 | ||
3846 | The way this works is: | |
3847 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
3848 | double-precision value will be split across two logical registers. | |
3849 | The lower-numbered logical register will hold the low-order bits, | |
3850 | regardless of the processor's endianness. | |
3851 | - If we are on a 64-bit processor, and we are looking for a | |
3852 | single-precision value, it will be in the low ordered bits | |
3853 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
3854 | save slot in memory. | |
3855 | - If we are in 64-bit mode, everything is straightforward. | |
3856 | ||
3857 | Note that this code only deals with "live" registers at the top of the | |
3858 | stack. We will attempt to deal with saved registers later, when | |
3859 | the raw/cooked register interface is in place. (We need a general | |
3860 | interface that can deal with dynamic saved register sizes -- fp | |
3861 | regs could be 32 bits wide in one frame and 64 on the frame above | |
3862 | and below). */ | |
3863 | ||
67b2c998 DJ |
3864 | static struct type * |
3865 | mips_float_register_type (void) | |
3866 | { | |
361d1df0 | 3867 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
3868 | return builtin_type_ieee_single_big; |
3869 | else | |
3870 | return builtin_type_ieee_single_little; | |
3871 | } | |
3872 | ||
3873 | static struct type * | |
3874 | mips_double_register_type (void) | |
3875 | { | |
361d1df0 | 3876 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
3877 | return builtin_type_ieee_double_big; |
3878 | else | |
3879 | return builtin_type_ieee_double_little; | |
3880 | } | |
3881 | ||
dd824b04 DJ |
3882 | /* Copy a 32-bit single-precision value from the current frame |
3883 | into rare_buffer. */ | |
3884 | ||
3885 | static void | |
3886 | mips_read_fp_register_single (int regno, char *rare_buffer) | |
3887 | { | |
3888 | int raw_size = REGISTER_RAW_SIZE (regno); | |
3889 | char *raw_buffer = alloca (raw_size); | |
3890 | ||
cda5a58a | 3891 | if (!frame_register_read (selected_frame, regno, raw_buffer)) |
dd824b04 DJ |
3892 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
3893 | if (raw_size == 8) | |
3894 | { | |
3895 | /* We have a 64-bit value for this register. Find the low-order | |
3896 | 32 bits. */ | |
3897 | int offset; | |
3898 | ||
3899 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3900 | offset = 4; | |
3901 | else | |
3902 | offset = 0; | |
3903 | ||
3904 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
3905 | } | |
3906 | else | |
3907 | { | |
3908 | memcpy (rare_buffer, raw_buffer, 4); | |
3909 | } | |
3910 | } | |
3911 | ||
3912 | /* Copy a 64-bit double-precision value from the current frame into | |
3913 | rare_buffer. This may include getting half of it from the next | |
3914 | register. */ | |
3915 | ||
3916 | static void | |
3917 | mips_read_fp_register_double (int regno, char *rare_buffer) | |
3918 | { | |
3919 | int raw_size = REGISTER_RAW_SIZE (regno); | |
3920 | ||
3921 | if (raw_size == 8 && !mips2_fp_compat ()) | |
3922 | { | |
3923 | /* We have a 64-bit value for this register, and we should use | |
3924 | all 64 bits. */ | |
cda5a58a | 3925 | if (!frame_register_read (selected_frame, regno, rare_buffer)) |
dd824b04 DJ |
3926 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
3927 | } | |
3928 | else | |
3929 | { | |
3930 | if ((regno - FP0_REGNUM) & 1) | |
3931 | internal_error (__FILE__, __LINE__, | |
3932 | "mips_read_fp_register_double: bad access to " | |
3933 | "odd-numbered FP register"); | |
3934 | ||
3935 | /* mips_read_fp_register_single will find the correct 32 bits from | |
3936 | each register. */ | |
3937 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3938 | { | |
3939 | mips_read_fp_register_single (regno, rare_buffer + 4); | |
3940 | mips_read_fp_register_single (regno + 1, rare_buffer); | |
3941 | } | |
361d1df0 | 3942 | else |
dd824b04 DJ |
3943 | { |
3944 | mips_read_fp_register_single (regno, rare_buffer); | |
3945 | mips_read_fp_register_single (regno + 1, rare_buffer + 4); | |
3946 | } | |
3947 | } | |
3948 | } | |
3949 | ||
c906108c | 3950 | static void |
acdb74a0 | 3951 | mips_print_register (int regnum, int all) |
c906108c | 3952 | { |
119d55d8 | 3953 | char *raw_buffer = alloca (MAX_REGISTER_RAW_SIZE); |
c906108c SS |
3954 | |
3955 | /* Get the data in raw format. */ | |
cda5a58a | 3956 | if (!frame_register_read (selected_frame, regnum, raw_buffer)) |
c906108c SS |
3957 | { |
3958 | printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum)); | |
3959 | return; | |
3960 | } | |
3961 | ||
dd824b04 DJ |
3962 | /* If we have a actual 32-bit floating point register (or we are in |
3963 | 32-bit compatibility mode), and the register is even-numbered, | |
3964 | also print it as a double (spanning two registers). */ | |
c906108c | 3965 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT |
dd824b04 DJ |
3966 | && (REGISTER_RAW_SIZE (regnum) == 4 |
3967 | || mips2_fp_compat ()) | |
c5aa993b | 3968 | && !((regnum - FP0_REGNUM) & 1)) |
dd824b04 | 3969 | { |
cb3d25d1 | 3970 | char *dbuffer = alloca (2 * MAX_REGISTER_RAW_SIZE); |
c906108c | 3971 | |
dd824b04 | 3972 | mips_read_fp_register_double (regnum, dbuffer); |
c906108c | 3973 | |
dd824b04 | 3974 | printf_filtered ("(d%d: ", regnum - FP0_REGNUM); |
67b2c998 | 3975 | val_print (mips_double_register_type (), dbuffer, 0, 0, |
dd824b04 DJ |
3976 | gdb_stdout, 0, 1, 0, Val_pretty_default); |
3977 | printf_filtered ("); "); | |
3978 | } | |
c906108c SS |
3979 | fputs_filtered (REGISTER_NAME (regnum), gdb_stdout); |
3980 | ||
3981 | /* The problem with printing numeric register names (r26, etc.) is that | |
3982 | the user can't use them on input. Probably the best solution is to | |
3983 | fix it so that either the numeric or the funky (a2, etc.) names | |
3984 | are accepted on input. */ | |
3985 | if (regnum < MIPS_NUMREGS) | |
3986 | printf_filtered ("(r%d): ", regnum); | |
3987 | else | |
3988 | printf_filtered (": "); | |
3989 | ||
3990 | /* If virtual format is floating, print it that way. */ | |
3991 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) | |
dd824b04 DJ |
3992 | if (REGISTER_RAW_SIZE (regnum) == 8 && !mips2_fp_compat ()) |
3993 | { | |
3994 | /* We have a meaningful 64-bit value in this register. Show | |
3995 | it as a 32-bit float and a 64-bit double. */ | |
d7449b42 | 3996 | int offset = 4 * (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG); |
c906108c SS |
3997 | |
3998 | printf_filtered (" (float) "); | |
67b2c998 | 3999 | val_print (mips_float_register_type (), raw_buffer + offset, 0, 0, |
c906108c SS |
4000 | gdb_stdout, 0, 1, 0, Val_pretty_default); |
4001 | printf_filtered (", (double) "); | |
67b2c998 | 4002 | val_print (mips_double_register_type (), raw_buffer, 0, 0, |
c906108c SS |
4003 | gdb_stdout, 0, 1, 0, Val_pretty_default); |
4004 | } | |
4005 | else | |
4006 | val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0, | |
4007 | gdb_stdout, 0, 1, 0, Val_pretty_default); | |
4008 | /* Else print as integer in hex. */ | |
4009 | else | |
ed9a39eb JM |
4010 | { |
4011 | int offset; | |
4012 | ||
d7449b42 | 4013 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
ed9a39eb JM |
4014 | offset = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum); |
4015 | else | |
4016 | offset = 0; | |
361d1df0 | 4017 | |
ed9a39eb JM |
4018 | print_scalar_formatted (raw_buffer + offset, |
4019 | REGISTER_VIRTUAL_TYPE (regnum), | |
4020 | 'x', 0, gdb_stdout); | |
4021 | } | |
c906108c SS |
4022 | } |
4023 | ||
361d1df0 | 4024 | /* Replacement for generic do_registers_info. |
c906108c SS |
4025 | Print regs in pretty columns. */ |
4026 | ||
4027 | static int | |
acdb74a0 | 4028 | do_fp_register_row (int regnum) |
c5aa993b | 4029 | { /* do values for FP (float) regs */ |
dd824b04 | 4030 | char *raw_buffer; |
c906108c SS |
4031 | double doub, flt1, flt2; /* doubles extracted from raw hex data */ |
4032 | int inv1, inv2, inv3; | |
c5aa993b | 4033 | |
dd824b04 | 4034 | raw_buffer = (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM)); |
c906108c | 4035 | |
dd824b04 | 4036 | if (REGISTER_RAW_SIZE (regnum) == 4 || mips2_fp_compat ()) |
c906108c | 4037 | { |
dd824b04 DJ |
4038 | /* 4-byte registers: we can fit two registers per row. */ |
4039 | /* Also print every pair of 4-byte regs as an 8-byte double. */ | |
4040 | mips_read_fp_register_single (regnum, raw_buffer); | |
67b2c998 | 4041 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c5aa993b | 4042 | |
dd824b04 | 4043 | mips_read_fp_register_single (regnum + 1, raw_buffer); |
67b2c998 | 4044 | flt2 = unpack_double (mips_float_register_type (), raw_buffer, &inv2); |
dd824b04 DJ |
4045 | |
4046 | mips_read_fp_register_double (regnum, raw_buffer); | |
67b2c998 | 4047 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv3); |
361d1df0 | 4048 | |
1adad886 AC |
4049 | printf_filtered (" %-5s", REGISTER_NAME (regnum)); |
4050 | if (inv1) | |
4051 | printf_filtered (": <invalid float>"); | |
4052 | else | |
4053 | printf_filtered ("%-17.9g", flt1); | |
4054 | ||
4055 | printf_filtered (" %-5s", REGISTER_NAME (regnum + 1)); | |
4056 | if (inv2) | |
4057 | printf_filtered (": <invalid float>"); | |
4058 | else | |
4059 | printf_filtered ("%-17.9g", flt2); | |
4060 | ||
4061 | printf_filtered (" dbl: "); | |
4062 | if (inv3) | |
4063 | printf_filtered ("<invalid double>"); | |
4064 | else | |
4065 | printf_filtered ("%-24.17g", doub); | |
4066 | printf_filtered ("\n"); | |
4067 | ||
c906108c | 4068 | /* may want to do hex display here (future enhancement) */ |
c5aa993b | 4069 | regnum += 2; |
c906108c SS |
4070 | } |
4071 | else | |
dd824b04 DJ |
4072 | { |
4073 | /* Eight byte registers: print each one as float AND as double. */ | |
4074 | mips_read_fp_register_single (regnum, raw_buffer); | |
67b2c998 | 4075 | flt1 = unpack_double (mips_double_register_type (), raw_buffer, &inv1); |
c906108c | 4076 | |
dd824b04 | 4077 | mips_read_fp_register_double (regnum, raw_buffer); |
67b2c998 | 4078 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv3); |
361d1df0 | 4079 | |
1adad886 AC |
4080 | printf_filtered (" %-5s: ", REGISTER_NAME (regnum)); |
4081 | if (inv1) | |
4082 | printf_filtered ("<invalid float>"); | |
4083 | else | |
4084 | printf_filtered ("flt: %-17.9g", flt1); | |
4085 | ||
4086 | printf_filtered (" dbl: "); | |
4087 | if (inv3) | |
4088 | printf_filtered ("<invalid double>"); | |
4089 | else | |
4090 | printf_filtered ("%-24.17g", doub); | |
4091 | ||
4092 | printf_filtered ("\n"); | |
c906108c SS |
4093 | /* may want to do hex display here (future enhancement) */ |
4094 | regnum++; | |
4095 | } | |
4096 | return regnum; | |
4097 | } | |
4098 | ||
4099 | /* Print a row's worth of GP (int) registers, with name labels above */ | |
4100 | ||
4101 | static int | |
acdb74a0 | 4102 | do_gp_register_row (int regnum) |
c906108c SS |
4103 | { |
4104 | /* do values for GP (int) regs */ | |
cb3d25d1 | 4105 | char *raw_buffer = alloca (MAX_REGISTER_RAW_SIZE); |
c906108c SS |
4106 | int ncols = (MIPS_REGSIZE == 8 ? 4 : 8); /* display cols per row */ |
4107 | int col, byte; | |
4108 | int start_regnum = regnum; | |
4109 | int numregs = NUM_REGS; | |
4110 | ||
4111 | ||
4112 | /* For GP registers, we print a separate row of names above the vals */ | |
4113 | printf_filtered (" "); | |
4114 | for (col = 0; col < ncols && regnum < numregs; regnum++) | |
4115 | { | |
4116 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 4117 | continue; /* unused register */ |
c906108c | 4118 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
c5aa993b JM |
4119 | break; /* end the row: reached FP register */ |
4120 | printf_filtered (MIPS_REGSIZE == 8 ? "%17s" : "%9s", | |
c906108c SS |
4121 | REGISTER_NAME (regnum)); |
4122 | col++; | |
4123 | } | |
c5aa993b | 4124 | printf_filtered (start_regnum < MIPS_NUMREGS ? "\n R%-4d" : "\n ", |
c906108c SS |
4125 | start_regnum); /* print the R0 to R31 names */ |
4126 | ||
4127 | regnum = start_regnum; /* go back to start of row */ | |
4128 | /* now print the values in hex, 4 or 8 to the row */ | |
4129 | for (col = 0; col < ncols && regnum < numregs; regnum++) | |
4130 | { | |
4131 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 4132 | continue; /* unused register */ |
c906108c | 4133 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
c5aa993b | 4134 | break; /* end row: reached FP register */ |
c906108c | 4135 | /* OK: get the data in raw format. */ |
cda5a58a | 4136 | if (!frame_register_read (selected_frame, regnum, raw_buffer)) |
c906108c SS |
4137 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); |
4138 | /* pad small registers */ | |
43e526b9 | 4139 | for (byte = 0; byte < (MIPS_REGSIZE - REGISTER_VIRTUAL_SIZE (regnum)); byte++) |
c906108c SS |
4140 | printf_filtered (" "); |
4141 | /* Now print the register value in hex, endian order. */ | |
d7449b42 | 4142 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
43e526b9 JM |
4143 | for (byte = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum); |
4144 | byte < REGISTER_RAW_SIZE (regnum); | |
4145 | byte++) | |
c906108c SS |
4146 | printf_filtered ("%02x", (unsigned char) raw_buffer[byte]); |
4147 | else | |
43e526b9 JM |
4148 | for (byte = REGISTER_VIRTUAL_SIZE (regnum) - 1; |
4149 | byte >= 0; | |
4150 | byte--) | |
c906108c SS |
4151 | printf_filtered ("%02x", (unsigned char) raw_buffer[byte]); |
4152 | printf_filtered (" "); | |
4153 | col++; | |
4154 | } | |
c5aa993b | 4155 | if (col > 0) /* ie. if we actually printed anything... */ |
c906108c SS |
4156 | printf_filtered ("\n"); |
4157 | ||
4158 | return regnum; | |
4159 | } | |
4160 | ||
4161 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
4162 | ||
bf1f5b4c | 4163 | static void |
acdb74a0 | 4164 | mips_do_registers_info (int regnum, int fpregs) |
c906108c | 4165 | { |
c5aa993b | 4166 | if (regnum != -1) /* do one specified register */ |
c906108c SS |
4167 | { |
4168 | if (*(REGISTER_NAME (regnum)) == '\0') | |
4169 | error ("Not a valid register for the current processor type"); | |
4170 | ||
4171 | mips_print_register (regnum, 0); | |
4172 | printf_filtered ("\n"); | |
4173 | } | |
c5aa993b JM |
4174 | else |
4175 | /* do all (or most) registers */ | |
c906108c SS |
4176 | { |
4177 | regnum = 0; | |
4178 | while (regnum < NUM_REGS) | |
4179 | { | |
c5aa993b JM |
4180 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
4181 | if (fpregs) /* true for "INFO ALL-REGISTERS" command */ | |
c906108c SS |
4182 | regnum = do_fp_register_row (regnum); /* FP regs */ |
4183 | else | |
4184 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
4185 | else | |
4186 | regnum = do_gp_register_row (regnum); /* GP (int) regs */ | |
4187 | } | |
4188 | } | |
4189 | } | |
4190 | ||
c906108c SS |
4191 | /* Is this a branch with a delay slot? */ |
4192 | ||
a14ed312 | 4193 | static int is_delayed (unsigned long); |
c906108c SS |
4194 | |
4195 | static int | |
acdb74a0 | 4196 | is_delayed (unsigned long insn) |
c906108c SS |
4197 | { |
4198 | int i; | |
4199 | for (i = 0; i < NUMOPCODES; ++i) | |
4200 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4201 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4202 | break; | |
4203 | return (i < NUMOPCODES | |
4204 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4205 | | INSN_COND_BRANCH_DELAY | |
4206 | | INSN_COND_BRANCH_LIKELY))); | |
4207 | } | |
4208 | ||
4209 | int | |
acdb74a0 | 4210 | mips_step_skips_delay (CORE_ADDR pc) |
c906108c SS |
4211 | { |
4212 | char buf[MIPS_INSTLEN]; | |
4213 | ||
4214 | /* There is no branch delay slot on MIPS16. */ | |
4215 | if (pc_is_mips16 (pc)) | |
4216 | return 0; | |
4217 | ||
4218 | if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0) | |
4219 | /* If error reading memory, guess that it is not a delayed branch. */ | |
4220 | return 0; | |
c5aa993b | 4221 | return is_delayed ((unsigned long) extract_unsigned_integer (buf, MIPS_INSTLEN)); |
c906108c SS |
4222 | } |
4223 | ||
4224 | ||
4225 | /* Skip the PC past function prologue instructions (32-bit version). | |
4226 | This is a helper function for mips_skip_prologue. */ | |
4227 | ||
4228 | static CORE_ADDR | |
f7b9e9fc | 4229 | mips32_skip_prologue (CORE_ADDR pc) |
c906108c | 4230 | { |
c5aa993b JM |
4231 | t_inst inst; |
4232 | CORE_ADDR end_pc; | |
4233 | int seen_sp_adjust = 0; | |
4234 | int load_immediate_bytes = 0; | |
4235 | ||
4236 | /* Skip the typical prologue instructions. These are the stack adjustment | |
4237 | instruction and the instructions that save registers on the stack | |
4238 | or in the gcc frame. */ | |
4239 | for (end_pc = pc + 100; pc < end_pc; pc += MIPS_INSTLEN) | |
4240 | { | |
4241 | unsigned long high_word; | |
c906108c | 4242 | |
c5aa993b JM |
4243 | inst = mips_fetch_instruction (pc); |
4244 | high_word = (inst >> 16) & 0xffff; | |
c906108c | 4245 | |
c5aa993b JM |
4246 | if (high_word == 0x27bd /* addiu $sp,$sp,offset */ |
4247 | || high_word == 0x67bd) /* daddiu $sp,$sp,offset */ | |
4248 | seen_sp_adjust = 1; | |
4249 | else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */ | |
4250 | inst == 0x03a8e823) /* subu $sp,$sp,$t0 */ | |
4251 | seen_sp_adjust = 1; | |
4252 | else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */ | |
4253 | || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */ | |
4254 | && (inst & 0x001F0000)) /* reg != $zero */ | |
4255 | continue; | |
4256 | ||
4257 | else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */ | |
4258 | continue; | |
4259 | else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000)) | |
4260 | /* sx reg,n($s8) */ | |
4261 | continue; /* reg != $zero */ | |
4262 | ||
4263 | /* move $s8,$sp. With different versions of gas this will be either | |
4264 | `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'. | |
4265 | Accept any one of these. */ | |
4266 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
4267 | continue; | |
4268 | ||
4269 | else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */ | |
4270 | continue; | |
4271 | else if (high_word == 0x3c1c) /* lui $gp,n */ | |
4272 | continue; | |
4273 | else if (high_word == 0x279c) /* addiu $gp,$gp,n */ | |
4274 | continue; | |
4275 | else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
4276 | || inst == 0x033ce021) /* addu $gp,$t9,$gp */ | |
4277 | continue; | |
4278 | /* The following instructions load $at or $t0 with an immediate | |
4279 | value in preparation for a stack adjustment via | |
4280 | subu $sp,$sp,[$at,$t0]. These instructions could also initialize | |
4281 | a local variable, so we accept them only before a stack adjustment | |
4282 | instruction was seen. */ | |
4283 | else if (!seen_sp_adjust) | |
4284 | { | |
4285 | if (high_word == 0x3c01 || /* lui $at,n */ | |
4286 | high_word == 0x3c08) /* lui $t0,n */ | |
4287 | { | |
4288 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
4289 | continue; | |
4290 | } | |
4291 | else if (high_word == 0x3421 || /* ori $at,$at,n */ | |
4292 | high_word == 0x3508 || /* ori $t0,$t0,n */ | |
4293 | high_word == 0x3401 || /* ori $at,$zero,n */ | |
4294 | high_word == 0x3408) /* ori $t0,$zero,n */ | |
4295 | { | |
4296 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
4297 | continue; | |
4298 | } | |
4299 | else | |
4300 | break; | |
4301 | } | |
4302 | else | |
4303 | break; | |
c906108c SS |
4304 | } |
4305 | ||
c5aa993b JM |
4306 | /* In a frameless function, we might have incorrectly |
4307 | skipped some load immediate instructions. Undo the skipping | |
4308 | if the load immediate was not followed by a stack adjustment. */ | |
4309 | if (load_immediate_bytes && !seen_sp_adjust) | |
4310 | pc -= load_immediate_bytes; | |
4311 | return pc; | |
c906108c SS |
4312 | } |
4313 | ||
4314 | /* Skip the PC past function prologue instructions (16-bit version). | |
4315 | This is a helper function for mips_skip_prologue. */ | |
4316 | ||
4317 | static CORE_ADDR | |
f7b9e9fc | 4318 | mips16_skip_prologue (CORE_ADDR pc) |
c906108c | 4319 | { |
c5aa993b JM |
4320 | CORE_ADDR end_pc; |
4321 | int extend_bytes = 0; | |
4322 | int prev_extend_bytes; | |
c906108c | 4323 | |
c5aa993b JM |
4324 | /* Table of instructions likely to be found in a function prologue. */ |
4325 | static struct | |
c906108c SS |
4326 | { |
4327 | unsigned short inst; | |
4328 | unsigned short mask; | |
c5aa993b JM |
4329 | } |
4330 | table[] = | |
4331 | { | |
c906108c | 4332 | { |
c5aa993b JM |
4333 | 0x6300, 0xff00 |
4334 | } | |
4335 | , /* addiu $sp,offset */ | |
4336 | { | |
4337 | 0xfb00, 0xff00 | |
4338 | } | |
4339 | , /* daddiu $sp,offset */ | |
4340 | { | |
4341 | 0xd000, 0xf800 | |
4342 | } | |
4343 | , /* sw reg,n($sp) */ | |
4344 | { | |
4345 | 0xf900, 0xff00 | |
4346 | } | |
4347 | , /* sd reg,n($sp) */ | |
4348 | { | |
4349 | 0x6200, 0xff00 | |
4350 | } | |
4351 | , /* sw $ra,n($sp) */ | |
4352 | { | |
4353 | 0xfa00, 0xff00 | |
4354 | } | |
4355 | , /* sd $ra,n($sp) */ | |
4356 | { | |
4357 | 0x673d, 0xffff | |
4358 | } | |
4359 | , /* move $s1,sp */ | |
4360 | { | |
4361 | 0xd980, 0xff80 | |
4362 | } | |
4363 | , /* sw $a0-$a3,n($s1) */ | |
4364 | { | |
4365 | 0x6704, 0xff1c | |
4366 | } | |
4367 | , /* move reg,$a0-$a3 */ | |
4368 | { | |
4369 | 0xe809, 0xf81f | |
4370 | } | |
4371 | , /* entry pseudo-op */ | |
4372 | { | |
4373 | 0x0100, 0xff00 | |
4374 | } | |
4375 | , /* addiu $s1,$sp,n */ | |
4376 | { | |
4377 | 0, 0 | |
4378 | } /* end of table marker */ | |
4379 | }; | |
4380 | ||
4381 | /* Skip the typical prologue instructions. These are the stack adjustment | |
4382 | instruction and the instructions that save registers on the stack | |
4383 | or in the gcc frame. */ | |
4384 | for (end_pc = pc + 100; pc < end_pc; pc += MIPS16_INSTLEN) | |
4385 | { | |
4386 | unsigned short inst; | |
4387 | int i; | |
c906108c | 4388 | |
c5aa993b | 4389 | inst = mips_fetch_instruction (pc); |
c906108c | 4390 | |
c5aa993b JM |
4391 | /* Normally we ignore an extend instruction. However, if it is |
4392 | not followed by a valid prologue instruction, we must adjust | |
4393 | the pc back over the extend so that it won't be considered | |
4394 | part of the prologue. */ | |
4395 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
4396 | { | |
4397 | extend_bytes = MIPS16_INSTLEN; | |
4398 | continue; | |
4399 | } | |
4400 | prev_extend_bytes = extend_bytes; | |
4401 | extend_bytes = 0; | |
c906108c | 4402 | |
c5aa993b JM |
4403 | /* Check for other valid prologue instructions besides extend. */ |
4404 | for (i = 0; table[i].mask != 0; i++) | |
4405 | if ((inst & table[i].mask) == table[i].inst) /* found, get out */ | |
4406 | break; | |
4407 | if (table[i].mask != 0) /* it was in table? */ | |
4408 | continue; /* ignore it */ | |
4409 | else | |
4410 | /* non-prologue */ | |
4411 | { | |
4412 | /* Return the current pc, adjusted backwards by 2 if | |
4413 | the previous instruction was an extend. */ | |
4414 | return pc - prev_extend_bytes; | |
4415 | } | |
c906108c SS |
4416 | } |
4417 | return pc; | |
4418 | } | |
4419 | ||
4420 | /* To skip prologues, I use this predicate. Returns either PC itself | |
4421 | if the code at PC does not look like a function prologue; otherwise | |
4422 | returns an address that (if we're lucky) follows the prologue. If | |
4423 | LENIENT, then we must skip everything which is involved in setting | |
4424 | up the frame (it's OK to skip more, just so long as we don't skip | |
4425 | anything which might clobber the registers which are being saved. | |
4426 | We must skip more in the case where part of the prologue is in the | |
4427 | delay slot of a non-prologue instruction). */ | |
4428 | ||
f7ab6ec6 | 4429 | static CORE_ADDR |
f7b9e9fc | 4430 | mips_skip_prologue (CORE_ADDR pc) |
c906108c SS |
4431 | { |
4432 | /* See if we can determine the end of the prologue via the symbol table. | |
4433 | If so, then return either PC, or the PC after the prologue, whichever | |
4434 | is greater. */ | |
4435 | ||
4436 | CORE_ADDR post_prologue_pc = after_prologue (pc, NULL); | |
4437 | ||
4438 | if (post_prologue_pc != 0) | |
4439 | return max (pc, post_prologue_pc); | |
4440 | ||
4441 | /* Can't determine prologue from the symbol table, need to examine | |
4442 | instructions. */ | |
4443 | ||
4444 | if (pc_is_mips16 (pc)) | |
f7b9e9fc | 4445 | return mips16_skip_prologue (pc); |
c906108c | 4446 | else |
f7b9e9fc | 4447 | return mips32_skip_prologue (pc); |
c906108c | 4448 | } |
c906108c | 4449 | |
7a292a7a SS |
4450 | /* Determine how a return value is stored within the MIPS register |
4451 | file, given the return type `valtype'. */ | |
4452 | ||
4453 | struct return_value_word | |
4454 | { | |
4455 | int len; | |
4456 | int reg; | |
4457 | int reg_offset; | |
4458 | int buf_offset; | |
4459 | }; | |
4460 | ||
7a292a7a | 4461 | static void |
acdb74a0 AC |
4462 | return_value_location (struct type *valtype, |
4463 | struct return_value_word *hi, | |
4464 | struct return_value_word *lo) | |
7a292a7a SS |
4465 | { |
4466 | int len = TYPE_LENGTH (valtype); | |
c5aa993b | 4467 | |
7a292a7a SS |
4468 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT |
4469 | && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8)) | |
4470 | || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4))) | |
4471 | { | |
4472 | if (!FP_REGISTER_DOUBLE && len == 8) | |
4473 | { | |
4474 | /* We need to break a 64bit float in two 32 bit halves and | |
c5aa993b | 4475 | spread them across a floating-point register pair. */ |
d7449b42 AC |
4476 | lo->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
4477 | hi->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 0 : 4; | |
4478 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
7a292a7a SS |
4479 | && REGISTER_RAW_SIZE (FP0_REGNUM) == 8) |
4480 | ? 4 : 0); | |
4481 | hi->reg_offset = lo->reg_offset; | |
4482 | lo->reg = FP0_REGNUM + 0; | |
4483 | hi->reg = FP0_REGNUM + 1; | |
4484 | lo->len = 4; | |
4485 | hi->len = 4; | |
4486 | } | |
4487 | else | |
4488 | { | |
4489 | /* The floating point value fits in a single floating-point | |
c5aa993b | 4490 | register. */ |
d7449b42 | 4491 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
4492 | && REGISTER_RAW_SIZE (FP0_REGNUM) == 8 |
4493 | && len == 4) | |
4494 | ? 4 : 0); | |
4495 | lo->reg = FP0_REGNUM; | |
4496 | lo->len = len; | |
4497 | lo->buf_offset = 0; | |
4498 | hi->len = 0; | |
4499 | hi->reg_offset = 0; | |
4500 | hi->buf_offset = 0; | |
4501 | hi->reg = 0; | |
4502 | } | |
4503 | } | |
4504 | else | |
4505 | { | |
4506 | /* Locate a result possibly spread across two registers. */ | |
4507 | int regnum = 2; | |
4508 | lo->reg = regnum + 0; | |
4509 | hi->reg = regnum + 1; | |
d7449b42 | 4510 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
4511 | && len < MIPS_SAVED_REGSIZE) |
4512 | { | |
bf1f5b4c MS |
4513 | /* "un-left-justify" the value in the low register */ |
4514 | lo->reg_offset = MIPS_SAVED_REGSIZE - len; | |
bcb0cc15 | 4515 | lo->len = len; |
bf1f5b4c | 4516 | hi->reg_offset = 0; |
7a292a7a SS |
4517 | hi->len = 0; |
4518 | } | |
d7449b42 | 4519 | else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
4520 | && len > MIPS_SAVED_REGSIZE /* odd-size structs */ |
4521 | && len < MIPS_SAVED_REGSIZE * 2 | |
4522 | && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || | |
4523 | TYPE_CODE (valtype) == TYPE_CODE_UNION)) | |
4524 | { | |
4525 | /* "un-left-justify" the value spread across two registers. */ | |
4526 | lo->reg_offset = 2 * MIPS_SAVED_REGSIZE - len; | |
4527 | lo->len = MIPS_SAVED_REGSIZE - lo->reg_offset; | |
4528 | hi->reg_offset = 0; | |
4529 | hi->len = len - lo->len; | |
4530 | } | |
4531 | else | |
4532 | { | |
4533 | /* Only perform a partial copy of the second register. */ | |
4534 | lo->reg_offset = 0; | |
4535 | hi->reg_offset = 0; | |
4536 | if (len > MIPS_SAVED_REGSIZE) | |
4537 | { | |
4538 | lo->len = MIPS_SAVED_REGSIZE; | |
4539 | hi->len = len - MIPS_SAVED_REGSIZE; | |
4540 | } | |
4541 | else | |
4542 | { | |
4543 | lo->len = len; | |
4544 | hi->len = 0; | |
4545 | } | |
4546 | } | |
d7449b42 | 4547 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
4548 | && REGISTER_RAW_SIZE (regnum) == 8 |
4549 | && MIPS_SAVED_REGSIZE == 4) | |
4550 | { | |
4551 | /* Account for the fact that only the least-signficant part | |
c5aa993b | 4552 | of the register is being used */ |
7a292a7a SS |
4553 | lo->reg_offset += 4; |
4554 | hi->reg_offset += 4; | |
4555 | } | |
4556 | lo->buf_offset = 0; | |
4557 | hi->buf_offset = lo->len; | |
4558 | } | |
4559 | } | |
4560 | ||
4561 | /* Given a return value in `regbuf' with a type `valtype', extract and | |
4562 | copy its value into `valbuf'. */ | |
4563 | ||
46cac009 AC |
4564 | static void |
4565 | mips_eabi_extract_return_value (struct type *valtype, | |
4566 | char regbuf[REGISTER_BYTES], | |
4567 | char *valbuf) | |
4568 | { | |
4569 | struct return_value_word lo; | |
4570 | struct return_value_word hi; | |
4571 | return_value_location (valtype, &hi, &lo); | |
4572 | ||
4573 | memcpy (valbuf + lo.buf_offset, | |
4574 | regbuf + REGISTER_BYTE (lo.reg) + lo.reg_offset, | |
4575 | lo.len); | |
4576 | ||
4577 | if (hi.len > 0) | |
4578 | memcpy (valbuf + hi.buf_offset, | |
4579 | regbuf + REGISTER_BYTE (hi.reg) + hi.reg_offset, | |
4580 | hi.len); | |
4581 | } | |
4582 | ||
46cac009 AC |
4583 | static void |
4584 | mips_o64_extract_return_value (struct type *valtype, | |
4585 | char regbuf[REGISTER_BYTES], | |
4586 | char *valbuf) | |
4587 | { | |
4588 | struct return_value_word lo; | |
4589 | struct return_value_word hi; | |
4590 | return_value_location (valtype, &hi, &lo); | |
4591 | ||
4592 | memcpy (valbuf + lo.buf_offset, | |
4593 | regbuf + REGISTER_BYTE (lo.reg) + lo.reg_offset, | |
4594 | lo.len); | |
4595 | ||
4596 | if (hi.len > 0) | |
4597 | memcpy (valbuf + hi.buf_offset, | |
4598 | regbuf + REGISTER_BYTE (hi.reg) + hi.reg_offset, | |
4599 | hi.len); | |
4600 | } | |
4601 | ||
7a292a7a SS |
4602 | /* Given a return value in `valbuf' with a type `valtype', write it's |
4603 | value into the appropriate register. */ | |
4604 | ||
46cac009 AC |
4605 | static void |
4606 | mips_eabi_store_return_value (struct type *valtype, char *valbuf) | |
4607 | { | |
4608 | char *raw_buffer = alloca (MAX_REGISTER_RAW_SIZE); | |
4609 | struct return_value_word lo; | |
4610 | struct return_value_word hi; | |
4611 | return_value_location (valtype, &hi, &lo); | |
4612 | ||
4613 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4614 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
4615 | write_register_bytes (REGISTER_BYTE (lo.reg), | |
4616 | raw_buffer, | |
4617 | REGISTER_RAW_SIZE (lo.reg)); | |
4618 | ||
4619 | if (hi.len > 0) | |
4620 | { | |
4621 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4622 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
4623 | write_register_bytes (REGISTER_BYTE (hi.reg), | |
4624 | raw_buffer, | |
4625 | REGISTER_RAW_SIZE (hi.reg)); | |
4626 | } | |
4627 | } | |
4628 | ||
4629 | static void | |
cb1d2653 | 4630 | mips_o64_store_return_value (struct type *valtype, char *valbuf) |
46cac009 AC |
4631 | { |
4632 | char *raw_buffer = alloca (MAX_REGISTER_RAW_SIZE); | |
4633 | struct return_value_word lo; | |
4634 | struct return_value_word hi; | |
4635 | return_value_location (valtype, &hi, &lo); | |
4636 | ||
4637 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4638 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
4639 | write_register_bytes (REGISTER_BYTE (lo.reg), | |
4640 | raw_buffer, | |
4641 | REGISTER_RAW_SIZE (lo.reg)); | |
4642 | ||
4643 | if (hi.len > 0) | |
4644 | { | |
4645 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4646 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
4647 | write_register_bytes (REGISTER_BYTE (hi.reg), | |
4648 | raw_buffer, | |
4649 | REGISTER_RAW_SIZE (hi.reg)); | |
4650 | } | |
4651 | } | |
4652 | ||
cb1d2653 AC |
4653 | /* O32 ABI stuff. */ |
4654 | ||
46cac009 | 4655 | static void |
cb1d2653 AC |
4656 | mips_o32_xfer_return_value (struct type *type, |
4657 | struct regcache *regcache, | |
4658 | bfd_byte *in, const bfd_byte *out) | |
46cac009 | 4659 | { |
cb1d2653 AC |
4660 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
4661 | if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4662 | && TYPE_LENGTH (type) == 4 | |
4663 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
46cac009 | 4664 | { |
cb1d2653 AC |
4665 | /* A single-precision floating-point value. It fits in the |
4666 | least significant part of FP0. */ | |
4667 | if (mips_debug) | |
4668 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
4669 | mips_xfer_register (regcache, FP0_REGNUM, TYPE_LENGTH (type), | |
4670 | TARGET_BYTE_ORDER, in, out, 0); | |
4671 | } | |
4672 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4673 | && TYPE_LENGTH (type) == 8 | |
4674 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4675 | { | |
4676 | /* A double-precision floating-point value. It fits in the | |
4677 | least significant part of FP0/FP1 but with byte ordering | |
4678 | based on the target (???). */ | |
4679 | if (mips_debug) | |
4680 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0/$fp1\n"); | |
4681 | switch (TARGET_BYTE_ORDER) | |
4682 | { | |
4683 | case BFD_ENDIAN_LITTLE: | |
4684 | mips_xfer_register (regcache, FP0_REGNUM + 0, 4, | |
4685 | TARGET_BYTE_ORDER, in, out, 0); | |
4686 | mips_xfer_register (regcache, FP0_REGNUM + 1, 4, | |
4687 | TARGET_BYTE_ORDER, in, out, 4); | |
4688 | break; | |
4689 | case BFD_ENDIAN_BIG: | |
4690 | mips_xfer_register (regcache, FP0_REGNUM + 1, 4, | |
4691 | TARGET_BYTE_ORDER, in, out, 0); | |
4692 | mips_xfer_register (regcache, FP0_REGNUM + 0, 4, | |
4693 | TARGET_BYTE_ORDER, in, out, 4); | |
4694 | break; | |
4695 | default: | |
4696 | internal_error (__FILE__, __LINE__, "bad switch"); | |
4697 | } | |
4698 | } | |
4699 | #if 0 | |
4700 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4701 | && TYPE_NFIELDS (type) <= 2 | |
4702 | && TYPE_NFIELDS (type) >= 1 | |
4703 | && ((TYPE_NFIELDS (type) == 1 | |
4704 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4705 | == TYPE_CODE_FLT)) | |
4706 | || (TYPE_NFIELDS (type) == 2 | |
4707 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4708 | == TYPE_CODE_FLT) | |
4709 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
4710 | == TYPE_CODE_FLT))) | |
4711 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4712 | { | |
4713 | /* A struct that contains one or two floats. Each value is part | |
4714 | in the least significant part of their floating point | |
4715 | register.. */ | |
4716 | bfd_byte *reg = alloca (MAX_REGISTER_RAW_SIZE); | |
4717 | int regnum; | |
4718 | int field; | |
4719 | for (field = 0, regnum = FP0_REGNUM; | |
4720 | field < TYPE_NFIELDS (type); | |
4721 | field++, regnum += 2) | |
4722 | { | |
4723 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
4724 | / TARGET_CHAR_BIT); | |
4725 | if (mips_debug) | |
4726 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", offset); | |
4727 | mips_xfer_register (regcache, regnum, TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
4728 | TARGET_BYTE_ORDER, in, out, offset); | |
4729 | } | |
4730 | } | |
4731 | #endif | |
4732 | #if 0 | |
4733 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4734 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4735 | { | |
4736 | /* A structure or union. Extract the left justified value, | |
4737 | regardless of the byte order. I.e. DO NOT USE | |
4738 | mips_xfer_lower. */ | |
4739 | int offset; | |
4740 | int regnum; | |
4741 | for (offset = 0, regnum = V0_REGNUM; | |
4742 | offset < TYPE_LENGTH (type); | |
4743 | offset += REGISTER_RAW_SIZE (regnum), regnum++) | |
4744 | { | |
4745 | int xfer = REGISTER_RAW_SIZE (regnum); | |
4746 | if (offset + xfer > TYPE_LENGTH (type)) | |
4747 | xfer = TYPE_LENGTH (type) - offset; | |
4748 | if (mips_debug) | |
4749 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
4750 | offset, xfer, regnum); | |
4751 | mips_xfer_register (regcache, regnum, xfer, BFD_ENDIAN_UNKNOWN, | |
4752 | in, out, offset); | |
4753 | } | |
4754 | } | |
4755 | #endif | |
4756 | else | |
4757 | { | |
4758 | /* A scalar extract each part but least-significant-byte | |
4759 | justified. o32 thinks registers are 4 byte, regardless of | |
4760 | the ISA. mips_stack_argsize controls this. */ | |
4761 | int offset; | |
4762 | int regnum; | |
4763 | for (offset = 0, regnum = V0_REGNUM; | |
4764 | offset < TYPE_LENGTH (type); | |
4765 | offset += mips_stack_argsize (), regnum++) | |
4766 | { | |
4767 | int xfer = mips_stack_argsize (); | |
4768 | int pos = 0; | |
4769 | if (offset + xfer > TYPE_LENGTH (type)) | |
4770 | xfer = TYPE_LENGTH (type) - offset; | |
4771 | if (mips_debug) | |
4772 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4773 | offset, xfer, regnum); | |
4774 | mips_xfer_register (regcache, regnum, xfer, TARGET_BYTE_ORDER, | |
4775 | in, out, offset); | |
4776 | } | |
46cac009 AC |
4777 | } |
4778 | } | |
4779 | ||
cb1d2653 AC |
4780 | static void |
4781 | mips_o32_extract_return_value (struct type *type, | |
4782 | struct regcache *regcache, | |
ebba8386 | 4783 | void *valbuf) |
cb1d2653 AC |
4784 | { |
4785 | mips_o32_xfer_return_value (type, regcache, valbuf, NULL); | |
4786 | } | |
4787 | ||
4788 | static void | |
4789 | mips_o32_store_return_value (struct type *type, char *valbuf) | |
4790 | { | |
4791 | mips_o32_xfer_return_value (type, current_regcache, NULL, valbuf); | |
4792 | } | |
4793 | ||
4794 | /* N32/N44 ABI stuff. */ | |
4795 | ||
46cac009 | 4796 | static void |
88658117 AC |
4797 | mips_n32n64_xfer_return_value (struct type *type, |
4798 | struct regcache *regcache, | |
4799 | bfd_byte *in, const bfd_byte *out) | |
c906108c | 4800 | { |
88658117 AC |
4801 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
4802 | if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4803 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
7a292a7a | 4804 | { |
88658117 AC |
4805 | /* A floating-point value belongs in the least significant part |
4806 | of FP0. */ | |
4807 | if (mips_debug) | |
4808 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
4809 | mips_xfer_register (regcache, FP0_REGNUM, TYPE_LENGTH (type), | |
4810 | TARGET_BYTE_ORDER, in, out, 0); | |
4811 | } | |
4812 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4813 | && TYPE_NFIELDS (type) <= 2 | |
4814 | && TYPE_NFIELDS (type) >= 1 | |
4815 | && ((TYPE_NFIELDS (type) == 1 | |
4816 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4817 | == TYPE_CODE_FLT)) | |
4818 | || (TYPE_NFIELDS (type) == 2 | |
4819 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4820 | == TYPE_CODE_FLT) | |
4821 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
4822 | == TYPE_CODE_FLT))) | |
4823 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4824 | { | |
4825 | /* A struct that contains one or two floats. Each value is part | |
4826 | in the least significant part of their floating point | |
4827 | register.. */ | |
4828 | bfd_byte *reg = alloca (MAX_REGISTER_RAW_SIZE); | |
4829 | int regnum; | |
4830 | int field; | |
4831 | for (field = 0, regnum = FP0_REGNUM; | |
4832 | field < TYPE_NFIELDS (type); | |
4833 | field++, regnum += 2) | |
4834 | { | |
4835 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
4836 | / TARGET_CHAR_BIT); | |
4837 | if (mips_debug) | |
4838 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", offset); | |
4839 | mips_xfer_register (regcache, regnum, TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
4840 | TARGET_BYTE_ORDER, in, out, offset); | |
4841 | } | |
7a292a7a | 4842 | } |
88658117 AC |
4843 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
4844 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4845 | { | |
4846 | /* A structure or union. Extract the left justified value, | |
4847 | regardless of the byte order. I.e. DO NOT USE | |
4848 | mips_xfer_lower. */ | |
4849 | int offset; | |
4850 | int regnum; | |
4851 | for (offset = 0, regnum = V0_REGNUM; | |
4852 | offset < TYPE_LENGTH (type); | |
4853 | offset += REGISTER_RAW_SIZE (regnum), regnum++) | |
4854 | { | |
4855 | int xfer = REGISTER_RAW_SIZE (regnum); | |
4856 | if (offset + xfer > TYPE_LENGTH (type)) | |
4857 | xfer = TYPE_LENGTH (type) - offset; | |
4858 | if (mips_debug) | |
4859 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
4860 | offset, xfer, regnum); | |
4861 | mips_xfer_register (regcache, regnum, xfer, BFD_ENDIAN_UNKNOWN, | |
4862 | in, out, offset); | |
4863 | } | |
4864 | } | |
4865 | else | |
4866 | { | |
4867 | /* A scalar extract each part but least-significant-byte | |
4868 | justified. */ | |
4869 | int offset; | |
4870 | int regnum; | |
4871 | for (offset = 0, regnum = V0_REGNUM; | |
4872 | offset < TYPE_LENGTH (type); | |
4873 | offset += REGISTER_RAW_SIZE (regnum), regnum++) | |
4874 | { | |
4875 | int xfer = REGISTER_RAW_SIZE (regnum); | |
4876 | int pos = 0; | |
4877 | if (offset + xfer > TYPE_LENGTH (type)) | |
4878 | xfer = TYPE_LENGTH (type) - offset; | |
4879 | if (mips_debug) | |
4880 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4881 | offset, xfer, regnum); | |
4882 | mips_xfer_register (regcache, regnum, xfer, TARGET_BYTE_ORDER, | |
4883 | in, out, offset); | |
4884 | } | |
4885 | } | |
4886 | } | |
4887 | ||
4888 | static void | |
4889 | mips_n32n64_extract_return_value (struct type *type, | |
4890 | struct regcache *regcache, | |
ebba8386 | 4891 | void *valbuf) |
88658117 AC |
4892 | { |
4893 | mips_n32n64_xfer_return_value (type, regcache, valbuf, NULL); | |
4894 | } | |
4895 | ||
4896 | static void | |
4897 | mips_n32n64_store_return_value (struct type *type, char *valbuf) | |
4898 | { | |
4899 | mips_n32n64_xfer_return_value (type, current_regcache, NULL, valbuf); | |
c906108c SS |
4900 | } |
4901 | ||
2f1488ce MS |
4902 | static void |
4903 | mips_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) | |
4904 | { | |
4905 | /* Nothing to do -- push_arguments does all the work. */ | |
4906 | } | |
4907 | ||
4908 | static CORE_ADDR | |
4909 | mips_extract_struct_value_address (struct regcache *ignore) | |
4910 | { | |
4911 | /* FIXME: This will only work at random. The caller passes the | |
4912 | struct_return address in V0, but it is not preserved. It may | |
4913 | still be there, or this may be a random value. */ | |
4914 | return read_register (V0_REGNUM); | |
4915 | } | |
4916 | ||
c906108c SS |
4917 | /* Exported procedure: Is PC in the signal trampoline code */ |
4918 | ||
102182a9 MS |
4919 | static int |
4920 | mips_pc_in_sigtramp (CORE_ADDR pc, char *ignore) | |
c906108c SS |
4921 | { |
4922 | if (sigtramp_address == 0) | |
4923 | fixup_sigtramp (); | |
4924 | return (pc >= sigtramp_address && pc < sigtramp_end); | |
4925 | } | |
4926 | ||
a5ea2558 AC |
4927 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
4928 | used for all MIPS-specific commands. */ | |
4929 | ||
a5ea2558 | 4930 | static void |
acdb74a0 | 4931 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
4932 | { |
4933 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
4934 | } | |
4935 | ||
a5ea2558 | 4936 | static void |
acdb74a0 | 4937 | set_mips_command (char *args, int from_tty) |
a5ea2558 AC |
4938 | { |
4939 | printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
4940 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); | |
4941 | } | |
4942 | ||
c906108c SS |
4943 | /* Commands to show/set the MIPS FPU type. */ |
4944 | ||
c906108c | 4945 | static void |
acdb74a0 | 4946 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 4947 | { |
c906108c SS |
4948 | char *fpu; |
4949 | switch (MIPS_FPU_TYPE) | |
4950 | { | |
4951 | case MIPS_FPU_SINGLE: | |
4952 | fpu = "single-precision"; | |
4953 | break; | |
4954 | case MIPS_FPU_DOUBLE: | |
4955 | fpu = "double-precision"; | |
4956 | break; | |
4957 | case MIPS_FPU_NONE: | |
4958 | fpu = "absent (none)"; | |
4959 | break; | |
93d56215 AC |
4960 | default: |
4961 | internal_error (__FILE__, __LINE__, "bad switch"); | |
c906108c SS |
4962 | } |
4963 | if (mips_fpu_type_auto) | |
4964 | printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
4965 | fpu); | |
4966 | else | |
4967 | printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n", | |
4968 | fpu); | |
4969 | } | |
4970 | ||
4971 | ||
c906108c | 4972 | static void |
acdb74a0 | 4973 | set_mipsfpu_command (char *args, int from_tty) |
c906108c SS |
4974 | { |
4975 | printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
4976 | show_mipsfpu_command (args, from_tty); | |
4977 | } | |
4978 | ||
c906108c | 4979 | static void |
acdb74a0 | 4980 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c SS |
4981 | { |
4982 | mips_fpu_type = MIPS_FPU_SINGLE; | |
4983 | mips_fpu_type_auto = 0; | |
9e364162 | 4984 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_SINGLE; |
c906108c SS |
4985 | } |
4986 | ||
c906108c | 4987 | static void |
acdb74a0 | 4988 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c SS |
4989 | { |
4990 | mips_fpu_type = MIPS_FPU_DOUBLE; | |
4991 | mips_fpu_type_auto = 0; | |
9e364162 | 4992 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_DOUBLE; |
c906108c SS |
4993 | } |
4994 | ||
c906108c | 4995 | static void |
acdb74a0 | 4996 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c SS |
4997 | { |
4998 | mips_fpu_type = MIPS_FPU_NONE; | |
4999 | mips_fpu_type_auto = 0; | |
9e364162 | 5000 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_NONE; |
c906108c SS |
5001 | } |
5002 | ||
c906108c | 5003 | static void |
acdb74a0 | 5004 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
5005 | { |
5006 | mips_fpu_type_auto = 1; | |
5007 | } | |
5008 | ||
5009 | /* Command to set the processor type. */ | |
5010 | ||
5011 | void | |
acdb74a0 | 5012 | mips_set_processor_type_command (char *args, int from_tty) |
c906108c SS |
5013 | { |
5014 | int i; | |
5015 | ||
5016 | if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0') | |
5017 | { | |
5018 | printf_unfiltered ("The known MIPS processor types are as follows:\n\n"); | |
5019 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
5020 | printf_unfiltered ("%s\n", mips_processor_type_table[i].name); | |
5021 | ||
5022 | /* Restore the value. */ | |
4fcf66da | 5023 | tmp_mips_processor_type = xstrdup (mips_processor_type); |
c906108c SS |
5024 | |
5025 | return; | |
5026 | } | |
c5aa993b | 5027 | |
c906108c SS |
5028 | if (!mips_set_processor_type (tmp_mips_processor_type)) |
5029 | { | |
5030 | error ("Unknown processor type `%s'.", tmp_mips_processor_type); | |
5031 | /* Restore its value. */ | |
4fcf66da | 5032 | tmp_mips_processor_type = xstrdup (mips_processor_type); |
c906108c SS |
5033 | } |
5034 | } | |
5035 | ||
5036 | static void | |
acdb74a0 | 5037 | mips_show_processor_type_command (char *args, int from_tty) |
c906108c SS |
5038 | { |
5039 | } | |
5040 | ||
5041 | /* Modify the actual processor type. */ | |
5042 | ||
5a89d8aa | 5043 | static int |
acdb74a0 | 5044 | mips_set_processor_type (char *str) |
c906108c | 5045 | { |
1012bd0e | 5046 | int i; |
c906108c SS |
5047 | |
5048 | if (str == NULL) | |
5049 | return 0; | |
5050 | ||
5051 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
5052 | { | |
5053 | if (strcasecmp (str, mips_processor_type_table[i].name) == 0) | |
5054 | { | |
5055 | mips_processor_type = str; | |
cce74817 | 5056 | mips_processor_reg_names = mips_processor_type_table[i].regnames; |
c906108c | 5057 | return 1; |
c906108c SS |
5058 | /* FIXME tweak fpu flag too */ |
5059 | } | |
5060 | } | |
5061 | ||
5062 | return 0; | |
5063 | } | |
5064 | ||
5065 | /* Attempt to identify the particular processor model by reading the | |
5066 | processor id. */ | |
5067 | ||
5068 | char * | |
acdb74a0 | 5069 | mips_read_processor_type (void) |
c906108c SS |
5070 | { |
5071 | CORE_ADDR prid; | |
5072 | ||
5073 | prid = read_register (PRID_REGNUM); | |
5074 | ||
5075 | if ((prid & ~0xf) == 0x700) | |
c5aa993b | 5076 | return savestring ("r3041", strlen ("r3041")); |
c906108c SS |
5077 | |
5078 | return NULL; | |
5079 | } | |
5080 | ||
5081 | /* Just like reinit_frame_cache, but with the right arguments to be | |
5082 | callable as an sfunc. */ | |
5083 | ||
5084 | static void | |
acdb74a0 AC |
5085 | reinit_frame_cache_sfunc (char *args, int from_tty, |
5086 | struct cmd_list_element *c) | |
c906108c SS |
5087 | { |
5088 | reinit_frame_cache (); | |
5089 | } | |
5090 | ||
5091 | int | |
acdb74a0 | 5092 | gdb_print_insn_mips (bfd_vma memaddr, disassemble_info *info) |
c906108c SS |
5093 | { |
5094 | mips_extra_func_info_t proc_desc; | |
5095 | ||
5096 | /* Search for the function containing this address. Set the low bit | |
5097 | of the address when searching, in case we were given an even address | |
5098 | that is the start of a 16-bit function. If we didn't do this, | |
5099 | the search would fail because the symbol table says the function | |
5100 | starts at an odd address, i.e. 1 byte past the given address. */ | |
5101 | memaddr = ADDR_BITS_REMOVE (memaddr); | |
5102 | proc_desc = non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr), NULL); | |
5103 | ||
5104 | /* Make an attempt to determine if this is a 16-bit function. If | |
5105 | the procedure descriptor exists and the address therein is odd, | |
5106 | it's definitely a 16-bit function. Otherwise, we have to just | |
5107 | guess that if the address passed in is odd, it's 16-bits. */ | |
5108 | if (proc_desc) | |
361d1df0 | 5109 | info->mach = pc_is_mips16 (PROC_LOW_ADDR (proc_desc)) ? |
65c11066 | 5110 | bfd_mach_mips16 : TM_PRINT_INSN_MACH; |
c906108c | 5111 | else |
361d1df0 | 5112 | info->mach = pc_is_mips16 (memaddr) ? |
65c11066 | 5113 | bfd_mach_mips16 : TM_PRINT_INSN_MACH; |
c906108c SS |
5114 | |
5115 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 5116 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 5117 | |
c906108c | 5118 | /* Call the appropriate disassembler based on the target endian-ness. */ |
d7449b42 | 5119 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
5120 | return print_insn_big_mips (memaddr, info); |
5121 | else | |
5122 | return print_insn_little_mips (memaddr, info); | |
5123 | } | |
5124 | ||
5125 | /* Old-style breakpoint macros. | |
5126 | The IDT board uses an unusual breakpoint value, and sometimes gets | |
5127 | confused when it sees the usual MIPS breakpoint instruction. */ | |
5128 | ||
5129 | #define BIG_BREAKPOINT {0, 0x5, 0, 0xd} | |
5130 | #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0} | |
5131 | #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd} | |
5132 | #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0} | |
5133 | #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd} | |
5134 | #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0} | |
5135 | #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5} | |
5136 | #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8} | |
5137 | ||
5138 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program | |
5139 | counter value to determine whether a 16- or 32-bit breakpoint should be | |
5140 | used. It returns a pointer to a string of bytes that encode a breakpoint | |
5141 | instruction, stores the length of the string to *lenptr, and adjusts pc | |
5142 | (if necessary) to point to the actual memory location where the | |
5143 | breakpoint should be inserted. */ | |
5144 | ||
f7ab6ec6 | 5145 | static const unsigned char * |
acdb74a0 | 5146 | mips_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr) |
c906108c | 5147 | { |
d7449b42 | 5148 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
5149 | { |
5150 | if (pc_is_mips16 (*pcptr)) | |
5151 | { | |
1012bd0e EZ |
5152 | static unsigned char mips16_big_breakpoint[] = |
5153 | MIPS16_BIG_BREAKPOINT; | |
c906108c | 5154 | *pcptr = UNMAKE_MIPS16_ADDR (*pcptr); |
c5aa993b | 5155 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
5156 | return mips16_big_breakpoint; |
5157 | } | |
5158 | else | |
5159 | { | |
1012bd0e EZ |
5160 | static unsigned char big_breakpoint[] = BIG_BREAKPOINT; |
5161 | static unsigned char pmon_big_breakpoint[] = PMON_BIG_BREAKPOINT; | |
5162 | static unsigned char idt_big_breakpoint[] = IDT_BIG_BREAKPOINT; | |
c906108c | 5163 | |
c5aa993b | 5164 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
5165 | |
5166 | if (strcmp (target_shortname, "mips") == 0) | |
5167 | return idt_big_breakpoint; | |
5168 | else if (strcmp (target_shortname, "ddb") == 0 | |
5169 | || strcmp (target_shortname, "pmon") == 0 | |
5170 | || strcmp (target_shortname, "lsi") == 0) | |
5171 | return pmon_big_breakpoint; | |
5172 | else | |
5173 | return big_breakpoint; | |
5174 | } | |
5175 | } | |
5176 | else | |
5177 | { | |
5178 | if (pc_is_mips16 (*pcptr)) | |
5179 | { | |
1012bd0e EZ |
5180 | static unsigned char mips16_little_breakpoint[] = |
5181 | MIPS16_LITTLE_BREAKPOINT; | |
c906108c | 5182 | *pcptr = UNMAKE_MIPS16_ADDR (*pcptr); |
c5aa993b | 5183 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
5184 | return mips16_little_breakpoint; |
5185 | } | |
5186 | else | |
5187 | { | |
1012bd0e EZ |
5188 | static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT; |
5189 | static unsigned char pmon_little_breakpoint[] = | |
5190 | PMON_LITTLE_BREAKPOINT; | |
5191 | static unsigned char idt_little_breakpoint[] = | |
5192 | IDT_LITTLE_BREAKPOINT; | |
c906108c | 5193 | |
c5aa993b | 5194 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
5195 | |
5196 | if (strcmp (target_shortname, "mips") == 0) | |
5197 | return idt_little_breakpoint; | |
5198 | else if (strcmp (target_shortname, "ddb") == 0 | |
5199 | || strcmp (target_shortname, "pmon") == 0 | |
5200 | || strcmp (target_shortname, "lsi") == 0) | |
5201 | return pmon_little_breakpoint; | |
5202 | else | |
5203 | return little_breakpoint; | |
5204 | } | |
5205 | } | |
5206 | } | |
5207 | ||
5208 | /* If PC is in a mips16 call or return stub, return the address of the target | |
5209 | PC, which is either the callee or the caller. There are several | |
5210 | cases which must be handled: | |
5211 | ||
5212 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 5213 | target PC is in $31 ($ra). |
c906108c | 5214 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 5215 | and the target PC is in $2. |
c906108c | 5216 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
5217 | before the jal instruction, this is effectively a call stub |
5218 | and the the target PC is in $2. Otherwise this is effectively | |
5219 | a return stub and the target PC is in $18. | |
c906108c SS |
5220 | |
5221 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
5222 | gory details. | |
5223 | ||
5224 | This function implements the SKIP_TRAMPOLINE_CODE macro. | |
c5aa993b | 5225 | */ |
c906108c | 5226 | |
757a7cc6 | 5227 | static CORE_ADDR |
acdb74a0 | 5228 | mips_skip_stub (CORE_ADDR pc) |
c906108c SS |
5229 | { |
5230 | char *name; | |
5231 | CORE_ADDR start_addr; | |
5232 | ||
5233 | /* Find the starting address and name of the function containing the PC. */ | |
5234 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
5235 | return 0; | |
5236 | ||
5237 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
5238 | target PC is in $31 ($ra). */ | |
5239 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5240 | || strcmp (name, "__mips16_ret_df") == 0) | |
6c997a34 | 5241 | return read_signed_register (RA_REGNUM); |
c906108c SS |
5242 | |
5243 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5244 | { | |
5245 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
5246 | and the target PC is in $2. */ | |
5247 | if (name[19] >= '0' && name[19] <= '9') | |
6c997a34 | 5248 | return read_signed_register (2); |
c906108c SS |
5249 | |
5250 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
5251 | before the jal instruction, this is effectively a call stub |
5252 | and the the target PC is in $2. Otherwise this is effectively | |
5253 | a return stub and the target PC is in $18. */ | |
c906108c SS |
5254 | else if (name[19] == 's' || name[19] == 'd') |
5255 | { | |
5256 | if (pc == start_addr) | |
5257 | { | |
5258 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
5259 | stub. Such a stub for a function bar might have a name |
5260 | like __fn_stub_bar, and might look like this: | |
5261 | mfc1 $4,$f13 | |
5262 | mfc1 $5,$f12 | |
5263 | mfc1 $6,$f15 | |
5264 | mfc1 $7,$f14 | |
5265 | la $1,bar (becomes a lui/addiu pair) | |
5266 | jr $1 | |
5267 | So scan down to the lui/addi and extract the target | |
5268 | address from those two instructions. */ | |
c906108c | 5269 | |
6c997a34 | 5270 | CORE_ADDR target_pc = read_signed_register (2); |
c906108c SS |
5271 | t_inst inst; |
5272 | int i; | |
5273 | ||
5274 | /* See if the name of the target function is __fn_stub_*. */ | |
5275 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == 0) | |
5276 | return target_pc; | |
5277 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
5278 | && strcmp (name, "etext") != 0 | |
5279 | && strcmp (name, "_etext") != 0) | |
5280 | return target_pc; | |
5281 | ||
5282 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
5283 | The limit on the search is arbitrarily set to 20 |
5284 | instructions. FIXME. */ | |
c906108c SS |
5285 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN) |
5286 | { | |
c5aa993b JM |
5287 | inst = mips_fetch_instruction (target_pc); |
5288 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
5289 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
5290 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
5291 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
5292 | } |
5293 | ||
5294 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
5295 | return target_pc; | |
5296 | } | |
5297 | else | |
5298 | /* This is the 'return' part of a call stub. The return | |
5299 | address is in $r18. */ | |
6c997a34 | 5300 | return read_signed_register (18); |
c906108c SS |
5301 | } |
5302 | } | |
c5aa993b | 5303 | return 0; /* not a stub */ |
c906108c SS |
5304 | } |
5305 | ||
5306 | ||
5307 | /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline). | |
5308 | This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */ | |
5309 | ||
757a7cc6 | 5310 | static int |
acdb74a0 | 5311 | mips_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
5312 | { |
5313 | CORE_ADDR start_addr; | |
5314 | ||
5315 | /* Find the starting address of the function containing the PC. If the | |
5316 | caller didn't give us a name, look it up at the same time. */ | |
5317 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0) | |
5318 | return 0; | |
5319 | ||
5320 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5321 | { | |
5322 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */ | |
5323 | if (name[19] >= '0' && name[19] <= '9') | |
5324 | return 1; | |
5325 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b | 5326 | before the jal instruction, this is effectively a call stub. */ |
c906108c SS |
5327 | else if (name[19] == 's' || name[19] == 'd') |
5328 | return pc == start_addr; | |
5329 | } | |
5330 | ||
c5aa993b | 5331 | return 0; /* not a stub */ |
c906108c SS |
5332 | } |
5333 | ||
5334 | ||
5335 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
5336 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
5337 | ||
e41b17f0 | 5338 | static int |
acdb74a0 | 5339 | mips_in_return_stub (CORE_ADDR pc, char *name) |
c906108c SS |
5340 | { |
5341 | CORE_ADDR start_addr; | |
5342 | ||
5343 | /* Find the starting address of the function containing the PC. */ | |
5344 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
5345 | return 0; | |
5346 | ||
5347 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */ | |
5348 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5349 | || strcmp (name, "__mips16_ret_df") == 0) | |
5350 | return 1; | |
5351 | ||
5352 | /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start, | |
c5aa993b | 5353 | i.e. after the jal instruction, this is effectively a return stub. */ |
c906108c SS |
5354 | if (strncmp (name, "__mips16_call_stub_", 19) == 0 |
5355 | && (name[19] == 's' || name[19] == 'd') | |
5356 | && pc != start_addr) | |
5357 | return 1; | |
5358 | ||
c5aa993b | 5359 | return 0; /* not a stub */ |
c906108c SS |
5360 | } |
5361 | ||
5362 | ||
5363 | /* Return non-zero if the PC is in a library helper function that should | |
5364 | be ignored. This implements the IGNORE_HELPER_CALL macro. */ | |
5365 | ||
5366 | int | |
acdb74a0 | 5367 | mips_ignore_helper (CORE_ADDR pc) |
c906108c SS |
5368 | { |
5369 | char *name; | |
5370 | ||
5371 | /* Find the starting address and name of the function containing the PC. */ | |
5372 | if (find_pc_partial_function (pc, &name, NULL, NULL) == 0) | |
5373 | return 0; | |
5374 | ||
5375 | /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function | |
5376 | that we want to ignore. */ | |
5377 | return (strcmp (name, "__mips16_ret_sf") == 0 | |
5378 | || strcmp (name, "__mips16_ret_df") == 0); | |
5379 | } | |
5380 | ||
5381 | ||
5382 | /* Return a location where we can set a breakpoint that will be hit | |
5383 | when an inferior function call returns. This is normally the | |
5384 | program's entry point. Executables that don't have an entry | |
5385 | point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS | |
5386 | whose address is the location where the breakpoint should be placed. */ | |
5387 | ||
f7ab6ec6 | 5388 | static CORE_ADDR |
acdb74a0 | 5389 | mips_call_dummy_address (void) |
c906108c SS |
5390 | { |
5391 | struct minimal_symbol *sym; | |
5392 | ||
5393 | sym = lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL, NULL); | |
5394 | if (sym) | |
5395 | return SYMBOL_VALUE_ADDRESS (sym); | |
5396 | else | |
5397 | return entry_point_address (); | |
5398 | } | |
5399 | ||
5400 | ||
9dcb560c | 5401 | /* If the current gcc for this target does not produce correct debugging |
b9a8e3bf JB |
5402 | information for float parameters, both prototyped and unprototyped, then |
5403 | define this macro. This forces gdb to always assume that floats are | |
5404 | passed as doubles and then converted in the callee. | |
5405 | ||
5406 | For the mips chip, it appears that the debug info marks the parameters as | |
5407 | floats regardless of whether the function is prototyped, but the actual | |
5408 | values are passed as doubles for the non-prototyped case and floats for | |
5409 | the prototyped case. Thus we choose to make the non-prototyped case work | |
5410 | for C and break the prototyped case, since the non-prototyped case is | |
5411 | probably much more common. (FIXME). */ | |
5412 | ||
5413 | static int | |
5414 | mips_coerce_float_to_double (struct type *formal, struct type *actual) | |
5415 | { | |
5416 | return current_language->la_language == language_c; | |
5417 | } | |
5418 | ||
47a8d4ba AC |
5419 | /* When debugging a 64 MIPS target running a 32 bit ABI, the size of |
5420 | the register stored on the stack (32) is different to its real raw | |
5421 | size (64). The below ensures that registers are fetched from the | |
5422 | stack using their ABI size and then stored into the RAW_BUFFER | |
5423 | using their raw size. | |
5424 | ||
5425 | The alternative to adding this function would be to add an ABI | |
5426 | macro - REGISTER_STACK_SIZE(). */ | |
5427 | ||
5428 | static void | |
acdb74a0 AC |
5429 | mips_get_saved_register (char *raw_buffer, |
5430 | int *optimized, | |
5431 | CORE_ADDR *addrp, | |
5432 | struct frame_info *frame, | |
5433 | int regnum, | |
5434 | enum lval_type *lval) | |
47a8d4ba AC |
5435 | { |
5436 | CORE_ADDR addr; | |
5437 | ||
5438 | if (!target_has_registers) | |
5439 | error ("No registers."); | |
5440 | ||
5441 | /* Normal systems don't optimize out things with register numbers. */ | |
5442 | if (optimized != NULL) | |
5443 | *optimized = 0; | |
5444 | addr = find_saved_register (frame, regnum); | |
5445 | if (addr != 0) | |
5446 | { | |
5447 | if (lval != NULL) | |
5448 | *lval = lval_memory; | |
5449 | if (regnum == SP_REGNUM) | |
5450 | { | |
5451 | if (raw_buffer != NULL) | |
5452 | { | |
5453 | /* Put it back in target format. */ | |
5454 | store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), | |
5455 | (LONGEST) addr); | |
5456 | } | |
5457 | if (addrp != NULL) | |
5458 | *addrp = 0; | |
5459 | return; | |
5460 | } | |
5461 | if (raw_buffer != NULL) | |
5462 | { | |
5463 | LONGEST val; | |
5464 | if (regnum < 32) | |
5465 | /* Only MIPS_SAVED_REGSIZE bytes of GP registers are | |
5466 | saved. */ | |
5467 | val = read_memory_integer (addr, MIPS_SAVED_REGSIZE); | |
5468 | else | |
5469 | val = read_memory_integer (addr, REGISTER_RAW_SIZE (regnum)); | |
5470 | store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), val); | |
5471 | } | |
5472 | } | |
5473 | else | |
5474 | { | |
5475 | if (lval != NULL) | |
5476 | *lval = lval_register; | |
5477 | addr = REGISTER_BYTE (regnum); | |
5478 | if (raw_buffer != NULL) | |
5479 | read_register_gen (regnum, raw_buffer); | |
5480 | } | |
5481 | if (addrp != NULL) | |
5482 | *addrp = addr; | |
5483 | } | |
2acceee2 | 5484 | |
f7b9e9fc AC |
5485 | /* Immediately after a function call, return the saved pc. |
5486 | Can't always go through the frames for this because on some machines | |
5487 | the new frame is not set up until the new function executes | |
5488 | some instructions. */ | |
5489 | ||
5490 | static CORE_ADDR | |
5491 | mips_saved_pc_after_call (struct frame_info *frame) | |
5492 | { | |
6c997a34 | 5493 | return read_signed_register (RA_REGNUM); |
f7b9e9fc AC |
5494 | } |
5495 | ||
5496 | ||
88c72b7d AC |
5497 | /* Convert a dbx stab register number (from `r' declaration) to a gdb |
5498 | REGNUM */ | |
5499 | ||
5500 | static int | |
5501 | mips_stab_reg_to_regnum (int num) | |
5502 | { | |
5503 | if (num < 32) | |
5504 | return num; | |
361d1df0 | 5505 | else |
88c72b7d AC |
5506 | return num + FP0_REGNUM - 38; |
5507 | } | |
5508 | ||
5509 | /* Convert a ecoff register number to a gdb REGNUM */ | |
5510 | ||
5511 | static int | |
5512 | mips_ecoff_reg_to_regnum (int num) | |
5513 | { | |
5514 | if (num < 32) | |
5515 | return num; | |
5516 | else | |
5517 | return num + FP0_REGNUM - 32; | |
5518 | } | |
5519 | ||
fc0c74b1 AC |
5520 | /* Convert an integer into an address. By first converting the value |
5521 | into a pointer and then extracting it signed, the address is | |
5522 | guarenteed to be correctly sign extended. */ | |
5523 | ||
5524 | static CORE_ADDR | |
5525 | mips_integer_to_address (struct type *type, void *buf) | |
5526 | { | |
5527 | char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5528 | LONGEST val = unpack_long (type, buf); | |
5529 | store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val); | |
5530 | return extract_signed_integer (tmp, | |
5531 | TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5532 | } | |
5533 | ||
caaa3122 DJ |
5534 | static void |
5535 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
5536 | { | |
5537 | enum mips_abi *abip = (enum mips_abi *) obj; | |
5538 | const char *name = bfd_get_section_name (abfd, sect); | |
5539 | ||
5540 | if (*abip != MIPS_ABI_UNKNOWN) | |
5541 | return; | |
5542 | ||
5543 | if (strncmp (name, ".mdebug.", 8) != 0) | |
5544 | return; | |
5545 | ||
5546 | if (strcmp (name, ".mdebug.abi32") == 0) | |
5547 | *abip = MIPS_ABI_O32; | |
5548 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
5549 | *abip = MIPS_ABI_N32; | |
e3bddbfa KB |
5550 | else if (strcmp (name, ".mdebug.abiN64") == 0) |
5551 | *abip = MIPS_ABI_N64; | |
caaa3122 DJ |
5552 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
5553 | *abip = MIPS_ABI_O64; | |
5554 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
5555 | *abip = MIPS_ABI_EABI32; | |
5556 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
5557 | *abip = MIPS_ABI_EABI64; | |
5558 | else | |
5559 | warning ("unsupported ABI %s.", name + 8); | |
5560 | } | |
5561 | ||
2e4ebe70 DJ |
5562 | static enum mips_abi |
5563 | global_mips_abi (void) | |
5564 | { | |
5565 | int i; | |
5566 | ||
5567 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
5568 | if (mips_abi_strings[i] == mips_abi_string) | |
5569 | return (enum mips_abi) i; | |
5570 | ||
5571 | internal_error (__FILE__, __LINE__, | |
5572 | "unknown ABI string"); | |
5573 | } | |
5574 | ||
c2d11a7d | 5575 | static struct gdbarch * |
acdb74a0 AC |
5576 | mips_gdbarch_init (struct gdbarch_info info, |
5577 | struct gdbarch_list *arches) | |
c2d11a7d JM |
5578 | { |
5579 | static LONGEST mips_call_dummy_words[] = | |
5580 | {0}; | |
5581 | struct gdbarch *gdbarch; | |
5582 | struct gdbarch_tdep *tdep; | |
5583 | int elf_flags; | |
2e4ebe70 | 5584 | enum mips_abi mips_abi, found_abi, wanted_abi; |
70f80edf | 5585 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; |
c2d11a7d | 5586 | |
1d06468c EZ |
5587 | /* Reset the disassembly info, in case it was set to something |
5588 | non-default. */ | |
5589 | tm_print_insn_info.flavour = bfd_target_unknown_flavour; | |
5590 | tm_print_insn_info.arch = bfd_arch_unknown; | |
5591 | tm_print_insn_info.mach = 0; | |
5592 | ||
70f80edf JT |
5593 | elf_flags = 0; |
5594 | ||
5595 | if (info.abfd) | |
5596 | { | |
5597 | /* First of all, extract the elf_flags, if available. */ | |
5598 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5599 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
5600 | ||
5601 | /* Try to determine the OS ABI of the object we are loading. If | |
5602 | we end up with `unknown', just leave it that way. */ | |
5603 | osabi = gdbarch_lookup_osabi (info.abfd); | |
5604 | } | |
c2d11a7d | 5605 | |
102182a9 | 5606 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
5607 | switch ((elf_flags & EF_MIPS_ABI)) |
5608 | { | |
5609 | case E_MIPS_ABI_O32: | |
5610 | mips_abi = MIPS_ABI_O32; | |
5611 | break; | |
5612 | case E_MIPS_ABI_O64: | |
5613 | mips_abi = MIPS_ABI_O64; | |
5614 | break; | |
5615 | case E_MIPS_ABI_EABI32: | |
5616 | mips_abi = MIPS_ABI_EABI32; | |
5617 | break; | |
5618 | case E_MIPS_ABI_EABI64: | |
4a7f7ba8 | 5619 | mips_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
5620 | break; |
5621 | default: | |
acdb74a0 AC |
5622 | if ((elf_flags & EF_MIPS_ABI2)) |
5623 | mips_abi = MIPS_ABI_N32; | |
5624 | else | |
5625 | mips_abi = MIPS_ABI_UNKNOWN; | |
0dadbba0 AC |
5626 | break; |
5627 | } | |
acdb74a0 | 5628 | |
caaa3122 DJ |
5629 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
5630 | if (mips_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) | |
5631 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &mips_abi); | |
5632 | ||
2e4ebe70 DJ |
5633 | /* If we have no bfd, then mips_abi will still be MIPS_ABI_UNKNOWN. |
5634 | Use the ABI from the last architecture if there is one. */ | |
5635 | if (info.abfd == NULL && arches != NULL) | |
5636 | mips_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
5637 | ||
32a6503c | 5638 | /* Try the architecture for any hint of the correct ABI. */ |
bf64bfd6 AC |
5639 | if (mips_abi == MIPS_ABI_UNKNOWN |
5640 | && info.bfd_arch_info != NULL | |
5641 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5642 | { | |
5643 | switch (info.bfd_arch_info->mach) | |
5644 | { | |
5645 | case bfd_mach_mips3900: | |
5646 | mips_abi = MIPS_ABI_EABI32; | |
5647 | break; | |
5648 | case bfd_mach_mips4100: | |
5649 | case bfd_mach_mips5000: | |
5650 | mips_abi = MIPS_ABI_EABI64; | |
5651 | break; | |
1d06468c EZ |
5652 | case bfd_mach_mips8000: |
5653 | case bfd_mach_mips10000: | |
32a6503c KB |
5654 | /* On Irix, ELF64 executables use the N64 ABI. The |
5655 | pseudo-sections which describe the ABI aren't present | |
5656 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
5657 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
5658 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
5659 | mips_abi = MIPS_ABI_N64; | |
5660 | else | |
5661 | mips_abi = MIPS_ABI_N32; | |
1d06468c | 5662 | break; |
bf64bfd6 AC |
5663 | } |
5664 | } | |
2e4ebe70 | 5665 | |
2e4ebe70 DJ |
5666 | if (mips_abi == MIPS_ABI_UNKNOWN) |
5667 | mips_abi = MIPS_ABI_O32; | |
5668 | ||
5669 | /* Now that we have found what the ABI for this binary would be, | |
5670 | check whether the user is overriding it. */ | |
5671 | found_abi = mips_abi; | |
5672 | wanted_abi = global_mips_abi (); | |
5673 | if (wanted_abi != MIPS_ABI_UNKNOWN) | |
5674 | mips_abi = wanted_abi; | |
5675 | ||
4b9b3959 AC |
5676 | if (gdbarch_debug) |
5677 | { | |
5678 | fprintf_unfiltered (gdb_stdlog, | |
9ace0497 | 5679 | "mips_gdbarch_init: elf_flags = 0x%08x\n", |
4b9b3959 | 5680 | elf_flags); |
4b9b3959 AC |
5681 | fprintf_unfiltered (gdb_stdlog, |
5682 | "mips_gdbarch_init: mips_abi = %d\n", | |
5683 | mips_abi); | |
2e4ebe70 DJ |
5684 | fprintf_unfiltered (gdb_stdlog, |
5685 | "mips_gdbarch_init: found_mips_abi = %d\n", | |
5686 | found_abi); | |
4b9b3959 | 5687 | } |
0dadbba0 | 5688 | |
c2d11a7d JM |
5689 | /* try to find a pre-existing architecture */ |
5690 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
5691 | arches != NULL; | |
5692 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
5693 | { | |
5694 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 5695 | using. */ |
9103eae0 | 5696 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 5697 | continue; |
9103eae0 | 5698 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 5699 | continue; |
70f80edf JT |
5700 | if (gdbarch_tdep (arches->gdbarch)->osabi == osabi) |
5701 | return arches->gdbarch; | |
c2d11a7d JM |
5702 | } |
5703 | ||
102182a9 | 5704 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
5705 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
5706 | gdbarch = gdbarch_alloc (&info, tdep); | |
5707 | tdep->elf_flags = elf_flags; | |
70f80edf | 5708 | tdep->osabi = osabi; |
c2d11a7d | 5709 | |
102182a9 | 5710 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
5711 | set_gdbarch_short_bit (gdbarch, 16); |
5712 | set_gdbarch_int_bit (gdbarch, 32); | |
5713 | set_gdbarch_float_bit (gdbarch, 32); | |
5714 | set_gdbarch_double_bit (gdbarch, 64); | |
5715 | set_gdbarch_long_double_bit (gdbarch, 64); | |
46cd78fb | 5716 | set_gdbarch_register_raw_size (gdbarch, mips_register_raw_size); |
d05285fa MS |
5717 | set_gdbarch_max_register_raw_size (gdbarch, 8); |
5718 | set_gdbarch_max_register_virtual_size (gdbarch, 8); | |
2e4ebe70 | 5719 | tdep->found_abi = found_abi; |
0dadbba0 | 5720 | tdep->mips_abi = mips_abi; |
1d06468c | 5721 | |
f7ab6ec6 MS |
5722 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
5723 | mips_elf_make_msymbol_special); | |
5724 | ||
0dadbba0 | 5725 | switch (mips_abi) |
c2d11a7d | 5726 | { |
0dadbba0 | 5727 | case MIPS_ABI_O32: |
46cac009 | 5728 | set_gdbarch_push_arguments (gdbarch, mips_o32_push_arguments); |
ebba8386 | 5729 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_o32_store_return_value); |
cb1d2653 | 5730 | set_gdbarch_extract_return_value (gdbarch, mips_o32_extract_return_value); |
a5ea2558 | 5731 | tdep->mips_default_saved_regsize = 4; |
0dadbba0 | 5732 | tdep->mips_default_stack_argsize = 4; |
c2d11a7d | 5733 | tdep->mips_fp_register_double = 0; |
acdb74a0 AC |
5734 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
5735 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1; | |
5213ab06 | 5736 | tdep->gdb_target_is_mips64 = 0; |
4014092b | 5737 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5738 | set_gdbarch_long_bit (gdbarch, 32); |
5739 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5740 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8b389c40 MS |
5741 | set_gdbarch_reg_struct_has_addr (gdbarch, |
5742 | mips_o32_reg_struct_has_addr); | |
cb811fe7 MS |
5743 | set_gdbarch_use_struct_convention (gdbarch, |
5744 | mips_o32_use_struct_convention); | |
c2d11a7d | 5745 | break; |
0dadbba0 | 5746 | case MIPS_ABI_O64: |
46cac009 | 5747 | set_gdbarch_push_arguments (gdbarch, mips_o64_push_arguments); |
ebba8386 | 5748 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_o64_store_return_value); |
46cac009 | 5749 | set_gdbarch_deprecated_extract_return_value (gdbarch, mips_o64_extract_return_value); |
a5ea2558 | 5750 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 | 5751 | tdep->mips_default_stack_argsize = 8; |
c2d11a7d | 5752 | tdep->mips_fp_register_double = 1; |
acdb74a0 AC |
5753 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
5754 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1; | |
5213ab06 | 5755 | tdep->gdb_target_is_mips64 = 1; |
361d1df0 | 5756 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5757 | set_gdbarch_long_bit (gdbarch, 32); |
5758 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5759 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8b389c40 MS |
5760 | set_gdbarch_reg_struct_has_addr (gdbarch, |
5761 | mips_o32_reg_struct_has_addr); | |
cb811fe7 MS |
5762 | set_gdbarch_use_struct_convention (gdbarch, |
5763 | mips_o32_use_struct_convention); | |
c2d11a7d | 5764 | break; |
0dadbba0 | 5765 | case MIPS_ABI_EABI32: |
46e0f506 | 5766 | set_gdbarch_push_arguments (gdbarch, mips_eabi_push_arguments); |
ebba8386 | 5767 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_eabi_store_return_value); |
46cac009 | 5768 | set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value); |
a5ea2558 | 5769 | tdep->mips_default_saved_regsize = 4; |
0dadbba0 | 5770 | tdep->mips_default_stack_argsize = 4; |
c2d11a7d | 5771 | tdep->mips_fp_register_double = 0; |
acdb74a0 AC |
5772 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
5773 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1; | |
5213ab06 | 5774 | tdep->gdb_target_is_mips64 = 0; |
4014092b | 5775 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5776 | set_gdbarch_long_bit (gdbarch, 32); |
5777 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5778 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8b389c40 MS |
5779 | set_gdbarch_reg_struct_has_addr (gdbarch, |
5780 | mips_eabi_reg_struct_has_addr); | |
cb811fe7 MS |
5781 | set_gdbarch_use_struct_convention (gdbarch, |
5782 | mips_eabi_use_struct_convention); | |
c2d11a7d | 5783 | break; |
0dadbba0 | 5784 | case MIPS_ABI_EABI64: |
46e0f506 | 5785 | set_gdbarch_push_arguments (gdbarch, mips_eabi_push_arguments); |
ebba8386 | 5786 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_eabi_store_return_value); |
46cac009 | 5787 | set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value); |
a5ea2558 | 5788 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 | 5789 | tdep->mips_default_stack_argsize = 8; |
c2d11a7d | 5790 | tdep->mips_fp_register_double = 1; |
acdb74a0 AC |
5791 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
5792 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1; | |
5213ab06 | 5793 | tdep->gdb_target_is_mips64 = 1; |
4014092b | 5794 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5795 | set_gdbarch_long_bit (gdbarch, 64); |
5796 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5797 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8b389c40 MS |
5798 | set_gdbarch_reg_struct_has_addr (gdbarch, |
5799 | mips_eabi_reg_struct_has_addr); | |
cb811fe7 MS |
5800 | set_gdbarch_use_struct_convention (gdbarch, |
5801 | mips_eabi_use_struct_convention); | |
c2d11a7d | 5802 | break; |
0dadbba0 | 5803 | case MIPS_ABI_N32: |
cb3d25d1 | 5804 | set_gdbarch_push_arguments (gdbarch, mips_n32n64_push_arguments); |
ebba8386 | 5805 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_n32n64_store_return_value); |
88658117 | 5806 | set_gdbarch_extract_return_value (gdbarch, mips_n32n64_extract_return_value); |
63db5580 | 5807 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 AC |
5808 | tdep->mips_default_stack_argsize = 8; |
5809 | tdep->mips_fp_register_double = 1; | |
acdb74a0 AC |
5810 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
5811 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1; | |
6acdf5c7 | 5812 | tdep->gdb_target_is_mips64 = 1; |
4014092b | 5813 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
5814 | set_gdbarch_long_bit (gdbarch, 32); |
5815 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5816 | set_gdbarch_long_long_bit (gdbarch, 64); | |
1d06468c EZ |
5817 | |
5818 | /* Set up the disassembler info, so that we get the right | |
28d169de KB |
5819 | register names from libopcodes. */ |
5820 | tm_print_insn_info.flavour = bfd_target_elf_flavour; | |
5821 | tm_print_insn_info.arch = bfd_arch_mips; | |
5822 | if (info.bfd_arch_info != NULL | |
5823 | && info.bfd_arch_info->arch == bfd_arch_mips | |
5824 | && info.bfd_arch_info->mach) | |
5825 | tm_print_insn_info.mach = info.bfd_arch_info->mach; | |
5826 | else | |
5827 | tm_print_insn_info.mach = bfd_mach_mips8000; | |
cb811fe7 MS |
5828 | |
5829 | set_gdbarch_use_struct_convention (gdbarch, | |
5830 | mips_n32n64_use_struct_convention); | |
8b389c40 MS |
5831 | set_gdbarch_reg_struct_has_addr (gdbarch, |
5832 | mips_n32n64_reg_struct_has_addr); | |
28d169de KB |
5833 | break; |
5834 | case MIPS_ABI_N64: | |
cb3d25d1 | 5835 | set_gdbarch_push_arguments (gdbarch, mips_n32n64_push_arguments); |
ebba8386 | 5836 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_n32n64_store_return_value); |
88658117 | 5837 | set_gdbarch_extract_return_value (gdbarch, mips_n32n64_extract_return_value); |
28d169de KB |
5838 | tdep->mips_default_saved_regsize = 8; |
5839 | tdep->mips_default_stack_argsize = 8; | |
5840 | tdep->mips_fp_register_double = 1; | |
5841 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; | |
5842 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1; | |
28d169de KB |
5843 | tdep->gdb_target_is_mips64 = 1; |
5844 | tdep->default_mask_address_p = 0; | |
5845 | set_gdbarch_long_bit (gdbarch, 64); | |
5846 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5847 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5848 | ||
5849 | /* Set up the disassembler info, so that we get the right | |
1d06468c EZ |
5850 | register names from libopcodes. */ |
5851 | tm_print_insn_info.flavour = bfd_target_elf_flavour; | |
5852 | tm_print_insn_info.arch = bfd_arch_mips; | |
5853 | if (info.bfd_arch_info != NULL | |
5854 | && info.bfd_arch_info->arch == bfd_arch_mips | |
5855 | && info.bfd_arch_info->mach) | |
5856 | tm_print_insn_info.mach = info.bfd_arch_info->mach; | |
5857 | else | |
5858 | tm_print_insn_info.mach = bfd_mach_mips8000; | |
cb811fe7 MS |
5859 | |
5860 | set_gdbarch_use_struct_convention (gdbarch, | |
5861 | mips_n32n64_use_struct_convention); | |
8b389c40 MS |
5862 | set_gdbarch_reg_struct_has_addr (gdbarch, |
5863 | mips_n32n64_reg_struct_has_addr); | |
0dadbba0 | 5864 | break; |
c2d11a7d | 5865 | default: |
2e4ebe70 DJ |
5866 | internal_error (__FILE__, __LINE__, |
5867 | "unknown ABI in switch"); | |
c2d11a7d JM |
5868 | } |
5869 | ||
a5ea2558 AC |
5870 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
5871 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
5872 | comment: | |
5873 | ||
5874 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
5875 | flag in object files because to do so would make it impossible to | |
102182a9 | 5876 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 5877 | unnecessarily restrictive. |
361d1df0 | 5878 | |
a5ea2558 AC |
5879 | We could solve this problem by adding "-gp32" multilibs to gcc, |
5880 | but to set this flag before gcc is built with such multilibs will | |
5881 | break too many systems.'' | |
5882 | ||
5883 | But even more unhelpfully, the default linker output target for | |
5884 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
5885 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 5886 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
5887 | this flag to detect 32-bit mode would do the wrong thing given |
5888 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 5889 | as 32-bit programs by default. */ |
a5ea2558 | 5890 | |
c2d11a7d JM |
5891 | /* enable/disable the MIPS FPU */ |
5892 | if (!mips_fpu_type_auto) | |
5893 | tdep->mips_fpu_type = mips_fpu_type; | |
5894 | else if (info.bfd_arch_info != NULL | |
5895 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5896 | switch (info.bfd_arch_info->mach) | |
5897 | { | |
b0069a17 | 5898 | case bfd_mach_mips3900: |
c2d11a7d | 5899 | case bfd_mach_mips4100: |
ed9a39eb | 5900 | case bfd_mach_mips4111: |
c2d11a7d JM |
5901 | tdep->mips_fpu_type = MIPS_FPU_NONE; |
5902 | break; | |
bf64bfd6 AC |
5903 | case bfd_mach_mips4650: |
5904 | tdep->mips_fpu_type = MIPS_FPU_SINGLE; | |
5905 | break; | |
c2d11a7d JM |
5906 | default: |
5907 | tdep->mips_fpu_type = MIPS_FPU_DOUBLE; | |
5908 | break; | |
5909 | } | |
5910 | else | |
5911 | tdep->mips_fpu_type = MIPS_FPU_DOUBLE; | |
5912 | ||
5913 | /* MIPS version of register names. NOTE: At present the MIPS | |
5914 | register name management is part way between the old - | |
5915 | #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr). | |
102182a9 | 5916 | Further work on it is required. */ |
18f81521 MS |
5917 | /* NOTE: many targets (esp. embedded) do not go thru the |
5918 | gdbarch_register_name vector at all, instead bypassing it | |
5919 | by defining REGISTER_NAMES. */ | |
c2d11a7d | 5920 | set_gdbarch_register_name (gdbarch, mips_register_name); |
6c997a34 | 5921 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
c2d11a7d JM |
5922 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); |
5923 | set_gdbarch_read_fp (gdbarch, generic_target_read_fp); | |
bcb0cc15 | 5924 | set_gdbarch_read_sp (gdbarch, mips_read_sp); |
c2d11a7d JM |
5925 | set_gdbarch_write_sp (gdbarch, generic_target_write_sp); |
5926 | ||
102182a9 MS |
5927 | /* Add/remove bits from an address. The MIPS needs be careful to |
5928 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
5929 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
5930 | ||
10312cc4 AC |
5931 | /* There's a mess in stack frame creation. See comments in |
5932 | blockframe.c near reference to INIT_FRAME_PC_FIRST. */ | |
5933 | set_gdbarch_init_frame_pc_first (gdbarch, mips_init_frame_pc_first); | |
7824d2f2 | 5934 | set_gdbarch_init_frame_pc (gdbarch, init_frame_pc_noop); |
10312cc4 | 5935 | |
102182a9 | 5936 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d AC |
5937 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
5938 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, mips_ecoff_reg_to_regnum); | |
5939 | ||
c2d11a7d JM |
5940 | /* Initialize a frame */ |
5941 | set_gdbarch_init_extra_frame_info (gdbarch, mips_init_extra_frame_info); | |
d28e01f4 | 5942 | set_gdbarch_frame_init_saved_regs (gdbarch, mips_frame_init_saved_regs); |
c2d11a7d JM |
5943 | |
5944 | /* MIPS version of CALL_DUMMY */ | |
5945 | ||
5946 | set_gdbarch_call_dummy_p (gdbarch, 1); | |
5947 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); | |
5948 | set_gdbarch_use_generic_dummy_frames (gdbarch, 0); | |
5949 | set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT); | |
5950 | set_gdbarch_call_dummy_address (gdbarch, mips_call_dummy_address); | |
f7ab6ec6 MS |
5951 | set_gdbarch_push_return_address (gdbarch, mips_push_return_address); |
5952 | set_gdbarch_push_dummy_frame (gdbarch, mips_push_dummy_frame); | |
5953 | set_gdbarch_pop_frame (gdbarch, mips_pop_frame); | |
c2d11a7d JM |
5954 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); |
5955 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); | |
5956 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); | |
5957 | set_gdbarch_call_dummy_length (gdbarch, 0); | |
f7ab6ec6 | 5958 | set_gdbarch_fix_call_dummy (gdbarch, mips_fix_call_dummy); |
c2d11a7d JM |
5959 | set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_at_entry_point); |
5960 | set_gdbarch_call_dummy_words (gdbarch, mips_call_dummy_words); | |
5961 | set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (mips_call_dummy_words)); | |
5962 | set_gdbarch_push_return_address (gdbarch, mips_push_return_address); | |
bf1f5b4c | 5963 | set_gdbarch_register_convertible (gdbarch, mips_register_convertible); |
d05285fa MS |
5964 | set_gdbarch_register_convert_to_virtual (gdbarch, |
5965 | mips_register_convert_to_virtual); | |
5966 | set_gdbarch_register_convert_to_raw (gdbarch, | |
5967 | mips_register_convert_to_raw); | |
5968 | ||
b9a8e3bf | 5969 | set_gdbarch_coerce_float_to_double (gdbarch, mips_coerce_float_to_double); |
c2d11a7d | 5970 | |
b5d1566e | 5971 | set_gdbarch_frame_chain (gdbarch, mips_frame_chain); |
c4093a6a | 5972 | set_gdbarch_frame_chain_valid (gdbarch, func_frame_chain_valid); |
b5d1566e MS |
5973 | set_gdbarch_frameless_function_invocation (gdbarch, |
5974 | generic_frameless_function_invocation_not); | |
5975 | set_gdbarch_frame_saved_pc (gdbarch, mips_frame_saved_pc); | |
5976 | set_gdbarch_frame_args_address (gdbarch, default_frame_address); | |
5977 | set_gdbarch_frame_locals_address (gdbarch, default_frame_address); | |
5978 | set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown); | |
5979 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
5980 | ||
47a8d4ba | 5981 | set_gdbarch_get_saved_register (gdbarch, mips_get_saved_register); |
c2d11a7d | 5982 | |
f7b9e9fc AC |
5983 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
5984 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
5985 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
f7b9e9fc AC |
5986 | |
5987 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
5988 | set_gdbarch_saved_pc_after_call (gdbarch, mips_saved_pc_after_call); | |
5989 | ||
fc0c74b1 AC |
5990 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
5991 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
5992 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 5993 | |
102182a9 MS |
5994 | set_gdbarch_function_start_offset (gdbarch, 0); |
5995 | ||
32a6503c KB |
5996 | /* There are MIPS targets which do not yet use this since they still |
5997 | define REGISTER_VIRTUAL_TYPE. */ | |
78fde5f8 | 5998 | set_gdbarch_register_virtual_type (gdbarch, mips_register_virtual_type); |
102182a9 | 5999 | set_gdbarch_register_virtual_size (gdbarch, generic_register_size); |
78fde5f8 | 6000 | |
bf1f5b4c | 6001 | set_gdbarch_do_registers_info (gdbarch, mips_do_registers_info); |
102182a9 | 6002 | set_gdbarch_pc_in_sigtramp (gdbarch, mips_pc_in_sigtramp); |
bf1f5b4c | 6003 | |
70f80edf JT |
6004 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
6005 | gdbarch_init_osabi (info, gdbarch, osabi); | |
6006 | ||
2f1488ce MS |
6007 | set_gdbarch_store_struct_return (gdbarch, mips_store_struct_return); |
6008 | set_gdbarch_extract_struct_value_address (gdbarch, | |
6009 | mips_extract_struct_value_address); | |
757a7cc6 MS |
6010 | |
6011 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_stub); | |
6012 | ||
6013 | set_gdbarch_in_solib_call_trampoline (gdbarch, mips_in_call_stub); | |
e41b17f0 | 6014 | set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); |
757a7cc6 | 6015 | |
4b9b3959 AC |
6016 | return gdbarch; |
6017 | } | |
6018 | ||
2e4ebe70 DJ |
6019 | static void |
6020 | mips_abi_update (char *ignore_args, int from_tty, | |
6021 | struct cmd_list_element *c) | |
6022 | { | |
6023 | struct gdbarch_info info; | |
6024 | ||
6025 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
6026 | mips_gdbarch_init will take care of the rest. */ | |
6027 | gdbarch_info_init (&info); | |
6028 | gdbarch_update_p (info); | |
6029 | } | |
6030 | ||
4b9b3959 AC |
6031 | static void |
6032 | mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
6033 | { | |
6034 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
6035 | if (tdep != NULL) | |
c2d11a7d | 6036 | { |
acdb74a0 AC |
6037 | int ef_mips_arch; |
6038 | int ef_mips_32bitmode; | |
6039 | /* determine the ISA */ | |
6040 | switch (tdep->elf_flags & EF_MIPS_ARCH) | |
6041 | { | |
6042 | case E_MIPS_ARCH_1: | |
6043 | ef_mips_arch = 1; | |
6044 | break; | |
6045 | case E_MIPS_ARCH_2: | |
6046 | ef_mips_arch = 2; | |
6047 | break; | |
6048 | case E_MIPS_ARCH_3: | |
6049 | ef_mips_arch = 3; | |
6050 | break; | |
6051 | case E_MIPS_ARCH_4: | |
93d56215 | 6052 | ef_mips_arch = 4; |
acdb74a0 AC |
6053 | break; |
6054 | default: | |
93d56215 | 6055 | ef_mips_arch = 0; |
acdb74a0 AC |
6056 | break; |
6057 | } | |
6058 | /* determine the size of a pointer */ | |
6059 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); | |
4b9b3959 AC |
6060 | fprintf_unfiltered (file, |
6061 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 6062 | tdep->elf_flags); |
4b9b3959 | 6063 | fprintf_unfiltered (file, |
acdb74a0 AC |
6064 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
6065 | ef_mips_32bitmode); | |
6066 | fprintf_unfiltered (file, | |
6067 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
6068 | ef_mips_arch); | |
6069 | fprintf_unfiltered (file, | |
6070 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6071 | tdep->mips_abi, | |
2e4ebe70 | 6072 | mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
6073 | fprintf_unfiltered (file, |
6074 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
6075 | mips_mask_address_p (), | |
6076 | tdep->default_mask_address_p); | |
c2d11a7d | 6077 | } |
4b9b3959 AC |
6078 | fprintf_unfiltered (file, |
6079 | "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n", | |
6080 | FP_REGISTER_DOUBLE); | |
6081 | fprintf_unfiltered (file, | |
6082 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
6083 | MIPS_DEFAULT_FPU_TYPE, | |
6084 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6085 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6086 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6087 | : "???")); | |
6088 | fprintf_unfiltered (file, | |
6089 | "mips_dump_tdep: MIPS_EABI = %d\n", | |
6090 | MIPS_EABI); | |
6091 | fprintf_unfiltered (file, | |
acdb74a0 AC |
6092 | "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n", |
6093 | MIPS_LAST_FP_ARG_REGNUM, | |
6094 | MIPS_LAST_FP_ARG_REGNUM - FPA0_REGNUM + 1); | |
4b9b3959 AC |
6095 | fprintf_unfiltered (file, |
6096 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
6097 | MIPS_FPU_TYPE, | |
6098 | (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6099 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6100 | : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6101 | : "???")); | |
6102 | fprintf_unfiltered (file, | |
6103 | "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n", | |
6104 | MIPS_DEFAULT_SAVED_REGSIZE); | |
4b9b3959 AC |
6105 | fprintf_unfiltered (file, |
6106 | "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n", | |
6107 | FP_REGISTER_DOUBLE); | |
4b9b3959 AC |
6108 | fprintf_unfiltered (file, |
6109 | "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n", | |
6110 | MIPS_DEFAULT_STACK_ARGSIZE); | |
6111 | fprintf_unfiltered (file, | |
6112 | "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n", | |
6113 | MIPS_STACK_ARGSIZE); | |
6114 | fprintf_unfiltered (file, | |
6115 | "mips_dump_tdep: MIPS_REGSIZE = %d\n", | |
6116 | MIPS_REGSIZE); | |
2475bac3 AC |
6117 | fprintf_unfiltered (file, |
6118 | "mips_dump_tdep: A0_REGNUM = %d\n", | |
6119 | A0_REGNUM); | |
6120 | fprintf_unfiltered (file, | |
6121 | "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n", | |
6122 | XSTRING (ADDR_BITS_REMOVE(ADDR))); | |
6123 | fprintf_unfiltered (file, | |
6124 | "mips_dump_tdep: ATTACH_DETACH # %s\n", | |
6125 | XSTRING (ATTACH_DETACH)); | |
6126 | fprintf_unfiltered (file, | |
6127 | "mips_dump_tdep: BADVADDR_REGNUM = %d\n", | |
6128 | BADVADDR_REGNUM); | |
6129 | fprintf_unfiltered (file, | |
6130 | "mips_dump_tdep: BIG_BREAKPOINT = delete?\n"); | |
6131 | fprintf_unfiltered (file, | |
6132 | "mips_dump_tdep: CAUSE_REGNUM = %d\n", | |
6133 | CAUSE_REGNUM); | |
6134 | fprintf_unfiltered (file, | |
6135 | "mips_dump_tdep: CPLUS_MARKER = %c\n", | |
6136 | CPLUS_MARKER); | |
2475bac3 AC |
6137 | fprintf_unfiltered (file, |
6138 | "mips_dump_tdep: DO_REGISTERS_INFO # %s\n", | |
6139 | XSTRING (DO_REGISTERS_INFO)); | |
6140 | fprintf_unfiltered (file, | |
6141 | "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n", | |
6142 | XSTRING (DWARF_REG_TO_REGNUM (REGNUM))); | |
6143 | fprintf_unfiltered (file, | |
6144 | "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n", | |
6145 | XSTRING (ECOFF_REG_TO_REGNUM (REGNUM))); | |
2475bac3 AC |
6146 | fprintf_unfiltered (file, |
6147 | "mips_dump_tdep: FCRCS_REGNUM = %d\n", | |
6148 | FCRCS_REGNUM); | |
6149 | fprintf_unfiltered (file, | |
6150 | "mips_dump_tdep: FCRIR_REGNUM = %d\n", | |
6151 | FCRIR_REGNUM); | |
6152 | fprintf_unfiltered (file, | |
6153 | "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n", | |
6154 | FIRST_EMBED_REGNUM); | |
6155 | fprintf_unfiltered (file, | |
6156 | "mips_dump_tdep: FPA0_REGNUM = %d\n", | |
6157 | FPA0_REGNUM); | |
6158 | fprintf_unfiltered (file, | |
6159 | "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n", | |
6160 | GDB_TARGET_IS_MIPS64); | |
6161 | fprintf_unfiltered (file, | |
6162 | "mips_dump_tdep: GDB_TARGET_MASK_DISAS_PC # %s\n", | |
6163 | XSTRING (GDB_TARGET_MASK_DISAS_PC (PC))); | |
6164 | fprintf_unfiltered (file, | |
6165 | "mips_dump_tdep: GDB_TARGET_UNMASK_DISAS_PC # %s\n", | |
6166 | XSTRING (GDB_TARGET_UNMASK_DISAS_PC (PC))); | |
6167 | fprintf_unfiltered (file, | |
6168 | "mips_dump_tdep: GEN_REG_SAVE_MASK = %d\n", | |
6169 | GEN_REG_SAVE_MASK); | |
6170 | fprintf_unfiltered (file, | |
6171 | "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n", | |
6172 | XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT)); | |
6173 | fprintf_unfiltered (file, | |
6174 | "mips_dump_tdep: HI_REGNUM = %d\n", | |
6175 | HI_REGNUM); | |
6176 | fprintf_unfiltered (file, | |
6177 | "mips_dump_tdep: IDT_BIG_BREAKPOINT = delete?\n"); | |
6178 | fprintf_unfiltered (file, | |
6179 | "mips_dump_tdep: IDT_LITTLE_BREAKPOINT = delete?\n"); | |
6180 | fprintf_unfiltered (file, | |
6181 | "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n", | |
6182 | XSTRING (IGNORE_HELPER_CALL (PC))); | |
2475bac3 AC |
6183 | fprintf_unfiltered (file, |
6184 | "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n", | |
6185 | XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME))); | |
6186 | fprintf_unfiltered (file, | |
6187 | "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n", | |
6188 | XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME))); | |
6189 | fprintf_unfiltered (file, | |
6190 | "mips_dump_tdep: IS_MIPS16_ADDR = FIXME!\n"); | |
6191 | fprintf_unfiltered (file, | |
6192 | "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n", | |
6193 | LAST_EMBED_REGNUM); | |
6194 | fprintf_unfiltered (file, | |
6195 | "mips_dump_tdep: LITTLE_BREAKPOINT = delete?\n"); | |
6196 | fprintf_unfiltered (file, | |
6197 | "mips_dump_tdep: LO_REGNUM = %d\n", | |
6198 | LO_REGNUM); | |
6199 | #ifdef MACHINE_CPROC_FP_OFFSET | |
6200 | fprintf_unfiltered (file, | |
6201 | "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n", | |
6202 | MACHINE_CPROC_FP_OFFSET); | |
6203 | #endif | |
6204 | #ifdef MACHINE_CPROC_PC_OFFSET | |
6205 | fprintf_unfiltered (file, | |
6206 | "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n", | |
6207 | MACHINE_CPROC_PC_OFFSET); | |
6208 | #endif | |
6209 | #ifdef MACHINE_CPROC_SP_OFFSET | |
6210 | fprintf_unfiltered (file, | |
6211 | "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n", | |
6212 | MACHINE_CPROC_SP_OFFSET); | |
6213 | #endif | |
6214 | fprintf_unfiltered (file, | |
6215 | "mips_dump_tdep: MAKE_MIPS16_ADDR = FIXME!\n"); | |
6216 | fprintf_unfiltered (file, | |
6217 | "mips_dump_tdep: MIPS16_BIG_BREAKPOINT = delete?\n"); | |
6218 | fprintf_unfiltered (file, | |
6219 | "mips_dump_tdep: MIPS16_INSTLEN = %d\n", | |
6220 | MIPS16_INSTLEN); | |
6221 | fprintf_unfiltered (file, | |
6222 | "mips_dump_tdep: MIPS16_LITTLE_BREAKPOINT = delete?\n"); | |
6223 | fprintf_unfiltered (file, | |
6224 | "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n"); | |
6225 | fprintf_unfiltered (file, | |
6226 | "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n"); | |
6227 | fprintf_unfiltered (file, | |
6228 | "mips_dump_tdep: MIPS_INSTLEN = %d\n", | |
6229 | MIPS_INSTLEN); | |
6230 | fprintf_unfiltered (file, | |
acdb74a0 AC |
6231 | "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n", |
6232 | MIPS_LAST_ARG_REGNUM, | |
6233 | MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1); | |
2475bac3 AC |
6234 | fprintf_unfiltered (file, |
6235 | "mips_dump_tdep: MIPS_NUMREGS = %d\n", | |
6236 | MIPS_NUMREGS); | |
6237 | fprintf_unfiltered (file, | |
6238 | "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n"); | |
6239 | fprintf_unfiltered (file, | |
6240 | "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n", | |
6241 | MIPS_SAVED_REGSIZE); | |
2475bac3 AC |
6242 | fprintf_unfiltered (file, |
6243 | "mips_dump_tdep: OP_LDFPR = used?\n"); | |
6244 | fprintf_unfiltered (file, | |
6245 | "mips_dump_tdep: OP_LDGPR = used?\n"); | |
6246 | fprintf_unfiltered (file, | |
6247 | "mips_dump_tdep: PMON_BIG_BREAKPOINT = delete?\n"); | |
6248 | fprintf_unfiltered (file, | |
6249 | "mips_dump_tdep: PMON_LITTLE_BREAKPOINT = delete?\n"); | |
6250 | fprintf_unfiltered (file, | |
6251 | "mips_dump_tdep: PRID_REGNUM = %d\n", | |
6252 | PRID_REGNUM); | |
6253 | fprintf_unfiltered (file, | |
6254 | "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n", | |
6255 | XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME))); | |
6256 | fprintf_unfiltered (file, | |
6257 | "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n"); | |
6258 | fprintf_unfiltered (file, | |
6259 | "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n"); | |
6260 | fprintf_unfiltered (file, | |
6261 | "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n"); | |
6262 | fprintf_unfiltered (file, | |
6263 | "mips_dump_tdep: PROC_FRAME_REG = function?\n"); | |
6264 | fprintf_unfiltered (file, | |
6265 | "mips_dump_tdep: PROC_FREG_MASK = function?\n"); | |
6266 | fprintf_unfiltered (file, | |
6267 | "mips_dump_tdep: PROC_FREG_OFFSET = function?\n"); | |
6268 | fprintf_unfiltered (file, | |
6269 | "mips_dump_tdep: PROC_HIGH_ADDR = function?\n"); | |
6270 | fprintf_unfiltered (file, | |
6271 | "mips_dump_tdep: PROC_LOW_ADDR = function?\n"); | |
6272 | fprintf_unfiltered (file, | |
6273 | "mips_dump_tdep: PROC_PC_REG = function?\n"); | |
6274 | fprintf_unfiltered (file, | |
6275 | "mips_dump_tdep: PROC_REG_MASK = function?\n"); | |
6276 | fprintf_unfiltered (file, | |
6277 | "mips_dump_tdep: PROC_REG_OFFSET = function?\n"); | |
6278 | fprintf_unfiltered (file, | |
6279 | "mips_dump_tdep: PROC_SYMBOL = function?\n"); | |
6280 | fprintf_unfiltered (file, | |
6281 | "mips_dump_tdep: PS_REGNUM = %d\n", | |
6282 | PS_REGNUM); | |
6283 | fprintf_unfiltered (file, | |
6284 | "mips_dump_tdep: PUSH_FP_REGNUM = %d\n", | |
6285 | PUSH_FP_REGNUM); | |
6286 | fprintf_unfiltered (file, | |
6287 | "mips_dump_tdep: RA_REGNUM = %d\n", | |
6288 | RA_REGNUM); | |
6289 | fprintf_unfiltered (file, | |
6290 | "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n", | |
6291 | XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM, VALTYPE, RAW_BUFFER))); | |
6292 | fprintf_unfiltered (file, | |
6293 | "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n", | |
6294 | XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM, VALTYPE, RAW_BUFFER))); | |
6295 | fprintf_unfiltered (file, | |
6296 | "mips_dump_tdep: REGISTER_NAMES = delete?\n"); | |
6297 | fprintf_unfiltered (file, | |
6298 | "mips_dump_tdep: ROUND_DOWN = function?\n"); | |
6299 | fprintf_unfiltered (file, | |
6300 | "mips_dump_tdep: ROUND_UP = function?\n"); | |
6301 | #ifdef SAVED_BYTES | |
6302 | fprintf_unfiltered (file, | |
6303 | "mips_dump_tdep: SAVED_BYTES = %d\n", | |
6304 | SAVED_BYTES); | |
6305 | #endif | |
6306 | #ifdef SAVED_FP | |
6307 | fprintf_unfiltered (file, | |
6308 | "mips_dump_tdep: SAVED_FP = %d\n", | |
6309 | SAVED_FP); | |
6310 | #endif | |
6311 | #ifdef SAVED_PC | |
6312 | fprintf_unfiltered (file, | |
6313 | "mips_dump_tdep: SAVED_PC = %d\n", | |
6314 | SAVED_PC); | |
6315 | #endif | |
6316 | fprintf_unfiltered (file, | |
6317 | "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n", | |
6318 | XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS))); | |
6319 | fprintf_unfiltered (file, | |
6320 | "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n"); | |
6321 | fprintf_unfiltered (file, | |
6322 | "mips_dump_tdep: SIGFRAME_BASE = %d\n", | |
6323 | SIGFRAME_BASE); | |
6324 | fprintf_unfiltered (file, | |
6325 | "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n", | |
6326 | SIGFRAME_FPREGSAVE_OFF); | |
6327 | fprintf_unfiltered (file, | |
6328 | "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n", | |
6329 | SIGFRAME_PC_OFF); | |
6330 | fprintf_unfiltered (file, | |
6331 | "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n", | |
6332 | SIGFRAME_REGSAVE_OFF); | |
6333 | fprintf_unfiltered (file, | |
6334 | "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n", | |
6335 | SIGFRAME_REG_SIZE); | |
6336 | fprintf_unfiltered (file, | |
6337 | "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n", | |
6338 | XSTRING (SKIP_TRAMPOLINE_CODE (PC))); | |
6339 | fprintf_unfiltered (file, | |
6340 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n", | |
6341 | XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P))); | |
6342 | fprintf_unfiltered (file, | |
b0ed3589 AC |
6343 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n", |
6344 | SOFTWARE_SINGLE_STEP_P ()); | |
2475bac3 AC |
6345 | fprintf_unfiltered (file, |
6346 | "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n", | |
6347 | XSTRING (STAB_REG_TO_REGNUM (REGNUM))); | |
6348 | #ifdef STACK_END_ADDR | |
6349 | fprintf_unfiltered (file, | |
6350 | "mips_dump_tdep: STACK_END_ADDR = %d\n", | |
6351 | STACK_END_ADDR); | |
6352 | #endif | |
6353 | fprintf_unfiltered (file, | |
6354 | "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n", | |
6355 | XSTRING (STEP_SKIPS_DELAY (PC))); | |
6356 | fprintf_unfiltered (file, | |
6357 | "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n", | |
6358 | STEP_SKIPS_DELAY_P); | |
6359 | fprintf_unfiltered (file, | |
6360 | "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n", | |
6361 | XSTRING (STOPPED_BY_WATCHPOINT (WS))); | |
6362 | fprintf_unfiltered (file, | |
6363 | "mips_dump_tdep: T9_REGNUM = %d\n", | |
6364 | T9_REGNUM); | |
6365 | fprintf_unfiltered (file, | |
6366 | "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n"); | |
6367 | fprintf_unfiltered (file, | |
6368 | "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n", | |
6369 | XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE,CNT,OTHERTYPE))); | |
6370 | fprintf_unfiltered (file, | |
6371 | "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n", | |
6372 | XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS)); | |
6373 | fprintf_unfiltered (file, | |
6374 | "mips_dump_tdep: TARGET_MIPS = used?\n"); | |
6375 | fprintf_unfiltered (file, | |
6376 | "mips_dump_tdep: TM_PRINT_INSN_MACH # %s\n", | |
6377 | XSTRING (TM_PRINT_INSN_MACH)); | |
6378 | #ifdef TRACE_CLEAR | |
6379 | fprintf_unfiltered (file, | |
6380 | "mips_dump_tdep: TRACE_CLEAR # %s\n", | |
6381 | XSTRING (TRACE_CLEAR (THREAD, STATE))); | |
6382 | #endif | |
6383 | #ifdef TRACE_FLAVOR | |
6384 | fprintf_unfiltered (file, | |
6385 | "mips_dump_tdep: TRACE_FLAVOR = %d\n", | |
6386 | TRACE_FLAVOR); | |
6387 | #endif | |
6388 | #ifdef TRACE_FLAVOR_SIZE | |
6389 | fprintf_unfiltered (file, | |
6390 | "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n", | |
6391 | TRACE_FLAVOR_SIZE); | |
6392 | #endif | |
6393 | #ifdef TRACE_SET | |
6394 | fprintf_unfiltered (file, | |
6395 | "mips_dump_tdep: TRACE_SET # %s\n", | |
6396 | XSTRING (TRACE_SET (X,STATE))); | |
6397 | #endif | |
6398 | fprintf_unfiltered (file, | |
6399 | "mips_dump_tdep: UNMAKE_MIPS16_ADDR = function?\n"); | |
6400 | #ifdef UNUSED_REGNUM | |
6401 | fprintf_unfiltered (file, | |
6402 | "mips_dump_tdep: UNUSED_REGNUM = %d\n", | |
6403 | UNUSED_REGNUM); | |
6404 | #endif | |
6405 | fprintf_unfiltered (file, | |
6406 | "mips_dump_tdep: V0_REGNUM = %d\n", | |
6407 | V0_REGNUM); | |
6408 | fprintf_unfiltered (file, | |
6409 | "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n", | |
6410 | (long) VM_MIN_ADDRESS); | |
6411 | #ifdef VX_NUM_REGS | |
6412 | fprintf_unfiltered (file, | |
6413 | "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n", | |
6414 | VX_NUM_REGS); | |
6415 | #endif | |
6416 | fprintf_unfiltered (file, | |
6417 | "mips_dump_tdep: ZERO_REGNUM = %d\n", | |
6418 | ZERO_REGNUM); | |
6419 | fprintf_unfiltered (file, | |
6420 | "mips_dump_tdep: _PROC_MAGIC_ = %d\n", | |
6421 | _PROC_MAGIC_); | |
70f80edf JT |
6422 | |
6423 | fprintf_unfiltered (file, | |
6424 | "mips_dump_tdep: OS ABI = %s\n", | |
6425 | gdbarch_osabi_name (tdep->osabi)); | |
c2d11a7d JM |
6426 | } |
6427 | ||
c906108c | 6428 | void |
acdb74a0 | 6429 | _initialize_mips_tdep (void) |
c906108c SS |
6430 | { |
6431 | static struct cmd_list_element *mipsfpulist = NULL; | |
6432 | struct cmd_list_element *c; | |
6433 | ||
2e4ebe70 DJ |
6434 | mips_abi_string = mips_abi_strings [MIPS_ABI_UNKNOWN]; |
6435 | if (MIPS_ABI_LAST + 1 | |
6436 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
6437 | internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync"); | |
6438 | ||
4b9b3959 | 6439 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c5aa993b | 6440 | if (!tm_print_insn) /* Someone may have already set it */ |
c906108c SS |
6441 | tm_print_insn = gdb_print_insn_mips; |
6442 | ||
a5ea2558 AC |
6443 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
6444 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
6445 | "Various MIPS specific commands.", | |
6446 | &setmipscmdlist, "set mips ", 0, &setlist); | |
6447 | ||
6448 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
6449 | "Various MIPS specific commands.", | |
6450 | &showmipscmdlist, "show mips ", 0, &showlist); | |
6451 | ||
6452 | /* Allow the user to override the saved register size. */ | |
6453 | add_show_from_set (add_set_enum_cmd ("saved-gpreg-size", | |
1ed2a135 AC |
6454 | class_obscure, |
6455 | size_enums, | |
6456 | &mips_saved_regsize_string, "\ | |
a5ea2558 AC |
6457 | Set size of general purpose registers saved on the stack.\n\ |
6458 | This option can be set to one of:\n\ | |
6459 | 32 - Force GDB to treat saved GP registers as 32-bit\n\ | |
6460 | 64 - Force GDB to treat saved GP registers as 64-bit\n\ | |
6461 | auto - Allow GDB to use the target's default setting or autodetect the\n\ | |
6462 | saved GP register size from information contained in the executable.\n\ | |
6463 | (default: auto)", | |
1ed2a135 | 6464 | &setmipscmdlist), |
a5ea2558 AC |
6465 | &showmipscmdlist); |
6466 | ||
d929b26f AC |
6467 | /* Allow the user to override the argument stack size. */ |
6468 | add_show_from_set (add_set_enum_cmd ("stack-arg-size", | |
6469 | class_obscure, | |
6470 | size_enums, | |
1ed2a135 | 6471 | &mips_stack_argsize_string, "\ |
d929b26f AC |
6472 | Set the amount of stack space reserved for each argument.\n\ |
6473 | This option can be set to one of:\n\ | |
6474 | 32 - Force GDB to allocate 32-bit chunks per argument\n\ | |
6475 | 64 - Force GDB to allocate 64-bit chunks per argument\n\ | |
6476 | auto - Allow GDB to determine the correct setting from the current\n\ | |
6477 | target and executable (default)", | |
6478 | &setmipscmdlist), | |
6479 | &showmipscmdlist); | |
6480 | ||
2e4ebe70 DJ |
6481 | /* Allow the user to override the ABI. */ |
6482 | c = add_set_enum_cmd | |
6483 | ("abi", class_obscure, mips_abi_strings, &mips_abi_string, | |
6484 | "Set the ABI used by this program.\n" | |
6485 | "This option can be set to one of:\n" | |
6486 | " auto - the default ABI associated with the current binary\n" | |
6487 | " o32\n" | |
6488 | " o64\n" | |
6489 | " n32\n" | |
f3a7b3a5 | 6490 | " n64\n" |
2e4ebe70 DJ |
6491 | " eabi32\n" |
6492 | " eabi64", | |
6493 | &setmipscmdlist); | |
6494 | add_show_from_set (c, &showmipscmdlist); | |
6495 | set_cmd_sfunc (c, mips_abi_update); | |
6496 | ||
c906108c SS |
6497 | /* Let the user turn off floating point and set the fence post for |
6498 | heuristic_proc_start. */ | |
6499 | ||
6500 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
6501 | "Set use of MIPS floating-point coprocessor.", | |
6502 | &mipsfpulist, "set mipsfpu ", 0, &setlist); | |
6503 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
6504 | "Select single-precision MIPS floating-point coprocessor.", | |
6505 | &mipsfpulist); | |
6506 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
8e1a459b | 6507 | "Select double-precision MIPS floating-point coprocessor.", |
c906108c SS |
6508 | &mipsfpulist); |
6509 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
6510 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
6511 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
6512 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
6513 | "Select no MIPS floating-point coprocessor.", | |
6514 | &mipsfpulist); | |
6515 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); | |
6516 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
6517 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
6518 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
6519 | "Select MIPS floating-point coprocessor automatically.", | |
6520 | &mipsfpulist); | |
6521 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
6522 | "Show current use of MIPS floating-point coprocessor target.", | |
6523 | &showlist); | |
6524 | ||
c906108c SS |
6525 | /* We really would like to have both "0" and "unlimited" work, but |
6526 | command.c doesn't deal with that. So make it a var_zinteger | |
6527 | because the user can always use "999999" or some such for unlimited. */ | |
6528 | c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger, | |
6529 | (char *) &heuristic_fence_post, | |
6530 | "\ | |
6531 | Set the distance searched for the start of a function.\n\ | |
6532 | If you are debugging a stripped executable, GDB needs to search through the\n\ | |
6533 | program for the start of a function. This command sets the distance of the\n\ | |
6534 | search. The only need to set it is when debugging a stripped executable.", | |
6535 | &setlist); | |
6536 | /* We need to throw away the frame cache when we set this, since it | |
6537 | might change our ability to get backtraces. */ | |
9f60d481 | 6538 | set_cmd_sfunc (c, reinit_frame_cache_sfunc); |
c906108c SS |
6539 | add_show_from_set (c, &showlist); |
6540 | ||
6541 | /* Allow the user to control whether the upper bits of 64-bit | |
6542 | addresses should be zeroed. */ | |
e9e68a56 AC |
6543 | add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, "\ |
6544 | Set zeroing of upper 32 bits of 64-bit addresses.\n\ | |
6545 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ | |
6546 | allow GDB to determine the correct value.\n", "\ | |
6547 | Show zeroing of upper 32 bits of 64-bit addresses.", | |
6548 | NULL, show_mask_address, | |
6549 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
6550 | |
6551 | /* Allow the user to control the size of 32 bit registers within the | |
6552 | raw remote packet. */ | |
6553 | add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs", | |
6554 | class_obscure, | |
6555 | var_boolean, | |
6556 | (char *)&mips64_transfers_32bit_regs_p, "\ | |
6557 | Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\ | |
6558 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ | |
6559 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
6560 | 64 bits for others. Use \"off\" to disable compatibility mode", | |
6561 | &setlist), | |
6562 | &showlist); | |
9ace0497 AC |
6563 | |
6564 | /* Debug this files internals. */ | |
6565 | add_show_from_set (add_set_cmd ("mips", class_maintenance, var_zinteger, | |
6566 | &mips_debug, "Set mips debugging.\n\ | |
6567 | When non-zero, mips specific debugging is enabled.", &setdebuglist), | |
6568 | &showdebuglist); | |
c906108c | 6569 | } |