Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
e2882c85 | 3 | Copyright (C) 1988-2018 Free Software Foundation, Inc. |
bf64bfd6 | 4 | |
c906108c SS |
5 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
6 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
7 | ||
c5aa993b | 8 | This file is part of GDB. |
c906108c | 9 | |
c5aa993b JM |
10 | This program is free software; you can redistribute it and/or modify |
11 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 12 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 13 | (at your option) any later version. |
c906108c | 14 | |
c5aa993b JM |
15 | This program is distributed in the hope that it will be useful, |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
c906108c | 19 | |
c5aa993b | 20 | You should have received a copy of the GNU General Public License |
a9762ec7 | 21 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
22 | |
23 | #include "defs.h" | |
c906108c SS |
24 | #include "frame.h" |
25 | #include "inferior.h" | |
26 | #include "symtab.h" | |
27 | #include "value.h" | |
28 | #include "gdbcmd.h" | |
29 | #include "language.h" | |
30 | #include "gdbcore.h" | |
31 | #include "symfile.h" | |
32 | #include "objfiles.h" | |
33 | #include "gdbtypes.h" | |
34 | #include "target.h" | |
28d069e6 | 35 | #include "arch-utils.h" |
4e052eda | 36 | #include "regcache.h" |
70f80edf | 37 | #include "osabi.h" |
d1973055 | 38 | #include "mips-tdep.h" |
fe898f56 | 39 | #include "block.h" |
a4b8ebc8 | 40 | #include "reggroups.h" |
c906108c | 41 | #include "opcode/mips.h" |
c2d11a7d JM |
42 | #include "elf/mips.h" |
43 | #include "elf-bfd.h" | |
2475bac3 | 44 | #include "symcat.h" |
a4b8ebc8 | 45 | #include "sim-regno.h" |
a89aa300 | 46 | #include "dis-asm.h" |
e47ad6c0 | 47 | #include "disasm.h" |
edfae063 AC |
48 | #include "frame-unwind.h" |
49 | #include "frame-base.h" | |
50 | #include "trad-frame.h" | |
7d9b040b | 51 | #include "infcall.h" |
29709017 DJ |
52 | #include "remote.h" |
53 | #include "target-descriptions.h" | |
2bd0c3d7 | 54 | #include "dwarf2-frame.h" |
f8b73d13 | 55 | #include "user-regs.h" |
79a45b7d | 56 | #include "valprint.h" |
175ff332 | 57 | #include "ax.h" |
f69fdf9b | 58 | #include "target-float.h" |
325fac50 | 59 | #include <algorithm> |
c906108c | 60 | |
8d5f9dcb DJ |
61 | static const struct objfile_data *mips_pdr_data; |
62 | ||
5bbcb741 | 63 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 64 | |
ab50adb6 MR |
65 | static int mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, |
66 | ULONGEST inst); | |
67 | static int micromips_instruction_has_delay_slot (ULONGEST insn, int mustbe32); | |
68 | static int mips16_instruction_has_delay_slot (unsigned short inst, | |
69 | int mustbe32); | |
70 | ||
71 | static int mips32_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, | |
72 | CORE_ADDR addr); | |
73 | static int micromips_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, | |
74 | CORE_ADDR addr, int mustbe32); | |
75 | static int mips16_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, | |
76 | CORE_ADDR addr, int mustbe32); | |
4cc0665f | 77 | |
1bab7383 YQ |
78 | static void mips_print_float_info (struct gdbarch *, struct ui_file *, |
79 | struct frame_info *, const char *); | |
80 | ||
24e05951 | 81 | /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ |
dd824b04 DJ |
82 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ |
83 | #define ST0_FR (1 << 26) | |
84 | ||
b0069a17 AC |
85 | /* The sizes of floating point registers. */ |
86 | ||
87 | enum | |
88 | { | |
89 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
90 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
91 | }; | |
92 | ||
1a69e1e4 DJ |
93 | enum |
94 | { | |
95 | MIPS32_REGSIZE = 4, | |
96 | MIPS64_REGSIZE = 8 | |
97 | }; | |
0dadbba0 | 98 | |
2e4ebe70 DJ |
99 | static const char *mips_abi_string; |
100 | ||
40478521 | 101 | static const char *const mips_abi_strings[] = { |
2e4ebe70 DJ |
102 | "auto", |
103 | "n32", | |
104 | "o32", | |
28d169de | 105 | "n64", |
2e4ebe70 DJ |
106 | "o64", |
107 | "eabi32", | |
108 | "eabi64", | |
109 | NULL | |
110 | }; | |
111 | ||
44f1c4d7 YQ |
112 | /* Enum describing the different kinds of breakpoints. */ |
113 | ||
114 | enum mips_breakpoint_kind | |
115 | { | |
116 | /* 16-bit MIPS16 mode breakpoint. */ | |
117 | MIPS_BP_KIND_MIPS16 = 2, | |
118 | ||
119 | /* 16-bit microMIPS mode breakpoint. */ | |
120 | MIPS_BP_KIND_MICROMIPS16 = 3, | |
121 | ||
122 | /* 32-bit standard MIPS mode breakpoint. */ | |
123 | MIPS_BP_KIND_MIPS32 = 4, | |
124 | ||
125 | /* 32-bit microMIPS mode breakpoint. */ | |
126 | MIPS_BP_KIND_MICROMIPS32 = 5, | |
127 | }; | |
128 | ||
4cc0665f MR |
129 | /* For backwards compatibility we default to MIPS16. This flag is |
130 | overridden as soon as unambiguous ELF file flags tell us the | |
131 | compressed ISA encoding used. */ | |
132 | static const char mips_compression_mips16[] = "mips16"; | |
133 | static const char mips_compression_micromips[] = "micromips"; | |
134 | static const char *const mips_compression_strings[] = | |
135 | { | |
136 | mips_compression_mips16, | |
137 | mips_compression_micromips, | |
138 | NULL | |
139 | }; | |
140 | ||
141 | static const char *mips_compression_string = mips_compression_mips16; | |
142 | ||
f8b73d13 DJ |
143 | /* The standard register names, and all the valid aliases for them. */ |
144 | struct register_alias | |
145 | { | |
146 | const char *name; | |
147 | int regnum; | |
148 | }; | |
149 | ||
150 | /* Aliases for o32 and most other ABIs. */ | |
151 | const struct register_alias mips_o32_aliases[] = { | |
152 | { "ta0", 12 }, | |
153 | { "ta1", 13 }, | |
154 | { "ta2", 14 }, | |
155 | { "ta3", 15 } | |
156 | }; | |
157 | ||
158 | /* Aliases for n32 and n64. */ | |
159 | const struct register_alias mips_n32_n64_aliases[] = { | |
160 | { "ta0", 8 }, | |
161 | { "ta1", 9 }, | |
162 | { "ta2", 10 }, | |
163 | { "ta3", 11 } | |
164 | }; | |
165 | ||
166 | /* Aliases for ABI-independent registers. */ | |
167 | const struct register_alias mips_register_aliases[] = { | |
168 | /* The architecture manuals specify these ABI-independent names for | |
169 | the GPRs. */ | |
170 | #define R(n) { "r" #n, n } | |
171 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
172 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
173 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
174 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
175 | #undef R | |
176 | ||
177 | /* k0 and k1 are sometimes called these instead (for "kernel | |
178 | temp"). */ | |
179 | { "kt0", 26 }, | |
180 | { "kt1", 27 }, | |
181 | ||
182 | /* This is the traditional GDB name for the CP0 status register. */ | |
183 | { "sr", MIPS_PS_REGNUM }, | |
184 | ||
185 | /* This is the traditional GDB name for the CP0 BadVAddr register. */ | |
186 | { "bad", MIPS_EMBED_BADVADDR_REGNUM }, | |
187 | ||
188 | /* This is the traditional GDB name for the FCSR. */ | |
189 | { "fsr", MIPS_EMBED_FP0_REGNUM + 32 } | |
190 | }; | |
191 | ||
865093a3 AR |
192 | const struct register_alias mips_numeric_register_aliases[] = { |
193 | #define R(n) { #n, n } | |
194 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
195 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
196 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
197 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
198 | #undef R | |
199 | }; | |
200 | ||
c906108c SS |
201 | #ifndef MIPS_DEFAULT_FPU_TYPE |
202 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
203 | #endif | |
204 | static int mips_fpu_type_auto = 1; | |
205 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 206 | |
ccce17b0 | 207 | static unsigned int mips_debug = 0; |
7a292a7a | 208 | |
29709017 DJ |
209 | /* Properties (for struct target_desc) describing the g/G packet |
210 | layout. */ | |
211 | #define PROPERTY_GP32 "internal: transfers-32bit-registers" | |
212 | #define PROPERTY_GP64 "internal: transfers-64bit-registers" | |
213 | ||
4eb0ad19 DJ |
214 | struct target_desc *mips_tdesc_gp32; |
215 | struct target_desc *mips_tdesc_gp64; | |
216 | ||
471b9d15 MR |
217 | /* The current set of options to be passed to the disassembler. */ |
218 | static char *mips_disassembler_options; | |
219 | ||
220 | /* Implicit disassembler options for individual ABIs. These tell | |
221 | libopcodes to use general-purpose register names corresponding | |
222 | to the ABI we have selected, perhaps via a `set mips abi ...' | |
223 | override, rather than ones inferred from the ABI set in the ELF | |
224 | headers of the binary file selected for debugging. */ | |
225 | static const char mips_disassembler_options_o32[] = "gpr-names=32"; | |
226 | static const char mips_disassembler_options_n32[] = "gpr-names=n32"; | |
227 | static const char mips_disassembler_options_n64[] = "gpr-names=64"; | |
228 | ||
56cea623 AC |
229 | const struct mips_regnum * |
230 | mips_regnum (struct gdbarch *gdbarch) | |
231 | { | |
232 | return gdbarch_tdep (gdbarch)->regnum; | |
233 | } | |
234 | ||
235 | static int | |
236 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
237 | { | |
238 | return mips_regnum (gdbarch)->fp0 + 12; | |
239 | } | |
240 | ||
004159a2 MR |
241 | /* Return 1 if REGNUM refers to a floating-point general register, raw |
242 | or cooked. Otherwise return 0. */ | |
243 | ||
244 | static int | |
245 | mips_float_register_p (struct gdbarch *gdbarch, int regnum) | |
246 | { | |
247 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
248 | ||
249 | return (rawnum >= mips_regnum (gdbarch)->fp0 | |
250 | && rawnum < mips_regnum (gdbarch)->fp0 + 32); | |
251 | } | |
252 | ||
74ed0bb4 MD |
253 | #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \ |
254 | == MIPS_ABI_EABI32 \ | |
255 | || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64) | |
c2d11a7d | 256 | |
025bb325 MS |
257 | #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \ |
258 | (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum) | |
c2d11a7d | 259 | |
025bb325 MS |
260 | #define MIPS_LAST_ARG_REGNUM(gdbarch) \ |
261 | (gdbarch_tdep (gdbarch)->mips_last_arg_regnum) | |
c2d11a7d | 262 | |
74ed0bb4 | 263 | #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type) |
c2d11a7d | 264 | |
d1973055 KB |
265 | /* Return the MIPS ABI associated with GDBARCH. */ |
266 | enum mips_abi | |
267 | mips_abi (struct gdbarch *gdbarch) | |
268 | { | |
269 | return gdbarch_tdep (gdbarch)->mips_abi; | |
270 | } | |
271 | ||
4246e332 | 272 | int |
1b13c4f6 | 273 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 | 274 | { |
29709017 DJ |
275 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
276 | ||
277 | /* If we know how big the registers are, use that size. */ | |
278 | if (tdep->register_size_valid_p) | |
279 | return tdep->register_size; | |
280 | ||
281 | /* Fall back to the previous behavior. */ | |
4246e332 AC |
282 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word |
283 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
284 | } | |
285 | ||
b3464d03 PA |
286 | /* Max saved register size. */ |
287 | #define MAX_MIPS_ABI_REGSIZE 8 | |
288 | ||
025bb325 | 289 | /* Return the currently configured (or set) saved register size. */ |
480d3dd2 | 290 | |
e6bc2e8a | 291 | unsigned int |
13326b4e | 292 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 293 | { |
1a69e1e4 DJ |
294 | switch (mips_abi (gdbarch)) |
295 | { | |
296 | case MIPS_ABI_EABI32: | |
297 | case MIPS_ABI_O32: | |
298 | return 4; | |
299 | case MIPS_ABI_N32: | |
300 | case MIPS_ABI_N64: | |
301 | case MIPS_ABI_O64: | |
302 | case MIPS_ABI_EABI64: | |
303 | return 8; | |
304 | case MIPS_ABI_UNKNOWN: | |
305 | case MIPS_ABI_LAST: | |
306 | default: | |
307 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
308 | } | |
d929b26f AC |
309 | } |
310 | ||
4cc0665f MR |
311 | /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here |
312 | are some functions to handle addresses associated with compressed | |
313 | code including but not limited to testing, setting, or clearing | |
314 | bit 0 of such addresses. */ | |
742c84f6 | 315 | |
4cc0665f MR |
316 | /* Return one iff compressed code is the MIPS16 instruction set. */ |
317 | ||
318 | static int | |
319 | is_mips16_isa (struct gdbarch *gdbarch) | |
320 | { | |
321 | return gdbarch_tdep (gdbarch)->mips_isa == ISA_MIPS16; | |
322 | } | |
323 | ||
324 | /* Return one iff compressed code is the microMIPS instruction set. */ | |
325 | ||
326 | static int | |
327 | is_micromips_isa (struct gdbarch *gdbarch) | |
328 | { | |
329 | return gdbarch_tdep (gdbarch)->mips_isa == ISA_MICROMIPS; | |
330 | } | |
331 | ||
332 | /* Return one iff ADDR denotes compressed code. */ | |
333 | ||
334 | static int | |
335 | is_compact_addr (CORE_ADDR addr) | |
742c84f6 MR |
336 | { |
337 | return ((addr) & 1); | |
338 | } | |
339 | ||
4cc0665f MR |
340 | /* Return one iff ADDR denotes standard ISA code. */ |
341 | ||
342 | static int | |
343 | is_mips_addr (CORE_ADDR addr) | |
344 | { | |
345 | return !is_compact_addr (addr); | |
346 | } | |
347 | ||
348 | /* Return one iff ADDR denotes MIPS16 code. */ | |
349 | ||
350 | static int | |
351 | is_mips16_addr (struct gdbarch *gdbarch, CORE_ADDR addr) | |
352 | { | |
353 | return is_compact_addr (addr) && is_mips16_isa (gdbarch); | |
354 | } | |
355 | ||
356 | /* Return one iff ADDR denotes microMIPS code. */ | |
357 | ||
358 | static int | |
359 | is_micromips_addr (struct gdbarch *gdbarch, CORE_ADDR addr) | |
360 | { | |
361 | return is_compact_addr (addr) && is_micromips_isa (gdbarch); | |
362 | } | |
363 | ||
364 | /* Strip the ISA (compression) bit off from ADDR. */ | |
365 | ||
742c84f6 | 366 | static CORE_ADDR |
4cc0665f | 367 | unmake_compact_addr (CORE_ADDR addr) |
742c84f6 MR |
368 | { |
369 | return ((addr) & ~(CORE_ADDR) 1); | |
370 | } | |
371 | ||
4cc0665f MR |
372 | /* Add the ISA (compression) bit to ADDR. */ |
373 | ||
742c84f6 | 374 | static CORE_ADDR |
4cc0665f | 375 | make_compact_addr (CORE_ADDR addr) |
742c84f6 MR |
376 | { |
377 | return ((addr) | (CORE_ADDR) 1); | |
378 | } | |
379 | ||
3e29f34a MR |
380 | /* Extern version of unmake_compact_addr; we use a separate function |
381 | so that unmake_compact_addr can be inlined throughout this file. */ | |
382 | ||
383 | CORE_ADDR | |
384 | mips_unmake_compact_addr (CORE_ADDR addr) | |
385 | { | |
386 | return unmake_compact_addr (addr); | |
387 | } | |
388 | ||
71b8ef93 | 389 | /* Functions for setting and testing a bit in a minimal symbol that |
4cc0665f MR |
390 | marks it as MIPS16 or microMIPS function. The MSB of the minimal |
391 | symbol's "info" field is used for this purpose. | |
5a89d8aa | 392 | |
4cc0665f MR |
393 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is |
394 | "special", i.e. refers to a MIPS16 or microMIPS function, and sets | |
395 | one of the "special" bits in a minimal symbol to mark it accordingly. | |
396 | The test checks an ELF-private flag that is valid for true function | |
1bbce132 MR |
397 | symbols only; for synthetic symbols such as for PLT stubs that have |
398 | no ELF-private part at all the MIPS BFD backend arranges for this | |
399 | information to be carried in the asymbol's udata field instead. | |
5a89d8aa | 400 | |
4cc0665f MR |
401 | msymbol_is_mips16 and msymbol_is_micromips test the "special" bit |
402 | in a minimal symbol. */ | |
5a89d8aa | 403 | |
5a89d8aa | 404 | static void |
6d82d43b AC |
405 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
406 | { | |
4cc0665f | 407 | elf_symbol_type *elfsym = (elf_symbol_type *) sym; |
1bbce132 | 408 | unsigned char st_other; |
4cc0665f | 409 | |
1bbce132 MR |
410 | if ((sym->flags & BSF_SYNTHETIC) == 0) |
411 | st_other = elfsym->internal_elf_sym.st_other; | |
412 | else if ((sym->flags & BSF_FUNCTION) != 0) | |
413 | st_other = sym->udata.i; | |
414 | else | |
4cc0665f MR |
415 | return; |
416 | ||
1bbce132 | 417 | if (ELF_ST_IS_MICROMIPS (st_other)) |
3e29f34a | 418 | { |
f161c171 | 419 | MSYMBOL_TARGET_FLAG_MICROMIPS (msym) = 1; |
3e29f34a MR |
420 | SET_MSYMBOL_VALUE_ADDRESS (msym, MSYMBOL_VALUE_RAW_ADDRESS (msym) | 1); |
421 | } | |
1bbce132 | 422 | else if (ELF_ST_IS_MIPS16 (st_other)) |
3e29f34a | 423 | { |
f161c171 | 424 | MSYMBOL_TARGET_FLAG_MIPS16 (msym) = 1; |
3e29f34a MR |
425 | SET_MSYMBOL_VALUE_ADDRESS (msym, MSYMBOL_VALUE_RAW_ADDRESS (msym) | 1); |
426 | } | |
4cc0665f MR |
427 | } |
428 | ||
429 | /* Return one iff MSYM refers to standard ISA code. */ | |
430 | ||
431 | static int | |
432 | msymbol_is_mips (struct minimal_symbol *msym) | |
433 | { | |
f161c171 MR |
434 | return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym) |
435 | | MSYMBOL_TARGET_FLAG_MICROMIPS (msym)); | |
5a89d8aa MS |
436 | } |
437 | ||
4cc0665f MR |
438 | /* Return one iff MSYM refers to MIPS16 code. */ |
439 | ||
71b8ef93 | 440 | static int |
4cc0665f | 441 | msymbol_is_mips16 (struct minimal_symbol *msym) |
71b8ef93 | 442 | { |
f161c171 | 443 | return MSYMBOL_TARGET_FLAG_MIPS16 (msym); |
71b8ef93 MS |
444 | } |
445 | ||
4cc0665f MR |
446 | /* Return one iff MSYM refers to microMIPS code. */ |
447 | ||
448 | static int | |
449 | msymbol_is_micromips (struct minimal_symbol *msym) | |
450 | { | |
f161c171 | 451 | return MSYMBOL_TARGET_FLAG_MICROMIPS (msym); |
4cc0665f MR |
452 | } |
453 | ||
3e29f34a MR |
454 | /* Set the ISA bit in the main symbol too, complementing the corresponding |
455 | minimal symbol setting and reflecting the run-time value of the symbol. | |
456 | The need for comes from the ISA bit having been cleared as code in | |
457 | `_bfd_mips_elf_symbol_processing' separated it into the ELF symbol's | |
458 | `st_other' STO_MIPS16 or STO_MICROMIPS annotation, making the values | |
459 | of symbols referring to compressed code different in GDB to the values | |
460 | used by actual code. That in turn makes them evaluate incorrectly in | |
461 | expressions, producing results different to what the same expressions | |
462 | yield when compiled into the program being debugged. */ | |
463 | ||
464 | static void | |
465 | mips_make_symbol_special (struct symbol *sym, struct objfile *objfile) | |
466 | { | |
467 | if (SYMBOL_CLASS (sym) == LOC_BLOCK) | |
468 | { | |
469 | /* We are in symbol reading so it is OK to cast away constness. */ | |
470 | struct block *block = (struct block *) SYMBOL_BLOCK_VALUE (sym); | |
471 | CORE_ADDR compact_block_start; | |
472 | struct bound_minimal_symbol msym; | |
473 | ||
474 | compact_block_start = BLOCK_START (block) | 1; | |
475 | msym = lookup_minimal_symbol_by_pc (compact_block_start); | |
476 | if (msym.minsym && !msymbol_is_mips (msym.minsym)) | |
477 | { | |
478 | BLOCK_START (block) = compact_block_start; | |
479 | } | |
480 | } | |
481 | } | |
482 | ||
88658117 AC |
483 | /* XFER a value from the big/little/left end of the register. |
484 | Depending on the size of the value it might occupy the entire | |
485 | register or just part of it. Make an allowance for this, aligning | |
486 | things accordingly. */ | |
487 | ||
488 | static void | |
ba32f989 DJ |
489 | mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache, |
490 | int reg_num, int length, | |
870cd05e MK |
491 | enum bfd_endian endian, gdb_byte *in, |
492 | const gdb_byte *out, int buf_offset) | |
88658117 | 493 | { |
88658117 | 494 | int reg_offset = 0; |
72a155b4 UW |
495 | |
496 | gdb_assert (reg_num >= gdbarch_num_regs (gdbarch)); | |
cb1d2653 AC |
497 | /* Need to transfer the left or right part of the register, based on |
498 | the targets byte order. */ | |
88658117 AC |
499 | switch (endian) |
500 | { | |
501 | case BFD_ENDIAN_BIG: | |
72a155b4 | 502 | reg_offset = register_size (gdbarch, reg_num) - length; |
88658117 AC |
503 | break; |
504 | case BFD_ENDIAN_LITTLE: | |
505 | reg_offset = 0; | |
506 | break; | |
6d82d43b | 507 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
508 | reg_offset = 0; |
509 | break; | |
510 | default: | |
e2e0b3e5 | 511 | internal_error (__FILE__, __LINE__, _("bad switch")); |
88658117 AC |
512 | } |
513 | if (mips_debug) | |
cb1d2653 AC |
514 | fprintf_unfiltered (gdb_stderr, |
515 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
516 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
517 | if (mips_debug && out != NULL) |
518 | { | |
519 | int i; | |
cb1d2653 | 520 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 521 | for (i = 0; i < length; i++) |
cb1d2653 | 522 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
523 | } |
524 | if (in != NULL) | |
73bb0000 | 525 | regcache->cooked_read_part (reg_num, reg_offset, length, in + buf_offset); |
88658117 | 526 | if (out != NULL) |
e4c4a59b | 527 | regcache->cooked_write_part (reg_num, reg_offset, length, out + buf_offset); |
88658117 AC |
528 | if (mips_debug && in != NULL) |
529 | { | |
530 | int i; | |
cb1d2653 | 531 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 532 | for (i = 0; i < length; i++) |
cb1d2653 | 533 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
534 | } |
535 | if (mips_debug) | |
536 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
537 | } | |
538 | ||
dd824b04 DJ |
539 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
540 | compatiblity mode. A return value of 1 means that we have | |
541 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
542 | ||
543 | static int | |
9c9acae0 | 544 | mips2_fp_compat (struct frame_info *frame) |
dd824b04 | 545 | { |
72a155b4 | 546 | struct gdbarch *gdbarch = get_frame_arch (frame); |
dd824b04 DJ |
547 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not |
548 | meaningful. */ | |
72a155b4 | 549 | if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4) |
dd824b04 DJ |
550 | return 0; |
551 | ||
552 | #if 0 | |
553 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
554 | in all the places we deal with FP registers. PR gdb/413. */ | |
555 | /* Otherwise check the FR bit in the status register - it controls | |
556 | the FP compatiblity mode. If it is clear we are in compatibility | |
557 | mode. */ | |
9c9acae0 | 558 | if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0) |
dd824b04 DJ |
559 | return 1; |
560 | #endif | |
361d1df0 | 561 | |
dd824b04 DJ |
562 | return 0; |
563 | } | |
564 | ||
7a292a7a | 565 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 566 | |
74ed0bb4 | 567 | static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR); |
c906108c | 568 | |
025bb325 | 569 | /* The list of available "set mips " and "show mips " commands. */ |
acdb74a0 AC |
570 | |
571 | static struct cmd_list_element *setmipscmdlist = NULL; | |
572 | static struct cmd_list_element *showmipscmdlist = NULL; | |
573 | ||
5e2e9765 KB |
574 | /* Integer registers 0 thru 31 are handled explicitly by |
575 | mips_register_name(). Processor specific registers 32 and above | |
8a9fc081 | 576 | are listed in the following tables. */ |
691c0433 | 577 | |
6d82d43b AC |
578 | enum |
579 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
580 | |
581 | /* Generic MIPS. */ | |
582 | ||
583 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
584 | "sr", "lo", "hi", "bad", "cause", "pc", |
585 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
586 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
587 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
588 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
1faeff08 | 589 | "fsr", "fir", |
691c0433 AC |
590 | }; |
591 | ||
691c0433 AC |
592 | /* Names of tx39 registers. */ |
593 | ||
594 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
595 | "sr", "lo", "hi", "bad", "cause", "pc", |
596 | "", "", "", "", "", "", "", "", | |
597 | "", "", "", "", "", "", "", "", | |
598 | "", "", "", "", "", "", "", "", | |
599 | "", "", "", "", "", "", "", "", | |
600 | "", "", "", "", | |
601 | "", "", "", "", "", "", "", "", | |
1faeff08 | 602 | "", "", "config", "cache", "debug", "depc", "epc", |
691c0433 AC |
603 | }; |
604 | ||
44099a67 | 605 | /* Names of registers with Linux kernels. */ |
1faeff08 MR |
606 | static const char *mips_linux_reg_names[NUM_MIPS_PROCESSOR_REGS] = { |
607 | "sr", "lo", "hi", "bad", "cause", "pc", | |
608 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
609 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
610 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
611 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
612 | "fsr", "fir" | |
613 | }; | |
614 | ||
cce74817 | 615 | |
5e2e9765 | 616 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 617 | static const char * |
d93859e2 | 618 | mips_register_name (struct gdbarch *gdbarch, int regno) |
cce74817 | 619 | { |
d93859e2 | 620 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
5e2e9765 | 621 | /* GPR names for all ABIs other than n32/n64. */ |
a121b7c1 | 622 | static const char *mips_gpr_names[] = { |
6d82d43b AC |
623 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
624 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
625 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
626 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
627 | }; |
628 | ||
629 | /* GPR names for n32 and n64 ABIs. */ | |
a121b7c1 | 630 | static const char *mips_n32_n64_gpr_names[] = { |
6d82d43b AC |
631 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
632 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
633 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
634 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
635 | }; |
636 | ||
d93859e2 | 637 | enum mips_abi abi = mips_abi (gdbarch); |
5e2e9765 | 638 | |
f57d151a | 639 | /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, |
6229fbea HZ |
640 | but then don't make the raw register names visible. This (upper) |
641 | range of user visible register numbers are the pseudo-registers. | |
642 | ||
643 | This approach was adopted accommodate the following scenario: | |
644 | It is possible to debug a 64-bit device using a 32-bit | |
645 | programming model. In such instances, the raw registers are | |
646 | configured to be 64-bits wide, while the pseudo registers are | |
647 | configured to be 32-bits wide. The registers that the user | |
648 | sees - the pseudo registers - match the users expectations | |
649 | given the programming model being used. */ | |
d93859e2 UW |
650 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
651 | if (regno < gdbarch_num_regs (gdbarch)) | |
a4b8ebc8 AC |
652 | return ""; |
653 | ||
5e2e9765 KB |
654 | /* The MIPS integer registers are always mapped from 0 to 31. The |
655 | names of the registers (which reflects the conventions regarding | |
656 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 657 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
658 | { |
659 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 660 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 661 | else |
a4b8ebc8 | 662 | return mips_gpr_names[rawnum]; |
5e2e9765 | 663 | } |
d93859e2 UW |
664 | else if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
665 | return tdesc_register_name (gdbarch, rawnum); | |
666 | else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch)) | |
691c0433 AC |
667 | { |
668 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
1faeff08 MR |
669 | if (tdep->mips_processor_reg_names[rawnum - 32]) |
670 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
671 | return ""; | |
691c0433 | 672 | } |
5e2e9765 KB |
673 | else |
674 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 675 | _("mips_register_name: bad register number %d"), rawnum); |
cce74817 | 676 | } |
5e2e9765 | 677 | |
a4b8ebc8 | 678 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 679 | |
a4b8ebc8 AC |
680 | static int |
681 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
682 | struct reggroup *reggroup) | |
683 | { | |
684 | int vector_p; | |
685 | int float_p; | |
686 | int raw_p; | |
72a155b4 UW |
687 | int rawnum = regnum % gdbarch_num_regs (gdbarch); |
688 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
a4b8ebc8 AC |
689 | if (reggroup == all_reggroup) |
690 | return pseudo; | |
691 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
692 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
693 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
694 | (gdbarch), as not all architectures are multi-arch. */ | |
72a155b4 UW |
695 | raw_p = rawnum < gdbarch_num_regs (gdbarch); |
696 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
697 | || gdbarch_register_name (gdbarch, regnum)[0] == '\0') | |
a4b8ebc8 AC |
698 | return 0; |
699 | if (reggroup == float_reggroup) | |
700 | return float_p && pseudo; | |
701 | if (reggroup == vector_reggroup) | |
702 | return vector_p && pseudo; | |
703 | if (reggroup == general_reggroup) | |
704 | return (!vector_p && !float_p) && pseudo; | |
705 | /* Save the pseudo registers. Need to make certain that any code | |
706 | extracting register values from a saved register cache also uses | |
707 | pseudo registers. */ | |
708 | if (reggroup == save_reggroup) | |
709 | return raw_p && pseudo; | |
710 | /* Restore the same pseudo register. */ | |
711 | if (reggroup == restore_reggroup) | |
712 | return raw_p && pseudo; | |
6d82d43b | 713 | return 0; |
a4b8ebc8 AC |
714 | } |
715 | ||
f8b73d13 DJ |
716 | /* Return the groups that a MIPS register can be categorised into. |
717 | This version is only used if we have a target description which | |
718 | describes real registers (and their groups). */ | |
719 | ||
720 | static int | |
721 | mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
722 | struct reggroup *reggroup) | |
723 | { | |
724 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
725 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
726 | int ret; | |
727 | ||
728 | /* Only save, restore, and display the pseudo registers. Need to | |
729 | make certain that any code extracting register values from a | |
730 | saved register cache also uses pseudo registers. | |
731 | ||
732 | Note: saving and restoring the pseudo registers is slightly | |
733 | strange; if we have 64 bits, we should save and restore all | |
734 | 64 bits. But this is hard and has little benefit. */ | |
735 | if (!pseudo) | |
736 | return 0; | |
737 | ||
738 | ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup); | |
739 | if (ret != -1) | |
740 | return ret; | |
741 | ||
742 | return mips_register_reggroup_p (gdbarch, regnum, reggroup); | |
743 | } | |
744 | ||
a4b8ebc8 | 745 | /* Map the symbol table registers which live in the range [1 * |
f57d151a | 746 | gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw |
47ebcfbe | 747 | registers. Take care of alignment and size problems. */ |
c5aa993b | 748 | |
05d1431c | 749 | static enum register_status |
849d0ba8 | 750 | mips_pseudo_register_read (struct gdbarch *gdbarch, readable_regcache *regcache, |
47a35522 | 751 | int cookednum, gdb_byte *buf) |
a4b8ebc8 | 752 | { |
72a155b4 UW |
753 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
754 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
755 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 756 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
03f50fc8 | 757 | return regcache->raw_read (rawnum, buf); |
6d82d43b AC |
758 | else if (register_size (gdbarch, rawnum) > |
759 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 760 | { |
8bdf35dc | 761 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
03f50fc8 | 762 | return regcache->raw_read_part (rawnum, 0, 4, buf); |
47ebcfbe | 763 | else |
8bdf35dc KB |
764 | { |
765 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
766 | LONGEST regval; | |
05d1431c PA |
767 | enum register_status status; |
768 | ||
03f50fc8 | 769 | status = regcache->raw_read (rawnum, ®val); |
05d1431c PA |
770 | if (status == REG_VALID) |
771 | store_signed_integer (buf, 4, byte_order, regval); | |
772 | return status; | |
8bdf35dc | 773 | } |
47ebcfbe AC |
774 | } |
775 | else | |
e2e0b3e5 | 776 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 AC |
777 | } |
778 | ||
779 | static void | |
6d82d43b AC |
780 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
781 | struct regcache *regcache, int cookednum, | |
47a35522 | 782 | const gdb_byte *buf) |
a4b8ebc8 | 783 | { |
72a155b4 UW |
784 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
785 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
786 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 787 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
10eaee5f | 788 | regcache->raw_write (rawnum, buf); |
6d82d43b AC |
789 | else if (register_size (gdbarch, rawnum) > |
790 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 791 | { |
8bdf35dc | 792 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
4f0420fd | 793 | regcache->raw_write_part (rawnum, 0, 4, buf); |
47ebcfbe | 794 | else |
8bdf35dc KB |
795 | { |
796 | /* Sign extend the shortened version of the register prior | |
797 | to placing it in the raw register. This is required for | |
798 | some mips64 parts in order to avoid unpredictable behavior. */ | |
799 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
800 | LONGEST regval = extract_signed_integer (buf, 4, byte_order); | |
801 | regcache_raw_write_signed (regcache, rawnum, regval); | |
802 | } | |
47ebcfbe AC |
803 | } |
804 | else | |
e2e0b3e5 | 805 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 | 806 | } |
c5aa993b | 807 | |
175ff332 HZ |
808 | static int |
809 | mips_ax_pseudo_register_collect (struct gdbarch *gdbarch, | |
810 | struct agent_expr *ax, int reg) | |
811 | { | |
812 | int rawnum = reg % gdbarch_num_regs (gdbarch); | |
813 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) | |
814 | && reg < 2 * gdbarch_num_regs (gdbarch)); | |
815 | ||
816 | ax_reg_mask (ax, rawnum); | |
817 | ||
818 | return 0; | |
819 | } | |
820 | ||
821 | static int | |
822 | mips_ax_pseudo_register_push_stack (struct gdbarch *gdbarch, | |
823 | struct agent_expr *ax, int reg) | |
824 | { | |
825 | int rawnum = reg % gdbarch_num_regs (gdbarch); | |
826 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) | |
827 | && reg < 2 * gdbarch_num_regs (gdbarch)); | |
828 | if (register_size (gdbarch, rawnum) >= register_size (gdbarch, reg)) | |
829 | { | |
830 | ax_reg (ax, rawnum); | |
831 | ||
832 | if (register_size (gdbarch, rawnum) > register_size (gdbarch, reg)) | |
833 | { | |
834 | if (!gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
835 | || gdbarch_byte_order (gdbarch) != BFD_ENDIAN_BIG) | |
836 | { | |
837 | ax_const_l (ax, 32); | |
838 | ax_simple (ax, aop_lsh); | |
839 | } | |
840 | ax_const_l (ax, 32); | |
841 | ax_simple (ax, aop_rsh_signed); | |
842 | } | |
843 | } | |
844 | else | |
845 | internal_error (__FILE__, __LINE__, _("bad register size")); | |
846 | ||
847 | return 0; | |
848 | } | |
849 | ||
4cc0665f | 850 | /* Table to translate 3-bit register field to actual register number. */ |
d467df4e | 851 | static const signed char mips_reg3_to_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
852 | |
853 | /* Heuristic_proc_start may hunt through the text section for a long | |
854 | time across a 2400 baud serial line. Allows the user to limit this | |
855 | search. */ | |
856 | ||
44096aee | 857 | static int heuristic_fence_post = 0; |
c906108c | 858 | |
46cd78fb | 859 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
860 | register N. NOTE: This defines the pseudo register type so need to |
861 | rebuild the architecture vector. */ | |
43e526b9 JM |
862 | |
863 | static int mips64_transfers_32bit_regs_p = 0; | |
864 | ||
719ec221 | 865 | static void |
eb4c3f4a | 866 | set_mips64_transfers_32bit_regs (const char *args, int from_tty, |
719ec221 | 867 | struct cmd_list_element *c) |
43e526b9 | 868 | { |
719ec221 AC |
869 | struct gdbarch_info info; |
870 | gdbarch_info_init (&info); | |
871 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
872 | instead of relying on globals. Doing that would let generic code | |
873 | handle the search for this specific architecture. */ | |
874 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 875 | { |
719ec221 | 876 | mips64_transfers_32bit_regs_p = 0; |
8a3fe4f8 | 877 | error (_("32-bit compatibility mode not supported")); |
a4b8ebc8 | 878 | } |
a4b8ebc8 AC |
879 | } |
880 | ||
47ebcfbe | 881 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 882 | |
ee51a8c7 KB |
883 | /* This predicate tests for the case of an 8 byte floating point |
884 | value that is being transferred to or from a pair of floating point | |
885 | registers each of which are (or are considered to be) only 4 bytes | |
886 | wide. */ | |
ff2e87ac | 887 | static int |
ee51a8c7 KB |
888 | mips_convert_register_float_case_p (struct gdbarch *gdbarch, int regnum, |
889 | struct type *type) | |
ff2e87ac | 890 | { |
0abe36f5 MD |
891 | return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
892 | && register_size (gdbarch, regnum) == 4 | |
004159a2 | 893 | && mips_float_register_p (gdbarch, regnum) |
6d82d43b | 894 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
895 | } |
896 | ||
ee51a8c7 KB |
897 | /* This predicate tests for the case of a value of less than 8 |
898 | bytes in width that is being transfered to or from an 8 byte | |
899 | general purpose register. */ | |
900 | static int | |
901 | mips_convert_register_gpreg_case_p (struct gdbarch *gdbarch, int regnum, | |
902 | struct type *type) | |
903 | { | |
904 | int num_regs = gdbarch_num_regs (gdbarch); | |
905 | ||
906 | return (register_size (gdbarch, regnum) == 8 | |
907 | && regnum % num_regs > 0 && regnum % num_regs < 32 | |
908 | && TYPE_LENGTH (type) < 8); | |
909 | } | |
910 | ||
911 | static int | |
025bb325 MS |
912 | mips_convert_register_p (struct gdbarch *gdbarch, |
913 | int regnum, struct type *type) | |
ee51a8c7 | 914 | { |
eaa05d59 MR |
915 | return (mips_convert_register_float_case_p (gdbarch, regnum, type) |
916 | || mips_convert_register_gpreg_case_p (gdbarch, regnum, type)); | |
ee51a8c7 KB |
917 | } |
918 | ||
8dccd430 | 919 | static int |
ff2e87ac | 920 | mips_register_to_value (struct frame_info *frame, int regnum, |
8dccd430 PA |
921 | struct type *type, gdb_byte *to, |
922 | int *optimizedp, int *unavailablep) | |
102182a9 | 923 | { |
ee51a8c7 KB |
924 | struct gdbarch *gdbarch = get_frame_arch (frame); |
925 | ||
926 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
927 | { | |
928 | get_frame_register (frame, regnum + 0, to + 4); | |
929 | get_frame_register (frame, regnum + 1, to + 0); | |
8dccd430 PA |
930 | |
931 | if (!get_frame_register_bytes (frame, regnum + 0, 0, 4, to + 4, | |
932 | optimizedp, unavailablep)) | |
933 | return 0; | |
934 | ||
935 | if (!get_frame_register_bytes (frame, regnum + 1, 0, 4, to + 0, | |
936 | optimizedp, unavailablep)) | |
937 | return 0; | |
938 | *optimizedp = *unavailablep = 0; | |
939 | return 1; | |
ee51a8c7 KB |
940 | } |
941 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
942 | { | |
943 | int len = TYPE_LENGTH (type); | |
8dccd430 PA |
944 | CORE_ADDR offset; |
945 | ||
946 | offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 8 - len : 0; | |
947 | if (!get_frame_register_bytes (frame, regnum, offset, len, to, | |
948 | optimizedp, unavailablep)) | |
949 | return 0; | |
950 | ||
951 | *optimizedp = *unavailablep = 0; | |
952 | return 1; | |
ee51a8c7 KB |
953 | } |
954 | else | |
955 | { | |
956 | internal_error (__FILE__, __LINE__, | |
957 | _("mips_register_to_value: unrecognized case")); | |
958 | } | |
102182a9 MS |
959 | } |
960 | ||
42c466d7 | 961 | static void |
ff2e87ac | 962 | mips_value_to_register (struct frame_info *frame, int regnum, |
47a35522 | 963 | struct type *type, const gdb_byte *from) |
102182a9 | 964 | { |
ee51a8c7 KB |
965 | struct gdbarch *gdbarch = get_frame_arch (frame); |
966 | ||
967 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
968 | { | |
969 | put_frame_register (frame, regnum + 0, from + 4); | |
970 | put_frame_register (frame, regnum + 1, from + 0); | |
971 | } | |
972 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
973 | { | |
974 | gdb_byte fill[8]; | |
975 | int len = TYPE_LENGTH (type); | |
976 | ||
977 | /* Sign extend values, irrespective of type, that are stored to | |
978 | a 64-bit general purpose register. (32-bit unsigned values | |
979 | are stored as signed quantities within a 64-bit register. | |
980 | When performing an operation, in compiled code, that combines | |
981 | a 32-bit unsigned value with a signed 64-bit value, a type | |
982 | conversion is first performed that zeroes out the high 32 bits.) */ | |
983 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
984 | { | |
985 | if (from[0] & 0x80) | |
986 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, -1); | |
987 | else | |
988 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, 0); | |
989 | put_frame_register_bytes (frame, regnum, 0, 8 - len, fill); | |
990 | put_frame_register_bytes (frame, regnum, 8 - len, len, from); | |
991 | } | |
992 | else | |
993 | { | |
994 | if (from[len-1] & 0x80) | |
995 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, -1); | |
996 | else | |
997 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, 0); | |
998 | put_frame_register_bytes (frame, regnum, 0, len, from); | |
999 | put_frame_register_bytes (frame, regnum, len, 8 - len, fill); | |
1000 | } | |
1001 | } | |
1002 | else | |
1003 | { | |
1004 | internal_error (__FILE__, __LINE__, | |
1005 | _("mips_value_to_register: unrecognized case")); | |
1006 | } | |
102182a9 MS |
1007 | } |
1008 | ||
a4b8ebc8 AC |
1009 | /* Return the GDB type object for the "standard" data type of data in |
1010 | register REG. */ | |
78fde5f8 KB |
1011 | |
1012 | static struct type * | |
a4b8ebc8 AC |
1013 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
1014 | { | |
72a155b4 | 1015 | gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch)); |
004159a2 | 1016 | if (mips_float_register_p (gdbarch, regnum)) |
a6425924 | 1017 | { |
5ef80fb0 | 1018 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 1019 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
8da61cc4 | 1020 | if (mips_isa_regsize (gdbarch) == 4) |
27067745 | 1021 | return builtin_type (gdbarch)->builtin_float; |
8da61cc4 | 1022 | else |
27067745 | 1023 | return builtin_type (gdbarch)->builtin_double; |
a6425924 | 1024 | } |
72a155b4 | 1025 | else if (regnum < gdbarch_num_regs (gdbarch)) |
d5ac5a39 AC |
1026 | { |
1027 | /* The raw or ISA registers. These are all sized according to | |
1028 | the ISA regsize. */ | |
1029 | if (mips_isa_regsize (gdbarch) == 4) | |
df4df182 | 1030 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 | 1031 | else |
df4df182 | 1032 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 1033 | } |
78fde5f8 | 1034 | else |
d5ac5a39 | 1035 | { |
1faeff08 MR |
1036 | int rawnum = regnum - gdbarch_num_regs (gdbarch); |
1037 | ||
d5ac5a39 AC |
1038 | /* The cooked or ABI registers. These are sized according to |
1039 | the ABI (with a few complications). */ | |
1faeff08 MR |
1040 | if (rawnum == mips_regnum (gdbarch)->fp_control_status |
1041 | || rawnum == mips_regnum (gdbarch)->fp_implementation_revision) | |
1042 | return builtin_type (gdbarch)->builtin_int32; | |
de4bfa86 | 1043 | else if (gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX |
1faeff08 MR |
1044 | && rawnum >= MIPS_FIRST_EMBED_REGNUM |
1045 | && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
d5ac5a39 AC |
1046 | /* The pseudo/cooked view of the embedded registers is always |
1047 | 32-bit. The raw view is handled below. */ | |
df4df182 | 1048 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
1049 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
1050 | /* The target, while possibly using a 64-bit register buffer, | |
1051 | is only transfering 32-bits of each integer register. | |
1052 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
df4df182 | 1053 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
1054 | else if (mips_abi_regsize (gdbarch) == 4) |
1055 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
1056 | 32- or 64-bit). */ | |
df4df182 | 1057 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
1058 | else |
1059 | /* 64-bit ABI. */ | |
df4df182 | 1060 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 1061 | } |
78fde5f8 KB |
1062 | } |
1063 | ||
f8b73d13 DJ |
1064 | /* Return the GDB type for the pseudo register REGNUM, which is the |
1065 | ABI-level view. This function is only called if there is a target | |
1066 | description which includes registers, so we know precisely the | |
1067 | types of hardware registers. */ | |
1068 | ||
1069 | static struct type * | |
1070 | mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
1071 | { | |
1072 | const int num_regs = gdbarch_num_regs (gdbarch); | |
f8b73d13 DJ |
1073 | int rawnum = regnum % num_regs; |
1074 | struct type *rawtype; | |
1075 | ||
1076 | gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); | |
1077 | ||
1078 | /* Absent registers are still absent. */ | |
1079 | rawtype = gdbarch_register_type (gdbarch, rawnum); | |
1080 | if (TYPE_LENGTH (rawtype) == 0) | |
1081 | return rawtype; | |
1082 | ||
a6912260 MR |
1083 | /* Present the floating point registers however the hardware did; |
1084 | do not try to convert between FPU layouts. */ | |
de13fcf2 | 1085 | if (mips_float_register_p (gdbarch, rawnum)) |
f8b73d13 DJ |
1086 | return rawtype; |
1087 | ||
78b86327 MR |
1088 | /* Floating-point control registers are always 32-bit even though for |
1089 | backwards compatibility reasons 64-bit targets will transfer them | |
1090 | as 64-bit quantities even if using XML descriptions. */ | |
1091 | if (rawnum == mips_regnum (gdbarch)->fp_control_status | |
1092 | || rawnum == mips_regnum (gdbarch)->fp_implementation_revision) | |
1093 | return builtin_type (gdbarch)->builtin_int32; | |
1094 | ||
f8b73d13 DJ |
1095 | /* Use pointer types for registers if we can. For n32 we can not, |
1096 | since we do not have a 64-bit pointer type. */ | |
0dfff4cb UW |
1097 | if (mips_abi_regsize (gdbarch) |
1098 | == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr)) | |
f8b73d13 | 1099 | { |
1faeff08 MR |
1100 | if (rawnum == MIPS_SP_REGNUM |
1101 | || rawnum == mips_regnum (gdbarch)->badvaddr) | |
0dfff4cb | 1102 | return builtin_type (gdbarch)->builtin_data_ptr; |
1faeff08 | 1103 | else if (rawnum == mips_regnum (gdbarch)->pc) |
0dfff4cb | 1104 | return builtin_type (gdbarch)->builtin_func_ptr; |
f8b73d13 DJ |
1105 | } |
1106 | ||
1107 | if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8 | |
1faeff08 MR |
1108 | && ((rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_PS_REGNUM) |
1109 | || rawnum == mips_regnum (gdbarch)->lo | |
1110 | || rawnum == mips_regnum (gdbarch)->hi | |
1111 | || rawnum == mips_regnum (gdbarch)->badvaddr | |
1112 | || rawnum == mips_regnum (gdbarch)->cause | |
1113 | || rawnum == mips_regnum (gdbarch)->pc | |
1114 | || (mips_regnum (gdbarch)->dspacc != -1 | |
1115 | && rawnum >= mips_regnum (gdbarch)->dspacc | |
1116 | && rawnum < mips_regnum (gdbarch)->dspacc + 6))) | |
df4df182 | 1117 | return builtin_type (gdbarch)->builtin_int32; |
f8b73d13 | 1118 | |
a6912260 MR |
1119 | /* The pseudo/cooked view of embedded registers is always |
1120 | 32-bit, even if the target transfers 64-bit values for them. | |
1121 | New targets relying on XML descriptions should only transfer | |
1122 | the necessary 32 bits, but older versions of GDB expected 64, | |
1123 | so allow the target to provide 64 bits without interfering | |
1124 | with the displayed type. */ | |
de4bfa86 | 1125 | if (gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX |
78b86327 | 1126 | && rawnum >= MIPS_FIRST_EMBED_REGNUM |
1faeff08 | 1127 | && rawnum <= MIPS_LAST_EMBED_REGNUM) |
a6912260 | 1128 | return builtin_type (gdbarch)->builtin_int32; |
1faeff08 | 1129 | |
f8b73d13 DJ |
1130 | /* For all other registers, pass through the hardware type. */ |
1131 | return rawtype; | |
1132 | } | |
bcb0cc15 | 1133 | |
025bb325 | 1134 | /* Should the upper word of 64-bit addresses be zeroed? */ |
ea33cd92 | 1135 | static enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
1136 | |
1137 | static int | |
480d3dd2 | 1138 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
1139 | { |
1140 | switch (mask_address_var) | |
1141 | { | |
7f19b9a2 | 1142 | case AUTO_BOOLEAN_TRUE: |
4014092b | 1143 | return 1; |
7f19b9a2 | 1144 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
1145 | return 0; |
1146 | break; | |
7f19b9a2 | 1147 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 1148 | return tdep->default_mask_address_p; |
4014092b | 1149 | default: |
025bb325 MS |
1150 | internal_error (__FILE__, __LINE__, |
1151 | _("mips_mask_address_p: bad switch")); | |
4014092b | 1152 | return -1; |
361d1df0 | 1153 | } |
4014092b AC |
1154 | } |
1155 | ||
1156 | static void | |
08546159 AC |
1157 | show_mask_address (struct ui_file *file, int from_tty, |
1158 | struct cmd_list_element *c, const char *value) | |
4014092b | 1159 | { |
f5656ead | 1160 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ()); |
08546159 AC |
1161 | |
1162 | deprecated_show_value_hack (file, from_tty, c, value); | |
4014092b AC |
1163 | switch (mask_address_var) |
1164 | { | |
7f19b9a2 | 1165 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
1166 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
1167 | break; | |
7f19b9a2 | 1168 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
1169 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
1170 | break; | |
7f19b9a2 | 1171 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
1172 | printf_filtered |
1173 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
1174 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
1175 | break; |
1176 | default: | |
e2e0b3e5 | 1177 | internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); |
4014092b | 1178 | break; |
361d1df0 | 1179 | } |
4014092b | 1180 | } |
c906108c | 1181 | |
4cc0665f MR |
1182 | /* Tell if the program counter value in MEMADDR is in a standard ISA |
1183 | function. */ | |
1184 | ||
1185 | int | |
1186 | mips_pc_is_mips (CORE_ADDR memaddr) | |
1187 | { | |
7cbd4a93 | 1188 | struct bound_minimal_symbol sym; |
4cc0665f MR |
1189 | |
1190 | /* Flags indicating that this is a MIPS16 or microMIPS function is | |
1191 | stored by elfread.c in the high bit of the info field. Use this | |
1192 | to decide if the function is standard MIPS. Otherwise if bit 0 | |
1193 | of the address is clear, then this is a standard MIPS function. */ | |
3e29f34a | 1194 | sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); |
7cbd4a93 TT |
1195 | if (sym.minsym) |
1196 | return msymbol_is_mips (sym.minsym); | |
4cc0665f MR |
1197 | else |
1198 | return is_mips_addr (memaddr); | |
1199 | } | |
1200 | ||
c906108c SS |
1201 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
1202 | ||
0fe7e7c8 | 1203 | int |
4cc0665f | 1204 | mips_pc_is_mips16 (struct gdbarch *gdbarch, CORE_ADDR memaddr) |
c906108c | 1205 | { |
7cbd4a93 | 1206 | struct bound_minimal_symbol sym; |
c906108c | 1207 | |
91912e4d MR |
1208 | /* A flag indicating that this is a MIPS16 function is stored by |
1209 | elfread.c in the high bit of the info field. Use this to decide | |
4cc0665f MR |
1210 | if the function is MIPS16. Otherwise if bit 0 of the address is |
1211 | set, then ELF file flags will tell if this is a MIPS16 function. */ | |
3e29f34a | 1212 | sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); |
7cbd4a93 TT |
1213 | if (sym.minsym) |
1214 | return msymbol_is_mips16 (sym.minsym); | |
4cc0665f MR |
1215 | else |
1216 | return is_mips16_addr (gdbarch, memaddr); | |
1217 | } | |
1218 | ||
1219 | /* Tell if the program counter value in MEMADDR is in a microMIPS function. */ | |
1220 | ||
1221 | int | |
1222 | mips_pc_is_micromips (struct gdbarch *gdbarch, CORE_ADDR memaddr) | |
1223 | { | |
7cbd4a93 | 1224 | struct bound_minimal_symbol sym; |
4cc0665f MR |
1225 | |
1226 | /* A flag indicating that this is a microMIPS function is stored by | |
1227 | elfread.c in the high bit of the info field. Use this to decide | |
1228 | if the function is microMIPS. Otherwise if bit 0 of the address | |
1229 | is set, then ELF file flags will tell if this is a microMIPS | |
1230 | function. */ | |
3e29f34a | 1231 | sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); |
7cbd4a93 TT |
1232 | if (sym.minsym) |
1233 | return msymbol_is_micromips (sym.minsym); | |
4cc0665f MR |
1234 | else |
1235 | return is_micromips_addr (gdbarch, memaddr); | |
1236 | } | |
1237 | ||
1238 | /* Tell the ISA type of the function the program counter value in MEMADDR | |
1239 | is in. */ | |
1240 | ||
1241 | static enum mips_isa | |
1242 | mips_pc_isa (struct gdbarch *gdbarch, CORE_ADDR memaddr) | |
1243 | { | |
7cbd4a93 | 1244 | struct bound_minimal_symbol sym; |
4cc0665f MR |
1245 | |
1246 | /* A flag indicating that this is a MIPS16 or a microMIPS function | |
1247 | is stored by elfread.c in the high bit of the info field. Use | |
1248 | this to decide if the function is MIPS16 or microMIPS or normal | |
1249 | MIPS. Otherwise if bit 0 of the address is set, then ELF file | |
1250 | flags will tell if this is a MIPS16 or a microMIPS function. */ | |
3e29f34a | 1251 | sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); |
7cbd4a93 | 1252 | if (sym.minsym) |
4cc0665f | 1253 | { |
7cbd4a93 | 1254 | if (msymbol_is_micromips (sym.minsym)) |
4cc0665f | 1255 | return ISA_MICROMIPS; |
7cbd4a93 | 1256 | else if (msymbol_is_mips16 (sym.minsym)) |
4cc0665f MR |
1257 | return ISA_MIPS16; |
1258 | else | |
1259 | return ISA_MIPS; | |
1260 | } | |
c906108c | 1261 | else |
4cc0665f MR |
1262 | { |
1263 | if (is_mips_addr (memaddr)) | |
1264 | return ISA_MIPS; | |
1265 | else if (is_micromips_addr (gdbarch, memaddr)) | |
1266 | return ISA_MICROMIPS; | |
1267 | else | |
1268 | return ISA_MIPS16; | |
1269 | } | |
c906108c SS |
1270 | } |
1271 | ||
3e29f34a MR |
1272 | /* Set the ISA bit correctly in the PC, used by DWARF-2 machinery. |
1273 | The need for comes from the ISA bit having been cleared, making | |
1274 | addresses in FDE, range records, etc. referring to compressed code | |
1275 | different to those in line information, the symbol table and finally | |
1276 | the PC register. That in turn confuses many operations. */ | |
1277 | ||
1278 | static CORE_ADDR | |
1279 | mips_adjust_dwarf2_addr (CORE_ADDR pc) | |
1280 | { | |
1281 | pc = unmake_compact_addr (pc); | |
1282 | return mips_pc_is_mips (pc) ? pc : make_compact_addr (pc); | |
1283 | } | |
1284 | ||
1285 | /* Recalculate the line record requested so that the resulting PC has | |
1286 | the ISA bit set correctly, used by DWARF-2 machinery. The need for | |
1287 | this adjustment comes from some records associated with compressed | |
1288 | code having the ISA bit cleared, most notably at function prologue | |
1289 | ends. The ISA bit is in this context retrieved from the minimal | |
1290 | symbol covering the address requested, which in turn has been | |
1291 | constructed from the binary's symbol table rather than DWARF-2 | |
1292 | information. The correct setting of the ISA bit is required for | |
1293 | breakpoint addresses to correctly match against the stop PC. | |
1294 | ||
1295 | As line entries can specify relative address adjustments we need to | |
1296 | keep track of the absolute value of the last line address recorded | |
1297 | in line information, so that we can calculate the actual address to | |
1298 | apply the ISA bit adjustment to. We use PC for this tracking and | |
1299 | keep the original address there. | |
1300 | ||
1301 | As such relative address adjustments can be odd within compressed | |
1302 | code we need to keep track of the last line address with the ISA | |
1303 | bit adjustment applied too, as the original address may or may not | |
1304 | have had the ISA bit set. We use ADJ_PC for this tracking and keep | |
1305 | the adjusted address there. | |
1306 | ||
1307 | For relative address adjustments we then use these variables to | |
1308 | calculate the address intended by line information, which will be | |
1309 | PC-relative, and return an updated adjustment carrying ISA bit | |
1310 | information, which will be ADJ_PC-relative. For absolute address | |
1311 | adjustments we just return the same address that we store in ADJ_PC | |
1312 | too. | |
1313 | ||
1314 | As the first line entry can be relative to an implied address value | |
1315 | of 0 we need to have the initial address set up that we store in PC | |
1316 | and ADJ_PC. This is arranged with a call from `dwarf_decode_lines_1' | |
1317 | that sets PC to 0 and ADJ_PC accordingly, usually 0 as well. */ | |
1318 | ||
1319 | static CORE_ADDR | |
1320 | mips_adjust_dwarf2_line (CORE_ADDR addr, int rel) | |
1321 | { | |
1322 | static CORE_ADDR adj_pc; | |
1323 | static CORE_ADDR pc; | |
1324 | CORE_ADDR isa_pc; | |
1325 | ||
1326 | pc = rel ? pc + addr : addr; | |
1327 | isa_pc = mips_adjust_dwarf2_addr (pc); | |
1328 | addr = rel ? isa_pc - adj_pc : isa_pc; | |
1329 | adj_pc = isa_pc; | |
1330 | return addr; | |
1331 | } | |
1332 | ||
14132e89 MR |
1333 | /* Various MIPS16 thunk (aka stub or trampoline) names. */ |
1334 | ||
1335 | static const char mips_str_mips16_call_stub[] = "__mips16_call_stub_"; | |
1336 | static const char mips_str_mips16_ret_stub[] = "__mips16_ret_"; | |
1337 | static const char mips_str_call_fp_stub[] = "__call_stub_fp_"; | |
1338 | static const char mips_str_call_stub[] = "__call_stub_"; | |
1339 | static const char mips_str_fn_stub[] = "__fn_stub_"; | |
1340 | ||
1341 | /* This is used as a PIC thunk prefix. */ | |
1342 | ||
1343 | static const char mips_str_pic[] = ".pic."; | |
1344 | ||
1345 | /* Return non-zero if the PC is inside a call thunk (aka stub or | |
1346 | trampoline) that should be treated as a temporary frame. */ | |
1347 | ||
1348 | static int | |
1349 | mips_in_frame_stub (CORE_ADDR pc) | |
1350 | { | |
1351 | CORE_ADDR start_addr; | |
1352 | const char *name; | |
1353 | ||
1354 | /* Find the starting address of the function containing the PC. */ | |
1355 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
1356 | return 0; | |
1357 | ||
1358 | /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */ | |
61012eef | 1359 | if (startswith (name, mips_str_mips16_call_stub)) |
14132e89 MR |
1360 | return 1; |
1361 | /* If the PC is in __call_stub_*, this is a call/return or a call stub. */ | |
61012eef | 1362 | if (startswith (name, mips_str_call_stub)) |
14132e89 MR |
1363 | return 1; |
1364 | /* If the PC is in __fn_stub_*, this is a call stub. */ | |
61012eef | 1365 | if (startswith (name, mips_str_fn_stub)) |
14132e89 MR |
1366 | return 1; |
1367 | ||
1368 | return 0; /* Not a stub. */ | |
1369 | } | |
1370 | ||
b2fa5097 | 1371 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
025bb325 | 1372 | all registers should be sign extended for simplicity? */ |
6c997a34 AC |
1373 | |
1374 | static CORE_ADDR | |
c113ed0c | 1375 | mips_read_pc (readable_regcache *regcache) |
6c997a34 | 1376 | { |
ac7936df | 1377 | int regnum = gdbarch_pc_regnum (regcache->arch ()); |
70242eb1 | 1378 | LONGEST pc; |
8376de04 | 1379 | |
c113ed0c | 1380 | regcache->cooked_read (regnum, &pc); |
61a1198a | 1381 | return pc; |
b6cb9035 AC |
1382 | } |
1383 | ||
58dfe9ff AC |
1384 | static CORE_ADDR |
1385 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1386 | { | |
14132e89 | 1387 | CORE_ADDR pc; |
930bd0e0 | 1388 | |
8376de04 | 1389 | pc = frame_unwind_register_signed (next_frame, gdbarch_pc_regnum (gdbarch)); |
14132e89 MR |
1390 | /* macro/2012-04-20: This hack skips over MIPS16 call thunks as |
1391 | intermediate frames. In this case we can get the caller's address | |
1392 | from $ra, or if $ra contains an address within a thunk as well, then | |
1393 | it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10} | |
1394 | and thus the caller's address is in $s2. */ | |
1395 | if (frame_relative_level (next_frame) >= 0 && mips_in_frame_stub (pc)) | |
1396 | { | |
1397 | pc = frame_unwind_register_signed | |
1398 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM); | |
14132e89 | 1399 | if (mips_in_frame_stub (pc)) |
3e29f34a MR |
1400 | pc = frame_unwind_register_signed |
1401 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); | |
14132e89 | 1402 | } |
930bd0e0 | 1403 | return pc; |
edfae063 AC |
1404 | } |
1405 | ||
30244cd8 UW |
1406 | static CORE_ADDR |
1407 | mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1408 | { | |
72a155b4 UW |
1409 | return frame_unwind_register_signed |
1410 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM); | |
30244cd8 UW |
1411 | } |
1412 | ||
b8a22b94 | 1413 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that |
edfae063 AC |
1414 | dummy frame. The frame ID's base needs to match the TOS value |
1415 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
1416 | breakpoint. */ | |
1417 | ||
1418 | static struct frame_id | |
b8a22b94 | 1419 | mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
edfae063 | 1420 | { |
f57d151a | 1421 | return frame_id_build |
b8a22b94 DJ |
1422 | (get_frame_register_signed (this_frame, |
1423 | gdbarch_num_regs (gdbarch) | |
1424 | + MIPS_SP_REGNUM), | |
1425 | get_frame_pc (this_frame)); | |
58dfe9ff AC |
1426 | } |
1427 | ||
5a439849 MR |
1428 | /* Implement the "write_pc" gdbarch method. */ |
1429 | ||
1430 | void | |
61a1198a | 1431 | mips_write_pc (struct regcache *regcache, CORE_ADDR pc) |
b6cb9035 | 1432 | { |
ac7936df | 1433 | int regnum = gdbarch_pc_regnum (regcache->arch ()); |
8376de04 | 1434 | |
3e29f34a | 1435 | regcache_cooked_write_unsigned (regcache, regnum, pc); |
6c997a34 | 1436 | } |
c906108c | 1437 | |
4cc0665f MR |
1438 | /* Fetch and return instruction from the specified location. Handle |
1439 | MIPS16/microMIPS as appropriate. */ | |
c906108c | 1440 | |
d37cca3d | 1441 | static ULONGEST |
4cc0665f | 1442 | mips_fetch_instruction (struct gdbarch *gdbarch, |
d09f2c3f | 1443 | enum mips_isa isa, CORE_ADDR addr, int *errp) |
c906108c | 1444 | { |
e17a4113 | 1445 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 1446 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c | 1447 | int instlen; |
d09f2c3f | 1448 | int err; |
c906108c | 1449 | |
4cc0665f | 1450 | switch (isa) |
c906108c | 1451 | { |
4cc0665f MR |
1452 | case ISA_MICROMIPS: |
1453 | case ISA_MIPS16: | |
95ac2dcf | 1454 | instlen = MIPS_INSN16_SIZE; |
4cc0665f MR |
1455 | addr = unmake_compact_addr (addr); |
1456 | break; | |
1457 | case ISA_MIPS: | |
1458 | instlen = MIPS_INSN32_SIZE; | |
1459 | break; | |
1460 | default: | |
1461 | internal_error (__FILE__, __LINE__, _("invalid ISA")); | |
1462 | break; | |
c906108c | 1463 | } |
d09f2c3f PA |
1464 | err = target_read_memory (addr, buf, instlen); |
1465 | if (errp != NULL) | |
1466 | *errp = err; | |
1467 | if (err != 0) | |
4cc0665f | 1468 | { |
d09f2c3f PA |
1469 | if (errp == NULL) |
1470 | memory_error (TARGET_XFER_E_IO, addr); | |
4cc0665f MR |
1471 | return 0; |
1472 | } | |
e17a4113 | 1473 | return extract_unsigned_integer (buf, instlen, byte_order); |
c906108c SS |
1474 | } |
1475 | ||
025bb325 | 1476 | /* These are the fields of 32 bit mips instructions. */ |
e135b889 DJ |
1477 | #define mips32_op(x) (x >> 26) |
1478 | #define itype_op(x) (x >> 26) | |
1479 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 1480 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 1481 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 1482 | |
e135b889 DJ |
1483 | #define jtype_op(x) (x >> 26) |
1484 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 1485 | |
e135b889 DJ |
1486 | #define rtype_op(x) (x >> 26) |
1487 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
1488 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
1489 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
1490 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
1491 | #define rtype_funct(x) (x & 0x3f) | |
c906108c | 1492 | |
4cc0665f MR |
1493 | /* MicroMIPS instruction fields. */ |
1494 | #define micromips_op(x) ((x) >> 10) | |
1495 | ||
1496 | /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest | |
1497 | bit and the size respectively of the field extracted. */ | |
1498 | #define b0s4_imm(x) ((x) & 0xf) | |
1499 | #define b0s5_imm(x) ((x) & 0x1f) | |
1500 | #define b0s5_reg(x) ((x) & 0x1f) | |
1501 | #define b0s7_imm(x) ((x) & 0x7f) | |
1502 | #define b0s10_imm(x) ((x) & 0x3ff) | |
1503 | #define b1s4_imm(x) (((x) >> 1) & 0xf) | |
1504 | #define b1s9_imm(x) (((x) >> 1) & 0x1ff) | |
1505 | #define b2s3_cc(x) (((x) >> 2) & 0x7) | |
1506 | #define b4s2_regl(x) (((x) >> 4) & 0x3) | |
1507 | #define b5s5_op(x) (((x) >> 5) & 0x1f) | |
1508 | #define b5s5_reg(x) (((x) >> 5) & 0x1f) | |
1509 | #define b6s4_op(x) (((x) >> 6) & 0xf) | |
1510 | #define b7s3_reg(x) (((x) >> 7) & 0x7) | |
1511 | ||
1512 | /* 32-bit instruction formats, B and S refer to the lowest bit and the size | |
1513 | respectively of the field extracted. */ | |
1514 | #define b0s6_op(x) ((x) & 0x3f) | |
1515 | #define b0s11_op(x) ((x) & 0x7ff) | |
1516 | #define b0s12_imm(x) ((x) & 0xfff) | |
1517 | #define b0s16_imm(x) ((x) & 0xffff) | |
1518 | #define b0s26_imm(x) ((x) & 0x3ffffff) | |
1519 | #define b6s10_ext(x) (((x) >> 6) & 0x3ff) | |
1520 | #define b11s5_reg(x) (((x) >> 11) & 0x1f) | |
1521 | #define b12s4_op(x) (((x) >> 12) & 0xf) | |
1522 | ||
1523 | /* Return the size in bytes of the instruction INSN encoded in the ISA | |
1524 | instruction set. */ | |
1525 | ||
1526 | static int | |
1527 | mips_insn_size (enum mips_isa isa, ULONGEST insn) | |
1528 | { | |
1529 | switch (isa) | |
1530 | { | |
1531 | case ISA_MICROMIPS: | |
100b4f2e MR |
1532 | if ((micromips_op (insn) & 0x4) == 0x4 |
1533 | || (micromips_op (insn) & 0x7) == 0x0) | |
4cc0665f MR |
1534 | return 2 * MIPS_INSN16_SIZE; |
1535 | else | |
1536 | return MIPS_INSN16_SIZE; | |
1537 | case ISA_MIPS16: | |
1538 | if ((insn & 0xf800) == 0xf000) | |
1539 | return 2 * MIPS_INSN16_SIZE; | |
1540 | else | |
1541 | return MIPS_INSN16_SIZE; | |
1542 | case ISA_MIPS: | |
1543 | return MIPS_INSN32_SIZE; | |
1544 | } | |
1545 | internal_error (__FILE__, __LINE__, _("invalid ISA")); | |
1546 | } | |
1547 | ||
06987e64 MK |
1548 | static LONGEST |
1549 | mips32_relative_offset (ULONGEST inst) | |
c5aa993b | 1550 | { |
06987e64 | 1551 | return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; |
c906108c SS |
1552 | } |
1553 | ||
a385295e MR |
1554 | /* Determine the address of the next instruction executed after the INST |
1555 | floating condition branch instruction at PC. COUNT specifies the | |
1556 | number of the floating condition bits tested by the branch. */ | |
1557 | ||
1558 | static CORE_ADDR | |
7113a196 | 1559 | mips32_bc1_pc (struct gdbarch *gdbarch, struct regcache *regcache, |
a385295e MR |
1560 | ULONGEST inst, CORE_ADDR pc, int count) |
1561 | { | |
1562 | int fcsr = mips_regnum (gdbarch)->fp_control_status; | |
1563 | int cnum = (itype_rt (inst) >> 2) & (count - 1); | |
1564 | int tf = itype_rt (inst) & 1; | |
1565 | int mask = (1 << count) - 1; | |
1566 | ULONGEST fcs; | |
1567 | int cond; | |
1568 | ||
1569 | if (fcsr == -1) | |
1570 | /* No way to handle; it'll most likely trap anyway. */ | |
1571 | return pc; | |
1572 | ||
7113a196 | 1573 | fcs = regcache_raw_get_unsigned (regcache, fcsr); |
a385295e MR |
1574 | cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); |
1575 | ||
1576 | if (((cond >> cnum) & mask) != mask * !tf) | |
1577 | pc += mips32_relative_offset (inst); | |
1578 | else | |
1579 | pc += 4; | |
1580 | ||
1581 | return pc; | |
1582 | } | |
1583 | ||
f94363d7 AP |
1584 | /* Return nonzero if the gdbarch is an Octeon series. */ |
1585 | ||
1586 | static int | |
1587 | is_octeon (struct gdbarch *gdbarch) | |
1588 | { | |
1589 | const struct bfd_arch_info *info = gdbarch_bfd_arch_info (gdbarch); | |
1590 | ||
1591 | return (info->mach == bfd_mach_mips_octeon | |
1592 | || info->mach == bfd_mach_mips_octeonp | |
1593 | || info->mach == bfd_mach_mips_octeon2); | |
1594 | } | |
1595 | ||
1596 | /* Return true if the OP represents the Octeon's BBIT instruction. */ | |
1597 | ||
1598 | static int | |
1599 | is_octeon_bbit_op (int op, struct gdbarch *gdbarch) | |
1600 | { | |
1601 | if (!is_octeon (gdbarch)) | |
1602 | return 0; | |
1603 | /* BBIT0 is encoded as LWC2: 110 010. */ | |
1604 | /* BBIT032 is encoded as LDC2: 110 110. */ | |
1605 | /* BBIT1 is encoded as SWC2: 111 010. */ | |
1606 | /* BBIT132 is encoded as SDC2: 111 110. */ | |
1607 | if (op == 50 || op == 54 || op == 58 || op == 62) | |
1608 | return 1; | |
1609 | return 0; | |
1610 | } | |
1611 | ||
1612 | ||
f49e4e6d MS |
1613 | /* Determine where to set a single step breakpoint while considering |
1614 | branch prediction. */ | |
78a59c2f | 1615 | |
5a89d8aa | 1616 | static CORE_ADDR |
7113a196 | 1617 | mips32_next_pc (struct regcache *regcache, CORE_ADDR pc) |
c5aa993b | 1618 | { |
ac7936df | 1619 | struct gdbarch *gdbarch = regcache->arch (); |
c5aa993b JM |
1620 | unsigned long inst; |
1621 | int op; | |
4cc0665f | 1622 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
4f5bcb50 | 1623 | op = itype_op (inst); |
025bb325 MS |
1624 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch |
1625 | instruction. */ | |
c5aa993b | 1626 | { |
4f5bcb50 | 1627 | if (op >> 2 == 5) |
6d82d43b | 1628 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 1629 | { |
4f5bcb50 | 1630 | switch (op & 0x03) |
c906108c | 1631 | { |
e135b889 DJ |
1632 | case 0: /* BEQL */ |
1633 | goto equal_branch; | |
1634 | case 1: /* BNEL */ | |
1635 | goto neq_branch; | |
1636 | case 2: /* BLEZL */ | |
1637 | goto less_branch; | |
313628cc | 1638 | case 3: /* BGTZL */ |
e135b889 | 1639 | goto greater_branch; |
c5aa993b JM |
1640 | default: |
1641 | pc += 4; | |
c906108c SS |
1642 | } |
1643 | } | |
4f5bcb50 | 1644 | else if (op == 17 && itype_rs (inst) == 8) |
6d82d43b | 1645 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
7113a196 | 1646 | pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 1); |
4f5bcb50 | 1647 | else if (op == 17 && itype_rs (inst) == 9 |
a385295e MR |
1648 | && (itype_rt (inst) & 2) == 0) |
1649 | /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */ | |
7113a196 | 1650 | pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 2); |
4f5bcb50 | 1651 | else if (op == 17 && itype_rs (inst) == 10 |
a385295e MR |
1652 | && (itype_rt (inst) & 2) == 0) |
1653 | /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */ | |
7113a196 | 1654 | pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 4); |
4f5bcb50 | 1655 | else if (op == 29) |
9e8da49c MR |
1656 | /* JALX: 011101 */ |
1657 | /* The new PC will be alternate mode. */ | |
1658 | { | |
1659 | unsigned long reg; | |
1660 | ||
1661 | reg = jtype_target (inst) << 2; | |
1662 | /* Add 1 to indicate 16-bit mode -- invert ISA mode. */ | |
1663 | pc = ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + reg + 1; | |
1664 | } | |
f94363d7 AP |
1665 | else if (is_octeon_bbit_op (op, gdbarch)) |
1666 | { | |
1667 | int bit, branch_if; | |
1668 | ||
1669 | branch_if = op == 58 || op == 62; | |
1670 | bit = itype_rt (inst); | |
1671 | ||
1672 | /* Take into account the *32 instructions. */ | |
1673 | if (op == 54 || op == 62) | |
1674 | bit += 32; | |
1675 | ||
7113a196 YQ |
1676 | if (((regcache_raw_get_signed (regcache, |
1677 | itype_rs (inst)) >> bit) & 1) | |
f94363d7 AP |
1678 | == branch_if) |
1679 | pc += mips32_relative_offset (inst) + 4; | |
1680 | else | |
1681 | pc += 8; /* After the delay slot. */ | |
1682 | } | |
1683 | ||
c5aa993b | 1684 | else |
025bb325 | 1685 | pc += 4; /* Not a branch, next instruction is easy. */ |
c906108c SS |
1686 | } |
1687 | else | |
025bb325 | 1688 | { /* This gets way messy. */ |
c5aa993b | 1689 | |
025bb325 | 1690 | /* Further subdivide into SPECIAL, REGIMM and other. */ |
4f5bcb50 | 1691 | switch (op & 0x07) /* Extract bits 28,27,26. */ |
c906108c | 1692 | { |
c5aa993b JM |
1693 | case 0: /* SPECIAL */ |
1694 | op = rtype_funct (inst); | |
1695 | switch (op) | |
1696 | { | |
1697 | case 8: /* JR */ | |
1698 | case 9: /* JALR */ | |
025bb325 | 1699 | /* Set PC to that address. */ |
7113a196 | 1700 | pc = regcache_raw_get_signed (regcache, rtype_rs (inst)); |
c5aa993b | 1701 | break; |
e38d4e1a DJ |
1702 | case 12: /* SYSCALL */ |
1703 | { | |
1704 | struct gdbarch_tdep *tdep; | |
1705 | ||
7113a196 | 1706 | tdep = gdbarch_tdep (gdbarch); |
e38d4e1a | 1707 | if (tdep->syscall_next_pc != NULL) |
7113a196 | 1708 | pc = tdep->syscall_next_pc (get_current_frame ()); |
e38d4e1a DJ |
1709 | else |
1710 | pc += 4; | |
1711 | } | |
1712 | break; | |
c5aa993b JM |
1713 | default: |
1714 | pc += 4; | |
1715 | } | |
1716 | ||
6d82d43b | 1717 | break; /* end SPECIAL */ |
025bb325 | 1718 | case 1: /* REGIMM */ |
c906108c | 1719 | { |
e135b889 DJ |
1720 | op = itype_rt (inst); /* branch condition */ |
1721 | switch (op) | |
c906108c | 1722 | { |
c5aa993b | 1723 | case 0: /* BLTZ */ |
e135b889 DJ |
1724 | case 2: /* BLTZL */ |
1725 | case 16: /* BLTZAL */ | |
c5aa993b | 1726 | case 18: /* BLTZALL */ |
c906108c | 1727 | less_branch: |
7113a196 | 1728 | if (regcache_raw_get_signed (regcache, itype_rs (inst)) < 0) |
c5aa993b JM |
1729 | pc += mips32_relative_offset (inst) + 4; |
1730 | else | |
1731 | pc += 8; /* after the delay slot */ | |
1732 | break; | |
e135b889 | 1733 | case 1: /* BGEZ */ |
c5aa993b JM |
1734 | case 3: /* BGEZL */ |
1735 | case 17: /* BGEZAL */ | |
1736 | case 19: /* BGEZALL */ | |
7113a196 | 1737 | if (regcache_raw_get_signed (regcache, itype_rs (inst)) >= 0) |
c5aa993b JM |
1738 | pc += mips32_relative_offset (inst) + 4; |
1739 | else | |
1740 | pc += 8; /* after the delay slot */ | |
1741 | break; | |
a385295e MR |
1742 | case 0x1c: /* BPOSGE32 */ |
1743 | case 0x1e: /* BPOSGE64 */ | |
1744 | pc += 4; | |
1745 | if (itype_rs (inst) == 0) | |
1746 | { | |
1747 | unsigned int pos = (op & 2) ? 64 : 32; | |
1748 | int dspctl = mips_regnum (gdbarch)->dspctl; | |
1749 | ||
1750 | if (dspctl == -1) | |
1751 | /* No way to handle; it'll most likely trap anyway. */ | |
1752 | break; | |
1753 | ||
7113a196 YQ |
1754 | if ((regcache_raw_get_unsigned (regcache, |
1755 | dspctl) & 0x7f) >= pos) | |
a385295e MR |
1756 | pc += mips32_relative_offset (inst); |
1757 | else | |
1758 | pc += 4; | |
1759 | } | |
1760 | break; | |
e135b889 | 1761 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1762 | default: |
1763 | pc += 4; | |
c906108c SS |
1764 | } |
1765 | } | |
6d82d43b | 1766 | break; /* end REGIMM */ |
c5aa993b JM |
1767 | case 2: /* J */ |
1768 | case 3: /* JAL */ | |
1769 | { | |
1770 | unsigned long reg; | |
1771 | reg = jtype_target (inst) << 2; | |
025bb325 | 1772 | /* Upper four bits get never changed... */ |
5b652102 | 1773 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
c906108c | 1774 | } |
c5aa993b | 1775 | break; |
e135b889 | 1776 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1777 | equal_branch: |
7113a196 YQ |
1778 | if (regcache_raw_get_signed (regcache, itype_rs (inst)) == |
1779 | regcache_raw_get_signed (regcache, itype_rt (inst))) | |
c5aa993b JM |
1780 | pc += mips32_relative_offset (inst) + 4; |
1781 | else | |
1782 | pc += 8; | |
1783 | break; | |
e135b889 | 1784 | case 5: /* BNE, BNEL */ |
c5aa993b | 1785 | neq_branch: |
7113a196 YQ |
1786 | if (regcache_raw_get_signed (regcache, itype_rs (inst)) != |
1787 | regcache_raw_get_signed (regcache, itype_rt (inst))) | |
c5aa993b JM |
1788 | pc += mips32_relative_offset (inst) + 4; |
1789 | else | |
1790 | pc += 8; | |
1791 | break; | |
e135b889 | 1792 | case 6: /* BLEZ, BLEZL */ |
7113a196 | 1793 | if (regcache_raw_get_signed (regcache, itype_rs (inst)) <= 0) |
c5aa993b JM |
1794 | pc += mips32_relative_offset (inst) + 4; |
1795 | else | |
1796 | pc += 8; | |
1797 | break; | |
1798 | case 7: | |
e135b889 DJ |
1799 | default: |
1800 | greater_branch: /* BGTZ, BGTZL */ | |
7113a196 | 1801 | if (regcache_raw_get_signed (regcache, itype_rs (inst)) > 0) |
c5aa993b JM |
1802 | pc += mips32_relative_offset (inst) + 4; |
1803 | else | |
1804 | pc += 8; | |
1805 | break; | |
c5aa993b JM |
1806 | } /* switch */ |
1807 | } /* else */ | |
1808 | return pc; | |
1809 | } /* mips32_next_pc */ | |
c906108c | 1810 | |
4cc0665f MR |
1811 | /* Extract the 7-bit signed immediate offset from the microMIPS instruction |
1812 | INSN. */ | |
1813 | ||
1814 | static LONGEST | |
1815 | micromips_relative_offset7 (ULONGEST insn) | |
1816 | { | |
1817 | return ((b0s7_imm (insn) ^ 0x40) - 0x40) << 1; | |
1818 | } | |
1819 | ||
1820 | /* Extract the 10-bit signed immediate offset from the microMIPS instruction | |
1821 | INSN. */ | |
1822 | ||
1823 | static LONGEST | |
1824 | micromips_relative_offset10 (ULONGEST insn) | |
1825 | { | |
1826 | return ((b0s10_imm (insn) ^ 0x200) - 0x200) << 1; | |
1827 | } | |
1828 | ||
1829 | /* Extract the 16-bit signed immediate offset from the microMIPS instruction | |
1830 | INSN. */ | |
1831 | ||
1832 | static LONGEST | |
1833 | micromips_relative_offset16 (ULONGEST insn) | |
1834 | { | |
1835 | return ((b0s16_imm (insn) ^ 0x8000) - 0x8000) << 1; | |
1836 | } | |
1837 | ||
1838 | /* Return the size in bytes of the microMIPS instruction at the address PC. */ | |
1839 | ||
1840 | static int | |
1841 | micromips_pc_insn_size (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1842 | { | |
1843 | ULONGEST insn; | |
1844 | ||
1845 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
1846 | return mips_insn_size (ISA_MICROMIPS, insn); | |
1847 | } | |
1848 | ||
1849 | /* Calculate the address of the next microMIPS instruction to execute | |
1850 | after the INSN coprocessor 1 conditional branch instruction at the | |
1851 | address PC. COUNT denotes the number of coprocessor condition bits | |
1852 | examined by the branch. */ | |
1853 | ||
1854 | static CORE_ADDR | |
7113a196 | 1855 | micromips_bc1_pc (struct gdbarch *gdbarch, struct regcache *regcache, |
4cc0665f MR |
1856 | ULONGEST insn, CORE_ADDR pc, int count) |
1857 | { | |
1858 | int fcsr = mips_regnum (gdbarch)->fp_control_status; | |
1859 | int cnum = b2s3_cc (insn >> 16) & (count - 1); | |
1860 | int tf = b5s5_op (insn >> 16) & 1; | |
1861 | int mask = (1 << count) - 1; | |
1862 | ULONGEST fcs; | |
1863 | int cond; | |
1864 | ||
1865 | if (fcsr == -1) | |
1866 | /* No way to handle; it'll most likely trap anyway. */ | |
1867 | return pc; | |
1868 | ||
7113a196 | 1869 | fcs = regcache_raw_get_unsigned (regcache, fcsr); |
4cc0665f MR |
1870 | cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); |
1871 | ||
1872 | if (((cond >> cnum) & mask) != mask * !tf) | |
1873 | pc += micromips_relative_offset16 (insn); | |
1874 | else | |
1875 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1876 | ||
1877 | return pc; | |
1878 | } | |
1879 | ||
1880 | /* Calculate the address of the next microMIPS instruction to execute | |
1881 | after the instruction at the address PC. */ | |
1882 | ||
1883 | static CORE_ADDR | |
7113a196 | 1884 | micromips_next_pc (struct regcache *regcache, CORE_ADDR pc) |
4cc0665f | 1885 | { |
ac7936df | 1886 | struct gdbarch *gdbarch = regcache->arch (); |
4cc0665f MR |
1887 | ULONGEST insn; |
1888 | ||
1889 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
1890 | pc += MIPS_INSN16_SIZE; | |
1891 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
1892 | { | |
4cc0665f MR |
1893 | /* 32-bit instructions. */ |
1894 | case 2 * MIPS_INSN16_SIZE: | |
1895 | insn <<= 16; | |
1896 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
1897 | pc += MIPS_INSN16_SIZE; | |
1898 | switch (micromips_op (insn >> 16)) | |
1899 | { | |
1900 | case 0x00: /* POOL32A: bits 000000 */ | |
6592ceed MR |
1901 | switch (b0s6_op (insn)) |
1902 | { | |
1903 | case 0x3c: /* POOL32Axf: bits 000000 ... 111100 */ | |
1904 | switch (b6s10_ext (insn)) | |
1905 | { | |
1906 | case 0x3c: /* JALR: 000000 0000111100 111100 */ | |
1907 | case 0x7c: /* JALR.HB: 000000 0001111100 111100 */ | |
1908 | case 0x13c: /* JALRS: 000000 0100111100 111100 */ | |
1909 | case 0x17c: /* JALRS.HB: 000000 0101111100 111100 */ | |
1910 | pc = regcache_raw_get_signed (regcache, | |
1911 | b0s5_reg (insn >> 16)); | |
1912 | break; | |
1913 | case 0x22d: /* SYSCALL: 000000 1000101101 111100 */ | |
1914 | { | |
1915 | struct gdbarch_tdep *tdep; | |
1916 | ||
1917 | tdep = gdbarch_tdep (gdbarch); | |
1918 | if (tdep->syscall_next_pc != NULL) | |
1919 | pc = tdep->syscall_next_pc (get_current_frame ()); | |
1920 | } | |
1921 | break; | |
1922 | } | |
1923 | break; | |
1924 | } | |
4cc0665f MR |
1925 | break; |
1926 | ||
1927 | case 0x10: /* POOL32I: bits 010000 */ | |
1928 | switch (b5s5_op (insn >> 16)) | |
1929 | { | |
1930 | case 0x00: /* BLTZ: bits 010000 00000 */ | |
1931 | case 0x01: /* BLTZAL: bits 010000 00001 */ | |
1932 | case 0x11: /* BLTZALS: bits 010000 10001 */ | |
7113a196 YQ |
1933 | if (regcache_raw_get_signed (regcache, |
1934 | b0s5_reg (insn >> 16)) < 0) | |
4cc0665f MR |
1935 | pc += micromips_relative_offset16 (insn); |
1936 | else | |
1937 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1938 | break; | |
1939 | ||
1940 | case 0x02: /* BGEZ: bits 010000 00010 */ | |
1941 | case 0x03: /* BGEZAL: bits 010000 00011 */ | |
1942 | case 0x13: /* BGEZALS: bits 010000 10011 */ | |
7113a196 YQ |
1943 | if (regcache_raw_get_signed (regcache, |
1944 | b0s5_reg (insn >> 16)) >= 0) | |
4cc0665f MR |
1945 | pc += micromips_relative_offset16 (insn); |
1946 | else | |
1947 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1948 | break; | |
1949 | ||
1950 | case 0x04: /* BLEZ: bits 010000 00100 */ | |
7113a196 YQ |
1951 | if (regcache_raw_get_signed (regcache, |
1952 | b0s5_reg (insn >> 16)) <= 0) | |
4cc0665f MR |
1953 | pc += micromips_relative_offset16 (insn); |
1954 | else | |
1955 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1956 | break; | |
1957 | ||
1958 | case 0x05: /* BNEZC: bits 010000 00101 */ | |
7113a196 YQ |
1959 | if (regcache_raw_get_signed (regcache, |
1960 | b0s5_reg (insn >> 16)) != 0) | |
4cc0665f MR |
1961 | pc += micromips_relative_offset16 (insn); |
1962 | break; | |
1963 | ||
1964 | case 0x06: /* BGTZ: bits 010000 00110 */ | |
7113a196 YQ |
1965 | if (regcache_raw_get_signed (regcache, |
1966 | b0s5_reg (insn >> 16)) > 0) | |
4cc0665f MR |
1967 | pc += micromips_relative_offset16 (insn); |
1968 | else | |
1969 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1970 | break; | |
1971 | ||
1972 | case 0x07: /* BEQZC: bits 010000 00111 */ | |
7113a196 YQ |
1973 | if (regcache_raw_get_signed (regcache, |
1974 | b0s5_reg (insn >> 16)) == 0) | |
4cc0665f MR |
1975 | pc += micromips_relative_offset16 (insn); |
1976 | break; | |
1977 | ||
1978 | case 0x14: /* BC2F: bits 010000 10100 xxx00 */ | |
1979 | case 0x15: /* BC2T: bits 010000 10101 xxx00 */ | |
1980 | if (((insn >> 16) & 0x3) == 0x0) | |
1981 | /* BC2F, BC2T: don't know how to handle these. */ | |
1982 | break; | |
1983 | break; | |
1984 | ||
1985 | case 0x1a: /* BPOSGE64: bits 010000 11010 */ | |
1986 | case 0x1b: /* BPOSGE32: bits 010000 11011 */ | |
1987 | { | |
1988 | unsigned int pos = (b5s5_op (insn >> 16) & 1) ? 32 : 64; | |
1989 | int dspctl = mips_regnum (gdbarch)->dspctl; | |
1990 | ||
1991 | if (dspctl == -1) | |
1992 | /* No way to handle; it'll most likely trap anyway. */ | |
1993 | break; | |
1994 | ||
7113a196 YQ |
1995 | if ((regcache_raw_get_unsigned (regcache, |
1996 | dspctl) & 0x7f) >= pos) | |
4cc0665f MR |
1997 | pc += micromips_relative_offset16 (insn); |
1998 | else | |
1999 | pc += micromips_pc_insn_size (gdbarch, pc); | |
2000 | } | |
2001 | break; | |
2002 | ||
2003 | case 0x1c: /* BC1F: bits 010000 11100 xxx00 */ | |
2004 | /* BC1ANY2F: bits 010000 11100 xxx01 */ | |
2005 | case 0x1d: /* BC1T: bits 010000 11101 xxx00 */ | |
2006 | /* BC1ANY2T: bits 010000 11101 xxx01 */ | |
2007 | if (((insn >> 16) & 0x2) == 0x0) | |
7113a196 | 2008 | pc = micromips_bc1_pc (gdbarch, regcache, insn, pc, |
4cc0665f MR |
2009 | ((insn >> 16) & 0x1) + 1); |
2010 | break; | |
2011 | ||
2012 | case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */ | |
2013 | case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */ | |
2014 | if (((insn >> 16) & 0x3) == 0x1) | |
7113a196 | 2015 | pc = micromips_bc1_pc (gdbarch, regcache, insn, pc, 4); |
4cc0665f MR |
2016 | break; |
2017 | } | |
2018 | break; | |
2019 | ||
2020 | case 0x1d: /* JALS: bits 011101 */ | |
2021 | case 0x35: /* J: bits 110101 */ | |
2022 | case 0x3d: /* JAL: bits 111101 */ | |
2023 | pc = ((pc | 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn) << 1); | |
2024 | break; | |
2025 | ||
2026 | case 0x25: /* BEQ: bits 100101 */ | |
7113a196 YQ |
2027 | if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16)) |
2028 | == regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16))) | |
4cc0665f MR |
2029 | pc += micromips_relative_offset16 (insn); |
2030 | else | |
2031 | pc += micromips_pc_insn_size (gdbarch, pc); | |
2032 | break; | |
2033 | ||
2034 | case 0x2d: /* BNE: bits 101101 */ | |
7113a196 YQ |
2035 | if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16)) |
2036 | != regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16))) | |
4cc0665f MR |
2037 | pc += micromips_relative_offset16 (insn); |
2038 | else | |
2039 | pc += micromips_pc_insn_size (gdbarch, pc); | |
2040 | break; | |
2041 | ||
2042 | case 0x3c: /* JALX: bits 111100 */ | |
2043 | pc = ((pc | 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn) << 2); | |
2044 | break; | |
2045 | } | |
2046 | break; | |
2047 | ||
2048 | /* 16-bit instructions. */ | |
2049 | case MIPS_INSN16_SIZE: | |
2050 | switch (micromips_op (insn)) | |
2051 | { | |
2052 | case 0x11: /* POOL16C: bits 010001 */ | |
2053 | if ((b5s5_op (insn) & 0x1c) == 0xc) | |
2054 | /* JR16, JRC, JALR16, JALRS16: 010001 011xx */ | |
7113a196 | 2055 | pc = regcache_raw_get_signed (regcache, b0s5_reg (insn)); |
4cc0665f MR |
2056 | else if (b5s5_op (insn) == 0x18) |
2057 | /* JRADDIUSP: bits 010001 11000 */ | |
7113a196 | 2058 | pc = regcache_raw_get_signed (regcache, MIPS_RA_REGNUM); |
4cc0665f MR |
2059 | break; |
2060 | ||
2061 | case 0x23: /* BEQZ16: bits 100011 */ | |
2062 | { | |
2063 | int rs = mips_reg3_to_reg[b7s3_reg (insn)]; | |
2064 | ||
7113a196 | 2065 | if (regcache_raw_get_signed (regcache, rs) == 0) |
4cc0665f MR |
2066 | pc += micromips_relative_offset7 (insn); |
2067 | else | |
2068 | pc += micromips_pc_insn_size (gdbarch, pc); | |
2069 | } | |
2070 | break; | |
2071 | ||
2072 | case 0x2b: /* BNEZ16: bits 101011 */ | |
2073 | { | |
2074 | int rs = mips_reg3_to_reg[b7s3_reg (insn)]; | |
2075 | ||
7113a196 | 2076 | if (regcache_raw_get_signed (regcache, rs) != 0) |
4cc0665f MR |
2077 | pc += micromips_relative_offset7 (insn); |
2078 | else | |
2079 | pc += micromips_pc_insn_size (gdbarch, pc); | |
2080 | } | |
2081 | break; | |
2082 | ||
2083 | case 0x33: /* B16: bits 110011 */ | |
2084 | pc += micromips_relative_offset10 (insn); | |
2085 | break; | |
2086 | } | |
2087 | break; | |
2088 | } | |
2089 | ||
2090 | return pc; | |
2091 | } | |
2092 | ||
c906108c | 2093 | /* Decoding the next place to set a breakpoint is irregular for the |
025bb325 MS |
2094 | mips 16 variant, but fortunately, there fewer instructions. We have |
2095 | to cope ith extensions for 16 bit instructions and a pair of actual | |
2096 | 32 bit instructions. We dont want to set a single step instruction | |
2097 | on the extend instruction either. */ | |
c906108c SS |
2098 | |
2099 | /* Lots of mips16 instruction formats */ | |
2100 | /* Predicting jumps requires itype,ritype,i8type | |
025bb325 | 2101 | and their extensions extItype,extritype,extI8type. */ |
c906108c SS |
2102 | enum mips16_inst_fmts |
2103 | { | |
c5aa993b JM |
2104 | itype, /* 0 immediate 5,10 */ |
2105 | ritype, /* 1 5,3,8 */ | |
2106 | rrtype, /* 2 5,3,3,5 */ | |
2107 | rritype, /* 3 5,3,3,5 */ | |
2108 | rrrtype, /* 4 5,3,3,3,2 */ | |
2109 | rriatype, /* 5 5,3,3,1,4 */ | |
2110 | shifttype, /* 6 5,3,3,3,2 */ | |
2111 | i8type, /* 7 5,3,8 */ | |
2112 | i8movtype, /* 8 5,3,3,5 */ | |
2113 | i8mov32rtype, /* 9 5,3,5,3 */ | |
2114 | i64type, /* 10 5,3,8 */ | |
2115 | ri64type, /* 11 5,3,3,5 */ | |
2116 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
2117 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
2118 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
2119 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
2120 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
2121 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
2122 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
2123 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
2124 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
2125 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
2126 | }; | |
12f02c2a | 2127 | /* I am heaping all the fields of the formats into one structure and |
025bb325 | 2128 | then, only the fields which are involved in instruction extension. */ |
c906108c | 2129 | struct upk_mips16 |
6d82d43b AC |
2130 | { |
2131 | CORE_ADDR offset; | |
025bb325 | 2132 | unsigned int regx; /* Function in i8 type. */ |
6d82d43b AC |
2133 | unsigned int regy; |
2134 | }; | |
c906108c SS |
2135 | |
2136 | ||
12f02c2a | 2137 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
c68cf8ad | 2138 | for the bits which make up the immediate extension. */ |
c906108c | 2139 | |
12f02c2a AC |
2140 | static CORE_ADDR |
2141 | extended_offset (unsigned int extension) | |
c906108c | 2142 | { |
12f02c2a | 2143 | CORE_ADDR value; |
130854df | 2144 | |
4c2051c6 | 2145 | value = (extension >> 16) & 0x1f; /* Extract 15:11. */ |
c5aa993b | 2146 | value = value << 6; |
4c2051c6 | 2147 | value |= (extension >> 21) & 0x3f; /* Extract 10:5. */ |
c5aa993b | 2148 | value = value << 5; |
130854df MR |
2149 | value |= extension & 0x1f; /* Extract 4:0. */ |
2150 | ||
c5aa993b | 2151 | return value; |
c906108c SS |
2152 | } |
2153 | ||
2154 | /* Only call this function if you know that this is an extendable | |
bcf1ea1e MR |
2155 | instruction. It won't malfunction, but why make excess remote memory |
2156 | references? If the immediate operands get sign extended or something, | |
2157 | do it after the extension is performed. */ | |
c906108c | 2158 | /* FIXME: Every one of these cases needs to worry about sign extension |
bcf1ea1e | 2159 | when the offset is to be used in relative addressing. */ |
c906108c | 2160 | |
12f02c2a | 2161 | static unsigned int |
e17a4113 | 2162 | fetch_mips_16 (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 2163 | { |
e17a4113 | 2164 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 2165 | gdb_byte buf[8]; |
a2fb2cee MR |
2166 | |
2167 | pc = unmake_compact_addr (pc); /* Clear the low order bit. */ | |
c5aa993b | 2168 | target_read_memory (pc, buf, 2); |
e17a4113 | 2169 | return extract_unsigned_integer (buf, 2, byte_order); |
c906108c SS |
2170 | } |
2171 | ||
2172 | static void | |
e17a4113 | 2173 | unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc, |
12f02c2a AC |
2174 | unsigned int extension, |
2175 | unsigned int inst, | |
6d82d43b | 2176 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 2177 | { |
12f02c2a AC |
2178 | CORE_ADDR offset; |
2179 | int regx; | |
2180 | int regy; | |
2181 | switch (insn_format) | |
c906108c | 2182 | { |
c5aa993b | 2183 | case itype: |
c906108c | 2184 | { |
12f02c2a AC |
2185 | CORE_ADDR value; |
2186 | if (extension) | |
c5aa993b | 2187 | { |
4c2051c6 MR |
2188 | value = extended_offset ((extension << 16) | inst); |
2189 | value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ | |
c906108c SS |
2190 | } |
2191 | else | |
c5aa993b | 2192 | { |
12f02c2a | 2193 | value = inst & 0x7ff; |
4c2051c6 | 2194 | value = (value ^ 0x400) - 0x400; /* Sign-extend. */ |
c906108c | 2195 | } |
12f02c2a AC |
2196 | offset = value; |
2197 | regx = -1; | |
2198 | regy = -1; | |
c906108c | 2199 | } |
c5aa993b JM |
2200 | break; |
2201 | case ritype: | |
2202 | case i8type: | |
025bb325 | 2203 | { /* A register identifier and an offset. */ |
c906108c | 2204 | /* Most of the fields are the same as I type but the |
025bb325 | 2205 | immediate value is of a different length. */ |
12f02c2a AC |
2206 | CORE_ADDR value; |
2207 | if (extension) | |
c906108c | 2208 | { |
4c2051c6 MR |
2209 | value = extended_offset ((extension << 16) | inst); |
2210 | value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ | |
c906108c | 2211 | } |
c5aa993b JM |
2212 | else |
2213 | { | |
4c2051c6 MR |
2214 | value = inst & 0xff; /* 8 bits */ |
2215 | value = (value ^ 0x80) - 0x80; /* Sign-extend. */ | |
c5aa993b | 2216 | } |
12f02c2a | 2217 | offset = value; |
4c2051c6 | 2218 | regx = (inst >> 8) & 0x07; /* i8 funct */ |
12f02c2a | 2219 | regy = -1; |
c5aa993b | 2220 | break; |
c906108c | 2221 | } |
c5aa993b | 2222 | case jalxtype: |
c906108c | 2223 | { |
c5aa993b | 2224 | unsigned long value; |
12f02c2a AC |
2225 | unsigned int nexthalf; |
2226 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b | 2227 | value = value << 16; |
4cc0665f MR |
2228 | nexthalf = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc + 2, NULL); |
2229 | /* Low bit still set. */ | |
c5aa993b | 2230 | value |= nexthalf; |
12f02c2a AC |
2231 | offset = value; |
2232 | regx = -1; | |
2233 | regy = -1; | |
c5aa993b | 2234 | break; |
c906108c SS |
2235 | } |
2236 | default: | |
e2e0b3e5 | 2237 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c | 2238 | } |
12f02c2a AC |
2239 | upk->offset = offset; |
2240 | upk->regx = regx; | |
2241 | upk->regy = regy; | |
c906108c SS |
2242 | } |
2243 | ||
2244 | ||
484933d1 MR |
2245 | /* Calculate the destination of a branch whose 16-bit opcode word is at PC, |
2246 | and having a signed 16-bit OFFSET. */ | |
2247 | ||
c5aa993b JM |
2248 | static CORE_ADDR |
2249 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 2250 | { |
484933d1 | 2251 | return pc + (offset << 1) + 2; |
c906108c SS |
2252 | } |
2253 | ||
12f02c2a | 2254 | static CORE_ADDR |
7113a196 | 2255 | extended_mips16_next_pc (regcache *regcache, CORE_ADDR pc, |
6d82d43b | 2256 | unsigned int extension, unsigned int insn) |
c906108c | 2257 | { |
ac7936df | 2258 | struct gdbarch *gdbarch = regcache->arch (); |
12f02c2a AC |
2259 | int op = (insn >> 11); |
2260 | switch (op) | |
c906108c | 2261 | { |
6d82d43b | 2262 | case 2: /* Branch */ |
12f02c2a | 2263 | { |
12f02c2a | 2264 | struct upk_mips16 upk; |
e17a4113 | 2265 | unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk); |
484933d1 | 2266 | pc = add_offset_16 (pc, upk.offset); |
12f02c2a AC |
2267 | break; |
2268 | } | |
025bb325 MS |
2269 | case 3: /* JAL , JALX - Watch out, these are 32 bit |
2270 | instructions. */ | |
12f02c2a AC |
2271 | { |
2272 | struct upk_mips16 upk; | |
e17a4113 | 2273 | unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk); |
484933d1 | 2274 | pc = ((pc + 2) & (~(CORE_ADDR) 0x0fffffff)) | (upk.offset << 2); |
12f02c2a | 2275 | if ((insn >> 10) & 0x01) /* Exchange mode */ |
025bb325 | 2276 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode. */ |
12f02c2a AC |
2277 | else |
2278 | pc |= 0x01; | |
2279 | break; | |
2280 | } | |
6d82d43b | 2281 | case 4: /* beqz */ |
12f02c2a AC |
2282 | { |
2283 | struct upk_mips16 upk; | |
2284 | int reg; | |
e17a4113 | 2285 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
7113a196 | 2286 | reg = regcache_raw_get_signed (regcache, mips_reg3_to_reg[upk.regx]); |
12f02c2a | 2287 | if (reg == 0) |
484933d1 | 2288 | pc = add_offset_16 (pc, upk.offset); |
12f02c2a AC |
2289 | else |
2290 | pc += 2; | |
2291 | break; | |
2292 | } | |
6d82d43b | 2293 | case 5: /* bnez */ |
12f02c2a AC |
2294 | { |
2295 | struct upk_mips16 upk; | |
2296 | int reg; | |
e17a4113 | 2297 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
7113a196 | 2298 | reg = regcache_raw_get_signed (regcache, mips_reg3_to_reg[upk.regx]); |
12f02c2a | 2299 | if (reg != 0) |
484933d1 | 2300 | pc = add_offset_16 (pc, upk.offset); |
12f02c2a AC |
2301 | else |
2302 | pc += 2; | |
2303 | break; | |
2304 | } | |
6d82d43b | 2305 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
2306 | { |
2307 | struct upk_mips16 upk; | |
2308 | int reg; | |
e17a4113 | 2309 | unpack_mips16 (gdbarch, pc, extension, insn, i8type, &upk); |
12f02c2a | 2310 | /* upk.regx contains the opcode */ |
7113a196 YQ |
2311 | /* Test register is 24 */ |
2312 | reg = regcache_raw_get_signed (regcache, 24); | |
12f02c2a AC |
2313 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ |
2314 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
484933d1 | 2315 | pc = add_offset_16 (pc, upk.offset); |
12f02c2a AC |
2316 | else |
2317 | pc += 2; | |
2318 | break; | |
2319 | } | |
6d82d43b | 2320 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
2321 | { |
2322 | struct upk_mips16 upk; | |
2323 | /* upk.fmt = rrtype; */ | |
2324 | op = insn & 0x1f; | |
2325 | if (op == 0) | |
c5aa993b | 2326 | { |
12f02c2a AC |
2327 | int reg; |
2328 | upk.regx = (insn >> 8) & 0x07; | |
2329 | upk.regy = (insn >> 5) & 0x07; | |
4c2051c6 | 2330 | if ((upk.regy & 1) == 0) |
4cc0665f | 2331 | reg = mips_reg3_to_reg[upk.regx]; |
4c2051c6 MR |
2332 | else |
2333 | reg = 31; /* Function return instruction. */ | |
7113a196 | 2334 | pc = regcache_raw_get_signed (regcache, reg); |
c906108c | 2335 | } |
12f02c2a | 2336 | else |
c5aa993b | 2337 | pc += 2; |
12f02c2a AC |
2338 | break; |
2339 | } | |
2340 | case 30: | |
2341 | /* This is an instruction extension. Fetch the real instruction | |
2342 | (which follows the extension) and decode things based on | |
025bb325 | 2343 | that. */ |
12f02c2a AC |
2344 | { |
2345 | pc += 2; | |
7113a196 | 2346 | pc = extended_mips16_next_pc (regcache, pc, insn, |
e17a4113 | 2347 | fetch_mips_16 (gdbarch, pc)); |
12f02c2a AC |
2348 | break; |
2349 | } | |
2350 | default: | |
2351 | { | |
2352 | pc += 2; | |
2353 | break; | |
2354 | } | |
c906108c | 2355 | } |
c5aa993b | 2356 | return pc; |
12f02c2a | 2357 | } |
c906108c | 2358 | |
5a89d8aa | 2359 | static CORE_ADDR |
7113a196 | 2360 | mips16_next_pc (struct regcache *regcache, CORE_ADDR pc) |
12f02c2a | 2361 | { |
ac7936df | 2362 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 2363 | unsigned int insn = fetch_mips_16 (gdbarch, pc); |
7113a196 | 2364 | return extended_mips16_next_pc (regcache, pc, 0, insn); |
12f02c2a AC |
2365 | } |
2366 | ||
2367 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 2368 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a | 2369 | It works by decoding the current instruction and predicting where a |
1aee363c | 2370 | branch will go. This isn't hard because all the data is available. |
4cc0665f | 2371 | The MIPS32, MIPS16 and microMIPS variants are quite different. */ |
ad527d2e | 2372 | static CORE_ADDR |
7113a196 | 2373 | mips_next_pc (struct regcache *regcache, CORE_ADDR pc) |
c906108c | 2374 | { |
ac7936df | 2375 | struct gdbarch *gdbarch = regcache->arch (); |
4cc0665f MR |
2376 | |
2377 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
7113a196 | 2378 | return mips16_next_pc (regcache, pc); |
4cc0665f | 2379 | else if (mips_pc_is_micromips (gdbarch, pc)) |
7113a196 | 2380 | return micromips_next_pc (regcache, pc); |
c5aa993b | 2381 | else |
7113a196 | 2382 | return mips32_next_pc (regcache, pc); |
12f02c2a | 2383 | } |
c906108c | 2384 | |
ab50adb6 MR |
2385 | /* Return non-zero if the MIPS16 instruction INSN is a compact branch |
2386 | or jump. */ | |
2387 | ||
2388 | static int | |
2389 | mips16_instruction_is_compact_branch (unsigned short insn) | |
2390 | { | |
2391 | switch (insn & 0xf800) | |
2392 | { | |
2393 | case 0xe800: | |
2394 | return (insn & 0x009f) == 0x80; /* JALRC/JRC */ | |
2395 | case 0x6000: | |
2396 | return (insn & 0x0600) == 0; /* BTNEZ/BTEQZ */ | |
2397 | case 0x2800: /* BNEZ */ | |
2398 | case 0x2000: /* BEQZ */ | |
2399 | case 0x1000: /* B */ | |
2400 | return 1; | |
2401 | default: | |
2402 | return 0; | |
2403 | } | |
2404 | } | |
2405 | ||
2406 | /* Return non-zero if the microMIPS instruction INSN is a compact branch | |
2407 | or jump. */ | |
2408 | ||
2409 | static int | |
2410 | micromips_instruction_is_compact_branch (unsigned short insn) | |
2411 | { | |
2412 | switch (micromips_op (insn)) | |
2413 | { | |
2414 | case 0x11: /* POOL16C: bits 010001 */ | |
2415 | return (b5s5_op (insn) == 0x18 | |
2416 | /* JRADDIUSP: bits 010001 11000 */ | |
2417 | || b5s5_op (insn) == 0xd); | |
2418 | /* JRC: bits 010011 01101 */ | |
2419 | case 0x10: /* POOL32I: bits 010000 */ | |
2420 | return (b5s5_op (insn) & 0x1d) == 0x5; | |
2421 | /* BEQZC/BNEZC: bits 010000 001x1 */ | |
2422 | default: | |
2423 | return 0; | |
2424 | } | |
2425 | } | |
2426 | ||
edfae063 AC |
2427 | struct mips_frame_cache |
2428 | { | |
2429 | CORE_ADDR base; | |
2430 | struct trad_frame_saved_reg *saved_regs; | |
2431 | }; | |
2432 | ||
29639122 JB |
2433 | /* Set a register's saved stack address in temp_saved_regs. If an |
2434 | address has already been set for this register, do nothing; this | |
2435 | way we will only recognize the first save of a given register in a | |
2436 | function prologue. | |
eec63939 | 2437 | |
f57d151a UW |
2438 | For simplicity, save the address in both [0 .. gdbarch_num_regs) and |
2439 | [gdbarch_num_regs .. 2*gdbarch_num_regs). | |
2440 | Strictly speaking, only the second range is used as it is only second | |
2441 | range (the ABI instead of ISA registers) that comes into play when finding | |
2442 | saved registers in a frame. */ | |
eec63939 AC |
2443 | |
2444 | static void | |
74ed0bb4 MD |
2445 | set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache, |
2446 | int regnum, CORE_ADDR offset) | |
eec63939 | 2447 | { |
29639122 JB |
2448 | if (this_cache != NULL |
2449 | && this_cache->saved_regs[regnum].addr == -1) | |
2450 | { | |
74ed0bb4 MD |
2451 | this_cache->saved_regs[regnum + 0 * gdbarch_num_regs (gdbarch)].addr |
2452 | = offset; | |
2453 | this_cache->saved_regs[regnum + 1 * gdbarch_num_regs (gdbarch)].addr | |
2454 | = offset; | |
29639122 | 2455 | } |
eec63939 AC |
2456 | } |
2457 | ||
eec63939 | 2458 | |
29639122 JB |
2459 | /* Fetch the immediate value from a MIPS16 instruction. |
2460 | If the previous instruction was an EXTEND, use it to extend | |
2461 | the upper bits of the immediate value. This is a helper function | |
2462 | for mips16_scan_prologue. */ | |
eec63939 | 2463 | |
29639122 JB |
2464 | static int |
2465 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ | |
2466 | unsigned short inst, /* current instruction */ | |
2467 | int nbits, /* number of bits in imm field */ | |
2468 | int scale, /* scale factor to be applied to imm */ | |
025bb325 | 2469 | int is_signed) /* is the imm field signed? */ |
eec63939 | 2470 | { |
29639122 | 2471 | int offset; |
eec63939 | 2472 | |
29639122 JB |
2473 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
2474 | { | |
2475 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
2476 | if (offset & 0x8000) /* check for negative extend */ | |
2477 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
2478 | return offset | (inst & 0x1f); | |
2479 | } | |
eec63939 | 2480 | else |
29639122 JB |
2481 | { |
2482 | int max_imm = 1 << nbits; | |
2483 | int mask = max_imm - 1; | |
2484 | int sign_bit = max_imm >> 1; | |
45c9dd44 | 2485 | |
29639122 JB |
2486 | offset = inst & mask; |
2487 | if (is_signed && (offset & sign_bit)) | |
2488 | offset = 0 - (max_imm - offset); | |
2489 | return offset * scale; | |
2490 | } | |
2491 | } | |
eec63939 | 2492 | |
65596487 | 2493 | |
29639122 JB |
2494 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
2495 | the associated FRAME_CACHE if not null. | |
2496 | Return the address of the first instruction past the prologue. */ | |
eec63939 | 2497 | |
29639122 | 2498 | static CORE_ADDR |
e17a4113 UW |
2499 | mips16_scan_prologue (struct gdbarch *gdbarch, |
2500 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 2501 | struct frame_info *this_frame, |
29639122 JB |
2502 | struct mips_frame_cache *this_cache) |
2503 | { | |
ab50adb6 MR |
2504 | int prev_non_prologue_insn = 0; |
2505 | int this_non_prologue_insn; | |
2506 | int non_prologue_insns = 0; | |
2507 | CORE_ADDR prev_pc; | |
29639122 | 2508 | CORE_ADDR cur_pc; |
025bb325 | 2509 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer. */ |
29639122 JB |
2510 | CORE_ADDR sp; |
2511 | long frame_offset = 0; /* Size of stack frame. */ | |
2512 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
2513 | int frame_reg = MIPS_SP_REGNUM; | |
025bb325 | 2514 | unsigned short prev_inst = 0; /* saved copy of previous instruction. */ |
29639122 JB |
2515 | unsigned inst = 0; /* current instruction */ |
2516 | unsigned entry_inst = 0; /* the entry instruction */ | |
2207132d | 2517 | unsigned save_inst = 0; /* the save instruction */ |
ab50adb6 MR |
2518 | int prev_delay_slot = 0; |
2519 | int in_delay_slot; | |
29639122 | 2520 | int reg, offset; |
a343eb3c | 2521 | |
29639122 | 2522 | int extend_bytes = 0; |
ab50adb6 MR |
2523 | int prev_extend_bytes = 0; |
2524 | CORE_ADDR end_prologue_addr; | |
a343eb3c | 2525 | |
29639122 | 2526 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
2527 | THIS_FRAME. */ |
2528 | if (this_frame != NULL) | |
2529 | sp = get_frame_register_signed (this_frame, | |
2530 | gdbarch_num_regs (gdbarch) | |
2531 | + MIPS_SP_REGNUM); | |
29639122 JB |
2532 | else |
2533 | sp = 0; | |
eec63939 | 2534 | |
29639122 JB |
2535 | if (limit_pc > start_pc + 200) |
2536 | limit_pc = start_pc + 200; | |
ab50adb6 | 2537 | prev_pc = start_pc; |
eec63939 | 2538 | |
ab50adb6 MR |
2539 | /* Permit at most one non-prologue non-control-transfer instruction |
2540 | in the middle which may have been reordered by the compiler for | |
2541 | optimisation. */ | |
95ac2dcf | 2542 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) |
29639122 | 2543 | { |
ab50adb6 MR |
2544 | this_non_prologue_insn = 0; |
2545 | in_delay_slot = 0; | |
2546 | ||
29639122 JB |
2547 | /* Save the previous instruction. If it's an EXTEND, we'll extract |
2548 | the immediate offset extension from it in mips16_get_imm. */ | |
2549 | prev_inst = inst; | |
eec63939 | 2550 | |
025bb325 | 2551 | /* Fetch and decode the instruction. */ |
4cc0665f MR |
2552 | inst = (unsigned short) mips_fetch_instruction (gdbarch, ISA_MIPS16, |
2553 | cur_pc, NULL); | |
eec63939 | 2554 | |
29639122 JB |
2555 | /* Normally we ignore extend instructions. However, if it is |
2556 | not followed by a valid prologue instruction, then this | |
2557 | instruction is not part of the prologue either. We must | |
2558 | remember in this case to adjust the end_prologue_addr back | |
2559 | over the extend. */ | |
2560 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
2561 | { | |
95ac2dcf | 2562 | extend_bytes = MIPS_INSN16_SIZE; |
29639122 JB |
2563 | continue; |
2564 | } | |
eec63939 | 2565 | |
29639122 JB |
2566 | prev_extend_bytes = extend_bytes; |
2567 | extend_bytes = 0; | |
eec63939 | 2568 | |
29639122 JB |
2569 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
2570 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2571 | { | |
2572 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
025bb325 | 2573 | if (offset < 0) /* Negative stack adjustment? */ |
29639122 JB |
2574 | frame_offset -= offset; |
2575 | else | |
2576 | /* Exit loop if a positive stack adjustment is found, which | |
2577 | usually means that the stack cleanup code in the function | |
2578 | epilogue is reached. */ | |
2579 | break; | |
2580 | } | |
2581 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
2582 | { | |
2583 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
4cc0665f | 2584 | reg = mips_reg3_to_reg[(inst & 0x700) >> 8]; |
74ed0bb4 | 2585 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
2586 | } |
2587 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
2588 | { | |
2589 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
4cc0665f | 2590 | reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
74ed0bb4 | 2591 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
2592 | } |
2593 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
2594 | { | |
2595 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
74ed0bb4 | 2596 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
2597 | } |
2598 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
2599 | { | |
2600 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
74ed0bb4 | 2601 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
2602 | } |
2603 | else if (inst == 0x673d) /* move $s1, $sp */ | |
2604 | { | |
2605 | frame_addr = sp; | |
2606 | frame_reg = 17; | |
2607 | } | |
2608 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
2609 | { | |
2610 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2611 | frame_addr = sp + offset; | |
2612 | frame_reg = 17; | |
2613 | frame_adjust = offset; | |
2614 | } | |
2615 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
2616 | { | |
2617 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
4cc0665f | 2618 | reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
74ed0bb4 | 2619 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
2620 | } |
2621 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
2622 | { | |
2623 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
4cc0665f | 2624 | reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
74ed0bb4 | 2625 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
2626 | } |
2627 | else if ((inst & 0xf81f) == 0xe809 | |
2628 | && (inst & 0x700) != 0x700) /* entry */ | |
025bb325 | 2629 | entry_inst = inst; /* Save for later processing. */ |
2207132d MR |
2630 | else if ((inst & 0xff80) == 0x6480) /* save */ |
2631 | { | |
025bb325 | 2632 | save_inst = inst; /* Save for later processing. */ |
2207132d MR |
2633 | if (prev_extend_bytes) /* extend */ |
2634 | save_inst |= prev_inst << 16; | |
2635 | } | |
29639122 JB |
2636 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
2637 | { | |
2638 | /* This instruction is part of the prologue, but we don't | |
2639 | need to do anything special to handle it. */ | |
2640 | } | |
ab50adb6 MR |
2641 | else if (mips16_instruction_has_delay_slot (inst, 0)) |
2642 | /* JAL/JALR/JALX/JR */ | |
2643 | { | |
2644 | /* The instruction in the delay slot can be a part | |
2645 | of the prologue, so move forward once more. */ | |
2646 | in_delay_slot = 1; | |
2647 | if (mips16_instruction_has_delay_slot (inst, 1)) | |
2648 | /* JAL/JALX */ | |
2649 | { | |
2650 | prev_extend_bytes = MIPS_INSN16_SIZE; | |
2651 | cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ | |
2652 | } | |
2653 | } | |
29639122 JB |
2654 | else |
2655 | { | |
ab50adb6 | 2656 | this_non_prologue_insn = 1; |
29639122 | 2657 | } |
ab50adb6 MR |
2658 | |
2659 | non_prologue_insns += this_non_prologue_insn; | |
2660 | ||
2661 | /* A jump or branch, or enough non-prologue insns seen? If so, | |
2662 | then we must have reached the end of the prologue by now. */ | |
2663 | if (prev_delay_slot || non_prologue_insns > 1 | |
2664 | || mips16_instruction_is_compact_branch (inst)) | |
2665 | break; | |
2666 | ||
2667 | prev_non_prologue_insn = this_non_prologue_insn; | |
2668 | prev_delay_slot = in_delay_slot; | |
2669 | prev_pc = cur_pc - prev_extend_bytes; | |
29639122 | 2670 | } |
eec63939 | 2671 | |
29639122 JB |
2672 | /* The entry instruction is typically the first instruction in a function, |
2673 | and it stores registers at offsets relative to the value of the old SP | |
2674 | (before the prologue). But the value of the sp parameter to this | |
2675 | function is the new SP (after the prologue has been executed). So we | |
2676 | can't calculate those offsets until we've seen the entire prologue, | |
025bb325 | 2677 | and can calculate what the old SP must have been. */ |
29639122 JB |
2678 | if (entry_inst != 0) |
2679 | { | |
2680 | int areg_count = (entry_inst >> 8) & 7; | |
2681 | int sreg_count = (entry_inst >> 6) & 3; | |
eec63939 | 2682 | |
29639122 JB |
2683 | /* The entry instruction always subtracts 32 from the SP. */ |
2684 | frame_offset += 32; | |
2685 | ||
2686 | /* Now we can calculate what the SP must have been at the | |
2687 | start of the function prologue. */ | |
2688 | sp += frame_offset; | |
2689 | ||
2690 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
2691 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
2692 | { | |
74ed0bb4 | 2693 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 2694 | offset += mips_abi_regsize (gdbarch); |
29639122 JB |
2695 | } |
2696 | ||
2697 | /* Check if the ra register was pushed on the stack. */ | |
2698 | offset = -4; | |
2699 | if (entry_inst & 0x20) | |
2700 | { | |
74ed0bb4 | 2701 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
72a155b4 | 2702 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
2703 | } |
2704 | ||
2705 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
2706 | for (reg = 16; reg < sreg_count + 16; reg++) | |
2707 | { | |
74ed0bb4 | 2708 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 2709 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
2710 | } |
2711 | } | |
2712 | ||
2207132d MR |
2713 | /* The SAVE instruction is similar to ENTRY, except that defined by the |
2714 | MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the | |
2715 | size of the frame is specified as an immediate field of instruction | |
2716 | and an extended variation exists which lets additional registers and | |
2717 | frame space to be specified. The instruction always treats registers | |
2718 | as 32-bit so its usefulness for 64-bit ABIs is questionable. */ | |
2719 | if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4) | |
2720 | { | |
2721 | static int args_table[16] = { | |
2722 | 0, 0, 0, 0, 1, 1, 1, 1, | |
2723 | 2, 2, 2, 0, 3, 3, 4, -1, | |
2724 | }; | |
2725 | static int astatic_table[16] = { | |
2726 | 0, 1, 2, 3, 0, 1, 2, 3, | |
2727 | 0, 1, 2, 4, 0, 1, 0, -1, | |
2728 | }; | |
2729 | int aregs = (save_inst >> 16) & 0xf; | |
2730 | int xsregs = (save_inst >> 24) & 0x7; | |
2731 | int args = args_table[aregs]; | |
2732 | int astatic = astatic_table[aregs]; | |
2733 | long frame_size; | |
2734 | ||
2735 | if (args < 0) | |
2736 | { | |
2737 | warning (_("Invalid number of argument registers encoded in SAVE.")); | |
2738 | args = 0; | |
2739 | } | |
2740 | if (astatic < 0) | |
2741 | { | |
2742 | warning (_("Invalid number of static registers encoded in SAVE.")); | |
2743 | astatic = 0; | |
2744 | } | |
2745 | ||
2746 | /* For standard SAVE the frame size of 0 means 128. */ | |
2747 | frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf); | |
2748 | if (frame_size == 0 && (save_inst >> 16) == 0) | |
2749 | frame_size = 16; | |
2750 | frame_size *= 8; | |
2751 | frame_offset += frame_size; | |
2752 | ||
2753 | /* Now we can calculate what the SP must have been at the | |
2754 | start of the function prologue. */ | |
2755 | sp += frame_offset; | |
2756 | ||
2757 | /* Check if A0-A3 were saved in the caller's argument save area. */ | |
2758 | for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++) | |
2759 | { | |
74ed0bb4 | 2760 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
2761 | offset += mips_abi_regsize (gdbarch); |
2762 | } | |
2763 | ||
2764 | offset = -4; | |
2765 | ||
2766 | /* Check if the RA register was pushed on the stack. */ | |
2767 | if (save_inst & 0x40) | |
2768 | { | |
74ed0bb4 | 2769 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
2207132d MR |
2770 | offset -= mips_abi_regsize (gdbarch); |
2771 | } | |
2772 | ||
2773 | /* Check if the S8 register was pushed on the stack. */ | |
2774 | if (xsregs > 6) | |
2775 | { | |
74ed0bb4 | 2776 | set_reg_offset (gdbarch, this_cache, 30, sp + offset); |
2207132d MR |
2777 | offset -= mips_abi_regsize (gdbarch); |
2778 | xsregs--; | |
2779 | } | |
2780 | /* Check if S2-S7 were pushed on the stack. */ | |
2781 | for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--) | |
2782 | { | |
74ed0bb4 | 2783 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
2784 | offset -= mips_abi_regsize (gdbarch); |
2785 | } | |
2786 | ||
2787 | /* Check if the S1 register was pushed on the stack. */ | |
2788 | if (save_inst & 0x10) | |
2789 | { | |
74ed0bb4 | 2790 | set_reg_offset (gdbarch, this_cache, 17, sp + offset); |
2207132d MR |
2791 | offset -= mips_abi_regsize (gdbarch); |
2792 | } | |
2793 | /* Check if the S0 register was pushed on the stack. */ | |
2794 | if (save_inst & 0x20) | |
2795 | { | |
74ed0bb4 | 2796 | set_reg_offset (gdbarch, this_cache, 16, sp + offset); |
2207132d MR |
2797 | offset -= mips_abi_regsize (gdbarch); |
2798 | } | |
2799 | ||
4cc0665f MR |
2800 | /* Check if A0-A3 were pushed on the stack. */ |
2801 | for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--) | |
2802 | { | |
2803 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); | |
2804 | offset -= mips_abi_regsize (gdbarch); | |
2805 | } | |
2806 | } | |
2807 | ||
2808 | if (this_cache != NULL) | |
2809 | { | |
2810 | this_cache->base = | |
2811 | (get_frame_register_signed (this_frame, | |
2812 | gdbarch_num_regs (gdbarch) + frame_reg) | |
2813 | + frame_offset - frame_adjust); | |
2814 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should | |
2815 | be able to get rid of the assignment below, evetually. But it's | |
2816 | still needed for now. */ | |
2817 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) | |
2818 | + mips_regnum (gdbarch)->pc] | |
2819 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; | |
2820 | } | |
2821 | ||
ab50adb6 MR |
2822 | /* Set end_prologue_addr to the address of the instruction immediately |
2823 | after the last one we scanned. Unless the last one looked like a | |
2824 | non-prologue instruction (and we looked ahead), in which case use | |
2825 | its address instead. */ | |
2826 | end_prologue_addr = (prev_non_prologue_insn || prev_delay_slot | |
2827 | ? prev_pc : cur_pc - prev_extend_bytes); | |
4cc0665f MR |
2828 | |
2829 | return end_prologue_addr; | |
2830 | } | |
2831 | ||
2832 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). | |
2833 | Procedures that use the 32-bit instruction set are handled by the | |
2834 | mips_insn32 unwinder. */ | |
2835 | ||
2836 | static struct mips_frame_cache * | |
2837 | mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache) | |
2838 | { | |
2839 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2840 | struct mips_frame_cache *cache; | |
2841 | ||
2842 | if ((*this_cache) != NULL) | |
19ba03f4 | 2843 | return (struct mips_frame_cache *) (*this_cache); |
4cc0665f MR |
2844 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
2845 | (*this_cache) = cache; | |
2846 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
2847 | ||
2848 | /* Analyze the function prologue. */ | |
2849 | { | |
2850 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); | |
2851 | CORE_ADDR start_addr; | |
2852 | ||
2853 | find_pc_partial_function (pc, NULL, &start_addr, NULL); | |
2854 | if (start_addr == 0) | |
2855 | start_addr = heuristic_proc_start (gdbarch, pc); | |
2856 | /* We can't analyze the prologue if we couldn't find the begining | |
2857 | of the function. */ | |
2858 | if (start_addr == 0) | |
2859 | return cache; | |
2860 | ||
19ba03f4 SM |
2861 | mips16_scan_prologue (gdbarch, start_addr, pc, this_frame, |
2862 | (struct mips_frame_cache *) *this_cache); | |
4cc0665f MR |
2863 | } |
2864 | ||
2865 | /* gdbarch_sp_regnum contains the value and not the address. */ | |
2866 | trad_frame_set_value (cache->saved_regs, | |
2867 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, | |
2868 | cache->base); | |
2869 | ||
19ba03f4 | 2870 | return (struct mips_frame_cache *) (*this_cache); |
4cc0665f MR |
2871 | } |
2872 | ||
2873 | static void | |
2874 | mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache, | |
2875 | struct frame_id *this_id) | |
2876 | { | |
2877 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, | |
2878 | this_cache); | |
2879 | /* This marks the outermost frame. */ | |
2880 | if (info->base == 0) | |
2881 | return; | |
2882 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); | |
2883 | } | |
2884 | ||
2885 | static struct value * | |
2886 | mips_insn16_frame_prev_register (struct frame_info *this_frame, | |
2887 | void **this_cache, int regnum) | |
2888 | { | |
2889 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, | |
2890 | this_cache); | |
2891 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); | |
2892 | } | |
2893 | ||
2894 | static int | |
2895 | mips_insn16_frame_sniffer (const struct frame_unwind *self, | |
2896 | struct frame_info *this_frame, void **this_cache) | |
2897 | { | |
2898 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2899 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2900 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
2901 | return 1; | |
2902 | return 0; | |
2903 | } | |
2904 | ||
2905 | static const struct frame_unwind mips_insn16_frame_unwind = | |
2906 | { | |
2907 | NORMAL_FRAME, | |
2908 | default_frame_unwind_stop_reason, | |
2909 | mips_insn16_frame_this_id, | |
2910 | mips_insn16_frame_prev_register, | |
2911 | NULL, | |
2912 | mips_insn16_frame_sniffer | |
2913 | }; | |
2914 | ||
2915 | static CORE_ADDR | |
2916 | mips_insn16_frame_base_address (struct frame_info *this_frame, | |
2917 | void **this_cache) | |
2918 | { | |
2919 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, | |
2920 | this_cache); | |
2921 | return info->base; | |
2922 | } | |
2923 | ||
2924 | static const struct frame_base mips_insn16_frame_base = | |
2925 | { | |
2926 | &mips_insn16_frame_unwind, | |
2927 | mips_insn16_frame_base_address, | |
2928 | mips_insn16_frame_base_address, | |
2929 | mips_insn16_frame_base_address | |
2930 | }; | |
2931 | ||
2932 | static const struct frame_base * | |
2933 | mips_insn16_frame_base_sniffer (struct frame_info *this_frame) | |
2934 | { | |
2935 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2936 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2937 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
2938 | return &mips_insn16_frame_base; | |
2939 | else | |
2940 | return NULL; | |
2941 | } | |
2942 | ||
2943 | /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped | |
2944 | to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are | |
2945 | interpreted directly, and then multiplied by 4. */ | |
2946 | ||
2947 | static int | |
2948 | micromips_decode_imm9 (int imm) | |
2949 | { | |
2950 | imm = (imm ^ 0x100) - 0x100; | |
2951 | if (imm > -3 && imm < 2) | |
2952 | imm ^= 0x100; | |
2953 | return imm << 2; | |
2954 | } | |
2955 | ||
2956 | /* Analyze the function prologue from START_PC to LIMIT_PC. Return | |
2957 | the address of the first instruction past the prologue. */ | |
2958 | ||
2959 | static CORE_ADDR | |
2960 | micromips_scan_prologue (struct gdbarch *gdbarch, | |
2961 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
2962 | struct frame_info *this_frame, | |
2963 | struct mips_frame_cache *this_cache) | |
2964 | { | |
ab50adb6 | 2965 | CORE_ADDR end_prologue_addr; |
4cc0665f MR |
2966 | int prev_non_prologue_insn = 0; |
2967 | int frame_reg = MIPS_SP_REGNUM; | |
2968 | int this_non_prologue_insn; | |
2969 | int non_prologue_insns = 0; | |
2970 | long frame_offset = 0; /* Size of stack frame. */ | |
2971 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
ab50adb6 MR |
2972 | int prev_delay_slot = 0; |
2973 | int in_delay_slot; | |
4cc0665f MR |
2974 | CORE_ADDR prev_pc; |
2975 | CORE_ADDR cur_pc; | |
2976 | ULONGEST insn; /* current instruction */ | |
2977 | CORE_ADDR sp; | |
2978 | long offset; | |
2979 | long sp_adj; | |
2980 | long v1_off = 0; /* The assumption is LUI will replace it. */ | |
2981 | int reglist; | |
2982 | int breg; | |
2983 | int dreg; | |
2984 | int sreg; | |
2985 | int treg; | |
2986 | int loc; | |
2987 | int op; | |
2988 | int s; | |
2989 | int i; | |
2990 | ||
2991 | /* Can be called when there's no process, and hence when there's no | |
2992 | THIS_FRAME. */ | |
2993 | if (this_frame != NULL) | |
2994 | sp = get_frame_register_signed (this_frame, | |
2995 | gdbarch_num_regs (gdbarch) | |
2996 | + MIPS_SP_REGNUM); | |
2997 | else | |
2998 | sp = 0; | |
2999 | ||
3000 | if (limit_pc > start_pc + 200) | |
3001 | limit_pc = start_pc + 200; | |
3002 | prev_pc = start_pc; | |
3003 | ||
3004 | /* Permit at most one non-prologue non-control-transfer instruction | |
3005 | in the middle which may have been reordered by the compiler for | |
3006 | optimisation. */ | |
3007 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += loc) | |
3008 | { | |
3009 | this_non_prologue_insn = 0; | |
ab50adb6 | 3010 | in_delay_slot = 0; |
4cc0665f MR |
3011 | sp_adj = 0; |
3012 | loc = 0; | |
3013 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, cur_pc, NULL); | |
3014 | loc += MIPS_INSN16_SIZE; | |
3015 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
3016 | { | |
4cc0665f MR |
3017 | /* 32-bit instructions. */ |
3018 | case 2 * MIPS_INSN16_SIZE: | |
3019 | insn <<= 16; | |
3020 | insn |= mips_fetch_instruction (gdbarch, | |
3021 | ISA_MICROMIPS, cur_pc + loc, NULL); | |
3022 | loc += MIPS_INSN16_SIZE; | |
3023 | switch (micromips_op (insn >> 16)) | |
3024 | { | |
3025 | /* Record $sp/$fp adjustment. */ | |
3026 | /* Discard (D)ADDU $gp,$jp used for PIC code. */ | |
3027 | case 0x0: /* POOL32A: bits 000000 */ | |
3028 | case 0x16: /* POOL32S: bits 010110 */ | |
3029 | op = b0s11_op (insn); | |
3030 | sreg = b0s5_reg (insn >> 16); | |
3031 | treg = b5s5_reg (insn >> 16); | |
3032 | dreg = b11s5_reg (insn); | |
3033 | if (op == 0x1d0 | |
3034 | /* SUBU: bits 000000 00111010000 */ | |
3035 | /* DSUBU: bits 010110 00111010000 */ | |
3036 | && dreg == MIPS_SP_REGNUM && sreg == MIPS_SP_REGNUM | |
3037 | && treg == 3) | |
3038 | /* (D)SUBU $sp, $v1 */ | |
3039 | sp_adj = v1_off; | |
3040 | else if (op != 0x150 | |
3041 | /* ADDU: bits 000000 00101010000 */ | |
3042 | /* DADDU: bits 010110 00101010000 */ | |
3043 | || dreg != 28 || sreg != 28 || treg != MIPS_T9_REGNUM) | |
3044 | this_non_prologue_insn = 1; | |
3045 | break; | |
3046 | ||
3047 | case 0x8: /* POOL32B: bits 001000 */ | |
3048 | op = b12s4_op (insn); | |
3049 | breg = b0s5_reg (insn >> 16); | |
3050 | reglist = sreg = b5s5_reg (insn >> 16); | |
3051 | offset = (b0s12_imm (insn) ^ 0x800) - 0x800; | |
3052 | if ((op == 0x9 || op == 0xc) | |
3053 | /* SWP: bits 001000 1001 */ | |
3054 | /* SDP: bits 001000 1100 */ | |
3055 | && breg == MIPS_SP_REGNUM && sreg < MIPS_RA_REGNUM) | |
3056 | /* S[DW]P reg,offset($sp) */ | |
3057 | { | |
3058 | s = 4 << ((b12s4_op (insn) & 0x4) == 0x4); | |
3059 | set_reg_offset (gdbarch, this_cache, | |
3060 | sreg, sp + offset); | |
3061 | set_reg_offset (gdbarch, this_cache, | |
3062 | sreg + 1, sp + offset + s); | |
3063 | } | |
3064 | else if ((op == 0xd || op == 0xf) | |
3065 | /* SWM: bits 001000 1101 */ | |
3066 | /* SDM: bits 001000 1111 */ | |
3067 | && breg == MIPS_SP_REGNUM | |
3068 | /* SWM reglist,offset($sp) */ | |
3069 | && ((reglist >= 1 && reglist <= 9) | |
3070 | || (reglist >= 16 && reglist <= 25))) | |
3071 | { | |
325fac50 | 3072 | int sreglist = std::min(reglist & 0xf, 8); |
4cc0665f MR |
3073 | |
3074 | s = 4 << ((b12s4_op (insn) & 0x2) == 0x2); | |
3075 | for (i = 0; i < sreglist; i++) | |
3076 | set_reg_offset (gdbarch, this_cache, 16 + i, sp + s * i); | |
3077 | if ((reglist & 0xf) > 8) | |
3078 | set_reg_offset (gdbarch, this_cache, 30, sp + s * i++); | |
3079 | if ((reglist & 0x10) == 0x10) | |
3080 | set_reg_offset (gdbarch, this_cache, | |
3081 | MIPS_RA_REGNUM, sp + s * i++); | |
3082 | } | |
3083 | else | |
3084 | this_non_prologue_insn = 1; | |
3085 | break; | |
3086 | ||
3087 | /* Record $sp/$fp adjustment. */ | |
3088 | /* Discard (D)ADDIU $gp used for PIC code. */ | |
3089 | case 0xc: /* ADDIU: bits 001100 */ | |
3090 | case 0x17: /* DADDIU: bits 010111 */ | |
3091 | sreg = b0s5_reg (insn >> 16); | |
3092 | dreg = b5s5_reg (insn >> 16); | |
3093 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
3094 | if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM) | |
3095 | /* (D)ADDIU $sp, imm */ | |
3096 | sp_adj = offset; | |
3097 | else if (sreg == MIPS_SP_REGNUM && dreg == 30) | |
3098 | /* (D)ADDIU $fp, $sp, imm */ | |
3099 | { | |
4cc0665f MR |
3100 | frame_adjust = offset; |
3101 | frame_reg = 30; | |
3102 | } | |
3103 | else if (sreg != 28 || dreg != 28) | |
3104 | /* (D)ADDIU $gp, imm */ | |
3105 | this_non_prologue_insn = 1; | |
3106 | break; | |
3107 | ||
3108 | /* LUI $v1 is used for larger $sp adjustments. */ | |
3356937a | 3109 | /* Discard LUI $gp used for PIC code. */ |
4cc0665f MR |
3110 | case 0x10: /* POOL32I: bits 010000 */ |
3111 | if (b5s5_op (insn >> 16) == 0xd | |
3112 | /* LUI: bits 010000 001101 */ | |
3113 | && b0s5_reg (insn >> 16) == 3) | |
3114 | /* LUI $v1, imm */ | |
3115 | v1_off = ((b0s16_imm (insn) << 16) ^ 0x80000000) - 0x80000000; | |
3116 | else if (b5s5_op (insn >> 16) != 0xd | |
3117 | /* LUI: bits 010000 001101 */ | |
3118 | || b0s5_reg (insn >> 16) != 28) | |
3119 | /* LUI $gp, imm */ | |
3120 | this_non_prologue_insn = 1; | |
3121 | break; | |
3122 | ||
3123 | /* ORI $v1 is used for larger $sp adjustments. */ | |
3124 | case 0x14: /* ORI: bits 010100 */ | |
3125 | sreg = b0s5_reg (insn >> 16); | |
3126 | dreg = b5s5_reg (insn >> 16); | |
3127 | if (sreg == 3 && dreg == 3) | |
3128 | /* ORI $v1, imm */ | |
3129 | v1_off |= b0s16_imm (insn); | |
3130 | else | |
3131 | this_non_prologue_insn = 1; | |
3132 | break; | |
3133 | ||
3134 | case 0x26: /* SWC1: bits 100110 */ | |
3135 | case 0x2e: /* SDC1: bits 101110 */ | |
3136 | breg = b0s5_reg (insn >> 16); | |
3137 | if (breg != MIPS_SP_REGNUM) | |
3138 | /* S[DW]C1 reg,offset($sp) */ | |
3139 | this_non_prologue_insn = 1; | |
3140 | break; | |
3141 | ||
3142 | case 0x36: /* SD: bits 110110 */ | |
3143 | case 0x3e: /* SW: bits 111110 */ | |
3144 | breg = b0s5_reg (insn >> 16); | |
3145 | sreg = b5s5_reg (insn >> 16); | |
3146 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
3147 | if (breg == MIPS_SP_REGNUM) | |
3148 | /* S[DW] reg,offset($sp) */ | |
3149 | set_reg_offset (gdbarch, this_cache, sreg, sp + offset); | |
3150 | else | |
3151 | this_non_prologue_insn = 1; | |
3152 | break; | |
3153 | ||
3154 | default: | |
ab50adb6 MR |
3155 | /* The instruction in the delay slot can be a part |
3156 | of the prologue, so move forward once more. */ | |
3157 | if (micromips_instruction_has_delay_slot (insn, 0)) | |
3158 | in_delay_slot = 1; | |
3159 | else | |
3160 | this_non_prologue_insn = 1; | |
4cc0665f MR |
3161 | break; |
3162 | } | |
ab50adb6 | 3163 | insn >>= 16; |
4cc0665f MR |
3164 | break; |
3165 | ||
3166 | /* 16-bit instructions. */ | |
3167 | case MIPS_INSN16_SIZE: | |
3168 | switch (micromips_op (insn)) | |
3169 | { | |
3170 | case 0x3: /* MOVE: bits 000011 */ | |
3171 | sreg = b0s5_reg (insn); | |
3172 | dreg = b5s5_reg (insn); | |
3173 | if (sreg == MIPS_SP_REGNUM && dreg == 30) | |
3174 | /* MOVE $fp, $sp */ | |
78cc6c2d | 3175 | frame_reg = 30; |
4cc0665f MR |
3176 | else if ((sreg & 0x1c) != 0x4) |
3177 | /* MOVE reg, $a0-$a3 */ | |
3178 | this_non_prologue_insn = 1; | |
3179 | break; | |
3180 | ||
3181 | case 0x11: /* POOL16C: bits 010001 */ | |
3182 | if (b6s4_op (insn) == 0x5) | |
3183 | /* SWM: bits 010001 0101 */ | |
3184 | { | |
3185 | offset = ((b0s4_imm (insn) << 2) ^ 0x20) - 0x20; | |
3186 | reglist = b4s2_regl (insn); | |
3187 | for (i = 0; i <= reglist; i++) | |
3188 | set_reg_offset (gdbarch, this_cache, 16 + i, sp + 4 * i); | |
3189 | set_reg_offset (gdbarch, this_cache, | |
3190 | MIPS_RA_REGNUM, sp + 4 * i++); | |
3191 | } | |
3192 | else | |
3193 | this_non_prologue_insn = 1; | |
3194 | break; | |
3195 | ||
3196 | case 0x13: /* POOL16D: bits 010011 */ | |
3197 | if ((insn & 0x1) == 0x1) | |
3198 | /* ADDIUSP: bits 010011 1 */ | |
3199 | sp_adj = micromips_decode_imm9 (b1s9_imm (insn)); | |
3200 | else if (b5s5_reg (insn) == MIPS_SP_REGNUM) | |
3201 | /* ADDIUS5: bits 010011 0 */ | |
3202 | /* ADDIUS5 $sp, imm */ | |
3203 | sp_adj = (b1s4_imm (insn) ^ 8) - 8; | |
3204 | else | |
3205 | this_non_prologue_insn = 1; | |
3206 | break; | |
3207 | ||
3208 | case 0x32: /* SWSP: bits 110010 */ | |
3209 | offset = b0s5_imm (insn) << 2; | |
3210 | sreg = b5s5_reg (insn); | |
3211 | set_reg_offset (gdbarch, this_cache, sreg, sp + offset); | |
3212 | break; | |
3213 | ||
3214 | default: | |
ab50adb6 MR |
3215 | /* The instruction in the delay slot can be a part |
3216 | of the prologue, so move forward once more. */ | |
3217 | if (micromips_instruction_has_delay_slot (insn << 16, 0)) | |
3218 | in_delay_slot = 1; | |
3219 | else | |
3220 | this_non_prologue_insn = 1; | |
4cc0665f MR |
3221 | break; |
3222 | } | |
3223 | break; | |
3224 | } | |
3225 | if (sp_adj < 0) | |
3226 | frame_offset -= sp_adj; | |
3227 | ||
3228 | non_prologue_insns += this_non_prologue_insn; | |
ab50adb6 MR |
3229 | |
3230 | /* A jump or branch, enough non-prologue insns seen or positive | |
3231 | stack adjustment? If so, then we must have reached the end | |
3232 | of the prologue by now. */ | |
3233 | if (prev_delay_slot || non_prologue_insns > 1 || sp_adj > 0 | |
3234 | || micromips_instruction_is_compact_branch (insn)) | |
3235 | break; | |
3236 | ||
4cc0665f | 3237 | prev_non_prologue_insn = this_non_prologue_insn; |
ab50adb6 | 3238 | prev_delay_slot = in_delay_slot; |
4cc0665f | 3239 | prev_pc = cur_pc; |
2207132d MR |
3240 | } |
3241 | ||
29639122 JB |
3242 | if (this_cache != NULL) |
3243 | { | |
3244 | this_cache->base = | |
4cc0665f | 3245 | (get_frame_register_signed (this_frame, |
b8a22b94 | 3246 | gdbarch_num_regs (gdbarch) + frame_reg) |
4cc0665f | 3247 | + frame_offset - frame_adjust); |
29639122 | 3248 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should |
4cc0665f MR |
3249 | be able to get rid of the assignment below, evetually. But it's |
3250 | still needed for now. */ | |
72a155b4 UW |
3251 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
3252 | + mips_regnum (gdbarch)->pc] | |
4cc0665f | 3253 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; |
29639122 JB |
3254 | } |
3255 | ||
ab50adb6 MR |
3256 | /* Set end_prologue_addr to the address of the instruction immediately |
3257 | after the last one we scanned. Unless the last one looked like a | |
3258 | non-prologue instruction (and we looked ahead), in which case use | |
3259 | its address instead. */ | |
3260 | end_prologue_addr | |
3261 | = prev_non_prologue_insn || prev_delay_slot ? prev_pc : cur_pc; | |
29639122 JB |
3262 | |
3263 | return end_prologue_addr; | |
eec63939 AC |
3264 | } |
3265 | ||
4cc0665f | 3266 | /* Heuristic unwinder for procedures using microMIPS instructions. |
29639122 | 3267 | Procedures that use the 32-bit instruction set are handled by the |
4cc0665f | 3268 | mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */ |
29639122 JB |
3269 | |
3270 | static struct mips_frame_cache * | |
4cc0665f | 3271 | mips_micro_frame_cache (struct frame_info *this_frame, void **this_cache) |
eec63939 | 3272 | { |
e17a4113 | 3273 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 3274 | struct mips_frame_cache *cache; |
eec63939 AC |
3275 | |
3276 | if ((*this_cache) != NULL) | |
19ba03f4 | 3277 | return (struct mips_frame_cache *) (*this_cache); |
4cc0665f | 3278 | |
29639122 JB |
3279 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
3280 | (*this_cache) = cache; | |
b8a22b94 | 3281 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
eec63939 | 3282 | |
29639122 JB |
3283 | /* Analyze the function prologue. */ |
3284 | { | |
b8a22b94 | 3285 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 3286 | CORE_ADDR start_addr; |
eec63939 | 3287 | |
29639122 JB |
3288 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
3289 | if (start_addr == 0) | |
4cc0665f | 3290 | start_addr = heuristic_proc_start (get_frame_arch (this_frame), pc); |
29639122 JB |
3291 | /* We can't analyze the prologue if we couldn't find the begining |
3292 | of the function. */ | |
3293 | if (start_addr == 0) | |
3294 | return cache; | |
eec63939 | 3295 | |
19ba03f4 SM |
3296 | micromips_scan_prologue (gdbarch, start_addr, pc, this_frame, |
3297 | (struct mips_frame_cache *) *this_cache); | |
29639122 | 3298 | } |
4cc0665f | 3299 | |
3e8c568d | 3300 | /* gdbarch_sp_regnum contains the value and not the address. */ |
72a155b4 | 3301 | trad_frame_set_value (cache->saved_regs, |
e17a4113 | 3302 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
72a155b4 | 3303 | cache->base); |
eec63939 | 3304 | |
19ba03f4 | 3305 | return (struct mips_frame_cache *) (*this_cache); |
eec63939 AC |
3306 | } |
3307 | ||
3308 | static void | |
4cc0665f MR |
3309 | mips_micro_frame_this_id (struct frame_info *this_frame, void **this_cache, |
3310 | struct frame_id *this_id) | |
eec63939 | 3311 | { |
4cc0665f MR |
3312 | struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
3313 | this_cache); | |
21327321 DJ |
3314 | /* This marks the outermost frame. */ |
3315 | if (info->base == 0) | |
3316 | return; | |
b8a22b94 | 3317 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
eec63939 AC |
3318 | } |
3319 | ||
b8a22b94 | 3320 | static struct value * |
4cc0665f MR |
3321 | mips_micro_frame_prev_register (struct frame_info *this_frame, |
3322 | void **this_cache, int regnum) | |
eec63939 | 3323 | { |
4cc0665f MR |
3324 | struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
3325 | this_cache); | |
b8a22b94 DJ |
3326 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
3327 | } | |
3328 | ||
3329 | static int | |
4cc0665f MR |
3330 | mips_micro_frame_sniffer (const struct frame_unwind *self, |
3331 | struct frame_info *this_frame, void **this_cache) | |
b8a22b94 | 3332 | { |
4cc0665f | 3333 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
b8a22b94 | 3334 | CORE_ADDR pc = get_frame_pc (this_frame); |
4cc0665f MR |
3335 | |
3336 | if (mips_pc_is_micromips (gdbarch, pc)) | |
b8a22b94 DJ |
3337 | return 1; |
3338 | return 0; | |
eec63939 AC |
3339 | } |
3340 | ||
4cc0665f | 3341 | static const struct frame_unwind mips_micro_frame_unwind = |
eec63939 AC |
3342 | { |
3343 | NORMAL_FRAME, | |
8fbca658 | 3344 | default_frame_unwind_stop_reason, |
4cc0665f MR |
3345 | mips_micro_frame_this_id, |
3346 | mips_micro_frame_prev_register, | |
b8a22b94 | 3347 | NULL, |
4cc0665f | 3348 | mips_micro_frame_sniffer |
eec63939 AC |
3349 | }; |
3350 | ||
eec63939 | 3351 | static CORE_ADDR |
4cc0665f MR |
3352 | mips_micro_frame_base_address (struct frame_info *this_frame, |
3353 | void **this_cache) | |
eec63939 | 3354 | { |
4cc0665f MR |
3355 | struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
3356 | this_cache); | |
29639122 | 3357 | return info->base; |
eec63939 AC |
3358 | } |
3359 | ||
4cc0665f | 3360 | static const struct frame_base mips_micro_frame_base = |
eec63939 | 3361 | { |
4cc0665f MR |
3362 | &mips_micro_frame_unwind, |
3363 | mips_micro_frame_base_address, | |
3364 | mips_micro_frame_base_address, | |
3365 | mips_micro_frame_base_address | |
eec63939 AC |
3366 | }; |
3367 | ||
3368 | static const struct frame_base * | |
4cc0665f | 3369 | mips_micro_frame_base_sniffer (struct frame_info *this_frame) |
eec63939 | 3370 | { |
4cc0665f | 3371 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
b8a22b94 | 3372 | CORE_ADDR pc = get_frame_pc (this_frame); |
4cc0665f MR |
3373 | |
3374 | if (mips_pc_is_micromips (gdbarch, pc)) | |
3375 | return &mips_micro_frame_base; | |
eec63939 AC |
3376 | else |
3377 | return NULL; | |
edfae063 AC |
3378 | } |
3379 | ||
29639122 JB |
3380 | /* Mark all the registers as unset in the saved_regs array |
3381 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
3382 | ||
74ed0bb4 MD |
3383 | static void |
3384 | reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache) | |
c906108c | 3385 | { |
29639122 JB |
3386 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
3387 | return; | |
3388 | ||
3389 | { | |
74ed0bb4 | 3390 | const int num_regs = gdbarch_num_regs (gdbarch); |
29639122 | 3391 | int i; |
64159455 | 3392 | |
29639122 JB |
3393 | for (i = 0; i < num_regs; i++) |
3394 | { | |
3395 | this_cache->saved_regs[i].addr = -1; | |
3396 | } | |
3397 | } | |
c906108c SS |
3398 | } |
3399 | ||
025bb325 | 3400 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
29639122 JB |
3401 | the associated FRAME_CACHE if not null. |
3402 | Return the address of the first instruction past the prologue. */ | |
c906108c | 3403 | |
875e1767 | 3404 | static CORE_ADDR |
e17a4113 UW |
3405 | mips32_scan_prologue (struct gdbarch *gdbarch, |
3406 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 3407 | struct frame_info *this_frame, |
29639122 | 3408 | struct mips_frame_cache *this_cache) |
c906108c | 3409 | { |
ab50adb6 MR |
3410 | int prev_non_prologue_insn; |
3411 | int this_non_prologue_insn; | |
3412 | int non_prologue_insns; | |
025bb325 MS |
3413 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for |
3414 | frame-pointer. */ | |
ab50adb6 MR |
3415 | int prev_delay_slot; |
3416 | CORE_ADDR prev_pc; | |
3417 | CORE_ADDR cur_pc; | |
29639122 JB |
3418 | CORE_ADDR sp; |
3419 | long frame_offset; | |
3420 | int frame_reg = MIPS_SP_REGNUM; | |
8fa9cfa1 | 3421 | |
ab50adb6 | 3422 | CORE_ADDR end_prologue_addr; |
29639122 JB |
3423 | int seen_sp_adjust = 0; |
3424 | int load_immediate_bytes = 0; | |
ab50adb6 | 3425 | int in_delay_slot; |
7d1e6fb8 | 3426 | int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8); |
8fa9cfa1 | 3427 | |
29639122 | 3428 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
3429 | THIS_FRAME. */ |
3430 | if (this_frame != NULL) | |
3431 | sp = get_frame_register_signed (this_frame, | |
3432 | gdbarch_num_regs (gdbarch) | |
3433 | + MIPS_SP_REGNUM); | |
8fa9cfa1 | 3434 | else |
29639122 | 3435 | sp = 0; |
9022177c | 3436 | |
29639122 JB |
3437 | if (limit_pc > start_pc + 200) |
3438 | limit_pc = start_pc + 200; | |
9022177c | 3439 | |
29639122 | 3440 | restart: |
ab50adb6 MR |
3441 | prev_non_prologue_insn = 0; |
3442 | non_prologue_insns = 0; | |
3443 | prev_delay_slot = 0; | |
3444 | prev_pc = start_pc; | |
9022177c | 3445 | |
ab50adb6 MR |
3446 | /* Permit at most one non-prologue non-control-transfer instruction |
3447 | in the middle which may have been reordered by the compiler for | |
3448 | optimisation. */ | |
29639122 | 3449 | frame_offset = 0; |
95ac2dcf | 3450 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) |
9022177c | 3451 | { |
eaa6a9a4 MR |
3452 | unsigned long inst, high_word; |
3453 | long offset; | |
29639122 | 3454 | int reg; |
9022177c | 3455 | |
ab50adb6 MR |
3456 | this_non_prologue_insn = 0; |
3457 | in_delay_slot = 0; | |
3458 | ||
025bb325 | 3459 | /* Fetch the instruction. */ |
4cc0665f MR |
3460 | inst = (unsigned long) mips_fetch_instruction (gdbarch, ISA_MIPS, |
3461 | cur_pc, NULL); | |
9022177c | 3462 | |
29639122 JB |
3463 | /* Save some code by pre-extracting some useful fields. */ |
3464 | high_word = (inst >> 16) & 0xffff; | |
eaa6a9a4 | 3465 | offset = ((inst & 0xffff) ^ 0x8000) - 0x8000; |
29639122 | 3466 | reg = high_word & 0x1f; |
fe29b929 | 3467 | |
025bb325 | 3468 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
29639122 JB |
3469 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
3470 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
3471 | { | |
eaa6a9a4 MR |
3472 | if (offset < 0) /* Negative stack adjustment? */ |
3473 | frame_offset -= offset; | |
29639122 JB |
3474 | else |
3475 | /* Exit loop if a positive stack adjustment is found, which | |
3476 | usually means that the stack cleanup code in the function | |
3477 | epilogue is reached. */ | |
3478 | break; | |
3479 | seen_sp_adjust = 1; | |
3480 | } | |
7d1e6fb8 KB |
3481 | else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ |
3482 | && !regsize_is_64_bits) | |
29639122 | 3483 | { |
eaa6a9a4 | 3484 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 | 3485 | } |
7d1e6fb8 KB |
3486 | else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ |
3487 | && regsize_is_64_bits) | |
29639122 JB |
3488 | { |
3489 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ | |
eaa6a9a4 | 3490 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
3491 | } |
3492 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
3493 | { | |
3494 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
eaa6a9a4 MR |
3495 | if (offset != frame_offset) |
3496 | frame_addr = sp + offset; | |
b8a22b94 | 3497 | else if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
3498 | { |
3499 | unsigned alloca_adjust; | |
a4b8ebc8 | 3500 | |
29639122 | 3501 | frame_reg = 30; |
b8a22b94 DJ |
3502 | frame_addr = get_frame_register_signed |
3503 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
ca9c94ef | 3504 | frame_offset = 0; |
d2ca4222 | 3505 | |
eaa6a9a4 | 3506 | alloca_adjust = (unsigned) (frame_addr - (sp + offset)); |
29639122 JB |
3507 | if (alloca_adjust > 0) |
3508 | { | |
025bb325 | 3509 | /* FP > SP + frame_size. This may be because of |
29639122 JB |
3510 | an alloca or somethings similar. Fix sp to |
3511 | "pre-alloca" value, and try again. */ | |
3512 | sp += alloca_adjust; | |
3513 | /* Need to reset the status of all registers. Otherwise, | |
3514 | we will hit a guard that prevents the new address | |
3515 | for each register to be recomputed during the second | |
3516 | pass. */ | |
74ed0bb4 | 3517 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
3518 | goto restart; |
3519 | } | |
3520 | } | |
3521 | } | |
3522 | /* move $30,$sp. With different versions of gas this will be either | |
3523 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
3524 | Accept any one of these. */ | |
3525 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
3526 | { | |
3527 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
b8a22b94 | 3528 | if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
3529 | { |
3530 | unsigned alloca_adjust; | |
c906108c | 3531 | |
29639122 | 3532 | frame_reg = 30; |
b8a22b94 DJ |
3533 | frame_addr = get_frame_register_signed |
3534 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 3535 | |
29639122 JB |
3536 | alloca_adjust = (unsigned) (frame_addr - sp); |
3537 | if (alloca_adjust > 0) | |
3538 | { | |
025bb325 | 3539 | /* FP > SP + frame_size. This may be because of |
29639122 JB |
3540 | an alloca or somethings similar. Fix sp to |
3541 | "pre-alloca" value, and try again. */ | |
3542 | sp = frame_addr; | |
3543 | /* Need to reset the status of all registers. Otherwise, | |
3544 | we will hit a guard that prevents the new address | |
3545 | for each register to be recomputed during the second | |
3546 | pass. */ | |
74ed0bb4 | 3547 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
3548 | goto restart; |
3549 | } | |
3550 | } | |
3551 | } | |
7d1e6fb8 KB |
3552 | else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */ |
3553 | && !regsize_is_64_bits) | |
29639122 | 3554 | { |
eaa6a9a4 | 3555 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
3556 | } |
3557 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | |
3558 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ | |
3559 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | |
3560 | || high_word == 0x3c1c /* lui $gp,n */ | |
3561 | || high_word == 0x279c /* addiu $gp,$gp,n */ | |
3562 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
3563 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | |
3564 | ) | |
19080931 MR |
3565 | { |
3566 | /* These instructions are part of the prologue, but we don't | |
3567 | need to do anything special to handle them. */ | |
3568 | } | |
29639122 JB |
3569 | /* The instructions below load $at or $t0 with an immediate |
3570 | value in preparation for a stack adjustment via | |
025bb325 | 3571 | subu $sp,$sp,[$at,$t0]. These instructions could also |
29639122 JB |
3572 | initialize a local variable, so we accept them only before |
3573 | a stack adjustment instruction was seen. */ | |
3574 | else if (!seen_sp_adjust | |
ab50adb6 | 3575 | && !prev_delay_slot |
19080931 MR |
3576 | && (high_word == 0x3c01 /* lui $at,n */ |
3577 | || high_word == 0x3c08 /* lui $t0,n */ | |
3578 | || high_word == 0x3421 /* ori $at,$at,n */ | |
3579 | || high_word == 0x3508 /* ori $t0,$t0,n */ | |
3580 | || high_word == 0x3401 /* ori $at,$zero,n */ | |
3581 | || high_word == 0x3408 /* ori $t0,$zero,n */ | |
3582 | )) | |
3583 | { | |
ab50adb6 | 3584 | load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ |
19080931 | 3585 | } |
ab50adb6 MR |
3586 | /* Check for branches and jumps. The instruction in the delay |
3587 | slot can be a part of the prologue, so move forward once more. */ | |
3588 | else if (mips32_instruction_has_delay_slot (gdbarch, inst)) | |
3589 | { | |
3590 | in_delay_slot = 1; | |
3591 | } | |
3592 | /* This instruction is not an instruction typically found | |
3593 | in a prologue, so we must have reached the end of the | |
3594 | prologue. */ | |
29639122 | 3595 | else |
19080931 | 3596 | { |
ab50adb6 | 3597 | this_non_prologue_insn = 1; |
19080931 | 3598 | } |
db5f024e | 3599 | |
ab50adb6 MR |
3600 | non_prologue_insns += this_non_prologue_insn; |
3601 | ||
3602 | /* A jump or branch, or enough non-prologue insns seen? If so, | |
3603 | then we must have reached the end of the prologue by now. */ | |
3604 | if (prev_delay_slot || non_prologue_insns > 1) | |
db5f024e | 3605 | break; |
ab50adb6 MR |
3606 | |
3607 | prev_non_prologue_insn = this_non_prologue_insn; | |
3608 | prev_delay_slot = in_delay_slot; | |
3609 | prev_pc = cur_pc; | |
a4b8ebc8 | 3610 | } |
c906108c | 3611 | |
29639122 JB |
3612 | if (this_cache != NULL) |
3613 | { | |
3614 | this_cache->base = | |
b8a22b94 DJ |
3615 | (get_frame_register_signed (this_frame, |
3616 | gdbarch_num_regs (gdbarch) + frame_reg) | |
29639122 JB |
3617 | + frame_offset); |
3618 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of | |
3619 | this assignment below, eventually. But it's still needed | |
3620 | for now. */ | |
72a155b4 UW |
3621 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
3622 | + mips_regnum (gdbarch)->pc] | |
3623 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) | |
f57d151a | 3624 | + MIPS_RA_REGNUM]; |
29639122 | 3625 | } |
c906108c | 3626 | |
ab50adb6 MR |
3627 | /* Set end_prologue_addr to the address of the instruction immediately |
3628 | after the last one we scanned. Unless the last one looked like a | |
3629 | non-prologue instruction (and we looked ahead), in which case use | |
3630 | its address instead. */ | |
3631 | end_prologue_addr | |
3632 | = prev_non_prologue_insn || prev_delay_slot ? prev_pc : cur_pc; | |
29639122 JB |
3633 | |
3634 | /* In a frameless function, we might have incorrectly | |
025bb325 | 3635 | skipped some load immediate instructions. Undo the skipping |
29639122 JB |
3636 | if the load immediate was not followed by a stack adjustment. */ |
3637 | if (load_immediate_bytes && !seen_sp_adjust) | |
3638 | end_prologue_addr -= load_immediate_bytes; | |
c906108c | 3639 | |
29639122 | 3640 | return end_prologue_addr; |
c906108c SS |
3641 | } |
3642 | ||
29639122 JB |
3643 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
3644 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
3645 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
4cc0665f | 3646 | unwinder. Likewise microMIPS and the mips_micro unwinder. */ |
c906108c | 3647 | |
29639122 | 3648 | static struct mips_frame_cache * |
b8a22b94 | 3649 | mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache) |
c906108c | 3650 | { |
e17a4113 | 3651 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 3652 | struct mips_frame_cache *cache; |
c906108c | 3653 | |
29639122 | 3654 | if ((*this_cache) != NULL) |
19ba03f4 | 3655 | return (struct mips_frame_cache *) (*this_cache); |
c5aa993b | 3656 | |
29639122 JB |
3657 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
3658 | (*this_cache) = cache; | |
b8a22b94 | 3659 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
c5aa993b | 3660 | |
29639122 JB |
3661 | /* Analyze the function prologue. */ |
3662 | { | |
b8a22b94 | 3663 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 3664 | CORE_ADDR start_addr; |
c906108c | 3665 | |
29639122 JB |
3666 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
3667 | if (start_addr == 0) | |
e17a4113 | 3668 | start_addr = heuristic_proc_start (gdbarch, pc); |
29639122 JB |
3669 | /* We can't analyze the prologue if we couldn't find the begining |
3670 | of the function. */ | |
3671 | if (start_addr == 0) | |
3672 | return cache; | |
c5aa993b | 3673 | |
19ba03f4 SM |
3674 | mips32_scan_prologue (gdbarch, start_addr, pc, this_frame, |
3675 | (struct mips_frame_cache *) *this_cache); | |
29639122 JB |
3676 | } |
3677 | ||
3e8c568d | 3678 | /* gdbarch_sp_regnum contains the value and not the address. */ |
f57d151a | 3679 | trad_frame_set_value (cache->saved_regs, |
e17a4113 | 3680 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
f57d151a | 3681 | cache->base); |
c5aa993b | 3682 | |
19ba03f4 | 3683 | return (struct mips_frame_cache *) (*this_cache); |
c906108c SS |
3684 | } |
3685 | ||
29639122 | 3686 | static void |
b8a22b94 | 3687 | mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 | 3688 | struct frame_id *this_id) |
c906108c | 3689 | { |
b8a22b94 | 3690 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 3691 | this_cache); |
21327321 DJ |
3692 | /* This marks the outermost frame. */ |
3693 | if (info->base == 0) | |
3694 | return; | |
b8a22b94 | 3695 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
29639122 | 3696 | } |
c906108c | 3697 | |
b8a22b94 DJ |
3698 | static struct value * |
3699 | mips_insn32_frame_prev_register (struct frame_info *this_frame, | |
3700 | void **this_cache, int regnum) | |
29639122 | 3701 | { |
b8a22b94 | 3702 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 3703 | this_cache); |
b8a22b94 DJ |
3704 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
3705 | } | |
3706 | ||
3707 | static int | |
3708 | mips_insn32_frame_sniffer (const struct frame_unwind *self, | |
3709 | struct frame_info *this_frame, void **this_cache) | |
3710 | { | |
3711 | CORE_ADDR pc = get_frame_pc (this_frame); | |
4cc0665f | 3712 | if (mips_pc_is_mips (pc)) |
b8a22b94 DJ |
3713 | return 1; |
3714 | return 0; | |
c906108c SS |
3715 | } |
3716 | ||
29639122 JB |
3717 | static const struct frame_unwind mips_insn32_frame_unwind = |
3718 | { | |
3719 | NORMAL_FRAME, | |
8fbca658 | 3720 | default_frame_unwind_stop_reason, |
29639122 | 3721 | mips_insn32_frame_this_id, |
b8a22b94 DJ |
3722 | mips_insn32_frame_prev_register, |
3723 | NULL, | |
3724 | mips_insn32_frame_sniffer | |
29639122 | 3725 | }; |
c906108c | 3726 | |
1c645fec | 3727 | static CORE_ADDR |
b8a22b94 | 3728 | mips_insn32_frame_base_address (struct frame_info *this_frame, |
29639122 | 3729 | void **this_cache) |
c906108c | 3730 | { |
b8a22b94 | 3731 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 JB |
3732 | this_cache); |
3733 | return info->base; | |
3734 | } | |
c906108c | 3735 | |
29639122 JB |
3736 | static const struct frame_base mips_insn32_frame_base = |
3737 | { | |
3738 | &mips_insn32_frame_unwind, | |
3739 | mips_insn32_frame_base_address, | |
3740 | mips_insn32_frame_base_address, | |
3741 | mips_insn32_frame_base_address | |
3742 | }; | |
1c645fec | 3743 | |
29639122 | 3744 | static const struct frame_base * |
b8a22b94 | 3745 | mips_insn32_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 3746 | { |
b8a22b94 | 3747 | CORE_ADDR pc = get_frame_pc (this_frame); |
4cc0665f | 3748 | if (mips_pc_is_mips (pc)) |
29639122 | 3749 | return &mips_insn32_frame_base; |
a65bbe44 | 3750 | else |
29639122 JB |
3751 | return NULL; |
3752 | } | |
a65bbe44 | 3753 | |
29639122 | 3754 | static struct trad_frame_cache * |
b8a22b94 | 3755 | mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache) |
29639122 JB |
3756 | { |
3757 | CORE_ADDR pc; | |
3758 | CORE_ADDR start_addr; | |
3759 | CORE_ADDR stack_addr; | |
3760 | struct trad_frame_cache *this_trad_cache; | |
b8a22b94 DJ |
3761 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
3762 | int num_regs = gdbarch_num_regs (gdbarch); | |
c906108c | 3763 | |
29639122 | 3764 | if ((*this_cache) != NULL) |
19ba03f4 | 3765 | return (struct trad_frame_cache *) (*this_cache); |
b8a22b94 | 3766 | this_trad_cache = trad_frame_cache_zalloc (this_frame); |
29639122 | 3767 | (*this_cache) = this_trad_cache; |
1c645fec | 3768 | |
29639122 | 3769 | /* The return address is in the link register. */ |
3e8c568d | 3770 | trad_frame_set_reg_realreg (this_trad_cache, |
72a155b4 | 3771 | gdbarch_pc_regnum (gdbarch), |
b8a22b94 | 3772 | num_regs + MIPS_RA_REGNUM); |
1c645fec | 3773 | |
29639122 JB |
3774 | /* Frame ID, since it's a frameless / stackless function, no stack |
3775 | space is allocated and SP on entry is the current SP. */ | |
b8a22b94 | 3776 | pc = get_frame_pc (this_frame); |
29639122 | 3777 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
b8a22b94 DJ |
3778 | stack_addr = get_frame_register_signed (this_frame, |
3779 | num_regs + MIPS_SP_REGNUM); | |
aa6c981f | 3780 | trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr)); |
1c645fec | 3781 | |
29639122 JB |
3782 | /* Assume that the frame's base is the same as the |
3783 | stack-pointer. */ | |
3784 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
c906108c | 3785 | |
29639122 JB |
3786 | return this_trad_cache; |
3787 | } | |
c906108c | 3788 | |
29639122 | 3789 | static void |
b8a22b94 | 3790 | mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 JB |
3791 | struct frame_id *this_id) |
3792 | { | |
3793 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 3794 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
3795 | trad_frame_get_id (this_trad_cache, this_id); |
3796 | } | |
c906108c | 3797 | |
b8a22b94 DJ |
3798 | static struct value * |
3799 | mips_stub_frame_prev_register (struct frame_info *this_frame, | |
3800 | void **this_cache, int regnum) | |
29639122 JB |
3801 | { |
3802 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 DJ |
3803 | = mips_stub_frame_cache (this_frame, this_cache); |
3804 | return trad_frame_get_register (this_trad_cache, this_frame, regnum); | |
29639122 | 3805 | } |
c906108c | 3806 | |
b8a22b94 DJ |
3807 | static int |
3808 | mips_stub_frame_sniffer (const struct frame_unwind *self, | |
3809 | struct frame_info *this_frame, void **this_cache) | |
29639122 | 3810 | { |
aa6c981f | 3811 | gdb_byte dummy[4]; |
b8a22b94 | 3812 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
7cbd4a93 | 3813 | struct bound_minimal_symbol msym; |
979b38e0 | 3814 | |
aa6c981f | 3815 | /* Use the stub unwinder for unreadable code. */ |
b8a22b94 DJ |
3816 | if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) |
3817 | return 1; | |
aa6c981f | 3818 | |
3e5d3a5a | 3819 | if (in_plt_section (pc) || in_mips_stubs_section (pc)) |
b8a22b94 | 3820 | return 1; |
979b38e0 | 3821 | |
db5f024e DJ |
3822 | /* Calling a PIC function from a non-PIC function passes through a |
3823 | stub. The stub for foo is named ".pic.foo". */ | |
3824 | msym = lookup_minimal_symbol_by_pc (pc); | |
7cbd4a93 | 3825 | if (msym.minsym != NULL |
efd66ac6 | 3826 | && MSYMBOL_LINKAGE_NAME (msym.minsym) != NULL |
61012eef | 3827 | && startswith (MSYMBOL_LINKAGE_NAME (msym.minsym), ".pic.")) |
db5f024e DJ |
3828 | return 1; |
3829 | ||
b8a22b94 | 3830 | return 0; |
29639122 | 3831 | } |
c906108c | 3832 | |
b8a22b94 DJ |
3833 | static const struct frame_unwind mips_stub_frame_unwind = |
3834 | { | |
3835 | NORMAL_FRAME, | |
8fbca658 | 3836 | default_frame_unwind_stop_reason, |
b8a22b94 DJ |
3837 | mips_stub_frame_this_id, |
3838 | mips_stub_frame_prev_register, | |
3839 | NULL, | |
3840 | mips_stub_frame_sniffer | |
3841 | }; | |
3842 | ||
29639122 | 3843 | static CORE_ADDR |
b8a22b94 | 3844 | mips_stub_frame_base_address (struct frame_info *this_frame, |
29639122 JB |
3845 | void **this_cache) |
3846 | { | |
3847 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 3848 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
3849 | return trad_frame_get_this_base (this_trad_cache); |
3850 | } | |
0fce0821 | 3851 | |
29639122 JB |
3852 | static const struct frame_base mips_stub_frame_base = |
3853 | { | |
3854 | &mips_stub_frame_unwind, | |
3855 | mips_stub_frame_base_address, | |
3856 | mips_stub_frame_base_address, | |
3857 | mips_stub_frame_base_address | |
3858 | }; | |
3859 | ||
3860 | static const struct frame_base * | |
b8a22b94 | 3861 | mips_stub_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 3862 | { |
b8a22b94 | 3863 | if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL)) |
29639122 JB |
3864 | return &mips_stub_frame_base; |
3865 | else | |
3866 | return NULL; | |
3867 | } | |
3868 | ||
29639122 | 3869 | /* mips_addr_bits_remove - remove useless address bits */ |
65596487 | 3870 | |
29639122 | 3871 | static CORE_ADDR |
24568a2c | 3872 | mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) |
65596487 | 3873 | { |
24568a2c | 3874 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
930bd0e0 | 3875 | |
29639122 JB |
3876 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) |
3877 | /* This hack is a work-around for existing boards using PMON, the | |
3878 | simulator, and any other 64-bit targets that doesn't have true | |
3879 | 64-bit addressing. On these targets, the upper 32 bits of | |
3880 | addresses are ignored by the hardware. Thus, the PC or SP are | |
3881 | likely to have been sign extended to all 1s by instruction | |
3882 | sequences that load 32-bit addresses. For example, a typical | |
3883 | piece of code that loads an address is this: | |
65596487 | 3884 | |
29639122 JB |
3885 | lui $r2, <upper 16 bits> |
3886 | ori $r2, <lower 16 bits> | |
65596487 | 3887 | |
29639122 JB |
3888 | But the lui sign-extends the value such that the upper 32 bits |
3889 | may be all 1s. The workaround is simply to mask off these | |
3890 | bits. In the future, gcc may be changed to support true 64-bit | |
3891 | addressing, and this masking will have to be disabled. */ | |
3892 | return addr &= 0xffffffffUL; | |
3893 | else | |
3894 | return addr; | |
65596487 JB |
3895 | } |
3896 | ||
3d5f6d12 DJ |
3897 | |
3898 | /* Checks for an atomic sequence of instructions beginning with a LL/LLD | |
3899 | instruction and ending with a SC/SCD instruction. If such a sequence | |
3900 | is found, attempt to step through it. A breakpoint is placed at the end of | |
3901 | the sequence. */ | |
3902 | ||
4cc0665f MR |
3903 | /* Instructions used during single-stepping of atomic sequences, standard |
3904 | ISA version. */ | |
3905 | #define LL_OPCODE 0x30 | |
3906 | #define LLD_OPCODE 0x34 | |
3907 | #define SC_OPCODE 0x38 | |
3908 | #define SCD_OPCODE 0x3c | |
3909 | ||
a0ff9e1a | 3910 | static std::vector<CORE_ADDR> |
93f9a11f | 3911 | mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) |
3d5f6d12 | 3912 | { |
70ab8ccd | 3913 | CORE_ADDR breaks[2] = {CORE_ADDR_MAX, CORE_ADDR_MAX}; |
3d5f6d12 DJ |
3914 | CORE_ADDR loc = pc; |
3915 | CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ | |
4cc0665f | 3916 | ULONGEST insn; |
3d5f6d12 DJ |
3917 | int insn_count; |
3918 | int index; | |
3919 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
3920 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
3921 | ||
4cc0665f | 3922 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); |
3d5f6d12 DJ |
3923 | /* Assume all atomic sequences start with a ll/lld instruction. */ |
3924 | if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE) | |
a0ff9e1a | 3925 | return {}; |
3d5f6d12 DJ |
3926 | |
3927 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" | |
3928 | instructions. */ | |
3929 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
3930 | { | |
3931 | int is_branch = 0; | |
3932 | loc += MIPS_INSN32_SIZE; | |
4cc0665f | 3933 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); |
3d5f6d12 DJ |
3934 | |
3935 | /* Assume that there is at most one branch in the atomic | |
3936 | sequence. If a branch is found, put a breakpoint in its | |
3937 | destination address. */ | |
3938 | switch (itype_op (insn)) | |
3939 | { | |
3940 | case 0: /* SPECIAL */ | |
3941 | if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */ | |
a0ff9e1a | 3942 | return {}; /* fallback to the standard single-step code. */ |
3d5f6d12 DJ |
3943 | break; |
3944 | case 1: /* REGIMM */ | |
a385295e MR |
3945 | is_branch = ((itype_rt (insn) & 0xc) == 0 /* B{LT,GE}Z* */ |
3946 | || ((itype_rt (insn) & 0x1e) == 0 | |
3947 | && itype_rs (insn) == 0)); /* BPOSGE* */ | |
3d5f6d12 DJ |
3948 | break; |
3949 | case 2: /* J */ | |
3950 | case 3: /* JAL */ | |
a0ff9e1a | 3951 | return {}; /* fallback to the standard single-step code. */ |
3d5f6d12 DJ |
3952 | case 4: /* BEQ */ |
3953 | case 5: /* BNE */ | |
3954 | case 6: /* BLEZ */ | |
3955 | case 7: /* BGTZ */ | |
3956 | case 20: /* BEQL */ | |
3957 | case 21: /* BNEL */ | |
3958 | case 22: /* BLEZL */ | |
3959 | case 23: /* BGTTL */ | |
3960 | is_branch = 1; | |
3961 | break; | |
3962 | case 17: /* COP1 */ | |
a385295e MR |
3963 | is_branch = ((itype_rs (insn) == 9 || itype_rs (insn) == 10) |
3964 | && (itype_rt (insn) & 0x2) == 0); | |
3965 | if (is_branch) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */ | |
3966 | break; | |
3967 | /* Fall through. */ | |
3d5f6d12 DJ |
3968 | case 18: /* COP2 */ |
3969 | case 19: /* COP3 */ | |
3970 | is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */ | |
3971 | break; | |
3972 | } | |
3973 | if (is_branch) | |
3974 | { | |
3975 | branch_bp = loc + mips32_relative_offset (insn) + 4; | |
3976 | if (last_breakpoint >= 1) | |
a0ff9e1a SM |
3977 | return {}; /* More than one branch found, fallback to the |
3978 | standard single-step code. */ | |
3d5f6d12 DJ |
3979 | breaks[1] = branch_bp; |
3980 | last_breakpoint++; | |
3981 | } | |
3982 | ||
3983 | if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE) | |
3984 | break; | |
3985 | } | |
3986 | ||
3987 | /* Assume that the atomic sequence ends with a sc/scd instruction. */ | |
3988 | if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE) | |
a0ff9e1a | 3989 | return {}; |
3d5f6d12 DJ |
3990 | |
3991 | loc += MIPS_INSN32_SIZE; | |
3992 | ||
3993 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
3994 | breaks[0] = loc; | |
3995 | ||
3996 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
025bb325 | 3997 | placed (branch instruction's destination) in the atomic sequence. */ |
3d5f6d12 DJ |
3998 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) |
3999 | last_breakpoint = 0; | |
4000 | ||
a0ff9e1a SM |
4001 | std::vector<CORE_ADDR> next_pcs; |
4002 | ||
3d5f6d12 DJ |
4003 | /* Effectively inserts the breakpoints. */ |
4004 | for (index = 0; index <= last_breakpoint; index++) | |
a0ff9e1a | 4005 | next_pcs.push_back (breaks[index]); |
3d5f6d12 | 4006 | |
93f9a11f | 4007 | return next_pcs; |
3d5f6d12 DJ |
4008 | } |
4009 | ||
a0ff9e1a | 4010 | static std::vector<CORE_ADDR> |
4cc0665f | 4011 | micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch, |
4cc0665f MR |
4012 | CORE_ADDR pc) |
4013 | { | |
4014 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
4015 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
70ab8ccd | 4016 | CORE_ADDR breaks[2] = {CORE_ADDR_MAX, CORE_ADDR_MAX}; |
4b844a38 AT |
4017 | CORE_ADDR branch_bp = 0; /* Breakpoint at branch instruction's |
4018 | destination. */ | |
4cc0665f MR |
4019 | CORE_ADDR loc = pc; |
4020 | int sc_found = 0; | |
4021 | ULONGEST insn; | |
4022 | int insn_count; | |
4023 | int index; | |
4024 | ||
4025 | /* Assume all atomic sequences start with a ll/lld instruction. */ | |
4026 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); | |
4027 | if (micromips_op (insn) != 0x18) /* POOL32C: bits 011000 */ | |
a0ff9e1a | 4028 | return {}; |
4cc0665f MR |
4029 | loc += MIPS_INSN16_SIZE; |
4030 | insn <<= 16; | |
4031 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); | |
4032 | if ((b12s4_op (insn) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */ | |
a0ff9e1a | 4033 | return {}; |
4cc0665f MR |
4034 | loc += MIPS_INSN16_SIZE; |
4035 | ||
4036 | /* Assume all atomic sequences end with an sc/scd instruction. Assume | |
4037 | that no atomic sequence is longer than "atomic_sequence_length" | |
4038 | instructions. */ | |
4039 | for (insn_count = 0; | |
4040 | !sc_found && insn_count < atomic_sequence_length; | |
4041 | ++insn_count) | |
4042 | { | |
4043 | int is_branch = 0; | |
4044 | ||
4045 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); | |
4046 | loc += MIPS_INSN16_SIZE; | |
4047 | ||
4048 | /* Assume that there is at most one conditional branch in the | |
4049 | atomic sequence. If a branch is found, put a breakpoint in | |
4050 | its destination address. */ | |
4051 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
4052 | { | |
4cc0665f MR |
4053 | /* 32-bit instructions. */ |
4054 | case 2 * MIPS_INSN16_SIZE: | |
4055 | switch (micromips_op (insn)) | |
4056 | { | |
4057 | case 0x10: /* POOL32I: bits 010000 */ | |
4058 | if ((b5s5_op (insn) & 0x18) != 0x0 | |
4059 | /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */ | |
4060 | /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */ | |
4061 | && (b5s5_op (insn) & 0x1d) != 0x11 | |
4062 | /* BLTZALS, BGEZALS: bits 010000 100x1 */ | |
4063 | && ((b5s5_op (insn) & 0x1e) != 0x14 | |
4064 | || (insn & 0x3) != 0x0) | |
4065 | /* BC2F, BC2T: bits 010000 1010x xxx00 */ | |
4066 | && (b5s5_op (insn) & 0x1e) != 0x1a | |
4067 | /* BPOSGE64, BPOSGE32: bits 010000 1101x */ | |
4068 | && ((b5s5_op (insn) & 0x1e) != 0x1c | |
4069 | || (insn & 0x3) != 0x0) | |
4070 | /* BC1F, BC1T: bits 010000 1110x xxx00 */ | |
4071 | && ((b5s5_op (insn) & 0x1c) != 0x1c | |
4072 | || (insn & 0x3) != 0x1)) | |
4073 | /* BC1ANY*: bits 010000 111xx xxx01 */ | |
4074 | break; | |
4075 | /* Fall through. */ | |
4076 | ||
4077 | case 0x25: /* BEQ: bits 100101 */ | |
4078 | case 0x2d: /* BNE: bits 101101 */ | |
4079 | insn <<= 16; | |
4080 | insn |= mips_fetch_instruction (gdbarch, | |
4081 | ISA_MICROMIPS, loc, NULL); | |
4082 | branch_bp = (loc + MIPS_INSN16_SIZE | |
4083 | + micromips_relative_offset16 (insn)); | |
4084 | is_branch = 1; | |
4085 | break; | |
4086 | ||
4087 | case 0x00: /* POOL32A: bits 000000 */ | |
4088 | insn <<= 16; | |
4089 | insn |= mips_fetch_instruction (gdbarch, | |
4090 | ISA_MICROMIPS, loc, NULL); | |
4091 | if (b0s6_op (insn) != 0x3c | |
4092 | /* POOL32Axf: bits 000000 ... 111100 */ | |
4093 | || (b6s10_ext (insn) & 0x2bf) != 0x3c) | |
4094 | /* JALR, JALR.HB: 000000 000x111100 111100 */ | |
4095 | /* JALRS, JALRS.HB: 000000 010x111100 111100 */ | |
4096 | break; | |
4097 | /* Fall through. */ | |
4098 | ||
4099 | case 0x1d: /* JALS: bits 011101 */ | |
4100 | case 0x35: /* J: bits 110101 */ | |
4101 | case 0x3d: /* JAL: bits 111101 */ | |
4102 | case 0x3c: /* JALX: bits 111100 */ | |
a0ff9e1a | 4103 | return {}; /* Fall back to the standard single-step code. */ |
4cc0665f MR |
4104 | |
4105 | case 0x18: /* POOL32C: bits 011000 */ | |
4106 | if ((b12s4_op (insn) & 0xb) == 0xb) | |
4107 | /* SC, SCD: bits 011000 1x11 */ | |
4108 | sc_found = 1; | |
4109 | break; | |
4110 | } | |
4111 | loc += MIPS_INSN16_SIZE; | |
4112 | break; | |
4113 | ||
4114 | /* 16-bit instructions. */ | |
4115 | case MIPS_INSN16_SIZE: | |
4116 | switch (micromips_op (insn)) | |
4117 | { | |
4118 | case 0x23: /* BEQZ16: bits 100011 */ | |
4119 | case 0x2b: /* BNEZ16: bits 101011 */ | |
4120 | branch_bp = loc + micromips_relative_offset7 (insn); | |
4121 | is_branch = 1; | |
4122 | break; | |
4123 | ||
4124 | case 0x11: /* POOL16C: bits 010001 */ | |
4125 | if ((b5s5_op (insn) & 0x1c) != 0xc | |
4126 | /* JR16, JRC, JALR16, JALRS16: 010001 011xx */ | |
4127 | && b5s5_op (insn) != 0x18) | |
4128 | /* JRADDIUSP: bits 010001 11000 */ | |
4129 | break; | |
a0ff9e1a | 4130 | return {}; /* Fall back to the standard single-step code. */ |
4cc0665f MR |
4131 | |
4132 | case 0x33: /* B16: bits 110011 */ | |
a0ff9e1a | 4133 | return {}; /* Fall back to the standard single-step code. */ |
4cc0665f MR |
4134 | } |
4135 | break; | |
4136 | } | |
4137 | if (is_branch) | |
4138 | { | |
4139 | if (last_breakpoint >= 1) | |
a0ff9e1a SM |
4140 | return {}; /* More than one branch found, fallback to the |
4141 | standard single-step code. */ | |
4cc0665f MR |
4142 | breaks[1] = branch_bp; |
4143 | last_breakpoint++; | |
4144 | } | |
4145 | } | |
4146 | if (!sc_found) | |
a0ff9e1a | 4147 | return {}; |
4cc0665f MR |
4148 | |
4149 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
4150 | breaks[0] = loc; | |
4151 | ||
4152 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
4153 | placed (branch instruction's destination) in the atomic sequence */ | |
4154 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) | |
4155 | last_breakpoint = 0; | |
4156 | ||
a0ff9e1a SM |
4157 | std::vector<CORE_ADDR> next_pcs; |
4158 | ||
4cc0665f MR |
4159 | /* Effectively inserts the breakpoints. */ |
4160 | for (index = 0; index <= last_breakpoint; index++) | |
a0ff9e1a | 4161 | next_pcs.push_back (breaks[index]); |
4cc0665f | 4162 | |
93f9a11f | 4163 | return next_pcs; |
4cc0665f MR |
4164 | } |
4165 | ||
a0ff9e1a | 4166 | static std::vector<CORE_ADDR> |
93f9a11f | 4167 | deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) |
4cc0665f MR |
4168 | { |
4169 | if (mips_pc_is_mips (pc)) | |
93f9a11f | 4170 | return mips_deal_with_atomic_sequence (gdbarch, pc); |
4cc0665f | 4171 | else if (mips_pc_is_micromips (gdbarch, pc)) |
93f9a11f | 4172 | return micromips_deal_with_atomic_sequence (gdbarch, pc); |
4cc0665f | 4173 | else |
a0ff9e1a | 4174 | return {}; |
4cc0665f MR |
4175 | } |
4176 | ||
29639122 JB |
4177 | /* mips_software_single_step() is called just before we want to resume |
4178 | the inferior, if we want to single-step it but there is no hardware | |
4179 | or kernel single-step support (MIPS on GNU/Linux for example). We find | |
e0cd558a | 4180 | the target of the coming instruction and breakpoint it. */ |
29639122 | 4181 | |
a0ff9e1a | 4182 | std::vector<CORE_ADDR> |
f5ea389a | 4183 | mips_software_single_step (struct regcache *regcache) |
c906108c | 4184 | { |
ac7936df | 4185 | struct gdbarch *gdbarch = regcache->arch (); |
8181d85f | 4186 | CORE_ADDR pc, next_pc; |
65596487 | 4187 | |
7113a196 | 4188 | pc = regcache_read_pc (regcache); |
a0ff9e1a SM |
4189 | std::vector<CORE_ADDR> next_pcs = deal_with_atomic_sequence (gdbarch, pc); |
4190 | ||
4191 | if (!next_pcs.empty ()) | |
93f9a11f | 4192 | return next_pcs; |
3d5f6d12 | 4193 | |
7113a196 | 4194 | next_pc = mips_next_pc (regcache, pc); |
e6590a1b | 4195 | |
a0ff9e1a | 4196 | return {next_pc}; |
29639122 | 4197 | } |
a65bbe44 | 4198 | |
29639122 | 4199 | /* Test whether the PC points to the return instruction at the |
025bb325 | 4200 | end of a function. */ |
65596487 | 4201 | |
29639122 | 4202 | static int |
e17a4113 | 4203 | mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 | 4204 | { |
6321c22a MR |
4205 | ULONGEST insn; |
4206 | ULONGEST hint; | |
4207 | ||
4208 | /* This used to check for MIPS16, but this piece of code is never | |
4cc0665f MR |
4209 | called for MIPS16 functions. And likewise microMIPS ones. */ |
4210 | gdb_assert (mips_pc_is_mips (pc)); | |
6321c22a | 4211 | |
4cc0665f | 4212 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
6321c22a MR |
4213 | hint = 0x7c0; |
4214 | return (insn & ~hint) == 0x3e00008; /* jr(.hb) $ra */ | |
29639122 | 4215 | } |
c906108c | 4216 | |
c906108c | 4217 | |
29639122 JB |
4218 | /* This fencepost looks highly suspicious to me. Removing it also |
4219 | seems suspicious as it could affect remote debugging across serial | |
4220 | lines. */ | |
c906108c | 4221 | |
29639122 | 4222 | static CORE_ADDR |
74ed0bb4 | 4223 | heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 JB |
4224 | { |
4225 | CORE_ADDR start_pc; | |
4226 | CORE_ADDR fence; | |
4227 | int instlen; | |
4228 | int seen_adjsp = 0; | |
d6b48e9c | 4229 | struct inferior *inf; |
65596487 | 4230 | |
74ed0bb4 | 4231 | pc = gdbarch_addr_bits_remove (gdbarch, pc); |
29639122 JB |
4232 | start_pc = pc; |
4233 | fence = start_pc - heuristic_fence_post; | |
4234 | if (start_pc == 0) | |
4235 | return 0; | |
65596487 | 4236 | |
44096aee | 4237 | if (heuristic_fence_post == -1 || fence < VM_MIN_ADDRESS) |
29639122 | 4238 | fence = VM_MIN_ADDRESS; |
65596487 | 4239 | |
4cc0665f | 4240 | instlen = mips_pc_is_mips (pc) ? MIPS_INSN32_SIZE : MIPS_INSN16_SIZE; |
98b4dd94 | 4241 | |
d6b48e9c PA |
4242 | inf = current_inferior (); |
4243 | ||
025bb325 | 4244 | /* Search back for previous return. */ |
29639122 JB |
4245 | for (start_pc -= instlen;; start_pc -= instlen) |
4246 | if (start_pc < fence) | |
4247 | { | |
4248 | /* It's not clear to me why we reach this point when | |
4249 | stop_soon, but with this test, at least we | |
4250 | don't print out warnings for every child forked (eg, on | |
4251 | decstation). 22apr93 rich@cygnus.com. */ | |
16c381f0 | 4252 | if (inf->control.stop_soon == NO_STOP_QUIETLY) |
29639122 JB |
4253 | { |
4254 | static int blurb_printed = 0; | |
98b4dd94 | 4255 | |
5af949e3 UW |
4256 | warning (_("GDB can't find the start of the function at %s."), |
4257 | paddress (gdbarch, pc)); | |
29639122 JB |
4258 | |
4259 | if (!blurb_printed) | |
4260 | { | |
4261 | /* This actually happens frequently in embedded | |
4262 | development, when you first connect to a board | |
4263 | and your stack pointer and pc are nowhere in | |
4264 | particular. This message needs to give people | |
4265 | in that situation enough information to | |
4266 | determine that it's no big deal. */ | |
4267 | printf_filtered ("\n\ | |
5af949e3 | 4268 | GDB is unable to find the start of the function at %s\n\ |
29639122 JB |
4269 | and thus can't determine the size of that function's stack frame.\n\ |
4270 | This means that GDB may be unable to access that stack frame, or\n\ | |
4271 | the frames below it.\n\ | |
4272 | This problem is most likely caused by an invalid program counter or\n\ | |
4273 | stack pointer.\n\ | |
4274 | However, if you think GDB should simply search farther back\n\ | |
5af949e3 | 4275 | from %s for code which looks like the beginning of a\n\ |
29639122 | 4276 | function, you can increase the range of the search using the `set\n\ |
5af949e3 UW |
4277 | heuristic-fence-post' command.\n", |
4278 | paddress (gdbarch, pc), paddress (gdbarch, pc)); | |
29639122 JB |
4279 | blurb_printed = 1; |
4280 | } | |
4281 | } | |
4282 | ||
4283 | return 0; | |
4284 | } | |
4cc0665f | 4285 | else if (mips_pc_is_mips16 (gdbarch, start_pc)) |
29639122 JB |
4286 | { |
4287 | unsigned short inst; | |
4288 | ||
4289 | /* On MIPS16, any one of the following is likely to be the | |
4290 | start of a function: | |
193774b3 MR |
4291 | extend save |
4292 | save | |
29639122 JB |
4293 | entry |
4294 | addiu sp,-n | |
4295 | daddiu sp,-n | |
025bb325 | 4296 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */ |
4cc0665f | 4297 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, start_pc, NULL); |
193774b3 MR |
4298 | if ((inst & 0xff80) == 0x6480) /* save */ |
4299 | { | |
4300 | if (start_pc - instlen >= fence) | |
4301 | { | |
4cc0665f MR |
4302 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, |
4303 | start_pc - instlen, NULL); | |
193774b3 MR |
4304 | if ((inst & 0xf800) == 0xf000) /* extend */ |
4305 | start_pc -= instlen; | |
4306 | } | |
4307 | break; | |
4308 | } | |
4309 | else if (((inst & 0xf81f) == 0xe809 | |
4310 | && (inst & 0x700) != 0x700) /* entry */ | |
4311 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
4312 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
4313 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
29639122 JB |
4314 | break; |
4315 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
4316 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
4317 | seen_adjsp = 1; | |
4318 | else | |
4319 | seen_adjsp = 0; | |
4320 | } | |
4cc0665f MR |
4321 | else if (mips_pc_is_micromips (gdbarch, start_pc)) |
4322 | { | |
4323 | ULONGEST insn; | |
4324 | int stop = 0; | |
4325 | long offset; | |
4326 | int dreg; | |
4327 | int sreg; | |
4328 | ||
4329 | /* On microMIPS, any one of the following is likely to be the | |
4330 | start of a function: | |
4331 | ADDIUSP -imm | |
4332 | (D)ADDIU $sp, -imm | |
4333 | LUI $gp, imm */ | |
4334 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
4335 | switch (micromips_op (insn)) | |
4336 | { | |
4337 | case 0xc: /* ADDIU: bits 001100 */ | |
4338 | case 0x17: /* DADDIU: bits 010111 */ | |
4339 | sreg = b0s5_reg (insn); | |
4340 | dreg = b5s5_reg (insn); | |
4341 | insn <<= 16; | |
4342 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, | |
4343 | pc + MIPS_INSN16_SIZE, NULL); | |
4344 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
4345 | if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM | |
4346 | /* (D)ADDIU $sp, imm */ | |
4347 | && offset < 0) | |
4348 | stop = 1; | |
4349 | break; | |
4350 | ||
4351 | case 0x10: /* POOL32I: bits 010000 */ | |
4352 | if (b5s5_op (insn) == 0xd | |
4353 | /* LUI: bits 010000 001101 */ | |
4354 | && b0s5_reg (insn >> 16) == 28) | |
4355 | /* LUI $gp, imm */ | |
4356 | stop = 1; | |
4357 | break; | |
4358 | ||
4359 | case 0x13: /* POOL16D: bits 010011 */ | |
4360 | if ((insn & 0x1) == 0x1) | |
4361 | /* ADDIUSP: bits 010011 1 */ | |
4362 | { | |
4363 | offset = micromips_decode_imm9 (b1s9_imm (insn)); | |
4364 | if (offset < 0) | |
4365 | /* ADDIUSP -imm */ | |
4366 | stop = 1; | |
4367 | } | |
4368 | else | |
4369 | /* ADDIUS5: bits 010011 0 */ | |
4370 | { | |
4371 | dreg = b5s5_reg (insn); | |
4372 | offset = (b1s4_imm (insn) ^ 8) - 8; | |
4373 | if (dreg == MIPS_SP_REGNUM && offset < 0) | |
4374 | /* ADDIUS5 $sp, -imm */ | |
4375 | stop = 1; | |
4376 | } | |
4377 | break; | |
4378 | } | |
4379 | if (stop) | |
4380 | break; | |
4381 | } | |
e17a4113 | 4382 | else if (mips_about_to_return (gdbarch, start_pc)) |
29639122 | 4383 | { |
4c7d22cb | 4384 | /* Skip return and its delay slot. */ |
95ac2dcf | 4385 | start_pc += 2 * MIPS_INSN32_SIZE; |
29639122 JB |
4386 | break; |
4387 | } | |
4388 | ||
4389 | return start_pc; | |
c906108c SS |
4390 | } |
4391 | ||
6c0d6680 DJ |
4392 | struct mips_objfile_private |
4393 | { | |
4394 | bfd_size_type size; | |
4395 | char *contents; | |
4396 | }; | |
4397 | ||
f09ded24 AC |
4398 | /* According to the current ABI, should the type be passed in a |
4399 | floating-point register (assuming that there is space)? When there | |
a1f5b845 | 4400 | is no FPU, FP are not even considered as possible candidates for |
f09ded24 | 4401 | FP registers and, consequently this returns false - forces FP |
025bb325 | 4402 | arguments into integer registers. */ |
f09ded24 AC |
4403 | |
4404 | static int | |
74ed0bb4 MD |
4405 | fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode, |
4406 | struct type *arg_type) | |
f09ded24 AC |
4407 | { |
4408 | return ((typecode == TYPE_CODE_FLT | |
74ed0bb4 | 4409 | || (MIPS_EABI (gdbarch) |
6d82d43b AC |
4410 | && (typecode == TYPE_CODE_STRUCT |
4411 | || typecode == TYPE_CODE_UNION) | |
f09ded24 | 4412 | && TYPE_NFIELDS (arg_type) == 1 |
b2d6f210 MS |
4413 | && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0))) |
4414 | == TYPE_CODE_FLT)) | |
74ed0bb4 | 4415 | && MIPS_FPU_TYPE(gdbarch) != MIPS_FPU_NONE); |
f09ded24 AC |
4416 | } |
4417 | ||
49e790b0 | 4418 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
025bb325 | 4419 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ |
49e790b0 DJ |
4420 | |
4421 | static int | |
4422 | mips_type_needs_double_align (struct type *type) | |
4423 | { | |
4424 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 4425 | |
49e790b0 DJ |
4426 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
4427 | return 1; | |
4428 | else if (typecode == TYPE_CODE_STRUCT) | |
4429 | { | |
4430 | if (TYPE_NFIELDS (type) < 1) | |
4431 | return 0; | |
4432 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
4433 | } | |
4434 | else if (typecode == TYPE_CODE_UNION) | |
4435 | { | |
361d1df0 | 4436 | int i, n; |
49e790b0 DJ |
4437 | |
4438 | n = TYPE_NFIELDS (type); | |
4439 | for (i = 0; i < n; i++) | |
4440 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
4441 | return 1; | |
4442 | return 0; | |
4443 | } | |
4444 | return 0; | |
4445 | } | |
4446 | ||
dc604539 AC |
4447 | /* Adjust the address downward (direction of stack growth) so that it |
4448 | is correctly aligned for a new stack frame. */ | |
4449 | static CORE_ADDR | |
4450 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
4451 | { | |
5b03f266 | 4452 | return align_down (addr, 16); |
dc604539 AC |
4453 | } |
4454 | ||
8ae38c14 | 4455 | /* Implement the "push_dummy_code" gdbarch method. */ |
2c76a0c7 JB |
4456 | |
4457 | static CORE_ADDR | |
4458 | mips_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
4459 | CORE_ADDR funaddr, struct value **args, | |
4460 | int nargs, struct type *value_type, | |
4461 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, | |
4462 | struct regcache *regcache) | |
4463 | { | |
2c76a0c7 | 4464 | static gdb_byte nop_insn[] = { 0, 0, 0, 0 }; |
2e81047f MR |
4465 | CORE_ADDR nop_addr; |
4466 | CORE_ADDR bp_slot; | |
2c76a0c7 JB |
4467 | |
4468 | /* Reserve enough room on the stack for our breakpoint instruction. */ | |
2e81047f MR |
4469 | bp_slot = sp - sizeof (nop_insn); |
4470 | ||
4471 | /* Return to microMIPS mode if calling microMIPS code to avoid | |
4472 | triggering an address error exception on processors that only | |
4473 | support microMIPS execution. */ | |
4474 | *bp_addr = (mips_pc_is_micromips (gdbarch, funaddr) | |
4475 | ? make_compact_addr (bp_slot) : bp_slot); | |
2c76a0c7 JB |
4476 | |
4477 | /* The breakpoint layer automatically adjusts the address of | |
4478 | breakpoints inserted in a branch delay slot. With enough | |
4479 | bad luck, the 4 bytes located just before our breakpoint | |
4480 | instruction could look like a branch instruction, and thus | |
4481 | trigger the adjustement, and break the function call entirely. | |
4482 | So, we reserve those 4 bytes and write a nop instruction | |
4483 | to prevent that from happening. */ | |
2e81047f | 4484 | nop_addr = bp_slot - sizeof (nop_insn); |
2c76a0c7 JB |
4485 | write_memory (nop_addr, nop_insn, sizeof (nop_insn)); |
4486 | sp = mips_frame_align (gdbarch, nop_addr); | |
4487 | ||
4488 | /* Inferior resumes at the function entry point. */ | |
4489 | *real_pc = funaddr; | |
4490 | ||
4491 | return sp; | |
4492 | } | |
4493 | ||
f7ab6ec6 | 4494 | static CORE_ADDR |
7d9b040b | 4495 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4496 | struct regcache *regcache, CORE_ADDR bp_addr, |
4497 | int nargs, struct value **args, CORE_ADDR sp, | |
4498 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
4499 | { |
4500 | int argreg; | |
4501 | int float_argreg; | |
4502 | int argnum; | |
4503 | int len = 0; | |
4504 | int stack_offset = 0; | |
e17a4113 | 4505 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 4506 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
b3464d03 | 4507 | int abi_regsize = mips_abi_regsize (gdbarch); |
c906108c | 4508 | |
25ab4790 AC |
4509 | /* For shared libraries, "t9" needs to point at the function |
4510 | address. */ | |
4c7d22cb | 4511 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
4512 | |
4513 | /* Set the return address register to point to the entry point of | |
4514 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 4515 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 4516 | |
c906108c | 4517 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
4518 | are properly aligned. The stack has to be at least 64-bit |
4519 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4520 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4521 | aligned, so we round to this widest known alignment. */ | |
4522 | ||
5b03f266 AC |
4523 | sp = align_down (sp, 16); |
4524 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 4525 | |
46e0f506 | 4526 | /* Now make space on the stack for the args. We allocate more |
c906108c | 4527 | than necessary for EABI, because the first few arguments are |
46e0f506 | 4528 | passed in registers, but that's OK. */ |
c906108c | 4529 | for (argnum = 0; argnum < nargs; argnum++) |
b3464d03 | 4530 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), abi_regsize); |
5b03f266 | 4531 | sp -= align_up (len, 16); |
c906108c | 4532 | |
9ace0497 | 4533 | if (mips_debug) |
6d82d43b | 4534 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
4535 | "mips_eabi_push_dummy_call: sp=%s allocated %ld\n", |
4536 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
9ace0497 | 4537 | |
c906108c | 4538 | /* Initialize the integer and float register pointers. */ |
4c7d22cb | 4539 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 4540 | float_argreg = mips_fpa0_regnum (gdbarch); |
c906108c | 4541 | |
46e0f506 | 4542 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 4543 | if (struct_return) |
9ace0497 AC |
4544 | { |
4545 | if (mips_debug) | |
4546 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
4547 | "mips_eabi_push_dummy_call: " |
4548 | "struct_return reg=%d %s\n", | |
5af949e3 | 4549 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 4550 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
9ace0497 | 4551 | } |
c906108c SS |
4552 | |
4553 | /* Now load as many as possible of the first arguments into | |
4554 | registers, and push the rest onto the stack. Loop thru args | |
4555 | from first to last. */ | |
4556 | for (argnum = 0; argnum < nargs; argnum++) | |
4557 | { | |
47a35522 | 4558 | const gdb_byte *val; |
b3464d03 PA |
4559 | /* This holds the address of structures that are passed by |
4560 | reference. */ | |
4561 | gdb_byte ref_valbuf[MAX_MIPS_ABI_REGSIZE]; | |
ea7c478f | 4562 | struct value *arg = args[argnum]; |
4991999e | 4563 | struct type *arg_type = check_typedef (value_type (arg)); |
c906108c SS |
4564 | int len = TYPE_LENGTH (arg_type); |
4565 | enum type_code typecode = TYPE_CODE (arg_type); | |
4566 | ||
9ace0497 AC |
4567 | if (mips_debug) |
4568 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4569 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 4570 | argnum + 1, len, (int) typecode); |
9ace0497 | 4571 | |
c906108c | 4572 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 4573 | reference. */ |
b3464d03 | 4574 | if (len > abi_regsize |
9ace0497 | 4575 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 4576 | { |
b3464d03 PA |
4577 | gdb_assert (abi_regsize <= ARRAY_SIZE (ref_valbuf)); |
4578 | store_unsigned_integer (ref_valbuf, abi_regsize, byte_order, | |
e17a4113 | 4579 | value_address (arg)); |
c906108c | 4580 | typecode = TYPE_CODE_PTR; |
b3464d03 PA |
4581 | len = abi_regsize; |
4582 | val = ref_valbuf; | |
9ace0497 AC |
4583 | if (mips_debug) |
4584 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
4585 | } |
4586 | else | |
47a35522 | 4587 | val = value_contents (arg); |
c906108c SS |
4588 | |
4589 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
4590 | even-numbered floating point register. Round the FP register |
4591 | up before the check to see if there are any FP registers | |
46e0f506 MS |
4592 | left. Non MIPS_EABI targets also pass the FP in the integer |
4593 | registers so also round up normal registers. */ | |
b3464d03 | 4594 | if (abi_regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type)) |
acdb74a0 AC |
4595 | { |
4596 | if ((float_argreg & 1)) | |
4597 | float_argreg++; | |
4598 | } | |
c906108c SS |
4599 | |
4600 | /* Floating point arguments passed in registers have to be | |
4601 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
4602 | are passed in register pairs; the even register gets |
4603 | the low word, and the odd register gets the high word. | |
4604 | On non-EABI processors, the first two floating point arguments are | |
4605 | also copied to general registers, because MIPS16 functions | |
4606 | don't use float registers for arguments. This duplication of | |
4607 | arguments in general registers can't hurt non-MIPS16 functions | |
4608 | because those registers are normally skipped. */ | |
1012bd0e EZ |
4609 | /* MIPS_EABI squeezes a struct that contains a single floating |
4610 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 4611 | stack. */ |
74ed0bb4 MD |
4612 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
4613 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
c906108c | 4614 | { |
6da397e0 KB |
4615 | /* EABI32 will pass doubles in consecutive registers, even on |
4616 | 64-bit cores. At one time, we used to check the size of | |
4617 | `float_argreg' to determine whether or not to pass doubles | |
4618 | in consecutive registers, but this is not sufficient for | |
4619 | making the ABI determination. */ | |
4620 | if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) | |
c906108c | 4621 | { |
72a155b4 | 4622 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 4623 | == BFD_ENDIAN_BIG ? 4 : 0; |
a8852dc5 | 4624 | long regval; |
c906108c SS |
4625 | |
4626 | /* Write the low word of the double to the even register(s). */ | |
a8852dc5 KB |
4627 | regval = extract_signed_integer (val + low_offset, |
4628 | 4, byte_order); | |
9ace0497 | 4629 | if (mips_debug) |
acdb74a0 | 4630 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 4631 | float_argreg, phex (regval, 4)); |
a8852dc5 | 4632 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
4633 | |
4634 | /* Write the high word of the double to the odd register(s). */ | |
a8852dc5 KB |
4635 | regval = extract_signed_integer (val + 4 - low_offset, |
4636 | 4, byte_order); | |
9ace0497 | 4637 | if (mips_debug) |
acdb74a0 | 4638 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 4639 | float_argreg, phex (regval, 4)); |
a8852dc5 | 4640 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
4641 | } |
4642 | else | |
4643 | { | |
4644 | /* This is a floating point value that fits entirely | |
4645 | in a single register. */ | |
53a5351d | 4646 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 4647 | above to ensure that it is even register aligned. */ |
a8852dc5 | 4648 | LONGEST regval = extract_signed_integer (val, len, byte_order); |
9ace0497 | 4649 | if (mips_debug) |
acdb74a0 | 4650 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 4651 | float_argreg, phex (regval, len)); |
a8852dc5 | 4652 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
4653 | } |
4654 | } | |
4655 | else | |
4656 | { | |
4657 | /* Copy the argument to general registers or the stack in | |
4658 | register-sized pieces. Large arguments are split between | |
4659 | registers and stack. */ | |
b3464d03 | 4660 | /* Note: structs whose size is not a multiple of abi_regsize |
1a69e1e4 | 4661 | are treated specially: Irix cc passes |
d5ac5a39 AC |
4662 | them in registers where gcc sometimes puts them on the |
4663 | stack. For maximum compatibility, we will put them in | |
4664 | both places. */ | |
b3464d03 | 4665 | int odd_sized_struct = (len > abi_regsize && len % abi_regsize != 0); |
46e0f506 | 4666 | |
f09ded24 | 4667 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 4668 | register are only written to memory. */ |
c906108c SS |
4669 | while (len > 0) |
4670 | { | |
ebafbe83 | 4671 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 4672 | int stack_used_p = 0; |
b3464d03 | 4673 | int partial_len = (len < abi_regsize ? len : abi_regsize); |
c906108c | 4674 | |
acdb74a0 AC |
4675 | if (mips_debug) |
4676 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4677 | partial_len); | |
4678 | ||
566f0f7a | 4679 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 4680 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
f09ded24 | 4681 | || odd_sized_struct |
74ed0bb4 | 4682 | || fp_register_arg_p (gdbarch, typecode, arg_type)) |
c906108c | 4683 | { |
c906108c | 4684 | /* Should shorter than int integer values be |
025bb325 | 4685 | promoted to int before being stored? */ |
c906108c | 4686 | int longword_offset = 0; |
9ace0497 | 4687 | CORE_ADDR addr; |
566f0f7a | 4688 | stack_used_p = 1; |
72a155b4 | 4689 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
7a292a7a | 4690 | { |
b3464d03 | 4691 | if (abi_regsize == 8 |
480d3dd2 AC |
4692 | && (typecode == TYPE_CODE_INT |
4693 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 4694 | || typecode == TYPE_CODE_FLT) && len <= 4) |
b3464d03 | 4695 | longword_offset = abi_regsize - len; |
480d3dd2 AC |
4696 | else if ((typecode == TYPE_CODE_STRUCT |
4697 | || typecode == TYPE_CODE_UNION) | |
b3464d03 PA |
4698 | && TYPE_LENGTH (arg_type) < abi_regsize) |
4699 | longword_offset = abi_regsize - len; | |
7a292a7a | 4700 | } |
c5aa993b | 4701 | |
9ace0497 AC |
4702 | if (mips_debug) |
4703 | { | |
5af949e3 UW |
4704 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
4705 | paddress (gdbarch, stack_offset)); | |
4706 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
4707 | paddress (gdbarch, longword_offset)); | |
9ace0497 | 4708 | } |
361d1df0 | 4709 | |
9ace0497 AC |
4710 | addr = sp + stack_offset + longword_offset; |
4711 | ||
4712 | if (mips_debug) | |
4713 | { | |
4714 | int i; | |
5af949e3 UW |
4715 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
4716 | paddress (gdbarch, addr)); | |
9ace0497 AC |
4717 | for (i = 0; i < partial_len; i++) |
4718 | { | |
6d82d43b | 4719 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 4720 | val[i] & 0xff); |
9ace0497 AC |
4721 | } |
4722 | } | |
4723 | write_memory (addr, val, partial_len); | |
c906108c SS |
4724 | } |
4725 | ||
f09ded24 AC |
4726 | /* Note!!! This is NOT an else clause. Odd sized |
4727 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 4728 | arguments will not. */ |
566f0f7a | 4729 | /* Write this portion of the argument to a general |
6d82d43b | 4730 | purpose register. */ |
74ed0bb4 MD |
4731 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch) |
4732 | && !fp_register_arg_p (gdbarch, typecode, arg_type)) | |
c906108c | 4733 | { |
6d82d43b | 4734 | LONGEST regval = |
a8852dc5 | 4735 | extract_signed_integer (val, partial_len, byte_order); |
c906108c | 4736 | |
9ace0497 | 4737 | if (mips_debug) |
acdb74a0 | 4738 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 4739 | argreg, |
b3464d03 | 4740 | phex (regval, abi_regsize)); |
a8852dc5 | 4741 | regcache_cooked_write_signed (regcache, argreg, regval); |
c906108c | 4742 | argreg++; |
c906108c | 4743 | } |
c5aa993b | 4744 | |
c906108c SS |
4745 | len -= partial_len; |
4746 | val += partial_len; | |
4747 | ||
b021a221 MS |
4748 | /* Compute the offset into the stack at which we will |
4749 | copy the next parameter. | |
566f0f7a | 4750 | |
566f0f7a | 4751 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 4752 | only needs to be adjusted when it has been used. */ |
c906108c | 4753 | |
46e0f506 | 4754 | if (stack_used_p) |
b3464d03 | 4755 | stack_offset += align_up (partial_len, abi_regsize); |
c906108c SS |
4756 | } |
4757 | } | |
9ace0497 AC |
4758 | if (mips_debug) |
4759 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
4760 | } |
4761 | ||
f10683bb | 4762 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4763 | |
0f71a2f6 JM |
4764 | /* Return adjusted stack pointer. */ |
4765 | return sp; | |
4766 | } | |
4767 | ||
a1f5b845 | 4768 | /* Determine the return value convention being used. */ |
6d82d43b | 4769 | |
9c8fdbfa | 4770 | static enum return_value_convention |
6a3a010b | 4771 | mips_eabi_return_value (struct gdbarch *gdbarch, struct value *function, |
9c8fdbfa | 4772 | struct type *type, struct regcache *regcache, |
47a35522 | 4773 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 4774 | { |
609ba780 JM |
4775 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4776 | int fp_return_type = 0; | |
4777 | int offset, regnum, xfer; | |
4778 | ||
9c8fdbfa AC |
4779 | if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
4780 | return RETURN_VALUE_STRUCT_CONVENTION; | |
609ba780 JM |
4781 | |
4782 | /* Floating point type? */ | |
4783 | if (tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4784 | { | |
4785 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
4786 | fp_return_type = 1; | |
4787 | /* Structs with a single field of float type | |
4788 | are returned in a floating point register. */ | |
4789 | if ((TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4790 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4791 | && TYPE_NFIELDS (type) == 1) | |
4792 | { | |
4793 | struct type *fieldtype = TYPE_FIELD_TYPE (type, 0); | |
4794 | ||
4795 | if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT) | |
4796 | fp_return_type = 1; | |
4797 | } | |
4798 | } | |
4799 | ||
4800 | if (fp_return_type) | |
4801 | { | |
4802 | /* A floating-point value belongs in the least significant part | |
4803 | of FP0/FP1. */ | |
4804 | if (mips_debug) | |
4805 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
4806 | regnum = mips_regnum (gdbarch)->fp0; | |
4807 | } | |
4808 | else | |
4809 | { | |
4810 | /* An integer value goes in V0/V1. */ | |
4811 | if (mips_debug) | |
4812 | fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n"); | |
4813 | regnum = MIPS_V0_REGNUM; | |
4814 | } | |
4815 | for (offset = 0; | |
4816 | offset < TYPE_LENGTH (type); | |
4817 | offset += mips_abi_regsize (gdbarch), regnum++) | |
4818 | { | |
4819 | xfer = mips_abi_regsize (gdbarch); | |
4820 | if (offset + xfer > TYPE_LENGTH (type)) | |
4821 | xfer = TYPE_LENGTH (type) - offset; | |
4822 | mips_xfer_register (gdbarch, regcache, | |
4823 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
4824 | gdbarch_byte_order (gdbarch), readbuf, writebuf, | |
4825 | offset); | |
4826 | } | |
4827 | ||
9c8fdbfa | 4828 | return RETURN_VALUE_REGISTER_CONVENTION; |
6d82d43b AC |
4829 | } |
4830 | ||
6d82d43b AC |
4831 | |
4832 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 4833 | |
8d26208a DJ |
4834 | /* Search for a naturally aligned double at OFFSET inside a struct |
4835 | ARG_TYPE. The N32 / N64 ABIs pass these in floating point | |
4836 | registers. */ | |
4837 | ||
4838 | static int | |
74ed0bb4 MD |
4839 | mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type, |
4840 | int offset) | |
8d26208a DJ |
4841 | { |
4842 | int i; | |
4843 | ||
4844 | if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT) | |
4845 | return 0; | |
4846 | ||
74ed0bb4 | 4847 | if (MIPS_FPU_TYPE (gdbarch) != MIPS_FPU_DOUBLE) |
8d26208a DJ |
4848 | return 0; |
4849 | ||
4850 | if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE) | |
4851 | return 0; | |
4852 | ||
4853 | for (i = 0; i < TYPE_NFIELDS (arg_type); i++) | |
4854 | { | |
4855 | int pos; | |
4856 | struct type *field_type; | |
4857 | ||
4858 | /* We're only looking at normal fields. */ | |
5bc60cfb | 4859 | if (field_is_static (&TYPE_FIELD (arg_type, i)) |
8d26208a DJ |
4860 | || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0) |
4861 | continue; | |
4862 | ||
4863 | /* If we have gone past the offset, there is no double to pass. */ | |
4864 | pos = TYPE_FIELD_BITPOS (arg_type, i) / 8; | |
4865 | if (pos > offset) | |
4866 | return 0; | |
4867 | ||
4868 | field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i)); | |
4869 | ||
4870 | /* If this field is entirely before the requested offset, go | |
4871 | on to the next one. */ | |
4872 | if (pos + TYPE_LENGTH (field_type) <= offset) | |
4873 | continue; | |
4874 | ||
4875 | /* If this is our special aligned double, we can stop. */ | |
4876 | if (TYPE_CODE (field_type) == TYPE_CODE_FLT | |
4877 | && TYPE_LENGTH (field_type) == MIPS64_REGSIZE) | |
4878 | return 1; | |
4879 | ||
4880 | /* This field starts at or before the requested offset, and | |
4881 | overlaps it. If it is a structure, recurse inwards. */ | |
74ed0bb4 | 4882 | return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos); |
8d26208a DJ |
4883 | } |
4884 | ||
4885 | return 0; | |
4886 | } | |
4887 | ||
f7ab6ec6 | 4888 | static CORE_ADDR |
7d9b040b | 4889 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4890 | struct regcache *regcache, CORE_ADDR bp_addr, |
4891 | int nargs, struct value **args, CORE_ADDR sp, | |
4892 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
4893 | { |
4894 | int argreg; | |
4895 | int float_argreg; | |
4896 | int argnum; | |
4897 | int len = 0; | |
4898 | int stack_offset = 0; | |
e17a4113 | 4899 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 4900 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 4901 | |
25ab4790 AC |
4902 | /* For shared libraries, "t9" needs to point at the function |
4903 | address. */ | |
4c7d22cb | 4904 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
4905 | |
4906 | /* Set the return address register to point to the entry point of | |
4907 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 4908 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 4909 | |
cb3d25d1 MS |
4910 | /* First ensure that the stack and structure return address (if any) |
4911 | are properly aligned. The stack has to be at least 64-bit | |
4912 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4913 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4914 | aligned, so we round to this widest known alignment. */ | |
4915 | ||
5b03f266 AC |
4916 | sp = align_down (sp, 16); |
4917 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
4918 | |
4919 | /* Now make space on the stack for the args. */ | |
4920 | for (argnum = 0; argnum < nargs; argnum++) | |
1a69e1e4 | 4921 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE); |
5b03f266 | 4922 | sp -= align_up (len, 16); |
cb3d25d1 MS |
4923 | |
4924 | if (mips_debug) | |
6d82d43b | 4925 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
4926 | "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n", |
4927 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
4928 | |
4929 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 4930 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 4931 | float_argreg = mips_fpa0_regnum (gdbarch); |
cb3d25d1 | 4932 | |
46e0f506 | 4933 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
4934 | if (struct_return) |
4935 | { | |
4936 | if (mips_debug) | |
4937 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
4938 | "mips_n32n64_push_dummy_call: " |
4939 | "struct_return reg=%d %s\n", | |
5af949e3 | 4940 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 4941 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
cb3d25d1 MS |
4942 | } |
4943 | ||
4944 | /* Now load as many as possible of the first arguments into | |
4945 | registers, and push the rest onto the stack. Loop thru args | |
4946 | from first to last. */ | |
4947 | for (argnum = 0; argnum < nargs; argnum++) | |
4948 | { | |
47a35522 | 4949 | const gdb_byte *val; |
cb3d25d1 | 4950 | struct value *arg = args[argnum]; |
4991999e | 4951 | struct type *arg_type = check_typedef (value_type (arg)); |
cb3d25d1 MS |
4952 | int len = TYPE_LENGTH (arg_type); |
4953 | enum type_code typecode = TYPE_CODE (arg_type); | |
4954 | ||
4955 | if (mips_debug) | |
4956 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4957 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
4958 | argnum + 1, len, (int) typecode); |
4959 | ||
47a35522 | 4960 | val = value_contents (arg); |
cb3d25d1 | 4961 | |
5b68030f JM |
4962 | /* A 128-bit long double value requires an even-odd pair of |
4963 | floating-point registers. */ | |
4964 | if (len == 16 | |
4965 | && fp_register_arg_p (gdbarch, typecode, arg_type) | |
4966 | && (float_argreg & 1)) | |
4967 | { | |
4968 | float_argreg++; | |
4969 | argreg++; | |
4970 | } | |
4971 | ||
74ed0bb4 MD |
4972 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
4973 | && argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) | |
cb3d25d1 MS |
4974 | { |
4975 | /* This is a floating point value that fits entirely | |
5b68030f JM |
4976 | in a single register or a pair of registers. */ |
4977 | int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE); | |
e17a4113 | 4978 | LONGEST regval = extract_unsigned_integer (val, reglen, byte_order); |
cb3d25d1 MS |
4979 | if (mips_debug) |
4980 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5b68030f | 4981 | float_argreg, phex (regval, reglen)); |
8d26208a | 4982 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); |
cb3d25d1 MS |
4983 | |
4984 | if (mips_debug) | |
4985 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5b68030f | 4986 | argreg, phex (regval, reglen)); |
9c9acae0 | 4987 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a DJ |
4988 | float_argreg++; |
4989 | argreg++; | |
5b68030f JM |
4990 | if (len == 16) |
4991 | { | |
e17a4113 UW |
4992 | regval = extract_unsigned_integer (val + reglen, |
4993 | reglen, byte_order); | |
5b68030f JM |
4994 | if (mips_debug) |
4995 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4996 | float_argreg, phex (regval, reglen)); | |
4997 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); | |
4998 | ||
4999 | if (mips_debug) | |
5000 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5001 | argreg, phex (regval, reglen)); | |
5002 | regcache_cooked_write_unsigned (regcache, argreg, regval); | |
5003 | float_argreg++; | |
5004 | argreg++; | |
5005 | } | |
cb3d25d1 MS |
5006 | } |
5007 | else | |
5008 | { | |
5009 | /* Copy the argument to general registers or the stack in | |
5010 | register-sized pieces. Large arguments are split between | |
5011 | registers and stack. */ | |
ab2e1992 MR |
5012 | /* For N32/N64, structs, unions, or other composite types are |
5013 | treated as a sequence of doublewords, and are passed in integer | |
5014 | or floating point registers as though they were simple scalar | |
5015 | parameters to the extent that they fit, with any excess on the | |
5016 | stack packed according to the normal memory layout of the | |
5017 | object. | |
5018 | The caller does not reserve space for the register arguments; | |
5019 | the callee is responsible for reserving it if required. */ | |
cb3d25d1 | 5020 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 5021 | register are only written to memory. */ |
cb3d25d1 MS |
5022 | while (len > 0) |
5023 | { | |
ad018eee | 5024 | /* Remember if the argument was written to the stack. */ |
cb3d25d1 | 5025 | int stack_used_p = 0; |
1a69e1e4 | 5026 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
cb3d25d1 MS |
5027 | |
5028 | if (mips_debug) | |
5029 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
5030 | partial_len); | |
5031 | ||
74ed0bb4 MD |
5032 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
5033 | gdb_assert (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)); | |
8d26208a | 5034 | |
cb3d25d1 | 5035 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 5036 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 MS |
5037 | { |
5038 | /* Should shorter than int integer values be | |
025bb325 | 5039 | promoted to int before being stored? */ |
cb3d25d1 MS |
5040 | int longword_offset = 0; |
5041 | CORE_ADDR addr; | |
5042 | stack_used_p = 1; | |
72a155b4 | 5043 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
cb3d25d1 | 5044 | { |
1a69e1e4 | 5045 | if ((typecode == TYPE_CODE_INT |
5b68030f | 5046 | || typecode == TYPE_CODE_PTR) |
1a69e1e4 DJ |
5047 | && len <= 4) |
5048 | longword_offset = MIPS64_REGSIZE - len; | |
cb3d25d1 MS |
5049 | } |
5050 | ||
5051 | if (mips_debug) | |
5052 | { | |
5af949e3 UW |
5053 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
5054 | paddress (gdbarch, stack_offset)); | |
5055 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
5056 | paddress (gdbarch, longword_offset)); | |
cb3d25d1 MS |
5057 | } |
5058 | ||
5059 | addr = sp + stack_offset + longword_offset; | |
5060 | ||
5061 | if (mips_debug) | |
5062 | { | |
5063 | int i; | |
5af949e3 UW |
5064 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
5065 | paddress (gdbarch, addr)); | |
cb3d25d1 MS |
5066 | for (i = 0; i < partial_len; i++) |
5067 | { | |
6d82d43b | 5068 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
5069 | val[i] & 0xff); |
5070 | } | |
5071 | } | |
5072 | write_memory (addr, val, partial_len); | |
5073 | } | |
5074 | ||
5075 | /* Note!!! This is NOT an else clause. Odd sized | |
8d26208a | 5076 | structs may go thru BOTH paths. */ |
cb3d25d1 | 5077 | /* Write this portion of the argument to a general |
6d82d43b | 5078 | purpose register. */ |
74ed0bb4 | 5079 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 | 5080 | { |
5863b5d5 MR |
5081 | LONGEST regval; |
5082 | ||
5083 | /* Sign extend pointers, 32-bit integers and signed | |
5084 | 16-bit and 8-bit integers; everything else is taken | |
5085 | as is. */ | |
5086 | ||
5087 | if ((partial_len == 4 | |
5088 | && (typecode == TYPE_CODE_PTR | |
5089 | || typecode == TYPE_CODE_INT)) | |
5090 | || (partial_len < 4 | |
5091 | && typecode == TYPE_CODE_INT | |
5092 | && !TYPE_UNSIGNED (arg_type))) | |
e17a4113 UW |
5093 | regval = extract_signed_integer (val, partial_len, |
5094 | byte_order); | |
5863b5d5 | 5095 | else |
e17a4113 UW |
5096 | regval = extract_unsigned_integer (val, partial_len, |
5097 | byte_order); | |
cb3d25d1 MS |
5098 | |
5099 | /* A non-floating-point argument being passed in a | |
5100 | general register. If a struct or union, and if | |
5101 | the remaining length is smaller than the register | |
5102 | size, we have to adjust the register value on | |
5103 | big endian targets. | |
5104 | ||
5105 | It does not seem to be necessary to do the | |
1a69e1e4 | 5106 | same for integral types. */ |
cb3d25d1 | 5107 | |
72a155b4 | 5108 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 5109 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
5110 | && (typecode == TYPE_CODE_STRUCT |
5111 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 5112 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 5113 | * TARGET_CHAR_BIT); |
cb3d25d1 MS |
5114 | |
5115 | if (mips_debug) | |
5116 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
5117 | argreg, | |
1a69e1e4 | 5118 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 5119 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a | 5120 | |
74ed0bb4 | 5121 | if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type, |
8d26208a DJ |
5122 | TYPE_LENGTH (arg_type) - len)) |
5123 | { | |
5124 | if (mips_debug) | |
5125 | fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s", | |
5126 | float_argreg, | |
5127 | phex (regval, MIPS64_REGSIZE)); | |
5128 | regcache_cooked_write_unsigned (regcache, float_argreg, | |
5129 | regval); | |
5130 | } | |
5131 | ||
5132 | float_argreg++; | |
cb3d25d1 MS |
5133 | argreg++; |
5134 | } | |
5135 | ||
5136 | len -= partial_len; | |
5137 | val += partial_len; | |
5138 | ||
b021a221 MS |
5139 | /* Compute the offset into the stack at which we will |
5140 | copy the next parameter. | |
cb3d25d1 MS |
5141 | |
5142 | In N32 (N64?), the stack_offset only needs to be | |
5143 | adjusted when it has been used. */ | |
5144 | ||
5145 | if (stack_used_p) | |
1a69e1e4 | 5146 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
cb3d25d1 MS |
5147 | } |
5148 | } | |
5149 | if (mips_debug) | |
5150 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
5151 | } | |
5152 | ||
f10683bb | 5153 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 5154 | |
cb3d25d1 MS |
5155 | /* Return adjusted stack pointer. */ |
5156 | return sp; | |
5157 | } | |
5158 | ||
6d82d43b | 5159 | static enum return_value_convention |
6a3a010b | 5160 | mips_n32n64_return_value (struct gdbarch *gdbarch, struct value *function, |
6d82d43b | 5161 | struct type *type, struct regcache *regcache, |
47a35522 | 5162 | gdb_byte *readbuf, const gdb_byte *writebuf) |
ebafbe83 | 5163 | { |
72a155b4 | 5164 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
b18bb924 MR |
5165 | |
5166 | /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004 | |
5167 | ||
5168 | Function results are returned in $2 (and $3 if needed), or $f0 (and $f2 | |
5169 | if needed), as appropriate for the type. Composite results (struct, | |
5170 | union, or array) are returned in $2/$f0 and $3/$f2 according to the | |
5171 | following rules: | |
5172 | ||
5173 | * A struct with only one or two floating point fields is returned in $f0 | |
5174 | (and $f2 if necessary). This is a generalization of the Fortran COMPLEX | |
5175 | case. | |
5176 | ||
f08877ba | 5177 | * Any other composite results of at most 128 bits are returned in |
b18bb924 MR |
5178 | $2 (first 64 bits) and $3 (remainder, if necessary). |
5179 | ||
5180 | * Larger composite results are handled by converting the function to a | |
5181 | procedure with an implicit first parameter, which is a pointer to an area | |
5182 | reserved by the caller to receive the result. [The o32-bit ABI requires | |
5183 | that all composite results be handled by conversion to implicit first | |
5184 | parameters. The MIPS/SGI Fortran implementation has always made a | |
5185 | specific exception to return COMPLEX results in the floating point | |
5186 | registers.] */ | |
5187 | ||
f08877ba | 5188 | if (TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE) |
6d82d43b | 5189 | return RETURN_VALUE_STRUCT_CONVENTION; |
d05f6826 DJ |
5190 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
5191 | && TYPE_LENGTH (type) == 16 | |
5192 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5193 | { | |
5194 | /* A 128-bit floating-point value fills both $f0 and $f2. The | |
5195 | two registers are used in the same as memory order, so the | |
5196 | eight bytes with the lower memory address are in $f0. */ | |
5197 | if (mips_debug) | |
5198 | fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n"); | |
ba32f989 | 5199 | mips_xfer_register (gdbarch, regcache, |
dca9aa3a MR |
5200 | (gdbarch_num_regs (gdbarch) |
5201 | + mips_regnum (gdbarch)->fp0), | |
72a155b4 | 5202 | 8, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5203 | readbuf, writebuf, 0); |
ba32f989 | 5204 | mips_xfer_register (gdbarch, regcache, |
dca9aa3a MR |
5205 | (gdbarch_num_regs (gdbarch) |
5206 | + mips_regnum (gdbarch)->fp0 + 2), | |
72a155b4 | 5207 | 8, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5208 | readbuf ? readbuf + 8 : readbuf, |
d05f6826 DJ |
5209 | writebuf ? writebuf + 8 : writebuf, 0); |
5210 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5211 | } | |
6d82d43b AC |
5212 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
5213 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5214 | { | |
59aa1faa | 5215 | /* A single or double floating-point value that fits in FP0. */ |
6d82d43b AC |
5216 | if (mips_debug) |
5217 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 5218 | mips_xfer_register (gdbarch, regcache, |
dca9aa3a MR |
5219 | (gdbarch_num_regs (gdbarch) |
5220 | + mips_regnum (gdbarch)->fp0), | |
6d82d43b | 5221 | TYPE_LENGTH (type), |
72a155b4 | 5222 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 5223 | readbuf, writebuf, 0); |
6d82d43b AC |
5224 | return RETURN_VALUE_REGISTER_CONVENTION; |
5225 | } | |
5226 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
5227 | && TYPE_NFIELDS (type) <= 2 | |
5228 | && TYPE_NFIELDS (type) >= 1 | |
5229 | && ((TYPE_NFIELDS (type) == 1 | |
b18bb924 | 5230 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b AC |
5231 | == TYPE_CODE_FLT)) |
5232 | || (TYPE_NFIELDS (type) == 2 | |
b18bb924 | 5233 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b | 5234 | == TYPE_CODE_FLT) |
b18bb924 | 5235 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1))) |
5b68030f | 5236 | == TYPE_CODE_FLT)))) |
6d82d43b AC |
5237 | { |
5238 | /* A struct that contains one or two floats. Each value is part | |
5239 | in the least significant part of their floating point | |
5b68030f | 5240 | register (or GPR, for soft float). */ |
6d82d43b AC |
5241 | int regnum; |
5242 | int field; | |
5b68030f JM |
5243 | for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE |
5244 | ? mips_regnum (gdbarch)->fp0 | |
5245 | : MIPS_V0_REGNUM); | |
6d82d43b AC |
5246 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
5247 | { | |
5248 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
5249 | / TARGET_CHAR_BIT); | |
5250 | if (mips_debug) | |
5251 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
5252 | offset); | |
5b68030f JM |
5253 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)) == 16) |
5254 | { | |
5255 | /* A 16-byte long double field goes in two consecutive | |
5256 | registers. */ | |
5257 | mips_xfer_register (gdbarch, regcache, | |
5258 | gdbarch_num_regs (gdbarch) + regnum, | |
5259 | 8, | |
5260 | gdbarch_byte_order (gdbarch), | |
5261 | readbuf, writebuf, offset); | |
5262 | mips_xfer_register (gdbarch, regcache, | |
5263 | gdbarch_num_regs (gdbarch) + regnum + 1, | |
5264 | 8, | |
5265 | gdbarch_byte_order (gdbarch), | |
5266 | readbuf, writebuf, offset + 8); | |
5267 | } | |
5268 | else | |
5269 | mips_xfer_register (gdbarch, regcache, | |
5270 | gdbarch_num_regs (gdbarch) + regnum, | |
5271 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
5272 | gdbarch_byte_order (gdbarch), | |
5273 | readbuf, writebuf, offset); | |
6d82d43b AC |
5274 | } |
5275 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5276 | } | |
5277 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
f08877ba JB |
5278 | || TYPE_CODE (type) == TYPE_CODE_UNION |
5279 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
6d82d43b | 5280 | { |
f08877ba | 5281 | /* A composite type. Extract the left justified value, |
6d82d43b AC |
5282 | regardless of the byte order. I.e. DO NOT USE |
5283 | mips_xfer_lower. */ | |
5284 | int offset; | |
5285 | int regnum; | |
4c7d22cb | 5286 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 5287 | offset < TYPE_LENGTH (type); |
72a155b4 | 5288 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 5289 | { |
72a155b4 | 5290 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
5291 | if (offset + xfer > TYPE_LENGTH (type)) |
5292 | xfer = TYPE_LENGTH (type) - offset; | |
5293 | if (mips_debug) | |
5294 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
5295 | offset, xfer, regnum); | |
ba32f989 DJ |
5296 | mips_xfer_register (gdbarch, regcache, |
5297 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 UW |
5298 | xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf, |
5299 | offset); | |
6d82d43b AC |
5300 | } |
5301 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5302 | } | |
5303 | else | |
5304 | { | |
5305 | /* A scalar extract each part but least-significant-byte | |
5306 | justified. */ | |
5307 | int offset; | |
5308 | int regnum; | |
4c7d22cb | 5309 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 5310 | offset < TYPE_LENGTH (type); |
72a155b4 | 5311 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 5312 | { |
72a155b4 | 5313 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
5314 | if (offset + xfer > TYPE_LENGTH (type)) |
5315 | xfer = TYPE_LENGTH (type) - offset; | |
5316 | if (mips_debug) | |
5317 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
5318 | offset, xfer, regnum); | |
ba32f989 DJ |
5319 | mips_xfer_register (gdbarch, regcache, |
5320 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 5321 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5322 | readbuf, writebuf, offset); |
6d82d43b AC |
5323 | } |
5324 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5325 | } | |
5326 | } | |
5327 | ||
6a3a010b MR |
5328 | /* Which registers to use for passing floating-point values between |
5329 | function calls, one of floating-point, general and both kinds of | |
5330 | registers. O32 and O64 use different register kinds for standard | |
5331 | MIPS and MIPS16 code; to make the handling of cases where we may | |
5332 | not know what kind of code is being used (e.g. no debug information) | |
5333 | easier we sometimes use both kinds. */ | |
5334 | ||
5335 | enum mips_fval_reg | |
5336 | { | |
5337 | mips_fval_fpr, | |
5338 | mips_fval_gpr, | |
5339 | mips_fval_both | |
5340 | }; | |
5341 | ||
6d82d43b AC |
5342 | /* O32 ABI stuff. */ |
5343 | ||
5344 | static CORE_ADDR | |
7d9b040b | 5345 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
5346 | struct regcache *regcache, CORE_ADDR bp_addr, |
5347 | int nargs, struct value **args, CORE_ADDR sp, | |
5348 | int struct_return, CORE_ADDR struct_addr) | |
5349 | { | |
5350 | int argreg; | |
5351 | int float_argreg; | |
5352 | int argnum; | |
5353 | int len = 0; | |
5354 | int stack_offset = 0; | |
e17a4113 | 5355 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 5356 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
5357 | |
5358 | /* For shared libraries, "t9" needs to point at the function | |
5359 | address. */ | |
4c7d22cb | 5360 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
6d82d43b AC |
5361 | |
5362 | /* Set the return address register to point to the entry point of | |
5363 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 5364 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
6d82d43b AC |
5365 | |
5366 | /* First ensure that the stack and structure return address (if any) | |
5367 | are properly aligned. The stack has to be at least 64-bit | |
5368 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
5369 | aligned. For n32 and n64, stack frames need to be 128-bit |
5370 | aligned, so we round to this widest known alignment. */ | |
5371 | ||
5b03f266 AC |
5372 | sp = align_down (sp, 16); |
5373 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
5374 | |
5375 | /* Now make space on the stack for the args. */ | |
5376 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
5377 | { |
5378 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
968b5391 MR |
5379 | |
5380 | /* Align to double-word if necessary. */ | |
2afd3f0a | 5381 | if (mips_type_needs_double_align (arg_type)) |
1a69e1e4 | 5382 | len = align_up (len, MIPS32_REGSIZE * 2); |
968b5391 | 5383 | /* Allocate space on the stack. */ |
354ecfd5 | 5384 | len += align_up (TYPE_LENGTH (arg_type), MIPS32_REGSIZE); |
968b5391 | 5385 | } |
5b03f266 | 5386 | sp -= align_up (len, 16); |
ebafbe83 MS |
5387 | |
5388 | if (mips_debug) | |
6d82d43b | 5389 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
5390 | "mips_o32_push_dummy_call: sp=%s allocated %ld\n", |
5391 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
5392 | |
5393 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 5394 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 5395 | float_argreg = mips_fpa0_regnum (gdbarch); |
ebafbe83 | 5396 | |
bcb0cc15 | 5397 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
5398 | if (struct_return) |
5399 | { | |
5400 | if (mips_debug) | |
5401 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
5402 | "mips_o32_push_dummy_call: " |
5403 | "struct_return reg=%d %s\n", | |
5af949e3 | 5404 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 5405 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 5406 | stack_offset += MIPS32_REGSIZE; |
ebafbe83 MS |
5407 | } |
5408 | ||
5409 | /* Now load as many as possible of the first arguments into | |
5410 | registers, and push the rest onto the stack. Loop thru args | |
5411 | from first to last. */ | |
5412 | for (argnum = 0; argnum < nargs; argnum++) | |
5413 | { | |
47a35522 | 5414 | const gdb_byte *val; |
ebafbe83 | 5415 | struct value *arg = args[argnum]; |
4991999e | 5416 | struct type *arg_type = check_typedef (value_type (arg)); |
ebafbe83 MS |
5417 | int len = TYPE_LENGTH (arg_type); |
5418 | enum type_code typecode = TYPE_CODE (arg_type); | |
5419 | ||
5420 | if (mips_debug) | |
5421 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 5422 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
5423 | argnum + 1, len, (int) typecode); |
5424 | ||
47a35522 | 5425 | val = value_contents (arg); |
46cac009 AC |
5426 | |
5427 | /* 32-bit ABIs always start floating point arguments in an | |
5428 | even-numbered floating point register. Round the FP register | |
5429 | up before the check to see if there are any FP registers | |
6a3a010b MR |
5430 | left. O32 targets also pass the FP in the integer registers |
5431 | so also round up normal registers. */ | |
74ed0bb4 | 5432 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
46cac009 AC |
5433 | { |
5434 | if ((float_argreg & 1)) | |
5435 | float_argreg++; | |
5436 | } | |
5437 | ||
5438 | /* Floating point arguments passed in registers have to be | |
6a3a010b MR |
5439 | treated specially. On 32-bit architectures, doubles are |
5440 | passed in register pairs; the even FP register gets the | |
5441 | low word, and the odd FP register gets the high word. | |
5442 | On O32, the first two floating point arguments are also | |
5443 | copied to general registers, following their memory order, | |
5444 | because MIPS16 functions don't use float registers for | |
5445 | arguments. This duplication of arguments in general | |
5446 | registers can't hurt non-MIPS16 functions, because those | |
5447 | registers are normally skipped. */ | |
46cac009 | 5448 | |
74ed0bb4 MD |
5449 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
5450 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
46cac009 | 5451 | { |
8b07f6d8 | 5452 | if (register_size (gdbarch, float_argreg) < 8 && len == 8) |
46cac009 | 5453 | { |
6a3a010b MR |
5454 | int freg_offset = gdbarch_byte_order (gdbarch) |
5455 | == BFD_ENDIAN_BIG ? 1 : 0; | |
46cac009 AC |
5456 | unsigned long regval; |
5457 | ||
6a3a010b MR |
5458 | /* First word. */ |
5459 | regval = extract_unsigned_integer (val, 4, byte_order); | |
46cac009 AC |
5460 | if (mips_debug) |
5461 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
6a3a010b MR |
5462 | float_argreg + freg_offset, |
5463 | phex (regval, 4)); | |
025bb325 | 5464 | regcache_cooked_write_unsigned (regcache, |
6a3a010b MR |
5465 | float_argreg++ + freg_offset, |
5466 | regval); | |
46cac009 AC |
5467 | if (mips_debug) |
5468 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5469 | argreg, phex (regval, 4)); | |
9c9acae0 | 5470 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 | 5471 | |
6a3a010b MR |
5472 | /* Second word. */ |
5473 | regval = extract_unsigned_integer (val + 4, 4, byte_order); | |
46cac009 AC |
5474 | if (mips_debug) |
5475 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
6a3a010b MR |
5476 | float_argreg - freg_offset, |
5477 | phex (regval, 4)); | |
025bb325 | 5478 | regcache_cooked_write_unsigned (regcache, |
6a3a010b MR |
5479 | float_argreg++ - freg_offset, |
5480 | regval); | |
46cac009 AC |
5481 | if (mips_debug) |
5482 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5483 | argreg, phex (regval, 4)); | |
9c9acae0 | 5484 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
5485 | } |
5486 | else | |
5487 | { | |
5488 | /* This is a floating point value that fits entirely | |
5489 | in a single register. */ | |
5490 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 5491 | above to ensure that it is even register aligned. */ |
e17a4113 | 5492 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
46cac009 AC |
5493 | if (mips_debug) |
5494 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5495 | float_argreg, phex (regval, len)); | |
025bb325 MS |
5496 | regcache_cooked_write_unsigned (regcache, |
5497 | float_argreg++, regval); | |
5b68030f JM |
5498 | /* Although two FP registers are reserved for each |
5499 | argument, only one corresponding integer register is | |
5500 | reserved. */ | |
46cac009 AC |
5501 | if (mips_debug) |
5502 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5503 | argreg, phex (regval, len)); | |
5b68030f | 5504 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
5505 | } |
5506 | /* Reserve space for the FP register. */ | |
1a69e1e4 | 5507 | stack_offset += align_up (len, MIPS32_REGSIZE); |
46cac009 AC |
5508 | } |
5509 | else | |
5510 | { | |
5511 | /* Copy the argument to general registers or the stack in | |
5512 | register-sized pieces. Large arguments are split between | |
5513 | registers and stack. */ | |
1a69e1e4 DJ |
5514 | /* Note: structs whose size is not a multiple of MIPS32_REGSIZE |
5515 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
5516 | them in registers where gcc sometimes puts them on the |
5517 | stack. For maximum compatibility, we will put them in | |
5518 | both places. */ | |
1a69e1e4 DJ |
5519 | int odd_sized_struct = (len > MIPS32_REGSIZE |
5520 | && len % MIPS32_REGSIZE != 0); | |
46cac009 AC |
5521 | /* Structures should be aligned to eight bytes (even arg registers) |
5522 | on MIPS_ABI_O32, if their first member has double precision. */ | |
2afd3f0a | 5523 | if (mips_type_needs_double_align (arg_type)) |
46cac009 AC |
5524 | { |
5525 | if ((argreg & 1)) | |
968b5391 MR |
5526 | { |
5527 | argreg++; | |
1a69e1e4 | 5528 | stack_offset += MIPS32_REGSIZE; |
968b5391 | 5529 | } |
46cac009 | 5530 | } |
46cac009 AC |
5531 | while (len > 0) |
5532 | { | |
1a69e1e4 | 5533 | int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); |
46cac009 AC |
5534 | |
5535 | if (mips_debug) | |
5536 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
5537 | partial_len); | |
5538 | ||
5539 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 5540 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 5541 | || odd_sized_struct) |
46cac009 AC |
5542 | { |
5543 | /* Should shorter than int integer values be | |
025bb325 | 5544 | promoted to int before being stored? */ |
46cac009 AC |
5545 | int longword_offset = 0; |
5546 | CORE_ADDR addr; | |
46cac009 AC |
5547 | |
5548 | if (mips_debug) | |
5549 | { | |
5af949e3 UW |
5550 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
5551 | paddress (gdbarch, stack_offset)); | |
5552 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
5553 | paddress (gdbarch, longword_offset)); | |
46cac009 AC |
5554 | } |
5555 | ||
5556 | addr = sp + stack_offset + longword_offset; | |
5557 | ||
5558 | if (mips_debug) | |
5559 | { | |
5560 | int i; | |
5af949e3 UW |
5561 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
5562 | paddress (gdbarch, addr)); | |
46cac009 AC |
5563 | for (i = 0; i < partial_len; i++) |
5564 | { | |
6d82d43b | 5565 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
5566 | val[i] & 0xff); |
5567 | } | |
5568 | } | |
5569 | write_memory (addr, val, partial_len); | |
5570 | } | |
5571 | ||
5572 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 5573 | structs may go thru BOTH paths. */ |
46cac009 | 5574 | /* Write this portion of the argument to a general |
6d82d43b | 5575 | purpose register. */ |
74ed0bb4 | 5576 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
46cac009 | 5577 | { |
e17a4113 UW |
5578 | LONGEST regval = extract_signed_integer (val, partial_len, |
5579 | byte_order); | |
4246e332 | 5580 | /* Value may need to be sign extended, because |
1b13c4f6 | 5581 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
5582 | |
5583 | /* A non-floating-point argument being passed in a | |
5584 | general register. If a struct or union, and if | |
5585 | the remaining length is smaller than the register | |
5586 | size, we have to adjust the register value on | |
5587 | big endian targets. | |
5588 | ||
5589 | It does not seem to be necessary to do the | |
5590 | same for integral types. | |
5591 | ||
5592 | Also don't do this adjustment on O64 binaries. | |
5593 | ||
5594 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
5595 | outputting LE O32 with sizeof (struct) < | |
e914cb17 MR |
5596 | mips_abi_regsize(), generates a left shift |
5597 | as part of storing the argument in a register | |
5598 | (the left shift isn't generated when | |
1b13c4f6 | 5599 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
5600 | it is quite possible that this is GCC |
5601 | contradicting the LE/O32 ABI, GDB has not been | |
5602 | adjusted to accommodate this. Either someone | |
5603 | needs to demonstrate that the LE/O32 ABI | |
5604 | specifies such a left shift OR this new ABI gets | |
5605 | identified as such and GDB gets tweaked | |
5606 | accordingly. */ | |
5607 | ||
72a155b4 | 5608 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 5609 | && partial_len < MIPS32_REGSIZE |
06f9a1af MR |
5610 | && (typecode == TYPE_CODE_STRUCT |
5611 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 5612 | regval <<= ((MIPS32_REGSIZE - partial_len) |
9ecf7166 | 5613 | * TARGET_CHAR_BIT); |
46cac009 AC |
5614 | |
5615 | if (mips_debug) | |
5616 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
5617 | argreg, | |
1a69e1e4 | 5618 | phex (regval, MIPS32_REGSIZE)); |
9c9acae0 | 5619 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
46cac009 AC |
5620 | argreg++; |
5621 | ||
5622 | /* Prevent subsequent floating point arguments from | |
5623 | being passed in floating point registers. */ | |
74ed0bb4 | 5624 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
46cac009 AC |
5625 | } |
5626 | ||
5627 | len -= partial_len; | |
5628 | val += partial_len; | |
5629 | ||
b021a221 MS |
5630 | /* Compute the offset into the stack at which we will |
5631 | copy the next parameter. | |
46cac009 | 5632 | |
6d82d43b AC |
5633 | In older ABIs, the caller reserved space for |
5634 | registers that contained arguments. This was loosely | |
5635 | refered to as their "home". Consequently, space is | |
5636 | always allocated. */ | |
46cac009 | 5637 | |
1a69e1e4 | 5638 | stack_offset += align_up (partial_len, MIPS32_REGSIZE); |
46cac009 AC |
5639 | } |
5640 | } | |
5641 | if (mips_debug) | |
5642 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
5643 | } | |
5644 | ||
f10683bb | 5645 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 5646 | |
46cac009 AC |
5647 | /* Return adjusted stack pointer. */ |
5648 | return sp; | |
5649 | } | |
5650 | ||
6d82d43b | 5651 | static enum return_value_convention |
6a3a010b | 5652 | mips_o32_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 | 5653 | struct type *type, struct regcache *regcache, |
47a35522 | 5654 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 5655 | { |
6a3a010b | 5656 | CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0; |
4cc0665f | 5657 | int mips16 = mips_pc_is_mips16 (gdbarch, func_addr); |
72a155b4 | 5658 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
6a3a010b | 5659 | enum mips_fval_reg fval_reg; |
6d82d43b | 5660 | |
6a3a010b | 5661 | fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both; |
6d82d43b AC |
5662 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
5663 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
5664 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
5665 | return RETURN_VALUE_STRUCT_CONVENTION; | |
5666 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
5667 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5668 | { | |
6a3a010b MR |
5669 | /* A single-precision floating-point value. If reading in or copying, |
5670 | then we get it from/put it to FP0 for standard MIPS code or GPR2 | |
5671 | for MIPS16 code. If writing out only, then we put it to both FP0 | |
5672 | and GPR2. We do not support reading in with no function known, if | |
5673 | this safety check ever triggers, then we'll have to try harder. */ | |
5674 | gdb_assert (function || !readbuf); | |
6d82d43b | 5675 | if (mips_debug) |
6a3a010b MR |
5676 | switch (fval_reg) |
5677 | { | |
5678 | case mips_fval_fpr: | |
5679 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
5680 | break; | |
5681 | case mips_fval_gpr: | |
5682 | fprintf_unfiltered (gdb_stderr, "Return float in $2\n"); | |
5683 | break; | |
5684 | case mips_fval_both: | |
5685 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n"); | |
5686 | break; | |
5687 | } | |
5688 | if (fval_reg != mips_fval_gpr) | |
5689 | mips_xfer_register (gdbarch, regcache, | |
5690 | (gdbarch_num_regs (gdbarch) | |
5691 | + mips_regnum (gdbarch)->fp0), | |
5692 | TYPE_LENGTH (type), | |
5693 | gdbarch_byte_order (gdbarch), | |
5694 | readbuf, writebuf, 0); | |
5695 | if (fval_reg != mips_fval_fpr) | |
5696 | mips_xfer_register (gdbarch, regcache, | |
5697 | gdbarch_num_regs (gdbarch) + 2, | |
5698 | TYPE_LENGTH (type), | |
5699 | gdbarch_byte_order (gdbarch), | |
5700 | readbuf, writebuf, 0); | |
6d82d43b AC |
5701 | return RETURN_VALUE_REGISTER_CONVENTION; |
5702 | } | |
5703 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
5704 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5705 | { | |
6a3a010b MR |
5706 | /* A double-precision floating-point value. If reading in or copying, |
5707 | then we get it from/put it to FP1 and FP0 for standard MIPS code or | |
5708 | GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it | |
5709 | to both FP1/FP0 and GPR2/GPR3. We do not support reading in with | |
5710 | no function known, if this safety check ever triggers, then we'll | |
5711 | have to try harder. */ | |
5712 | gdb_assert (function || !readbuf); | |
6d82d43b | 5713 | if (mips_debug) |
6a3a010b MR |
5714 | switch (fval_reg) |
5715 | { | |
5716 | case mips_fval_fpr: | |
5717 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
5718 | break; | |
5719 | case mips_fval_gpr: | |
5720 | fprintf_unfiltered (gdb_stderr, "Return float in $2/$3\n"); | |
5721 | break; | |
5722 | case mips_fval_both: | |
5723 | fprintf_unfiltered (gdb_stderr, | |
5724 | "Return float in $fp1/$fp0 and $2/$3\n"); | |
5725 | break; | |
5726 | } | |
5727 | if (fval_reg != mips_fval_gpr) | |
6d82d43b | 5728 | { |
6a3a010b MR |
5729 | /* The most significant part goes in FP1, and the least significant |
5730 | in FP0. */ | |
5731 | switch (gdbarch_byte_order (gdbarch)) | |
5732 | { | |
5733 | case BFD_ENDIAN_LITTLE: | |
5734 | mips_xfer_register (gdbarch, regcache, | |
5735 | (gdbarch_num_regs (gdbarch) | |
5736 | + mips_regnum (gdbarch)->fp0 + 0), | |
5737 | 4, gdbarch_byte_order (gdbarch), | |
5738 | readbuf, writebuf, 0); | |
5739 | mips_xfer_register (gdbarch, regcache, | |
5740 | (gdbarch_num_regs (gdbarch) | |
5741 | + mips_regnum (gdbarch)->fp0 + 1), | |
5742 | 4, gdbarch_byte_order (gdbarch), | |
5743 | readbuf, writebuf, 4); | |
5744 | break; | |
5745 | case BFD_ENDIAN_BIG: | |
5746 | mips_xfer_register (gdbarch, regcache, | |
5747 | (gdbarch_num_regs (gdbarch) | |
5748 | + mips_regnum (gdbarch)->fp0 + 1), | |
5749 | 4, gdbarch_byte_order (gdbarch), | |
5750 | readbuf, writebuf, 0); | |
5751 | mips_xfer_register (gdbarch, regcache, | |
5752 | (gdbarch_num_regs (gdbarch) | |
5753 | + mips_regnum (gdbarch)->fp0 + 0), | |
5754 | 4, gdbarch_byte_order (gdbarch), | |
5755 | readbuf, writebuf, 4); | |
5756 | break; | |
5757 | default: | |
5758 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
5759 | } | |
5760 | } | |
5761 | if (fval_reg != mips_fval_fpr) | |
5762 | { | |
5763 | /* The two 32-bit parts are always placed in GPR2 and GPR3 | |
5764 | following these registers' memory order. */ | |
ba32f989 | 5765 | mips_xfer_register (gdbarch, regcache, |
6a3a010b | 5766 | gdbarch_num_regs (gdbarch) + 2, |
72a155b4 | 5767 | 4, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5768 | readbuf, writebuf, 0); |
ba32f989 | 5769 | mips_xfer_register (gdbarch, regcache, |
6a3a010b | 5770 | gdbarch_num_regs (gdbarch) + 3, |
72a155b4 | 5771 | 4, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5772 | readbuf, writebuf, 4); |
6d82d43b AC |
5773 | } |
5774 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5775 | } | |
5776 | #if 0 | |
5777 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
5778 | && TYPE_NFIELDS (type) <= 2 | |
5779 | && TYPE_NFIELDS (type) >= 1 | |
5780 | && ((TYPE_NFIELDS (type) == 1 | |
5781 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
5782 | == TYPE_CODE_FLT)) | |
5783 | || (TYPE_NFIELDS (type) == 2 | |
5784 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
5785 | == TYPE_CODE_FLT) | |
5786 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
5787 | == TYPE_CODE_FLT))) | |
5788 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5789 | { | |
5790 | /* A struct that contains one or two floats. Each value is part | |
5791 | in the least significant part of their floating point | |
5792 | register.. */ | |
6d82d43b AC |
5793 | int regnum; |
5794 | int field; | |
72a155b4 | 5795 | for (field = 0, regnum = mips_regnum (gdbarch)->fp0; |
6d82d43b AC |
5796 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
5797 | { | |
5798 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
5799 | / TARGET_CHAR_BIT); | |
5800 | if (mips_debug) | |
5801 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
5802 | offset); | |
ba32f989 DJ |
5803 | mips_xfer_register (gdbarch, regcache, |
5804 | gdbarch_num_regs (gdbarch) + regnum, | |
6d82d43b | 5805 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
72a155b4 | 5806 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 5807 | readbuf, writebuf, offset); |
6d82d43b AC |
5808 | } |
5809 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5810 | } | |
5811 | #endif | |
5812 | #if 0 | |
5813 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
5814 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
5815 | { | |
5816 | /* A structure or union. Extract the left justified value, | |
5817 | regardless of the byte order. I.e. DO NOT USE | |
5818 | mips_xfer_lower. */ | |
5819 | int offset; | |
5820 | int regnum; | |
4c7d22cb | 5821 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 5822 | offset < TYPE_LENGTH (type); |
72a155b4 | 5823 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 5824 | { |
72a155b4 | 5825 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
5826 | if (offset + xfer > TYPE_LENGTH (type)) |
5827 | xfer = TYPE_LENGTH (type) - offset; | |
5828 | if (mips_debug) | |
5829 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
5830 | offset, xfer, regnum); | |
ba32f989 DJ |
5831 | mips_xfer_register (gdbarch, regcache, |
5832 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
6d82d43b AC |
5833 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
5834 | } | |
5835 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5836 | } | |
5837 | #endif | |
5838 | else | |
5839 | { | |
5840 | /* A scalar extract each part but least-significant-byte | |
5841 | justified. o32 thinks registers are 4 byte, regardless of | |
1a69e1e4 | 5842 | the ISA. */ |
6d82d43b AC |
5843 | int offset; |
5844 | int regnum; | |
4c7d22cb | 5845 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 5846 | offset < TYPE_LENGTH (type); |
1a69e1e4 | 5847 | offset += MIPS32_REGSIZE, regnum++) |
6d82d43b | 5848 | { |
1a69e1e4 | 5849 | int xfer = MIPS32_REGSIZE; |
6d82d43b AC |
5850 | if (offset + xfer > TYPE_LENGTH (type)) |
5851 | xfer = TYPE_LENGTH (type) - offset; | |
5852 | if (mips_debug) | |
5853 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
5854 | offset, xfer, regnum); | |
ba32f989 DJ |
5855 | mips_xfer_register (gdbarch, regcache, |
5856 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
72a155b4 | 5857 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 5858 | readbuf, writebuf, offset); |
6d82d43b AC |
5859 | } |
5860 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5861 | } | |
5862 | } | |
5863 | ||
5864 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
5865 | ABI. */ | |
46cac009 AC |
5866 | |
5867 | static CORE_ADDR | |
7d9b040b | 5868 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
5869 | struct regcache *regcache, CORE_ADDR bp_addr, |
5870 | int nargs, | |
5871 | struct value **args, CORE_ADDR sp, | |
5872 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
5873 | { |
5874 | int argreg; | |
5875 | int float_argreg; | |
5876 | int argnum; | |
5877 | int len = 0; | |
5878 | int stack_offset = 0; | |
e17a4113 | 5879 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 5880 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 5881 | |
25ab4790 AC |
5882 | /* For shared libraries, "t9" needs to point at the function |
5883 | address. */ | |
4c7d22cb | 5884 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
5885 | |
5886 | /* Set the return address register to point to the entry point of | |
5887 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 5888 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 5889 | |
46cac009 AC |
5890 | /* First ensure that the stack and structure return address (if any) |
5891 | are properly aligned. The stack has to be at least 64-bit | |
5892 | aligned even on 32-bit machines, because doubles must be 64-bit | |
5893 | aligned. For n32 and n64, stack frames need to be 128-bit | |
5894 | aligned, so we round to this widest known alignment. */ | |
5895 | ||
5b03f266 AC |
5896 | sp = align_down (sp, 16); |
5897 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
5898 | |
5899 | /* Now make space on the stack for the args. */ | |
5900 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
5901 | { |
5902 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
968b5391 | 5903 | |
968b5391 | 5904 | /* Allocate space on the stack. */ |
354ecfd5 | 5905 | len += align_up (TYPE_LENGTH (arg_type), MIPS64_REGSIZE); |
968b5391 | 5906 | } |
5b03f266 | 5907 | sp -= align_up (len, 16); |
46cac009 AC |
5908 | |
5909 | if (mips_debug) | |
6d82d43b | 5910 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
5911 | "mips_o64_push_dummy_call: sp=%s allocated %ld\n", |
5912 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
46cac009 AC |
5913 | |
5914 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 5915 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 5916 | float_argreg = mips_fpa0_regnum (gdbarch); |
46cac009 AC |
5917 | |
5918 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
5919 | if (struct_return) | |
5920 | { | |
5921 | if (mips_debug) | |
5922 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
5923 | "mips_o64_push_dummy_call: " |
5924 | "struct_return reg=%d %s\n", | |
5af949e3 | 5925 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 5926 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 5927 | stack_offset += MIPS64_REGSIZE; |
46cac009 AC |
5928 | } |
5929 | ||
5930 | /* Now load as many as possible of the first arguments into | |
5931 | registers, and push the rest onto the stack. Loop thru args | |
5932 | from first to last. */ | |
5933 | for (argnum = 0; argnum < nargs; argnum++) | |
5934 | { | |
47a35522 | 5935 | const gdb_byte *val; |
46cac009 | 5936 | struct value *arg = args[argnum]; |
4991999e | 5937 | struct type *arg_type = check_typedef (value_type (arg)); |
46cac009 AC |
5938 | int len = TYPE_LENGTH (arg_type); |
5939 | enum type_code typecode = TYPE_CODE (arg_type); | |
5940 | ||
5941 | if (mips_debug) | |
5942 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 5943 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
5944 | argnum + 1, len, (int) typecode); |
5945 | ||
47a35522 | 5946 | val = value_contents (arg); |
ebafbe83 | 5947 | |
ebafbe83 | 5948 | /* Floating point arguments passed in registers have to be |
6a3a010b MR |
5949 | treated specially. On 32-bit architectures, doubles are |
5950 | passed in register pairs; the even FP register gets the | |
5951 | low word, and the odd FP register gets the high word. | |
5952 | On O64, the first two floating point arguments are also | |
5953 | copied to general registers, because MIPS16 functions | |
5954 | don't use float registers for arguments. This duplication | |
5955 | of arguments in general registers can't hurt non-MIPS16 | |
5956 | functions because those registers are normally skipped. */ | |
ebafbe83 | 5957 | |
74ed0bb4 MD |
5958 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
5959 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
ebafbe83 | 5960 | { |
e17a4113 | 5961 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
2afd3f0a MR |
5962 | if (mips_debug) |
5963 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5964 | float_argreg, phex (regval, len)); | |
9c9acae0 | 5965 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
2afd3f0a MR |
5966 | if (mips_debug) |
5967 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5968 | argreg, phex (regval, len)); | |
9c9acae0 | 5969 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
2afd3f0a | 5970 | argreg++; |
ebafbe83 | 5971 | /* Reserve space for the FP register. */ |
1a69e1e4 | 5972 | stack_offset += align_up (len, MIPS64_REGSIZE); |
ebafbe83 MS |
5973 | } |
5974 | else | |
5975 | { | |
5976 | /* Copy the argument to general registers or the stack in | |
5977 | register-sized pieces. Large arguments are split between | |
5978 | registers and stack. */ | |
1a69e1e4 | 5979 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
5980 | are treated specially: Irix cc passes them in registers |
5981 | where gcc sometimes puts them on the stack. For maximum | |
5982 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
5983 | int odd_sized_struct = (len > MIPS64_REGSIZE |
5984 | && len % MIPS64_REGSIZE != 0); | |
ebafbe83 MS |
5985 | while (len > 0) |
5986 | { | |
1a69e1e4 | 5987 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
ebafbe83 MS |
5988 | |
5989 | if (mips_debug) | |
5990 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
5991 | partial_len); | |
5992 | ||
5993 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 5994 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 5995 | || odd_sized_struct) |
ebafbe83 MS |
5996 | { |
5997 | /* Should shorter than int integer values be | |
025bb325 | 5998 | promoted to int before being stored? */ |
ebafbe83 MS |
5999 | int longword_offset = 0; |
6000 | CORE_ADDR addr; | |
72a155b4 | 6001 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ebafbe83 | 6002 | { |
1a69e1e4 DJ |
6003 | if ((typecode == TYPE_CODE_INT |
6004 | || typecode == TYPE_CODE_PTR | |
6005 | || typecode == TYPE_CODE_FLT) | |
6006 | && len <= 4) | |
6007 | longword_offset = MIPS64_REGSIZE - len; | |
ebafbe83 MS |
6008 | } |
6009 | ||
6010 | if (mips_debug) | |
6011 | { | |
5af949e3 UW |
6012 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
6013 | paddress (gdbarch, stack_offset)); | |
6014 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
6015 | paddress (gdbarch, longword_offset)); | |
ebafbe83 MS |
6016 | } |
6017 | ||
6018 | addr = sp + stack_offset + longword_offset; | |
6019 | ||
6020 | if (mips_debug) | |
6021 | { | |
6022 | int i; | |
5af949e3 UW |
6023 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
6024 | paddress (gdbarch, addr)); | |
ebafbe83 MS |
6025 | for (i = 0; i < partial_len; i++) |
6026 | { | |
6d82d43b | 6027 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
6028 | val[i] & 0xff); |
6029 | } | |
6030 | } | |
6031 | write_memory (addr, val, partial_len); | |
6032 | } | |
6033 | ||
6034 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 6035 | structs may go thru BOTH paths. */ |
ebafbe83 | 6036 | /* Write this portion of the argument to a general |
6d82d43b | 6037 | purpose register. */ |
74ed0bb4 | 6038 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
ebafbe83 | 6039 | { |
e17a4113 UW |
6040 | LONGEST regval = extract_signed_integer (val, partial_len, |
6041 | byte_order); | |
4246e332 | 6042 | /* Value may need to be sign extended, because |
1b13c4f6 | 6043 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
6044 | |
6045 | /* A non-floating-point argument being passed in a | |
6046 | general register. If a struct or union, and if | |
6047 | the remaining length is smaller than the register | |
6048 | size, we have to adjust the register value on | |
6049 | big endian targets. | |
6050 | ||
6051 | It does not seem to be necessary to do the | |
025bb325 | 6052 | same for integral types. */ |
480d3dd2 | 6053 | |
72a155b4 | 6054 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 6055 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
6056 | && (typecode == TYPE_CODE_STRUCT |
6057 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 6058 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 6059 | * TARGET_CHAR_BIT); |
ebafbe83 MS |
6060 | |
6061 | if (mips_debug) | |
6062 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
6063 | argreg, | |
1a69e1e4 | 6064 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 6065 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
ebafbe83 MS |
6066 | argreg++; |
6067 | ||
6068 | /* Prevent subsequent floating point arguments from | |
6069 | being passed in floating point registers. */ | |
74ed0bb4 | 6070 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
ebafbe83 MS |
6071 | } |
6072 | ||
6073 | len -= partial_len; | |
6074 | val += partial_len; | |
6075 | ||
b021a221 MS |
6076 | /* Compute the offset into the stack at which we will |
6077 | copy the next parameter. | |
ebafbe83 | 6078 | |
6d82d43b AC |
6079 | In older ABIs, the caller reserved space for |
6080 | registers that contained arguments. This was loosely | |
6081 | refered to as their "home". Consequently, space is | |
6082 | always allocated. */ | |
ebafbe83 | 6083 | |
1a69e1e4 | 6084 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
ebafbe83 MS |
6085 | } |
6086 | } | |
6087 | if (mips_debug) | |
6088 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
6089 | } | |
6090 | ||
f10683bb | 6091 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 6092 | |
ebafbe83 MS |
6093 | /* Return adjusted stack pointer. */ |
6094 | return sp; | |
6095 | } | |
6096 | ||
9c8fdbfa | 6097 | static enum return_value_convention |
6a3a010b | 6098 | mips_o64_return_value (struct gdbarch *gdbarch, struct value *function, |
9c8fdbfa | 6099 | struct type *type, struct regcache *regcache, |
47a35522 | 6100 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 6101 | { |
6a3a010b | 6102 | CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0; |
4cc0665f | 6103 | int mips16 = mips_pc_is_mips16 (gdbarch, func_addr); |
6a3a010b | 6104 | enum mips_fval_reg fval_reg; |
7a076fd2 | 6105 | |
6a3a010b | 6106 | fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both; |
7a076fd2 FF |
6107 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
6108 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
6109 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
6110 | return RETURN_VALUE_STRUCT_CONVENTION; | |
74ed0bb4 | 6111 | else if (fp_register_arg_p (gdbarch, TYPE_CODE (type), type)) |
7a076fd2 | 6112 | { |
6a3a010b MR |
6113 | /* A floating-point value. If reading in or copying, then we get it |
6114 | from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code. | |
6115 | If writing out only, then we put it to both FP0 and GPR2. We do | |
6116 | not support reading in with no function known, if this safety | |
6117 | check ever triggers, then we'll have to try harder. */ | |
6118 | gdb_assert (function || !readbuf); | |
7a076fd2 | 6119 | if (mips_debug) |
6a3a010b MR |
6120 | switch (fval_reg) |
6121 | { | |
6122 | case mips_fval_fpr: | |
6123 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
6124 | break; | |
6125 | case mips_fval_gpr: | |
6126 | fprintf_unfiltered (gdb_stderr, "Return float in $2\n"); | |
6127 | break; | |
6128 | case mips_fval_both: | |
6129 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n"); | |
6130 | break; | |
6131 | } | |
6132 | if (fval_reg != mips_fval_gpr) | |
6133 | mips_xfer_register (gdbarch, regcache, | |
6134 | (gdbarch_num_regs (gdbarch) | |
6135 | + mips_regnum (gdbarch)->fp0), | |
6136 | TYPE_LENGTH (type), | |
6137 | gdbarch_byte_order (gdbarch), | |
6138 | readbuf, writebuf, 0); | |
6139 | if (fval_reg != mips_fval_fpr) | |
6140 | mips_xfer_register (gdbarch, regcache, | |
6141 | gdbarch_num_regs (gdbarch) + 2, | |
6142 | TYPE_LENGTH (type), | |
6143 | gdbarch_byte_order (gdbarch), | |
6144 | readbuf, writebuf, 0); | |
7a076fd2 FF |
6145 | return RETURN_VALUE_REGISTER_CONVENTION; |
6146 | } | |
6147 | else | |
6148 | { | |
6149 | /* A scalar extract each part but least-significant-byte | |
025bb325 | 6150 | justified. */ |
7a076fd2 FF |
6151 | int offset; |
6152 | int regnum; | |
6153 | for (offset = 0, regnum = MIPS_V0_REGNUM; | |
6154 | offset < TYPE_LENGTH (type); | |
1a69e1e4 | 6155 | offset += MIPS64_REGSIZE, regnum++) |
7a076fd2 | 6156 | { |
1a69e1e4 | 6157 | int xfer = MIPS64_REGSIZE; |
7a076fd2 FF |
6158 | if (offset + xfer > TYPE_LENGTH (type)) |
6159 | xfer = TYPE_LENGTH (type) - offset; | |
6160 | if (mips_debug) | |
6161 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
6162 | offset, xfer, regnum); | |
ba32f989 DJ |
6163 | mips_xfer_register (gdbarch, regcache, |
6164 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 6165 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 6166 | readbuf, writebuf, offset); |
7a076fd2 FF |
6167 | } |
6168 | return RETURN_VALUE_REGISTER_CONVENTION; | |
6169 | } | |
6d82d43b AC |
6170 | } |
6171 | ||
dd824b04 DJ |
6172 | /* Floating point register management. |
6173 | ||
6174 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
6175 | 64bit operations, these early MIPS cpus treat fp register pairs | |
6176 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
6177 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
6178 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
6179 | double precision floats into two 32-bit chunks and store them in | |
6180 | consecutive fp regs. To display 64-bit floats stored in this | |
6181 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
6182 | Throw in user-configurable endianness and you have a real mess. | |
6183 | ||
6184 | The way this works is: | |
6185 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
6186 | double-precision value will be split across two logical registers. | |
6187 | The lower-numbered logical register will hold the low-order bits, | |
6188 | regardless of the processor's endianness. | |
6189 | - If we are on a 64-bit processor, and we are looking for a | |
6190 | single-precision value, it will be in the low ordered bits | |
6191 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
6192 | save slot in memory. | |
6193 | - If we are in 64-bit mode, everything is straightforward. | |
6194 | ||
6195 | Note that this code only deals with "live" registers at the top of the | |
6196 | stack. We will attempt to deal with saved registers later, when | |
025bb325 | 6197 | the raw/cooked register interface is in place. (We need a general |
dd824b04 DJ |
6198 | interface that can deal with dynamic saved register sizes -- fp |
6199 | regs could be 32 bits wide in one frame and 64 on the frame above | |
6200 | and below). */ | |
6201 | ||
6202 | /* Copy a 32-bit single-precision value from the current frame | |
6203 | into rare_buffer. */ | |
6204 | ||
6205 | static void | |
e11c53d2 | 6206 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
47a35522 | 6207 | gdb_byte *rare_buffer) |
dd824b04 | 6208 | { |
72a155b4 UW |
6209 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6210 | int raw_size = register_size (gdbarch, regno); | |
224c3ddb | 6211 | gdb_byte *raw_buffer = (gdb_byte *) alloca (raw_size); |
dd824b04 | 6212 | |
ca9d61b9 | 6213 | if (!deprecated_frame_register_read (frame, regno, raw_buffer)) |
c9f4d572 | 6214 | error (_("can't read register %d (%s)"), |
72a155b4 | 6215 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
6216 | if (raw_size == 8) |
6217 | { | |
6218 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 6219 | 32 bits. */ |
dd824b04 DJ |
6220 | int offset; |
6221 | ||
72a155b4 | 6222 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 DJ |
6223 | offset = 4; |
6224 | else | |
6225 | offset = 0; | |
6226 | ||
6227 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
6228 | } | |
6229 | else | |
6230 | { | |
6231 | memcpy (rare_buffer, raw_buffer, 4); | |
6232 | } | |
6233 | } | |
6234 | ||
6235 | /* Copy a 64-bit double-precision value from the current frame into | |
6236 | rare_buffer. This may include getting half of it from the next | |
6237 | register. */ | |
6238 | ||
6239 | static void | |
e11c53d2 | 6240 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
47a35522 | 6241 | gdb_byte *rare_buffer) |
dd824b04 | 6242 | { |
72a155b4 UW |
6243 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6244 | int raw_size = register_size (gdbarch, regno); | |
dd824b04 | 6245 | |
9c9acae0 | 6246 | if (raw_size == 8 && !mips2_fp_compat (frame)) |
dd824b04 DJ |
6247 | { |
6248 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 6249 | all 64 bits. */ |
ca9d61b9 | 6250 | if (!deprecated_frame_register_read (frame, regno, rare_buffer)) |
c9f4d572 | 6251 | error (_("can't read register %d (%s)"), |
72a155b4 | 6252 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
6253 | } |
6254 | else | |
6255 | { | |
72a155b4 | 6256 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
82e91389 | 6257 | |
72a155b4 | 6258 | if ((rawnum - mips_regnum (gdbarch)->fp0) & 1) |
dd824b04 | 6259 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
6260 | _("mips_read_fp_register_double: bad access to " |
6261 | "odd-numbered FP register")); | |
dd824b04 DJ |
6262 | |
6263 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 6264 | each register. */ |
72a155b4 | 6265 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 | 6266 | { |
e11c53d2 AC |
6267 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
6268 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 6269 | } |
361d1df0 | 6270 | else |
dd824b04 | 6271 | { |
e11c53d2 AC |
6272 | mips_read_fp_register_single (frame, regno, rare_buffer); |
6273 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
6274 | } |
6275 | } | |
6276 | } | |
6277 | ||
c906108c | 6278 | static void |
e11c53d2 AC |
6279 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
6280 | int regnum) | |
025bb325 | 6281 | { /* Do values for FP (float) regs. */ |
72a155b4 | 6282 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 6283 | gdb_byte *raw_buffer; |
8ba0dd51 UW |
6284 | std::string flt_str, dbl_str; |
6285 | ||
f69fdf9b UW |
6286 | const struct type *flt_type = builtin_type (gdbarch)->builtin_float; |
6287 | const struct type *dbl_type = builtin_type (gdbarch)->builtin_double; | |
c5aa993b | 6288 | |
224c3ddb SM |
6289 | raw_buffer |
6290 | = ((gdb_byte *) | |
6291 | alloca (2 * register_size (gdbarch, mips_regnum (gdbarch)->fp0))); | |
c906108c | 6292 | |
72a155b4 | 6293 | fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum)); |
c9f4d572 | 6294 | fprintf_filtered (file, "%*s", |
72a155b4 | 6295 | 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)), |
e11c53d2 | 6296 | ""); |
f0ef6b29 | 6297 | |
72a155b4 | 6298 | if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame)) |
c906108c | 6299 | { |
79a45b7d TT |
6300 | struct value_print_options opts; |
6301 | ||
f0ef6b29 KB |
6302 | /* 4-byte registers: Print hex and floating. Also print even |
6303 | numbered registers as doubles. */ | |
e11c53d2 | 6304 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
f69fdf9b | 6305 | flt_str = target_float_to_string (raw_buffer, flt_type, "%-17.9g"); |
c5aa993b | 6306 | |
79a45b7d | 6307 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
6308 | print_scalar_formatted (raw_buffer, |
6309 | builtin_type (gdbarch)->builtin_uint32, | |
6310 | &opts, 'w', file); | |
dd824b04 | 6311 | |
8ba0dd51 | 6312 | fprintf_filtered (file, " flt: %s", flt_str.c_str ()); |
1adad886 | 6313 | |
72a155b4 | 6314 | if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0) |
f0ef6b29 | 6315 | { |
e11c53d2 | 6316 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f69fdf9b | 6317 | dbl_str = target_float_to_string (raw_buffer, dbl_type, "%-24.17g"); |
1adad886 | 6318 | |
8ba0dd51 | 6319 | fprintf_filtered (file, " dbl: %s", dbl_str.c_str ()); |
f0ef6b29 | 6320 | } |
c906108c SS |
6321 | } |
6322 | else | |
dd824b04 | 6323 | { |
79a45b7d TT |
6324 | struct value_print_options opts; |
6325 | ||
f0ef6b29 | 6326 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 6327 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
f69fdf9b | 6328 | flt_str = target_float_to_string (raw_buffer, flt_type, "%-17.9g"); |
c906108c | 6329 | |
e11c53d2 | 6330 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f69fdf9b | 6331 | dbl_str = target_float_to_string (raw_buffer, dbl_type, "%-24.17g"); |
f0ef6b29 | 6332 | |
79a45b7d | 6333 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
6334 | print_scalar_formatted (raw_buffer, |
6335 | builtin_type (gdbarch)->builtin_uint64, | |
6336 | &opts, 'g', file); | |
f0ef6b29 | 6337 | |
8ba0dd51 UW |
6338 | fprintf_filtered (file, " flt: %s", flt_str.c_str ()); |
6339 | fprintf_filtered (file, " dbl: %s", dbl_str.c_str ()); | |
f0ef6b29 KB |
6340 | } |
6341 | } | |
6342 | ||
6343 | static void | |
e11c53d2 | 6344 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
0cc93a06 | 6345 | int regnum) |
f0ef6b29 | 6346 | { |
a4b8ebc8 | 6347 | struct gdbarch *gdbarch = get_frame_arch (frame); |
79a45b7d | 6348 | struct value_print_options opts; |
de15c4ab | 6349 | struct value *val; |
1adad886 | 6350 | |
004159a2 | 6351 | if (mips_float_register_p (gdbarch, regnum)) |
f0ef6b29 | 6352 | { |
e11c53d2 | 6353 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
6354 | return; |
6355 | } | |
6356 | ||
de15c4ab | 6357 | val = get_frame_register_value (frame, regnum); |
f0ef6b29 | 6358 | |
72a155b4 | 6359 | fputs_filtered (gdbarch_register_name (gdbarch, regnum), file); |
f0ef6b29 KB |
6360 | |
6361 | /* The problem with printing numeric register names (r26, etc.) is that | |
6362 | the user can't use them on input. Probably the best solution is to | |
6363 | fix it so that either the numeric or the funky (a2, etc.) names | |
6364 | are accepted on input. */ | |
6365 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 6366 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 6367 | else |
e11c53d2 | 6368 | fprintf_filtered (file, ": "); |
f0ef6b29 | 6369 | |
79a45b7d | 6370 | get_formatted_print_options (&opts, 'x'); |
de15c4ab | 6371 | val_print_scalar_formatted (value_type (val), |
de15c4ab PA |
6372 | value_embedded_offset (val), |
6373 | val, | |
6374 | &opts, 0, file); | |
c906108c SS |
6375 | } |
6376 | ||
1bab7383 YQ |
6377 | /* Print IEEE exception condition bits in FLAGS. */ |
6378 | ||
6379 | static void | |
6380 | print_fpu_flags (struct ui_file *file, int flags) | |
6381 | { | |
6382 | if (flags & (1 << 0)) | |
6383 | fputs_filtered (" inexact", file); | |
6384 | if (flags & (1 << 1)) | |
6385 | fputs_filtered (" uflow", file); | |
6386 | if (flags & (1 << 2)) | |
6387 | fputs_filtered (" oflow", file); | |
6388 | if (flags & (1 << 3)) | |
6389 | fputs_filtered (" div0", file); | |
6390 | if (flags & (1 << 4)) | |
6391 | fputs_filtered (" inval", file); | |
6392 | if (flags & (1 << 5)) | |
6393 | fputs_filtered (" unimp", file); | |
6394 | fputc_filtered ('\n', file); | |
6395 | } | |
6396 | ||
6397 | /* Print interesting information about the floating point processor | |
6398 | (if present) or emulator. */ | |
6399 | ||
6400 | static void | |
6401 | mips_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, | |
6402 | struct frame_info *frame, const char *args) | |
6403 | { | |
6404 | int fcsr = mips_regnum (gdbarch)->fp_control_status; | |
6405 | enum mips_fpu_type type = MIPS_FPU_TYPE (gdbarch); | |
6406 | ULONGEST fcs = 0; | |
6407 | int i; | |
6408 | ||
6409 | if (fcsr == -1 || !read_frame_register_unsigned (frame, fcsr, &fcs)) | |
6410 | type = MIPS_FPU_NONE; | |
6411 | ||
6412 | fprintf_filtered (file, "fpu type: %s\n", | |
6413 | type == MIPS_FPU_DOUBLE ? "double-precision" | |
6414 | : type == MIPS_FPU_SINGLE ? "single-precision" | |
6415 | : "none / unused"); | |
6416 | ||
6417 | if (type == MIPS_FPU_NONE) | |
6418 | return; | |
6419 | ||
6420 | fprintf_filtered (file, "reg size: %d bits\n", | |
6421 | register_size (gdbarch, mips_regnum (gdbarch)->fp0) * 8); | |
6422 | ||
6423 | fputs_filtered ("cond :", file); | |
6424 | if (fcs & (1 << 23)) | |
6425 | fputs_filtered (" 0", file); | |
6426 | for (i = 1; i <= 7; i++) | |
6427 | if (fcs & (1 << (24 + i))) | |
6428 | fprintf_filtered (file, " %d", i); | |
6429 | fputc_filtered ('\n', file); | |
6430 | ||
6431 | fputs_filtered ("cause :", file); | |
6432 | print_fpu_flags (file, (fcs >> 12) & 0x3f); | |
6433 | fputs ("mask :", stdout); | |
6434 | print_fpu_flags (file, (fcs >> 7) & 0x1f); | |
6435 | fputs ("flags :", stdout); | |
6436 | print_fpu_flags (file, (fcs >> 2) & 0x1f); | |
6437 | ||
6438 | fputs_filtered ("rounding: ", file); | |
6439 | switch (fcs & 3) | |
6440 | { | |
6441 | case 0: fputs_filtered ("nearest\n", file); break; | |
6442 | case 1: fputs_filtered ("zero\n", file); break; | |
6443 | case 2: fputs_filtered ("+inf\n", file); break; | |
6444 | case 3: fputs_filtered ("-inf\n", file); break; | |
6445 | } | |
6446 | ||
6447 | fputs_filtered ("flush :", file); | |
6448 | if (fcs & (1 << 21)) | |
6449 | fputs_filtered (" nearest", file); | |
6450 | if (fcs & (1 << 22)) | |
6451 | fputs_filtered (" override", file); | |
6452 | if (fcs & (1 << 24)) | |
6453 | fputs_filtered (" zero", file); | |
6454 | if ((fcs & (0xb << 21)) == 0) | |
6455 | fputs_filtered (" no", file); | |
6456 | fputc_filtered ('\n', file); | |
6457 | ||
6458 | fprintf_filtered (file, "nan2008 : %s\n", fcs & (1 << 18) ? "yes" : "no"); | |
6459 | fprintf_filtered (file, "abs2008 : %s\n", fcs & (1 << 19) ? "yes" : "no"); | |
6460 | fputc_filtered ('\n', file); | |
6461 | ||
6462 | default_print_float_info (gdbarch, file, frame, args); | |
6463 | } | |
6464 | ||
f0ef6b29 KB |
6465 | /* Replacement for generic do_registers_info. |
6466 | Print regs in pretty columns. */ | |
6467 | ||
6468 | static int | |
e11c53d2 AC |
6469 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
6470 | int regnum) | |
f0ef6b29 | 6471 | { |
e11c53d2 AC |
6472 | fprintf_filtered (file, " "); |
6473 | mips_print_fp_register (file, frame, regnum); | |
6474 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
6475 | return regnum + 1; |
6476 | } | |
6477 | ||
6478 | ||
025bb325 | 6479 | /* Print a row's worth of GP (int) registers, with name labels above. */ |
c906108c SS |
6480 | |
6481 | static int | |
e11c53d2 | 6482 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 6483 | int start_regnum) |
c906108c | 6484 | { |
a4b8ebc8 | 6485 | struct gdbarch *gdbarch = get_frame_arch (frame); |
025bb325 | 6486 | /* Do values for GP (int) regs. */ |
313c5961 AH |
6487 | const gdb_byte *raw_buffer; |
6488 | struct value *value; | |
025bb325 MS |
6489 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols |
6490 | per row. */ | |
c906108c | 6491 | int col, byte; |
a4b8ebc8 | 6492 | int regnum; |
c906108c | 6493 | |
025bb325 | 6494 | /* For GP registers, we print a separate row of names above the vals. */ |
a4b8ebc8 | 6495 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
6496 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
6497 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 6498 | regnum++) |
c906108c | 6499 | { |
72a155b4 | 6500 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 6501 | continue; /* unused register */ |
004159a2 | 6502 | if (mips_float_register_p (gdbarch, regnum)) |
025bb325 | 6503 | break; /* End the row: reached FP register. */ |
0cc93a06 | 6504 | /* Large registers are handled separately. */ |
72a155b4 | 6505 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
6506 | { |
6507 | if (col > 0) | |
6508 | break; /* End the row before this register. */ | |
6509 | ||
6510 | /* Print this register on a row by itself. */ | |
6511 | mips_print_register (file, frame, regnum); | |
6512 | fprintf_filtered (file, "\n"); | |
6513 | return regnum + 1; | |
6514 | } | |
d05f6826 DJ |
6515 | if (col == 0) |
6516 | fprintf_filtered (file, " "); | |
6d82d43b | 6517 | fprintf_filtered (file, |
72a155b4 UW |
6518 | mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s", |
6519 | gdbarch_register_name (gdbarch, regnum)); | |
c906108c SS |
6520 | col++; |
6521 | } | |
d05f6826 DJ |
6522 | |
6523 | if (col == 0) | |
6524 | return regnum; | |
6525 | ||
025bb325 | 6526 | /* Print the R0 to R31 names. */ |
72a155b4 | 6527 | if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS) |
f57d151a | 6528 | fprintf_filtered (file, "\n R%-4d", |
72a155b4 | 6529 | start_regnum % gdbarch_num_regs (gdbarch)); |
20e6603c AC |
6530 | else |
6531 | fprintf_filtered (file, "\n "); | |
c906108c | 6532 | |
025bb325 | 6533 | /* Now print the values in hex, 4 or 8 to the row. */ |
a4b8ebc8 | 6534 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
6535 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
6536 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 6537 | regnum++) |
c906108c | 6538 | { |
72a155b4 | 6539 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 6540 | continue; /* unused register */ |
004159a2 | 6541 | if (mips_float_register_p (gdbarch, regnum)) |
025bb325 | 6542 | break; /* End row: reached FP register. */ |
72a155b4 | 6543 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
6544 | break; /* End row: large register. */ |
6545 | ||
c906108c | 6546 | /* OK: get the data in raw format. */ |
313c5961 AH |
6547 | value = get_frame_register_value (frame, regnum); |
6548 | if (value_optimized_out (value) | |
6549 | || !value_entirely_available (value)) | |
325c9fd4 JB |
6550 | { |
6551 | fprintf_filtered (file, "%*s ", | |
6552 | (int) mips_abi_regsize (gdbarch) * 2, | |
6553 | (mips_abi_regsize (gdbarch) == 4 ? "<unavl>" | |
6554 | : "<unavailable>")); | |
6555 | col++; | |
6556 | continue; | |
6557 | } | |
313c5961 | 6558 | raw_buffer = value_contents_all (value); |
c906108c | 6559 | /* pad small registers */ |
4246e332 | 6560 | for (byte = 0; |
72a155b4 UW |
6561 | byte < (mips_abi_regsize (gdbarch) |
6562 | - register_size (gdbarch, regnum)); byte++) | |
428544e8 | 6563 | fprintf_filtered (file, " "); |
025bb325 | 6564 | /* Now print the register value in hex, endian order. */ |
72a155b4 | 6565 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b | 6566 | for (byte = |
72a155b4 UW |
6567 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
6568 | byte < register_size (gdbarch, regnum); byte++) | |
47a35522 | 6569 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
c906108c | 6570 | else |
72a155b4 | 6571 | for (byte = register_size (gdbarch, regnum) - 1; |
6d82d43b | 6572 | byte >= 0; byte--) |
47a35522 | 6573 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
e11c53d2 | 6574 | fprintf_filtered (file, " "); |
c906108c SS |
6575 | col++; |
6576 | } | |
025bb325 | 6577 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 6578 | fprintf_filtered (file, "\n"); |
c906108c SS |
6579 | |
6580 | return regnum; | |
6581 | } | |
6582 | ||
025bb325 | 6583 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */ |
c906108c | 6584 | |
bf1f5b4c | 6585 | static void |
e11c53d2 AC |
6586 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
6587 | struct frame_info *frame, int regnum, int all) | |
c906108c | 6588 | { |
025bb325 | 6589 | if (regnum != -1) /* Do one specified register. */ |
c906108c | 6590 | { |
72a155b4 UW |
6591 | gdb_assert (regnum >= gdbarch_num_regs (gdbarch)); |
6592 | if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
8a3fe4f8 | 6593 | error (_("Not a valid register for the current processor type")); |
c906108c | 6594 | |
0cc93a06 | 6595 | mips_print_register (file, frame, regnum); |
e11c53d2 | 6596 | fprintf_filtered (file, "\n"); |
c906108c | 6597 | } |
c5aa993b | 6598 | else |
025bb325 | 6599 | /* Do all (or most) registers. */ |
c906108c | 6600 | { |
72a155b4 UW |
6601 | regnum = gdbarch_num_regs (gdbarch); |
6602 | while (regnum < gdbarch_num_regs (gdbarch) | |
6603 | + gdbarch_num_pseudo_regs (gdbarch)) | |
c906108c | 6604 | { |
004159a2 | 6605 | if (mips_float_register_p (gdbarch, regnum)) |
e11c53d2 | 6606 | { |
025bb325 | 6607 | if (all) /* True for "INFO ALL-REGISTERS" command. */ |
e11c53d2 AC |
6608 | regnum = print_fp_register_row (file, frame, regnum); |
6609 | else | |
025bb325 | 6610 | regnum += MIPS_NUMREGS; /* Skip floating point regs. */ |
e11c53d2 | 6611 | } |
c906108c | 6612 | else |
e11c53d2 | 6613 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
6614 | } |
6615 | } | |
6616 | } | |
6617 | ||
63807e1d | 6618 | static int |
3352ef37 AC |
6619 | mips_single_step_through_delay (struct gdbarch *gdbarch, |
6620 | struct frame_info *frame) | |
c906108c | 6621 | { |
3352ef37 | 6622 | CORE_ADDR pc = get_frame_pc (frame); |
4cc0665f MR |
6623 | enum mips_isa isa; |
6624 | ULONGEST insn; | |
4cc0665f MR |
6625 | int size; |
6626 | ||
6627 | if ((mips_pc_is_mips (pc) | |
ab50adb6 | 6628 | && !mips32_insn_at_pc_has_delay_slot (gdbarch, pc)) |
4cc0665f | 6629 | || (mips_pc_is_micromips (gdbarch, pc) |
ab50adb6 | 6630 | && !micromips_insn_at_pc_has_delay_slot (gdbarch, pc, 0)) |
4cc0665f | 6631 | || (mips_pc_is_mips16 (gdbarch, pc) |
ab50adb6 | 6632 | && !mips16_insn_at_pc_has_delay_slot (gdbarch, pc, 0))) |
06648491 MK |
6633 | return 0; |
6634 | ||
4cc0665f MR |
6635 | isa = mips_pc_isa (gdbarch, pc); |
6636 | /* _has_delay_slot above will have validated the read. */ | |
6637 | insn = mips_fetch_instruction (gdbarch, isa, pc, NULL); | |
6638 | size = mips_insn_size (isa, insn); | |
8b86c959 YQ |
6639 | |
6640 | const address_space *aspace = get_frame_address_space (frame); | |
6641 | ||
4cc0665f | 6642 | return breakpoint_here_p (aspace, pc + size) != no_breakpoint_here; |
c906108c SS |
6643 | } |
6644 | ||
6d82d43b AC |
6645 | /* To skip prologues, I use this predicate. Returns either PC itself |
6646 | if the code at PC does not look like a function prologue; otherwise | |
6647 | returns an address that (if we're lucky) follows the prologue. If | |
6648 | LENIENT, then we must skip everything which is involved in setting | |
6649 | up the frame (it's OK to skip more, just so long as we don't skip | |
6650 | anything which might clobber the registers which are being saved. | |
6651 | We must skip more in the case where part of the prologue is in the | |
6652 | delay slot of a non-prologue instruction). */ | |
6653 | ||
6654 | static CORE_ADDR | |
6093d2eb | 6655 | mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
6d82d43b | 6656 | { |
8b622e6a AC |
6657 | CORE_ADDR limit_pc; |
6658 | CORE_ADDR func_addr; | |
6659 | ||
6d82d43b AC |
6660 | /* See if we can determine the end of the prologue via the symbol table. |
6661 | If so, then return either PC, or the PC after the prologue, whichever | |
6662 | is greater. */ | |
8b622e6a AC |
6663 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
6664 | { | |
d80b854b UW |
6665 | CORE_ADDR post_prologue_pc |
6666 | = skip_prologue_using_sal (gdbarch, func_addr); | |
8b622e6a | 6667 | if (post_prologue_pc != 0) |
325fac50 | 6668 | return std::max (pc, post_prologue_pc); |
8b622e6a | 6669 | } |
6d82d43b AC |
6670 | |
6671 | /* Can't determine prologue from the symbol table, need to examine | |
6672 | instructions. */ | |
6673 | ||
98b4dd94 JB |
6674 | /* Find an upper limit on the function prologue using the debug |
6675 | information. If the debug information could not be used to provide | |
6676 | that bound, then use an arbitrary large number as the upper bound. */ | |
d80b854b | 6677 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
98b4dd94 JB |
6678 | if (limit_pc == 0) |
6679 | limit_pc = pc + 100; /* Magic. */ | |
6680 | ||
4cc0665f | 6681 | if (mips_pc_is_mips16 (gdbarch, pc)) |
e17a4113 | 6682 | return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
4cc0665f MR |
6683 | else if (mips_pc_is_micromips (gdbarch, pc)) |
6684 | return micromips_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); | |
6d82d43b | 6685 | else |
e17a4113 | 6686 | return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
88658117 AC |
6687 | } |
6688 | ||
c9cf6e20 MG |
6689 | /* Implement the stack_frame_destroyed_p gdbarch method (32-bit version). |
6690 | This is a helper function for mips_stack_frame_destroyed_p. */ | |
6691 | ||
97ab0fdd | 6692 | static int |
c9cf6e20 | 6693 | mips32_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
6694 | { |
6695 | CORE_ADDR func_addr = 0, func_end = 0; | |
6696 | ||
6697 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
6698 | { | |
6699 | /* The MIPS epilogue is max. 12 bytes long. */ | |
6700 | CORE_ADDR addr = func_end - 12; | |
6701 | ||
6702 | if (addr < func_addr + 4) | |
6703 | addr = func_addr + 4; | |
6704 | if (pc < addr) | |
6705 | return 0; | |
6706 | ||
6707 | for (; pc < func_end; pc += MIPS_INSN32_SIZE) | |
6708 | { | |
6709 | unsigned long high_word; | |
6710 | unsigned long inst; | |
6711 | ||
4cc0665f | 6712 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
97ab0fdd MR |
6713 | high_word = (inst >> 16) & 0xffff; |
6714 | ||
6715 | if (high_word != 0x27bd /* addiu $sp,$sp,offset */ | |
6716 | && high_word != 0x67bd /* daddiu $sp,$sp,offset */ | |
6717 | && inst != 0x03e00008 /* jr $ra */ | |
6718 | && inst != 0x00000000) /* nop */ | |
6719 | return 0; | |
6720 | } | |
6721 | ||
6722 | return 1; | |
6723 | } | |
6724 | ||
6725 | return 0; | |
6726 | } | |
6727 | ||
c9cf6e20 MG |
6728 | /* Implement the stack_frame_destroyed_p gdbarch method (microMIPS version). |
6729 | This is a helper function for mips_stack_frame_destroyed_p. */ | |
4cc0665f MR |
6730 | |
6731 | static int | |
c9cf6e20 | 6732 | micromips_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
4cc0665f MR |
6733 | { |
6734 | CORE_ADDR func_addr = 0; | |
6735 | CORE_ADDR func_end = 0; | |
6736 | CORE_ADDR addr; | |
6737 | ULONGEST insn; | |
6738 | long offset; | |
6739 | int dreg; | |
6740 | int sreg; | |
6741 | int loc; | |
6742 | ||
6743 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
6744 | return 0; | |
6745 | ||
6746 | /* The microMIPS epilogue is max. 12 bytes long. */ | |
6747 | addr = func_end - 12; | |
6748 | ||
6749 | if (addr < func_addr + 2) | |
6750 | addr = func_addr + 2; | |
6751 | if (pc < addr) | |
6752 | return 0; | |
6753 | ||
6754 | for (; pc < func_end; pc += loc) | |
6755 | { | |
6756 | loc = 0; | |
6757 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
6758 | loc += MIPS_INSN16_SIZE; | |
6759 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
6760 | { | |
4cc0665f MR |
6761 | /* 32-bit instructions. */ |
6762 | case 2 * MIPS_INSN16_SIZE: | |
6763 | insn <<= 16; | |
6764 | insn |= mips_fetch_instruction (gdbarch, | |
6765 | ISA_MICROMIPS, pc + loc, NULL); | |
6766 | loc += MIPS_INSN16_SIZE; | |
6767 | switch (micromips_op (insn >> 16)) | |
6768 | { | |
6769 | case 0xc: /* ADDIU: bits 001100 */ | |
6770 | case 0x17: /* DADDIU: bits 010111 */ | |
6771 | sreg = b0s5_reg (insn >> 16); | |
6772 | dreg = b5s5_reg (insn >> 16); | |
6773 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
6774 | if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM | |
6775 | /* (D)ADDIU $sp, imm */ | |
6776 | && offset >= 0) | |
6777 | break; | |
6778 | return 0; | |
6779 | ||
6780 | default: | |
6781 | return 0; | |
6782 | } | |
6783 | break; | |
6784 | ||
6785 | /* 16-bit instructions. */ | |
6786 | case MIPS_INSN16_SIZE: | |
6787 | switch (micromips_op (insn)) | |
6788 | { | |
6789 | case 0x3: /* MOVE: bits 000011 */ | |
6790 | sreg = b0s5_reg (insn); | |
6791 | dreg = b5s5_reg (insn); | |
6792 | if (sreg == 0 && dreg == 0) | |
6793 | /* MOVE $zero, $zero aka NOP */ | |
6794 | break; | |
6795 | return 0; | |
6796 | ||
6797 | case 0x11: /* POOL16C: bits 010001 */ | |
6798 | if (b5s5_op (insn) == 0x18 | |
6799 | /* JRADDIUSP: bits 010011 11000 */ | |
6800 | || (b5s5_op (insn) == 0xd | |
6801 | /* JRC: bits 010011 01101 */ | |
6802 | && b0s5_reg (insn) == MIPS_RA_REGNUM)) | |
6803 | /* JRC $ra */ | |
6804 | break; | |
6805 | return 0; | |
6806 | ||
6807 | case 0x13: /* POOL16D: bits 010011 */ | |
6808 | offset = micromips_decode_imm9 (b1s9_imm (insn)); | |
6809 | if ((insn & 0x1) == 0x1 | |
6810 | /* ADDIUSP: bits 010011 1 */ | |
6811 | && offset > 0) | |
6812 | break; | |
6813 | return 0; | |
6814 | ||
6815 | default: | |
6816 | return 0; | |
6817 | } | |
6818 | } | |
6819 | } | |
6820 | ||
6821 | return 1; | |
6822 | } | |
6823 | ||
c9cf6e20 MG |
6824 | /* Implement the stack_frame_destroyed_p gdbarch method (16-bit version). |
6825 | This is a helper function for mips_stack_frame_destroyed_p. */ | |
6826 | ||
97ab0fdd | 6827 | static int |
c9cf6e20 | 6828 | mips16_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
6829 | { |
6830 | CORE_ADDR func_addr = 0, func_end = 0; | |
6831 | ||
6832 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
6833 | { | |
6834 | /* The MIPS epilogue is max. 12 bytes long. */ | |
6835 | CORE_ADDR addr = func_end - 12; | |
6836 | ||
6837 | if (addr < func_addr + 4) | |
6838 | addr = func_addr + 4; | |
6839 | if (pc < addr) | |
6840 | return 0; | |
6841 | ||
6842 | for (; pc < func_end; pc += MIPS_INSN16_SIZE) | |
6843 | { | |
6844 | unsigned short inst; | |
6845 | ||
4cc0665f | 6846 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc, NULL); |
97ab0fdd MR |
6847 | |
6848 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
6849 | continue; | |
6850 | ||
6851 | if (inst != 0x6300 /* addiu $sp,offset */ | |
6852 | && inst != 0xfb00 /* daddiu $sp,$sp,offset */ | |
6853 | && inst != 0xe820 /* jr $ra */ | |
6854 | && inst != 0xe8a0 /* jrc $ra */ | |
6855 | && inst != 0x6500) /* nop */ | |
6856 | return 0; | |
6857 | } | |
6858 | ||
6859 | return 1; | |
6860 | } | |
6861 | ||
6862 | return 0; | |
6863 | } | |
6864 | ||
c9cf6e20 MG |
6865 | /* Implement the stack_frame_destroyed_p gdbarch method. |
6866 | ||
6867 | The epilogue is defined here as the area at the end of a function, | |
97ab0fdd | 6868 | after an instruction which destroys the function's stack frame. */ |
c9cf6e20 | 6869 | |
97ab0fdd | 6870 | static int |
c9cf6e20 | 6871 | mips_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd | 6872 | { |
4cc0665f | 6873 | if (mips_pc_is_mips16 (gdbarch, pc)) |
c9cf6e20 | 6874 | return mips16_stack_frame_destroyed_p (gdbarch, pc); |
4cc0665f | 6875 | else if (mips_pc_is_micromips (gdbarch, pc)) |
c9cf6e20 | 6876 | return micromips_stack_frame_destroyed_p (gdbarch, pc); |
97ab0fdd | 6877 | else |
c9cf6e20 | 6878 | return mips32_stack_frame_destroyed_p (gdbarch, pc); |
97ab0fdd MR |
6879 | } |
6880 | ||
025bb325 | 6881 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
a5ea2558 AC |
6882 | used for all MIPS-specific commands. */ |
6883 | ||
a5ea2558 | 6884 | static void |
981a3fb3 | 6885 | show_mips_command (const char *args, int from_tty) |
a5ea2558 AC |
6886 | { |
6887 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
6888 | } | |
6889 | ||
a5ea2558 | 6890 | static void |
981a3fb3 | 6891 | set_mips_command (const char *args, int from_tty) |
a5ea2558 | 6892 | { |
6d82d43b AC |
6893 | printf_unfiltered |
6894 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
6895 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
6896 | } | |
6897 | ||
c906108c SS |
6898 | /* Commands to show/set the MIPS FPU type. */ |
6899 | ||
c906108c | 6900 | static void |
bd4c9dfe | 6901 | show_mipsfpu_command (const char *args, int from_tty) |
c906108c | 6902 | { |
a121b7c1 | 6903 | const char *fpu; |
6ca0852e | 6904 | |
f5656ead | 6905 | if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips) |
6ca0852e UW |
6906 | { |
6907 | printf_unfiltered | |
6908 | ("The MIPS floating-point coprocessor is unknown " | |
6909 | "because the current architecture is not MIPS.\n"); | |
6910 | return; | |
6911 | } | |
6912 | ||
f5656ead | 6913 | switch (MIPS_FPU_TYPE (target_gdbarch ())) |
c906108c SS |
6914 | { |
6915 | case MIPS_FPU_SINGLE: | |
6916 | fpu = "single-precision"; | |
6917 | break; | |
6918 | case MIPS_FPU_DOUBLE: | |
6919 | fpu = "double-precision"; | |
6920 | break; | |
6921 | case MIPS_FPU_NONE: | |
6922 | fpu = "absent (none)"; | |
6923 | break; | |
93d56215 | 6924 | default: |
e2e0b3e5 | 6925 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c SS |
6926 | } |
6927 | if (mips_fpu_type_auto) | |
025bb325 MS |
6928 | printf_unfiltered ("The MIPS floating-point coprocessor " |
6929 | "is set automatically (currently %s)\n", | |
6930 | fpu); | |
c906108c | 6931 | else |
6d82d43b AC |
6932 | printf_unfiltered |
6933 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
6934 | } |
6935 | ||
6936 | ||
c906108c | 6937 | static void |
981a3fb3 | 6938 | set_mipsfpu_command (const char *args, int from_tty) |
c906108c | 6939 | { |
025bb325 MS |
6940 | printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", " |
6941 | "\"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
6942 | show_mipsfpu_command (args, from_tty); |
6943 | } | |
6944 | ||
c906108c | 6945 | static void |
bd4c9dfe | 6946 | set_mipsfpu_single_command (const char *args, int from_tty) |
c906108c | 6947 | { |
8d5838b5 AC |
6948 | struct gdbarch_info info; |
6949 | gdbarch_info_init (&info); | |
c906108c SS |
6950 | mips_fpu_type = MIPS_FPU_SINGLE; |
6951 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
6952 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
6953 | instead of relying on globals. Doing that would let generic code | |
6954 | handle the search for this specific architecture. */ | |
6955 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 6956 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
6957 | } |
6958 | ||
c906108c | 6959 | static void |
bd4c9dfe | 6960 | set_mipsfpu_double_command (const char *args, int from_tty) |
c906108c | 6961 | { |
8d5838b5 AC |
6962 | struct gdbarch_info info; |
6963 | gdbarch_info_init (&info); | |
c906108c SS |
6964 | mips_fpu_type = MIPS_FPU_DOUBLE; |
6965 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
6966 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
6967 | instead of relying on globals. Doing that would let generic code | |
6968 | handle the search for this specific architecture. */ | |
6969 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 6970 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
6971 | } |
6972 | ||
c906108c | 6973 | static void |
bd4c9dfe | 6974 | set_mipsfpu_none_command (const char *args, int from_tty) |
c906108c | 6975 | { |
8d5838b5 AC |
6976 | struct gdbarch_info info; |
6977 | gdbarch_info_init (&info); | |
c906108c SS |
6978 | mips_fpu_type = MIPS_FPU_NONE; |
6979 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
6980 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
6981 | instead of relying on globals. Doing that would let generic code | |
6982 | handle the search for this specific architecture. */ | |
6983 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 6984 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
6985 | } |
6986 | ||
c906108c | 6987 | static void |
bd4c9dfe | 6988 | set_mipsfpu_auto_command (const char *args, int from_tty) |
c906108c SS |
6989 | { |
6990 | mips_fpu_type_auto = 1; | |
6991 | } | |
6992 | ||
c906108c SS |
6993 | /* Just like reinit_frame_cache, but with the right arguments to be |
6994 | callable as an sfunc. */ | |
6995 | ||
6996 | static void | |
eb4c3f4a | 6997 | reinit_frame_cache_sfunc (const char *args, int from_tty, |
acdb74a0 | 6998 | struct cmd_list_element *c) |
c906108c SS |
6999 | { |
7000 | reinit_frame_cache (); | |
7001 | } | |
7002 | ||
a89aa300 AC |
7003 | static int |
7004 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 7005 | { |
e47ad6c0 YQ |
7006 | gdb_disassembler *di |
7007 | = static_cast<gdb_disassembler *>(info->application_data); | |
7008 | struct gdbarch *gdbarch = di->arch (); | |
4cc0665f | 7009 | |
d31431ed AC |
7010 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
7011 | disassembler needs to be able to locally determine the ISA, and | |
7012 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
7013 | work. */ | |
4cc0665f | 7014 | if (mips_pc_is_mips16 (gdbarch, memaddr)) |
ec4045ea | 7015 | info->mach = bfd_mach_mips16; |
4cc0665f MR |
7016 | else if (mips_pc_is_micromips (gdbarch, memaddr)) |
7017 | info->mach = bfd_mach_mips_micromips; | |
c906108c SS |
7018 | |
7019 | /* Round down the instruction address to the appropriate boundary. */ | |
4cc0665f MR |
7020 | memaddr &= (info->mach == bfd_mach_mips16 |
7021 | || info->mach == bfd_mach_mips_micromips) ? ~1 : ~3; | |
c5aa993b | 7022 | |
6394c606 | 7023 | return default_print_insn (memaddr, info); |
c906108c SS |
7024 | } |
7025 | ||
cd6c3b4f YQ |
7026 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ |
7027 | ||
d19280ad YQ |
7028 | static int |
7029 | mips_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
c906108c | 7030 | { |
4cc0665f MR |
7031 | CORE_ADDR pc = *pcptr; |
7032 | ||
d19280ad | 7033 | if (mips_pc_is_mips16 (gdbarch, pc)) |
c906108c | 7034 | { |
d19280ad YQ |
7035 | *pcptr = unmake_compact_addr (pc); |
7036 | return MIPS_BP_KIND_MIPS16; | |
7037 | } | |
7038 | else if (mips_pc_is_micromips (gdbarch, pc)) | |
7039 | { | |
7040 | ULONGEST insn; | |
7041 | int status; | |
c906108c | 7042 | |
d19280ad YQ |
7043 | *pcptr = unmake_compact_addr (pc); |
7044 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status); | |
7045 | if (status || (mips_insn_size (ISA_MICROMIPS, insn) == 2)) | |
7046 | return MIPS_BP_KIND_MICROMIPS16; | |
7047 | else | |
7048 | return MIPS_BP_KIND_MICROMIPS32; | |
c906108c SS |
7049 | } |
7050 | else | |
d19280ad YQ |
7051 | return MIPS_BP_KIND_MIPS32; |
7052 | } | |
7053 | ||
cd6c3b4f YQ |
7054 | /* Implement the sw_breakpoint_from_kind gdbarch method. */ |
7055 | ||
d19280ad YQ |
7056 | static const gdb_byte * |
7057 | mips_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) | |
7058 | { | |
7059 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
7060 | ||
7061 | switch (kind) | |
c906108c | 7062 | { |
d19280ad YQ |
7063 | case MIPS_BP_KIND_MIPS16: |
7064 | { | |
7065 | static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; | |
7066 | static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; | |
7067 | ||
7068 | *size = 2; | |
7069 | if (byte_order_for_code == BFD_ENDIAN_BIG) | |
7070 | return mips16_big_breakpoint; | |
7071 | else | |
c906108c | 7072 | return mips16_little_breakpoint; |
d19280ad YQ |
7073 | } |
7074 | case MIPS_BP_KIND_MICROMIPS16: | |
7075 | { | |
7076 | static gdb_byte micromips16_big_breakpoint[] = { 0x46, 0x85 }; | |
7077 | static gdb_byte micromips16_little_breakpoint[] = { 0x85, 0x46 }; | |
7078 | ||
7079 | *size = 2; | |
7080 | ||
7081 | if (byte_order_for_code == BFD_ENDIAN_BIG) | |
7082 | return micromips16_big_breakpoint; | |
7083 | else | |
7084 | return micromips16_little_breakpoint; | |
7085 | } | |
7086 | case MIPS_BP_KIND_MICROMIPS32: | |
7087 | { | |
7088 | static gdb_byte micromips32_big_breakpoint[] = { 0, 0x5, 0, 0x7 }; | |
7089 | static gdb_byte micromips32_little_breakpoint[] = { 0x5, 0, 0x7, 0 }; | |
7090 | ||
7091 | *size = 4; | |
7092 | if (byte_order_for_code == BFD_ENDIAN_BIG) | |
7093 | return micromips32_big_breakpoint; | |
7094 | else | |
7095 | return micromips32_little_breakpoint; | |
7096 | } | |
7097 | case MIPS_BP_KIND_MIPS32: | |
7098 | { | |
7099 | static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; | |
7100 | static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; | |
c906108c | 7101 | |
d19280ad YQ |
7102 | *size = 4; |
7103 | if (byte_order_for_code == BFD_ENDIAN_BIG) | |
7104 | return big_breakpoint; | |
7105 | else | |
7e3d947d | 7106 | return little_breakpoint; |
d19280ad YQ |
7107 | } |
7108 | default: | |
7109 | gdb_assert_not_reached ("unexpected mips breakpoint kind"); | |
7110 | }; | |
c906108c SS |
7111 | } |
7112 | ||
ab50adb6 MR |
7113 | /* Return non-zero if the standard MIPS instruction INST has a branch |
7114 | delay slot (i.e. it is a jump or branch instruction). This function | |
7115 | is based on mips32_next_pc. */ | |
c8cef75f MR |
7116 | |
7117 | static int | |
ab50adb6 | 7118 | mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, ULONGEST inst) |
c8cef75f | 7119 | { |
c8cef75f | 7120 | int op; |
a385295e MR |
7121 | int rs; |
7122 | int rt; | |
c8cef75f | 7123 | |
c8cef75f MR |
7124 | op = itype_op (inst); |
7125 | if ((inst & 0xe0000000) != 0) | |
a385295e MR |
7126 | { |
7127 | rs = itype_rs (inst); | |
7128 | rt = itype_rt (inst); | |
f94363d7 AP |
7129 | return (is_octeon_bbit_op (op, gdbarch) |
7130 | || op >> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ | |
a385295e MR |
7131 | || op == 29 /* JALX: bits 011101 */ |
7132 | || (op == 17 | |
7133 | && (rs == 8 | |
c8cef75f | 7134 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
a385295e MR |
7135 | || (rs == 9 && (rt & 0x2) == 0) |
7136 | /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */ | |
7137 | || (rs == 10 && (rt & 0x2) == 0)))); | |
7138 | /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */ | |
7139 | } | |
c8cef75f MR |
7140 | else |
7141 | switch (op & 0x07) /* extract bits 28,27,26 */ | |
7142 | { | |
7143 | case 0: /* SPECIAL */ | |
7144 | op = rtype_funct (inst); | |
7145 | return (op == 8 /* JR */ | |
7146 | || op == 9); /* JALR */ | |
7147 | break; /* end SPECIAL */ | |
7148 | case 1: /* REGIMM */ | |
a385295e MR |
7149 | rs = itype_rs (inst); |
7150 | rt = itype_rt (inst); /* branch condition */ | |
7151 | return ((rt & 0xc) == 0 | |
c8cef75f MR |
7152 | /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */ |
7153 | /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */ | |
a385295e MR |
7154 | || ((rt & 0x1e) == 0x1c && rs == 0)); |
7155 | /* BPOSGE32, BPOSGE64: bits 1110x */ | |
c8cef75f MR |
7156 | break; /* end REGIMM */ |
7157 | default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */ | |
7158 | return 1; | |
7159 | break; | |
7160 | } | |
7161 | } | |
7162 | ||
ab50adb6 MR |
7163 | /* Return non-zero if a standard MIPS instruction at ADDR has a branch |
7164 | delay slot (i.e. it is a jump or branch instruction). */ | |
c8cef75f | 7165 | |
4cc0665f | 7166 | static int |
ab50adb6 | 7167 | mips32_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr) |
4cc0665f MR |
7168 | { |
7169 | ULONGEST insn; | |
7170 | int status; | |
7171 | ||
ab50adb6 | 7172 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, addr, &status); |
4cc0665f MR |
7173 | if (status) |
7174 | return 0; | |
7175 | ||
ab50adb6 MR |
7176 | return mips32_instruction_has_delay_slot (gdbarch, insn); |
7177 | } | |
4cc0665f | 7178 | |
ab50adb6 MR |
7179 | /* Return non-zero if the microMIPS instruction INSN, comprising the |
7180 | 16-bit major opcode word in the high 16 bits and any second word | |
7181 | in the low 16 bits, has a branch delay slot (i.e. it is a non-compact | |
7182 | jump or branch instruction). The instruction must be 32-bit if | |
7183 | MUSTBE32 is set or can be any instruction otherwise. */ | |
7184 | ||
7185 | static int | |
7186 | micromips_instruction_has_delay_slot (ULONGEST insn, int mustbe32) | |
7187 | { | |
7188 | ULONGEST major = insn >> 16; | |
4cc0665f | 7189 | |
ab50adb6 MR |
7190 | switch (micromips_op (major)) |
7191 | { | |
7192 | /* 16-bit instructions. */ | |
7193 | case 0x33: /* B16: bits 110011 */ | |
7194 | case 0x2b: /* BNEZ16: bits 101011 */ | |
7195 | case 0x23: /* BEQZ16: bits 100011 */ | |
7196 | return !mustbe32; | |
7197 | case 0x11: /* POOL16C: bits 010001 */ | |
7198 | return (!mustbe32 | |
7199 | && ((b5s5_op (major) == 0xc | |
7200 | /* JR16: bits 010001 01100 */ | |
7201 | || (b5s5_op (major) & 0x1e) == 0xe))); | |
7202 | /* JALR16, JALRS16: bits 010001 0111x */ | |
7203 | /* 32-bit instructions. */ | |
7204 | case 0x3d: /* JAL: bits 111101 */ | |
7205 | case 0x3c: /* JALX: bits 111100 */ | |
7206 | case 0x35: /* J: bits 110101 */ | |
7207 | case 0x2d: /* BNE: bits 101101 */ | |
7208 | case 0x25: /* BEQ: bits 100101 */ | |
7209 | case 0x1d: /* JALS: bits 011101 */ | |
7210 | return 1; | |
7211 | case 0x10: /* POOL32I: bits 010000 */ | |
7212 | return ((b5s5_op (major) & 0x1c) == 0x0 | |
4cc0665f | 7213 | /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */ |
ab50adb6 | 7214 | || (b5s5_op (major) & 0x1d) == 0x4 |
4cc0665f | 7215 | /* BLEZ, BGTZ: bits 010000 001x0 */ |
ab50adb6 | 7216 | || (b5s5_op (major) & 0x1d) == 0x11 |
4cc0665f | 7217 | /* BLTZALS, BGEZALS: bits 010000 100x1 */ |
ab50adb6 MR |
7218 | || ((b5s5_op (major) & 0x1e) == 0x14 |
7219 | && (major & 0x3) == 0x0) | |
4cc0665f | 7220 | /* BC2F, BC2T: bits 010000 1010x xxx00 */ |
ab50adb6 | 7221 | || (b5s5_op (major) & 0x1e) == 0x1a |
4cc0665f | 7222 | /* BPOSGE64, BPOSGE32: bits 010000 1101x */ |
ab50adb6 MR |
7223 | || ((b5s5_op (major) & 0x1e) == 0x1c |
7224 | && (major & 0x3) == 0x0) | |
4cc0665f | 7225 | /* BC1F, BC1T: bits 010000 1110x xxx00 */ |
ab50adb6 MR |
7226 | || ((b5s5_op (major) & 0x1c) == 0x1c |
7227 | && (major & 0x3) == 0x1)); | |
4cc0665f | 7228 | /* BC1ANY*: bits 010000 111xx xxx01 */ |
ab50adb6 MR |
7229 | case 0x0: /* POOL32A: bits 000000 */ |
7230 | return (b0s6_op (insn) == 0x3c | |
7231 | /* POOL32Axf: bits 000000 ... 111100 */ | |
7232 | && (b6s10_ext (insn) & 0x2bf) == 0x3c); | |
7233 | /* JALR, JALR.HB: 000000 000x111100 111100 */ | |
7234 | /* JALRS, JALRS.HB: 000000 010x111100 111100 */ | |
7235 | default: | |
7236 | return 0; | |
7237 | } | |
4cc0665f MR |
7238 | } |
7239 | ||
ab50adb6 | 7240 | /* Return non-zero if a microMIPS instruction at ADDR has a branch delay |
ae790652 MR |
7241 | slot (i.e. it is a non-compact jump instruction). The instruction |
7242 | must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */ | |
7243 | ||
c8cef75f | 7244 | static int |
ab50adb6 MR |
7245 | micromips_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, |
7246 | CORE_ADDR addr, int mustbe32) | |
c8cef75f | 7247 | { |
ab50adb6 | 7248 | ULONGEST insn; |
c8cef75f | 7249 | int status; |
3f7f3650 | 7250 | int size; |
c8cef75f | 7251 | |
ab50adb6 | 7252 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status); |
c8cef75f MR |
7253 | if (status) |
7254 | return 0; | |
3f7f3650 | 7255 | size = mips_insn_size (ISA_MICROMIPS, insn); |
ab50adb6 | 7256 | insn <<= 16; |
3f7f3650 | 7257 | if (size == 2 * MIPS_INSN16_SIZE) |
ab50adb6 MR |
7258 | { |
7259 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status); | |
7260 | if (status) | |
7261 | return 0; | |
7262 | } | |
7263 | ||
7264 | return micromips_instruction_has_delay_slot (insn, mustbe32); | |
7265 | } | |
c8cef75f | 7266 | |
ab50adb6 MR |
7267 | /* Return non-zero if the MIPS16 instruction INST, which must be |
7268 | a 32-bit instruction if MUSTBE32 is set or can be any instruction | |
7269 | otherwise, has a branch delay slot (i.e. it is a non-compact jump | |
7270 | instruction). This function is based on mips16_next_pc. */ | |
7271 | ||
7272 | static int | |
7273 | mips16_instruction_has_delay_slot (unsigned short inst, int mustbe32) | |
7274 | { | |
ae790652 MR |
7275 | if ((inst & 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */ |
7276 | return !mustbe32; | |
c8cef75f MR |
7277 | return (inst & 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */ |
7278 | } | |
7279 | ||
ab50adb6 MR |
7280 | /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay |
7281 | slot (i.e. it is a non-compact jump instruction). The instruction | |
7282 | must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */ | |
7283 | ||
7284 | static int | |
7285 | mips16_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, | |
7286 | CORE_ADDR addr, int mustbe32) | |
7287 | { | |
7288 | unsigned short insn; | |
7289 | int status; | |
7290 | ||
7291 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS16, addr, &status); | |
7292 | if (status) | |
7293 | return 0; | |
7294 | ||
7295 | return mips16_instruction_has_delay_slot (insn, mustbe32); | |
7296 | } | |
7297 | ||
c8cef75f MR |
7298 | /* Calculate the starting address of the MIPS memory segment BPADDR is in. |
7299 | This assumes KSSEG exists. */ | |
7300 | ||
7301 | static CORE_ADDR | |
7302 | mips_segment_boundary (CORE_ADDR bpaddr) | |
7303 | { | |
7304 | CORE_ADDR mask = CORE_ADDR_MAX; | |
7305 | int segsize; | |
7306 | ||
7307 | if (sizeof (CORE_ADDR) == 8) | |
7308 | /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid | |
7309 | a compiler warning produced where CORE_ADDR is a 32-bit type even | |
7310 | though in that case this is dead code). */ | |
7311 | switch (bpaddr >> ((sizeof (CORE_ADDR) << 3) - 2) & 3) | |
7312 | { | |
7313 | case 3: | |
7314 | if (bpaddr == (bfd_signed_vma) (int32_t) bpaddr) | |
7315 | segsize = 29; /* 32-bit compatibility segment */ | |
7316 | else | |
7317 | segsize = 62; /* xkseg */ | |
7318 | break; | |
7319 | case 2: /* xkphys */ | |
7320 | segsize = 59; | |
7321 | break; | |
7322 | default: /* xksseg (1), xkuseg/kuseg (0) */ | |
7323 | segsize = 62; | |
7324 | break; | |
7325 | } | |
7326 | else if (bpaddr & 0x80000000) /* kernel segment */ | |
7327 | segsize = 29; | |
7328 | else | |
7329 | segsize = 31; /* user segment */ | |
7330 | mask <<= segsize; | |
7331 | return bpaddr & mask; | |
7332 | } | |
7333 | ||
7334 | /* Move the breakpoint at BPADDR out of any branch delay slot by shifting | |
7335 | it backwards if necessary. Return the address of the new location. */ | |
7336 | ||
7337 | static CORE_ADDR | |
7338 | mips_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) | |
7339 | { | |
22e048c9 | 7340 | CORE_ADDR prev_addr; |
c8cef75f MR |
7341 | CORE_ADDR boundary; |
7342 | CORE_ADDR func_addr; | |
7343 | ||
7344 | /* If a breakpoint is set on the instruction in a branch delay slot, | |
7345 | GDB gets confused. When the breakpoint is hit, the PC isn't on | |
7346 | the instruction in the branch delay slot, the PC will point to | |
7347 | the branch instruction. Since the PC doesn't match any known | |
7348 | breakpoints, GDB reports a trap exception. | |
7349 | ||
7350 | There are two possible fixes for this problem. | |
7351 | ||
7352 | 1) When the breakpoint gets hit, see if the BD bit is set in the | |
7353 | Cause register (which indicates the last exception occurred in a | |
7354 | branch delay slot). If the BD bit is set, fix the PC to point to | |
7355 | the instruction in the branch delay slot. | |
7356 | ||
7357 | 2) When the user sets the breakpoint, don't allow him to set the | |
7358 | breakpoint on the instruction in the branch delay slot. Instead | |
7359 | move the breakpoint to the branch instruction (which will have | |
7360 | the same result). | |
7361 | ||
7362 | The problem with the first solution is that if the user then | |
7363 | single-steps the processor, the branch instruction will get | |
7364 | skipped (since GDB thinks the PC is on the instruction in the | |
7365 | branch delay slot). | |
7366 | ||
7367 | So, we'll use the second solution. To do this we need to know if | |
7368 | the instruction we're trying to set the breakpoint on is in the | |
7369 | branch delay slot. */ | |
7370 | ||
7371 | boundary = mips_segment_boundary (bpaddr); | |
7372 | ||
7373 | /* Make sure we don't scan back before the beginning of the current | |
7374 | function, since we may fetch constant data or insns that look like | |
7375 | a jump. Of course we might do that anyway if the compiler has | |
7376 | moved constants inline. :-( */ | |
7377 | if (find_pc_partial_function (bpaddr, NULL, &func_addr, NULL) | |
7378 | && func_addr > boundary && func_addr <= bpaddr) | |
7379 | boundary = func_addr; | |
7380 | ||
4cc0665f | 7381 | if (mips_pc_is_mips (bpaddr)) |
c8cef75f MR |
7382 | { |
7383 | if (bpaddr == boundary) | |
7384 | return bpaddr; | |
7385 | ||
7386 | /* If the previous instruction has a branch delay slot, we have | |
7387 | to move the breakpoint to the branch instruction. */ | |
7388 | prev_addr = bpaddr - 4; | |
ab50adb6 | 7389 | if (mips32_insn_at_pc_has_delay_slot (gdbarch, prev_addr)) |
c8cef75f MR |
7390 | bpaddr = prev_addr; |
7391 | } | |
7392 | else | |
7393 | { | |
ab50adb6 | 7394 | int (*insn_at_pc_has_delay_slot) (struct gdbarch *, CORE_ADDR, int); |
c8cef75f MR |
7395 | CORE_ADDR addr, jmpaddr; |
7396 | int i; | |
7397 | ||
4cc0665f | 7398 | boundary = unmake_compact_addr (boundary); |
c8cef75f MR |
7399 | |
7400 | /* The only MIPS16 instructions with delay slots are JAL, JALX, | |
7401 | JALR and JR. An absolute JAL/JALX is always 4 bytes long, | |
7402 | so try for that first, then try the 2 byte JALR/JR. | |
4cc0665f MR |
7403 | The microMIPS ASE has a whole range of jumps and branches |
7404 | with delay slots, some of which take 4 bytes and some take | |
7405 | 2 bytes, so the idea is the same. | |
c8cef75f MR |
7406 | FIXME: We have to assume that bpaddr is not the second half |
7407 | of an extended instruction. */ | |
ab50adb6 MR |
7408 | insn_at_pc_has_delay_slot = (mips_pc_is_micromips (gdbarch, bpaddr) |
7409 | ? micromips_insn_at_pc_has_delay_slot | |
7410 | : mips16_insn_at_pc_has_delay_slot); | |
c8cef75f MR |
7411 | |
7412 | jmpaddr = 0; | |
7413 | addr = bpaddr; | |
7414 | for (i = 1; i < 4; i++) | |
7415 | { | |
4cc0665f | 7416 | if (unmake_compact_addr (addr) == boundary) |
c8cef75f | 7417 | break; |
4cc0665f | 7418 | addr -= MIPS_INSN16_SIZE; |
ab50adb6 | 7419 | if (i == 1 && insn_at_pc_has_delay_slot (gdbarch, addr, 0)) |
c8cef75f MR |
7420 | /* Looks like a JR/JALR at [target-1], but it could be |
7421 | the second word of a previous JAL/JALX, so record it | |
7422 | and check back one more. */ | |
7423 | jmpaddr = addr; | |
ab50adb6 | 7424 | else if (i > 1 && insn_at_pc_has_delay_slot (gdbarch, addr, 1)) |
c8cef75f MR |
7425 | { |
7426 | if (i == 2) | |
7427 | /* Looks like a JAL/JALX at [target-2], but it could also | |
7428 | be the second word of a previous JAL/JALX, record it, | |
7429 | and check back one more. */ | |
7430 | jmpaddr = addr; | |
7431 | else | |
7432 | /* Looks like a JAL/JALX at [target-3], so any previously | |
7433 | recorded JAL/JALX or JR/JALR must be wrong, because: | |
7434 | ||
7435 | >-3: JAL | |
7436 | -2: JAL-ext (can't be JAL/JALX) | |
7437 | -1: bdslot (can't be JR/JALR) | |
7438 | 0: target insn | |
7439 | ||
7440 | Of course it could be another JAL-ext which looks | |
7441 | like a JAL, but in that case we'd have broken out | |
7442 | of this loop at [target-2]: | |
7443 | ||
7444 | -4: JAL | |
7445 | >-3: JAL-ext | |
7446 | -2: bdslot (can't be jmp) | |
7447 | -1: JR/JALR | |
7448 | 0: target insn */ | |
7449 | jmpaddr = 0; | |
7450 | } | |
7451 | else | |
7452 | { | |
7453 | /* Not a jump instruction: if we're at [target-1] this | |
7454 | could be the second word of a JAL/JALX, so continue; | |
7455 | otherwise we're done. */ | |
7456 | if (i > 1) | |
7457 | break; | |
7458 | } | |
7459 | } | |
7460 | ||
7461 | if (jmpaddr) | |
7462 | bpaddr = jmpaddr; | |
7463 | } | |
7464 | ||
7465 | return bpaddr; | |
7466 | } | |
7467 | ||
14132e89 MR |
7468 | /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16 |
7469 | call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */ | |
7470 | ||
7471 | static int | |
7472 | mips_is_stub_suffix (const char *suffix, int zero) | |
7473 | { | |
7474 | switch (suffix[0]) | |
7475 | { | |
7476 | case '0': | |
7477 | return zero && suffix[1] == '\0'; | |
7478 | case '1': | |
7479 | return suffix[1] == '\0' || (suffix[1] == '0' && suffix[2] == '\0'); | |
7480 | case '2': | |
7481 | case '5': | |
7482 | case '6': | |
7483 | case '9': | |
7484 | return suffix[1] == '\0'; | |
7485 | default: | |
7486 | return 0; | |
7487 | } | |
7488 | } | |
7489 | ||
7490 | /* Return non-zero if MODE is one of the mode infixes used for MIPS16 | |
7491 | call stubs, one of sf, df, sc, or dc. */ | |
7492 | ||
7493 | static int | |
7494 | mips_is_stub_mode (const char *mode) | |
7495 | { | |
7496 | return ((mode[0] == 's' || mode[0] == 'd') | |
7497 | && (mode[1] == 'f' || mode[1] == 'c')); | |
7498 | } | |
7499 | ||
7500 | /* Code at PC is a compiler-generated stub. Such a stub for a function | |
7501 | bar might have a name like __fn_stub_bar, and might look like this: | |
7502 | ||
7503 | mfc1 $4, $f13 | |
7504 | mfc1 $5, $f12 | |
7505 | mfc1 $6, $f15 | |
7506 | mfc1 $7, $f14 | |
7507 | ||
7508 | followed by (or interspersed with): | |
7509 | ||
7510 | j bar | |
7511 | ||
7512 | or: | |
7513 | ||
7514 | lui $25, %hi(bar) | |
7515 | addiu $25, $25, %lo(bar) | |
7516 | jr $25 | |
7517 | ||
7518 | ($1 may be used in old code; for robustness we accept any register) | |
7519 | or, in PIC code: | |
7520 | ||
7521 | lui $28, %hi(_gp_disp) | |
7522 | addiu $28, $28, %lo(_gp_disp) | |
7523 | addu $28, $28, $25 | |
7524 | lw $25, %got(bar) | |
7525 | addiu $25, $25, %lo(bar) | |
7526 | jr $25 | |
7527 | ||
7528 | In the case of a __call_stub_bar stub, the sequence to set up | |
7529 | arguments might look like this: | |
7530 | ||
7531 | mtc1 $4, $f13 | |
7532 | mtc1 $5, $f12 | |
7533 | mtc1 $6, $f15 | |
7534 | mtc1 $7, $f14 | |
7535 | ||
7536 | followed by (or interspersed with) one of the jump sequences above. | |
7537 | ||
7538 | In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead | |
7539 | of J or JR, respectively, followed by: | |
7540 | ||
7541 | mfc1 $2, $f0 | |
7542 | mfc1 $3, $f1 | |
7543 | jr $18 | |
7544 | ||
7545 | We are at the beginning of the stub here, and scan down and extract | |
7546 | the target address from the jump immediate instruction or, if a jump | |
7547 | register instruction is used, from the register referred. Return | |
7548 | the value of PC calculated or 0 if inconclusive. | |
7549 | ||
7550 | The limit on the search is arbitrarily set to 20 instructions. FIXME. */ | |
7551 | ||
7552 | static CORE_ADDR | |
7553 | mips_get_mips16_fn_stub_pc (struct frame_info *frame, CORE_ADDR pc) | |
7554 | { | |
7555 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
7556 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
7557 | int addrreg = MIPS_ZERO_REGNUM; | |
7558 | CORE_ADDR start_pc = pc; | |
7559 | CORE_ADDR target_pc = 0; | |
7560 | CORE_ADDR addr = 0; | |
7561 | CORE_ADDR gp = 0; | |
7562 | int status = 0; | |
7563 | int i; | |
7564 | ||
7565 | for (i = 0; | |
7566 | status == 0 && target_pc == 0 && i < 20; | |
7567 | i++, pc += MIPS_INSN32_SIZE) | |
7568 | { | |
4cc0665f | 7569 | ULONGEST inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
14132e89 MR |
7570 | CORE_ADDR imm; |
7571 | int rt; | |
7572 | int rs; | |
7573 | int rd; | |
7574 | ||
7575 | switch (itype_op (inst)) | |
7576 | { | |
7577 | case 0: /* SPECIAL */ | |
7578 | switch (rtype_funct (inst)) | |
7579 | { | |
7580 | case 8: /* JR */ | |
7581 | case 9: /* JALR */ | |
7582 | rs = rtype_rs (inst); | |
7583 | if (rs == MIPS_GP_REGNUM) | |
7584 | target_pc = gp; /* Hmm... */ | |
7585 | else if (rs == addrreg) | |
7586 | target_pc = addr; | |
7587 | break; | |
7588 | ||
7589 | case 0x21: /* ADDU */ | |
7590 | rt = rtype_rt (inst); | |
7591 | rs = rtype_rs (inst); | |
7592 | rd = rtype_rd (inst); | |
7593 | if (rd == MIPS_GP_REGNUM | |
7594 | && ((rs == MIPS_GP_REGNUM && rt == MIPS_T9_REGNUM) | |
7595 | || (rs == MIPS_T9_REGNUM && rt == MIPS_GP_REGNUM))) | |
7596 | gp += start_pc; | |
7597 | break; | |
7598 | } | |
7599 | break; | |
7600 | ||
7601 | case 2: /* J */ | |
7602 | case 3: /* JAL */ | |
7603 | target_pc = jtype_target (inst) << 2; | |
7604 | target_pc += ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); | |
7605 | break; | |
7606 | ||
7607 | case 9: /* ADDIU */ | |
7608 | rt = itype_rt (inst); | |
7609 | rs = itype_rs (inst); | |
7610 | if (rt == rs) | |
7611 | { | |
7612 | imm = (itype_immediate (inst) ^ 0x8000) - 0x8000; | |
7613 | if (rt == MIPS_GP_REGNUM) | |
7614 | gp += imm; | |
7615 | else if (rt == addrreg) | |
7616 | addr += imm; | |
7617 | } | |
7618 | break; | |
7619 | ||
7620 | case 0xf: /* LUI */ | |
7621 | rt = itype_rt (inst); | |
7622 | imm = ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 16; | |
7623 | if (rt == MIPS_GP_REGNUM) | |
7624 | gp = imm; | |
7625 | else if (rt != MIPS_ZERO_REGNUM) | |
7626 | { | |
7627 | addrreg = rt; | |
7628 | addr = imm; | |
7629 | } | |
7630 | break; | |
7631 | ||
7632 | case 0x23: /* LW */ | |
7633 | rt = itype_rt (inst); | |
7634 | rs = itype_rs (inst); | |
7635 | imm = (itype_immediate (inst) ^ 0x8000) - 0x8000; | |
7636 | if (gp != 0 && rs == MIPS_GP_REGNUM) | |
7637 | { | |
7638 | gdb_byte buf[4]; | |
7639 | ||
7640 | memset (buf, 0, sizeof (buf)); | |
7641 | status = target_read_memory (gp + imm, buf, sizeof (buf)); | |
7642 | addrreg = rt; | |
7643 | addr = extract_signed_integer (buf, sizeof (buf), byte_order); | |
7644 | } | |
7645 | break; | |
7646 | } | |
7647 | } | |
7648 | ||
7649 | return target_pc; | |
7650 | } | |
7651 | ||
7652 | /* If PC is in a MIPS16 call or return stub, return the address of the | |
7653 | target PC, which is either the callee or the caller. There are several | |
c906108c SS |
7654 | cases which must be handled: |
7655 | ||
14132e89 MR |
7656 | * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub |
7657 | and the target PC is in $31 ($ra). | |
c906108c | 7658 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
14132e89 MR |
7659 | and the target PC is in $2. |
7660 | * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10}, | |
7661 | i.e. before the JALR instruction, this is effectively a call stub | |
7662 | and the target PC is in $2. Otherwise this is effectively | |
7663 | a return stub and the target PC is in $18. | |
7664 | * If the PC is at the start of __call_stub_fp_*, i.e. before the | |
7665 | JAL or JALR instruction, this is effectively a call stub and the | |
7666 | target PC is buried in the instruction stream. Otherwise this | |
7667 | is effectively a return stub and the target PC is in $18. | |
7668 | * If the PC is in __call_stub_* or in __fn_stub_*, this is a call | |
7669 | stub and the target PC is buried in the instruction stream. | |
7670 | ||
7671 | See the source code for the stubs in gcc/config/mips/mips16.S, or the | |
7672 | stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the | |
e7d6a6d2 | 7673 | gory details. */ |
c906108c | 7674 | |
757a7cc6 | 7675 | static CORE_ADDR |
db5f024e | 7676 | mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 7677 | { |
e17a4113 | 7678 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 7679 | CORE_ADDR start_addr; |
14132e89 MR |
7680 | const char *name; |
7681 | size_t prefixlen; | |
c906108c SS |
7682 | |
7683 | /* Find the starting address and name of the function containing the PC. */ | |
7684 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
7685 | return 0; | |
7686 | ||
14132e89 MR |
7687 | /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub |
7688 | and the target PC is in $31 ($ra). */ | |
7689 | prefixlen = strlen (mips_str_mips16_ret_stub); | |
7690 | if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0 | |
7691 | && mips_is_stub_mode (name + prefixlen) | |
7692 | && name[prefixlen + 2] == '\0') | |
7693 | return get_frame_register_signed | |
7694 | (frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM); | |
7695 | ||
7696 | /* If the PC is in __mips16_call_stub_*, this is one of the call | |
7697 | call/return stubs. */ | |
7698 | prefixlen = strlen (mips_str_mips16_call_stub); | |
7699 | if (strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0) | |
c906108c SS |
7700 | { |
7701 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
7702 | and the target PC is in $2. */ | |
14132e89 MR |
7703 | if (mips_is_stub_suffix (name + prefixlen, 0)) |
7704 | return get_frame_register_signed | |
7705 | (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); | |
c906108c | 7706 | |
14132e89 MR |
7707 | /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10}, |
7708 | i.e. before the JALR instruction, this is effectively a call stub | |
b021a221 | 7709 | and the target PC is in $2. Otherwise this is effectively |
c5aa993b | 7710 | a return stub and the target PC is in $18. */ |
14132e89 MR |
7711 | else if (mips_is_stub_mode (name + prefixlen) |
7712 | && name[prefixlen + 2] == '_' | |
7713 | && mips_is_stub_suffix (name + prefixlen + 3, 0)) | |
c906108c SS |
7714 | { |
7715 | if (pc == start_addr) | |
14132e89 MR |
7716 | /* This is the 'call' part of a call stub. The return |
7717 | address is in $2. */ | |
7718 | return get_frame_register_signed | |
7719 | (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); | |
c906108c SS |
7720 | else |
7721 | /* This is the 'return' part of a call stub. The return | |
14132e89 MR |
7722 | address is in $18. */ |
7723 | return get_frame_register_signed | |
7724 | (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); | |
c906108c | 7725 | } |
14132e89 MR |
7726 | else |
7727 | return 0; /* Not a stub. */ | |
7728 | } | |
7729 | ||
7730 | /* If the PC is in __call_stub_* or __fn_stub*, this is one of the | |
7731 | compiler-generated call or call/return stubs. */ | |
61012eef GB |
7732 | if (startswith (name, mips_str_fn_stub) |
7733 | || startswith (name, mips_str_call_stub)) | |
14132e89 MR |
7734 | { |
7735 | if (pc == start_addr) | |
7736 | /* This is the 'call' part of a call stub. Call this helper | |
7737 | to scan through this code for interesting instructions | |
7738 | and determine the final PC. */ | |
7739 | return mips_get_mips16_fn_stub_pc (frame, pc); | |
7740 | else | |
7741 | /* This is the 'return' part of a call stub. The return address | |
7742 | is in $18. */ | |
7743 | return get_frame_register_signed | |
7744 | (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); | |
c906108c | 7745 | } |
14132e89 MR |
7746 | |
7747 | return 0; /* Not a stub. */ | |
7748 | } | |
7749 | ||
7750 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
7751 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
7752 | ||
7753 | static int | |
7754 | mips_in_return_stub (struct gdbarch *gdbarch, CORE_ADDR pc, const char *name) | |
7755 | { | |
7756 | CORE_ADDR start_addr; | |
7757 | size_t prefixlen; | |
7758 | ||
7759 | /* Find the starting address of the function containing the PC. */ | |
7760 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
7761 | return 0; | |
7762 | ||
7763 | /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at | |
7764 | the start, i.e. after the JALR instruction, this is effectively | |
7765 | a return stub. */ | |
7766 | prefixlen = strlen (mips_str_mips16_call_stub); | |
7767 | if (pc != start_addr | |
7768 | && strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0 | |
7769 | && mips_is_stub_mode (name + prefixlen) | |
7770 | && name[prefixlen + 2] == '_' | |
7771 | && mips_is_stub_suffix (name + prefixlen + 3, 1)) | |
7772 | return 1; | |
7773 | ||
7774 | /* If the PC is in __call_stub_fp_* but not at the start, i.e. after | |
7775 | the JAL or JALR instruction, this is effectively a return stub. */ | |
7776 | prefixlen = strlen (mips_str_call_fp_stub); | |
7777 | if (pc != start_addr | |
7778 | && strncmp (name, mips_str_call_fp_stub, prefixlen) == 0) | |
7779 | return 1; | |
7780 | ||
7781 | /* Consume the .pic. prefix of any PIC stub, this function must return | |
7782 | true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub | |
7783 | or the call stub path will trigger in handle_inferior_event causing | |
7784 | it to go astray. */ | |
7785 | prefixlen = strlen (mips_str_pic); | |
7786 | if (strncmp (name, mips_str_pic, prefixlen) == 0) | |
7787 | name += prefixlen; | |
7788 | ||
7789 | /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */ | |
7790 | prefixlen = strlen (mips_str_mips16_ret_stub); | |
7791 | if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0 | |
7792 | && mips_is_stub_mode (name + prefixlen) | |
7793 | && name[prefixlen + 2] == '\0') | |
7794 | return 1; | |
7795 | ||
7796 | return 0; /* Not a stub. */ | |
c906108c SS |
7797 | } |
7798 | ||
db5f024e DJ |
7799 | /* If the current PC is the start of a non-PIC-to-PIC stub, return the |
7800 | PC of the stub target. The stub just loads $t9 and jumps to it, | |
7801 | so that $t9 has the correct value at function entry. */ | |
7802 | ||
7803 | static CORE_ADDR | |
7804 | mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
7805 | { | |
e17a4113 UW |
7806 | struct gdbarch *gdbarch = get_frame_arch (frame); |
7807 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
7cbd4a93 | 7808 | struct bound_minimal_symbol msym; |
db5f024e DJ |
7809 | int i; |
7810 | gdb_byte stub_code[16]; | |
7811 | int32_t stub_words[4]; | |
7812 | ||
7813 | /* The stub for foo is named ".pic.foo", and is either two | |
7814 | instructions inserted before foo or a three instruction sequence | |
7815 | which jumps to foo. */ | |
7816 | msym = lookup_minimal_symbol_by_pc (pc); | |
7cbd4a93 | 7817 | if (msym.minsym == NULL |
77e371c0 | 7818 | || BMSYMBOL_VALUE_ADDRESS (msym) != pc |
efd66ac6 | 7819 | || MSYMBOL_LINKAGE_NAME (msym.minsym) == NULL |
61012eef | 7820 | || !startswith (MSYMBOL_LINKAGE_NAME (msym.minsym), ".pic.")) |
db5f024e DJ |
7821 | return 0; |
7822 | ||
7823 | /* A two-instruction header. */ | |
7cbd4a93 | 7824 | if (MSYMBOL_SIZE (msym.minsym) == 8) |
db5f024e DJ |
7825 | return pc + 8; |
7826 | ||
7827 | /* A three-instruction (plus delay slot) trampoline. */ | |
7cbd4a93 | 7828 | if (MSYMBOL_SIZE (msym.minsym) == 16) |
db5f024e DJ |
7829 | { |
7830 | if (target_read_memory (pc, stub_code, 16) != 0) | |
7831 | return 0; | |
7832 | for (i = 0; i < 4; i++) | |
e17a4113 UW |
7833 | stub_words[i] = extract_unsigned_integer (stub_code + i * 4, |
7834 | 4, byte_order); | |
db5f024e DJ |
7835 | |
7836 | /* A stub contains these instructions: | |
7837 | lui t9, %hi(target) | |
7838 | j target | |
7839 | addiu t9, t9, %lo(target) | |
7840 | nop | |
7841 | ||
7842 | This works even for N64, since stubs are only generated with | |
7843 | -msym32. */ | |
7844 | if ((stub_words[0] & 0xffff0000U) == 0x3c190000 | |
7845 | && (stub_words[1] & 0xfc000000U) == 0x08000000 | |
7846 | && (stub_words[2] & 0xffff0000U) == 0x27390000 | |
7847 | && stub_words[3] == 0x00000000) | |
34b192ce MR |
7848 | return ((((stub_words[0] & 0x0000ffff) << 16) |
7849 | + (stub_words[2] & 0x0000ffff)) ^ 0x8000) - 0x8000; | |
db5f024e DJ |
7850 | } |
7851 | ||
7852 | /* Not a recognized stub. */ | |
7853 | return 0; | |
7854 | } | |
7855 | ||
7856 | static CORE_ADDR | |
7857 | mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
7858 | { | |
14132e89 | 7859 | CORE_ADDR requested_pc = pc; |
db5f024e | 7860 | CORE_ADDR target_pc; |
14132e89 MR |
7861 | CORE_ADDR new_pc; |
7862 | ||
7863 | do | |
7864 | { | |
7865 | target_pc = pc; | |
db5f024e | 7866 | |
14132e89 MR |
7867 | new_pc = mips_skip_mips16_trampoline_code (frame, pc); |
7868 | if (new_pc) | |
3e29f34a | 7869 | pc = new_pc; |
db5f024e | 7870 | |
14132e89 MR |
7871 | new_pc = find_solib_trampoline_target (frame, pc); |
7872 | if (new_pc) | |
3e29f34a | 7873 | pc = new_pc; |
db5f024e | 7874 | |
14132e89 MR |
7875 | new_pc = mips_skip_pic_trampoline_code (frame, pc); |
7876 | if (new_pc) | |
3e29f34a | 7877 | pc = new_pc; |
14132e89 MR |
7878 | } |
7879 | while (pc != target_pc); | |
db5f024e | 7880 | |
14132e89 | 7881 | return pc != requested_pc ? pc : 0; |
db5f024e DJ |
7882 | } |
7883 | ||
a4b8ebc8 | 7884 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
f57d151a | 7885 | [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
7886 | |
7887 | static int | |
d3f73121 | 7888 | mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 7889 | { |
a4b8ebc8 | 7890 | int regnum; |
2f38ef89 | 7891 | if (num >= 0 && num < 32) |
a4b8ebc8 | 7892 | regnum = num; |
2f38ef89 | 7893 | else if (num >= 38 && num < 70) |
d3f73121 | 7894 | regnum = num + mips_regnum (gdbarch)->fp0 - 38; |
040b99fd | 7895 | else if (num == 70) |
d3f73121 | 7896 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 7897 | else if (num == 71) |
d3f73121 | 7898 | regnum = mips_regnum (gdbarch)->lo; |
1faeff08 MR |
7899 | else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 72 && num < 78) |
7900 | regnum = num + mips_regnum (gdbarch)->dspacc - 72; | |
2f38ef89 | 7901 | else |
0fde2c53 | 7902 | return -1; |
d3f73121 | 7903 | return gdbarch_num_regs (gdbarch) + regnum; |
88c72b7d AC |
7904 | } |
7905 | ||
2f38ef89 | 7906 | |
a4b8ebc8 | 7907 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
f57d151a | 7908 | gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
7909 | |
7910 | static int | |
d3f73121 | 7911 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 7912 | { |
a4b8ebc8 | 7913 | int regnum; |
2f38ef89 | 7914 | if (num >= 0 && num < 32) |
a4b8ebc8 | 7915 | regnum = num; |
2f38ef89 | 7916 | else if (num >= 32 && num < 64) |
d3f73121 | 7917 | regnum = num + mips_regnum (gdbarch)->fp0 - 32; |
040b99fd | 7918 | else if (num == 64) |
d3f73121 | 7919 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 7920 | else if (num == 65) |
d3f73121 | 7921 | regnum = mips_regnum (gdbarch)->lo; |
1faeff08 MR |
7922 | else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 66 && num < 72) |
7923 | regnum = num + mips_regnum (gdbarch)->dspacc - 66; | |
2f38ef89 | 7924 | else |
0fde2c53 | 7925 | return -1; |
d3f73121 | 7926 | return gdbarch_num_regs (gdbarch) + regnum; |
a4b8ebc8 AC |
7927 | } |
7928 | ||
7929 | static int | |
e7faf938 | 7930 | mips_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
a4b8ebc8 AC |
7931 | { |
7932 | /* Only makes sense to supply raw registers. */ | |
e7faf938 | 7933 | gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)); |
a4b8ebc8 AC |
7934 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to |
7935 | decide if it is valid. Should instead define a standard sim/gdb | |
7936 | register numbering scheme. */ | |
e7faf938 MD |
7937 | if (gdbarch_register_name (gdbarch, |
7938 | gdbarch_num_regs (gdbarch) + regnum) != NULL | |
7939 | && gdbarch_register_name (gdbarch, | |
025bb325 MS |
7940 | gdbarch_num_regs (gdbarch) |
7941 | + regnum)[0] != '\0') | |
a4b8ebc8 AC |
7942 | return regnum; |
7943 | else | |
6d82d43b | 7944 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
7945 | } |
7946 | ||
2f38ef89 | 7947 | |
4844f454 CV |
7948 | /* Convert an integer into an address. Extracting the value signed |
7949 | guarantees a correctly sign extended address. */ | |
fc0c74b1 AC |
7950 | |
7951 | static CORE_ADDR | |
79dd2d24 | 7952 | mips_integer_to_address (struct gdbarch *gdbarch, |
870cd05e | 7953 | struct type *type, const gdb_byte *buf) |
fc0c74b1 | 7954 | { |
e17a4113 UW |
7955 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7956 | return extract_signed_integer (buf, TYPE_LENGTH (type), byte_order); | |
fc0c74b1 AC |
7957 | } |
7958 | ||
82e91389 DJ |
7959 | /* Dummy virtual frame pointer method. This is no more or less accurate |
7960 | than most other architectures; we just need to be explicit about it, | |
7961 | because the pseudo-register gdbarch_sp_regnum will otherwise lead to | |
7962 | an assertion failure. */ | |
7963 | ||
7964 | static void | |
a54fba4c MD |
7965 | mips_virtual_frame_pointer (struct gdbarch *gdbarch, |
7966 | CORE_ADDR pc, int *reg, LONGEST *offset) | |
82e91389 DJ |
7967 | { |
7968 | *reg = MIPS_SP_REGNUM; | |
7969 | *offset = 0; | |
7970 | } | |
7971 | ||
caaa3122 DJ |
7972 | static void |
7973 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
7974 | { | |
7975 | enum mips_abi *abip = (enum mips_abi *) obj; | |
7976 | const char *name = bfd_get_section_name (abfd, sect); | |
7977 | ||
7978 | if (*abip != MIPS_ABI_UNKNOWN) | |
7979 | return; | |
7980 | ||
61012eef | 7981 | if (!startswith (name, ".mdebug.")) |
caaa3122 DJ |
7982 | return; |
7983 | ||
7984 | if (strcmp (name, ".mdebug.abi32") == 0) | |
7985 | *abip = MIPS_ABI_O32; | |
7986 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
7987 | *abip = MIPS_ABI_N32; | |
62a49b2c | 7988 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 7989 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
7990 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
7991 | *abip = MIPS_ABI_O64; | |
7992 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
7993 | *abip = MIPS_ABI_EABI32; | |
7994 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
7995 | *abip = MIPS_ABI_EABI64; | |
7996 | else | |
8a3fe4f8 | 7997 | warning (_("unsupported ABI %s."), name + 8); |
caaa3122 DJ |
7998 | } |
7999 | ||
22e47e37 FF |
8000 | static void |
8001 | mips_find_long_section (bfd *abfd, asection *sect, void *obj) | |
8002 | { | |
8003 | int *lbp = (int *) obj; | |
8004 | const char *name = bfd_get_section_name (abfd, sect); | |
8005 | ||
61012eef | 8006 | if (startswith (name, ".gcc_compiled_long32")) |
22e47e37 | 8007 | *lbp = 32; |
61012eef | 8008 | else if (startswith (name, ".gcc_compiled_long64")) |
22e47e37 | 8009 | *lbp = 64; |
61012eef | 8010 | else if (startswith (name, ".gcc_compiled_long")) |
22e47e37 FF |
8011 | warning (_("unrecognized .gcc_compiled_longXX")); |
8012 | } | |
8013 | ||
2e4ebe70 DJ |
8014 | static enum mips_abi |
8015 | global_mips_abi (void) | |
8016 | { | |
8017 | int i; | |
8018 | ||
8019 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
8020 | if (mips_abi_strings[i] == mips_abi_string) | |
8021 | return (enum mips_abi) i; | |
8022 | ||
e2e0b3e5 | 8023 | internal_error (__FILE__, __LINE__, _("unknown ABI string")); |
2e4ebe70 DJ |
8024 | } |
8025 | ||
4cc0665f MR |
8026 | /* Return the default compressed instruction set, either of MIPS16 |
8027 | or microMIPS, selected when none could have been determined from | |
8028 | the ELF header of the binary being executed (or no binary has been | |
8029 | selected. */ | |
8030 | ||
8031 | static enum mips_isa | |
8032 | global_mips_compression (void) | |
8033 | { | |
8034 | int i; | |
8035 | ||
8036 | for (i = 0; mips_compression_strings[i] != NULL; i++) | |
8037 | if (mips_compression_strings[i] == mips_compression_string) | |
8038 | return (enum mips_isa) i; | |
8039 | ||
8040 | internal_error (__FILE__, __LINE__, _("unknown compressed ISA string")); | |
8041 | } | |
8042 | ||
29709017 DJ |
8043 | static void |
8044 | mips_register_g_packet_guesses (struct gdbarch *gdbarch) | |
8045 | { | |
29709017 DJ |
8046 | /* If the size matches the set of 32-bit or 64-bit integer registers, |
8047 | assume that's what we've got. */ | |
4eb0ad19 DJ |
8048 | register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32); |
8049 | register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64); | |
29709017 DJ |
8050 | |
8051 | /* If the size matches the full set of registers GDB traditionally | |
8052 | knows about, including floating point, for either 32-bit or | |
8053 | 64-bit, assume that's what we've got. */ | |
4eb0ad19 DJ |
8054 | register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32); |
8055 | register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64); | |
29709017 DJ |
8056 | |
8057 | /* Otherwise we don't have a useful guess. */ | |
8058 | } | |
8059 | ||
f8b73d13 DJ |
8060 | static struct value * |
8061 | value_of_mips_user_reg (struct frame_info *frame, const void *baton) | |
8062 | { | |
19ba03f4 | 8063 | const int *reg_p = (const int *) baton; |
f8b73d13 DJ |
8064 | return value_of_register (*reg_p, frame); |
8065 | } | |
8066 | ||
c2d11a7d | 8067 | static struct gdbarch * |
6d82d43b | 8068 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 8069 | { |
c2d11a7d JM |
8070 | struct gdbarch *gdbarch; |
8071 | struct gdbarch_tdep *tdep; | |
8072 | int elf_flags; | |
2e4ebe70 | 8073 | enum mips_abi mips_abi, found_abi, wanted_abi; |
f8b73d13 | 8074 | int i, num_regs; |
8d5838b5 | 8075 | enum mips_fpu_type fpu_type; |
f8b73d13 | 8076 | struct tdesc_arch_data *tdesc_data = NULL; |
d929bc19 | 8077 | int elf_fpu_type = Val_GNU_MIPS_ABI_FP_ANY; |
1faeff08 MR |
8078 | const char **reg_names; |
8079 | struct mips_regnum mips_regnum, *regnum; | |
4cc0665f | 8080 | enum mips_isa mips_isa; |
1faeff08 MR |
8081 | int dspacc; |
8082 | int dspctl; | |
8083 | ||
ec03c1ac AC |
8084 | /* First of all, extract the elf_flags, if available. */ |
8085 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
8086 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
8087 | else if (arches != NULL) |
8088 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
8089 | else |
8090 | elf_flags = 0; | |
8091 | if (gdbarch_debug) | |
8092 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 8093 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 8094 | |
102182a9 | 8095 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
8096 | switch ((elf_flags & EF_MIPS_ABI)) |
8097 | { | |
8098 | case E_MIPS_ABI_O32: | |
ec03c1ac | 8099 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
8100 | break; |
8101 | case E_MIPS_ABI_O64: | |
ec03c1ac | 8102 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
8103 | break; |
8104 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 8105 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
8106 | break; |
8107 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 8108 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
8109 | break; |
8110 | default: | |
acdb74a0 | 8111 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 8112 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 8113 | else |
ec03c1ac | 8114 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
8115 | break; |
8116 | } | |
acdb74a0 | 8117 | |
caaa3122 | 8118 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
8119 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
8120 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 8121 | |
dc305454 | 8122 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
8123 | MIPS architecture (if there is one). */ |
8124 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
8125 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 8126 | |
32a6503c | 8127 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 8128 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
8129 | && info.bfd_arch_info != NULL |
8130 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
8131 | { | |
8132 | switch (info.bfd_arch_info->mach) | |
8133 | { | |
8134 | case bfd_mach_mips3900: | |
ec03c1ac | 8135 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
8136 | break; |
8137 | case bfd_mach_mips4100: | |
8138 | case bfd_mach_mips5000: | |
ec03c1ac | 8139 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 8140 | break; |
1d06468c EZ |
8141 | case bfd_mach_mips8000: |
8142 | case bfd_mach_mips10000: | |
32a6503c KB |
8143 | /* On Irix, ELF64 executables use the N64 ABI. The |
8144 | pseudo-sections which describe the ABI aren't present | |
8145 | on IRIX. (Even for executables created by gcc.) */ | |
e6c2f47b PA |
8146 | if (info.abfd != NULL |
8147 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
28d169de | 8148 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) |
ec03c1ac | 8149 | found_abi = MIPS_ABI_N64; |
28d169de | 8150 | else |
ec03c1ac | 8151 | found_abi = MIPS_ABI_N32; |
1d06468c | 8152 | break; |
bf64bfd6 AC |
8153 | } |
8154 | } | |
2e4ebe70 | 8155 | |
26c53e50 DJ |
8156 | /* Default 64-bit objects to N64 instead of O32. */ |
8157 | if (found_abi == MIPS_ABI_UNKNOWN | |
8158 | && info.abfd != NULL | |
8159 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
8160 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
8161 | found_abi = MIPS_ABI_N64; | |
8162 | ||
ec03c1ac AC |
8163 | if (gdbarch_debug) |
8164 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
8165 | found_abi); | |
8166 | ||
8167 | /* What has the user specified from the command line? */ | |
8168 | wanted_abi = global_mips_abi (); | |
8169 | if (gdbarch_debug) | |
8170 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
8171 | wanted_abi); | |
2e4ebe70 DJ |
8172 | |
8173 | /* Now that we have found what the ABI for this binary would be, | |
8174 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
8175 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
8176 | mips_abi = wanted_abi; | |
ec03c1ac AC |
8177 | else if (found_abi != MIPS_ABI_UNKNOWN) |
8178 | mips_abi = found_abi; | |
8179 | else | |
8180 | mips_abi = MIPS_ABI_O32; | |
8181 | if (gdbarch_debug) | |
8182 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
8183 | mips_abi); | |
2e4ebe70 | 8184 | |
c5196c92 MR |
8185 | /* Make sure we don't use a 32-bit architecture with a 64-bit ABI. */ |
8186 | if (mips_abi != MIPS_ABI_EABI32 | |
8187 | && mips_abi != MIPS_ABI_O32 | |
8188 | && info.bfd_arch_info != NULL | |
8189 | && info.bfd_arch_info->arch == bfd_arch_mips | |
8190 | && info.bfd_arch_info->bits_per_word < 64) | |
8191 | info.bfd_arch_info = bfd_lookup_arch (bfd_arch_mips, bfd_mach_mips4000); | |
8192 | ||
4cc0665f MR |
8193 | /* Determine the default compressed ISA. */ |
8194 | if ((elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0 | |
8195 | && (elf_flags & EF_MIPS_ARCH_ASE_M16) == 0) | |
8196 | mips_isa = ISA_MICROMIPS; | |
8197 | else if ((elf_flags & EF_MIPS_ARCH_ASE_M16) != 0 | |
8198 | && (elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) == 0) | |
8199 | mips_isa = ISA_MIPS16; | |
8200 | else | |
8201 | mips_isa = global_mips_compression (); | |
8202 | mips_compression_string = mips_compression_strings[mips_isa]; | |
8203 | ||
ec03c1ac | 8204 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 8205 | if (gdbarch_debug) |
ec03c1ac | 8206 | fprintf_unfiltered (gdb_stdlog, |
025bb325 MS |
8207 | "mips_gdbarch_init: " |
8208 | "mips64_transfers_32bit_regs_p = %d\n", | |
ec03c1ac | 8209 | mips64_transfers_32bit_regs_p); |
0dadbba0 | 8210 | |
8d5838b5 | 8211 | /* Determine the MIPS FPU type. */ |
609ca2b9 DJ |
8212 | #ifdef HAVE_ELF |
8213 | if (info.abfd | |
8214 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
8215 | elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
8216 | Tag_GNU_MIPS_ABI_FP); | |
8217 | #endif /* HAVE_ELF */ | |
8218 | ||
8d5838b5 AC |
8219 | if (!mips_fpu_type_auto) |
8220 | fpu_type = mips_fpu_type; | |
d929bc19 | 8221 | else if (elf_fpu_type != Val_GNU_MIPS_ABI_FP_ANY) |
609ca2b9 DJ |
8222 | { |
8223 | switch (elf_fpu_type) | |
8224 | { | |
d929bc19 | 8225 | case Val_GNU_MIPS_ABI_FP_DOUBLE: |
609ca2b9 DJ |
8226 | fpu_type = MIPS_FPU_DOUBLE; |
8227 | break; | |
d929bc19 | 8228 | case Val_GNU_MIPS_ABI_FP_SINGLE: |
609ca2b9 DJ |
8229 | fpu_type = MIPS_FPU_SINGLE; |
8230 | break; | |
d929bc19 | 8231 | case Val_GNU_MIPS_ABI_FP_SOFT: |
609ca2b9 DJ |
8232 | default: |
8233 | /* Soft float or unknown. */ | |
8234 | fpu_type = MIPS_FPU_NONE; | |
8235 | break; | |
8236 | } | |
8237 | } | |
8d5838b5 AC |
8238 | else if (info.bfd_arch_info != NULL |
8239 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
8240 | switch (info.bfd_arch_info->mach) | |
8241 | { | |
8242 | case bfd_mach_mips3900: | |
8243 | case bfd_mach_mips4100: | |
8244 | case bfd_mach_mips4111: | |
a9d61c86 | 8245 | case bfd_mach_mips4120: |
8d5838b5 AC |
8246 | fpu_type = MIPS_FPU_NONE; |
8247 | break; | |
8248 | case bfd_mach_mips4650: | |
8249 | fpu_type = MIPS_FPU_SINGLE; | |
8250 | break; | |
8251 | default: | |
8252 | fpu_type = MIPS_FPU_DOUBLE; | |
8253 | break; | |
8254 | } | |
8255 | else if (arches != NULL) | |
a2f1f308 | 8256 | fpu_type = MIPS_FPU_TYPE (arches->gdbarch); |
8d5838b5 AC |
8257 | else |
8258 | fpu_type = MIPS_FPU_DOUBLE; | |
8259 | if (gdbarch_debug) | |
8260 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 8261 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 8262 | |
29709017 DJ |
8263 | /* Check for blatant incompatibilities. */ |
8264 | ||
8265 | /* If we have only 32-bit registers, then we can't debug a 64-bit | |
8266 | ABI. */ | |
8267 | if (info.target_desc | |
8268 | && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL | |
8269 | && mips_abi != MIPS_ABI_EABI32 | |
8270 | && mips_abi != MIPS_ABI_O32) | |
37c33887 MR |
8271 | return NULL; |
8272 | ||
8273 | /* Fill in the OS dependent register numbers and names. */ | |
8274 | if (info.osabi == GDB_OSABI_LINUX) | |
f8b73d13 | 8275 | { |
37c33887 MR |
8276 | mips_regnum.fp0 = 38; |
8277 | mips_regnum.pc = 37; | |
8278 | mips_regnum.cause = 36; | |
8279 | mips_regnum.badvaddr = 35; | |
8280 | mips_regnum.hi = 34; | |
8281 | mips_regnum.lo = 33; | |
8282 | mips_regnum.fp_control_status = 70; | |
8283 | mips_regnum.fp_implementation_revision = 71; | |
8284 | mips_regnum.dspacc = -1; | |
8285 | mips_regnum.dspctl = -1; | |
8286 | dspacc = 72; | |
8287 | dspctl = 78; | |
8288 | num_regs = 90; | |
8289 | reg_names = mips_linux_reg_names; | |
8290 | } | |
8291 | else | |
8292 | { | |
8293 | mips_regnum.lo = MIPS_EMBED_LO_REGNUM; | |
8294 | mips_regnum.hi = MIPS_EMBED_HI_REGNUM; | |
8295 | mips_regnum.badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
8296 | mips_regnum.cause = MIPS_EMBED_CAUSE_REGNUM; | |
8297 | mips_regnum.pc = MIPS_EMBED_PC_REGNUM; | |
8298 | mips_regnum.fp0 = MIPS_EMBED_FP0_REGNUM; | |
8299 | mips_regnum.fp_control_status = 70; | |
8300 | mips_regnum.fp_implementation_revision = 71; | |
8301 | mips_regnum.dspacc = dspacc = -1; | |
8302 | mips_regnum.dspctl = dspctl = -1; | |
8303 | num_regs = MIPS_LAST_EMBED_REGNUM + 1; | |
8304 | if (info.bfd_arch_info != NULL | |
8305 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
8306 | reg_names = mips_tx39_reg_names; | |
8307 | else | |
8308 | reg_names = mips_generic_reg_names; | |
8309 | } | |
8310 | ||
8311 | /* Check any target description for validity. */ | |
8312 | if (tdesc_has_registers (info.target_desc)) | |
8313 | { | |
8314 | static const char *const mips_gprs[] = { | |
8315 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
8316 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
8317 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
8318 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
8319 | }; | |
8320 | static const char *const mips_fprs[] = { | |
8321 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
8322 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
8323 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
8324 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
8325 | }; | |
8326 | ||
8327 | const struct tdesc_feature *feature; | |
8328 | int valid_p; | |
8329 | ||
8330 | feature = tdesc_find_feature (info.target_desc, | |
8331 | "org.gnu.gdb.mips.cpu"); | |
8332 | if (feature == NULL) | |
8333 | return NULL; | |
8334 | ||
8335 | tdesc_data = tdesc_data_alloc (); | |
8336 | ||
8337 | valid_p = 1; | |
8338 | for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) | |
8339 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
8340 | mips_gprs[i]); | |
8341 | ||
8342 | ||
8343 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8344 | mips_regnum.lo, "lo"); | |
8345 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8346 | mips_regnum.hi, "hi"); | |
8347 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8348 | mips_regnum.pc, "pc"); | |
8349 | ||
8350 | if (!valid_p) | |
8351 | { | |
8352 | tdesc_data_cleanup (tdesc_data); | |
8353 | return NULL; | |
8354 | } | |
8355 | ||
8356 | feature = tdesc_find_feature (info.target_desc, | |
8357 | "org.gnu.gdb.mips.cp0"); | |
8358 | if (feature == NULL) | |
8359 | { | |
8360 | tdesc_data_cleanup (tdesc_data); | |
8361 | return NULL; | |
8362 | } | |
8363 | ||
8364 | valid_p = 1; | |
8365 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8366 | mips_regnum.badvaddr, "badvaddr"); | |
8367 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8368 | MIPS_PS_REGNUM, "status"); | |
8369 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8370 | mips_regnum.cause, "cause"); | |
8371 | ||
8372 | if (!valid_p) | |
8373 | { | |
8374 | tdesc_data_cleanup (tdesc_data); | |
8375 | return NULL; | |
8376 | } | |
8377 | ||
8378 | /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS | |
8379 | backend is not prepared for that, though. */ | |
8380 | feature = tdesc_find_feature (info.target_desc, | |
8381 | "org.gnu.gdb.mips.fpu"); | |
8382 | if (feature == NULL) | |
8383 | { | |
8384 | tdesc_data_cleanup (tdesc_data); | |
8385 | return NULL; | |
8386 | } | |
8387 | ||
8388 | valid_p = 1; | |
8389 | for (i = 0; i < 32; i++) | |
8390 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8391 | i + mips_regnum.fp0, mips_fprs[i]); | |
8392 | ||
8393 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8394 | mips_regnum.fp_control_status, | |
8395 | "fcsr"); | |
8396 | valid_p | |
8397 | &= tdesc_numbered_register (feature, tdesc_data, | |
8398 | mips_regnum.fp_implementation_revision, | |
8399 | "fir"); | |
8400 | ||
8401 | if (!valid_p) | |
8402 | { | |
8403 | tdesc_data_cleanup (tdesc_data); | |
8404 | return NULL; | |
8405 | } | |
8406 | ||
8407 | num_regs = mips_regnum.fp_implementation_revision + 1; | |
8408 | ||
8409 | if (dspacc >= 0) | |
8410 | { | |
8411 | feature = tdesc_find_feature (info.target_desc, | |
8412 | "org.gnu.gdb.mips.dsp"); | |
8413 | /* The DSP registers are optional; it's OK if they are absent. */ | |
8414 | if (feature != NULL) | |
8415 | { | |
8416 | i = 0; | |
8417 | valid_p = 1; | |
8418 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8419 | dspacc + i++, "hi1"); | |
8420 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8421 | dspacc + i++, "lo1"); | |
8422 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8423 | dspacc + i++, "hi2"); | |
8424 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8425 | dspacc + i++, "lo2"); | |
8426 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8427 | dspacc + i++, "hi3"); | |
8428 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8429 | dspacc + i++, "lo3"); | |
8430 | ||
8431 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8432 | dspctl, "dspctl"); | |
8433 | ||
8434 | if (!valid_p) | |
8435 | { | |
8436 | tdesc_data_cleanup (tdesc_data); | |
8437 | return NULL; | |
8438 | } | |
8439 | ||
8440 | mips_regnum.dspacc = dspacc; | |
8441 | mips_regnum.dspctl = dspctl; | |
8442 | ||
8443 | num_regs = mips_regnum.dspctl + 1; | |
8444 | } | |
8445 | } | |
8446 | ||
8447 | /* It would be nice to detect an attempt to use a 64-bit ABI | |
8448 | when only 32-bit registers are provided. */ | |
8449 | reg_names = NULL; | |
f8b73d13 | 8450 | } |
29709017 | 8451 | |
025bb325 | 8452 | /* Try to find a pre-existing architecture. */ |
c2d11a7d JM |
8453 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
8454 | arches != NULL; | |
8455 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
8456 | { | |
d54398a7 MR |
8457 | /* MIPS needs to be pedantic about which ABI and the compressed |
8458 | ISA variation the object is using. */ | |
9103eae0 | 8459 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 8460 | continue; |
9103eae0 | 8461 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 8462 | continue; |
d54398a7 MR |
8463 | if (gdbarch_tdep (arches->gdbarch)->mips_isa != mips_isa) |
8464 | continue; | |
719ec221 AC |
8465 | /* Need to be pedantic about which register virtual size is |
8466 | used. */ | |
8467 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
8468 | != mips64_transfers_32bit_regs_p) | |
8469 | continue; | |
8d5838b5 | 8470 | /* Be pedantic about which FPU is selected. */ |
a2f1f308 | 8471 | if (MIPS_FPU_TYPE (arches->gdbarch) != fpu_type) |
8d5838b5 | 8472 | continue; |
f8b73d13 DJ |
8473 | |
8474 | if (tdesc_data != NULL) | |
8475 | tdesc_data_cleanup (tdesc_data); | |
4be87837 | 8476 | return arches->gdbarch; |
c2d11a7d JM |
8477 | } |
8478 | ||
102182a9 | 8479 | /* Need a new architecture. Fill in a target specific vector. */ |
cdd238da | 8480 | tdep = XCNEW (struct gdbarch_tdep); |
c2d11a7d JM |
8481 | gdbarch = gdbarch_alloc (&info, tdep); |
8482 | tdep->elf_flags = elf_flags; | |
719ec221 | 8483 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
8484 | tdep->found_abi = found_abi; |
8485 | tdep->mips_abi = mips_abi; | |
4cc0665f | 8486 | tdep->mips_isa = mips_isa; |
8d5838b5 | 8487 | tdep->mips_fpu_type = fpu_type; |
29709017 DJ |
8488 | tdep->register_size_valid_p = 0; |
8489 | tdep->register_size = 0; | |
8490 | ||
8491 | if (info.target_desc) | |
8492 | { | |
8493 | /* Some useful properties can be inferred from the target. */ | |
8494 | if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) | |
8495 | { | |
8496 | tdep->register_size_valid_p = 1; | |
8497 | tdep->register_size = 4; | |
8498 | } | |
8499 | else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) | |
8500 | { | |
8501 | tdep->register_size_valid_p = 1; | |
8502 | tdep->register_size = 8; | |
8503 | } | |
8504 | } | |
c2d11a7d | 8505 | |
102182a9 | 8506 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
8507 | set_gdbarch_short_bit (gdbarch, 16); |
8508 | set_gdbarch_int_bit (gdbarch, 32); | |
8509 | set_gdbarch_float_bit (gdbarch, 32); | |
8510 | set_gdbarch_double_bit (gdbarch, 64); | |
8511 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
8512 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
8513 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
8514 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 8515 | |
175ff332 HZ |
8516 | set_gdbarch_ax_pseudo_register_collect (gdbarch, |
8517 | mips_ax_pseudo_register_collect); | |
8518 | set_gdbarch_ax_pseudo_register_push_stack | |
8519 | (gdbarch, mips_ax_pseudo_register_push_stack); | |
8520 | ||
6d82d43b | 8521 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 | 8522 | mips_elf_make_msymbol_special); |
3e29f34a MR |
8523 | set_gdbarch_make_symbol_special (gdbarch, mips_make_symbol_special); |
8524 | set_gdbarch_adjust_dwarf2_addr (gdbarch, mips_adjust_dwarf2_addr); | |
8525 | set_gdbarch_adjust_dwarf2_line (gdbarch, mips_adjust_dwarf2_line); | |
f7ab6ec6 | 8526 | |
1faeff08 MR |
8527 | regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, struct mips_regnum); |
8528 | *regnum = mips_regnum; | |
1faeff08 MR |
8529 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
8530 | set_gdbarch_num_regs (gdbarch, num_regs); | |
8531 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
8532 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
8533 | set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer); | |
8534 | tdep->mips_processor_reg_names = reg_names; | |
8535 | tdep->regnum = regnum; | |
fe29b929 | 8536 | |
0dadbba0 | 8537 | switch (mips_abi) |
c2d11a7d | 8538 | { |
0dadbba0 | 8539 | case MIPS_ABI_O32: |
25ab4790 | 8540 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 8541 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
4c7d22cb | 8542 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 8543 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 8544 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8545 | set_gdbarch_long_bit (gdbarch, 32); |
8546 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8547 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8548 | break; | |
0dadbba0 | 8549 | case MIPS_ABI_O64: |
25ab4790 | 8550 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
9c8fdbfa | 8551 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
4c7d22cb | 8552 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 8553 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 8554 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8555 | set_gdbarch_long_bit (gdbarch, 32); |
8556 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8557 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8558 | break; | |
0dadbba0 | 8559 | case MIPS_ABI_EABI32: |
25ab4790 | 8560 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 8561 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 8562 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8563 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 8564 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8565 | set_gdbarch_long_bit (gdbarch, 32); |
8566 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8567 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8568 | break; | |
0dadbba0 | 8569 | case MIPS_ABI_EABI64: |
25ab4790 | 8570 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 8571 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 8572 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8573 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 8574 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8575 | set_gdbarch_long_bit (gdbarch, 64); |
8576 | set_gdbarch_ptr_bit (gdbarch, 64); | |
8577 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8578 | break; | |
0dadbba0 | 8579 | case MIPS_ABI_N32: |
25ab4790 | 8580 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 8581 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 8582 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8583 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 8584 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
8585 | set_gdbarch_long_bit (gdbarch, 32); |
8586 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8587 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 8588 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 8589 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
28d169de KB |
8590 | break; |
8591 | case MIPS_ABI_N64: | |
25ab4790 | 8592 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 8593 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 8594 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8595 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
8596 | tdep->default_mask_address_p = 0; |
8597 | set_gdbarch_long_bit (gdbarch, 64); | |
8598 | set_gdbarch_ptr_bit (gdbarch, 64); | |
8599 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 8600 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 8601 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
0dadbba0 | 8602 | break; |
c2d11a7d | 8603 | default: |
e2e0b3e5 | 8604 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); |
c2d11a7d JM |
8605 | } |
8606 | ||
22e47e37 FF |
8607 | /* GCC creates a pseudo-section whose name specifies the size of |
8608 | longs, since -mlong32 or -mlong64 may be used independent of | |
8609 | other options. How those options affect pointer sizes is ABI and | |
8610 | architecture dependent, so use them to override the default sizes | |
8611 | set by the ABI. This table shows the relationship between ABI, | |
8612 | -mlongXX, and size of pointers: | |
8613 | ||
8614 | ABI -mlongXX ptr bits | |
8615 | --- -------- -------- | |
8616 | o32 32 32 | |
8617 | o32 64 32 | |
8618 | n32 32 32 | |
8619 | n32 64 64 | |
8620 | o64 32 32 | |
8621 | o64 64 64 | |
8622 | n64 32 32 | |
8623 | n64 64 64 | |
8624 | eabi32 32 32 | |
8625 | eabi32 64 32 | |
8626 | eabi64 32 32 | |
8627 | eabi64 64 64 | |
8628 | ||
8629 | Note that for o32 and eabi32, pointers are always 32 bits | |
8630 | regardless of any -mlongXX option. For all others, pointers and | |
025bb325 | 8631 | longs are the same, as set by -mlongXX or set by defaults. */ |
22e47e37 FF |
8632 | |
8633 | if (info.abfd != NULL) | |
8634 | { | |
8635 | int long_bit = 0; | |
8636 | ||
8637 | bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); | |
8638 | if (long_bit) | |
8639 | { | |
8640 | set_gdbarch_long_bit (gdbarch, long_bit); | |
8641 | switch (mips_abi) | |
8642 | { | |
8643 | case MIPS_ABI_O32: | |
8644 | case MIPS_ABI_EABI32: | |
8645 | break; | |
8646 | case MIPS_ABI_N32: | |
8647 | case MIPS_ABI_O64: | |
8648 | case MIPS_ABI_N64: | |
8649 | case MIPS_ABI_EABI64: | |
8650 | set_gdbarch_ptr_bit (gdbarch, long_bit); | |
8651 | break; | |
8652 | default: | |
8653 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); | |
8654 | } | |
8655 | } | |
8656 | } | |
8657 | ||
a5ea2558 AC |
8658 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
8659 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
8660 | comment: | |
8661 | ||
8662 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
8663 | flag in object files because to do so would make it impossible to | |
102182a9 | 8664 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 8665 | unnecessarily restrictive. |
361d1df0 | 8666 | |
a5ea2558 AC |
8667 | We could solve this problem by adding "-gp32" multilibs to gcc, |
8668 | but to set this flag before gcc is built with such multilibs will | |
8669 | break too many systems.'' | |
8670 | ||
8671 | But even more unhelpfully, the default linker output target for | |
8672 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
8673 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 8674 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
8675 | this flag to detect 32-bit mode would do the wrong thing given |
8676 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 8677 | as 32-bit programs by default. */ |
a5ea2558 | 8678 | |
6c997a34 | 8679 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 8680 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
c2d11a7d | 8681 | |
102182a9 MS |
8682 | /* Add/remove bits from an address. The MIPS needs be careful to |
8683 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
8684 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
8685 | ||
58dfe9ff AC |
8686 | /* Unwind the frame. */ |
8687 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
30244cd8 | 8688 | set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); |
b8a22b94 | 8689 | set_gdbarch_dummy_id (gdbarch, mips_dummy_id); |
10312cc4 | 8690 | |
102182a9 | 8691 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 8692 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
8693 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
8694 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
6d82d43b AC |
8695 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, |
8696 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 8697 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 8698 | |
025bb325 | 8699 | /* MIPS version of CALL_DUMMY. */ |
c2d11a7d | 8700 | |
2c76a0c7 JB |
8701 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
8702 | set_gdbarch_push_dummy_code (gdbarch, mips_push_dummy_code); | |
dc604539 | 8703 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 8704 | |
1bab7383 YQ |
8705 | set_gdbarch_print_float_info (gdbarch, mips_print_float_info); |
8706 | ||
87783b8b AC |
8707 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
8708 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
8709 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
8710 | ||
f7b9e9fc | 8711 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
04180708 YQ |
8712 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, mips_breakpoint_kind_from_pc); |
8713 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, mips_sw_breakpoint_from_kind); | |
c8cef75f MR |
8714 | set_gdbarch_adjust_breakpoint_address (gdbarch, |
8715 | mips_adjust_breakpoint_address); | |
f7b9e9fc AC |
8716 | |
8717 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 8718 | |
c9cf6e20 | 8719 | set_gdbarch_stack_frame_destroyed_p (gdbarch, mips_stack_frame_destroyed_p); |
97ab0fdd | 8720 | |
fc0c74b1 AC |
8721 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
8722 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
8723 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 8724 | |
a4b8ebc8 | 8725 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 8726 | |
e11c53d2 | 8727 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 8728 | |
471b9d15 MR |
8729 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); |
8730 | if (mips_abi == MIPS_ABI_N64) | |
8731 | set_gdbarch_disassembler_options_implicit | |
8732 | (gdbarch, (const char *) mips_disassembler_options_n64); | |
8733 | else if (mips_abi == MIPS_ABI_N32) | |
8734 | set_gdbarch_disassembler_options_implicit | |
8735 | (gdbarch, (const char *) mips_disassembler_options_n32); | |
9dae60cc | 8736 | else |
471b9d15 MR |
8737 | set_gdbarch_disassembler_options_implicit |
8738 | (gdbarch, (const char *) mips_disassembler_options_o32); | |
8739 | set_gdbarch_disassembler_options (gdbarch, &mips_disassembler_options); | |
8740 | set_gdbarch_valid_disassembler_options (gdbarch, | |
8741 | disassembler_options_mips ()); | |
e5ab0dce | 8742 | |
d92524f1 PM |
8743 | /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint, |
8744 | HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint | |
3a3bc038 | 8745 | need to all be folded into the target vector. Since they are |
d92524f1 PM |
8746 | being used as guards for target_stopped_by_watchpoint, why not have |
8747 | target_stopped_by_watchpoint return the type of watchpoint that the code | |
3a3bc038 AC |
8748 | is sitting on? */ |
8749 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
8750 | ||
e7d6a6d2 | 8751 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
757a7cc6 | 8752 | |
14132e89 MR |
8753 | /* NOTE drow/2012-04-25: We overload the core solib trampoline code |
8754 | to support MIPS16. This is a bad thing. Make sure not to do it | |
8755 | if we have an OS ABI that actually supports shared libraries, since | |
8756 | shared library support is more important. If we have an OS someday | |
8757 | that supports both shared libraries and MIPS16, we'll have to find | |
8758 | a better place for these. | |
8759 | macro/2012-04-25: But that applies to return trampolines only and | |
8760 | currently no MIPS OS ABI uses shared libraries that have them. */ | |
8761 | set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); | |
8762 | ||
025bb325 MS |
8763 | set_gdbarch_single_step_through_delay (gdbarch, |
8764 | mips_single_step_through_delay); | |
3352ef37 | 8765 | |
0d5de010 DJ |
8766 | /* Virtual tables. */ |
8767 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
8768 | ||
29709017 DJ |
8769 | mips_register_g_packet_guesses (gdbarch); |
8770 | ||
6de918a6 | 8771 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
0dba2a6c | 8772 | info.tdesc_data = tdesc_data; |
6de918a6 | 8773 | gdbarch_init_osabi (info, gdbarch); |
757a7cc6 | 8774 | |
9aac7884 MR |
8775 | /* The hook may have adjusted num_regs, fetch the final value and |
8776 | set pc_regnum and sp_regnum now that it has been fixed. */ | |
9aac7884 MR |
8777 | num_regs = gdbarch_num_regs (gdbarch); |
8778 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); | |
8779 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
8780 | ||
5792a79b | 8781 | /* Unwind the frame. */ |
b8a22b94 DJ |
8782 | dwarf2_append_unwinders (gdbarch); |
8783 | frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind); | |
8784 | frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind); | |
4cc0665f | 8785 | frame_unwind_append_unwinder (gdbarch, &mips_micro_frame_unwind); |
b8a22b94 | 8786 | frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind); |
2bd0c3d7 | 8787 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
eec63939 | 8788 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
45c9dd44 | 8789 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
4cc0665f | 8790 | frame_base_append_sniffer (gdbarch, mips_micro_frame_base_sniffer); |
45c9dd44 | 8791 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); |
5792a79b | 8792 | |
f8b73d13 DJ |
8793 | if (tdesc_data) |
8794 | { | |
8795 | set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); | |
7cc46491 | 8796 | tdesc_use_registers (gdbarch, info.target_desc, tdesc_data); |
f8b73d13 DJ |
8797 | |
8798 | /* Override the normal target description methods to handle our | |
8799 | dual real and pseudo registers. */ | |
8800 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
025bb325 MS |
8801 | set_gdbarch_register_reggroup_p (gdbarch, |
8802 | mips_tdesc_register_reggroup_p); | |
f8b73d13 DJ |
8803 | |
8804 | num_regs = gdbarch_num_regs (gdbarch); | |
8805 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
8806 | set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs); | |
8807 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
8808 | } | |
8809 | ||
8810 | /* Add ABI-specific aliases for the registers. */ | |
8811 | if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) | |
8812 | for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++) | |
8813 | user_reg_add (gdbarch, mips_n32_n64_aliases[i].name, | |
8814 | value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); | |
8815 | else | |
8816 | for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) | |
8817 | user_reg_add (gdbarch, mips_o32_aliases[i].name, | |
8818 | value_of_mips_user_reg, &mips_o32_aliases[i].regnum); | |
8819 | ||
8820 | /* Add some other standard aliases. */ | |
8821 | for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) | |
8822 | user_reg_add (gdbarch, mips_register_aliases[i].name, | |
8823 | value_of_mips_user_reg, &mips_register_aliases[i].regnum); | |
8824 | ||
865093a3 AR |
8825 | for (i = 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++) |
8826 | user_reg_add (gdbarch, mips_numeric_register_aliases[i].name, | |
8827 | value_of_mips_user_reg, | |
8828 | &mips_numeric_register_aliases[i].regnum); | |
8829 | ||
4b9b3959 AC |
8830 | return gdbarch; |
8831 | } | |
8832 | ||
2e4ebe70 | 8833 | static void |
eb4c3f4a TT |
8834 | mips_abi_update (const char *ignore_args, |
8835 | int from_tty, struct cmd_list_element *c) | |
2e4ebe70 DJ |
8836 | { |
8837 | struct gdbarch_info info; | |
8838 | ||
8839 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
8840 | mips_gdbarch_init will take care of the rest. */ | |
8841 | gdbarch_info_init (&info); | |
8842 | gdbarch_update_p (info); | |
8843 | } | |
8844 | ||
ad188201 KB |
8845 | /* Print out which MIPS ABI is in use. */ |
8846 | ||
8847 | static void | |
1f8ca57c JB |
8848 | show_mips_abi (struct ui_file *file, |
8849 | int from_tty, | |
8850 | struct cmd_list_element *ignored_cmd, | |
8851 | const char *ignored_value) | |
ad188201 | 8852 | { |
f5656ead | 8853 | if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips) |
1f8ca57c JB |
8854 | fprintf_filtered |
8855 | (file, | |
8856 | "The MIPS ABI is unknown because the current architecture " | |
8857 | "is not MIPS.\n"); | |
ad188201 KB |
8858 | else |
8859 | { | |
8860 | enum mips_abi global_abi = global_mips_abi (); | |
f5656ead | 8861 | enum mips_abi actual_abi = mips_abi (target_gdbarch ()); |
ad188201 KB |
8862 | const char *actual_abi_str = mips_abi_strings[actual_abi]; |
8863 | ||
8864 | if (global_abi == MIPS_ABI_UNKNOWN) | |
1f8ca57c JB |
8865 | fprintf_filtered |
8866 | (file, | |
8867 | "The MIPS ABI is set automatically (currently \"%s\").\n", | |
6d82d43b | 8868 | actual_abi_str); |
ad188201 | 8869 | else if (global_abi == actual_abi) |
1f8ca57c JB |
8870 | fprintf_filtered |
8871 | (file, | |
8872 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6d82d43b | 8873 | actual_abi_str); |
ad188201 KB |
8874 | else |
8875 | { | |
8876 | /* Probably shouldn't happen... */ | |
025bb325 MS |
8877 | fprintf_filtered (file, |
8878 | "The (auto detected) MIPS ABI \"%s\" is in use " | |
8879 | "even though the user setting was \"%s\".\n", | |
6d82d43b | 8880 | actual_abi_str, mips_abi_strings[global_abi]); |
ad188201 KB |
8881 | } |
8882 | } | |
8883 | } | |
8884 | ||
4cc0665f MR |
8885 | /* Print out which MIPS compressed ISA encoding is used. */ |
8886 | ||
8887 | static void | |
8888 | show_mips_compression (struct ui_file *file, int from_tty, | |
8889 | struct cmd_list_element *c, const char *value) | |
8890 | { | |
8891 | fprintf_filtered (file, _("The compressed ISA encoding used is %s.\n"), | |
8892 | value); | |
8893 | } | |
8894 | ||
a4f320fd MR |
8895 | /* Return a textual name for MIPS FPU type FPU_TYPE. */ |
8896 | ||
8897 | static const char * | |
8898 | mips_fpu_type_str (enum mips_fpu_type fpu_type) | |
8899 | { | |
8900 | switch (fpu_type) | |
8901 | { | |
8902 | case MIPS_FPU_NONE: | |
8903 | return "none"; | |
8904 | case MIPS_FPU_SINGLE: | |
8905 | return "single"; | |
8906 | case MIPS_FPU_DOUBLE: | |
8907 | return "double"; | |
8908 | default: | |
8909 | return "???"; | |
8910 | } | |
8911 | } | |
8912 | ||
4b9b3959 | 8913 | static void |
72a155b4 | 8914 | mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
4b9b3959 | 8915 | { |
72a155b4 | 8916 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4b9b3959 | 8917 | if (tdep != NULL) |
c2d11a7d | 8918 | { |
acdb74a0 AC |
8919 | int ef_mips_arch; |
8920 | int ef_mips_32bitmode; | |
f49e4e6d | 8921 | /* Determine the ISA. */ |
acdb74a0 AC |
8922 | switch (tdep->elf_flags & EF_MIPS_ARCH) |
8923 | { | |
8924 | case E_MIPS_ARCH_1: | |
8925 | ef_mips_arch = 1; | |
8926 | break; | |
8927 | case E_MIPS_ARCH_2: | |
8928 | ef_mips_arch = 2; | |
8929 | break; | |
8930 | case E_MIPS_ARCH_3: | |
8931 | ef_mips_arch = 3; | |
8932 | break; | |
8933 | case E_MIPS_ARCH_4: | |
93d56215 | 8934 | ef_mips_arch = 4; |
acdb74a0 AC |
8935 | break; |
8936 | default: | |
93d56215 | 8937 | ef_mips_arch = 0; |
acdb74a0 AC |
8938 | break; |
8939 | } | |
f49e4e6d | 8940 | /* Determine the size of a pointer. */ |
acdb74a0 | 8941 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); |
4b9b3959 AC |
8942 | fprintf_unfiltered (file, |
8943 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 8944 | tdep->elf_flags); |
4b9b3959 | 8945 | fprintf_unfiltered (file, |
acdb74a0 AC |
8946 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
8947 | ef_mips_32bitmode); | |
8948 | fprintf_unfiltered (file, | |
8949 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
8950 | ef_mips_arch); | |
8951 | fprintf_unfiltered (file, | |
8952 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 8953 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b | 8954 | fprintf_unfiltered (file, |
025bb325 MS |
8955 | "mips_dump_tdep: " |
8956 | "mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 8957 | mips_mask_address_p (tdep), |
4014092b | 8958 | tdep->default_mask_address_p); |
c2d11a7d | 8959 | } |
4b9b3959 AC |
8960 | fprintf_unfiltered (file, |
8961 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
8962 | MIPS_DEFAULT_FPU_TYPE, | |
a4f320fd | 8963 | mips_fpu_type_str (MIPS_DEFAULT_FPU_TYPE)); |
74ed0bb4 MD |
8964 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", |
8965 | MIPS_EABI (gdbarch)); | |
4b9b3959 AC |
8966 | fprintf_unfiltered (file, |
8967 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
74ed0bb4 | 8968 | MIPS_FPU_TYPE (gdbarch), |
a4f320fd | 8969 | mips_fpu_type_str (MIPS_FPU_TYPE (gdbarch))); |
c2d11a7d JM |
8970 | } |
8971 | ||
c906108c | 8972 | void |
acdb74a0 | 8973 | _initialize_mips_tdep (void) |
c906108c SS |
8974 | { |
8975 | static struct cmd_list_element *mipsfpulist = NULL; | |
c906108c | 8976 | |
6d82d43b | 8977 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
8978 | if (MIPS_ABI_LAST + 1 |
8979 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
e2e0b3e5 | 8980 | internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync")); |
2e4ebe70 | 8981 | |
4b9b3959 | 8982 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 8983 | |
8d5f9dcb DJ |
8984 | mips_pdr_data = register_objfile_data (); |
8985 | ||
4eb0ad19 DJ |
8986 | /* Create feature sets with the appropriate properties. The values |
8987 | are not important. */ | |
8988 | mips_tdesc_gp32 = allocate_target_description (); | |
8989 | set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, ""); | |
8990 | ||
8991 | mips_tdesc_gp64 = allocate_target_description (); | |
8992 | set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, ""); | |
8993 | ||
025bb325 | 8994 | /* Add root prefix command for all "set mips"/"show mips" commands. */ |
a5ea2558 | 8995 | add_prefix_cmd ("mips", no_class, set_mips_command, |
1bedd215 | 8996 | _("Various MIPS specific commands."), |
a5ea2558 AC |
8997 | &setmipscmdlist, "set mips ", 0, &setlist); |
8998 | ||
8999 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
1bedd215 | 9000 | _("Various MIPS specific commands."), |
a5ea2558 AC |
9001 | &showmipscmdlist, "show mips ", 0, &showlist); |
9002 | ||
025bb325 | 9003 | /* Allow the user to override the ABI. */ |
7ab04401 AC |
9004 | add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, |
9005 | &mips_abi_string, _("\ | |
9006 | Set the MIPS ABI used by this program."), _("\ | |
9007 | Show the MIPS ABI used by this program."), _("\ | |
9008 | This option can be set to one of:\n\ | |
9009 | auto - the default ABI associated with the current binary\n\ | |
9010 | o32\n\ | |
9011 | o64\n\ | |
9012 | n32\n\ | |
9013 | n64\n\ | |
9014 | eabi32\n\ | |
9015 | eabi64"), | |
9016 | mips_abi_update, | |
9017 | show_mips_abi, | |
9018 | &setmipscmdlist, &showmipscmdlist); | |
2e4ebe70 | 9019 | |
4cc0665f MR |
9020 | /* Allow the user to set the ISA to assume for compressed code if ELF |
9021 | file flags don't tell or there is no program file selected. This | |
9022 | setting is updated whenever unambiguous ELF file flags are interpreted, | |
9023 | and carried over to subsequent sessions. */ | |
9024 | add_setshow_enum_cmd ("compression", class_obscure, mips_compression_strings, | |
9025 | &mips_compression_string, _("\ | |
9026 | Set the compressed ISA encoding used by MIPS code."), _("\ | |
9027 | Show the compressed ISA encoding used by MIPS code."), _("\ | |
9028 | Select the compressed ISA encoding used in functions that have no symbol\n\ | |
9029 | information available. The encoding can be set to either of:\n\ | |
9030 | mips16\n\ | |
9031 | micromips\n\ | |
9032 | and is updated automatically from ELF file flags if available."), | |
9033 | mips_abi_update, | |
9034 | show_mips_compression, | |
9035 | &setmipscmdlist, &showmipscmdlist); | |
9036 | ||
c906108c SS |
9037 | /* Let the user turn off floating point and set the fence post for |
9038 | heuristic_proc_start. */ | |
9039 | ||
9040 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
1bedd215 | 9041 | _("Set use of MIPS floating-point coprocessor."), |
c906108c SS |
9042 | &mipsfpulist, "set mipsfpu ", 0, &setlist); |
9043 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
1a966eab | 9044 | _("Select single-precision MIPS floating-point coprocessor."), |
c906108c SS |
9045 | &mipsfpulist); |
9046 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
1a966eab | 9047 | _("Select double-precision MIPS floating-point coprocessor."), |
c906108c SS |
9048 | &mipsfpulist); |
9049 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
9050 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
9051 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
9052 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
1a966eab | 9053 | _("Select no MIPS floating-point coprocessor."), &mipsfpulist); |
c906108c SS |
9054 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
9055 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
9056 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
9057 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
1a966eab | 9058 | _("Select MIPS floating-point coprocessor automatically."), |
c906108c SS |
9059 | &mipsfpulist); |
9060 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
1a966eab | 9061 | _("Show current use of MIPS floating-point coprocessor target."), |
c906108c SS |
9062 | &showlist); |
9063 | ||
c906108c SS |
9064 | /* We really would like to have both "0" and "unlimited" work, but |
9065 | command.c doesn't deal with that. So make it a var_zinteger | |
9066 | because the user can always use "999999" or some such for unlimited. */ | |
6bcadd06 | 9067 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
7915a72c AC |
9068 | &heuristic_fence_post, _("\ |
9069 | Set the distance searched for the start of a function."), _("\ | |
9070 | Show the distance searched for the start of a function."), _("\ | |
c906108c SS |
9071 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
9072 | program for the start of a function. This command sets the distance of the\n\ | |
7915a72c | 9073 | search. The only need to set it is when debugging a stripped executable."), |
2c5b56ce | 9074 | reinit_frame_cache_sfunc, |
025bb325 MS |
9075 | NULL, /* FIXME: i18n: The distance searched for |
9076 | the start of a function is %s. */ | |
6bcadd06 | 9077 | &setlist, &showlist); |
c906108c SS |
9078 | |
9079 | /* Allow the user to control whether the upper bits of 64-bit | |
9080 | addresses should be zeroed. */ | |
7915a72c AC |
9081 | add_setshow_auto_boolean_cmd ("mask-address", no_class, |
9082 | &mask_address_var, _("\ | |
9083 | Set zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
9084 | Show zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
cce7e648 | 9085 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\ |
7915a72c | 9086 | allow GDB to determine the correct value."), |
08546159 AC |
9087 | NULL, show_mask_address, |
9088 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
9089 | |
9090 | /* Allow the user to control the size of 32 bit registers within the | |
9091 | raw remote packet. */ | |
b3f42336 | 9092 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
7915a72c AC |
9093 | &mips64_transfers_32bit_regs_p, _("\ |
9094 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
9095 | _("\ | |
9096 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
9097 | _("\ | |
719ec221 AC |
9098 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
9099 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
7915a72c | 9100 | 64 bits for others. Use \"off\" to disable compatibility mode"), |
2c5b56ce | 9101 | set_mips64_transfers_32bit_regs, |
025bb325 MS |
9102 | NULL, /* FIXME: i18n: Compatibility with 64-bit |
9103 | MIPS target that transfers 32-bit | |
9104 | quantities is %s. */ | |
7915a72c | 9105 | &setlist, &showlist); |
9ace0497 | 9106 | |
025bb325 | 9107 | /* Debug this files internals. */ |
ccce17b0 YQ |
9108 | add_setshow_zuinteger_cmd ("mips", class_maintenance, |
9109 | &mips_debug, _("\ | |
7915a72c AC |
9110 | Set mips debugging."), _("\ |
9111 | Show mips debugging."), _("\ | |
9112 | When non-zero, mips specific debugging is enabled."), | |
ccce17b0 YQ |
9113 | NULL, |
9114 | NULL, /* FIXME: i18n: Mips debugging is | |
9115 | currently %s. */ | |
9116 | &setdebuglist, &showdebuglist); | |
c906108c | 9117 | } |