Commit | Line | Data |
---|---|---|
c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
3666a048 | 3 | Copyright (C) 1988-2021 Free Software Foundation, Inc. |
bf64bfd6 | 4 | |
c906108c SS |
5 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
6 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
7 | ||
c5aa993b | 8 | This file is part of GDB. |
c906108c | 9 | |
c5aa993b JM |
10 | This program is free software; you can redistribute it and/or modify |
11 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 12 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 13 | (at your option) any later version. |
c906108c | 14 | |
c5aa993b JM |
15 | This program is distributed in the hope that it will be useful, |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
c906108c | 19 | |
c5aa993b | 20 | You should have received a copy of the GNU General Public License |
a9762ec7 | 21 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
22 | |
23 | #include "defs.h" | |
c906108c SS |
24 | #include "frame.h" |
25 | #include "inferior.h" | |
26 | #include "symtab.h" | |
27 | #include "value.h" | |
28 | #include "gdbcmd.h" | |
29 | #include "language.h" | |
30 | #include "gdbcore.h" | |
31 | #include "symfile.h" | |
32 | #include "objfiles.h" | |
33 | #include "gdbtypes.h" | |
34 | #include "target.h" | |
28d069e6 | 35 | #include "arch-utils.h" |
4e052eda | 36 | #include "regcache.h" |
70f80edf | 37 | #include "osabi.h" |
d1973055 | 38 | #include "mips-tdep.h" |
fe898f56 | 39 | #include "block.h" |
a4b8ebc8 | 40 | #include "reggroups.h" |
c906108c | 41 | #include "opcode/mips.h" |
c2d11a7d JM |
42 | #include "elf/mips.h" |
43 | #include "elf-bfd.h" | |
2475bac3 | 44 | #include "symcat.h" |
a4b8ebc8 | 45 | #include "sim-regno.h" |
a89aa300 | 46 | #include "dis-asm.h" |
e47ad6c0 | 47 | #include "disasm.h" |
edfae063 AC |
48 | #include "frame-unwind.h" |
49 | #include "frame-base.h" | |
50 | #include "trad-frame.h" | |
7d9b040b | 51 | #include "infcall.h" |
29709017 DJ |
52 | #include "remote.h" |
53 | #include "target-descriptions.h" | |
82ca8957 | 54 | #include "dwarf2/frame.h" |
f8b73d13 | 55 | #include "user-regs.h" |
79a45b7d | 56 | #include "valprint.h" |
175ff332 | 57 | #include "ax.h" |
f69fdf9b | 58 | #include "target-float.h" |
325fac50 | 59 | #include <algorithm> |
c906108c | 60 | |
5bbcb741 | 61 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 62 | |
ab50adb6 MR |
63 | static int mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, |
64 | ULONGEST inst); | |
65 | static int micromips_instruction_has_delay_slot (ULONGEST insn, int mustbe32); | |
66 | static int mips16_instruction_has_delay_slot (unsigned short inst, | |
67 | int mustbe32); | |
68 | ||
69 | static int mips32_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, | |
70 | CORE_ADDR addr); | |
71 | static int micromips_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, | |
72 | CORE_ADDR addr, int mustbe32); | |
73 | static int mips16_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, | |
74 | CORE_ADDR addr, int mustbe32); | |
4cc0665f | 75 | |
1bab7383 YQ |
76 | static void mips_print_float_info (struct gdbarch *, struct ui_file *, |
77 | struct frame_info *, const char *); | |
78 | ||
24e05951 | 79 | /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ |
dd824b04 DJ |
80 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ |
81 | #define ST0_FR (1 << 26) | |
82 | ||
b0069a17 AC |
83 | /* The sizes of floating point registers. */ |
84 | ||
85 | enum | |
86 | { | |
87 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
88 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
89 | }; | |
90 | ||
1a69e1e4 DJ |
91 | enum |
92 | { | |
93 | MIPS32_REGSIZE = 4, | |
94 | MIPS64_REGSIZE = 8 | |
95 | }; | |
0dadbba0 | 96 | |
2e4ebe70 DJ |
97 | static const char *mips_abi_string; |
98 | ||
40478521 | 99 | static const char *const mips_abi_strings[] = { |
2e4ebe70 DJ |
100 | "auto", |
101 | "n32", | |
102 | "o32", | |
28d169de | 103 | "n64", |
2e4ebe70 DJ |
104 | "o64", |
105 | "eabi32", | |
106 | "eabi64", | |
107 | NULL | |
108 | }; | |
109 | ||
44f1c4d7 YQ |
110 | /* Enum describing the different kinds of breakpoints. */ |
111 | ||
112 | enum mips_breakpoint_kind | |
113 | { | |
114 | /* 16-bit MIPS16 mode breakpoint. */ | |
115 | MIPS_BP_KIND_MIPS16 = 2, | |
116 | ||
117 | /* 16-bit microMIPS mode breakpoint. */ | |
118 | MIPS_BP_KIND_MICROMIPS16 = 3, | |
119 | ||
120 | /* 32-bit standard MIPS mode breakpoint. */ | |
121 | MIPS_BP_KIND_MIPS32 = 4, | |
122 | ||
123 | /* 32-bit microMIPS mode breakpoint. */ | |
124 | MIPS_BP_KIND_MICROMIPS32 = 5, | |
125 | }; | |
126 | ||
4cc0665f MR |
127 | /* For backwards compatibility we default to MIPS16. This flag is |
128 | overridden as soon as unambiguous ELF file flags tell us the | |
129 | compressed ISA encoding used. */ | |
130 | static const char mips_compression_mips16[] = "mips16"; | |
131 | static const char mips_compression_micromips[] = "micromips"; | |
132 | static const char *const mips_compression_strings[] = | |
133 | { | |
134 | mips_compression_mips16, | |
135 | mips_compression_micromips, | |
136 | NULL | |
137 | }; | |
138 | ||
139 | static const char *mips_compression_string = mips_compression_mips16; | |
140 | ||
f8b73d13 DJ |
141 | /* The standard register names, and all the valid aliases for them. */ |
142 | struct register_alias | |
143 | { | |
144 | const char *name; | |
145 | int regnum; | |
146 | }; | |
147 | ||
148 | /* Aliases for o32 and most other ABIs. */ | |
149 | const struct register_alias mips_o32_aliases[] = { | |
150 | { "ta0", 12 }, | |
151 | { "ta1", 13 }, | |
152 | { "ta2", 14 }, | |
153 | { "ta3", 15 } | |
154 | }; | |
155 | ||
156 | /* Aliases for n32 and n64. */ | |
157 | const struct register_alias mips_n32_n64_aliases[] = { | |
158 | { "ta0", 8 }, | |
159 | { "ta1", 9 }, | |
160 | { "ta2", 10 }, | |
161 | { "ta3", 11 } | |
162 | }; | |
163 | ||
164 | /* Aliases for ABI-independent registers. */ | |
165 | const struct register_alias mips_register_aliases[] = { | |
166 | /* The architecture manuals specify these ABI-independent names for | |
167 | the GPRs. */ | |
168 | #define R(n) { "r" #n, n } | |
169 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
170 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
171 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
172 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
173 | #undef R | |
174 | ||
175 | /* k0 and k1 are sometimes called these instead (for "kernel | |
176 | temp"). */ | |
177 | { "kt0", 26 }, | |
178 | { "kt1", 27 }, | |
179 | ||
180 | /* This is the traditional GDB name for the CP0 status register. */ | |
181 | { "sr", MIPS_PS_REGNUM }, | |
182 | ||
183 | /* This is the traditional GDB name for the CP0 BadVAddr register. */ | |
184 | { "bad", MIPS_EMBED_BADVADDR_REGNUM }, | |
185 | ||
186 | /* This is the traditional GDB name for the FCSR. */ | |
187 | { "fsr", MIPS_EMBED_FP0_REGNUM + 32 } | |
188 | }; | |
189 | ||
865093a3 AR |
190 | const struct register_alias mips_numeric_register_aliases[] = { |
191 | #define R(n) { #n, n } | |
192 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
193 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
194 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
195 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
196 | #undef R | |
197 | }; | |
198 | ||
c906108c SS |
199 | #ifndef MIPS_DEFAULT_FPU_TYPE |
200 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
201 | #endif | |
202 | static int mips_fpu_type_auto = 1; | |
203 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 204 | |
ccce17b0 | 205 | static unsigned int mips_debug = 0; |
7a292a7a | 206 | |
29709017 DJ |
207 | /* Properties (for struct target_desc) describing the g/G packet |
208 | layout. */ | |
209 | #define PROPERTY_GP32 "internal: transfers-32bit-registers" | |
210 | #define PROPERTY_GP64 "internal: transfers-64bit-registers" | |
211 | ||
4eb0ad19 DJ |
212 | struct target_desc *mips_tdesc_gp32; |
213 | struct target_desc *mips_tdesc_gp64; | |
214 | ||
471b9d15 MR |
215 | /* The current set of options to be passed to the disassembler. */ |
216 | static char *mips_disassembler_options; | |
217 | ||
218 | /* Implicit disassembler options for individual ABIs. These tell | |
219 | libopcodes to use general-purpose register names corresponding | |
220 | to the ABI we have selected, perhaps via a `set mips abi ...' | |
221 | override, rather than ones inferred from the ABI set in the ELF | |
222 | headers of the binary file selected for debugging. */ | |
223 | static const char mips_disassembler_options_o32[] = "gpr-names=32"; | |
224 | static const char mips_disassembler_options_n32[] = "gpr-names=n32"; | |
225 | static const char mips_disassembler_options_n64[] = "gpr-names=64"; | |
226 | ||
56cea623 AC |
227 | const struct mips_regnum * |
228 | mips_regnum (struct gdbarch *gdbarch) | |
229 | { | |
230 | return gdbarch_tdep (gdbarch)->regnum; | |
231 | } | |
232 | ||
233 | static int | |
234 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
235 | { | |
236 | return mips_regnum (gdbarch)->fp0 + 12; | |
237 | } | |
238 | ||
004159a2 MR |
239 | /* Return 1 if REGNUM refers to a floating-point general register, raw |
240 | or cooked. Otherwise return 0. */ | |
241 | ||
242 | static int | |
243 | mips_float_register_p (struct gdbarch *gdbarch, int regnum) | |
244 | { | |
245 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
246 | ||
247 | return (rawnum >= mips_regnum (gdbarch)->fp0 | |
248 | && rawnum < mips_regnum (gdbarch)->fp0 + 32); | |
249 | } | |
250 | ||
74ed0bb4 MD |
251 | #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \ |
252 | == MIPS_ABI_EABI32 \ | |
253 | || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64) | |
c2d11a7d | 254 | |
025bb325 MS |
255 | #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \ |
256 | (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum) | |
c2d11a7d | 257 | |
025bb325 MS |
258 | #define MIPS_LAST_ARG_REGNUM(gdbarch) \ |
259 | (gdbarch_tdep (gdbarch)->mips_last_arg_regnum) | |
c2d11a7d | 260 | |
74ed0bb4 | 261 | #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type) |
c2d11a7d | 262 | |
d1973055 KB |
263 | /* Return the MIPS ABI associated with GDBARCH. */ |
264 | enum mips_abi | |
265 | mips_abi (struct gdbarch *gdbarch) | |
266 | { | |
267 | return gdbarch_tdep (gdbarch)->mips_abi; | |
268 | } | |
269 | ||
4246e332 | 270 | int |
1b13c4f6 | 271 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 | 272 | { |
29709017 DJ |
273 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
274 | ||
275 | /* If we know how big the registers are, use that size. */ | |
276 | if (tdep->register_size_valid_p) | |
277 | return tdep->register_size; | |
278 | ||
279 | /* Fall back to the previous behavior. */ | |
4246e332 AC |
280 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word |
281 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
282 | } | |
283 | ||
b3464d03 PA |
284 | /* Max saved register size. */ |
285 | #define MAX_MIPS_ABI_REGSIZE 8 | |
286 | ||
025bb325 | 287 | /* Return the currently configured (or set) saved register size. */ |
480d3dd2 | 288 | |
e6bc2e8a | 289 | unsigned int |
13326b4e | 290 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 291 | { |
1a69e1e4 DJ |
292 | switch (mips_abi (gdbarch)) |
293 | { | |
294 | case MIPS_ABI_EABI32: | |
295 | case MIPS_ABI_O32: | |
296 | return 4; | |
297 | case MIPS_ABI_N32: | |
298 | case MIPS_ABI_N64: | |
299 | case MIPS_ABI_O64: | |
300 | case MIPS_ABI_EABI64: | |
301 | return 8; | |
302 | case MIPS_ABI_UNKNOWN: | |
303 | case MIPS_ABI_LAST: | |
304 | default: | |
305 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
306 | } | |
d929b26f AC |
307 | } |
308 | ||
4cc0665f MR |
309 | /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here |
310 | are some functions to handle addresses associated with compressed | |
311 | code including but not limited to testing, setting, or clearing | |
312 | bit 0 of such addresses. */ | |
742c84f6 | 313 | |
4cc0665f MR |
314 | /* Return one iff compressed code is the MIPS16 instruction set. */ |
315 | ||
316 | static int | |
317 | is_mips16_isa (struct gdbarch *gdbarch) | |
318 | { | |
319 | return gdbarch_tdep (gdbarch)->mips_isa == ISA_MIPS16; | |
320 | } | |
321 | ||
322 | /* Return one iff compressed code is the microMIPS instruction set. */ | |
323 | ||
324 | static int | |
325 | is_micromips_isa (struct gdbarch *gdbarch) | |
326 | { | |
327 | return gdbarch_tdep (gdbarch)->mips_isa == ISA_MICROMIPS; | |
328 | } | |
329 | ||
330 | /* Return one iff ADDR denotes compressed code. */ | |
331 | ||
332 | static int | |
333 | is_compact_addr (CORE_ADDR addr) | |
742c84f6 MR |
334 | { |
335 | return ((addr) & 1); | |
336 | } | |
337 | ||
4cc0665f MR |
338 | /* Return one iff ADDR denotes standard ISA code. */ |
339 | ||
340 | static int | |
341 | is_mips_addr (CORE_ADDR addr) | |
342 | { | |
343 | return !is_compact_addr (addr); | |
344 | } | |
345 | ||
346 | /* Return one iff ADDR denotes MIPS16 code. */ | |
347 | ||
348 | static int | |
349 | is_mips16_addr (struct gdbarch *gdbarch, CORE_ADDR addr) | |
350 | { | |
351 | return is_compact_addr (addr) && is_mips16_isa (gdbarch); | |
352 | } | |
353 | ||
354 | /* Return one iff ADDR denotes microMIPS code. */ | |
355 | ||
356 | static int | |
357 | is_micromips_addr (struct gdbarch *gdbarch, CORE_ADDR addr) | |
358 | { | |
359 | return is_compact_addr (addr) && is_micromips_isa (gdbarch); | |
360 | } | |
361 | ||
362 | /* Strip the ISA (compression) bit off from ADDR. */ | |
363 | ||
742c84f6 | 364 | static CORE_ADDR |
4cc0665f | 365 | unmake_compact_addr (CORE_ADDR addr) |
742c84f6 MR |
366 | { |
367 | return ((addr) & ~(CORE_ADDR) 1); | |
368 | } | |
369 | ||
4cc0665f MR |
370 | /* Add the ISA (compression) bit to ADDR. */ |
371 | ||
742c84f6 | 372 | static CORE_ADDR |
4cc0665f | 373 | make_compact_addr (CORE_ADDR addr) |
742c84f6 MR |
374 | { |
375 | return ((addr) | (CORE_ADDR) 1); | |
376 | } | |
377 | ||
3e29f34a MR |
378 | /* Extern version of unmake_compact_addr; we use a separate function |
379 | so that unmake_compact_addr can be inlined throughout this file. */ | |
380 | ||
381 | CORE_ADDR | |
382 | mips_unmake_compact_addr (CORE_ADDR addr) | |
383 | { | |
384 | return unmake_compact_addr (addr); | |
385 | } | |
386 | ||
71b8ef93 | 387 | /* Functions for setting and testing a bit in a minimal symbol that |
4cc0665f MR |
388 | marks it as MIPS16 or microMIPS function. The MSB of the minimal |
389 | symbol's "info" field is used for this purpose. | |
5a89d8aa | 390 | |
4cc0665f MR |
391 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is |
392 | "special", i.e. refers to a MIPS16 or microMIPS function, and sets | |
393 | one of the "special" bits in a minimal symbol to mark it accordingly. | |
394 | The test checks an ELF-private flag that is valid for true function | |
1bbce132 MR |
395 | symbols only; for synthetic symbols such as for PLT stubs that have |
396 | no ELF-private part at all the MIPS BFD backend arranges for this | |
397 | information to be carried in the asymbol's udata field instead. | |
5a89d8aa | 398 | |
4cc0665f MR |
399 | msymbol_is_mips16 and msymbol_is_micromips test the "special" bit |
400 | in a minimal symbol. */ | |
5a89d8aa | 401 | |
5a89d8aa | 402 | static void |
6d82d43b AC |
403 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
404 | { | |
4cc0665f | 405 | elf_symbol_type *elfsym = (elf_symbol_type *) sym; |
1bbce132 | 406 | unsigned char st_other; |
4cc0665f | 407 | |
1bbce132 MR |
408 | if ((sym->flags & BSF_SYNTHETIC) == 0) |
409 | st_other = elfsym->internal_elf_sym.st_other; | |
410 | else if ((sym->flags & BSF_FUNCTION) != 0) | |
411 | st_other = sym->udata.i; | |
412 | else | |
4cc0665f MR |
413 | return; |
414 | ||
1bbce132 | 415 | if (ELF_ST_IS_MICROMIPS (st_other)) |
3e29f34a | 416 | { |
f161c171 | 417 | MSYMBOL_TARGET_FLAG_MICROMIPS (msym) = 1; |
3e29f34a MR |
418 | SET_MSYMBOL_VALUE_ADDRESS (msym, MSYMBOL_VALUE_RAW_ADDRESS (msym) | 1); |
419 | } | |
1bbce132 | 420 | else if (ELF_ST_IS_MIPS16 (st_other)) |
3e29f34a | 421 | { |
f161c171 | 422 | MSYMBOL_TARGET_FLAG_MIPS16 (msym) = 1; |
3e29f34a MR |
423 | SET_MSYMBOL_VALUE_ADDRESS (msym, MSYMBOL_VALUE_RAW_ADDRESS (msym) | 1); |
424 | } | |
4cc0665f MR |
425 | } |
426 | ||
427 | /* Return one iff MSYM refers to standard ISA code. */ | |
428 | ||
429 | static int | |
430 | msymbol_is_mips (struct minimal_symbol *msym) | |
431 | { | |
f161c171 MR |
432 | return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym) |
433 | | MSYMBOL_TARGET_FLAG_MICROMIPS (msym)); | |
5a89d8aa MS |
434 | } |
435 | ||
4cc0665f MR |
436 | /* Return one iff MSYM refers to MIPS16 code. */ |
437 | ||
71b8ef93 | 438 | static int |
4cc0665f | 439 | msymbol_is_mips16 (struct minimal_symbol *msym) |
71b8ef93 | 440 | { |
f161c171 | 441 | return MSYMBOL_TARGET_FLAG_MIPS16 (msym); |
71b8ef93 MS |
442 | } |
443 | ||
4cc0665f MR |
444 | /* Return one iff MSYM refers to microMIPS code. */ |
445 | ||
446 | static int | |
447 | msymbol_is_micromips (struct minimal_symbol *msym) | |
448 | { | |
f161c171 | 449 | return MSYMBOL_TARGET_FLAG_MICROMIPS (msym); |
4cc0665f MR |
450 | } |
451 | ||
3e29f34a MR |
452 | /* Set the ISA bit in the main symbol too, complementing the corresponding |
453 | minimal symbol setting and reflecting the run-time value of the symbol. | |
454 | The need for comes from the ISA bit having been cleared as code in | |
455 | `_bfd_mips_elf_symbol_processing' separated it into the ELF symbol's | |
456 | `st_other' STO_MIPS16 or STO_MICROMIPS annotation, making the values | |
457 | of symbols referring to compressed code different in GDB to the values | |
458 | used by actual code. That in turn makes them evaluate incorrectly in | |
459 | expressions, producing results different to what the same expressions | |
460 | yield when compiled into the program being debugged. */ | |
461 | ||
462 | static void | |
463 | mips_make_symbol_special (struct symbol *sym, struct objfile *objfile) | |
464 | { | |
465 | if (SYMBOL_CLASS (sym) == LOC_BLOCK) | |
466 | { | |
467 | /* We are in symbol reading so it is OK to cast away constness. */ | |
468 | struct block *block = (struct block *) SYMBOL_BLOCK_VALUE (sym); | |
469 | CORE_ADDR compact_block_start; | |
470 | struct bound_minimal_symbol msym; | |
471 | ||
472 | compact_block_start = BLOCK_START (block) | 1; | |
473 | msym = lookup_minimal_symbol_by_pc (compact_block_start); | |
474 | if (msym.minsym && !msymbol_is_mips (msym.minsym)) | |
475 | { | |
476 | BLOCK_START (block) = compact_block_start; | |
477 | } | |
478 | } | |
479 | } | |
480 | ||
88658117 AC |
481 | /* XFER a value from the big/little/left end of the register. |
482 | Depending on the size of the value it might occupy the entire | |
483 | register or just part of it. Make an allowance for this, aligning | |
484 | things accordingly. */ | |
485 | ||
486 | static void | |
ba32f989 DJ |
487 | mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache, |
488 | int reg_num, int length, | |
870cd05e MK |
489 | enum bfd_endian endian, gdb_byte *in, |
490 | const gdb_byte *out, int buf_offset) | |
88658117 | 491 | { |
88658117 | 492 | int reg_offset = 0; |
72a155b4 UW |
493 | |
494 | gdb_assert (reg_num >= gdbarch_num_regs (gdbarch)); | |
cb1d2653 AC |
495 | /* Need to transfer the left or right part of the register, based on |
496 | the targets byte order. */ | |
88658117 AC |
497 | switch (endian) |
498 | { | |
499 | case BFD_ENDIAN_BIG: | |
72a155b4 | 500 | reg_offset = register_size (gdbarch, reg_num) - length; |
88658117 AC |
501 | break; |
502 | case BFD_ENDIAN_LITTLE: | |
503 | reg_offset = 0; | |
504 | break; | |
6d82d43b | 505 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
506 | reg_offset = 0; |
507 | break; | |
508 | default: | |
e2e0b3e5 | 509 | internal_error (__FILE__, __LINE__, _("bad switch")); |
88658117 AC |
510 | } |
511 | if (mips_debug) | |
cb1d2653 AC |
512 | fprintf_unfiltered (gdb_stderr, |
513 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
514 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
515 | if (mips_debug && out != NULL) |
516 | { | |
517 | int i; | |
cb1d2653 | 518 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 519 | for (i = 0; i < length; i++) |
cb1d2653 | 520 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
521 | } |
522 | if (in != NULL) | |
73bb0000 | 523 | regcache->cooked_read_part (reg_num, reg_offset, length, in + buf_offset); |
88658117 | 524 | if (out != NULL) |
e4c4a59b | 525 | regcache->cooked_write_part (reg_num, reg_offset, length, out + buf_offset); |
88658117 AC |
526 | if (mips_debug && in != NULL) |
527 | { | |
528 | int i; | |
cb1d2653 | 529 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 530 | for (i = 0; i < length; i++) |
cb1d2653 | 531 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
532 | } |
533 | if (mips_debug) | |
534 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
535 | } | |
536 | ||
dd824b04 DJ |
537 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
538 | compatiblity mode. A return value of 1 means that we have | |
539 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
540 | ||
541 | static int | |
9c9acae0 | 542 | mips2_fp_compat (struct frame_info *frame) |
dd824b04 | 543 | { |
72a155b4 | 544 | struct gdbarch *gdbarch = get_frame_arch (frame); |
dd824b04 DJ |
545 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not |
546 | meaningful. */ | |
72a155b4 | 547 | if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4) |
dd824b04 DJ |
548 | return 0; |
549 | ||
550 | #if 0 | |
551 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
552 | in all the places we deal with FP registers. PR gdb/413. */ | |
553 | /* Otherwise check the FR bit in the status register - it controls | |
554 | the FP compatiblity mode. If it is clear we are in compatibility | |
555 | mode. */ | |
9c9acae0 | 556 | if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0) |
dd824b04 DJ |
557 | return 1; |
558 | #endif | |
361d1df0 | 559 | |
dd824b04 DJ |
560 | return 0; |
561 | } | |
562 | ||
7a292a7a | 563 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 564 | |
74ed0bb4 | 565 | static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR); |
c906108c | 566 | |
025bb325 | 567 | /* The list of available "set mips " and "show mips " commands. */ |
acdb74a0 AC |
568 | |
569 | static struct cmd_list_element *setmipscmdlist = NULL; | |
570 | static struct cmd_list_element *showmipscmdlist = NULL; | |
571 | ||
5e2e9765 KB |
572 | /* Integer registers 0 thru 31 are handled explicitly by |
573 | mips_register_name(). Processor specific registers 32 and above | |
8a9fc081 | 574 | are listed in the following tables. */ |
691c0433 | 575 | |
6d82d43b AC |
576 | enum |
577 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
578 | |
579 | /* Generic MIPS. */ | |
580 | ||
27087b7f | 581 | static const char * const mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { |
6d82d43b AC |
582 | "sr", "lo", "hi", "bad", "cause", "pc", |
583 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
584 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
585 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
586 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
1faeff08 | 587 | "fsr", "fir", |
691c0433 AC |
588 | }; |
589 | ||
691c0433 AC |
590 | /* Names of tx39 registers. */ |
591 | ||
27087b7f | 592 | static const char * const mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { |
6d82d43b AC |
593 | "sr", "lo", "hi", "bad", "cause", "pc", |
594 | "", "", "", "", "", "", "", "", | |
595 | "", "", "", "", "", "", "", "", | |
596 | "", "", "", "", "", "", "", "", | |
597 | "", "", "", "", "", "", "", "", | |
598 | "", "", "", "", | |
599 | "", "", "", "", "", "", "", "", | |
1faeff08 | 600 | "", "", "config", "cache", "debug", "depc", "epc", |
691c0433 AC |
601 | }; |
602 | ||
44099a67 | 603 | /* Names of registers with Linux kernels. */ |
27087b7f | 604 | static const char * const mips_linux_reg_names[NUM_MIPS_PROCESSOR_REGS] = { |
1faeff08 MR |
605 | "sr", "lo", "hi", "bad", "cause", "pc", |
606 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
607 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
608 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
609 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
610 | "fsr", "fir" | |
611 | }; | |
612 | ||
cce74817 | 613 | |
5e2e9765 | 614 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 615 | static const char * |
d93859e2 | 616 | mips_register_name (struct gdbarch *gdbarch, int regno) |
cce74817 | 617 | { |
d93859e2 | 618 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
5e2e9765 | 619 | /* GPR names for all ABIs other than n32/n64. */ |
a121b7c1 | 620 | static const char *mips_gpr_names[] = { |
6d82d43b AC |
621 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
622 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
623 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
624 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
625 | }; |
626 | ||
627 | /* GPR names for n32 and n64 ABIs. */ | |
a121b7c1 | 628 | static const char *mips_n32_n64_gpr_names[] = { |
6d82d43b AC |
629 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
630 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
631 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
632 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
633 | }; |
634 | ||
d93859e2 | 635 | enum mips_abi abi = mips_abi (gdbarch); |
5e2e9765 | 636 | |
f57d151a | 637 | /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, |
6229fbea HZ |
638 | but then don't make the raw register names visible. This (upper) |
639 | range of user visible register numbers are the pseudo-registers. | |
640 | ||
641 | This approach was adopted accommodate the following scenario: | |
642 | It is possible to debug a 64-bit device using a 32-bit | |
643 | programming model. In such instances, the raw registers are | |
644 | configured to be 64-bits wide, while the pseudo registers are | |
645 | configured to be 32-bits wide. The registers that the user | |
646 | sees - the pseudo registers - match the users expectations | |
647 | given the programming model being used. */ | |
d93859e2 UW |
648 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
649 | if (regno < gdbarch_num_regs (gdbarch)) | |
a4b8ebc8 AC |
650 | return ""; |
651 | ||
5e2e9765 KB |
652 | /* The MIPS integer registers are always mapped from 0 to 31. The |
653 | names of the registers (which reflects the conventions regarding | |
654 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 655 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
656 | { |
657 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 658 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 659 | else |
a4b8ebc8 | 660 | return mips_gpr_names[rawnum]; |
5e2e9765 | 661 | } |
d93859e2 UW |
662 | else if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
663 | return tdesc_register_name (gdbarch, rawnum); | |
664 | else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch)) | |
691c0433 AC |
665 | { |
666 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
1faeff08 MR |
667 | if (tdep->mips_processor_reg_names[rawnum - 32]) |
668 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
669 | return ""; | |
691c0433 | 670 | } |
5e2e9765 KB |
671 | else |
672 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 673 | _("mips_register_name: bad register number %d"), rawnum); |
cce74817 | 674 | } |
5e2e9765 | 675 | |
a4b8ebc8 | 676 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 677 | |
a4b8ebc8 AC |
678 | static int |
679 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
680 | struct reggroup *reggroup) | |
681 | { | |
682 | int vector_p; | |
683 | int float_p; | |
684 | int raw_p; | |
72a155b4 UW |
685 | int rawnum = regnum % gdbarch_num_regs (gdbarch); |
686 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
a4b8ebc8 AC |
687 | if (reggroup == all_reggroup) |
688 | return pseudo; | |
bd63c870 | 689 | vector_p = register_type (gdbarch, regnum)->is_vector (); |
78134374 | 690 | float_p = register_type (gdbarch, regnum)->code () == TYPE_CODE_FLT; |
a4b8ebc8 AC |
691 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs |
692 | (gdbarch), as not all architectures are multi-arch. */ | |
72a155b4 UW |
693 | raw_p = rawnum < gdbarch_num_regs (gdbarch); |
694 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
695 | || gdbarch_register_name (gdbarch, regnum)[0] == '\0') | |
a4b8ebc8 AC |
696 | return 0; |
697 | if (reggroup == float_reggroup) | |
698 | return float_p && pseudo; | |
699 | if (reggroup == vector_reggroup) | |
700 | return vector_p && pseudo; | |
701 | if (reggroup == general_reggroup) | |
702 | return (!vector_p && !float_p) && pseudo; | |
703 | /* Save the pseudo registers. Need to make certain that any code | |
704 | extracting register values from a saved register cache also uses | |
705 | pseudo registers. */ | |
706 | if (reggroup == save_reggroup) | |
707 | return raw_p && pseudo; | |
708 | /* Restore the same pseudo register. */ | |
709 | if (reggroup == restore_reggroup) | |
710 | return raw_p && pseudo; | |
6d82d43b | 711 | return 0; |
a4b8ebc8 AC |
712 | } |
713 | ||
f8b73d13 DJ |
714 | /* Return the groups that a MIPS register can be categorised into. |
715 | This version is only used if we have a target description which | |
716 | describes real registers (and their groups). */ | |
717 | ||
718 | static int | |
719 | mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
720 | struct reggroup *reggroup) | |
721 | { | |
722 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
723 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
724 | int ret; | |
725 | ||
726 | /* Only save, restore, and display the pseudo registers. Need to | |
727 | make certain that any code extracting register values from a | |
728 | saved register cache also uses pseudo registers. | |
729 | ||
730 | Note: saving and restoring the pseudo registers is slightly | |
731 | strange; if we have 64 bits, we should save and restore all | |
732 | 64 bits. But this is hard and has little benefit. */ | |
733 | if (!pseudo) | |
734 | return 0; | |
735 | ||
736 | ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup); | |
737 | if (ret != -1) | |
738 | return ret; | |
739 | ||
740 | return mips_register_reggroup_p (gdbarch, regnum, reggroup); | |
741 | } | |
742 | ||
a4b8ebc8 | 743 | /* Map the symbol table registers which live in the range [1 * |
f57d151a | 744 | gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw |
47ebcfbe | 745 | registers. Take care of alignment and size problems. */ |
c5aa993b | 746 | |
05d1431c | 747 | static enum register_status |
849d0ba8 | 748 | mips_pseudo_register_read (struct gdbarch *gdbarch, readable_regcache *regcache, |
47a35522 | 749 | int cookednum, gdb_byte *buf) |
a4b8ebc8 | 750 | { |
72a155b4 UW |
751 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
752 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
753 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 754 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
03f50fc8 | 755 | return regcache->raw_read (rawnum, buf); |
6d82d43b AC |
756 | else if (register_size (gdbarch, rawnum) > |
757 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 758 | { |
8bdf35dc | 759 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
03f50fc8 | 760 | return regcache->raw_read_part (rawnum, 0, 4, buf); |
47ebcfbe | 761 | else |
8bdf35dc KB |
762 | { |
763 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
764 | LONGEST regval; | |
05d1431c PA |
765 | enum register_status status; |
766 | ||
03f50fc8 | 767 | status = regcache->raw_read (rawnum, ®val); |
05d1431c PA |
768 | if (status == REG_VALID) |
769 | store_signed_integer (buf, 4, byte_order, regval); | |
770 | return status; | |
8bdf35dc | 771 | } |
47ebcfbe AC |
772 | } |
773 | else | |
e2e0b3e5 | 774 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 AC |
775 | } |
776 | ||
777 | static void | |
6d82d43b AC |
778 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
779 | struct regcache *regcache, int cookednum, | |
47a35522 | 780 | const gdb_byte *buf) |
a4b8ebc8 | 781 | { |
72a155b4 UW |
782 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
783 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
784 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 785 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
10eaee5f | 786 | regcache->raw_write (rawnum, buf); |
6d82d43b AC |
787 | else if (register_size (gdbarch, rawnum) > |
788 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 789 | { |
8bdf35dc | 790 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
4f0420fd | 791 | regcache->raw_write_part (rawnum, 0, 4, buf); |
47ebcfbe | 792 | else |
8bdf35dc KB |
793 | { |
794 | /* Sign extend the shortened version of the register prior | |
795 | to placing it in the raw register. This is required for | |
796 | some mips64 parts in order to avoid unpredictable behavior. */ | |
797 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
798 | LONGEST regval = extract_signed_integer (buf, 4, byte_order); | |
799 | regcache_raw_write_signed (regcache, rawnum, regval); | |
800 | } | |
47ebcfbe AC |
801 | } |
802 | else | |
e2e0b3e5 | 803 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 | 804 | } |
c5aa993b | 805 | |
175ff332 HZ |
806 | static int |
807 | mips_ax_pseudo_register_collect (struct gdbarch *gdbarch, | |
808 | struct agent_expr *ax, int reg) | |
809 | { | |
810 | int rawnum = reg % gdbarch_num_regs (gdbarch); | |
811 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) | |
812 | && reg < 2 * gdbarch_num_regs (gdbarch)); | |
813 | ||
814 | ax_reg_mask (ax, rawnum); | |
815 | ||
816 | return 0; | |
817 | } | |
818 | ||
819 | static int | |
820 | mips_ax_pseudo_register_push_stack (struct gdbarch *gdbarch, | |
821 | struct agent_expr *ax, int reg) | |
822 | { | |
823 | int rawnum = reg % gdbarch_num_regs (gdbarch); | |
824 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) | |
825 | && reg < 2 * gdbarch_num_regs (gdbarch)); | |
826 | if (register_size (gdbarch, rawnum) >= register_size (gdbarch, reg)) | |
827 | { | |
828 | ax_reg (ax, rawnum); | |
829 | ||
830 | if (register_size (gdbarch, rawnum) > register_size (gdbarch, reg)) | |
dda83cd7 | 831 | { |
175ff332 HZ |
832 | if (!gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p |
833 | || gdbarch_byte_order (gdbarch) != BFD_ENDIAN_BIG) | |
834 | { | |
835 | ax_const_l (ax, 32); | |
836 | ax_simple (ax, aop_lsh); | |
837 | } | |
838 | ax_const_l (ax, 32); | |
839 | ax_simple (ax, aop_rsh_signed); | |
840 | } | |
841 | } | |
842 | else | |
843 | internal_error (__FILE__, __LINE__, _("bad register size")); | |
844 | ||
845 | return 0; | |
846 | } | |
847 | ||
4cc0665f | 848 | /* Table to translate 3-bit register field to actual register number. */ |
d467df4e | 849 | static const signed char mips_reg3_to_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
850 | |
851 | /* Heuristic_proc_start may hunt through the text section for a long | |
852 | time across a 2400 baud serial line. Allows the user to limit this | |
853 | search. */ | |
854 | ||
44096aee | 855 | static int heuristic_fence_post = 0; |
c906108c | 856 | |
46cd78fb | 857 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
858 | register N. NOTE: This defines the pseudo register type so need to |
859 | rebuild the architecture vector. */ | |
43e526b9 | 860 | |
491144b5 | 861 | static bool mips64_transfers_32bit_regs_p = false; |
43e526b9 | 862 | |
719ec221 | 863 | static void |
eb4c3f4a | 864 | set_mips64_transfers_32bit_regs (const char *args, int from_tty, |
719ec221 | 865 | struct cmd_list_element *c) |
43e526b9 | 866 | { |
719ec221 AC |
867 | struct gdbarch_info info; |
868 | gdbarch_info_init (&info); | |
869 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
870 | instead of relying on globals. Doing that would let generic code | |
871 | handle the search for this specific architecture. */ | |
872 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 873 | { |
719ec221 | 874 | mips64_transfers_32bit_regs_p = 0; |
8a3fe4f8 | 875 | error (_("32-bit compatibility mode not supported")); |
a4b8ebc8 | 876 | } |
a4b8ebc8 AC |
877 | } |
878 | ||
47ebcfbe | 879 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 880 | |
ee51a8c7 KB |
881 | /* This predicate tests for the case of an 8 byte floating point |
882 | value that is being transferred to or from a pair of floating point | |
883 | registers each of which are (or are considered to be) only 4 bytes | |
884 | wide. */ | |
ff2e87ac | 885 | static int |
ee51a8c7 KB |
886 | mips_convert_register_float_case_p (struct gdbarch *gdbarch, int regnum, |
887 | struct type *type) | |
ff2e87ac | 888 | { |
0abe36f5 MD |
889 | return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
890 | && register_size (gdbarch, regnum) == 4 | |
004159a2 | 891 | && mips_float_register_p (gdbarch, regnum) |
78134374 | 892 | && type->code () == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
893 | } |
894 | ||
ee51a8c7 KB |
895 | /* This predicate tests for the case of a value of less than 8 |
896 | bytes in width that is being transfered to or from an 8 byte | |
897 | general purpose register. */ | |
898 | static int | |
899 | mips_convert_register_gpreg_case_p (struct gdbarch *gdbarch, int regnum, | |
900 | struct type *type) | |
901 | { | |
902 | int num_regs = gdbarch_num_regs (gdbarch); | |
903 | ||
904 | return (register_size (gdbarch, regnum) == 8 | |
dda83cd7 SM |
905 | && regnum % num_regs > 0 && regnum % num_regs < 32 |
906 | && TYPE_LENGTH (type) < 8); | |
ee51a8c7 KB |
907 | } |
908 | ||
909 | static int | |
025bb325 MS |
910 | mips_convert_register_p (struct gdbarch *gdbarch, |
911 | int regnum, struct type *type) | |
ee51a8c7 | 912 | { |
eaa05d59 MR |
913 | return (mips_convert_register_float_case_p (gdbarch, regnum, type) |
914 | || mips_convert_register_gpreg_case_p (gdbarch, regnum, type)); | |
ee51a8c7 KB |
915 | } |
916 | ||
8dccd430 | 917 | static int |
ff2e87ac | 918 | mips_register_to_value (struct frame_info *frame, int regnum, |
8dccd430 PA |
919 | struct type *type, gdb_byte *to, |
920 | int *optimizedp, int *unavailablep) | |
102182a9 | 921 | { |
ee51a8c7 KB |
922 | struct gdbarch *gdbarch = get_frame_arch (frame); |
923 | ||
924 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
925 | { | |
926 | get_frame_register (frame, regnum + 0, to + 4); | |
927 | get_frame_register (frame, regnum + 1, to + 0); | |
8dccd430 | 928 | |
bdec2917 | 929 | if (!get_frame_register_bytes (frame, regnum + 0, 0, {to + 4, 4}, |
8dccd430 PA |
930 | optimizedp, unavailablep)) |
931 | return 0; | |
932 | ||
bdec2917 | 933 | if (!get_frame_register_bytes (frame, regnum + 1, 0, {to + 0, 4}, |
8dccd430 PA |
934 | optimizedp, unavailablep)) |
935 | return 0; | |
936 | *optimizedp = *unavailablep = 0; | |
937 | return 1; | |
ee51a8c7 KB |
938 | } |
939 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
940 | { | |
bdec2917 | 941 | size_t len = TYPE_LENGTH (type); |
8dccd430 PA |
942 | CORE_ADDR offset; |
943 | ||
944 | offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 8 - len : 0; | |
bdec2917 | 945 | if (!get_frame_register_bytes (frame, regnum, offset, {to, len}, |
8dccd430 PA |
946 | optimizedp, unavailablep)) |
947 | return 0; | |
948 | ||
949 | *optimizedp = *unavailablep = 0; | |
950 | return 1; | |
ee51a8c7 KB |
951 | } |
952 | else | |
953 | { | |
954 | internal_error (__FILE__, __LINE__, | |
dda83cd7 | 955 | _("mips_register_to_value: unrecognized case")); |
ee51a8c7 | 956 | } |
102182a9 MS |
957 | } |
958 | ||
42c466d7 | 959 | static void |
ff2e87ac | 960 | mips_value_to_register (struct frame_info *frame, int regnum, |
47a35522 | 961 | struct type *type, const gdb_byte *from) |
102182a9 | 962 | { |
ee51a8c7 KB |
963 | struct gdbarch *gdbarch = get_frame_arch (frame); |
964 | ||
965 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
966 | { | |
967 | put_frame_register (frame, regnum + 0, from + 4); | |
968 | put_frame_register (frame, regnum + 1, from + 0); | |
969 | } | |
970 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
971 | { | |
972 | gdb_byte fill[8]; | |
bdec2917 | 973 | size_t len = TYPE_LENGTH (type); |
ee51a8c7 KB |
974 | |
975 | /* Sign extend values, irrespective of type, that are stored to | |
dda83cd7 | 976 | a 64-bit general purpose register. (32-bit unsigned values |
ee51a8c7 KB |
977 | are stored as signed quantities within a 64-bit register. |
978 | When performing an operation, in compiled code, that combines | |
979 | a 32-bit unsigned value with a signed 64-bit value, a type | |
980 | conversion is first performed that zeroes out the high 32 bits.) */ | |
981 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
982 | { | |
983 | if (from[0] & 0x80) | |
984 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, -1); | |
985 | else | |
986 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, 0); | |
bdec2917 LM |
987 | put_frame_register_bytes (frame, regnum, 0, {fill, 8 - len}); |
988 | put_frame_register_bytes (frame, regnum, 8 - len, {from, len}); | |
ee51a8c7 KB |
989 | } |
990 | else | |
991 | { | |
992 | if (from[len-1] & 0x80) | |
993 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, -1); | |
994 | else | |
995 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, 0); | |
bdec2917 LM |
996 | put_frame_register_bytes (frame, regnum, 0, {from, len}); |
997 | put_frame_register_bytes (frame, regnum, len, {fill, 8 - len}); | |
ee51a8c7 KB |
998 | } |
999 | } | |
1000 | else | |
1001 | { | |
1002 | internal_error (__FILE__, __LINE__, | |
dda83cd7 | 1003 | _("mips_value_to_register: unrecognized case")); |
ee51a8c7 | 1004 | } |
102182a9 MS |
1005 | } |
1006 | ||
a4b8ebc8 AC |
1007 | /* Return the GDB type object for the "standard" data type of data in |
1008 | register REG. */ | |
78fde5f8 KB |
1009 | |
1010 | static struct type * | |
a4b8ebc8 AC |
1011 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
1012 | { | |
72a155b4 | 1013 | gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch)); |
004159a2 | 1014 | if (mips_float_register_p (gdbarch, regnum)) |
a6425924 | 1015 | { |
5ef80fb0 | 1016 | /* The floating-point registers raw, or cooked, always match |
dda83cd7 | 1017 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
8da61cc4 | 1018 | if (mips_isa_regsize (gdbarch) == 4) |
27067745 | 1019 | return builtin_type (gdbarch)->builtin_float; |
8da61cc4 | 1020 | else |
27067745 | 1021 | return builtin_type (gdbarch)->builtin_double; |
a6425924 | 1022 | } |
72a155b4 | 1023 | else if (regnum < gdbarch_num_regs (gdbarch)) |
d5ac5a39 AC |
1024 | { |
1025 | /* The raw or ISA registers. These are all sized according to | |
1026 | the ISA regsize. */ | |
1027 | if (mips_isa_regsize (gdbarch) == 4) | |
df4df182 | 1028 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 | 1029 | else |
df4df182 | 1030 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 1031 | } |
78fde5f8 | 1032 | else |
d5ac5a39 | 1033 | { |
1faeff08 MR |
1034 | int rawnum = regnum - gdbarch_num_regs (gdbarch); |
1035 | ||
d5ac5a39 AC |
1036 | /* The cooked or ABI registers. These are sized according to |
1037 | the ABI (with a few complications). */ | |
1faeff08 MR |
1038 | if (rawnum == mips_regnum (gdbarch)->fp_control_status |
1039 | || rawnum == mips_regnum (gdbarch)->fp_implementation_revision) | |
1040 | return builtin_type (gdbarch)->builtin_int32; | |
de4bfa86 | 1041 | else if (gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX |
1faeff08 MR |
1042 | && rawnum >= MIPS_FIRST_EMBED_REGNUM |
1043 | && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
d5ac5a39 AC |
1044 | /* The pseudo/cooked view of the embedded registers is always |
1045 | 32-bit. The raw view is handled below. */ | |
df4df182 | 1046 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
1047 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
1048 | /* The target, while possibly using a 64-bit register buffer, | |
1049 | is only transfering 32-bits of each integer register. | |
1050 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
df4df182 | 1051 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
1052 | else if (mips_abi_regsize (gdbarch) == 4) |
1053 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
1054 | 32- or 64-bit). */ | |
df4df182 | 1055 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
1056 | else |
1057 | /* 64-bit ABI. */ | |
df4df182 | 1058 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 1059 | } |
78fde5f8 KB |
1060 | } |
1061 | ||
f8b73d13 DJ |
1062 | /* Return the GDB type for the pseudo register REGNUM, which is the |
1063 | ABI-level view. This function is only called if there is a target | |
1064 | description which includes registers, so we know precisely the | |
1065 | types of hardware registers. */ | |
1066 | ||
1067 | static struct type * | |
1068 | mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
1069 | { | |
1070 | const int num_regs = gdbarch_num_regs (gdbarch); | |
f8b73d13 DJ |
1071 | int rawnum = regnum % num_regs; |
1072 | struct type *rawtype; | |
1073 | ||
1074 | gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); | |
1075 | ||
1076 | /* Absent registers are still absent. */ | |
1077 | rawtype = gdbarch_register_type (gdbarch, rawnum); | |
1078 | if (TYPE_LENGTH (rawtype) == 0) | |
1079 | return rawtype; | |
1080 | ||
a6912260 MR |
1081 | /* Present the floating point registers however the hardware did; |
1082 | do not try to convert between FPU layouts. */ | |
de13fcf2 | 1083 | if (mips_float_register_p (gdbarch, rawnum)) |
f8b73d13 DJ |
1084 | return rawtype; |
1085 | ||
78b86327 MR |
1086 | /* Floating-point control registers are always 32-bit even though for |
1087 | backwards compatibility reasons 64-bit targets will transfer them | |
1088 | as 64-bit quantities even if using XML descriptions. */ | |
1089 | if (rawnum == mips_regnum (gdbarch)->fp_control_status | |
1090 | || rawnum == mips_regnum (gdbarch)->fp_implementation_revision) | |
1091 | return builtin_type (gdbarch)->builtin_int32; | |
1092 | ||
f8b73d13 DJ |
1093 | /* Use pointer types for registers if we can. For n32 we can not, |
1094 | since we do not have a 64-bit pointer type. */ | |
0dfff4cb UW |
1095 | if (mips_abi_regsize (gdbarch) |
1096 | == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr)) | |
f8b73d13 | 1097 | { |
1faeff08 MR |
1098 | if (rawnum == MIPS_SP_REGNUM |
1099 | || rawnum == mips_regnum (gdbarch)->badvaddr) | |
0dfff4cb | 1100 | return builtin_type (gdbarch)->builtin_data_ptr; |
1faeff08 | 1101 | else if (rawnum == mips_regnum (gdbarch)->pc) |
0dfff4cb | 1102 | return builtin_type (gdbarch)->builtin_func_ptr; |
f8b73d13 DJ |
1103 | } |
1104 | ||
1105 | if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8 | |
1faeff08 MR |
1106 | && ((rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_PS_REGNUM) |
1107 | || rawnum == mips_regnum (gdbarch)->lo | |
1108 | || rawnum == mips_regnum (gdbarch)->hi | |
1109 | || rawnum == mips_regnum (gdbarch)->badvaddr | |
1110 | || rawnum == mips_regnum (gdbarch)->cause | |
1111 | || rawnum == mips_regnum (gdbarch)->pc | |
1112 | || (mips_regnum (gdbarch)->dspacc != -1 | |
1113 | && rawnum >= mips_regnum (gdbarch)->dspacc | |
1114 | && rawnum < mips_regnum (gdbarch)->dspacc + 6))) | |
df4df182 | 1115 | return builtin_type (gdbarch)->builtin_int32; |
f8b73d13 | 1116 | |
a6912260 MR |
1117 | /* The pseudo/cooked view of embedded registers is always |
1118 | 32-bit, even if the target transfers 64-bit values for them. | |
1119 | New targets relying on XML descriptions should only transfer | |
1120 | the necessary 32 bits, but older versions of GDB expected 64, | |
1121 | so allow the target to provide 64 bits without interfering | |
1122 | with the displayed type. */ | |
de4bfa86 | 1123 | if (gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX |
78b86327 | 1124 | && rawnum >= MIPS_FIRST_EMBED_REGNUM |
1faeff08 | 1125 | && rawnum <= MIPS_LAST_EMBED_REGNUM) |
a6912260 | 1126 | return builtin_type (gdbarch)->builtin_int32; |
1faeff08 | 1127 | |
f8b73d13 DJ |
1128 | /* For all other registers, pass through the hardware type. */ |
1129 | return rawtype; | |
1130 | } | |
bcb0cc15 | 1131 | |
025bb325 | 1132 | /* Should the upper word of 64-bit addresses be zeroed? */ |
ea33cd92 | 1133 | static enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
1134 | |
1135 | static int | |
480d3dd2 | 1136 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
1137 | { |
1138 | switch (mask_address_var) | |
1139 | { | |
7f19b9a2 | 1140 | case AUTO_BOOLEAN_TRUE: |
4014092b | 1141 | return 1; |
7f19b9a2 | 1142 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
1143 | return 0; |
1144 | break; | |
7f19b9a2 | 1145 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 1146 | return tdep->default_mask_address_p; |
4014092b | 1147 | default: |
025bb325 MS |
1148 | internal_error (__FILE__, __LINE__, |
1149 | _("mips_mask_address_p: bad switch")); | |
4014092b | 1150 | return -1; |
361d1df0 | 1151 | } |
4014092b AC |
1152 | } |
1153 | ||
1154 | static void | |
08546159 AC |
1155 | show_mask_address (struct ui_file *file, int from_tty, |
1156 | struct cmd_list_element *c, const char *value) | |
4014092b | 1157 | { |
f5656ead | 1158 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ()); |
08546159 AC |
1159 | |
1160 | deprecated_show_value_hack (file, from_tty, c, value); | |
4014092b AC |
1161 | switch (mask_address_var) |
1162 | { | |
7f19b9a2 | 1163 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
1164 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
1165 | break; | |
7f19b9a2 | 1166 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
1167 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
1168 | break; | |
7f19b9a2 | 1169 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
1170 | printf_filtered |
1171 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
1172 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
1173 | break; |
1174 | default: | |
e2e0b3e5 | 1175 | internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); |
4014092b | 1176 | break; |
361d1df0 | 1177 | } |
4014092b | 1178 | } |
c906108c | 1179 | |
4cc0665f MR |
1180 | /* Tell if the program counter value in MEMADDR is in a standard ISA |
1181 | function. */ | |
1182 | ||
1183 | int | |
1184 | mips_pc_is_mips (CORE_ADDR memaddr) | |
1185 | { | |
7cbd4a93 | 1186 | struct bound_minimal_symbol sym; |
4cc0665f MR |
1187 | |
1188 | /* Flags indicating that this is a MIPS16 or microMIPS function is | |
1189 | stored by elfread.c in the high bit of the info field. Use this | |
1190 | to decide if the function is standard MIPS. Otherwise if bit 0 | |
1191 | of the address is clear, then this is a standard MIPS function. */ | |
3e29f34a | 1192 | sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); |
7cbd4a93 TT |
1193 | if (sym.minsym) |
1194 | return msymbol_is_mips (sym.minsym); | |
4cc0665f MR |
1195 | else |
1196 | return is_mips_addr (memaddr); | |
1197 | } | |
1198 | ||
c906108c SS |
1199 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
1200 | ||
0fe7e7c8 | 1201 | int |
4cc0665f | 1202 | mips_pc_is_mips16 (struct gdbarch *gdbarch, CORE_ADDR memaddr) |
c906108c | 1203 | { |
7cbd4a93 | 1204 | struct bound_minimal_symbol sym; |
c906108c | 1205 | |
91912e4d MR |
1206 | /* A flag indicating that this is a MIPS16 function is stored by |
1207 | elfread.c in the high bit of the info field. Use this to decide | |
4cc0665f MR |
1208 | if the function is MIPS16. Otherwise if bit 0 of the address is |
1209 | set, then ELF file flags will tell if this is a MIPS16 function. */ | |
3e29f34a | 1210 | sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); |
7cbd4a93 TT |
1211 | if (sym.minsym) |
1212 | return msymbol_is_mips16 (sym.minsym); | |
4cc0665f MR |
1213 | else |
1214 | return is_mips16_addr (gdbarch, memaddr); | |
1215 | } | |
1216 | ||
1217 | /* Tell if the program counter value in MEMADDR is in a microMIPS function. */ | |
1218 | ||
1219 | int | |
1220 | mips_pc_is_micromips (struct gdbarch *gdbarch, CORE_ADDR memaddr) | |
1221 | { | |
7cbd4a93 | 1222 | struct bound_minimal_symbol sym; |
4cc0665f MR |
1223 | |
1224 | /* A flag indicating that this is a microMIPS function is stored by | |
1225 | elfread.c in the high bit of the info field. Use this to decide | |
1226 | if the function is microMIPS. Otherwise if bit 0 of the address | |
1227 | is set, then ELF file flags will tell if this is a microMIPS | |
1228 | function. */ | |
3e29f34a | 1229 | sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); |
7cbd4a93 TT |
1230 | if (sym.minsym) |
1231 | return msymbol_is_micromips (sym.minsym); | |
4cc0665f MR |
1232 | else |
1233 | return is_micromips_addr (gdbarch, memaddr); | |
1234 | } | |
1235 | ||
1236 | /* Tell the ISA type of the function the program counter value in MEMADDR | |
1237 | is in. */ | |
1238 | ||
1239 | static enum mips_isa | |
1240 | mips_pc_isa (struct gdbarch *gdbarch, CORE_ADDR memaddr) | |
1241 | { | |
7cbd4a93 | 1242 | struct bound_minimal_symbol sym; |
4cc0665f MR |
1243 | |
1244 | /* A flag indicating that this is a MIPS16 or a microMIPS function | |
1245 | is stored by elfread.c in the high bit of the info field. Use | |
1246 | this to decide if the function is MIPS16 or microMIPS or normal | |
1247 | MIPS. Otherwise if bit 0 of the address is set, then ELF file | |
1248 | flags will tell if this is a MIPS16 or a microMIPS function. */ | |
3e29f34a | 1249 | sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); |
7cbd4a93 | 1250 | if (sym.minsym) |
4cc0665f | 1251 | { |
7cbd4a93 | 1252 | if (msymbol_is_micromips (sym.minsym)) |
4cc0665f | 1253 | return ISA_MICROMIPS; |
7cbd4a93 | 1254 | else if (msymbol_is_mips16 (sym.minsym)) |
4cc0665f MR |
1255 | return ISA_MIPS16; |
1256 | else | |
1257 | return ISA_MIPS; | |
1258 | } | |
c906108c | 1259 | else |
4cc0665f MR |
1260 | { |
1261 | if (is_mips_addr (memaddr)) | |
1262 | return ISA_MIPS; | |
1263 | else if (is_micromips_addr (gdbarch, memaddr)) | |
1264 | return ISA_MICROMIPS; | |
1265 | else | |
1266 | return ISA_MIPS16; | |
1267 | } | |
c906108c SS |
1268 | } |
1269 | ||
3e29f34a MR |
1270 | /* Set the ISA bit correctly in the PC, used by DWARF-2 machinery. |
1271 | The need for comes from the ISA bit having been cleared, making | |
1272 | addresses in FDE, range records, etc. referring to compressed code | |
1273 | different to those in line information, the symbol table and finally | |
1274 | the PC register. That in turn confuses many operations. */ | |
1275 | ||
1276 | static CORE_ADDR | |
1277 | mips_adjust_dwarf2_addr (CORE_ADDR pc) | |
1278 | { | |
1279 | pc = unmake_compact_addr (pc); | |
1280 | return mips_pc_is_mips (pc) ? pc : make_compact_addr (pc); | |
1281 | } | |
1282 | ||
1283 | /* Recalculate the line record requested so that the resulting PC has | |
1284 | the ISA bit set correctly, used by DWARF-2 machinery. The need for | |
1285 | this adjustment comes from some records associated with compressed | |
1286 | code having the ISA bit cleared, most notably at function prologue | |
1287 | ends. The ISA bit is in this context retrieved from the minimal | |
1288 | symbol covering the address requested, which in turn has been | |
1289 | constructed from the binary's symbol table rather than DWARF-2 | |
1290 | information. The correct setting of the ISA bit is required for | |
1291 | breakpoint addresses to correctly match against the stop PC. | |
1292 | ||
1293 | As line entries can specify relative address adjustments we need to | |
1294 | keep track of the absolute value of the last line address recorded | |
1295 | in line information, so that we can calculate the actual address to | |
1296 | apply the ISA bit adjustment to. We use PC for this tracking and | |
1297 | keep the original address there. | |
1298 | ||
1299 | As such relative address adjustments can be odd within compressed | |
1300 | code we need to keep track of the last line address with the ISA | |
1301 | bit adjustment applied too, as the original address may or may not | |
1302 | have had the ISA bit set. We use ADJ_PC for this tracking and keep | |
1303 | the adjusted address there. | |
1304 | ||
1305 | For relative address adjustments we then use these variables to | |
1306 | calculate the address intended by line information, which will be | |
1307 | PC-relative, and return an updated adjustment carrying ISA bit | |
1308 | information, which will be ADJ_PC-relative. For absolute address | |
1309 | adjustments we just return the same address that we store in ADJ_PC | |
1310 | too. | |
1311 | ||
1312 | As the first line entry can be relative to an implied address value | |
1313 | of 0 we need to have the initial address set up that we store in PC | |
1314 | and ADJ_PC. This is arranged with a call from `dwarf_decode_lines_1' | |
1315 | that sets PC to 0 and ADJ_PC accordingly, usually 0 as well. */ | |
1316 | ||
1317 | static CORE_ADDR | |
1318 | mips_adjust_dwarf2_line (CORE_ADDR addr, int rel) | |
1319 | { | |
1320 | static CORE_ADDR adj_pc; | |
1321 | static CORE_ADDR pc; | |
1322 | CORE_ADDR isa_pc; | |
1323 | ||
1324 | pc = rel ? pc + addr : addr; | |
1325 | isa_pc = mips_adjust_dwarf2_addr (pc); | |
1326 | addr = rel ? isa_pc - adj_pc : isa_pc; | |
1327 | adj_pc = isa_pc; | |
1328 | return addr; | |
1329 | } | |
1330 | ||
14132e89 MR |
1331 | /* Various MIPS16 thunk (aka stub or trampoline) names. */ |
1332 | ||
1333 | static const char mips_str_mips16_call_stub[] = "__mips16_call_stub_"; | |
1334 | static const char mips_str_mips16_ret_stub[] = "__mips16_ret_"; | |
1335 | static const char mips_str_call_fp_stub[] = "__call_stub_fp_"; | |
1336 | static const char mips_str_call_stub[] = "__call_stub_"; | |
1337 | static const char mips_str_fn_stub[] = "__fn_stub_"; | |
1338 | ||
1339 | /* This is used as a PIC thunk prefix. */ | |
1340 | ||
1341 | static const char mips_str_pic[] = ".pic."; | |
1342 | ||
1343 | /* Return non-zero if the PC is inside a call thunk (aka stub or | |
1344 | trampoline) that should be treated as a temporary frame. */ | |
1345 | ||
1346 | static int | |
1347 | mips_in_frame_stub (CORE_ADDR pc) | |
1348 | { | |
1349 | CORE_ADDR start_addr; | |
1350 | const char *name; | |
1351 | ||
1352 | /* Find the starting address of the function containing the PC. */ | |
1353 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
1354 | return 0; | |
1355 | ||
1356 | /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */ | |
61012eef | 1357 | if (startswith (name, mips_str_mips16_call_stub)) |
14132e89 MR |
1358 | return 1; |
1359 | /* If the PC is in __call_stub_*, this is a call/return or a call stub. */ | |
61012eef | 1360 | if (startswith (name, mips_str_call_stub)) |
14132e89 MR |
1361 | return 1; |
1362 | /* If the PC is in __fn_stub_*, this is a call stub. */ | |
61012eef | 1363 | if (startswith (name, mips_str_fn_stub)) |
14132e89 MR |
1364 | return 1; |
1365 | ||
1366 | return 0; /* Not a stub. */ | |
1367 | } | |
1368 | ||
b2fa5097 | 1369 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
025bb325 | 1370 | all registers should be sign extended for simplicity? */ |
6c997a34 AC |
1371 | |
1372 | static CORE_ADDR | |
c113ed0c | 1373 | mips_read_pc (readable_regcache *regcache) |
6c997a34 | 1374 | { |
ac7936df | 1375 | int regnum = gdbarch_pc_regnum (regcache->arch ()); |
70242eb1 | 1376 | LONGEST pc; |
8376de04 | 1377 | |
c113ed0c | 1378 | regcache->cooked_read (regnum, &pc); |
61a1198a | 1379 | return pc; |
b6cb9035 AC |
1380 | } |
1381 | ||
58dfe9ff AC |
1382 | static CORE_ADDR |
1383 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1384 | { | |
14132e89 | 1385 | CORE_ADDR pc; |
930bd0e0 | 1386 | |
8376de04 | 1387 | pc = frame_unwind_register_signed (next_frame, gdbarch_pc_regnum (gdbarch)); |
14132e89 MR |
1388 | /* macro/2012-04-20: This hack skips over MIPS16 call thunks as |
1389 | intermediate frames. In this case we can get the caller's address | |
1390 | from $ra, or if $ra contains an address within a thunk as well, then | |
1391 | it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10} | |
1392 | and thus the caller's address is in $s2. */ | |
1393 | if (frame_relative_level (next_frame) >= 0 && mips_in_frame_stub (pc)) | |
1394 | { | |
1395 | pc = frame_unwind_register_signed | |
1396 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM); | |
14132e89 | 1397 | if (mips_in_frame_stub (pc)) |
3e29f34a MR |
1398 | pc = frame_unwind_register_signed |
1399 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); | |
14132e89 | 1400 | } |
930bd0e0 | 1401 | return pc; |
edfae063 AC |
1402 | } |
1403 | ||
30244cd8 UW |
1404 | static CORE_ADDR |
1405 | mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1406 | { | |
72a155b4 UW |
1407 | return frame_unwind_register_signed |
1408 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM); | |
30244cd8 UW |
1409 | } |
1410 | ||
b8a22b94 | 1411 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that |
edfae063 AC |
1412 | dummy frame. The frame ID's base needs to match the TOS value |
1413 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
1414 | breakpoint. */ | |
1415 | ||
1416 | static struct frame_id | |
b8a22b94 | 1417 | mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
edfae063 | 1418 | { |
f57d151a | 1419 | return frame_id_build |
b8a22b94 DJ |
1420 | (get_frame_register_signed (this_frame, |
1421 | gdbarch_num_regs (gdbarch) | |
1422 | + MIPS_SP_REGNUM), | |
1423 | get_frame_pc (this_frame)); | |
58dfe9ff AC |
1424 | } |
1425 | ||
5a439849 MR |
1426 | /* Implement the "write_pc" gdbarch method. */ |
1427 | ||
1428 | void | |
61a1198a | 1429 | mips_write_pc (struct regcache *regcache, CORE_ADDR pc) |
b6cb9035 | 1430 | { |
ac7936df | 1431 | int regnum = gdbarch_pc_regnum (regcache->arch ()); |
8376de04 | 1432 | |
3e29f34a | 1433 | regcache_cooked_write_unsigned (regcache, regnum, pc); |
6c997a34 | 1434 | } |
c906108c | 1435 | |
4cc0665f MR |
1436 | /* Fetch and return instruction from the specified location. Handle |
1437 | MIPS16/microMIPS as appropriate. */ | |
c906108c | 1438 | |
d37cca3d | 1439 | static ULONGEST |
4cc0665f | 1440 | mips_fetch_instruction (struct gdbarch *gdbarch, |
d09f2c3f | 1441 | enum mips_isa isa, CORE_ADDR addr, int *errp) |
c906108c | 1442 | { |
e17a4113 | 1443 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 1444 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c | 1445 | int instlen; |
d09f2c3f | 1446 | int err; |
c906108c | 1447 | |
4cc0665f | 1448 | switch (isa) |
c906108c | 1449 | { |
4cc0665f MR |
1450 | case ISA_MICROMIPS: |
1451 | case ISA_MIPS16: | |
95ac2dcf | 1452 | instlen = MIPS_INSN16_SIZE; |
4cc0665f MR |
1453 | addr = unmake_compact_addr (addr); |
1454 | break; | |
1455 | case ISA_MIPS: | |
1456 | instlen = MIPS_INSN32_SIZE; | |
1457 | break; | |
1458 | default: | |
1459 | internal_error (__FILE__, __LINE__, _("invalid ISA")); | |
1460 | break; | |
c906108c | 1461 | } |
d09f2c3f PA |
1462 | err = target_read_memory (addr, buf, instlen); |
1463 | if (errp != NULL) | |
1464 | *errp = err; | |
1465 | if (err != 0) | |
4cc0665f | 1466 | { |
d09f2c3f PA |
1467 | if (errp == NULL) |
1468 | memory_error (TARGET_XFER_E_IO, addr); | |
4cc0665f MR |
1469 | return 0; |
1470 | } | |
e17a4113 | 1471 | return extract_unsigned_integer (buf, instlen, byte_order); |
c906108c SS |
1472 | } |
1473 | ||
025bb325 | 1474 | /* These are the fields of 32 bit mips instructions. */ |
e135b889 DJ |
1475 | #define mips32_op(x) (x >> 26) |
1476 | #define itype_op(x) (x >> 26) | |
1477 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 1478 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 1479 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 1480 | |
e135b889 DJ |
1481 | #define jtype_op(x) (x >> 26) |
1482 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 1483 | |
e135b889 DJ |
1484 | #define rtype_op(x) (x >> 26) |
1485 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
1486 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
1487 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
1488 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
1489 | #define rtype_funct(x) (x & 0x3f) | |
c906108c | 1490 | |
4cc0665f MR |
1491 | /* MicroMIPS instruction fields. */ |
1492 | #define micromips_op(x) ((x) >> 10) | |
1493 | ||
1494 | /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest | |
1495 | bit and the size respectively of the field extracted. */ | |
1496 | #define b0s4_imm(x) ((x) & 0xf) | |
1497 | #define b0s5_imm(x) ((x) & 0x1f) | |
1498 | #define b0s5_reg(x) ((x) & 0x1f) | |
1499 | #define b0s7_imm(x) ((x) & 0x7f) | |
1500 | #define b0s10_imm(x) ((x) & 0x3ff) | |
1501 | #define b1s4_imm(x) (((x) >> 1) & 0xf) | |
1502 | #define b1s9_imm(x) (((x) >> 1) & 0x1ff) | |
1503 | #define b2s3_cc(x) (((x) >> 2) & 0x7) | |
1504 | #define b4s2_regl(x) (((x) >> 4) & 0x3) | |
1505 | #define b5s5_op(x) (((x) >> 5) & 0x1f) | |
1506 | #define b5s5_reg(x) (((x) >> 5) & 0x1f) | |
1507 | #define b6s4_op(x) (((x) >> 6) & 0xf) | |
1508 | #define b7s3_reg(x) (((x) >> 7) & 0x7) | |
1509 | ||
1510 | /* 32-bit instruction formats, B and S refer to the lowest bit and the size | |
1511 | respectively of the field extracted. */ | |
1512 | #define b0s6_op(x) ((x) & 0x3f) | |
1513 | #define b0s11_op(x) ((x) & 0x7ff) | |
1514 | #define b0s12_imm(x) ((x) & 0xfff) | |
1515 | #define b0s16_imm(x) ((x) & 0xffff) | |
1516 | #define b0s26_imm(x) ((x) & 0x3ffffff) | |
1517 | #define b6s10_ext(x) (((x) >> 6) & 0x3ff) | |
1518 | #define b11s5_reg(x) (((x) >> 11) & 0x1f) | |
1519 | #define b12s4_op(x) (((x) >> 12) & 0xf) | |
1520 | ||
1521 | /* Return the size in bytes of the instruction INSN encoded in the ISA | |
1522 | instruction set. */ | |
1523 | ||
1524 | static int | |
1525 | mips_insn_size (enum mips_isa isa, ULONGEST insn) | |
1526 | { | |
1527 | switch (isa) | |
1528 | { | |
1529 | case ISA_MICROMIPS: | |
100b4f2e MR |
1530 | if ((micromips_op (insn) & 0x4) == 0x4 |
1531 | || (micromips_op (insn) & 0x7) == 0x0) | |
dda83cd7 | 1532 | return 2 * MIPS_INSN16_SIZE; |
4cc0665f | 1533 | else |
dda83cd7 | 1534 | return MIPS_INSN16_SIZE; |
4cc0665f MR |
1535 | case ISA_MIPS16: |
1536 | if ((insn & 0xf800) == 0xf000) | |
1537 | return 2 * MIPS_INSN16_SIZE; | |
1538 | else | |
1539 | return MIPS_INSN16_SIZE; | |
1540 | case ISA_MIPS: | |
1541 | return MIPS_INSN32_SIZE; | |
1542 | } | |
1543 | internal_error (__FILE__, __LINE__, _("invalid ISA")); | |
1544 | } | |
1545 | ||
06987e64 MK |
1546 | static LONGEST |
1547 | mips32_relative_offset (ULONGEST inst) | |
c5aa993b | 1548 | { |
06987e64 | 1549 | return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; |
c906108c SS |
1550 | } |
1551 | ||
a385295e MR |
1552 | /* Determine the address of the next instruction executed after the INST |
1553 | floating condition branch instruction at PC. COUNT specifies the | |
1554 | number of the floating condition bits tested by the branch. */ | |
1555 | ||
1556 | static CORE_ADDR | |
7113a196 | 1557 | mips32_bc1_pc (struct gdbarch *gdbarch, struct regcache *regcache, |
a385295e MR |
1558 | ULONGEST inst, CORE_ADDR pc, int count) |
1559 | { | |
1560 | int fcsr = mips_regnum (gdbarch)->fp_control_status; | |
1561 | int cnum = (itype_rt (inst) >> 2) & (count - 1); | |
1562 | int tf = itype_rt (inst) & 1; | |
1563 | int mask = (1 << count) - 1; | |
1564 | ULONGEST fcs; | |
1565 | int cond; | |
1566 | ||
1567 | if (fcsr == -1) | |
1568 | /* No way to handle; it'll most likely trap anyway. */ | |
1569 | return pc; | |
1570 | ||
7113a196 | 1571 | fcs = regcache_raw_get_unsigned (regcache, fcsr); |
a385295e MR |
1572 | cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); |
1573 | ||
1574 | if (((cond >> cnum) & mask) != mask * !tf) | |
1575 | pc += mips32_relative_offset (inst); | |
1576 | else | |
1577 | pc += 4; | |
1578 | ||
1579 | return pc; | |
1580 | } | |
1581 | ||
f94363d7 AP |
1582 | /* Return nonzero if the gdbarch is an Octeon series. */ |
1583 | ||
1584 | static int | |
1585 | is_octeon (struct gdbarch *gdbarch) | |
1586 | { | |
1587 | const struct bfd_arch_info *info = gdbarch_bfd_arch_info (gdbarch); | |
1588 | ||
1589 | return (info->mach == bfd_mach_mips_octeon | |
dda83cd7 SM |
1590 | || info->mach == bfd_mach_mips_octeonp |
1591 | || info->mach == bfd_mach_mips_octeon2); | |
f94363d7 AP |
1592 | } |
1593 | ||
1594 | /* Return true if the OP represents the Octeon's BBIT instruction. */ | |
1595 | ||
1596 | static int | |
1597 | is_octeon_bbit_op (int op, struct gdbarch *gdbarch) | |
1598 | { | |
1599 | if (!is_octeon (gdbarch)) | |
1600 | return 0; | |
1601 | /* BBIT0 is encoded as LWC2: 110 010. */ | |
1602 | /* BBIT032 is encoded as LDC2: 110 110. */ | |
1603 | /* BBIT1 is encoded as SWC2: 111 010. */ | |
1604 | /* BBIT132 is encoded as SDC2: 111 110. */ | |
1605 | if (op == 50 || op == 54 || op == 58 || op == 62) | |
1606 | return 1; | |
1607 | return 0; | |
1608 | } | |
1609 | ||
1610 | ||
f49e4e6d MS |
1611 | /* Determine where to set a single step breakpoint while considering |
1612 | branch prediction. */ | |
78a59c2f | 1613 | |
5a89d8aa | 1614 | static CORE_ADDR |
7113a196 | 1615 | mips32_next_pc (struct regcache *regcache, CORE_ADDR pc) |
c5aa993b | 1616 | { |
ac7936df | 1617 | struct gdbarch *gdbarch = regcache->arch (); |
c5aa993b JM |
1618 | unsigned long inst; |
1619 | int op; | |
4cc0665f | 1620 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
4f5bcb50 | 1621 | op = itype_op (inst); |
025bb325 MS |
1622 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch |
1623 | instruction. */ | |
c5aa993b | 1624 | { |
4f5bcb50 | 1625 | if (op >> 2 == 5) |
6d82d43b | 1626 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 1627 | { |
4f5bcb50 | 1628 | switch (op & 0x03) |
c906108c | 1629 | { |
e135b889 DJ |
1630 | case 0: /* BEQL */ |
1631 | goto equal_branch; | |
1632 | case 1: /* BNEL */ | |
1633 | goto neq_branch; | |
1634 | case 2: /* BLEZL */ | |
1635 | goto less_branch; | |
313628cc | 1636 | case 3: /* BGTZL */ |
e135b889 | 1637 | goto greater_branch; |
c5aa993b JM |
1638 | default: |
1639 | pc += 4; | |
c906108c SS |
1640 | } |
1641 | } | |
4f5bcb50 | 1642 | else if (op == 17 && itype_rs (inst) == 8) |
6d82d43b | 1643 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
7113a196 | 1644 | pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 1); |
4f5bcb50 | 1645 | else if (op == 17 && itype_rs (inst) == 9 |
a385295e MR |
1646 | && (itype_rt (inst) & 2) == 0) |
1647 | /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */ | |
7113a196 | 1648 | pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 2); |
4f5bcb50 | 1649 | else if (op == 17 && itype_rs (inst) == 10 |
a385295e MR |
1650 | && (itype_rt (inst) & 2) == 0) |
1651 | /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */ | |
7113a196 | 1652 | pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 4); |
4f5bcb50 | 1653 | else if (op == 29) |
9e8da49c MR |
1654 | /* JALX: 011101 */ |
1655 | /* The new PC will be alternate mode. */ | |
1656 | { | |
1657 | unsigned long reg; | |
1658 | ||
1659 | reg = jtype_target (inst) << 2; | |
1660 | /* Add 1 to indicate 16-bit mode -- invert ISA mode. */ | |
1661 | pc = ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + reg + 1; | |
1662 | } | |
f94363d7 AP |
1663 | else if (is_octeon_bbit_op (op, gdbarch)) |
1664 | { | |
1665 | int bit, branch_if; | |
1666 | ||
1667 | branch_if = op == 58 || op == 62; | |
1668 | bit = itype_rt (inst); | |
1669 | ||
1670 | /* Take into account the *32 instructions. */ | |
1671 | if (op == 54 || op == 62) | |
1672 | bit += 32; | |
1673 | ||
7113a196 YQ |
1674 | if (((regcache_raw_get_signed (regcache, |
1675 | itype_rs (inst)) >> bit) & 1) | |
dda83cd7 | 1676 | == branch_if) |
f94363d7 | 1677 | pc += mips32_relative_offset (inst) + 4; |
dda83cd7 | 1678 | else |
f94363d7 AP |
1679 | pc += 8; /* After the delay slot. */ |
1680 | } | |
1681 | ||
c5aa993b | 1682 | else |
025bb325 | 1683 | pc += 4; /* Not a branch, next instruction is easy. */ |
c906108c SS |
1684 | } |
1685 | else | |
025bb325 | 1686 | { /* This gets way messy. */ |
c5aa993b | 1687 | |
025bb325 | 1688 | /* Further subdivide into SPECIAL, REGIMM and other. */ |
4f5bcb50 | 1689 | switch (op & 0x07) /* Extract bits 28,27,26. */ |
c906108c | 1690 | { |
c5aa993b JM |
1691 | case 0: /* SPECIAL */ |
1692 | op = rtype_funct (inst); | |
1693 | switch (op) | |
1694 | { | |
1695 | case 8: /* JR */ | |
1696 | case 9: /* JALR */ | |
025bb325 | 1697 | /* Set PC to that address. */ |
7113a196 | 1698 | pc = regcache_raw_get_signed (regcache, rtype_rs (inst)); |
c5aa993b | 1699 | break; |
e38d4e1a DJ |
1700 | case 12: /* SYSCALL */ |
1701 | { | |
1702 | struct gdbarch_tdep *tdep; | |
1703 | ||
7113a196 | 1704 | tdep = gdbarch_tdep (gdbarch); |
e38d4e1a | 1705 | if (tdep->syscall_next_pc != NULL) |
7113a196 | 1706 | pc = tdep->syscall_next_pc (get_current_frame ()); |
e38d4e1a DJ |
1707 | else |
1708 | pc += 4; | |
1709 | } | |
1710 | break; | |
c5aa993b JM |
1711 | default: |
1712 | pc += 4; | |
1713 | } | |
1714 | ||
6d82d43b | 1715 | break; /* end SPECIAL */ |
025bb325 | 1716 | case 1: /* REGIMM */ |
c906108c | 1717 | { |
e135b889 DJ |
1718 | op = itype_rt (inst); /* branch condition */ |
1719 | switch (op) | |
c906108c | 1720 | { |
c5aa993b | 1721 | case 0: /* BLTZ */ |
e135b889 DJ |
1722 | case 2: /* BLTZL */ |
1723 | case 16: /* BLTZAL */ | |
c5aa993b | 1724 | case 18: /* BLTZALL */ |
c906108c | 1725 | less_branch: |
7113a196 | 1726 | if (regcache_raw_get_signed (regcache, itype_rs (inst)) < 0) |
c5aa993b JM |
1727 | pc += mips32_relative_offset (inst) + 4; |
1728 | else | |
1729 | pc += 8; /* after the delay slot */ | |
1730 | break; | |
e135b889 | 1731 | case 1: /* BGEZ */ |
c5aa993b JM |
1732 | case 3: /* BGEZL */ |
1733 | case 17: /* BGEZAL */ | |
1734 | case 19: /* BGEZALL */ | |
7113a196 | 1735 | if (regcache_raw_get_signed (regcache, itype_rs (inst)) >= 0) |
c5aa993b JM |
1736 | pc += mips32_relative_offset (inst) + 4; |
1737 | else | |
1738 | pc += 8; /* after the delay slot */ | |
1739 | break; | |
a385295e MR |
1740 | case 0x1c: /* BPOSGE32 */ |
1741 | case 0x1e: /* BPOSGE64 */ | |
1742 | pc += 4; | |
1743 | if (itype_rs (inst) == 0) | |
1744 | { | |
1745 | unsigned int pos = (op & 2) ? 64 : 32; | |
1746 | int dspctl = mips_regnum (gdbarch)->dspctl; | |
1747 | ||
1748 | if (dspctl == -1) | |
1749 | /* No way to handle; it'll most likely trap anyway. */ | |
1750 | break; | |
1751 | ||
7113a196 YQ |
1752 | if ((regcache_raw_get_unsigned (regcache, |
1753 | dspctl) & 0x7f) >= pos) | |
a385295e MR |
1754 | pc += mips32_relative_offset (inst); |
1755 | else | |
1756 | pc += 4; | |
1757 | } | |
1758 | break; | |
e135b889 | 1759 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1760 | default: |
1761 | pc += 4; | |
c906108c SS |
1762 | } |
1763 | } | |
6d82d43b | 1764 | break; /* end REGIMM */ |
c5aa993b JM |
1765 | case 2: /* J */ |
1766 | case 3: /* JAL */ | |
1767 | { | |
1768 | unsigned long reg; | |
1769 | reg = jtype_target (inst) << 2; | |
025bb325 | 1770 | /* Upper four bits get never changed... */ |
5b652102 | 1771 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
c906108c | 1772 | } |
c5aa993b | 1773 | break; |
e135b889 | 1774 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1775 | equal_branch: |
7113a196 YQ |
1776 | if (regcache_raw_get_signed (regcache, itype_rs (inst)) == |
1777 | regcache_raw_get_signed (regcache, itype_rt (inst))) | |
c5aa993b JM |
1778 | pc += mips32_relative_offset (inst) + 4; |
1779 | else | |
1780 | pc += 8; | |
1781 | break; | |
e135b889 | 1782 | case 5: /* BNE, BNEL */ |
c5aa993b | 1783 | neq_branch: |
7113a196 YQ |
1784 | if (regcache_raw_get_signed (regcache, itype_rs (inst)) != |
1785 | regcache_raw_get_signed (regcache, itype_rt (inst))) | |
c5aa993b JM |
1786 | pc += mips32_relative_offset (inst) + 4; |
1787 | else | |
1788 | pc += 8; | |
1789 | break; | |
e135b889 | 1790 | case 6: /* BLEZ, BLEZL */ |
7113a196 | 1791 | if (regcache_raw_get_signed (regcache, itype_rs (inst)) <= 0) |
c5aa993b JM |
1792 | pc += mips32_relative_offset (inst) + 4; |
1793 | else | |
1794 | pc += 8; | |
1795 | break; | |
1796 | case 7: | |
e135b889 DJ |
1797 | default: |
1798 | greater_branch: /* BGTZ, BGTZL */ | |
7113a196 | 1799 | if (regcache_raw_get_signed (regcache, itype_rs (inst)) > 0) |
c5aa993b JM |
1800 | pc += mips32_relative_offset (inst) + 4; |
1801 | else | |
1802 | pc += 8; | |
1803 | break; | |
c5aa993b JM |
1804 | } /* switch */ |
1805 | } /* else */ | |
1806 | return pc; | |
1807 | } /* mips32_next_pc */ | |
c906108c | 1808 | |
4cc0665f MR |
1809 | /* Extract the 7-bit signed immediate offset from the microMIPS instruction |
1810 | INSN. */ | |
1811 | ||
1812 | static LONGEST | |
1813 | micromips_relative_offset7 (ULONGEST insn) | |
1814 | { | |
1815 | return ((b0s7_imm (insn) ^ 0x40) - 0x40) << 1; | |
1816 | } | |
1817 | ||
1818 | /* Extract the 10-bit signed immediate offset from the microMIPS instruction | |
1819 | INSN. */ | |
1820 | ||
1821 | static LONGEST | |
1822 | micromips_relative_offset10 (ULONGEST insn) | |
1823 | { | |
1824 | return ((b0s10_imm (insn) ^ 0x200) - 0x200) << 1; | |
1825 | } | |
1826 | ||
1827 | /* Extract the 16-bit signed immediate offset from the microMIPS instruction | |
1828 | INSN. */ | |
1829 | ||
1830 | static LONGEST | |
1831 | micromips_relative_offset16 (ULONGEST insn) | |
1832 | { | |
1833 | return ((b0s16_imm (insn) ^ 0x8000) - 0x8000) << 1; | |
1834 | } | |
1835 | ||
1836 | /* Return the size in bytes of the microMIPS instruction at the address PC. */ | |
1837 | ||
1838 | static int | |
1839 | micromips_pc_insn_size (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1840 | { | |
1841 | ULONGEST insn; | |
1842 | ||
1843 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
1844 | return mips_insn_size (ISA_MICROMIPS, insn); | |
1845 | } | |
1846 | ||
1847 | /* Calculate the address of the next microMIPS instruction to execute | |
1848 | after the INSN coprocessor 1 conditional branch instruction at the | |
1849 | address PC. COUNT denotes the number of coprocessor condition bits | |
1850 | examined by the branch. */ | |
1851 | ||
1852 | static CORE_ADDR | |
7113a196 | 1853 | micromips_bc1_pc (struct gdbarch *gdbarch, struct regcache *regcache, |
4cc0665f MR |
1854 | ULONGEST insn, CORE_ADDR pc, int count) |
1855 | { | |
1856 | int fcsr = mips_regnum (gdbarch)->fp_control_status; | |
1857 | int cnum = b2s3_cc (insn >> 16) & (count - 1); | |
1858 | int tf = b5s5_op (insn >> 16) & 1; | |
1859 | int mask = (1 << count) - 1; | |
1860 | ULONGEST fcs; | |
1861 | int cond; | |
1862 | ||
1863 | if (fcsr == -1) | |
1864 | /* No way to handle; it'll most likely trap anyway. */ | |
1865 | return pc; | |
1866 | ||
7113a196 | 1867 | fcs = regcache_raw_get_unsigned (regcache, fcsr); |
4cc0665f MR |
1868 | cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); |
1869 | ||
1870 | if (((cond >> cnum) & mask) != mask * !tf) | |
1871 | pc += micromips_relative_offset16 (insn); | |
1872 | else | |
1873 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1874 | ||
1875 | return pc; | |
1876 | } | |
1877 | ||
1878 | /* Calculate the address of the next microMIPS instruction to execute | |
1879 | after the instruction at the address PC. */ | |
1880 | ||
1881 | static CORE_ADDR | |
7113a196 | 1882 | micromips_next_pc (struct regcache *regcache, CORE_ADDR pc) |
4cc0665f | 1883 | { |
ac7936df | 1884 | struct gdbarch *gdbarch = regcache->arch (); |
4cc0665f MR |
1885 | ULONGEST insn; |
1886 | ||
1887 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
1888 | pc += MIPS_INSN16_SIZE; | |
1889 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
1890 | { | |
4cc0665f MR |
1891 | /* 32-bit instructions. */ |
1892 | case 2 * MIPS_INSN16_SIZE: | |
1893 | insn <<= 16; | |
1894 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
1895 | pc += MIPS_INSN16_SIZE; | |
1896 | switch (micromips_op (insn >> 16)) | |
1897 | { | |
1898 | case 0x00: /* POOL32A: bits 000000 */ | |
6592ceed MR |
1899 | switch (b0s6_op (insn)) |
1900 | { | |
1901 | case 0x3c: /* POOL32Axf: bits 000000 ... 111100 */ | |
1902 | switch (b6s10_ext (insn)) | |
1903 | { | |
1904 | case 0x3c: /* JALR: 000000 0000111100 111100 */ | |
1905 | case 0x7c: /* JALR.HB: 000000 0001111100 111100 */ | |
1906 | case 0x13c: /* JALRS: 000000 0100111100 111100 */ | |
1907 | case 0x17c: /* JALRS.HB: 000000 0101111100 111100 */ | |
1908 | pc = regcache_raw_get_signed (regcache, | |
1909 | b0s5_reg (insn >> 16)); | |
1910 | break; | |
1911 | case 0x22d: /* SYSCALL: 000000 1000101101 111100 */ | |
1912 | { | |
1913 | struct gdbarch_tdep *tdep; | |
1914 | ||
1915 | tdep = gdbarch_tdep (gdbarch); | |
1916 | if (tdep->syscall_next_pc != NULL) | |
1917 | pc = tdep->syscall_next_pc (get_current_frame ()); | |
1918 | } | |
1919 | break; | |
1920 | } | |
1921 | break; | |
1922 | } | |
4cc0665f MR |
1923 | break; |
1924 | ||
1925 | case 0x10: /* POOL32I: bits 010000 */ | |
1926 | switch (b5s5_op (insn >> 16)) | |
1927 | { | |
1928 | case 0x00: /* BLTZ: bits 010000 00000 */ | |
1929 | case 0x01: /* BLTZAL: bits 010000 00001 */ | |
1930 | case 0x11: /* BLTZALS: bits 010000 10001 */ | |
7113a196 YQ |
1931 | if (regcache_raw_get_signed (regcache, |
1932 | b0s5_reg (insn >> 16)) < 0) | |
4cc0665f MR |
1933 | pc += micromips_relative_offset16 (insn); |
1934 | else | |
1935 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1936 | break; | |
1937 | ||
1938 | case 0x02: /* BGEZ: bits 010000 00010 */ | |
1939 | case 0x03: /* BGEZAL: bits 010000 00011 */ | |
1940 | case 0x13: /* BGEZALS: bits 010000 10011 */ | |
7113a196 YQ |
1941 | if (regcache_raw_get_signed (regcache, |
1942 | b0s5_reg (insn >> 16)) >= 0) | |
4cc0665f MR |
1943 | pc += micromips_relative_offset16 (insn); |
1944 | else | |
1945 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1946 | break; | |
1947 | ||
1948 | case 0x04: /* BLEZ: bits 010000 00100 */ | |
7113a196 YQ |
1949 | if (regcache_raw_get_signed (regcache, |
1950 | b0s5_reg (insn >> 16)) <= 0) | |
4cc0665f MR |
1951 | pc += micromips_relative_offset16 (insn); |
1952 | else | |
1953 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1954 | break; | |
1955 | ||
1956 | case 0x05: /* BNEZC: bits 010000 00101 */ | |
7113a196 YQ |
1957 | if (regcache_raw_get_signed (regcache, |
1958 | b0s5_reg (insn >> 16)) != 0) | |
4cc0665f MR |
1959 | pc += micromips_relative_offset16 (insn); |
1960 | break; | |
1961 | ||
1962 | case 0x06: /* BGTZ: bits 010000 00110 */ | |
7113a196 YQ |
1963 | if (regcache_raw_get_signed (regcache, |
1964 | b0s5_reg (insn >> 16)) > 0) | |
4cc0665f MR |
1965 | pc += micromips_relative_offset16 (insn); |
1966 | else | |
1967 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1968 | break; | |
1969 | ||
1970 | case 0x07: /* BEQZC: bits 010000 00111 */ | |
7113a196 YQ |
1971 | if (regcache_raw_get_signed (regcache, |
1972 | b0s5_reg (insn >> 16)) == 0) | |
4cc0665f MR |
1973 | pc += micromips_relative_offset16 (insn); |
1974 | break; | |
1975 | ||
1976 | case 0x14: /* BC2F: bits 010000 10100 xxx00 */ | |
1977 | case 0x15: /* BC2T: bits 010000 10101 xxx00 */ | |
1978 | if (((insn >> 16) & 0x3) == 0x0) | |
1979 | /* BC2F, BC2T: don't know how to handle these. */ | |
1980 | break; | |
1981 | break; | |
1982 | ||
1983 | case 0x1a: /* BPOSGE64: bits 010000 11010 */ | |
1984 | case 0x1b: /* BPOSGE32: bits 010000 11011 */ | |
1985 | { | |
1986 | unsigned int pos = (b5s5_op (insn >> 16) & 1) ? 32 : 64; | |
1987 | int dspctl = mips_regnum (gdbarch)->dspctl; | |
1988 | ||
1989 | if (dspctl == -1) | |
1990 | /* No way to handle; it'll most likely trap anyway. */ | |
1991 | break; | |
1992 | ||
7113a196 YQ |
1993 | if ((regcache_raw_get_unsigned (regcache, |
1994 | dspctl) & 0x7f) >= pos) | |
4cc0665f MR |
1995 | pc += micromips_relative_offset16 (insn); |
1996 | else | |
1997 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1998 | } | |
1999 | break; | |
2000 | ||
2001 | case 0x1c: /* BC1F: bits 010000 11100 xxx00 */ | |
2002 | /* BC1ANY2F: bits 010000 11100 xxx01 */ | |
2003 | case 0x1d: /* BC1T: bits 010000 11101 xxx00 */ | |
2004 | /* BC1ANY2T: bits 010000 11101 xxx01 */ | |
2005 | if (((insn >> 16) & 0x2) == 0x0) | |
7113a196 | 2006 | pc = micromips_bc1_pc (gdbarch, regcache, insn, pc, |
4cc0665f MR |
2007 | ((insn >> 16) & 0x1) + 1); |
2008 | break; | |
2009 | ||
2010 | case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */ | |
2011 | case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */ | |
2012 | if (((insn >> 16) & 0x3) == 0x1) | |
7113a196 | 2013 | pc = micromips_bc1_pc (gdbarch, regcache, insn, pc, 4); |
4cc0665f MR |
2014 | break; |
2015 | } | |
2016 | break; | |
2017 | ||
2018 | case 0x1d: /* JALS: bits 011101 */ | |
2019 | case 0x35: /* J: bits 110101 */ | |
2020 | case 0x3d: /* JAL: bits 111101 */ | |
2021 | pc = ((pc | 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn) << 1); | |
2022 | break; | |
2023 | ||
2024 | case 0x25: /* BEQ: bits 100101 */ | |
7113a196 YQ |
2025 | if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16)) |
2026 | == regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16))) | |
4cc0665f MR |
2027 | pc += micromips_relative_offset16 (insn); |
2028 | else | |
2029 | pc += micromips_pc_insn_size (gdbarch, pc); | |
2030 | break; | |
2031 | ||
2032 | case 0x2d: /* BNE: bits 101101 */ | |
7113a196 YQ |
2033 | if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16)) |
2034 | != regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16))) | |
4cc0665f MR |
2035 | pc += micromips_relative_offset16 (insn); |
2036 | else | |
2037 | pc += micromips_pc_insn_size (gdbarch, pc); | |
2038 | break; | |
2039 | ||
2040 | case 0x3c: /* JALX: bits 111100 */ | |
2041 | pc = ((pc | 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn) << 2); | |
2042 | break; | |
2043 | } | |
2044 | break; | |
2045 | ||
2046 | /* 16-bit instructions. */ | |
2047 | case MIPS_INSN16_SIZE: | |
2048 | switch (micromips_op (insn)) | |
2049 | { | |
2050 | case 0x11: /* POOL16C: bits 010001 */ | |
2051 | if ((b5s5_op (insn) & 0x1c) == 0xc) | |
2052 | /* JR16, JRC, JALR16, JALRS16: 010001 011xx */ | |
7113a196 | 2053 | pc = regcache_raw_get_signed (regcache, b0s5_reg (insn)); |
4cc0665f MR |
2054 | else if (b5s5_op (insn) == 0x18) |
2055 | /* JRADDIUSP: bits 010001 11000 */ | |
7113a196 | 2056 | pc = regcache_raw_get_signed (regcache, MIPS_RA_REGNUM); |
4cc0665f MR |
2057 | break; |
2058 | ||
2059 | case 0x23: /* BEQZ16: bits 100011 */ | |
2060 | { | |
2061 | int rs = mips_reg3_to_reg[b7s3_reg (insn)]; | |
2062 | ||
7113a196 | 2063 | if (regcache_raw_get_signed (regcache, rs) == 0) |
4cc0665f MR |
2064 | pc += micromips_relative_offset7 (insn); |
2065 | else | |
2066 | pc += micromips_pc_insn_size (gdbarch, pc); | |
2067 | } | |
2068 | break; | |
2069 | ||
2070 | case 0x2b: /* BNEZ16: bits 101011 */ | |
2071 | { | |
2072 | int rs = mips_reg3_to_reg[b7s3_reg (insn)]; | |
2073 | ||
7113a196 | 2074 | if (regcache_raw_get_signed (regcache, rs) != 0) |
4cc0665f MR |
2075 | pc += micromips_relative_offset7 (insn); |
2076 | else | |
2077 | pc += micromips_pc_insn_size (gdbarch, pc); | |
2078 | } | |
2079 | break; | |
2080 | ||
2081 | case 0x33: /* B16: bits 110011 */ | |
2082 | pc += micromips_relative_offset10 (insn); | |
2083 | break; | |
2084 | } | |
2085 | break; | |
2086 | } | |
2087 | ||
2088 | return pc; | |
2089 | } | |
2090 | ||
c906108c | 2091 | /* Decoding the next place to set a breakpoint is irregular for the |
025bb325 MS |
2092 | mips 16 variant, but fortunately, there fewer instructions. We have |
2093 | to cope ith extensions for 16 bit instructions and a pair of actual | |
2094 | 32 bit instructions. We dont want to set a single step instruction | |
2095 | on the extend instruction either. */ | |
c906108c SS |
2096 | |
2097 | /* Lots of mips16 instruction formats */ | |
2098 | /* Predicting jumps requires itype,ritype,i8type | |
025bb325 | 2099 | and their extensions extItype,extritype,extI8type. */ |
c906108c SS |
2100 | enum mips16_inst_fmts |
2101 | { | |
c5aa993b JM |
2102 | itype, /* 0 immediate 5,10 */ |
2103 | ritype, /* 1 5,3,8 */ | |
2104 | rrtype, /* 2 5,3,3,5 */ | |
2105 | rritype, /* 3 5,3,3,5 */ | |
2106 | rrrtype, /* 4 5,3,3,3,2 */ | |
2107 | rriatype, /* 5 5,3,3,1,4 */ | |
2108 | shifttype, /* 6 5,3,3,3,2 */ | |
2109 | i8type, /* 7 5,3,8 */ | |
2110 | i8movtype, /* 8 5,3,3,5 */ | |
2111 | i8mov32rtype, /* 9 5,3,5,3 */ | |
2112 | i64type, /* 10 5,3,8 */ | |
2113 | ri64type, /* 11 5,3,3,5 */ | |
2114 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
2115 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
2116 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
2117 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
2118 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
2119 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
2120 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
2121 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
2122 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
2123 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
2124 | }; | |
12f02c2a | 2125 | /* I am heaping all the fields of the formats into one structure and |
025bb325 | 2126 | then, only the fields which are involved in instruction extension. */ |
c906108c | 2127 | struct upk_mips16 |
6d82d43b AC |
2128 | { |
2129 | CORE_ADDR offset; | |
025bb325 | 2130 | unsigned int regx; /* Function in i8 type. */ |
6d82d43b AC |
2131 | unsigned int regy; |
2132 | }; | |
c906108c SS |
2133 | |
2134 | ||
12f02c2a | 2135 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
c68cf8ad | 2136 | for the bits which make up the immediate extension. */ |
c906108c | 2137 | |
12f02c2a AC |
2138 | static CORE_ADDR |
2139 | extended_offset (unsigned int extension) | |
c906108c | 2140 | { |
12f02c2a | 2141 | CORE_ADDR value; |
130854df | 2142 | |
4c2051c6 | 2143 | value = (extension >> 16) & 0x1f; /* Extract 15:11. */ |
c5aa993b | 2144 | value = value << 6; |
4c2051c6 | 2145 | value |= (extension >> 21) & 0x3f; /* Extract 10:5. */ |
c5aa993b | 2146 | value = value << 5; |
130854df MR |
2147 | value |= extension & 0x1f; /* Extract 4:0. */ |
2148 | ||
c5aa993b | 2149 | return value; |
c906108c SS |
2150 | } |
2151 | ||
2152 | /* Only call this function if you know that this is an extendable | |
bcf1ea1e MR |
2153 | instruction. It won't malfunction, but why make excess remote memory |
2154 | references? If the immediate operands get sign extended or something, | |
2155 | do it after the extension is performed. */ | |
c906108c | 2156 | /* FIXME: Every one of these cases needs to worry about sign extension |
bcf1ea1e | 2157 | when the offset is to be used in relative addressing. */ |
c906108c | 2158 | |
12f02c2a | 2159 | static unsigned int |
e17a4113 | 2160 | fetch_mips_16 (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 2161 | { |
e17a4113 | 2162 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 2163 | gdb_byte buf[8]; |
a2fb2cee MR |
2164 | |
2165 | pc = unmake_compact_addr (pc); /* Clear the low order bit. */ | |
c5aa993b | 2166 | target_read_memory (pc, buf, 2); |
e17a4113 | 2167 | return extract_unsigned_integer (buf, 2, byte_order); |
c906108c SS |
2168 | } |
2169 | ||
2170 | static void | |
e17a4113 | 2171 | unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc, |
12f02c2a AC |
2172 | unsigned int extension, |
2173 | unsigned int inst, | |
6d82d43b | 2174 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 2175 | { |
12f02c2a AC |
2176 | CORE_ADDR offset; |
2177 | int regx; | |
2178 | int regy; | |
2179 | switch (insn_format) | |
c906108c | 2180 | { |
c5aa993b | 2181 | case itype: |
c906108c | 2182 | { |
12f02c2a AC |
2183 | CORE_ADDR value; |
2184 | if (extension) | |
c5aa993b | 2185 | { |
4c2051c6 MR |
2186 | value = extended_offset ((extension << 16) | inst); |
2187 | value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ | |
c906108c SS |
2188 | } |
2189 | else | |
c5aa993b | 2190 | { |
12f02c2a | 2191 | value = inst & 0x7ff; |
4c2051c6 | 2192 | value = (value ^ 0x400) - 0x400; /* Sign-extend. */ |
c906108c | 2193 | } |
12f02c2a AC |
2194 | offset = value; |
2195 | regx = -1; | |
2196 | regy = -1; | |
c906108c | 2197 | } |
c5aa993b JM |
2198 | break; |
2199 | case ritype: | |
2200 | case i8type: | |
025bb325 | 2201 | { /* A register identifier and an offset. */ |
c906108c | 2202 | /* Most of the fields are the same as I type but the |
025bb325 | 2203 | immediate value is of a different length. */ |
12f02c2a AC |
2204 | CORE_ADDR value; |
2205 | if (extension) | |
c906108c | 2206 | { |
4c2051c6 MR |
2207 | value = extended_offset ((extension << 16) | inst); |
2208 | value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ | |
c906108c | 2209 | } |
c5aa993b JM |
2210 | else |
2211 | { | |
4c2051c6 MR |
2212 | value = inst & 0xff; /* 8 bits */ |
2213 | value = (value ^ 0x80) - 0x80; /* Sign-extend. */ | |
c5aa993b | 2214 | } |
12f02c2a | 2215 | offset = value; |
4c2051c6 | 2216 | regx = (inst >> 8) & 0x07; /* i8 funct */ |
12f02c2a | 2217 | regy = -1; |
c5aa993b | 2218 | break; |
c906108c | 2219 | } |
c5aa993b | 2220 | case jalxtype: |
c906108c | 2221 | { |
c5aa993b | 2222 | unsigned long value; |
12f02c2a AC |
2223 | unsigned int nexthalf; |
2224 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b | 2225 | value = value << 16; |
4cc0665f MR |
2226 | nexthalf = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc + 2, NULL); |
2227 | /* Low bit still set. */ | |
c5aa993b | 2228 | value |= nexthalf; |
12f02c2a AC |
2229 | offset = value; |
2230 | regx = -1; | |
2231 | regy = -1; | |
c5aa993b | 2232 | break; |
c906108c SS |
2233 | } |
2234 | default: | |
e2e0b3e5 | 2235 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c | 2236 | } |
12f02c2a AC |
2237 | upk->offset = offset; |
2238 | upk->regx = regx; | |
2239 | upk->regy = regy; | |
c906108c SS |
2240 | } |
2241 | ||
2242 | ||
484933d1 MR |
2243 | /* Calculate the destination of a branch whose 16-bit opcode word is at PC, |
2244 | and having a signed 16-bit OFFSET. */ | |
2245 | ||
c5aa993b JM |
2246 | static CORE_ADDR |
2247 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 2248 | { |
484933d1 | 2249 | return pc + (offset << 1) + 2; |
c906108c SS |
2250 | } |
2251 | ||
12f02c2a | 2252 | static CORE_ADDR |
7113a196 | 2253 | extended_mips16_next_pc (regcache *regcache, CORE_ADDR pc, |
6d82d43b | 2254 | unsigned int extension, unsigned int insn) |
c906108c | 2255 | { |
ac7936df | 2256 | struct gdbarch *gdbarch = regcache->arch (); |
12f02c2a AC |
2257 | int op = (insn >> 11); |
2258 | switch (op) | |
c906108c | 2259 | { |
6d82d43b | 2260 | case 2: /* Branch */ |
12f02c2a | 2261 | { |
12f02c2a | 2262 | struct upk_mips16 upk; |
e17a4113 | 2263 | unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk); |
484933d1 | 2264 | pc = add_offset_16 (pc, upk.offset); |
12f02c2a AC |
2265 | break; |
2266 | } | |
025bb325 MS |
2267 | case 3: /* JAL , JALX - Watch out, these are 32 bit |
2268 | instructions. */ | |
12f02c2a AC |
2269 | { |
2270 | struct upk_mips16 upk; | |
e17a4113 | 2271 | unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk); |
484933d1 | 2272 | pc = ((pc + 2) & (~(CORE_ADDR) 0x0fffffff)) | (upk.offset << 2); |
12f02c2a | 2273 | if ((insn >> 10) & 0x01) /* Exchange mode */ |
025bb325 | 2274 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode. */ |
12f02c2a AC |
2275 | else |
2276 | pc |= 0x01; | |
2277 | break; | |
2278 | } | |
6d82d43b | 2279 | case 4: /* beqz */ |
12f02c2a AC |
2280 | { |
2281 | struct upk_mips16 upk; | |
2282 | int reg; | |
e17a4113 | 2283 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
7113a196 | 2284 | reg = regcache_raw_get_signed (regcache, mips_reg3_to_reg[upk.regx]); |
12f02c2a | 2285 | if (reg == 0) |
484933d1 | 2286 | pc = add_offset_16 (pc, upk.offset); |
12f02c2a AC |
2287 | else |
2288 | pc += 2; | |
2289 | break; | |
2290 | } | |
6d82d43b | 2291 | case 5: /* bnez */ |
12f02c2a AC |
2292 | { |
2293 | struct upk_mips16 upk; | |
2294 | int reg; | |
e17a4113 | 2295 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
7113a196 | 2296 | reg = regcache_raw_get_signed (regcache, mips_reg3_to_reg[upk.regx]); |
12f02c2a | 2297 | if (reg != 0) |
484933d1 | 2298 | pc = add_offset_16 (pc, upk.offset); |
12f02c2a AC |
2299 | else |
2300 | pc += 2; | |
2301 | break; | |
2302 | } | |
6d82d43b | 2303 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
2304 | { |
2305 | struct upk_mips16 upk; | |
2306 | int reg; | |
e17a4113 | 2307 | unpack_mips16 (gdbarch, pc, extension, insn, i8type, &upk); |
12f02c2a | 2308 | /* upk.regx contains the opcode */ |
7113a196 YQ |
2309 | /* Test register is 24 */ |
2310 | reg = regcache_raw_get_signed (regcache, 24); | |
12f02c2a AC |
2311 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ |
2312 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
484933d1 | 2313 | pc = add_offset_16 (pc, upk.offset); |
12f02c2a AC |
2314 | else |
2315 | pc += 2; | |
2316 | break; | |
2317 | } | |
6d82d43b | 2318 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
2319 | { |
2320 | struct upk_mips16 upk; | |
2321 | /* upk.fmt = rrtype; */ | |
2322 | op = insn & 0x1f; | |
2323 | if (op == 0) | |
c5aa993b | 2324 | { |
12f02c2a AC |
2325 | int reg; |
2326 | upk.regx = (insn >> 8) & 0x07; | |
2327 | upk.regy = (insn >> 5) & 0x07; | |
4c2051c6 | 2328 | if ((upk.regy & 1) == 0) |
4cc0665f | 2329 | reg = mips_reg3_to_reg[upk.regx]; |
4c2051c6 MR |
2330 | else |
2331 | reg = 31; /* Function return instruction. */ | |
7113a196 | 2332 | pc = regcache_raw_get_signed (regcache, reg); |
c906108c | 2333 | } |
12f02c2a | 2334 | else |
c5aa993b | 2335 | pc += 2; |
12f02c2a AC |
2336 | break; |
2337 | } | |
2338 | case 30: | |
2339 | /* This is an instruction extension. Fetch the real instruction | |
dda83cd7 SM |
2340 | (which follows the extension) and decode things based on |
2341 | that. */ | |
12f02c2a AC |
2342 | { |
2343 | pc += 2; | |
7113a196 | 2344 | pc = extended_mips16_next_pc (regcache, pc, insn, |
e17a4113 | 2345 | fetch_mips_16 (gdbarch, pc)); |
12f02c2a AC |
2346 | break; |
2347 | } | |
2348 | default: | |
2349 | { | |
2350 | pc += 2; | |
2351 | break; | |
2352 | } | |
c906108c | 2353 | } |
c5aa993b | 2354 | return pc; |
12f02c2a | 2355 | } |
c906108c | 2356 | |
5a89d8aa | 2357 | static CORE_ADDR |
7113a196 | 2358 | mips16_next_pc (struct regcache *regcache, CORE_ADDR pc) |
12f02c2a | 2359 | { |
ac7936df | 2360 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 2361 | unsigned int insn = fetch_mips_16 (gdbarch, pc); |
7113a196 | 2362 | return extended_mips16_next_pc (regcache, pc, 0, insn); |
12f02c2a AC |
2363 | } |
2364 | ||
2365 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 2366 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a | 2367 | It works by decoding the current instruction and predicting where a |
1aee363c | 2368 | branch will go. This isn't hard because all the data is available. |
4cc0665f | 2369 | The MIPS32, MIPS16 and microMIPS variants are quite different. */ |
ad527d2e | 2370 | static CORE_ADDR |
7113a196 | 2371 | mips_next_pc (struct regcache *regcache, CORE_ADDR pc) |
c906108c | 2372 | { |
ac7936df | 2373 | struct gdbarch *gdbarch = regcache->arch (); |
4cc0665f MR |
2374 | |
2375 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
7113a196 | 2376 | return mips16_next_pc (regcache, pc); |
4cc0665f | 2377 | else if (mips_pc_is_micromips (gdbarch, pc)) |
7113a196 | 2378 | return micromips_next_pc (regcache, pc); |
c5aa993b | 2379 | else |
7113a196 | 2380 | return mips32_next_pc (regcache, pc); |
12f02c2a | 2381 | } |
c906108c | 2382 | |
ab50adb6 MR |
2383 | /* Return non-zero if the MIPS16 instruction INSN is a compact branch |
2384 | or jump. */ | |
2385 | ||
2386 | static int | |
2387 | mips16_instruction_is_compact_branch (unsigned short insn) | |
2388 | { | |
2389 | switch (insn & 0xf800) | |
2390 | { | |
2391 | case 0xe800: | |
2392 | return (insn & 0x009f) == 0x80; /* JALRC/JRC */ | |
2393 | case 0x6000: | |
2394 | return (insn & 0x0600) == 0; /* BTNEZ/BTEQZ */ | |
2395 | case 0x2800: /* BNEZ */ | |
2396 | case 0x2000: /* BEQZ */ | |
2397 | case 0x1000: /* B */ | |
2398 | return 1; | |
2399 | default: | |
2400 | return 0; | |
2401 | } | |
2402 | } | |
2403 | ||
2404 | /* Return non-zero if the microMIPS instruction INSN is a compact branch | |
2405 | or jump. */ | |
2406 | ||
2407 | static int | |
2408 | micromips_instruction_is_compact_branch (unsigned short insn) | |
2409 | { | |
2410 | switch (micromips_op (insn)) | |
2411 | { | |
2412 | case 0x11: /* POOL16C: bits 010001 */ | |
2413 | return (b5s5_op (insn) == 0x18 | |
2414 | /* JRADDIUSP: bits 010001 11000 */ | |
2415 | || b5s5_op (insn) == 0xd); | |
2416 | /* JRC: bits 010011 01101 */ | |
2417 | case 0x10: /* POOL32I: bits 010000 */ | |
2418 | return (b5s5_op (insn) & 0x1d) == 0x5; | |
2419 | /* BEQZC/BNEZC: bits 010000 001x1 */ | |
2420 | default: | |
2421 | return 0; | |
2422 | } | |
2423 | } | |
2424 | ||
edfae063 AC |
2425 | struct mips_frame_cache |
2426 | { | |
2427 | CORE_ADDR base; | |
098caef4 | 2428 | trad_frame_saved_reg *saved_regs; |
edfae063 AC |
2429 | }; |
2430 | ||
29639122 JB |
2431 | /* Set a register's saved stack address in temp_saved_regs. If an |
2432 | address has already been set for this register, do nothing; this | |
2433 | way we will only recognize the first save of a given register in a | |
2434 | function prologue. | |
eec63939 | 2435 | |
f57d151a UW |
2436 | For simplicity, save the address in both [0 .. gdbarch_num_regs) and |
2437 | [gdbarch_num_regs .. 2*gdbarch_num_regs). | |
2438 | Strictly speaking, only the second range is used as it is only second | |
2439 | range (the ABI instead of ISA registers) that comes into play when finding | |
2440 | saved registers in a frame. */ | |
eec63939 AC |
2441 | |
2442 | static void | |
74ed0bb4 MD |
2443 | set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache, |
2444 | int regnum, CORE_ADDR offset) | |
eec63939 | 2445 | { |
29639122 | 2446 | if (this_cache != NULL |
a9a87d35 LM |
2447 | && this_cache->saved_regs[regnum].is_realreg () |
2448 | && this_cache->saved_regs[regnum].realreg () == regnum) | |
29639122 | 2449 | { |
098caef4 LM |
2450 | this_cache->saved_regs[regnum + 0 |
2451 | * gdbarch_num_regs (gdbarch)].set_addr (offset); | |
2452 | this_cache->saved_regs[regnum + 1 | |
2453 | * gdbarch_num_regs (gdbarch)].set_addr (offset); | |
29639122 | 2454 | } |
eec63939 AC |
2455 | } |
2456 | ||
eec63939 | 2457 | |
29639122 JB |
2458 | /* Fetch the immediate value from a MIPS16 instruction. |
2459 | If the previous instruction was an EXTEND, use it to extend | |
2460 | the upper bits of the immediate value. This is a helper function | |
2461 | for mips16_scan_prologue. */ | |
eec63939 | 2462 | |
29639122 JB |
2463 | static int |
2464 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ | |
2465 | unsigned short inst, /* current instruction */ | |
2466 | int nbits, /* number of bits in imm field */ | |
2467 | int scale, /* scale factor to be applied to imm */ | |
025bb325 | 2468 | int is_signed) /* is the imm field signed? */ |
eec63939 | 2469 | { |
29639122 | 2470 | int offset; |
eec63939 | 2471 | |
29639122 JB |
2472 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
2473 | { | |
2474 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
2475 | if (offset & 0x8000) /* check for negative extend */ | |
2476 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
2477 | return offset | (inst & 0x1f); | |
2478 | } | |
eec63939 | 2479 | else |
29639122 JB |
2480 | { |
2481 | int max_imm = 1 << nbits; | |
2482 | int mask = max_imm - 1; | |
2483 | int sign_bit = max_imm >> 1; | |
45c9dd44 | 2484 | |
29639122 JB |
2485 | offset = inst & mask; |
2486 | if (is_signed && (offset & sign_bit)) | |
2487 | offset = 0 - (max_imm - offset); | |
2488 | return offset * scale; | |
2489 | } | |
2490 | } | |
eec63939 | 2491 | |
65596487 | 2492 | |
29639122 JB |
2493 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
2494 | the associated FRAME_CACHE if not null. | |
2495 | Return the address of the first instruction past the prologue. */ | |
eec63939 | 2496 | |
29639122 | 2497 | static CORE_ADDR |
e17a4113 UW |
2498 | mips16_scan_prologue (struct gdbarch *gdbarch, |
2499 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
dda83cd7 SM |
2500 | struct frame_info *this_frame, |
2501 | struct mips_frame_cache *this_cache) | |
29639122 | 2502 | { |
ab50adb6 MR |
2503 | int prev_non_prologue_insn = 0; |
2504 | int this_non_prologue_insn; | |
2505 | int non_prologue_insns = 0; | |
2506 | CORE_ADDR prev_pc; | |
29639122 | 2507 | CORE_ADDR cur_pc; |
025bb325 | 2508 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer. */ |
29639122 JB |
2509 | CORE_ADDR sp; |
2510 | long frame_offset = 0; /* Size of stack frame. */ | |
2511 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
2512 | int frame_reg = MIPS_SP_REGNUM; | |
025bb325 | 2513 | unsigned short prev_inst = 0; /* saved copy of previous instruction. */ |
29639122 JB |
2514 | unsigned inst = 0; /* current instruction */ |
2515 | unsigned entry_inst = 0; /* the entry instruction */ | |
2207132d | 2516 | unsigned save_inst = 0; /* the save instruction */ |
ab50adb6 MR |
2517 | int prev_delay_slot = 0; |
2518 | int in_delay_slot; | |
29639122 | 2519 | int reg, offset; |
a343eb3c | 2520 | |
29639122 | 2521 | int extend_bytes = 0; |
ab50adb6 MR |
2522 | int prev_extend_bytes = 0; |
2523 | CORE_ADDR end_prologue_addr; | |
a343eb3c | 2524 | |
29639122 | 2525 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
2526 | THIS_FRAME. */ |
2527 | if (this_frame != NULL) | |
2528 | sp = get_frame_register_signed (this_frame, | |
2529 | gdbarch_num_regs (gdbarch) | |
2530 | + MIPS_SP_REGNUM); | |
29639122 JB |
2531 | else |
2532 | sp = 0; | |
eec63939 | 2533 | |
29639122 JB |
2534 | if (limit_pc > start_pc + 200) |
2535 | limit_pc = start_pc + 200; | |
ab50adb6 | 2536 | prev_pc = start_pc; |
eec63939 | 2537 | |
ab50adb6 MR |
2538 | /* Permit at most one non-prologue non-control-transfer instruction |
2539 | in the middle which may have been reordered by the compiler for | |
2540 | optimisation. */ | |
95ac2dcf | 2541 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) |
29639122 | 2542 | { |
ab50adb6 MR |
2543 | this_non_prologue_insn = 0; |
2544 | in_delay_slot = 0; | |
2545 | ||
29639122 | 2546 | /* Save the previous instruction. If it's an EXTEND, we'll extract |
dda83cd7 | 2547 | the immediate offset extension from it in mips16_get_imm. */ |
29639122 | 2548 | prev_inst = inst; |
eec63939 | 2549 | |
025bb325 | 2550 | /* Fetch and decode the instruction. */ |
4cc0665f MR |
2551 | inst = (unsigned short) mips_fetch_instruction (gdbarch, ISA_MIPS16, |
2552 | cur_pc, NULL); | |
eec63939 | 2553 | |
29639122 | 2554 | /* Normally we ignore extend instructions. However, if it is |
dda83cd7 SM |
2555 | not followed by a valid prologue instruction, then this |
2556 | instruction is not part of the prologue either. We must | |
2557 | remember in this case to adjust the end_prologue_addr back | |
2558 | over the extend. */ | |
29639122 | 2559 | if ((inst & 0xf800) == 0xf000) /* extend */ |
dda83cd7 SM |
2560 | { |
2561 | extend_bytes = MIPS_INSN16_SIZE; | |
2562 | continue; | |
2563 | } | |
eec63939 | 2564 | |
29639122 JB |
2565 | prev_extend_bytes = extend_bytes; |
2566 | extend_bytes = 0; | |
eec63939 | 2567 | |
29639122 JB |
2568 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
2569 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2570 | { | |
2571 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
025bb325 | 2572 | if (offset < 0) /* Negative stack adjustment? */ |
29639122 JB |
2573 | frame_offset -= offset; |
2574 | else | |
2575 | /* Exit loop if a positive stack adjustment is found, which | |
2576 | usually means that the stack cleanup code in the function | |
2577 | epilogue is reached. */ | |
2578 | break; | |
2579 | } | |
2580 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
2581 | { | |
2582 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
4cc0665f | 2583 | reg = mips_reg3_to_reg[(inst & 0x700) >> 8]; |
74ed0bb4 | 2584 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
2585 | } |
2586 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
2587 | { | |
2588 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
4cc0665f | 2589 | reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
74ed0bb4 | 2590 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
2591 | } |
2592 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
2593 | { | |
2594 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
74ed0bb4 | 2595 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
2596 | } |
2597 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
2598 | { | |
2599 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
74ed0bb4 | 2600 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
2601 | } |
2602 | else if (inst == 0x673d) /* move $s1, $sp */ | |
2603 | { | |
2604 | frame_addr = sp; | |
2605 | frame_reg = 17; | |
2606 | } | |
2607 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
2608 | { | |
2609 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2610 | frame_addr = sp + offset; | |
2611 | frame_reg = 17; | |
2612 | frame_adjust = offset; | |
2613 | } | |
2614 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
2615 | { | |
2616 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
4cc0665f | 2617 | reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
74ed0bb4 | 2618 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
2619 | } |
2620 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
2621 | { | |
2622 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
4cc0665f | 2623 | reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
74ed0bb4 | 2624 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
2625 | } |
2626 | else if ((inst & 0xf81f) == 0xe809 | |
dda83cd7 | 2627 | && (inst & 0x700) != 0x700) /* entry */ |
025bb325 | 2628 | entry_inst = inst; /* Save for later processing. */ |
2207132d MR |
2629 | else if ((inst & 0xff80) == 0x6480) /* save */ |
2630 | { | |
025bb325 | 2631 | save_inst = inst; /* Save for later processing. */ |
2207132d MR |
2632 | if (prev_extend_bytes) /* extend */ |
2633 | save_inst |= prev_inst << 16; | |
2634 | } | |
29639122 | 2635 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
dda83cd7 SM |
2636 | { |
2637 | /* This instruction is part of the prologue, but we don't | |
2638 | need to do anything special to handle it. */ | |
2639 | } | |
ab50adb6 MR |
2640 | else if (mips16_instruction_has_delay_slot (inst, 0)) |
2641 | /* JAL/JALR/JALX/JR */ | |
2642 | { | |
2643 | /* The instruction in the delay slot can be a part | |
2644 | of the prologue, so move forward once more. */ | |
2645 | in_delay_slot = 1; | |
2646 | if (mips16_instruction_has_delay_slot (inst, 1)) | |
2647 | /* JAL/JALX */ | |
2648 | { | |
2649 | prev_extend_bytes = MIPS_INSN16_SIZE; | |
2650 | cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ | |
2651 | } | |
2652 | } | |
29639122 | 2653 | else |
dda83cd7 | 2654 | { |
ab50adb6 | 2655 | this_non_prologue_insn = 1; |
dda83cd7 | 2656 | } |
ab50adb6 MR |
2657 | |
2658 | non_prologue_insns += this_non_prologue_insn; | |
2659 | ||
2660 | /* A jump or branch, or enough non-prologue insns seen? If so, | |
dda83cd7 | 2661 | then we must have reached the end of the prologue by now. */ |
ab50adb6 MR |
2662 | if (prev_delay_slot || non_prologue_insns > 1 |
2663 | || mips16_instruction_is_compact_branch (inst)) | |
2664 | break; | |
2665 | ||
2666 | prev_non_prologue_insn = this_non_prologue_insn; | |
2667 | prev_delay_slot = in_delay_slot; | |
2668 | prev_pc = cur_pc - prev_extend_bytes; | |
29639122 | 2669 | } |
eec63939 | 2670 | |
29639122 JB |
2671 | /* The entry instruction is typically the first instruction in a function, |
2672 | and it stores registers at offsets relative to the value of the old SP | |
2673 | (before the prologue). But the value of the sp parameter to this | |
2674 | function is the new SP (after the prologue has been executed). So we | |
2675 | can't calculate those offsets until we've seen the entire prologue, | |
025bb325 | 2676 | and can calculate what the old SP must have been. */ |
29639122 JB |
2677 | if (entry_inst != 0) |
2678 | { | |
2679 | int areg_count = (entry_inst >> 8) & 7; | |
2680 | int sreg_count = (entry_inst >> 6) & 3; | |
eec63939 | 2681 | |
29639122 JB |
2682 | /* The entry instruction always subtracts 32 from the SP. */ |
2683 | frame_offset += 32; | |
2684 | ||
2685 | /* Now we can calculate what the SP must have been at the | |
dda83cd7 | 2686 | start of the function prologue. */ |
29639122 JB |
2687 | sp += frame_offset; |
2688 | ||
2689 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
2690 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
2691 | { | |
74ed0bb4 | 2692 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 2693 | offset += mips_abi_regsize (gdbarch); |
29639122 JB |
2694 | } |
2695 | ||
2696 | /* Check if the ra register was pushed on the stack. */ | |
2697 | offset = -4; | |
2698 | if (entry_inst & 0x20) | |
2699 | { | |
74ed0bb4 | 2700 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
72a155b4 | 2701 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
2702 | } |
2703 | ||
2704 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
2705 | for (reg = 16; reg < sreg_count + 16; reg++) | |
2706 | { | |
74ed0bb4 | 2707 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 2708 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
2709 | } |
2710 | } | |
2711 | ||
2207132d MR |
2712 | /* The SAVE instruction is similar to ENTRY, except that defined by the |
2713 | MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the | |
2714 | size of the frame is specified as an immediate field of instruction | |
2715 | and an extended variation exists which lets additional registers and | |
2716 | frame space to be specified. The instruction always treats registers | |
2717 | as 32-bit so its usefulness for 64-bit ABIs is questionable. */ | |
2718 | if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4) | |
2719 | { | |
2720 | static int args_table[16] = { | |
2721 | 0, 0, 0, 0, 1, 1, 1, 1, | |
2722 | 2, 2, 2, 0, 3, 3, 4, -1, | |
2723 | }; | |
2724 | static int astatic_table[16] = { | |
2725 | 0, 1, 2, 3, 0, 1, 2, 3, | |
2726 | 0, 1, 2, 4, 0, 1, 0, -1, | |
2727 | }; | |
2728 | int aregs = (save_inst >> 16) & 0xf; | |
2729 | int xsregs = (save_inst >> 24) & 0x7; | |
2730 | int args = args_table[aregs]; | |
2731 | int astatic = astatic_table[aregs]; | |
2732 | long frame_size; | |
2733 | ||
2734 | if (args < 0) | |
2735 | { | |
2736 | warning (_("Invalid number of argument registers encoded in SAVE.")); | |
2737 | args = 0; | |
2738 | } | |
2739 | if (astatic < 0) | |
2740 | { | |
2741 | warning (_("Invalid number of static registers encoded in SAVE.")); | |
2742 | astatic = 0; | |
2743 | } | |
2744 | ||
2745 | /* For standard SAVE the frame size of 0 means 128. */ | |
2746 | frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf); | |
2747 | if (frame_size == 0 && (save_inst >> 16) == 0) | |
2748 | frame_size = 16; | |
2749 | frame_size *= 8; | |
2750 | frame_offset += frame_size; | |
2751 | ||
2752 | /* Now we can calculate what the SP must have been at the | |
dda83cd7 | 2753 | start of the function prologue. */ |
2207132d MR |
2754 | sp += frame_offset; |
2755 | ||
2756 | /* Check if A0-A3 were saved in the caller's argument save area. */ | |
2757 | for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++) | |
2758 | { | |
74ed0bb4 | 2759 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
2760 | offset += mips_abi_regsize (gdbarch); |
2761 | } | |
2762 | ||
2763 | offset = -4; | |
2764 | ||
2765 | /* Check if the RA register was pushed on the stack. */ | |
2766 | if (save_inst & 0x40) | |
2767 | { | |
74ed0bb4 | 2768 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
2207132d MR |
2769 | offset -= mips_abi_regsize (gdbarch); |
2770 | } | |
2771 | ||
2772 | /* Check if the S8 register was pushed on the stack. */ | |
2773 | if (xsregs > 6) | |
2774 | { | |
74ed0bb4 | 2775 | set_reg_offset (gdbarch, this_cache, 30, sp + offset); |
2207132d MR |
2776 | offset -= mips_abi_regsize (gdbarch); |
2777 | xsregs--; | |
2778 | } | |
2779 | /* Check if S2-S7 were pushed on the stack. */ | |
2780 | for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--) | |
2781 | { | |
74ed0bb4 | 2782 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
2783 | offset -= mips_abi_regsize (gdbarch); |
2784 | } | |
2785 | ||
2786 | /* Check if the S1 register was pushed on the stack. */ | |
2787 | if (save_inst & 0x10) | |
2788 | { | |
74ed0bb4 | 2789 | set_reg_offset (gdbarch, this_cache, 17, sp + offset); |
2207132d MR |
2790 | offset -= mips_abi_regsize (gdbarch); |
2791 | } | |
2792 | /* Check if the S0 register was pushed on the stack. */ | |
2793 | if (save_inst & 0x20) | |
2794 | { | |
74ed0bb4 | 2795 | set_reg_offset (gdbarch, this_cache, 16, sp + offset); |
2207132d MR |
2796 | offset -= mips_abi_regsize (gdbarch); |
2797 | } | |
2798 | ||
4cc0665f MR |
2799 | /* Check if A0-A3 were pushed on the stack. */ |
2800 | for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--) | |
2801 | { | |
2802 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); | |
2803 | offset -= mips_abi_regsize (gdbarch); | |
2804 | } | |
2805 | } | |
2806 | ||
2807 | if (this_cache != NULL) | |
2808 | { | |
2809 | this_cache->base = | |
dda83cd7 | 2810 | (get_frame_register_signed (this_frame, |
4cc0665f | 2811 | gdbarch_num_regs (gdbarch) + frame_reg) |
dda83cd7 | 2812 | + frame_offset - frame_adjust); |
4cc0665f | 2813 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should |
dda83cd7 SM |
2814 | be able to get rid of the assignment below, evetually. But it's |
2815 | still needed for now. */ | |
4cc0665f MR |
2816 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
2817 | + mips_regnum (gdbarch)->pc] | |
dda83cd7 | 2818 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; |
4cc0665f MR |
2819 | } |
2820 | ||
ab50adb6 MR |
2821 | /* Set end_prologue_addr to the address of the instruction immediately |
2822 | after the last one we scanned. Unless the last one looked like a | |
2823 | non-prologue instruction (and we looked ahead), in which case use | |
2824 | its address instead. */ | |
2825 | end_prologue_addr = (prev_non_prologue_insn || prev_delay_slot | |
2826 | ? prev_pc : cur_pc - prev_extend_bytes); | |
4cc0665f MR |
2827 | |
2828 | return end_prologue_addr; | |
2829 | } | |
2830 | ||
2831 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). | |
2832 | Procedures that use the 32-bit instruction set are handled by the | |
2833 | mips_insn32 unwinder. */ | |
2834 | ||
2835 | static struct mips_frame_cache * | |
2836 | mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache) | |
2837 | { | |
2838 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2839 | struct mips_frame_cache *cache; | |
2840 | ||
2841 | if ((*this_cache) != NULL) | |
19ba03f4 | 2842 | return (struct mips_frame_cache *) (*this_cache); |
4cc0665f MR |
2843 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
2844 | (*this_cache) = cache; | |
2845 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
2846 | ||
2847 | /* Analyze the function prologue. */ | |
2848 | { | |
2849 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); | |
2850 | CORE_ADDR start_addr; | |
2851 | ||
2852 | find_pc_partial_function (pc, NULL, &start_addr, NULL); | |
2853 | if (start_addr == 0) | |
2854 | start_addr = heuristic_proc_start (gdbarch, pc); | |
2855 | /* We can't analyze the prologue if we couldn't find the begining | |
2856 | of the function. */ | |
2857 | if (start_addr == 0) | |
2858 | return cache; | |
2859 | ||
19ba03f4 SM |
2860 | mips16_scan_prologue (gdbarch, start_addr, pc, this_frame, |
2861 | (struct mips_frame_cache *) *this_cache); | |
4cc0665f MR |
2862 | } |
2863 | ||
2864 | /* gdbarch_sp_regnum contains the value and not the address. */ | |
a9a87d35 LM |
2865 | cache->saved_regs[gdbarch_num_regs (gdbarch) |
2866 | + MIPS_SP_REGNUM].set_value (cache->base); | |
4cc0665f | 2867 | |
19ba03f4 | 2868 | return (struct mips_frame_cache *) (*this_cache); |
4cc0665f MR |
2869 | } |
2870 | ||
2871 | static void | |
2872 | mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache, | |
2873 | struct frame_id *this_id) | |
2874 | { | |
2875 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, | |
2876 | this_cache); | |
2877 | /* This marks the outermost frame. */ | |
2878 | if (info->base == 0) | |
2879 | return; | |
2880 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); | |
2881 | } | |
2882 | ||
2883 | static struct value * | |
2884 | mips_insn16_frame_prev_register (struct frame_info *this_frame, | |
2885 | void **this_cache, int regnum) | |
2886 | { | |
2887 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, | |
2888 | this_cache); | |
2889 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); | |
2890 | } | |
2891 | ||
2892 | static int | |
2893 | mips_insn16_frame_sniffer (const struct frame_unwind *self, | |
2894 | struct frame_info *this_frame, void **this_cache) | |
2895 | { | |
2896 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2897 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2898 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
2899 | return 1; | |
2900 | return 0; | |
2901 | } | |
2902 | ||
2903 | static const struct frame_unwind mips_insn16_frame_unwind = | |
2904 | { | |
2905 | NORMAL_FRAME, | |
2906 | default_frame_unwind_stop_reason, | |
2907 | mips_insn16_frame_this_id, | |
2908 | mips_insn16_frame_prev_register, | |
2909 | NULL, | |
2910 | mips_insn16_frame_sniffer | |
2911 | }; | |
2912 | ||
2913 | static CORE_ADDR | |
2914 | mips_insn16_frame_base_address (struct frame_info *this_frame, | |
2915 | void **this_cache) | |
2916 | { | |
2917 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, | |
2918 | this_cache); | |
2919 | return info->base; | |
2920 | } | |
2921 | ||
2922 | static const struct frame_base mips_insn16_frame_base = | |
2923 | { | |
2924 | &mips_insn16_frame_unwind, | |
2925 | mips_insn16_frame_base_address, | |
2926 | mips_insn16_frame_base_address, | |
2927 | mips_insn16_frame_base_address | |
2928 | }; | |
2929 | ||
2930 | static const struct frame_base * | |
2931 | mips_insn16_frame_base_sniffer (struct frame_info *this_frame) | |
2932 | { | |
2933 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2934 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2935 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
2936 | return &mips_insn16_frame_base; | |
2937 | else | |
2938 | return NULL; | |
2939 | } | |
2940 | ||
2941 | /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped | |
2942 | to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are | |
2943 | interpreted directly, and then multiplied by 4. */ | |
2944 | ||
2945 | static int | |
2946 | micromips_decode_imm9 (int imm) | |
2947 | { | |
2948 | imm = (imm ^ 0x100) - 0x100; | |
2949 | if (imm > -3 && imm < 2) | |
2950 | imm ^= 0x100; | |
2951 | return imm << 2; | |
2952 | } | |
2953 | ||
2954 | /* Analyze the function prologue from START_PC to LIMIT_PC. Return | |
2955 | the address of the first instruction past the prologue. */ | |
2956 | ||
2957 | static CORE_ADDR | |
2958 | micromips_scan_prologue (struct gdbarch *gdbarch, | |
2959 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
2960 | struct frame_info *this_frame, | |
2961 | struct mips_frame_cache *this_cache) | |
2962 | { | |
ab50adb6 | 2963 | CORE_ADDR end_prologue_addr; |
4cc0665f MR |
2964 | int prev_non_prologue_insn = 0; |
2965 | int frame_reg = MIPS_SP_REGNUM; | |
2966 | int this_non_prologue_insn; | |
2967 | int non_prologue_insns = 0; | |
2968 | long frame_offset = 0; /* Size of stack frame. */ | |
2969 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
ab50adb6 MR |
2970 | int prev_delay_slot = 0; |
2971 | int in_delay_slot; | |
4cc0665f MR |
2972 | CORE_ADDR prev_pc; |
2973 | CORE_ADDR cur_pc; | |
2974 | ULONGEST insn; /* current instruction */ | |
2975 | CORE_ADDR sp; | |
2976 | long offset; | |
2977 | long sp_adj; | |
2978 | long v1_off = 0; /* The assumption is LUI will replace it. */ | |
2979 | int reglist; | |
2980 | int breg; | |
2981 | int dreg; | |
2982 | int sreg; | |
2983 | int treg; | |
2984 | int loc; | |
2985 | int op; | |
2986 | int s; | |
2987 | int i; | |
2988 | ||
2989 | /* Can be called when there's no process, and hence when there's no | |
2990 | THIS_FRAME. */ | |
2991 | if (this_frame != NULL) | |
2992 | sp = get_frame_register_signed (this_frame, | |
2993 | gdbarch_num_regs (gdbarch) | |
2994 | + MIPS_SP_REGNUM); | |
2995 | else | |
2996 | sp = 0; | |
2997 | ||
2998 | if (limit_pc > start_pc + 200) | |
2999 | limit_pc = start_pc + 200; | |
3000 | prev_pc = start_pc; | |
3001 | ||
3002 | /* Permit at most one non-prologue non-control-transfer instruction | |
3003 | in the middle which may have been reordered by the compiler for | |
3004 | optimisation. */ | |
3005 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += loc) | |
3006 | { | |
3007 | this_non_prologue_insn = 0; | |
ab50adb6 | 3008 | in_delay_slot = 0; |
4cc0665f MR |
3009 | sp_adj = 0; |
3010 | loc = 0; | |
3011 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, cur_pc, NULL); | |
3012 | loc += MIPS_INSN16_SIZE; | |
3013 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
3014 | { | |
4cc0665f MR |
3015 | /* 32-bit instructions. */ |
3016 | case 2 * MIPS_INSN16_SIZE: | |
3017 | insn <<= 16; | |
3018 | insn |= mips_fetch_instruction (gdbarch, | |
3019 | ISA_MICROMIPS, cur_pc + loc, NULL); | |
3020 | loc += MIPS_INSN16_SIZE; | |
3021 | switch (micromips_op (insn >> 16)) | |
3022 | { | |
3023 | /* Record $sp/$fp adjustment. */ | |
3024 | /* Discard (D)ADDU $gp,$jp used for PIC code. */ | |
3025 | case 0x0: /* POOL32A: bits 000000 */ | |
3026 | case 0x16: /* POOL32S: bits 010110 */ | |
3027 | op = b0s11_op (insn); | |
3028 | sreg = b0s5_reg (insn >> 16); | |
3029 | treg = b5s5_reg (insn >> 16); | |
3030 | dreg = b11s5_reg (insn); | |
3031 | if (op == 0x1d0 | |
3032 | /* SUBU: bits 000000 00111010000 */ | |
3033 | /* DSUBU: bits 010110 00111010000 */ | |
3034 | && dreg == MIPS_SP_REGNUM && sreg == MIPS_SP_REGNUM | |
3035 | && treg == 3) | |
3036 | /* (D)SUBU $sp, $v1 */ | |
3037 | sp_adj = v1_off; | |
3038 | else if (op != 0x150 | |
3039 | /* ADDU: bits 000000 00101010000 */ | |
3040 | /* DADDU: bits 010110 00101010000 */ | |
3041 | || dreg != 28 || sreg != 28 || treg != MIPS_T9_REGNUM) | |
3042 | this_non_prologue_insn = 1; | |
3043 | break; | |
3044 | ||
3045 | case 0x8: /* POOL32B: bits 001000 */ | |
3046 | op = b12s4_op (insn); | |
3047 | breg = b0s5_reg (insn >> 16); | |
3048 | reglist = sreg = b5s5_reg (insn >> 16); | |
3049 | offset = (b0s12_imm (insn) ^ 0x800) - 0x800; | |
3050 | if ((op == 0x9 || op == 0xc) | |
3051 | /* SWP: bits 001000 1001 */ | |
3052 | /* SDP: bits 001000 1100 */ | |
3053 | && breg == MIPS_SP_REGNUM && sreg < MIPS_RA_REGNUM) | |
3054 | /* S[DW]P reg,offset($sp) */ | |
3055 | { | |
3056 | s = 4 << ((b12s4_op (insn) & 0x4) == 0x4); | |
3057 | set_reg_offset (gdbarch, this_cache, | |
3058 | sreg, sp + offset); | |
3059 | set_reg_offset (gdbarch, this_cache, | |
3060 | sreg + 1, sp + offset + s); | |
3061 | } | |
3062 | else if ((op == 0xd || op == 0xf) | |
3063 | /* SWM: bits 001000 1101 */ | |
3064 | /* SDM: bits 001000 1111 */ | |
3065 | && breg == MIPS_SP_REGNUM | |
3066 | /* SWM reglist,offset($sp) */ | |
3067 | && ((reglist >= 1 && reglist <= 9) | |
3068 | || (reglist >= 16 && reglist <= 25))) | |
3069 | { | |
325fac50 | 3070 | int sreglist = std::min(reglist & 0xf, 8); |
4cc0665f MR |
3071 | |
3072 | s = 4 << ((b12s4_op (insn) & 0x2) == 0x2); | |
3073 | for (i = 0; i < sreglist; i++) | |
3074 | set_reg_offset (gdbarch, this_cache, 16 + i, sp + s * i); | |
3075 | if ((reglist & 0xf) > 8) | |
3076 | set_reg_offset (gdbarch, this_cache, 30, sp + s * i++); | |
3077 | if ((reglist & 0x10) == 0x10) | |
3078 | set_reg_offset (gdbarch, this_cache, | |
3079 | MIPS_RA_REGNUM, sp + s * i++); | |
3080 | } | |
3081 | else | |
3082 | this_non_prologue_insn = 1; | |
3083 | break; | |
3084 | ||
3085 | /* Record $sp/$fp adjustment. */ | |
3086 | /* Discard (D)ADDIU $gp used for PIC code. */ | |
3087 | case 0xc: /* ADDIU: bits 001100 */ | |
3088 | case 0x17: /* DADDIU: bits 010111 */ | |
3089 | sreg = b0s5_reg (insn >> 16); | |
3090 | dreg = b5s5_reg (insn >> 16); | |
3091 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
3092 | if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM) | |
3093 | /* (D)ADDIU $sp, imm */ | |
3094 | sp_adj = offset; | |
3095 | else if (sreg == MIPS_SP_REGNUM && dreg == 30) | |
3096 | /* (D)ADDIU $fp, $sp, imm */ | |
3097 | { | |
4cc0665f MR |
3098 | frame_adjust = offset; |
3099 | frame_reg = 30; | |
3100 | } | |
3101 | else if (sreg != 28 || dreg != 28) | |
3102 | /* (D)ADDIU $gp, imm */ | |
3103 | this_non_prologue_insn = 1; | |
3104 | break; | |
3105 | ||
3106 | /* LUI $v1 is used for larger $sp adjustments. */ | |
3356937a | 3107 | /* Discard LUI $gp used for PIC code. */ |
4cc0665f MR |
3108 | case 0x10: /* POOL32I: bits 010000 */ |
3109 | if (b5s5_op (insn >> 16) == 0xd | |
3110 | /* LUI: bits 010000 001101 */ | |
3111 | && b0s5_reg (insn >> 16) == 3) | |
3112 | /* LUI $v1, imm */ | |
3113 | v1_off = ((b0s16_imm (insn) << 16) ^ 0x80000000) - 0x80000000; | |
3114 | else if (b5s5_op (insn >> 16) != 0xd | |
3115 | /* LUI: bits 010000 001101 */ | |
3116 | || b0s5_reg (insn >> 16) != 28) | |
3117 | /* LUI $gp, imm */ | |
3118 | this_non_prologue_insn = 1; | |
3119 | break; | |
3120 | ||
3121 | /* ORI $v1 is used for larger $sp adjustments. */ | |
3122 | case 0x14: /* ORI: bits 010100 */ | |
3123 | sreg = b0s5_reg (insn >> 16); | |
3124 | dreg = b5s5_reg (insn >> 16); | |
3125 | if (sreg == 3 && dreg == 3) | |
3126 | /* ORI $v1, imm */ | |
3127 | v1_off |= b0s16_imm (insn); | |
3128 | else | |
3129 | this_non_prologue_insn = 1; | |
3130 | break; | |
3131 | ||
3132 | case 0x26: /* SWC1: bits 100110 */ | |
3133 | case 0x2e: /* SDC1: bits 101110 */ | |
3134 | breg = b0s5_reg (insn >> 16); | |
3135 | if (breg != MIPS_SP_REGNUM) | |
3136 | /* S[DW]C1 reg,offset($sp) */ | |
3137 | this_non_prologue_insn = 1; | |
3138 | break; | |
3139 | ||
3140 | case 0x36: /* SD: bits 110110 */ | |
3141 | case 0x3e: /* SW: bits 111110 */ | |
3142 | breg = b0s5_reg (insn >> 16); | |
3143 | sreg = b5s5_reg (insn >> 16); | |
3144 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
3145 | if (breg == MIPS_SP_REGNUM) | |
3146 | /* S[DW] reg,offset($sp) */ | |
3147 | set_reg_offset (gdbarch, this_cache, sreg, sp + offset); | |
3148 | else | |
3149 | this_non_prologue_insn = 1; | |
3150 | break; | |
3151 | ||
3152 | default: | |
ab50adb6 | 3153 | /* The instruction in the delay slot can be a part |
dda83cd7 | 3154 | of the prologue, so move forward once more. */ |
ab50adb6 MR |
3155 | if (micromips_instruction_has_delay_slot (insn, 0)) |
3156 | in_delay_slot = 1; | |
3157 | else | |
3158 | this_non_prologue_insn = 1; | |
4cc0665f MR |
3159 | break; |
3160 | } | |
ab50adb6 | 3161 | insn >>= 16; |
4cc0665f MR |
3162 | break; |
3163 | ||
3164 | /* 16-bit instructions. */ | |
3165 | case MIPS_INSN16_SIZE: | |
3166 | switch (micromips_op (insn)) | |
3167 | { | |
3168 | case 0x3: /* MOVE: bits 000011 */ | |
3169 | sreg = b0s5_reg (insn); | |
3170 | dreg = b5s5_reg (insn); | |
3171 | if (sreg == MIPS_SP_REGNUM && dreg == 30) | |
3172 | /* MOVE $fp, $sp */ | |
78cc6c2d | 3173 | frame_reg = 30; |
4cc0665f MR |
3174 | else if ((sreg & 0x1c) != 0x4) |
3175 | /* MOVE reg, $a0-$a3 */ | |
3176 | this_non_prologue_insn = 1; | |
3177 | break; | |
3178 | ||
3179 | case 0x11: /* POOL16C: bits 010001 */ | |
3180 | if (b6s4_op (insn) == 0x5) | |
3181 | /* SWM: bits 010001 0101 */ | |
3182 | { | |
3183 | offset = ((b0s4_imm (insn) << 2) ^ 0x20) - 0x20; | |
3184 | reglist = b4s2_regl (insn); | |
3185 | for (i = 0; i <= reglist; i++) | |
3186 | set_reg_offset (gdbarch, this_cache, 16 + i, sp + 4 * i); | |
3187 | set_reg_offset (gdbarch, this_cache, | |
3188 | MIPS_RA_REGNUM, sp + 4 * i++); | |
3189 | } | |
3190 | else | |
3191 | this_non_prologue_insn = 1; | |
3192 | break; | |
3193 | ||
3194 | case 0x13: /* POOL16D: bits 010011 */ | |
3195 | if ((insn & 0x1) == 0x1) | |
3196 | /* ADDIUSP: bits 010011 1 */ | |
3197 | sp_adj = micromips_decode_imm9 (b1s9_imm (insn)); | |
3198 | else if (b5s5_reg (insn) == MIPS_SP_REGNUM) | |
3199 | /* ADDIUS5: bits 010011 0 */ | |
3200 | /* ADDIUS5 $sp, imm */ | |
3201 | sp_adj = (b1s4_imm (insn) ^ 8) - 8; | |
3202 | else | |
3203 | this_non_prologue_insn = 1; | |
3204 | break; | |
3205 | ||
3206 | case 0x32: /* SWSP: bits 110010 */ | |
3207 | offset = b0s5_imm (insn) << 2; | |
3208 | sreg = b5s5_reg (insn); | |
3209 | set_reg_offset (gdbarch, this_cache, sreg, sp + offset); | |
3210 | break; | |
3211 | ||
3212 | default: | |
ab50adb6 | 3213 | /* The instruction in the delay slot can be a part |
dda83cd7 | 3214 | of the prologue, so move forward once more. */ |
ab50adb6 MR |
3215 | if (micromips_instruction_has_delay_slot (insn << 16, 0)) |
3216 | in_delay_slot = 1; | |
3217 | else | |
3218 | this_non_prologue_insn = 1; | |
4cc0665f MR |
3219 | break; |
3220 | } | |
3221 | break; | |
3222 | } | |
3223 | if (sp_adj < 0) | |
3224 | frame_offset -= sp_adj; | |
3225 | ||
3226 | non_prologue_insns += this_non_prologue_insn; | |
ab50adb6 MR |
3227 | |
3228 | /* A jump or branch, enough non-prologue insns seen or positive | |
dda83cd7 SM |
3229 | stack adjustment? If so, then we must have reached the end |
3230 | of the prologue by now. */ | |
ab50adb6 MR |
3231 | if (prev_delay_slot || non_prologue_insns > 1 || sp_adj > 0 |
3232 | || micromips_instruction_is_compact_branch (insn)) | |
3233 | break; | |
3234 | ||
4cc0665f | 3235 | prev_non_prologue_insn = this_non_prologue_insn; |
ab50adb6 | 3236 | prev_delay_slot = in_delay_slot; |
4cc0665f | 3237 | prev_pc = cur_pc; |
2207132d MR |
3238 | } |
3239 | ||
29639122 JB |
3240 | if (this_cache != NULL) |
3241 | { | |
3242 | this_cache->base = | |
4cc0665f | 3243 | (get_frame_register_signed (this_frame, |
b8a22b94 | 3244 | gdbarch_num_regs (gdbarch) + frame_reg) |
4cc0665f | 3245 | + frame_offset - frame_adjust); |
29639122 | 3246 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should |
4cc0665f MR |
3247 | be able to get rid of the assignment below, evetually. But it's |
3248 | still needed for now. */ | |
72a155b4 UW |
3249 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
3250 | + mips_regnum (gdbarch)->pc] | |
4cc0665f | 3251 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; |
29639122 JB |
3252 | } |
3253 | ||
ab50adb6 MR |
3254 | /* Set end_prologue_addr to the address of the instruction immediately |
3255 | after the last one we scanned. Unless the last one looked like a | |
3256 | non-prologue instruction (and we looked ahead), in which case use | |
3257 | its address instead. */ | |
3258 | end_prologue_addr | |
3259 | = prev_non_prologue_insn || prev_delay_slot ? prev_pc : cur_pc; | |
29639122 JB |
3260 | |
3261 | return end_prologue_addr; | |
eec63939 AC |
3262 | } |
3263 | ||
4cc0665f | 3264 | /* Heuristic unwinder for procedures using microMIPS instructions. |
29639122 | 3265 | Procedures that use the 32-bit instruction set are handled by the |
4cc0665f | 3266 | mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */ |
29639122 JB |
3267 | |
3268 | static struct mips_frame_cache * | |
4cc0665f | 3269 | mips_micro_frame_cache (struct frame_info *this_frame, void **this_cache) |
eec63939 | 3270 | { |
e17a4113 | 3271 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 3272 | struct mips_frame_cache *cache; |
eec63939 AC |
3273 | |
3274 | if ((*this_cache) != NULL) | |
19ba03f4 | 3275 | return (struct mips_frame_cache *) (*this_cache); |
4cc0665f | 3276 | |
29639122 JB |
3277 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
3278 | (*this_cache) = cache; | |
b8a22b94 | 3279 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
eec63939 | 3280 | |
29639122 JB |
3281 | /* Analyze the function prologue. */ |
3282 | { | |
b8a22b94 | 3283 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 3284 | CORE_ADDR start_addr; |
eec63939 | 3285 | |
29639122 JB |
3286 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
3287 | if (start_addr == 0) | |
4cc0665f | 3288 | start_addr = heuristic_proc_start (get_frame_arch (this_frame), pc); |
29639122 JB |
3289 | /* We can't analyze the prologue if we couldn't find the begining |
3290 | of the function. */ | |
3291 | if (start_addr == 0) | |
3292 | return cache; | |
eec63939 | 3293 | |
19ba03f4 SM |
3294 | micromips_scan_prologue (gdbarch, start_addr, pc, this_frame, |
3295 | (struct mips_frame_cache *) *this_cache); | |
29639122 | 3296 | } |
4cc0665f | 3297 | |
3e8c568d | 3298 | /* gdbarch_sp_regnum contains the value and not the address. */ |
a9a87d35 LM |
3299 | cache->saved_regs[gdbarch_num_regs (gdbarch) |
3300 | + MIPS_SP_REGNUM].set_value (cache->base); | |
eec63939 | 3301 | |
19ba03f4 | 3302 | return (struct mips_frame_cache *) (*this_cache); |
eec63939 AC |
3303 | } |
3304 | ||
3305 | static void | |
4cc0665f MR |
3306 | mips_micro_frame_this_id (struct frame_info *this_frame, void **this_cache, |
3307 | struct frame_id *this_id) | |
eec63939 | 3308 | { |
4cc0665f MR |
3309 | struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
3310 | this_cache); | |
21327321 DJ |
3311 | /* This marks the outermost frame. */ |
3312 | if (info->base == 0) | |
3313 | return; | |
b8a22b94 | 3314 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
eec63939 AC |
3315 | } |
3316 | ||
b8a22b94 | 3317 | static struct value * |
4cc0665f MR |
3318 | mips_micro_frame_prev_register (struct frame_info *this_frame, |
3319 | void **this_cache, int regnum) | |
eec63939 | 3320 | { |
4cc0665f MR |
3321 | struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
3322 | this_cache); | |
b8a22b94 DJ |
3323 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
3324 | } | |
3325 | ||
3326 | static int | |
4cc0665f MR |
3327 | mips_micro_frame_sniffer (const struct frame_unwind *self, |
3328 | struct frame_info *this_frame, void **this_cache) | |
b8a22b94 | 3329 | { |
4cc0665f | 3330 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
b8a22b94 | 3331 | CORE_ADDR pc = get_frame_pc (this_frame); |
4cc0665f MR |
3332 | |
3333 | if (mips_pc_is_micromips (gdbarch, pc)) | |
b8a22b94 DJ |
3334 | return 1; |
3335 | return 0; | |
eec63939 AC |
3336 | } |
3337 | ||
4cc0665f | 3338 | static const struct frame_unwind mips_micro_frame_unwind = |
eec63939 AC |
3339 | { |
3340 | NORMAL_FRAME, | |
8fbca658 | 3341 | default_frame_unwind_stop_reason, |
4cc0665f MR |
3342 | mips_micro_frame_this_id, |
3343 | mips_micro_frame_prev_register, | |
b8a22b94 | 3344 | NULL, |
4cc0665f | 3345 | mips_micro_frame_sniffer |
eec63939 AC |
3346 | }; |
3347 | ||
eec63939 | 3348 | static CORE_ADDR |
4cc0665f MR |
3349 | mips_micro_frame_base_address (struct frame_info *this_frame, |
3350 | void **this_cache) | |
eec63939 | 3351 | { |
4cc0665f MR |
3352 | struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
3353 | this_cache); | |
29639122 | 3354 | return info->base; |
eec63939 AC |
3355 | } |
3356 | ||
4cc0665f | 3357 | static const struct frame_base mips_micro_frame_base = |
eec63939 | 3358 | { |
4cc0665f MR |
3359 | &mips_micro_frame_unwind, |
3360 | mips_micro_frame_base_address, | |
3361 | mips_micro_frame_base_address, | |
3362 | mips_micro_frame_base_address | |
eec63939 AC |
3363 | }; |
3364 | ||
3365 | static const struct frame_base * | |
4cc0665f | 3366 | mips_micro_frame_base_sniffer (struct frame_info *this_frame) |
eec63939 | 3367 | { |
4cc0665f | 3368 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
b8a22b94 | 3369 | CORE_ADDR pc = get_frame_pc (this_frame); |
4cc0665f MR |
3370 | |
3371 | if (mips_pc_is_micromips (gdbarch, pc)) | |
3372 | return &mips_micro_frame_base; | |
eec63939 AC |
3373 | else |
3374 | return NULL; | |
edfae063 AC |
3375 | } |
3376 | ||
29639122 JB |
3377 | /* Mark all the registers as unset in the saved_regs array |
3378 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
3379 | ||
74ed0bb4 MD |
3380 | static void |
3381 | reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache) | |
c906108c | 3382 | { |
29639122 JB |
3383 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
3384 | return; | |
3385 | ||
3386 | { | |
74ed0bb4 | 3387 | const int num_regs = gdbarch_num_regs (gdbarch); |
29639122 | 3388 | int i; |
64159455 | 3389 | |
a9a87d35 LM |
3390 | /* Reset the register values to their default state. Register i's value |
3391 | is in register i. */ | |
29639122 | 3392 | for (i = 0; i < num_regs; i++) |
a9a87d35 | 3393 | this_cache->saved_regs[i].set_realreg (i); |
29639122 | 3394 | } |
c906108c SS |
3395 | } |
3396 | ||
025bb325 | 3397 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
29639122 JB |
3398 | the associated FRAME_CACHE if not null. |
3399 | Return the address of the first instruction past the prologue. */ | |
c906108c | 3400 | |
875e1767 | 3401 | static CORE_ADDR |
e17a4113 UW |
3402 | mips32_scan_prologue (struct gdbarch *gdbarch, |
3403 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
dda83cd7 SM |
3404 | struct frame_info *this_frame, |
3405 | struct mips_frame_cache *this_cache) | |
c906108c | 3406 | { |
ab50adb6 MR |
3407 | int prev_non_prologue_insn; |
3408 | int this_non_prologue_insn; | |
3409 | int non_prologue_insns; | |
025bb325 MS |
3410 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for |
3411 | frame-pointer. */ | |
ab50adb6 MR |
3412 | int prev_delay_slot; |
3413 | CORE_ADDR prev_pc; | |
3414 | CORE_ADDR cur_pc; | |
29639122 JB |
3415 | CORE_ADDR sp; |
3416 | long frame_offset; | |
3417 | int frame_reg = MIPS_SP_REGNUM; | |
8fa9cfa1 | 3418 | |
ab50adb6 | 3419 | CORE_ADDR end_prologue_addr; |
29639122 JB |
3420 | int seen_sp_adjust = 0; |
3421 | int load_immediate_bytes = 0; | |
ab50adb6 | 3422 | int in_delay_slot; |
7d1e6fb8 | 3423 | int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8); |
8fa9cfa1 | 3424 | |
29639122 | 3425 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
3426 | THIS_FRAME. */ |
3427 | if (this_frame != NULL) | |
3428 | sp = get_frame_register_signed (this_frame, | |
3429 | gdbarch_num_regs (gdbarch) | |
3430 | + MIPS_SP_REGNUM); | |
8fa9cfa1 | 3431 | else |
29639122 | 3432 | sp = 0; |
9022177c | 3433 | |
29639122 JB |
3434 | if (limit_pc > start_pc + 200) |
3435 | limit_pc = start_pc + 200; | |
9022177c | 3436 | |
29639122 | 3437 | restart: |
ab50adb6 MR |
3438 | prev_non_prologue_insn = 0; |
3439 | non_prologue_insns = 0; | |
3440 | prev_delay_slot = 0; | |
3441 | prev_pc = start_pc; | |
9022177c | 3442 | |
ab50adb6 MR |
3443 | /* Permit at most one non-prologue non-control-transfer instruction |
3444 | in the middle which may have been reordered by the compiler for | |
3445 | optimisation. */ | |
29639122 | 3446 | frame_offset = 0; |
95ac2dcf | 3447 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) |
9022177c | 3448 | { |
eaa6a9a4 MR |
3449 | unsigned long inst, high_word; |
3450 | long offset; | |
29639122 | 3451 | int reg; |
9022177c | 3452 | |
ab50adb6 MR |
3453 | this_non_prologue_insn = 0; |
3454 | in_delay_slot = 0; | |
3455 | ||
025bb325 | 3456 | /* Fetch the instruction. */ |
4cc0665f MR |
3457 | inst = (unsigned long) mips_fetch_instruction (gdbarch, ISA_MIPS, |
3458 | cur_pc, NULL); | |
9022177c | 3459 | |
29639122 JB |
3460 | /* Save some code by pre-extracting some useful fields. */ |
3461 | high_word = (inst >> 16) & 0xffff; | |
eaa6a9a4 | 3462 | offset = ((inst & 0xffff) ^ 0x8000) - 0x8000; |
29639122 | 3463 | reg = high_word & 0x1f; |
fe29b929 | 3464 | |
025bb325 | 3465 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
29639122 JB |
3466 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
3467 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
3468 | { | |
eaa6a9a4 | 3469 | if (offset < 0) /* Negative stack adjustment? */ |
dda83cd7 | 3470 | frame_offset -= offset; |
29639122 JB |
3471 | else |
3472 | /* Exit loop if a positive stack adjustment is found, which | |
3473 | usually means that the stack cleanup code in the function | |
3474 | epilogue is reached. */ | |
3475 | break; | |
dda83cd7 | 3476 | seen_sp_adjust = 1; |
29639122 | 3477 | } |
7d1e6fb8 | 3478 | else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ |
dda83cd7 | 3479 | && !regsize_is_64_bits) |
29639122 | 3480 | { |
eaa6a9a4 | 3481 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 | 3482 | } |
7d1e6fb8 | 3483 | else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ |
dda83cd7 | 3484 | && regsize_is_64_bits) |
29639122 JB |
3485 | { |
3486 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ | |
eaa6a9a4 | 3487 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
3488 | } |
3489 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
3490 | { | |
3491 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
eaa6a9a4 MR |
3492 | if (offset != frame_offset) |
3493 | frame_addr = sp + offset; | |
b8a22b94 | 3494 | else if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
3495 | { |
3496 | unsigned alloca_adjust; | |
a4b8ebc8 | 3497 | |
29639122 | 3498 | frame_reg = 30; |
b8a22b94 DJ |
3499 | frame_addr = get_frame_register_signed |
3500 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
ca9c94ef | 3501 | frame_offset = 0; |
d2ca4222 | 3502 | |
eaa6a9a4 | 3503 | alloca_adjust = (unsigned) (frame_addr - (sp + offset)); |
29639122 JB |
3504 | if (alloca_adjust > 0) |
3505 | { | |
dda83cd7 SM |
3506 | /* FP > SP + frame_size. This may be because of |
3507 | an alloca or somethings similar. Fix sp to | |
3508 | "pre-alloca" value, and try again. */ | |
29639122 | 3509 | sp += alloca_adjust; |
dda83cd7 SM |
3510 | /* Need to reset the status of all registers. Otherwise, |
3511 | we will hit a guard that prevents the new address | |
3512 | for each register to be recomputed during the second | |
3513 | pass. */ | |
3514 | reset_saved_regs (gdbarch, this_cache); | |
29639122 JB |
3515 | goto restart; |
3516 | } | |
3517 | } | |
3518 | } | |
3519 | /* move $30,$sp. With different versions of gas this will be either | |
dda83cd7 SM |
3520 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. |
3521 | Accept any one of these. */ | |
29639122 JB |
3522 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) |
3523 | { | |
3524 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
b8a22b94 | 3525 | if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
3526 | { |
3527 | unsigned alloca_adjust; | |
c906108c | 3528 | |
29639122 | 3529 | frame_reg = 30; |
b8a22b94 DJ |
3530 | frame_addr = get_frame_register_signed |
3531 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 3532 | |
29639122 JB |
3533 | alloca_adjust = (unsigned) (frame_addr - sp); |
3534 | if (alloca_adjust > 0) | |
dda83cd7 SM |
3535 | { |
3536 | /* FP > SP + frame_size. This may be because of | |
3537 | an alloca or somethings similar. Fix sp to | |
3538 | "pre-alloca" value, and try again. */ | |
3539 | sp = frame_addr; | |
3540 | /* Need to reset the status of all registers. Otherwise, | |
3541 | we will hit a guard that prevents the new address | |
3542 | for each register to be recomputed during the second | |
3543 | pass. */ | |
3544 | reset_saved_regs (gdbarch, this_cache); | |
3545 | goto restart; | |
3546 | } | |
29639122 JB |
3547 | } |
3548 | } | |
7d1e6fb8 | 3549 | else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */ |
dda83cd7 | 3550 | && !regsize_is_64_bits) |
29639122 | 3551 | { |
eaa6a9a4 | 3552 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
3553 | } |
3554 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | |
dda83cd7 SM |
3555 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ |
3556 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | |
3557 | || high_word == 0x3c1c /* lui $gp,n */ | |
3558 | || high_word == 0x279c /* addiu $gp,$gp,n */ | |
3559 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
3560 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | |
3561 | ) | |
19080931 MR |
3562 | { |
3563 | /* These instructions are part of the prologue, but we don't | |
3564 | need to do anything special to handle them. */ | |
3565 | } | |
29639122 | 3566 | /* The instructions below load $at or $t0 with an immediate |
dda83cd7 SM |
3567 | value in preparation for a stack adjustment via |
3568 | subu $sp,$sp,[$at,$t0]. These instructions could also | |
3569 | initialize a local variable, so we accept them only before | |
3570 | a stack adjustment instruction was seen. */ | |
29639122 | 3571 | else if (!seen_sp_adjust |
ab50adb6 | 3572 | && !prev_delay_slot |
19080931 MR |
3573 | && (high_word == 0x3c01 /* lui $at,n */ |
3574 | || high_word == 0x3c08 /* lui $t0,n */ | |
3575 | || high_word == 0x3421 /* ori $at,$at,n */ | |
3576 | || high_word == 0x3508 /* ori $t0,$t0,n */ | |
3577 | || high_word == 0x3401 /* ori $at,$zero,n */ | |
3578 | || high_word == 0x3408 /* ori $t0,$zero,n */ | |
3579 | )) | |
3580 | { | |
ab50adb6 | 3581 | load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ |
19080931 | 3582 | } |
ab50adb6 | 3583 | /* Check for branches and jumps. The instruction in the delay |
dda83cd7 | 3584 | slot can be a part of the prologue, so move forward once more. */ |
ab50adb6 MR |
3585 | else if (mips32_instruction_has_delay_slot (gdbarch, inst)) |
3586 | { | |
3587 | in_delay_slot = 1; | |
3588 | } | |
3589 | /* This instruction is not an instruction typically found | |
dda83cd7 SM |
3590 | in a prologue, so we must have reached the end of the |
3591 | prologue. */ | |
29639122 | 3592 | else |
19080931 | 3593 | { |
ab50adb6 | 3594 | this_non_prologue_insn = 1; |
19080931 | 3595 | } |
db5f024e | 3596 | |
ab50adb6 MR |
3597 | non_prologue_insns += this_non_prologue_insn; |
3598 | ||
3599 | /* A jump or branch, or enough non-prologue insns seen? If so, | |
dda83cd7 | 3600 | then we must have reached the end of the prologue by now. */ |
ab50adb6 | 3601 | if (prev_delay_slot || non_prologue_insns > 1) |
db5f024e | 3602 | break; |
ab50adb6 MR |
3603 | |
3604 | prev_non_prologue_insn = this_non_prologue_insn; | |
3605 | prev_delay_slot = in_delay_slot; | |
3606 | prev_pc = cur_pc; | |
a4b8ebc8 | 3607 | } |
c906108c | 3608 | |
29639122 JB |
3609 | if (this_cache != NULL) |
3610 | { | |
3611 | this_cache->base = | |
dda83cd7 | 3612 | (get_frame_register_signed (this_frame, |
b8a22b94 | 3613 | gdbarch_num_regs (gdbarch) + frame_reg) |
dda83cd7 | 3614 | + frame_offset); |
29639122 | 3615 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of |
dda83cd7 SM |
3616 | this assignment below, eventually. But it's still needed |
3617 | for now. */ | |
72a155b4 UW |
3618 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
3619 | + mips_regnum (gdbarch)->pc] | |
dda83cd7 | 3620 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
f57d151a | 3621 | + MIPS_RA_REGNUM]; |
29639122 | 3622 | } |
c906108c | 3623 | |
ab50adb6 MR |
3624 | /* Set end_prologue_addr to the address of the instruction immediately |
3625 | after the last one we scanned. Unless the last one looked like a | |
3626 | non-prologue instruction (and we looked ahead), in which case use | |
3627 | its address instead. */ | |
3628 | end_prologue_addr | |
3629 | = prev_non_prologue_insn || prev_delay_slot ? prev_pc : cur_pc; | |
29639122 JB |
3630 | |
3631 | /* In a frameless function, we might have incorrectly | |
025bb325 | 3632 | skipped some load immediate instructions. Undo the skipping |
29639122 JB |
3633 | if the load immediate was not followed by a stack adjustment. */ |
3634 | if (load_immediate_bytes && !seen_sp_adjust) | |
3635 | end_prologue_addr -= load_immediate_bytes; | |
c906108c | 3636 | |
29639122 | 3637 | return end_prologue_addr; |
c906108c SS |
3638 | } |
3639 | ||
29639122 JB |
3640 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
3641 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
3642 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
4cc0665f | 3643 | unwinder. Likewise microMIPS and the mips_micro unwinder. */ |
c906108c | 3644 | |
29639122 | 3645 | static struct mips_frame_cache * |
b8a22b94 | 3646 | mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache) |
c906108c | 3647 | { |
e17a4113 | 3648 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 3649 | struct mips_frame_cache *cache; |
c906108c | 3650 | |
29639122 | 3651 | if ((*this_cache) != NULL) |
19ba03f4 | 3652 | return (struct mips_frame_cache *) (*this_cache); |
c5aa993b | 3653 | |
29639122 JB |
3654 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
3655 | (*this_cache) = cache; | |
b8a22b94 | 3656 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
c5aa993b | 3657 | |
29639122 JB |
3658 | /* Analyze the function prologue. */ |
3659 | { | |
b8a22b94 | 3660 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 3661 | CORE_ADDR start_addr; |
c906108c | 3662 | |
29639122 JB |
3663 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
3664 | if (start_addr == 0) | |
e17a4113 | 3665 | start_addr = heuristic_proc_start (gdbarch, pc); |
29639122 JB |
3666 | /* We can't analyze the prologue if we couldn't find the begining |
3667 | of the function. */ | |
3668 | if (start_addr == 0) | |
3669 | return cache; | |
c5aa993b | 3670 | |
19ba03f4 SM |
3671 | mips32_scan_prologue (gdbarch, start_addr, pc, this_frame, |
3672 | (struct mips_frame_cache *) *this_cache); | |
29639122 JB |
3673 | } |
3674 | ||
3e8c568d | 3675 | /* gdbarch_sp_regnum contains the value and not the address. */ |
a9a87d35 LM |
3676 | cache->saved_regs[gdbarch_num_regs (gdbarch) |
3677 | + MIPS_SP_REGNUM].set_value (cache->base); | |
c5aa993b | 3678 | |
19ba03f4 | 3679 | return (struct mips_frame_cache *) (*this_cache); |
c906108c SS |
3680 | } |
3681 | ||
29639122 | 3682 | static void |
b8a22b94 | 3683 | mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 | 3684 | struct frame_id *this_id) |
c906108c | 3685 | { |
b8a22b94 | 3686 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 3687 | this_cache); |
21327321 DJ |
3688 | /* This marks the outermost frame. */ |
3689 | if (info->base == 0) | |
3690 | return; | |
b8a22b94 | 3691 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
29639122 | 3692 | } |
c906108c | 3693 | |
b8a22b94 DJ |
3694 | static struct value * |
3695 | mips_insn32_frame_prev_register (struct frame_info *this_frame, | |
3696 | void **this_cache, int regnum) | |
29639122 | 3697 | { |
b8a22b94 | 3698 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 3699 | this_cache); |
b8a22b94 DJ |
3700 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
3701 | } | |
3702 | ||
3703 | static int | |
3704 | mips_insn32_frame_sniffer (const struct frame_unwind *self, | |
3705 | struct frame_info *this_frame, void **this_cache) | |
3706 | { | |
3707 | CORE_ADDR pc = get_frame_pc (this_frame); | |
4cc0665f | 3708 | if (mips_pc_is_mips (pc)) |
b8a22b94 DJ |
3709 | return 1; |
3710 | return 0; | |
c906108c SS |
3711 | } |
3712 | ||
29639122 JB |
3713 | static const struct frame_unwind mips_insn32_frame_unwind = |
3714 | { | |
3715 | NORMAL_FRAME, | |
8fbca658 | 3716 | default_frame_unwind_stop_reason, |
29639122 | 3717 | mips_insn32_frame_this_id, |
b8a22b94 DJ |
3718 | mips_insn32_frame_prev_register, |
3719 | NULL, | |
3720 | mips_insn32_frame_sniffer | |
29639122 | 3721 | }; |
c906108c | 3722 | |
1c645fec | 3723 | static CORE_ADDR |
b8a22b94 | 3724 | mips_insn32_frame_base_address (struct frame_info *this_frame, |
29639122 | 3725 | void **this_cache) |
c906108c | 3726 | { |
b8a22b94 | 3727 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 JB |
3728 | this_cache); |
3729 | return info->base; | |
3730 | } | |
c906108c | 3731 | |
29639122 JB |
3732 | static const struct frame_base mips_insn32_frame_base = |
3733 | { | |
3734 | &mips_insn32_frame_unwind, | |
3735 | mips_insn32_frame_base_address, | |
3736 | mips_insn32_frame_base_address, | |
3737 | mips_insn32_frame_base_address | |
3738 | }; | |
1c645fec | 3739 | |
29639122 | 3740 | static const struct frame_base * |
b8a22b94 | 3741 | mips_insn32_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 3742 | { |
b8a22b94 | 3743 | CORE_ADDR pc = get_frame_pc (this_frame); |
4cc0665f | 3744 | if (mips_pc_is_mips (pc)) |
29639122 | 3745 | return &mips_insn32_frame_base; |
a65bbe44 | 3746 | else |
29639122 JB |
3747 | return NULL; |
3748 | } | |
a65bbe44 | 3749 | |
29639122 | 3750 | static struct trad_frame_cache * |
b8a22b94 | 3751 | mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache) |
29639122 JB |
3752 | { |
3753 | CORE_ADDR pc; | |
3754 | CORE_ADDR start_addr; | |
3755 | CORE_ADDR stack_addr; | |
3756 | struct trad_frame_cache *this_trad_cache; | |
b8a22b94 DJ |
3757 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
3758 | int num_regs = gdbarch_num_regs (gdbarch); | |
c906108c | 3759 | |
29639122 | 3760 | if ((*this_cache) != NULL) |
19ba03f4 | 3761 | return (struct trad_frame_cache *) (*this_cache); |
b8a22b94 | 3762 | this_trad_cache = trad_frame_cache_zalloc (this_frame); |
29639122 | 3763 | (*this_cache) = this_trad_cache; |
1c645fec | 3764 | |
29639122 | 3765 | /* The return address is in the link register. */ |
3e8c568d | 3766 | trad_frame_set_reg_realreg (this_trad_cache, |
72a155b4 | 3767 | gdbarch_pc_regnum (gdbarch), |
b8a22b94 | 3768 | num_regs + MIPS_RA_REGNUM); |
1c645fec | 3769 | |
29639122 JB |
3770 | /* Frame ID, since it's a frameless / stackless function, no stack |
3771 | space is allocated and SP on entry is the current SP. */ | |
b8a22b94 | 3772 | pc = get_frame_pc (this_frame); |
29639122 | 3773 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
b8a22b94 DJ |
3774 | stack_addr = get_frame_register_signed (this_frame, |
3775 | num_regs + MIPS_SP_REGNUM); | |
aa6c981f | 3776 | trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr)); |
1c645fec | 3777 | |
29639122 JB |
3778 | /* Assume that the frame's base is the same as the |
3779 | stack-pointer. */ | |
3780 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
c906108c | 3781 | |
29639122 JB |
3782 | return this_trad_cache; |
3783 | } | |
c906108c | 3784 | |
29639122 | 3785 | static void |
b8a22b94 | 3786 | mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 JB |
3787 | struct frame_id *this_id) |
3788 | { | |
3789 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 3790 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
3791 | trad_frame_get_id (this_trad_cache, this_id); |
3792 | } | |
c906108c | 3793 | |
b8a22b94 DJ |
3794 | static struct value * |
3795 | mips_stub_frame_prev_register (struct frame_info *this_frame, | |
3796 | void **this_cache, int regnum) | |
29639122 JB |
3797 | { |
3798 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 DJ |
3799 | = mips_stub_frame_cache (this_frame, this_cache); |
3800 | return trad_frame_get_register (this_trad_cache, this_frame, regnum); | |
29639122 | 3801 | } |
c906108c | 3802 | |
b8a22b94 DJ |
3803 | static int |
3804 | mips_stub_frame_sniffer (const struct frame_unwind *self, | |
3805 | struct frame_info *this_frame, void **this_cache) | |
29639122 | 3806 | { |
aa6c981f | 3807 | gdb_byte dummy[4]; |
b8a22b94 | 3808 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
7cbd4a93 | 3809 | struct bound_minimal_symbol msym; |
979b38e0 | 3810 | |
aa6c981f | 3811 | /* Use the stub unwinder for unreadable code. */ |
b8a22b94 DJ |
3812 | if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) |
3813 | return 1; | |
aa6c981f | 3814 | |
3e5d3a5a | 3815 | if (in_plt_section (pc) || in_mips_stubs_section (pc)) |
b8a22b94 | 3816 | return 1; |
979b38e0 | 3817 | |
db5f024e DJ |
3818 | /* Calling a PIC function from a non-PIC function passes through a |
3819 | stub. The stub for foo is named ".pic.foo". */ | |
3820 | msym = lookup_minimal_symbol_by_pc (pc); | |
7cbd4a93 | 3821 | if (msym.minsym != NULL |
c9d95fa3 CB |
3822 | && msym.minsym->linkage_name () != NULL |
3823 | && startswith (msym.minsym->linkage_name (), ".pic.")) | |
db5f024e DJ |
3824 | return 1; |
3825 | ||
b8a22b94 | 3826 | return 0; |
29639122 | 3827 | } |
c906108c | 3828 | |
b8a22b94 DJ |
3829 | static const struct frame_unwind mips_stub_frame_unwind = |
3830 | { | |
3831 | NORMAL_FRAME, | |
8fbca658 | 3832 | default_frame_unwind_stop_reason, |
b8a22b94 DJ |
3833 | mips_stub_frame_this_id, |
3834 | mips_stub_frame_prev_register, | |
3835 | NULL, | |
3836 | mips_stub_frame_sniffer | |
3837 | }; | |
3838 | ||
29639122 | 3839 | static CORE_ADDR |
b8a22b94 | 3840 | mips_stub_frame_base_address (struct frame_info *this_frame, |
29639122 JB |
3841 | void **this_cache) |
3842 | { | |
3843 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 3844 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
3845 | return trad_frame_get_this_base (this_trad_cache); |
3846 | } | |
0fce0821 | 3847 | |
29639122 JB |
3848 | static const struct frame_base mips_stub_frame_base = |
3849 | { | |
3850 | &mips_stub_frame_unwind, | |
3851 | mips_stub_frame_base_address, | |
3852 | mips_stub_frame_base_address, | |
3853 | mips_stub_frame_base_address | |
3854 | }; | |
3855 | ||
3856 | static const struct frame_base * | |
b8a22b94 | 3857 | mips_stub_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 3858 | { |
b8a22b94 | 3859 | if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL)) |
29639122 JB |
3860 | return &mips_stub_frame_base; |
3861 | else | |
3862 | return NULL; | |
3863 | } | |
3864 | ||
29639122 | 3865 | /* mips_addr_bits_remove - remove useless address bits */ |
65596487 | 3866 | |
29639122 | 3867 | static CORE_ADDR |
24568a2c | 3868 | mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) |
65596487 | 3869 | { |
24568a2c | 3870 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
930bd0e0 | 3871 | |
29639122 JB |
3872 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) |
3873 | /* This hack is a work-around for existing boards using PMON, the | |
3874 | simulator, and any other 64-bit targets that doesn't have true | |
3875 | 64-bit addressing. On these targets, the upper 32 bits of | |
3876 | addresses are ignored by the hardware. Thus, the PC or SP are | |
3877 | likely to have been sign extended to all 1s by instruction | |
3878 | sequences that load 32-bit addresses. For example, a typical | |
3879 | piece of code that loads an address is this: | |
65596487 | 3880 | |
29639122 JB |
3881 | lui $r2, <upper 16 bits> |
3882 | ori $r2, <lower 16 bits> | |
65596487 | 3883 | |
29639122 JB |
3884 | But the lui sign-extends the value such that the upper 32 bits |
3885 | may be all 1s. The workaround is simply to mask off these | |
3886 | bits. In the future, gcc may be changed to support true 64-bit | |
3887 | addressing, and this masking will have to be disabled. */ | |
3888 | return addr &= 0xffffffffUL; | |
3889 | else | |
3890 | return addr; | |
65596487 JB |
3891 | } |
3892 | ||
3d5f6d12 DJ |
3893 | |
3894 | /* Checks for an atomic sequence of instructions beginning with a LL/LLD | |
3895 | instruction and ending with a SC/SCD instruction. If such a sequence | |
3896 | is found, attempt to step through it. A breakpoint is placed at the end of | |
3897 | the sequence. */ | |
3898 | ||
4cc0665f MR |
3899 | /* Instructions used during single-stepping of atomic sequences, standard |
3900 | ISA version. */ | |
3901 | #define LL_OPCODE 0x30 | |
3902 | #define LLD_OPCODE 0x34 | |
3903 | #define SC_OPCODE 0x38 | |
3904 | #define SCD_OPCODE 0x3c | |
3905 | ||
a0ff9e1a | 3906 | static std::vector<CORE_ADDR> |
93f9a11f | 3907 | mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) |
3d5f6d12 | 3908 | { |
70ab8ccd | 3909 | CORE_ADDR breaks[2] = {CORE_ADDR_MAX, CORE_ADDR_MAX}; |
3d5f6d12 DJ |
3910 | CORE_ADDR loc = pc; |
3911 | CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ | |
4cc0665f | 3912 | ULONGEST insn; |
3d5f6d12 DJ |
3913 | int insn_count; |
3914 | int index; | |
3915 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
3916 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
3917 | ||
4cc0665f | 3918 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); |
3d5f6d12 DJ |
3919 | /* Assume all atomic sequences start with a ll/lld instruction. */ |
3920 | if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE) | |
a0ff9e1a | 3921 | return {}; |
3d5f6d12 DJ |
3922 | |
3923 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" | |
3924 | instructions. */ | |
3925 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
3926 | { | |
3927 | int is_branch = 0; | |
3928 | loc += MIPS_INSN32_SIZE; | |
4cc0665f | 3929 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); |
3d5f6d12 DJ |
3930 | |
3931 | /* Assume that there is at most one branch in the atomic | |
3932 | sequence. If a branch is found, put a breakpoint in its | |
3933 | destination address. */ | |
3934 | switch (itype_op (insn)) | |
3935 | { | |
3936 | case 0: /* SPECIAL */ | |
3937 | if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */ | |
a0ff9e1a | 3938 | return {}; /* fallback to the standard single-step code. */ |
3d5f6d12 DJ |
3939 | break; |
3940 | case 1: /* REGIMM */ | |
a385295e MR |
3941 | is_branch = ((itype_rt (insn) & 0xc) == 0 /* B{LT,GE}Z* */ |
3942 | || ((itype_rt (insn) & 0x1e) == 0 | |
3943 | && itype_rs (insn) == 0)); /* BPOSGE* */ | |
3d5f6d12 DJ |
3944 | break; |
3945 | case 2: /* J */ | |
3946 | case 3: /* JAL */ | |
a0ff9e1a | 3947 | return {}; /* fallback to the standard single-step code. */ |
3d5f6d12 DJ |
3948 | case 4: /* BEQ */ |
3949 | case 5: /* BNE */ | |
3950 | case 6: /* BLEZ */ | |
3951 | case 7: /* BGTZ */ | |
3952 | case 20: /* BEQL */ | |
3953 | case 21: /* BNEL */ | |
3954 | case 22: /* BLEZL */ | |
3955 | case 23: /* BGTTL */ | |
3956 | is_branch = 1; | |
3957 | break; | |
3958 | case 17: /* COP1 */ | |
a385295e MR |
3959 | is_branch = ((itype_rs (insn) == 9 || itype_rs (insn) == 10) |
3960 | && (itype_rt (insn) & 0x2) == 0); | |
3961 | if (is_branch) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */ | |
3962 | break; | |
3963 | /* Fall through. */ | |
3d5f6d12 DJ |
3964 | case 18: /* COP2 */ |
3965 | case 19: /* COP3 */ | |
3966 | is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */ | |
3967 | break; | |
3968 | } | |
3969 | if (is_branch) | |
3970 | { | |
3971 | branch_bp = loc + mips32_relative_offset (insn) + 4; | |
3972 | if (last_breakpoint >= 1) | |
a0ff9e1a SM |
3973 | return {}; /* More than one branch found, fallback to the |
3974 | standard single-step code. */ | |
3d5f6d12 DJ |
3975 | breaks[1] = branch_bp; |
3976 | last_breakpoint++; | |
3977 | } | |
3978 | ||
3979 | if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE) | |
3980 | break; | |
3981 | } | |
3982 | ||
3983 | /* Assume that the atomic sequence ends with a sc/scd instruction. */ | |
3984 | if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE) | |
a0ff9e1a | 3985 | return {}; |
3d5f6d12 DJ |
3986 | |
3987 | loc += MIPS_INSN32_SIZE; | |
3988 | ||
3989 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
3990 | breaks[0] = loc; | |
3991 | ||
3992 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
025bb325 | 3993 | placed (branch instruction's destination) in the atomic sequence. */ |
3d5f6d12 DJ |
3994 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) |
3995 | last_breakpoint = 0; | |
3996 | ||
a0ff9e1a SM |
3997 | std::vector<CORE_ADDR> next_pcs; |
3998 | ||
3d5f6d12 DJ |
3999 | /* Effectively inserts the breakpoints. */ |
4000 | for (index = 0; index <= last_breakpoint; index++) | |
a0ff9e1a | 4001 | next_pcs.push_back (breaks[index]); |
3d5f6d12 | 4002 | |
93f9a11f | 4003 | return next_pcs; |
3d5f6d12 DJ |
4004 | } |
4005 | ||
a0ff9e1a | 4006 | static std::vector<CORE_ADDR> |
4cc0665f | 4007 | micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch, |
4cc0665f MR |
4008 | CORE_ADDR pc) |
4009 | { | |
4010 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
4011 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
70ab8ccd | 4012 | CORE_ADDR breaks[2] = {CORE_ADDR_MAX, CORE_ADDR_MAX}; |
4b844a38 AT |
4013 | CORE_ADDR branch_bp = 0; /* Breakpoint at branch instruction's |
4014 | destination. */ | |
4cc0665f MR |
4015 | CORE_ADDR loc = pc; |
4016 | int sc_found = 0; | |
4017 | ULONGEST insn; | |
4018 | int insn_count; | |
4019 | int index; | |
4020 | ||
4021 | /* Assume all atomic sequences start with a ll/lld instruction. */ | |
4022 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); | |
4023 | if (micromips_op (insn) != 0x18) /* POOL32C: bits 011000 */ | |
a0ff9e1a | 4024 | return {}; |
4cc0665f MR |
4025 | loc += MIPS_INSN16_SIZE; |
4026 | insn <<= 16; | |
4027 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); | |
4028 | if ((b12s4_op (insn) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */ | |
a0ff9e1a | 4029 | return {}; |
4cc0665f MR |
4030 | loc += MIPS_INSN16_SIZE; |
4031 | ||
4032 | /* Assume all atomic sequences end with an sc/scd instruction. Assume | |
4033 | that no atomic sequence is longer than "atomic_sequence_length" | |
4034 | instructions. */ | |
4035 | for (insn_count = 0; | |
4036 | !sc_found && insn_count < atomic_sequence_length; | |
4037 | ++insn_count) | |
4038 | { | |
4039 | int is_branch = 0; | |
4040 | ||
4041 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); | |
4042 | loc += MIPS_INSN16_SIZE; | |
4043 | ||
4044 | /* Assume that there is at most one conditional branch in the | |
dda83cd7 SM |
4045 | atomic sequence. If a branch is found, put a breakpoint in |
4046 | its destination address. */ | |
4cc0665f MR |
4047 | switch (mips_insn_size (ISA_MICROMIPS, insn)) |
4048 | { | |
4cc0665f MR |
4049 | /* 32-bit instructions. */ |
4050 | case 2 * MIPS_INSN16_SIZE: | |
4051 | switch (micromips_op (insn)) | |
4052 | { | |
4053 | case 0x10: /* POOL32I: bits 010000 */ | |
4054 | if ((b5s5_op (insn) & 0x18) != 0x0 | |
4055 | /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */ | |
4056 | /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */ | |
4057 | && (b5s5_op (insn) & 0x1d) != 0x11 | |
4058 | /* BLTZALS, BGEZALS: bits 010000 100x1 */ | |
4059 | && ((b5s5_op (insn) & 0x1e) != 0x14 | |
4060 | || (insn & 0x3) != 0x0) | |
4061 | /* BC2F, BC2T: bits 010000 1010x xxx00 */ | |
4062 | && (b5s5_op (insn) & 0x1e) != 0x1a | |
4063 | /* BPOSGE64, BPOSGE32: bits 010000 1101x */ | |
4064 | && ((b5s5_op (insn) & 0x1e) != 0x1c | |
4065 | || (insn & 0x3) != 0x0) | |
4066 | /* BC1F, BC1T: bits 010000 1110x xxx00 */ | |
4067 | && ((b5s5_op (insn) & 0x1c) != 0x1c | |
4068 | || (insn & 0x3) != 0x1)) | |
4069 | /* BC1ANY*: bits 010000 111xx xxx01 */ | |
4070 | break; | |
4071 | /* Fall through. */ | |
4072 | ||
4073 | case 0x25: /* BEQ: bits 100101 */ | |
4074 | case 0x2d: /* BNE: bits 101101 */ | |
4075 | insn <<= 16; | |
4076 | insn |= mips_fetch_instruction (gdbarch, | |
4077 | ISA_MICROMIPS, loc, NULL); | |
4078 | branch_bp = (loc + MIPS_INSN16_SIZE | |
4079 | + micromips_relative_offset16 (insn)); | |
4080 | is_branch = 1; | |
4081 | break; | |
4082 | ||
4083 | case 0x00: /* POOL32A: bits 000000 */ | |
4084 | insn <<= 16; | |
4085 | insn |= mips_fetch_instruction (gdbarch, | |
4086 | ISA_MICROMIPS, loc, NULL); | |
4087 | if (b0s6_op (insn) != 0x3c | |
4088 | /* POOL32Axf: bits 000000 ... 111100 */ | |
4089 | || (b6s10_ext (insn) & 0x2bf) != 0x3c) | |
4090 | /* JALR, JALR.HB: 000000 000x111100 111100 */ | |
4091 | /* JALRS, JALRS.HB: 000000 010x111100 111100 */ | |
4092 | break; | |
4093 | /* Fall through. */ | |
4094 | ||
4095 | case 0x1d: /* JALS: bits 011101 */ | |
4096 | case 0x35: /* J: bits 110101 */ | |
4097 | case 0x3d: /* JAL: bits 111101 */ | |
4098 | case 0x3c: /* JALX: bits 111100 */ | |
a0ff9e1a | 4099 | return {}; /* Fall back to the standard single-step code. */ |
4cc0665f MR |
4100 | |
4101 | case 0x18: /* POOL32C: bits 011000 */ | |
4102 | if ((b12s4_op (insn) & 0xb) == 0xb) | |
4103 | /* SC, SCD: bits 011000 1x11 */ | |
4104 | sc_found = 1; | |
4105 | break; | |
4106 | } | |
4107 | loc += MIPS_INSN16_SIZE; | |
4108 | break; | |
4109 | ||
4110 | /* 16-bit instructions. */ | |
4111 | case MIPS_INSN16_SIZE: | |
4112 | switch (micromips_op (insn)) | |
4113 | { | |
4114 | case 0x23: /* BEQZ16: bits 100011 */ | |
4115 | case 0x2b: /* BNEZ16: bits 101011 */ | |
4116 | branch_bp = loc + micromips_relative_offset7 (insn); | |
4117 | is_branch = 1; | |
4118 | break; | |
4119 | ||
4120 | case 0x11: /* POOL16C: bits 010001 */ | |
4121 | if ((b5s5_op (insn) & 0x1c) != 0xc | |
4122 | /* JR16, JRC, JALR16, JALRS16: 010001 011xx */ | |
dda83cd7 | 4123 | && b5s5_op (insn) != 0x18) |
4cc0665f | 4124 | /* JRADDIUSP: bits 010001 11000 */ |
dda83cd7 | 4125 | break; |
a0ff9e1a | 4126 | return {}; /* Fall back to the standard single-step code. */ |
4cc0665f MR |
4127 | |
4128 | case 0x33: /* B16: bits 110011 */ | |
a0ff9e1a | 4129 | return {}; /* Fall back to the standard single-step code. */ |
4cc0665f MR |
4130 | } |
4131 | break; | |
4132 | } | |
4133 | if (is_branch) | |
4134 | { | |
4135 | if (last_breakpoint >= 1) | |
a0ff9e1a SM |
4136 | return {}; /* More than one branch found, fallback to the |
4137 | standard single-step code. */ | |
4cc0665f MR |
4138 | breaks[1] = branch_bp; |
4139 | last_breakpoint++; | |
4140 | } | |
4141 | } | |
4142 | if (!sc_found) | |
a0ff9e1a | 4143 | return {}; |
4cc0665f MR |
4144 | |
4145 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
4146 | breaks[0] = loc; | |
4147 | ||
4148 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
4149 | placed (branch instruction's destination) in the atomic sequence */ | |
4150 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) | |
4151 | last_breakpoint = 0; | |
4152 | ||
a0ff9e1a SM |
4153 | std::vector<CORE_ADDR> next_pcs; |
4154 | ||
4cc0665f MR |
4155 | /* Effectively inserts the breakpoints. */ |
4156 | for (index = 0; index <= last_breakpoint; index++) | |
a0ff9e1a | 4157 | next_pcs.push_back (breaks[index]); |
4cc0665f | 4158 | |
93f9a11f | 4159 | return next_pcs; |
4cc0665f MR |
4160 | } |
4161 | ||
a0ff9e1a | 4162 | static std::vector<CORE_ADDR> |
93f9a11f | 4163 | deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) |
4cc0665f MR |
4164 | { |
4165 | if (mips_pc_is_mips (pc)) | |
93f9a11f | 4166 | return mips_deal_with_atomic_sequence (gdbarch, pc); |
4cc0665f | 4167 | else if (mips_pc_is_micromips (gdbarch, pc)) |
93f9a11f | 4168 | return micromips_deal_with_atomic_sequence (gdbarch, pc); |
4cc0665f | 4169 | else |
a0ff9e1a | 4170 | return {}; |
4cc0665f MR |
4171 | } |
4172 | ||
29639122 JB |
4173 | /* mips_software_single_step() is called just before we want to resume |
4174 | the inferior, if we want to single-step it but there is no hardware | |
4175 | or kernel single-step support (MIPS on GNU/Linux for example). We find | |
e0cd558a | 4176 | the target of the coming instruction and breakpoint it. */ |
29639122 | 4177 | |
a0ff9e1a | 4178 | std::vector<CORE_ADDR> |
f5ea389a | 4179 | mips_software_single_step (struct regcache *regcache) |
c906108c | 4180 | { |
ac7936df | 4181 | struct gdbarch *gdbarch = regcache->arch (); |
8181d85f | 4182 | CORE_ADDR pc, next_pc; |
65596487 | 4183 | |
7113a196 | 4184 | pc = regcache_read_pc (regcache); |
a0ff9e1a SM |
4185 | std::vector<CORE_ADDR> next_pcs = deal_with_atomic_sequence (gdbarch, pc); |
4186 | ||
4187 | if (!next_pcs.empty ()) | |
93f9a11f | 4188 | return next_pcs; |
3d5f6d12 | 4189 | |
7113a196 | 4190 | next_pc = mips_next_pc (regcache, pc); |
e6590a1b | 4191 | |
a0ff9e1a | 4192 | return {next_pc}; |
29639122 | 4193 | } |
a65bbe44 | 4194 | |
29639122 | 4195 | /* Test whether the PC points to the return instruction at the |
025bb325 | 4196 | end of a function. */ |
65596487 | 4197 | |
29639122 | 4198 | static int |
e17a4113 | 4199 | mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 | 4200 | { |
6321c22a MR |
4201 | ULONGEST insn; |
4202 | ULONGEST hint; | |
4203 | ||
4204 | /* This used to check for MIPS16, but this piece of code is never | |
4cc0665f MR |
4205 | called for MIPS16 functions. And likewise microMIPS ones. */ |
4206 | gdb_assert (mips_pc_is_mips (pc)); | |
6321c22a | 4207 | |
4cc0665f | 4208 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
6321c22a MR |
4209 | hint = 0x7c0; |
4210 | return (insn & ~hint) == 0x3e00008; /* jr(.hb) $ra */ | |
29639122 | 4211 | } |
c906108c | 4212 | |
c906108c | 4213 | |
29639122 JB |
4214 | /* This fencepost looks highly suspicious to me. Removing it also |
4215 | seems suspicious as it could affect remote debugging across serial | |
4216 | lines. */ | |
c906108c | 4217 | |
29639122 | 4218 | static CORE_ADDR |
74ed0bb4 | 4219 | heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 JB |
4220 | { |
4221 | CORE_ADDR start_pc; | |
4222 | CORE_ADDR fence; | |
4223 | int instlen; | |
4224 | int seen_adjsp = 0; | |
d6b48e9c | 4225 | struct inferior *inf; |
65596487 | 4226 | |
74ed0bb4 | 4227 | pc = gdbarch_addr_bits_remove (gdbarch, pc); |
29639122 JB |
4228 | start_pc = pc; |
4229 | fence = start_pc - heuristic_fence_post; | |
4230 | if (start_pc == 0) | |
4231 | return 0; | |
65596487 | 4232 | |
44096aee | 4233 | if (heuristic_fence_post == -1 || fence < VM_MIN_ADDRESS) |
29639122 | 4234 | fence = VM_MIN_ADDRESS; |
65596487 | 4235 | |
4cc0665f | 4236 | instlen = mips_pc_is_mips (pc) ? MIPS_INSN32_SIZE : MIPS_INSN16_SIZE; |
98b4dd94 | 4237 | |
d6b48e9c PA |
4238 | inf = current_inferior (); |
4239 | ||
025bb325 | 4240 | /* Search back for previous return. */ |
29639122 JB |
4241 | for (start_pc -= instlen;; start_pc -= instlen) |
4242 | if (start_pc < fence) | |
4243 | { | |
4244 | /* It's not clear to me why we reach this point when | |
4245 | stop_soon, but with this test, at least we | |
4246 | don't print out warnings for every child forked (eg, on | |
4247 | decstation). 22apr93 rich@cygnus.com. */ | |
16c381f0 | 4248 | if (inf->control.stop_soon == NO_STOP_QUIETLY) |
29639122 JB |
4249 | { |
4250 | static int blurb_printed = 0; | |
98b4dd94 | 4251 | |
5af949e3 UW |
4252 | warning (_("GDB can't find the start of the function at %s."), |
4253 | paddress (gdbarch, pc)); | |
29639122 JB |
4254 | |
4255 | if (!blurb_printed) | |
4256 | { | |
4257 | /* This actually happens frequently in embedded | |
4258 | development, when you first connect to a board | |
4259 | and your stack pointer and pc are nowhere in | |
4260 | particular. This message needs to give people | |
4261 | in that situation enough information to | |
4262 | determine that it's no big deal. */ | |
4263 | printf_filtered ("\n\ | |
5af949e3 | 4264 | GDB is unable to find the start of the function at %s\n\ |
29639122 JB |
4265 | and thus can't determine the size of that function's stack frame.\n\ |
4266 | This means that GDB may be unable to access that stack frame, or\n\ | |
4267 | the frames below it.\n\ | |
4268 | This problem is most likely caused by an invalid program counter or\n\ | |
4269 | stack pointer.\n\ | |
4270 | However, if you think GDB should simply search farther back\n\ | |
5af949e3 | 4271 | from %s for code which looks like the beginning of a\n\ |
29639122 | 4272 | function, you can increase the range of the search using the `set\n\ |
5af949e3 UW |
4273 | heuristic-fence-post' command.\n", |
4274 | paddress (gdbarch, pc), paddress (gdbarch, pc)); | |
29639122 JB |
4275 | blurb_printed = 1; |
4276 | } | |
4277 | } | |
4278 | ||
4279 | return 0; | |
4280 | } | |
4cc0665f | 4281 | else if (mips_pc_is_mips16 (gdbarch, start_pc)) |
29639122 JB |
4282 | { |
4283 | unsigned short inst; | |
4284 | ||
4285 | /* On MIPS16, any one of the following is likely to be the | |
4286 | start of a function: | |
193774b3 MR |
4287 | extend save |
4288 | save | |
29639122 JB |
4289 | entry |
4290 | addiu sp,-n | |
4291 | daddiu sp,-n | |
025bb325 | 4292 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */ |
4cc0665f | 4293 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, start_pc, NULL); |
193774b3 MR |
4294 | if ((inst & 0xff80) == 0x6480) /* save */ |
4295 | { | |
4296 | if (start_pc - instlen >= fence) | |
4297 | { | |
4cc0665f MR |
4298 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, |
4299 | start_pc - instlen, NULL); | |
193774b3 MR |
4300 | if ((inst & 0xf800) == 0xf000) /* extend */ |
4301 | start_pc -= instlen; | |
4302 | } | |
4303 | break; | |
4304 | } | |
4305 | else if (((inst & 0xf81f) == 0xe809 | |
4306 | && (inst & 0x700) != 0x700) /* entry */ | |
4307 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
4308 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
4309 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
29639122 JB |
4310 | break; |
4311 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
4312 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
4313 | seen_adjsp = 1; | |
4314 | else | |
4315 | seen_adjsp = 0; | |
4316 | } | |
4cc0665f MR |
4317 | else if (mips_pc_is_micromips (gdbarch, start_pc)) |
4318 | { | |
4319 | ULONGEST insn; | |
4320 | int stop = 0; | |
4321 | long offset; | |
4322 | int dreg; | |
4323 | int sreg; | |
4324 | ||
4325 | /* On microMIPS, any one of the following is likely to be the | |
4326 | start of a function: | |
4327 | ADDIUSP -imm | |
4328 | (D)ADDIU $sp, -imm | |
4329 | LUI $gp, imm */ | |
4330 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
4331 | switch (micromips_op (insn)) | |
4332 | { | |
4333 | case 0xc: /* ADDIU: bits 001100 */ | |
4334 | case 0x17: /* DADDIU: bits 010111 */ | |
4335 | sreg = b0s5_reg (insn); | |
4336 | dreg = b5s5_reg (insn); | |
4337 | insn <<= 16; | |
4338 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, | |
4339 | pc + MIPS_INSN16_SIZE, NULL); | |
4340 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
4341 | if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM | |
4342 | /* (D)ADDIU $sp, imm */ | |
4343 | && offset < 0) | |
4344 | stop = 1; | |
4345 | break; | |
4346 | ||
4347 | case 0x10: /* POOL32I: bits 010000 */ | |
4348 | if (b5s5_op (insn) == 0xd | |
4349 | /* LUI: bits 010000 001101 */ | |
4350 | && b0s5_reg (insn >> 16) == 28) | |
4351 | /* LUI $gp, imm */ | |
4352 | stop = 1; | |
4353 | break; | |
4354 | ||
4355 | case 0x13: /* POOL16D: bits 010011 */ | |
4356 | if ((insn & 0x1) == 0x1) | |
4357 | /* ADDIUSP: bits 010011 1 */ | |
4358 | { | |
4359 | offset = micromips_decode_imm9 (b1s9_imm (insn)); | |
4360 | if (offset < 0) | |
4361 | /* ADDIUSP -imm */ | |
4362 | stop = 1; | |
4363 | } | |
4364 | else | |
4365 | /* ADDIUS5: bits 010011 0 */ | |
4366 | { | |
4367 | dreg = b5s5_reg (insn); | |
4368 | offset = (b1s4_imm (insn) ^ 8) - 8; | |
4369 | if (dreg == MIPS_SP_REGNUM && offset < 0) | |
4370 | /* ADDIUS5 $sp, -imm */ | |
4371 | stop = 1; | |
4372 | } | |
4373 | break; | |
4374 | } | |
4375 | if (stop) | |
4376 | break; | |
4377 | } | |
e17a4113 | 4378 | else if (mips_about_to_return (gdbarch, start_pc)) |
29639122 | 4379 | { |
4c7d22cb | 4380 | /* Skip return and its delay slot. */ |
95ac2dcf | 4381 | start_pc += 2 * MIPS_INSN32_SIZE; |
29639122 JB |
4382 | break; |
4383 | } | |
4384 | ||
4385 | return start_pc; | |
c906108c SS |
4386 | } |
4387 | ||
6c0d6680 DJ |
4388 | struct mips_objfile_private |
4389 | { | |
4390 | bfd_size_type size; | |
4391 | char *contents; | |
4392 | }; | |
4393 | ||
f09ded24 AC |
4394 | /* According to the current ABI, should the type be passed in a |
4395 | floating-point register (assuming that there is space)? When there | |
a1f5b845 | 4396 | is no FPU, FP are not even considered as possible candidates for |
f09ded24 | 4397 | FP registers and, consequently this returns false - forces FP |
025bb325 | 4398 | arguments into integer registers. */ |
f09ded24 AC |
4399 | |
4400 | static int | |
74ed0bb4 MD |
4401 | fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode, |
4402 | struct type *arg_type) | |
f09ded24 AC |
4403 | { |
4404 | return ((typecode == TYPE_CODE_FLT | |
74ed0bb4 | 4405 | || (MIPS_EABI (gdbarch) |
6d82d43b AC |
4406 | && (typecode == TYPE_CODE_STRUCT |
4407 | || typecode == TYPE_CODE_UNION) | |
1f704f76 | 4408 | && arg_type->num_fields () == 1 |
940da03e | 4409 | && check_typedef (arg_type->field (0).type ())->code () |
b2d6f210 | 4410 | == TYPE_CODE_FLT)) |
74ed0bb4 | 4411 | && MIPS_FPU_TYPE(gdbarch) != MIPS_FPU_NONE); |
f09ded24 AC |
4412 | } |
4413 | ||
49e790b0 | 4414 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
025bb325 | 4415 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ |
49e790b0 DJ |
4416 | |
4417 | static int | |
4418 | mips_type_needs_double_align (struct type *type) | |
4419 | { | |
78134374 | 4420 | enum type_code typecode = type->code (); |
361d1df0 | 4421 | |
49e790b0 DJ |
4422 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
4423 | return 1; | |
4424 | else if (typecode == TYPE_CODE_STRUCT) | |
4425 | { | |
1f704f76 | 4426 | if (type->num_fields () < 1) |
49e790b0 | 4427 | return 0; |
940da03e | 4428 | return mips_type_needs_double_align (type->field (0).type ()); |
49e790b0 DJ |
4429 | } |
4430 | else if (typecode == TYPE_CODE_UNION) | |
4431 | { | |
361d1df0 | 4432 | int i, n; |
49e790b0 | 4433 | |
1f704f76 | 4434 | n = type->num_fields (); |
49e790b0 | 4435 | for (i = 0; i < n; i++) |
940da03e | 4436 | if (mips_type_needs_double_align (type->field (i).type ())) |
49e790b0 DJ |
4437 | return 1; |
4438 | return 0; | |
4439 | } | |
4440 | return 0; | |
4441 | } | |
4442 | ||
dc604539 AC |
4443 | /* Adjust the address downward (direction of stack growth) so that it |
4444 | is correctly aligned for a new stack frame. */ | |
4445 | static CORE_ADDR | |
4446 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
4447 | { | |
5b03f266 | 4448 | return align_down (addr, 16); |
dc604539 AC |
4449 | } |
4450 | ||
8ae38c14 | 4451 | /* Implement the "push_dummy_code" gdbarch method. */ |
2c76a0c7 JB |
4452 | |
4453 | static CORE_ADDR | |
4454 | mips_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
4455 | CORE_ADDR funaddr, struct value **args, | |
4456 | int nargs, struct type *value_type, | |
4457 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, | |
4458 | struct regcache *regcache) | |
4459 | { | |
2c76a0c7 | 4460 | static gdb_byte nop_insn[] = { 0, 0, 0, 0 }; |
2e81047f MR |
4461 | CORE_ADDR nop_addr; |
4462 | CORE_ADDR bp_slot; | |
2c76a0c7 JB |
4463 | |
4464 | /* Reserve enough room on the stack for our breakpoint instruction. */ | |
2e81047f MR |
4465 | bp_slot = sp - sizeof (nop_insn); |
4466 | ||
4467 | /* Return to microMIPS mode if calling microMIPS code to avoid | |
4468 | triggering an address error exception on processors that only | |
4469 | support microMIPS execution. */ | |
4470 | *bp_addr = (mips_pc_is_micromips (gdbarch, funaddr) | |
4471 | ? make_compact_addr (bp_slot) : bp_slot); | |
2c76a0c7 JB |
4472 | |
4473 | /* The breakpoint layer automatically adjusts the address of | |
4474 | breakpoints inserted in a branch delay slot. With enough | |
4475 | bad luck, the 4 bytes located just before our breakpoint | |
4476 | instruction could look like a branch instruction, and thus | |
4477 | trigger the adjustement, and break the function call entirely. | |
4478 | So, we reserve those 4 bytes and write a nop instruction | |
4479 | to prevent that from happening. */ | |
2e81047f | 4480 | nop_addr = bp_slot - sizeof (nop_insn); |
2c76a0c7 JB |
4481 | write_memory (nop_addr, nop_insn, sizeof (nop_insn)); |
4482 | sp = mips_frame_align (gdbarch, nop_addr); | |
4483 | ||
4484 | /* Inferior resumes at the function entry point. */ | |
4485 | *real_pc = funaddr; | |
4486 | ||
4487 | return sp; | |
4488 | } | |
4489 | ||
f7ab6ec6 | 4490 | static CORE_ADDR |
7d9b040b | 4491 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4492 | struct regcache *regcache, CORE_ADDR bp_addr, |
4493 | int nargs, struct value **args, CORE_ADDR sp, | |
cf84fa6b AH |
4494 | function_call_return_method return_method, |
4495 | CORE_ADDR struct_addr) | |
c906108c SS |
4496 | { |
4497 | int argreg; | |
4498 | int float_argreg; | |
4499 | int argnum; | |
b926417a | 4500 | int arg_space = 0; |
c906108c | 4501 | int stack_offset = 0; |
e17a4113 | 4502 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 4503 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
b3464d03 | 4504 | int abi_regsize = mips_abi_regsize (gdbarch); |
c906108c | 4505 | |
25ab4790 AC |
4506 | /* For shared libraries, "t9" needs to point at the function |
4507 | address. */ | |
4c7d22cb | 4508 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
4509 | |
4510 | /* Set the return address register to point to the entry point of | |
4511 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 4512 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 4513 | |
c906108c | 4514 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
4515 | are properly aligned. The stack has to be at least 64-bit |
4516 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4517 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4518 | aligned, so we round to this widest known alignment. */ | |
4519 | ||
5b03f266 AC |
4520 | sp = align_down (sp, 16); |
4521 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 4522 | |
46e0f506 | 4523 | /* Now make space on the stack for the args. We allocate more |
c906108c | 4524 | than necessary for EABI, because the first few arguments are |
46e0f506 | 4525 | passed in registers, but that's OK. */ |
c906108c | 4526 | for (argnum = 0; argnum < nargs; argnum++) |
b926417a TT |
4527 | arg_space += align_up (TYPE_LENGTH (value_type (args[argnum])), abi_regsize); |
4528 | sp -= align_up (arg_space, 16); | |
c906108c | 4529 | |
9ace0497 | 4530 | if (mips_debug) |
6d82d43b | 4531 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 | 4532 | "mips_eabi_push_dummy_call: sp=%s allocated %ld\n", |
b926417a TT |
4533 | paddress (gdbarch, sp), |
4534 | (long) align_up (arg_space, 16)); | |
9ace0497 | 4535 | |
c906108c | 4536 | /* Initialize the integer and float register pointers. */ |
4c7d22cb | 4537 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 4538 | float_argreg = mips_fpa0_regnum (gdbarch); |
c906108c | 4539 | |
46e0f506 | 4540 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cf84fa6b | 4541 | if (return_method == return_method_struct) |
9ace0497 AC |
4542 | { |
4543 | if (mips_debug) | |
4544 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
4545 | "mips_eabi_push_dummy_call: " |
4546 | "struct_return reg=%d %s\n", | |
5af949e3 | 4547 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 4548 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
9ace0497 | 4549 | } |
c906108c SS |
4550 | |
4551 | /* Now load as many as possible of the first arguments into | |
4552 | registers, and push the rest onto the stack. Loop thru args | |
4553 | from first to last. */ | |
4554 | for (argnum = 0; argnum < nargs; argnum++) | |
4555 | { | |
47a35522 | 4556 | const gdb_byte *val; |
b3464d03 PA |
4557 | /* This holds the address of structures that are passed by |
4558 | reference. */ | |
4559 | gdb_byte ref_valbuf[MAX_MIPS_ABI_REGSIZE]; | |
ea7c478f | 4560 | struct value *arg = args[argnum]; |
4991999e | 4561 | struct type *arg_type = check_typedef (value_type (arg)); |
c906108c | 4562 | int len = TYPE_LENGTH (arg_type); |
78134374 | 4563 | enum type_code typecode = arg_type->code (); |
c906108c | 4564 | |
9ace0497 AC |
4565 | if (mips_debug) |
4566 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4567 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 4568 | argnum + 1, len, (int) typecode); |
9ace0497 | 4569 | |
c906108c | 4570 | /* The EABI passes structures that do not fit in a register by |
dda83cd7 | 4571 | reference. */ |
b3464d03 | 4572 | if (len > abi_regsize |
9ace0497 | 4573 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 4574 | { |
b3464d03 PA |
4575 | gdb_assert (abi_regsize <= ARRAY_SIZE (ref_valbuf)); |
4576 | store_unsigned_integer (ref_valbuf, abi_regsize, byte_order, | |
e17a4113 | 4577 | value_address (arg)); |
c906108c | 4578 | typecode = TYPE_CODE_PTR; |
b3464d03 PA |
4579 | len = abi_regsize; |
4580 | val = ref_valbuf; | |
9ace0497 AC |
4581 | if (mips_debug) |
4582 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
4583 | } |
4584 | else | |
47a35522 | 4585 | val = value_contents (arg); |
c906108c SS |
4586 | |
4587 | /* 32-bit ABIs always start floating point arguments in an | |
dda83cd7 SM |
4588 | even-numbered floating point register. Round the FP register |
4589 | up before the check to see if there are any FP registers | |
4590 | left. Non MIPS_EABI targets also pass the FP in the integer | |
4591 | registers so also round up normal registers. */ | |
b3464d03 | 4592 | if (abi_regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type)) |
acdb74a0 AC |
4593 | { |
4594 | if ((float_argreg & 1)) | |
4595 | float_argreg++; | |
4596 | } | |
c906108c SS |
4597 | |
4598 | /* Floating point arguments passed in registers have to be | |
dda83cd7 SM |
4599 | treated specially. On 32-bit architectures, doubles |
4600 | are passed in register pairs; the even register gets | |
4601 | the low word, and the odd register gets the high word. | |
4602 | On non-EABI processors, the first two floating point arguments are | |
4603 | also copied to general registers, because MIPS16 functions | |
4604 | don't use float registers for arguments. This duplication of | |
4605 | arguments in general registers can't hurt non-MIPS16 functions | |
4606 | because those registers are normally skipped. */ | |
1012bd0e | 4607 | /* MIPS_EABI squeezes a struct that contains a single floating |
dda83cd7 SM |
4608 | point value into an FP register instead of pushing it onto the |
4609 | stack. */ | |
74ed0bb4 MD |
4610 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
4611 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
c906108c | 4612 | { |
6da397e0 KB |
4613 | /* EABI32 will pass doubles in consecutive registers, even on |
4614 | 64-bit cores. At one time, we used to check the size of | |
4615 | `float_argreg' to determine whether or not to pass doubles | |
4616 | in consecutive registers, but this is not sufficient for | |
4617 | making the ABI determination. */ | |
4618 | if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) | |
c906108c | 4619 | { |
72a155b4 | 4620 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 4621 | == BFD_ENDIAN_BIG ? 4 : 0; |
a8852dc5 | 4622 | long regval; |
c906108c SS |
4623 | |
4624 | /* Write the low word of the double to the even register(s). */ | |
a8852dc5 KB |
4625 | regval = extract_signed_integer (val + low_offset, |
4626 | 4, byte_order); | |
9ace0497 | 4627 | if (mips_debug) |
acdb74a0 | 4628 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 4629 | float_argreg, phex (regval, 4)); |
a8852dc5 | 4630 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
4631 | |
4632 | /* Write the high word of the double to the odd register(s). */ | |
a8852dc5 KB |
4633 | regval = extract_signed_integer (val + 4 - low_offset, |
4634 | 4, byte_order); | |
9ace0497 | 4635 | if (mips_debug) |
acdb74a0 | 4636 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 4637 | float_argreg, phex (regval, 4)); |
a8852dc5 | 4638 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
4639 | } |
4640 | else | |
4641 | { | |
4642 | /* This is a floating point value that fits entirely | |
dda83cd7 | 4643 | in a single register. */ |
53a5351d | 4644 | /* On 32 bit ABI's the float_argreg is further adjusted |
dda83cd7 | 4645 | above to ensure that it is even register aligned. */ |
a8852dc5 | 4646 | LONGEST regval = extract_signed_integer (val, len, byte_order); |
9ace0497 | 4647 | if (mips_debug) |
acdb74a0 | 4648 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 4649 | float_argreg, phex (regval, len)); |
a8852dc5 | 4650 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
4651 | } |
4652 | } | |
4653 | else | |
4654 | { | |
4655 | /* Copy the argument to general registers or the stack in | |
4656 | register-sized pieces. Large arguments are split between | |
4657 | registers and stack. */ | |
b3464d03 | 4658 | /* Note: structs whose size is not a multiple of abi_regsize |
1a69e1e4 | 4659 | are treated specially: Irix cc passes |
d5ac5a39 AC |
4660 | them in registers where gcc sometimes puts them on the |
4661 | stack. For maximum compatibility, we will put them in | |
4662 | both places. */ | |
b3464d03 | 4663 | int odd_sized_struct = (len > abi_regsize && len % abi_regsize != 0); |
46e0f506 | 4664 | |
f09ded24 | 4665 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 4666 | register are only written to memory. */ |
c906108c SS |
4667 | while (len > 0) |
4668 | { | |
ebafbe83 | 4669 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 4670 | int stack_used_p = 0; |
b3464d03 | 4671 | int partial_len = (len < abi_regsize ? len : abi_regsize); |
c906108c | 4672 | |
acdb74a0 AC |
4673 | if (mips_debug) |
4674 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4675 | partial_len); | |
4676 | ||
566f0f7a | 4677 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 4678 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
f09ded24 | 4679 | || odd_sized_struct |
74ed0bb4 | 4680 | || fp_register_arg_p (gdbarch, typecode, arg_type)) |
c906108c | 4681 | { |
c906108c | 4682 | /* Should shorter than int integer values be |
025bb325 | 4683 | promoted to int before being stored? */ |
c906108c | 4684 | int longword_offset = 0; |
9ace0497 | 4685 | CORE_ADDR addr; |
566f0f7a | 4686 | stack_used_p = 1; |
72a155b4 | 4687 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
7a292a7a | 4688 | { |
b3464d03 | 4689 | if (abi_regsize == 8 |
480d3dd2 AC |
4690 | && (typecode == TYPE_CODE_INT |
4691 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 4692 | || typecode == TYPE_CODE_FLT) && len <= 4) |
b3464d03 | 4693 | longword_offset = abi_regsize - len; |
480d3dd2 AC |
4694 | else if ((typecode == TYPE_CODE_STRUCT |
4695 | || typecode == TYPE_CODE_UNION) | |
b3464d03 PA |
4696 | && TYPE_LENGTH (arg_type) < abi_regsize) |
4697 | longword_offset = abi_regsize - len; | |
7a292a7a | 4698 | } |
c5aa993b | 4699 | |
9ace0497 AC |
4700 | if (mips_debug) |
4701 | { | |
5af949e3 UW |
4702 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
4703 | paddress (gdbarch, stack_offset)); | |
4704 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
4705 | paddress (gdbarch, longword_offset)); | |
9ace0497 | 4706 | } |
361d1df0 | 4707 | |
9ace0497 AC |
4708 | addr = sp + stack_offset + longword_offset; |
4709 | ||
4710 | if (mips_debug) | |
4711 | { | |
4712 | int i; | |
5af949e3 UW |
4713 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
4714 | paddress (gdbarch, addr)); | |
9ace0497 AC |
4715 | for (i = 0; i < partial_len; i++) |
4716 | { | |
6d82d43b | 4717 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 4718 | val[i] & 0xff); |
9ace0497 AC |
4719 | } |
4720 | } | |
4721 | write_memory (addr, val, partial_len); | |
c906108c SS |
4722 | } |
4723 | ||
f09ded24 | 4724 | /* Note!!! This is NOT an else clause. Odd sized |
dda83cd7 SM |
4725 | structs may go thru BOTH paths. Floating point |
4726 | arguments will not. */ | |
566f0f7a | 4727 | /* Write this portion of the argument to a general |
dda83cd7 | 4728 | purpose register. */ |
74ed0bb4 MD |
4729 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch) |
4730 | && !fp_register_arg_p (gdbarch, typecode, arg_type)) | |
c906108c | 4731 | { |
6d82d43b | 4732 | LONGEST regval = |
a8852dc5 | 4733 | extract_signed_integer (val, partial_len, byte_order); |
c906108c | 4734 | |
9ace0497 | 4735 | if (mips_debug) |
acdb74a0 | 4736 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 4737 | argreg, |
b3464d03 | 4738 | phex (regval, abi_regsize)); |
a8852dc5 | 4739 | regcache_cooked_write_signed (regcache, argreg, regval); |
c906108c | 4740 | argreg++; |
c906108c | 4741 | } |
c5aa993b | 4742 | |
c906108c SS |
4743 | len -= partial_len; |
4744 | val += partial_len; | |
4745 | ||
b021a221 | 4746 | /* Compute the offset into the stack at which we will |
dda83cd7 | 4747 | copy the next parameter. |
566f0f7a | 4748 | |
dda83cd7 SM |
4749 | In the new EABI (and the NABI32), the stack_offset |
4750 | only needs to be adjusted when it has been used. */ | |
c906108c | 4751 | |
46e0f506 | 4752 | if (stack_used_p) |
b3464d03 | 4753 | stack_offset += align_up (partial_len, abi_regsize); |
c906108c SS |
4754 | } |
4755 | } | |
9ace0497 AC |
4756 | if (mips_debug) |
4757 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
4758 | } |
4759 | ||
f10683bb | 4760 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4761 | |
0f71a2f6 JM |
4762 | /* Return adjusted stack pointer. */ |
4763 | return sp; | |
4764 | } | |
4765 | ||
a1f5b845 | 4766 | /* Determine the return value convention being used. */ |
6d82d43b | 4767 | |
9c8fdbfa | 4768 | static enum return_value_convention |
6a3a010b | 4769 | mips_eabi_return_value (struct gdbarch *gdbarch, struct value *function, |
9c8fdbfa | 4770 | struct type *type, struct regcache *regcache, |
47a35522 | 4771 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 4772 | { |
609ba780 JM |
4773 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4774 | int fp_return_type = 0; | |
4775 | int offset, regnum, xfer; | |
4776 | ||
9c8fdbfa AC |
4777 | if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
4778 | return RETURN_VALUE_STRUCT_CONVENTION; | |
609ba780 JM |
4779 | |
4780 | /* Floating point type? */ | |
4781 | if (tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4782 | { | |
78134374 | 4783 | if (type->code () == TYPE_CODE_FLT) |
609ba780 JM |
4784 | fp_return_type = 1; |
4785 | /* Structs with a single field of float type | |
4786 | are returned in a floating point register. */ | |
78134374 SM |
4787 | if ((type->code () == TYPE_CODE_STRUCT |
4788 | || type->code () == TYPE_CODE_UNION) | |
1f704f76 | 4789 | && type->num_fields () == 1) |
609ba780 | 4790 | { |
940da03e | 4791 | struct type *fieldtype = type->field (0).type (); |
609ba780 | 4792 | |
78134374 | 4793 | if (check_typedef (fieldtype)->code () == TYPE_CODE_FLT) |
609ba780 JM |
4794 | fp_return_type = 1; |
4795 | } | |
4796 | } | |
4797 | ||
4798 | if (fp_return_type) | |
4799 | { | |
4800 | /* A floating-point value belongs in the least significant part | |
4801 | of FP0/FP1. */ | |
4802 | if (mips_debug) | |
4803 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
4804 | regnum = mips_regnum (gdbarch)->fp0; | |
4805 | } | |
4806 | else | |
4807 | { | |
4808 | /* An integer value goes in V0/V1. */ | |
4809 | if (mips_debug) | |
4810 | fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n"); | |
4811 | regnum = MIPS_V0_REGNUM; | |
4812 | } | |
4813 | for (offset = 0; | |
4814 | offset < TYPE_LENGTH (type); | |
4815 | offset += mips_abi_regsize (gdbarch), regnum++) | |
4816 | { | |
4817 | xfer = mips_abi_regsize (gdbarch); | |
4818 | if (offset + xfer > TYPE_LENGTH (type)) | |
4819 | xfer = TYPE_LENGTH (type) - offset; | |
4820 | mips_xfer_register (gdbarch, regcache, | |
4821 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
4822 | gdbarch_byte_order (gdbarch), readbuf, writebuf, | |
4823 | offset); | |
4824 | } | |
4825 | ||
9c8fdbfa | 4826 | return RETURN_VALUE_REGISTER_CONVENTION; |
6d82d43b AC |
4827 | } |
4828 | ||
6d82d43b AC |
4829 | |
4830 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 4831 | |
8d26208a DJ |
4832 | /* Search for a naturally aligned double at OFFSET inside a struct |
4833 | ARG_TYPE. The N32 / N64 ABIs pass these in floating point | |
4834 | registers. */ | |
4835 | ||
4836 | static int | |
74ed0bb4 MD |
4837 | mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type, |
4838 | int offset) | |
8d26208a DJ |
4839 | { |
4840 | int i; | |
4841 | ||
78134374 | 4842 | if (arg_type->code () != TYPE_CODE_STRUCT) |
8d26208a DJ |
4843 | return 0; |
4844 | ||
74ed0bb4 | 4845 | if (MIPS_FPU_TYPE (gdbarch) != MIPS_FPU_DOUBLE) |
8d26208a DJ |
4846 | return 0; |
4847 | ||
4848 | if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE) | |
4849 | return 0; | |
4850 | ||
1f704f76 | 4851 | for (i = 0; i < arg_type->num_fields (); i++) |
8d26208a DJ |
4852 | { |
4853 | int pos; | |
4854 | struct type *field_type; | |
4855 | ||
4856 | /* We're only looking at normal fields. */ | |
ceacbf6e | 4857 | if (field_is_static (&arg_type->field (i)) |
8d26208a DJ |
4858 | || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0) |
4859 | continue; | |
4860 | ||
4861 | /* If we have gone past the offset, there is no double to pass. */ | |
4862 | pos = TYPE_FIELD_BITPOS (arg_type, i) / 8; | |
4863 | if (pos > offset) | |
4864 | return 0; | |
4865 | ||
940da03e | 4866 | field_type = check_typedef (arg_type->field (i).type ()); |
8d26208a DJ |
4867 | |
4868 | /* If this field is entirely before the requested offset, go | |
4869 | on to the next one. */ | |
4870 | if (pos + TYPE_LENGTH (field_type) <= offset) | |
4871 | continue; | |
4872 | ||
4873 | /* If this is our special aligned double, we can stop. */ | |
78134374 | 4874 | if (field_type->code () == TYPE_CODE_FLT |
8d26208a DJ |
4875 | && TYPE_LENGTH (field_type) == MIPS64_REGSIZE) |
4876 | return 1; | |
4877 | ||
4878 | /* This field starts at or before the requested offset, and | |
4879 | overlaps it. If it is a structure, recurse inwards. */ | |
74ed0bb4 | 4880 | return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos); |
8d26208a DJ |
4881 | } |
4882 | ||
4883 | return 0; | |
4884 | } | |
4885 | ||
f7ab6ec6 | 4886 | static CORE_ADDR |
7d9b040b | 4887 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4888 | struct regcache *regcache, CORE_ADDR bp_addr, |
4889 | int nargs, struct value **args, CORE_ADDR sp, | |
cf84fa6b AH |
4890 | function_call_return_method return_method, |
4891 | CORE_ADDR struct_addr) | |
cb3d25d1 MS |
4892 | { |
4893 | int argreg; | |
4894 | int float_argreg; | |
4895 | int argnum; | |
b926417a | 4896 | int arg_space = 0; |
cb3d25d1 | 4897 | int stack_offset = 0; |
e17a4113 | 4898 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 4899 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 4900 | |
25ab4790 AC |
4901 | /* For shared libraries, "t9" needs to point at the function |
4902 | address. */ | |
4c7d22cb | 4903 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
4904 | |
4905 | /* Set the return address register to point to the entry point of | |
4906 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 4907 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 4908 | |
cb3d25d1 MS |
4909 | /* First ensure that the stack and structure return address (if any) |
4910 | are properly aligned. The stack has to be at least 64-bit | |
4911 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4912 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4913 | aligned, so we round to this widest known alignment. */ | |
4914 | ||
5b03f266 AC |
4915 | sp = align_down (sp, 16); |
4916 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
4917 | |
4918 | /* Now make space on the stack for the args. */ | |
4919 | for (argnum = 0; argnum < nargs; argnum++) | |
b926417a TT |
4920 | arg_space += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE); |
4921 | sp -= align_up (arg_space, 16); | |
cb3d25d1 MS |
4922 | |
4923 | if (mips_debug) | |
6d82d43b | 4924 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 | 4925 | "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n", |
b926417a TT |
4926 | paddress (gdbarch, sp), |
4927 | (long) align_up (arg_space, 16)); | |
cb3d25d1 MS |
4928 | |
4929 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 4930 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 4931 | float_argreg = mips_fpa0_regnum (gdbarch); |
cb3d25d1 | 4932 | |
46e0f506 | 4933 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cf84fa6b | 4934 | if (return_method == return_method_struct) |
cb3d25d1 MS |
4935 | { |
4936 | if (mips_debug) | |
4937 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
4938 | "mips_n32n64_push_dummy_call: " |
4939 | "struct_return reg=%d %s\n", | |
5af949e3 | 4940 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 4941 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
cb3d25d1 MS |
4942 | } |
4943 | ||
4944 | /* Now load as many as possible of the first arguments into | |
4945 | registers, and push the rest onto the stack. Loop thru args | |
4946 | from first to last. */ | |
4947 | for (argnum = 0; argnum < nargs; argnum++) | |
4948 | { | |
47a35522 | 4949 | const gdb_byte *val; |
cb3d25d1 | 4950 | struct value *arg = args[argnum]; |
4991999e | 4951 | struct type *arg_type = check_typedef (value_type (arg)); |
cb3d25d1 | 4952 | int len = TYPE_LENGTH (arg_type); |
78134374 | 4953 | enum type_code typecode = arg_type->code (); |
cb3d25d1 MS |
4954 | |
4955 | if (mips_debug) | |
4956 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4957 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
4958 | argnum + 1, len, (int) typecode); |
4959 | ||
47a35522 | 4960 | val = value_contents (arg); |
cb3d25d1 | 4961 | |
5b68030f JM |
4962 | /* A 128-bit long double value requires an even-odd pair of |
4963 | floating-point registers. */ | |
4964 | if (len == 16 | |
4965 | && fp_register_arg_p (gdbarch, typecode, arg_type) | |
4966 | && (float_argreg & 1)) | |
4967 | { | |
4968 | float_argreg++; | |
4969 | argreg++; | |
4970 | } | |
4971 | ||
74ed0bb4 MD |
4972 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
4973 | && argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) | |
cb3d25d1 MS |
4974 | { |
4975 | /* This is a floating point value that fits entirely | |
5b68030f JM |
4976 | in a single register or a pair of registers. */ |
4977 | int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE); | |
e17a4113 | 4978 | LONGEST regval = extract_unsigned_integer (val, reglen, byte_order); |
cb3d25d1 MS |
4979 | if (mips_debug) |
4980 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5b68030f | 4981 | float_argreg, phex (regval, reglen)); |
8d26208a | 4982 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); |
cb3d25d1 MS |
4983 | |
4984 | if (mips_debug) | |
4985 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5b68030f | 4986 | argreg, phex (regval, reglen)); |
9c9acae0 | 4987 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a DJ |
4988 | float_argreg++; |
4989 | argreg++; | |
5b68030f JM |
4990 | if (len == 16) |
4991 | { | |
e17a4113 UW |
4992 | regval = extract_unsigned_integer (val + reglen, |
4993 | reglen, byte_order); | |
5b68030f JM |
4994 | if (mips_debug) |
4995 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4996 | float_argreg, phex (regval, reglen)); | |
4997 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); | |
4998 | ||
4999 | if (mips_debug) | |
5000 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5001 | argreg, phex (regval, reglen)); | |
5002 | regcache_cooked_write_unsigned (regcache, argreg, regval); | |
5003 | float_argreg++; | |
5004 | argreg++; | |
5005 | } | |
cb3d25d1 MS |
5006 | } |
5007 | else | |
5008 | { | |
5009 | /* Copy the argument to general registers or the stack in | |
5010 | register-sized pieces. Large arguments are split between | |
5011 | registers and stack. */ | |
ab2e1992 MR |
5012 | /* For N32/N64, structs, unions, or other composite types are |
5013 | treated as a sequence of doublewords, and are passed in integer | |
5014 | or floating point registers as though they were simple scalar | |
5015 | parameters to the extent that they fit, with any excess on the | |
5016 | stack packed according to the normal memory layout of the | |
5017 | object. | |
5018 | The caller does not reserve space for the register arguments; | |
5019 | the callee is responsible for reserving it if required. */ | |
cb3d25d1 | 5020 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 5021 | register are only written to memory. */ |
cb3d25d1 MS |
5022 | while (len > 0) |
5023 | { | |
ad018eee | 5024 | /* Remember if the argument was written to the stack. */ |
cb3d25d1 | 5025 | int stack_used_p = 0; |
1a69e1e4 | 5026 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
cb3d25d1 MS |
5027 | |
5028 | if (mips_debug) | |
5029 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
5030 | partial_len); | |
5031 | ||
74ed0bb4 MD |
5032 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
5033 | gdb_assert (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)); | |
8d26208a | 5034 | |
cb3d25d1 | 5035 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 5036 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 MS |
5037 | { |
5038 | /* Should shorter than int integer values be | |
025bb325 | 5039 | promoted to int before being stored? */ |
cb3d25d1 MS |
5040 | int longword_offset = 0; |
5041 | CORE_ADDR addr; | |
5042 | stack_used_p = 1; | |
72a155b4 | 5043 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
cb3d25d1 | 5044 | { |
1a69e1e4 | 5045 | if ((typecode == TYPE_CODE_INT |
5b68030f | 5046 | || typecode == TYPE_CODE_PTR) |
1a69e1e4 DJ |
5047 | && len <= 4) |
5048 | longword_offset = MIPS64_REGSIZE - len; | |
cb3d25d1 MS |
5049 | } |
5050 | ||
5051 | if (mips_debug) | |
5052 | { | |
5af949e3 UW |
5053 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
5054 | paddress (gdbarch, stack_offset)); | |
5055 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
5056 | paddress (gdbarch, longword_offset)); | |
cb3d25d1 MS |
5057 | } |
5058 | ||
5059 | addr = sp + stack_offset + longword_offset; | |
5060 | ||
5061 | if (mips_debug) | |
5062 | { | |
5063 | int i; | |
5af949e3 UW |
5064 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
5065 | paddress (gdbarch, addr)); | |
cb3d25d1 MS |
5066 | for (i = 0; i < partial_len; i++) |
5067 | { | |
6d82d43b | 5068 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
5069 | val[i] & 0xff); |
5070 | } | |
5071 | } | |
5072 | write_memory (addr, val, partial_len); | |
5073 | } | |
5074 | ||
5075 | /* Note!!! This is NOT an else clause. Odd sized | |
dda83cd7 | 5076 | structs may go thru BOTH paths. */ |
cb3d25d1 | 5077 | /* Write this portion of the argument to a general |
dda83cd7 | 5078 | purpose register. */ |
74ed0bb4 | 5079 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 | 5080 | { |
5863b5d5 MR |
5081 | LONGEST regval; |
5082 | ||
5083 | /* Sign extend pointers, 32-bit integers and signed | |
5084 | 16-bit and 8-bit integers; everything else is taken | |
5085 | as is. */ | |
5086 | ||
5087 | if ((partial_len == 4 | |
5088 | && (typecode == TYPE_CODE_PTR | |
5089 | || typecode == TYPE_CODE_INT)) | |
5090 | || (partial_len < 4 | |
5091 | && typecode == TYPE_CODE_INT | |
c6d940a9 | 5092 | && !arg_type->is_unsigned ())) |
e17a4113 UW |
5093 | regval = extract_signed_integer (val, partial_len, |
5094 | byte_order); | |
5863b5d5 | 5095 | else |
e17a4113 UW |
5096 | regval = extract_unsigned_integer (val, partial_len, |
5097 | byte_order); | |
cb3d25d1 MS |
5098 | |
5099 | /* A non-floating-point argument being passed in a | |
5100 | general register. If a struct or union, and if | |
5101 | the remaining length is smaller than the register | |
5102 | size, we have to adjust the register value on | |
5103 | big endian targets. | |
5104 | ||
5105 | It does not seem to be necessary to do the | |
1a69e1e4 | 5106 | same for integral types. */ |
cb3d25d1 | 5107 | |
72a155b4 | 5108 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 5109 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
5110 | && (typecode == TYPE_CODE_STRUCT |
5111 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 5112 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 5113 | * TARGET_CHAR_BIT); |
cb3d25d1 MS |
5114 | |
5115 | if (mips_debug) | |
5116 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
5117 | argreg, | |
1a69e1e4 | 5118 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 5119 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a | 5120 | |
74ed0bb4 | 5121 | if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type, |
8d26208a DJ |
5122 | TYPE_LENGTH (arg_type) - len)) |
5123 | { | |
5124 | if (mips_debug) | |
5125 | fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s", | |
5126 | float_argreg, | |
5127 | phex (regval, MIPS64_REGSIZE)); | |
5128 | regcache_cooked_write_unsigned (regcache, float_argreg, | |
5129 | regval); | |
5130 | } | |
5131 | ||
5132 | float_argreg++; | |
cb3d25d1 MS |
5133 | argreg++; |
5134 | } | |
5135 | ||
5136 | len -= partial_len; | |
5137 | val += partial_len; | |
5138 | ||
b021a221 | 5139 | /* Compute the offset into the stack at which we will |
dda83cd7 | 5140 | copy the next parameter. |
cb3d25d1 | 5141 | |
dda83cd7 SM |
5142 | In N32 (N64?), the stack_offset only needs to be |
5143 | adjusted when it has been used. */ | |
cb3d25d1 MS |
5144 | |
5145 | if (stack_used_p) | |
1a69e1e4 | 5146 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
cb3d25d1 MS |
5147 | } |
5148 | } | |
5149 | if (mips_debug) | |
5150 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
5151 | } | |
5152 | ||
f10683bb | 5153 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 5154 | |
cb3d25d1 MS |
5155 | /* Return adjusted stack pointer. */ |
5156 | return sp; | |
5157 | } | |
5158 | ||
6d82d43b | 5159 | static enum return_value_convention |
6a3a010b | 5160 | mips_n32n64_return_value (struct gdbarch *gdbarch, struct value *function, |
6d82d43b | 5161 | struct type *type, struct regcache *regcache, |
47a35522 | 5162 | gdb_byte *readbuf, const gdb_byte *writebuf) |
ebafbe83 | 5163 | { |
72a155b4 | 5164 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
b18bb924 MR |
5165 | |
5166 | /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004 | |
5167 | ||
5168 | Function results are returned in $2 (and $3 if needed), or $f0 (and $f2 | |
5169 | if needed), as appropriate for the type. Composite results (struct, | |
5170 | union, or array) are returned in $2/$f0 and $3/$f2 according to the | |
5171 | following rules: | |
5172 | ||
5173 | * A struct with only one or two floating point fields is returned in $f0 | |
5174 | (and $f2 if necessary). This is a generalization of the Fortran COMPLEX | |
5175 | case. | |
5176 | ||
f08877ba | 5177 | * Any other composite results of at most 128 bits are returned in |
b18bb924 MR |
5178 | $2 (first 64 bits) and $3 (remainder, if necessary). |
5179 | ||
5180 | * Larger composite results are handled by converting the function to a | |
5181 | procedure with an implicit first parameter, which is a pointer to an area | |
5182 | reserved by the caller to receive the result. [The o32-bit ABI requires | |
5183 | that all composite results be handled by conversion to implicit first | |
5184 | parameters. The MIPS/SGI Fortran implementation has always made a | |
5185 | specific exception to return COMPLEX results in the floating point | |
5186 | registers.] */ | |
5187 | ||
f08877ba | 5188 | if (TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE) |
6d82d43b | 5189 | return RETURN_VALUE_STRUCT_CONVENTION; |
78134374 | 5190 | else if (type->code () == TYPE_CODE_FLT |
d05f6826 DJ |
5191 | && TYPE_LENGTH (type) == 16 |
5192 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5193 | { | |
5194 | /* A 128-bit floating-point value fills both $f0 and $f2. The | |
5195 | two registers are used in the same as memory order, so the | |
5196 | eight bytes with the lower memory address are in $f0. */ | |
5197 | if (mips_debug) | |
5198 | fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n"); | |
ba32f989 | 5199 | mips_xfer_register (gdbarch, regcache, |
dca9aa3a MR |
5200 | (gdbarch_num_regs (gdbarch) |
5201 | + mips_regnum (gdbarch)->fp0), | |
72a155b4 | 5202 | 8, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5203 | readbuf, writebuf, 0); |
ba32f989 | 5204 | mips_xfer_register (gdbarch, regcache, |
dca9aa3a MR |
5205 | (gdbarch_num_regs (gdbarch) |
5206 | + mips_regnum (gdbarch)->fp0 + 2), | |
72a155b4 | 5207 | 8, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5208 | readbuf ? readbuf + 8 : readbuf, |
d05f6826 DJ |
5209 | writebuf ? writebuf + 8 : writebuf, 0); |
5210 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5211 | } | |
78134374 | 5212 | else if (type->code () == TYPE_CODE_FLT |
6d82d43b AC |
5213 | && tdep->mips_fpu_type != MIPS_FPU_NONE) |
5214 | { | |
59aa1faa | 5215 | /* A single or double floating-point value that fits in FP0. */ |
6d82d43b AC |
5216 | if (mips_debug) |
5217 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 5218 | mips_xfer_register (gdbarch, regcache, |
dca9aa3a MR |
5219 | (gdbarch_num_regs (gdbarch) |
5220 | + mips_regnum (gdbarch)->fp0), | |
6d82d43b | 5221 | TYPE_LENGTH (type), |
72a155b4 | 5222 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 5223 | readbuf, writebuf, 0); |
6d82d43b AC |
5224 | return RETURN_VALUE_REGISTER_CONVENTION; |
5225 | } | |
78134374 | 5226 | else if (type->code () == TYPE_CODE_STRUCT |
1f704f76 SM |
5227 | && type->num_fields () <= 2 |
5228 | && type->num_fields () >= 1 | |
5229 | && ((type->num_fields () == 1 | |
940da03e | 5230 | && (check_typedef (type->field (0).type ())->code () |
6d82d43b | 5231 | == TYPE_CODE_FLT)) |
1f704f76 | 5232 | || (type->num_fields () == 2 |
940da03e | 5233 | && (check_typedef (type->field (0).type ())->code () |
6d82d43b | 5234 | == TYPE_CODE_FLT) |
940da03e | 5235 | && (check_typedef (type->field (1).type ())->code () |
5b68030f | 5236 | == TYPE_CODE_FLT)))) |
6d82d43b AC |
5237 | { |
5238 | /* A struct that contains one or two floats. Each value is part | |
dda83cd7 SM |
5239 | in the least significant part of their floating point |
5240 | register (or GPR, for soft float). */ | |
6d82d43b AC |
5241 | int regnum; |
5242 | int field; | |
5b68030f JM |
5243 | for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE |
5244 | ? mips_regnum (gdbarch)->fp0 | |
5245 | : MIPS_V0_REGNUM); | |
1f704f76 | 5246 | field < type->num_fields (); field++, regnum += 2) |
6d82d43b | 5247 | { |
80fc5e77 | 5248 | int offset = (FIELD_BITPOS (type->field (field)) |
6d82d43b AC |
5249 | / TARGET_CHAR_BIT); |
5250 | if (mips_debug) | |
5251 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
5252 | offset); | |
940da03e | 5253 | if (TYPE_LENGTH (type->field (field).type ()) == 16) |
5b68030f JM |
5254 | { |
5255 | /* A 16-byte long double field goes in two consecutive | |
5256 | registers. */ | |
5257 | mips_xfer_register (gdbarch, regcache, | |
5258 | gdbarch_num_regs (gdbarch) + regnum, | |
5259 | 8, | |
5260 | gdbarch_byte_order (gdbarch), | |
5261 | readbuf, writebuf, offset); | |
5262 | mips_xfer_register (gdbarch, regcache, | |
5263 | gdbarch_num_regs (gdbarch) + regnum + 1, | |
5264 | 8, | |
5265 | gdbarch_byte_order (gdbarch), | |
5266 | readbuf, writebuf, offset + 8); | |
5267 | } | |
5268 | else | |
5269 | mips_xfer_register (gdbarch, regcache, | |
5270 | gdbarch_num_regs (gdbarch) + regnum, | |
940da03e | 5271 | TYPE_LENGTH (type->field (field).type ()), |
5b68030f JM |
5272 | gdbarch_byte_order (gdbarch), |
5273 | readbuf, writebuf, offset); | |
6d82d43b AC |
5274 | } |
5275 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5276 | } | |
78134374 SM |
5277 | else if (type->code () == TYPE_CODE_STRUCT |
5278 | || type->code () == TYPE_CODE_UNION | |
5279 | || type->code () == TYPE_CODE_ARRAY) | |
6d82d43b | 5280 | { |
f08877ba | 5281 | /* A composite type. Extract the left justified value, |
dda83cd7 SM |
5282 | regardless of the byte order. I.e. DO NOT USE |
5283 | mips_xfer_lower. */ | |
6d82d43b AC |
5284 | int offset; |
5285 | int regnum; | |
4c7d22cb | 5286 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 5287 | offset < TYPE_LENGTH (type); |
72a155b4 | 5288 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 5289 | { |
72a155b4 | 5290 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
5291 | if (offset + xfer > TYPE_LENGTH (type)) |
5292 | xfer = TYPE_LENGTH (type) - offset; | |
5293 | if (mips_debug) | |
5294 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
5295 | offset, xfer, regnum); | |
ba32f989 DJ |
5296 | mips_xfer_register (gdbarch, regcache, |
5297 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 UW |
5298 | xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf, |
5299 | offset); | |
6d82d43b AC |
5300 | } |
5301 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5302 | } | |
5303 | else | |
5304 | { | |
5305 | /* A scalar extract each part but least-significant-byte | |
dda83cd7 | 5306 | justified. */ |
6d82d43b AC |
5307 | int offset; |
5308 | int regnum; | |
4c7d22cb | 5309 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 5310 | offset < TYPE_LENGTH (type); |
72a155b4 | 5311 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 5312 | { |
72a155b4 | 5313 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
5314 | if (offset + xfer > TYPE_LENGTH (type)) |
5315 | xfer = TYPE_LENGTH (type) - offset; | |
5316 | if (mips_debug) | |
5317 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
5318 | offset, xfer, regnum); | |
ba32f989 DJ |
5319 | mips_xfer_register (gdbarch, regcache, |
5320 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 5321 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5322 | readbuf, writebuf, offset); |
6d82d43b AC |
5323 | } |
5324 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5325 | } | |
5326 | } | |
5327 | ||
6a3a010b MR |
5328 | /* Which registers to use for passing floating-point values between |
5329 | function calls, one of floating-point, general and both kinds of | |
5330 | registers. O32 and O64 use different register kinds for standard | |
5331 | MIPS and MIPS16 code; to make the handling of cases where we may | |
5332 | not know what kind of code is being used (e.g. no debug information) | |
5333 | easier we sometimes use both kinds. */ | |
5334 | ||
5335 | enum mips_fval_reg | |
5336 | { | |
5337 | mips_fval_fpr, | |
5338 | mips_fval_gpr, | |
5339 | mips_fval_both | |
5340 | }; | |
5341 | ||
6d82d43b AC |
5342 | /* O32 ABI stuff. */ |
5343 | ||
5344 | static CORE_ADDR | |
7d9b040b | 5345 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
5346 | struct regcache *regcache, CORE_ADDR bp_addr, |
5347 | int nargs, struct value **args, CORE_ADDR sp, | |
cf84fa6b AH |
5348 | function_call_return_method return_method, |
5349 | CORE_ADDR struct_addr) | |
6d82d43b AC |
5350 | { |
5351 | int argreg; | |
5352 | int float_argreg; | |
5353 | int argnum; | |
b926417a | 5354 | int arg_space = 0; |
6d82d43b | 5355 | int stack_offset = 0; |
e17a4113 | 5356 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 5357 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
5358 | |
5359 | /* For shared libraries, "t9" needs to point at the function | |
5360 | address. */ | |
4c7d22cb | 5361 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
6d82d43b AC |
5362 | |
5363 | /* Set the return address register to point to the entry point of | |
5364 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 5365 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
6d82d43b AC |
5366 | |
5367 | /* First ensure that the stack and structure return address (if any) | |
5368 | are properly aligned. The stack has to be at least 64-bit | |
5369 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
5370 | aligned. For n32 and n64, stack frames need to be 128-bit |
5371 | aligned, so we round to this widest known alignment. */ | |
5372 | ||
5b03f266 AC |
5373 | sp = align_down (sp, 16); |
5374 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
5375 | |
5376 | /* Now make space on the stack for the args. */ | |
5377 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
5378 | { |
5379 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
968b5391 MR |
5380 | |
5381 | /* Align to double-word if necessary. */ | |
2afd3f0a | 5382 | if (mips_type_needs_double_align (arg_type)) |
b926417a | 5383 | arg_space = align_up (arg_space, MIPS32_REGSIZE * 2); |
968b5391 | 5384 | /* Allocate space on the stack. */ |
b926417a | 5385 | arg_space += align_up (TYPE_LENGTH (arg_type), MIPS32_REGSIZE); |
968b5391 | 5386 | } |
b926417a | 5387 | sp -= align_up (arg_space, 16); |
ebafbe83 MS |
5388 | |
5389 | if (mips_debug) | |
6d82d43b | 5390 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 | 5391 | "mips_o32_push_dummy_call: sp=%s allocated %ld\n", |
b926417a TT |
5392 | paddress (gdbarch, sp), |
5393 | (long) align_up (arg_space, 16)); | |
ebafbe83 MS |
5394 | |
5395 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 5396 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 5397 | float_argreg = mips_fpa0_regnum (gdbarch); |
ebafbe83 | 5398 | |
bcb0cc15 | 5399 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cf84fa6b | 5400 | if (return_method == return_method_struct) |
ebafbe83 MS |
5401 | { |
5402 | if (mips_debug) | |
5403 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
5404 | "mips_o32_push_dummy_call: " |
5405 | "struct_return reg=%d %s\n", | |
5af949e3 | 5406 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 5407 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 5408 | stack_offset += MIPS32_REGSIZE; |
ebafbe83 MS |
5409 | } |
5410 | ||
5411 | /* Now load as many as possible of the first arguments into | |
5412 | registers, and push the rest onto the stack. Loop thru args | |
5413 | from first to last. */ | |
5414 | for (argnum = 0; argnum < nargs; argnum++) | |
5415 | { | |
47a35522 | 5416 | const gdb_byte *val; |
ebafbe83 | 5417 | struct value *arg = args[argnum]; |
4991999e | 5418 | struct type *arg_type = check_typedef (value_type (arg)); |
ebafbe83 | 5419 | int len = TYPE_LENGTH (arg_type); |
78134374 | 5420 | enum type_code typecode = arg_type->code (); |
ebafbe83 MS |
5421 | |
5422 | if (mips_debug) | |
5423 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 5424 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
5425 | argnum + 1, len, (int) typecode); |
5426 | ||
47a35522 | 5427 | val = value_contents (arg); |
46cac009 AC |
5428 | |
5429 | /* 32-bit ABIs always start floating point arguments in an | |
dda83cd7 SM |
5430 | even-numbered floating point register. Round the FP register |
5431 | up before the check to see if there are any FP registers | |
5432 | left. O32 targets also pass the FP in the integer registers | |
5433 | so also round up normal registers. */ | |
74ed0bb4 | 5434 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
46cac009 AC |
5435 | { |
5436 | if ((float_argreg & 1)) | |
5437 | float_argreg++; | |
5438 | } | |
5439 | ||
5440 | /* Floating point arguments passed in registers have to be | |
dda83cd7 SM |
5441 | treated specially. On 32-bit architectures, doubles are |
5442 | passed in register pairs; the even FP register gets the | |
5443 | low word, and the odd FP register gets the high word. | |
5444 | On O32, the first two floating point arguments are also | |
5445 | copied to general registers, following their memory order, | |
5446 | because MIPS16 functions don't use float registers for | |
5447 | arguments. This duplication of arguments in general | |
5448 | registers can't hurt non-MIPS16 functions, because those | |
5449 | registers are normally skipped. */ | |
46cac009 | 5450 | |
74ed0bb4 MD |
5451 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
5452 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
46cac009 | 5453 | { |
8b07f6d8 | 5454 | if (register_size (gdbarch, float_argreg) < 8 && len == 8) |
46cac009 | 5455 | { |
6a3a010b MR |
5456 | int freg_offset = gdbarch_byte_order (gdbarch) |
5457 | == BFD_ENDIAN_BIG ? 1 : 0; | |
46cac009 AC |
5458 | unsigned long regval; |
5459 | ||
6a3a010b MR |
5460 | /* First word. */ |
5461 | regval = extract_unsigned_integer (val, 4, byte_order); | |
46cac009 AC |
5462 | if (mips_debug) |
5463 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
6a3a010b MR |
5464 | float_argreg + freg_offset, |
5465 | phex (regval, 4)); | |
025bb325 | 5466 | regcache_cooked_write_unsigned (regcache, |
6a3a010b MR |
5467 | float_argreg++ + freg_offset, |
5468 | regval); | |
46cac009 AC |
5469 | if (mips_debug) |
5470 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5471 | argreg, phex (regval, 4)); | |
9c9acae0 | 5472 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 | 5473 | |
6a3a010b MR |
5474 | /* Second word. */ |
5475 | regval = extract_unsigned_integer (val + 4, 4, byte_order); | |
46cac009 AC |
5476 | if (mips_debug) |
5477 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
6a3a010b MR |
5478 | float_argreg - freg_offset, |
5479 | phex (regval, 4)); | |
025bb325 | 5480 | regcache_cooked_write_unsigned (regcache, |
6a3a010b MR |
5481 | float_argreg++ - freg_offset, |
5482 | regval); | |
46cac009 AC |
5483 | if (mips_debug) |
5484 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5485 | argreg, phex (regval, 4)); | |
9c9acae0 | 5486 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
5487 | } |
5488 | else | |
5489 | { | |
5490 | /* This is a floating point value that fits entirely | |
dda83cd7 | 5491 | in a single register. */ |
46cac009 | 5492 | /* On 32 bit ABI's the float_argreg is further adjusted |
dda83cd7 | 5493 | above to ensure that it is even register aligned. */ |
e17a4113 | 5494 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
46cac009 AC |
5495 | if (mips_debug) |
5496 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5497 | float_argreg, phex (regval, len)); | |
025bb325 MS |
5498 | regcache_cooked_write_unsigned (regcache, |
5499 | float_argreg++, regval); | |
5b68030f JM |
5500 | /* Although two FP registers are reserved for each |
5501 | argument, only one corresponding integer register is | |
5502 | reserved. */ | |
46cac009 AC |
5503 | if (mips_debug) |
5504 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5505 | argreg, phex (regval, len)); | |
5b68030f | 5506 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
5507 | } |
5508 | /* Reserve space for the FP register. */ | |
1a69e1e4 | 5509 | stack_offset += align_up (len, MIPS32_REGSIZE); |
46cac009 AC |
5510 | } |
5511 | else | |
5512 | { | |
5513 | /* Copy the argument to general registers or the stack in | |
5514 | register-sized pieces. Large arguments are split between | |
5515 | registers and stack. */ | |
1a69e1e4 DJ |
5516 | /* Note: structs whose size is not a multiple of MIPS32_REGSIZE |
5517 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
5518 | them in registers where gcc sometimes puts them on the |
5519 | stack. For maximum compatibility, we will put them in | |
5520 | both places. */ | |
1a69e1e4 DJ |
5521 | int odd_sized_struct = (len > MIPS32_REGSIZE |
5522 | && len % MIPS32_REGSIZE != 0); | |
46cac009 AC |
5523 | /* Structures should be aligned to eight bytes (even arg registers) |
5524 | on MIPS_ABI_O32, if their first member has double precision. */ | |
2afd3f0a | 5525 | if (mips_type_needs_double_align (arg_type)) |
46cac009 AC |
5526 | { |
5527 | if ((argreg & 1)) | |
968b5391 MR |
5528 | { |
5529 | argreg++; | |
1a69e1e4 | 5530 | stack_offset += MIPS32_REGSIZE; |
968b5391 | 5531 | } |
46cac009 | 5532 | } |
46cac009 AC |
5533 | while (len > 0) |
5534 | { | |
1a69e1e4 | 5535 | int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); |
46cac009 AC |
5536 | |
5537 | if (mips_debug) | |
5538 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
5539 | partial_len); | |
5540 | ||
5541 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 5542 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 5543 | || odd_sized_struct) |
46cac009 AC |
5544 | { |
5545 | /* Should shorter than int integer values be | |
025bb325 | 5546 | promoted to int before being stored? */ |
46cac009 AC |
5547 | int longword_offset = 0; |
5548 | CORE_ADDR addr; | |
46cac009 AC |
5549 | |
5550 | if (mips_debug) | |
5551 | { | |
5af949e3 UW |
5552 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
5553 | paddress (gdbarch, stack_offset)); | |
5554 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
5555 | paddress (gdbarch, longword_offset)); | |
46cac009 AC |
5556 | } |
5557 | ||
5558 | addr = sp + stack_offset + longword_offset; | |
5559 | ||
5560 | if (mips_debug) | |
5561 | { | |
5562 | int i; | |
5af949e3 UW |
5563 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
5564 | paddress (gdbarch, addr)); | |
46cac009 AC |
5565 | for (i = 0; i < partial_len; i++) |
5566 | { | |
6d82d43b | 5567 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
5568 | val[i] & 0xff); |
5569 | } | |
5570 | } | |
5571 | write_memory (addr, val, partial_len); | |
5572 | } | |
5573 | ||
5574 | /* Note!!! This is NOT an else clause. Odd sized | |
dda83cd7 | 5575 | structs may go thru BOTH paths. */ |
46cac009 | 5576 | /* Write this portion of the argument to a general |
dda83cd7 | 5577 | purpose register. */ |
74ed0bb4 | 5578 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
46cac009 | 5579 | { |
e17a4113 UW |
5580 | LONGEST regval = extract_signed_integer (val, partial_len, |
5581 | byte_order); | |
4246e332 | 5582 | /* Value may need to be sign extended, because |
1b13c4f6 | 5583 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
5584 | |
5585 | /* A non-floating-point argument being passed in a | |
5586 | general register. If a struct or union, and if | |
5587 | the remaining length is smaller than the register | |
5588 | size, we have to adjust the register value on | |
5589 | big endian targets. | |
5590 | ||
5591 | It does not seem to be necessary to do the | |
5592 | same for integral types. | |
5593 | ||
5594 | Also don't do this adjustment on O64 binaries. | |
5595 | ||
5596 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
5597 | outputting LE O32 with sizeof (struct) < | |
e914cb17 MR |
5598 | mips_abi_regsize(), generates a left shift |
5599 | as part of storing the argument in a register | |
5600 | (the left shift isn't generated when | |
1b13c4f6 | 5601 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
5602 | it is quite possible that this is GCC |
5603 | contradicting the LE/O32 ABI, GDB has not been | |
5604 | adjusted to accommodate this. Either someone | |
5605 | needs to demonstrate that the LE/O32 ABI | |
5606 | specifies such a left shift OR this new ABI gets | |
5607 | identified as such and GDB gets tweaked | |
5608 | accordingly. */ | |
5609 | ||
72a155b4 | 5610 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 5611 | && partial_len < MIPS32_REGSIZE |
06f9a1af MR |
5612 | && (typecode == TYPE_CODE_STRUCT |
5613 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 5614 | regval <<= ((MIPS32_REGSIZE - partial_len) |
9ecf7166 | 5615 | * TARGET_CHAR_BIT); |
46cac009 AC |
5616 | |
5617 | if (mips_debug) | |
5618 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
5619 | argreg, | |
1a69e1e4 | 5620 | phex (regval, MIPS32_REGSIZE)); |
9c9acae0 | 5621 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
46cac009 AC |
5622 | argreg++; |
5623 | ||
5624 | /* Prevent subsequent floating point arguments from | |
5625 | being passed in floating point registers. */ | |
74ed0bb4 | 5626 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
46cac009 AC |
5627 | } |
5628 | ||
5629 | len -= partial_len; | |
5630 | val += partial_len; | |
5631 | ||
b021a221 | 5632 | /* Compute the offset into the stack at which we will |
dda83cd7 | 5633 | copy the next parameter. |
46cac009 | 5634 | |
dda83cd7 SM |
5635 | In older ABIs, the caller reserved space for |
5636 | registers that contained arguments. This was loosely | |
5637 | refered to as their "home". Consequently, space is | |
5638 | always allocated. */ | |
46cac009 | 5639 | |
1a69e1e4 | 5640 | stack_offset += align_up (partial_len, MIPS32_REGSIZE); |
46cac009 AC |
5641 | } |
5642 | } | |
5643 | if (mips_debug) | |
5644 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
5645 | } | |
5646 | ||
f10683bb | 5647 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 5648 | |
46cac009 AC |
5649 | /* Return adjusted stack pointer. */ |
5650 | return sp; | |
5651 | } | |
5652 | ||
6d82d43b | 5653 | static enum return_value_convention |
6a3a010b | 5654 | mips_o32_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 | 5655 | struct type *type, struct regcache *regcache, |
47a35522 | 5656 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 5657 | { |
6a3a010b | 5658 | CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0; |
4cc0665f | 5659 | int mips16 = mips_pc_is_mips16 (gdbarch, func_addr); |
72a155b4 | 5660 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
6a3a010b | 5661 | enum mips_fval_reg fval_reg; |
6d82d43b | 5662 | |
6a3a010b | 5663 | fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both; |
78134374 SM |
5664 | if (type->code () == TYPE_CODE_STRUCT |
5665 | || type->code () == TYPE_CODE_UNION | |
5666 | || type->code () == TYPE_CODE_ARRAY) | |
6d82d43b | 5667 | return RETURN_VALUE_STRUCT_CONVENTION; |
78134374 | 5668 | else if (type->code () == TYPE_CODE_FLT |
6d82d43b AC |
5669 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) |
5670 | { | |
6a3a010b | 5671 | /* A single-precision floating-point value. If reading in or copying, |
dda83cd7 SM |
5672 | then we get it from/put it to FP0 for standard MIPS code or GPR2 |
5673 | for MIPS16 code. If writing out only, then we put it to both FP0 | |
5674 | and GPR2. We do not support reading in with no function known, if | |
5675 | this safety check ever triggers, then we'll have to try harder. */ | |
6a3a010b | 5676 | gdb_assert (function || !readbuf); |
6d82d43b | 5677 | if (mips_debug) |
6a3a010b MR |
5678 | switch (fval_reg) |
5679 | { | |
5680 | case mips_fval_fpr: | |
5681 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
5682 | break; | |
5683 | case mips_fval_gpr: | |
5684 | fprintf_unfiltered (gdb_stderr, "Return float in $2\n"); | |
5685 | break; | |
5686 | case mips_fval_both: | |
5687 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n"); | |
5688 | break; | |
5689 | } | |
5690 | if (fval_reg != mips_fval_gpr) | |
5691 | mips_xfer_register (gdbarch, regcache, | |
5692 | (gdbarch_num_regs (gdbarch) | |
5693 | + mips_regnum (gdbarch)->fp0), | |
5694 | TYPE_LENGTH (type), | |
5695 | gdbarch_byte_order (gdbarch), | |
5696 | readbuf, writebuf, 0); | |
5697 | if (fval_reg != mips_fval_fpr) | |
5698 | mips_xfer_register (gdbarch, regcache, | |
5699 | gdbarch_num_regs (gdbarch) + 2, | |
5700 | TYPE_LENGTH (type), | |
5701 | gdbarch_byte_order (gdbarch), | |
5702 | readbuf, writebuf, 0); | |
6d82d43b AC |
5703 | return RETURN_VALUE_REGISTER_CONVENTION; |
5704 | } | |
78134374 | 5705 | else if (type->code () == TYPE_CODE_FLT |
6d82d43b AC |
5706 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) |
5707 | { | |
6a3a010b | 5708 | /* A double-precision floating-point value. If reading in or copying, |
dda83cd7 SM |
5709 | then we get it from/put it to FP1 and FP0 for standard MIPS code or |
5710 | GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it | |
5711 | to both FP1/FP0 and GPR2/GPR3. We do not support reading in with | |
5712 | no function known, if this safety check ever triggers, then we'll | |
5713 | have to try harder. */ | |
6a3a010b | 5714 | gdb_assert (function || !readbuf); |
6d82d43b | 5715 | if (mips_debug) |
6a3a010b MR |
5716 | switch (fval_reg) |
5717 | { | |
5718 | case mips_fval_fpr: | |
5719 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
5720 | break; | |
5721 | case mips_fval_gpr: | |
5722 | fprintf_unfiltered (gdb_stderr, "Return float in $2/$3\n"); | |
5723 | break; | |
5724 | case mips_fval_both: | |
5725 | fprintf_unfiltered (gdb_stderr, | |
5726 | "Return float in $fp1/$fp0 and $2/$3\n"); | |
5727 | break; | |
5728 | } | |
5729 | if (fval_reg != mips_fval_gpr) | |
6d82d43b | 5730 | { |
6a3a010b MR |
5731 | /* The most significant part goes in FP1, and the least significant |
5732 | in FP0. */ | |
5733 | switch (gdbarch_byte_order (gdbarch)) | |
5734 | { | |
5735 | case BFD_ENDIAN_LITTLE: | |
5736 | mips_xfer_register (gdbarch, regcache, | |
5737 | (gdbarch_num_regs (gdbarch) | |
5738 | + mips_regnum (gdbarch)->fp0 + 0), | |
5739 | 4, gdbarch_byte_order (gdbarch), | |
5740 | readbuf, writebuf, 0); | |
5741 | mips_xfer_register (gdbarch, regcache, | |
5742 | (gdbarch_num_regs (gdbarch) | |
5743 | + mips_regnum (gdbarch)->fp0 + 1), | |
5744 | 4, gdbarch_byte_order (gdbarch), | |
5745 | readbuf, writebuf, 4); | |
5746 | break; | |
5747 | case BFD_ENDIAN_BIG: | |
5748 | mips_xfer_register (gdbarch, regcache, | |
5749 | (gdbarch_num_regs (gdbarch) | |
5750 | + mips_regnum (gdbarch)->fp0 + 1), | |
5751 | 4, gdbarch_byte_order (gdbarch), | |
5752 | readbuf, writebuf, 0); | |
5753 | mips_xfer_register (gdbarch, regcache, | |
5754 | (gdbarch_num_regs (gdbarch) | |
5755 | + mips_regnum (gdbarch)->fp0 + 0), | |
5756 | 4, gdbarch_byte_order (gdbarch), | |
5757 | readbuf, writebuf, 4); | |
5758 | break; | |
5759 | default: | |
5760 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
5761 | } | |
5762 | } | |
5763 | if (fval_reg != mips_fval_fpr) | |
5764 | { | |
5765 | /* The two 32-bit parts are always placed in GPR2 and GPR3 | |
5766 | following these registers' memory order. */ | |
ba32f989 | 5767 | mips_xfer_register (gdbarch, regcache, |
6a3a010b | 5768 | gdbarch_num_regs (gdbarch) + 2, |
72a155b4 | 5769 | 4, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5770 | readbuf, writebuf, 0); |
ba32f989 | 5771 | mips_xfer_register (gdbarch, regcache, |
6a3a010b | 5772 | gdbarch_num_regs (gdbarch) + 3, |
72a155b4 | 5773 | 4, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5774 | readbuf, writebuf, 4); |
6d82d43b AC |
5775 | } |
5776 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5777 | } | |
5778 | #if 0 | |
78134374 | 5779 | else if (type->code () == TYPE_CODE_STRUCT |
1f704f76 SM |
5780 | && type->num_fields () <= 2 |
5781 | && type->num_fields () >= 1 | |
5782 | && ((type->num_fields () == 1 | |
940da03e | 5783 | && (TYPE_CODE (type->field (0).type ()) |
6d82d43b | 5784 | == TYPE_CODE_FLT)) |
1f704f76 | 5785 | || (type->num_fields () == 2 |
940da03e | 5786 | && (TYPE_CODE (type->field (0).type ()) |
6d82d43b | 5787 | == TYPE_CODE_FLT) |
940da03e | 5788 | && (TYPE_CODE (type->field (1).type ()) |
6d82d43b AC |
5789 | == TYPE_CODE_FLT))) |
5790 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5791 | { | |
5792 | /* A struct that contains one or two floats. Each value is part | |
dda83cd7 SM |
5793 | in the least significant part of their floating point |
5794 | register.. */ | |
6d82d43b AC |
5795 | int regnum; |
5796 | int field; | |
72a155b4 | 5797 | for (field = 0, regnum = mips_regnum (gdbarch)->fp0; |
1f704f76 | 5798 | field < type->num_fields (); field++, regnum += 2) |
6d82d43b | 5799 | { |
80fc5e77 | 5800 | int offset = (FIELD_BITPOS (type->fields ()[field]) |
6d82d43b AC |
5801 | / TARGET_CHAR_BIT); |
5802 | if (mips_debug) | |
5803 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
5804 | offset); | |
ba32f989 DJ |
5805 | mips_xfer_register (gdbarch, regcache, |
5806 | gdbarch_num_regs (gdbarch) + regnum, | |
940da03e | 5807 | TYPE_LENGTH (type->field (field).type ()), |
72a155b4 | 5808 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 5809 | readbuf, writebuf, offset); |
6d82d43b AC |
5810 | } |
5811 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5812 | } | |
5813 | #endif | |
5814 | #if 0 | |
78134374 SM |
5815 | else if (type->code () == TYPE_CODE_STRUCT |
5816 | || type->code () == TYPE_CODE_UNION) | |
6d82d43b AC |
5817 | { |
5818 | /* A structure or union. Extract the left justified value, | |
dda83cd7 SM |
5819 | regardless of the byte order. I.e. DO NOT USE |
5820 | mips_xfer_lower. */ | |
6d82d43b AC |
5821 | int offset; |
5822 | int regnum; | |
4c7d22cb | 5823 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 5824 | offset < TYPE_LENGTH (type); |
72a155b4 | 5825 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 5826 | { |
72a155b4 | 5827 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
5828 | if (offset + xfer > TYPE_LENGTH (type)) |
5829 | xfer = TYPE_LENGTH (type) - offset; | |
5830 | if (mips_debug) | |
5831 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
5832 | offset, xfer, regnum); | |
ba32f989 DJ |
5833 | mips_xfer_register (gdbarch, regcache, |
5834 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
6d82d43b AC |
5835 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
5836 | } | |
5837 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5838 | } | |
5839 | #endif | |
5840 | else | |
5841 | { | |
5842 | /* A scalar extract each part but least-significant-byte | |
dda83cd7 SM |
5843 | justified. o32 thinks registers are 4 byte, regardless of |
5844 | the ISA. */ | |
6d82d43b AC |
5845 | int offset; |
5846 | int regnum; | |
4c7d22cb | 5847 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 5848 | offset < TYPE_LENGTH (type); |
1a69e1e4 | 5849 | offset += MIPS32_REGSIZE, regnum++) |
6d82d43b | 5850 | { |
1a69e1e4 | 5851 | int xfer = MIPS32_REGSIZE; |
6d82d43b AC |
5852 | if (offset + xfer > TYPE_LENGTH (type)) |
5853 | xfer = TYPE_LENGTH (type) - offset; | |
5854 | if (mips_debug) | |
5855 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
5856 | offset, xfer, regnum); | |
ba32f989 DJ |
5857 | mips_xfer_register (gdbarch, regcache, |
5858 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
72a155b4 | 5859 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 5860 | readbuf, writebuf, offset); |
6d82d43b AC |
5861 | } |
5862 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5863 | } | |
5864 | } | |
5865 | ||
5866 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
5867 | ABI. */ | |
46cac009 AC |
5868 | |
5869 | static CORE_ADDR | |
7d9b040b | 5870 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
5871 | struct regcache *regcache, CORE_ADDR bp_addr, |
5872 | int nargs, | |
5873 | struct value **args, CORE_ADDR sp, | |
cf84fa6b | 5874 | function_call_return_method return_method, CORE_ADDR struct_addr) |
46cac009 AC |
5875 | { |
5876 | int argreg; | |
5877 | int float_argreg; | |
5878 | int argnum; | |
b926417a | 5879 | int arg_space = 0; |
46cac009 | 5880 | int stack_offset = 0; |
e17a4113 | 5881 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 5882 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 5883 | |
25ab4790 AC |
5884 | /* For shared libraries, "t9" needs to point at the function |
5885 | address. */ | |
4c7d22cb | 5886 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
5887 | |
5888 | /* Set the return address register to point to the entry point of | |
5889 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 5890 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 5891 | |
46cac009 AC |
5892 | /* First ensure that the stack and structure return address (if any) |
5893 | are properly aligned. The stack has to be at least 64-bit | |
5894 | aligned even on 32-bit machines, because doubles must be 64-bit | |
5895 | aligned. For n32 and n64, stack frames need to be 128-bit | |
5896 | aligned, so we round to this widest known alignment. */ | |
5897 | ||
5b03f266 AC |
5898 | sp = align_down (sp, 16); |
5899 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
5900 | |
5901 | /* Now make space on the stack for the args. */ | |
5902 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
5903 | { |
5904 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
968b5391 | 5905 | |
968b5391 | 5906 | /* Allocate space on the stack. */ |
b926417a | 5907 | arg_space += align_up (TYPE_LENGTH (arg_type), MIPS64_REGSIZE); |
968b5391 | 5908 | } |
b926417a | 5909 | sp -= align_up (arg_space, 16); |
46cac009 AC |
5910 | |
5911 | if (mips_debug) | |
6d82d43b | 5912 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 | 5913 | "mips_o64_push_dummy_call: sp=%s allocated %ld\n", |
b926417a TT |
5914 | paddress (gdbarch, sp), |
5915 | (long) align_up (arg_space, 16)); | |
46cac009 AC |
5916 | |
5917 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 5918 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 5919 | float_argreg = mips_fpa0_regnum (gdbarch); |
46cac009 AC |
5920 | |
5921 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
cf84fa6b | 5922 | if (return_method == return_method_struct) |
46cac009 AC |
5923 | { |
5924 | if (mips_debug) | |
5925 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
5926 | "mips_o64_push_dummy_call: " |
5927 | "struct_return reg=%d %s\n", | |
5af949e3 | 5928 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 5929 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 5930 | stack_offset += MIPS64_REGSIZE; |
46cac009 AC |
5931 | } |
5932 | ||
5933 | /* Now load as many as possible of the first arguments into | |
5934 | registers, and push the rest onto the stack. Loop thru args | |
5935 | from first to last. */ | |
5936 | for (argnum = 0; argnum < nargs; argnum++) | |
5937 | { | |
47a35522 | 5938 | const gdb_byte *val; |
46cac009 | 5939 | struct value *arg = args[argnum]; |
4991999e | 5940 | struct type *arg_type = check_typedef (value_type (arg)); |
46cac009 | 5941 | int len = TYPE_LENGTH (arg_type); |
78134374 | 5942 | enum type_code typecode = arg_type->code (); |
46cac009 AC |
5943 | |
5944 | if (mips_debug) | |
5945 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 5946 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
5947 | argnum + 1, len, (int) typecode); |
5948 | ||
47a35522 | 5949 | val = value_contents (arg); |
ebafbe83 | 5950 | |
ebafbe83 | 5951 | /* Floating point arguments passed in registers have to be |
dda83cd7 SM |
5952 | treated specially. On 32-bit architectures, doubles are |
5953 | passed in register pairs; the even FP register gets the | |
5954 | low word, and the odd FP register gets the high word. | |
5955 | On O64, the first two floating point arguments are also | |
5956 | copied to general registers, because MIPS16 functions | |
5957 | don't use float registers for arguments. This duplication | |
5958 | of arguments in general registers can't hurt non-MIPS16 | |
5959 | functions because those registers are normally skipped. */ | |
ebafbe83 | 5960 | |
74ed0bb4 MD |
5961 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
5962 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
ebafbe83 | 5963 | { |
e17a4113 | 5964 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
2afd3f0a MR |
5965 | if (mips_debug) |
5966 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5967 | float_argreg, phex (regval, len)); | |
9c9acae0 | 5968 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
2afd3f0a MR |
5969 | if (mips_debug) |
5970 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5971 | argreg, phex (regval, len)); | |
9c9acae0 | 5972 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
2afd3f0a | 5973 | argreg++; |
ebafbe83 | 5974 | /* Reserve space for the FP register. */ |
1a69e1e4 | 5975 | stack_offset += align_up (len, MIPS64_REGSIZE); |
ebafbe83 MS |
5976 | } |
5977 | else | |
5978 | { | |
5979 | /* Copy the argument to general registers or the stack in | |
5980 | register-sized pieces. Large arguments are split between | |
5981 | registers and stack. */ | |
1a69e1e4 | 5982 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
5983 | are treated specially: Irix cc passes them in registers |
5984 | where gcc sometimes puts them on the stack. For maximum | |
5985 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
5986 | int odd_sized_struct = (len > MIPS64_REGSIZE |
5987 | && len % MIPS64_REGSIZE != 0); | |
ebafbe83 MS |
5988 | while (len > 0) |
5989 | { | |
1a69e1e4 | 5990 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
ebafbe83 MS |
5991 | |
5992 | if (mips_debug) | |
5993 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
5994 | partial_len); | |
5995 | ||
5996 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 5997 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 5998 | || odd_sized_struct) |
ebafbe83 MS |
5999 | { |
6000 | /* Should shorter than int integer values be | |
025bb325 | 6001 | promoted to int before being stored? */ |
ebafbe83 MS |
6002 | int longword_offset = 0; |
6003 | CORE_ADDR addr; | |
72a155b4 | 6004 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ebafbe83 | 6005 | { |
1a69e1e4 DJ |
6006 | if ((typecode == TYPE_CODE_INT |
6007 | || typecode == TYPE_CODE_PTR | |
6008 | || typecode == TYPE_CODE_FLT) | |
6009 | && len <= 4) | |
6010 | longword_offset = MIPS64_REGSIZE - len; | |
ebafbe83 MS |
6011 | } |
6012 | ||
6013 | if (mips_debug) | |
6014 | { | |
5af949e3 UW |
6015 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
6016 | paddress (gdbarch, stack_offset)); | |
6017 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
6018 | paddress (gdbarch, longword_offset)); | |
ebafbe83 MS |
6019 | } |
6020 | ||
6021 | addr = sp + stack_offset + longword_offset; | |
6022 | ||
6023 | if (mips_debug) | |
6024 | { | |
6025 | int i; | |
5af949e3 UW |
6026 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
6027 | paddress (gdbarch, addr)); | |
ebafbe83 MS |
6028 | for (i = 0; i < partial_len; i++) |
6029 | { | |
6d82d43b | 6030 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
6031 | val[i] & 0xff); |
6032 | } | |
6033 | } | |
6034 | write_memory (addr, val, partial_len); | |
6035 | } | |
6036 | ||
6037 | /* Note!!! This is NOT an else clause. Odd sized | |
dda83cd7 | 6038 | structs may go thru BOTH paths. */ |
ebafbe83 | 6039 | /* Write this portion of the argument to a general |
dda83cd7 | 6040 | purpose register. */ |
74ed0bb4 | 6041 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
ebafbe83 | 6042 | { |
e17a4113 UW |
6043 | LONGEST regval = extract_signed_integer (val, partial_len, |
6044 | byte_order); | |
4246e332 | 6045 | /* Value may need to be sign extended, because |
1b13c4f6 | 6046 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
6047 | |
6048 | /* A non-floating-point argument being passed in a | |
6049 | general register. If a struct or union, and if | |
6050 | the remaining length is smaller than the register | |
6051 | size, we have to adjust the register value on | |
6052 | big endian targets. | |
6053 | ||
6054 | It does not seem to be necessary to do the | |
025bb325 | 6055 | same for integral types. */ |
480d3dd2 | 6056 | |
72a155b4 | 6057 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 6058 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
6059 | && (typecode == TYPE_CODE_STRUCT |
6060 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 6061 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 6062 | * TARGET_CHAR_BIT); |
ebafbe83 MS |
6063 | |
6064 | if (mips_debug) | |
6065 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
6066 | argreg, | |
1a69e1e4 | 6067 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 6068 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
ebafbe83 MS |
6069 | argreg++; |
6070 | ||
6071 | /* Prevent subsequent floating point arguments from | |
6072 | being passed in floating point registers. */ | |
74ed0bb4 | 6073 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
ebafbe83 MS |
6074 | } |
6075 | ||
6076 | len -= partial_len; | |
6077 | val += partial_len; | |
6078 | ||
b021a221 | 6079 | /* Compute the offset into the stack at which we will |
dda83cd7 | 6080 | copy the next parameter. |
ebafbe83 | 6081 | |
dda83cd7 SM |
6082 | In older ABIs, the caller reserved space for |
6083 | registers that contained arguments. This was loosely | |
6084 | refered to as their "home". Consequently, space is | |
6085 | always allocated. */ | |
ebafbe83 | 6086 | |
1a69e1e4 | 6087 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
ebafbe83 MS |
6088 | } |
6089 | } | |
6090 | if (mips_debug) | |
6091 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
6092 | } | |
6093 | ||
f10683bb | 6094 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 6095 | |
ebafbe83 MS |
6096 | /* Return adjusted stack pointer. */ |
6097 | return sp; | |
6098 | } | |
6099 | ||
9c8fdbfa | 6100 | static enum return_value_convention |
6a3a010b | 6101 | mips_o64_return_value (struct gdbarch *gdbarch, struct value *function, |
9c8fdbfa | 6102 | struct type *type, struct regcache *regcache, |
47a35522 | 6103 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 6104 | { |
6a3a010b | 6105 | CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0; |
4cc0665f | 6106 | int mips16 = mips_pc_is_mips16 (gdbarch, func_addr); |
6a3a010b | 6107 | enum mips_fval_reg fval_reg; |
7a076fd2 | 6108 | |
6a3a010b | 6109 | fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both; |
78134374 SM |
6110 | if (type->code () == TYPE_CODE_STRUCT |
6111 | || type->code () == TYPE_CODE_UNION | |
6112 | || type->code () == TYPE_CODE_ARRAY) | |
7a076fd2 | 6113 | return RETURN_VALUE_STRUCT_CONVENTION; |
78134374 | 6114 | else if (fp_register_arg_p (gdbarch, type->code (), type)) |
7a076fd2 | 6115 | { |
6a3a010b | 6116 | /* A floating-point value. If reading in or copying, then we get it |
dda83cd7 SM |
6117 | from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code. |
6118 | If writing out only, then we put it to both FP0 and GPR2. We do | |
6119 | not support reading in with no function known, if this safety | |
6120 | check ever triggers, then we'll have to try harder. */ | |
6a3a010b | 6121 | gdb_assert (function || !readbuf); |
7a076fd2 | 6122 | if (mips_debug) |
6a3a010b MR |
6123 | switch (fval_reg) |
6124 | { | |
6125 | case mips_fval_fpr: | |
6126 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
6127 | break; | |
6128 | case mips_fval_gpr: | |
6129 | fprintf_unfiltered (gdb_stderr, "Return float in $2\n"); | |
6130 | break; | |
6131 | case mips_fval_both: | |
6132 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n"); | |
6133 | break; | |
6134 | } | |
6135 | if (fval_reg != mips_fval_gpr) | |
6136 | mips_xfer_register (gdbarch, regcache, | |
6137 | (gdbarch_num_regs (gdbarch) | |
6138 | + mips_regnum (gdbarch)->fp0), | |
6139 | TYPE_LENGTH (type), | |
6140 | gdbarch_byte_order (gdbarch), | |
6141 | readbuf, writebuf, 0); | |
6142 | if (fval_reg != mips_fval_fpr) | |
6143 | mips_xfer_register (gdbarch, regcache, | |
6144 | gdbarch_num_regs (gdbarch) + 2, | |
6145 | TYPE_LENGTH (type), | |
6146 | gdbarch_byte_order (gdbarch), | |
6147 | readbuf, writebuf, 0); | |
7a076fd2 FF |
6148 | return RETURN_VALUE_REGISTER_CONVENTION; |
6149 | } | |
6150 | else | |
6151 | { | |
6152 | /* A scalar extract each part but least-significant-byte | |
dda83cd7 | 6153 | justified. */ |
7a076fd2 FF |
6154 | int offset; |
6155 | int regnum; | |
6156 | for (offset = 0, regnum = MIPS_V0_REGNUM; | |
6157 | offset < TYPE_LENGTH (type); | |
1a69e1e4 | 6158 | offset += MIPS64_REGSIZE, regnum++) |
7a076fd2 | 6159 | { |
1a69e1e4 | 6160 | int xfer = MIPS64_REGSIZE; |
7a076fd2 FF |
6161 | if (offset + xfer > TYPE_LENGTH (type)) |
6162 | xfer = TYPE_LENGTH (type) - offset; | |
6163 | if (mips_debug) | |
6164 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
6165 | offset, xfer, regnum); | |
ba32f989 DJ |
6166 | mips_xfer_register (gdbarch, regcache, |
6167 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 6168 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 6169 | readbuf, writebuf, offset); |
7a076fd2 FF |
6170 | } |
6171 | return RETURN_VALUE_REGISTER_CONVENTION; | |
6172 | } | |
6d82d43b AC |
6173 | } |
6174 | ||
dd824b04 DJ |
6175 | /* Floating point register management. |
6176 | ||
6177 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
6178 | 64bit operations, these early MIPS cpus treat fp register pairs | |
6179 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
6180 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
6181 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
6182 | double precision floats into two 32-bit chunks and store them in | |
6183 | consecutive fp regs. To display 64-bit floats stored in this | |
6184 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
6185 | Throw in user-configurable endianness and you have a real mess. | |
6186 | ||
6187 | The way this works is: | |
6188 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
6189 | double-precision value will be split across two logical registers. | |
6190 | The lower-numbered logical register will hold the low-order bits, | |
6191 | regardless of the processor's endianness. | |
6192 | - If we are on a 64-bit processor, and we are looking for a | |
6193 | single-precision value, it will be in the low ordered bits | |
6194 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
6195 | save slot in memory. | |
6196 | - If we are in 64-bit mode, everything is straightforward. | |
6197 | ||
6198 | Note that this code only deals with "live" registers at the top of the | |
6199 | stack. We will attempt to deal with saved registers later, when | |
025bb325 | 6200 | the raw/cooked register interface is in place. (We need a general |
dd824b04 DJ |
6201 | interface that can deal with dynamic saved register sizes -- fp |
6202 | regs could be 32 bits wide in one frame and 64 on the frame above | |
6203 | and below). */ | |
6204 | ||
6205 | /* Copy a 32-bit single-precision value from the current frame | |
6206 | into rare_buffer. */ | |
6207 | ||
6208 | static void | |
e11c53d2 | 6209 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
47a35522 | 6210 | gdb_byte *rare_buffer) |
dd824b04 | 6211 | { |
72a155b4 UW |
6212 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6213 | int raw_size = register_size (gdbarch, regno); | |
224c3ddb | 6214 | gdb_byte *raw_buffer = (gdb_byte *) alloca (raw_size); |
dd824b04 | 6215 | |
ca9d61b9 | 6216 | if (!deprecated_frame_register_read (frame, regno, raw_buffer)) |
c9f4d572 | 6217 | error (_("can't read register %d (%s)"), |
72a155b4 | 6218 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
6219 | if (raw_size == 8) |
6220 | { | |
6221 | /* We have a 64-bit value for this register. Find the low-order | |
dda83cd7 | 6222 | 32 bits. */ |
dd824b04 DJ |
6223 | int offset; |
6224 | ||
72a155b4 | 6225 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 DJ |
6226 | offset = 4; |
6227 | else | |
6228 | offset = 0; | |
6229 | ||
6230 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
6231 | } | |
6232 | else | |
6233 | { | |
6234 | memcpy (rare_buffer, raw_buffer, 4); | |
6235 | } | |
6236 | } | |
6237 | ||
6238 | /* Copy a 64-bit double-precision value from the current frame into | |
6239 | rare_buffer. This may include getting half of it from the next | |
6240 | register. */ | |
6241 | ||
6242 | static void | |
e11c53d2 | 6243 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
47a35522 | 6244 | gdb_byte *rare_buffer) |
dd824b04 | 6245 | { |
72a155b4 UW |
6246 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6247 | int raw_size = register_size (gdbarch, regno); | |
dd824b04 | 6248 | |
9c9acae0 | 6249 | if (raw_size == 8 && !mips2_fp_compat (frame)) |
dd824b04 DJ |
6250 | { |
6251 | /* We have a 64-bit value for this register, and we should use | |
dda83cd7 | 6252 | all 64 bits. */ |
ca9d61b9 | 6253 | if (!deprecated_frame_register_read (frame, regno, rare_buffer)) |
c9f4d572 | 6254 | error (_("can't read register %d (%s)"), |
72a155b4 | 6255 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
6256 | } |
6257 | else | |
6258 | { | |
72a155b4 | 6259 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
82e91389 | 6260 | |
72a155b4 | 6261 | if ((rawnum - mips_regnum (gdbarch)->fp0) & 1) |
dd824b04 | 6262 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
6263 | _("mips_read_fp_register_double: bad access to " |
6264 | "odd-numbered FP register")); | |
dd824b04 DJ |
6265 | |
6266 | /* mips_read_fp_register_single will find the correct 32 bits from | |
dda83cd7 | 6267 | each register. */ |
72a155b4 | 6268 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 | 6269 | { |
e11c53d2 AC |
6270 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
6271 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 6272 | } |
361d1df0 | 6273 | else |
dd824b04 | 6274 | { |
e11c53d2 AC |
6275 | mips_read_fp_register_single (frame, regno, rare_buffer); |
6276 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
6277 | } |
6278 | } | |
6279 | } | |
6280 | ||
c906108c | 6281 | static void |
e11c53d2 AC |
6282 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
6283 | int regnum) | |
025bb325 | 6284 | { /* Do values for FP (float) regs. */ |
72a155b4 | 6285 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 6286 | gdb_byte *raw_buffer; |
8ba0dd51 UW |
6287 | std::string flt_str, dbl_str; |
6288 | ||
f69fdf9b UW |
6289 | const struct type *flt_type = builtin_type (gdbarch)->builtin_float; |
6290 | const struct type *dbl_type = builtin_type (gdbarch)->builtin_double; | |
c5aa993b | 6291 | |
224c3ddb SM |
6292 | raw_buffer |
6293 | = ((gdb_byte *) | |
6294 | alloca (2 * register_size (gdbarch, mips_regnum (gdbarch)->fp0))); | |
c906108c | 6295 | |
72a155b4 | 6296 | fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum)); |
c9f4d572 | 6297 | fprintf_filtered (file, "%*s", |
72a155b4 | 6298 | 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)), |
e11c53d2 | 6299 | ""); |
f0ef6b29 | 6300 | |
72a155b4 | 6301 | if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame)) |
c906108c | 6302 | { |
79a45b7d TT |
6303 | struct value_print_options opts; |
6304 | ||
f0ef6b29 | 6305 | /* 4-byte registers: Print hex and floating. Also print even |
dda83cd7 | 6306 | numbered registers as doubles. */ |
e11c53d2 | 6307 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
f69fdf9b | 6308 | flt_str = target_float_to_string (raw_buffer, flt_type, "%-17.9g"); |
c5aa993b | 6309 | |
79a45b7d | 6310 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
6311 | print_scalar_formatted (raw_buffer, |
6312 | builtin_type (gdbarch)->builtin_uint32, | |
6313 | &opts, 'w', file); | |
dd824b04 | 6314 | |
8ba0dd51 | 6315 | fprintf_filtered (file, " flt: %s", flt_str.c_str ()); |
1adad886 | 6316 | |
72a155b4 | 6317 | if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0) |
f0ef6b29 | 6318 | { |
e11c53d2 | 6319 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f69fdf9b | 6320 | dbl_str = target_float_to_string (raw_buffer, dbl_type, "%-24.17g"); |
1adad886 | 6321 | |
8ba0dd51 | 6322 | fprintf_filtered (file, " dbl: %s", dbl_str.c_str ()); |
f0ef6b29 | 6323 | } |
c906108c SS |
6324 | } |
6325 | else | |
dd824b04 | 6326 | { |
79a45b7d TT |
6327 | struct value_print_options opts; |
6328 | ||
f0ef6b29 | 6329 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 6330 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
f69fdf9b | 6331 | flt_str = target_float_to_string (raw_buffer, flt_type, "%-17.9g"); |
c906108c | 6332 | |
e11c53d2 | 6333 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f69fdf9b | 6334 | dbl_str = target_float_to_string (raw_buffer, dbl_type, "%-24.17g"); |
f0ef6b29 | 6335 | |
79a45b7d | 6336 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
6337 | print_scalar_formatted (raw_buffer, |
6338 | builtin_type (gdbarch)->builtin_uint64, | |
6339 | &opts, 'g', file); | |
f0ef6b29 | 6340 | |
8ba0dd51 UW |
6341 | fprintf_filtered (file, " flt: %s", flt_str.c_str ()); |
6342 | fprintf_filtered (file, " dbl: %s", dbl_str.c_str ()); | |
f0ef6b29 KB |
6343 | } |
6344 | } | |
6345 | ||
6346 | static void | |
e11c53d2 | 6347 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
0cc93a06 | 6348 | int regnum) |
f0ef6b29 | 6349 | { |
a4b8ebc8 | 6350 | struct gdbarch *gdbarch = get_frame_arch (frame); |
79a45b7d | 6351 | struct value_print_options opts; |
de15c4ab | 6352 | struct value *val; |
1adad886 | 6353 | |
004159a2 | 6354 | if (mips_float_register_p (gdbarch, regnum)) |
f0ef6b29 | 6355 | { |
e11c53d2 | 6356 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
6357 | return; |
6358 | } | |
6359 | ||
de15c4ab | 6360 | val = get_frame_register_value (frame, regnum); |
f0ef6b29 | 6361 | |
72a155b4 | 6362 | fputs_filtered (gdbarch_register_name (gdbarch, regnum), file); |
f0ef6b29 KB |
6363 | |
6364 | /* The problem with printing numeric register names (r26, etc.) is that | |
6365 | the user can't use them on input. Probably the best solution is to | |
6366 | fix it so that either the numeric or the funky (a2, etc.) names | |
6367 | are accepted on input. */ | |
6368 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 6369 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 6370 | else |
e11c53d2 | 6371 | fprintf_filtered (file, ": "); |
f0ef6b29 | 6372 | |
79a45b7d | 6373 | get_formatted_print_options (&opts, 'x'); |
4dba70ee | 6374 | value_print_scalar_formatted (val, &opts, 0, file); |
c906108c SS |
6375 | } |
6376 | ||
1bab7383 YQ |
6377 | /* Print IEEE exception condition bits in FLAGS. */ |
6378 | ||
6379 | static void | |
6380 | print_fpu_flags (struct ui_file *file, int flags) | |
6381 | { | |
6382 | if (flags & (1 << 0)) | |
6383 | fputs_filtered (" inexact", file); | |
6384 | if (flags & (1 << 1)) | |
6385 | fputs_filtered (" uflow", file); | |
6386 | if (flags & (1 << 2)) | |
6387 | fputs_filtered (" oflow", file); | |
6388 | if (flags & (1 << 3)) | |
6389 | fputs_filtered (" div0", file); | |
6390 | if (flags & (1 << 4)) | |
6391 | fputs_filtered (" inval", file); | |
6392 | if (flags & (1 << 5)) | |
6393 | fputs_filtered (" unimp", file); | |
6394 | fputc_filtered ('\n', file); | |
6395 | } | |
6396 | ||
6397 | /* Print interesting information about the floating point processor | |
6398 | (if present) or emulator. */ | |
6399 | ||
6400 | static void | |
6401 | mips_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, | |
6402 | struct frame_info *frame, const char *args) | |
6403 | { | |
6404 | int fcsr = mips_regnum (gdbarch)->fp_control_status; | |
6405 | enum mips_fpu_type type = MIPS_FPU_TYPE (gdbarch); | |
6406 | ULONGEST fcs = 0; | |
6407 | int i; | |
6408 | ||
6409 | if (fcsr == -1 || !read_frame_register_unsigned (frame, fcsr, &fcs)) | |
6410 | type = MIPS_FPU_NONE; | |
6411 | ||
6412 | fprintf_filtered (file, "fpu type: %s\n", | |
6413 | type == MIPS_FPU_DOUBLE ? "double-precision" | |
6414 | : type == MIPS_FPU_SINGLE ? "single-precision" | |
6415 | : "none / unused"); | |
6416 | ||
6417 | if (type == MIPS_FPU_NONE) | |
6418 | return; | |
6419 | ||
6420 | fprintf_filtered (file, "reg size: %d bits\n", | |
6421 | register_size (gdbarch, mips_regnum (gdbarch)->fp0) * 8); | |
6422 | ||
6423 | fputs_filtered ("cond :", file); | |
6424 | if (fcs & (1 << 23)) | |
6425 | fputs_filtered (" 0", file); | |
6426 | for (i = 1; i <= 7; i++) | |
6427 | if (fcs & (1 << (24 + i))) | |
6428 | fprintf_filtered (file, " %d", i); | |
6429 | fputc_filtered ('\n', file); | |
6430 | ||
6431 | fputs_filtered ("cause :", file); | |
6432 | print_fpu_flags (file, (fcs >> 12) & 0x3f); | |
6433 | fputs ("mask :", stdout); | |
6434 | print_fpu_flags (file, (fcs >> 7) & 0x1f); | |
6435 | fputs ("flags :", stdout); | |
6436 | print_fpu_flags (file, (fcs >> 2) & 0x1f); | |
6437 | ||
6438 | fputs_filtered ("rounding: ", file); | |
6439 | switch (fcs & 3) | |
6440 | { | |
6441 | case 0: fputs_filtered ("nearest\n", file); break; | |
6442 | case 1: fputs_filtered ("zero\n", file); break; | |
6443 | case 2: fputs_filtered ("+inf\n", file); break; | |
6444 | case 3: fputs_filtered ("-inf\n", file); break; | |
6445 | } | |
6446 | ||
6447 | fputs_filtered ("flush :", file); | |
6448 | if (fcs & (1 << 21)) | |
6449 | fputs_filtered (" nearest", file); | |
6450 | if (fcs & (1 << 22)) | |
6451 | fputs_filtered (" override", file); | |
6452 | if (fcs & (1 << 24)) | |
6453 | fputs_filtered (" zero", file); | |
6454 | if ((fcs & (0xb << 21)) == 0) | |
6455 | fputs_filtered (" no", file); | |
6456 | fputc_filtered ('\n', file); | |
6457 | ||
6458 | fprintf_filtered (file, "nan2008 : %s\n", fcs & (1 << 18) ? "yes" : "no"); | |
6459 | fprintf_filtered (file, "abs2008 : %s\n", fcs & (1 << 19) ? "yes" : "no"); | |
6460 | fputc_filtered ('\n', file); | |
6461 | ||
6462 | default_print_float_info (gdbarch, file, frame, args); | |
6463 | } | |
6464 | ||
f0ef6b29 KB |
6465 | /* Replacement for generic do_registers_info. |
6466 | Print regs in pretty columns. */ | |
6467 | ||
6468 | static int | |
e11c53d2 AC |
6469 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
6470 | int regnum) | |
f0ef6b29 | 6471 | { |
e11c53d2 AC |
6472 | fprintf_filtered (file, " "); |
6473 | mips_print_fp_register (file, frame, regnum); | |
6474 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
6475 | return regnum + 1; |
6476 | } | |
6477 | ||
6478 | ||
025bb325 | 6479 | /* Print a row's worth of GP (int) registers, with name labels above. */ |
c906108c SS |
6480 | |
6481 | static int | |
e11c53d2 | 6482 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 6483 | int start_regnum) |
c906108c | 6484 | { |
a4b8ebc8 | 6485 | struct gdbarch *gdbarch = get_frame_arch (frame); |
025bb325 | 6486 | /* Do values for GP (int) regs. */ |
313c5961 AH |
6487 | const gdb_byte *raw_buffer; |
6488 | struct value *value; | |
025bb325 MS |
6489 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols |
6490 | per row. */ | |
c906108c | 6491 | int col, byte; |
a4b8ebc8 | 6492 | int regnum; |
c906108c | 6493 | |
025bb325 | 6494 | /* For GP registers, we print a separate row of names above the vals. */ |
a4b8ebc8 | 6495 | for (col = 0, regnum = start_regnum; |
f6efe3f8 | 6496 | col < ncols && regnum < gdbarch_num_cooked_regs (gdbarch); |
f57d151a | 6497 | regnum++) |
c906108c | 6498 | { |
72a155b4 | 6499 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 6500 | continue; /* unused register */ |
004159a2 | 6501 | if (mips_float_register_p (gdbarch, regnum)) |
025bb325 | 6502 | break; /* End the row: reached FP register. */ |
0cc93a06 | 6503 | /* Large registers are handled separately. */ |
72a155b4 | 6504 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
6505 | { |
6506 | if (col > 0) | |
6507 | break; /* End the row before this register. */ | |
6508 | ||
6509 | /* Print this register on a row by itself. */ | |
6510 | mips_print_register (file, frame, regnum); | |
6511 | fprintf_filtered (file, "\n"); | |
6512 | return regnum + 1; | |
6513 | } | |
d05f6826 DJ |
6514 | if (col == 0) |
6515 | fprintf_filtered (file, " "); | |
6d82d43b | 6516 | fprintf_filtered (file, |
72a155b4 UW |
6517 | mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s", |
6518 | gdbarch_register_name (gdbarch, regnum)); | |
c906108c SS |
6519 | col++; |
6520 | } | |
d05f6826 DJ |
6521 | |
6522 | if (col == 0) | |
6523 | return regnum; | |
6524 | ||
025bb325 | 6525 | /* Print the R0 to R31 names. */ |
72a155b4 | 6526 | if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS) |
f57d151a | 6527 | fprintf_filtered (file, "\n R%-4d", |
72a155b4 | 6528 | start_regnum % gdbarch_num_regs (gdbarch)); |
20e6603c AC |
6529 | else |
6530 | fprintf_filtered (file, "\n "); | |
c906108c | 6531 | |
025bb325 | 6532 | /* Now print the values in hex, 4 or 8 to the row. */ |
a4b8ebc8 | 6533 | for (col = 0, regnum = start_regnum; |
f6efe3f8 | 6534 | col < ncols && regnum < gdbarch_num_cooked_regs (gdbarch); |
f57d151a | 6535 | regnum++) |
c906108c | 6536 | { |
72a155b4 | 6537 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 6538 | continue; /* unused register */ |
004159a2 | 6539 | if (mips_float_register_p (gdbarch, regnum)) |
025bb325 | 6540 | break; /* End row: reached FP register. */ |
72a155b4 | 6541 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
6542 | break; /* End row: large register. */ |
6543 | ||
c906108c | 6544 | /* OK: get the data in raw format. */ |
313c5961 AH |
6545 | value = get_frame_register_value (frame, regnum); |
6546 | if (value_optimized_out (value) | |
6547 | || !value_entirely_available (value)) | |
325c9fd4 JB |
6548 | { |
6549 | fprintf_filtered (file, "%*s ", | |
6550 | (int) mips_abi_regsize (gdbarch) * 2, | |
6551 | (mips_abi_regsize (gdbarch) == 4 ? "<unavl>" | |
6552 | : "<unavailable>")); | |
6553 | col++; | |
6554 | continue; | |
6555 | } | |
313c5961 | 6556 | raw_buffer = value_contents_all (value); |
c906108c | 6557 | /* pad small registers */ |
4246e332 | 6558 | for (byte = 0; |
72a155b4 UW |
6559 | byte < (mips_abi_regsize (gdbarch) |
6560 | - register_size (gdbarch, regnum)); byte++) | |
428544e8 | 6561 | fprintf_filtered (file, " "); |
025bb325 | 6562 | /* Now print the register value in hex, endian order. */ |
72a155b4 | 6563 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b | 6564 | for (byte = |
72a155b4 UW |
6565 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
6566 | byte < register_size (gdbarch, regnum); byte++) | |
47a35522 | 6567 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
c906108c | 6568 | else |
72a155b4 | 6569 | for (byte = register_size (gdbarch, regnum) - 1; |
6d82d43b | 6570 | byte >= 0; byte--) |
47a35522 | 6571 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
e11c53d2 | 6572 | fprintf_filtered (file, " "); |
c906108c SS |
6573 | col++; |
6574 | } | |
025bb325 | 6575 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 6576 | fprintf_filtered (file, "\n"); |
c906108c SS |
6577 | |
6578 | return regnum; | |
6579 | } | |
6580 | ||
025bb325 | 6581 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */ |
c906108c | 6582 | |
bf1f5b4c | 6583 | static void |
e11c53d2 AC |
6584 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
6585 | struct frame_info *frame, int regnum, int all) | |
c906108c | 6586 | { |
025bb325 | 6587 | if (regnum != -1) /* Do one specified register. */ |
c906108c | 6588 | { |
72a155b4 UW |
6589 | gdb_assert (regnum >= gdbarch_num_regs (gdbarch)); |
6590 | if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
8a3fe4f8 | 6591 | error (_("Not a valid register for the current processor type")); |
c906108c | 6592 | |
0cc93a06 | 6593 | mips_print_register (file, frame, regnum); |
e11c53d2 | 6594 | fprintf_filtered (file, "\n"); |
c906108c | 6595 | } |
c5aa993b | 6596 | else |
025bb325 | 6597 | /* Do all (or most) registers. */ |
c906108c | 6598 | { |
72a155b4 | 6599 | regnum = gdbarch_num_regs (gdbarch); |
f6efe3f8 | 6600 | while (regnum < gdbarch_num_cooked_regs (gdbarch)) |
c906108c | 6601 | { |
004159a2 | 6602 | if (mips_float_register_p (gdbarch, regnum)) |
e11c53d2 | 6603 | { |
025bb325 | 6604 | if (all) /* True for "INFO ALL-REGISTERS" command. */ |
e11c53d2 AC |
6605 | regnum = print_fp_register_row (file, frame, regnum); |
6606 | else | |
025bb325 | 6607 | regnum += MIPS_NUMREGS; /* Skip floating point regs. */ |
e11c53d2 | 6608 | } |
c906108c | 6609 | else |
e11c53d2 | 6610 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
6611 | } |
6612 | } | |
6613 | } | |
6614 | ||
63807e1d | 6615 | static int |
3352ef37 AC |
6616 | mips_single_step_through_delay (struct gdbarch *gdbarch, |
6617 | struct frame_info *frame) | |
c906108c | 6618 | { |
3352ef37 | 6619 | CORE_ADDR pc = get_frame_pc (frame); |
4cc0665f MR |
6620 | enum mips_isa isa; |
6621 | ULONGEST insn; | |
4cc0665f MR |
6622 | int size; |
6623 | ||
6624 | if ((mips_pc_is_mips (pc) | |
ab50adb6 | 6625 | && !mips32_insn_at_pc_has_delay_slot (gdbarch, pc)) |
4cc0665f | 6626 | || (mips_pc_is_micromips (gdbarch, pc) |
ab50adb6 | 6627 | && !micromips_insn_at_pc_has_delay_slot (gdbarch, pc, 0)) |
4cc0665f | 6628 | || (mips_pc_is_mips16 (gdbarch, pc) |
ab50adb6 | 6629 | && !mips16_insn_at_pc_has_delay_slot (gdbarch, pc, 0))) |
06648491 MK |
6630 | return 0; |
6631 | ||
4cc0665f MR |
6632 | isa = mips_pc_isa (gdbarch, pc); |
6633 | /* _has_delay_slot above will have validated the read. */ | |
6634 | insn = mips_fetch_instruction (gdbarch, isa, pc, NULL); | |
6635 | size = mips_insn_size (isa, insn); | |
8b86c959 YQ |
6636 | |
6637 | const address_space *aspace = get_frame_address_space (frame); | |
6638 | ||
4cc0665f | 6639 | return breakpoint_here_p (aspace, pc + size) != no_breakpoint_here; |
c906108c SS |
6640 | } |
6641 | ||
6d82d43b AC |
6642 | /* To skip prologues, I use this predicate. Returns either PC itself |
6643 | if the code at PC does not look like a function prologue; otherwise | |
6644 | returns an address that (if we're lucky) follows the prologue. If | |
6645 | LENIENT, then we must skip everything which is involved in setting | |
6646 | up the frame (it's OK to skip more, just so long as we don't skip | |
6647 | anything which might clobber the registers which are being saved. | |
6648 | We must skip more in the case where part of the prologue is in the | |
6649 | delay slot of a non-prologue instruction). */ | |
6650 | ||
6651 | static CORE_ADDR | |
6093d2eb | 6652 | mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
6d82d43b | 6653 | { |
8b622e6a AC |
6654 | CORE_ADDR limit_pc; |
6655 | CORE_ADDR func_addr; | |
6656 | ||
6d82d43b AC |
6657 | /* See if we can determine the end of the prologue via the symbol table. |
6658 | If so, then return either PC, or the PC after the prologue, whichever | |
6659 | is greater. */ | |
8b622e6a AC |
6660 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
6661 | { | |
d80b854b UW |
6662 | CORE_ADDR post_prologue_pc |
6663 | = skip_prologue_using_sal (gdbarch, func_addr); | |
8b622e6a | 6664 | if (post_prologue_pc != 0) |
325fac50 | 6665 | return std::max (pc, post_prologue_pc); |
8b622e6a | 6666 | } |
6d82d43b AC |
6667 | |
6668 | /* Can't determine prologue from the symbol table, need to examine | |
6669 | instructions. */ | |
6670 | ||
98b4dd94 JB |
6671 | /* Find an upper limit on the function prologue using the debug |
6672 | information. If the debug information could not be used to provide | |
6673 | that bound, then use an arbitrary large number as the upper bound. */ | |
d80b854b | 6674 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
98b4dd94 JB |
6675 | if (limit_pc == 0) |
6676 | limit_pc = pc + 100; /* Magic. */ | |
6677 | ||
4cc0665f | 6678 | if (mips_pc_is_mips16 (gdbarch, pc)) |
e17a4113 | 6679 | return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
4cc0665f MR |
6680 | else if (mips_pc_is_micromips (gdbarch, pc)) |
6681 | return micromips_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); | |
6d82d43b | 6682 | else |
e17a4113 | 6683 | return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
88658117 AC |
6684 | } |
6685 | ||
c9cf6e20 MG |
6686 | /* Implement the stack_frame_destroyed_p gdbarch method (32-bit version). |
6687 | This is a helper function for mips_stack_frame_destroyed_p. */ | |
6688 | ||
97ab0fdd | 6689 | static int |
c9cf6e20 | 6690 | mips32_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
6691 | { |
6692 | CORE_ADDR func_addr = 0, func_end = 0; | |
6693 | ||
6694 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
6695 | { | |
6696 | /* The MIPS epilogue is max. 12 bytes long. */ | |
6697 | CORE_ADDR addr = func_end - 12; | |
6698 | ||
6699 | if (addr < func_addr + 4) | |
dda83cd7 | 6700 | addr = func_addr + 4; |
97ab0fdd | 6701 | if (pc < addr) |
dda83cd7 | 6702 | return 0; |
97ab0fdd MR |
6703 | |
6704 | for (; pc < func_end; pc += MIPS_INSN32_SIZE) | |
6705 | { | |
6706 | unsigned long high_word; | |
6707 | unsigned long inst; | |
6708 | ||
4cc0665f | 6709 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
97ab0fdd MR |
6710 | high_word = (inst >> 16) & 0xffff; |
6711 | ||
6712 | if (high_word != 0x27bd /* addiu $sp,$sp,offset */ | |
6713 | && high_word != 0x67bd /* daddiu $sp,$sp,offset */ | |
6714 | && inst != 0x03e00008 /* jr $ra */ | |
6715 | && inst != 0x00000000) /* nop */ | |
6716 | return 0; | |
6717 | } | |
6718 | ||
6719 | return 1; | |
6720 | } | |
6721 | ||
6722 | return 0; | |
6723 | } | |
6724 | ||
c9cf6e20 MG |
6725 | /* Implement the stack_frame_destroyed_p gdbarch method (microMIPS version). |
6726 | This is a helper function for mips_stack_frame_destroyed_p. */ | |
4cc0665f MR |
6727 | |
6728 | static int | |
c9cf6e20 | 6729 | micromips_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
4cc0665f MR |
6730 | { |
6731 | CORE_ADDR func_addr = 0; | |
6732 | CORE_ADDR func_end = 0; | |
6733 | CORE_ADDR addr; | |
6734 | ULONGEST insn; | |
6735 | long offset; | |
6736 | int dreg; | |
6737 | int sreg; | |
6738 | int loc; | |
6739 | ||
6740 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
6741 | return 0; | |
6742 | ||
6743 | /* The microMIPS epilogue is max. 12 bytes long. */ | |
6744 | addr = func_end - 12; | |
6745 | ||
6746 | if (addr < func_addr + 2) | |
6747 | addr = func_addr + 2; | |
6748 | if (pc < addr) | |
6749 | return 0; | |
6750 | ||
6751 | for (; pc < func_end; pc += loc) | |
6752 | { | |
6753 | loc = 0; | |
6754 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
6755 | loc += MIPS_INSN16_SIZE; | |
6756 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
6757 | { | |
4cc0665f MR |
6758 | /* 32-bit instructions. */ |
6759 | case 2 * MIPS_INSN16_SIZE: | |
6760 | insn <<= 16; | |
6761 | insn |= mips_fetch_instruction (gdbarch, | |
6762 | ISA_MICROMIPS, pc + loc, NULL); | |
6763 | loc += MIPS_INSN16_SIZE; | |
6764 | switch (micromips_op (insn >> 16)) | |
6765 | { | |
6766 | case 0xc: /* ADDIU: bits 001100 */ | |
6767 | case 0x17: /* DADDIU: bits 010111 */ | |
6768 | sreg = b0s5_reg (insn >> 16); | |
6769 | dreg = b5s5_reg (insn >> 16); | |
6770 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
6771 | if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM | |
6772 | /* (D)ADDIU $sp, imm */ | |
6773 | && offset >= 0) | |
6774 | break; | |
6775 | return 0; | |
6776 | ||
6777 | default: | |
6778 | return 0; | |
6779 | } | |
6780 | break; | |
6781 | ||
6782 | /* 16-bit instructions. */ | |
6783 | case MIPS_INSN16_SIZE: | |
6784 | switch (micromips_op (insn)) | |
6785 | { | |
6786 | case 0x3: /* MOVE: bits 000011 */ | |
6787 | sreg = b0s5_reg (insn); | |
6788 | dreg = b5s5_reg (insn); | |
6789 | if (sreg == 0 && dreg == 0) | |
6790 | /* MOVE $zero, $zero aka NOP */ | |
6791 | break; | |
6792 | return 0; | |
6793 | ||
6794 | case 0x11: /* POOL16C: bits 010001 */ | |
6795 | if (b5s5_op (insn) == 0x18 | |
6796 | /* JRADDIUSP: bits 010011 11000 */ | |
6797 | || (b5s5_op (insn) == 0xd | |
6798 | /* JRC: bits 010011 01101 */ | |
6799 | && b0s5_reg (insn) == MIPS_RA_REGNUM)) | |
6800 | /* JRC $ra */ | |
6801 | break; | |
6802 | return 0; | |
6803 | ||
6804 | case 0x13: /* POOL16D: bits 010011 */ | |
6805 | offset = micromips_decode_imm9 (b1s9_imm (insn)); | |
6806 | if ((insn & 0x1) == 0x1 | |
6807 | /* ADDIUSP: bits 010011 1 */ | |
6808 | && offset > 0) | |
6809 | break; | |
6810 | return 0; | |
6811 | ||
6812 | default: | |
6813 | return 0; | |
6814 | } | |
6815 | } | |
6816 | } | |
6817 | ||
6818 | return 1; | |
6819 | } | |
6820 | ||
c9cf6e20 MG |
6821 | /* Implement the stack_frame_destroyed_p gdbarch method (16-bit version). |
6822 | This is a helper function for mips_stack_frame_destroyed_p. */ | |
6823 | ||
97ab0fdd | 6824 | static int |
c9cf6e20 | 6825 | mips16_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
6826 | { |
6827 | CORE_ADDR func_addr = 0, func_end = 0; | |
6828 | ||
6829 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
6830 | { | |
6831 | /* The MIPS epilogue is max. 12 bytes long. */ | |
6832 | CORE_ADDR addr = func_end - 12; | |
6833 | ||
6834 | if (addr < func_addr + 4) | |
dda83cd7 | 6835 | addr = func_addr + 4; |
97ab0fdd | 6836 | if (pc < addr) |
dda83cd7 | 6837 | return 0; |
97ab0fdd MR |
6838 | |
6839 | for (; pc < func_end; pc += MIPS_INSN16_SIZE) | |
6840 | { | |
6841 | unsigned short inst; | |
6842 | ||
4cc0665f | 6843 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc, NULL); |
97ab0fdd MR |
6844 | |
6845 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
6846 | continue; | |
6847 | ||
6848 | if (inst != 0x6300 /* addiu $sp,offset */ | |
6849 | && inst != 0xfb00 /* daddiu $sp,$sp,offset */ | |
6850 | && inst != 0xe820 /* jr $ra */ | |
6851 | && inst != 0xe8a0 /* jrc $ra */ | |
6852 | && inst != 0x6500) /* nop */ | |
6853 | return 0; | |
6854 | } | |
6855 | ||
6856 | return 1; | |
6857 | } | |
6858 | ||
6859 | return 0; | |
6860 | } | |
6861 | ||
c9cf6e20 MG |
6862 | /* Implement the stack_frame_destroyed_p gdbarch method. |
6863 | ||
6864 | The epilogue is defined here as the area at the end of a function, | |
97ab0fdd | 6865 | after an instruction which destroys the function's stack frame. */ |
c9cf6e20 | 6866 | |
97ab0fdd | 6867 | static int |
c9cf6e20 | 6868 | mips_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd | 6869 | { |
4cc0665f | 6870 | if (mips_pc_is_mips16 (gdbarch, pc)) |
c9cf6e20 | 6871 | return mips16_stack_frame_destroyed_p (gdbarch, pc); |
4cc0665f | 6872 | else if (mips_pc_is_micromips (gdbarch, pc)) |
c9cf6e20 | 6873 | return micromips_stack_frame_destroyed_p (gdbarch, pc); |
97ab0fdd | 6874 | else |
c9cf6e20 | 6875 | return mips32_stack_frame_destroyed_p (gdbarch, pc); |
97ab0fdd MR |
6876 | } |
6877 | ||
c906108c SS |
6878 | /* Commands to show/set the MIPS FPU type. */ |
6879 | ||
c906108c | 6880 | static void |
bd4c9dfe | 6881 | show_mipsfpu_command (const char *args, int from_tty) |
c906108c | 6882 | { |
a121b7c1 | 6883 | const char *fpu; |
6ca0852e | 6884 | |
f5656ead | 6885 | if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips) |
6ca0852e UW |
6886 | { |
6887 | printf_unfiltered | |
6888 | ("The MIPS floating-point coprocessor is unknown " | |
6889 | "because the current architecture is not MIPS.\n"); | |
6890 | return; | |
6891 | } | |
6892 | ||
f5656ead | 6893 | switch (MIPS_FPU_TYPE (target_gdbarch ())) |
c906108c SS |
6894 | { |
6895 | case MIPS_FPU_SINGLE: | |
6896 | fpu = "single-precision"; | |
6897 | break; | |
6898 | case MIPS_FPU_DOUBLE: | |
6899 | fpu = "double-precision"; | |
6900 | break; | |
6901 | case MIPS_FPU_NONE: | |
6902 | fpu = "absent (none)"; | |
6903 | break; | |
93d56215 | 6904 | default: |
e2e0b3e5 | 6905 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c SS |
6906 | } |
6907 | if (mips_fpu_type_auto) | |
025bb325 MS |
6908 | printf_unfiltered ("The MIPS floating-point coprocessor " |
6909 | "is set automatically (currently %s)\n", | |
6910 | fpu); | |
c906108c | 6911 | else |
6d82d43b AC |
6912 | printf_unfiltered |
6913 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
6914 | } |
6915 | ||
6916 | ||
c906108c | 6917 | static void |
bd4c9dfe | 6918 | set_mipsfpu_single_command (const char *args, int from_tty) |
c906108c | 6919 | { |
8d5838b5 AC |
6920 | struct gdbarch_info info; |
6921 | gdbarch_info_init (&info); | |
c906108c SS |
6922 | mips_fpu_type = MIPS_FPU_SINGLE; |
6923 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
6924 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
6925 | instead of relying on globals. Doing that would let generic code | |
6926 | handle the search for this specific architecture. */ | |
6927 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 6928 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
6929 | } |
6930 | ||
c906108c | 6931 | static void |
bd4c9dfe | 6932 | set_mipsfpu_double_command (const char *args, int from_tty) |
c906108c | 6933 | { |
8d5838b5 AC |
6934 | struct gdbarch_info info; |
6935 | gdbarch_info_init (&info); | |
c906108c SS |
6936 | mips_fpu_type = MIPS_FPU_DOUBLE; |
6937 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
6938 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
6939 | instead of relying on globals. Doing that would let generic code | |
6940 | handle the search for this specific architecture. */ | |
6941 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 6942 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
6943 | } |
6944 | ||
c906108c | 6945 | static void |
bd4c9dfe | 6946 | set_mipsfpu_none_command (const char *args, int from_tty) |
c906108c | 6947 | { |
8d5838b5 AC |
6948 | struct gdbarch_info info; |
6949 | gdbarch_info_init (&info); | |
c906108c SS |
6950 | mips_fpu_type = MIPS_FPU_NONE; |
6951 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
6952 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
6953 | instead of relying on globals. Doing that would let generic code | |
6954 | handle the search for this specific architecture. */ | |
6955 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 6956 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
6957 | } |
6958 | ||
c906108c | 6959 | static void |
bd4c9dfe | 6960 | set_mipsfpu_auto_command (const char *args, int from_tty) |
c906108c SS |
6961 | { |
6962 | mips_fpu_type_auto = 1; | |
6963 | } | |
6964 | ||
c906108c SS |
6965 | /* Just like reinit_frame_cache, but with the right arguments to be |
6966 | callable as an sfunc. */ | |
6967 | ||
6968 | static void | |
eb4c3f4a | 6969 | reinit_frame_cache_sfunc (const char *args, int from_tty, |
acdb74a0 | 6970 | struct cmd_list_element *c) |
c906108c SS |
6971 | { |
6972 | reinit_frame_cache (); | |
6973 | } | |
6974 | ||
a89aa300 AC |
6975 | static int |
6976 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 6977 | { |
e47ad6c0 YQ |
6978 | gdb_disassembler *di |
6979 | = static_cast<gdb_disassembler *>(info->application_data); | |
6980 | struct gdbarch *gdbarch = di->arch (); | |
4cc0665f | 6981 | |
d31431ed AC |
6982 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
6983 | disassembler needs to be able to locally determine the ISA, and | |
6984 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
6985 | work. */ | |
4cc0665f | 6986 | if (mips_pc_is_mips16 (gdbarch, memaddr)) |
ec4045ea | 6987 | info->mach = bfd_mach_mips16; |
4cc0665f MR |
6988 | else if (mips_pc_is_micromips (gdbarch, memaddr)) |
6989 | info->mach = bfd_mach_mips_micromips; | |
c906108c SS |
6990 | |
6991 | /* Round down the instruction address to the appropriate boundary. */ | |
4cc0665f MR |
6992 | memaddr &= (info->mach == bfd_mach_mips16 |
6993 | || info->mach == bfd_mach_mips_micromips) ? ~1 : ~3; | |
c5aa993b | 6994 | |
6394c606 | 6995 | return default_print_insn (memaddr, info); |
c906108c SS |
6996 | } |
6997 | ||
cd6c3b4f YQ |
6998 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ |
6999 | ||
d19280ad YQ |
7000 | static int |
7001 | mips_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
c906108c | 7002 | { |
4cc0665f MR |
7003 | CORE_ADDR pc = *pcptr; |
7004 | ||
d19280ad | 7005 | if (mips_pc_is_mips16 (gdbarch, pc)) |
c906108c | 7006 | { |
d19280ad YQ |
7007 | *pcptr = unmake_compact_addr (pc); |
7008 | return MIPS_BP_KIND_MIPS16; | |
7009 | } | |
7010 | else if (mips_pc_is_micromips (gdbarch, pc)) | |
7011 | { | |
7012 | ULONGEST insn; | |
7013 | int status; | |
c906108c | 7014 | |
d19280ad YQ |
7015 | *pcptr = unmake_compact_addr (pc); |
7016 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status); | |
7017 | if (status || (mips_insn_size (ISA_MICROMIPS, insn) == 2)) | |
7018 | return MIPS_BP_KIND_MICROMIPS16; | |
7019 | else | |
7020 | return MIPS_BP_KIND_MICROMIPS32; | |
c906108c SS |
7021 | } |
7022 | else | |
d19280ad YQ |
7023 | return MIPS_BP_KIND_MIPS32; |
7024 | } | |
7025 | ||
cd6c3b4f YQ |
7026 | /* Implement the sw_breakpoint_from_kind gdbarch method. */ |
7027 | ||
d19280ad YQ |
7028 | static const gdb_byte * |
7029 | mips_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) | |
7030 | { | |
7031 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
7032 | ||
7033 | switch (kind) | |
c906108c | 7034 | { |
d19280ad YQ |
7035 | case MIPS_BP_KIND_MIPS16: |
7036 | { | |
7037 | static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; | |
7038 | static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; | |
7039 | ||
7040 | *size = 2; | |
7041 | if (byte_order_for_code == BFD_ENDIAN_BIG) | |
7042 | return mips16_big_breakpoint; | |
7043 | else | |
c906108c | 7044 | return mips16_little_breakpoint; |
d19280ad YQ |
7045 | } |
7046 | case MIPS_BP_KIND_MICROMIPS16: | |
7047 | { | |
7048 | static gdb_byte micromips16_big_breakpoint[] = { 0x46, 0x85 }; | |
7049 | static gdb_byte micromips16_little_breakpoint[] = { 0x85, 0x46 }; | |
7050 | ||
7051 | *size = 2; | |
7052 | ||
7053 | if (byte_order_for_code == BFD_ENDIAN_BIG) | |
7054 | return micromips16_big_breakpoint; | |
7055 | else | |
7056 | return micromips16_little_breakpoint; | |
7057 | } | |
7058 | case MIPS_BP_KIND_MICROMIPS32: | |
7059 | { | |
7060 | static gdb_byte micromips32_big_breakpoint[] = { 0, 0x5, 0, 0x7 }; | |
7061 | static gdb_byte micromips32_little_breakpoint[] = { 0x5, 0, 0x7, 0 }; | |
7062 | ||
7063 | *size = 4; | |
7064 | if (byte_order_for_code == BFD_ENDIAN_BIG) | |
7065 | return micromips32_big_breakpoint; | |
7066 | else | |
7067 | return micromips32_little_breakpoint; | |
7068 | } | |
7069 | case MIPS_BP_KIND_MIPS32: | |
7070 | { | |
7071 | static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; | |
7072 | static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; | |
c906108c | 7073 | |
d19280ad YQ |
7074 | *size = 4; |
7075 | if (byte_order_for_code == BFD_ENDIAN_BIG) | |
7076 | return big_breakpoint; | |
7077 | else | |
7e3d947d | 7078 | return little_breakpoint; |
d19280ad YQ |
7079 | } |
7080 | default: | |
7081 | gdb_assert_not_reached ("unexpected mips breakpoint kind"); | |
7082 | }; | |
c906108c SS |
7083 | } |
7084 | ||
ab50adb6 MR |
7085 | /* Return non-zero if the standard MIPS instruction INST has a branch |
7086 | delay slot (i.e. it is a jump or branch instruction). This function | |
7087 | is based on mips32_next_pc. */ | |
c8cef75f MR |
7088 | |
7089 | static int | |
ab50adb6 | 7090 | mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, ULONGEST inst) |
c8cef75f | 7091 | { |
c8cef75f | 7092 | int op; |
a385295e MR |
7093 | int rs; |
7094 | int rt; | |
c8cef75f | 7095 | |
c8cef75f MR |
7096 | op = itype_op (inst); |
7097 | if ((inst & 0xe0000000) != 0) | |
a385295e MR |
7098 | { |
7099 | rs = itype_rs (inst); | |
7100 | rt = itype_rt (inst); | |
f94363d7 AP |
7101 | return (is_octeon_bbit_op (op, gdbarch) |
7102 | || op >> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ | |
a385295e MR |
7103 | || op == 29 /* JALX: bits 011101 */ |
7104 | || (op == 17 | |
7105 | && (rs == 8 | |
c8cef75f | 7106 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
a385295e MR |
7107 | || (rs == 9 && (rt & 0x2) == 0) |
7108 | /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */ | |
7109 | || (rs == 10 && (rt & 0x2) == 0)))); | |
7110 | /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */ | |
7111 | } | |
c8cef75f MR |
7112 | else |
7113 | switch (op & 0x07) /* extract bits 28,27,26 */ | |
7114 | { | |
7115 | case 0: /* SPECIAL */ | |
7116 | op = rtype_funct (inst); | |
7117 | return (op == 8 /* JR */ | |
7118 | || op == 9); /* JALR */ | |
7119 | break; /* end SPECIAL */ | |
7120 | case 1: /* REGIMM */ | |
a385295e MR |
7121 | rs = itype_rs (inst); |
7122 | rt = itype_rt (inst); /* branch condition */ | |
7123 | return ((rt & 0xc) == 0 | |
c8cef75f MR |
7124 | /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */ |
7125 | /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */ | |
a385295e MR |
7126 | || ((rt & 0x1e) == 0x1c && rs == 0)); |
7127 | /* BPOSGE32, BPOSGE64: bits 1110x */ | |
c8cef75f MR |
7128 | break; /* end REGIMM */ |
7129 | default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */ | |
7130 | return 1; | |
7131 | break; | |
7132 | } | |
7133 | } | |
7134 | ||
ab50adb6 MR |
7135 | /* Return non-zero if a standard MIPS instruction at ADDR has a branch |
7136 | delay slot (i.e. it is a jump or branch instruction). */ | |
c8cef75f | 7137 | |
4cc0665f | 7138 | static int |
ab50adb6 | 7139 | mips32_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr) |
4cc0665f MR |
7140 | { |
7141 | ULONGEST insn; | |
7142 | int status; | |
7143 | ||
ab50adb6 | 7144 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, addr, &status); |
4cc0665f MR |
7145 | if (status) |
7146 | return 0; | |
7147 | ||
ab50adb6 MR |
7148 | return mips32_instruction_has_delay_slot (gdbarch, insn); |
7149 | } | |
4cc0665f | 7150 | |
ab50adb6 MR |
7151 | /* Return non-zero if the microMIPS instruction INSN, comprising the |
7152 | 16-bit major opcode word in the high 16 bits and any second word | |
7153 | in the low 16 bits, has a branch delay slot (i.e. it is a non-compact | |
7154 | jump or branch instruction). The instruction must be 32-bit if | |
7155 | MUSTBE32 is set or can be any instruction otherwise. */ | |
7156 | ||
7157 | static int | |
7158 | micromips_instruction_has_delay_slot (ULONGEST insn, int mustbe32) | |
7159 | { | |
7160 | ULONGEST major = insn >> 16; | |
4cc0665f | 7161 | |
ab50adb6 MR |
7162 | switch (micromips_op (major)) |
7163 | { | |
7164 | /* 16-bit instructions. */ | |
7165 | case 0x33: /* B16: bits 110011 */ | |
7166 | case 0x2b: /* BNEZ16: bits 101011 */ | |
7167 | case 0x23: /* BEQZ16: bits 100011 */ | |
7168 | return !mustbe32; | |
7169 | case 0x11: /* POOL16C: bits 010001 */ | |
7170 | return (!mustbe32 | |
7171 | && ((b5s5_op (major) == 0xc | |
7172 | /* JR16: bits 010001 01100 */ | |
7173 | || (b5s5_op (major) & 0x1e) == 0xe))); | |
7174 | /* JALR16, JALRS16: bits 010001 0111x */ | |
7175 | /* 32-bit instructions. */ | |
7176 | case 0x3d: /* JAL: bits 111101 */ | |
7177 | case 0x3c: /* JALX: bits 111100 */ | |
7178 | case 0x35: /* J: bits 110101 */ | |
7179 | case 0x2d: /* BNE: bits 101101 */ | |
7180 | case 0x25: /* BEQ: bits 100101 */ | |
7181 | case 0x1d: /* JALS: bits 011101 */ | |
7182 | return 1; | |
7183 | case 0x10: /* POOL32I: bits 010000 */ | |
7184 | return ((b5s5_op (major) & 0x1c) == 0x0 | |
4cc0665f | 7185 | /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */ |
ab50adb6 | 7186 | || (b5s5_op (major) & 0x1d) == 0x4 |
4cc0665f | 7187 | /* BLEZ, BGTZ: bits 010000 001x0 */ |
ab50adb6 | 7188 | || (b5s5_op (major) & 0x1d) == 0x11 |
4cc0665f | 7189 | /* BLTZALS, BGEZALS: bits 010000 100x1 */ |
ab50adb6 MR |
7190 | || ((b5s5_op (major) & 0x1e) == 0x14 |
7191 | && (major & 0x3) == 0x0) | |
4cc0665f | 7192 | /* BC2F, BC2T: bits 010000 1010x xxx00 */ |
ab50adb6 | 7193 | || (b5s5_op (major) & 0x1e) == 0x1a |
4cc0665f | 7194 | /* BPOSGE64, BPOSGE32: bits 010000 1101x */ |
ab50adb6 MR |
7195 | || ((b5s5_op (major) & 0x1e) == 0x1c |
7196 | && (major & 0x3) == 0x0) | |
4cc0665f | 7197 | /* BC1F, BC1T: bits 010000 1110x xxx00 */ |
ab50adb6 MR |
7198 | || ((b5s5_op (major) & 0x1c) == 0x1c |
7199 | && (major & 0x3) == 0x1)); | |
4cc0665f | 7200 | /* BC1ANY*: bits 010000 111xx xxx01 */ |
ab50adb6 MR |
7201 | case 0x0: /* POOL32A: bits 000000 */ |
7202 | return (b0s6_op (insn) == 0x3c | |
7203 | /* POOL32Axf: bits 000000 ... 111100 */ | |
7204 | && (b6s10_ext (insn) & 0x2bf) == 0x3c); | |
7205 | /* JALR, JALR.HB: 000000 000x111100 111100 */ | |
7206 | /* JALRS, JALRS.HB: 000000 010x111100 111100 */ | |
7207 | default: | |
7208 | return 0; | |
7209 | } | |
4cc0665f MR |
7210 | } |
7211 | ||
ab50adb6 | 7212 | /* Return non-zero if a microMIPS instruction at ADDR has a branch delay |
ae790652 MR |
7213 | slot (i.e. it is a non-compact jump instruction). The instruction |
7214 | must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */ | |
7215 | ||
c8cef75f | 7216 | static int |
ab50adb6 MR |
7217 | micromips_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, |
7218 | CORE_ADDR addr, int mustbe32) | |
c8cef75f | 7219 | { |
ab50adb6 | 7220 | ULONGEST insn; |
c8cef75f | 7221 | int status; |
3f7f3650 | 7222 | int size; |
c8cef75f | 7223 | |
ab50adb6 | 7224 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status); |
c8cef75f MR |
7225 | if (status) |
7226 | return 0; | |
3f7f3650 | 7227 | size = mips_insn_size (ISA_MICROMIPS, insn); |
ab50adb6 | 7228 | insn <<= 16; |
3f7f3650 | 7229 | if (size == 2 * MIPS_INSN16_SIZE) |
ab50adb6 MR |
7230 | { |
7231 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status); | |
7232 | if (status) | |
7233 | return 0; | |
7234 | } | |
7235 | ||
7236 | return micromips_instruction_has_delay_slot (insn, mustbe32); | |
7237 | } | |
c8cef75f | 7238 | |
ab50adb6 MR |
7239 | /* Return non-zero if the MIPS16 instruction INST, which must be |
7240 | a 32-bit instruction if MUSTBE32 is set or can be any instruction | |
7241 | otherwise, has a branch delay slot (i.e. it is a non-compact jump | |
7242 | instruction). This function is based on mips16_next_pc. */ | |
7243 | ||
7244 | static int | |
7245 | mips16_instruction_has_delay_slot (unsigned short inst, int mustbe32) | |
7246 | { | |
ae790652 MR |
7247 | if ((inst & 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */ |
7248 | return !mustbe32; | |
c8cef75f MR |
7249 | return (inst & 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */ |
7250 | } | |
7251 | ||
ab50adb6 MR |
7252 | /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay |
7253 | slot (i.e. it is a non-compact jump instruction). The instruction | |
7254 | must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */ | |
7255 | ||
7256 | static int | |
7257 | mips16_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, | |
7258 | CORE_ADDR addr, int mustbe32) | |
7259 | { | |
7260 | unsigned short insn; | |
7261 | int status; | |
7262 | ||
7263 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS16, addr, &status); | |
7264 | if (status) | |
7265 | return 0; | |
7266 | ||
7267 | return mips16_instruction_has_delay_slot (insn, mustbe32); | |
7268 | } | |
7269 | ||
c8cef75f MR |
7270 | /* Calculate the starting address of the MIPS memory segment BPADDR is in. |
7271 | This assumes KSSEG exists. */ | |
7272 | ||
7273 | static CORE_ADDR | |
7274 | mips_segment_boundary (CORE_ADDR bpaddr) | |
7275 | { | |
7276 | CORE_ADDR mask = CORE_ADDR_MAX; | |
7277 | int segsize; | |
7278 | ||
7279 | if (sizeof (CORE_ADDR) == 8) | |
7280 | /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid | |
7281 | a compiler warning produced where CORE_ADDR is a 32-bit type even | |
7282 | though in that case this is dead code). */ | |
7283 | switch (bpaddr >> ((sizeof (CORE_ADDR) << 3) - 2) & 3) | |
7284 | { | |
7285 | case 3: | |
7286 | if (bpaddr == (bfd_signed_vma) (int32_t) bpaddr) | |
7287 | segsize = 29; /* 32-bit compatibility segment */ | |
7288 | else | |
7289 | segsize = 62; /* xkseg */ | |
7290 | break; | |
7291 | case 2: /* xkphys */ | |
7292 | segsize = 59; | |
7293 | break; | |
7294 | default: /* xksseg (1), xkuseg/kuseg (0) */ | |
7295 | segsize = 62; | |
7296 | break; | |
7297 | } | |
7298 | else if (bpaddr & 0x80000000) /* kernel segment */ | |
7299 | segsize = 29; | |
7300 | else | |
7301 | segsize = 31; /* user segment */ | |
7302 | mask <<= segsize; | |
7303 | return bpaddr & mask; | |
7304 | } | |
7305 | ||
7306 | /* Move the breakpoint at BPADDR out of any branch delay slot by shifting | |
7307 | it backwards if necessary. Return the address of the new location. */ | |
7308 | ||
7309 | static CORE_ADDR | |
7310 | mips_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) | |
7311 | { | |
22e048c9 | 7312 | CORE_ADDR prev_addr; |
c8cef75f MR |
7313 | CORE_ADDR boundary; |
7314 | CORE_ADDR func_addr; | |
7315 | ||
7316 | /* If a breakpoint is set on the instruction in a branch delay slot, | |
7317 | GDB gets confused. When the breakpoint is hit, the PC isn't on | |
7318 | the instruction in the branch delay slot, the PC will point to | |
7319 | the branch instruction. Since the PC doesn't match any known | |
7320 | breakpoints, GDB reports a trap exception. | |
7321 | ||
7322 | There are two possible fixes for this problem. | |
7323 | ||
7324 | 1) When the breakpoint gets hit, see if the BD bit is set in the | |
7325 | Cause register (which indicates the last exception occurred in a | |
7326 | branch delay slot). If the BD bit is set, fix the PC to point to | |
7327 | the instruction in the branch delay slot. | |
7328 | ||
7329 | 2) When the user sets the breakpoint, don't allow him to set the | |
7330 | breakpoint on the instruction in the branch delay slot. Instead | |
7331 | move the breakpoint to the branch instruction (which will have | |
7332 | the same result). | |
7333 | ||
7334 | The problem with the first solution is that if the user then | |
7335 | single-steps the processor, the branch instruction will get | |
7336 | skipped (since GDB thinks the PC is on the instruction in the | |
7337 | branch delay slot). | |
7338 | ||
7339 | So, we'll use the second solution. To do this we need to know if | |
7340 | the instruction we're trying to set the breakpoint on is in the | |
7341 | branch delay slot. */ | |
7342 | ||
7343 | boundary = mips_segment_boundary (bpaddr); | |
7344 | ||
7345 | /* Make sure we don't scan back before the beginning of the current | |
7346 | function, since we may fetch constant data or insns that look like | |
7347 | a jump. Of course we might do that anyway if the compiler has | |
7348 | moved constants inline. :-( */ | |
7349 | if (find_pc_partial_function (bpaddr, NULL, &func_addr, NULL) | |
7350 | && func_addr > boundary && func_addr <= bpaddr) | |
7351 | boundary = func_addr; | |
7352 | ||
4cc0665f | 7353 | if (mips_pc_is_mips (bpaddr)) |
c8cef75f MR |
7354 | { |
7355 | if (bpaddr == boundary) | |
7356 | return bpaddr; | |
7357 | ||
7358 | /* If the previous instruction has a branch delay slot, we have | |
dda83cd7 | 7359 | to move the breakpoint to the branch instruction. */ |
c8cef75f | 7360 | prev_addr = bpaddr - 4; |
ab50adb6 | 7361 | if (mips32_insn_at_pc_has_delay_slot (gdbarch, prev_addr)) |
c8cef75f MR |
7362 | bpaddr = prev_addr; |
7363 | } | |
7364 | else | |
7365 | { | |
ab50adb6 | 7366 | int (*insn_at_pc_has_delay_slot) (struct gdbarch *, CORE_ADDR, int); |
c8cef75f MR |
7367 | CORE_ADDR addr, jmpaddr; |
7368 | int i; | |
7369 | ||
4cc0665f | 7370 | boundary = unmake_compact_addr (boundary); |
c8cef75f MR |
7371 | |
7372 | /* The only MIPS16 instructions with delay slots are JAL, JALX, | |
dda83cd7 SM |
7373 | JALR and JR. An absolute JAL/JALX is always 4 bytes long, |
7374 | so try for that first, then try the 2 byte JALR/JR. | |
7375 | The microMIPS ASE has a whole range of jumps and branches | |
7376 | with delay slots, some of which take 4 bytes and some take | |
7377 | 2 bytes, so the idea is the same. | |
7378 | FIXME: We have to assume that bpaddr is not the second half | |
7379 | of an extended instruction. */ | |
ab50adb6 MR |
7380 | insn_at_pc_has_delay_slot = (mips_pc_is_micromips (gdbarch, bpaddr) |
7381 | ? micromips_insn_at_pc_has_delay_slot | |
7382 | : mips16_insn_at_pc_has_delay_slot); | |
c8cef75f MR |
7383 | |
7384 | jmpaddr = 0; | |
7385 | addr = bpaddr; | |
7386 | for (i = 1; i < 4; i++) | |
7387 | { | |
4cc0665f | 7388 | if (unmake_compact_addr (addr) == boundary) |
c8cef75f | 7389 | break; |
4cc0665f | 7390 | addr -= MIPS_INSN16_SIZE; |
ab50adb6 | 7391 | if (i == 1 && insn_at_pc_has_delay_slot (gdbarch, addr, 0)) |
c8cef75f MR |
7392 | /* Looks like a JR/JALR at [target-1], but it could be |
7393 | the second word of a previous JAL/JALX, so record it | |
7394 | and check back one more. */ | |
7395 | jmpaddr = addr; | |
ab50adb6 | 7396 | else if (i > 1 && insn_at_pc_has_delay_slot (gdbarch, addr, 1)) |
c8cef75f MR |
7397 | { |
7398 | if (i == 2) | |
7399 | /* Looks like a JAL/JALX at [target-2], but it could also | |
7400 | be the second word of a previous JAL/JALX, record it, | |
7401 | and check back one more. */ | |
7402 | jmpaddr = addr; | |
7403 | else | |
7404 | /* Looks like a JAL/JALX at [target-3], so any previously | |
7405 | recorded JAL/JALX or JR/JALR must be wrong, because: | |
7406 | ||
7407 | >-3: JAL | |
7408 | -2: JAL-ext (can't be JAL/JALX) | |
7409 | -1: bdslot (can't be JR/JALR) | |
7410 | 0: target insn | |
7411 | ||
7412 | Of course it could be another JAL-ext which looks | |
7413 | like a JAL, but in that case we'd have broken out | |
7414 | of this loop at [target-2]: | |
7415 | ||
7416 | -4: JAL | |
7417 | >-3: JAL-ext | |
7418 | -2: bdslot (can't be jmp) | |
7419 | -1: JR/JALR | |
7420 | 0: target insn */ | |
7421 | jmpaddr = 0; | |
7422 | } | |
7423 | else | |
7424 | { | |
7425 | /* Not a jump instruction: if we're at [target-1] this | |
dda83cd7 SM |
7426 | could be the second word of a JAL/JALX, so continue; |
7427 | otherwise we're done. */ | |
c8cef75f MR |
7428 | if (i > 1) |
7429 | break; | |
7430 | } | |
7431 | } | |
7432 | ||
7433 | if (jmpaddr) | |
7434 | bpaddr = jmpaddr; | |
7435 | } | |
7436 | ||
7437 | return bpaddr; | |
7438 | } | |
7439 | ||
14132e89 MR |
7440 | /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16 |
7441 | call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */ | |
7442 | ||
7443 | static int | |
7444 | mips_is_stub_suffix (const char *suffix, int zero) | |
7445 | { | |
7446 | switch (suffix[0]) | |
7447 | { | |
7448 | case '0': | |
7449 | return zero && suffix[1] == '\0'; | |
7450 | case '1': | |
7451 | return suffix[1] == '\0' || (suffix[1] == '0' && suffix[2] == '\0'); | |
7452 | case '2': | |
7453 | case '5': | |
7454 | case '6': | |
7455 | case '9': | |
7456 | return suffix[1] == '\0'; | |
7457 | default: | |
7458 | return 0; | |
7459 | } | |
7460 | } | |
7461 | ||
7462 | /* Return non-zero if MODE is one of the mode infixes used for MIPS16 | |
7463 | call stubs, one of sf, df, sc, or dc. */ | |
7464 | ||
7465 | static int | |
7466 | mips_is_stub_mode (const char *mode) | |
7467 | { | |
7468 | return ((mode[0] == 's' || mode[0] == 'd') | |
7469 | && (mode[1] == 'f' || mode[1] == 'c')); | |
7470 | } | |
7471 | ||
7472 | /* Code at PC is a compiler-generated stub. Such a stub for a function | |
7473 | bar might have a name like __fn_stub_bar, and might look like this: | |
7474 | ||
7475 | mfc1 $4, $f13 | |
7476 | mfc1 $5, $f12 | |
7477 | mfc1 $6, $f15 | |
7478 | mfc1 $7, $f14 | |
7479 | ||
7480 | followed by (or interspersed with): | |
7481 | ||
7482 | j bar | |
7483 | ||
7484 | or: | |
7485 | ||
7486 | lui $25, %hi(bar) | |
7487 | addiu $25, $25, %lo(bar) | |
7488 | jr $25 | |
7489 | ||
7490 | ($1 may be used in old code; for robustness we accept any register) | |
7491 | or, in PIC code: | |
7492 | ||
7493 | lui $28, %hi(_gp_disp) | |
7494 | addiu $28, $28, %lo(_gp_disp) | |
7495 | addu $28, $28, $25 | |
7496 | lw $25, %got(bar) | |
7497 | addiu $25, $25, %lo(bar) | |
7498 | jr $25 | |
7499 | ||
7500 | In the case of a __call_stub_bar stub, the sequence to set up | |
7501 | arguments might look like this: | |
7502 | ||
7503 | mtc1 $4, $f13 | |
7504 | mtc1 $5, $f12 | |
7505 | mtc1 $6, $f15 | |
7506 | mtc1 $7, $f14 | |
7507 | ||
7508 | followed by (or interspersed with) one of the jump sequences above. | |
7509 | ||
7510 | In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead | |
7511 | of J or JR, respectively, followed by: | |
7512 | ||
7513 | mfc1 $2, $f0 | |
7514 | mfc1 $3, $f1 | |
7515 | jr $18 | |
7516 | ||
7517 | We are at the beginning of the stub here, and scan down and extract | |
7518 | the target address from the jump immediate instruction or, if a jump | |
7519 | register instruction is used, from the register referred. Return | |
7520 | the value of PC calculated or 0 if inconclusive. | |
7521 | ||
7522 | The limit on the search is arbitrarily set to 20 instructions. FIXME. */ | |
7523 | ||
7524 | static CORE_ADDR | |
7525 | mips_get_mips16_fn_stub_pc (struct frame_info *frame, CORE_ADDR pc) | |
7526 | { | |
7527 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
7528 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
7529 | int addrreg = MIPS_ZERO_REGNUM; | |
7530 | CORE_ADDR start_pc = pc; | |
7531 | CORE_ADDR target_pc = 0; | |
7532 | CORE_ADDR addr = 0; | |
7533 | CORE_ADDR gp = 0; | |
7534 | int status = 0; | |
7535 | int i; | |
7536 | ||
7537 | for (i = 0; | |
7538 | status == 0 && target_pc == 0 && i < 20; | |
7539 | i++, pc += MIPS_INSN32_SIZE) | |
7540 | { | |
4cc0665f | 7541 | ULONGEST inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
14132e89 MR |
7542 | CORE_ADDR imm; |
7543 | int rt; | |
7544 | int rs; | |
7545 | int rd; | |
7546 | ||
7547 | switch (itype_op (inst)) | |
7548 | { | |
7549 | case 0: /* SPECIAL */ | |
7550 | switch (rtype_funct (inst)) | |
7551 | { | |
7552 | case 8: /* JR */ | |
7553 | case 9: /* JALR */ | |
7554 | rs = rtype_rs (inst); | |
7555 | if (rs == MIPS_GP_REGNUM) | |
7556 | target_pc = gp; /* Hmm... */ | |
7557 | else if (rs == addrreg) | |
7558 | target_pc = addr; | |
7559 | break; | |
7560 | ||
7561 | case 0x21: /* ADDU */ | |
7562 | rt = rtype_rt (inst); | |
7563 | rs = rtype_rs (inst); | |
7564 | rd = rtype_rd (inst); | |
7565 | if (rd == MIPS_GP_REGNUM | |
7566 | && ((rs == MIPS_GP_REGNUM && rt == MIPS_T9_REGNUM) | |
7567 | || (rs == MIPS_T9_REGNUM && rt == MIPS_GP_REGNUM))) | |
7568 | gp += start_pc; | |
7569 | break; | |
7570 | } | |
7571 | break; | |
7572 | ||
7573 | case 2: /* J */ | |
7574 | case 3: /* JAL */ | |
7575 | target_pc = jtype_target (inst) << 2; | |
7576 | target_pc += ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); | |
7577 | break; | |
7578 | ||
7579 | case 9: /* ADDIU */ | |
7580 | rt = itype_rt (inst); | |
7581 | rs = itype_rs (inst); | |
7582 | if (rt == rs) | |
7583 | { | |
7584 | imm = (itype_immediate (inst) ^ 0x8000) - 0x8000; | |
7585 | if (rt == MIPS_GP_REGNUM) | |
7586 | gp += imm; | |
7587 | else if (rt == addrreg) | |
7588 | addr += imm; | |
7589 | } | |
7590 | break; | |
7591 | ||
7592 | case 0xf: /* LUI */ | |
7593 | rt = itype_rt (inst); | |
7594 | imm = ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 16; | |
7595 | if (rt == MIPS_GP_REGNUM) | |
7596 | gp = imm; | |
7597 | else if (rt != MIPS_ZERO_REGNUM) | |
7598 | { | |
7599 | addrreg = rt; | |
7600 | addr = imm; | |
7601 | } | |
7602 | break; | |
7603 | ||
7604 | case 0x23: /* LW */ | |
7605 | rt = itype_rt (inst); | |
7606 | rs = itype_rs (inst); | |
7607 | imm = (itype_immediate (inst) ^ 0x8000) - 0x8000; | |
7608 | if (gp != 0 && rs == MIPS_GP_REGNUM) | |
7609 | { | |
7610 | gdb_byte buf[4]; | |
7611 | ||
7612 | memset (buf, 0, sizeof (buf)); | |
7613 | status = target_read_memory (gp + imm, buf, sizeof (buf)); | |
7614 | addrreg = rt; | |
7615 | addr = extract_signed_integer (buf, sizeof (buf), byte_order); | |
7616 | } | |
7617 | break; | |
7618 | } | |
7619 | } | |
7620 | ||
7621 | return target_pc; | |
7622 | } | |
7623 | ||
7624 | /* If PC is in a MIPS16 call or return stub, return the address of the | |
7625 | target PC, which is either the callee or the caller. There are several | |
c906108c SS |
7626 | cases which must be handled: |
7627 | ||
14132e89 MR |
7628 | * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub |
7629 | and the target PC is in $31 ($ra). | |
c906108c | 7630 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
14132e89 MR |
7631 | and the target PC is in $2. |
7632 | * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10}, | |
7633 | i.e. before the JALR instruction, this is effectively a call stub | |
7634 | and the target PC is in $2. Otherwise this is effectively | |
7635 | a return stub and the target PC is in $18. | |
7636 | * If the PC is at the start of __call_stub_fp_*, i.e. before the | |
7637 | JAL or JALR instruction, this is effectively a call stub and the | |
7638 | target PC is buried in the instruction stream. Otherwise this | |
7639 | is effectively a return stub and the target PC is in $18. | |
7640 | * If the PC is in __call_stub_* or in __fn_stub_*, this is a call | |
7641 | stub and the target PC is buried in the instruction stream. | |
7642 | ||
7643 | See the source code for the stubs in gcc/config/mips/mips16.S, or the | |
7644 | stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the | |
e7d6a6d2 | 7645 | gory details. */ |
c906108c | 7646 | |
757a7cc6 | 7647 | static CORE_ADDR |
db5f024e | 7648 | mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 7649 | { |
e17a4113 | 7650 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 7651 | CORE_ADDR start_addr; |
14132e89 MR |
7652 | const char *name; |
7653 | size_t prefixlen; | |
c906108c SS |
7654 | |
7655 | /* Find the starting address and name of the function containing the PC. */ | |
7656 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
7657 | return 0; | |
7658 | ||
14132e89 MR |
7659 | /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub |
7660 | and the target PC is in $31 ($ra). */ | |
7661 | prefixlen = strlen (mips_str_mips16_ret_stub); | |
7662 | if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0 | |
7663 | && mips_is_stub_mode (name + prefixlen) | |
7664 | && name[prefixlen + 2] == '\0') | |
7665 | return get_frame_register_signed | |
7666 | (frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM); | |
7667 | ||
7668 | /* If the PC is in __mips16_call_stub_*, this is one of the call | |
7669 | call/return stubs. */ | |
7670 | prefixlen = strlen (mips_str_mips16_call_stub); | |
7671 | if (strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0) | |
c906108c SS |
7672 | { |
7673 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
dda83cd7 | 7674 | and the target PC is in $2. */ |
14132e89 MR |
7675 | if (mips_is_stub_suffix (name + prefixlen, 0)) |
7676 | return get_frame_register_signed | |
7677 | (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); | |
c906108c | 7678 | |
14132e89 | 7679 | /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10}, |
dda83cd7 SM |
7680 | i.e. before the JALR instruction, this is effectively a call stub |
7681 | and the target PC is in $2. Otherwise this is effectively | |
7682 | a return stub and the target PC is in $18. */ | |
14132e89 MR |
7683 | else if (mips_is_stub_mode (name + prefixlen) |
7684 | && name[prefixlen + 2] == '_' | |
7685 | && mips_is_stub_suffix (name + prefixlen + 3, 0)) | |
c906108c SS |
7686 | { |
7687 | if (pc == start_addr) | |
14132e89 MR |
7688 | /* This is the 'call' part of a call stub. The return |
7689 | address is in $2. */ | |
7690 | return get_frame_register_signed | |
7691 | (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); | |
c906108c SS |
7692 | else |
7693 | /* This is the 'return' part of a call stub. The return | |
14132e89 MR |
7694 | address is in $18. */ |
7695 | return get_frame_register_signed | |
7696 | (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); | |
c906108c | 7697 | } |
14132e89 MR |
7698 | else |
7699 | return 0; /* Not a stub. */ | |
7700 | } | |
7701 | ||
7702 | /* If the PC is in __call_stub_* or __fn_stub*, this is one of the | |
7703 | compiler-generated call or call/return stubs. */ | |
61012eef GB |
7704 | if (startswith (name, mips_str_fn_stub) |
7705 | || startswith (name, mips_str_call_stub)) | |
14132e89 MR |
7706 | { |
7707 | if (pc == start_addr) | |
7708 | /* This is the 'call' part of a call stub. Call this helper | |
7709 | to scan through this code for interesting instructions | |
7710 | and determine the final PC. */ | |
7711 | return mips_get_mips16_fn_stub_pc (frame, pc); | |
7712 | else | |
7713 | /* This is the 'return' part of a call stub. The return address | |
7714 | is in $18. */ | |
7715 | return get_frame_register_signed | |
7716 | (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); | |
c906108c | 7717 | } |
14132e89 MR |
7718 | |
7719 | return 0; /* Not a stub. */ | |
7720 | } | |
7721 | ||
7722 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
7723 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
7724 | ||
7725 | static int | |
7726 | mips_in_return_stub (struct gdbarch *gdbarch, CORE_ADDR pc, const char *name) | |
7727 | { | |
7728 | CORE_ADDR start_addr; | |
7729 | size_t prefixlen; | |
7730 | ||
7731 | /* Find the starting address of the function containing the PC. */ | |
7732 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
7733 | return 0; | |
7734 | ||
7735 | /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at | |
7736 | the start, i.e. after the JALR instruction, this is effectively | |
7737 | a return stub. */ | |
7738 | prefixlen = strlen (mips_str_mips16_call_stub); | |
7739 | if (pc != start_addr | |
7740 | && strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0 | |
7741 | && mips_is_stub_mode (name + prefixlen) | |
7742 | && name[prefixlen + 2] == '_' | |
7743 | && mips_is_stub_suffix (name + prefixlen + 3, 1)) | |
7744 | return 1; | |
7745 | ||
7746 | /* If the PC is in __call_stub_fp_* but not at the start, i.e. after | |
7747 | the JAL or JALR instruction, this is effectively a return stub. */ | |
7748 | prefixlen = strlen (mips_str_call_fp_stub); | |
7749 | if (pc != start_addr | |
7750 | && strncmp (name, mips_str_call_fp_stub, prefixlen) == 0) | |
7751 | return 1; | |
7752 | ||
7753 | /* Consume the .pic. prefix of any PIC stub, this function must return | |
7754 | true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub | |
7755 | or the call stub path will trigger in handle_inferior_event causing | |
7756 | it to go astray. */ | |
7757 | prefixlen = strlen (mips_str_pic); | |
7758 | if (strncmp (name, mips_str_pic, prefixlen) == 0) | |
7759 | name += prefixlen; | |
7760 | ||
7761 | /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */ | |
7762 | prefixlen = strlen (mips_str_mips16_ret_stub); | |
7763 | if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0 | |
7764 | && mips_is_stub_mode (name + prefixlen) | |
7765 | && name[prefixlen + 2] == '\0') | |
7766 | return 1; | |
7767 | ||
7768 | return 0; /* Not a stub. */ | |
c906108c SS |
7769 | } |
7770 | ||
db5f024e DJ |
7771 | /* If the current PC is the start of a non-PIC-to-PIC stub, return the |
7772 | PC of the stub target. The stub just loads $t9 and jumps to it, | |
7773 | so that $t9 has the correct value at function entry. */ | |
7774 | ||
7775 | static CORE_ADDR | |
7776 | mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
7777 | { | |
e17a4113 UW |
7778 | struct gdbarch *gdbarch = get_frame_arch (frame); |
7779 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
7cbd4a93 | 7780 | struct bound_minimal_symbol msym; |
db5f024e DJ |
7781 | int i; |
7782 | gdb_byte stub_code[16]; | |
7783 | int32_t stub_words[4]; | |
7784 | ||
7785 | /* The stub for foo is named ".pic.foo", and is either two | |
7786 | instructions inserted before foo or a three instruction sequence | |
7787 | which jumps to foo. */ | |
7788 | msym = lookup_minimal_symbol_by_pc (pc); | |
7cbd4a93 | 7789 | if (msym.minsym == NULL |
77e371c0 | 7790 | || BMSYMBOL_VALUE_ADDRESS (msym) != pc |
c9d95fa3 CB |
7791 | || msym.minsym->linkage_name () == NULL |
7792 | || !startswith (msym.minsym->linkage_name (), ".pic.")) | |
db5f024e DJ |
7793 | return 0; |
7794 | ||
7795 | /* A two-instruction header. */ | |
7cbd4a93 | 7796 | if (MSYMBOL_SIZE (msym.minsym) == 8) |
db5f024e DJ |
7797 | return pc + 8; |
7798 | ||
7799 | /* A three-instruction (plus delay slot) trampoline. */ | |
7cbd4a93 | 7800 | if (MSYMBOL_SIZE (msym.minsym) == 16) |
db5f024e DJ |
7801 | { |
7802 | if (target_read_memory (pc, stub_code, 16) != 0) | |
7803 | return 0; | |
7804 | for (i = 0; i < 4; i++) | |
e17a4113 UW |
7805 | stub_words[i] = extract_unsigned_integer (stub_code + i * 4, |
7806 | 4, byte_order); | |
db5f024e DJ |
7807 | |
7808 | /* A stub contains these instructions: | |
7809 | lui t9, %hi(target) | |
7810 | j target | |
7811 | addiu t9, t9, %lo(target) | |
7812 | nop | |
7813 | ||
7814 | This works even for N64, since stubs are only generated with | |
7815 | -msym32. */ | |
7816 | if ((stub_words[0] & 0xffff0000U) == 0x3c190000 | |
7817 | && (stub_words[1] & 0xfc000000U) == 0x08000000 | |
7818 | && (stub_words[2] & 0xffff0000U) == 0x27390000 | |
7819 | && stub_words[3] == 0x00000000) | |
34b192ce MR |
7820 | return ((((stub_words[0] & 0x0000ffff) << 16) |
7821 | + (stub_words[2] & 0x0000ffff)) ^ 0x8000) - 0x8000; | |
db5f024e DJ |
7822 | } |
7823 | ||
7824 | /* Not a recognized stub. */ | |
7825 | return 0; | |
7826 | } | |
7827 | ||
7828 | static CORE_ADDR | |
7829 | mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
7830 | { | |
14132e89 | 7831 | CORE_ADDR requested_pc = pc; |
db5f024e | 7832 | CORE_ADDR target_pc; |
14132e89 MR |
7833 | CORE_ADDR new_pc; |
7834 | ||
7835 | do | |
7836 | { | |
7837 | target_pc = pc; | |
db5f024e | 7838 | |
14132e89 MR |
7839 | new_pc = mips_skip_mips16_trampoline_code (frame, pc); |
7840 | if (new_pc) | |
3e29f34a | 7841 | pc = new_pc; |
db5f024e | 7842 | |
14132e89 MR |
7843 | new_pc = find_solib_trampoline_target (frame, pc); |
7844 | if (new_pc) | |
3e29f34a | 7845 | pc = new_pc; |
db5f024e | 7846 | |
14132e89 MR |
7847 | new_pc = mips_skip_pic_trampoline_code (frame, pc); |
7848 | if (new_pc) | |
3e29f34a | 7849 | pc = new_pc; |
14132e89 MR |
7850 | } |
7851 | while (pc != target_pc); | |
db5f024e | 7852 | |
14132e89 | 7853 | return pc != requested_pc ? pc : 0; |
db5f024e DJ |
7854 | } |
7855 | ||
a4b8ebc8 | 7856 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
f57d151a | 7857 | [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
7858 | |
7859 | static int | |
d3f73121 | 7860 | mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 7861 | { |
a4b8ebc8 | 7862 | int regnum; |
2f38ef89 | 7863 | if (num >= 0 && num < 32) |
a4b8ebc8 | 7864 | regnum = num; |
2f38ef89 | 7865 | else if (num >= 38 && num < 70) |
d3f73121 | 7866 | regnum = num + mips_regnum (gdbarch)->fp0 - 38; |
040b99fd | 7867 | else if (num == 70) |
d3f73121 | 7868 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 7869 | else if (num == 71) |
d3f73121 | 7870 | regnum = mips_regnum (gdbarch)->lo; |
1faeff08 MR |
7871 | else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 72 && num < 78) |
7872 | regnum = num + mips_regnum (gdbarch)->dspacc - 72; | |
2f38ef89 | 7873 | else |
0fde2c53 | 7874 | return -1; |
d3f73121 | 7875 | return gdbarch_num_regs (gdbarch) + regnum; |
88c72b7d AC |
7876 | } |
7877 | ||
2f38ef89 | 7878 | |
a4b8ebc8 | 7879 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
f57d151a | 7880 | gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
7881 | |
7882 | static int | |
d3f73121 | 7883 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 7884 | { |
a4b8ebc8 | 7885 | int regnum; |
2f38ef89 | 7886 | if (num >= 0 && num < 32) |
a4b8ebc8 | 7887 | regnum = num; |
2f38ef89 | 7888 | else if (num >= 32 && num < 64) |
d3f73121 | 7889 | regnum = num + mips_regnum (gdbarch)->fp0 - 32; |
040b99fd | 7890 | else if (num == 64) |
d3f73121 | 7891 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 7892 | else if (num == 65) |
d3f73121 | 7893 | regnum = mips_regnum (gdbarch)->lo; |
1faeff08 MR |
7894 | else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 66 && num < 72) |
7895 | regnum = num + mips_regnum (gdbarch)->dspacc - 66; | |
2f38ef89 | 7896 | else |
0fde2c53 | 7897 | return -1; |
d3f73121 | 7898 | return gdbarch_num_regs (gdbarch) + regnum; |
a4b8ebc8 AC |
7899 | } |
7900 | ||
7901 | static int | |
e7faf938 | 7902 | mips_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
a4b8ebc8 AC |
7903 | { |
7904 | /* Only makes sense to supply raw registers. */ | |
e7faf938 | 7905 | gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)); |
a4b8ebc8 AC |
7906 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to |
7907 | decide if it is valid. Should instead define a standard sim/gdb | |
7908 | register numbering scheme. */ | |
e7faf938 MD |
7909 | if (gdbarch_register_name (gdbarch, |
7910 | gdbarch_num_regs (gdbarch) + regnum) != NULL | |
7911 | && gdbarch_register_name (gdbarch, | |
dda83cd7 | 7912 | gdbarch_num_regs (gdbarch) |
025bb325 | 7913 | + regnum)[0] != '\0') |
a4b8ebc8 AC |
7914 | return regnum; |
7915 | else | |
6d82d43b | 7916 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
7917 | } |
7918 | ||
2f38ef89 | 7919 | |
4844f454 CV |
7920 | /* Convert an integer into an address. Extracting the value signed |
7921 | guarantees a correctly sign extended address. */ | |
fc0c74b1 AC |
7922 | |
7923 | static CORE_ADDR | |
79dd2d24 | 7924 | mips_integer_to_address (struct gdbarch *gdbarch, |
870cd05e | 7925 | struct type *type, const gdb_byte *buf) |
fc0c74b1 | 7926 | { |
e17a4113 UW |
7927 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7928 | return extract_signed_integer (buf, TYPE_LENGTH (type), byte_order); | |
fc0c74b1 AC |
7929 | } |
7930 | ||
82e91389 DJ |
7931 | /* Dummy virtual frame pointer method. This is no more or less accurate |
7932 | than most other architectures; we just need to be explicit about it, | |
7933 | because the pseudo-register gdbarch_sp_regnum will otherwise lead to | |
7934 | an assertion failure. */ | |
7935 | ||
7936 | static void | |
a54fba4c MD |
7937 | mips_virtual_frame_pointer (struct gdbarch *gdbarch, |
7938 | CORE_ADDR pc, int *reg, LONGEST *offset) | |
82e91389 DJ |
7939 | { |
7940 | *reg = MIPS_SP_REGNUM; | |
7941 | *offset = 0; | |
7942 | } | |
7943 | ||
caaa3122 DJ |
7944 | static void |
7945 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
7946 | { | |
7947 | enum mips_abi *abip = (enum mips_abi *) obj; | |
fd361982 | 7948 | const char *name = bfd_section_name (sect); |
caaa3122 DJ |
7949 | |
7950 | if (*abip != MIPS_ABI_UNKNOWN) | |
7951 | return; | |
7952 | ||
61012eef | 7953 | if (!startswith (name, ".mdebug.")) |
caaa3122 DJ |
7954 | return; |
7955 | ||
7956 | if (strcmp (name, ".mdebug.abi32") == 0) | |
7957 | *abip = MIPS_ABI_O32; | |
7958 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
7959 | *abip = MIPS_ABI_N32; | |
62a49b2c | 7960 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 7961 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
7962 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
7963 | *abip = MIPS_ABI_O64; | |
7964 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
7965 | *abip = MIPS_ABI_EABI32; | |
7966 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
7967 | *abip = MIPS_ABI_EABI64; | |
7968 | else | |
8a3fe4f8 | 7969 | warning (_("unsupported ABI %s."), name + 8); |
caaa3122 DJ |
7970 | } |
7971 | ||
22e47e37 FF |
7972 | static void |
7973 | mips_find_long_section (bfd *abfd, asection *sect, void *obj) | |
7974 | { | |
7975 | int *lbp = (int *) obj; | |
fd361982 | 7976 | const char *name = bfd_section_name (sect); |
22e47e37 | 7977 | |
61012eef | 7978 | if (startswith (name, ".gcc_compiled_long32")) |
22e47e37 | 7979 | *lbp = 32; |
61012eef | 7980 | else if (startswith (name, ".gcc_compiled_long64")) |
22e47e37 | 7981 | *lbp = 64; |
61012eef | 7982 | else if (startswith (name, ".gcc_compiled_long")) |
22e47e37 FF |
7983 | warning (_("unrecognized .gcc_compiled_longXX")); |
7984 | } | |
7985 | ||
2e4ebe70 DJ |
7986 | static enum mips_abi |
7987 | global_mips_abi (void) | |
7988 | { | |
7989 | int i; | |
7990 | ||
7991 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
7992 | if (mips_abi_strings[i] == mips_abi_string) | |
7993 | return (enum mips_abi) i; | |
7994 | ||
e2e0b3e5 | 7995 | internal_error (__FILE__, __LINE__, _("unknown ABI string")); |
2e4ebe70 DJ |
7996 | } |
7997 | ||
4cc0665f MR |
7998 | /* Return the default compressed instruction set, either of MIPS16 |
7999 | or microMIPS, selected when none could have been determined from | |
8000 | the ELF header of the binary being executed (or no binary has been | |
8001 | selected. */ | |
8002 | ||
8003 | static enum mips_isa | |
8004 | global_mips_compression (void) | |
8005 | { | |
8006 | int i; | |
8007 | ||
8008 | for (i = 0; mips_compression_strings[i] != NULL; i++) | |
8009 | if (mips_compression_strings[i] == mips_compression_string) | |
8010 | return (enum mips_isa) i; | |
8011 | ||
8012 | internal_error (__FILE__, __LINE__, _("unknown compressed ISA string")); | |
8013 | } | |
8014 | ||
29709017 DJ |
8015 | static void |
8016 | mips_register_g_packet_guesses (struct gdbarch *gdbarch) | |
8017 | { | |
29709017 DJ |
8018 | /* If the size matches the set of 32-bit or 64-bit integer registers, |
8019 | assume that's what we've got. */ | |
4eb0ad19 DJ |
8020 | register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32); |
8021 | register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64); | |
29709017 DJ |
8022 | |
8023 | /* If the size matches the full set of registers GDB traditionally | |
8024 | knows about, including floating point, for either 32-bit or | |
8025 | 64-bit, assume that's what we've got. */ | |
4eb0ad19 DJ |
8026 | register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32); |
8027 | register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64); | |
29709017 DJ |
8028 | |
8029 | /* Otherwise we don't have a useful guess. */ | |
8030 | } | |
8031 | ||
f8b73d13 DJ |
8032 | static struct value * |
8033 | value_of_mips_user_reg (struct frame_info *frame, const void *baton) | |
8034 | { | |
19ba03f4 | 8035 | const int *reg_p = (const int *) baton; |
f8b73d13 DJ |
8036 | return value_of_register (*reg_p, frame); |
8037 | } | |
8038 | ||
c2d11a7d | 8039 | static struct gdbarch * |
6d82d43b | 8040 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 8041 | { |
c2d11a7d JM |
8042 | struct gdbarch *gdbarch; |
8043 | struct gdbarch_tdep *tdep; | |
8044 | int elf_flags; | |
2e4ebe70 | 8045 | enum mips_abi mips_abi, found_abi, wanted_abi; |
f8b73d13 | 8046 | int i, num_regs; |
8d5838b5 | 8047 | enum mips_fpu_type fpu_type; |
c1e1314d | 8048 | tdesc_arch_data_up tdesc_data; |
d929bc19 | 8049 | int elf_fpu_type = Val_GNU_MIPS_ABI_FP_ANY; |
27087b7f | 8050 | const char * const *reg_names; |
1faeff08 | 8051 | struct mips_regnum mips_regnum, *regnum; |
4cc0665f | 8052 | enum mips_isa mips_isa; |
1faeff08 MR |
8053 | int dspacc; |
8054 | int dspctl; | |
8055 | ||
ec03c1ac AC |
8056 | /* First of all, extract the elf_flags, if available. */ |
8057 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
8058 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
8059 | else if (arches != NULL) |
8060 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
8061 | else |
8062 | elf_flags = 0; | |
8063 | if (gdbarch_debug) | |
8064 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 8065 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 8066 | |
102182a9 | 8067 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
8068 | switch ((elf_flags & EF_MIPS_ABI)) |
8069 | { | |
8070 | case E_MIPS_ABI_O32: | |
ec03c1ac | 8071 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
8072 | break; |
8073 | case E_MIPS_ABI_O64: | |
ec03c1ac | 8074 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
8075 | break; |
8076 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 8077 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
8078 | break; |
8079 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 8080 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
8081 | break; |
8082 | default: | |
acdb74a0 | 8083 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 8084 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 8085 | else |
ec03c1ac | 8086 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
8087 | break; |
8088 | } | |
acdb74a0 | 8089 | |
caaa3122 | 8090 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
8091 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
8092 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 8093 | |
dc305454 | 8094 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
8095 | MIPS architecture (if there is one). */ |
8096 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
8097 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 8098 | |
32a6503c | 8099 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 8100 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
8101 | && info.bfd_arch_info != NULL |
8102 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
8103 | { | |
8104 | switch (info.bfd_arch_info->mach) | |
8105 | { | |
8106 | case bfd_mach_mips3900: | |
ec03c1ac | 8107 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
8108 | break; |
8109 | case bfd_mach_mips4100: | |
8110 | case bfd_mach_mips5000: | |
ec03c1ac | 8111 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 8112 | break; |
1d06468c EZ |
8113 | case bfd_mach_mips8000: |
8114 | case bfd_mach_mips10000: | |
32a6503c KB |
8115 | /* On Irix, ELF64 executables use the N64 ABI. The |
8116 | pseudo-sections which describe the ABI aren't present | |
8117 | on IRIX. (Even for executables created by gcc.) */ | |
e6c2f47b PA |
8118 | if (info.abfd != NULL |
8119 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
28d169de | 8120 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) |
ec03c1ac | 8121 | found_abi = MIPS_ABI_N64; |
28d169de | 8122 | else |
ec03c1ac | 8123 | found_abi = MIPS_ABI_N32; |
1d06468c | 8124 | break; |
bf64bfd6 AC |
8125 | } |
8126 | } | |
2e4ebe70 | 8127 | |
26c53e50 DJ |
8128 | /* Default 64-bit objects to N64 instead of O32. */ |
8129 | if (found_abi == MIPS_ABI_UNKNOWN | |
8130 | && info.abfd != NULL | |
8131 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
8132 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
8133 | found_abi = MIPS_ABI_N64; | |
8134 | ||
ec03c1ac AC |
8135 | if (gdbarch_debug) |
8136 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
8137 | found_abi); | |
8138 | ||
8139 | /* What has the user specified from the command line? */ | |
8140 | wanted_abi = global_mips_abi (); | |
8141 | if (gdbarch_debug) | |
8142 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
8143 | wanted_abi); | |
2e4ebe70 DJ |
8144 | |
8145 | /* Now that we have found what the ABI for this binary would be, | |
8146 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
8147 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
8148 | mips_abi = wanted_abi; | |
ec03c1ac AC |
8149 | else if (found_abi != MIPS_ABI_UNKNOWN) |
8150 | mips_abi = found_abi; | |
8151 | else | |
8152 | mips_abi = MIPS_ABI_O32; | |
8153 | if (gdbarch_debug) | |
8154 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
8155 | mips_abi); | |
2e4ebe70 | 8156 | |
c5196c92 MR |
8157 | /* Make sure we don't use a 32-bit architecture with a 64-bit ABI. */ |
8158 | if (mips_abi != MIPS_ABI_EABI32 | |
8159 | && mips_abi != MIPS_ABI_O32 | |
8160 | && info.bfd_arch_info != NULL | |
8161 | && info.bfd_arch_info->arch == bfd_arch_mips | |
8162 | && info.bfd_arch_info->bits_per_word < 64) | |
8163 | info.bfd_arch_info = bfd_lookup_arch (bfd_arch_mips, bfd_mach_mips4000); | |
8164 | ||
4cc0665f MR |
8165 | /* Determine the default compressed ISA. */ |
8166 | if ((elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0 | |
8167 | && (elf_flags & EF_MIPS_ARCH_ASE_M16) == 0) | |
8168 | mips_isa = ISA_MICROMIPS; | |
8169 | else if ((elf_flags & EF_MIPS_ARCH_ASE_M16) != 0 | |
8170 | && (elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) == 0) | |
8171 | mips_isa = ISA_MIPS16; | |
8172 | else | |
8173 | mips_isa = global_mips_compression (); | |
8174 | mips_compression_string = mips_compression_strings[mips_isa]; | |
8175 | ||
ec03c1ac | 8176 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 8177 | if (gdbarch_debug) |
ec03c1ac | 8178 | fprintf_unfiltered (gdb_stdlog, |
025bb325 MS |
8179 | "mips_gdbarch_init: " |
8180 | "mips64_transfers_32bit_regs_p = %d\n", | |
ec03c1ac | 8181 | mips64_transfers_32bit_regs_p); |
0dadbba0 | 8182 | |
8d5838b5 | 8183 | /* Determine the MIPS FPU type. */ |
609ca2b9 DJ |
8184 | #ifdef HAVE_ELF |
8185 | if (info.abfd | |
8186 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
8187 | elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
8188 | Tag_GNU_MIPS_ABI_FP); | |
8189 | #endif /* HAVE_ELF */ | |
8190 | ||
8d5838b5 AC |
8191 | if (!mips_fpu_type_auto) |
8192 | fpu_type = mips_fpu_type; | |
d929bc19 | 8193 | else if (elf_fpu_type != Val_GNU_MIPS_ABI_FP_ANY) |
609ca2b9 DJ |
8194 | { |
8195 | switch (elf_fpu_type) | |
8196 | { | |
d929bc19 | 8197 | case Val_GNU_MIPS_ABI_FP_DOUBLE: |
609ca2b9 DJ |
8198 | fpu_type = MIPS_FPU_DOUBLE; |
8199 | break; | |
d929bc19 | 8200 | case Val_GNU_MIPS_ABI_FP_SINGLE: |
609ca2b9 DJ |
8201 | fpu_type = MIPS_FPU_SINGLE; |
8202 | break; | |
d929bc19 | 8203 | case Val_GNU_MIPS_ABI_FP_SOFT: |
609ca2b9 DJ |
8204 | default: |
8205 | /* Soft float or unknown. */ | |
8206 | fpu_type = MIPS_FPU_NONE; | |
8207 | break; | |
8208 | } | |
8209 | } | |
8d5838b5 AC |
8210 | else if (info.bfd_arch_info != NULL |
8211 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
8212 | switch (info.bfd_arch_info->mach) | |
8213 | { | |
8214 | case bfd_mach_mips3900: | |
8215 | case bfd_mach_mips4100: | |
8216 | case bfd_mach_mips4111: | |
a9d61c86 | 8217 | case bfd_mach_mips4120: |
8d5838b5 AC |
8218 | fpu_type = MIPS_FPU_NONE; |
8219 | break; | |
8220 | case bfd_mach_mips4650: | |
8221 | fpu_type = MIPS_FPU_SINGLE; | |
8222 | break; | |
8223 | default: | |
8224 | fpu_type = MIPS_FPU_DOUBLE; | |
8225 | break; | |
8226 | } | |
8227 | else if (arches != NULL) | |
a2f1f308 | 8228 | fpu_type = MIPS_FPU_TYPE (arches->gdbarch); |
8d5838b5 AC |
8229 | else |
8230 | fpu_type = MIPS_FPU_DOUBLE; | |
8231 | if (gdbarch_debug) | |
8232 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 8233 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 8234 | |
29709017 DJ |
8235 | /* Check for blatant incompatibilities. */ |
8236 | ||
8237 | /* If we have only 32-bit registers, then we can't debug a 64-bit | |
8238 | ABI. */ | |
8239 | if (info.target_desc | |
8240 | && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL | |
8241 | && mips_abi != MIPS_ABI_EABI32 | |
8242 | && mips_abi != MIPS_ABI_O32) | |
37c33887 MR |
8243 | return NULL; |
8244 | ||
8245 | /* Fill in the OS dependent register numbers and names. */ | |
8246 | if (info.osabi == GDB_OSABI_LINUX) | |
f8b73d13 | 8247 | { |
37c33887 MR |
8248 | mips_regnum.fp0 = 38; |
8249 | mips_regnum.pc = 37; | |
8250 | mips_regnum.cause = 36; | |
8251 | mips_regnum.badvaddr = 35; | |
8252 | mips_regnum.hi = 34; | |
8253 | mips_regnum.lo = 33; | |
8254 | mips_regnum.fp_control_status = 70; | |
8255 | mips_regnum.fp_implementation_revision = 71; | |
8256 | mips_regnum.dspacc = -1; | |
8257 | mips_regnum.dspctl = -1; | |
8258 | dspacc = 72; | |
8259 | dspctl = 78; | |
8260 | num_regs = 90; | |
8261 | reg_names = mips_linux_reg_names; | |
8262 | } | |
8263 | else | |
8264 | { | |
8265 | mips_regnum.lo = MIPS_EMBED_LO_REGNUM; | |
8266 | mips_regnum.hi = MIPS_EMBED_HI_REGNUM; | |
8267 | mips_regnum.badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
8268 | mips_regnum.cause = MIPS_EMBED_CAUSE_REGNUM; | |
8269 | mips_regnum.pc = MIPS_EMBED_PC_REGNUM; | |
8270 | mips_regnum.fp0 = MIPS_EMBED_FP0_REGNUM; | |
8271 | mips_regnum.fp_control_status = 70; | |
8272 | mips_regnum.fp_implementation_revision = 71; | |
8273 | mips_regnum.dspacc = dspacc = -1; | |
8274 | mips_regnum.dspctl = dspctl = -1; | |
8275 | num_regs = MIPS_LAST_EMBED_REGNUM + 1; | |
8276 | if (info.bfd_arch_info != NULL | |
dda83cd7 SM |
8277 | && info.bfd_arch_info->mach == bfd_mach_mips3900) |
8278 | reg_names = mips_tx39_reg_names; | |
37c33887 | 8279 | else |
dda83cd7 | 8280 | reg_names = mips_generic_reg_names; |
37c33887 MR |
8281 | } |
8282 | ||
8283 | /* Check any target description for validity. */ | |
8284 | if (tdesc_has_registers (info.target_desc)) | |
8285 | { | |
8286 | static const char *const mips_gprs[] = { | |
8287 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
8288 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
8289 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
8290 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
8291 | }; | |
8292 | static const char *const mips_fprs[] = { | |
8293 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
8294 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
8295 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
8296 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
8297 | }; | |
8298 | ||
8299 | const struct tdesc_feature *feature; | |
8300 | int valid_p; | |
8301 | ||
8302 | feature = tdesc_find_feature (info.target_desc, | |
8303 | "org.gnu.gdb.mips.cpu"); | |
8304 | if (feature == NULL) | |
8305 | return NULL; | |
8306 | ||
8307 | tdesc_data = tdesc_data_alloc (); | |
8308 | ||
8309 | valid_p = 1; | |
8310 | for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) | |
c1e1314d | 8311 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), i, |
37c33887 MR |
8312 | mips_gprs[i]); |
8313 | ||
8314 | ||
c1e1314d | 8315 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 | 8316 | mips_regnum.lo, "lo"); |
c1e1314d | 8317 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 | 8318 | mips_regnum.hi, "hi"); |
c1e1314d | 8319 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 MR |
8320 | mips_regnum.pc, "pc"); |
8321 | ||
8322 | if (!valid_p) | |
c1e1314d | 8323 | return NULL; |
37c33887 MR |
8324 | |
8325 | feature = tdesc_find_feature (info.target_desc, | |
8326 | "org.gnu.gdb.mips.cp0"); | |
8327 | if (feature == NULL) | |
c1e1314d | 8328 | return NULL; |
37c33887 MR |
8329 | |
8330 | valid_p = 1; | |
c1e1314d | 8331 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 | 8332 | mips_regnum.badvaddr, "badvaddr"); |
c1e1314d | 8333 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 | 8334 | MIPS_PS_REGNUM, "status"); |
c1e1314d | 8335 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 MR |
8336 | mips_regnum.cause, "cause"); |
8337 | ||
8338 | if (!valid_p) | |
c1e1314d | 8339 | return NULL; |
37c33887 MR |
8340 | |
8341 | /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS | |
8342 | backend is not prepared for that, though. */ | |
8343 | feature = tdesc_find_feature (info.target_desc, | |
8344 | "org.gnu.gdb.mips.fpu"); | |
8345 | if (feature == NULL) | |
c1e1314d | 8346 | return NULL; |
37c33887 MR |
8347 | |
8348 | valid_p = 1; | |
8349 | for (i = 0; i < 32; i++) | |
c1e1314d | 8350 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 MR |
8351 | i + mips_regnum.fp0, mips_fprs[i]); |
8352 | ||
c1e1314d | 8353 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 MR |
8354 | mips_regnum.fp_control_status, |
8355 | "fcsr"); | |
8356 | valid_p | |
c1e1314d | 8357 | &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 MR |
8358 | mips_regnum.fp_implementation_revision, |
8359 | "fir"); | |
8360 | ||
8361 | if (!valid_p) | |
c1e1314d | 8362 | return NULL; |
37c33887 MR |
8363 | |
8364 | num_regs = mips_regnum.fp_implementation_revision + 1; | |
8365 | ||
8366 | if (dspacc >= 0) | |
8367 | { | |
8368 | feature = tdesc_find_feature (info.target_desc, | |
8369 | "org.gnu.gdb.mips.dsp"); | |
8370 | /* The DSP registers are optional; it's OK if they are absent. */ | |
8371 | if (feature != NULL) | |
8372 | { | |
8373 | i = 0; | |
8374 | valid_p = 1; | |
c1e1314d | 8375 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 | 8376 | dspacc + i++, "hi1"); |
c1e1314d | 8377 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 | 8378 | dspacc + i++, "lo1"); |
c1e1314d | 8379 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 | 8380 | dspacc + i++, "hi2"); |
c1e1314d | 8381 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 | 8382 | dspacc + i++, "lo2"); |
c1e1314d | 8383 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 | 8384 | dspacc + i++, "hi3"); |
c1e1314d | 8385 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 MR |
8386 | dspacc + i++, "lo3"); |
8387 | ||
c1e1314d | 8388 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 MR |
8389 | dspctl, "dspctl"); |
8390 | ||
8391 | if (!valid_p) | |
c1e1314d | 8392 | return NULL; |
37c33887 MR |
8393 | |
8394 | mips_regnum.dspacc = dspacc; | |
8395 | mips_regnum.dspctl = dspctl; | |
8396 | ||
8397 | num_regs = mips_regnum.dspctl + 1; | |
8398 | } | |
8399 | } | |
8400 | ||
8401 | /* It would be nice to detect an attempt to use a 64-bit ABI | |
8402 | when only 32-bit registers are provided. */ | |
8403 | reg_names = NULL; | |
f8b73d13 | 8404 | } |
29709017 | 8405 | |
025bb325 | 8406 | /* Try to find a pre-existing architecture. */ |
c2d11a7d JM |
8407 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
8408 | arches != NULL; | |
8409 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
8410 | { | |
d54398a7 | 8411 | /* MIPS needs to be pedantic about which ABI and the compressed |
dda83cd7 | 8412 | ISA variation the object is using. */ |
9103eae0 | 8413 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 8414 | continue; |
9103eae0 | 8415 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 8416 | continue; |
d54398a7 MR |
8417 | if (gdbarch_tdep (arches->gdbarch)->mips_isa != mips_isa) |
8418 | continue; | |
719ec221 | 8419 | /* Need to be pedantic about which register virtual size is |
dda83cd7 | 8420 | used. */ |
719ec221 AC |
8421 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p |
8422 | != mips64_transfers_32bit_regs_p) | |
8423 | continue; | |
8d5838b5 | 8424 | /* Be pedantic about which FPU is selected. */ |
a2f1f308 | 8425 | if (MIPS_FPU_TYPE (arches->gdbarch) != fpu_type) |
8d5838b5 | 8426 | continue; |
f8b73d13 | 8427 | |
4be87837 | 8428 | return arches->gdbarch; |
c2d11a7d JM |
8429 | } |
8430 | ||
102182a9 | 8431 | /* Need a new architecture. Fill in a target specific vector. */ |
cdd238da | 8432 | tdep = XCNEW (struct gdbarch_tdep); |
c2d11a7d JM |
8433 | gdbarch = gdbarch_alloc (&info, tdep); |
8434 | tdep->elf_flags = elf_flags; | |
719ec221 | 8435 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
8436 | tdep->found_abi = found_abi; |
8437 | tdep->mips_abi = mips_abi; | |
4cc0665f | 8438 | tdep->mips_isa = mips_isa; |
8d5838b5 | 8439 | tdep->mips_fpu_type = fpu_type; |
29709017 DJ |
8440 | tdep->register_size_valid_p = 0; |
8441 | tdep->register_size = 0; | |
8442 | ||
8443 | if (info.target_desc) | |
8444 | { | |
8445 | /* Some useful properties can be inferred from the target. */ | |
8446 | if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) | |
8447 | { | |
8448 | tdep->register_size_valid_p = 1; | |
8449 | tdep->register_size = 4; | |
8450 | } | |
8451 | else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) | |
8452 | { | |
8453 | tdep->register_size_valid_p = 1; | |
8454 | tdep->register_size = 8; | |
8455 | } | |
8456 | } | |
c2d11a7d | 8457 | |
102182a9 | 8458 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
8459 | set_gdbarch_short_bit (gdbarch, 16); |
8460 | set_gdbarch_int_bit (gdbarch, 32); | |
8461 | set_gdbarch_float_bit (gdbarch, 32); | |
8462 | set_gdbarch_double_bit (gdbarch, 64); | |
8463 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
8464 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
8465 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
8466 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 8467 | |
175ff332 HZ |
8468 | set_gdbarch_ax_pseudo_register_collect (gdbarch, |
8469 | mips_ax_pseudo_register_collect); | |
8470 | set_gdbarch_ax_pseudo_register_push_stack | |
8471 | (gdbarch, mips_ax_pseudo_register_push_stack); | |
8472 | ||
6d82d43b | 8473 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 | 8474 | mips_elf_make_msymbol_special); |
3e29f34a MR |
8475 | set_gdbarch_make_symbol_special (gdbarch, mips_make_symbol_special); |
8476 | set_gdbarch_adjust_dwarf2_addr (gdbarch, mips_adjust_dwarf2_addr); | |
8477 | set_gdbarch_adjust_dwarf2_line (gdbarch, mips_adjust_dwarf2_line); | |
f7ab6ec6 | 8478 | |
1faeff08 MR |
8479 | regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, struct mips_regnum); |
8480 | *regnum = mips_regnum; | |
1faeff08 MR |
8481 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
8482 | set_gdbarch_num_regs (gdbarch, num_regs); | |
8483 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
8484 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
8485 | set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer); | |
8486 | tdep->mips_processor_reg_names = reg_names; | |
8487 | tdep->regnum = regnum; | |
fe29b929 | 8488 | |
0dadbba0 | 8489 | switch (mips_abi) |
c2d11a7d | 8490 | { |
0dadbba0 | 8491 | case MIPS_ABI_O32: |
25ab4790 | 8492 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 8493 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
4c7d22cb | 8494 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 8495 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 8496 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8497 | set_gdbarch_long_bit (gdbarch, 32); |
8498 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8499 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8500 | break; | |
0dadbba0 | 8501 | case MIPS_ABI_O64: |
25ab4790 | 8502 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
9c8fdbfa | 8503 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
4c7d22cb | 8504 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 8505 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 8506 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8507 | set_gdbarch_long_bit (gdbarch, 32); |
8508 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8509 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8510 | break; | |
0dadbba0 | 8511 | case MIPS_ABI_EABI32: |
25ab4790 | 8512 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 8513 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 8514 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8515 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 8516 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8517 | set_gdbarch_long_bit (gdbarch, 32); |
8518 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8519 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8520 | break; | |
0dadbba0 | 8521 | case MIPS_ABI_EABI64: |
25ab4790 | 8522 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 8523 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 8524 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8525 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 8526 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8527 | set_gdbarch_long_bit (gdbarch, 64); |
8528 | set_gdbarch_ptr_bit (gdbarch, 64); | |
8529 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8530 | break; | |
0dadbba0 | 8531 | case MIPS_ABI_N32: |
25ab4790 | 8532 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 8533 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 8534 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8535 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 8536 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
8537 | set_gdbarch_long_bit (gdbarch, 32); |
8538 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8539 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 8540 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 8541 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
28d169de KB |
8542 | break; |
8543 | case MIPS_ABI_N64: | |
25ab4790 | 8544 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 8545 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 8546 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8547 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
8548 | tdep->default_mask_address_p = 0; |
8549 | set_gdbarch_long_bit (gdbarch, 64); | |
8550 | set_gdbarch_ptr_bit (gdbarch, 64); | |
8551 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 8552 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 8553 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
0dadbba0 | 8554 | break; |
c2d11a7d | 8555 | default: |
e2e0b3e5 | 8556 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); |
c2d11a7d JM |
8557 | } |
8558 | ||
22e47e37 FF |
8559 | /* GCC creates a pseudo-section whose name specifies the size of |
8560 | longs, since -mlong32 or -mlong64 may be used independent of | |
8561 | other options. How those options affect pointer sizes is ABI and | |
8562 | architecture dependent, so use them to override the default sizes | |
8563 | set by the ABI. This table shows the relationship between ABI, | |
8564 | -mlongXX, and size of pointers: | |
8565 | ||
8566 | ABI -mlongXX ptr bits | |
8567 | --- -------- -------- | |
8568 | o32 32 32 | |
8569 | o32 64 32 | |
8570 | n32 32 32 | |
8571 | n32 64 64 | |
8572 | o64 32 32 | |
8573 | o64 64 64 | |
8574 | n64 32 32 | |
8575 | n64 64 64 | |
8576 | eabi32 32 32 | |
8577 | eabi32 64 32 | |
8578 | eabi64 32 32 | |
8579 | eabi64 64 64 | |
8580 | ||
8581 | Note that for o32 and eabi32, pointers are always 32 bits | |
8582 | regardless of any -mlongXX option. For all others, pointers and | |
025bb325 | 8583 | longs are the same, as set by -mlongXX or set by defaults. */ |
22e47e37 FF |
8584 | |
8585 | if (info.abfd != NULL) | |
8586 | { | |
8587 | int long_bit = 0; | |
8588 | ||
8589 | bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); | |
8590 | if (long_bit) | |
8591 | { | |
8592 | set_gdbarch_long_bit (gdbarch, long_bit); | |
8593 | switch (mips_abi) | |
8594 | { | |
8595 | case MIPS_ABI_O32: | |
8596 | case MIPS_ABI_EABI32: | |
8597 | break; | |
8598 | case MIPS_ABI_N32: | |
8599 | case MIPS_ABI_O64: | |
8600 | case MIPS_ABI_N64: | |
8601 | case MIPS_ABI_EABI64: | |
8602 | set_gdbarch_ptr_bit (gdbarch, long_bit); | |
8603 | break; | |
8604 | default: | |
8605 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); | |
8606 | } | |
8607 | } | |
8608 | } | |
8609 | ||
a5ea2558 AC |
8610 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
8611 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
8612 | comment: | |
8613 | ||
8614 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
8615 | flag in object files because to do so would make it impossible to | |
102182a9 | 8616 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 8617 | unnecessarily restrictive. |
361d1df0 | 8618 | |
a5ea2558 AC |
8619 | We could solve this problem by adding "-gp32" multilibs to gcc, |
8620 | but to set this flag before gcc is built with such multilibs will | |
8621 | break too many systems.'' | |
8622 | ||
8623 | But even more unhelpfully, the default linker output target for | |
8624 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
8625 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 8626 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
8627 | this flag to detect 32-bit mode would do the wrong thing given |
8628 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 8629 | as 32-bit programs by default. */ |
a5ea2558 | 8630 | |
6c997a34 | 8631 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 8632 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
c2d11a7d | 8633 | |
102182a9 MS |
8634 | /* Add/remove bits from an address. The MIPS needs be careful to |
8635 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
8636 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
8637 | ||
58dfe9ff AC |
8638 | /* Unwind the frame. */ |
8639 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
30244cd8 | 8640 | set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); |
b8a22b94 | 8641 | set_gdbarch_dummy_id (gdbarch, mips_dummy_id); |
10312cc4 | 8642 | |
102182a9 | 8643 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 8644 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
8645 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
8646 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
6d82d43b AC |
8647 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, |
8648 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 8649 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 8650 | |
025bb325 | 8651 | /* MIPS version of CALL_DUMMY. */ |
c2d11a7d | 8652 | |
2c76a0c7 JB |
8653 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
8654 | set_gdbarch_push_dummy_code (gdbarch, mips_push_dummy_code); | |
dc604539 | 8655 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 8656 | |
1bab7383 YQ |
8657 | set_gdbarch_print_float_info (gdbarch, mips_print_float_info); |
8658 | ||
87783b8b AC |
8659 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
8660 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
8661 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
8662 | ||
f7b9e9fc | 8663 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
04180708 YQ |
8664 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, mips_breakpoint_kind_from_pc); |
8665 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, mips_sw_breakpoint_from_kind); | |
c8cef75f MR |
8666 | set_gdbarch_adjust_breakpoint_address (gdbarch, |
8667 | mips_adjust_breakpoint_address); | |
f7b9e9fc AC |
8668 | |
8669 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 8670 | |
c9cf6e20 | 8671 | set_gdbarch_stack_frame_destroyed_p (gdbarch, mips_stack_frame_destroyed_p); |
97ab0fdd | 8672 | |
fc0c74b1 AC |
8673 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
8674 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
8675 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 8676 | |
a4b8ebc8 | 8677 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 8678 | |
e11c53d2 | 8679 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 8680 | |
471b9d15 MR |
8681 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); |
8682 | if (mips_abi == MIPS_ABI_N64) | |
8683 | set_gdbarch_disassembler_options_implicit | |
8684 | (gdbarch, (const char *) mips_disassembler_options_n64); | |
8685 | else if (mips_abi == MIPS_ABI_N32) | |
8686 | set_gdbarch_disassembler_options_implicit | |
8687 | (gdbarch, (const char *) mips_disassembler_options_n32); | |
9dae60cc | 8688 | else |
471b9d15 MR |
8689 | set_gdbarch_disassembler_options_implicit |
8690 | (gdbarch, (const char *) mips_disassembler_options_o32); | |
8691 | set_gdbarch_disassembler_options (gdbarch, &mips_disassembler_options); | |
8692 | set_gdbarch_valid_disassembler_options (gdbarch, | |
8693 | disassembler_options_mips ()); | |
e5ab0dce | 8694 | |
d92524f1 PM |
8695 | /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint, |
8696 | HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint | |
3a3bc038 | 8697 | need to all be folded into the target vector. Since they are |
d92524f1 PM |
8698 | being used as guards for target_stopped_by_watchpoint, why not have |
8699 | target_stopped_by_watchpoint return the type of watchpoint that the code | |
3a3bc038 AC |
8700 | is sitting on? */ |
8701 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
8702 | ||
e7d6a6d2 | 8703 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
757a7cc6 | 8704 | |
14132e89 MR |
8705 | /* NOTE drow/2012-04-25: We overload the core solib trampoline code |
8706 | to support MIPS16. This is a bad thing. Make sure not to do it | |
8707 | if we have an OS ABI that actually supports shared libraries, since | |
8708 | shared library support is more important. If we have an OS someday | |
8709 | that supports both shared libraries and MIPS16, we'll have to find | |
8710 | a better place for these. | |
8711 | macro/2012-04-25: But that applies to return trampolines only and | |
8712 | currently no MIPS OS ABI uses shared libraries that have them. */ | |
8713 | set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); | |
8714 | ||
025bb325 MS |
8715 | set_gdbarch_single_step_through_delay (gdbarch, |
8716 | mips_single_step_through_delay); | |
3352ef37 | 8717 | |
0d5de010 DJ |
8718 | /* Virtual tables. */ |
8719 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
8720 | ||
29709017 DJ |
8721 | mips_register_g_packet_guesses (gdbarch); |
8722 | ||
6de918a6 | 8723 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
c1e1314d | 8724 | info.tdesc_data = tdesc_data.get (); |
6de918a6 | 8725 | gdbarch_init_osabi (info, gdbarch); |
757a7cc6 | 8726 | |
9aac7884 MR |
8727 | /* The hook may have adjusted num_regs, fetch the final value and |
8728 | set pc_regnum and sp_regnum now that it has been fixed. */ | |
9aac7884 MR |
8729 | num_regs = gdbarch_num_regs (gdbarch); |
8730 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); | |
8731 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
8732 | ||
5792a79b | 8733 | /* Unwind the frame. */ |
b8a22b94 DJ |
8734 | dwarf2_append_unwinders (gdbarch); |
8735 | frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind); | |
8736 | frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind); | |
4cc0665f | 8737 | frame_unwind_append_unwinder (gdbarch, &mips_micro_frame_unwind); |
b8a22b94 | 8738 | frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind); |
2bd0c3d7 | 8739 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
eec63939 | 8740 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
45c9dd44 | 8741 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
4cc0665f | 8742 | frame_base_append_sniffer (gdbarch, mips_micro_frame_base_sniffer); |
45c9dd44 | 8743 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); |
5792a79b | 8744 | |
c1e1314d | 8745 | if (tdesc_data != nullptr) |
f8b73d13 DJ |
8746 | { |
8747 | set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); | |
c1e1314d | 8748 | tdesc_use_registers (gdbarch, info.target_desc, std::move (tdesc_data)); |
f8b73d13 DJ |
8749 | |
8750 | /* Override the normal target description methods to handle our | |
8751 | dual real and pseudo registers. */ | |
8752 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
025bb325 MS |
8753 | set_gdbarch_register_reggroup_p (gdbarch, |
8754 | mips_tdesc_register_reggroup_p); | |
f8b73d13 DJ |
8755 | |
8756 | num_regs = gdbarch_num_regs (gdbarch); | |
8757 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
8758 | set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs); | |
8759 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
8760 | } | |
8761 | ||
8762 | /* Add ABI-specific aliases for the registers. */ | |
8763 | if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) | |
8764 | for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++) | |
8765 | user_reg_add (gdbarch, mips_n32_n64_aliases[i].name, | |
8766 | value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); | |
8767 | else | |
8768 | for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) | |
8769 | user_reg_add (gdbarch, mips_o32_aliases[i].name, | |
8770 | value_of_mips_user_reg, &mips_o32_aliases[i].regnum); | |
8771 | ||
8772 | /* Add some other standard aliases. */ | |
8773 | for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) | |
8774 | user_reg_add (gdbarch, mips_register_aliases[i].name, | |
8775 | value_of_mips_user_reg, &mips_register_aliases[i].regnum); | |
8776 | ||
865093a3 AR |
8777 | for (i = 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++) |
8778 | user_reg_add (gdbarch, mips_numeric_register_aliases[i].name, | |
8779 | value_of_mips_user_reg, | |
8780 | &mips_numeric_register_aliases[i].regnum); | |
8781 | ||
4b9b3959 AC |
8782 | return gdbarch; |
8783 | } | |
8784 | ||
2e4ebe70 | 8785 | static void |
eb4c3f4a TT |
8786 | mips_abi_update (const char *ignore_args, |
8787 | int from_tty, struct cmd_list_element *c) | |
2e4ebe70 DJ |
8788 | { |
8789 | struct gdbarch_info info; | |
8790 | ||
8791 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
8792 | mips_gdbarch_init will take care of the rest. */ | |
8793 | gdbarch_info_init (&info); | |
8794 | gdbarch_update_p (info); | |
8795 | } | |
8796 | ||
ad188201 KB |
8797 | /* Print out which MIPS ABI is in use. */ |
8798 | ||
8799 | static void | |
1f8ca57c JB |
8800 | show_mips_abi (struct ui_file *file, |
8801 | int from_tty, | |
8802 | struct cmd_list_element *ignored_cmd, | |
8803 | const char *ignored_value) | |
ad188201 | 8804 | { |
f5656ead | 8805 | if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips) |
1f8ca57c JB |
8806 | fprintf_filtered |
8807 | (file, | |
8808 | "The MIPS ABI is unknown because the current architecture " | |
8809 | "is not MIPS.\n"); | |
ad188201 KB |
8810 | else |
8811 | { | |
8812 | enum mips_abi global_abi = global_mips_abi (); | |
f5656ead | 8813 | enum mips_abi actual_abi = mips_abi (target_gdbarch ()); |
ad188201 KB |
8814 | const char *actual_abi_str = mips_abi_strings[actual_abi]; |
8815 | ||
8816 | if (global_abi == MIPS_ABI_UNKNOWN) | |
1f8ca57c JB |
8817 | fprintf_filtered |
8818 | (file, | |
8819 | "The MIPS ABI is set automatically (currently \"%s\").\n", | |
6d82d43b | 8820 | actual_abi_str); |
ad188201 | 8821 | else if (global_abi == actual_abi) |
1f8ca57c JB |
8822 | fprintf_filtered |
8823 | (file, | |
8824 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6d82d43b | 8825 | actual_abi_str); |
ad188201 KB |
8826 | else |
8827 | { | |
8828 | /* Probably shouldn't happen... */ | |
025bb325 MS |
8829 | fprintf_filtered (file, |
8830 | "The (auto detected) MIPS ABI \"%s\" is in use " | |
8831 | "even though the user setting was \"%s\".\n", | |
6d82d43b | 8832 | actual_abi_str, mips_abi_strings[global_abi]); |
ad188201 KB |
8833 | } |
8834 | } | |
8835 | } | |
8836 | ||
4cc0665f MR |
8837 | /* Print out which MIPS compressed ISA encoding is used. */ |
8838 | ||
8839 | static void | |
8840 | show_mips_compression (struct ui_file *file, int from_tty, | |
8841 | struct cmd_list_element *c, const char *value) | |
8842 | { | |
8843 | fprintf_filtered (file, _("The compressed ISA encoding used is %s.\n"), | |
8844 | value); | |
8845 | } | |
8846 | ||
a4f320fd MR |
8847 | /* Return a textual name for MIPS FPU type FPU_TYPE. */ |
8848 | ||
8849 | static const char * | |
8850 | mips_fpu_type_str (enum mips_fpu_type fpu_type) | |
8851 | { | |
8852 | switch (fpu_type) | |
8853 | { | |
8854 | case MIPS_FPU_NONE: | |
8855 | return "none"; | |
8856 | case MIPS_FPU_SINGLE: | |
8857 | return "single"; | |
8858 | case MIPS_FPU_DOUBLE: | |
8859 | return "double"; | |
8860 | default: | |
8861 | return "???"; | |
8862 | } | |
8863 | } | |
8864 | ||
4b9b3959 | 8865 | static void |
72a155b4 | 8866 | mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
4b9b3959 | 8867 | { |
72a155b4 | 8868 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4b9b3959 | 8869 | if (tdep != NULL) |
c2d11a7d | 8870 | { |
acdb74a0 AC |
8871 | int ef_mips_arch; |
8872 | int ef_mips_32bitmode; | |
f49e4e6d | 8873 | /* Determine the ISA. */ |
acdb74a0 AC |
8874 | switch (tdep->elf_flags & EF_MIPS_ARCH) |
8875 | { | |
8876 | case E_MIPS_ARCH_1: | |
8877 | ef_mips_arch = 1; | |
8878 | break; | |
8879 | case E_MIPS_ARCH_2: | |
8880 | ef_mips_arch = 2; | |
8881 | break; | |
8882 | case E_MIPS_ARCH_3: | |
8883 | ef_mips_arch = 3; | |
8884 | break; | |
8885 | case E_MIPS_ARCH_4: | |
93d56215 | 8886 | ef_mips_arch = 4; |
acdb74a0 AC |
8887 | break; |
8888 | default: | |
93d56215 | 8889 | ef_mips_arch = 0; |
acdb74a0 AC |
8890 | break; |
8891 | } | |
f49e4e6d | 8892 | /* Determine the size of a pointer. */ |
acdb74a0 | 8893 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); |
4b9b3959 AC |
8894 | fprintf_unfiltered (file, |
8895 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 8896 | tdep->elf_flags); |
4b9b3959 | 8897 | fprintf_unfiltered (file, |
acdb74a0 AC |
8898 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
8899 | ef_mips_32bitmode); | |
8900 | fprintf_unfiltered (file, | |
8901 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
8902 | ef_mips_arch); | |
8903 | fprintf_unfiltered (file, | |
8904 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 8905 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b | 8906 | fprintf_unfiltered (file, |
025bb325 MS |
8907 | "mips_dump_tdep: " |
8908 | "mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 8909 | mips_mask_address_p (tdep), |
4014092b | 8910 | tdep->default_mask_address_p); |
c2d11a7d | 8911 | } |
4b9b3959 AC |
8912 | fprintf_unfiltered (file, |
8913 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
8914 | MIPS_DEFAULT_FPU_TYPE, | |
a4f320fd | 8915 | mips_fpu_type_str (MIPS_DEFAULT_FPU_TYPE)); |
74ed0bb4 MD |
8916 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", |
8917 | MIPS_EABI (gdbarch)); | |
4b9b3959 AC |
8918 | fprintf_unfiltered (file, |
8919 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
74ed0bb4 | 8920 | MIPS_FPU_TYPE (gdbarch), |
a4f320fd | 8921 | mips_fpu_type_str (MIPS_FPU_TYPE (gdbarch))); |
c2d11a7d JM |
8922 | } |
8923 | ||
6c265988 | 8924 | void _initialize_mips_tdep (); |
c906108c | 8925 | void |
6c265988 | 8926 | _initialize_mips_tdep () |
c906108c SS |
8927 | { |
8928 | static struct cmd_list_element *mipsfpulist = NULL; | |
c906108c | 8929 | |
6d82d43b | 8930 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
8931 | if (MIPS_ABI_LAST + 1 |
8932 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
e2e0b3e5 | 8933 | internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync")); |
2e4ebe70 | 8934 | |
4b9b3959 | 8935 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 8936 | |
4eb0ad19 DJ |
8937 | /* Create feature sets with the appropriate properties. The values |
8938 | are not important. */ | |
51a948fd | 8939 | mips_tdesc_gp32 = allocate_target_description ().release (); |
4eb0ad19 DJ |
8940 | set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, ""); |
8941 | ||
51a948fd | 8942 | mips_tdesc_gp64 = allocate_target_description ().release (); |
4eb0ad19 DJ |
8943 | set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, ""); |
8944 | ||
025bb325 | 8945 | /* Add root prefix command for all "set mips"/"show mips" commands. */ |
0743fc83 TT |
8946 | add_basic_prefix_cmd ("mips", no_class, |
8947 | _("Various MIPS specific commands."), | |
8948 | &setmipscmdlist, "set mips ", 0, &setlist); | |
a5ea2558 | 8949 | |
0743fc83 TT |
8950 | add_show_prefix_cmd ("mips", no_class, |
8951 | _("Various MIPS specific commands."), | |
8952 | &showmipscmdlist, "show mips ", 0, &showlist); | |
a5ea2558 | 8953 | |
025bb325 | 8954 | /* Allow the user to override the ABI. */ |
7ab04401 AC |
8955 | add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, |
8956 | &mips_abi_string, _("\ | |
8957 | Set the MIPS ABI used by this program."), _("\ | |
8958 | Show the MIPS ABI used by this program."), _("\ | |
8959 | This option can be set to one of:\n\ | |
8960 | auto - the default ABI associated with the current binary\n\ | |
8961 | o32\n\ | |
8962 | o64\n\ | |
8963 | n32\n\ | |
8964 | n64\n\ | |
8965 | eabi32\n\ | |
8966 | eabi64"), | |
8967 | mips_abi_update, | |
8968 | show_mips_abi, | |
8969 | &setmipscmdlist, &showmipscmdlist); | |
2e4ebe70 | 8970 | |
4cc0665f MR |
8971 | /* Allow the user to set the ISA to assume for compressed code if ELF |
8972 | file flags don't tell or there is no program file selected. This | |
8973 | setting is updated whenever unambiguous ELF file flags are interpreted, | |
8974 | and carried over to subsequent sessions. */ | |
8975 | add_setshow_enum_cmd ("compression", class_obscure, mips_compression_strings, | |
8976 | &mips_compression_string, _("\ | |
8977 | Set the compressed ISA encoding used by MIPS code."), _("\ | |
8978 | Show the compressed ISA encoding used by MIPS code."), _("\ | |
8979 | Select the compressed ISA encoding used in functions that have no symbol\n\ | |
8980 | information available. The encoding can be set to either of:\n\ | |
8981 | mips16\n\ | |
8982 | micromips\n\ | |
8983 | and is updated automatically from ELF file flags if available."), | |
8984 | mips_abi_update, | |
8985 | show_mips_compression, | |
8986 | &setmipscmdlist, &showmipscmdlist); | |
8987 | ||
c906108c SS |
8988 | /* Let the user turn off floating point and set the fence post for |
8989 | heuristic_proc_start. */ | |
8990 | ||
3b6acaee TT |
8991 | add_basic_prefix_cmd ("mipsfpu", class_support, |
8992 | _("Set use of MIPS floating-point coprocessor."), | |
8993 | &mipsfpulist, "set mipsfpu ", 0, &setlist); | |
c906108c | 8994 | add_cmd ("single", class_support, set_mipsfpu_single_command, |
1a966eab | 8995 | _("Select single-precision MIPS floating-point coprocessor."), |
c906108c SS |
8996 | &mipsfpulist); |
8997 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
1a966eab | 8998 | _("Select double-precision MIPS floating-point coprocessor."), |
c906108c SS |
8999 | &mipsfpulist); |
9000 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
9001 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
9002 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
9003 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
1a966eab | 9004 | _("Select no MIPS floating-point coprocessor."), &mipsfpulist); |
c906108c SS |
9005 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
9006 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
9007 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
9008 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
1a966eab | 9009 | _("Select MIPS floating-point coprocessor automatically."), |
c906108c SS |
9010 | &mipsfpulist); |
9011 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
1a966eab | 9012 | _("Show current use of MIPS floating-point coprocessor target."), |
c906108c SS |
9013 | &showlist); |
9014 | ||
c906108c SS |
9015 | /* We really would like to have both "0" and "unlimited" work, but |
9016 | command.c doesn't deal with that. So make it a var_zinteger | |
9017 | because the user can always use "999999" or some such for unlimited. */ | |
6bcadd06 | 9018 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
7915a72c AC |
9019 | &heuristic_fence_post, _("\ |
9020 | Set the distance searched for the start of a function."), _("\ | |
9021 | Show the distance searched for the start of a function."), _("\ | |
c906108c SS |
9022 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
9023 | program for the start of a function. This command sets the distance of the\n\ | |
7915a72c | 9024 | search. The only need to set it is when debugging a stripped executable."), |
2c5b56ce | 9025 | reinit_frame_cache_sfunc, |
025bb325 MS |
9026 | NULL, /* FIXME: i18n: The distance searched for |
9027 | the start of a function is %s. */ | |
6bcadd06 | 9028 | &setlist, &showlist); |
c906108c SS |
9029 | |
9030 | /* Allow the user to control whether the upper bits of 64-bit | |
9031 | addresses should be zeroed. */ | |
7915a72c AC |
9032 | add_setshow_auto_boolean_cmd ("mask-address", no_class, |
9033 | &mask_address_var, _("\ | |
9034 | Set zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
9035 | Show zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
cce7e648 | 9036 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\ |
7915a72c | 9037 | allow GDB to determine the correct value."), |
08546159 AC |
9038 | NULL, show_mask_address, |
9039 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
9040 | |
9041 | /* Allow the user to control the size of 32 bit registers within the | |
9042 | raw remote packet. */ | |
b3f42336 | 9043 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
7915a72c AC |
9044 | &mips64_transfers_32bit_regs_p, _("\ |
9045 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
9046 | _("\ | |
9047 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
9048 | _("\ | |
719ec221 AC |
9049 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
9050 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
7915a72c | 9051 | 64 bits for others. Use \"off\" to disable compatibility mode"), |
2c5b56ce | 9052 | set_mips64_transfers_32bit_regs, |
025bb325 MS |
9053 | NULL, /* FIXME: i18n: Compatibility with 64-bit |
9054 | MIPS target that transfers 32-bit | |
9055 | quantities is %s. */ | |
7915a72c | 9056 | &setlist, &showlist); |
9ace0497 | 9057 | |
025bb325 | 9058 | /* Debug this files internals. */ |
ccce17b0 YQ |
9059 | add_setshow_zuinteger_cmd ("mips", class_maintenance, |
9060 | &mips_debug, _("\ | |
7915a72c AC |
9061 | Set mips debugging."), _("\ |
9062 | Show mips debugging."), _("\ | |
9063 | When non-zero, mips specific debugging is enabled."), | |
ccce17b0 YQ |
9064 | NULL, |
9065 | NULL, /* FIXME: i18n: Mips debugging is | |
9066 | currently %s. */ | |
9067 | &setdebuglist, &showdebuglist); | |
c906108c | 9068 | } |