Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
e2882c85 | 3 | Copyright (C) 1988-2018 Free Software Foundation, Inc. |
bf64bfd6 | 4 | |
c906108c SS |
5 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
6 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
7 | ||
c5aa993b | 8 | This file is part of GDB. |
c906108c | 9 | |
c5aa993b JM |
10 | This program is free software; you can redistribute it and/or modify |
11 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 12 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 13 | (at your option) any later version. |
c906108c | 14 | |
c5aa993b JM |
15 | This program is distributed in the hope that it will be useful, |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
c906108c | 19 | |
c5aa993b | 20 | You should have received a copy of the GNU General Public License |
a9762ec7 | 21 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
22 | |
23 | #include "defs.h" | |
c906108c SS |
24 | #include "frame.h" |
25 | #include "inferior.h" | |
26 | #include "symtab.h" | |
27 | #include "value.h" | |
28 | #include "gdbcmd.h" | |
29 | #include "language.h" | |
30 | #include "gdbcore.h" | |
31 | #include "symfile.h" | |
32 | #include "objfiles.h" | |
33 | #include "gdbtypes.h" | |
34 | #include "target.h" | |
28d069e6 | 35 | #include "arch-utils.h" |
4e052eda | 36 | #include "regcache.h" |
70f80edf | 37 | #include "osabi.h" |
d1973055 | 38 | #include "mips-tdep.h" |
fe898f56 | 39 | #include "block.h" |
a4b8ebc8 | 40 | #include "reggroups.h" |
c906108c | 41 | #include "opcode/mips.h" |
c2d11a7d JM |
42 | #include "elf/mips.h" |
43 | #include "elf-bfd.h" | |
2475bac3 | 44 | #include "symcat.h" |
a4b8ebc8 | 45 | #include "sim-regno.h" |
a89aa300 | 46 | #include "dis-asm.h" |
e47ad6c0 | 47 | #include "disasm.h" |
edfae063 AC |
48 | #include "frame-unwind.h" |
49 | #include "frame-base.h" | |
50 | #include "trad-frame.h" | |
7d9b040b | 51 | #include "infcall.h" |
29709017 DJ |
52 | #include "remote.h" |
53 | #include "target-descriptions.h" | |
2bd0c3d7 | 54 | #include "dwarf2-frame.h" |
f8b73d13 | 55 | #include "user-regs.h" |
79a45b7d | 56 | #include "valprint.h" |
175ff332 | 57 | #include "ax.h" |
f69fdf9b | 58 | #include "target-float.h" |
325fac50 | 59 | #include <algorithm> |
c906108c | 60 | |
8d5f9dcb DJ |
61 | static const struct objfile_data *mips_pdr_data; |
62 | ||
5bbcb741 | 63 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 64 | |
ab50adb6 MR |
65 | static int mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, |
66 | ULONGEST inst); | |
67 | static int micromips_instruction_has_delay_slot (ULONGEST insn, int mustbe32); | |
68 | static int mips16_instruction_has_delay_slot (unsigned short inst, | |
69 | int mustbe32); | |
70 | ||
71 | static int mips32_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, | |
72 | CORE_ADDR addr); | |
73 | static int micromips_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, | |
74 | CORE_ADDR addr, int mustbe32); | |
75 | static int mips16_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, | |
76 | CORE_ADDR addr, int mustbe32); | |
4cc0665f | 77 | |
1bab7383 YQ |
78 | static void mips_print_float_info (struct gdbarch *, struct ui_file *, |
79 | struct frame_info *, const char *); | |
80 | ||
24e05951 | 81 | /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ |
dd824b04 DJ |
82 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ |
83 | #define ST0_FR (1 << 26) | |
84 | ||
b0069a17 AC |
85 | /* The sizes of floating point registers. */ |
86 | ||
87 | enum | |
88 | { | |
89 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
90 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
91 | }; | |
92 | ||
1a69e1e4 DJ |
93 | enum |
94 | { | |
95 | MIPS32_REGSIZE = 4, | |
96 | MIPS64_REGSIZE = 8 | |
97 | }; | |
0dadbba0 | 98 | |
2e4ebe70 DJ |
99 | static const char *mips_abi_string; |
100 | ||
40478521 | 101 | static const char *const mips_abi_strings[] = { |
2e4ebe70 DJ |
102 | "auto", |
103 | "n32", | |
104 | "o32", | |
28d169de | 105 | "n64", |
2e4ebe70 DJ |
106 | "o64", |
107 | "eabi32", | |
108 | "eabi64", | |
109 | NULL | |
110 | }; | |
111 | ||
44f1c4d7 YQ |
112 | /* Enum describing the different kinds of breakpoints. */ |
113 | ||
114 | enum mips_breakpoint_kind | |
115 | { | |
116 | /* 16-bit MIPS16 mode breakpoint. */ | |
117 | MIPS_BP_KIND_MIPS16 = 2, | |
118 | ||
119 | /* 16-bit microMIPS mode breakpoint. */ | |
120 | MIPS_BP_KIND_MICROMIPS16 = 3, | |
121 | ||
122 | /* 32-bit standard MIPS mode breakpoint. */ | |
123 | MIPS_BP_KIND_MIPS32 = 4, | |
124 | ||
125 | /* 32-bit microMIPS mode breakpoint. */ | |
126 | MIPS_BP_KIND_MICROMIPS32 = 5, | |
127 | }; | |
128 | ||
4cc0665f MR |
129 | /* For backwards compatibility we default to MIPS16. This flag is |
130 | overridden as soon as unambiguous ELF file flags tell us the | |
131 | compressed ISA encoding used. */ | |
132 | static const char mips_compression_mips16[] = "mips16"; | |
133 | static const char mips_compression_micromips[] = "micromips"; | |
134 | static const char *const mips_compression_strings[] = | |
135 | { | |
136 | mips_compression_mips16, | |
137 | mips_compression_micromips, | |
138 | NULL | |
139 | }; | |
140 | ||
141 | static const char *mips_compression_string = mips_compression_mips16; | |
142 | ||
f8b73d13 DJ |
143 | /* The standard register names, and all the valid aliases for them. */ |
144 | struct register_alias | |
145 | { | |
146 | const char *name; | |
147 | int regnum; | |
148 | }; | |
149 | ||
150 | /* Aliases for o32 and most other ABIs. */ | |
151 | const struct register_alias mips_o32_aliases[] = { | |
152 | { "ta0", 12 }, | |
153 | { "ta1", 13 }, | |
154 | { "ta2", 14 }, | |
155 | { "ta3", 15 } | |
156 | }; | |
157 | ||
158 | /* Aliases for n32 and n64. */ | |
159 | const struct register_alias mips_n32_n64_aliases[] = { | |
160 | { "ta0", 8 }, | |
161 | { "ta1", 9 }, | |
162 | { "ta2", 10 }, | |
163 | { "ta3", 11 } | |
164 | }; | |
165 | ||
166 | /* Aliases for ABI-independent registers. */ | |
167 | const struct register_alias mips_register_aliases[] = { | |
168 | /* The architecture manuals specify these ABI-independent names for | |
169 | the GPRs. */ | |
170 | #define R(n) { "r" #n, n } | |
171 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
172 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
173 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
174 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
175 | #undef R | |
176 | ||
177 | /* k0 and k1 are sometimes called these instead (for "kernel | |
178 | temp"). */ | |
179 | { "kt0", 26 }, | |
180 | { "kt1", 27 }, | |
181 | ||
182 | /* This is the traditional GDB name for the CP0 status register. */ | |
183 | { "sr", MIPS_PS_REGNUM }, | |
184 | ||
185 | /* This is the traditional GDB name for the CP0 BadVAddr register. */ | |
186 | { "bad", MIPS_EMBED_BADVADDR_REGNUM }, | |
187 | ||
188 | /* This is the traditional GDB name for the FCSR. */ | |
189 | { "fsr", MIPS_EMBED_FP0_REGNUM + 32 } | |
190 | }; | |
191 | ||
865093a3 AR |
192 | const struct register_alias mips_numeric_register_aliases[] = { |
193 | #define R(n) { #n, n } | |
194 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
195 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
196 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
197 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
198 | #undef R | |
199 | }; | |
200 | ||
c906108c SS |
201 | #ifndef MIPS_DEFAULT_FPU_TYPE |
202 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
203 | #endif | |
204 | static int mips_fpu_type_auto = 1; | |
205 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 206 | |
ccce17b0 | 207 | static unsigned int mips_debug = 0; |
7a292a7a | 208 | |
29709017 DJ |
209 | /* Properties (for struct target_desc) describing the g/G packet |
210 | layout. */ | |
211 | #define PROPERTY_GP32 "internal: transfers-32bit-registers" | |
212 | #define PROPERTY_GP64 "internal: transfers-64bit-registers" | |
213 | ||
4eb0ad19 DJ |
214 | struct target_desc *mips_tdesc_gp32; |
215 | struct target_desc *mips_tdesc_gp64; | |
216 | ||
56cea623 AC |
217 | const struct mips_regnum * |
218 | mips_regnum (struct gdbarch *gdbarch) | |
219 | { | |
220 | return gdbarch_tdep (gdbarch)->regnum; | |
221 | } | |
222 | ||
223 | static int | |
224 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
225 | { | |
226 | return mips_regnum (gdbarch)->fp0 + 12; | |
227 | } | |
228 | ||
004159a2 MR |
229 | /* Return 1 if REGNUM refers to a floating-point general register, raw |
230 | or cooked. Otherwise return 0. */ | |
231 | ||
232 | static int | |
233 | mips_float_register_p (struct gdbarch *gdbarch, int regnum) | |
234 | { | |
235 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
236 | ||
237 | return (rawnum >= mips_regnum (gdbarch)->fp0 | |
238 | && rawnum < mips_regnum (gdbarch)->fp0 + 32); | |
239 | } | |
240 | ||
74ed0bb4 MD |
241 | #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \ |
242 | == MIPS_ABI_EABI32 \ | |
243 | || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64) | |
c2d11a7d | 244 | |
025bb325 MS |
245 | #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \ |
246 | (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum) | |
c2d11a7d | 247 | |
025bb325 MS |
248 | #define MIPS_LAST_ARG_REGNUM(gdbarch) \ |
249 | (gdbarch_tdep (gdbarch)->mips_last_arg_regnum) | |
c2d11a7d | 250 | |
74ed0bb4 | 251 | #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type) |
c2d11a7d | 252 | |
d1973055 KB |
253 | /* Return the MIPS ABI associated with GDBARCH. */ |
254 | enum mips_abi | |
255 | mips_abi (struct gdbarch *gdbarch) | |
256 | { | |
257 | return gdbarch_tdep (gdbarch)->mips_abi; | |
258 | } | |
259 | ||
4246e332 | 260 | int |
1b13c4f6 | 261 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 | 262 | { |
29709017 DJ |
263 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
264 | ||
265 | /* If we know how big the registers are, use that size. */ | |
266 | if (tdep->register_size_valid_p) | |
267 | return tdep->register_size; | |
268 | ||
269 | /* Fall back to the previous behavior. */ | |
4246e332 AC |
270 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word |
271 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
272 | } | |
273 | ||
b3464d03 PA |
274 | /* Max saved register size. */ |
275 | #define MAX_MIPS_ABI_REGSIZE 8 | |
276 | ||
025bb325 | 277 | /* Return the currently configured (or set) saved register size. */ |
480d3dd2 | 278 | |
e6bc2e8a | 279 | unsigned int |
13326b4e | 280 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 281 | { |
1a69e1e4 DJ |
282 | switch (mips_abi (gdbarch)) |
283 | { | |
284 | case MIPS_ABI_EABI32: | |
285 | case MIPS_ABI_O32: | |
286 | return 4; | |
287 | case MIPS_ABI_N32: | |
288 | case MIPS_ABI_N64: | |
289 | case MIPS_ABI_O64: | |
290 | case MIPS_ABI_EABI64: | |
291 | return 8; | |
292 | case MIPS_ABI_UNKNOWN: | |
293 | case MIPS_ABI_LAST: | |
294 | default: | |
295 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
296 | } | |
d929b26f AC |
297 | } |
298 | ||
4cc0665f MR |
299 | /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here |
300 | are some functions to handle addresses associated with compressed | |
301 | code including but not limited to testing, setting, or clearing | |
302 | bit 0 of such addresses. */ | |
742c84f6 | 303 | |
4cc0665f MR |
304 | /* Return one iff compressed code is the MIPS16 instruction set. */ |
305 | ||
306 | static int | |
307 | is_mips16_isa (struct gdbarch *gdbarch) | |
308 | { | |
309 | return gdbarch_tdep (gdbarch)->mips_isa == ISA_MIPS16; | |
310 | } | |
311 | ||
312 | /* Return one iff compressed code is the microMIPS instruction set. */ | |
313 | ||
314 | static int | |
315 | is_micromips_isa (struct gdbarch *gdbarch) | |
316 | { | |
317 | return gdbarch_tdep (gdbarch)->mips_isa == ISA_MICROMIPS; | |
318 | } | |
319 | ||
320 | /* Return one iff ADDR denotes compressed code. */ | |
321 | ||
322 | static int | |
323 | is_compact_addr (CORE_ADDR addr) | |
742c84f6 MR |
324 | { |
325 | return ((addr) & 1); | |
326 | } | |
327 | ||
4cc0665f MR |
328 | /* Return one iff ADDR denotes standard ISA code. */ |
329 | ||
330 | static int | |
331 | is_mips_addr (CORE_ADDR addr) | |
332 | { | |
333 | return !is_compact_addr (addr); | |
334 | } | |
335 | ||
336 | /* Return one iff ADDR denotes MIPS16 code. */ | |
337 | ||
338 | static int | |
339 | is_mips16_addr (struct gdbarch *gdbarch, CORE_ADDR addr) | |
340 | { | |
341 | return is_compact_addr (addr) && is_mips16_isa (gdbarch); | |
342 | } | |
343 | ||
344 | /* Return one iff ADDR denotes microMIPS code. */ | |
345 | ||
346 | static int | |
347 | is_micromips_addr (struct gdbarch *gdbarch, CORE_ADDR addr) | |
348 | { | |
349 | return is_compact_addr (addr) && is_micromips_isa (gdbarch); | |
350 | } | |
351 | ||
352 | /* Strip the ISA (compression) bit off from ADDR. */ | |
353 | ||
742c84f6 | 354 | static CORE_ADDR |
4cc0665f | 355 | unmake_compact_addr (CORE_ADDR addr) |
742c84f6 MR |
356 | { |
357 | return ((addr) & ~(CORE_ADDR) 1); | |
358 | } | |
359 | ||
4cc0665f MR |
360 | /* Add the ISA (compression) bit to ADDR. */ |
361 | ||
742c84f6 | 362 | static CORE_ADDR |
4cc0665f | 363 | make_compact_addr (CORE_ADDR addr) |
742c84f6 MR |
364 | { |
365 | return ((addr) | (CORE_ADDR) 1); | |
366 | } | |
367 | ||
3e29f34a MR |
368 | /* Extern version of unmake_compact_addr; we use a separate function |
369 | so that unmake_compact_addr can be inlined throughout this file. */ | |
370 | ||
371 | CORE_ADDR | |
372 | mips_unmake_compact_addr (CORE_ADDR addr) | |
373 | { | |
374 | return unmake_compact_addr (addr); | |
375 | } | |
376 | ||
71b8ef93 | 377 | /* Functions for setting and testing a bit in a minimal symbol that |
4cc0665f MR |
378 | marks it as MIPS16 or microMIPS function. The MSB of the minimal |
379 | symbol's "info" field is used for this purpose. | |
5a89d8aa | 380 | |
4cc0665f MR |
381 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is |
382 | "special", i.e. refers to a MIPS16 or microMIPS function, and sets | |
383 | one of the "special" bits in a minimal symbol to mark it accordingly. | |
384 | The test checks an ELF-private flag that is valid for true function | |
1bbce132 MR |
385 | symbols only; for synthetic symbols such as for PLT stubs that have |
386 | no ELF-private part at all the MIPS BFD backend arranges for this | |
387 | information to be carried in the asymbol's udata field instead. | |
5a89d8aa | 388 | |
4cc0665f MR |
389 | msymbol_is_mips16 and msymbol_is_micromips test the "special" bit |
390 | in a minimal symbol. */ | |
5a89d8aa | 391 | |
5a89d8aa | 392 | static void |
6d82d43b AC |
393 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
394 | { | |
4cc0665f | 395 | elf_symbol_type *elfsym = (elf_symbol_type *) sym; |
1bbce132 | 396 | unsigned char st_other; |
4cc0665f | 397 | |
1bbce132 MR |
398 | if ((sym->flags & BSF_SYNTHETIC) == 0) |
399 | st_other = elfsym->internal_elf_sym.st_other; | |
400 | else if ((sym->flags & BSF_FUNCTION) != 0) | |
401 | st_other = sym->udata.i; | |
402 | else | |
4cc0665f MR |
403 | return; |
404 | ||
1bbce132 | 405 | if (ELF_ST_IS_MICROMIPS (st_other)) |
3e29f34a | 406 | { |
f161c171 | 407 | MSYMBOL_TARGET_FLAG_MICROMIPS (msym) = 1; |
3e29f34a MR |
408 | SET_MSYMBOL_VALUE_ADDRESS (msym, MSYMBOL_VALUE_RAW_ADDRESS (msym) | 1); |
409 | } | |
1bbce132 | 410 | else if (ELF_ST_IS_MIPS16 (st_other)) |
3e29f34a | 411 | { |
f161c171 | 412 | MSYMBOL_TARGET_FLAG_MIPS16 (msym) = 1; |
3e29f34a MR |
413 | SET_MSYMBOL_VALUE_ADDRESS (msym, MSYMBOL_VALUE_RAW_ADDRESS (msym) | 1); |
414 | } | |
4cc0665f MR |
415 | } |
416 | ||
417 | /* Return one iff MSYM refers to standard ISA code. */ | |
418 | ||
419 | static int | |
420 | msymbol_is_mips (struct minimal_symbol *msym) | |
421 | { | |
f161c171 MR |
422 | return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym) |
423 | | MSYMBOL_TARGET_FLAG_MICROMIPS (msym)); | |
5a89d8aa MS |
424 | } |
425 | ||
4cc0665f MR |
426 | /* Return one iff MSYM refers to MIPS16 code. */ |
427 | ||
71b8ef93 | 428 | static int |
4cc0665f | 429 | msymbol_is_mips16 (struct minimal_symbol *msym) |
71b8ef93 | 430 | { |
f161c171 | 431 | return MSYMBOL_TARGET_FLAG_MIPS16 (msym); |
71b8ef93 MS |
432 | } |
433 | ||
4cc0665f MR |
434 | /* Return one iff MSYM refers to microMIPS code. */ |
435 | ||
436 | static int | |
437 | msymbol_is_micromips (struct minimal_symbol *msym) | |
438 | { | |
f161c171 | 439 | return MSYMBOL_TARGET_FLAG_MICROMIPS (msym); |
4cc0665f MR |
440 | } |
441 | ||
3e29f34a MR |
442 | /* Set the ISA bit in the main symbol too, complementing the corresponding |
443 | minimal symbol setting and reflecting the run-time value of the symbol. | |
444 | The need for comes from the ISA bit having been cleared as code in | |
445 | `_bfd_mips_elf_symbol_processing' separated it into the ELF symbol's | |
446 | `st_other' STO_MIPS16 or STO_MICROMIPS annotation, making the values | |
447 | of symbols referring to compressed code different in GDB to the values | |
448 | used by actual code. That in turn makes them evaluate incorrectly in | |
449 | expressions, producing results different to what the same expressions | |
450 | yield when compiled into the program being debugged. */ | |
451 | ||
452 | static void | |
453 | mips_make_symbol_special (struct symbol *sym, struct objfile *objfile) | |
454 | { | |
455 | if (SYMBOL_CLASS (sym) == LOC_BLOCK) | |
456 | { | |
457 | /* We are in symbol reading so it is OK to cast away constness. */ | |
458 | struct block *block = (struct block *) SYMBOL_BLOCK_VALUE (sym); | |
459 | CORE_ADDR compact_block_start; | |
460 | struct bound_minimal_symbol msym; | |
461 | ||
462 | compact_block_start = BLOCK_START (block) | 1; | |
463 | msym = lookup_minimal_symbol_by_pc (compact_block_start); | |
464 | if (msym.minsym && !msymbol_is_mips (msym.minsym)) | |
465 | { | |
466 | BLOCK_START (block) = compact_block_start; | |
467 | } | |
468 | } | |
469 | } | |
470 | ||
88658117 AC |
471 | /* XFER a value from the big/little/left end of the register. |
472 | Depending on the size of the value it might occupy the entire | |
473 | register or just part of it. Make an allowance for this, aligning | |
474 | things accordingly. */ | |
475 | ||
476 | static void | |
ba32f989 DJ |
477 | mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache, |
478 | int reg_num, int length, | |
870cd05e MK |
479 | enum bfd_endian endian, gdb_byte *in, |
480 | const gdb_byte *out, int buf_offset) | |
88658117 | 481 | { |
88658117 | 482 | int reg_offset = 0; |
72a155b4 UW |
483 | |
484 | gdb_assert (reg_num >= gdbarch_num_regs (gdbarch)); | |
cb1d2653 AC |
485 | /* Need to transfer the left or right part of the register, based on |
486 | the targets byte order. */ | |
88658117 AC |
487 | switch (endian) |
488 | { | |
489 | case BFD_ENDIAN_BIG: | |
72a155b4 | 490 | reg_offset = register_size (gdbarch, reg_num) - length; |
88658117 AC |
491 | break; |
492 | case BFD_ENDIAN_LITTLE: | |
493 | reg_offset = 0; | |
494 | break; | |
6d82d43b | 495 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
496 | reg_offset = 0; |
497 | break; | |
498 | default: | |
e2e0b3e5 | 499 | internal_error (__FILE__, __LINE__, _("bad switch")); |
88658117 AC |
500 | } |
501 | if (mips_debug) | |
cb1d2653 AC |
502 | fprintf_unfiltered (gdb_stderr, |
503 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
504 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
505 | if (mips_debug && out != NULL) |
506 | { | |
507 | int i; | |
cb1d2653 | 508 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 509 | for (i = 0; i < length; i++) |
cb1d2653 | 510 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
511 | } |
512 | if (in != NULL) | |
6d82d43b AC |
513 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
514 | in + buf_offset); | |
88658117 | 515 | if (out != NULL) |
6d82d43b AC |
516 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
517 | out + buf_offset); | |
88658117 AC |
518 | if (mips_debug && in != NULL) |
519 | { | |
520 | int i; | |
cb1d2653 | 521 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 522 | for (i = 0; i < length; i++) |
cb1d2653 | 523 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
524 | } |
525 | if (mips_debug) | |
526 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
527 | } | |
528 | ||
dd824b04 DJ |
529 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
530 | compatiblity mode. A return value of 1 means that we have | |
531 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
532 | ||
533 | static int | |
9c9acae0 | 534 | mips2_fp_compat (struct frame_info *frame) |
dd824b04 | 535 | { |
72a155b4 | 536 | struct gdbarch *gdbarch = get_frame_arch (frame); |
dd824b04 DJ |
537 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not |
538 | meaningful. */ | |
72a155b4 | 539 | if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4) |
dd824b04 DJ |
540 | return 0; |
541 | ||
542 | #if 0 | |
543 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
544 | in all the places we deal with FP registers. PR gdb/413. */ | |
545 | /* Otherwise check the FR bit in the status register - it controls | |
546 | the FP compatiblity mode. If it is clear we are in compatibility | |
547 | mode. */ | |
9c9acae0 | 548 | if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0) |
dd824b04 DJ |
549 | return 1; |
550 | #endif | |
361d1df0 | 551 | |
dd824b04 DJ |
552 | return 0; |
553 | } | |
554 | ||
7a292a7a | 555 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 556 | |
74ed0bb4 | 557 | static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR); |
c906108c | 558 | |
025bb325 | 559 | /* The list of available "set mips " and "show mips " commands. */ |
acdb74a0 AC |
560 | |
561 | static struct cmd_list_element *setmipscmdlist = NULL; | |
562 | static struct cmd_list_element *showmipscmdlist = NULL; | |
563 | ||
5e2e9765 KB |
564 | /* Integer registers 0 thru 31 are handled explicitly by |
565 | mips_register_name(). Processor specific registers 32 and above | |
8a9fc081 | 566 | are listed in the following tables. */ |
691c0433 | 567 | |
6d82d43b AC |
568 | enum |
569 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
570 | |
571 | /* Generic MIPS. */ | |
572 | ||
573 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
574 | "sr", "lo", "hi", "bad", "cause", "pc", |
575 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
576 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
577 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
578 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
1faeff08 | 579 | "fsr", "fir", |
691c0433 AC |
580 | }; |
581 | ||
691c0433 AC |
582 | /* Names of tx39 registers. */ |
583 | ||
584 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
585 | "sr", "lo", "hi", "bad", "cause", "pc", |
586 | "", "", "", "", "", "", "", "", | |
587 | "", "", "", "", "", "", "", "", | |
588 | "", "", "", "", "", "", "", "", | |
589 | "", "", "", "", "", "", "", "", | |
590 | "", "", "", "", | |
591 | "", "", "", "", "", "", "", "", | |
1faeff08 | 592 | "", "", "config", "cache", "debug", "depc", "epc", |
691c0433 AC |
593 | }; |
594 | ||
44099a67 | 595 | /* Names of registers with Linux kernels. */ |
1faeff08 MR |
596 | static const char *mips_linux_reg_names[NUM_MIPS_PROCESSOR_REGS] = { |
597 | "sr", "lo", "hi", "bad", "cause", "pc", | |
598 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
599 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
600 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
601 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
602 | "fsr", "fir" | |
603 | }; | |
604 | ||
cce74817 | 605 | |
5e2e9765 | 606 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 607 | static const char * |
d93859e2 | 608 | mips_register_name (struct gdbarch *gdbarch, int regno) |
cce74817 | 609 | { |
d93859e2 | 610 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
5e2e9765 | 611 | /* GPR names for all ABIs other than n32/n64. */ |
a121b7c1 | 612 | static const char *mips_gpr_names[] = { |
6d82d43b AC |
613 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
614 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
615 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
616 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
617 | }; |
618 | ||
619 | /* GPR names for n32 and n64 ABIs. */ | |
a121b7c1 | 620 | static const char *mips_n32_n64_gpr_names[] = { |
6d82d43b AC |
621 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
622 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
623 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
624 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
625 | }; |
626 | ||
d93859e2 | 627 | enum mips_abi abi = mips_abi (gdbarch); |
5e2e9765 | 628 | |
f57d151a | 629 | /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, |
6229fbea HZ |
630 | but then don't make the raw register names visible. This (upper) |
631 | range of user visible register numbers are the pseudo-registers. | |
632 | ||
633 | This approach was adopted accommodate the following scenario: | |
634 | It is possible to debug a 64-bit device using a 32-bit | |
635 | programming model. In such instances, the raw registers are | |
636 | configured to be 64-bits wide, while the pseudo registers are | |
637 | configured to be 32-bits wide. The registers that the user | |
638 | sees - the pseudo registers - match the users expectations | |
639 | given the programming model being used. */ | |
d93859e2 UW |
640 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
641 | if (regno < gdbarch_num_regs (gdbarch)) | |
a4b8ebc8 AC |
642 | return ""; |
643 | ||
5e2e9765 KB |
644 | /* The MIPS integer registers are always mapped from 0 to 31. The |
645 | names of the registers (which reflects the conventions regarding | |
646 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 647 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
648 | { |
649 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 650 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 651 | else |
a4b8ebc8 | 652 | return mips_gpr_names[rawnum]; |
5e2e9765 | 653 | } |
d93859e2 UW |
654 | else if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
655 | return tdesc_register_name (gdbarch, rawnum); | |
656 | else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch)) | |
691c0433 AC |
657 | { |
658 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
1faeff08 MR |
659 | if (tdep->mips_processor_reg_names[rawnum - 32]) |
660 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
661 | return ""; | |
691c0433 | 662 | } |
5e2e9765 KB |
663 | else |
664 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 665 | _("mips_register_name: bad register number %d"), rawnum); |
cce74817 | 666 | } |
5e2e9765 | 667 | |
a4b8ebc8 | 668 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 669 | |
a4b8ebc8 AC |
670 | static int |
671 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
672 | struct reggroup *reggroup) | |
673 | { | |
674 | int vector_p; | |
675 | int float_p; | |
676 | int raw_p; | |
72a155b4 UW |
677 | int rawnum = regnum % gdbarch_num_regs (gdbarch); |
678 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
a4b8ebc8 AC |
679 | if (reggroup == all_reggroup) |
680 | return pseudo; | |
681 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
682 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
683 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
684 | (gdbarch), as not all architectures are multi-arch. */ | |
72a155b4 UW |
685 | raw_p = rawnum < gdbarch_num_regs (gdbarch); |
686 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
687 | || gdbarch_register_name (gdbarch, regnum)[0] == '\0') | |
a4b8ebc8 AC |
688 | return 0; |
689 | if (reggroup == float_reggroup) | |
690 | return float_p && pseudo; | |
691 | if (reggroup == vector_reggroup) | |
692 | return vector_p && pseudo; | |
693 | if (reggroup == general_reggroup) | |
694 | return (!vector_p && !float_p) && pseudo; | |
695 | /* Save the pseudo registers. Need to make certain that any code | |
696 | extracting register values from a saved register cache also uses | |
697 | pseudo registers. */ | |
698 | if (reggroup == save_reggroup) | |
699 | return raw_p && pseudo; | |
700 | /* Restore the same pseudo register. */ | |
701 | if (reggroup == restore_reggroup) | |
702 | return raw_p && pseudo; | |
6d82d43b | 703 | return 0; |
a4b8ebc8 AC |
704 | } |
705 | ||
f8b73d13 DJ |
706 | /* Return the groups that a MIPS register can be categorised into. |
707 | This version is only used if we have a target description which | |
708 | describes real registers (and their groups). */ | |
709 | ||
710 | static int | |
711 | mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
712 | struct reggroup *reggroup) | |
713 | { | |
714 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
715 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
716 | int ret; | |
717 | ||
718 | /* Only save, restore, and display the pseudo registers. Need to | |
719 | make certain that any code extracting register values from a | |
720 | saved register cache also uses pseudo registers. | |
721 | ||
722 | Note: saving and restoring the pseudo registers is slightly | |
723 | strange; if we have 64 bits, we should save and restore all | |
724 | 64 bits. But this is hard and has little benefit. */ | |
725 | if (!pseudo) | |
726 | return 0; | |
727 | ||
728 | ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup); | |
729 | if (ret != -1) | |
730 | return ret; | |
731 | ||
732 | return mips_register_reggroup_p (gdbarch, regnum, reggroup); | |
733 | } | |
734 | ||
a4b8ebc8 | 735 | /* Map the symbol table registers which live in the range [1 * |
f57d151a | 736 | gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw |
47ebcfbe | 737 | registers. Take care of alignment and size problems. */ |
c5aa993b | 738 | |
05d1431c | 739 | static enum register_status |
a4b8ebc8 | 740 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
47a35522 | 741 | int cookednum, gdb_byte *buf) |
a4b8ebc8 | 742 | { |
72a155b4 UW |
743 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
744 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
745 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 746 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
03f50fc8 | 747 | return regcache->raw_read (rawnum, buf); |
6d82d43b AC |
748 | else if (register_size (gdbarch, rawnum) > |
749 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 750 | { |
8bdf35dc | 751 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
03f50fc8 | 752 | return regcache->raw_read_part (rawnum, 0, 4, buf); |
47ebcfbe | 753 | else |
8bdf35dc KB |
754 | { |
755 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
756 | LONGEST regval; | |
05d1431c PA |
757 | enum register_status status; |
758 | ||
03f50fc8 | 759 | status = regcache->raw_read (rawnum, ®val); |
05d1431c PA |
760 | if (status == REG_VALID) |
761 | store_signed_integer (buf, 4, byte_order, regval); | |
762 | return status; | |
8bdf35dc | 763 | } |
47ebcfbe AC |
764 | } |
765 | else | |
e2e0b3e5 | 766 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 AC |
767 | } |
768 | ||
769 | static void | |
6d82d43b AC |
770 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
771 | struct regcache *regcache, int cookednum, | |
47a35522 | 772 | const gdb_byte *buf) |
a4b8ebc8 | 773 | { |
72a155b4 UW |
774 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
775 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
776 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 777 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 778 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
779 | else if (register_size (gdbarch, rawnum) > |
780 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 781 | { |
8bdf35dc | 782 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
47ebcfbe AC |
783 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); |
784 | else | |
8bdf35dc KB |
785 | { |
786 | /* Sign extend the shortened version of the register prior | |
787 | to placing it in the raw register. This is required for | |
788 | some mips64 parts in order to avoid unpredictable behavior. */ | |
789 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
790 | LONGEST regval = extract_signed_integer (buf, 4, byte_order); | |
791 | regcache_raw_write_signed (regcache, rawnum, regval); | |
792 | } | |
47ebcfbe AC |
793 | } |
794 | else | |
e2e0b3e5 | 795 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 | 796 | } |
c5aa993b | 797 | |
175ff332 HZ |
798 | static int |
799 | mips_ax_pseudo_register_collect (struct gdbarch *gdbarch, | |
800 | struct agent_expr *ax, int reg) | |
801 | { | |
802 | int rawnum = reg % gdbarch_num_regs (gdbarch); | |
803 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) | |
804 | && reg < 2 * gdbarch_num_regs (gdbarch)); | |
805 | ||
806 | ax_reg_mask (ax, rawnum); | |
807 | ||
808 | return 0; | |
809 | } | |
810 | ||
811 | static int | |
812 | mips_ax_pseudo_register_push_stack (struct gdbarch *gdbarch, | |
813 | struct agent_expr *ax, int reg) | |
814 | { | |
815 | int rawnum = reg % gdbarch_num_regs (gdbarch); | |
816 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) | |
817 | && reg < 2 * gdbarch_num_regs (gdbarch)); | |
818 | if (register_size (gdbarch, rawnum) >= register_size (gdbarch, reg)) | |
819 | { | |
820 | ax_reg (ax, rawnum); | |
821 | ||
822 | if (register_size (gdbarch, rawnum) > register_size (gdbarch, reg)) | |
823 | { | |
824 | if (!gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
825 | || gdbarch_byte_order (gdbarch) != BFD_ENDIAN_BIG) | |
826 | { | |
827 | ax_const_l (ax, 32); | |
828 | ax_simple (ax, aop_lsh); | |
829 | } | |
830 | ax_const_l (ax, 32); | |
831 | ax_simple (ax, aop_rsh_signed); | |
832 | } | |
833 | } | |
834 | else | |
835 | internal_error (__FILE__, __LINE__, _("bad register size")); | |
836 | ||
837 | return 0; | |
838 | } | |
839 | ||
4cc0665f | 840 | /* Table to translate 3-bit register field to actual register number. */ |
d467df4e | 841 | static const signed char mips_reg3_to_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
842 | |
843 | /* Heuristic_proc_start may hunt through the text section for a long | |
844 | time across a 2400 baud serial line. Allows the user to limit this | |
845 | search. */ | |
846 | ||
44096aee | 847 | static int heuristic_fence_post = 0; |
c906108c | 848 | |
46cd78fb | 849 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
850 | register N. NOTE: This defines the pseudo register type so need to |
851 | rebuild the architecture vector. */ | |
43e526b9 JM |
852 | |
853 | static int mips64_transfers_32bit_regs_p = 0; | |
854 | ||
719ec221 | 855 | static void |
eb4c3f4a | 856 | set_mips64_transfers_32bit_regs (const char *args, int from_tty, |
719ec221 | 857 | struct cmd_list_element *c) |
43e526b9 | 858 | { |
719ec221 AC |
859 | struct gdbarch_info info; |
860 | gdbarch_info_init (&info); | |
861 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
862 | instead of relying on globals. Doing that would let generic code | |
863 | handle the search for this specific architecture. */ | |
864 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 865 | { |
719ec221 | 866 | mips64_transfers_32bit_regs_p = 0; |
8a3fe4f8 | 867 | error (_("32-bit compatibility mode not supported")); |
a4b8ebc8 | 868 | } |
a4b8ebc8 AC |
869 | } |
870 | ||
47ebcfbe | 871 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 872 | |
ee51a8c7 KB |
873 | /* This predicate tests for the case of an 8 byte floating point |
874 | value that is being transferred to or from a pair of floating point | |
875 | registers each of which are (or are considered to be) only 4 bytes | |
876 | wide. */ | |
ff2e87ac | 877 | static int |
ee51a8c7 KB |
878 | mips_convert_register_float_case_p (struct gdbarch *gdbarch, int regnum, |
879 | struct type *type) | |
ff2e87ac | 880 | { |
0abe36f5 MD |
881 | return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
882 | && register_size (gdbarch, regnum) == 4 | |
004159a2 | 883 | && mips_float_register_p (gdbarch, regnum) |
6d82d43b | 884 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
885 | } |
886 | ||
ee51a8c7 KB |
887 | /* This predicate tests for the case of a value of less than 8 |
888 | bytes in width that is being transfered to or from an 8 byte | |
889 | general purpose register. */ | |
890 | static int | |
891 | mips_convert_register_gpreg_case_p (struct gdbarch *gdbarch, int regnum, | |
892 | struct type *type) | |
893 | { | |
894 | int num_regs = gdbarch_num_regs (gdbarch); | |
895 | ||
896 | return (register_size (gdbarch, regnum) == 8 | |
897 | && regnum % num_regs > 0 && regnum % num_regs < 32 | |
898 | && TYPE_LENGTH (type) < 8); | |
899 | } | |
900 | ||
901 | static int | |
025bb325 MS |
902 | mips_convert_register_p (struct gdbarch *gdbarch, |
903 | int regnum, struct type *type) | |
ee51a8c7 | 904 | { |
eaa05d59 MR |
905 | return (mips_convert_register_float_case_p (gdbarch, regnum, type) |
906 | || mips_convert_register_gpreg_case_p (gdbarch, regnum, type)); | |
ee51a8c7 KB |
907 | } |
908 | ||
8dccd430 | 909 | static int |
ff2e87ac | 910 | mips_register_to_value (struct frame_info *frame, int regnum, |
8dccd430 PA |
911 | struct type *type, gdb_byte *to, |
912 | int *optimizedp, int *unavailablep) | |
102182a9 | 913 | { |
ee51a8c7 KB |
914 | struct gdbarch *gdbarch = get_frame_arch (frame); |
915 | ||
916 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
917 | { | |
918 | get_frame_register (frame, regnum + 0, to + 4); | |
919 | get_frame_register (frame, regnum + 1, to + 0); | |
8dccd430 PA |
920 | |
921 | if (!get_frame_register_bytes (frame, regnum + 0, 0, 4, to + 4, | |
922 | optimizedp, unavailablep)) | |
923 | return 0; | |
924 | ||
925 | if (!get_frame_register_bytes (frame, regnum + 1, 0, 4, to + 0, | |
926 | optimizedp, unavailablep)) | |
927 | return 0; | |
928 | *optimizedp = *unavailablep = 0; | |
929 | return 1; | |
ee51a8c7 KB |
930 | } |
931 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
932 | { | |
933 | int len = TYPE_LENGTH (type); | |
8dccd430 PA |
934 | CORE_ADDR offset; |
935 | ||
936 | offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 8 - len : 0; | |
937 | if (!get_frame_register_bytes (frame, regnum, offset, len, to, | |
938 | optimizedp, unavailablep)) | |
939 | return 0; | |
940 | ||
941 | *optimizedp = *unavailablep = 0; | |
942 | return 1; | |
ee51a8c7 KB |
943 | } |
944 | else | |
945 | { | |
946 | internal_error (__FILE__, __LINE__, | |
947 | _("mips_register_to_value: unrecognized case")); | |
948 | } | |
102182a9 MS |
949 | } |
950 | ||
42c466d7 | 951 | static void |
ff2e87ac | 952 | mips_value_to_register (struct frame_info *frame, int regnum, |
47a35522 | 953 | struct type *type, const gdb_byte *from) |
102182a9 | 954 | { |
ee51a8c7 KB |
955 | struct gdbarch *gdbarch = get_frame_arch (frame); |
956 | ||
957 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
958 | { | |
959 | put_frame_register (frame, regnum + 0, from + 4); | |
960 | put_frame_register (frame, regnum + 1, from + 0); | |
961 | } | |
962 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
963 | { | |
964 | gdb_byte fill[8]; | |
965 | int len = TYPE_LENGTH (type); | |
966 | ||
967 | /* Sign extend values, irrespective of type, that are stored to | |
968 | a 64-bit general purpose register. (32-bit unsigned values | |
969 | are stored as signed quantities within a 64-bit register. | |
970 | When performing an operation, in compiled code, that combines | |
971 | a 32-bit unsigned value with a signed 64-bit value, a type | |
972 | conversion is first performed that zeroes out the high 32 bits.) */ | |
973 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
974 | { | |
975 | if (from[0] & 0x80) | |
976 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, -1); | |
977 | else | |
978 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, 0); | |
979 | put_frame_register_bytes (frame, regnum, 0, 8 - len, fill); | |
980 | put_frame_register_bytes (frame, regnum, 8 - len, len, from); | |
981 | } | |
982 | else | |
983 | { | |
984 | if (from[len-1] & 0x80) | |
985 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, -1); | |
986 | else | |
987 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, 0); | |
988 | put_frame_register_bytes (frame, regnum, 0, len, from); | |
989 | put_frame_register_bytes (frame, regnum, len, 8 - len, fill); | |
990 | } | |
991 | } | |
992 | else | |
993 | { | |
994 | internal_error (__FILE__, __LINE__, | |
995 | _("mips_value_to_register: unrecognized case")); | |
996 | } | |
102182a9 MS |
997 | } |
998 | ||
a4b8ebc8 AC |
999 | /* Return the GDB type object for the "standard" data type of data in |
1000 | register REG. */ | |
78fde5f8 KB |
1001 | |
1002 | static struct type * | |
a4b8ebc8 AC |
1003 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
1004 | { | |
72a155b4 | 1005 | gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch)); |
004159a2 | 1006 | if (mips_float_register_p (gdbarch, regnum)) |
a6425924 | 1007 | { |
5ef80fb0 | 1008 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 1009 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
8da61cc4 | 1010 | if (mips_isa_regsize (gdbarch) == 4) |
27067745 | 1011 | return builtin_type (gdbarch)->builtin_float; |
8da61cc4 | 1012 | else |
27067745 | 1013 | return builtin_type (gdbarch)->builtin_double; |
a6425924 | 1014 | } |
72a155b4 | 1015 | else if (regnum < gdbarch_num_regs (gdbarch)) |
d5ac5a39 AC |
1016 | { |
1017 | /* The raw or ISA registers. These are all sized according to | |
1018 | the ISA regsize. */ | |
1019 | if (mips_isa_regsize (gdbarch) == 4) | |
df4df182 | 1020 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 | 1021 | else |
df4df182 | 1022 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 1023 | } |
78fde5f8 | 1024 | else |
d5ac5a39 | 1025 | { |
1faeff08 MR |
1026 | int rawnum = regnum - gdbarch_num_regs (gdbarch); |
1027 | ||
d5ac5a39 AC |
1028 | /* The cooked or ABI registers. These are sized according to |
1029 | the ABI (with a few complications). */ | |
1faeff08 MR |
1030 | if (rawnum == mips_regnum (gdbarch)->fp_control_status |
1031 | || rawnum == mips_regnum (gdbarch)->fp_implementation_revision) | |
1032 | return builtin_type (gdbarch)->builtin_int32; | |
de4bfa86 | 1033 | else if (gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX |
1faeff08 MR |
1034 | && rawnum >= MIPS_FIRST_EMBED_REGNUM |
1035 | && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
d5ac5a39 AC |
1036 | /* The pseudo/cooked view of the embedded registers is always |
1037 | 32-bit. The raw view is handled below. */ | |
df4df182 | 1038 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
1039 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
1040 | /* The target, while possibly using a 64-bit register buffer, | |
1041 | is only transfering 32-bits of each integer register. | |
1042 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
df4df182 | 1043 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
1044 | else if (mips_abi_regsize (gdbarch) == 4) |
1045 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
1046 | 32- or 64-bit). */ | |
df4df182 | 1047 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
1048 | else |
1049 | /* 64-bit ABI. */ | |
df4df182 | 1050 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 1051 | } |
78fde5f8 KB |
1052 | } |
1053 | ||
f8b73d13 DJ |
1054 | /* Return the GDB type for the pseudo register REGNUM, which is the |
1055 | ABI-level view. This function is only called if there is a target | |
1056 | description which includes registers, so we know precisely the | |
1057 | types of hardware registers. */ | |
1058 | ||
1059 | static struct type * | |
1060 | mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
1061 | { | |
1062 | const int num_regs = gdbarch_num_regs (gdbarch); | |
f8b73d13 DJ |
1063 | int rawnum = regnum % num_regs; |
1064 | struct type *rawtype; | |
1065 | ||
1066 | gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); | |
1067 | ||
1068 | /* Absent registers are still absent. */ | |
1069 | rawtype = gdbarch_register_type (gdbarch, rawnum); | |
1070 | if (TYPE_LENGTH (rawtype) == 0) | |
1071 | return rawtype; | |
1072 | ||
a6912260 MR |
1073 | /* Present the floating point registers however the hardware did; |
1074 | do not try to convert between FPU layouts. */ | |
de13fcf2 | 1075 | if (mips_float_register_p (gdbarch, rawnum)) |
f8b73d13 DJ |
1076 | return rawtype; |
1077 | ||
78b86327 MR |
1078 | /* Floating-point control registers are always 32-bit even though for |
1079 | backwards compatibility reasons 64-bit targets will transfer them | |
1080 | as 64-bit quantities even if using XML descriptions. */ | |
1081 | if (rawnum == mips_regnum (gdbarch)->fp_control_status | |
1082 | || rawnum == mips_regnum (gdbarch)->fp_implementation_revision) | |
1083 | return builtin_type (gdbarch)->builtin_int32; | |
1084 | ||
f8b73d13 DJ |
1085 | /* Use pointer types for registers if we can. For n32 we can not, |
1086 | since we do not have a 64-bit pointer type. */ | |
0dfff4cb UW |
1087 | if (mips_abi_regsize (gdbarch) |
1088 | == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr)) | |
f8b73d13 | 1089 | { |
1faeff08 MR |
1090 | if (rawnum == MIPS_SP_REGNUM |
1091 | || rawnum == mips_regnum (gdbarch)->badvaddr) | |
0dfff4cb | 1092 | return builtin_type (gdbarch)->builtin_data_ptr; |
1faeff08 | 1093 | else if (rawnum == mips_regnum (gdbarch)->pc) |
0dfff4cb | 1094 | return builtin_type (gdbarch)->builtin_func_ptr; |
f8b73d13 DJ |
1095 | } |
1096 | ||
1097 | if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8 | |
1faeff08 MR |
1098 | && ((rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_PS_REGNUM) |
1099 | || rawnum == mips_regnum (gdbarch)->lo | |
1100 | || rawnum == mips_regnum (gdbarch)->hi | |
1101 | || rawnum == mips_regnum (gdbarch)->badvaddr | |
1102 | || rawnum == mips_regnum (gdbarch)->cause | |
1103 | || rawnum == mips_regnum (gdbarch)->pc | |
1104 | || (mips_regnum (gdbarch)->dspacc != -1 | |
1105 | && rawnum >= mips_regnum (gdbarch)->dspacc | |
1106 | && rawnum < mips_regnum (gdbarch)->dspacc + 6))) | |
df4df182 | 1107 | return builtin_type (gdbarch)->builtin_int32; |
f8b73d13 | 1108 | |
a6912260 MR |
1109 | /* The pseudo/cooked view of embedded registers is always |
1110 | 32-bit, even if the target transfers 64-bit values for them. | |
1111 | New targets relying on XML descriptions should only transfer | |
1112 | the necessary 32 bits, but older versions of GDB expected 64, | |
1113 | so allow the target to provide 64 bits without interfering | |
1114 | with the displayed type. */ | |
de4bfa86 | 1115 | if (gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX |
78b86327 | 1116 | && rawnum >= MIPS_FIRST_EMBED_REGNUM |
1faeff08 | 1117 | && rawnum <= MIPS_LAST_EMBED_REGNUM) |
a6912260 | 1118 | return builtin_type (gdbarch)->builtin_int32; |
1faeff08 | 1119 | |
f8b73d13 DJ |
1120 | /* For all other registers, pass through the hardware type. */ |
1121 | return rawtype; | |
1122 | } | |
bcb0cc15 | 1123 | |
025bb325 | 1124 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 1125 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
1126 | |
1127 | static int | |
480d3dd2 | 1128 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
1129 | { |
1130 | switch (mask_address_var) | |
1131 | { | |
7f19b9a2 | 1132 | case AUTO_BOOLEAN_TRUE: |
4014092b | 1133 | return 1; |
7f19b9a2 | 1134 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
1135 | return 0; |
1136 | break; | |
7f19b9a2 | 1137 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 1138 | return tdep->default_mask_address_p; |
4014092b | 1139 | default: |
025bb325 MS |
1140 | internal_error (__FILE__, __LINE__, |
1141 | _("mips_mask_address_p: bad switch")); | |
4014092b | 1142 | return -1; |
361d1df0 | 1143 | } |
4014092b AC |
1144 | } |
1145 | ||
1146 | static void | |
08546159 AC |
1147 | show_mask_address (struct ui_file *file, int from_tty, |
1148 | struct cmd_list_element *c, const char *value) | |
4014092b | 1149 | { |
f5656ead | 1150 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ()); |
08546159 AC |
1151 | |
1152 | deprecated_show_value_hack (file, from_tty, c, value); | |
4014092b AC |
1153 | switch (mask_address_var) |
1154 | { | |
7f19b9a2 | 1155 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
1156 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
1157 | break; | |
7f19b9a2 | 1158 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
1159 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
1160 | break; | |
7f19b9a2 | 1161 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
1162 | printf_filtered |
1163 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
1164 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
1165 | break; |
1166 | default: | |
e2e0b3e5 | 1167 | internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); |
4014092b | 1168 | break; |
361d1df0 | 1169 | } |
4014092b | 1170 | } |
c906108c | 1171 | |
4cc0665f MR |
1172 | /* Tell if the program counter value in MEMADDR is in a standard ISA |
1173 | function. */ | |
1174 | ||
1175 | int | |
1176 | mips_pc_is_mips (CORE_ADDR memaddr) | |
1177 | { | |
7cbd4a93 | 1178 | struct bound_minimal_symbol sym; |
4cc0665f MR |
1179 | |
1180 | /* Flags indicating that this is a MIPS16 or microMIPS function is | |
1181 | stored by elfread.c in the high bit of the info field. Use this | |
1182 | to decide if the function is standard MIPS. Otherwise if bit 0 | |
1183 | of the address is clear, then this is a standard MIPS function. */ | |
3e29f34a | 1184 | sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); |
7cbd4a93 TT |
1185 | if (sym.minsym) |
1186 | return msymbol_is_mips (sym.minsym); | |
4cc0665f MR |
1187 | else |
1188 | return is_mips_addr (memaddr); | |
1189 | } | |
1190 | ||
c906108c SS |
1191 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
1192 | ||
0fe7e7c8 | 1193 | int |
4cc0665f | 1194 | mips_pc_is_mips16 (struct gdbarch *gdbarch, CORE_ADDR memaddr) |
c906108c | 1195 | { |
7cbd4a93 | 1196 | struct bound_minimal_symbol sym; |
c906108c | 1197 | |
91912e4d MR |
1198 | /* A flag indicating that this is a MIPS16 function is stored by |
1199 | elfread.c in the high bit of the info field. Use this to decide | |
4cc0665f MR |
1200 | if the function is MIPS16. Otherwise if bit 0 of the address is |
1201 | set, then ELF file flags will tell if this is a MIPS16 function. */ | |
3e29f34a | 1202 | sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); |
7cbd4a93 TT |
1203 | if (sym.minsym) |
1204 | return msymbol_is_mips16 (sym.minsym); | |
4cc0665f MR |
1205 | else |
1206 | return is_mips16_addr (gdbarch, memaddr); | |
1207 | } | |
1208 | ||
1209 | /* Tell if the program counter value in MEMADDR is in a microMIPS function. */ | |
1210 | ||
1211 | int | |
1212 | mips_pc_is_micromips (struct gdbarch *gdbarch, CORE_ADDR memaddr) | |
1213 | { | |
7cbd4a93 | 1214 | struct bound_minimal_symbol sym; |
4cc0665f MR |
1215 | |
1216 | /* A flag indicating that this is a microMIPS function is stored by | |
1217 | elfread.c in the high bit of the info field. Use this to decide | |
1218 | if the function is microMIPS. Otherwise if bit 0 of the address | |
1219 | is set, then ELF file flags will tell if this is a microMIPS | |
1220 | function. */ | |
3e29f34a | 1221 | sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); |
7cbd4a93 TT |
1222 | if (sym.minsym) |
1223 | return msymbol_is_micromips (sym.minsym); | |
4cc0665f MR |
1224 | else |
1225 | return is_micromips_addr (gdbarch, memaddr); | |
1226 | } | |
1227 | ||
1228 | /* Tell the ISA type of the function the program counter value in MEMADDR | |
1229 | is in. */ | |
1230 | ||
1231 | static enum mips_isa | |
1232 | mips_pc_isa (struct gdbarch *gdbarch, CORE_ADDR memaddr) | |
1233 | { | |
7cbd4a93 | 1234 | struct bound_minimal_symbol sym; |
4cc0665f MR |
1235 | |
1236 | /* A flag indicating that this is a MIPS16 or a microMIPS function | |
1237 | is stored by elfread.c in the high bit of the info field. Use | |
1238 | this to decide if the function is MIPS16 or microMIPS or normal | |
1239 | MIPS. Otherwise if bit 0 of the address is set, then ELF file | |
1240 | flags will tell if this is a MIPS16 or a microMIPS function. */ | |
3e29f34a | 1241 | sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); |
7cbd4a93 | 1242 | if (sym.minsym) |
4cc0665f | 1243 | { |
7cbd4a93 | 1244 | if (msymbol_is_micromips (sym.minsym)) |
4cc0665f | 1245 | return ISA_MICROMIPS; |
7cbd4a93 | 1246 | else if (msymbol_is_mips16 (sym.minsym)) |
4cc0665f MR |
1247 | return ISA_MIPS16; |
1248 | else | |
1249 | return ISA_MIPS; | |
1250 | } | |
c906108c | 1251 | else |
4cc0665f MR |
1252 | { |
1253 | if (is_mips_addr (memaddr)) | |
1254 | return ISA_MIPS; | |
1255 | else if (is_micromips_addr (gdbarch, memaddr)) | |
1256 | return ISA_MICROMIPS; | |
1257 | else | |
1258 | return ISA_MIPS16; | |
1259 | } | |
c906108c SS |
1260 | } |
1261 | ||
3e29f34a MR |
1262 | /* Set the ISA bit correctly in the PC, used by DWARF-2 machinery. |
1263 | The need for comes from the ISA bit having been cleared, making | |
1264 | addresses in FDE, range records, etc. referring to compressed code | |
1265 | different to those in line information, the symbol table and finally | |
1266 | the PC register. That in turn confuses many operations. */ | |
1267 | ||
1268 | static CORE_ADDR | |
1269 | mips_adjust_dwarf2_addr (CORE_ADDR pc) | |
1270 | { | |
1271 | pc = unmake_compact_addr (pc); | |
1272 | return mips_pc_is_mips (pc) ? pc : make_compact_addr (pc); | |
1273 | } | |
1274 | ||
1275 | /* Recalculate the line record requested so that the resulting PC has | |
1276 | the ISA bit set correctly, used by DWARF-2 machinery. The need for | |
1277 | this adjustment comes from some records associated with compressed | |
1278 | code having the ISA bit cleared, most notably at function prologue | |
1279 | ends. The ISA bit is in this context retrieved from the minimal | |
1280 | symbol covering the address requested, which in turn has been | |
1281 | constructed from the binary's symbol table rather than DWARF-2 | |
1282 | information. The correct setting of the ISA bit is required for | |
1283 | breakpoint addresses to correctly match against the stop PC. | |
1284 | ||
1285 | As line entries can specify relative address adjustments we need to | |
1286 | keep track of the absolute value of the last line address recorded | |
1287 | in line information, so that we can calculate the actual address to | |
1288 | apply the ISA bit adjustment to. We use PC for this tracking and | |
1289 | keep the original address there. | |
1290 | ||
1291 | As such relative address adjustments can be odd within compressed | |
1292 | code we need to keep track of the last line address with the ISA | |
1293 | bit adjustment applied too, as the original address may or may not | |
1294 | have had the ISA bit set. We use ADJ_PC for this tracking and keep | |
1295 | the adjusted address there. | |
1296 | ||
1297 | For relative address adjustments we then use these variables to | |
1298 | calculate the address intended by line information, which will be | |
1299 | PC-relative, and return an updated adjustment carrying ISA bit | |
1300 | information, which will be ADJ_PC-relative. For absolute address | |
1301 | adjustments we just return the same address that we store in ADJ_PC | |
1302 | too. | |
1303 | ||
1304 | As the first line entry can be relative to an implied address value | |
1305 | of 0 we need to have the initial address set up that we store in PC | |
1306 | and ADJ_PC. This is arranged with a call from `dwarf_decode_lines_1' | |
1307 | that sets PC to 0 and ADJ_PC accordingly, usually 0 as well. */ | |
1308 | ||
1309 | static CORE_ADDR | |
1310 | mips_adjust_dwarf2_line (CORE_ADDR addr, int rel) | |
1311 | { | |
1312 | static CORE_ADDR adj_pc; | |
1313 | static CORE_ADDR pc; | |
1314 | CORE_ADDR isa_pc; | |
1315 | ||
1316 | pc = rel ? pc + addr : addr; | |
1317 | isa_pc = mips_adjust_dwarf2_addr (pc); | |
1318 | addr = rel ? isa_pc - adj_pc : isa_pc; | |
1319 | adj_pc = isa_pc; | |
1320 | return addr; | |
1321 | } | |
1322 | ||
14132e89 MR |
1323 | /* Various MIPS16 thunk (aka stub or trampoline) names. */ |
1324 | ||
1325 | static const char mips_str_mips16_call_stub[] = "__mips16_call_stub_"; | |
1326 | static const char mips_str_mips16_ret_stub[] = "__mips16_ret_"; | |
1327 | static const char mips_str_call_fp_stub[] = "__call_stub_fp_"; | |
1328 | static const char mips_str_call_stub[] = "__call_stub_"; | |
1329 | static const char mips_str_fn_stub[] = "__fn_stub_"; | |
1330 | ||
1331 | /* This is used as a PIC thunk prefix. */ | |
1332 | ||
1333 | static const char mips_str_pic[] = ".pic."; | |
1334 | ||
1335 | /* Return non-zero if the PC is inside a call thunk (aka stub or | |
1336 | trampoline) that should be treated as a temporary frame. */ | |
1337 | ||
1338 | static int | |
1339 | mips_in_frame_stub (CORE_ADDR pc) | |
1340 | { | |
1341 | CORE_ADDR start_addr; | |
1342 | const char *name; | |
1343 | ||
1344 | /* Find the starting address of the function containing the PC. */ | |
1345 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
1346 | return 0; | |
1347 | ||
1348 | /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */ | |
61012eef | 1349 | if (startswith (name, mips_str_mips16_call_stub)) |
14132e89 MR |
1350 | return 1; |
1351 | /* If the PC is in __call_stub_*, this is a call/return or a call stub. */ | |
61012eef | 1352 | if (startswith (name, mips_str_call_stub)) |
14132e89 MR |
1353 | return 1; |
1354 | /* If the PC is in __fn_stub_*, this is a call stub. */ | |
61012eef | 1355 | if (startswith (name, mips_str_fn_stub)) |
14132e89 MR |
1356 | return 1; |
1357 | ||
1358 | return 0; /* Not a stub. */ | |
1359 | } | |
1360 | ||
b2fa5097 | 1361 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
025bb325 | 1362 | all registers should be sign extended for simplicity? */ |
6c997a34 AC |
1363 | |
1364 | static CORE_ADDR | |
61a1198a | 1365 | mips_read_pc (struct regcache *regcache) |
6c997a34 | 1366 | { |
ac7936df | 1367 | int regnum = gdbarch_pc_regnum (regcache->arch ()); |
70242eb1 | 1368 | LONGEST pc; |
8376de04 | 1369 | |
61a1198a UW |
1370 | regcache_cooked_read_signed (regcache, regnum, &pc); |
1371 | return pc; | |
b6cb9035 AC |
1372 | } |
1373 | ||
58dfe9ff AC |
1374 | static CORE_ADDR |
1375 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1376 | { | |
14132e89 | 1377 | CORE_ADDR pc; |
930bd0e0 | 1378 | |
8376de04 | 1379 | pc = frame_unwind_register_signed (next_frame, gdbarch_pc_regnum (gdbarch)); |
14132e89 MR |
1380 | /* macro/2012-04-20: This hack skips over MIPS16 call thunks as |
1381 | intermediate frames. In this case we can get the caller's address | |
1382 | from $ra, or if $ra contains an address within a thunk as well, then | |
1383 | it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10} | |
1384 | and thus the caller's address is in $s2. */ | |
1385 | if (frame_relative_level (next_frame) >= 0 && mips_in_frame_stub (pc)) | |
1386 | { | |
1387 | pc = frame_unwind_register_signed | |
1388 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM); | |
14132e89 | 1389 | if (mips_in_frame_stub (pc)) |
3e29f34a MR |
1390 | pc = frame_unwind_register_signed |
1391 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); | |
14132e89 | 1392 | } |
930bd0e0 | 1393 | return pc; |
edfae063 AC |
1394 | } |
1395 | ||
30244cd8 UW |
1396 | static CORE_ADDR |
1397 | mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1398 | { | |
72a155b4 UW |
1399 | return frame_unwind_register_signed |
1400 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM); | |
30244cd8 UW |
1401 | } |
1402 | ||
b8a22b94 | 1403 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that |
edfae063 AC |
1404 | dummy frame. The frame ID's base needs to match the TOS value |
1405 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
1406 | breakpoint. */ | |
1407 | ||
1408 | static struct frame_id | |
b8a22b94 | 1409 | mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
edfae063 | 1410 | { |
f57d151a | 1411 | return frame_id_build |
b8a22b94 DJ |
1412 | (get_frame_register_signed (this_frame, |
1413 | gdbarch_num_regs (gdbarch) | |
1414 | + MIPS_SP_REGNUM), | |
1415 | get_frame_pc (this_frame)); | |
58dfe9ff AC |
1416 | } |
1417 | ||
5a439849 MR |
1418 | /* Implement the "write_pc" gdbarch method. */ |
1419 | ||
1420 | void | |
61a1198a | 1421 | mips_write_pc (struct regcache *regcache, CORE_ADDR pc) |
b6cb9035 | 1422 | { |
ac7936df | 1423 | int regnum = gdbarch_pc_regnum (regcache->arch ()); |
8376de04 | 1424 | |
3e29f34a | 1425 | regcache_cooked_write_unsigned (regcache, regnum, pc); |
6c997a34 | 1426 | } |
c906108c | 1427 | |
4cc0665f MR |
1428 | /* Fetch and return instruction from the specified location. Handle |
1429 | MIPS16/microMIPS as appropriate. */ | |
c906108c | 1430 | |
d37cca3d | 1431 | static ULONGEST |
4cc0665f | 1432 | mips_fetch_instruction (struct gdbarch *gdbarch, |
d09f2c3f | 1433 | enum mips_isa isa, CORE_ADDR addr, int *errp) |
c906108c | 1434 | { |
e17a4113 | 1435 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 1436 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c | 1437 | int instlen; |
d09f2c3f | 1438 | int err; |
c906108c | 1439 | |
4cc0665f | 1440 | switch (isa) |
c906108c | 1441 | { |
4cc0665f MR |
1442 | case ISA_MICROMIPS: |
1443 | case ISA_MIPS16: | |
95ac2dcf | 1444 | instlen = MIPS_INSN16_SIZE; |
4cc0665f MR |
1445 | addr = unmake_compact_addr (addr); |
1446 | break; | |
1447 | case ISA_MIPS: | |
1448 | instlen = MIPS_INSN32_SIZE; | |
1449 | break; | |
1450 | default: | |
1451 | internal_error (__FILE__, __LINE__, _("invalid ISA")); | |
1452 | break; | |
c906108c | 1453 | } |
d09f2c3f PA |
1454 | err = target_read_memory (addr, buf, instlen); |
1455 | if (errp != NULL) | |
1456 | *errp = err; | |
1457 | if (err != 0) | |
4cc0665f | 1458 | { |
d09f2c3f PA |
1459 | if (errp == NULL) |
1460 | memory_error (TARGET_XFER_E_IO, addr); | |
4cc0665f MR |
1461 | return 0; |
1462 | } | |
e17a4113 | 1463 | return extract_unsigned_integer (buf, instlen, byte_order); |
c906108c SS |
1464 | } |
1465 | ||
025bb325 | 1466 | /* These are the fields of 32 bit mips instructions. */ |
e135b889 DJ |
1467 | #define mips32_op(x) (x >> 26) |
1468 | #define itype_op(x) (x >> 26) | |
1469 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 1470 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 1471 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 1472 | |
e135b889 DJ |
1473 | #define jtype_op(x) (x >> 26) |
1474 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 1475 | |
e135b889 DJ |
1476 | #define rtype_op(x) (x >> 26) |
1477 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
1478 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
1479 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
1480 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
1481 | #define rtype_funct(x) (x & 0x3f) | |
c906108c | 1482 | |
4cc0665f MR |
1483 | /* MicroMIPS instruction fields. */ |
1484 | #define micromips_op(x) ((x) >> 10) | |
1485 | ||
1486 | /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest | |
1487 | bit and the size respectively of the field extracted. */ | |
1488 | #define b0s4_imm(x) ((x) & 0xf) | |
1489 | #define b0s5_imm(x) ((x) & 0x1f) | |
1490 | #define b0s5_reg(x) ((x) & 0x1f) | |
1491 | #define b0s7_imm(x) ((x) & 0x7f) | |
1492 | #define b0s10_imm(x) ((x) & 0x3ff) | |
1493 | #define b1s4_imm(x) (((x) >> 1) & 0xf) | |
1494 | #define b1s9_imm(x) (((x) >> 1) & 0x1ff) | |
1495 | #define b2s3_cc(x) (((x) >> 2) & 0x7) | |
1496 | #define b4s2_regl(x) (((x) >> 4) & 0x3) | |
1497 | #define b5s5_op(x) (((x) >> 5) & 0x1f) | |
1498 | #define b5s5_reg(x) (((x) >> 5) & 0x1f) | |
1499 | #define b6s4_op(x) (((x) >> 6) & 0xf) | |
1500 | #define b7s3_reg(x) (((x) >> 7) & 0x7) | |
1501 | ||
1502 | /* 32-bit instruction formats, B and S refer to the lowest bit and the size | |
1503 | respectively of the field extracted. */ | |
1504 | #define b0s6_op(x) ((x) & 0x3f) | |
1505 | #define b0s11_op(x) ((x) & 0x7ff) | |
1506 | #define b0s12_imm(x) ((x) & 0xfff) | |
1507 | #define b0s16_imm(x) ((x) & 0xffff) | |
1508 | #define b0s26_imm(x) ((x) & 0x3ffffff) | |
1509 | #define b6s10_ext(x) (((x) >> 6) & 0x3ff) | |
1510 | #define b11s5_reg(x) (((x) >> 11) & 0x1f) | |
1511 | #define b12s4_op(x) (((x) >> 12) & 0xf) | |
1512 | ||
1513 | /* Return the size in bytes of the instruction INSN encoded in the ISA | |
1514 | instruction set. */ | |
1515 | ||
1516 | static int | |
1517 | mips_insn_size (enum mips_isa isa, ULONGEST insn) | |
1518 | { | |
1519 | switch (isa) | |
1520 | { | |
1521 | case ISA_MICROMIPS: | |
100b4f2e MR |
1522 | if ((micromips_op (insn) & 0x4) == 0x4 |
1523 | || (micromips_op (insn) & 0x7) == 0x0) | |
4cc0665f MR |
1524 | return 2 * MIPS_INSN16_SIZE; |
1525 | else | |
1526 | return MIPS_INSN16_SIZE; | |
1527 | case ISA_MIPS16: | |
1528 | if ((insn & 0xf800) == 0xf000) | |
1529 | return 2 * MIPS_INSN16_SIZE; | |
1530 | else | |
1531 | return MIPS_INSN16_SIZE; | |
1532 | case ISA_MIPS: | |
1533 | return MIPS_INSN32_SIZE; | |
1534 | } | |
1535 | internal_error (__FILE__, __LINE__, _("invalid ISA")); | |
1536 | } | |
1537 | ||
06987e64 MK |
1538 | static LONGEST |
1539 | mips32_relative_offset (ULONGEST inst) | |
c5aa993b | 1540 | { |
06987e64 | 1541 | return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; |
c906108c SS |
1542 | } |
1543 | ||
a385295e MR |
1544 | /* Determine the address of the next instruction executed after the INST |
1545 | floating condition branch instruction at PC. COUNT specifies the | |
1546 | number of the floating condition bits tested by the branch. */ | |
1547 | ||
1548 | static CORE_ADDR | |
7113a196 | 1549 | mips32_bc1_pc (struct gdbarch *gdbarch, struct regcache *regcache, |
a385295e MR |
1550 | ULONGEST inst, CORE_ADDR pc, int count) |
1551 | { | |
1552 | int fcsr = mips_regnum (gdbarch)->fp_control_status; | |
1553 | int cnum = (itype_rt (inst) >> 2) & (count - 1); | |
1554 | int tf = itype_rt (inst) & 1; | |
1555 | int mask = (1 << count) - 1; | |
1556 | ULONGEST fcs; | |
1557 | int cond; | |
1558 | ||
1559 | if (fcsr == -1) | |
1560 | /* No way to handle; it'll most likely trap anyway. */ | |
1561 | return pc; | |
1562 | ||
7113a196 | 1563 | fcs = regcache_raw_get_unsigned (regcache, fcsr); |
a385295e MR |
1564 | cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); |
1565 | ||
1566 | if (((cond >> cnum) & mask) != mask * !tf) | |
1567 | pc += mips32_relative_offset (inst); | |
1568 | else | |
1569 | pc += 4; | |
1570 | ||
1571 | return pc; | |
1572 | } | |
1573 | ||
f94363d7 AP |
1574 | /* Return nonzero if the gdbarch is an Octeon series. */ |
1575 | ||
1576 | static int | |
1577 | is_octeon (struct gdbarch *gdbarch) | |
1578 | { | |
1579 | const struct bfd_arch_info *info = gdbarch_bfd_arch_info (gdbarch); | |
1580 | ||
1581 | return (info->mach == bfd_mach_mips_octeon | |
1582 | || info->mach == bfd_mach_mips_octeonp | |
1583 | || info->mach == bfd_mach_mips_octeon2); | |
1584 | } | |
1585 | ||
1586 | /* Return true if the OP represents the Octeon's BBIT instruction. */ | |
1587 | ||
1588 | static int | |
1589 | is_octeon_bbit_op (int op, struct gdbarch *gdbarch) | |
1590 | { | |
1591 | if (!is_octeon (gdbarch)) | |
1592 | return 0; | |
1593 | /* BBIT0 is encoded as LWC2: 110 010. */ | |
1594 | /* BBIT032 is encoded as LDC2: 110 110. */ | |
1595 | /* BBIT1 is encoded as SWC2: 111 010. */ | |
1596 | /* BBIT132 is encoded as SDC2: 111 110. */ | |
1597 | if (op == 50 || op == 54 || op == 58 || op == 62) | |
1598 | return 1; | |
1599 | return 0; | |
1600 | } | |
1601 | ||
1602 | ||
f49e4e6d MS |
1603 | /* Determine where to set a single step breakpoint while considering |
1604 | branch prediction. */ | |
78a59c2f | 1605 | |
5a89d8aa | 1606 | static CORE_ADDR |
7113a196 | 1607 | mips32_next_pc (struct regcache *regcache, CORE_ADDR pc) |
c5aa993b | 1608 | { |
ac7936df | 1609 | struct gdbarch *gdbarch = regcache->arch (); |
c5aa993b JM |
1610 | unsigned long inst; |
1611 | int op; | |
4cc0665f | 1612 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
4f5bcb50 | 1613 | op = itype_op (inst); |
025bb325 MS |
1614 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch |
1615 | instruction. */ | |
c5aa993b | 1616 | { |
4f5bcb50 | 1617 | if (op >> 2 == 5) |
6d82d43b | 1618 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 1619 | { |
4f5bcb50 | 1620 | switch (op & 0x03) |
c906108c | 1621 | { |
e135b889 DJ |
1622 | case 0: /* BEQL */ |
1623 | goto equal_branch; | |
1624 | case 1: /* BNEL */ | |
1625 | goto neq_branch; | |
1626 | case 2: /* BLEZL */ | |
1627 | goto less_branch; | |
313628cc | 1628 | case 3: /* BGTZL */ |
e135b889 | 1629 | goto greater_branch; |
c5aa993b JM |
1630 | default: |
1631 | pc += 4; | |
c906108c SS |
1632 | } |
1633 | } | |
4f5bcb50 | 1634 | else if (op == 17 && itype_rs (inst) == 8) |
6d82d43b | 1635 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
7113a196 | 1636 | pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 1); |
4f5bcb50 | 1637 | else if (op == 17 && itype_rs (inst) == 9 |
a385295e MR |
1638 | && (itype_rt (inst) & 2) == 0) |
1639 | /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */ | |
7113a196 | 1640 | pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 2); |
4f5bcb50 | 1641 | else if (op == 17 && itype_rs (inst) == 10 |
a385295e MR |
1642 | && (itype_rt (inst) & 2) == 0) |
1643 | /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */ | |
7113a196 | 1644 | pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 4); |
4f5bcb50 | 1645 | else if (op == 29) |
9e8da49c MR |
1646 | /* JALX: 011101 */ |
1647 | /* The new PC will be alternate mode. */ | |
1648 | { | |
1649 | unsigned long reg; | |
1650 | ||
1651 | reg = jtype_target (inst) << 2; | |
1652 | /* Add 1 to indicate 16-bit mode -- invert ISA mode. */ | |
1653 | pc = ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + reg + 1; | |
1654 | } | |
f94363d7 AP |
1655 | else if (is_octeon_bbit_op (op, gdbarch)) |
1656 | { | |
1657 | int bit, branch_if; | |
1658 | ||
1659 | branch_if = op == 58 || op == 62; | |
1660 | bit = itype_rt (inst); | |
1661 | ||
1662 | /* Take into account the *32 instructions. */ | |
1663 | if (op == 54 || op == 62) | |
1664 | bit += 32; | |
1665 | ||
7113a196 YQ |
1666 | if (((regcache_raw_get_signed (regcache, |
1667 | itype_rs (inst)) >> bit) & 1) | |
f94363d7 AP |
1668 | == branch_if) |
1669 | pc += mips32_relative_offset (inst) + 4; | |
1670 | else | |
1671 | pc += 8; /* After the delay slot. */ | |
1672 | } | |
1673 | ||
c5aa993b | 1674 | else |
025bb325 | 1675 | pc += 4; /* Not a branch, next instruction is easy. */ |
c906108c SS |
1676 | } |
1677 | else | |
025bb325 | 1678 | { /* This gets way messy. */ |
c5aa993b | 1679 | |
025bb325 | 1680 | /* Further subdivide into SPECIAL, REGIMM and other. */ |
4f5bcb50 | 1681 | switch (op & 0x07) /* Extract bits 28,27,26. */ |
c906108c | 1682 | { |
c5aa993b JM |
1683 | case 0: /* SPECIAL */ |
1684 | op = rtype_funct (inst); | |
1685 | switch (op) | |
1686 | { | |
1687 | case 8: /* JR */ | |
1688 | case 9: /* JALR */ | |
025bb325 | 1689 | /* Set PC to that address. */ |
7113a196 | 1690 | pc = regcache_raw_get_signed (regcache, rtype_rs (inst)); |
c5aa993b | 1691 | break; |
e38d4e1a DJ |
1692 | case 12: /* SYSCALL */ |
1693 | { | |
1694 | struct gdbarch_tdep *tdep; | |
1695 | ||
7113a196 | 1696 | tdep = gdbarch_tdep (gdbarch); |
e38d4e1a | 1697 | if (tdep->syscall_next_pc != NULL) |
7113a196 | 1698 | pc = tdep->syscall_next_pc (get_current_frame ()); |
e38d4e1a DJ |
1699 | else |
1700 | pc += 4; | |
1701 | } | |
1702 | break; | |
c5aa993b JM |
1703 | default: |
1704 | pc += 4; | |
1705 | } | |
1706 | ||
6d82d43b | 1707 | break; /* end SPECIAL */ |
025bb325 | 1708 | case 1: /* REGIMM */ |
c906108c | 1709 | { |
e135b889 DJ |
1710 | op = itype_rt (inst); /* branch condition */ |
1711 | switch (op) | |
c906108c | 1712 | { |
c5aa993b | 1713 | case 0: /* BLTZ */ |
e135b889 DJ |
1714 | case 2: /* BLTZL */ |
1715 | case 16: /* BLTZAL */ | |
c5aa993b | 1716 | case 18: /* BLTZALL */ |
c906108c | 1717 | less_branch: |
7113a196 | 1718 | if (regcache_raw_get_signed (regcache, itype_rs (inst)) < 0) |
c5aa993b JM |
1719 | pc += mips32_relative_offset (inst) + 4; |
1720 | else | |
1721 | pc += 8; /* after the delay slot */ | |
1722 | break; | |
e135b889 | 1723 | case 1: /* BGEZ */ |
c5aa993b JM |
1724 | case 3: /* BGEZL */ |
1725 | case 17: /* BGEZAL */ | |
1726 | case 19: /* BGEZALL */ | |
7113a196 | 1727 | if (regcache_raw_get_signed (regcache, itype_rs (inst)) >= 0) |
c5aa993b JM |
1728 | pc += mips32_relative_offset (inst) + 4; |
1729 | else | |
1730 | pc += 8; /* after the delay slot */ | |
1731 | break; | |
a385295e MR |
1732 | case 0x1c: /* BPOSGE32 */ |
1733 | case 0x1e: /* BPOSGE64 */ | |
1734 | pc += 4; | |
1735 | if (itype_rs (inst) == 0) | |
1736 | { | |
1737 | unsigned int pos = (op & 2) ? 64 : 32; | |
1738 | int dspctl = mips_regnum (gdbarch)->dspctl; | |
1739 | ||
1740 | if (dspctl == -1) | |
1741 | /* No way to handle; it'll most likely trap anyway. */ | |
1742 | break; | |
1743 | ||
7113a196 YQ |
1744 | if ((regcache_raw_get_unsigned (regcache, |
1745 | dspctl) & 0x7f) >= pos) | |
a385295e MR |
1746 | pc += mips32_relative_offset (inst); |
1747 | else | |
1748 | pc += 4; | |
1749 | } | |
1750 | break; | |
e135b889 | 1751 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1752 | default: |
1753 | pc += 4; | |
c906108c SS |
1754 | } |
1755 | } | |
6d82d43b | 1756 | break; /* end REGIMM */ |
c5aa993b JM |
1757 | case 2: /* J */ |
1758 | case 3: /* JAL */ | |
1759 | { | |
1760 | unsigned long reg; | |
1761 | reg = jtype_target (inst) << 2; | |
025bb325 | 1762 | /* Upper four bits get never changed... */ |
5b652102 | 1763 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
c906108c | 1764 | } |
c5aa993b | 1765 | break; |
e135b889 | 1766 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1767 | equal_branch: |
7113a196 YQ |
1768 | if (regcache_raw_get_signed (regcache, itype_rs (inst)) == |
1769 | regcache_raw_get_signed (regcache, itype_rt (inst))) | |
c5aa993b JM |
1770 | pc += mips32_relative_offset (inst) + 4; |
1771 | else | |
1772 | pc += 8; | |
1773 | break; | |
e135b889 | 1774 | case 5: /* BNE, BNEL */ |
c5aa993b | 1775 | neq_branch: |
7113a196 YQ |
1776 | if (regcache_raw_get_signed (regcache, itype_rs (inst)) != |
1777 | regcache_raw_get_signed (regcache, itype_rt (inst))) | |
c5aa993b JM |
1778 | pc += mips32_relative_offset (inst) + 4; |
1779 | else | |
1780 | pc += 8; | |
1781 | break; | |
e135b889 | 1782 | case 6: /* BLEZ, BLEZL */ |
7113a196 | 1783 | if (regcache_raw_get_signed (regcache, itype_rs (inst)) <= 0) |
c5aa993b JM |
1784 | pc += mips32_relative_offset (inst) + 4; |
1785 | else | |
1786 | pc += 8; | |
1787 | break; | |
1788 | case 7: | |
e135b889 DJ |
1789 | default: |
1790 | greater_branch: /* BGTZ, BGTZL */ | |
7113a196 | 1791 | if (regcache_raw_get_signed (regcache, itype_rs (inst)) > 0) |
c5aa993b JM |
1792 | pc += mips32_relative_offset (inst) + 4; |
1793 | else | |
1794 | pc += 8; | |
1795 | break; | |
c5aa993b JM |
1796 | } /* switch */ |
1797 | } /* else */ | |
1798 | return pc; | |
1799 | } /* mips32_next_pc */ | |
c906108c | 1800 | |
4cc0665f MR |
1801 | /* Extract the 7-bit signed immediate offset from the microMIPS instruction |
1802 | INSN. */ | |
1803 | ||
1804 | static LONGEST | |
1805 | micromips_relative_offset7 (ULONGEST insn) | |
1806 | { | |
1807 | return ((b0s7_imm (insn) ^ 0x40) - 0x40) << 1; | |
1808 | } | |
1809 | ||
1810 | /* Extract the 10-bit signed immediate offset from the microMIPS instruction | |
1811 | INSN. */ | |
1812 | ||
1813 | static LONGEST | |
1814 | micromips_relative_offset10 (ULONGEST insn) | |
1815 | { | |
1816 | return ((b0s10_imm (insn) ^ 0x200) - 0x200) << 1; | |
1817 | } | |
1818 | ||
1819 | /* Extract the 16-bit signed immediate offset from the microMIPS instruction | |
1820 | INSN. */ | |
1821 | ||
1822 | static LONGEST | |
1823 | micromips_relative_offset16 (ULONGEST insn) | |
1824 | { | |
1825 | return ((b0s16_imm (insn) ^ 0x8000) - 0x8000) << 1; | |
1826 | } | |
1827 | ||
1828 | /* Return the size in bytes of the microMIPS instruction at the address PC. */ | |
1829 | ||
1830 | static int | |
1831 | micromips_pc_insn_size (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1832 | { | |
1833 | ULONGEST insn; | |
1834 | ||
1835 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
1836 | return mips_insn_size (ISA_MICROMIPS, insn); | |
1837 | } | |
1838 | ||
1839 | /* Calculate the address of the next microMIPS instruction to execute | |
1840 | after the INSN coprocessor 1 conditional branch instruction at the | |
1841 | address PC. COUNT denotes the number of coprocessor condition bits | |
1842 | examined by the branch. */ | |
1843 | ||
1844 | static CORE_ADDR | |
7113a196 | 1845 | micromips_bc1_pc (struct gdbarch *gdbarch, struct regcache *regcache, |
4cc0665f MR |
1846 | ULONGEST insn, CORE_ADDR pc, int count) |
1847 | { | |
1848 | int fcsr = mips_regnum (gdbarch)->fp_control_status; | |
1849 | int cnum = b2s3_cc (insn >> 16) & (count - 1); | |
1850 | int tf = b5s5_op (insn >> 16) & 1; | |
1851 | int mask = (1 << count) - 1; | |
1852 | ULONGEST fcs; | |
1853 | int cond; | |
1854 | ||
1855 | if (fcsr == -1) | |
1856 | /* No way to handle; it'll most likely trap anyway. */ | |
1857 | return pc; | |
1858 | ||
7113a196 | 1859 | fcs = regcache_raw_get_unsigned (regcache, fcsr); |
4cc0665f MR |
1860 | cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); |
1861 | ||
1862 | if (((cond >> cnum) & mask) != mask * !tf) | |
1863 | pc += micromips_relative_offset16 (insn); | |
1864 | else | |
1865 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1866 | ||
1867 | return pc; | |
1868 | } | |
1869 | ||
1870 | /* Calculate the address of the next microMIPS instruction to execute | |
1871 | after the instruction at the address PC. */ | |
1872 | ||
1873 | static CORE_ADDR | |
7113a196 | 1874 | micromips_next_pc (struct regcache *regcache, CORE_ADDR pc) |
4cc0665f | 1875 | { |
ac7936df | 1876 | struct gdbarch *gdbarch = regcache->arch (); |
4cc0665f MR |
1877 | ULONGEST insn; |
1878 | ||
1879 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
1880 | pc += MIPS_INSN16_SIZE; | |
1881 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
1882 | { | |
4cc0665f MR |
1883 | /* 32-bit instructions. */ |
1884 | case 2 * MIPS_INSN16_SIZE: | |
1885 | insn <<= 16; | |
1886 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
1887 | pc += MIPS_INSN16_SIZE; | |
1888 | switch (micromips_op (insn >> 16)) | |
1889 | { | |
1890 | case 0x00: /* POOL32A: bits 000000 */ | |
1891 | if (b0s6_op (insn) == 0x3c | |
1892 | /* POOL32Axf: bits 000000 ... 111100 */ | |
1893 | && (b6s10_ext (insn) & 0x2bf) == 0x3c) | |
1894 | /* JALR, JALR.HB: 000000 000x111100 111100 */ | |
1895 | /* JALRS, JALRS.HB: 000000 010x111100 111100 */ | |
7113a196 | 1896 | pc = regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16)); |
4cc0665f MR |
1897 | break; |
1898 | ||
1899 | case 0x10: /* POOL32I: bits 010000 */ | |
1900 | switch (b5s5_op (insn >> 16)) | |
1901 | { | |
1902 | case 0x00: /* BLTZ: bits 010000 00000 */ | |
1903 | case 0x01: /* BLTZAL: bits 010000 00001 */ | |
1904 | case 0x11: /* BLTZALS: bits 010000 10001 */ | |
7113a196 YQ |
1905 | if (regcache_raw_get_signed (regcache, |
1906 | b0s5_reg (insn >> 16)) < 0) | |
4cc0665f MR |
1907 | pc += micromips_relative_offset16 (insn); |
1908 | else | |
1909 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1910 | break; | |
1911 | ||
1912 | case 0x02: /* BGEZ: bits 010000 00010 */ | |
1913 | case 0x03: /* BGEZAL: bits 010000 00011 */ | |
1914 | case 0x13: /* BGEZALS: bits 010000 10011 */ | |
7113a196 YQ |
1915 | if (regcache_raw_get_signed (regcache, |
1916 | b0s5_reg (insn >> 16)) >= 0) | |
4cc0665f MR |
1917 | pc += micromips_relative_offset16 (insn); |
1918 | else | |
1919 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1920 | break; | |
1921 | ||
1922 | case 0x04: /* BLEZ: bits 010000 00100 */ | |
7113a196 YQ |
1923 | if (regcache_raw_get_signed (regcache, |
1924 | b0s5_reg (insn >> 16)) <= 0) | |
4cc0665f MR |
1925 | pc += micromips_relative_offset16 (insn); |
1926 | else | |
1927 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1928 | break; | |
1929 | ||
1930 | case 0x05: /* BNEZC: bits 010000 00101 */ | |
7113a196 YQ |
1931 | if (regcache_raw_get_signed (regcache, |
1932 | b0s5_reg (insn >> 16)) != 0) | |
4cc0665f MR |
1933 | pc += micromips_relative_offset16 (insn); |
1934 | break; | |
1935 | ||
1936 | case 0x06: /* BGTZ: bits 010000 00110 */ | |
7113a196 YQ |
1937 | if (regcache_raw_get_signed (regcache, |
1938 | b0s5_reg (insn >> 16)) > 0) | |
4cc0665f MR |
1939 | pc += micromips_relative_offset16 (insn); |
1940 | else | |
1941 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1942 | break; | |
1943 | ||
1944 | case 0x07: /* BEQZC: bits 010000 00111 */ | |
7113a196 YQ |
1945 | if (regcache_raw_get_signed (regcache, |
1946 | b0s5_reg (insn >> 16)) == 0) | |
4cc0665f MR |
1947 | pc += micromips_relative_offset16 (insn); |
1948 | break; | |
1949 | ||
1950 | case 0x14: /* BC2F: bits 010000 10100 xxx00 */ | |
1951 | case 0x15: /* BC2T: bits 010000 10101 xxx00 */ | |
1952 | if (((insn >> 16) & 0x3) == 0x0) | |
1953 | /* BC2F, BC2T: don't know how to handle these. */ | |
1954 | break; | |
1955 | break; | |
1956 | ||
1957 | case 0x1a: /* BPOSGE64: bits 010000 11010 */ | |
1958 | case 0x1b: /* BPOSGE32: bits 010000 11011 */ | |
1959 | { | |
1960 | unsigned int pos = (b5s5_op (insn >> 16) & 1) ? 32 : 64; | |
1961 | int dspctl = mips_regnum (gdbarch)->dspctl; | |
1962 | ||
1963 | if (dspctl == -1) | |
1964 | /* No way to handle; it'll most likely trap anyway. */ | |
1965 | break; | |
1966 | ||
7113a196 YQ |
1967 | if ((regcache_raw_get_unsigned (regcache, |
1968 | dspctl) & 0x7f) >= pos) | |
4cc0665f MR |
1969 | pc += micromips_relative_offset16 (insn); |
1970 | else | |
1971 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1972 | } | |
1973 | break; | |
1974 | ||
1975 | case 0x1c: /* BC1F: bits 010000 11100 xxx00 */ | |
1976 | /* BC1ANY2F: bits 010000 11100 xxx01 */ | |
1977 | case 0x1d: /* BC1T: bits 010000 11101 xxx00 */ | |
1978 | /* BC1ANY2T: bits 010000 11101 xxx01 */ | |
1979 | if (((insn >> 16) & 0x2) == 0x0) | |
7113a196 | 1980 | pc = micromips_bc1_pc (gdbarch, regcache, insn, pc, |
4cc0665f MR |
1981 | ((insn >> 16) & 0x1) + 1); |
1982 | break; | |
1983 | ||
1984 | case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */ | |
1985 | case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */ | |
1986 | if (((insn >> 16) & 0x3) == 0x1) | |
7113a196 | 1987 | pc = micromips_bc1_pc (gdbarch, regcache, insn, pc, 4); |
4cc0665f MR |
1988 | break; |
1989 | } | |
1990 | break; | |
1991 | ||
1992 | case 0x1d: /* JALS: bits 011101 */ | |
1993 | case 0x35: /* J: bits 110101 */ | |
1994 | case 0x3d: /* JAL: bits 111101 */ | |
1995 | pc = ((pc | 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn) << 1); | |
1996 | break; | |
1997 | ||
1998 | case 0x25: /* BEQ: bits 100101 */ | |
7113a196 YQ |
1999 | if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16)) |
2000 | == regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16))) | |
4cc0665f MR |
2001 | pc += micromips_relative_offset16 (insn); |
2002 | else | |
2003 | pc += micromips_pc_insn_size (gdbarch, pc); | |
2004 | break; | |
2005 | ||
2006 | case 0x2d: /* BNE: bits 101101 */ | |
7113a196 YQ |
2007 | if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16)) |
2008 | != regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16))) | |
4cc0665f MR |
2009 | pc += micromips_relative_offset16 (insn); |
2010 | else | |
2011 | pc += micromips_pc_insn_size (gdbarch, pc); | |
2012 | break; | |
2013 | ||
2014 | case 0x3c: /* JALX: bits 111100 */ | |
2015 | pc = ((pc | 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn) << 2); | |
2016 | break; | |
2017 | } | |
2018 | break; | |
2019 | ||
2020 | /* 16-bit instructions. */ | |
2021 | case MIPS_INSN16_SIZE: | |
2022 | switch (micromips_op (insn)) | |
2023 | { | |
2024 | case 0x11: /* POOL16C: bits 010001 */ | |
2025 | if ((b5s5_op (insn) & 0x1c) == 0xc) | |
2026 | /* JR16, JRC, JALR16, JALRS16: 010001 011xx */ | |
7113a196 | 2027 | pc = regcache_raw_get_signed (regcache, b0s5_reg (insn)); |
4cc0665f MR |
2028 | else if (b5s5_op (insn) == 0x18) |
2029 | /* JRADDIUSP: bits 010001 11000 */ | |
7113a196 | 2030 | pc = regcache_raw_get_signed (regcache, MIPS_RA_REGNUM); |
4cc0665f MR |
2031 | break; |
2032 | ||
2033 | case 0x23: /* BEQZ16: bits 100011 */ | |
2034 | { | |
2035 | int rs = mips_reg3_to_reg[b7s3_reg (insn)]; | |
2036 | ||
7113a196 | 2037 | if (regcache_raw_get_signed (regcache, rs) == 0) |
4cc0665f MR |
2038 | pc += micromips_relative_offset7 (insn); |
2039 | else | |
2040 | pc += micromips_pc_insn_size (gdbarch, pc); | |
2041 | } | |
2042 | break; | |
2043 | ||
2044 | case 0x2b: /* BNEZ16: bits 101011 */ | |
2045 | { | |
2046 | int rs = mips_reg3_to_reg[b7s3_reg (insn)]; | |
2047 | ||
7113a196 | 2048 | if (regcache_raw_get_signed (regcache, rs) != 0) |
4cc0665f MR |
2049 | pc += micromips_relative_offset7 (insn); |
2050 | else | |
2051 | pc += micromips_pc_insn_size (gdbarch, pc); | |
2052 | } | |
2053 | break; | |
2054 | ||
2055 | case 0x33: /* B16: bits 110011 */ | |
2056 | pc += micromips_relative_offset10 (insn); | |
2057 | break; | |
2058 | } | |
2059 | break; | |
2060 | } | |
2061 | ||
2062 | return pc; | |
2063 | } | |
2064 | ||
c906108c | 2065 | /* Decoding the next place to set a breakpoint is irregular for the |
025bb325 MS |
2066 | mips 16 variant, but fortunately, there fewer instructions. We have |
2067 | to cope ith extensions for 16 bit instructions and a pair of actual | |
2068 | 32 bit instructions. We dont want to set a single step instruction | |
2069 | on the extend instruction either. */ | |
c906108c SS |
2070 | |
2071 | /* Lots of mips16 instruction formats */ | |
2072 | /* Predicting jumps requires itype,ritype,i8type | |
025bb325 | 2073 | and their extensions extItype,extritype,extI8type. */ |
c906108c SS |
2074 | enum mips16_inst_fmts |
2075 | { | |
c5aa993b JM |
2076 | itype, /* 0 immediate 5,10 */ |
2077 | ritype, /* 1 5,3,8 */ | |
2078 | rrtype, /* 2 5,3,3,5 */ | |
2079 | rritype, /* 3 5,3,3,5 */ | |
2080 | rrrtype, /* 4 5,3,3,3,2 */ | |
2081 | rriatype, /* 5 5,3,3,1,4 */ | |
2082 | shifttype, /* 6 5,3,3,3,2 */ | |
2083 | i8type, /* 7 5,3,8 */ | |
2084 | i8movtype, /* 8 5,3,3,5 */ | |
2085 | i8mov32rtype, /* 9 5,3,5,3 */ | |
2086 | i64type, /* 10 5,3,8 */ | |
2087 | ri64type, /* 11 5,3,3,5 */ | |
2088 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
2089 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
2090 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
2091 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
2092 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
2093 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
2094 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
2095 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
2096 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
2097 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
2098 | }; | |
12f02c2a | 2099 | /* I am heaping all the fields of the formats into one structure and |
025bb325 | 2100 | then, only the fields which are involved in instruction extension. */ |
c906108c | 2101 | struct upk_mips16 |
6d82d43b AC |
2102 | { |
2103 | CORE_ADDR offset; | |
025bb325 | 2104 | unsigned int regx; /* Function in i8 type. */ |
6d82d43b AC |
2105 | unsigned int regy; |
2106 | }; | |
c906108c SS |
2107 | |
2108 | ||
12f02c2a | 2109 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
c68cf8ad | 2110 | for the bits which make up the immediate extension. */ |
c906108c | 2111 | |
12f02c2a AC |
2112 | static CORE_ADDR |
2113 | extended_offset (unsigned int extension) | |
c906108c | 2114 | { |
12f02c2a | 2115 | CORE_ADDR value; |
130854df | 2116 | |
4c2051c6 | 2117 | value = (extension >> 16) & 0x1f; /* Extract 15:11. */ |
c5aa993b | 2118 | value = value << 6; |
4c2051c6 | 2119 | value |= (extension >> 21) & 0x3f; /* Extract 10:5. */ |
c5aa993b | 2120 | value = value << 5; |
130854df MR |
2121 | value |= extension & 0x1f; /* Extract 4:0. */ |
2122 | ||
c5aa993b | 2123 | return value; |
c906108c SS |
2124 | } |
2125 | ||
2126 | /* Only call this function if you know that this is an extendable | |
bcf1ea1e MR |
2127 | instruction. It won't malfunction, but why make excess remote memory |
2128 | references? If the immediate operands get sign extended or something, | |
2129 | do it after the extension is performed. */ | |
c906108c | 2130 | /* FIXME: Every one of these cases needs to worry about sign extension |
bcf1ea1e | 2131 | when the offset is to be used in relative addressing. */ |
c906108c | 2132 | |
12f02c2a | 2133 | static unsigned int |
e17a4113 | 2134 | fetch_mips_16 (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 2135 | { |
e17a4113 | 2136 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 2137 | gdb_byte buf[8]; |
a2fb2cee MR |
2138 | |
2139 | pc = unmake_compact_addr (pc); /* Clear the low order bit. */ | |
c5aa993b | 2140 | target_read_memory (pc, buf, 2); |
e17a4113 | 2141 | return extract_unsigned_integer (buf, 2, byte_order); |
c906108c SS |
2142 | } |
2143 | ||
2144 | static void | |
e17a4113 | 2145 | unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc, |
12f02c2a AC |
2146 | unsigned int extension, |
2147 | unsigned int inst, | |
6d82d43b | 2148 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 2149 | { |
12f02c2a AC |
2150 | CORE_ADDR offset; |
2151 | int regx; | |
2152 | int regy; | |
2153 | switch (insn_format) | |
c906108c | 2154 | { |
c5aa993b | 2155 | case itype: |
c906108c | 2156 | { |
12f02c2a AC |
2157 | CORE_ADDR value; |
2158 | if (extension) | |
c5aa993b | 2159 | { |
4c2051c6 MR |
2160 | value = extended_offset ((extension << 16) | inst); |
2161 | value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ | |
c906108c SS |
2162 | } |
2163 | else | |
c5aa993b | 2164 | { |
12f02c2a | 2165 | value = inst & 0x7ff; |
4c2051c6 | 2166 | value = (value ^ 0x400) - 0x400; /* Sign-extend. */ |
c906108c | 2167 | } |
12f02c2a AC |
2168 | offset = value; |
2169 | regx = -1; | |
2170 | regy = -1; | |
c906108c | 2171 | } |
c5aa993b JM |
2172 | break; |
2173 | case ritype: | |
2174 | case i8type: | |
025bb325 | 2175 | { /* A register identifier and an offset. */ |
c906108c | 2176 | /* Most of the fields are the same as I type but the |
025bb325 | 2177 | immediate value is of a different length. */ |
12f02c2a AC |
2178 | CORE_ADDR value; |
2179 | if (extension) | |
c906108c | 2180 | { |
4c2051c6 MR |
2181 | value = extended_offset ((extension << 16) | inst); |
2182 | value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ | |
c906108c | 2183 | } |
c5aa993b JM |
2184 | else |
2185 | { | |
4c2051c6 MR |
2186 | value = inst & 0xff; /* 8 bits */ |
2187 | value = (value ^ 0x80) - 0x80; /* Sign-extend. */ | |
c5aa993b | 2188 | } |
12f02c2a | 2189 | offset = value; |
4c2051c6 | 2190 | regx = (inst >> 8) & 0x07; /* i8 funct */ |
12f02c2a | 2191 | regy = -1; |
c5aa993b | 2192 | break; |
c906108c | 2193 | } |
c5aa993b | 2194 | case jalxtype: |
c906108c | 2195 | { |
c5aa993b | 2196 | unsigned long value; |
12f02c2a AC |
2197 | unsigned int nexthalf; |
2198 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b | 2199 | value = value << 16; |
4cc0665f MR |
2200 | nexthalf = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc + 2, NULL); |
2201 | /* Low bit still set. */ | |
c5aa993b | 2202 | value |= nexthalf; |
12f02c2a AC |
2203 | offset = value; |
2204 | regx = -1; | |
2205 | regy = -1; | |
c5aa993b | 2206 | break; |
c906108c SS |
2207 | } |
2208 | default: | |
e2e0b3e5 | 2209 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c | 2210 | } |
12f02c2a AC |
2211 | upk->offset = offset; |
2212 | upk->regx = regx; | |
2213 | upk->regy = regy; | |
c906108c SS |
2214 | } |
2215 | ||
2216 | ||
484933d1 MR |
2217 | /* Calculate the destination of a branch whose 16-bit opcode word is at PC, |
2218 | and having a signed 16-bit OFFSET. */ | |
2219 | ||
c5aa993b JM |
2220 | static CORE_ADDR |
2221 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 2222 | { |
484933d1 | 2223 | return pc + (offset << 1) + 2; |
c906108c SS |
2224 | } |
2225 | ||
12f02c2a | 2226 | static CORE_ADDR |
7113a196 | 2227 | extended_mips16_next_pc (regcache *regcache, CORE_ADDR pc, |
6d82d43b | 2228 | unsigned int extension, unsigned int insn) |
c906108c | 2229 | { |
ac7936df | 2230 | struct gdbarch *gdbarch = regcache->arch (); |
12f02c2a AC |
2231 | int op = (insn >> 11); |
2232 | switch (op) | |
c906108c | 2233 | { |
6d82d43b | 2234 | case 2: /* Branch */ |
12f02c2a | 2235 | { |
12f02c2a | 2236 | struct upk_mips16 upk; |
e17a4113 | 2237 | unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk); |
484933d1 | 2238 | pc = add_offset_16 (pc, upk.offset); |
12f02c2a AC |
2239 | break; |
2240 | } | |
025bb325 MS |
2241 | case 3: /* JAL , JALX - Watch out, these are 32 bit |
2242 | instructions. */ | |
12f02c2a AC |
2243 | { |
2244 | struct upk_mips16 upk; | |
e17a4113 | 2245 | unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk); |
484933d1 | 2246 | pc = ((pc + 2) & (~(CORE_ADDR) 0x0fffffff)) | (upk.offset << 2); |
12f02c2a | 2247 | if ((insn >> 10) & 0x01) /* Exchange mode */ |
025bb325 | 2248 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode. */ |
12f02c2a AC |
2249 | else |
2250 | pc |= 0x01; | |
2251 | break; | |
2252 | } | |
6d82d43b | 2253 | case 4: /* beqz */ |
12f02c2a AC |
2254 | { |
2255 | struct upk_mips16 upk; | |
2256 | int reg; | |
e17a4113 | 2257 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
7113a196 | 2258 | reg = regcache_raw_get_signed (regcache, mips_reg3_to_reg[upk.regx]); |
12f02c2a | 2259 | if (reg == 0) |
484933d1 | 2260 | pc = add_offset_16 (pc, upk.offset); |
12f02c2a AC |
2261 | else |
2262 | pc += 2; | |
2263 | break; | |
2264 | } | |
6d82d43b | 2265 | case 5: /* bnez */ |
12f02c2a AC |
2266 | { |
2267 | struct upk_mips16 upk; | |
2268 | int reg; | |
e17a4113 | 2269 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
7113a196 | 2270 | reg = regcache_raw_get_signed (regcache, mips_reg3_to_reg[upk.regx]); |
12f02c2a | 2271 | if (reg != 0) |
484933d1 | 2272 | pc = add_offset_16 (pc, upk.offset); |
12f02c2a AC |
2273 | else |
2274 | pc += 2; | |
2275 | break; | |
2276 | } | |
6d82d43b | 2277 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
2278 | { |
2279 | struct upk_mips16 upk; | |
2280 | int reg; | |
e17a4113 | 2281 | unpack_mips16 (gdbarch, pc, extension, insn, i8type, &upk); |
12f02c2a | 2282 | /* upk.regx contains the opcode */ |
7113a196 YQ |
2283 | /* Test register is 24 */ |
2284 | reg = regcache_raw_get_signed (regcache, 24); | |
12f02c2a AC |
2285 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ |
2286 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
484933d1 | 2287 | pc = add_offset_16 (pc, upk.offset); |
12f02c2a AC |
2288 | else |
2289 | pc += 2; | |
2290 | break; | |
2291 | } | |
6d82d43b | 2292 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
2293 | { |
2294 | struct upk_mips16 upk; | |
2295 | /* upk.fmt = rrtype; */ | |
2296 | op = insn & 0x1f; | |
2297 | if (op == 0) | |
c5aa993b | 2298 | { |
12f02c2a AC |
2299 | int reg; |
2300 | upk.regx = (insn >> 8) & 0x07; | |
2301 | upk.regy = (insn >> 5) & 0x07; | |
4c2051c6 | 2302 | if ((upk.regy & 1) == 0) |
4cc0665f | 2303 | reg = mips_reg3_to_reg[upk.regx]; |
4c2051c6 MR |
2304 | else |
2305 | reg = 31; /* Function return instruction. */ | |
7113a196 | 2306 | pc = regcache_raw_get_signed (regcache, reg); |
c906108c | 2307 | } |
12f02c2a | 2308 | else |
c5aa993b | 2309 | pc += 2; |
12f02c2a AC |
2310 | break; |
2311 | } | |
2312 | case 30: | |
2313 | /* This is an instruction extension. Fetch the real instruction | |
2314 | (which follows the extension) and decode things based on | |
025bb325 | 2315 | that. */ |
12f02c2a AC |
2316 | { |
2317 | pc += 2; | |
7113a196 | 2318 | pc = extended_mips16_next_pc (regcache, pc, insn, |
e17a4113 | 2319 | fetch_mips_16 (gdbarch, pc)); |
12f02c2a AC |
2320 | break; |
2321 | } | |
2322 | default: | |
2323 | { | |
2324 | pc += 2; | |
2325 | break; | |
2326 | } | |
c906108c | 2327 | } |
c5aa993b | 2328 | return pc; |
12f02c2a | 2329 | } |
c906108c | 2330 | |
5a89d8aa | 2331 | static CORE_ADDR |
7113a196 | 2332 | mips16_next_pc (struct regcache *regcache, CORE_ADDR pc) |
12f02c2a | 2333 | { |
ac7936df | 2334 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 2335 | unsigned int insn = fetch_mips_16 (gdbarch, pc); |
7113a196 | 2336 | return extended_mips16_next_pc (regcache, pc, 0, insn); |
12f02c2a AC |
2337 | } |
2338 | ||
2339 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 2340 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a | 2341 | It works by decoding the current instruction and predicting where a |
1aee363c | 2342 | branch will go. This isn't hard because all the data is available. |
4cc0665f | 2343 | The MIPS32, MIPS16 and microMIPS variants are quite different. */ |
ad527d2e | 2344 | static CORE_ADDR |
7113a196 | 2345 | mips_next_pc (struct regcache *regcache, CORE_ADDR pc) |
c906108c | 2346 | { |
ac7936df | 2347 | struct gdbarch *gdbarch = regcache->arch (); |
4cc0665f MR |
2348 | |
2349 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
7113a196 | 2350 | return mips16_next_pc (regcache, pc); |
4cc0665f | 2351 | else if (mips_pc_is_micromips (gdbarch, pc)) |
7113a196 | 2352 | return micromips_next_pc (regcache, pc); |
c5aa993b | 2353 | else |
7113a196 | 2354 | return mips32_next_pc (regcache, pc); |
12f02c2a | 2355 | } |
c906108c | 2356 | |
ab50adb6 MR |
2357 | /* Return non-zero if the MIPS16 instruction INSN is a compact branch |
2358 | or jump. */ | |
2359 | ||
2360 | static int | |
2361 | mips16_instruction_is_compact_branch (unsigned short insn) | |
2362 | { | |
2363 | switch (insn & 0xf800) | |
2364 | { | |
2365 | case 0xe800: | |
2366 | return (insn & 0x009f) == 0x80; /* JALRC/JRC */ | |
2367 | case 0x6000: | |
2368 | return (insn & 0x0600) == 0; /* BTNEZ/BTEQZ */ | |
2369 | case 0x2800: /* BNEZ */ | |
2370 | case 0x2000: /* BEQZ */ | |
2371 | case 0x1000: /* B */ | |
2372 | return 1; | |
2373 | default: | |
2374 | return 0; | |
2375 | } | |
2376 | } | |
2377 | ||
2378 | /* Return non-zero if the microMIPS instruction INSN is a compact branch | |
2379 | or jump. */ | |
2380 | ||
2381 | static int | |
2382 | micromips_instruction_is_compact_branch (unsigned short insn) | |
2383 | { | |
2384 | switch (micromips_op (insn)) | |
2385 | { | |
2386 | case 0x11: /* POOL16C: bits 010001 */ | |
2387 | return (b5s5_op (insn) == 0x18 | |
2388 | /* JRADDIUSP: bits 010001 11000 */ | |
2389 | || b5s5_op (insn) == 0xd); | |
2390 | /* JRC: bits 010011 01101 */ | |
2391 | case 0x10: /* POOL32I: bits 010000 */ | |
2392 | return (b5s5_op (insn) & 0x1d) == 0x5; | |
2393 | /* BEQZC/BNEZC: bits 010000 001x1 */ | |
2394 | default: | |
2395 | return 0; | |
2396 | } | |
2397 | } | |
2398 | ||
edfae063 AC |
2399 | struct mips_frame_cache |
2400 | { | |
2401 | CORE_ADDR base; | |
2402 | struct trad_frame_saved_reg *saved_regs; | |
2403 | }; | |
2404 | ||
29639122 JB |
2405 | /* Set a register's saved stack address in temp_saved_regs. If an |
2406 | address has already been set for this register, do nothing; this | |
2407 | way we will only recognize the first save of a given register in a | |
2408 | function prologue. | |
eec63939 | 2409 | |
f57d151a UW |
2410 | For simplicity, save the address in both [0 .. gdbarch_num_regs) and |
2411 | [gdbarch_num_regs .. 2*gdbarch_num_regs). | |
2412 | Strictly speaking, only the second range is used as it is only second | |
2413 | range (the ABI instead of ISA registers) that comes into play when finding | |
2414 | saved registers in a frame. */ | |
eec63939 AC |
2415 | |
2416 | static void | |
74ed0bb4 MD |
2417 | set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache, |
2418 | int regnum, CORE_ADDR offset) | |
eec63939 | 2419 | { |
29639122 JB |
2420 | if (this_cache != NULL |
2421 | && this_cache->saved_regs[regnum].addr == -1) | |
2422 | { | |
74ed0bb4 MD |
2423 | this_cache->saved_regs[regnum + 0 * gdbarch_num_regs (gdbarch)].addr |
2424 | = offset; | |
2425 | this_cache->saved_regs[regnum + 1 * gdbarch_num_regs (gdbarch)].addr | |
2426 | = offset; | |
29639122 | 2427 | } |
eec63939 AC |
2428 | } |
2429 | ||
eec63939 | 2430 | |
29639122 JB |
2431 | /* Fetch the immediate value from a MIPS16 instruction. |
2432 | If the previous instruction was an EXTEND, use it to extend | |
2433 | the upper bits of the immediate value. This is a helper function | |
2434 | for mips16_scan_prologue. */ | |
eec63939 | 2435 | |
29639122 JB |
2436 | static int |
2437 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ | |
2438 | unsigned short inst, /* current instruction */ | |
2439 | int nbits, /* number of bits in imm field */ | |
2440 | int scale, /* scale factor to be applied to imm */ | |
025bb325 | 2441 | int is_signed) /* is the imm field signed? */ |
eec63939 | 2442 | { |
29639122 | 2443 | int offset; |
eec63939 | 2444 | |
29639122 JB |
2445 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
2446 | { | |
2447 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
2448 | if (offset & 0x8000) /* check for negative extend */ | |
2449 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
2450 | return offset | (inst & 0x1f); | |
2451 | } | |
eec63939 | 2452 | else |
29639122 JB |
2453 | { |
2454 | int max_imm = 1 << nbits; | |
2455 | int mask = max_imm - 1; | |
2456 | int sign_bit = max_imm >> 1; | |
45c9dd44 | 2457 | |
29639122 JB |
2458 | offset = inst & mask; |
2459 | if (is_signed && (offset & sign_bit)) | |
2460 | offset = 0 - (max_imm - offset); | |
2461 | return offset * scale; | |
2462 | } | |
2463 | } | |
eec63939 | 2464 | |
65596487 | 2465 | |
29639122 JB |
2466 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
2467 | the associated FRAME_CACHE if not null. | |
2468 | Return the address of the first instruction past the prologue. */ | |
eec63939 | 2469 | |
29639122 | 2470 | static CORE_ADDR |
e17a4113 UW |
2471 | mips16_scan_prologue (struct gdbarch *gdbarch, |
2472 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 2473 | struct frame_info *this_frame, |
29639122 JB |
2474 | struct mips_frame_cache *this_cache) |
2475 | { | |
ab50adb6 MR |
2476 | int prev_non_prologue_insn = 0; |
2477 | int this_non_prologue_insn; | |
2478 | int non_prologue_insns = 0; | |
2479 | CORE_ADDR prev_pc; | |
29639122 | 2480 | CORE_ADDR cur_pc; |
025bb325 | 2481 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer. */ |
29639122 JB |
2482 | CORE_ADDR sp; |
2483 | long frame_offset = 0; /* Size of stack frame. */ | |
2484 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
2485 | int frame_reg = MIPS_SP_REGNUM; | |
025bb325 | 2486 | unsigned short prev_inst = 0; /* saved copy of previous instruction. */ |
29639122 JB |
2487 | unsigned inst = 0; /* current instruction */ |
2488 | unsigned entry_inst = 0; /* the entry instruction */ | |
2207132d | 2489 | unsigned save_inst = 0; /* the save instruction */ |
ab50adb6 MR |
2490 | int prev_delay_slot = 0; |
2491 | int in_delay_slot; | |
29639122 | 2492 | int reg, offset; |
a343eb3c | 2493 | |
29639122 | 2494 | int extend_bytes = 0; |
ab50adb6 MR |
2495 | int prev_extend_bytes = 0; |
2496 | CORE_ADDR end_prologue_addr; | |
a343eb3c | 2497 | |
29639122 | 2498 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
2499 | THIS_FRAME. */ |
2500 | if (this_frame != NULL) | |
2501 | sp = get_frame_register_signed (this_frame, | |
2502 | gdbarch_num_regs (gdbarch) | |
2503 | + MIPS_SP_REGNUM); | |
29639122 JB |
2504 | else |
2505 | sp = 0; | |
eec63939 | 2506 | |
29639122 JB |
2507 | if (limit_pc > start_pc + 200) |
2508 | limit_pc = start_pc + 200; | |
ab50adb6 | 2509 | prev_pc = start_pc; |
eec63939 | 2510 | |
ab50adb6 MR |
2511 | /* Permit at most one non-prologue non-control-transfer instruction |
2512 | in the middle which may have been reordered by the compiler for | |
2513 | optimisation. */ | |
95ac2dcf | 2514 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) |
29639122 | 2515 | { |
ab50adb6 MR |
2516 | this_non_prologue_insn = 0; |
2517 | in_delay_slot = 0; | |
2518 | ||
29639122 JB |
2519 | /* Save the previous instruction. If it's an EXTEND, we'll extract |
2520 | the immediate offset extension from it in mips16_get_imm. */ | |
2521 | prev_inst = inst; | |
eec63939 | 2522 | |
025bb325 | 2523 | /* Fetch and decode the instruction. */ |
4cc0665f MR |
2524 | inst = (unsigned short) mips_fetch_instruction (gdbarch, ISA_MIPS16, |
2525 | cur_pc, NULL); | |
eec63939 | 2526 | |
29639122 JB |
2527 | /* Normally we ignore extend instructions. However, if it is |
2528 | not followed by a valid prologue instruction, then this | |
2529 | instruction is not part of the prologue either. We must | |
2530 | remember in this case to adjust the end_prologue_addr back | |
2531 | over the extend. */ | |
2532 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
2533 | { | |
95ac2dcf | 2534 | extend_bytes = MIPS_INSN16_SIZE; |
29639122 JB |
2535 | continue; |
2536 | } | |
eec63939 | 2537 | |
29639122 JB |
2538 | prev_extend_bytes = extend_bytes; |
2539 | extend_bytes = 0; | |
eec63939 | 2540 | |
29639122 JB |
2541 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
2542 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2543 | { | |
2544 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
025bb325 | 2545 | if (offset < 0) /* Negative stack adjustment? */ |
29639122 JB |
2546 | frame_offset -= offset; |
2547 | else | |
2548 | /* Exit loop if a positive stack adjustment is found, which | |
2549 | usually means that the stack cleanup code in the function | |
2550 | epilogue is reached. */ | |
2551 | break; | |
2552 | } | |
2553 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
2554 | { | |
2555 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
4cc0665f | 2556 | reg = mips_reg3_to_reg[(inst & 0x700) >> 8]; |
74ed0bb4 | 2557 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
2558 | } |
2559 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
2560 | { | |
2561 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
4cc0665f | 2562 | reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
74ed0bb4 | 2563 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
2564 | } |
2565 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
2566 | { | |
2567 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
74ed0bb4 | 2568 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
2569 | } |
2570 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
2571 | { | |
2572 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
74ed0bb4 | 2573 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
2574 | } |
2575 | else if (inst == 0x673d) /* move $s1, $sp */ | |
2576 | { | |
2577 | frame_addr = sp; | |
2578 | frame_reg = 17; | |
2579 | } | |
2580 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
2581 | { | |
2582 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2583 | frame_addr = sp + offset; | |
2584 | frame_reg = 17; | |
2585 | frame_adjust = offset; | |
2586 | } | |
2587 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
2588 | { | |
2589 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
4cc0665f | 2590 | reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
74ed0bb4 | 2591 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
2592 | } |
2593 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
2594 | { | |
2595 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
4cc0665f | 2596 | reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
74ed0bb4 | 2597 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
2598 | } |
2599 | else if ((inst & 0xf81f) == 0xe809 | |
2600 | && (inst & 0x700) != 0x700) /* entry */ | |
025bb325 | 2601 | entry_inst = inst; /* Save for later processing. */ |
2207132d MR |
2602 | else if ((inst & 0xff80) == 0x6480) /* save */ |
2603 | { | |
025bb325 | 2604 | save_inst = inst; /* Save for later processing. */ |
2207132d MR |
2605 | if (prev_extend_bytes) /* extend */ |
2606 | save_inst |= prev_inst << 16; | |
2607 | } | |
29639122 JB |
2608 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
2609 | { | |
2610 | /* This instruction is part of the prologue, but we don't | |
2611 | need to do anything special to handle it. */ | |
2612 | } | |
ab50adb6 MR |
2613 | else if (mips16_instruction_has_delay_slot (inst, 0)) |
2614 | /* JAL/JALR/JALX/JR */ | |
2615 | { | |
2616 | /* The instruction in the delay slot can be a part | |
2617 | of the prologue, so move forward once more. */ | |
2618 | in_delay_slot = 1; | |
2619 | if (mips16_instruction_has_delay_slot (inst, 1)) | |
2620 | /* JAL/JALX */ | |
2621 | { | |
2622 | prev_extend_bytes = MIPS_INSN16_SIZE; | |
2623 | cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ | |
2624 | } | |
2625 | } | |
29639122 JB |
2626 | else |
2627 | { | |
ab50adb6 | 2628 | this_non_prologue_insn = 1; |
29639122 | 2629 | } |
ab50adb6 MR |
2630 | |
2631 | non_prologue_insns += this_non_prologue_insn; | |
2632 | ||
2633 | /* A jump or branch, or enough non-prologue insns seen? If so, | |
2634 | then we must have reached the end of the prologue by now. */ | |
2635 | if (prev_delay_slot || non_prologue_insns > 1 | |
2636 | || mips16_instruction_is_compact_branch (inst)) | |
2637 | break; | |
2638 | ||
2639 | prev_non_prologue_insn = this_non_prologue_insn; | |
2640 | prev_delay_slot = in_delay_slot; | |
2641 | prev_pc = cur_pc - prev_extend_bytes; | |
29639122 | 2642 | } |
eec63939 | 2643 | |
29639122 JB |
2644 | /* The entry instruction is typically the first instruction in a function, |
2645 | and it stores registers at offsets relative to the value of the old SP | |
2646 | (before the prologue). But the value of the sp parameter to this | |
2647 | function is the new SP (after the prologue has been executed). So we | |
2648 | can't calculate those offsets until we've seen the entire prologue, | |
025bb325 | 2649 | and can calculate what the old SP must have been. */ |
29639122 JB |
2650 | if (entry_inst != 0) |
2651 | { | |
2652 | int areg_count = (entry_inst >> 8) & 7; | |
2653 | int sreg_count = (entry_inst >> 6) & 3; | |
eec63939 | 2654 | |
29639122 JB |
2655 | /* The entry instruction always subtracts 32 from the SP. */ |
2656 | frame_offset += 32; | |
2657 | ||
2658 | /* Now we can calculate what the SP must have been at the | |
2659 | start of the function prologue. */ | |
2660 | sp += frame_offset; | |
2661 | ||
2662 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
2663 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
2664 | { | |
74ed0bb4 | 2665 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 2666 | offset += mips_abi_regsize (gdbarch); |
29639122 JB |
2667 | } |
2668 | ||
2669 | /* Check if the ra register was pushed on the stack. */ | |
2670 | offset = -4; | |
2671 | if (entry_inst & 0x20) | |
2672 | { | |
74ed0bb4 | 2673 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
72a155b4 | 2674 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
2675 | } |
2676 | ||
2677 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
2678 | for (reg = 16; reg < sreg_count + 16; reg++) | |
2679 | { | |
74ed0bb4 | 2680 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 2681 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
2682 | } |
2683 | } | |
2684 | ||
2207132d MR |
2685 | /* The SAVE instruction is similar to ENTRY, except that defined by the |
2686 | MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the | |
2687 | size of the frame is specified as an immediate field of instruction | |
2688 | and an extended variation exists which lets additional registers and | |
2689 | frame space to be specified. The instruction always treats registers | |
2690 | as 32-bit so its usefulness for 64-bit ABIs is questionable. */ | |
2691 | if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4) | |
2692 | { | |
2693 | static int args_table[16] = { | |
2694 | 0, 0, 0, 0, 1, 1, 1, 1, | |
2695 | 2, 2, 2, 0, 3, 3, 4, -1, | |
2696 | }; | |
2697 | static int astatic_table[16] = { | |
2698 | 0, 1, 2, 3, 0, 1, 2, 3, | |
2699 | 0, 1, 2, 4, 0, 1, 0, -1, | |
2700 | }; | |
2701 | int aregs = (save_inst >> 16) & 0xf; | |
2702 | int xsregs = (save_inst >> 24) & 0x7; | |
2703 | int args = args_table[aregs]; | |
2704 | int astatic = astatic_table[aregs]; | |
2705 | long frame_size; | |
2706 | ||
2707 | if (args < 0) | |
2708 | { | |
2709 | warning (_("Invalid number of argument registers encoded in SAVE.")); | |
2710 | args = 0; | |
2711 | } | |
2712 | if (astatic < 0) | |
2713 | { | |
2714 | warning (_("Invalid number of static registers encoded in SAVE.")); | |
2715 | astatic = 0; | |
2716 | } | |
2717 | ||
2718 | /* For standard SAVE the frame size of 0 means 128. */ | |
2719 | frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf); | |
2720 | if (frame_size == 0 && (save_inst >> 16) == 0) | |
2721 | frame_size = 16; | |
2722 | frame_size *= 8; | |
2723 | frame_offset += frame_size; | |
2724 | ||
2725 | /* Now we can calculate what the SP must have been at the | |
2726 | start of the function prologue. */ | |
2727 | sp += frame_offset; | |
2728 | ||
2729 | /* Check if A0-A3 were saved in the caller's argument save area. */ | |
2730 | for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++) | |
2731 | { | |
74ed0bb4 | 2732 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
2733 | offset += mips_abi_regsize (gdbarch); |
2734 | } | |
2735 | ||
2736 | offset = -4; | |
2737 | ||
2738 | /* Check if the RA register was pushed on the stack. */ | |
2739 | if (save_inst & 0x40) | |
2740 | { | |
74ed0bb4 | 2741 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
2207132d MR |
2742 | offset -= mips_abi_regsize (gdbarch); |
2743 | } | |
2744 | ||
2745 | /* Check if the S8 register was pushed on the stack. */ | |
2746 | if (xsregs > 6) | |
2747 | { | |
74ed0bb4 | 2748 | set_reg_offset (gdbarch, this_cache, 30, sp + offset); |
2207132d MR |
2749 | offset -= mips_abi_regsize (gdbarch); |
2750 | xsregs--; | |
2751 | } | |
2752 | /* Check if S2-S7 were pushed on the stack. */ | |
2753 | for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--) | |
2754 | { | |
74ed0bb4 | 2755 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
2756 | offset -= mips_abi_regsize (gdbarch); |
2757 | } | |
2758 | ||
2759 | /* Check if the S1 register was pushed on the stack. */ | |
2760 | if (save_inst & 0x10) | |
2761 | { | |
74ed0bb4 | 2762 | set_reg_offset (gdbarch, this_cache, 17, sp + offset); |
2207132d MR |
2763 | offset -= mips_abi_regsize (gdbarch); |
2764 | } | |
2765 | /* Check if the S0 register was pushed on the stack. */ | |
2766 | if (save_inst & 0x20) | |
2767 | { | |
74ed0bb4 | 2768 | set_reg_offset (gdbarch, this_cache, 16, sp + offset); |
2207132d MR |
2769 | offset -= mips_abi_regsize (gdbarch); |
2770 | } | |
2771 | ||
4cc0665f MR |
2772 | /* Check if A0-A3 were pushed on the stack. */ |
2773 | for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--) | |
2774 | { | |
2775 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); | |
2776 | offset -= mips_abi_regsize (gdbarch); | |
2777 | } | |
2778 | } | |
2779 | ||
2780 | if (this_cache != NULL) | |
2781 | { | |
2782 | this_cache->base = | |
2783 | (get_frame_register_signed (this_frame, | |
2784 | gdbarch_num_regs (gdbarch) + frame_reg) | |
2785 | + frame_offset - frame_adjust); | |
2786 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should | |
2787 | be able to get rid of the assignment below, evetually. But it's | |
2788 | still needed for now. */ | |
2789 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) | |
2790 | + mips_regnum (gdbarch)->pc] | |
2791 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; | |
2792 | } | |
2793 | ||
ab50adb6 MR |
2794 | /* Set end_prologue_addr to the address of the instruction immediately |
2795 | after the last one we scanned. Unless the last one looked like a | |
2796 | non-prologue instruction (and we looked ahead), in which case use | |
2797 | its address instead. */ | |
2798 | end_prologue_addr = (prev_non_prologue_insn || prev_delay_slot | |
2799 | ? prev_pc : cur_pc - prev_extend_bytes); | |
4cc0665f MR |
2800 | |
2801 | return end_prologue_addr; | |
2802 | } | |
2803 | ||
2804 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). | |
2805 | Procedures that use the 32-bit instruction set are handled by the | |
2806 | mips_insn32 unwinder. */ | |
2807 | ||
2808 | static struct mips_frame_cache * | |
2809 | mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache) | |
2810 | { | |
2811 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2812 | struct mips_frame_cache *cache; | |
2813 | ||
2814 | if ((*this_cache) != NULL) | |
19ba03f4 | 2815 | return (struct mips_frame_cache *) (*this_cache); |
4cc0665f MR |
2816 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
2817 | (*this_cache) = cache; | |
2818 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
2819 | ||
2820 | /* Analyze the function prologue. */ | |
2821 | { | |
2822 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); | |
2823 | CORE_ADDR start_addr; | |
2824 | ||
2825 | find_pc_partial_function (pc, NULL, &start_addr, NULL); | |
2826 | if (start_addr == 0) | |
2827 | start_addr = heuristic_proc_start (gdbarch, pc); | |
2828 | /* We can't analyze the prologue if we couldn't find the begining | |
2829 | of the function. */ | |
2830 | if (start_addr == 0) | |
2831 | return cache; | |
2832 | ||
19ba03f4 SM |
2833 | mips16_scan_prologue (gdbarch, start_addr, pc, this_frame, |
2834 | (struct mips_frame_cache *) *this_cache); | |
4cc0665f MR |
2835 | } |
2836 | ||
2837 | /* gdbarch_sp_regnum contains the value and not the address. */ | |
2838 | trad_frame_set_value (cache->saved_regs, | |
2839 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, | |
2840 | cache->base); | |
2841 | ||
19ba03f4 | 2842 | return (struct mips_frame_cache *) (*this_cache); |
4cc0665f MR |
2843 | } |
2844 | ||
2845 | static void | |
2846 | mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache, | |
2847 | struct frame_id *this_id) | |
2848 | { | |
2849 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, | |
2850 | this_cache); | |
2851 | /* This marks the outermost frame. */ | |
2852 | if (info->base == 0) | |
2853 | return; | |
2854 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); | |
2855 | } | |
2856 | ||
2857 | static struct value * | |
2858 | mips_insn16_frame_prev_register (struct frame_info *this_frame, | |
2859 | void **this_cache, int regnum) | |
2860 | { | |
2861 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, | |
2862 | this_cache); | |
2863 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); | |
2864 | } | |
2865 | ||
2866 | static int | |
2867 | mips_insn16_frame_sniffer (const struct frame_unwind *self, | |
2868 | struct frame_info *this_frame, void **this_cache) | |
2869 | { | |
2870 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2871 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2872 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
2873 | return 1; | |
2874 | return 0; | |
2875 | } | |
2876 | ||
2877 | static const struct frame_unwind mips_insn16_frame_unwind = | |
2878 | { | |
2879 | NORMAL_FRAME, | |
2880 | default_frame_unwind_stop_reason, | |
2881 | mips_insn16_frame_this_id, | |
2882 | mips_insn16_frame_prev_register, | |
2883 | NULL, | |
2884 | mips_insn16_frame_sniffer | |
2885 | }; | |
2886 | ||
2887 | static CORE_ADDR | |
2888 | mips_insn16_frame_base_address (struct frame_info *this_frame, | |
2889 | void **this_cache) | |
2890 | { | |
2891 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, | |
2892 | this_cache); | |
2893 | return info->base; | |
2894 | } | |
2895 | ||
2896 | static const struct frame_base mips_insn16_frame_base = | |
2897 | { | |
2898 | &mips_insn16_frame_unwind, | |
2899 | mips_insn16_frame_base_address, | |
2900 | mips_insn16_frame_base_address, | |
2901 | mips_insn16_frame_base_address | |
2902 | }; | |
2903 | ||
2904 | static const struct frame_base * | |
2905 | mips_insn16_frame_base_sniffer (struct frame_info *this_frame) | |
2906 | { | |
2907 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2908 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2909 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
2910 | return &mips_insn16_frame_base; | |
2911 | else | |
2912 | return NULL; | |
2913 | } | |
2914 | ||
2915 | /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped | |
2916 | to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are | |
2917 | interpreted directly, and then multiplied by 4. */ | |
2918 | ||
2919 | static int | |
2920 | micromips_decode_imm9 (int imm) | |
2921 | { | |
2922 | imm = (imm ^ 0x100) - 0x100; | |
2923 | if (imm > -3 && imm < 2) | |
2924 | imm ^= 0x100; | |
2925 | return imm << 2; | |
2926 | } | |
2927 | ||
2928 | /* Analyze the function prologue from START_PC to LIMIT_PC. Return | |
2929 | the address of the first instruction past the prologue. */ | |
2930 | ||
2931 | static CORE_ADDR | |
2932 | micromips_scan_prologue (struct gdbarch *gdbarch, | |
2933 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
2934 | struct frame_info *this_frame, | |
2935 | struct mips_frame_cache *this_cache) | |
2936 | { | |
ab50adb6 | 2937 | CORE_ADDR end_prologue_addr; |
4cc0665f MR |
2938 | int prev_non_prologue_insn = 0; |
2939 | int frame_reg = MIPS_SP_REGNUM; | |
2940 | int this_non_prologue_insn; | |
2941 | int non_prologue_insns = 0; | |
2942 | long frame_offset = 0; /* Size of stack frame. */ | |
2943 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
ab50adb6 MR |
2944 | int prev_delay_slot = 0; |
2945 | int in_delay_slot; | |
4cc0665f MR |
2946 | CORE_ADDR prev_pc; |
2947 | CORE_ADDR cur_pc; | |
2948 | ULONGEST insn; /* current instruction */ | |
2949 | CORE_ADDR sp; | |
2950 | long offset; | |
2951 | long sp_adj; | |
2952 | long v1_off = 0; /* The assumption is LUI will replace it. */ | |
2953 | int reglist; | |
2954 | int breg; | |
2955 | int dreg; | |
2956 | int sreg; | |
2957 | int treg; | |
2958 | int loc; | |
2959 | int op; | |
2960 | int s; | |
2961 | int i; | |
2962 | ||
2963 | /* Can be called when there's no process, and hence when there's no | |
2964 | THIS_FRAME. */ | |
2965 | if (this_frame != NULL) | |
2966 | sp = get_frame_register_signed (this_frame, | |
2967 | gdbarch_num_regs (gdbarch) | |
2968 | + MIPS_SP_REGNUM); | |
2969 | else | |
2970 | sp = 0; | |
2971 | ||
2972 | if (limit_pc > start_pc + 200) | |
2973 | limit_pc = start_pc + 200; | |
2974 | prev_pc = start_pc; | |
2975 | ||
2976 | /* Permit at most one non-prologue non-control-transfer instruction | |
2977 | in the middle which may have been reordered by the compiler for | |
2978 | optimisation. */ | |
2979 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += loc) | |
2980 | { | |
2981 | this_non_prologue_insn = 0; | |
ab50adb6 | 2982 | in_delay_slot = 0; |
4cc0665f MR |
2983 | sp_adj = 0; |
2984 | loc = 0; | |
2985 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, cur_pc, NULL); | |
2986 | loc += MIPS_INSN16_SIZE; | |
2987 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
2988 | { | |
4cc0665f MR |
2989 | /* 32-bit instructions. */ |
2990 | case 2 * MIPS_INSN16_SIZE: | |
2991 | insn <<= 16; | |
2992 | insn |= mips_fetch_instruction (gdbarch, | |
2993 | ISA_MICROMIPS, cur_pc + loc, NULL); | |
2994 | loc += MIPS_INSN16_SIZE; | |
2995 | switch (micromips_op (insn >> 16)) | |
2996 | { | |
2997 | /* Record $sp/$fp adjustment. */ | |
2998 | /* Discard (D)ADDU $gp,$jp used for PIC code. */ | |
2999 | case 0x0: /* POOL32A: bits 000000 */ | |
3000 | case 0x16: /* POOL32S: bits 010110 */ | |
3001 | op = b0s11_op (insn); | |
3002 | sreg = b0s5_reg (insn >> 16); | |
3003 | treg = b5s5_reg (insn >> 16); | |
3004 | dreg = b11s5_reg (insn); | |
3005 | if (op == 0x1d0 | |
3006 | /* SUBU: bits 000000 00111010000 */ | |
3007 | /* DSUBU: bits 010110 00111010000 */ | |
3008 | && dreg == MIPS_SP_REGNUM && sreg == MIPS_SP_REGNUM | |
3009 | && treg == 3) | |
3010 | /* (D)SUBU $sp, $v1 */ | |
3011 | sp_adj = v1_off; | |
3012 | else if (op != 0x150 | |
3013 | /* ADDU: bits 000000 00101010000 */ | |
3014 | /* DADDU: bits 010110 00101010000 */ | |
3015 | || dreg != 28 || sreg != 28 || treg != MIPS_T9_REGNUM) | |
3016 | this_non_prologue_insn = 1; | |
3017 | break; | |
3018 | ||
3019 | case 0x8: /* POOL32B: bits 001000 */ | |
3020 | op = b12s4_op (insn); | |
3021 | breg = b0s5_reg (insn >> 16); | |
3022 | reglist = sreg = b5s5_reg (insn >> 16); | |
3023 | offset = (b0s12_imm (insn) ^ 0x800) - 0x800; | |
3024 | if ((op == 0x9 || op == 0xc) | |
3025 | /* SWP: bits 001000 1001 */ | |
3026 | /* SDP: bits 001000 1100 */ | |
3027 | && breg == MIPS_SP_REGNUM && sreg < MIPS_RA_REGNUM) | |
3028 | /* S[DW]P reg,offset($sp) */ | |
3029 | { | |
3030 | s = 4 << ((b12s4_op (insn) & 0x4) == 0x4); | |
3031 | set_reg_offset (gdbarch, this_cache, | |
3032 | sreg, sp + offset); | |
3033 | set_reg_offset (gdbarch, this_cache, | |
3034 | sreg + 1, sp + offset + s); | |
3035 | } | |
3036 | else if ((op == 0xd || op == 0xf) | |
3037 | /* SWM: bits 001000 1101 */ | |
3038 | /* SDM: bits 001000 1111 */ | |
3039 | && breg == MIPS_SP_REGNUM | |
3040 | /* SWM reglist,offset($sp) */ | |
3041 | && ((reglist >= 1 && reglist <= 9) | |
3042 | || (reglist >= 16 && reglist <= 25))) | |
3043 | { | |
325fac50 | 3044 | int sreglist = std::min(reglist & 0xf, 8); |
4cc0665f MR |
3045 | |
3046 | s = 4 << ((b12s4_op (insn) & 0x2) == 0x2); | |
3047 | for (i = 0; i < sreglist; i++) | |
3048 | set_reg_offset (gdbarch, this_cache, 16 + i, sp + s * i); | |
3049 | if ((reglist & 0xf) > 8) | |
3050 | set_reg_offset (gdbarch, this_cache, 30, sp + s * i++); | |
3051 | if ((reglist & 0x10) == 0x10) | |
3052 | set_reg_offset (gdbarch, this_cache, | |
3053 | MIPS_RA_REGNUM, sp + s * i++); | |
3054 | } | |
3055 | else | |
3056 | this_non_prologue_insn = 1; | |
3057 | break; | |
3058 | ||
3059 | /* Record $sp/$fp adjustment. */ | |
3060 | /* Discard (D)ADDIU $gp used for PIC code. */ | |
3061 | case 0xc: /* ADDIU: bits 001100 */ | |
3062 | case 0x17: /* DADDIU: bits 010111 */ | |
3063 | sreg = b0s5_reg (insn >> 16); | |
3064 | dreg = b5s5_reg (insn >> 16); | |
3065 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
3066 | if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM) | |
3067 | /* (D)ADDIU $sp, imm */ | |
3068 | sp_adj = offset; | |
3069 | else if (sreg == MIPS_SP_REGNUM && dreg == 30) | |
3070 | /* (D)ADDIU $fp, $sp, imm */ | |
3071 | { | |
4cc0665f MR |
3072 | frame_adjust = offset; |
3073 | frame_reg = 30; | |
3074 | } | |
3075 | else if (sreg != 28 || dreg != 28) | |
3076 | /* (D)ADDIU $gp, imm */ | |
3077 | this_non_prologue_insn = 1; | |
3078 | break; | |
3079 | ||
3080 | /* LUI $v1 is used for larger $sp adjustments. */ | |
3356937a | 3081 | /* Discard LUI $gp used for PIC code. */ |
4cc0665f MR |
3082 | case 0x10: /* POOL32I: bits 010000 */ |
3083 | if (b5s5_op (insn >> 16) == 0xd | |
3084 | /* LUI: bits 010000 001101 */ | |
3085 | && b0s5_reg (insn >> 16) == 3) | |
3086 | /* LUI $v1, imm */ | |
3087 | v1_off = ((b0s16_imm (insn) << 16) ^ 0x80000000) - 0x80000000; | |
3088 | else if (b5s5_op (insn >> 16) != 0xd | |
3089 | /* LUI: bits 010000 001101 */ | |
3090 | || b0s5_reg (insn >> 16) != 28) | |
3091 | /* LUI $gp, imm */ | |
3092 | this_non_prologue_insn = 1; | |
3093 | break; | |
3094 | ||
3095 | /* ORI $v1 is used for larger $sp adjustments. */ | |
3096 | case 0x14: /* ORI: bits 010100 */ | |
3097 | sreg = b0s5_reg (insn >> 16); | |
3098 | dreg = b5s5_reg (insn >> 16); | |
3099 | if (sreg == 3 && dreg == 3) | |
3100 | /* ORI $v1, imm */ | |
3101 | v1_off |= b0s16_imm (insn); | |
3102 | else | |
3103 | this_non_prologue_insn = 1; | |
3104 | break; | |
3105 | ||
3106 | case 0x26: /* SWC1: bits 100110 */ | |
3107 | case 0x2e: /* SDC1: bits 101110 */ | |
3108 | breg = b0s5_reg (insn >> 16); | |
3109 | if (breg != MIPS_SP_REGNUM) | |
3110 | /* S[DW]C1 reg,offset($sp) */ | |
3111 | this_non_prologue_insn = 1; | |
3112 | break; | |
3113 | ||
3114 | case 0x36: /* SD: bits 110110 */ | |
3115 | case 0x3e: /* SW: bits 111110 */ | |
3116 | breg = b0s5_reg (insn >> 16); | |
3117 | sreg = b5s5_reg (insn >> 16); | |
3118 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
3119 | if (breg == MIPS_SP_REGNUM) | |
3120 | /* S[DW] reg,offset($sp) */ | |
3121 | set_reg_offset (gdbarch, this_cache, sreg, sp + offset); | |
3122 | else | |
3123 | this_non_prologue_insn = 1; | |
3124 | break; | |
3125 | ||
3126 | default: | |
ab50adb6 MR |
3127 | /* The instruction in the delay slot can be a part |
3128 | of the prologue, so move forward once more. */ | |
3129 | if (micromips_instruction_has_delay_slot (insn, 0)) | |
3130 | in_delay_slot = 1; | |
3131 | else | |
3132 | this_non_prologue_insn = 1; | |
4cc0665f MR |
3133 | break; |
3134 | } | |
ab50adb6 | 3135 | insn >>= 16; |
4cc0665f MR |
3136 | break; |
3137 | ||
3138 | /* 16-bit instructions. */ | |
3139 | case MIPS_INSN16_SIZE: | |
3140 | switch (micromips_op (insn)) | |
3141 | { | |
3142 | case 0x3: /* MOVE: bits 000011 */ | |
3143 | sreg = b0s5_reg (insn); | |
3144 | dreg = b5s5_reg (insn); | |
3145 | if (sreg == MIPS_SP_REGNUM && dreg == 30) | |
3146 | /* MOVE $fp, $sp */ | |
78cc6c2d | 3147 | frame_reg = 30; |
4cc0665f MR |
3148 | else if ((sreg & 0x1c) != 0x4) |
3149 | /* MOVE reg, $a0-$a3 */ | |
3150 | this_non_prologue_insn = 1; | |
3151 | break; | |
3152 | ||
3153 | case 0x11: /* POOL16C: bits 010001 */ | |
3154 | if (b6s4_op (insn) == 0x5) | |
3155 | /* SWM: bits 010001 0101 */ | |
3156 | { | |
3157 | offset = ((b0s4_imm (insn) << 2) ^ 0x20) - 0x20; | |
3158 | reglist = b4s2_regl (insn); | |
3159 | for (i = 0; i <= reglist; i++) | |
3160 | set_reg_offset (gdbarch, this_cache, 16 + i, sp + 4 * i); | |
3161 | set_reg_offset (gdbarch, this_cache, | |
3162 | MIPS_RA_REGNUM, sp + 4 * i++); | |
3163 | } | |
3164 | else | |
3165 | this_non_prologue_insn = 1; | |
3166 | break; | |
3167 | ||
3168 | case 0x13: /* POOL16D: bits 010011 */ | |
3169 | if ((insn & 0x1) == 0x1) | |
3170 | /* ADDIUSP: bits 010011 1 */ | |
3171 | sp_adj = micromips_decode_imm9 (b1s9_imm (insn)); | |
3172 | else if (b5s5_reg (insn) == MIPS_SP_REGNUM) | |
3173 | /* ADDIUS5: bits 010011 0 */ | |
3174 | /* ADDIUS5 $sp, imm */ | |
3175 | sp_adj = (b1s4_imm (insn) ^ 8) - 8; | |
3176 | else | |
3177 | this_non_prologue_insn = 1; | |
3178 | break; | |
3179 | ||
3180 | case 0x32: /* SWSP: bits 110010 */ | |
3181 | offset = b0s5_imm (insn) << 2; | |
3182 | sreg = b5s5_reg (insn); | |
3183 | set_reg_offset (gdbarch, this_cache, sreg, sp + offset); | |
3184 | break; | |
3185 | ||
3186 | default: | |
ab50adb6 MR |
3187 | /* The instruction in the delay slot can be a part |
3188 | of the prologue, so move forward once more. */ | |
3189 | if (micromips_instruction_has_delay_slot (insn << 16, 0)) | |
3190 | in_delay_slot = 1; | |
3191 | else | |
3192 | this_non_prologue_insn = 1; | |
4cc0665f MR |
3193 | break; |
3194 | } | |
3195 | break; | |
3196 | } | |
3197 | if (sp_adj < 0) | |
3198 | frame_offset -= sp_adj; | |
3199 | ||
3200 | non_prologue_insns += this_non_prologue_insn; | |
ab50adb6 MR |
3201 | |
3202 | /* A jump or branch, enough non-prologue insns seen or positive | |
3203 | stack adjustment? If so, then we must have reached the end | |
3204 | of the prologue by now. */ | |
3205 | if (prev_delay_slot || non_prologue_insns > 1 || sp_adj > 0 | |
3206 | || micromips_instruction_is_compact_branch (insn)) | |
3207 | break; | |
3208 | ||
4cc0665f | 3209 | prev_non_prologue_insn = this_non_prologue_insn; |
ab50adb6 | 3210 | prev_delay_slot = in_delay_slot; |
4cc0665f | 3211 | prev_pc = cur_pc; |
2207132d MR |
3212 | } |
3213 | ||
29639122 JB |
3214 | if (this_cache != NULL) |
3215 | { | |
3216 | this_cache->base = | |
4cc0665f | 3217 | (get_frame_register_signed (this_frame, |
b8a22b94 | 3218 | gdbarch_num_regs (gdbarch) + frame_reg) |
4cc0665f | 3219 | + frame_offset - frame_adjust); |
29639122 | 3220 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should |
4cc0665f MR |
3221 | be able to get rid of the assignment below, evetually. But it's |
3222 | still needed for now. */ | |
72a155b4 UW |
3223 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
3224 | + mips_regnum (gdbarch)->pc] | |
4cc0665f | 3225 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; |
29639122 JB |
3226 | } |
3227 | ||
ab50adb6 MR |
3228 | /* Set end_prologue_addr to the address of the instruction immediately |
3229 | after the last one we scanned. Unless the last one looked like a | |
3230 | non-prologue instruction (and we looked ahead), in which case use | |
3231 | its address instead. */ | |
3232 | end_prologue_addr | |
3233 | = prev_non_prologue_insn || prev_delay_slot ? prev_pc : cur_pc; | |
29639122 JB |
3234 | |
3235 | return end_prologue_addr; | |
eec63939 AC |
3236 | } |
3237 | ||
4cc0665f | 3238 | /* Heuristic unwinder for procedures using microMIPS instructions. |
29639122 | 3239 | Procedures that use the 32-bit instruction set are handled by the |
4cc0665f | 3240 | mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */ |
29639122 JB |
3241 | |
3242 | static struct mips_frame_cache * | |
4cc0665f | 3243 | mips_micro_frame_cache (struct frame_info *this_frame, void **this_cache) |
eec63939 | 3244 | { |
e17a4113 | 3245 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 3246 | struct mips_frame_cache *cache; |
eec63939 AC |
3247 | |
3248 | if ((*this_cache) != NULL) | |
19ba03f4 | 3249 | return (struct mips_frame_cache *) (*this_cache); |
4cc0665f | 3250 | |
29639122 JB |
3251 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
3252 | (*this_cache) = cache; | |
b8a22b94 | 3253 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
eec63939 | 3254 | |
29639122 JB |
3255 | /* Analyze the function prologue. */ |
3256 | { | |
b8a22b94 | 3257 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 3258 | CORE_ADDR start_addr; |
eec63939 | 3259 | |
29639122 JB |
3260 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
3261 | if (start_addr == 0) | |
4cc0665f | 3262 | start_addr = heuristic_proc_start (get_frame_arch (this_frame), pc); |
29639122 JB |
3263 | /* We can't analyze the prologue if we couldn't find the begining |
3264 | of the function. */ | |
3265 | if (start_addr == 0) | |
3266 | return cache; | |
eec63939 | 3267 | |
19ba03f4 SM |
3268 | micromips_scan_prologue (gdbarch, start_addr, pc, this_frame, |
3269 | (struct mips_frame_cache *) *this_cache); | |
29639122 | 3270 | } |
4cc0665f | 3271 | |
3e8c568d | 3272 | /* gdbarch_sp_regnum contains the value and not the address. */ |
72a155b4 | 3273 | trad_frame_set_value (cache->saved_regs, |
e17a4113 | 3274 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
72a155b4 | 3275 | cache->base); |
eec63939 | 3276 | |
19ba03f4 | 3277 | return (struct mips_frame_cache *) (*this_cache); |
eec63939 AC |
3278 | } |
3279 | ||
3280 | static void | |
4cc0665f MR |
3281 | mips_micro_frame_this_id (struct frame_info *this_frame, void **this_cache, |
3282 | struct frame_id *this_id) | |
eec63939 | 3283 | { |
4cc0665f MR |
3284 | struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
3285 | this_cache); | |
21327321 DJ |
3286 | /* This marks the outermost frame. */ |
3287 | if (info->base == 0) | |
3288 | return; | |
b8a22b94 | 3289 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
eec63939 AC |
3290 | } |
3291 | ||
b8a22b94 | 3292 | static struct value * |
4cc0665f MR |
3293 | mips_micro_frame_prev_register (struct frame_info *this_frame, |
3294 | void **this_cache, int regnum) | |
eec63939 | 3295 | { |
4cc0665f MR |
3296 | struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
3297 | this_cache); | |
b8a22b94 DJ |
3298 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
3299 | } | |
3300 | ||
3301 | static int | |
4cc0665f MR |
3302 | mips_micro_frame_sniffer (const struct frame_unwind *self, |
3303 | struct frame_info *this_frame, void **this_cache) | |
b8a22b94 | 3304 | { |
4cc0665f | 3305 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
b8a22b94 | 3306 | CORE_ADDR pc = get_frame_pc (this_frame); |
4cc0665f MR |
3307 | |
3308 | if (mips_pc_is_micromips (gdbarch, pc)) | |
b8a22b94 DJ |
3309 | return 1; |
3310 | return 0; | |
eec63939 AC |
3311 | } |
3312 | ||
4cc0665f | 3313 | static const struct frame_unwind mips_micro_frame_unwind = |
eec63939 AC |
3314 | { |
3315 | NORMAL_FRAME, | |
8fbca658 | 3316 | default_frame_unwind_stop_reason, |
4cc0665f MR |
3317 | mips_micro_frame_this_id, |
3318 | mips_micro_frame_prev_register, | |
b8a22b94 | 3319 | NULL, |
4cc0665f | 3320 | mips_micro_frame_sniffer |
eec63939 AC |
3321 | }; |
3322 | ||
eec63939 | 3323 | static CORE_ADDR |
4cc0665f MR |
3324 | mips_micro_frame_base_address (struct frame_info *this_frame, |
3325 | void **this_cache) | |
eec63939 | 3326 | { |
4cc0665f MR |
3327 | struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
3328 | this_cache); | |
29639122 | 3329 | return info->base; |
eec63939 AC |
3330 | } |
3331 | ||
4cc0665f | 3332 | static const struct frame_base mips_micro_frame_base = |
eec63939 | 3333 | { |
4cc0665f MR |
3334 | &mips_micro_frame_unwind, |
3335 | mips_micro_frame_base_address, | |
3336 | mips_micro_frame_base_address, | |
3337 | mips_micro_frame_base_address | |
eec63939 AC |
3338 | }; |
3339 | ||
3340 | static const struct frame_base * | |
4cc0665f | 3341 | mips_micro_frame_base_sniffer (struct frame_info *this_frame) |
eec63939 | 3342 | { |
4cc0665f | 3343 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
b8a22b94 | 3344 | CORE_ADDR pc = get_frame_pc (this_frame); |
4cc0665f MR |
3345 | |
3346 | if (mips_pc_is_micromips (gdbarch, pc)) | |
3347 | return &mips_micro_frame_base; | |
eec63939 AC |
3348 | else |
3349 | return NULL; | |
edfae063 AC |
3350 | } |
3351 | ||
29639122 JB |
3352 | /* Mark all the registers as unset in the saved_regs array |
3353 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
3354 | ||
74ed0bb4 MD |
3355 | static void |
3356 | reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache) | |
c906108c | 3357 | { |
29639122 JB |
3358 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
3359 | return; | |
3360 | ||
3361 | { | |
74ed0bb4 | 3362 | const int num_regs = gdbarch_num_regs (gdbarch); |
29639122 | 3363 | int i; |
64159455 | 3364 | |
29639122 JB |
3365 | for (i = 0; i < num_regs; i++) |
3366 | { | |
3367 | this_cache->saved_regs[i].addr = -1; | |
3368 | } | |
3369 | } | |
c906108c SS |
3370 | } |
3371 | ||
025bb325 | 3372 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
29639122 JB |
3373 | the associated FRAME_CACHE if not null. |
3374 | Return the address of the first instruction past the prologue. */ | |
c906108c | 3375 | |
875e1767 | 3376 | static CORE_ADDR |
e17a4113 UW |
3377 | mips32_scan_prologue (struct gdbarch *gdbarch, |
3378 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 3379 | struct frame_info *this_frame, |
29639122 | 3380 | struct mips_frame_cache *this_cache) |
c906108c | 3381 | { |
ab50adb6 MR |
3382 | int prev_non_prologue_insn; |
3383 | int this_non_prologue_insn; | |
3384 | int non_prologue_insns; | |
025bb325 MS |
3385 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for |
3386 | frame-pointer. */ | |
ab50adb6 MR |
3387 | int prev_delay_slot; |
3388 | CORE_ADDR prev_pc; | |
3389 | CORE_ADDR cur_pc; | |
29639122 JB |
3390 | CORE_ADDR sp; |
3391 | long frame_offset; | |
3392 | int frame_reg = MIPS_SP_REGNUM; | |
8fa9cfa1 | 3393 | |
ab50adb6 | 3394 | CORE_ADDR end_prologue_addr; |
29639122 JB |
3395 | int seen_sp_adjust = 0; |
3396 | int load_immediate_bytes = 0; | |
ab50adb6 | 3397 | int in_delay_slot; |
7d1e6fb8 | 3398 | int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8); |
8fa9cfa1 | 3399 | |
29639122 | 3400 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
3401 | THIS_FRAME. */ |
3402 | if (this_frame != NULL) | |
3403 | sp = get_frame_register_signed (this_frame, | |
3404 | gdbarch_num_regs (gdbarch) | |
3405 | + MIPS_SP_REGNUM); | |
8fa9cfa1 | 3406 | else |
29639122 | 3407 | sp = 0; |
9022177c | 3408 | |
29639122 JB |
3409 | if (limit_pc > start_pc + 200) |
3410 | limit_pc = start_pc + 200; | |
9022177c | 3411 | |
29639122 | 3412 | restart: |
ab50adb6 MR |
3413 | prev_non_prologue_insn = 0; |
3414 | non_prologue_insns = 0; | |
3415 | prev_delay_slot = 0; | |
3416 | prev_pc = start_pc; | |
9022177c | 3417 | |
ab50adb6 MR |
3418 | /* Permit at most one non-prologue non-control-transfer instruction |
3419 | in the middle which may have been reordered by the compiler for | |
3420 | optimisation. */ | |
29639122 | 3421 | frame_offset = 0; |
95ac2dcf | 3422 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) |
9022177c | 3423 | { |
eaa6a9a4 MR |
3424 | unsigned long inst, high_word; |
3425 | long offset; | |
29639122 | 3426 | int reg; |
9022177c | 3427 | |
ab50adb6 MR |
3428 | this_non_prologue_insn = 0; |
3429 | in_delay_slot = 0; | |
3430 | ||
025bb325 | 3431 | /* Fetch the instruction. */ |
4cc0665f MR |
3432 | inst = (unsigned long) mips_fetch_instruction (gdbarch, ISA_MIPS, |
3433 | cur_pc, NULL); | |
9022177c | 3434 | |
29639122 JB |
3435 | /* Save some code by pre-extracting some useful fields. */ |
3436 | high_word = (inst >> 16) & 0xffff; | |
eaa6a9a4 | 3437 | offset = ((inst & 0xffff) ^ 0x8000) - 0x8000; |
29639122 | 3438 | reg = high_word & 0x1f; |
fe29b929 | 3439 | |
025bb325 | 3440 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
29639122 JB |
3441 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
3442 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
3443 | { | |
eaa6a9a4 MR |
3444 | if (offset < 0) /* Negative stack adjustment? */ |
3445 | frame_offset -= offset; | |
29639122 JB |
3446 | else |
3447 | /* Exit loop if a positive stack adjustment is found, which | |
3448 | usually means that the stack cleanup code in the function | |
3449 | epilogue is reached. */ | |
3450 | break; | |
3451 | seen_sp_adjust = 1; | |
3452 | } | |
7d1e6fb8 KB |
3453 | else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ |
3454 | && !regsize_is_64_bits) | |
29639122 | 3455 | { |
eaa6a9a4 | 3456 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 | 3457 | } |
7d1e6fb8 KB |
3458 | else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ |
3459 | && regsize_is_64_bits) | |
29639122 JB |
3460 | { |
3461 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ | |
eaa6a9a4 | 3462 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
3463 | } |
3464 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
3465 | { | |
3466 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
eaa6a9a4 MR |
3467 | if (offset != frame_offset) |
3468 | frame_addr = sp + offset; | |
b8a22b94 | 3469 | else if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
3470 | { |
3471 | unsigned alloca_adjust; | |
a4b8ebc8 | 3472 | |
29639122 | 3473 | frame_reg = 30; |
b8a22b94 DJ |
3474 | frame_addr = get_frame_register_signed |
3475 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
ca9c94ef | 3476 | frame_offset = 0; |
d2ca4222 | 3477 | |
eaa6a9a4 | 3478 | alloca_adjust = (unsigned) (frame_addr - (sp + offset)); |
29639122 JB |
3479 | if (alloca_adjust > 0) |
3480 | { | |
025bb325 | 3481 | /* FP > SP + frame_size. This may be because of |
29639122 JB |
3482 | an alloca or somethings similar. Fix sp to |
3483 | "pre-alloca" value, and try again. */ | |
3484 | sp += alloca_adjust; | |
3485 | /* Need to reset the status of all registers. Otherwise, | |
3486 | we will hit a guard that prevents the new address | |
3487 | for each register to be recomputed during the second | |
3488 | pass. */ | |
74ed0bb4 | 3489 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
3490 | goto restart; |
3491 | } | |
3492 | } | |
3493 | } | |
3494 | /* move $30,$sp. With different versions of gas this will be either | |
3495 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
3496 | Accept any one of these. */ | |
3497 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
3498 | { | |
3499 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
b8a22b94 | 3500 | if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
3501 | { |
3502 | unsigned alloca_adjust; | |
c906108c | 3503 | |
29639122 | 3504 | frame_reg = 30; |
b8a22b94 DJ |
3505 | frame_addr = get_frame_register_signed |
3506 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 3507 | |
29639122 JB |
3508 | alloca_adjust = (unsigned) (frame_addr - sp); |
3509 | if (alloca_adjust > 0) | |
3510 | { | |
025bb325 | 3511 | /* FP > SP + frame_size. This may be because of |
29639122 JB |
3512 | an alloca or somethings similar. Fix sp to |
3513 | "pre-alloca" value, and try again. */ | |
3514 | sp = frame_addr; | |
3515 | /* Need to reset the status of all registers. Otherwise, | |
3516 | we will hit a guard that prevents the new address | |
3517 | for each register to be recomputed during the second | |
3518 | pass. */ | |
74ed0bb4 | 3519 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
3520 | goto restart; |
3521 | } | |
3522 | } | |
3523 | } | |
7d1e6fb8 KB |
3524 | else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */ |
3525 | && !regsize_is_64_bits) | |
29639122 | 3526 | { |
eaa6a9a4 | 3527 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
3528 | } |
3529 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | |
3530 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ | |
3531 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | |
3532 | || high_word == 0x3c1c /* lui $gp,n */ | |
3533 | || high_word == 0x279c /* addiu $gp,$gp,n */ | |
3534 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
3535 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | |
3536 | ) | |
19080931 MR |
3537 | { |
3538 | /* These instructions are part of the prologue, but we don't | |
3539 | need to do anything special to handle them. */ | |
3540 | } | |
29639122 JB |
3541 | /* The instructions below load $at or $t0 with an immediate |
3542 | value in preparation for a stack adjustment via | |
025bb325 | 3543 | subu $sp,$sp,[$at,$t0]. These instructions could also |
29639122 JB |
3544 | initialize a local variable, so we accept them only before |
3545 | a stack adjustment instruction was seen. */ | |
3546 | else if (!seen_sp_adjust | |
ab50adb6 | 3547 | && !prev_delay_slot |
19080931 MR |
3548 | && (high_word == 0x3c01 /* lui $at,n */ |
3549 | || high_word == 0x3c08 /* lui $t0,n */ | |
3550 | || high_word == 0x3421 /* ori $at,$at,n */ | |
3551 | || high_word == 0x3508 /* ori $t0,$t0,n */ | |
3552 | || high_word == 0x3401 /* ori $at,$zero,n */ | |
3553 | || high_word == 0x3408 /* ori $t0,$zero,n */ | |
3554 | )) | |
3555 | { | |
ab50adb6 | 3556 | load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ |
19080931 | 3557 | } |
ab50adb6 MR |
3558 | /* Check for branches and jumps. The instruction in the delay |
3559 | slot can be a part of the prologue, so move forward once more. */ | |
3560 | else if (mips32_instruction_has_delay_slot (gdbarch, inst)) | |
3561 | { | |
3562 | in_delay_slot = 1; | |
3563 | } | |
3564 | /* This instruction is not an instruction typically found | |
3565 | in a prologue, so we must have reached the end of the | |
3566 | prologue. */ | |
29639122 | 3567 | else |
19080931 | 3568 | { |
ab50adb6 | 3569 | this_non_prologue_insn = 1; |
19080931 | 3570 | } |
db5f024e | 3571 | |
ab50adb6 MR |
3572 | non_prologue_insns += this_non_prologue_insn; |
3573 | ||
3574 | /* A jump or branch, or enough non-prologue insns seen? If so, | |
3575 | then we must have reached the end of the prologue by now. */ | |
3576 | if (prev_delay_slot || non_prologue_insns > 1) | |
db5f024e | 3577 | break; |
ab50adb6 MR |
3578 | |
3579 | prev_non_prologue_insn = this_non_prologue_insn; | |
3580 | prev_delay_slot = in_delay_slot; | |
3581 | prev_pc = cur_pc; | |
a4b8ebc8 | 3582 | } |
c906108c | 3583 | |
29639122 JB |
3584 | if (this_cache != NULL) |
3585 | { | |
3586 | this_cache->base = | |
b8a22b94 DJ |
3587 | (get_frame_register_signed (this_frame, |
3588 | gdbarch_num_regs (gdbarch) + frame_reg) | |
29639122 JB |
3589 | + frame_offset); |
3590 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of | |
3591 | this assignment below, eventually. But it's still needed | |
3592 | for now. */ | |
72a155b4 UW |
3593 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
3594 | + mips_regnum (gdbarch)->pc] | |
3595 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) | |
f57d151a | 3596 | + MIPS_RA_REGNUM]; |
29639122 | 3597 | } |
c906108c | 3598 | |
ab50adb6 MR |
3599 | /* Set end_prologue_addr to the address of the instruction immediately |
3600 | after the last one we scanned. Unless the last one looked like a | |
3601 | non-prologue instruction (and we looked ahead), in which case use | |
3602 | its address instead. */ | |
3603 | end_prologue_addr | |
3604 | = prev_non_prologue_insn || prev_delay_slot ? prev_pc : cur_pc; | |
29639122 JB |
3605 | |
3606 | /* In a frameless function, we might have incorrectly | |
025bb325 | 3607 | skipped some load immediate instructions. Undo the skipping |
29639122 JB |
3608 | if the load immediate was not followed by a stack adjustment. */ |
3609 | if (load_immediate_bytes && !seen_sp_adjust) | |
3610 | end_prologue_addr -= load_immediate_bytes; | |
c906108c | 3611 | |
29639122 | 3612 | return end_prologue_addr; |
c906108c SS |
3613 | } |
3614 | ||
29639122 JB |
3615 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
3616 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
3617 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
4cc0665f | 3618 | unwinder. Likewise microMIPS and the mips_micro unwinder. */ |
c906108c | 3619 | |
29639122 | 3620 | static struct mips_frame_cache * |
b8a22b94 | 3621 | mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache) |
c906108c | 3622 | { |
e17a4113 | 3623 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 3624 | struct mips_frame_cache *cache; |
c906108c | 3625 | |
29639122 | 3626 | if ((*this_cache) != NULL) |
19ba03f4 | 3627 | return (struct mips_frame_cache *) (*this_cache); |
c5aa993b | 3628 | |
29639122 JB |
3629 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
3630 | (*this_cache) = cache; | |
b8a22b94 | 3631 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
c5aa993b | 3632 | |
29639122 JB |
3633 | /* Analyze the function prologue. */ |
3634 | { | |
b8a22b94 | 3635 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 3636 | CORE_ADDR start_addr; |
c906108c | 3637 | |
29639122 JB |
3638 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
3639 | if (start_addr == 0) | |
e17a4113 | 3640 | start_addr = heuristic_proc_start (gdbarch, pc); |
29639122 JB |
3641 | /* We can't analyze the prologue if we couldn't find the begining |
3642 | of the function. */ | |
3643 | if (start_addr == 0) | |
3644 | return cache; | |
c5aa993b | 3645 | |
19ba03f4 SM |
3646 | mips32_scan_prologue (gdbarch, start_addr, pc, this_frame, |
3647 | (struct mips_frame_cache *) *this_cache); | |
29639122 JB |
3648 | } |
3649 | ||
3e8c568d | 3650 | /* gdbarch_sp_regnum contains the value and not the address. */ |
f57d151a | 3651 | trad_frame_set_value (cache->saved_regs, |
e17a4113 | 3652 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
f57d151a | 3653 | cache->base); |
c5aa993b | 3654 | |
19ba03f4 | 3655 | return (struct mips_frame_cache *) (*this_cache); |
c906108c SS |
3656 | } |
3657 | ||
29639122 | 3658 | static void |
b8a22b94 | 3659 | mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 | 3660 | struct frame_id *this_id) |
c906108c | 3661 | { |
b8a22b94 | 3662 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 3663 | this_cache); |
21327321 DJ |
3664 | /* This marks the outermost frame. */ |
3665 | if (info->base == 0) | |
3666 | return; | |
b8a22b94 | 3667 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
29639122 | 3668 | } |
c906108c | 3669 | |
b8a22b94 DJ |
3670 | static struct value * |
3671 | mips_insn32_frame_prev_register (struct frame_info *this_frame, | |
3672 | void **this_cache, int regnum) | |
29639122 | 3673 | { |
b8a22b94 | 3674 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 3675 | this_cache); |
b8a22b94 DJ |
3676 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
3677 | } | |
3678 | ||
3679 | static int | |
3680 | mips_insn32_frame_sniffer (const struct frame_unwind *self, | |
3681 | struct frame_info *this_frame, void **this_cache) | |
3682 | { | |
3683 | CORE_ADDR pc = get_frame_pc (this_frame); | |
4cc0665f | 3684 | if (mips_pc_is_mips (pc)) |
b8a22b94 DJ |
3685 | return 1; |
3686 | return 0; | |
c906108c SS |
3687 | } |
3688 | ||
29639122 JB |
3689 | static const struct frame_unwind mips_insn32_frame_unwind = |
3690 | { | |
3691 | NORMAL_FRAME, | |
8fbca658 | 3692 | default_frame_unwind_stop_reason, |
29639122 | 3693 | mips_insn32_frame_this_id, |
b8a22b94 DJ |
3694 | mips_insn32_frame_prev_register, |
3695 | NULL, | |
3696 | mips_insn32_frame_sniffer | |
29639122 | 3697 | }; |
c906108c | 3698 | |
1c645fec | 3699 | static CORE_ADDR |
b8a22b94 | 3700 | mips_insn32_frame_base_address (struct frame_info *this_frame, |
29639122 | 3701 | void **this_cache) |
c906108c | 3702 | { |
b8a22b94 | 3703 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 JB |
3704 | this_cache); |
3705 | return info->base; | |
3706 | } | |
c906108c | 3707 | |
29639122 JB |
3708 | static const struct frame_base mips_insn32_frame_base = |
3709 | { | |
3710 | &mips_insn32_frame_unwind, | |
3711 | mips_insn32_frame_base_address, | |
3712 | mips_insn32_frame_base_address, | |
3713 | mips_insn32_frame_base_address | |
3714 | }; | |
1c645fec | 3715 | |
29639122 | 3716 | static const struct frame_base * |
b8a22b94 | 3717 | mips_insn32_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 3718 | { |
b8a22b94 | 3719 | CORE_ADDR pc = get_frame_pc (this_frame); |
4cc0665f | 3720 | if (mips_pc_is_mips (pc)) |
29639122 | 3721 | return &mips_insn32_frame_base; |
a65bbe44 | 3722 | else |
29639122 JB |
3723 | return NULL; |
3724 | } | |
a65bbe44 | 3725 | |
29639122 | 3726 | static struct trad_frame_cache * |
b8a22b94 | 3727 | mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache) |
29639122 JB |
3728 | { |
3729 | CORE_ADDR pc; | |
3730 | CORE_ADDR start_addr; | |
3731 | CORE_ADDR stack_addr; | |
3732 | struct trad_frame_cache *this_trad_cache; | |
b8a22b94 DJ |
3733 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
3734 | int num_regs = gdbarch_num_regs (gdbarch); | |
c906108c | 3735 | |
29639122 | 3736 | if ((*this_cache) != NULL) |
19ba03f4 | 3737 | return (struct trad_frame_cache *) (*this_cache); |
b8a22b94 | 3738 | this_trad_cache = trad_frame_cache_zalloc (this_frame); |
29639122 | 3739 | (*this_cache) = this_trad_cache; |
1c645fec | 3740 | |
29639122 | 3741 | /* The return address is in the link register. */ |
3e8c568d | 3742 | trad_frame_set_reg_realreg (this_trad_cache, |
72a155b4 | 3743 | gdbarch_pc_regnum (gdbarch), |
b8a22b94 | 3744 | num_regs + MIPS_RA_REGNUM); |
1c645fec | 3745 | |
29639122 JB |
3746 | /* Frame ID, since it's a frameless / stackless function, no stack |
3747 | space is allocated and SP on entry is the current SP. */ | |
b8a22b94 | 3748 | pc = get_frame_pc (this_frame); |
29639122 | 3749 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
b8a22b94 DJ |
3750 | stack_addr = get_frame_register_signed (this_frame, |
3751 | num_regs + MIPS_SP_REGNUM); | |
aa6c981f | 3752 | trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr)); |
1c645fec | 3753 | |
29639122 JB |
3754 | /* Assume that the frame's base is the same as the |
3755 | stack-pointer. */ | |
3756 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
c906108c | 3757 | |
29639122 JB |
3758 | return this_trad_cache; |
3759 | } | |
c906108c | 3760 | |
29639122 | 3761 | static void |
b8a22b94 | 3762 | mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 JB |
3763 | struct frame_id *this_id) |
3764 | { | |
3765 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 3766 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
3767 | trad_frame_get_id (this_trad_cache, this_id); |
3768 | } | |
c906108c | 3769 | |
b8a22b94 DJ |
3770 | static struct value * |
3771 | mips_stub_frame_prev_register (struct frame_info *this_frame, | |
3772 | void **this_cache, int regnum) | |
29639122 JB |
3773 | { |
3774 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 DJ |
3775 | = mips_stub_frame_cache (this_frame, this_cache); |
3776 | return trad_frame_get_register (this_trad_cache, this_frame, regnum); | |
29639122 | 3777 | } |
c906108c | 3778 | |
b8a22b94 DJ |
3779 | static int |
3780 | mips_stub_frame_sniffer (const struct frame_unwind *self, | |
3781 | struct frame_info *this_frame, void **this_cache) | |
29639122 | 3782 | { |
aa6c981f | 3783 | gdb_byte dummy[4]; |
b8a22b94 | 3784 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
7cbd4a93 | 3785 | struct bound_minimal_symbol msym; |
979b38e0 | 3786 | |
aa6c981f | 3787 | /* Use the stub unwinder for unreadable code. */ |
b8a22b94 DJ |
3788 | if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) |
3789 | return 1; | |
aa6c981f | 3790 | |
3e5d3a5a | 3791 | if (in_plt_section (pc) || in_mips_stubs_section (pc)) |
b8a22b94 | 3792 | return 1; |
979b38e0 | 3793 | |
db5f024e DJ |
3794 | /* Calling a PIC function from a non-PIC function passes through a |
3795 | stub. The stub for foo is named ".pic.foo". */ | |
3796 | msym = lookup_minimal_symbol_by_pc (pc); | |
7cbd4a93 | 3797 | if (msym.minsym != NULL |
efd66ac6 | 3798 | && MSYMBOL_LINKAGE_NAME (msym.minsym) != NULL |
61012eef | 3799 | && startswith (MSYMBOL_LINKAGE_NAME (msym.minsym), ".pic.")) |
db5f024e DJ |
3800 | return 1; |
3801 | ||
b8a22b94 | 3802 | return 0; |
29639122 | 3803 | } |
c906108c | 3804 | |
b8a22b94 DJ |
3805 | static const struct frame_unwind mips_stub_frame_unwind = |
3806 | { | |
3807 | NORMAL_FRAME, | |
8fbca658 | 3808 | default_frame_unwind_stop_reason, |
b8a22b94 DJ |
3809 | mips_stub_frame_this_id, |
3810 | mips_stub_frame_prev_register, | |
3811 | NULL, | |
3812 | mips_stub_frame_sniffer | |
3813 | }; | |
3814 | ||
29639122 | 3815 | static CORE_ADDR |
b8a22b94 | 3816 | mips_stub_frame_base_address (struct frame_info *this_frame, |
29639122 JB |
3817 | void **this_cache) |
3818 | { | |
3819 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 3820 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
3821 | return trad_frame_get_this_base (this_trad_cache); |
3822 | } | |
0fce0821 | 3823 | |
29639122 JB |
3824 | static const struct frame_base mips_stub_frame_base = |
3825 | { | |
3826 | &mips_stub_frame_unwind, | |
3827 | mips_stub_frame_base_address, | |
3828 | mips_stub_frame_base_address, | |
3829 | mips_stub_frame_base_address | |
3830 | }; | |
3831 | ||
3832 | static const struct frame_base * | |
b8a22b94 | 3833 | mips_stub_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 3834 | { |
b8a22b94 | 3835 | if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL)) |
29639122 JB |
3836 | return &mips_stub_frame_base; |
3837 | else | |
3838 | return NULL; | |
3839 | } | |
3840 | ||
29639122 | 3841 | /* mips_addr_bits_remove - remove useless address bits */ |
65596487 | 3842 | |
29639122 | 3843 | static CORE_ADDR |
24568a2c | 3844 | mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) |
65596487 | 3845 | { |
24568a2c | 3846 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
930bd0e0 | 3847 | |
29639122 JB |
3848 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) |
3849 | /* This hack is a work-around for existing boards using PMON, the | |
3850 | simulator, and any other 64-bit targets that doesn't have true | |
3851 | 64-bit addressing. On these targets, the upper 32 bits of | |
3852 | addresses are ignored by the hardware. Thus, the PC or SP are | |
3853 | likely to have been sign extended to all 1s by instruction | |
3854 | sequences that load 32-bit addresses. For example, a typical | |
3855 | piece of code that loads an address is this: | |
65596487 | 3856 | |
29639122 JB |
3857 | lui $r2, <upper 16 bits> |
3858 | ori $r2, <lower 16 bits> | |
65596487 | 3859 | |
29639122 JB |
3860 | But the lui sign-extends the value such that the upper 32 bits |
3861 | may be all 1s. The workaround is simply to mask off these | |
3862 | bits. In the future, gcc may be changed to support true 64-bit | |
3863 | addressing, and this masking will have to be disabled. */ | |
3864 | return addr &= 0xffffffffUL; | |
3865 | else | |
3866 | return addr; | |
65596487 JB |
3867 | } |
3868 | ||
3d5f6d12 DJ |
3869 | |
3870 | /* Checks for an atomic sequence of instructions beginning with a LL/LLD | |
3871 | instruction and ending with a SC/SCD instruction. If such a sequence | |
3872 | is found, attempt to step through it. A breakpoint is placed at the end of | |
3873 | the sequence. */ | |
3874 | ||
4cc0665f MR |
3875 | /* Instructions used during single-stepping of atomic sequences, standard |
3876 | ISA version. */ | |
3877 | #define LL_OPCODE 0x30 | |
3878 | #define LLD_OPCODE 0x34 | |
3879 | #define SC_OPCODE 0x38 | |
3880 | #define SCD_OPCODE 0x3c | |
3881 | ||
a0ff9e1a | 3882 | static std::vector<CORE_ADDR> |
93f9a11f | 3883 | mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) |
3d5f6d12 DJ |
3884 | { |
3885 | CORE_ADDR breaks[2] = {-1, -1}; | |
3886 | CORE_ADDR loc = pc; | |
3887 | CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ | |
4cc0665f | 3888 | ULONGEST insn; |
3d5f6d12 DJ |
3889 | int insn_count; |
3890 | int index; | |
3891 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
3892 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
3893 | ||
4cc0665f | 3894 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); |
3d5f6d12 DJ |
3895 | /* Assume all atomic sequences start with a ll/lld instruction. */ |
3896 | if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE) | |
a0ff9e1a | 3897 | return {}; |
3d5f6d12 DJ |
3898 | |
3899 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" | |
3900 | instructions. */ | |
3901 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
3902 | { | |
3903 | int is_branch = 0; | |
3904 | loc += MIPS_INSN32_SIZE; | |
4cc0665f | 3905 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); |
3d5f6d12 DJ |
3906 | |
3907 | /* Assume that there is at most one branch in the atomic | |
3908 | sequence. If a branch is found, put a breakpoint in its | |
3909 | destination address. */ | |
3910 | switch (itype_op (insn)) | |
3911 | { | |
3912 | case 0: /* SPECIAL */ | |
3913 | if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */ | |
a0ff9e1a | 3914 | return {}; /* fallback to the standard single-step code. */ |
3d5f6d12 DJ |
3915 | break; |
3916 | case 1: /* REGIMM */ | |
a385295e MR |
3917 | is_branch = ((itype_rt (insn) & 0xc) == 0 /* B{LT,GE}Z* */ |
3918 | || ((itype_rt (insn) & 0x1e) == 0 | |
3919 | && itype_rs (insn) == 0)); /* BPOSGE* */ | |
3d5f6d12 DJ |
3920 | break; |
3921 | case 2: /* J */ | |
3922 | case 3: /* JAL */ | |
a0ff9e1a | 3923 | return {}; /* fallback to the standard single-step code. */ |
3d5f6d12 DJ |
3924 | case 4: /* BEQ */ |
3925 | case 5: /* BNE */ | |
3926 | case 6: /* BLEZ */ | |
3927 | case 7: /* BGTZ */ | |
3928 | case 20: /* BEQL */ | |
3929 | case 21: /* BNEL */ | |
3930 | case 22: /* BLEZL */ | |
3931 | case 23: /* BGTTL */ | |
3932 | is_branch = 1; | |
3933 | break; | |
3934 | case 17: /* COP1 */ | |
a385295e MR |
3935 | is_branch = ((itype_rs (insn) == 9 || itype_rs (insn) == 10) |
3936 | && (itype_rt (insn) & 0x2) == 0); | |
3937 | if (is_branch) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */ | |
3938 | break; | |
3939 | /* Fall through. */ | |
3d5f6d12 DJ |
3940 | case 18: /* COP2 */ |
3941 | case 19: /* COP3 */ | |
3942 | is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */ | |
3943 | break; | |
3944 | } | |
3945 | if (is_branch) | |
3946 | { | |
3947 | branch_bp = loc + mips32_relative_offset (insn) + 4; | |
3948 | if (last_breakpoint >= 1) | |
a0ff9e1a SM |
3949 | return {}; /* More than one branch found, fallback to the |
3950 | standard single-step code. */ | |
3d5f6d12 DJ |
3951 | breaks[1] = branch_bp; |
3952 | last_breakpoint++; | |
3953 | } | |
3954 | ||
3955 | if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE) | |
3956 | break; | |
3957 | } | |
3958 | ||
3959 | /* Assume that the atomic sequence ends with a sc/scd instruction. */ | |
3960 | if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE) | |
a0ff9e1a | 3961 | return {}; |
3d5f6d12 DJ |
3962 | |
3963 | loc += MIPS_INSN32_SIZE; | |
3964 | ||
3965 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
3966 | breaks[0] = loc; | |
3967 | ||
3968 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
025bb325 | 3969 | placed (branch instruction's destination) in the atomic sequence. */ |
3d5f6d12 DJ |
3970 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) |
3971 | last_breakpoint = 0; | |
3972 | ||
a0ff9e1a SM |
3973 | std::vector<CORE_ADDR> next_pcs; |
3974 | ||
3d5f6d12 DJ |
3975 | /* Effectively inserts the breakpoints. */ |
3976 | for (index = 0; index <= last_breakpoint; index++) | |
a0ff9e1a | 3977 | next_pcs.push_back (breaks[index]); |
3d5f6d12 | 3978 | |
93f9a11f | 3979 | return next_pcs; |
3d5f6d12 DJ |
3980 | } |
3981 | ||
a0ff9e1a | 3982 | static std::vector<CORE_ADDR> |
4cc0665f | 3983 | micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch, |
4cc0665f MR |
3984 | CORE_ADDR pc) |
3985 | { | |
3986 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
3987 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
3988 | CORE_ADDR breaks[2] = {-1, -1}; | |
4b844a38 AT |
3989 | CORE_ADDR branch_bp = 0; /* Breakpoint at branch instruction's |
3990 | destination. */ | |
4cc0665f MR |
3991 | CORE_ADDR loc = pc; |
3992 | int sc_found = 0; | |
3993 | ULONGEST insn; | |
3994 | int insn_count; | |
3995 | int index; | |
3996 | ||
3997 | /* Assume all atomic sequences start with a ll/lld instruction. */ | |
3998 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); | |
3999 | if (micromips_op (insn) != 0x18) /* POOL32C: bits 011000 */ | |
a0ff9e1a | 4000 | return {}; |
4cc0665f MR |
4001 | loc += MIPS_INSN16_SIZE; |
4002 | insn <<= 16; | |
4003 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); | |
4004 | if ((b12s4_op (insn) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */ | |
a0ff9e1a | 4005 | return {}; |
4cc0665f MR |
4006 | loc += MIPS_INSN16_SIZE; |
4007 | ||
4008 | /* Assume all atomic sequences end with an sc/scd instruction. Assume | |
4009 | that no atomic sequence is longer than "atomic_sequence_length" | |
4010 | instructions. */ | |
4011 | for (insn_count = 0; | |
4012 | !sc_found && insn_count < atomic_sequence_length; | |
4013 | ++insn_count) | |
4014 | { | |
4015 | int is_branch = 0; | |
4016 | ||
4017 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); | |
4018 | loc += MIPS_INSN16_SIZE; | |
4019 | ||
4020 | /* Assume that there is at most one conditional branch in the | |
4021 | atomic sequence. If a branch is found, put a breakpoint in | |
4022 | its destination address. */ | |
4023 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
4024 | { | |
4cc0665f MR |
4025 | /* 32-bit instructions. */ |
4026 | case 2 * MIPS_INSN16_SIZE: | |
4027 | switch (micromips_op (insn)) | |
4028 | { | |
4029 | case 0x10: /* POOL32I: bits 010000 */ | |
4030 | if ((b5s5_op (insn) & 0x18) != 0x0 | |
4031 | /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */ | |
4032 | /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */ | |
4033 | && (b5s5_op (insn) & 0x1d) != 0x11 | |
4034 | /* BLTZALS, BGEZALS: bits 010000 100x1 */ | |
4035 | && ((b5s5_op (insn) & 0x1e) != 0x14 | |
4036 | || (insn & 0x3) != 0x0) | |
4037 | /* BC2F, BC2T: bits 010000 1010x xxx00 */ | |
4038 | && (b5s5_op (insn) & 0x1e) != 0x1a | |
4039 | /* BPOSGE64, BPOSGE32: bits 010000 1101x */ | |
4040 | && ((b5s5_op (insn) & 0x1e) != 0x1c | |
4041 | || (insn & 0x3) != 0x0) | |
4042 | /* BC1F, BC1T: bits 010000 1110x xxx00 */ | |
4043 | && ((b5s5_op (insn) & 0x1c) != 0x1c | |
4044 | || (insn & 0x3) != 0x1)) | |
4045 | /* BC1ANY*: bits 010000 111xx xxx01 */ | |
4046 | break; | |
4047 | /* Fall through. */ | |
4048 | ||
4049 | case 0x25: /* BEQ: bits 100101 */ | |
4050 | case 0x2d: /* BNE: bits 101101 */ | |
4051 | insn <<= 16; | |
4052 | insn |= mips_fetch_instruction (gdbarch, | |
4053 | ISA_MICROMIPS, loc, NULL); | |
4054 | branch_bp = (loc + MIPS_INSN16_SIZE | |
4055 | + micromips_relative_offset16 (insn)); | |
4056 | is_branch = 1; | |
4057 | break; | |
4058 | ||
4059 | case 0x00: /* POOL32A: bits 000000 */ | |
4060 | insn <<= 16; | |
4061 | insn |= mips_fetch_instruction (gdbarch, | |
4062 | ISA_MICROMIPS, loc, NULL); | |
4063 | if (b0s6_op (insn) != 0x3c | |
4064 | /* POOL32Axf: bits 000000 ... 111100 */ | |
4065 | || (b6s10_ext (insn) & 0x2bf) != 0x3c) | |
4066 | /* JALR, JALR.HB: 000000 000x111100 111100 */ | |
4067 | /* JALRS, JALRS.HB: 000000 010x111100 111100 */ | |
4068 | break; | |
4069 | /* Fall through. */ | |
4070 | ||
4071 | case 0x1d: /* JALS: bits 011101 */ | |
4072 | case 0x35: /* J: bits 110101 */ | |
4073 | case 0x3d: /* JAL: bits 111101 */ | |
4074 | case 0x3c: /* JALX: bits 111100 */ | |
a0ff9e1a | 4075 | return {}; /* Fall back to the standard single-step code. */ |
4cc0665f MR |
4076 | |
4077 | case 0x18: /* POOL32C: bits 011000 */ | |
4078 | if ((b12s4_op (insn) & 0xb) == 0xb) | |
4079 | /* SC, SCD: bits 011000 1x11 */ | |
4080 | sc_found = 1; | |
4081 | break; | |
4082 | } | |
4083 | loc += MIPS_INSN16_SIZE; | |
4084 | break; | |
4085 | ||
4086 | /* 16-bit instructions. */ | |
4087 | case MIPS_INSN16_SIZE: | |
4088 | switch (micromips_op (insn)) | |
4089 | { | |
4090 | case 0x23: /* BEQZ16: bits 100011 */ | |
4091 | case 0x2b: /* BNEZ16: bits 101011 */ | |
4092 | branch_bp = loc + micromips_relative_offset7 (insn); | |
4093 | is_branch = 1; | |
4094 | break; | |
4095 | ||
4096 | case 0x11: /* POOL16C: bits 010001 */ | |
4097 | if ((b5s5_op (insn) & 0x1c) != 0xc | |
4098 | /* JR16, JRC, JALR16, JALRS16: 010001 011xx */ | |
4099 | && b5s5_op (insn) != 0x18) | |
4100 | /* JRADDIUSP: bits 010001 11000 */ | |
4101 | break; | |
a0ff9e1a | 4102 | return {}; /* Fall back to the standard single-step code. */ |
4cc0665f MR |
4103 | |
4104 | case 0x33: /* B16: bits 110011 */ | |
a0ff9e1a | 4105 | return {}; /* Fall back to the standard single-step code. */ |
4cc0665f MR |
4106 | } |
4107 | break; | |
4108 | } | |
4109 | if (is_branch) | |
4110 | { | |
4111 | if (last_breakpoint >= 1) | |
a0ff9e1a SM |
4112 | return {}; /* More than one branch found, fallback to the |
4113 | standard single-step code. */ | |
4cc0665f MR |
4114 | breaks[1] = branch_bp; |
4115 | last_breakpoint++; | |
4116 | } | |
4117 | } | |
4118 | if (!sc_found) | |
a0ff9e1a | 4119 | return {}; |
4cc0665f MR |
4120 | |
4121 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
4122 | breaks[0] = loc; | |
4123 | ||
4124 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
4125 | placed (branch instruction's destination) in the atomic sequence */ | |
4126 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) | |
4127 | last_breakpoint = 0; | |
4128 | ||
a0ff9e1a SM |
4129 | std::vector<CORE_ADDR> next_pcs; |
4130 | ||
4cc0665f MR |
4131 | /* Effectively inserts the breakpoints. */ |
4132 | for (index = 0; index <= last_breakpoint; index++) | |
a0ff9e1a | 4133 | next_pcs.push_back (breaks[index]); |
4cc0665f | 4134 | |
93f9a11f | 4135 | return next_pcs; |
4cc0665f MR |
4136 | } |
4137 | ||
a0ff9e1a | 4138 | static std::vector<CORE_ADDR> |
93f9a11f | 4139 | deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) |
4cc0665f MR |
4140 | { |
4141 | if (mips_pc_is_mips (pc)) | |
93f9a11f | 4142 | return mips_deal_with_atomic_sequence (gdbarch, pc); |
4cc0665f | 4143 | else if (mips_pc_is_micromips (gdbarch, pc)) |
93f9a11f | 4144 | return micromips_deal_with_atomic_sequence (gdbarch, pc); |
4cc0665f | 4145 | else |
a0ff9e1a | 4146 | return {}; |
4cc0665f MR |
4147 | } |
4148 | ||
29639122 JB |
4149 | /* mips_software_single_step() is called just before we want to resume |
4150 | the inferior, if we want to single-step it but there is no hardware | |
4151 | or kernel single-step support (MIPS on GNU/Linux for example). We find | |
e0cd558a | 4152 | the target of the coming instruction and breakpoint it. */ |
29639122 | 4153 | |
a0ff9e1a | 4154 | std::vector<CORE_ADDR> |
f5ea389a | 4155 | mips_software_single_step (struct regcache *regcache) |
c906108c | 4156 | { |
ac7936df | 4157 | struct gdbarch *gdbarch = regcache->arch (); |
8181d85f | 4158 | CORE_ADDR pc, next_pc; |
65596487 | 4159 | |
7113a196 | 4160 | pc = regcache_read_pc (regcache); |
a0ff9e1a SM |
4161 | std::vector<CORE_ADDR> next_pcs = deal_with_atomic_sequence (gdbarch, pc); |
4162 | ||
4163 | if (!next_pcs.empty ()) | |
93f9a11f | 4164 | return next_pcs; |
3d5f6d12 | 4165 | |
7113a196 | 4166 | next_pc = mips_next_pc (regcache, pc); |
e6590a1b | 4167 | |
a0ff9e1a | 4168 | return {next_pc}; |
29639122 | 4169 | } |
a65bbe44 | 4170 | |
29639122 | 4171 | /* Test whether the PC points to the return instruction at the |
025bb325 | 4172 | end of a function. */ |
65596487 | 4173 | |
29639122 | 4174 | static int |
e17a4113 | 4175 | mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 | 4176 | { |
6321c22a MR |
4177 | ULONGEST insn; |
4178 | ULONGEST hint; | |
4179 | ||
4180 | /* This used to check for MIPS16, but this piece of code is never | |
4cc0665f MR |
4181 | called for MIPS16 functions. And likewise microMIPS ones. */ |
4182 | gdb_assert (mips_pc_is_mips (pc)); | |
6321c22a | 4183 | |
4cc0665f | 4184 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
6321c22a MR |
4185 | hint = 0x7c0; |
4186 | return (insn & ~hint) == 0x3e00008; /* jr(.hb) $ra */ | |
29639122 | 4187 | } |
c906108c | 4188 | |
c906108c | 4189 | |
29639122 JB |
4190 | /* This fencepost looks highly suspicious to me. Removing it also |
4191 | seems suspicious as it could affect remote debugging across serial | |
4192 | lines. */ | |
c906108c | 4193 | |
29639122 | 4194 | static CORE_ADDR |
74ed0bb4 | 4195 | heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 JB |
4196 | { |
4197 | CORE_ADDR start_pc; | |
4198 | CORE_ADDR fence; | |
4199 | int instlen; | |
4200 | int seen_adjsp = 0; | |
d6b48e9c | 4201 | struct inferior *inf; |
65596487 | 4202 | |
74ed0bb4 | 4203 | pc = gdbarch_addr_bits_remove (gdbarch, pc); |
29639122 JB |
4204 | start_pc = pc; |
4205 | fence = start_pc - heuristic_fence_post; | |
4206 | if (start_pc == 0) | |
4207 | return 0; | |
65596487 | 4208 | |
44096aee | 4209 | if (heuristic_fence_post == -1 || fence < VM_MIN_ADDRESS) |
29639122 | 4210 | fence = VM_MIN_ADDRESS; |
65596487 | 4211 | |
4cc0665f | 4212 | instlen = mips_pc_is_mips (pc) ? MIPS_INSN32_SIZE : MIPS_INSN16_SIZE; |
98b4dd94 | 4213 | |
d6b48e9c PA |
4214 | inf = current_inferior (); |
4215 | ||
025bb325 | 4216 | /* Search back for previous return. */ |
29639122 JB |
4217 | for (start_pc -= instlen;; start_pc -= instlen) |
4218 | if (start_pc < fence) | |
4219 | { | |
4220 | /* It's not clear to me why we reach this point when | |
4221 | stop_soon, but with this test, at least we | |
4222 | don't print out warnings for every child forked (eg, on | |
4223 | decstation). 22apr93 rich@cygnus.com. */ | |
16c381f0 | 4224 | if (inf->control.stop_soon == NO_STOP_QUIETLY) |
29639122 JB |
4225 | { |
4226 | static int blurb_printed = 0; | |
98b4dd94 | 4227 | |
5af949e3 UW |
4228 | warning (_("GDB can't find the start of the function at %s."), |
4229 | paddress (gdbarch, pc)); | |
29639122 JB |
4230 | |
4231 | if (!blurb_printed) | |
4232 | { | |
4233 | /* This actually happens frequently in embedded | |
4234 | development, when you first connect to a board | |
4235 | and your stack pointer and pc are nowhere in | |
4236 | particular. This message needs to give people | |
4237 | in that situation enough information to | |
4238 | determine that it's no big deal. */ | |
4239 | printf_filtered ("\n\ | |
5af949e3 | 4240 | GDB is unable to find the start of the function at %s\n\ |
29639122 JB |
4241 | and thus can't determine the size of that function's stack frame.\n\ |
4242 | This means that GDB may be unable to access that stack frame, or\n\ | |
4243 | the frames below it.\n\ | |
4244 | This problem is most likely caused by an invalid program counter or\n\ | |
4245 | stack pointer.\n\ | |
4246 | However, if you think GDB should simply search farther back\n\ | |
5af949e3 | 4247 | from %s for code which looks like the beginning of a\n\ |
29639122 | 4248 | function, you can increase the range of the search using the `set\n\ |
5af949e3 UW |
4249 | heuristic-fence-post' command.\n", |
4250 | paddress (gdbarch, pc), paddress (gdbarch, pc)); | |
29639122 JB |
4251 | blurb_printed = 1; |
4252 | } | |
4253 | } | |
4254 | ||
4255 | return 0; | |
4256 | } | |
4cc0665f | 4257 | else if (mips_pc_is_mips16 (gdbarch, start_pc)) |
29639122 JB |
4258 | { |
4259 | unsigned short inst; | |
4260 | ||
4261 | /* On MIPS16, any one of the following is likely to be the | |
4262 | start of a function: | |
193774b3 MR |
4263 | extend save |
4264 | save | |
29639122 JB |
4265 | entry |
4266 | addiu sp,-n | |
4267 | daddiu sp,-n | |
025bb325 | 4268 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */ |
4cc0665f | 4269 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, start_pc, NULL); |
193774b3 MR |
4270 | if ((inst & 0xff80) == 0x6480) /* save */ |
4271 | { | |
4272 | if (start_pc - instlen >= fence) | |
4273 | { | |
4cc0665f MR |
4274 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, |
4275 | start_pc - instlen, NULL); | |
193774b3 MR |
4276 | if ((inst & 0xf800) == 0xf000) /* extend */ |
4277 | start_pc -= instlen; | |
4278 | } | |
4279 | break; | |
4280 | } | |
4281 | else if (((inst & 0xf81f) == 0xe809 | |
4282 | && (inst & 0x700) != 0x700) /* entry */ | |
4283 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
4284 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
4285 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
29639122 JB |
4286 | break; |
4287 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
4288 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
4289 | seen_adjsp = 1; | |
4290 | else | |
4291 | seen_adjsp = 0; | |
4292 | } | |
4cc0665f MR |
4293 | else if (mips_pc_is_micromips (gdbarch, start_pc)) |
4294 | { | |
4295 | ULONGEST insn; | |
4296 | int stop = 0; | |
4297 | long offset; | |
4298 | int dreg; | |
4299 | int sreg; | |
4300 | ||
4301 | /* On microMIPS, any one of the following is likely to be the | |
4302 | start of a function: | |
4303 | ADDIUSP -imm | |
4304 | (D)ADDIU $sp, -imm | |
4305 | LUI $gp, imm */ | |
4306 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
4307 | switch (micromips_op (insn)) | |
4308 | { | |
4309 | case 0xc: /* ADDIU: bits 001100 */ | |
4310 | case 0x17: /* DADDIU: bits 010111 */ | |
4311 | sreg = b0s5_reg (insn); | |
4312 | dreg = b5s5_reg (insn); | |
4313 | insn <<= 16; | |
4314 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, | |
4315 | pc + MIPS_INSN16_SIZE, NULL); | |
4316 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
4317 | if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM | |
4318 | /* (D)ADDIU $sp, imm */ | |
4319 | && offset < 0) | |
4320 | stop = 1; | |
4321 | break; | |
4322 | ||
4323 | case 0x10: /* POOL32I: bits 010000 */ | |
4324 | if (b5s5_op (insn) == 0xd | |
4325 | /* LUI: bits 010000 001101 */ | |
4326 | && b0s5_reg (insn >> 16) == 28) | |
4327 | /* LUI $gp, imm */ | |
4328 | stop = 1; | |
4329 | break; | |
4330 | ||
4331 | case 0x13: /* POOL16D: bits 010011 */ | |
4332 | if ((insn & 0x1) == 0x1) | |
4333 | /* ADDIUSP: bits 010011 1 */ | |
4334 | { | |
4335 | offset = micromips_decode_imm9 (b1s9_imm (insn)); | |
4336 | if (offset < 0) | |
4337 | /* ADDIUSP -imm */ | |
4338 | stop = 1; | |
4339 | } | |
4340 | else | |
4341 | /* ADDIUS5: bits 010011 0 */ | |
4342 | { | |
4343 | dreg = b5s5_reg (insn); | |
4344 | offset = (b1s4_imm (insn) ^ 8) - 8; | |
4345 | if (dreg == MIPS_SP_REGNUM && offset < 0) | |
4346 | /* ADDIUS5 $sp, -imm */ | |
4347 | stop = 1; | |
4348 | } | |
4349 | break; | |
4350 | } | |
4351 | if (stop) | |
4352 | break; | |
4353 | } | |
e17a4113 | 4354 | else if (mips_about_to_return (gdbarch, start_pc)) |
29639122 | 4355 | { |
4c7d22cb | 4356 | /* Skip return and its delay slot. */ |
95ac2dcf | 4357 | start_pc += 2 * MIPS_INSN32_SIZE; |
29639122 JB |
4358 | break; |
4359 | } | |
4360 | ||
4361 | return start_pc; | |
c906108c SS |
4362 | } |
4363 | ||
6c0d6680 DJ |
4364 | struct mips_objfile_private |
4365 | { | |
4366 | bfd_size_type size; | |
4367 | char *contents; | |
4368 | }; | |
4369 | ||
f09ded24 AC |
4370 | /* According to the current ABI, should the type be passed in a |
4371 | floating-point register (assuming that there is space)? When there | |
a1f5b845 | 4372 | is no FPU, FP are not even considered as possible candidates for |
f09ded24 | 4373 | FP registers and, consequently this returns false - forces FP |
025bb325 | 4374 | arguments into integer registers. */ |
f09ded24 AC |
4375 | |
4376 | static int | |
74ed0bb4 MD |
4377 | fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode, |
4378 | struct type *arg_type) | |
f09ded24 AC |
4379 | { |
4380 | return ((typecode == TYPE_CODE_FLT | |
74ed0bb4 | 4381 | || (MIPS_EABI (gdbarch) |
6d82d43b AC |
4382 | && (typecode == TYPE_CODE_STRUCT |
4383 | || typecode == TYPE_CODE_UNION) | |
f09ded24 | 4384 | && TYPE_NFIELDS (arg_type) == 1 |
b2d6f210 MS |
4385 | && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0))) |
4386 | == TYPE_CODE_FLT)) | |
74ed0bb4 | 4387 | && MIPS_FPU_TYPE(gdbarch) != MIPS_FPU_NONE); |
f09ded24 AC |
4388 | } |
4389 | ||
49e790b0 | 4390 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
025bb325 | 4391 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ |
49e790b0 DJ |
4392 | |
4393 | static int | |
4394 | mips_type_needs_double_align (struct type *type) | |
4395 | { | |
4396 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 4397 | |
49e790b0 DJ |
4398 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
4399 | return 1; | |
4400 | else if (typecode == TYPE_CODE_STRUCT) | |
4401 | { | |
4402 | if (TYPE_NFIELDS (type) < 1) | |
4403 | return 0; | |
4404 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
4405 | } | |
4406 | else if (typecode == TYPE_CODE_UNION) | |
4407 | { | |
361d1df0 | 4408 | int i, n; |
49e790b0 DJ |
4409 | |
4410 | n = TYPE_NFIELDS (type); | |
4411 | for (i = 0; i < n; i++) | |
4412 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
4413 | return 1; | |
4414 | return 0; | |
4415 | } | |
4416 | return 0; | |
4417 | } | |
4418 | ||
dc604539 AC |
4419 | /* Adjust the address downward (direction of stack growth) so that it |
4420 | is correctly aligned for a new stack frame. */ | |
4421 | static CORE_ADDR | |
4422 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
4423 | { | |
5b03f266 | 4424 | return align_down (addr, 16); |
dc604539 AC |
4425 | } |
4426 | ||
8ae38c14 | 4427 | /* Implement the "push_dummy_code" gdbarch method. */ |
2c76a0c7 JB |
4428 | |
4429 | static CORE_ADDR | |
4430 | mips_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
4431 | CORE_ADDR funaddr, struct value **args, | |
4432 | int nargs, struct type *value_type, | |
4433 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, | |
4434 | struct regcache *regcache) | |
4435 | { | |
2c76a0c7 | 4436 | static gdb_byte nop_insn[] = { 0, 0, 0, 0 }; |
2e81047f MR |
4437 | CORE_ADDR nop_addr; |
4438 | CORE_ADDR bp_slot; | |
2c76a0c7 JB |
4439 | |
4440 | /* Reserve enough room on the stack for our breakpoint instruction. */ | |
2e81047f MR |
4441 | bp_slot = sp - sizeof (nop_insn); |
4442 | ||
4443 | /* Return to microMIPS mode if calling microMIPS code to avoid | |
4444 | triggering an address error exception on processors that only | |
4445 | support microMIPS execution. */ | |
4446 | *bp_addr = (mips_pc_is_micromips (gdbarch, funaddr) | |
4447 | ? make_compact_addr (bp_slot) : bp_slot); | |
2c76a0c7 JB |
4448 | |
4449 | /* The breakpoint layer automatically adjusts the address of | |
4450 | breakpoints inserted in a branch delay slot. With enough | |
4451 | bad luck, the 4 bytes located just before our breakpoint | |
4452 | instruction could look like a branch instruction, and thus | |
4453 | trigger the adjustement, and break the function call entirely. | |
4454 | So, we reserve those 4 bytes and write a nop instruction | |
4455 | to prevent that from happening. */ | |
2e81047f | 4456 | nop_addr = bp_slot - sizeof (nop_insn); |
2c76a0c7 JB |
4457 | write_memory (nop_addr, nop_insn, sizeof (nop_insn)); |
4458 | sp = mips_frame_align (gdbarch, nop_addr); | |
4459 | ||
4460 | /* Inferior resumes at the function entry point. */ | |
4461 | *real_pc = funaddr; | |
4462 | ||
4463 | return sp; | |
4464 | } | |
4465 | ||
f7ab6ec6 | 4466 | static CORE_ADDR |
7d9b040b | 4467 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4468 | struct regcache *regcache, CORE_ADDR bp_addr, |
4469 | int nargs, struct value **args, CORE_ADDR sp, | |
4470 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
4471 | { |
4472 | int argreg; | |
4473 | int float_argreg; | |
4474 | int argnum; | |
4475 | int len = 0; | |
4476 | int stack_offset = 0; | |
e17a4113 | 4477 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 4478 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
b3464d03 | 4479 | int abi_regsize = mips_abi_regsize (gdbarch); |
c906108c | 4480 | |
25ab4790 AC |
4481 | /* For shared libraries, "t9" needs to point at the function |
4482 | address. */ | |
4c7d22cb | 4483 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
4484 | |
4485 | /* Set the return address register to point to the entry point of | |
4486 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 4487 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 4488 | |
c906108c | 4489 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
4490 | are properly aligned. The stack has to be at least 64-bit |
4491 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4492 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4493 | aligned, so we round to this widest known alignment. */ | |
4494 | ||
5b03f266 AC |
4495 | sp = align_down (sp, 16); |
4496 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 4497 | |
46e0f506 | 4498 | /* Now make space on the stack for the args. We allocate more |
c906108c | 4499 | than necessary for EABI, because the first few arguments are |
46e0f506 | 4500 | passed in registers, but that's OK. */ |
c906108c | 4501 | for (argnum = 0; argnum < nargs; argnum++) |
b3464d03 | 4502 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), abi_regsize); |
5b03f266 | 4503 | sp -= align_up (len, 16); |
c906108c | 4504 | |
9ace0497 | 4505 | if (mips_debug) |
6d82d43b | 4506 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
4507 | "mips_eabi_push_dummy_call: sp=%s allocated %ld\n", |
4508 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
9ace0497 | 4509 | |
c906108c | 4510 | /* Initialize the integer and float register pointers. */ |
4c7d22cb | 4511 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 4512 | float_argreg = mips_fpa0_regnum (gdbarch); |
c906108c | 4513 | |
46e0f506 | 4514 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 4515 | if (struct_return) |
9ace0497 AC |
4516 | { |
4517 | if (mips_debug) | |
4518 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
4519 | "mips_eabi_push_dummy_call: " |
4520 | "struct_return reg=%d %s\n", | |
5af949e3 | 4521 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 4522 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
9ace0497 | 4523 | } |
c906108c SS |
4524 | |
4525 | /* Now load as many as possible of the first arguments into | |
4526 | registers, and push the rest onto the stack. Loop thru args | |
4527 | from first to last. */ | |
4528 | for (argnum = 0; argnum < nargs; argnum++) | |
4529 | { | |
47a35522 | 4530 | const gdb_byte *val; |
b3464d03 PA |
4531 | /* This holds the address of structures that are passed by |
4532 | reference. */ | |
4533 | gdb_byte ref_valbuf[MAX_MIPS_ABI_REGSIZE]; | |
ea7c478f | 4534 | struct value *arg = args[argnum]; |
4991999e | 4535 | struct type *arg_type = check_typedef (value_type (arg)); |
c906108c SS |
4536 | int len = TYPE_LENGTH (arg_type); |
4537 | enum type_code typecode = TYPE_CODE (arg_type); | |
4538 | ||
9ace0497 AC |
4539 | if (mips_debug) |
4540 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4541 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 4542 | argnum + 1, len, (int) typecode); |
9ace0497 | 4543 | |
c906108c | 4544 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 4545 | reference. */ |
b3464d03 | 4546 | if (len > abi_regsize |
9ace0497 | 4547 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 4548 | { |
b3464d03 PA |
4549 | gdb_assert (abi_regsize <= ARRAY_SIZE (ref_valbuf)); |
4550 | store_unsigned_integer (ref_valbuf, abi_regsize, byte_order, | |
e17a4113 | 4551 | value_address (arg)); |
c906108c | 4552 | typecode = TYPE_CODE_PTR; |
b3464d03 PA |
4553 | len = abi_regsize; |
4554 | val = ref_valbuf; | |
9ace0497 AC |
4555 | if (mips_debug) |
4556 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
4557 | } |
4558 | else | |
47a35522 | 4559 | val = value_contents (arg); |
c906108c SS |
4560 | |
4561 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
4562 | even-numbered floating point register. Round the FP register |
4563 | up before the check to see if there are any FP registers | |
46e0f506 MS |
4564 | left. Non MIPS_EABI targets also pass the FP in the integer |
4565 | registers so also round up normal registers. */ | |
b3464d03 | 4566 | if (abi_regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type)) |
acdb74a0 AC |
4567 | { |
4568 | if ((float_argreg & 1)) | |
4569 | float_argreg++; | |
4570 | } | |
c906108c SS |
4571 | |
4572 | /* Floating point arguments passed in registers have to be | |
4573 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
4574 | are passed in register pairs; the even register gets |
4575 | the low word, and the odd register gets the high word. | |
4576 | On non-EABI processors, the first two floating point arguments are | |
4577 | also copied to general registers, because MIPS16 functions | |
4578 | don't use float registers for arguments. This duplication of | |
4579 | arguments in general registers can't hurt non-MIPS16 functions | |
4580 | because those registers are normally skipped. */ | |
1012bd0e EZ |
4581 | /* MIPS_EABI squeezes a struct that contains a single floating |
4582 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 4583 | stack. */ |
74ed0bb4 MD |
4584 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
4585 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
c906108c | 4586 | { |
6da397e0 KB |
4587 | /* EABI32 will pass doubles in consecutive registers, even on |
4588 | 64-bit cores. At one time, we used to check the size of | |
4589 | `float_argreg' to determine whether or not to pass doubles | |
4590 | in consecutive registers, but this is not sufficient for | |
4591 | making the ABI determination. */ | |
4592 | if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) | |
c906108c | 4593 | { |
72a155b4 | 4594 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 4595 | == BFD_ENDIAN_BIG ? 4 : 0; |
a8852dc5 | 4596 | long regval; |
c906108c SS |
4597 | |
4598 | /* Write the low word of the double to the even register(s). */ | |
a8852dc5 KB |
4599 | regval = extract_signed_integer (val + low_offset, |
4600 | 4, byte_order); | |
9ace0497 | 4601 | if (mips_debug) |
acdb74a0 | 4602 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 4603 | float_argreg, phex (regval, 4)); |
a8852dc5 | 4604 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
4605 | |
4606 | /* Write the high word of the double to the odd register(s). */ | |
a8852dc5 KB |
4607 | regval = extract_signed_integer (val + 4 - low_offset, |
4608 | 4, byte_order); | |
9ace0497 | 4609 | if (mips_debug) |
acdb74a0 | 4610 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 4611 | float_argreg, phex (regval, 4)); |
a8852dc5 | 4612 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
4613 | } |
4614 | else | |
4615 | { | |
4616 | /* This is a floating point value that fits entirely | |
4617 | in a single register. */ | |
53a5351d | 4618 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 4619 | above to ensure that it is even register aligned. */ |
a8852dc5 | 4620 | LONGEST regval = extract_signed_integer (val, len, byte_order); |
9ace0497 | 4621 | if (mips_debug) |
acdb74a0 | 4622 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 4623 | float_argreg, phex (regval, len)); |
a8852dc5 | 4624 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
4625 | } |
4626 | } | |
4627 | else | |
4628 | { | |
4629 | /* Copy the argument to general registers or the stack in | |
4630 | register-sized pieces. Large arguments are split between | |
4631 | registers and stack. */ | |
b3464d03 | 4632 | /* Note: structs whose size is not a multiple of abi_regsize |
1a69e1e4 | 4633 | are treated specially: Irix cc passes |
d5ac5a39 AC |
4634 | them in registers where gcc sometimes puts them on the |
4635 | stack. For maximum compatibility, we will put them in | |
4636 | both places. */ | |
b3464d03 | 4637 | int odd_sized_struct = (len > abi_regsize && len % abi_regsize != 0); |
46e0f506 | 4638 | |
f09ded24 | 4639 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 4640 | register are only written to memory. */ |
c906108c SS |
4641 | while (len > 0) |
4642 | { | |
ebafbe83 | 4643 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 4644 | int stack_used_p = 0; |
b3464d03 | 4645 | int partial_len = (len < abi_regsize ? len : abi_regsize); |
c906108c | 4646 | |
acdb74a0 AC |
4647 | if (mips_debug) |
4648 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4649 | partial_len); | |
4650 | ||
566f0f7a | 4651 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 4652 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
f09ded24 | 4653 | || odd_sized_struct |
74ed0bb4 | 4654 | || fp_register_arg_p (gdbarch, typecode, arg_type)) |
c906108c | 4655 | { |
c906108c | 4656 | /* Should shorter than int integer values be |
025bb325 | 4657 | promoted to int before being stored? */ |
c906108c | 4658 | int longword_offset = 0; |
9ace0497 | 4659 | CORE_ADDR addr; |
566f0f7a | 4660 | stack_used_p = 1; |
72a155b4 | 4661 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
7a292a7a | 4662 | { |
b3464d03 | 4663 | if (abi_regsize == 8 |
480d3dd2 AC |
4664 | && (typecode == TYPE_CODE_INT |
4665 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 4666 | || typecode == TYPE_CODE_FLT) && len <= 4) |
b3464d03 | 4667 | longword_offset = abi_regsize - len; |
480d3dd2 AC |
4668 | else if ((typecode == TYPE_CODE_STRUCT |
4669 | || typecode == TYPE_CODE_UNION) | |
b3464d03 PA |
4670 | && TYPE_LENGTH (arg_type) < abi_regsize) |
4671 | longword_offset = abi_regsize - len; | |
7a292a7a | 4672 | } |
c5aa993b | 4673 | |
9ace0497 AC |
4674 | if (mips_debug) |
4675 | { | |
5af949e3 UW |
4676 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
4677 | paddress (gdbarch, stack_offset)); | |
4678 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
4679 | paddress (gdbarch, longword_offset)); | |
9ace0497 | 4680 | } |
361d1df0 | 4681 | |
9ace0497 AC |
4682 | addr = sp + stack_offset + longword_offset; |
4683 | ||
4684 | if (mips_debug) | |
4685 | { | |
4686 | int i; | |
5af949e3 UW |
4687 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
4688 | paddress (gdbarch, addr)); | |
9ace0497 AC |
4689 | for (i = 0; i < partial_len; i++) |
4690 | { | |
6d82d43b | 4691 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 4692 | val[i] & 0xff); |
9ace0497 AC |
4693 | } |
4694 | } | |
4695 | write_memory (addr, val, partial_len); | |
c906108c SS |
4696 | } |
4697 | ||
f09ded24 AC |
4698 | /* Note!!! This is NOT an else clause. Odd sized |
4699 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 4700 | arguments will not. */ |
566f0f7a | 4701 | /* Write this portion of the argument to a general |
6d82d43b | 4702 | purpose register. */ |
74ed0bb4 MD |
4703 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch) |
4704 | && !fp_register_arg_p (gdbarch, typecode, arg_type)) | |
c906108c | 4705 | { |
6d82d43b | 4706 | LONGEST regval = |
a8852dc5 | 4707 | extract_signed_integer (val, partial_len, byte_order); |
c906108c | 4708 | |
9ace0497 | 4709 | if (mips_debug) |
acdb74a0 | 4710 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 4711 | argreg, |
b3464d03 | 4712 | phex (regval, abi_regsize)); |
a8852dc5 | 4713 | regcache_cooked_write_signed (regcache, argreg, regval); |
c906108c | 4714 | argreg++; |
c906108c | 4715 | } |
c5aa993b | 4716 | |
c906108c SS |
4717 | len -= partial_len; |
4718 | val += partial_len; | |
4719 | ||
b021a221 MS |
4720 | /* Compute the offset into the stack at which we will |
4721 | copy the next parameter. | |
566f0f7a | 4722 | |
566f0f7a | 4723 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 4724 | only needs to be adjusted when it has been used. */ |
c906108c | 4725 | |
46e0f506 | 4726 | if (stack_used_p) |
b3464d03 | 4727 | stack_offset += align_up (partial_len, abi_regsize); |
c906108c SS |
4728 | } |
4729 | } | |
9ace0497 AC |
4730 | if (mips_debug) |
4731 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
4732 | } |
4733 | ||
f10683bb | 4734 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4735 | |
0f71a2f6 JM |
4736 | /* Return adjusted stack pointer. */ |
4737 | return sp; | |
4738 | } | |
4739 | ||
a1f5b845 | 4740 | /* Determine the return value convention being used. */ |
6d82d43b | 4741 | |
9c8fdbfa | 4742 | static enum return_value_convention |
6a3a010b | 4743 | mips_eabi_return_value (struct gdbarch *gdbarch, struct value *function, |
9c8fdbfa | 4744 | struct type *type, struct regcache *regcache, |
47a35522 | 4745 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 4746 | { |
609ba780 JM |
4747 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4748 | int fp_return_type = 0; | |
4749 | int offset, regnum, xfer; | |
4750 | ||
9c8fdbfa AC |
4751 | if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
4752 | return RETURN_VALUE_STRUCT_CONVENTION; | |
609ba780 JM |
4753 | |
4754 | /* Floating point type? */ | |
4755 | if (tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4756 | { | |
4757 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
4758 | fp_return_type = 1; | |
4759 | /* Structs with a single field of float type | |
4760 | are returned in a floating point register. */ | |
4761 | if ((TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4762 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4763 | && TYPE_NFIELDS (type) == 1) | |
4764 | { | |
4765 | struct type *fieldtype = TYPE_FIELD_TYPE (type, 0); | |
4766 | ||
4767 | if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT) | |
4768 | fp_return_type = 1; | |
4769 | } | |
4770 | } | |
4771 | ||
4772 | if (fp_return_type) | |
4773 | { | |
4774 | /* A floating-point value belongs in the least significant part | |
4775 | of FP0/FP1. */ | |
4776 | if (mips_debug) | |
4777 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
4778 | regnum = mips_regnum (gdbarch)->fp0; | |
4779 | } | |
4780 | else | |
4781 | { | |
4782 | /* An integer value goes in V0/V1. */ | |
4783 | if (mips_debug) | |
4784 | fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n"); | |
4785 | regnum = MIPS_V0_REGNUM; | |
4786 | } | |
4787 | for (offset = 0; | |
4788 | offset < TYPE_LENGTH (type); | |
4789 | offset += mips_abi_regsize (gdbarch), regnum++) | |
4790 | { | |
4791 | xfer = mips_abi_regsize (gdbarch); | |
4792 | if (offset + xfer > TYPE_LENGTH (type)) | |
4793 | xfer = TYPE_LENGTH (type) - offset; | |
4794 | mips_xfer_register (gdbarch, regcache, | |
4795 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
4796 | gdbarch_byte_order (gdbarch), readbuf, writebuf, | |
4797 | offset); | |
4798 | } | |
4799 | ||
9c8fdbfa | 4800 | return RETURN_VALUE_REGISTER_CONVENTION; |
6d82d43b AC |
4801 | } |
4802 | ||
6d82d43b AC |
4803 | |
4804 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 4805 | |
8d26208a DJ |
4806 | /* Search for a naturally aligned double at OFFSET inside a struct |
4807 | ARG_TYPE. The N32 / N64 ABIs pass these in floating point | |
4808 | registers. */ | |
4809 | ||
4810 | static int | |
74ed0bb4 MD |
4811 | mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type, |
4812 | int offset) | |
8d26208a DJ |
4813 | { |
4814 | int i; | |
4815 | ||
4816 | if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT) | |
4817 | return 0; | |
4818 | ||
74ed0bb4 | 4819 | if (MIPS_FPU_TYPE (gdbarch) != MIPS_FPU_DOUBLE) |
8d26208a DJ |
4820 | return 0; |
4821 | ||
4822 | if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE) | |
4823 | return 0; | |
4824 | ||
4825 | for (i = 0; i < TYPE_NFIELDS (arg_type); i++) | |
4826 | { | |
4827 | int pos; | |
4828 | struct type *field_type; | |
4829 | ||
4830 | /* We're only looking at normal fields. */ | |
5bc60cfb | 4831 | if (field_is_static (&TYPE_FIELD (arg_type, i)) |
8d26208a DJ |
4832 | || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0) |
4833 | continue; | |
4834 | ||
4835 | /* If we have gone past the offset, there is no double to pass. */ | |
4836 | pos = TYPE_FIELD_BITPOS (arg_type, i) / 8; | |
4837 | if (pos > offset) | |
4838 | return 0; | |
4839 | ||
4840 | field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i)); | |
4841 | ||
4842 | /* If this field is entirely before the requested offset, go | |
4843 | on to the next one. */ | |
4844 | if (pos + TYPE_LENGTH (field_type) <= offset) | |
4845 | continue; | |
4846 | ||
4847 | /* If this is our special aligned double, we can stop. */ | |
4848 | if (TYPE_CODE (field_type) == TYPE_CODE_FLT | |
4849 | && TYPE_LENGTH (field_type) == MIPS64_REGSIZE) | |
4850 | return 1; | |
4851 | ||
4852 | /* This field starts at or before the requested offset, and | |
4853 | overlaps it. If it is a structure, recurse inwards. */ | |
74ed0bb4 | 4854 | return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos); |
8d26208a DJ |
4855 | } |
4856 | ||
4857 | return 0; | |
4858 | } | |
4859 | ||
f7ab6ec6 | 4860 | static CORE_ADDR |
7d9b040b | 4861 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4862 | struct regcache *regcache, CORE_ADDR bp_addr, |
4863 | int nargs, struct value **args, CORE_ADDR sp, | |
4864 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
4865 | { |
4866 | int argreg; | |
4867 | int float_argreg; | |
4868 | int argnum; | |
4869 | int len = 0; | |
4870 | int stack_offset = 0; | |
e17a4113 | 4871 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 4872 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 4873 | |
25ab4790 AC |
4874 | /* For shared libraries, "t9" needs to point at the function |
4875 | address. */ | |
4c7d22cb | 4876 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
4877 | |
4878 | /* Set the return address register to point to the entry point of | |
4879 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 4880 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 4881 | |
cb3d25d1 MS |
4882 | /* First ensure that the stack and structure return address (if any) |
4883 | are properly aligned. The stack has to be at least 64-bit | |
4884 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4885 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4886 | aligned, so we round to this widest known alignment. */ | |
4887 | ||
5b03f266 AC |
4888 | sp = align_down (sp, 16); |
4889 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
4890 | |
4891 | /* Now make space on the stack for the args. */ | |
4892 | for (argnum = 0; argnum < nargs; argnum++) | |
1a69e1e4 | 4893 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE); |
5b03f266 | 4894 | sp -= align_up (len, 16); |
cb3d25d1 MS |
4895 | |
4896 | if (mips_debug) | |
6d82d43b | 4897 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
4898 | "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n", |
4899 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
4900 | |
4901 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 4902 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 4903 | float_argreg = mips_fpa0_regnum (gdbarch); |
cb3d25d1 | 4904 | |
46e0f506 | 4905 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
4906 | if (struct_return) |
4907 | { | |
4908 | if (mips_debug) | |
4909 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
4910 | "mips_n32n64_push_dummy_call: " |
4911 | "struct_return reg=%d %s\n", | |
5af949e3 | 4912 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 4913 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
cb3d25d1 MS |
4914 | } |
4915 | ||
4916 | /* Now load as many as possible of the first arguments into | |
4917 | registers, and push the rest onto the stack. Loop thru args | |
4918 | from first to last. */ | |
4919 | for (argnum = 0; argnum < nargs; argnum++) | |
4920 | { | |
47a35522 | 4921 | const gdb_byte *val; |
cb3d25d1 | 4922 | struct value *arg = args[argnum]; |
4991999e | 4923 | struct type *arg_type = check_typedef (value_type (arg)); |
cb3d25d1 MS |
4924 | int len = TYPE_LENGTH (arg_type); |
4925 | enum type_code typecode = TYPE_CODE (arg_type); | |
4926 | ||
4927 | if (mips_debug) | |
4928 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4929 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
4930 | argnum + 1, len, (int) typecode); |
4931 | ||
47a35522 | 4932 | val = value_contents (arg); |
cb3d25d1 | 4933 | |
5b68030f JM |
4934 | /* A 128-bit long double value requires an even-odd pair of |
4935 | floating-point registers. */ | |
4936 | if (len == 16 | |
4937 | && fp_register_arg_p (gdbarch, typecode, arg_type) | |
4938 | && (float_argreg & 1)) | |
4939 | { | |
4940 | float_argreg++; | |
4941 | argreg++; | |
4942 | } | |
4943 | ||
74ed0bb4 MD |
4944 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
4945 | && argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) | |
cb3d25d1 MS |
4946 | { |
4947 | /* This is a floating point value that fits entirely | |
5b68030f JM |
4948 | in a single register or a pair of registers. */ |
4949 | int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE); | |
e17a4113 | 4950 | LONGEST regval = extract_unsigned_integer (val, reglen, byte_order); |
cb3d25d1 MS |
4951 | if (mips_debug) |
4952 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5b68030f | 4953 | float_argreg, phex (regval, reglen)); |
8d26208a | 4954 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); |
cb3d25d1 MS |
4955 | |
4956 | if (mips_debug) | |
4957 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5b68030f | 4958 | argreg, phex (regval, reglen)); |
9c9acae0 | 4959 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a DJ |
4960 | float_argreg++; |
4961 | argreg++; | |
5b68030f JM |
4962 | if (len == 16) |
4963 | { | |
e17a4113 UW |
4964 | regval = extract_unsigned_integer (val + reglen, |
4965 | reglen, byte_order); | |
5b68030f JM |
4966 | if (mips_debug) |
4967 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4968 | float_argreg, phex (regval, reglen)); | |
4969 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); | |
4970 | ||
4971 | if (mips_debug) | |
4972 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4973 | argreg, phex (regval, reglen)); | |
4974 | regcache_cooked_write_unsigned (regcache, argreg, regval); | |
4975 | float_argreg++; | |
4976 | argreg++; | |
4977 | } | |
cb3d25d1 MS |
4978 | } |
4979 | else | |
4980 | { | |
4981 | /* Copy the argument to general registers or the stack in | |
4982 | register-sized pieces. Large arguments are split between | |
4983 | registers and stack. */ | |
ab2e1992 MR |
4984 | /* For N32/N64, structs, unions, or other composite types are |
4985 | treated as a sequence of doublewords, and are passed in integer | |
4986 | or floating point registers as though they were simple scalar | |
4987 | parameters to the extent that they fit, with any excess on the | |
4988 | stack packed according to the normal memory layout of the | |
4989 | object. | |
4990 | The caller does not reserve space for the register arguments; | |
4991 | the callee is responsible for reserving it if required. */ | |
cb3d25d1 | 4992 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 4993 | register are only written to memory. */ |
cb3d25d1 MS |
4994 | while (len > 0) |
4995 | { | |
ad018eee | 4996 | /* Remember if the argument was written to the stack. */ |
cb3d25d1 | 4997 | int stack_used_p = 0; |
1a69e1e4 | 4998 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
cb3d25d1 MS |
4999 | |
5000 | if (mips_debug) | |
5001 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
5002 | partial_len); | |
5003 | ||
74ed0bb4 MD |
5004 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
5005 | gdb_assert (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)); | |
8d26208a | 5006 | |
cb3d25d1 | 5007 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 5008 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 MS |
5009 | { |
5010 | /* Should shorter than int integer values be | |
025bb325 | 5011 | promoted to int before being stored? */ |
cb3d25d1 MS |
5012 | int longword_offset = 0; |
5013 | CORE_ADDR addr; | |
5014 | stack_used_p = 1; | |
72a155b4 | 5015 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
cb3d25d1 | 5016 | { |
1a69e1e4 | 5017 | if ((typecode == TYPE_CODE_INT |
5b68030f | 5018 | || typecode == TYPE_CODE_PTR) |
1a69e1e4 DJ |
5019 | && len <= 4) |
5020 | longword_offset = MIPS64_REGSIZE - len; | |
cb3d25d1 MS |
5021 | } |
5022 | ||
5023 | if (mips_debug) | |
5024 | { | |
5af949e3 UW |
5025 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
5026 | paddress (gdbarch, stack_offset)); | |
5027 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
5028 | paddress (gdbarch, longword_offset)); | |
cb3d25d1 MS |
5029 | } |
5030 | ||
5031 | addr = sp + stack_offset + longword_offset; | |
5032 | ||
5033 | if (mips_debug) | |
5034 | { | |
5035 | int i; | |
5af949e3 UW |
5036 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
5037 | paddress (gdbarch, addr)); | |
cb3d25d1 MS |
5038 | for (i = 0; i < partial_len; i++) |
5039 | { | |
6d82d43b | 5040 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
5041 | val[i] & 0xff); |
5042 | } | |
5043 | } | |
5044 | write_memory (addr, val, partial_len); | |
5045 | } | |
5046 | ||
5047 | /* Note!!! This is NOT an else clause. Odd sized | |
8d26208a | 5048 | structs may go thru BOTH paths. */ |
cb3d25d1 | 5049 | /* Write this portion of the argument to a general |
6d82d43b | 5050 | purpose register. */ |
74ed0bb4 | 5051 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 | 5052 | { |
5863b5d5 MR |
5053 | LONGEST regval; |
5054 | ||
5055 | /* Sign extend pointers, 32-bit integers and signed | |
5056 | 16-bit and 8-bit integers; everything else is taken | |
5057 | as is. */ | |
5058 | ||
5059 | if ((partial_len == 4 | |
5060 | && (typecode == TYPE_CODE_PTR | |
5061 | || typecode == TYPE_CODE_INT)) | |
5062 | || (partial_len < 4 | |
5063 | && typecode == TYPE_CODE_INT | |
5064 | && !TYPE_UNSIGNED (arg_type))) | |
e17a4113 UW |
5065 | regval = extract_signed_integer (val, partial_len, |
5066 | byte_order); | |
5863b5d5 | 5067 | else |
e17a4113 UW |
5068 | regval = extract_unsigned_integer (val, partial_len, |
5069 | byte_order); | |
cb3d25d1 MS |
5070 | |
5071 | /* A non-floating-point argument being passed in a | |
5072 | general register. If a struct or union, and if | |
5073 | the remaining length is smaller than the register | |
5074 | size, we have to adjust the register value on | |
5075 | big endian targets. | |
5076 | ||
5077 | It does not seem to be necessary to do the | |
1a69e1e4 | 5078 | same for integral types. */ |
cb3d25d1 | 5079 | |
72a155b4 | 5080 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 5081 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
5082 | && (typecode == TYPE_CODE_STRUCT |
5083 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 5084 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 5085 | * TARGET_CHAR_BIT); |
cb3d25d1 MS |
5086 | |
5087 | if (mips_debug) | |
5088 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
5089 | argreg, | |
1a69e1e4 | 5090 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 5091 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a | 5092 | |
74ed0bb4 | 5093 | if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type, |
8d26208a DJ |
5094 | TYPE_LENGTH (arg_type) - len)) |
5095 | { | |
5096 | if (mips_debug) | |
5097 | fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s", | |
5098 | float_argreg, | |
5099 | phex (regval, MIPS64_REGSIZE)); | |
5100 | regcache_cooked_write_unsigned (regcache, float_argreg, | |
5101 | regval); | |
5102 | } | |
5103 | ||
5104 | float_argreg++; | |
cb3d25d1 MS |
5105 | argreg++; |
5106 | } | |
5107 | ||
5108 | len -= partial_len; | |
5109 | val += partial_len; | |
5110 | ||
b021a221 MS |
5111 | /* Compute the offset into the stack at which we will |
5112 | copy the next parameter. | |
cb3d25d1 MS |
5113 | |
5114 | In N32 (N64?), the stack_offset only needs to be | |
5115 | adjusted when it has been used. */ | |
5116 | ||
5117 | if (stack_used_p) | |
1a69e1e4 | 5118 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
cb3d25d1 MS |
5119 | } |
5120 | } | |
5121 | if (mips_debug) | |
5122 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
5123 | } | |
5124 | ||
f10683bb | 5125 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 5126 | |
cb3d25d1 MS |
5127 | /* Return adjusted stack pointer. */ |
5128 | return sp; | |
5129 | } | |
5130 | ||
6d82d43b | 5131 | static enum return_value_convention |
6a3a010b | 5132 | mips_n32n64_return_value (struct gdbarch *gdbarch, struct value *function, |
6d82d43b | 5133 | struct type *type, struct regcache *regcache, |
47a35522 | 5134 | gdb_byte *readbuf, const gdb_byte *writebuf) |
ebafbe83 | 5135 | { |
72a155b4 | 5136 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
b18bb924 MR |
5137 | |
5138 | /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004 | |
5139 | ||
5140 | Function results are returned in $2 (and $3 if needed), or $f0 (and $f2 | |
5141 | if needed), as appropriate for the type. Composite results (struct, | |
5142 | union, or array) are returned in $2/$f0 and $3/$f2 according to the | |
5143 | following rules: | |
5144 | ||
5145 | * A struct with only one or two floating point fields is returned in $f0 | |
5146 | (and $f2 if necessary). This is a generalization of the Fortran COMPLEX | |
5147 | case. | |
5148 | ||
f08877ba | 5149 | * Any other composite results of at most 128 bits are returned in |
b18bb924 MR |
5150 | $2 (first 64 bits) and $3 (remainder, if necessary). |
5151 | ||
5152 | * Larger composite results are handled by converting the function to a | |
5153 | procedure with an implicit first parameter, which is a pointer to an area | |
5154 | reserved by the caller to receive the result. [The o32-bit ABI requires | |
5155 | that all composite results be handled by conversion to implicit first | |
5156 | parameters. The MIPS/SGI Fortran implementation has always made a | |
5157 | specific exception to return COMPLEX results in the floating point | |
5158 | registers.] */ | |
5159 | ||
f08877ba | 5160 | if (TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE) |
6d82d43b | 5161 | return RETURN_VALUE_STRUCT_CONVENTION; |
d05f6826 DJ |
5162 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
5163 | && TYPE_LENGTH (type) == 16 | |
5164 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5165 | { | |
5166 | /* A 128-bit floating-point value fills both $f0 and $f2. The | |
5167 | two registers are used in the same as memory order, so the | |
5168 | eight bytes with the lower memory address are in $f0. */ | |
5169 | if (mips_debug) | |
5170 | fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n"); | |
ba32f989 | 5171 | mips_xfer_register (gdbarch, regcache, |
dca9aa3a MR |
5172 | (gdbarch_num_regs (gdbarch) |
5173 | + mips_regnum (gdbarch)->fp0), | |
72a155b4 | 5174 | 8, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5175 | readbuf, writebuf, 0); |
ba32f989 | 5176 | mips_xfer_register (gdbarch, regcache, |
dca9aa3a MR |
5177 | (gdbarch_num_regs (gdbarch) |
5178 | + mips_regnum (gdbarch)->fp0 + 2), | |
72a155b4 | 5179 | 8, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5180 | readbuf ? readbuf + 8 : readbuf, |
d05f6826 DJ |
5181 | writebuf ? writebuf + 8 : writebuf, 0); |
5182 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5183 | } | |
6d82d43b AC |
5184 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
5185 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5186 | { | |
59aa1faa | 5187 | /* A single or double floating-point value that fits in FP0. */ |
6d82d43b AC |
5188 | if (mips_debug) |
5189 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 5190 | mips_xfer_register (gdbarch, regcache, |
dca9aa3a MR |
5191 | (gdbarch_num_regs (gdbarch) |
5192 | + mips_regnum (gdbarch)->fp0), | |
6d82d43b | 5193 | TYPE_LENGTH (type), |
72a155b4 | 5194 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 5195 | readbuf, writebuf, 0); |
6d82d43b AC |
5196 | return RETURN_VALUE_REGISTER_CONVENTION; |
5197 | } | |
5198 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
5199 | && TYPE_NFIELDS (type) <= 2 | |
5200 | && TYPE_NFIELDS (type) >= 1 | |
5201 | && ((TYPE_NFIELDS (type) == 1 | |
b18bb924 | 5202 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b AC |
5203 | == TYPE_CODE_FLT)) |
5204 | || (TYPE_NFIELDS (type) == 2 | |
b18bb924 | 5205 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b | 5206 | == TYPE_CODE_FLT) |
b18bb924 | 5207 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1))) |
5b68030f | 5208 | == TYPE_CODE_FLT)))) |
6d82d43b AC |
5209 | { |
5210 | /* A struct that contains one or two floats. Each value is part | |
5211 | in the least significant part of their floating point | |
5b68030f | 5212 | register (or GPR, for soft float). */ |
6d82d43b AC |
5213 | int regnum; |
5214 | int field; | |
5b68030f JM |
5215 | for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE |
5216 | ? mips_regnum (gdbarch)->fp0 | |
5217 | : MIPS_V0_REGNUM); | |
6d82d43b AC |
5218 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
5219 | { | |
5220 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
5221 | / TARGET_CHAR_BIT); | |
5222 | if (mips_debug) | |
5223 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
5224 | offset); | |
5b68030f JM |
5225 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)) == 16) |
5226 | { | |
5227 | /* A 16-byte long double field goes in two consecutive | |
5228 | registers. */ | |
5229 | mips_xfer_register (gdbarch, regcache, | |
5230 | gdbarch_num_regs (gdbarch) + regnum, | |
5231 | 8, | |
5232 | gdbarch_byte_order (gdbarch), | |
5233 | readbuf, writebuf, offset); | |
5234 | mips_xfer_register (gdbarch, regcache, | |
5235 | gdbarch_num_regs (gdbarch) + regnum + 1, | |
5236 | 8, | |
5237 | gdbarch_byte_order (gdbarch), | |
5238 | readbuf, writebuf, offset + 8); | |
5239 | } | |
5240 | else | |
5241 | mips_xfer_register (gdbarch, regcache, | |
5242 | gdbarch_num_regs (gdbarch) + regnum, | |
5243 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
5244 | gdbarch_byte_order (gdbarch), | |
5245 | readbuf, writebuf, offset); | |
6d82d43b AC |
5246 | } |
5247 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5248 | } | |
5249 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
f08877ba JB |
5250 | || TYPE_CODE (type) == TYPE_CODE_UNION |
5251 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
6d82d43b | 5252 | { |
f08877ba | 5253 | /* A composite type. Extract the left justified value, |
6d82d43b AC |
5254 | regardless of the byte order. I.e. DO NOT USE |
5255 | mips_xfer_lower. */ | |
5256 | int offset; | |
5257 | int regnum; | |
4c7d22cb | 5258 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 5259 | offset < TYPE_LENGTH (type); |
72a155b4 | 5260 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 5261 | { |
72a155b4 | 5262 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
5263 | if (offset + xfer > TYPE_LENGTH (type)) |
5264 | xfer = TYPE_LENGTH (type) - offset; | |
5265 | if (mips_debug) | |
5266 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
5267 | offset, xfer, regnum); | |
ba32f989 DJ |
5268 | mips_xfer_register (gdbarch, regcache, |
5269 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 UW |
5270 | xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf, |
5271 | offset); | |
6d82d43b AC |
5272 | } |
5273 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5274 | } | |
5275 | else | |
5276 | { | |
5277 | /* A scalar extract each part but least-significant-byte | |
5278 | justified. */ | |
5279 | int offset; | |
5280 | int regnum; | |
4c7d22cb | 5281 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 5282 | offset < TYPE_LENGTH (type); |
72a155b4 | 5283 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 5284 | { |
72a155b4 | 5285 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
5286 | if (offset + xfer > TYPE_LENGTH (type)) |
5287 | xfer = TYPE_LENGTH (type) - offset; | |
5288 | if (mips_debug) | |
5289 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
5290 | offset, xfer, regnum); | |
ba32f989 DJ |
5291 | mips_xfer_register (gdbarch, regcache, |
5292 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 5293 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5294 | readbuf, writebuf, offset); |
6d82d43b AC |
5295 | } |
5296 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5297 | } | |
5298 | } | |
5299 | ||
6a3a010b MR |
5300 | /* Which registers to use for passing floating-point values between |
5301 | function calls, one of floating-point, general and both kinds of | |
5302 | registers. O32 and O64 use different register kinds for standard | |
5303 | MIPS and MIPS16 code; to make the handling of cases where we may | |
5304 | not know what kind of code is being used (e.g. no debug information) | |
5305 | easier we sometimes use both kinds. */ | |
5306 | ||
5307 | enum mips_fval_reg | |
5308 | { | |
5309 | mips_fval_fpr, | |
5310 | mips_fval_gpr, | |
5311 | mips_fval_both | |
5312 | }; | |
5313 | ||
6d82d43b AC |
5314 | /* O32 ABI stuff. */ |
5315 | ||
5316 | static CORE_ADDR | |
7d9b040b | 5317 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
5318 | struct regcache *regcache, CORE_ADDR bp_addr, |
5319 | int nargs, struct value **args, CORE_ADDR sp, | |
5320 | int struct_return, CORE_ADDR struct_addr) | |
5321 | { | |
5322 | int argreg; | |
5323 | int float_argreg; | |
5324 | int argnum; | |
5325 | int len = 0; | |
5326 | int stack_offset = 0; | |
e17a4113 | 5327 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 5328 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
5329 | |
5330 | /* For shared libraries, "t9" needs to point at the function | |
5331 | address. */ | |
4c7d22cb | 5332 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
6d82d43b AC |
5333 | |
5334 | /* Set the return address register to point to the entry point of | |
5335 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 5336 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
6d82d43b AC |
5337 | |
5338 | /* First ensure that the stack and structure return address (if any) | |
5339 | are properly aligned. The stack has to be at least 64-bit | |
5340 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
5341 | aligned. For n32 and n64, stack frames need to be 128-bit |
5342 | aligned, so we round to this widest known alignment. */ | |
5343 | ||
5b03f266 AC |
5344 | sp = align_down (sp, 16); |
5345 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
5346 | |
5347 | /* Now make space on the stack for the args. */ | |
5348 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
5349 | { |
5350 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
968b5391 MR |
5351 | |
5352 | /* Align to double-word if necessary. */ | |
2afd3f0a | 5353 | if (mips_type_needs_double_align (arg_type)) |
1a69e1e4 | 5354 | len = align_up (len, MIPS32_REGSIZE * 2); |
968b5391 | 5355 | /* Allocate space on the stack. */ |
354ecfd5 | 5356 | len += align_up (TYPE_LENGTH (arg_type), MIPS32_REGSIZE); |
968b5391 | 5357 | } |
5b03f266 | 5358 | sp -= align_up (len, 16); |
ebafbe83 MS |
5359 | |
5360 | if (mips_debug) | |
6d82d43b | 5361 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
5362 | "mips_o32_push_dummy_call: sp=%s allocated %ld\n", |
5363 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
5364 | |
5365 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 5366 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 5367 | float_argreg = mips_fpa0_regnum (gdbarch); |
ebafbe83 | 5368 | |
bcb0cc15 | 5369 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
5370 | if (struct_return) |
5371 | { | |
5372 | if (mips_debug) | |
5373 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
5374 | "mips_o32_push_dummy_call: " |
5375 | "struct_return reg=%d %s\n", | |
5af949e3 | 5376 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 5377 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 5378 | stack_offset += MIPS32_REGSIZE; |
ebafbe83 MS |
5379 | } |
5380 | ||
5381 | /* Now load as many as possible of the first arguments into | |
5382 | registers, and push the rest onto the stack. Loop thru args | |
5383 | from first to last. */ | |
5384 | for (argnum = 0; argnum < nargs; argnum++) | |
5385 | { | |
47a35522 | 5386 | const gdb_byte *val; |
ebafbe83 | 5387 | struct value *arg = args[argnum]; |
4991999e | 5388 | struct type *arg_type = check_typedef (value_type (arg)); |
ebafbe83 MS |
5389 | int len = TYPE_LENGTH (arg_type); |
5390 | enum type_code typecode = TYPE_CODE (arg_type); | |
5391 | ||
5392 | if (mips_debug) | |
5393 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 5394 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
5395 | argnum + 1, len, (int) typecode); |
5396 | ||
47a35522 | 5397 | val = value_contents (arg); |
46cac009 AC |
5398 | |
5399 | /* 32-bit ABIs always start floating point arguments in an | |
5400 | even-numbered floating point register. Round the FP register | |
5401 | up before the check to see if there are any FP registers | |
6a3a010b MR |
5402 | left. O32 targets also pass the FP in the integer registers |
5403 | so also round up normal registers. */ | |
74ed0bb4 | 5404 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
46cac009 AC |
5405 | { |
5406 | if ((float_argreg & 1)) | |
5407 | float_argreg++; | |
5408 | } | |
5409 | ||
5410 | /* Floating point arguments passed in registers have to be | |
6a3a010b MR |
5411 | treated specially. On 32-bit architectures, doubles are |
5412 | passed in register pairs; the even FP register gets the | |
5413 | low word, and the odd FP register gets the high word. | |
5414 | On O32, the first two floating point arguments are also | |
5415 | copied to general registers, following their memory order, | |
5416 | because MIPS16 functions don't use float registers for | |
5417 | arguments. This duplication of arguments in general | |
5418 | registers can't hurt non-MIPS16 functions, because those | |
5419 | registers are normally skipped. */ | |
46cac009 | 5420 | |
74ed0bb4 MD |
5421 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
5422 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
46cac009 | 5423 | { |
8b07f6d8 | 5424 | if (register_size (gdbarch, float_argreg) < 8 && len == 8) |
46cac009 | 5425 | { |
6a3a010b MR |
5426 | int freg_offset = gdbarch_byte_order (gdbarch) |
5427 | == BFD_ENDIAN_BIG ? 1 : 0; | |
46cac009 AC |
5428 | unsigned long regval; |
5429 | ||
6a3a010b MR |
5430 | /* First word. */ |
5431 | regval = extract_unsigned_integer (val, 4, byte_order); | |
46cac009 AC |
5432 | if (mips_debug) |
5433 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
6a3a010b MR |
5434 | float_argreg + freg_offset, |
5435 | phex (regval, 4)); | |
025bb325 | 5436 | regcache_cooked_write_unsigned (regcache, |
6a3a010b MR |
5437 | float_argreg++ + freg_offset, |
5438 | regval); | |
46cac009 AC |
5439 | if (mips_debug) |
5440 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5441 | argreg, phex (regval, 4)); | |
9c9acae0 | 5442 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 | 5443 | |
6a3a010b MR |
5444 | /* Second word. */ |
5445 | regval = extract_unsigned_integer (val + 4, 4, byte_order); | |
46cac009 AC |
5446 | if (mips_debug) |
5447 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
6a3a010b MR |
5448 | float_argreg - freg_offset, |
5449 | phex (regval, 4)); | |
025bb325 | 5450 | regcache_cooked_write_unsigned (regcache, |
6a3a010b MR |
5451 | float_argreg++ - freg_offset, |
5452 | regval); | |
46cac009 AC |
5453 | if (mips_debug) |
5454 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5455 | argreg, phex (regval, 4)); | |
9c9acae0 | 5456 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
5457 | } |
5458 | else | |
5459 | { | |
5460 | /* This is a floating point value that fits entirely | |
5461 | in a single register. */ | |
5462 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 5463 | above to ensure that it is even register aligned. */ |
e17a4113 | 5464 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
46cac009 AC |
5465 | if (mips_debug) |
5466 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5467 | float_argreg, phex (regval, len)); | |
025bb325 MS |
5468 | regcache_cooked_write_unsigned (regcache, |
5469 | float_argreg++, regval); | |
5b68030f JM |
5470 | /* Although two FP registers are reserved for each |
5471 | argument, only one corresponding integer register is | |
5472 | reserved. */ | |
46cac009 AC |
5473 | if (mips_debug) |
5474 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5475 | argreg, phex (regval, len)); | |
5b68030f | 5476 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
5477 | } |
5478 | /* Reserve space for the FP register. */ | |
1a69e1e4 | 5479 | stack_offset += align_up (len, MIPS32_REGSIZE); |
46cac009 AC |
5480 | } |
5481 | else | |
5482 | { | |
5483 | /* Copy the argument to general registers or the stack in | |
5484 | register-sized pieces. Large arguments are split between | |
5485 | registers and stack. */ | |
1a69e1e4 DJ |
5486 | /* Note: structs whose size is not a multiple of MIPS32_REGSIZE |
5487 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
5488 | them in registers where gcc sometimes puts them on the |
5489 | stack. For maximum compatibility, we will put them in | |
5490 | both places. */ | |
1a69e1e4 DJ |
5491 | int odd_sized_struct = (len > MIPS32_REGSIZE |
5492 | && len % MIPS32_REGSIZE != 0); | |
46cac009 AC |
5493 | /* Structures should be aligned to eight bytes (even arg registers) |
5494 | on MIPS_ABI_O32, if their first member has double precision. */ | |
2afd3f0a | 5495 | if (mips_type_needs_double_align (arg_type)) |
46cac009 AC |
5496 | { |
5497 | if ((argreg & 1)) | |
968b5391 MR |
5498 | { |
5499 | argreg++; | |
1a69e1e4 | 5500 | stack_offset += MIPS32_REGSIZE; |
968b5391 | 5501 | } |
46cac009 | 5502 | } |
46cac009 AC |
5503 | while (len > 0) |
5504 | { | |
1a69e1e4 | 5505 | int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); |
46cac009 AC |
5506 | |
5507 | if (mips_debug) | |
5508 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
5509 | partial_len); | |
5510 | ||
5511 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 5512 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 5513 | || odd_sized_struct) |
46cac009 AC |
5514 | { |
5515 | /* Should shorter than int integer values be | |
025bb325 | 5516 | promoted to int before being stored? */ |
46cac009 AC |
5517 | int longword_offset = 0; |
5518 | CORE_ADDR addr; | |
46cac009 AC |
5519 | |
5520 | if (mips_debug) | |
5521 | { | |
5af949e3 UW |
5522 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
5523 | paddress (gdbarch, stack_offset)); | |
5524 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
5525 | paddress (gdbarch, longword_offset)); | |
46cac009 AC |
5526 | } |
5527 | ||
5528 | addr = sp + stack_offset + longword_offset; | |
5529 | ||
5530 | if (mips_debug) | |
5531 | { | |
5532 | int i; | |
5af949e3 UW |
5533 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
5534 | paddress (gdbarch, addr)); | |
46cac009 AC |
5535 | for (i = 0; i < partial_len; i++) |
5536 | { | |
6d82d43b | 5537 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
5538 | val[i] & 0xff); |
5539 | } | |
5540 | } | |
5541 | write_memory (addr, val, partial_len); | |
5542 | } | |
5543 | ||
5544 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 5545 | structs may go thru BOTH paths. */ |
46cac009 | 5546 | /* Write this portion of the argument to a general |
6d82d43b | 5547 | purpose register. */ |
74ed0bb4 | 5548 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
46cac009 | 5549 | { |
e17a4113 UW |
5550 | LONGEST regval = extract_signed_integer (val, partial_len, |
5551 | byte_order); | |
4246e332 | 5552 | /* Value may need to be sign extended, because |
1b13c4f6 | 5553 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
5554 | |
5555 | /* A non-floating-point argument being passed in a | |
5556 | general register. If a struct or union, and if | |
5557 | the remaining length is smaller than the register | |
5558 | size, we have to adjust the register value on | |
5559 | big endian targets. | |
5560 | ||
5561 | It does not seem to be necessary to do the | |
5562 | same for integral types. | |
5563 | ||
5564 | Also don't do this adjustment on O64 binaries. | |
5565 | ||
5566 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
5567 | outputting LE O32 with sizeof (struct) < | |
e914cb17 MR |
5568 | mips_abi_regsize(), generates a left shift |
5569 | as part of storing the argument in a register | |
5570 | (the left shift isn't generated when | |
1b13c4f6 | 5571 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
5572 | it is quite possible that this is GCC |
5573 | contradicting the LE/O32 ABI, GDB has not been | |
5574 | adjusted to accommodate this. Either someone | |
5575 | needs to demonstrate that the LE/O32 ABI | |
5576 | specifies such a left shift OR this new ABI gets | |
5577 | identified as such and GDB gets tweaked | |
5578 | accordingly. */ | |
5579 | ||
72a155b4 | 5580 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 5581 | && partial_len < MIPS32_REGSIZE |
06f9a1af MR |
5582 | && (typecode == TYPE_CODE_STRUCT |
5583 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 5584 | regval <<= ((MIPS32_REGSIZE - partial_len) |
9ecf7166 | 5585 | * TARGET_CHAR_BIT); |
46cac009 AC |
5586 | |
5587 | if (mips_debug) | |
5588 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
5589 | argreg, | |
1a69e1e4 | 5590 | phex (regval, MIPS32_REGSIZE)); |
9c9acae0 | 5591 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
46cac009 AC |
5592 | argreg++; |
5593 | ||
5594 | /* Prevent subsequent floating point arguments from | |
5595 | being passed in floating point registers. */ | |
74ed0bb4 | 5596 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
46cac009 AC |
5597 | } |
5598 | ||
5599 | len -= partial_len; | |
5600 | val += partial_len; | |
5601 | ||
b021a221 MS |
5602 | /* Compute the offset into the stack at which we will |
5603 | copy the next parameter. | |
46cac009 | 5604 | |
6d82d43b AC |
5605 | In older ABIs, the caller reserved space for |
5606 | registers that contained arguments. This was loosely | |
5607 | refered to as their "home". Consequently, space is | |
5608 | always allocated. */ | |
46cac009 | 5609 | |
1a69e1e4 | 5610 | stack_offset += align_up (partial_len, MIPS32_REGSIZE); |
46cac009 AC |
5611 | } |
5612 | } | |
5613 | if (mips_debug) | |
5614 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
5615 | } | |
5616 | ||
f10683bb | 5617 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 5618 | |
46cac009 AC |
5619 | /* Return adjusted stack pointer. */ |
5620 | return sp; | |
5621 | } | |
5622 | ||
6d82d43b | 5623 | static enum return_value_convention |
6a3a010b | 5624 | mips_o32_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 | 5625 | struct type *type, struct regcache *regcache, |
47a35522 | 5626 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 5627 | { |
6a3a010b | 5628 | CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0; |
4cc0665f | 5629 | int mips16 = mips_pc_is_mips16 (gdbarch, func_addr); |
72a155b4 | 5630 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
6a3a010b | 5631 | enum mips_fval_reg fval_reg; |
6d82d43b | 5632 | |
6a3a010b | 5633 | fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both; |
6d82d43b AC |
5634 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
5635 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
5636 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
5637 | return RETURN_VALUE_STRUCT_CONVENTION; | |
5638 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
5639 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5640 | { | |
6a3a010b MR |
5641 | /* A single-precision floating-point value. If reading in or copying, |
5642 | then we get it from/put it to FP0 for standard MIPS code or GPR2 | |
5643 | for MIPS16 code. If writing out only, then we put it to both FP0 | |
5644 | and GPR2. We do not support reading in with no function known, if | |
5645 | this safety check ever triggers, then we'll have to try harder. */ | |
5646 | gdb_assert (function || !readbuf); | |
6d82d43b | 5647 | if (mips_debug) |
6a3a010b MR |
5648 | switch (fval_reg) |
5649 | { | |
5650 | case mips_fval_fpr: | |
5651 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
5652 | break; | |
5653 | case mips_fval_gpr: | |
5654 | fprintf_unfiltered (gdb_stderr, "Return float in $2\n"); | |
5655 | break; | |
5656 | case mips_fval_both: | |
5657 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n"); | |
5658 | break; | |
5659 | } | |
5660 | if (fval_reg != mips_fval_gpr) | |
5661 | mips_xfer_register (gdbarch, regcache, | |
5662 | (gdbarch_num_regs (gdbarch) | |
5663 | + mips_regnum (gdbarch)->fp0), | |
5664 | TYPE_LENGTH (type), | |
5665 | gdbarch_byte_order (gdbarch), | |
5666 | readbuf, writebuf, 0); | |
5667 | if (fval_reg != mips_fval_fpr) | |
5668 | mips_xfer_register (gdbarch, regcache, | |
5669 | gdbarch_num_regs (gdbarch) + 2, | |
5670 | TYPE_LENGTH (type), | |
5671 | gdbarch_byte_order (gdbarch), | |
5672 | readbuf, writebuf, 0); | |
6d82d43b AC |
5673 | return RETURN_VALUE_REGISTER_CONVENTION; |
5674 | } | |
5675 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
5676 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5677 | { | |
6a3a010b MR |
5678 | /* A double-precision floating-point value. If reading in or copying, |
5679 | then we get it from/put it to FP1 and FP0 for standard MIPS code or | |
5680 | GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it | |
5681 | to both FP1/FP0 and GPR2/GPR3. We do not support reading in with | |
5682 | no function known, if this safety check ever triggers, then we'll | |
5683 | have to try harder. */ | |
5684 | gdb_assert (function || !readbuf); | |
6d82d43b | 5685 | if (mips_debug) |
6a3a010b MR |
5686 | switch (fval_reg) |
5687 | { | |
5688 | case mips_fval_fpr: | |
5689 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
5690 | break; | |
5691 | case mips_fval_gpr: | |
5692 | fprintf_unfiltered (gdb_stderr, "Return float in $2/$3\n"); | |
5693 | break; | |
5694 | case mips_fval_both: | |
5695 | fprintf_unfiltered (gdb_stderr, | |
5696 | "Return float in $fp1/$fp0 and $2/$3\n"); | |
5697 | break; | |
5698 | } | |
5699 | if (fval_reg != mips_fval_gpr) | |
6d82d43b | 5700 | { |
6a3a010b MR |
5701 | /* The most significant part goes in FP1, and the least significant |
5702 | in FP0. */ | |
5703 | switch (gdbarch_byte_order (gdbarch)) | |
5704 | { | |
5705 | case BFD_ENDIAN_LITTLE: | |
5706 | mips_xfer_register (gdbarch, regcache, | |
5707 | (gdbarch_num_regs (gdbarch) | |
5708 | + mips_regnum (gdbarch)->fp0 + 0), | |
5709 | 4, gdbarch_byte_order (gdbarch), | |
5710 | readbuf, writebuf, 0); | |
5711 | mips_xfer_register (gdbarch, regcache, | |
5712 | (gdbarch_num_regs (gdbarch) | |
5713 | + mips_regnum (gdbarch)->fp0 + 1), | |
5714 | 4, gdbarch_byte_order (gdbarch), | |
5715 | readbuf, writebuf, 4); | |
5716 | break; | |
5717 | case BFD_ENDIAN_BIG: | |
5718 | mips_xfer_register (gdbarch, regcache, | |
5719 | (gdbarch_num_regs (gdbarch) | |
5720 | + mips_regnum (gdbarch)->fp0 + 1), | |
5721 | 4, gdbarch_byte_order (gdbarch), | |
5722 | readbuf, writebuf, 0); | |
5723 | mips_xfer_register (gdbarch, regcache, | |
5724 | (gdbarch_num_regs (gdbarch) | |
5725 | + mips_regnum (gdbarch)->fp0 + 0), | |
5726 | 4, gdbarch_byte_order (gdbarch), | |
5727 | readbuf, writebuf, 4); | |
5728 | break; | |
5729 | default: | |
5730 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
5731 | } | |
5732 | } | |
5733 | if (fval_reg != mips_fval_fpr) | |
5734 | { | |
5735 | /* The two 32-bit parts are always placed in GPR2 and GPR3 | |
5736 | following these registers' memory order. */ | |
ba32f989 | 5737 | mips_xfer_register (gdbarch, regcache, |
6a3a010b | 5738 | gdbarch_num_regs (gdbarch) + 2, |
72a155b4 | 5739 | 4, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5740 | readbuf, writebuf, 0); |
ba32f989 | 5741 | mips_xfer_register (gdbarch, regcache, |
6a3a010b | 5742 | gdbarch_num_regs (gdbarch) + 3, |
72a155b4 | 5743 | 4, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5744 | readbuf, writebuf, 4); |
6d82d43b AC |
5745 | } |
5746 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5747 | } | |
5748 | #if 0 | |
5749 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
5750 | && TYPE_NFIELDS (type) <= 2 | |
5751 | && TYPE_NFIELDS (type) >= 1 | |
5752 | && ((TYPE_NFIELDS (type) == 1 | |
5753 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
5754 | == TYPE_CODE_FLT)) | |
5755 | || (TYPE_NFIELDS (type) == 2 | |
5756 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
5757 | == TYPE_CODE_FLT) | |
5758 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
5759 | == TYPE_CODE_FLT))) | |
5760 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5761 | { | |
5762 | /* A struct that contains one or two floats. Each value is part | |
5763 | in the least significant part of their floating point | |
5764 | register.. */ | |
6d82d43b AC |
5765 | int regnum; |
5766 | int field; | |
72a155b4 | 5767 | for (field = 0, regnum = mips_regnum (gdbarch)->fp0; |
6d82d43b AC |
5768 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
5769 | { | |
5770 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
5771 | / TARGET_CHAR_BIT); | |
5772 | if (mips_debug) | |
5773 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
5774 | offset); | |
ba32f989 DJ |
5775 | mips_xfer_register (gdbarch, regcache, |
5776 | gdbarch_num_regs (gdbarch) + regnum, | |
6d82d43b | 5777 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
72a155b4 | 5778 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 5779 | readbuf, writebuf, offset); |
6d82d43b AC |
5780 | } |
5781 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5782 | } | |
5783 | #endif | |
5784 | #if 0 | |
5785 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
5786 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
5787 | { | |
5788 | /* A structure or union. Extract the left justified value, | |
5789 | regardless of the byte order. I.e. DO NOT USE | |
5790 | mips_xfer_lower. */ | |
5791 | int offset; | |
5792 | int regnum; | |
4c7d22cb | 5793 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 5794 | offset < TYPE_LENGTH (type); |
72a155b4 | 5795 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 5796 | { |
72a155b4 | 5797 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
5798 | if (offset + xfer > TYPE_LENGTH (type)) |
5799 | xfer = TYPE_LENGTH (type) - offset; | |
5800 | if (mips_debug) | |
5801 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
5802 | offset, xfer, regnum); | |
ba32f989 DJ |
5803 | mips_xfer_register (gdbarch, regcache, |
5804 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
6d82d43b AC |
5805 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
5806 | } | |
5807 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5808 | } | |
5809 | #endif | |
5810 | else | |
5811 | { | |
5812 | /* A scalar extract each part but least-significant-byte | |
5813 | justified. o32 thinks registers are 4 byte, regardless of | |
1a69e1e4 | 5814 | the ISA. */ |
6d82d43b AC |
5815 | int offset; |
5816 | int regnum; | |
4c7d22cb | 5817 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 5818 | offset < TYPE_LENGTH (type); |
1a69e1e4 | 5819 | offset += MIPS32_REGSIZE, regnum++) |
6d82d43b | 5820 | { |
1a69e1e4 | 5821 | int xfer = MIPS32_REGSIZE; |
6d82d43b AC |
5822 | if (offset + xfer > TYPE_LENGTH (type)) |
5823 | xfer = TYPE_LENGTH (type) - offset; | |
5824 | if (mips_debug) | |
5825 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
5826 | offset, xfer, regnum); | |
ba32f989 DJ |
5827 | mips_xfer_register (gdbarch, regcache, |
5828 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
72a155b4 | 5829 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 5830 | readbuf, writebuf, offset); |
6d82d43b AC |
5831 | } |
5832 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5833 | } | |
5834 | } | |
5835 | ||
5836 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
5837 | ABI. */ | |
46cac009 AC |
5838 | |
5839 | static CORE_ADDR | |
7d9b040b | 5840 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
5841 | struct regcache *regcache, CORE_ADDR bp_addr, |
5842 | int nargs, | |
5843 | struct value **args, CORE_ADDR sp, | |
5844 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
5845 | { |
5846 | int argreg; | |
5847 | int float_argreg; | |
5848 | int argnum; | |
5849 | int len = 0; | |
5850 | int stack_offset = 0; | |
e17a4113 | 5851 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 5852 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 5853 | |
25ab4790 AC |
5854 | /* For shared libraries, "t9" needs to point at the function |
5855 | address. */ | |
4c7d22cb | 5856 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
5857 | |
5858 | /* Set the return address register to point to the entry point of | |
5859 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 5860 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 5861 | |
46cac009 AC |
5862 | /* First ensure that the stack and structure return address (if any) |
5863 | are properly aligned. The stack has to be at least 64-bit | |
5864 | aligned even on 32-bit machines, because doubles must be 64-bit | |
5865 | aligned. For n32 and n64, stack frames need to be 128-bit | |
5866 | aligned, so we round to this widest known alignment. */ | |
5867 | ||
5b03f266 AC |
5868 | sp = align_down (sp, 16); |
5869 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
5870 | |
5871 | /* Now make space on the stack for the args. */ | |
5872 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
5873 | { |
5874 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
968b5391 | 5875 | |
968b5391 | 5876 | /* Allocate space on the stack. */ |
354ecfd5 | 5877 | len += align_up (TYPE_LENGTH (arg_type), MIPS64_REGSIZE); |
968b5391 | 5878 | } |
5b03f266 | 5879 | sp -= align_up (len, 16); |
46cac009 AC |
5880 | |
5881 | if (mips_debug) | |
6d82d43b | 5882 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
5883 | "mips_o64_push_dummy_call: sp=%s allocated %ld\n", |
5884 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
46cac009 AC |
5885 | |
5886 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 5887 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 5888 | float_argreg = mips_fpa0_regnum (gdbarch); |
46cac009 AC |
5889 | |
5890 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
5891 | if (struct_return) | |
5892 | { | |
5893 | if (mips_debug) | |
5894 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
5895 | "mips_o64_push_dummy_call: " |
5896 | "struct_return reg=%d %s\n", | |
5af949e3 | 5897 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 5898 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 5899 | stack_offset += MIPS64_REGSIZE; |
46cac009 AC |
5900 | } |
5901 | ||
5902 | /* Now load as many as possible of the first arguments into | |
5903 | registers, and push the rest onto the stack. Loop thru args | |
5904 | from first to last. */ | |
5905 | for (argnum = 0; argnum < nargs; argnum++) | |
5906 | { | |
47a35522 | 5907 | const gdb_byte *val; |
46cac009 | 5908 | struct value *arg = args[argnum]; |
4991999e | 5909 | struct type *arg_type = check_typedef (value_type (arg)); |
46cac009 AC |
5910 | int len = TYPE_LENGTH (arg_type); |
5911 | enum type_code typecode = TYPE_CODE (arg_type); | |
5912 | ||
5913 | if (mips_debug) | |
5914 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 5915 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
5916 | argnum + 1, len, (int) typecode); |
5917 | ||
47a35522 | 5918 | val = value_contents (arg); |
ebafbe83 | 5919 | |
ebafbe83 | 5920 | /* Floating point arguments passed in registers have to be |
6a3a010b MR |
5921 | treated specially. On 32-bit architectures, doubles are |
5922 | passed in register pairs; the even FP register gets the | |
5923 | low word, and the odd FP register gets the high word. | |
5924 | On O64, the first two floating point arguments are also | |
5925 | copied to general registers, because MIPS16 functions | |
5926 | don't use float registers for arguments. This duplication | |
5927 | of arguments in general registers can't hurt non-MIPS16 | |
5928 | functions because those registers are normally skipped. */ | |
ebafbe83 | 5929 | |
74ed0bb4 MD |
5930 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
5931 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
ebafbe83 | 5932 | { |
e17a4113 | 5933 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
2afd3f0a MR |
5934 | if (mips_debug) |
5935 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5936 | float_argreg, phex (regval, len)); | |
9c9acae0 | 5937 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
2afd3f0a MR |
5938 | if (mips_debug) |
5939 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5940 | argreg, phex (regval, len)); | |
9c9acae0 | 5941 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
2afd3f0a | 5942 | argreg++; |
ebafbe83 | 5943 | /* Reserve space for the FP register. */ |
1a69e1e4 | 5944 | stack_offset += align_up (len, MIPS64_REGSIZE); |
ebafbe83 MS |
5945 | } |
5946 | else | |
5947 | { | |
5948 | /* Copy the argument to general registers or the stack in | |
5949 | register-sized pieces. Large arguments are split between | |
5950 | registers and stack. */ | |
1a69e1e4 | 5951 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
5952 | are treated specially: Irix cc passes them in registers |
5953 | where gcc sometimes puts them on the stack. For maximum | |
5954 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
5955 | int odd_sized_struct = (len > MIPS64_REGSIZE |
5956 | && len % MIPS64_REGSIZE != 0); | |
ebafbe83 MS |
5957 | while (len > 0) |
5958 | { | |
1a69e1e4 | 5959 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
ebafbe83 MS |
5960 | |
5961 | if (mips_debug) | |
5962 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
5963 | partial_len); | |
5964 | ||
5965 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 5966 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 5967 | || odd_sized_struct) |
ebafbe83 MS |
5968 | { |
5969 | /* Should shorter than int integer values be | |
025bb325 | 5970 | promoted to int before being stored? */ |
ebafbe83 MS |
5971 | int longword_offset = 0; |
5972 | CORE_ADDR addr; | |
72a155b4 | 5973 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ebafbe83 | 5974 | { |
1a69e1e4 DJ |
5975 | if ((typecode == TYPE_CODE_INT |
5976 | || typecode == TYPE_CODE_PTR | |
5977 | || typecode == TYPE_CODE_FLT) | |
5978 | && len <= 4) | |
5979 | longword_offset = MIPS64_REGSIZE - len; | |
ebafbe83 MS |
5980 | } |
5981 | ||
5982 | if (mips_debug) | |
5983 | { | |
5af949e3 UW |
5984 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
5985 | paddress (gdbarch, stack_offset)); | |
5986 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
5987 | paddress (gdbarch, longword_offset)); | |
ebafbe83 MS |
5988 | } |
5989 | ||
5990 | addr = sp + stack_offset + longword_offset; | |
5991 | ||
5992 | if (mips_debug) | |
5993 | { | |
5994 | int i; | |
5af949e3 UW |
5995 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
5996 | paddress (gdbarch, addr)); | |
ebafbe83 MS |
5997 | for (i = 0; i < partial_len; i++) |
5998 | { | |
6d82d43b | 5999 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
6000 | val[i] & 0xff); |
6001 | } | |
6002 | } | |
6003 | write_memory (addr, val, partial_len); | |
6004 | } | |
6005 | ||
6006 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 6007 | structs may go thru BOTH paths. */ |
ebafbe83 | 6008 | /* Write this portion of the argument to a general |
6d82d43b | 6009 | purpose register. */ |
74ed0bb4 | 6010 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
ebafbe83 | 6011 | { |
e17a4113 UW |
6012 | LONGEST regval = extract_signed_integer (val, partial_len, |
6013 | byte_order); | |
4246e332 | 6014 | /* Value may need to be sign extended, because |
1b13c4f6 | 6015 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
6016 | |
6017 | /* A non-floating-point argument being passed in a | |
6018 | general register. If a struct or union, and if | |
6019 | the remaining length is smaller than the register | |
6020 | size, we have to adjust the register value on | |
6021 | big endian targets. | |
6022 | ||
6023 | It does not seem to be necessary to do the | |
025bb325 | 6024 | same for integral types. */ |
480d3dd2 | 6025 | |
72a155b4 | 6026 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 6027 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
6028 | && (typecode == TYPE_CODE_STRUCT |
6029 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 6030 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 6031 | * TARGET_CHAR_BIT); |
ebafbe83 MS |
6032 | |
6033 | if (mips_debug) | |
6034 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
6035 | argreg, | |
1a69e1e4 | 6036 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 6037 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
ebafbe83 MS |
6038 | argreg++; |
6039 | ||
6040 | /* Prevent subsequent floating point arguments from | |
6041 | being passed in floating point registers. */ | |
74ed0bb4 | 6042 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
ebafbe83 MS |
6043 | } |
6044 | ||
6045 | len -= partial_len; | |
6046 | val += partial_len; | |
6047 | ||
b021a221 MS |
6048 | /* Compute the offset into the stack at which we will |
6049 | copy the next parameter. | |
ebafbe83 | 6050 | |
6d82d43b AC |
6051 | In older ABIs, the caller reserved space for |
6052 | registers that contained arguments. This was loosely | |
6053 | refered to as their "home". Consequently, space is | |
6054 | always allocated. */ | |
ebafbe83 | 6055 | |
1a69e1e4 | 6056 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
ebafbe83 MS |
6057 | } |
6058 | } | |
6059 | if (mips_debug) | |
6060 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
6061 | } | |
6062 | ||
f10683bb | 6063 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 6064 | |
ebafbe83 MS |
6065 | /* Return adjusted stack pointer. */ |
6066 | return sp; | |
6067 | } | |
6068 | ||
9c8fdbfa | 6069 | static enum return_value_convention |
6a3a010b | 6070 | mips_o64_return_value (struct gdbarch *gdbarch, struct value *function, |
9c8fdbfa | 6071 | struct type *type, struct regcache *regcache, |
47a35522 | 6072 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 6073 | { |
6a3a010b | 6074 | CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0; |
4cc0665f | 6075 | int mips16 = mips_pc_is_mips16 (gdbarch, func_addr); |
6a3a010b | 6076 | enum mips_fval_reg fval_reg; |
7a076fd2 | 6077 | |
6a3a010b | 6078 | fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both; |
7a076fd2 FF |
6079 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
6080 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
6081 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
6082 | return RETURN_VALUE_STRUCT_CONVENTION; | |
74ed0bb4 | 6083 | else if (fp_register_arg_p (gdbarch, TYPE_CODE (type), type)) |
7a076fd2 | 6084 | { |
6a3a010b MR |
6085 | /* A floating-point value. If reading in or copying, then we get it |
6086 | from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code. | |
6087 | If writing out only, then we put it to both FP0 and GPR2. We do | |
6088 | not support reading in with no function known, if this safety | |
6089 | check ever triggers, then we'll have to try harder. */ | |
6090 | gdb_assert (function || !readbuf); | |
7a076fd2 | 6091 | if (mips_debug) |
6a3a010b MR |
6092 | switch (fval_reg) |
6093 | { | |
6094 | case mips_fval_fpr: | |
6095 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
6096 | break; | |
6097 | case mips_fval_gpr: | |
6098 | fprintf_unfiltered (gdb_stderr, "Return float in $2\n"); | |
6099 | break; | |
6100 | case mips_fval_both: | |
6101 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n"); | |
6102 | break; | |
6103 | } | |
6104 | if (fval_reg != mips_fval_gpr) | |
6105 | mips_xfer_register (gdbarch, regcache, | |
6106 | (gdbarch_num_regs (gdbarch) | |
6107 | + mips_regnum (gdbarch)->fp0), | |
6108 | TYPE_LENGTH (type), | |
6109 | gdbarch_byte_order (gdbarch), | |
6110 | readbuf, writebuf, 0); | |
6111 | if (fval_reg != mips_fval_fpr) | |
6112 | mips_xfer_register (gdbarch, regcache, | |
6113 | gdbarch_num_regs (gdbarch) + 2, | |
6114 | TYPE_LENGTH (type), | |
6115 | gdbarch_byte_order (gdbarch), | |
6116 | readbuf, writebuf, 0); | |
7a076fd2 FF |
6117 | return RETURN_VALUE_REGISTER_CONVENTION; |
6118 | } | |
6119 | else | |
6120 | { | |
6121 | /* A scalar extract each part but least-significant-byte | |
025bb325 | 6122 | justified. */ |
7a076fd2 FF |
6123 | int offset; |
6124 | int regnum; | |
6125 | for (offset = 0, regnum = MIPS_V0_REGNUM; | |
6126 | offset < TYPE_LENGTH (type); | |
1a69e1e4 | 6127 | offset += MIPS64_REGSIZE, regnum++) |
7a076fd2 | 6128 | { |
1a69e1e4 | 6129 | int xfer = MIPS64_REGSIZE; |
7a076fd2 FF |
6130 | if (offset + xfer > TYPE_LENGTH (type)) |
6131 | xfer = TYPE_LENGTH (type) - offset; | |
6132 | if (mips_debug) | |
6133 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
6134 | offset, xfer, regnum); | |
ba32f989 DJ |
6135 | mips_xfer_register (gdbarch, regcache, |
6136 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 6137 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 6138 | readbuf, writebuf, offset); |
7a076fd2 FF |
6139 | } |
6140 | return RETURN_VALUE_REGISTER_CONVENTION; | |
6141 | } | |
6d82d43b AC |
6142 | } |
6143 | ||
dd824b04 DJ |
6144 | /* Floating point register management. |
6145 | ||
6146 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
6147 | 64bit operations, these early MIPS cpus treat fp register pairs | |
6148 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
6149 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
6150 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
6151 | double precision floats into two 32-bit chunks and store them in | |
6152 | consecutive fp regs. To display 64-bit floats stored in this | |
6153 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
6154 | Throw in user-configurable endianness and you have a real mess. | |
6155 | ||
6156 | The way this works is: | |
6157 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
6158 | double-precision value will be split across two logical registers. | |
6159 | The lower-numbered logical register will hold the low-order bits, | |
6160 | regardless of the processor's endianness. | |
6161 | - If we are on a 64-bit processor, and we are looking for a | |
6162 | single-precision value, it will be in the low ordered bits | |
6163 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
6164 | save slot in memory. | |
6165 | - If we are in 64-bit mode, everything is straightforward. | |
6166 | ||
6167 | Note that this code only deals with "live" registers at the top of the | |
6168 | stack. We will attempt to deal with saved registers later, when | |
025bb325 | 6169 | the raw/cooked register interface is in place. (We need a general |
dd824b04 DJ |
6170 | interface that can deal with dynamic saved register sizes -- fp |
6171 | regs could be 32 bits wide in one frame and 64 on the frame above | |
6172 | and below). */ | |
6173 | ||
6174 | /* Copy a 32-bit single-precision value from the current frame | |
6175 | into rare_buffer. */ | |
6176 | ||
6177 | static void | |
e11c53d2 | 6178 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
47a35522 | 6179 | gdb_byte *rare_buffer) |
dd824b04 | 6180 | { |
72a155b4 UW |
6181 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6182 | int raw_size = register_size (gdbarch, regno); | |
224c3ddb | 6183 | gdb_byte *raw_buffer = (gdb_byte *) alloca (raw_size); |
dd824b04 | 6184 | |
ca9d61b9 | 6185 | if (!deprecated_frame_register_read (frame, regno, raw_buffer)) |
c9f4d572 | 6186 | error (_("can't read register %d (%s)"), |
72a155b4 | 6187 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
6188 | if (raw_size == 8) |
6189 | { | |
6190 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 6191 | 32 bits. */ |
dd824b04 DJ |
6192 | int offset; |
6193 | ||
72a155b4 | 6194 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 DJ |
6195 | offset = 4; |
6196 | else | |
6197 | offset = 0; | |
6198 | ||
6199 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
6200 | } | |
6201 | else | |
6202 | { | |
6203 | memcpy (rare_buffer, raw_buffer, 4); | |
6204 | } | |
6205 | } | |
6206 | ||
6207 | /* Copy a 64-bit double-precision value from the current frame into | |
6208 | rare_buffer. This may include getting half of it from the next | |
6209 | register. */ | |
6210 | ||
6211 | static void | |
e11c53d2 | 6212 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
47a35522 | 6213 | gdb_byte *rare_buffer) |
dd824b04 | 6214 | { |
72a155b4 UW |
6215 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6216 | int raw_size = register_size (gdbarch, regno); | |
dd824b04 | 6217 | |
9c9acae0 | 6218 | if (raw_size == 8 && !mips2_fp_compat (frame)) |
dd824b04 DJ |
6219 | { |
6220 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 6221 | all 64 bits. */ |
ca9d61b9 | 6222 | if (!deprecated_frame_register_read (frame, regno, rare_buffer)) |
c9f4d572 | 6223 | error (_("can't read register %d (%s)"), |
72a155b4 | 6224 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
6225 | } |
6226 | else | |
6227 | { | |
72a155b4 | 6228 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
82e91389 | 6229 | |
72a155b4 | 6230 | if ((rawnum - mips_regnum (gdbarch)->fp0) & 1) |
dd824b04 | 6231 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
6232 | _("mips_read_fp_register_double: bad access to " |
6233 | "odd-numbered FP register")); | |
dd824b04 DJ |
6234 | |
6235 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 6236 | each register. */ |
72a155b4 | 6237 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 | 6238 | { |
e11c53d2 AC |
6239 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
6240 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 6241 | } |
361d1df0 | 6242 | else |
dd824b04 | 6243 | { |
e11c53d2 AC |
6244 | mips_read_fp_register_single (frame, regno, rare_buffer); |
6245 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
6246 | } |
6247 | } | |
6248 | } | |
6249 | ||
c906108c | 6250 | static void |
e11c53d2 AC |
6251 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
6252 | int regnum) | |
025bb325 | 6253 | { /* Do values for FP (float) regs. */ |
72a155b4 | 6254 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 6255 | gdb_byte *raw_buffer; |
8ba0dd51 UW |
6256 | std::string flt_str, dbl_str; |
6257 | ||
f69fdf9b UW |
6258 | const struct type *flt_type = builtin_type (gdbarch)->builtin_float; |
6259 | const struct type *dbl_type = builtin_type (gdbarch)->builtin_double; | |
c5aa993b | 6260 | |
224c3ddb SM |
6261 | raw_buffer |
6262 | = ((gdb_byte *) | |
6263 | alloca (2 * register_size (gdbarch, mips_regnum (gdbarch)->fp0))); | |
c906108c | 6264 | |
72a155b4 | 6265 | fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum)); |
c9f4d572 | 6266 | fprintf_filtered (file, "%*s", |
72a155b4 | 6267 | 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)), |
e11c53d2 | 6268 | ""); |
f0ef6b29 | 6269 | |
72a155b4 | 6270 | if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame)) |
c906108c | 6271 | { |
79a45b7d TT |
6272 | struct value_print_options opts; |
6273 | ||
f0ef6b29 KB |
6274 | /* 4-byte registers: Print hex and floating. Also print even |
6275 | numbered registers as doubles. */ | |
e11c53d2 | 6276 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
f69fdf9b | 6277 | flt_str = target_float_to_string (raw_buffer, flt_type, "%-17.9g"); |
c5aa993b | 6278 | |
79a45b7d | 6279 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
6280 | print_scalar_formatted (raw_buffer, |
6281 | builtin_type (gdbarch)->builtin_uint32, | |
6282 | &opts, 'w', file); | |
dd824b04 | 6283 | |
8ba0dd51 | 6284 | fprintf_filtered (file, " flt: %s", flt_str.c_str ()); |
1adad886 | 6285 | |
72a155b4 | 6286 | if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0) |
f0ef6b29 | 6287 | { |
e11c53d2 | 6288 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f69fdf9b | 6289 | dbl_str = target_float_to_string (raw_buffer, dbl_type, "%-24.17g"); |
1adad886 | 6290 | |
8ba0dd51 | 6291 | fprintf_filtered (file, " dbl: %s", dbl_str.c_str ()); |
f0ef6b29 | 6292 | } |
c906108c SS |
6293 | } |
6294 | else | |
dd824b04 | 6295 | { |
79a45b7d TT |
6296 | struct value_print_options opts; |
6297 | ||
f0ef6b29 | 6298 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 6299 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
f69fdf9b | 6300 | flt_str = target_float_to_string (raw_buffer, flt_type, "%-17.9g"); |
c906108c | 6301 | |
e11c53d2 | 6302 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f69fdf9b | 6303 | dbl_str = target_float_to_string (raw_buffer, dbl_type, "%-24.17g"); |
f0ef6b29 | 6304 | |
79a45b7d | 6305 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
6306 | print_scalar_formatted (raw_buffer, |
6307 | builtin_type (gdbarch)->builtin_uint64, | |
6308 | &opts, 'g', file); | |
f0ef6b29 | 6309 | |
8ba0dd51 UW |
6310 | fprintf_filtered (file, " flt: %s", flt_str.c_str ()); |
6311 | fprintf_filtered (file, " dbl: %s", dbl_str.c_str ()); | |
f0ef6b29 KB |
6312 | } |
6313 | } | |
6314 | ||
6315 | static void | |
e11c53d2 | 6316 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
0cc93a06 | 6317 | int regnum) |
f0ef6b29 | 6318 | { |
a4b8ebc8 | 6319 | struct gdbarch *gdbarch = get_frame_arch (frame); |
79a45b7d | 6320 | struct value_print_options opts; |
de15c4ab | 6321 | struct value *val; |
1adad886 | 6322 | |
004159a2 | 6323 | if (mips_float_register_p (gdbarch, regnum)) |
f0ef6b29 | 6324 | { |
e11c53d2 | 6325 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
6326 | return; |
6327 | } | |
6328 | ||
de15c4ab | 6329 | val = get_frame_register_value (frame, regnum); |
f0ef6b29 | 6330 | |
72a155b4 | 6331 | fputs_filtered (gdbarch_register_name (gdbarch, regnum), file); |
f0ef6b29 KB |
6332 | |
6333 | /* The problem with printing numeric register names (r26, etc.) is that | |
6334 | the user can't use them on input. Probably the best solution is to | |
6335 | fix it so that either the numeric or the funky (a2, etc.) names | |
6336 | are accepted on input. */ | |
6337 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 6338 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 6339 | else |
e11c53d2 | 6340 | fprintf_filtered (file, ": "); |
f0ef6b29 | 6341 | |
79a45b7d | 6342 | get_formatted_print_options (&opts, 'x'); |
de15c4ab | 6343 | val_print_scalar_formatted (value_type (val), |
de15c4ab PA |
6344 | value_embedded_offset (val), |
6345 | val, | |
6346 | &opts, 0, file); | |
c906108c SS |
6347 | } |
6348 | ||
1bab7383 YQ |
6349 | /* Print IEEE exception condition bits in FLAGS. */ |
6350 | ||
6351 | static void | |
6352 | print_fpu_flags (struct ui_file *file, int flags) | |
6353 | { | |
6354 | if (flags & (1 << 0)) | |
6355 | fputs_filtered (" inexact", file); | |
6356 | if (flags & (1 << 1)) | |
6357 | fputs_filtered (" uflow", file); | |
6358 | if (flags & (1 << 2)) | |
6359 | fputs_filtered (" oflow", file); | |
6360 | if (flags & (1 << 3)) | |
6361 | fputs_filtered (" div0", file); | |
6362 | if (flags & (1 << 4)) | |
6363 | fputs_filtered (" inval", file); | |
6364 | if (flags & (1 << 5)) | |
6365 | fputs_filtered (" unimp", file); | |
6366 | fputc_filtered ('\n', file); | |
6367 | } | |
6368 | ||
6369 | /* Print interesting information about the floating point processor | |
6370 | (if present) or emulator. */ | |
6371 | ||
6372 | static void | |
6373 | mips_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, | |
6374 | struct frame_info *frame, const char *args) | |
6375 | { | |
6376 | int fcsr = mips_regnum (gdbarch)->fp_control_status; | |
6377 | enum mips_fpu_type type = MIPS_FPU_TYPE (gdbarch); | |
6378 | ULONGEST fcs = 0; | |
6379 | int i; | |
6380 | ||
6381 | if (fcsr == -1 || !read_frame_register_unsigned (frame, fcsr, &fcs)) | |
6382 | type = MIPS_FPU_NONE; | |
6383 | ||
6384 | fprintf_filtered (file, "fpu type: %s\n", | |
6385 | type == MIPS_FPU_DOUBLE ? "double-precision" | |
6386 | : type == MIPS_FPU_SINGLE ? "single-precision" | |
6387 | : "none / unused"); | |
6388 | ||
6389 | if (type == MIPS_FPU_NONE) | |
6390 | return; | |
6391 | ||
6392 | fprintf_filtered (file, "reg size: %d bits\n", | |
6393 | register_size (gdbarch, mips_regnum (gdbarch)->fp0) * 8); | |
6394 | ||
6395 | fputs_filtered ("cond :", file); | |
6396 | if (fcs & (1 << 23)) | |
6397 | fputs_filtered (" 0", file); | |
6398 | for (i = 1; i <= 7; i++) | |
6399 | if (fcs & (1 << (24 + i))) | |
6400 | fprintf_filtered (file, " %d", i); | |
6401 | fputc_filtered ('\n', file); | |
6402 | ||
6403 | fputs_filtered ("cause :", file); | |
6404 | print_fpu_flags (file, (fcs >> 12) & 0x3f); | |
6405 | fputs ("mask :", stdout); | |
6406 | print_fpu_flags (file, (fcs >> 7) & 0x1f); | |
6407 | fputs ("flags :", stdout); | |
6408 | print_fpu_flags (file, (fcs >> 2) & 0x1f); | |
6409 | ||
6410 | fputs_filtered ("rounding: ", file); | |
6411 | switch (fcs & 3) | |
6412 | { | |
6413 | case 0: fputs_filtered ("nearest\n", file); break; | |
6414 | case 1: fputs_filtered ("zero\n", file); break; | |
6415 | case 2: fputs_filtered ("+inf\n", file); break; | |
6416 | case 3: fputs_filtered ("-inf\n", file); break; | |
6417 | } | |
6418 | ||
6419 | fputs_filtered ("flush :", file); | |
6420 | if (fcs & (1 << 21)) | |
6421 | fputs_filtered (" nearest", file); | |
6422 | if (fcs & (1 << 22)) | |
6423 | fputs_filtered (" override", file); | |
6424 | if (fcs & (1 << 24)) | |
6425 | fputs_filtered (" zero", file); | |
6426 | if ((fcs & (0xb << 21)) == 0) | |
6427 | fputs_filtered (" no", file); | |
6428 | fputc_filtered ('\n', file); | |
6429 | ||
6430 | fprintf_filtered (file, "nan2008 : %s\n", fcs & (1 << 18) ? "yes" : "no"); | |
6431 | fprintf_filtered (file, "abs2008 : %s\n", fcs & (1 << 19) ? "yes" : "no"); | |
6432 | fputc_filtered ('\n', file); | |
6433 | ||
6434 | default_print_float_info (gdbarch, file, frame, args); | |
6435 | } | |
6436 | ||
f0ef6b29 KB |
6437 | /* Replacement for generic do_registers_info. |
6438 | Print regs in pretty columns. */ | |
6439 | ||
6440 | static int | |
e11c53d2 AC |
6441 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
6442 | int regnum) | |
f0ef6b29 | 6443 | { |
e11c53d2 AC |
6444 | fprintf_filtered (file, " "); |
6445 | mips_print_fp_register (file, frame, regnum); | |
6446 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
6447 | return regnum + 1; |
6448 | } | |
6449 | ||
6450 | ||
025bb325 | 6451 | /* Print a row's worth of GP (int) registers, with name labels above. */ |
c906108c SS |
6452 | |
6453 | static int | |
e11c53d2 | 6454 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 6455 | int start_regnum) |
c906108c | 6456 | { |
a4b8ebc8 | 6457 | struct gdbarch *gdbarch = get_frame_arch (frame); |
025bb325 | 6458 | /* Do values for GP (int) regs. */ |
313c5961 AH |
6459 | const gdb_byte *raw_buffer; |
6460 | struct value *value; | |
025bb325 MS |
6461 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols |
6462 | per row. */ | |
c906108c | 6463 | int col, byte; |
a4b8ebc8 | 6464 | int regnum; |
c906108c | 6465 | |
025bb325 | 6466 | /* For GP registers, we print a separate row of names above the vals. */ |
a4b8ebc8 | 6467 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
6468 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
6469 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 6470 | regnum++) |
c906108c | 6471 | { |
72a155b4 | 6472 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 6473 | continue; /* unused register */ |
004159a2 | 6474 | if (mips_float_register_p (gdbarch, regnum)) |
025bb325 | 6475 | break; /* End the row: reached FP register. */ |
0cc93a06 | 6476 | /* Large registers are handled separately. */ |
72a155b4 | 6477 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
6478 | { |
6479 | if (col > 0) | |
6480 | break; /* End the row before this register. */ | |
6481 | ||
6482 | /* Print this register on a row by itself. */ | |
6483 | mips_print_register (file, frame, regnum); | |
6484 | fprintf_filtered (file, "\n"); | |
6485 | return regnum + 1; | |
6486 | } | |
d05f6826 DJ |
6487 | if (col == 0) |
6488 | fprintf_filtered (file, " "); | |
6d82d43b | 6489 | fprintf_filtered (file, |
72a155b4 UW |
6490 | mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s", |
6491 | gdbarch_register_name (gdbarch, regnum)); | |
c906108c SS |
6492 | col++; |
6493 | } | |
d05f6826 DJ |
6494 | |
6495 | if (col == 0) | |
6496 | return regnum; | |
6497 | ||
025bb325 | 6498 | /* Print the R0 to R31 names. */ |
72a155b4 | 6499 | if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS) |
f57d151a | 6500 | fprintf_filtered (file, "\n R%-4d", |
72a155b4 | 6501 | start_regnum % gdbarch_num_regs (gdbarch)); |
20e6603c AC |
6502 | else |
6503 | fprintf_filtered (file, "\n "); | |
c906108c | 6504 | |
025bb325 | 6505 | /* Now print the values in hex, 4 or 8 to the row. */ |
a4b8ebc8 | 6506 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
6507 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
6508 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 6509 | regnum++) |
c906108c | 6510 | { |
72a155b4 | 6511 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 6512 | continue; /* unused register */ |
004159a2 | 6513 | if (mips_float_register_p (gdbarch, regnum)) |
025bb325 | 6514 | break; /* End row: reached FP register. */ |
72a155b4 | 6515 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
6516 | break; /* End row: large register. */ |
6517 | ||
c906108c | 6518 | /* OK: get the data in raw format. */ |
313c5961 AH |
6519 | value = get_frame_register_value (frame, regnum); |
6520 | if (value_optimized_out (value) | |
6521 | || !value_entirely_available (value)) | |
325c9fd4 JB |
6522 | { |
6523 | fprintf_filtered (file, "%*s ", | |
6524 | (int) mips_abi_regsize (gdbarch) * 2, | |
6525 | (mips_abi_regsize (gdbarch) == 4 ? "<unavl>" | |
6526 | : "<unavailable>")); | |
6527 | col++; | |
6528 | continue; | |
6529 | } | |
313c5961 | 6530 | raw_buffer = value_contents_all (value); |
c906108c | 6531 | /* pad small registers */ |
4246e332 | 6532 | for (byte = 0; |
72a155b4 UW |
6533 | byte < (mips_abi_regsize (gdbarch) |
6534 | - register_size (gdbarch, regnum)); byte++) | |
428544e8 | 6535 | fprintf_filtered (file, " "); |
025bb325 | 6536 | /* Now print the register value in hex, endian order. */ |
72a155b4 | 6537 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b | 6538 | for (byte = |
72a155b4 UW |
6539 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
6540 | byte < register_size (gdbarch, regnum); byte++) | |
47a35522 | 6541 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
c906108c | 6542 | else |
72a155b4 | 6543 | for (byte = register_size (gdbarch, regnum) - 1; |
6d82d43b | 6544 | byte >= 0; byte--) |
47a35522 | 6545 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
e11c53d2 | 6546 | fprintf_filtered (file, " "); |
c906108c SS |
6547 | col++; |
6548 | } | |
025bb325 | 6549 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 6550 | fprintf_filtered (file, "\n"); |
c906108c SS |
6551 | |
6552 | return regnum; | |
6553 | } | |
6554 | ||
025bb325 | 6555 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */ |
c906108c | 6556 | |
bf1f5b4c | 6557 | static void |
e11c53d2 AC |
6558 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
6559 | struct frame_info *frame, int regnum, int all) | |
c906108c | 6560 | { |
025bb325 | 6561 | if (regnum != -1) /* Do one specified register. */ |
c906108c | 6562 | { |
72a155b4 UW |
6563 | gdb_assert (regnum >= gdbarch_num_regs (gdbarch)); |
6564 | if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
8a3fe4f8 | 6565 | error (_("Not a valid register for the current processor type")); |
c906108c | 6566 | |
0cc93a06 | 6567 | mips_print_register (file, frame, regnum); |
e11c53d2 | 6568 | fprintf_filtered (file, "\n"); |
c906108c | 6569 | } |
c5aa993b | 6570 | else |
025bb325 | 6571 | /* Do all (or most) registers. */ |
c906108c | 6572 | { |
72a155b4 UW |
6573 | regnum = gdbarch_num_regs (gdbarch); |
6574 | while (regnum < gdbarch_num_regs (gdbarch) | |
6575 | + gdbarch_num_pseudo_regs (gdbarch)) | |
c906108c | 6576 | { |
004159a2 | 6577 | if (mips_float_register_p (gdbarch, regnum)) |
e11c53d2 | 6578 | { |
025bb325 | 6579 | if (all) /* True for "INFO ALL-REGISTERS" command. */ |
e11c53d2 AC |
6580 | regnum = print_fp_register_row (file, frame, regnum); |
6581 | else | |
025bb325 | 6582 | regnum += MIPS_NUMREGS; /* Skip floating point regs. */ |
e11c53d2 | 6583 | } |
c906108c | 6584 | else |
e11c53d2 | 6585 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
6586 | } |
6587 | } | |
6588 | } | |
6589 | ||
63807e1d | 6590 | static int |
3352ef37 AC |
6591 | mips_single_step_through_delay (struct gdbarch *gdbarch, |
6592 | struct frame_info *frame) | |
c906108c | 6593 | { |
3352ef37 | 6594 | CORE_ADDR pc = get_frame_pc (frame); |
4cc0665f MR |
6595 | enum mips_isa isa; |
6596 | ULONGEST insn; | |
4cc0665f MR |
6597 | int size; |
6598 | ||
6599 | if ((mips_pc_is_mips (pc) | |
ab50adb6 | 6600 | && !mips32_insn_at_pc_has_delay_slot (gdbarch, pc)) |
4cc0665f | 6601 | || (mips_pc_is_micromips (gdbarch, pc) |
ab50adb6 | 6602 | && !micromips_insn_at_pc_has_delay_slot (gdbarch, pc, 0)) |
4cc0665f | 6603 | || (mips_pc_is_mips16 (gdbarch, pc) |
ab50adb6 | 6604 | && !mips16_insn_at_pc_has_delay_slot (gdbarch, pc, 0))) |
06648491 MK |
6605 | return 0; |
6606 | ||
4cc0665f MR |
6607 | isa = mips_pc_isa (gdbarch, pc); |
6608 | /* _has_delay_slot above will have validated the read. */ | |
6609 | insn = mips_fetch_instruction (gdbarch, isa, pc, NULL); | |
6610 | size = mips_insn_size (isa, insn); | |
8b86c959 YQ |
6611 | |
6612 | const address_space *aspace = get_frame_address_space (frame); | |
6613 | ||
4cc0665f | 6614 | return breakpoint_here_p (aspace, pc + size) != no_breakpoint_here; |
c906108c SS |
6615 | } |
6616 | ||
6d82d43b AC |
6617 | /* To skip prologues, I use this predicate. Returns either PC itself |
6618 | if the code at PC does not look like a function prologue; otherwise | |
6619 | returns an address that (if we're lucky) follows the prologue. If | |
6620 | LENIENT, then we must skip everything which is involved in setting | |
6621 | up the frame (it's OK to skip more, just so long as we don't skip | |
6622 | anything which might clobber the registers which are being saved. | |
6623 | We must skip more in the case where part of the prologue is in the | |
6624 | delay slot of a non-prologue instruction). */ | |
6625 | ||
6626 | static CORE_ADDR | |
6093d2eb | 6627 | mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
6d82d43b | 6628 | { |
8b622e6a AC |
6629 | CORE_ADDR limit_pc; |
6630 | CORE_ADDR func_addr; | |
6631 | ||
6d82d43b AC |
6632 | /* See if we can determine the end of the prologue via the symbol table. |
6633 | If so, then return either PC, or the PC after the prologue, whichever | |
6634 | is greater. */ | |
8b622e6a AC |
6635 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
6636 | { | |
d80b854b UW |
6637 | CORE_ADDR post_prologue_pc |
6638 | = skip_prologue_using_sal (gdbarch, func_addr); | |
8b622e6a | 6639 | if (post_prologue_pc != 0) |
325fac50 | 6640 | return std::max (pc, post_prologue_pc); |
8b622e6a | 6641 | } |
6d82d43b AC |
6642 | |
6643 | /* Can't determine prologue from the symbol table, need to examine | |
6644 | instructions. */ | |
6645 | ||
98b4dd94 JB |
6646 | /* Find an upper limit on the function prologue using the debug |
6647 | information. If the debug information could not be used to provide | |
6648 | that bound, then use an arbitrary large number as the upper bound. */ | |
d80b854b | 6649 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
98b4dd94 JB |
6650 | if (limit_pc == 0) |
6651 | limit_pc = pc + 100; /* Magic. */ | |
6652 | ||
4cc0665f | 6653 | if (mips_pc_is_mips16 (gdbarch, pc)) |
e17a4113 | 6654 | return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
4cc0665f MR |
6655 | else if (mips_pc_is_micromips (gdbarch, pc)) |
6656 | return micromips_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); | |
6d82d43b | 6657 | else |
e17a4113 | 6658 | return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
88658117 AC |
6659 | } |
6660 | ||
c9cf6e20 MG |
6661 | /* Implement the stack_frame_destroyed_p gdbarch method (32-bit version). |
6662 | This is a helper function for mips_stack_frame_destroyed_p. */ | |
6663 | ||
97ab0fdd | 6664 | static int |
c9cf6e20 | 6665 | mips32_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
6666 | { |
6667 | CORE_ADDR func_addr = 0, func_end = 0; | |
6668 | ||
6669 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
6670 | { | |
6671 | /* The MIPS epilogue is max. 12 bytes long. */ | |
6672 | CORE_ADDR addr = func_end - 12; | |
6673 | ||
6674 | if (addr < func_addr + 4) | |
6675 | addr = func_addr + 4; | |
6676 | if (pc < addr) | |
6677 | return 0; | |
6678 | ||
6679 | for (; pc < func_end; pc += MIPS_INSN32_SIZE) | |
6680 | { | |
6681 | unsigned long high_word; | |
6682 | unsigned long inst; | |
6683 | ||
4cc0665f | 6684 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
97ab0fdd MR |
6685 | high_word = (inst >> 16) & 0xffff; |
6686 | ||
6687 | if (high_word != 0x27bd /* addiu $sp,$sp,offset */ | |
6688 | && high_word != 0x67bd /* daddiu $sp,$sp,offset */ | |
6689 | && inst != 0x03e00008 /* jr $ra */ | |
6690 | && inst != 0x00000000) /* nop */ | |
6691 | return 0; | |
6692 | } | |
6693 | ||
6694 | return 1; | |
6695 | } | |
6696 | ||
6697 | return 0; | |
6698 | } | |
6699 | ||
c9cf6e20 MG |
6700 | /* Implement the stack_frame_destroyed_p gdbarch method (microMIPS version). |
6701 | This is a helper function for mips_stack_frame_destroyed_p. */ | |
4cc0665f MR |
6702 | |
6703 | static int | |
c9cf6e20 | 6704 | micromips_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
4cc0665f MR |
6705 | { |
6706 | CORE_ADDR func_addr = 0; | |
6707 | CORE_ADDR func_end = 0; | |
6708 | CORE_ADDR addr; | |
6709 | ULONGEST insn; | |
6710 | long offset; | |
6711 | int dreg; | |
6712 | int sreg; | |
6713 | int loc; | |
6714 | ||
6715 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
6716 | return 0; | |
6717 | ||
6718 | /* The microMIPS epilogue is max. 12 bytes long. */ | |
6719 | addr = func_end - 12; | |
6720 | ||
6721 | if (addr < func_addr + 2) | |
6722 | addr = func_addr + 2; | |
6723 | if (pc < addr) | |
6724 | return 0; | |
6725 | ||
6726 | for (; pc < func_end; pc += loc) | |
6727 | { | |
6728 | loc = 0; | |
6729 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
6730 | loc += MIPS_INSN16_SIZE; | |
6731 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
6732 | { | |
4cc0665f MR |
6733 | /* 32-bit instructions. */ |
6734 | case 2 * MIPS_INSN16_SIZE: | |
6735 | insn <<= 16; | |
6736 | insn |= mips_fetch_instruction (gdbarch, | |
6737 | ISA_MICROMIPS, pc + loc, NULL); | |
6738 | loc += MIPS_INSN16_SIZE; | |
6739 | switch (micromips_op (insn >> 16)) | |
6740 | { | |
6741 | case 0xc: /* ADDIU: bits 001100 */ | |
6742 | case 0x17: /* DADDIU: bits 010111 */ | |
6743 | sreg = b0s5_reg (insn >> 16); | |
6744 | dreg = b5s5_reg (insn >> 16); | |
6745 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
6746 | if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM | |
6747 | /* (D)ADDIU $sp, imm */ | |
6748 | && offset >= 0) | |
6749 | break; | |
6750 | return 0; | |
6751 | ||
6752 | default: | |
6753 | return 0; | |
6754 | } | |
6755 | break; | |
6756 | ||
6757 | /* 16-bit instructions. */ | |
6758 | case MIPS_INSN16_SIZE: | |
6759 | switch (micromips_op (insn)) | |
6760 | { | |
6761 | case 0x3: /* MOVE: bits 000011 */ | |
6762 | sreg = b0s5_reg (insn); | |
6763 | dreg = b5s5_reg (insn); | |
6764 | if (sreg == 0 && dreg == 0) | |
6765 | /* MOVE $zero, $zero aka NOP */ | |
6766 | break; | |
6767 | return 0; | |
6768 | ||
6769 | case 0x11: /* POOL16C: bits 010001 */ | |
6770 | if (b5s5_op (insn) == 0x18 | |
6771 | /* JRADDIUSP: bits 010011 11000 */ | |
6772 | || (b5s5_op (insn) == 0xd | |
6773 | /* JRC: bits 010011 01101 */ | |
6774 | && b0s5_reg (insn) == MIPS_RA_REGNUM)) | |
6775 | /* JRC $ra */ | |
6776 | break; | |
6777 | return 0; | |
6778 | ||
6779 | case 0x13: /* POOL16D: bits 010011 */ | |
6780 | offset = micromips_decode_imm9 (b1s9_imm (insn)); | |
6781 | if ((insn & 0x1) == 0x1 | |
6782 | /* ADDIUSP: bits 010011 1 */ | |
6783 | && offset > 0) | |
6784 | break; | |
6785 | return 0; | |
6786 | ||
6787 | default: | |
6788 | return 0; | |
6789 | } | |
6790 | } | |
6791 | } | |
6792 | ||
6793 | return 1; | |
6794 | } | |
6795 | ||
c9cf6e20 MG |
6796 | /* Implement the stack_frame_destroyed_p gdbarch method (16-bit version). |
6797 | This is a helper function for mips_stack_frame_destroyed_p. */ | |
6798 | ||
97ab0fdd | 6799 | static int |
c9cf6e20 | 6800 | mips16_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
6801 | { |
6802 | CORE_ADDR func_addr = 0, func_end = 0; | |
6803 | ||
6804 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
6805 | { | |
6806 | /* The MIPS epilogue is max. 12 bytes long. */ | |
6807 | CORE_ADDR addr = func_end - 12; | |
6808 | ||
6809 | if (addr < func_addr + 4) | |
6810 | addr = func_addr + 4; | |
6811 | if (pc < addr) | |
6812 | return 0; | |
6813 | ||
6814 | for (; pc < func_end; pc += MIPS_INSN16_SIZE) | |
6815 | { | |
6816 | unsigned short inst; | |
6817 | ||
4cc0665f | 6818 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc, NULL); |
97ab0fdd MR |
6819 | |
6820 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
6821 | continue; | |
6822 | ||
6823 | if (inst != 0x6300 /* addiu $sp,offset */ | |
6824 | && inst != 0xfb00 /* daddiu $sp,$sp,offset */ | |
6825 | && inst != 0xe820 /* jr $ra */ | |
6826 | && inst != 0xe8a0 /* jrc $ra */ | |
6827 | && inst != 0x6500) /* nop */ | |
6828 | return 0; | |
6829 | } | |
6830 | ||
6831 | return 1; | |
6832 | } | |
6833 | ||
6834 | return 0; | |
6835 | } | |
6836 | ||
c9cf6e20 MG |
6837 | /* Implement the stack_frame_destroyed_p gdbarch method. |
6838 | ||
6839 | The epilogue is defined here as the area at the end of a function, | |
97ab0fdd | 6840 | after an instruction which destroys the function's stack frame. */ |
c9cf6e20 | 6841 | |
97ab0fdd | 6842 | static int |
c9cf6e20 | 6843 | mips_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd | 6844 | { |
4cc0665f | 6845 | if (mips_pc_is_mips16 (gdbarch, pc)) |
c9cf6e20 | 6846 | return mips16_stack_frame_destroyed_p (gdbarch, pc); |
4cc0665f | 6847 | else if (mips_pc_is_micromips (gdbarch, pc)) |
c9cf6e20 | 6848 | return micromips_stack_frame_destroyed_p (gdbarch, pc); |
97ab0fdd | 6849 | else |
c9cf6e20 | 6850 | return mips32_stack_frame_destroyed_p (gdbarch, pc); |
97ab0fdd MR |
6851 | } |
6852 | ||
025bb325 | 6853 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
a5ea2558 AC |
6854 | used for all MIPS-specific commands. */ |
6855 | ||
a5ea2558 | 6856 | static void |
981a3fb3 | 6857 | show_mips_command (const char *args, int from_tty) |
a5ea2558 AC |
6858 | { |
6859 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
6860 | } | |
6861 | ||
a5ea2558 | 6862 | static void |
981a3fb3 | 6863 | set_mips_command (const char *args, int from_tty) |
a5ea2558 | 6864 | { |
6d82d43b AC |
6865 | printf_unfiltered |
6866 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
6867 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
6868 | } | |
6869 | ||
c906108c SS |
6870 | /* Commands to show/set the MIPS FPU type. */ |
6871 | ||
c906108c | 6872 | static void |
bd4c9dfe | 6873 | show_mipsfpu_command (const char *args, int from_tty) |
c906108c | 6874 | { |
a121b7c1 | 6875 | const char *fpu; |
6ca0852e | 6876 | |
f5656ead | 6877 | if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips) |
6ca0852e UW |
6878 | { |
6879 | printf_unfiltered | |
6880 | ("The MIPS floating-point coprocessor is unknown " | |
6881 | "because the current architecture is not MIPS.\n"); | |
6882 | return; | |
6883 | } | |
6884 | ||
f5656ead | 6885 | switch (MIPS_FPU_TYPE (target_gdbarch ())) |
c906108c SS |
6886 | { |
6887 | case MIPS_FPU_SINGLE: | |
6888 | fpu = "single-precision"; | |
6889 | break; | |
6890 | case MIPS_FPU_DOUBLE: | |
6891 | fpu = "double-precision"; | |
6892 | break; | |
6893 | case MIPS_FPU_NONE: | |
6894 | fpu = "absent (none)"; | |
6895 | break; | |
93d56215 | 6896 | default: |
e2e0b3e5 | 6897 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c SS |
6898 | } |
6899 | if (mips_fpu_type_auto) | |
025bb325 MS |
6900 | printf_unfiltered ("The MIPS floating-point coprocessor " |
6901 | "is set automatically (currently %s)\n", | |
6902 | fpu); | |
c906108c | 6903 | else |
6d82d43b AC |
6904 | printf_unfiltered |
6905 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
6906 | } |
6907 | ||
6908 | ||
c906108c | 6909 | static void |
981a3fb3 | 6910 | set_mipsfpu_command (const char *args, int from_tty) |
c906108c | 6911 | { |
025bb325 MS |
6912 | printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", " |
6913 | "\"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
6914 | show_mipsfpu_command (args, from_tty); |
6915 | } | |
6916 | ||
c906108c | 6917 | static void |
bd4c9dfe | 6918 | set_mipsfpu_single_command (const char *args, int from_tty) |
c906108c | 6919 | { |
8d5838b5 AC |
6920 | struct gdbarch_info info; |
6921 | gdbarch_info_init (&info); | |
c906108c SS |
6922 | mips_fpu_type = MIPS_FPU_SINGLE; |
6923 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
6924 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
6925 | instead of relying on globals. Doing that would let generic code | |
6926 | handle the search for this specific architecture. */ | |
6927 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 6928 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
6929 | } |
6930 | ||
c906108c | 6931 | static void |
bd4c9dfe | 6932 | set_mipsfpu_double_command (const char *args, int from_tty) |
c906108c | 6933 | { |
8d5838b5 AC |
6934 | struct gdbarch_info info; |
6935 | gdbarch_info_init (&info); | |
c906108c SS |
6936 | mips_fpu_type = MIPS_FPU_DOUBLE; |
6937 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
6938 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
6939 | instead of relying on globals. Doing that would let generic code | |
6940 | handle the search for this specific architecture. */ | |
6941 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 6942 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
6943 | } |
6944 | ||
c906108c | 6945 | static void |
bd4c9dfe | 6946 | set_mipsfpu_none_command (const char *args, int from_tty) |
c906108c | 6947 | { |
8d5838b5 AC |
6948 | struct gdbarch_info info; |
6949 | gdbarch_info_init (&info); | |
c906108c SS |
6950 | mips_fpu_type = MIPS_FPU_NONE; |
6951 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
6952 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
6953 | instead of relying on globals. Doing that would let generic code | |
6954 | handle the search for this specific architecture. */ | |
6955 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 6956 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
6957 | } |
6958 | ||
c906108c | 6959 | static void |
bd4c9dfe | 6960 | set_mipsfpu_auto_command (const char *args, int from_tty) |
c906108c SS |
6961 | { |
6962 | mips_fpu_type_auto = 1; | |
6963 | } | |
6964 | ||
c906108c SS |
6965 | /* Just like reinit_frame_cache, but with the right arguments to be |
6966 | callable as an sfunc. */ | |
6967 | ||
6968 | static void | |
eb4c3f4a | 6969 | reinit_frame_cache_sfunc (const char *args, int from_tty, |
acdb74a0 | 6970 | struct cmd_list_element *c) |
c906108c SS |
6971 | { |
6972 | reinit_frame_cache (); | |
6973 | } | |
6974 | ||
a89aa300 AC |
6975 | static int |
6976 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 6977 | { |
e47ad6c0 YQ |
6978 | gdb_disassembler *di |
6979 | = static_cast<gdb_disassembler *>(info->application_data); | |
6980 | struct gdbarch *gdbarch = di->arch (); | |
4cc0665f | 6981 | |
d31431ed AC |
6982 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
6983 | disassembler needs to be able to locally determine the ISA, and | |
6984 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
6985 | work. */ | |
4cc0665f | 6986 | if (mips_pc_is_mips16 (gdbarch, memaddr)) |
ec4045ea | 6987 | info->mach = bfd_mach_mips16; |
4cc0665f MR |
6988 | else if (mips_pc_is_micromips (gdbarch, memaddr)) |
6989 | info->mach = bfd_mach_mips_micromips; | |
c906108c SS |
6990 | |
6991 | /* Round down the instruction address to the appropriate boundary. */ | |
4cc0665f MR |
6992 | memaddr &= (info->mach == bfd_mach_mips16 |
6993 | || info->mach == bfd_mach_mips_micromips) ? ~1 : ~3; | |
c5aa993b | 6994 | |
e5ab0dce | 6995 | /* Set the disassembler options. */ |
9dae60cc | 6996 | if (!info->disassembler_options) |
e5ab0dce AC |
6997 | /* This string is not recognized explicitly by the disassembler, |
6998 | but it tells the disassembler to not try to guess the ABI from | |
6999 | the bfd elf headers, such that, if the user overrides the ABI | |
7000 | of a program linked as NewABI, the disassembly will follow the | |
7001 | register naming conventions specified by the user. */ | |
7002 | info->disassembler_options = "gpr-names=32"; | |
7003 | ||
6394c606 | 7004 | return default_print_insn (memaddr, info); |
c906108c SS |
7005 | } |
7006 | ||
9dae60cc UW |
7007 | static int |
7008 | gdb_print_insn_mips_n32 (bfd_vma memaddr, struct disassemble_info *info) | |
7009 | { | |
7010 | /* Set up the disassembler info, so that we get the right | |
7011 | register names from libopcodes. */ | |
7012 | info->disassembler_options = "gpr-names=n32"; | |
7013 | info->flavour = bfd_target_elf_flavour; | |
7014 | ||
7015 | return gdb_print_insn_mips (memaddr, info); | |
7016 | } | |
7017 | ||
7018 | static int | |
7019 | gdb_print_insn_mips_n64 (bfd_vma memaddr, struct disassemble_info *info) | |
7020 | { | |
7021 | /* Set up the disassembler info, so that we get the right | |
7022 | register names from libopcodes. */ | |
7023 | info->disassembler_options = "gpr-names=64"; | |
7024 | info->flavour = bfd_target_elf_flavour; | |
7025 | ||
7026 | return gdb_print_insn_mips (memaddr, info); | |
7027 | } | |
7028 | ||
cd6c3b4f YQ |
7029 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ |
7030 | ||
d19280ad YQ |
7031 | static int |
7032 | mips_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
c906108c | 7033 | { |
4cc0665f MR |
7034 | CORE_ADDR pc = *pcptr; |
7035 | ||
d19280ad | 7036 | if (mips_pc_is_mips16 (gdbarch, pc)) |
c906108c | 7037 | { |
d19280ad YQ |
7038 | *pcptr = unmake_compact_addr (pc); |
7039 | return MIPS_BP_KIND_MIPS16; | |
7040 | } | |
7041 | else if (mips_pc_is_micromips (gdbarch, pc)) | |
7042 | { | |
7043 | ULONGEST insn; | |
7044 | int status; | |
c906108c | 7045 | |
d19280ad YQ |
7046 | *pcptr = unmake_compact_addr (pc); |
7047 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status); | |
7048 | if (status || (mips_insn_size (ISA_MICROMIPS, insn) == 2)) | |
7049 | return MIPS_BP_KIND_MICROMIPS16; | |
7050 | else | |
7051 | return MIPS_BP_KIND_MICROMIPS32; | |
c906108c SS |
7052 | } |
7053 | else | |
d19280ad YQ |
7054 | return MIPS_BP_KIND_MIPS32; |
7055 | } | |
7056 | ||
cd6c3b4f YQ |
7057 | /* Implement the sw_breakpoint_from_kind gdbarch method. */ |
7058 | ||
d19280ad YQ |
7059 | static const gdb_byte * |
7060 | mips_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) | |
7061 | { | |
7062 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
7063 | ||
7064 | switch (kind) | |
c906108c | 7065 | { |
d19280ad YQ |
7066 | case MIPS_BP_KIND_MIPS16: |
7067 | { | |
7068 | static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; | |
7069 | static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; | |
7070 | ||
7071 | *size = 2; | |
7072 | if (byte_order_for_code == BFD_ENDIAN_BIG) | |
7073 | return mips16_big_breakpoint; | |
7074 | else | |
c906108c | 7075 | return mips16_little_breakpoint; |
d19280ad YQ |
7076 | } |
7077 | case MIPS_BP_KIND_MICROMIPS16: | |
7078 | { | |
7079 | static gdb_byte micromips16_big_breakpoint[] = { 0x46, 0x85 }; | |
7080 | static gdb_byte micromips16_little_breakpoint[] = { 0x85, 0x46 }; | |
7081 | ||
7082 | *size = 2; | |
7083 | ||
7084 | if (byte_order_for_code == BFD_ENDIAN_BIG) | |
7085 | return micromips16_big_breakpoint; | |
7086 | else | |
7087 | return micromips16_little_breakpoint; | |
7088 | } | |
7089 | case MIPS_BP_KIND_MICROMIPS32: | |
7090 | { | |
7091 | static gdb_byte micromips32_big_breakpoint[] = { 0, 0x5, 0, 0x7 }; | |
7092 | static gdb_byte micromips32_little_breakpoint[] = { 0x5, 0, 0x7, 0 }; | |
7093 | ||
7094 | *size = 4; | |
7095 | if (byte_order_for_code == BFD_ENDIAN_BIG) | |
7096 | return micromips32_big_breakpoint; | |
7097 | else | |
7098 | return micromips32_little_breakpoint; | |
7099 | } | |
7100 | case MIPS_BP_KIND_MIPS32: | |
7101 | { | |
7102 | static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; | |
7103 | static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; | |
c906108c | 7104 | |
d19280ad YQ |
7105 | *size = 4; |
7106 | if (byte_order_for_code == BFD_ENDIAN_BIG) | |
7107 | return big_breakpoint; | |
7108 | else | |
7e3d947d | 7109 | return little_breakpoint; |
d19280ad YQ |
7110 | } |
7111 | default: | |
7112 | gdb_assert_not_reached ("unexpected mips breakpoint kind"); | |
7113 | }; | |
c906108c SS |
7114 | } |
7115 | ||
ab50adb6 MR |
7116 | /* Return non-zero if the standard MIPS instruction INST has a branch |
7117 | delay slot (i.e. it is a jump or branch instruction). This function | |
7118 | is based on mips32_next_pc. */ | |
c8cef75f MR |
7119 | |
7120 | static int | |
ab50adb6 | 7121 | mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, ULONGEST inst) |
c8cef75f | 7122 | { |
c8cef75f | 7123 | int op; |
a385295e MR |
7124 | int rs; |
7125 | int rt; | |
c8cef75f | 7126 | |
c8cef75f MR |
7127 | op = itype_op (inst); |
7128 | if ((inst & 0xe0000000) != 0) | |
a385295e MR |
7129 | { |
7130 | rs = itype_rs (inst); | |
7131 | rt = itype_rt (inst); | |
f94363d7 AP |
7132 | return (is_octeon_bbit_op (op, gdbarch) |
7133 | || op >> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ | |
a385295e MR |
7134 | || op == 29 /* JALX: bits 011101 */ |
7135 | || (op == 17 | |
7136 | && (rs == 8 | |
c8cef75f | 7137 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
a385295e MR |
7138 | || (rs == 9 && (rt & 0x2) == 0) |
7139 | /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */ | |
7140 | || (rs == 10 && (rt & 0x2) == 0)))); | |
7141 | /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */ | |
7142 | } | |
c8cef75f MR |
7143 | else |
7144 | switch (op & 0x07) /* extract bits 28,27,26 */ | |
7145 | { | |
7146 | case 0: /* SPECIAL */ | |
7147 | op = rtype_funct (inst); | |
7148 | return (op == 8 /* JR */ | |
7149 | || op == 9); /* JALR */ | |
7150 | break; /* end SPECIAL */ | |
7151 | case 1: /* REGIMM */ | |
a385295e MR |
7152 | rs = itype_rs (inst); |
7153 | rt = itype_rt (inst); /* branch condition */ | |
7154 | return ((rt & 0xc) == 0 | |
c8cef75f MR |
7155 | /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */ |
7156 | /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */ | |
a385295e MR |
7157 | || ((rt & 0x1e) == 0x1c && rs == 0)); |
7158 | /* BPOSGE32, BPOSGE64: bits 1110x */ | |
c8cef75f MR |
7159 | break; /* end REGIMM */ |
7160 | default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */ | |
7161 | return 1; | |
7162 | break; | |
7163 | } | |
7164 | } | |
7165 | ||
ab50adb6 MR |
7166 | /* Return non-zero if a standard MIPS instruction at ADDR has a branch |
7167 | delay slot (i.e. it is a jump or branch instruction). */ | |
c8cef75f | 7168 | |
4cc0665f | 7169 | static int |
ab50adb6 | 7170 | mips32_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr) |
4cc0665f MR |
7171 | { |
7172 | ULONGEST insn; | |
7173 | int status; | |
7174 | ||
ab50adb6 | 7175 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, addr, &status); |
4cc0665f MR |
7176 | if (status) |
7177 | return 0; | |
7178 | ||
ab50adb6 MR |
7179 | return mips32_instruction_has_delay_slot (gdbarch, insn); |
7180 | } | |
4cc0665f | 7181 | |
ab50adb6 MR |
7182 | /* Return non-zero if the microMIPS instruction INSN, comprising the |
7183 | 16-bit major opcode word in the high 16 bits and any second word | |
7184 | in the low 16 bits, has a branch delay slot (i.e. it is a non-compact | |
7185 | jump or branch instruction). The instruction must be 32-bit if | |
7186 | MUSTBE32 is set or can be any instruction otherwise. */ | |
7187 | ||
7188 | static int | |
7189 | micromips_instruction_has_delay_slot (ULONGEST insn, int mustbe32) | |
7190 | { | |
7191 | ULONGEST major = insn >> 16; | |
4cc0665f | 7192 | |
ab50adb6 MR |
7193 | switch (micromips_op (major)) |
7194 | { | |
7195 | /* 16-bit instructions. */ | |
7196 | case 0x33: /* B16: bits 110011 */ | |
7197 | case 0x2b: /* BNEZ16: bits 101011 */ | |
7198 | case 0x23: /* BEQZ16: bits 100011 */ | |
7199 | return !mustbe32; | |
7200 | case 0x11: /* POOL16C: bits 010001 */ | |
7201 | return (!mustbe32 | |
7202 | && ((b5s5_op (major) == 0xc | |
7203 | /* JR16: bits 010001 01100 */ | |
7204 | || (b5s5_op (major) & 0x1e) == 0xe))); | |
7205 | /* JALR16, JALRS16: bits 010001 0111x */ | |
7206 | /* 32-bit instructions. */ | |
7207 | case 0x3d: /* JAL: bits 111101 */ | |
7208 | case 0x3c: /* JALX: bits 111100 */ | |
7209 | case 0x35: /* J: bits 110101 */ | |
7210 | case 0x2d: /* BNE: bits 101101 */ | |
7211 | case 0x25: /* BEQ: bits 100101 */ | |
7212 | case 0x1d: /* JALS: bits 011101 */ | |
7213 | return 1; | |
7214 | case 0x10: /* POOL32I: bits 010000 */ | |
7215 | return ((b5s5_op (major) & 0x1c) == 0x0 | |
4cc0665f | 7216 | /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */ |
ab50adb6 | 7217 | || (b5s5_op (major) & 0x1d) == 0x4 |
4cc0665f | 7218 | /* BLEZ, BGTZ: bits 010000 001x0 */ |
ab50adb6 | 7219 | || (b5s5_op (major) & 0x1d) == 0x11 |
4cc0665f | 7220 | /* BLTZALS, BGEZALS: bits 010000 100x1 */ |
ab50adb6 MR |
7221 | || ((b5s5_op (major) & 0x1e) == 0x14 |
7222 | && (major & 0x3) == 0x0) | |
4cc0665f | 7223 | /* BC2F, BC2T: bits 010000 1010x xxx00 */ |
ab50adb6 | 7224 | || (b5s5_op (major) & 0x1e) == 0x1a |
4cc0665f | 7225 | /* BPOSGE64, BPOSGE32: bits 010000 1101x */ |
ab50adb6 MR |
7226 | || ((b5s5_op (major) & 0x1e) == 0x1c |
7227 | && (major & 0x3) == 0x0) | |
4cc0665f | 7228 | /* BC1F, BC1T: bits 010000 1110x xxx00 */ |
ab50adb6 MR |
7229 | || ((b5s5_op (major) & 0x1c) == 0x1c |
7230 | && (major & 0x3) == 0x1)); | |
4cc0665f | 7231 | /* BC1ANY*: bits 010000 111xx xxx01 */ |
ab50adb6 MR |
7232 | case 0x0: /* POOL32A: bits 000000 */ |
7233 | return (b0s6_op (insn) == 0x3c | |
7234 | /* POOL32Axf: bits 000000 ... 111100 */ | |
7235 | && (b6s10_ext (insn) & 0x2bf) == 0x3c); | |
7236 | /* JALR, JALR.HB: 000000 000x111100 111100 */ | |
7237 | /* JALRS, JALRS.HB: 000000 010x111100 111100 */ | |
7238 | default: | |
7239 | return 0; | |
7240 | } | |
4cc0665f MR |
7241 | } |
7242 | ||
ab50adb6 | 7243 | /* Return non-zero if a microMIPS instruction at ADDR has a branch delay |
ae790652 MR |
7244 | slot (i.e. it is a non-compact jump instruction). The instruction |
7245 | must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */ | |
7246 | ||
c8cef75f | 7247 | static int |
ab50adb6 MR |
7248 | micromips_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, |
7249 | CORE_ADDR addr, int mustbe32) | |
c8cef75f | 7250 | { |
ab50adb6 | 7251 | ULONGEST insn; |
c8cef75f | 7252 | int status; |
3f7f3650 | 7253 | int size; |
c8cef75f | 7254 | |
ab50adb6 | 7255 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status); |
c8cef75f MR |
7256 | if (status) |
7257 | return 0; | |
3f7f3650 | 7258 | size = mips_insn_size (ISA_MICROMIPS, insn); |
ab50adb6 | 7259 | insn <<= 16; |
3f7f3650 | 7260 | if (size == 2 * MIPS_INSN16_SIZE) |
ab50adb6 MR |
7261 | { |
7262 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status); | |
7263 | if (status) | |
7264 | return 0; | |
7265 | } | |
7266 | ||
7267 | return micromips_instruction_has_delay_slot (insn, mustbe32); | |
7268 | } | |
c8cef75f | 7269 | |
ab50adb6 MR |
7270 | /* Return non-zero if the MIPS16 instruction INST, which must be |
7271 | a 32-bit instruction if MUSTBE32 is set or can be any instruction | |
7272 | otherwise, has a branch delay slot (i.e. it is a non-compact jump | |
7273 | instruction). This function is based on mips16_next_pc. */ | |
7274 | ||
7275 | static int | |
7276 | mips16_instruction_has_delay_slot (unsigned short inst, int mustbe32) | |
7277 | { | |
ae790652 MR |
7278 | if ((inst & 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */ |
7279 | return !mustbe32; | |
c8cef75f MR |
7280 | return (inst & 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */ |
7281 | } | |
7282 | ||
ab50adb6 MR |
7283 | /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay |
7284 | slot (i.e. it is a non-compact jump instruction). The instruction | |
7285 | must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */ | |
7286 | ||
7287 | static int | |
7288 | mips16_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, | |
7289 | CORE_ADDR addr, int mustbe32) | |
7290 | { | |
7291 | unsigned short insn; | |
7292 | int status; | |
7293 | ||
7294 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS16, addr, &status); | |
7295 | if (status) | |
7296 | return 0; | |
7297 | ||
7298 | return mips16_instruction_has_delay_slot (insn, mustbe32); | |
7299 | } | |
7300 | ||
c8cef75f MR |
7301 | /* Calculate the starting address of the MIPS memory segment BPADDR is in. |
7302 | This assumes KSSEG exists. */ | |
7303 | ||
7304 | static CORE_ADDR | |
7305 | mips_segment_boundary (CORE_ADDR bpaddr) | |
7306 | { | |
7307 | CORE_ADDR mask = CORE_ADDR_MAX; | |
7308 | int segsize; | |
7309 | ||
7310 | if (sizeof (CORE_ADDR) == 8) | |
7311 | /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid | |
7312 | a compiler warning produced where CORE_ADDR is a 32-bit type even | |
7313 | though in that case this is dead code). */ | |
7314 | switch (bpaddr >> ((sizeof (CORE_ADDR) << 3) - 2) & 3) | |
7315 | { | |
7316 | case 3: | |
7317 | if (bpaddr == (bfd_signed_vma) (int32_t) bpaddr) | |
7318 | segsize = 29; /* 32-bit compatibility segment */ | |
7319 | else | |
7320 | segsize = 62; /* xkseg */ | |
7321 | break; | |
7322 | case 2: /* xkphys */ | |
7323 | segsize = 59; | |
7324 | break; | |
7325 | default: /* xksseg (1), xkuseg/kuseg (0) */ | |
7326 | segsize = 62; | |
7327 | break; | |
7328 | } | |
7329 | else if (bpaddr & 0x80000000) /* kernel segment */ | |
7330 | segsize = 29; | |
7331 | else | |
7332 | segsize = 31; /* user segment */ | |
7333 | mask <<= segsize; | |
7334 | return bpaddr & mask; | |
7335 | } | |
7336 | ||
7337 | /* Move the breakpoint at BPADDR out of any branch delay slot by shifting | |
7338 | it backwards if necessary. Return the address of the new location. */ | |
7339 | ||
7340 | static CORE_ADDR | |
7341 | mips_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) | |
7342 | { | |
22e048c9 | 7343 | CORE_ADDR prev_addr; |
c8cef75f MR |
7344 | CORE_ADDR boundary; |
7345 | CORE_ADDR func_addr; | |
7346 | ||
7347 | /* If a breakpoint is set on the instruction in a branch delay slot, | |
7348 | GDB gets confused. When the breakpoint is hit, the PC isn't on | |
7349 | the instruction in the branch delay slot, the PC will point to | |
7350 | the branch instruction. Since the PC doesn't match any known | |
7351 | breakpoints, GDB reports a trap exception. | |
7352 | ||
7353 | There are two possible fixes for this problem. | |
7354 | ||
7355 | 1) When the breakpoint gets hit, see if the BD bit is set in the | |
7356 | Cause register (which indicates the last exception occurred in a | |
7357 | branch delay slot). If the BD bit is set, fix the PC to point to | |
7358 | the instruction in the branch delay slot. | |
7359 | ||
7360 | 2) When the user sets the breakpoint, don't allow him to set the | |
7361 | breakpoint on the instruction in the branch delay slot. Instead | |
7362 | move the breakpoint to the branch instruction (which will have | |
7363 | the same result). | |
7364 | ||
7365 | The problem with the first solution is that if the user then | |
7366 | single-steps the processor, the branch instruction will get | |
7367 | skipped (since GDB thinks the PC is on the instruction in the | |
7368 | branch delay slot). | |
7369 | ||
7370 | So, we'll use the second solution. To do this we need to know if | |
7371 | the instruction we're trying to set the breakpoint on is in the | |
7372 | branch delay slot. */ | |
7373 | ||
7374 | boundary = mips_segment_boundary (bpaddr); | |
7375 | ||
7376 | /* Make sure we don't scan back before the beginning of the current | |
7377 | function, since we may fetch constant data or insns that look like | |
7378 | a jump. Of course we might do that anyway if the compiler has | |
7379 | moved constants inline. :-( */ | |
7380 | if (find_pc_partial_function (bpaddr, NULL, &func_addr, NULL) | |
7381 | && func_addr > boundary && func_addr <= bpaddr) | |
7382 | boundary = func_addr; | |
7383 | ||
4cc0665f | 7384 | if (mips_pc_is_mips (bpaddr)) |
c8cef75f MR |
7385 | { |
7386 | if (bpaddr == boundary) | |
7387 | return bpaddr; | |
7388 | ||
7389 | /* If the previous instruction has a branch delay slot, we have | |
7390 | to move the breakpoint to the branch instruction. */ | |
7391 | prev_addr = bpaddr - 4; | |
ab50adb6 | 7392 | if (mips32_insn_at_pc_has_delay_slot (gdbarch, prev_addr)) |
c8cef75f MR |
7393 | bpaddr = prev_addr; |
7394 | } | |
7395 | else | |
7396 | { | |
ab50adb6 | 7397 | int (*insn_at_pc_has_delay_slot) (struct gdbarch *, CORE_ADDR, int); |
c8cef75f MR |
7398 | CORE_ADDR addr, jmpaddr; |
7399 | int i; | |
7400 | ||
4cc0665f | 7401 | boundary = unmake_compact_addr (boundary); |
c8cef75f MR |
7402 | |
7403 | /* The only MIPS16 instructions with delay slots are JAL, JALX, | |
7404 | JALR and JR. An absolute JAL/JALX is always 4 bytes long, | |
7405 | so try for that first, then try the 2 byte JALR/JR. | |
4cc0665f MR |
7406 | The microMIPS ASE has a whole range of jumps and branches |
7407 | with delay slots, some of which take 4 bytes and some take | |
7408 | 2 bytes, so the idea is the same. | |
c8cef75f MR |
7409 | FIXME: We have to assume that bpaddr is not the second half |
7410 | of an extended instruction. */ | |
ab50adb6 MR |
7411 | insn_at_pc_has_delay_slot = (mips_pc_is_micromips (gdbarch, bpaddr) |
7412 | ? micromips_insn_at_pc_has_delay_slot | |
7413 | : mips16_insn_at_pc_has_delay_slot); | |
c8cef75f MR |
7414 | |
7415 | jmpaddr = 0; | |
7416 | addr = bpaddr; | |
7417 | for (i = 1; i < 4; i++) | |
7418 | { | |
4cc0665f | 7419 | if (unmake_compact_addr (addr) == boundary) |
c8cef75f | 7420 | break; |
4cc0665f | 7421 | addr -= MIPS_INSN16_SIZE; |
ab50adb6 | 7422 | if (i == 1 && insn_at_pc_has_delay_slot (gdbarch, addr, 0)) |
c8cef75f MR |
7423 | /* Looks like a JR/JALR at [target-1], but it could be |
7424 | the second word of a previous JAL/JALX, so record it | |
7425 | and check back one more. */ | |
7426 | jmpaddr = addr; | |
ab50adb6 | 7427 | else if (i > 1 && insn_at_pc_has_delay_slot (gdbarch, addr, 1)) |
c8cef75f MR |
7428 | { |
7429 | if (i == 2) | |
7430 | /* Looks like a JAL/JALX at [target-2], but it could also | |
7431 | be the second word of a previous JAL/JALX, record it, | |
7432 | and check back one more. */ | |
7433 | jmpaddr = addr; | |
7434 | else | |
7435 | /* Looks like a JAL/JALX at [target-3], so any previously | |
7436 | recorded JAL/JALX or JR/JALR must be wrong, because: | |
7437 | ||
7438 | >-3: JAL | |
7439 | -2: JAL-ext (can't be JAL/JALX) | |
7440 | -1: bdslot (can't be JR/JALR) | |
7441 | 0: target insn | |
7442 | ||
7443 | Of course it could be another JAL-ext which looks | |
7444 | like a JAL, but in that case we'd have broken out | |
7445 | of this loop at [target-2]: | |
7446 | ||
7447 | -4: JAL | |
7448 | >-3: JAL-ext | |
7449 | -2: bdslot (can't be jmp) | |
7450 | -1: JR/JALR | |
7451 | 0: target insn */ | |
7452 | jmpaddr = 0; | |
7453 | } | |
7454 | else | |
7455 | { | |
7456 | /* Not a jump instruction: if we're at [target-1] this | |
7457 | could be the second word of a JAL/JALX, so continue; | |
7458 | otherwise we're done. */ | |
7459 | if (i > 1) | |
7460 | break; | |
7461 | } | |
7462 | } | |
7463 | ||
7464 | if (jmpaddr) | |
7465 | bpaddr = jmpaddr; | |
7466 | } | |
7467 | ||
7468 | return bpaddr; | |
7469 | } | |
7470 | ||
14132e89 MR |
7471 | /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16 |
7472 | call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */ | |
7473 | ||
7474 | static int | |
7475 | mips_is_stub_suffix (const char *suffix, int zero) | |
7476 | { | |
7477 | switch (suffix[0]) | |
7478 | { | |
7479 | case '0': | |
7480 | return zero && suffix[1] == '\0'; | |
7481 | case '1': | |
7482 | return suffix[1] == '\0' || (suffix[1] == '0' && suffix[2] == '\0'); | |
7483 | case '2': | |
7484 | case '5': | |
7485 | case '6': | |
7486 | case '9': | |
7487 | return suffix[1] == '\0'; | |
7488 | default: | |
7489 | return 0; | |
7490 | } | |
7491 | } | |
7492 | ||
7493 | /* Return non-zero if MODE is one of the mode infixes used for MIPS16 | |
7494 | call stubs, one of sf, df, sc, or dc. */ | |
7495 | ||
7496 | static int | |
7497 | mips_is_stub_mode (const char *mode) | |
7498 | { | |
7499 | return ((mode[0] == 's' || mode[0] == 'd') | |
7500 | && (mode[1] == 'f' || mode[1] == 'c')); | |
7501 | } | |
7502 | ||
7503 | /* Code at PC is a compiler-generated stub. Such a stub for a function | |
7504 | bar might have a name like __fn_stub_bar, and might look like this: | |
7505 | ||
7506 | mfc1 $4, $f13 | |
7507 | mfc1 $5, $f12 | |
7508 | mfc1 $6, $f15 | |
7509 | mfc1 $7, $f14 | |
7510 | ||
7511 | followed by (or interspersed with): | |
7512 | ||
7513 | j bar | |
7514 | ||
7515 | or: | |
7516 | ||
7517 | lui $25, %hi(bar) | |
7518 | addiu $25, $25, %lo(bar) | |
7519 | jr $25 | |
7520 | ||
7521 | ($1 may be used in old code; for robustness we accept any register) | |
7522 | or, in PIC code: | |
7523 | ||
7524 | lui $28, %hi(_gp_disp) | |
7525 | addiu $28, $28, %lo(_gp_disp) | |
7526 | addu $28, $28, $25 | |
7527 | lw $25, %got(bar) | |
7528 | addiu $25, $25, %lo(bar) | |
7529 | jr $25 | |
7530 | ||
7531 | In the case of a __call_stub_bar stub, the sequence to set up | |
7532 | arguments might look like this: | |
7533 | ||
7534 | mtc1 $4, $f13 | |
7535 | mtc1 $5, $f12 | |
7536 | mtc1 $6, $f15 | |
7537 | mtc1 $7, $f14 | |
7538 | ||
7539 | followed by (or interspersed with) one of the jump sequences above. | |
7540 | ||
7541 | In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead | |
7542 | of J or JR, respectively, followed by: | |
7543 | ||
7544 | mfc1 $2, $f0 | |
7545 | mfc1 $3, $f1 | |
7546 | jr $18 | |
7547 | ||
7548 | We are at the beginning of the stub here, and scan down and extract | |
7549 | the target address from the jump immediate instruction or, if a jump | |
7550 | register instruction is used, from the register referred. Return | |
7551 | the value of PC calculated or 0 if inconclusive. | |
7552 | ||
7553 | The limit on the search is arbitrarily set to 20 instructions. FIXME. */ | |
7554 | ||
7555 | static CORE_ADDR | |
7556 | mips_get_mips16_fn_stub_pc (struct frame_info *frame, CORE_ADDR pc) | |
7557 | { | |
7558 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
7559 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
7560 | int addrreg = MIPS_ZERO_REGNUM; | |
7561 | CORE_ADDR start_pc = pc; | |
7562 | CORE_ADDR target_pc = 0; | |
7563 | CORE_ADDR addr = 0; | |
7564 | CORE_ADDR gp = 0; | |
7565 | int status = 0; | |
7566 | int i; | |
7567 | ||
7568 | for (i = 0; | |
7569 | status == 0 && target_pc == 0 && i < 20; | |
7570 | i++, pc += MIPS_INSN32_SIZE) | |
7571 | { | |
4cc0665f | 7572 | ULONGEST inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
14132e89 MR |
7573 | CORE_ADDR imm; |
7574 | int rt; | |
7575 | int rs; | |
7576 | int rd; | |
7577 | ||
7578 | switch (itype_op (inst)) | |
7579 | { | |
7580 | case 0: /* SPECIAL */ | |
7581 | switch (rtype_funct (inst)) | |
7582 | { | |
7583 | case 8: /* JR */ | |
7584 | case 9: /* JALR */ | |
7585 | rs = rtype_rs (inst); | |
7586 | if (rs == MIPS_GP_REGNUM) | |
7587 | target_pc = gp; /* Hmm... */ | |
7588 | else if (rs == addrreg) | |
7589 | target_pc = addr; | |
7590 | break; | |
7591 | ||
7592 | case 0x21: /* ADDU */ | |
7593 | rt = rtype_rt (inst); | |
7594 | rs = rtype_rs (inst); | |
7595 | rd = rtype_rd (inst); | |
7596 | if (rd == MIPS_GP_REGNUM | |
7597 | && ((rs == MIPS_GP_REGNUM && rt == MIPS_T9_REGNUM) | |
7598 | || (rs == MIPS_T9_REGNUM && rt == MIPS_GP_REGNUM))) | |
7599 | gp += start_pc; | |
7600 | break; | |
7601 | } | |
7602 | break; | |
7603 | ||
7604 | case 2: /* J */ | |
7605 | case 3: /* JAL */ | |
7606 | target_pc = jtype_target (inst) << 2; | |
7607 | target_pc += ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); | |
7608 | break; | |
7609 | ||
7610 | case 9: /* ADDIU */ | |
7611 | rt = itype_rt (inst); | |
7612 | rs = itype_rs (inst); | |
7613 | if (rt == rs) | |
7614 | { | |
7615 | imm = (itype_immediate (inst) ^ 0x8000) - 0x8000; | |
7616 | if (rt == MIPS_GP_REGNUM) | |
7617 | gp += imm; | |
7618 | else if (rt == addrreg) | |
7619 | addr += imm; | |
7620 | } | |
7621 | break; | |
7622 | ||
7623 | case 0xf: /* LUI */ | |
7624 | rt = itype_rt (inst); | |
7625 | imm = ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 16; | |
7626 | if (rt == MIPS_GP_REGNUM) | |
7627 | gp = imm; | |
7628 | else if (rt != MIPS_ZERO_REGNUM) | |
7629 | { | |
7630 | addrreg = rt; | |
7631 | addr = imm; | |
7632 | } | |
7633 | break; | |
7634 | ||
7635 | case 0x23: /* LW */ | |
7636 | rt = itype_rt (inst); | |
7637 | rs = itype_rs (inst); | |
7638 | imm = (itype_immediate (inst) ^ 0x8000) - 0x8000; | |
7639 | if (gp != 0 && rs == MIPS_GP_REGNUM) | |
7640 | { | |
7641 | gdb_byte buf[4]; | |
7642 | ||
7643 | memset (buf, 0, sizeof (buf)); | |
7644 | status = target_read_memory (gp + imm, buf, sizeof (buf)); | |
7645 | addrreg = rt; | |
7646 | addr = extract_signed_integer (buf, sizeof (buf), byte_order); | |
7647 | } | |
7648 | break; | |
7649 | } | |
7650 | } | |
7651 | ||
7652 | return target_pc; | |
7653 | } | |
7654 | ||
7655 | /* If PC is in a MIPS16 call or return stub, return the address of the | |
7656 | target PC, which is either the callee or the caller. There are several | |
c906108c SS |
7657 | cases which must be handled: |
7658 | ||
14132e89 MR |
7659 | * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub |
7660 | and the target PC is in $31 ($ra). | |
c906108c | 7661 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
14132e89 MR |
7662 | and the target PC is in $2. |
7663 | * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10}, | |
7664 | i.e. before the JALR instruction, this is effectively a call stub | |
7665 | and the target PC is in $2. Otherwise this is effectively | |
7666 | a return stub and the target PC is in $18. | |
7667 | * If the PC is at the start of __call_stub_fp_*, i.e. before the | |
7668 | JAL or JALR instruction, this is effectively a call stub and the | |
7669 | target PC is buried in the instruction stream. Otherwise this | |
7670 | is effectively a return stub and the target PC is in $18. | |
7671 | * If the PC is in __call_stub_* or in __fn_stub_*, this is a call | |
7672 | stub and the target PC is buried in the instruction stream. | |
7673 | ||
7674 | See the source code for the stubs in gcc/config/mips/mips16.S, or the | |
7675 | stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the | |
e7d6a6d2 | 7676 | gory details. */ |
c906108c | 7677 | |
757a7cc6 | 7678 | static CORE_ADDR |
db5f024e | 7679 | mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 7680 | { |
e17a4113 | 7681 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 7682 | CORE_ADDR start_addr; |
14132e89 MR |
7683 | const char *name; |
7684 | size_t prefixlen; | |
c906108c SS |
7685 | |
7686 | /* Find the starting address and name of the function containing the PC. */ | |
7687 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
7688 | return 0; | |
7689 | ||
14132e89 MR |
7690 | /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub |
7691 | and the target PC is in $31 ($ra). */ | |
7692 | prefixlen = strlen (mips_str_mips16_ret_stub); | |
7693 | if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0 | |
7694 | && mips_is_stub_mode (name + prefixlen) | |
7695 | && name[prefixlen + 2] == '\0') | |
7696 | return get_frame_register_signed | |
7697 | (frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM); | |
7698 | ||
7699 | /* If the PC is in __mips16_call_stub_*, this is one of the call | |
7700 | call/return stubs. */ | |
7701 | prefixlen = strlen (mips_str_mips16_call_stub); | |
7702 | if (strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0) | |
c906108c SS |
7703 | { |
7704 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
7705 | and the target PC is in $2. */ | |
14132e89 MR |
7706 | if (mips_is_stub_suffix (name + prefixlen, 0)) |
7707 | return get_frame_register_signed | |
7708 | (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); | |
c906108c | 7709 | |
14132e89 MR |
7710 | /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10}, |
7711 | i.e. before the JALR instruction, this is effectively a call stub | |
b021a221 | 7712 | and the target PC is in $2. Otherwise this is effectively |
c5aa993b | 7713 | a return stub and the target PC is in $18. */ |
14132e89 MR |
7714 | else if (mips_is_stub_mode (name + prefixlen) |
7715 | && name[prefixlen + 2] == '_' | |
7716 | && mips_is_stub_suffix (name + prefixlen + 3, 0)) | |
c906108c SS |
7717 | { |
7718 | if (pc == start_addr) | |
14132e89 MR |
7719 | /* This is the 'call' part of a call stub. The return |
7720 | address is in $2. */ | |
7721 | return get_frame_register_signed | |
7722 | (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); | |
c906108c SS |
7723 | else |
7724 | /* This is the 'return' part of a call stub. The return | |
14132e89 MR |
7725 | address is in $18. */ |
7726 | return get_frame_register_signed | |
7727 | (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); | |
c906108c | 7728 | } |
14132e89 MR |
7729 | else |
7730 | return 0; /* Not a stub. */ | |
7731 | } | |
7732 | ||
7733 | /* If the PC is in __call_stub_* or __fn_stub*, this is one of the | |
7734 | compiler-generated call or call/return stubs. */ | |
61012eef GB |
7735 | if (startswith (name, mips_str_fn_stub) |
7736 | || startswith (name, mips_str_call_stub)) | |
14132e89 MR |
7737 | { |
7738 | if (pc == start_addr) | |
7739 | /* This is the 'call' part of a call stub. Call this helper | |
7740 | to scan through this code for interesting instructions | |
7741 | and determine the final PC. */ | |
7742 | return mips_get_mips16_fn_stub_pc (frame, pc); | |
7743 | else | |
7744 | /* This is the 'return' part of a call stub. The return address | |
7745 | is in $18. */ | |
7746 | return get_frame_register_signed | |
7747 | (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); | |
c906108c | 7748 | } |
14132e89 MR |
7749 | |
7750 | return 0; /* Not a stub. */ | |
7751 | } | |
7752 | ||
7753 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
7754 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
7755 | ||
7756 | static int | |
7757 | mips_in_return_stub (struct gdbarch *gdbarch, CORE_ADDR pc, const char *name) | |
7758 | { | |
7759 | CORE_ADDR start_addr; | |
7760 | size_t prefixlen; | |
7761 | ||
7762 | /* Find the starting address of the function containing the PC. */ | |
7763 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
7764 | return 0; | |
7765 | ||
7766 | /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at | |
7767 | the start, i.e. after the JALR instruction, this is effectively | |
7768 | a return stub. */ | |
7769 | prefixlen = strlen (mips_str_mips16_call_stub); | |
7770 | if (pc != start_addr | |
7771 | && strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0 | |
7772 | && mips_is_stub_mode (name + prefixlen) | |
7773 | && name[prefixlen + 2] == '_' | |
7774 | && mips_is_stub_suffix (name + prefixlen + 3, 1)) | |
7775 | return 1; | |
7776 | ||
7777 | /* If the PC is in __call_stub_fp_* but not at the start, i.e. after | |
7778 | the JAL or JALR instruction, this is effectively a return stub. */ | |
7779 | prefixlen = strlen (mips_str_call_fp_stub); | |
7780 | if (pc != start_addr | |
7781 | && strncmp (name, mips_str_call_fp_stub, prefixlen) == 0) | |
7782 | return 1; | |
7783 | ||
7784 | /* Consume the .pic. prefix of any PIC stub, this function must return | |
7785 | true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub | |
7786 | or the call stub path will trigger in handle_inferior_event causing | |
7787 | it to go astray. */ | |
7788 | prefixlen = strlen (mips_str_pic); | |
7789 | if (strncmp (name, mips_str_pic, prefixlen) == 0) | |
7790 | name += prefixlen; | |
7791 | ||
7792 | /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */ | |
7793 | prefixlen = strlen (mips_str_mips16_ret_stub); | |
7794 | if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0 | |
7795 | && mips_is_stub_mode (name + prefixlen) | |
7796 | && name[prefixlen + 2] == '\0') | |
7797 | return 1; | |
7798 | ||
7799 | return 0; /* Not a stub. */ | |
c906108c SS |
7800 | } |
7801 | ||
db5f024e DJ |
7802 | /* If the current PC is the start of a non-PIC-to-PIC stub, return the |
7803 | PC of the stub target. The stub just loads $t9 and jumps to it, | |
7804 | so that $t9 has the correct value at function entry. */ | |
7805 | ||
7806 | static CORE_ADDR | |
7807 | mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
7808 | { | |
e17a4113 UW |
7809 | struct gdbarch *gdbarch = get_frame_arch (frame); |
7810 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
7cbd4a93 | 7811 | struct bound_minimal_symbol msym; |
db5f024e DJ |
7812 | int i; |
7813 | gdb_byte stub_code[16]; | |
7814 | int32_t stub_words[4]; | |
7815 | ||
7816 | /* The stub for foo is named ".pic.foo", and is either two | |
7817 | instructions inserted before foo or a three instruction sequence | |
7818 | which jumps to foo. */ | |
7819 | msym = lookup_minimal_symbol_by_pc (pc); | |
7cbd4a93 | 7820 | if (msym.minsym == NULL |
77e371c0 | 7821 | || BMSYMBOL_VALUE_ADDRESS (msym) != pc |
efd66ac6 | 7822 | || MSYMBOL_LINKAGE_NAME (msym.minsym) == NULL |
61012eef | 7823 | || !startswith (MSYMBOL_LINKAGE_NAME (msym.minsym), ".pic.")) |
db5f024e DJ |
7824 | return 0; |
7825 | ||
7826 | /* A two-instruction header. */ | |
7cbd4a93 | 7827 | if (MSYMBOL_SIZE (msym.minsym) == 8) |
db5f024e DJ |
7828 | return pc + 8; |
7829 | ||
7830 | /* A three-instruction (plus delay slot) trampoline. */ | |
7cbd4a93 | 7831 | if (MSYMBOL_SIZE (msym.minsym) == 16) |
db5f024e DJ |
7832 | { |
7833 | if (target_read_memory (pc, stub_code, 16) != 0) | |
7834 | return 0; | |
7835 | for (i = 0; i < 4; i++) | |
e17a4113 UW |
7836 | stub_words[i] = extract_unsigned_integer (stub_code + i * 4, |
7837 | 4, byte_order); | |
db5f024e DJ |
7838 | |
7839 | /* A stub contains these instructions: | |
7840 | lui t9, %hi(target) | |
7841 | j target | |
7842 | addiu t9, t9, %lo(target) | |
7843 | nop | |
7844 | ||
7845 | This works even for N64, since stubs are only generated with | |
7846 | -msym32. */ | |
7847 | if ((stub_words[0] & 0xffff0000U) == 0x3c190000 | |
7848 | && (stub_words[1] & 0xfc000000U) == 0x08000000 | |
7849 | && (stub_words[2] & 0xffff0000U) == 0x27390000 | |
7850 | && stub_words[3] == 0x00000000) | |
34b192ce MR |
7851 | return ((((stub_words[0] & 0x0000ffff) << 16) |
7852 | + (stub_words[2] & 0x0000ffff)) ^ 0x8000) - 0x8000; | |
db5f024e DJ |
7853 | } |
7854 | ||
7855 | /* Not a recognized stub. */ | |
7856 | return 0; | |
7857 | } | |
7858 | ||
7859 | static CORE_ADDR | |
7860 | mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
7861 | { | |
14132e89 | 7862 | CORE_ADDR requested_pc = pc; |
db5f024e | 7863 | CORE_ADDR target_pc; |
14132e89 MR |
7864 | CORE_ADDR new_pc; |
7865 | ||
7866 | do | |
7867 | { | |
7868 | target_pc = pc; | |
db5f024e | 7869 | |
14132e89 MR |
7870 | new_pc = mips_skip_mips16_trampoline_code (frame, pc); |
7871 | if (new_pc) | |
3e29f34a | 7872 | pc = new_pc; |
db5f024e | 7873 | |
14132e89 MR |
7874 | new_pc = find_solib_trampoline_target (frame, pc); |
7875 | if (new_pc) | |
3e29f34a | 7876 | pc = new_pc; |
db5f024e | 7877 | |
14132e89 MR |
7878 | new_pc = mips_skip_pic_trampoline_code (frame, pc); |
7879 | if (new_pc) | |
3e29f34a | 7880 | pc = new_pc; |
14132e89 MR |
7881 | } |
7882 | while (pc != target_pc); | |
db5f024e | 7883 | |
14132e89 | 7884 | return pc != requested_pc ? pc : 0; |
db5f024e DJ |
7885 | } |
7886 | ||
a4b8ebc8 | 7887 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
f57d151a | 7888 | [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
7889 | |
7890 | static int | |
d3f73121 | 7891 | mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 7892 | { |
a4b8ebc8 | 7893 | int regnum; |
2f38ef89 | 7894 | if (num >= 0 && num < 32) |
a4b8ebc8 | 7895 | regnum = num; |
2f38ef89 | 7896 | else if (num >= 38 && num < 70) |
d3f73121 | 7897 | regnum = num + mips_regnum (gdbarch)->fp0 - 38; |
040b99fd | 7898 | else if (num == 70) |
d3f73121 | 7899 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 7900 | else if (num == 71) |
d3f73121 | 7901 | regnum = mips_regnum (gdbarch)->lo; |
1faeff08 MR |
7902 | else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 72 && num < 78) |
7903 | regnum = num + mips_regnum (gdbarch)->dspacc - 72; | |
2f38ef89 | 7904 | else |
0fde2c53 | 7905 | return -1; |
d3f73121 | 7906 | return gdbarch_num_regs (gdbarch) + regnum; |
88c72b7d AC |
7907 | } |
7908 | ||
2f38ef89 | 7909 | |
a4b8ebc8 | 7910 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
f57d151a | 7911 | gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
7912 | |
7913 | static int | |
d3f73121 | 7914 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 7915 | { |
a4b8ebc8 | 7916 | int regnum; |
2f38ef89 | 7917 | if (num >= 0 && num < 32) |
a4b8ebc8 | 7918 | regnum = num; |
2f38ef89 | 7919 | else if (num >= 32 && num < 64) |
d3f73121 | 7920 | regnum = num + mips_regnum (gdbarch)->fp0 - 32; |
040b99fd | 7921 | else if (num == 64) |
d3f73121 | 7922 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 7923 | else if (num == 65) |
d3f73121 | 7924 | regnum = mips_regnum (gdbarch)->lo; |
1faeff08 MR |
7925 | else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 66 && num < 72) |
7926 | regnum = num + mips_regnum (gdbarch)->dspacc - 66; | |
2f38ef89 | 7927 | else |
0fde2c53 | 7928 | return -1; |
d3f73121 | 7929 | return gdbarch_num_regs (gdbarch) + regnum; |
a4b8ebc8 AC |
7930 | } |
7931 | ||
7932 | static int | |
e7faf938 | 7933 | mips_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
a4b8ebc8 AC |
7934 | { |
7935 | /* Only makes sense to supply raw registers. */ | |
e7faf938 | 7936 | gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)); |
a4b8ebc8 AC |
7937 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to |
7938 | decide if it is valid. Should instead define a standard sim/gdb | |
7939 | register numbering scheme. */ | |
e7faf938 MD |
7940 | if (gdbarch_register_name (gdbarch, |
7941 | gdbarch_num_regs (gdbarch) + regnum) != NULL | |
7942 | && gdbarch_register_name (gdbarch, | |
025bb325 MS |
7943 | gdbarch_num_regs (gdbarch) |
7944 | + regnum)[0] != '\0') | |
a4b8ebc8 AC |
7945 | return regnum; |
7946 | else | |
6d82d43b | 7947 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
7948 | } |
7949 | ||
2f38ef89 | 7950 | |
4844f454 CV |
7951 | /* Convert an integer into an address. Extracting the value signed |
7952 | guarantees a correctly sign extended address. */ | |
fc0c74b1 AC |
7953 | |
7954 | static CORE_ADDR | |
79dd2d24 | 7955 | mips_integer_to_address (struct gdbarch *gdbarch, |
870cd05e | 7956 | struct type *type, const gdb_byte *buf) |
fc0c74b1 | 7957 | { |
e17a4113 UW |
7958 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7959 | return extract_signed_integer (buf, TYPE_LENGTH (type), byte_order); | |
fc0c74b1 AC |
7960 | } |
7961 | ||
82e91389 DJ |
7962 | /* Dummy virtual frame pointer method. This is no more or less accurate |
7963 | than most other architectures; we just need to be explicit about it, | |
7964 | because the pseudo-register gdbarch_sp_regnum will otherwise lead to | |
7965 | an assertion failure. */ | |
7966 | ||
7967 | static void | |
a54fba4c MD |
7968 | mips_virtual_frame_pointer (struct gdbarch *gdbarch, |
7969 | CORE_ADDR pc, int *reg, LONGEST *offset) | |
82e91389 DJ |
7970 | { |
7971 | *reg = MIPS_SP_REGNUM; | |
7972 | *offset = 0; | |
7973 | } | |
7974 | ||
caaa3122 DJ |
7975 | static void |
7976 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
7977 | { | |
7978 | enum mips_abi *abip = (enum mips_abi *) obj; | |
7979 | const char *name = bfd_get_section_name (abfd, sect); | |
7980 | ||
7981 | if (*abip != MIPS_ABI_UNKNOWN) | |
7982 | return; | |
7983 | ||
61012eef | 7984 | if (!startswith (name, ".mdebug.")) |
caaa3122 DJ |
7985 | return; |
7986 | ||
7987 | if (strcmp (name, ".mdebug.abi32") == 0) | |
7988 | *abip = MIPS_ABI_O32; | |
7989 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
7990 | *abip = MIPS_ABI_N32; | |
62a49b2c | 7991 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 7992 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
7993 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
7994 | *abip = MIPS_ABI_O64; | |
7995 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
7996 | *abip = MIPS_ABI_EABI32; | |
7997 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
7998 | *abip = MIPS_ABI_EABI64; | |
7999 | else | |
8a3fe4f8 | 8000 | warning (_("unsupported ABI %s."), name + 8); |
caaa3122 DJ |
8001 | } |
8002 | ||
22e47e37 FF |
8003 | static void |
8004 | mips_find_long_section (bfd *abfd, asection *sect, void *obj) | |
8005 | { | |
8006 | int *lbp = (int *) obj; | |
8007 | const char *name = bfd_get_section_name (abfd, sect); | |
8008 | ||
61012eef | 8009 | if (startswith (name, ".gcc_compiled_long32")) |
22e47e37 | 8010 | *lbp = 32; |
61012eef | 8011 | else if (startswith (name, ".gcc_compiled_long64")) |
22e47e37 | 8012 | *lbp = 64; |
61012eef | 8013 | else if (startswith (name, ".gcc_compiled_long")) |
22e47e37 FF |
8014 | warning (_("unrecognized .gcc_compiled_longXX")); |
8015 | } | |
8016 | ||
2e4ebe70 DJ |
8017 | static enum mips_abi |
8018 | global_mips_abi (void) | |
8019 | { | |
8020 | int i; | |
8021 | ||
8022 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
8023 | if (mips_abi_strings[i] == mips_abi_string) | |
8024 | return (enum mips_abi) i; | |
8025 | ||
e2e0b3e5 | 8026 | internal_error (__FILE__, __LINE__, _("unknown ABI string")); |
2e4ebe70 DJ |
8027 | } |
8028 | ||
4cc0665f MR |
8029 | /* Return the default compressed instruction set, either of MIPS16 |
8030 | or microMIPS, selected when none could have been determined from | |
8031 | the ELF header of the binary being executed (or no binary has been | |
8032 | selected. */ | |
8033 | ||
8034 | static enum mips_isa | |
8035 | global_mips_compression (void) | |
8036 | { | |
8037 | int i; | |
8038 | ||
8039 | for (i = 0; mips_compression_strings[i] != NULL; i++) | |
8040 | if (mips_compression_strings[i] == mips_compression_string) | |
8041 | return (enum mips_isa) i; | |
8042 | ||
8043 | internal_error (__FILE__, __LINE__, _("unknown compressed ISA string")); | |
8044 | } | |
8045 | ||
29709017 DJ |
8046 | static void |
8047 | mips_register_g_packet_guesses (struct gdbarch *gdbarch) | |
8048 | { | |
29709017 DJ |
8049 | /* If the size matches the set of 32-bit or 64-bit integer registers, |
8050 | assume that's what we've got. */ | |
4eb0ad19 DJ |
8051 | register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32); |
8052 | register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64); | |
29709017 DJ |
8053 | |
8054 | /* If the size matches the full set of registers GDB traditionally | |
8055 | knows about, including floating point, for either 32-bit or | |
8056 | 64-bit, assume that's what we've got. */ | |
4eb0ad19 DJ |
8057 | register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32); |
8058 | register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64); | |
29709017 DJ |
8059 | |
8060 | /* Otherwise we don't have a useful guess. */ | |
8061 | } | |
8062 | ||
f8b73d13 DJ |
8063 | static struct value * |
8064 | value_of_mips_user_reg (struct frame_info *frame, const void *baton) | |
8065 | { | |
19ba03f4 | 8066 | const int *reg_p = (const int *) baton; |
f8b73d13 DJ |
8067 | return value_of_register (*reg_p, frame); |
8068 | } | |
8069 | ||
c2d11a7d | 8070 | static struct gdbarch * |
6d82d43b | 8071 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 8072 | { |
c2d11a7d JM |
8073 | struct gdbarch *gdbarch; |
8074 | struct gdbarch_tdep *tdep; | |
8075 | int elf_flags; | |
2e4ebe70 | 8076 | enum mips_abi mips_abi, found_abi, wanted_abi; |
f8b73d13 | 8077 | int i, num_regs; |
8d5838b5 | 8078 | enum mips_fpu_type fpu_type; |
f8b73d13 | 8079 | struct tdesc_arch_data *tdesc_data = NULL; |
d929bc19 | 8080 | int elf_fpu_type = Val_GNU_MIPS_ABI_FP_ANY; |
1faeff08 MR |
8081 | const char **reg_names; |
8082 | struct mips_regnum mips_regnum, *regnum; | |
4cc0665f | 8083 | enum mips_isa mips_isa; |
1faeff08 MR |
8084 | int dspacc; |
8085 | int dspctl; | |
8086 | ||
8087 | /* Fill in the OS dependent register numbers and names. */ | |
de4bfa86 | 8088 | if (info.osabi == GDB_OSABI_LINUX) |
1faeff08 MR |
8089 | { |
8090 | mips_regnum.fp0 = 38; | |
8091 | mips_regnum.pc = 37; | |
8092 | mips_regnum.cause = 36; | |
8093 | mips_regnum.badvaddr = 35; | |
8094 | mips_regnum.hi = 34; | |
8095 | mips_regnum.lo = 33; | |
8096 | mips_regnum.fp_control_status = 70; | |
8097 | mips_regnum.fp_implementation_revision = 71; | |
8098 | mips_regnum.dspacc = -1; | |
8099 | mips_regnum.dspctl = -1; | |
8100 | dspacc = 72; | |
8101 | dspctl = 78; | |
3877922e | 8102 | num_regs = 90; |
1faeff08 MR |
8103 | reg_names = mips_linux_reg_names; |
8104 | } | |
8105 | else | |
8106 | { | |
8107 | mips_regnum.lo = MIPS_EMBED_LO_REGNUM; | |
8108 | mips_regnum.hi = MIPS_EMBED_HI_REGNUM; | |
8109 | mips_regnum.badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
8110 | mips_regnum.cause = MIPS_EMBED_CAUSE_REGNUM; | |
8111 | mips_regnum.pc = MIPS_EMBED_PC_REGNUM; | |
8112 | mips_regnum.fp0 = MIPS_EMBED_FP0_REGNUM; | |
8113 | mips_regnum.fp_control_status = 70; | |
8114 | mips_regnum.fp_implementation_revision = 71; | |
8115 | mips_regnum.dspacc = dspacc = -1; | |
8116 | mips_regnum.dspctl = dspctl = -1; | |
8117 | num_regs = MIPS_LAST_EMBED_REGNUM + 1; | |
8118 | if (info.bfd_arch_info != NULL | |
8119 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
8120 | reg_names = mips_tx39_reg_names; | |
8121 | else | |
8122 | reg_names = mips_generic_reg_names; | |
8123 | } | |
f8b73d13 DJ |
8124 | |
8125 | /* Check any target description for validity. */ | |
8126 | if (tdesc_has_registers (info.target_desc)) | |
8127 | { | |
8128 | static const char *const mips_gprs[] = { | |
8129 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
8130 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
8131 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
8132 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
8133 | }; | |
8134 | static const char *const mips_fprs[] = { | |
8135 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
8136 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
8137 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
8138 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
8139 | }; | |
8140 | ||
8141 | const struct tdesc_feature *feature; | |
8142 | int valid_p; | |
8143 | ||
8144 | feature = tdesc_find_feature (info.target_desc, | |
8145 | "org.gnu.gdb.mips.cpu"); | |
8146 | if (feature == NULL) | |
8147 | return NULL; | |
8148 | ||
8149 | tdesc_data = tdesc_data_alloc (); | |
8150 | ||
8151 | valid_p = 1; | |
8152 | for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) | |
8153 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
8154 | mips_gprs[i]); | |
8155 | ||
8156 | ||
8157 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 8158 | mips_regnum.lo, "lo"); |
f8b73d13 | 8159 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
1faeff08 | 8160 | mips_regnum.hi, "hi"); |
f8b73d13 | 8161 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
1faeff08 | 8162 | mips_regnum.pc, "pc"); |
f8b73d13 DJ |
8163 | |
8164 | if (!valid_p) | |
8165 | { | |
8166 | tdesc_data_cleanup (tdesc_data); | |
8167 | return NULL; | |
8168 | } | |
8169 | ||
8170 | feature = tdesc_find_feature (info.target_desc, | |
8171 | "org.gnu.gdb.mips.cp0"); | |
8172 | if (feature == NULL) | |
8173 | { | |
8174 | tdesc_data_cleanup (tdesc_data); | |
8175 | return NULL; | |
8176 | } | |
8177 | ||
8178 | valid_p = 1; | |
8179 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 8180 | mips_regnum.badvaddr, "badvaddr"); |
f8b73d13 DJ |
8181 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
8182 | MIPS_PS_REGNUM, "status"); | |
8183 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 8184 | mips_regnum.cause, "cause"); |
f8b73d13 DJ |
8185 | |
8186 | if (!valid_p) | |
8187 | { | |
8188 | tdesc_data_cleanup (tdesc_data); | |
8189 | return NULL; | |
8190 | } | |
8191 | ||
8192 | /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS | |
8193 | backend is not prepared for that, though. */ | |
8194 | feature = tdesc_find_feature (info.target_desc, | |
8195 | "org.gnu.gdb.mips.fpu"); | |
8196 | if (feature == NULL) | |
8197 | { | |
8198 | tdesc_data_cleanup (tdesc_data); | |
8199 | return NULL; | |
8200 | } | |
8201 | ||
8202 | valid_p = 1; | |
8203 | for (i = 0; i < 32; i++) | |
8204 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 8205 | i + mips_regnum.fp0, mips_fprs[i]); |
f8b73d13 DJ |
8206 | |
8207 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 MR |
8208 | mips_regnum.fp_control_status, |
8209 | "fcsr"); | |
8210 | valid_p | |
8211 | &= tdesc_numbered_register (feature, tdesc_data, | |
8212 | mips_regnum.fp_implementation_revision, | |
8213 | "fir"); | |
f8b73d13 DJ |
8214 | |
8215 | if (!valid_p) | |
8216 | { | |
8217 | tdesc_data_cleanup (tdesc_data); | |
8218 | return NULL; | |
8219 | } | |
8220 | ||
3877922e MR |
8221 | num_regs = mips_regnum.fp_implementation_revision + 1; |
8222 | ||
1faeff08 MR |
8223 | if (dspacc >= 0) |
8224 | { | |
8225 | feature = tdesc_find_feature (info.target_desc, | |
8226 | "org.gnu.gdb.mips.dsp"); | |
8227 | /* The DSP registers are optional; it's OK if they are absent. */ | |
8228 | if (feature != NULL) | |
8229 | { | |
8230 | i = 0; | |
8231 | valid_p = 1; | |
8232 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8233 | dspacc + i++, "hi1"); | |
8234 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8235 | dspacc + i++, "lo1"); | |
8236 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8237 | dspacc + i++, "hi2"); | |
8238 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8239 | dspacc + i++, "lo2"); | |
8240 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8241 | dspacc + i++, "hi3"); | |
8242 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8243 | dspacc + i++, "lo3"); | |
8244 | ||
8245 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8246 | dspctl, "dspctl"); | |
8247 | ||
8248 | if (!valid_p) | |
8249 | { | |
8250 | tdesc_data_cleanup (tdesc_data); | |
8251 | return NULL; | |
8252 | } | |
8253 | ||
8254 | mips_regnum.dspacc = dspacc; | |
8255 | mips_regnum.dspctl = dspctl; | |
3877922e MR |
8256 | |
8257 | num_regs = mips_regnum.dspctl + 1; | |
1faeff08 MR |
8258 | } |
8259 | } | |
8260 | ||
f8b73d13 DJ |
8261 | /* It would be nice to detect an attempt to use a 64-bit ABI |
8262 | when only 32-bit registers are provided. */ | |
1faeff08 | 8263 | reg_names = NULL; |
f8b73d13 | 8264 | } |
c2d11a7d | 8265 | |
ec03c1ac AC |
8266 | /* First of all, extract the elf_flags, if available. */ |
8267 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
8268 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
8269 | else if (arches != NULL) |
8270 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
8271 | else |
8272 | elf_flags = 0; | |
8273 | if (gdbarch_debug) | |
8274 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 8275 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 8276 | |
102182a9 | 8277 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
8278 | switch ((elf_flags & EF_MIPS_ABI)) |
8279 | { | |
8280 | case E_MIPS_ABI_O32: | |
ec03c1ac | 8281 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
8282 | break; |
8283 | case E_MIPS_ABI_O64: | |
ec03c1ac | 8284 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
8285 | break; |
8286 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 8287 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
8288 | break; |
8289 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 8290 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
8291 | break; |
8292 | default: | |
acdb74a0 | 8293 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 8294 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 8295 | else |
ec03c1ac | 8296 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
8297 | break; |
8298 | } | |
acdb74a0 | 8299 | |
caaa3122 | 8300 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
8301 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
8302 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 8303 | |
dc305454 | 8304 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
8305 | MIPS architecture (if there is one). */ |
8306 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
8307 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 8308 | |
32a6503c | 8309 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 8310 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
8311 | && info.bfd_arch_info != NULL |
8312 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
8313 | { | |
8314 | switch (info.bfd_arch_info->mach) | |
8315 | { | |
8316 | case bfd_mach_mips3900: | |
ec03c1ac | 8317 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
8318 | break; |
8319 | case bfd_mach_mips4100: | |
8320 | case bfd_mach_mips5000: | |
ec03c1ac | 8321 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 8322 | break; |
1d06468c EZ |
8323 | case bfd_mach_mips8000: |
8324 | case bfd_mach_mips10000: | |
32a6503c KB |
8325 | /* On Irix, ELF64 executables use the N64 ABI. The |
8326 | pseudo-sections which describe the ABI aren't present | |
8327 | on IRIX. (Even for executables created by gcc.) */ | |
e6c2f47b PA |
8328 | if (info.abfd != NULL |
8329 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
28d169de | 8330 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) |
ec03c1ac | 8331 | found_abi = MIPS_ABI_N64; |
28d169de | 8332 | else |
ec03c1ac | 8333 | found_abi = MIPS_ABI_N32; |
1d06468c | 8334 | break; |
bf64bfd6 AC |
8335 | } |
8336 | } | |
2e4ebe70 | 8337 | |
26c53e50 DJ |
8338 | /* Default 64-bit objects to N64 instead of O32. */ |
8339 | if (found_abi == MIPS_ABI_UNKNOWN | |
8340 | && info.abfd != NULL | |
8341 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
8342 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
8343 | found_abi = MIPS_ABI_N64; | |
8344 | ||
ec03c1ac AC |
8345 | if (gdbarch_debug) |
8346 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
8347 | found_abi); | |
8348 | ||
8349 | /* What has the user specified from the command line? */ | |
8350 | wanted_abi = global_mips_abi (); | |
8351 | if (gdbarch_debug) | |
8352 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
8353 | wanted_abi); | |
2e4ebe70 DJ |
8354 | |
8355 | /* Now that we have found what the ABI for this binary would be, | |
8356 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
8357 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
8358 | mips_abi = wanted_abi; | |
ec03c1ac AC |
8359 | else if (found_abi != MIPS_ABI_UNKNOWN) |
8360 | mips_abi = found_abi; | |
8361 | else | |
8362 | mips_abi = MIPS_ABI_O32; | |
8363 | if (gdbarch_debug) | |
8364 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
8365 | mips_abi); | |
2e4ebe70 | 8366 | |
4cc0665f MR |
8367 | /* Determine the default compressed ISA. */ |
8368 | if ((elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0 | |
8369 | && (elf_flags & EF_MIPS_ARCH_ASE_M16) == 0) | |
8370 | mips_isa = ISA_MICROMIPS; | |
8371 | else if ((elf_flags & EF_MIPS_ARCH_ASE_M16) != 0 | |
8372 | && (elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) == 0) | |
8373 | mips_isa = ISA_MIPS16; | |
8374 | else | |
8375 | mips_isa = global_mips_compression (); | |
8376 | mips_compression_string = mips_compression_strings[mips_isa]; | |
8377 | ||
ec03c1ac | 8378 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 8379 | if (gdbarch_debug) |
ec03c1ac | 8380 | fprintf_unfiltered (gdb_stdlog, |
025bb325 MS |
8381 | "mips_gdbarch_init: " |
8382 | "mips64_transfers_32bit_regs_p = %d\n", | |
ec03c1ac | 8383 | mips64_transfers_32bit_regs_p); |
0dadbba0 | 8384 | |
8d5838b5 | 8385 | /* Determine the MIPS FPU type. */ |
609ca2b9 DJ |
8386 | #ifdef HAVE_ELF |
8387 | if (info.abfd | |
8388 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
8389 | elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
8390 | Tag_GNU_MIPS_ABI_FP); | |
8391 | #endif /* HAVE_ELF */ | |
8392 | ||
8d5838b5 AC |
8393 | if (!mips_fpu_type_auto) |
8394 | fpu_type = mips_fpu_type; | |
d929bc19 | 8395 | else if (elf_fpu_type != Val_GNU_MIPS_ABI_FP_ANY) |
609ca2b9 DJ |
8396 | { |
8397 | switch (elf_fpu_type) | |
8398 | { | |
d929bc19 | 8399 | case Val_GNU_MIPS_ABI_FP_DOUBLE: |
609ca2b9 DJ |
8400 | fpu_type = MIPS_FPU_DOUBLE; |
8401 | break; | |
d929bc19 | 8402 | case Val_GNU_MIPS_ABI_FP_SINGLE: |
609ca2b9 DJ |
8403 | fpu_type = MIPS_FPU_SINGLE; |
8404 | break; | |
d929bc19 | 8405 | case Val_GNU_MIPS_ABI_FP_SOFT: |
609ca2b9 DJ |
8406 | default: |
8407 | /* Soft float or unknown. */ | |
8408 | fpu_type = MIPS_FPU_NONE; | |
8409 | break; | |
8410 | } | |
8411 | } | |
8d5838b5 AC |
8412 | else if (info.bfd_arch_info != NULL |
8413 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
8414 | switch (info.bfd_arch_info->mach) | |
8415 | { | |
8416 | case bfd_mach_mips3900: | |
8417 | case bfd_mach_mips4100: | |
8418 | case bfd_mach_mips4111: | |
a9d61c86 | 8419 | case bfd_mach_mips4120: |
8d5838b5 AC |
8420 | fpu_type = MIPS_FPU_NONE; |
8421 | break; | |
8422 | case bfd_mach_mips4650: | |
8423 | fpu_type = MIPS_FPU_SINGLE; | |
8424 | break; | |
8425 | default: | |
8426 | fpu_type = MIPS_FPU_DOUBLE; | |
8427 | break; | |
8428 | } | |
8429 | else if (arches != NULL) | |
a2f1f308 | 8430 | fpu_type = MIPS_FPU_TYPE (arches->gdbarch); |
8d5838b5 AC |
8431 | else |
8432 | fpu_type = MIPS_FPU_DOUBLE; | |
8433 | if (gdbarch_debug) | |
8434 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 8435 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 8436 | |
29709017 DJ |
8437 | /* Check for blatant incompatibilities. */ |
8438 | ||
8439 | /* If we have only 32-bit registers, then we can't debug a 64-bit | |
8440 | ABI. */ | |
8441 | if (info.target_desc | |
8442 | && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL | |
8443 | && mips_abi != MIPS_ABI_EABI32 | |
8444 | && mips_abi != MIPS_ABI_O32) | |
f8b73d13 DJ |
8445 | { |
8446 | if (tdesc_data != NULL) | |
8447 | tdesc_data_cleanup (tdesc_data); | |
8448 | return NULL; | |
8449 | } | |
29709017 | 8450 | |
025bb325 | 8451 | /* Try to find a pre-existing architecture. */ |
c2d11a7d JM |
8452 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
8453 | arches != NULL; | |
8454 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
8455 | { | |
d54398a7 MR |
8456 | /* MIPS needs to be pedantic about which ABI and the compressed |
8457 | ISA variation the object is using. */ | |
9103eae0 | 8458 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 8459 | continue; |
9103eae0 | 8460 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 8461 | continue; |
d54398a7 MR |
8462 | if (gdbarch_tdep (arches->gdbarch)->mips_isa != mips_isa) |
8463 | continue; | |
719ec221 AC |
8464 | /* Need to be pedantic about which register virtual size is |
8465 | used. */ | |
8466 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
8467 | != mips64_transfers_32bit_regs_p) | |
8468 | continue; | |
8d5838b5 | 8469 | /* Be pedantic about which FPU is selected. */ |
a2f1f308 | 8470 | if (MIPS_FPU_TYPE (arches->gdbarch) != fpu_type) |
8d5838b5 | 8471 | continue; |
f8b73d13 DJ |
8472 | |
8473 | if (tdesc_data != NULL) | |
8474 | tdesc_data_cleanup (tdesc_data); | |
4be87837 | 8475 | return arches->gdbarch; |
c2d11a7d JM |
8476 | } |
8477 | ||
102182a9 | 8478 | /* Need a new architecture. Fill in a target specific vector. */ |
cdd238da | 8479 | tdep = XCNEW (struct gdbarch_tdep); |
c2d11a7d JM |
8480 | gdbarch = gdbarch_alloc (&info, tdep); |
8481 | tdep->elf_flags = elf_flags; | |
719ec221 | 8482 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
8483 | tdep->found_abi = found_abi; |
8484 | tdep->mips_abi = mips_abi; | |
4cc0665f | 8485 | tdep->mips_isa = mips_isa; |
8d5838b5 | 8486 | tdep->mips_fpu_type = fpu_type; |
29709017 DJ |
8487 | tdep->register_size_valid_p = 0; |
8488 | tdep->register_size = 0; | |
8489 | ||
8490 | if (info.target_desc) | |
8491 | { | |
8492 | /* Some useful properties can be inferred from the target. */ | |
8493 | if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) | |
8494 | { | |
8495 | tdep->register_size_valid_p = 1; | |
8496 | tdep->register_size = 4; | |
8497 | } | |
8498 | else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) | |
8499 | { | |
8500 | tdep->register_size_valid_p = 1; | |
8501 | tdep->register_size = 8; | |
8502 | } | |
8503 | } | |
c2d11a7d | 8504 | |
102182a9 | 8505 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
8506 | set_gdbarch_short_bit (gdbarch, 16); |
8507 | set_gdbarch_int_bit (gdbarch, 32); | |
8508 | set_gdbarch_float_bit (gdbarch, 32); | |
8509 | set_gdbarch_double_bit (gdbarch, 64); | |
8510 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
8511 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
8512 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
8513 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 8514 | |
175ff332 HZ |
8515 | set_gdbarch_ax_pseudo_register_collect (gdbarch, |
8516 | mips_ax_pseudo_register_collect); | |
8517 | set_gdbarch_ax_pseudo_register_push_stack | |
8518 | (gdbarch, mips_ax_pseudo_register_push_stack); | |
8519 | ||
6d82d43b | 8520 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 | 8521 | mips_elf_make_msymbol_special); |
3e29f34a MR |
8522 | set_gdbarch_make_symbol_special (gdbarch, mips_make_symbol_special); |
8523 | set_gdbarch_adjust_dwarf2_addr (gdbarch, mips_adjust_dwarf2_addr); | |
8524 | set_gdbarch_adjust_dwarf2_line (gdbarch, mips_adjust_dwarf2_line); | |
f7ab6ec6 | 8525 | |
1faeff08 MR |
8526 | regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, struct mips_regnum); |
8527 | *regnum = mips_regnum; | |
1faeff08 MR |
8528 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
8529 | set_gdbarch_num_regs (gdbarch, num_regs); | |
8530 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
8531 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
8532 | set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer); | |
8533 | tdep->mips_processor_reg_names = reg_names; | |
8534 | tdep->regnum = regnum; | |
fe29b929 | 8535 | |
0dadbba0 | 8536 | switch (mips_abi) |
c2d11a7d | 8537 | { |
0dadbba0 | 8538 | case MIPS_ABI_O32: |
25ab4790 | 8539 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 8540 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
4c7d22cb | 8541 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 8542 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 8543 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8544 | set_gdbarch_long_bit (gdbarch, 32); |
8545 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8546 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8547 | break; | |
0dadbba0 | 8548 | case MIPS_ABI_O64: |
25ab4790 | 8549 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
9c8fdbfa | 8550 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
4c7d22cb | 8551 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 8552 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 8553 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8554 | set_gdbarch_long_bit (gdbarch, 32); |
8555 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8556 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8557 | break; | |
0dadbba0 | 8558 | case MIPS_ABI_EABI32: |
25ab4790 | 8559 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 8560 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 8561 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8562 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 8563 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8564 | set_gdbarch_long_bit (gdbarch, 32); |
8565 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8566 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8567 | break; | |
0dadbba0 | 8568 | case MIPS_ABI_EABI64: |
25ab4790 | 8569 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 8570 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 8571 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8572 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 8573 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8574 | set_gdbarch_long_bit (gdbarch, 64); |
8575 | set_gdbarch_ptr_bit (gdbarch, 64); | |
8576 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8577 | break; | |
0dadbba0 | 8578 | case MIPS_ABI_N32: |
25ab4790 | 8579 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 8580 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 8581 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8582 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 8583 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
8584 | set_gdbarch_long_bit (gdbarch, 32); |
8585 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8586 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 8587 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 8588 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
28d169de KB |
8589 | break; |
8590 | case MIPS_ABI_N64: | |
25ab4790 | 8591 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 8592 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 8593 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8594 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
8595 | tdep->default_mask_address_p = 0; |
8596 | set_gdbarch_long_bit (gdbarch, 64); | |
8597 | set_gdbarch_ptr_bit (gdbarch, 64); | |
8598 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 8599 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 8600 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
0dadbba0 | 8601 | break; |
c2d11a7d | 8602 | default: |
e2e0b3e5 | 8603 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); |
c2d11a7d JM |
8604 | } |
8605 | ||
22e47e37 FF |
8606 | /* GCC creates a pseudo-section whose name specifies the size of |
8607 | longs, since -mlong32 or -mlong64 may be used independent of | |
8608 | other options. How those options affect pointer sizes is ABI and | |
8609 | architecture dependent, so use them to override the default sizes | |
8610 | set by the ABI. This table shows the relationship between ABI, | |
8611 | -mlongXX, and size of pointers: | |
8612 | ||
8613 | ABI -mlongXX ptr bits | |
8614 | --- -------- -------- | |
8615 | o32 32 32 | |
8616 | o32 64 32 | |
8617 | n32 32 32 | |
8618 | n32 64 64 | |
8619 | o64 32 32 | |
8620 | o64 64 64 | |
8621 | n64 32 32 | |
8622 | n64 64 64 | |
8623 | eabi32 32 32 | |
8624 | eabi32 64 32 | |
8625 | eabi64 32 32 | |
8626 | eabi64 64 64 | |
8627 | ||
8628 | Note that for o32 and eabi32, pointers are always 32 bits | |
8629 | regardless of any -mlongXX option. For all others, pointers and | |
025bb325 | 8630 | longs are the same, as set by -mlongXX or set by defaults. */ |
22e47e37 FF |
8631 | |
8632 | if (info.abfd != NULL) | |
8633 | { | |
8634 | int long_bit = 0; | |
8635 | ||
8636 | bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); | |
8637 | if (long_bit) | |
8638 | { | |
8639 | set_gdbarch_long_bit (gdbarch, long_bit); | |
8640 | switch (mips_abi) | |
8641 | { | |
8642 | case MIPS_ABI_O32: | |
8643 | case MIPS_ABI_EABI32: | |
8644 | break; | |
8645 | case MIPS_ABI_N32: | |
8646 | case MIPS_ABI_O64: | |
8647 | case MIPS_ABI_N64: | |
8648 | case MIPS_ABI_EABI64: | |
8649 | set_gdbarch_ptr_bit (gdbarch, long_bit); | |
8650 | break; | |
8651 | default: | |
8652 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); | |
8653 | } | |
8654 | } | |
8655 | } | |
8656 | ||
a5ea2558 AC |
8657 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
8658 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
8659 | comment: | |
8660 | ||
8661 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
8662 | flag in object files because to do so would make it impossible to | |
102182a9 | 8663 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 8664 | unnecessarily restrictive. |
361d1df0 | 8665 | |
a5ea2558 AC |
8666 | We could solve this problem by adding "-gp32" multilibs to gcc, |
8667 | but to set this flag before gcc is built with such multilibs will | |
8668 | break too many systems.'' | |
8669 | ||
8670 | But even more unhelpfully, the default linker output target for | |
8671 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
8672 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 8673 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
8674 | this flag to detect 32-bit mode would do the wrong thing given |
8675 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 8676 | as 32-bit programs by default. */ |
a5ea2558 | 8677 | |
6c997a34 | 8678 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 8679 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
c2d11a7d | 8680 | |
102182a9 MS |
8681 | /* Add/remove bits from an address. The MIPS needs be careful to |
8682 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
8683 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
8684 | ||
58dfe9ff AC |
8685 | /* Unwind the frame. */ |
8686 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
30244cd8 | 8687 | set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); |
b8a22b94 | 8688 | set_gdbarch_dummy_id (gdbarch, mips_dummy_id); |
10312cc4 | 8689 | |
102182a9 | 8690 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 8691 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
8692 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
8693 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
6d82d43b AC |
8694 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, |
8695 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 8696 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 8697 | |
025bb325 | 8698 | /* MIPS version of CALL_DUMMY. */ |
c2d11a7d | 8699 | |
2c76a0c7 JB |
8700 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
8701 | set_gdbarch_push_dummy_code (gdbarch, mips_push_dummy_code); | |
dc604539 | 8702 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 8703 | |
1bab7383 YQ |
8704 | set_gdbarch_print_float_info (gdbarch, mips_print_float_info); |
8705 | ||
87783b8b AC |
8706 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
8707 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
8708 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
8709 | ||
f7b9e9fc | 8710 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
04180708 YQ |
8711 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, mips_breakpoint_kind_from_pc); |
8712 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, mips_sw_breakpoint_from_kind); | |
c8cef75f MR |
8713 | set_gdbarch_adjust_breakpoint_address (gdbarch, |
8714 | mips_adjust_breakpoint_address); | |
f7b9e9fc AC |
8715 | |
8716 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 8717 | |
c9cf6e20 | 8718 | set_gdbarch_stack_frame_destroyed_p (gdbarch, mips_stack_frame_destroyed_p); |
97ab0fdd | 8719 | |
fc0c74b1 AC |
8720 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
8721 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
8722 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 8723 | |
a4b8ebc8 | 8724 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 8725 | |
e11c53d2 | 8726 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 8727 | |
9dae60cc UW |
8728 | if (mips_abi == MIPS_ABI_N32) |
8729 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n32); | |
8730 | else if (mips_abi == MIPS_ABI_N64) | |
8731 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n64); | |
8732 | else | |
8733 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); | |
e5ab0dce | 8734 | |
d92524f1 PM |
8735 | /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint, |
8736 | HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint | |
3a3bc038 | 8737 | need to all be folded into the target vector. Since they are |
d92524f1 PM |
8738 | being used as guards for target_stopped_by_watchpoint, why not have |
8739 | target_stopped_by_watchpoint return the type of watchpoint that the code | |
3a3bc038 AC |
8740 | is sitting on? */ |
8741 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
8742 | ||
e7d6a6d2 | 8743 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
757a7cc6 | 8744 | |
14132e89 MR |
8745 | /* NOTE drow/2012-04-25: We overload the core solib trampoline code |
8746 | to support MIPS16. This is a bad thing. Make sure not to do it | |
8747 | if we have an OS ABI that actually supports shared libraries, since | |
8748 | shared library support is more important. If we have an OS someday | |
8749 | that supports both shared libraries and MIPS16, we'll have to find | |
8750 | a better place for these. | |
8751 | macro/2012-04-25: But that applies to return trampolines only and | |
8752 | currently no MIPS OS ABI uses shared libraries that have them. */ | |
8753 | set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); | |
8754 | ||
025bb325 MS |
8755 | set_gdbarch_single_step_through_delay (gdbarch, |
8756 | mips_single_step_through_delay); | |
3352ef37 | 8757 | |
0d5de010 DJ |
8758 | /* Virtual tables. */ |
8759 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
8760 | ||
29709017 DJ |
8761 | mips_register_g_packet_guesses (gdbarch); |
8762 | ||
6de918a6 | 8763 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
0dba2a6c | 8764 | info.tdesc_data = tdesc_data; |
6de918a6 | 8765 | gdbarch_init_osabi (info, gdbarch); |
757a7cc6 | 8766 | |
9aac7884 MR |
8767 | /* The hook may have adjusted num_regs, fetch the final value and |
8768 | set pc_regnum and sp_regnum now that it has been fixed. */ | |
9aac7884 MR |
8769 | num_regs = gdbarch_num_regs (gdbarch); |
8770 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); | |
8771 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
8772 | ||
5792a79b | 8773 | /* Unwind the frame. */ |
b8a22b94 DJ |
8774 | dwarf2_append_unwinders (gdbarch); |
8775 | frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind); | |
8776 | frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind); | |
4cc0665f | 8777 | frame_unwind_append_unwinder (gdbarch, &mips_micro_frame_unwind); |
b8a22b94 | 8778 | frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind); |
2bd0c3d7 | 8779 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
eec63939 | 8780 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
45c9dd44 | 8781 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
4cc0665f | 8782 | frame_base_append_sniffer (gdbarch, mips_micro_frame_base_sniffer); |
45c9dd44 | 8783 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); |
5792a79b | 8784 | |
f8b73d13 DJ |
8785 | if (tdesc_data) |
8786 | { | |
8787 | set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); | |
7cc46491 | 8788 | tdesc_use_registers (gdbarch, info.target_desc, tdesc_data); |
f8b73d13 DJ |
8789 | |
8790 | /* Override the normal target description methods to handle our | |
8791 | dual real and pseudo registers. */ | |
8792 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
025bb325 MS |
8793 | set_gdbarch_register_reggroup_p (gdbarch, |
8794 | mips_tdesc_register_reggroup_p); | |
f8b73d13 DJ |
8795 | |
8796 | num_regs = gdbarch_num_regs (gdbarch); | |
8797 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
8798 | set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs); | |
8799 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
8800 | } | |
8801 | ||
8802 | /* Add ABI-specific aliases for the registers. */ | |
8803 | if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) | |
8804 | for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++) | |
8805 | user_reg_add (gdbarch, mips_n32_n64_aliases[i].name, | |
8806 | value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); | |
8807 | else | |
8808 | for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) | |
8809 | user_reg_add (gdbarch, mips_o32_aliases[i].name, | |
8810 | value_of_mips_user_reg, &mips_o32_aliases[i].regnum); | |
8811 | ||
8812 | /* Add some other standard aliases. */ | |
8813 | for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) | |
8814 | user_reg_add (gdbarch, mips_register_aliases[i].name, | |
8815 | value_of_mips_user_reg, &mips_register_aliases[i].regnum); | |
8816 | ||
865093a3 AR |
8817 | for (i = 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++) |
8818 | user_reg_add (gdbarch, mips_numeric_register_aliases[i].name, | |
8819 | value_of_mips_user_reg, | |
8820 | &mips_numeric_register_aliases[i].regnum); | |
8821 | ||
4b9b3959 AC |
8822 | return gdbarch; |
8823 | } | |
8824 | ||
2e4ebe70 | 8825 | static void |
eb4c3f4a TT |
8826 | mips_abi_update (const char *ignore_args, |
8827 | int from_tty, struct cmd_list_element *c) | |
2e4ebe70 DJ |
8828 | { |
8829 | struct gdbarch_info info; | |
8830 | ||
8831 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
8832 | mips_gdbarch_init will take care of the rest. */ | |
8833 | gdbarch_info_init (&info); | |
8834 | gdbarch_update_p (info); | |
8835 | } | |
8836 | ||
ad188201 KB |
8837 | /* Print out which MIPS ABI is in use. */ |
8838 | ||
8839 | static void | |
1f8ca57c JB |
8840 | show_mips_abi (struct ui_file *file, |
8841 | int from_tty, | |
8842 | struct cmd_list_element *ignored_cmd, | |
8843 | const char *ignored_value) | |
ad188201 | 8844 | { |
f5656ead | 8845 | if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips) |
1f8ca57c JB |
8846 | fprintf_filtered |
8847 | (file, | |
8848 | "The MIPS ABI is unknown because the current architecture " | |
8849 | "is not MIPS.\n"); | |
ad188201 KB |
8850 | else |
8851 | { | |
8852 | enum mips_abi global_abi = global_mips_abi (); | |
f5656ead | 8853 | enum mips_abi actual_abi = mips_abi (target_gdbarch ()); |
ad188201 KB |
8854 | const char *actual_abi_str = mips_abi_strings[actual_abi]; |
8855 | ||
8856 | if (global_abi == MIPS_ABI_UNKNOWN) | |
1f8ca57c JB |
8857 | fprintf_filtered |
8858 | (file, | |
8859 | "The MIPS ABI is set automatically (currently \"%s\").\n", | |
6d82d43b | 8860 | actual_abi_str); |
ad188201 | 8861 | else if (global_abi == actual_abi) |
1f8ca57c JB |
8862 | fprintf_filtered |
8863 | (file, | |
8864 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6d82d43b | 8865 | actual_abi_str); |
ad188201 KB |
8866 | else |
8867 | { | |
8868 | /* Probably shouldn't happen... */ | |
025bb325 MS |
8869 | fprintf_filtered (file, |
8870 | "The (auto detected) MIPS ABI \"%s\" is in use " | |
8871 | "even though the user setting was \"%s\".\n", | |
6d82d43b | 8872 | actual_abi_str, mips_abi_strings[global_abi]); |
ad188201 KB |
8873 | } |
8874 | } | |
8875 | } | |
8876 | ||
4cc0665f MR |
8877 | /* Print out which MIPS compressed ISA encoding is used. */ |
8878 | ||
8879 | static void | |
8880 | show_mips_compression (struct ui_file *file, int from_tty, | |
8881 | struct cmd_list_element *c, const char *value) | |
8882 | { | |
8883 | fprintf_filtered (file, _("The compressed ISA encoding used is %s.\n"), | |
8884 | value); | |
8885 | } | |
8886 | ||
a4f320fd MR |
8887 | /* Return a textual name for MIPS FPU type FPU_TYPE. */ |
8888 | ||
8889 | static const char * | |
8890 | mips_fpu_type_str (enum mips_fpu_type fpu_type) | |
8891 | { | |
8892 | switch (fpu_type) | |
8893 | { | |
8894 | case MIPS_FPU_NONE: | |
8895 | return "none"; | |
8896 | case MIPS_FPU_SINGLE: | |
8897 | return "single"; | |
8898 | case MIPS_FPU_DOUBLE: | |
8899 | return "double"; | |
8900 | default: | |
8901 | return "???"; | |
8902 | } | |
8903 | } | |
8904 | ||
4b9b3959 | 8905 | static void |
72a155b4 | 8906 | mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
4b9b3959 | 8907 | { |
72a155b4 | 8908 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4b9b3959 | 8909 | if (tdep != NULL) |
c2d11a7d | 8910 | { |
acdb74a0 AC |
8911 | int ef_mips_arch; |
8912 | int ef_mips_32bitmode; | |
f49e4e6d | 8913 | /* Determine the ISA. */ |
acdb74a0 AC |
8914 | switch (tdep->elf_flags & EF_MIPS_ARCH) |
8915 | { | |
8916 | case E_MIPS_ARCH_1: | |
8917 | ef_mips_arch = 1; | |
8918 | break; | |
8919 | case E_MIPS_ARCH_2: | |
8920 | ef_mips_arch = 2; | |
8921 | break; | |
8922 | case E_MIPS_ARCH_3: | |
8923 | ef_mips_arch = 3; | |
8924 | break; | |
8925 | case E_MIPS_ARCH_4: | |
93d56215 | 8926 | ef_mips_arch = 4; |
acdb74a0 AC |
8927 | break; |
8928 | default: | |
93d56215 | 8929 | ef_mips_arch = 0; |
acdb74a0 AC |
8930 | break; |
8931 | } | |
f49e4e6d | 8932 | /* Determine the size of a pointer. */ |
acdb74a0 | 8933 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); |
4b9b3959 AC |
8934 | fprintf_unfiltered (file, |
8935 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 8936 | tdep->elf_flags); |
4b9b3959 | 8937 | fprintf_unfiltered (file, |
acdb74a0 AC |
8938 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
8939 | ef_mips_32bitmode); | |
8940 | fprintf_unfiltered (file, | |
8941 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
8942 | ef_mips_arch); | |
8943 | fprintf_unfiltered (file, | |
8944 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 8945 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b | 8946 | fprintf_unfiltered (file, |
025bb325 MS |
8947 | "mips_dump_tdep: " |
8948 | "mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 8949 | mips_mask_address_p (tdep), |
4014092b | 8950 | tdep->default_mask_address_p); |
c2d11a7d | 8951 | } |
4b9b3959 AC |
8952 | fprintf_unfiltered (file, |
8953 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
8954 | MIPS_DEFAULT_FPU_TYPE, | |
a4f320fd | 8955 | mips_fpu_type_str (MIPS_DEFAULT_FPU_TYPE)); |
74ed0bb4 MD |
8956 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", |
8957 | MIPS_EABI (gdbarch)); | |
4b9b3959 AC |
8958 | fprintf_unfiltered (file, |
8959 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
74ed0bb4 | 8960 | MIPS_FPU_TYPE (gdbarch), |
a4f320fd | 8961 | mips_fpu_type_str (MIPS_FPU_TYPE (gdbarch))); |
c2d11a7d JM |
8962 | } |
8963 | ||
c906108c | 8964 | void |
acdb74a0 | 8965 | _initialize_mips_tdep (void) |
c906108c SS |
8966 | { |
8967 | static struct cmd_list_element *mipsfpulist = NULL; | |
c906108c | 8968 | |
6d82d43b | 8969 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
8970 | if (MIPS_ABI_LAST + 1 |
8971 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
e2e0b3e5 | 8972 | internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync")); |
2e4ebe70 | 8973 | |
4b9b3959 | 8974 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 8975 | |
8d5f9dcb DJ |
8976 | mips_pdr_data = register_objfile_data (); |
8977 | ||
4eb0ad19 DJ |
8978 | /* Create feature sets with the appropriate properties. The values |
8979 | are not important. */ | |
8980 | mips_tdesc_gp32 = allocate_target_description (); | |
8981 | set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, ""); | |
8982 | ||
8983 | mips_tdesc_gp64 = allocate_target_description (); | |
8984 | set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, ""); | |
8985 | ||
025bb325 | 8986 | /* Add root prefix command for all "set mips"/"show mips" commands. */ |
a5ea2558 | 8987 | add_prefix_cmd ("mips", no_class, set_mips_command, |
1bedd215 | 8988 | _("Various MIPS specific commands."), |
a5ea2558 AC |
8989 | &setmipscmdlist, "set mips ", 0, &setlist); |
8990 | ||
8991 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
1bedd215 | 8992 | _("Various MIPS specific commands."), |
a5ea2558 AC |
8993 | &showmipscmdlist, "show mips ", 0, &showlist); |
8994 | ||
025bb325 | 8995 | /* Allow the user to override the ABI. */ |
7ab04401 AC |
8996 | add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, |
8997 | &mips_abi_string, _("\ | |
8998 | Set the MIPS ABI used by this program."), _("\ | |
8999 | Show the MIPS ABI used by this program."), _("\ | |
9000 | This option can be set to one of:\n\ | |
9001 | auto - the default ABI associated with the current binary\n\ | |
9002 | o32\n\ | |
9003 | o64\n\ | |
9004 | n32\n\ | |
9005 | n64\n\ | |
9006 | eabi32\n\ | |
9007 | eabi64"), | |
9008 | mips_abi_update, | |
9009 | show_mips_abi, | |
9010 | &setmipscmdlist, &showmipscmdlist); | |
2e4ebe70 | 9011 | |
4cc0665f MR |
9012 | /* Allow the user to set the ISA to assume for compressed code if ELF |
9013 | file flags don't tell or there is no program file selected. This | |
9014 | setting is updated whenever unambiguous ELF file flags are interpreted, | |
9015 | and carried over to subsequent sessions. */ | |
9016 | add_setshow_enum_cmd ("compression", class_obscure, mips_compression_strings, | |
9017 | &mips_compression_string, _("\ | |
9018 | Set the compressed ISA encoding used by MIPS code."), _("\ | |
9019 | Show the compressed ISA encoding used by MIPS code."), _("\ | |
9020 | Select the compressed ISA encoding used in functions that have no symbol\n\ | |
9021 | information available. The encoding can be set to either of:\n\ | |
9022 | mips16\n\ | |
9023 | micromips\n\ | |
9024 | and is updated automatically from ELF file flags if available."), | |
9025 | mips_abi_update, | |
9026 | show_mips_compression, | |
9027 | &setmipscmdlist, &showmipscmdlist); | |
9028 | ||
c906108c SS |
9029 | /* Let the user turn off floating point and set the fence post for |
9030 | heuristic_proc_start. */ | |
9031 | ||
9032 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
1bedd215 | 9033 | _("Set use of MIPS floating-point coprocessor."), |
c906108c SS |
9034 | &mipsfpulist, "set mipsfpu ", 0, &setlist); |
9035 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
1a966eab | 9036 | _("Select single-precision MIPS floating-point coprocessor."), |
c906108c SS |
9037 | &mipsfpulist); |
9038 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
1a966eab | 9039 | _("Select double-precision MIPS floating-point coprocessor."), |
c906108c SS |
9040 | &mipsfpulist); |
9041 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
9042 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
9043 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
9044 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
1a966eab | 9045 | _("Select no MIPS floating-point coprocessor."), &mipsfpulist); |
c906108c SS |
9046 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
9047 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
9048 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
9049 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
1a966eab | 9050 | _("Select MIPS floating-point coprocessor automatically."), |
c906108c SS |
9051 | &mipsfpulist); |
9052 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
1a966eab | 9053 | _("Show current use of MIPS floating-point coprocessor target."), |
c906108c SS |
9054 | &showlist); |
9055 | ||
c906108c SS |
9056 | /* We really would like to have both "0" and "unlimited" work, but |
9057 | command.c doesn't deal with that. So make it a var_zinteger | |
9058 | because the user can always use "999999" or some such for unlimited. */ | |
6bcadd06 | 9059 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
7915a72c AC |
9060 | &heuristic_fence_post, _("\ |
9061 | Set the distance searched for the start of a function."), _("\ | |
9062 | Show the distance searched for the start of a function."), _("\ | |
c906108c SS |
9063 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
9064 | program for the start of a function. This command sets the distance of the\n\ | |
7915a72c | 9065 | search. The only need to set it is when debugging a stripped executable."), |
2c5b56ce | 9066 | reinit_frame_cache_sfunc, |
025bb325 MS |
9067 | NULL, /* FIXME: i18n: The distance searched for |
9068 | the start of a function is %s. */ | |
6bcadd06 | 9069 | &setlist, &showlist); |
c906108c SS |
9070 | |
9071 | /* Allow the user to control whether the upper bits of 64-bit | |
9072 | addresses should be zeroed. */ | |
7915a72c AC |
9073 | add_setshow_auto_boolean_cmd ("mask-address", no_class, |
9074 | &mask_address_var, _("\ | |
9075 | Set zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
9076 | Show zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
cce7e648 | 9077 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\ |
7915a72c | 9078 | allow GDB to determine the correct value."), |
08546159 AC |
9079 | NULL, show_mask_address, |
9080 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
9081 | |
9082 | /* Allow the user to control the size of 32 bit registers within the | |
9083 | raw remote packet. */ | |
b3f42336 | 9084 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
7915a72c AC |
9085 | &mips64_transfers_32bit_regs_p, _("\ |
9086 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
9087 | _("\ | |
9088 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
9089 | _("\ | |
719ec221 AC |
9090 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
9091 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
7915a72c | 9092 | 64 bits for others. Use \"off\" to disable compatibility mode"), |
2c5b56ce | 9093 | set_mips64_transfers_32bit_regs, |
025bb325 MS |
9094 | NULL, /* FIXME: i18n: Compatibility with 64-bit |
9095 | MIPS target that transfers 32-bit | |
9096 | quantities is %s. */ | |
7915a72c | 9097 | &setlist, &showlist); |
9ace0497 | 9098 | |
025bb325 | 9099 | /* Debug this files internals. */ |
ccce17b0 YQ |
9100 | add_setshow_zuinteger_cmd ("mips", class_maintenance, |
9101 | &mips_debug, _("\ | |
7915a72c AC |
9102 | Set mips debugging."), _("\ |
9103 | Show mips debugging."), _("\ | |
9104 | When non-zero, mips specific debugging is enabled."), | |
ccce17b0 YQ |
9105 | NULL, |
9106 | NULL, /* FIXME: i18n: Mips debugging is | |
9107 | currently %s. */ | |
9108 | &setdebuglist, &showdebuglist); | |
c906108c | 9109 | } |